2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ata/ata-pci.h>
54 /* local prototypes */
55 static int ata_intel_chipinit(device_t dev);
56 static int ata_intel_chipdeinit(device_t dev);
57 static int ata_intel_ch_attach(device_t dev);
58 static void ata_intel_reset(device_t dev);
59 static int ata_intel_old_setmode(device_t dev, int target, int mode);
60 static int ata_intel_new_setmode(device_t dev, int target, int mode);
61 static int ata_intel_sch_setmode(device_t dev, int target, int mode);
62 static int ata_intel_sata_getrev(device_t dev, int target);
63 static int ata_intel_sata_status(device_t dev);
64 static int ata_intel_sata_ahci_read(device_t dev, int port,
65 int reg, u_int32_t *result);
66 static int ata_intel_sata_cscr_read(device_t dev, int port,
67 int reg, u_int32_t *result);
68 static int ata_intel_sata_sidpr_read(device_t dev, int port,
69 int reg, u_int32_t *result);
70 static int ata_intel_sata_ahci_write(device_t dev, int port,
71 int reg, u_int32_t result);
72 static int ata_intel_sata_cscr_write(device_t dev, int port,
73 int reg, u_int32_t result);
74 static int ata_intel_sata_sidpr_write(device_t dev, int port,
75 int reg, u_int32_t result);
76 static int ata_intel_31244_ch_attach(device_t dev);
77 static int ata_intel_31244_ch_detach(device_t dev);
78 static int ata_intel_31244_status(device_t dev);
79 static void ata_intel_31244_tf_write(struct ata_request *request);
80 static void ata_intel_31244_reset(device_t dev);
89 struct ata_intel_data {
94 #define ATA_INTEL_SMAP(ctlr, ch) \
95 &((struct ata_intel_data *)((ctlr)->chipset_data))->smap[(ch)->unit * 2]
96 #define ATA_INTEL_LOCK(ctlr) \
97 mtx_lock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock)
98 #define ATA_INTEL_UNLOCK(ctlr) \
99 mtx_unlock(&((struct ata_intel_data *)((ctlr)->chipset_data))->lock)
102 * Intel chipset support functions
105 ata_intel_probe(device_t dev)
107 struct ata_pci_controller *ctlr = device_get_softc(dev);
108 static struct ata_chip_id ids[] =
109 {{ ATA_I82371FB, 0, 0, 2, ATA_WDMA2, "PIIX" },
110 { ATA_I82371SB, 0, 0, 2, ATA_WDMA2, "PIIX3" },
111 { ATA_I82371AB, 0, 0, 2, ATA_UDMA2, "PIIX4" },
112 { ATA_I82443MX, 0, 0, 2, ATA_UDMA2, "PIIX4" },
113 { ATA_I82451NX, 0, 0, 2, ATA_UDMA2, "PIIX4" },
114 { ATA_I82801AB, 0, 0, 2, ATA_UDMA2, "ICH0" },
115 { ATA_I82801AA, 0, 0, 2, ATA_UDMA4, "ICH" },
116 { ATA_I82372FB, 0, 0, 2, ATA_UDMA4, "ICH" },
117 { ATA_I82801BA, 0, 0, 2, ATA_UDMA5, "ICH2" },
118 { ATA_I82801BA_1, 0, 0, 2, ATA_UDMA5, "ICH2" },
119 { ATA_I82801CA, 0, 0, 2, ATA_UDMA5, "ICH3" },
120 { ATA_I82801CA_1, 0, 0, 2, ATA_UDMA5, "ICH3" },
121 { ATA_I82801DB, 0, 0, 2, ATA_UDMA5, "ICH4" },
122 { ATA_I82801DB_1, 0, 0, 2, ATA_UDMA5, "ICH4" },
123 { ATA_I82801EB, 0, 0, 2, ATA_UDMA5, "ICH5" },
124 { ATA_I82801EB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" },
125 { ATA_I82801EB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "ICH5" },
126 { ATA_I6300ESB, 0, 0, 2, ATA_UDMA5, "6300ESB" },
127 { ATA_I6300ESB_S1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" },
128 { ATA_I6300ESB_R1, 0, INTEL_ICH5, 2, ATA_SA150, "6300ESB" },
129 { ATA_I82801FB, 0, 0, 2, ATA_UDMA5, "ICH6" },
130 { ATA_I82801FB_S1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" },
131 { ATA_I82801FB_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6" },
132 { ATA_I82801FBM, 0, INTEL_AHCI, 0, ATA_SA150, "ICH6M" },
133 { ATA_I82801GB, 0, 0, 1, ATA_UDMA5, "ICH7" },
134 { ATA_I82801GB_S1, 0, INTEL_ICH7, 0, ATA_SA300, "ICH7" },
135 { ATA_I82801GB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
136 { ATA_I82801GB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH7" },
137 { ATA_I82801GBM_S1, 0, INTEL_ICH7, 0, ATA_SA150, "ICH7M" },
138 { ATA_I82801GBM_R1, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
139 { ATA_I82801GBM_AH, 0, INTEL_AHCI, 0, ATA_SA150, "ICH7M" },
140 { ATA_I63XXESB2, 0, 0, 1, ATA_UDMA5, "63XXESB2" },
141 { ATA_I63XXESB2_S1, 0, 0, 0, ATA_SA300, "63XXESB2" },
142 { ATA_I63XXESB2_S2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
143 { ATA_I63XXESB2_R1, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
144 { ATA_I63XXESB2_R2, 0, INTEL_AHCI, 0, ATA_SA300, "63XXESB2" },
145 { ATA_I82801HB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8" },
146 { ATA_I82801HB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH8" },
147 { ATA_I82801HB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
148 { ATA_I82801HB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
149 { ATA_I82801HB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8" },
150 { ATA_I82801HBM, 0, 0, 1, ATA_UDMA5, "ICH8M" },
151 { ATA_I82801HBM_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH8M" },
152 { ATA_I82801HBM_S2, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
153 { ATA_I82801HBM_S3, 0, INTEL_AHCI, 0, ATA_SA300, "ICH8M" },
154 { ATA_I82801IB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH9" },
155 { ATA_I82801IB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" },
156 { ATA_I82801IB_S3, 0, INTEL_6CH2, 0, ATA_SA300, "ICH9" },
157 { ATA_I82801IB_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
158 { ATA_I82801IB_AH6, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
159 { ATA_I82801IB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH9" },
160 { ATA_I82801JIB_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },
161 { ATA_I82801JIB_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
162 { ATA_I82801JIB_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
163 { ATA_I82801JIB_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
164 { ATA_I82801JD_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },
165 { ATA_I82801JD_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
166 { ATA_I82801JD_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
167 { ATA_I82801JD_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
168 { ATA_I82801JI_S1, 0, INTEL_6CH, 0, ATA_SA300, "ICH10" },
169 { ATA_I82801JI_AH, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
170 { ATA_I82801JI_R1, 0, INTEL_AHCI, 0, ATA_SA300, "ICH10" },
171 { ATA_I82801JI_S2, 0, INTEL_6CH2, 0, ATA_SA300, "ICH10" },
172 { ATA_5Series_S1, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
173 { ATA_5Series_S2, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
174 { ATA_5Series_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
175 { ATA_5Series_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
176 { ATA_5Series_R1, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
177 { ATA_5Series_S3, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
178 { ATA_5Series_S4, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
179 { ATA_5Series_AH3, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
180 { ATA_5Series_R2, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
181 { ATA_5Series_S5, 0, INTEL_6CH2, 0, ATA_SA300, "5 Series/3400 Series PCH" },
182 { ATA_5Series_S6, 0, INTEL_6CH, 0, ATA_SA300, "5 Series/3400 Series PCH" },
183 { ATA_5Series_AH4, 0, INTEL_AHCI, 0, ATA_SA300, "5 Series/3400 Series PCH" },
184 { ATA_CPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" },
185 { ATA_CPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Cougar Point" },
186 { ATA_CPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
187 { ATA_CPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
188 { ATA_CPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
189 { ATA_CPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Cougar Point" },
190 { ATA_CPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },
191 { ATA_CPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Cougar Point" },
192 { ATA_PBG_S1, 0, INTEL_6CH, 0, ATA_SA300, "Patsburg" },
193 { ATA_PBG_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
194 { ATA_PBG_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
195 { ATA_PBG_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Patsburg" },
196 { ATA_PBG_S2, 0, INTEL_6CH2, 0, ATA_SA300, "Patsburg" },
197 { ATA_PPT_S1, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" },
198 { ATA_PPT_S2, 0, INTEL_6CH, 0, ATA_SA300, "Panther Point" },
199 { ATA_PPT_AH1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
200 { ATA_PPT_AH2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
201 { ATA_PPT_R1, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
202 { ATA_PPT_R2, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
203 { ATA_PPT_R3, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
204 { ATA_PPT_R4, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
205 { ATA_PPT_S3, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" },
206 { ATA_PPT_S4, 0, INTEL_6CH2, 0, ATA_SA300, "Panther Point" },
207 { ATA_PPT_R5, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
208 { ATA_PPT_R6, 0, INTEL_AHCI, 0, ATA_SA300, "Panther Point" },
209 { ATA_I31244, 0, 0, 2, ATA_SA150, "31244" },
210 { ATA_ISCH, 0, 0, 1, ATA_UDMA5, "SCH" },
211 { ATA_DH89XXCC, 0, INTEL_AHCI, 0, ATA_SA300, "DH89xxCC" },
212 { 0, 0, 0, 0, 0, 0}};
214 if (pci_get_vendor(dev) != ATA_INTEL_ID)
217 if (!(ctlr->chip = ata_match_chip(dev, ids)))
221 ctlr->chipinit = ata_intel_chipinit;
222 ctlr->chipdeinit = ata_intel_chipdeinit;
223 return (BUS_PROBE_DEFAULT);
227 ata_intel_chipinit(device_t dev)
229 struct ata_pci_controller *ctlr = device_get_softc(dev);
230 struct ata_intel_data *data;
232 if (ata_setup_interrupt(dev, ata_generic_intr))
235 data = malloc(sizeof(struct ata_intel_data), M_ATAPCI, M_WAITOK | M_ZERO);
236 mtx_init(&data->lock, "Intel SATA lock", NULL, MTX_DEF);
237 ctlr->chipset_data = (void *)data;
239 /* good old PIIX needs special treatment (not implemented) */
240 if (ctlr->chip->chipid == ATA_I82371FB) {
241 ctlr->setmode = ata_intel_old_setmode;
244 /* the intel 31244 needs special care if in DPA mode */
245 else if (ctlr->chip->chipid == ATA_I31244) {
246 if (pci_get_subclass(dev) != PCIS_STORAGE_IDE) {
247 ctlr->r_type2 = SYS_RES_MEMORY;
248 ctlr->r_rid2 = PCIR_BAR(0);
249 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
254 ctlr->ch_attach = ata_intel_31244_ch_attach;
255 ctlr->ch_detach = ata_intel_31244_ch_detach;
256 ctlr->reset = ata_intel_31244_reset;
258 ctlr->setmode = ata_sata_setmode;
259 ctlr->getrev = ata_sata_getrev;
262 else if (ctlr->chip->chipid == ATA_ISCH) {
264 ctlr->ch_attach = ata_intel_ch_attach;
265 ctlr->ch_detach = ata_pci_ch_detach;
266 ctlr->setmode = ata_intel_sch_setmode;
268 /* non SATA intel chips goes here */
269 else if (ctlr->chip->max_dma < ATA_SA150) {
270 ctlr->channels = ctlr->chip->cfg2;
271 ctlr->ch_attach = ata_intel_ch_attach;
272 ctlr->ch_detach = ata_pci_ch_detach;
273 ctlr->setmode = ata_intel_new_setmode;
276 /* SATA parts can be either compat or AHCI */
278 /* force all ports active "the legacy way" */
279 pci_write_config(dev, 0x92, pci_read_config(dev, 0x92, 2) | 0x0f, 2);
281 ctlr->ch_attach = ata_intel_ch_attach;
282 ctlr->ch_detach = ata_pci_ch_detach;
283 ctlr->reset = ata_intel_reset;
286 * if we have AHCI capability and AHCI or RAID mode enabled
287 * in BIOS we try for AHCI mode
289 if ((ctlr->chip->cfg1 & INTEL_AHCI) &&
290 (pci_read_config(dev, 0x90, 1) & 0xc0) &&
291 (ata_ahci_chipinit(dev) != ENXIO))
294 /* BAR(5) may point to SATA interface registers */
295 if ((ctlr->chip->cfg1 & INTEL_ICH7)) {
296 ctlr->r_type2 = SYS_RES_MEMORY;
297 ctlr->r_rid2 = PCIR_BAR(5);
298 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
299 &ctlr->r_rid2, RF_ACTIVE);
300 if (ctlr->r_res2 != NULL) {
301 /* Set SCRAE bit to enable registers access. */
302 pci_write_config(dev, 0x94,
303 pci_read_config(dev, 0x94, 4) | (1 << 9), 4);
304 /* Set Ports Implemented register bits. */
305 ATA_OUTL(ctlr->r_res2, 0x0C,
306 ATA_INL(ctlr->r_res2, 0x0C) | 0xf);
308 /* Skip BAR(5) on ICH8M Apples, system locks up on access. */
309 } else if (ctlr->chip->chipid != ATA_I82801HBM_S1 ||
310 pci_get_subvendor(dev) != 0x106b) {
311 ctlr->r_type2 = SYS_RES_IOPORT;
312 ctlr->r_rid2 = PCIR_BAR(5);
313 ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
314 &ctlr->r_rid2, RF_ACTIVE);
316 if (ctlr->r_res2 != NULL ||
317 (ctlr->chip->cfg1 & INTEL_ICH5))
318 ctlr->getrev = ata_intel_sata_getrev;
319 ctlr->setmode = ata_sata_setmode;
325 ata_intel_chipdeinit(device_t dev)
327 struct ata_pci_controller *ctlr = device_get_softc(dev);
328 struct ata_intel_data *data;
330 data = ctlr->chipset_data;
331 mtx_destroy(&data->lock);
332 free(data, M_ATAPCI);
333 ctlr->chipset_data = NULL;
338 ata_intel_ch_attach(device_t dev)
340 struct ata_pci_controller *ctlr;
341 struct ata_channel *ch;
345 /* setup the usual register normal pci style */
346 if (ata_pci_ch_attach(dev))
349 ctlr = device_get_softc(device_get_parent(dev));
350 ch = device_get_softc(dev);
352 /* if r_res2 is valid it points to SATA interface registers */
354 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
355 ch->r_io[ATA_IDX_ADDR].offset = 0x00;
356 ch->r_io[ATA_IDX_DATA].res = ctlr->r_res2;
357 ch->r_io[ATA_IDX_DATA].offset = 0x04;
360 ch->flags |= ATA_ALWAYS_DMASTAT;
361 if (ctlr->chip->max_dma >= ATA_SA150) {
362 smap = ATA_INTEL_SMAP(ctlr, ch);
363 map = pci_read_config(device_get_parent(dev), 0x90, 1);
364 if (ctlr->chip->cfg1 & INTEL_ICH5) {
366 if ((map & 0x04) == 0) {
367 ch->flags |= ATA_SATA;
368 ch->flags |= ATA_NO_SLAVE;
369 smap[0] = (map & 0x01) ^ ch->unit;
371 } else if ((map & 0x02) == 0 && ch->unit == 0) {
372 ch->flags |= ATA_SATA;
373 smap[0] = (map & 0x01) ? 1 : 0;
374 smap[1] = (map & 0x01) ? 0 : 1;
375 } else if ((map & 0x02) != 0 && ch->unit == 1) {
376 ch->flags |= ATA_SATA;
377 smap[0] = (map & 0x01) ? 1 : 0;
378 smap[1] = (map & 0x01) ? 0 : 1;
380 } else if (ctlr->chip->cfg1 & INTEL_6CH2) {
381 ch->flags |= ATA_SATA;
382 ch->flags |= ATA_NO_SLAVE;
383 smap[0] = (ch->unit == 0) ? 0 : 1;
388 ch->flags |= ATA_SATA;
389 smap[0] = (ch->unit == 0) ? 0 : 1;
390 smap[1] = (ch->unit == 0) ? 2 : 3;
391 } else if (map == 0x02 && ch->unit == 0) {
392 ch->flags |= ATA_SATA;
395 } else if (map == 0x01 && ch->unit == 1) {
396 ch->flags |= ATA_SATA;
401 if (ch->flags & ATA_SATA) {
402 if ((ctlr->chip->cfg1 & INTEL_ICH5)) {
403 ch->flags |= ATA_PERIODIC_POLL;
404 ch->hw.status = ata_intel_sata_status;
405 ch->hw.pm_read = ata_intel_sata_cscr_read;
406 ch->hw.pm_write = ata_intel_sata_cscr_write;
407 } else if (ctlr->r_res2) {
408 ch->flags |= ATA_PERIODIC_POLL;
409 ch->hw.status = ata_intel_sata_status;
410 if ((ctlr->chip->cfg1 & INTEL_ICH7)) {
411 ch->hw.pm_read = ata_intel_sata_ahci_read;
412 ch->hw.pm_write = ata_intel_sata_ahci_write;
414 ch->hw.pm_read = ata_intel_sata_sidpr_read;
415 ch->hw.pm_write = ata_intel_sata_sidpr_write;
418 if (ch->hw.pm_write != NULL) {
419 ata_sata_scr_write(ch, 0,
420 ATA_SERROR, 0xffffffff);
421 if ((ch->flags & ATA_NO_SLAVE) == 0) {
422 ata_sata_scr_write(ch, 1,
423 ATA_SERROR, 0xffffffff);
427 ctlr->setmode = ata_intel_new_setmode;
428 } else if (ctlr->chip->chipid != ATA_ISCH)
429 ch->flags |= ATA_CHECKS_CABLE;
434 ata_intel_reset(device_t dev)
436 device_t parent = device_get_parent(dev);
437 struct ata_pci_controller *ctlr = device_get_softc(parent);
438 struct ata_channel *ch = device_get_softc(dev);
439 int mask, pshift, timeout, devs;
443 /* In combined mode, skip SATA stuff for PATA channel. */
444 if ((ch->flags & ATA_SATA) == 0)
445 return (ata_generic_reset(dev));
447 /* Do hard-reset on respective SATA ports. */
448 smap = ATA_INTEL_SMAP(ctlr, ch);
450 if ((ch->flags & ATA_NO_SLAVE) == 0)
451 mask |= (1 << smap[1]);
452 pci_write_config(parent, 0x92,
453 pci_read_config(parent, 0x92, 2) & ~mask, 2);
455 pci_write_config(parent, 0x92,
456 pci_read_config(parent, 0x92, 2) | mask, 2);
458 /* Wait up to 1 sec for "connect well". */
459 if (ctlr->chip->cfg1 & (INTEL_6CH | INTEL_6CH2))
463 for (timeout = 0; timeout < 100 ; timeout++) {
464 pcs = (pci_read_config(parent, 0x92, 2) >> pshift) & mask;
465 if ((pcs == mask) && (ATA_IDX_INB(ch, ATA_STATUS) != 0xff))
471 device_printf(dev, "SATA reset: ports status=0x%02x\n", pcs);
472 /* If any device found, do soft-reset. */
473 if (ch->hw.pm_read != NULL) {
474 devs = ata_sata_phy_reset(dev, 0, 2) ? ATA_ATA_MASTER : 0;
475 if ((ch->flags & ATA_NO_SLAVE) == 0)
476 devs |= ata_sata_phy_reset(dev, 1, 2) ?
479 devs = (pcs & (1 << smap[0])) ? ATA_ATA_MASTER : 0;
480 if ((ch->flags & ATA_NO_SLAVE) == 0)
481 devs |= (pcs & (1 << smap[1])) ?
485 ata_generic_reset(dev);
486 /* Reset may give fake slave when only ATAPI master present. */
487 ch->devices &= (devs | (devs * ATA_ATAPI_MASTER));
493 ata_intel_old_setmode(device_t dev, int target, int mode)
495 device_t parent = device_get_parent(dev);
496 struct ata_pci_controller *ctlr = device_get_softc(parent);
498 mode = min(mode, ctlr->chip->max_dma);
503 ata_intel_new_setmode(device_t dev, int target, int mode)
505 device_t parent = device_get_parent(dev);
506 struct ata_pci_controller *ctlr = device_get_softc(parent);
507 struct ata_channel *ch = device_get_softc(dev);
508 int devno = (ch->unit << 1) + target;
510 u_int32_t reg40 = pci_read_config(parent, 0x40, 4);
511 u_int8_t reg44 = pci_read_config(parent, 0x44, 1);
512 u_int8_t reg48 = pci_read_config(parent, 0x48, 1);
513 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2);
514 u_int16_t reg54 = pci_read_config(parent, 0x54, 2);
515 u_int32_t mask40 = 0, new40 = 0;
516 u_int8_t mask44 = 0, new44 = 0;
517 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 };
518 u_int8_t utimings[] = { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 };
520 /* In combined mode, skip PATA stuff for SATA channel. */
521 if (ch->flags & ATA_SATA)
522 return (ata_sata_setmode(dev, target, mode));
524 mode = min(mode, ctlr->chip->max_dma);
525 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
526 !(reg54 & (0x10 << devno))) {
527 ata_print_cable(dev, "controller");
530 /* Enable/disable UDMA and set timings. */
531 if (mode >= ATA_UDMA0) {
532 pci_write_config(parent, 0x48, reg48 | (0x0001 << devno), 2);
533 pci_write_config(parent, 0x4a,
534 (reg4a & ~(0x3 << (devno << 2))) |
535 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2);
538 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << devno), 2);
539 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2);
543 /* Set UDMA reference clock (33/66/133MHz). */
544 reg54 &= ~(0x1001 << devno);
545 if (mode >= ATA_UDMA5)
546 reg54 |= (0x1000 << devno);
547 else if (mode >= ATA_UDMA3)
548 reg54 |= (0x1 << devno);
549 pci_write_config(parent, 0x54, reg54, 2);
550 /* Allow PIO/WDMA timing controls. */
551 reg40 &= ~0x00ff00ff;
553 /* Set PIO/WDMA timings. */
556 new40 = timings[ata_mode2idx(piomode)] << 8;
559 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) |
560 (timings[ata_mode2idx(piomode)] & 0x03);
568 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4);
569 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1);
574 ata_intel_sch_setmode(device_t dev, int target, int mode)
576 device_t parent = device_get_parent(dev);
577 struct ata_pci_controller *ctlr = device_get_softc(parent);
578 u_int8_t dtim = 0x80 + (target << 2);
579 u_int32_t tim = pci_read_config(parent, dtim, 4);
582 mode = min(mode, ctlr->chip->max_dma);
583 if (mode >= ATA_UDMA0) {
586 tim |= ((mode & ATA_MODE_MASK) << 16);
588 } else if (mode >= ATA_WDMA0) {
591 tim |= ((mode & ATA_MODE_MASK) << 8);
592 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
593 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
597 tim |= (piomode & 0x7);
598 pci_write_config(parent, dtim, tim, 4);
603 ata_intel_sata_getrev(device_t dev, int target)
605 struct ata_channel *ch = device_get_softc(dev);
608 if (ata_sata_scr_read(ch, target, ATA_SSTATUS, &status) == 0)
609 return ((status & 0x0f0) >> 4);
614 ata_intel_sata_status(device_t dev)
616 struct ata_channel *ch = device_get_softc(dev);
618 ata_sata_phy_check_events(dev, 0);
619 if ((ch->flags & ATA_NO_SLAVE) == 0)
620 ata_sata_phy_check_events(dev, 1);
622 return ata_pci_status(dev);
626 ata_intel_sata_ahci_read(device_t dev, int port, int reg, u_int32_t *result)
628 struct ata_pci_controller *ctlr;
629 struct ata_channel *ch;
634 parent = device_get_parent(dev);
635 ctlr = device_get_softc(parent);
636 ch = device_get_softc(dev);
637 port = (port == 1) ? 1 : 0;
638 smap = ATA_INTEL_SMAP(ctlr, ch);
639 offset = 0x100 + smap[port] * 0x80;
653 *result = ATA_INL(ctlr->r_res2, offset + reg);
658 ata_intel_sata_cscr_read(device_t dev, int port, int reg, u_int32_t *result)
660 struct ata_pci_controller *ctlr;
661 struct ata_channel *ch;
665 parent = device_get_parent(dev);
666 ctlr = device_get_softc(parent);
667 ch = device_get_softc(dev);
668 smap = ATA_INTEL_SMAP(ctlr, ch);
669 port = (port == 1) ? 1 : 0;
683 ATA_INTEL_LOCK(ctlr);
684 pci_write_config(parent, 0xa0,
685 0x50 + smap[port] * 0x10 + reg * 4, 4);
686 *result = pci_read_config(parent, 0xa4, 4);
687 ATA_INTEL_UNLOCK(ctlr);
692 ata_intel_sata_sidpr_read(device_t dev, int port, int reg, u_int32_t *result)
694 struct ata_pci_controller *ctlr;
695 struct ata_channel *ch;
698 parent = device_get_parent(dev);
699 ctlr = device_get_softc(parent);
700 ch = device_get_softc(dev);
701 port = (port == 1) ? 1 : 0;
715 ATA_INTEL_LOCK(ctlr);
716 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg);
717 *result = ATA_IDX_INL(ch, ATA_IDX_DATA);
718 ATA_INTEL_UNLOCK(ctlr);
723 ata_intel_sata_ahci_write(device_t dev, int port, int reg, u_int32_t value)
725 struct ata_pci_controller *ctlr;
726 struct ata_channel *ch;
731 parent = device_get_parent(dev);
732 ctlr = device_get_softc(parent);
733 ch = device_get_softc(dev);
734 port = (port == 1) ? 1 : 0;
735 smap = ATA_INTEL_SMAP(ctlr, ch);
736 offset = 0x100 + smap[port] * 0x80;
750 ATA_OUTL(ctlr->r_res2, offset + reg, value);
755 ata_intel_sata_cscr_write(device_t dev, int port, int reg, u_int32_t value)
757 struct ata_pci_controller *ctlr;
758 struct ata_channel *ch;
762 parent = device_get_parent(dev);
763 ctlr = device_get_softc(parent);
764 ch = device_get_softc(dev);
765 smap = ATA_INTEL_SMAP(ctlr, ch);
766 port = (port == 1) ? 1 : 0;
780 ATA_INTEL_LOCK(ctlr);
781 pci_write_config(parent, 0xa0,
782 0x50 + smap[port] * 0x10 + reg * 4, 4);
783 pci_write_config(parent, 0xa4, value, 4);
784 ATA_INTEL_UNLOCK(ctlr);
789 ata_intel_sata_sidpr_write(device_t dev, int port, int reg, u_int32_t value)
791 struct ata_pci_controller *ctlr;
792 struct ata_channel *ch;
795 parent = device_get_parent(dev);
796 ctlr = device_get_softc(parent);
797 ch = device_get_softc(dev);
798 port = (port == 1) ? 1 : 0;
812 ATA_INTEL_LOCK(ctlr);
813 ATA_IDX_OUTL(ch, ATA_IDX_ADDR, ((ch->unit * 2 + port) << 8) + reg);
814 ATA_IDX_OUTL(ch, ATA_IDX_DATA, value);
815 ATA_INTEL_UNLOCK(ctlr);
820 ata_intel_31244_ch_attach(device_t dev)
822 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
823 struct ata_channel *ch = device_get_softc(dev);
827 ata_pci_dmainit(dev);
829 ch_offset = 0x200 + ch->unit * 0x200;
831 for (i = ATA_DATA; i < ATA_MAX_RES; i++)
832 ch->r_io[i].res = ctlr->r_res2;
834 /* setup ATA registers */
835 ch->r_io[ATA_DATA].offset = ch_offset + 0x00;
836 ch->r_io[ATA_FEATURE].offset = ch_offset + 0x06;
837 ch->r_io[ATA_COUNT].offset = ch_offset + 0x08;
838 ch->r_io[ATA_SECTOR].offset = ch_offset + 0x0c;
839 ch->r_io[ATA_CYL_LSB].offset = ch_offset + 0x10;
840 ch->r_io[ATA_CYL_MSB].offset = ch_offset + 0x14;
841 ch->r_io[ATA_DRIVE].offset = ch_offset + 0x18;
842 ch->r_io[ATA_COMMAND].offset = ch_offset + 0x1d;
843 ch->r_io[ATA_ERROR].offset = ch_offset + 0x04;
844 ch->r_io[ATA_STATUS].offset = ch_offset + 0x1c;
845 ch->r_io[ATA_ALTSTAT].offset = ch_offset + 0x28;
846 ch->r_io[ATA_CONTROL].offset = ch_offset + 0x29;
848 /* setup DMA registers */
849 ch->r_io[ATA_SSTATUS].offset = ch_offset + 0x100;
850 ch->r_io[ATA_SERROR].offset = ch_offset + 0x104;
851 ch->r_io[ATA_SCONTROL].offset = ch_offset + 0x108;
853 /* setup SATA registers */
854 ch->r_io[ATA_BMCMD_PORT].offset = ch_offset + 0x70;
855 ch->r_io[ATA_BMSTAT_PORT].offset = ch_offset + 0x72;
856 ch->r_io[ATA_BMDTP_PORT].offset = ch_offset + 0x74;
858 ch->flags |= ATA_NO_SLAVE;
859 ch->flags |= ATA_SATA;
861 ch->hw.status = ata_intel_31244_status;
862 ch->hw.tf_write = ata_intel_31244_tf_write;
864 /* enable PHY state change interrupt */
865 ATA_OUTL(ctlr->r_res2, 0x4,
866 ATA_INL(ctlr->r_res2, 0x04) | (0x01 << (ch->unit << 3)));
871 ata_intel_31244_ch_detach(device_t dev)
874 ata_pci_dmafini(dev);
879 ata_intel_31244_status(device_t dev)
881 /* do we have any PHY events ? */
882 ata_sata_phy_check_events(dev, -1);
884 /* any drive action to take care of ? */
885 return ata_pci_status(dev);
889 ata_intel_31244_tf_write(struct ata_request *request)
891 struct ata_channel *ch = device_get_softc(request->parent);
893 struct ata_device *atadev = device_get_softc(request->dev);
896 if (request->flags & ATA_R_48BIT) {
897 ATA_IDX_OUTW(ch, ATA_FEATURE, request->u.ata.feature);
898 ATA_IDX_OUTW(ch, ATA_COUNT, request->u.ata.count);
899 ATA_IDX_OUTW(ch, ATA_SECTOR, ((request->u.ata.lba >> 16) & 0xff00) |
900 (request->u.ata.lba & 0x00ff));
901 ATA_IDX_OUTW(ch, ATA_CYL_LSB, ((request->u.ata.lba >> 24) & 0xff00) |
902 ((request->u.ata.lba >> 8) & 0x00ff));
903 ATA_IDX_OUTW(ch, ATA_CYL_MSB, ((request->u.ata.lba >> 32) & 0xff00) |
904 ((request->u.ata.lba >> 16) & 0x00ff));
905 ATA_IDX_OUTW(ch, ATA_DRIVE, ATA_D_LBA | ATA_DEV(request->unit));
908 ATA_IDX_OUTB(ch, ATA_FEATURE, request->u.ata.feature);
909 ATA_IDX_OUTB(ch, ATA_COUNT, request->u.ata.count);
911 if (atadev->flags & ATA_D_USE_CHS) {
914 if (atadev->param.atavalid & ATA_FLAG_54_58) {
915 heads = atadev->param.current_heads;
916 sectors = atadev->param.current_sectors;
919 heads = atadev->param.heads;
920 sectors = atadev->param.sectors;
922 ATA_IDX_OUTB(ch, ATA_SECTOR, (request->u.ata.lba % sectors)+1);
923 ATA_IDX_OUTB(ch, ATA_CYL_LSB,
924 (request->u.ata.lba / (sectors * heads)));
925 ATA_IDX_OUTB(ch, ATA_CYL_MSB,
926 (request->u.ata.lba / (sectors * heads)) >> 8);
927 ATA_IDX_OUTB(ch, ATA_DRIVE, ATA_D_IBM | ATA_DEV(request->unit) |
928 (((request->u.ata.lba% (sectors * heads)) /
933 ATA_IDX_OUTB(ch, ATA_SECTOR, request->u.ata.lba);
934 ATA_IDX_OUTB(ch, ATA_CYL_LSB, request->u.ata.lba >> 8);
935 ATA_IDX_OUTB(ch, ATA_CYL_MSB, request->u.ata.lba >> 16);
936 ATA_IDX_OUTB(ch, ATA_DRIVE,
937 ATA_D_IBM | ATA_D_LBA | ATA_DEV(request->unit) |
938 ((request->u.ata.lba >> 24) & 0x0f));
946 ata_intel_31244_reset(device_t dev)
948 struct ata_channel *ch = device_get_softc(dev);
950 if (ata_sata_phy_reset(dev, -1, 1))
951 ata_generic_reset(dev);
956 ATA_DECLARE_DRIVER(ata_intel);
957 MODULE_DEPEND(ata_intel, ata_ahci, 1, 1, 1);