2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ata/ata-pci.h>
54 /* local prototypes */
55 static int ata_ite_chipinit(device_t dev);
56 static void ata_ite_821x_setmode(device_t dev, int mode);
57 static void ata_ite_8213_setmode(device_t dev, int mode);
61 * Integrated Technology Express Inc. (ITE) chipset support functions
64 ata_ite_probe(device_t dev)
66 struct ata_pci_controller *ctlr = device_get_softc(dev);
67 static struct ata_chip_id ids[] =
68 {{ ATA_IT8213F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8213F" },
69 { ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" },
70 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" },
73 if (pci_get_vendor(dev) != ATA_ITE_ID)
76 if (!(ctlr->chip = ata_match_chip(dev, ids)))
80 ctlr->chipinit = ata_ite_chipinit;
81 return (BUS_PROBE_DEFAULT);
85 ata_ite_chipinit(device_t dev)
87 struct ata_pci_controller *ctlr = device_get_softc(dev);
89 if (ata_setup_interrupt(dev, ata_generic_intr))
92 if (ctlr->chip->chipid == ATA_IT8213F) {
93 /* the ITE 8213F only has one channel */
96 ctlr->setmode = ata_ite_8213_setmode;
99 /* set PCI mode and 66Mhz reference clock */
100 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1);
102 /* set default active & recover timings */
103 pci_write_config(dev, 0x54, 0x31, 1);
104 pci_write_config(dev, 0x56, 0x31, 1);
106 ctlr->setmode = ata_ite_821x_setmode;
113 ata_ite_821x_setmode(device_t dev, int mode)
115 device_t gparent = GRANDPARENT(dev);
116 struct ata_channel *ch = device_get_softc(device_get_parent(dev));
117 struct ata_device *atadev = device_get_softc(dev);
118 int devno = (ch->unit << 1) + atadev->unit;
121 /* correct the mode for what the HW supports */
122 mode = ata_limit_mode(dev, mode, ATA_UDMA6);
124 /* check the CBLID bits for 80 conductor cable detection */
125 if (mode > ATA_UDMA2 && (pci_read_config(gparent, 0x40, 2) &
126 (ch->unit ? (1<<3) : (1<<2)))) {
127 ata_print_cable(dev, "controller");
131 /* set the wanted mode on the device */
132 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
135 device_printf(dev, "%s setting %s on ITE8212F chip\n",
136 (error) ? "failed" : "success", ata_mode2str(mode));
138 /* if the device accepted the mode change, setup the HW accordingly */
140 if (mode >= ATA_UDMA0) {
141 u_int8_t udmatiming[] =
142 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 };
144 /* enable UDMA mode */
145 pci_write_config(gparent, 0x50,
146 pci_read_config(gparent, 0x50, 1) &
147 ~(1 << (devno + 3)), 1);
149 /* set UDMA timing */
150 pci_write_config(gparent,
151 0x56 + (ch->unit << 2) + atadev->unit,
152 udmatiming[mode & ATA_MODE_MASK], 1);
155 u_int8_t chtiming[] =
156 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 };
158 /* disable UDMA mode */
159 pci_write_config(gparent, 0x50,
160 pci_read_config(gparent, 0x50, 1) |
161 (1 << (devno + 3)), 1);
163 /* set active and recover timing (shared between master & slave) */
164 if (pci_read_config(gparent, 0x54 + (ch->unit << 2), 1) <
165 chtiming[ata_mode2idx(mode)])
166 pci_write_config(gparent, 0x54 + (ch->unit << 2),
167 chtiming[ata_mode2idx(mode)], 1);
174 ata_ite_8213_setmode(device_t dev, int mode)
176 device_t gparent = GRANDPARENT(dev);
177 struct ata_pci_controller *ctlr = device_get_softc(gparent);
178 struct ata_device *atadev = device_get_softc(dev);
179 u_int16_t reg40 = pci_read_config(gparent, 0x40, 2);
180 u_int8_t reg44 = pci_read_config(gparent, 0x44, 1);
181 u_int8_t reg48 = pci_read_config(gparent, 0x48, 1);
182 u_int16_t reg4a = pci_read_config(gparent, 0x4a, 2);
183 u_int16_t reg54 = pci_read_config(gparent, 0x54, 2);
184 u_int16_t mask40 = 0, new40 = 0;
185 u_int8_t mask44 = 0, new44 = 0;
186 int devno = atadev->unit;
188 u_int8_t timings[] = { 0x00, 0x00, 0x10, 0x21, 0x23, 0x10, 0x21, 0x23,
189 0x23, 0x23, 0x23, 0x23, 0x23, 0x23 };
191 mode = ata_limit_mode(dev, mode, ctlr->chip->max_dma);
193 if (mode > ATA_UDMA2 && !(reg54 & (0x10 << devno))) {
194 ata_print_cable(dev, "controller");
198 error = ata_controlcmd(dev, ATA_SETFEATURES, ATA_SF_SETXFER, 0, mode);
201 device_printf(dev, "%ssetting %s on %s chip\n",
202 (error) ? "FAILURE " : "",
203 ata_mode2str(mode), ctlr->chip->text);
205 if (mode >= ATA_UDMA0) {
206 u_int8_t utimings[] = { 0x00, 0x01, 0x10, 0x01, 0x10, 0x01, 0x10 };
208 pci_write_config(gparent, 0x48, reg48 | (0x0001 << devno), 2);
209 pci_write_config(gparent, 0x4a,
210 (reg4a & ~(0x3 << (devno << 2))) |
211 (utimings[mode & ATA_MODE_MASK] << (devno<<2)), 2);
214 pci_write_config(gparent, 0x48, reg48 & ~(0x0001 << devno), 2);
215 pci_write_config(gparent, 0x4a, (reg4a & ~(0x3 << (devno << 2))),2);
217 if (mode >= ATA_UDMA2)
218 reg54 |= (0x1 << devno);
220 reg54 &= ~(0x1 << devno);
221 if (mode >= ATA_UDMA5)
222 reg54 |= (0x1000 << devno);
224 reg54 &= ~(0x1000 << devno);
225 pci_write_config(gparent, 0x54, reg54, 2);
229 if (atadev->unit == ATA_MASTER) {
230 reg40 |= (ata_atapi(dev) ? 0x04 : 0x00);
232 new40 = timings[ata_mode2idx(mode)] << 8;
235 reg40 |= (ata_atapi(dev) ? 0x40 : 0x00);
237 new44 = ((timings[ata_mode2idx(mode)] & 0x30) >> 2) |
238 (timings[ata_mode2idx(mode)] & 0x03);
240 pci_write_config(gparent, 0x40, (reg40 & ~mask40) | new40, 4);
241 pci_write_config(gparent, 0x44, (reg44 & ~mask44) | new44, 1);
247 ATA_DECLARE_DRIVER(ata_ite);