2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
39 #include <sys/mutex.h>
41 #include <sys/taskqueue.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
49 #include <dev/ata/ata-all.h>
50 #include <dev/ata/ata-pci.h>
53 /* local prototypes */
54 static int ata_cmd_ch_attach(device_t dev);
55 static int ata_cmd_status(device_t dev);
56 static int ata_cmd_setmode(device_t dev, int target, int mode);
57 static int ata_sii_ch_attach(device_t dev);
58 static int ata_sii_ch_detach(device_t dev);
59 static int ata_sii_status(device_t dev);
60 static void ata_sii_reset(device_t dev);
61 static int ata_sii_setmode(device_t dev, int target, int mode);
62 static int ata_siiprb_ch_attach(device_t dev);
63 static int ata_siiprb_ch_detach(device_t dev);
64 static int ata_siiprb_status(device_t dev);
65 static int ata_siiprb_begin_transaction(struct ata_request *request);
66 static int ata_siiprb_end_transaction(struct ata_request *request);
67 static int ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result);
68 static int ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t result);
69 static u_int32_t ata_siiprb_softreset(device_t dev, int port);
70 static void ata_siiprb_reset(device_t dev);
71 static void ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
72 static void ata_siiprb_dmainit(device_t dev);
78 #define SII_SETCLK 0x02
83 * Silicon Image Inc. (SiI) (former CMD) chipset support functions
86 ata_sii_probe(device_t dev)
88 struct ata_pci_controller *ctlr = device_get_softc(dev);
89 static const struct ata_chip_id ids[] =
90 {{ ATA_SII3114, 0x00, SII_MEMIO, SII_4CH, ATA_SA150, "3114" },
91 { ATA_SII3512, 0x02, SII_MEMIO, 0, ATA_SA150, "3512" },
92 { ATA_SII3112, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
93 { ATA_SII3112_1, 0x02, SII_MEMIO, 0, ATA_SA150, "3112" },
94 { ATA_SII3512, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3512" },
95 { ATA_SII3112, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
96 { ATA_SII3112_1, 0x00, SII_MEMIO, SII_BUG, ATA_SA150, "3112" },
97 { ATA_SII3124, 0x00, SII_PRBIO, SII_4CH, ATA_SA300, "3124" },
98 { ATA_SII3132, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
99 { ATA_SII3132_1, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
100 { ATA_SII3132_2, 0x00, SII_PRBIO, 0, ATA_SA300, "3132" },
101 { ATA_SII0680, 0x00, SII_MEMIO, SII_SETCLK, ATA_UDMA6, "680" },
102 { ATA_CMD649, 0x00, 0, SII_INTR, ATA_UDMA5, "(CMD) 649" },
103 { ATA_CMD648, 0x00, 0, SII_INTR, ATA_UDMA4, "(CMD) 648" },
104 { ATA_CMD646, 0x07, 0, 0, ATA_UDMA2, "(CMD) 646U2" },
105 { ATA_CMD646, 0x00, 0, 0, ATA_WDMA2, "(CMD) 646" },
106 { 0, 0, 0, 0, 0, 0}};
108 if (pci_get_vendor(dev) != ATA_SILICON_IMAGE_ID)
111 if (!(ctlr->chip = ata_match_chip(dev, ids)))
115 ctlr->chipinit = ata_sii_chipinit;
116 return (BUS_PROBE_DEFAULT);
120 ata_sii_chipinit(device_t dev)
122 struct ata_pci_controller *ctlr = device_get_softc(dev);
124 if (ata_setup_interrupt(dev, ata_generic_intr))
127 switch (ctlr->chip->cfg1) {
129 ctlr->r_type1 = SYS_RES_MEMORY;
130 ctlr->r_rid1 = PCIR_BAR(0);
131 if (!(ctlr->r_res1 = bus_alloc_resource_any(dev, ctlr->r_type1,
132 &ctlr->r_rid1, RF_ACTIVE)))
135 ctlr->r_rid2 = PCIR_BAR(2);
136 ctlr->r_type2 = SYS_RES_MEMORY;
137 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
138 &ctlr->r_rid2, RF_ACTIVE))){
139 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,ctlr->r_res1);
143 if (!bus_space_map(rman_get_bustag(ctlr->r_res2),
144 rman_get_bushandle(ctlr->r_res2), rman_get_size(ctlr->r_res2),
145 BUS_SPACE_MAP_LINEAR, NULL)) {
146 bus_release_resource(dev, ctlr->r_type1, ctlr->r_rid1,
148 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2,
153 ctlr->ch_attach = ata_siiprb_ch_attach;
154 ctlr->ch_detach = ata_siiprb_ch_detach;
155 ctlr->reset = ata_siiprb_reset;
156 ctlr->setmode = ata_sata_setmode;
157 ctlr->getrev = ata_sata_getrev;
158 ctlr->channels = (ctlr->chip->cfg2 == SII_4CH) ? 4 : 2;
160 /* reset controller */
161 ATA_OUTL(ctlr->r_res1, 0x0040, 0x80000000);
163 ATA_OUTL(ctlr->r_res1, 0x0040, 0x0000000f);
167 ctlr->r_type2 = SYS_RES_MEMORY;
168 ctlr->r_rid2 = PCIR_BAR(5);
169 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
170 &ctlr->r_rid2, RF_ACTIVE))){
171 if (ctlr->chip->chipid != ATA_SII0680 ||
172 (pci_read_config(dev, 0x8a, 1) & 1))
176 if (ctlr->chip->cfg2 & SII_SETCLK) {
177 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
178 pci_write_config(dev, 0x8a,
179 (pci_read_config(dev, 0x8a, 1) & 0xcf)|0x10,1);
180 if ((pci_read_config(dev, 0x8a, 1) & 0x30) != 0x10)
181 device_printf(dev, "%s could not set ATA133 clock\n",
185 /* if we have 4 channels enable the second set */
186 if (ctlr->chip->cfg2 & SII_4CH) {
187 ATA_OUTL(ctlr->r_res2, 0x0200, 0x00000002);
191 /* dont block interrupts from any channel */
192 pci_write_config(dev, 0x48,
193 (pci_read_config(dev, 0x48, 4) & ~0x03c00000), 4);
195 /* enable PCI interrupt as BIOS might not */
196 pci_write_config(dev, 0x8a, (pci_read_config(dev, 0x8a, 1) & 0x3f), 1);
199 ctlr->ch_attach = ata_sii_ch_attach;
200 ctlr->ch_detach = ata_sii_ch_detach;
203 if (ctlr->chip->max_dma >= ATA_SA150) {
204 ctlr->reset = ata_sii_reset;
205 ctlr->setmode = ata_sata_setmode;
206 ctlr->getrev = ata_sata_getrev;
209 ctlr->setmode = ata_sii_setmode;
213 if ((pci_read_config(dev, 0x51, 1) & 0x08) != 0x08) {
214 device_printf(dev, "HW has secondary channel disabled\n");
218 /* enable interrupt as BIOS might not */
219 pci_write_config(dev, 0x71, 0x01, 1);
221 ctlr->ch_attach = ata_cmd_ch_attach;
222 ctlr->ch_detach = ata_pci_ch_detach;
223 ctlr->setmode = ata_cmd_setmode;
230 ata_cmd_ch_attach(device_t dev)
232 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
233 struct ata_channel *ch = device_get_softc(dev);
235 /* setup the usual register normal pci style */
236 if (ata_pci_ch_attach(dev))
239 if (ctlr->chip->cfg2 & SII_INTR)
240 ch->hw.status = ata_cmd_status;
242 ch->flags |= ATA_NO_ATAPI_DMA;
248 ata_cmd_status(device_t dev)
250 struct ata_channel *ch = device_get_softc(dev);
253 if (((reg71 = pci_read_config(device_get_parent(dev), 0x71, 1)) &
254 (ch->unit ? 0x08 : 0x04))) {
255 pci_write_config(device_get_parent(dev), 0x71,
256 reg71 & ~(ch->unit ? 0x04 : 0x08), 1);
257 return ata_pci_status(dev);
263 ata_cmd_setmode(device_t dev, int target, int mode)
265 device_t parent = device_get_parent(dev);
266 struct ata_pci_controller *ctlr = device_get_softc(parent);
267 struct ata_channel *ch = device_get_softc(dev);
268 int devno = (ch->unit << 1) + target;
269 int treg = 0x54 + ((devno < 3) ? (devno << 1) : 7);
270 int ureg = ch->unit ? 0x7b : 0x73;
272 static const uint8_t piotimings[] =
273 { 0xa9, 0x57, 0x44, 0x32, 0x3f, 0x87, 0x32, 0x3f };
274 static const uint8_t udmatimings[][2] =
275 { { 0x31, 0xc2 }, { 0x21, 0x82 }, { 0x11, 0x42 },
276 { 0x25, 0x8a }, { 0x15, 0x4a }, { 0x05, 0x0a } };
278 mode = min(mode, ctlr->chip->max_dma);
279 if (mode >= ATA_UDMA0) {
280 u_int8_t umode = pci_read_config(parent, ureg, 1);
282 umode &= ~(target == 0 ? 0x35 : 0xca);
283 umode |= udmatimings[mode & ATA_MODE_MASK][target];
284 pci_write_config(parent, ureg, umode, 1);
287 pci_write_config(parent, ureg,
288 pci_read_config(parent, ureg, 1) &
289 ~(target == 0 ? 0x35 : 0xca), 1);
292 pci_write_config(parent, treg, piotimings[ata_mode2idx(piomode)], 1);
297 ata_sii_ch_attach(device_t dev)
299 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
300 struct ata_channel *ch = device_get_softc(dev);
301 int unit01 = (ch->unit & 1), unit10 = (ch->unit & 2);
304 for (i = ATA_DATA; i <= ATA_COMMAND; i++) {
305 ch->r_io[i].res = ctlr->r_res2;
306 ch->r_io[i].offset = 0x80 + i + (unit01 << 6) + (unit10 << 8);
308 ch->r_io[ATA_CONTROL].res = ctlr->r_res2;
309 ch->r_io[ATA_CONTROL].offset = 0x8a + (unit01 << 6) + (unit10 << 8);
310 ch->r_io[ATA_IDX_ADDR].res = ctlr->r_res2;
311 ata_default_registers(dev);
313 ch->r_io[ATA_BMCMD_PORT].res = ctlr->r_res2;
314 ch->r_io[ATA_BMCMD_PORT].offset = 0x00 + (unit01 << 3) + (unit10 << 8);
315 ch->r_io[ATA_BMSTAT_PORT].res = ctlr->r_res2;
316 ch->r_io[ATA_BMSTAT_PORT].offset = 0x02 + (unit01 << 3) + (unit10 << 8);
317 ch->r_io[ATA_BMDTP_PORT].res = ctlr->r_res2;
318 ch->r_io[ATA_BMDTP_PORT].offset = 0x04 + (unit01 << 3) + (unit10 << 8);
320 if (ctlr->chip->max_dma >= ATA_SA150) {
321 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
322 ch->r_io[ATA_SSTATUS].offset = 0x104 + (unit01 << 7) + (unit10 << 8);
323 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
324 ch->r_io[ATA_SERROR].offset = 0x108 + (unit01 << 7) + (unit10 << 8);
325 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
326 ch->r_io[ATA_SCONTROL].offset = 0x100 + (unit01 << 7) + (unit10 << 8);
327 ch->flags |= ATA_NO_SLAVE;
328 ch->flags |= ATA_SATA;
329 ch->flags |= ATA_KNOWN_PRESENCE;
331 /* enable PHY state change interrupt */
332 ATA_OUTL(ctlr->r_res2, 0x148 + (unit01 << 7) + (unit10 << 8),(1 << 16));
335 if (ctlr->chip->cfg2 & SII_BUG) {
336 /* work around errata in early chips */
337 ch->dma.boundary = 8192;
338 ch->dma.segsize = 15 * DEV_BSIZE;
342 ch->hw.status = ata_sii_status;
343 if (ctlr->chip->cfg2 & SII_SETCLK)
344 ch->flags |= ATA_CHECKS_CABLE;
346 ata_pci_dmainit(dev);
352 ata_sii_ch_detach(device_t dev)
355 ata_pci_dmafini(dev);
360 ata_sii_status(device_t dev)
362 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
363 struct ata_channel *ch = device_get_softc(dev);
364 int offset0 = ((ch->unit & 1) << 3) + ((ch->unit & 2) << 8);
365 int offset1 = ((ch->unit & 1) << 6) + ((ch->unit & 2) << 8);
367 /* do we have any PHY events ? */
368 if (ctlr->chip->max_dma >= ATA_SA150 &&
369 (ATA_INL(ctlr->r_res2, 0x10 + offset0) & 0x00000010))
370 ata_sata_phy_check_events(dev, -1);
372 if (ATA_INL(ctlr->r_res2, 0xa0 + offset1) & 0x00000800)
373 return ata_pci_status(dev);
379 ata_sii_reset(device_t dev)
381 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
382 struct ata_channel *ch = device_get_softc(dev);
383 int offset = ((ch->unit & 1) << 7) + ((ch->unit & 2) << 8);
386 /* Apply R_ERR on DMA activate FIS errata workaround. */
387 val = ATA_INL(ctlr->r_res2, 0x14c + offset);
388 if ((val & 0x3) == 0x1)
389 ATA_OUTL(ctlr->r_res2, 0x14c + offset, val & ~0x3);
391 if (ata_sata_phy_reset(dev, -1, 1))
392 ata_generic_reset(dev);
398 ata_sii_setmode(device_t dev, int target, int mode)
400 device_t parent = device_get_parent(dev);
401 struct ata_pci_controller *ctlr = device_get_softc(parent);
402 struct ata_channel *ch = device_get_softc(dev);
403 int rego = (ch->unit << 4) + (target << 1);
404 int mreg = ch->unit ? 0x84 : 0x80;
405 int mask = 0x03 << (target << 2);
406 int mval = pci_read_config(parent, mreg, 1) & ~mask;
408 u_int8_t preg = 0xa4 + rego;
409 u_int8_t dreg = 0xa8 + rego;
410 u_int8_t ureg = 0xac + rego;
411 static const uint16_t piotimings[] =
412 { 0x328a, 0x2283, 0x1104, 0x10c3, 0x10c1 };
413 static const uint16_t dmatimings[] = { 0x2208, 0x10c2, 0x10c1 };
414 static const uint8_t udmatimings[] =
415 { 0xf, 0xb, 0x7, 0x5, 0x3, 0x2, 0x1 };
417 mode = min(mode, ctlr->chip->max_dma);
419 if (ctlr->chip->cfg2 & SII_SETCLK) {
420 if (ata_dma_check_80pin && mode > ATA_UDMA2 &&
421 (pci_read_config(parent, 0x79, 1) &
422 (ch->unit ? 0x02 : 0x01))) {
423 ata_print_cable(dev, "controller");
427 if (mode >= ATA_UDMA0) {
428 pci_write_config(parent, mreg,
429 mval | (0x03 << (target << 2)), 1);
430 pci_write_config(parent, ureg,
431 (pci_read_config(parent, ureg, 1) & ~0x3f) |
432 udmatimings[mode & ATA_MODE_MASK], 1);
434 } else if (mode >= ATA_WDMA0) {
435 pci_write_config(parent, mreg,
436 mval | (0x02 << (target << 2)), 1);
437 pci_write_config(parent, dreg, dmatimings[mode & ATA_MODE_MASK], 2);
438 piomode = (mode == ATA_WDMA0) ? ATA_PIO0 :
439 (mode == ATA_WDMA1) ? ATA_PIO3 : ATA_PIO4;
441 pci_write_config(parent, mreg,
442 mval | (0x01 << (target << 2)), 1);
445 pci_write_config(parent, preg, piotimings[ata_mode2idx(piomode)], 2);
449 struct ata_siiprb_dma_prdentry {
455 #define ATA_SIIPRB_DMA_ENTRIES 129
456 struct ata_siiprb_ata_command {
457 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
460 struct ata_siiprb_atapi_command {
462 struct ata_siiprb_dma_prdentry prd[ATA_SIIPRB_DMA_ENTRIES];
465 struct ata_siiprb_command {
467 u_int16_t protocol_override;
468 u_int32_t transfer_count;
471 struct ata_siiprb_ata_command ata;
472 struct ata_siiprb_atapi_command atapi;
477 ata_siiprb_ch_attach(device_t dev)
479 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
480 struct ata_channel *ch = device_get_softc(dev);
481 int offset = ch->unit * 0x2000;
483 ata_siiprb_dmainit(dev);
485 /* set the SATA resources */
486 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
487 ch->r_io[ATA_SSTATUS].offset = 0x1f04 + offset;
488 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
489 ch->r_io[ATA_SERROR].offset = 0x1f08 + offset;
490 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
491 ch->r_io[ATA_SCONTROL].offset = 0x1f00 + offset;
492 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
493 ch->r_io[ATA_SACTIVE].offset = 0x1f0c + offset;
495 ch->hw.status = ata_siiprb_status;
496 ch->hw.begin_transaction = ata_siiprb_begin_transaction;
497 ch->hw.end_transaction = ata_siiprb_end_transaction;
498 ch->hw.command = NULL; /* not used here */
499 ch->hw.softreset = ata_siiprb_softreset;
500 ch->hw.pm_read = ata_siiprb_pm_read;
501 ch->hw.pm_write = ata_siiprb_pm_write;
502 ch->flags |= ATA_NO_SLAVE;
503 ch->flags |= ATA_SATA;
508 ata_siiprb_ch_detach(device_t dev)
510 struct ata_channel *ch = device_get_softc(dev);
512 if (ch->dma.work_tag && ch->dma.work_map)
513 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
514 BUS_DMASYNC_POSTWRITE);
520 ata_siiprb_status(device_t dev)
522 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
523 struct ata_channel *ch = device_get_softc(dev);
524 u_int32_t action = ATA_INL(ctlr->r_res1, 0x0044);
525 int offset = ch->unit * 0x2000;
527 if (action & (1 << ch->unit)) {
528 u_int32_t istatus = ATA_INL(ctlr->r_res2, 0x1008 + offset);
530 /* do we have any PHY events ? */
531 ata_sata_phy_check_events(dev, -1);
533 /* clear interrupt(s) */
534 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, istatus);
536 /* do we have any device action ? */
537 return (istatus & 0x00000003);
543 ata_siiprb_begin_transaction(struct ata_request *request)
545 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
546 struct ata_channel *ch = device_get_softc(request->parent);
547 struct ata_siiprb_command *prb;
548 struct ata_siiprb_dma_prdentry *prd;
549 int offset = ch->unit * 0x2000;
553 if (request->u.ata.command == ATA_DEVICE_RESET) {
555 return ATA_OP_FINISHED;
558 /* get a piece of the workspace for this request */
559 prb = (struct ata_siiprb_command *)ch->dma.work;
561 /* clear the prb structure */
562 bzero(prb, sizeof(struct ata_siiprb_command));
564 /* setup the FIS for this request */
565 if (!ata_request2fis_h2d(request, &prb->fis[0])) {
566 device_printf(request->parent, "setting up SATA FIS failed\n");
567 request->result = EIO;
568 return ATA_OP_FINISHED;
571 /* setup transfer type */
572 if (request->flags & ATA_R_ATAPI) {
573 bcopy(request->u.atapi.ccb, prb->u.atapi.ccb, 16);
574 if (request->flags & ATA_R_ATAPI16)
575 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000020);
577 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000020);
578 if (request->flags & ATA_R_READ)
579 prb->control = htole16(0x0010);
580 if (request->flags & ATA_R_WRITE)
581 prb->control = htole16(0x0020);
582 prd = &prb->u.atapi.prd[0];
585 prd = &prb->u.ata.prd[0];
587 /* if request moves data setup and load SG list */
588 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
589 if (ch->dma.load(request, prd, NULL)) {
590 device_printf(request->parent, "setting up DMA failed\n");
591 request->result = EIO;
592 return ATA_OP_FINISHED;
596 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
598 /* activate the prb */
599 prb_bus = ch->dma.work_bus;
600 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
601 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus>>32);
603 /* start the timeout */
604 callout_reset(&request->callout, request->timeout * hz,
605 (timeout_t*)ata_timeout, request);
606 return ATA_OP_CONTINUES;
610 ata_siiprb_end_transaction(struct ata_request *request)
612 struct ata_pci_controller *ctlr=device_get_softc(device_get_parent(request->parent));
613 struct ata_channel *ch = device_get_softc(request->parent);
614 struct ata_siiprb_command *prb;
615 int offset = ch->unit * 0x2000;
618 /* kill the timeout */
619 callout_stop(&request->callout);
621 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
623 prb = (struct ata_siiprb_command *)
624 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
626 /* any controller errors flagged ? */
627 if ((error = ATA_INL(ctlr->r_res2, 0x1024 + offset))) {
629 printf("ata_siiprb_end_transaction %s error=%08x\n",
630 ata_cmd2str(request), error);
632 /* if device error status get details */
633 if (error == 1 || error == 2) {
634 request->status = prb->fis[2];
635 if (request->status & ATA_S_ERROR)
636 request->error = prb->fis[3];
639 /* SOS XXX handle other controller errors here */
641 /* initialize port */
642 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000004);
644 /* poll for port ready */
645 for (timeout = 0; timeout < 1000; timeout++) {
647 if (ATA_INL(ctlr->r_res2, 0x1008 + offset) & 0x00040000)
652 device_printf(ch->dev, "port initialize timeout\n");
654 device_printf(ch->dev, "port initialize time=%dms\n", timeout);
658 /* Read back registers to the request struct. */
659 if ((request->flags & ATA_R_ATAPI) == 0 &&
660 ((request->status & ATA_S_ERROR) ||
661 (request->flags & (ATA_R_CONTROL | ATA_R_NEEDRESULT)))) {
662 request->u.ata.count = prb->fis[12] | ((u_int16_t)prb->fis[13] << 8);
663 request->u.ata.lba = prb->fis[4] | ((u_int64_t)prb->fis[5] << 8) |
664 ((u_int64_t)prb->fis[6] << 16);
665 if (request->flags & ATA_R_48BIT)
666 request->u.ata.lba |= ((u_int64_t)prb->fis[8] << 24) |
667 ((u_int64_t)prb->fis[9] << 32) |
668 ((u_int64_t)prb->fis[10] << 40);
670 request->u.ata.lba |= ((u_int64_t)(prb->fis[7] & 0x0f) << 24);
673 /* update progress */
674 if (!(request->status & ATA_S_ERROR) && !(request->flags & ATA_R_TIMEOUT)) {
675 if (request->flags & ATA_R_READ)
676 request->donecount = le32toh(prb->transfer_count);
678 request->donecount = request->bytecount;
681 /* release SG list etc */
682 ch->dma.unload(request);
684 return ATA_OP_FINISHED;
688 ata_siiprb_issue_cmd(device_t dev)
690 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
691 struct ata_channel *ch = device_get_softc(dev);
692 u_int64_t prb_bus = ch->dma.work_bus;
694 int offset = ch->unit * 0x2000;
697 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_PREWRITE);
699 /* issue command to chip */
700 ATA_OUTL(ctlr->r_res2, 0x1c00 + offset, prb_bus);
701 ATA_OUTL(ctlr->r_res2, 0x1c04 + offset, prb_bus >> 32);
703 /* poll for command finished */
704 for (timeout = 0; timeout < 10000; timeout++) {
706 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00010000)
710 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map, BUS_DMASYNC_POSTWRITE);
712 // SOS XXX ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x00010000);
713 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x08ff08ff);
719 device_printf(dev, "siiprb_issue_cmd time=%dms status=%08x\n",
725 ata_siiprb_pm_read(device_t dev, int port, int reg, u_int32_t *result)
727 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
728 struct ata_channel *ch = device_get_softc(dev);
729 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
730 int offset = ch->unit * 0x2000;
733 *result = ATA_IDX_INL(ch, reg);
751 bzero(prb, sizeof(struct ata_siiprb_command));
752 prb->fis[0] = 0x27; /* host to device */
753 prb->fis[1] = 0x8f; /* command FIS to PM port */
754 prb->fis[2] = ATA_READ_PM;
757 if (ata_siiprb_issue_cmd(dev)) {
758 device_printf(dev, "error reading PM port\n");
761 prb = (struct ata_siiprb_command *)
762 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
763 *result = prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
768 ata_siiprb_pm_write(device_t dev, int port, int reg, u_int32_t value)
770 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
771 struct ata_channel *ch = device_get_softc(dev);
772 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
773 int offset = ch->unit * 0x2000;
776 ATA_IDX_OUTL(ch, reg, value);
794 bzero(prb, sizeof(struct ata_siiprb_command));
795 prb->fis[0] = 0x27; /* host to device */
796 prb->fis[1] = 0x8f; /* command FIS to PM port */
797 prb->fis[2] = ATA_WRITE_PM;
800 prb->fis[12] = value & 0xff;
801 prb->fis[4] = (value >> 8) & 0xff;
802 prb->fis[5] = (value >> 16) & 0xff;
803 prb->fis[6] = (value >> 24) & 0xff;
804 if (ata_siiprb_issue_cmd(dev)) {
805 device_printf(dev, "error writing PM port\n");
808 prb = (struct ata_siiprb_command *)
809 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
814 ata_siiprb_softreset(device_t dev, int port)
816 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
817 struct ata_channel *ch = device_get_softc(dev);
818 struct ata_siiprb_command *prb = (struct ata_siiprb_command *)ch->dma.work;
820 int offset = ch->unit * 0x2000;
822 /* setup the workspace for a soft reset command */
823 bzero(prb, sizeof(struct ata_siiprb_command));
824 prb->control = htole16(0x0080);
825 prb->fis[1] = port & 0x0f;
827 /* issue soft reset */
828 if (ata_siiprb_issue_cmd(dev))
833 /* get possible signature */
834 prb = (struct ata_siiprb_command *)
835 ((u_int8_t *)rman_get_virtual(ctlr->r_res2) + offset);
836 signature=prb->fis[12]|(prb->fis[4]<<8)|(prb->fis[5]<<16)|(prb->fis[6]<<24);
838 /* clear error bits/interrupt */
839 ATA_IDX_OUTL(ch, ATA_SERROR, 0xffffffff);
845 ata_siiprb_reset(device_t dev)
847 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
848 struct ata_channel *ch = device_get_softc(dev);
849 int offset = ch->unit * 0x2000;
850 u_int32_t status, signature;
853 /* disable interrupts */
854 ATA_OUTL(ctlr->r_res2, 0x1014 + offset, 0x000000ff);
856 /* reset channel HW */
857 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000001);
859 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000001);
862 /* poll for channel ready */
863 for (timeout = 0; timeout < 1000; timeout++) {
864 if ((status = ATA_INL(ctlr->r_res2, 0x1008 + offset)) & 0x00040000)
871 device_printf(dev, "channel HW reset timeout\n");
873 device_printf(dev, "channel HW reset time=%dms\n", timeout);
877 if (!ata_sata_phy_reset(dev, -1, 1)) {
879 device_printf(dev, "phy reset found no device\n");
884 /* issue soft reset */
885 signature = ata_siiprb_softreset(dev, ATA_PM);
887 device_printf(dev, "SIGNATURE=%08x\n", signature);
889 /* figure out whats there */
890 switch (signature >> 16) {
892 ch->devices = ATA_ATA_MASTER;
895 ch->devices = ATA_PORTMULTIPLIER;
896 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x2000); /* enable PM support */
897 //SOS XXX need to clear all PM status and interrupts!!!!
898 ata_pm_identify(dev);
901 ch->devices = ATA_ATAPI_MASTER;
907 device_printf(dev, "siiprb_reset devices=%08x\n", ch->devices);
910 /* clear interrupt(s) */
911 ATA_OUTL(ctlr->r_res2, 0x1008 + offset, 0x000008ff);
913 /* require explicit interrupt ack */
914 ATA_OUTL(ctlr->r_res2, 0x1000 + offset, 0x00000008);
917 ATA_OUTL(ctlr->r_res2, 0x1004 + offset, 0x00000400);
919 /* enable interrupts wanted */
920 ATA_OUTL(ctlr->r_res2, 0x1010 + offset, 0x000000ff);
924 ata_siiprb_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
926 struct ata_dmasetprd_args *args = xsc;
927 struct ata_siiprb_dma_prdentry *prd = args->dmatab;
930 if ((args->error = error))
933 for (i = 0; i < nsegs; i++) {
934 prd[i].addr = htole64(segs[i].ds_addr);
935 prd[i].count = htole32(segs[i].ds_len);
937 prd[i - 1].control = htole32(ATA_DMA_EOT);
938 KASSERT(nsegs <= ATA_SIIPRB_DMA_ENTRIES,("too many DMA segment entries\n"));
943 ata_siiprb_dmainit(device_t dev)
945 struct ata_channel *ch = device_get_softc(dev);
947 /* note start and stop are not used here */
948 ch->dma.setprd = ata_siiprb_dmasetprd;
949 ch->dma.max_address = BUS_SPACE_MAXADDR;
950 ch->dma.max_iosize = (ATA_SIIPRB_DMA_ENTRIES - 1) * PAGE_SIZE;
954 ATA_DECLARE_DRIVER(ata_sii);