2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
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9 * notice, this list of conditions and the following disclaimer,
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14 * similar Disclaimer requirement for further binary redistribution.
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33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/module.h>
37 #include <sys/sysctl.h>
39 #include <sys/malloc.h>
42 #include <machine/stdarg.h>
44 #include <net/ethernet.h> /* XXX for ether_sprintf */
46 #include <dev/ath/ath_hal/ah.h>
49 * WiSoC boards overload the bus tag with information about the
50 * board layout. We must extract the bus space tag from that
51 * indirect structure. For everyone else the tag is passed in
53 * XXX cache indirect ref privately
55 #ifdef AH_SUPPORT_AR5312
57 ((bus_space_tag_t) ((struct ar531x_config *)((ah)->ah_st))->tag)
59 #define BUSTAG(ah) ((ah)->ah_st)
62 extern void ath_hal_printf(struct ath_hal *, const char*, ...)
64 extern void ath_hal_vprintf(struct ath_hal *, const char*, __va_list)
66 extern const char* ath_hal_ether_sprintf(const u_int8_t *mac);
67 extern void *ath_hal_malloc(size_t);
68 extern void ath_hal_free(void *);
70 extern void ath_hal_assert_failed(const char* filename,
71 int lineno, const char* msg);
74 extern void HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...);
77 /* NB: put this here instead of the driver to avoid circular references */
78 SYSCTL_NODE(_hw, OID_AUTO, ath, CTLFLAG_RD, 0, "Atheros driver parameters");
79 SYSCTL_NODE(_hw_ath, OID_AUTO, hal, CTLFLAG_RD, 0, "Atheros HAL parameters");
82 static int ath_hal_debug = 0;
83 SYSCTL_INT(_hw_ath_hal, OID_AUTO, debug, CTLFLAG_RW, &ath_hal_debug,
84 0, "Atheros HAL debugging printfs");
85 TUNABLE_INT("hw.ath.hal.debug", &ath_hal_debug);
88 /* NB: these are deprecated; they exist for now for compatibility */
89 int ath_hal_dma_beacon_response_time = 2; /* in TU's */
90 SYSCTL_INT(_hw_ath_hal, OID_AUTO, dma_brt, CTLFLAG_RW,
91 &ath_hal_dma_beacon_response_time, 0,
92 "Atheros HAL DMA beacon response time");
93 int ath_hal_sw_beacon_response_time = 10; /* in TU's */
94 SYSCTL_INT(_hw_ath_hal, OID_AUTO, sw_brt, CTLFLAG_RW,
95 &ath_hal_sw_beacon_response_time, 0,
96 "Atheros HAL software beacon response time");
97 int ath_hal_additional_swba_backoff = 0; /* in TU's */
98 SYSCTL_INT(_hw_ath_hal, OID_AUTO, swba_backoff, CTLFLAG_RW,
99 &ath_hal_additional_swba_backoff, 0,
100 "Atheros HAL additional SWBA backoff time");
102 MALLOC_DEFINE(M_ATH_HAL, "ath_hal", "ath hal data");
105 ath_hal_malloc(size_t size)
107 return malloc(size, M_ATH_HAL, M_NOWAIT | M_ZERO);
111 ath_hal_free(void* p)
113 return free(p, M_ATH_HAL);
117 ath_hal_vprintf(struct ath_hal *ah, const char* fmt, va_list ap)
123 ath_hal_printf(struct ath_hal *ah, const char* fmt, ...)
127 ath_hal_vprintf(ah, fmt, ap);
132 ath_hal_ether_sprintf(const u_int8_t *mac)
134 return ether_sprintf(mac);
139 HALDEBUG(struct ath_hal *ah, u_int mask, const char* fmt, ...)
141 if (ath_hal_debug & mask) {
144 ath_hal_vprintf(ah, fmt, ap);
148 #endif /* AH_DEBUG */
152 * ALQ register tracing support.
154 * Setting hw.ath.hal.alq=1 enables tracing of all register reads and
155 * writes to the file /tmp/ath_hal.log. The file format is a simple
156 * fixed-size array of records. When done logging set hw.ath.hal.alq=0
157 * and then decode the file with the arcode program (that is part of the
158 * HAL). If you start+stop tracing the data will be appended to an
161 * NB: doesn't handle multiple devices properly; only one DEVICE record
162 * is emitted and the different devices are not identified.
165 #include <sys/pcpu.h>
166 #include <dev/ath/ath_hal/ah_decode.h>
168 static struct alq *ath_hal_alq;
169 static int ath_hal_alq_emitdev; /* need to emit DEVICE record */
170 static u_int ath_hal_alq_lost; /* count of lost records */
171 static const char *ath_hal_logfile = "/tmp/ath_hal.log";
172 static u_int ath_hal_alq_qsize = 64*1024;
175 ath_hal_setlogging(int enable)
180 error = alq_open(&ath_hal_alq, ath_hal_logfile,
181 curthread->td_ucred, ALQ_DEFAULT_CMODE,
182 sizeof (struct athregrec), ath_hal_alq_qsize);
183 ath_hal_alq_lost = 0;
184 ath_hal_alq_emitdev = 1;
185 printf("ath_hal: logging to %s enabled\n",
189 alq_close(ath_hal_alq);
191 printf("ath_hal: logging disabled\n");
198 sysctl_hw_ath_hal_log(SYSCTL_HANDLER_ARGS)
202 enable = (ath_hal_alq != NULL);
203 error = sysctl_handle_int(oidp, &enable, 0, req);
204 if (error || !req->newptr)
207 return (ath_hal_setlogging(enable));
209 SYSCTL_PROC(_hw_ath_hal, OID_AUTO, alq, CTLTYPE_INT|CTLFLAG_RW,
210 0, 0, sysctl_hw_ath_hal_log, "I", "Enable HAL register logging");
211 SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_size, CTLFLAG_RW,
212 &ath_hal_alq_qsize, 0, "In-memory log size (#records)");
213 SYSCTL_INT(_hw_ath_hal, OID_AUTO, alq_lost, CTLFLAG_RW,
214 &ath_hal_alq_lost, 0, "Register operations not logged");
217 ath_hal_alq_get(struct ath_hal *ah)
221 if (ath_hal_alq_emitdev) {
222 ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
224 struct athregrec *r =
225 (struct athregrec *) ale->ae_data;
228 r->val = ah->ah_devid;
229 alq_post(ath_hal_alq, ale);
230 ath_hal_alq_emitdev = 0;
234 ale = alq_get(ath_hal_alq, ALQ_NOWAIT);
241 ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
243 bus_space_tag_t tag = BUSTAG(ah);
244 bus_space_handle_t h = ah->ah_sh;
247 struct ale *ale = ath_hal_alq_get(ah);
249 struct athregrec *r = (struct athregrec *) ale->ae_data;
253 alq_post(ath_hal_alq, ale);
256 #if _BYTE_ORDER == _BIG_ENDIAN
257 if (OS_REG_UNSWAPPED(reg))
258 bus_space_write_4(tag, h, reg, val);
261 bus_space_write_stream_4(tag, h, reg, val);
265 ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
267 bus_space_tag_t tag = BUSTAG(ah);
268 bus_space_handle_t h = ah->ah_sh;
271 #if _BYTE_ORDER == _BIG_ENDIAN
272 if (OS_REG_UNSWAPPED(reg))
273 val = bus_space_read_4(tag, h, reg);
276 val = bus_space_read_stream_4(tag, h, reg);
278 struct ale *ale = ath_hal_alq_get(ah);
280 struct athregrec *r = (struct athregrec *) ale->ae_data;
284 alq_post(ath_hal_alq, ale);
291 OS_MARK(struct ath_hal *ah, u_int id, u_int32_t v)
294 struct ale *ale = ath_hal_alq_get(ah);
296 struct athregrec *r = (struct athregrec *) ale->ae_data;
300 alq_post(ath_hal_alq, ale);
304 #elif defined(AH_DEBUG) || defined(AH_REGOPS_FUNC)
306 * Memory-mapped device register read/write. These are here
307 * as routines when debugging support is enabled and/or when
308 * explicitly configured to use function calls. The latter is
309 * for architectures that might need to do something before
310 * referencing memory (e.g. remap an i/o window).
312 * NB: see the comments in ah_osdep.h about byte-swapping register
313 * reads and writes to understand what's going on below.
317 ath_hal_reg_write(struct ath_hal *ah, u_int32_t reg, u_int32_t val)
319 bus_space_tag_t tag = BUSTAG(ah);
320 bus_space_handle_t h = ah->ah_sh;
322 #if _BYTE_ORDER == _BIG_ENDIAN
323 if (OS_REG_UNSWAPPED(reg))
324 bus_space_write_4(tag, h, reg, val);
327 bus_space_write_stream_4(tag, h, reg, val);
331 ath_hal_reg_read(struct ath_hal *ah, u_int32_t reg)
333 bus_space_tag_t tag = BUSTAG(ah);
334 bus_space_handle_t h = ah->ah_sh;
337 #if _BYTE_ORDER == _BIG_ENDIAN
338 if (OS_REG_UNSWAPPED(reg))
339 val = bus_space_read_4(tag, h, reg);
342 val = bus_space_read_stream_4(tag, h, reg);
345 #endif /* AH_DEBUG || AH_REGOPS_FUNC */
349 ath_hal_assert_failed(const char* filename, int lineno, const char *msg)
351 printf("Atheros HAL assertion failure: %s: line %u: %s\n",
352 filename, lineno, msg);
353 panic("ath_hal_assert");
355 #endif /* AH_ASSERT */