2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
20 #ifndef _DEV_ATH_DESC_H
21 #define _DEV_ATH_DESC_H
23 #include "opt_ah.h" /* NB: required for AH_SUPPORT_AR5416 */
26 * For now, define this for the structure definitions.
27 * Because of how the HAL / driver module currently builds,
28 * it's not very feasible to build the module without
29 * this defined. The rest of the code (eg in the driver
30 * body) can work fine with these fields being uninitialised;
31 * they'll be initialised to 0 anyway.
34 #ifndef AH_SUPPORT_AR5416
35 #define AH_SUPPORT_AR5416 1
39 * Transmit descriptor status. This structure is filled
40 * in only after the tx descriptor process method finds a
41 * ``done'' descriptor; at which point it returns something
42 * other than HAL_EINPROGRESS.
44 * Note that ts_antenna may not be valid for all h/w. It
45 * should be used only if non-zero.
47 struct ath_tx_status {
48 uint16_t ts_seqnum; /* h/w assigned sequence number */
49 uint16_t ts_tstamp; /* h/w assigned timestamp */
50 uint8_t ts_status; /* frame status, 0 => xmit ok */
51 uint8_t ts_rate; /* h/w transmit rate index */
52 int8_t ts_rssi; /* tx ack RSSI */
53 uint8_t ts_shortretry; /* # short retries */
54 uint8_t ts_longretry; /* # long retries */
55 uint8_t ts_virtcol; /* virtual collision count */
56 uint8_t ts_antenna; /* antenna information */
57 uint8_t ts_finaltsi; /* final transmit series index */
58 #ifdef AH_SUPPORT_AR5416
60 uint8_t ts_flags; /* misc flags */
61 uint8_t ts_queue_id; /* AR9300: TX queue id */
62 uint8_t ts_desc_id; /* AR9300: TX descriptor id */
63 uint8_t ts_tid; /* TID */
64 /* #define ts_rssi ts_rssi_combined */
65 uint32_t ts_ba_low; /* blockack bitmap low */
66 uint32_t ts_ba_high; /* blockack bitmap high */
67 uint32_t ts_evm0; /* evm bytes */
70 int8_t ts_rssi_ctl[3]; /* tx ack RSSI [ctl, chain 0-2] */
71 int8_t ts_rssi_ext[3]; /* tx ack RSSI [ext, chain 0-2] */
73 #endif /* AH_SUPPORT_AR5416 */
76 /* bits found in ts_status */
77 #define HAL_TXERR_XRETRY 0x01 /* excessive retries */
78 #define HAL_TXERR_FILT 0x02 /* blocked by tx filtering */
79 #define HAL_TXERR_FIFO 0x04 /* fifo underrun */
80 #define HAL_TXERR_XTXOP 0x08 /* txop exceeded */
81 #define HAL_TXERR_TIMER_EXPIRED 0x10 /* Tx timer expired */
83 /* bits found in ts_flags */
84 #define HAL_TX_BA 0x01 /* Block Ack seen */
85 #define HAL_TX_AGGR 0x02 /* Aggregate */
86 #define HAL_TX_DESC_CFG_ERR 0x10 /* Error in 20/40 desc config */
87 #define HAL_TX_DATA_UNDERRUN 0x20 /* Tx buffer underrun */
88 #define HAL_TX_DELIM_UNDERRUN 0x40 /* Tx delimiter underrun */
91 * Receive descriptor status. This structure is filled
92 * in only after the rx descriptor process method finds a
93 * ``done'' descriptor; at which point it returns something
94 * other than HAL_EINPROGRESS.
96 * If rx_status is zero, then the frame was received ok;
97 * otherwise the error information is indicated and rs_phyerr
98 * contains a phy error code if HAL_RXERR_PHY is set. In general
99 * the frame contents is undefined when an error occurred thought
100 * for some errors (e.g. a decryption error), it may be meaningful.
102 * Note that the receive timestamp is expanded using the TSF to
103 * at least 15 bits (regardless of what the h/w provides directly).
104 * Newer hardware supports a full 32-bits; use HAL_CAP_32TSTAMP to
105 * find out if the hardware is capable.
107 * rx_rssi is in units of dbm above the noise floor. This value
108 * is measured during the preamble and PLCP; i.e. with the initial
109 * 4us of detection. The noise floor is typically a consistent
110 * -96dBm absolute power in a 20MHz channel.
112 struct ath_rx_status {
113 uint16_t rs_datalen; /* rx frame length */
114 uint8_t rs_status; /* rx status, 0 => recv ok */
115 uint8_t rs_phyerr; /* phy error code */
116 int8_t rs_rssi; /* rx frame RSSI (combined for 11n) */
117 uint8_t rs_keyix; /* key cache index */
118 uint8_t rs_rate; /* h/w receive rate index */
119 uint8_t rs_more; /* more descriptors follow */
120 uint32_t rs_tstamp; /* h/w assigned timestamp */
121 uint32_t rs_antenna; /* antenna information */
122 #ifdef AH_SUPPORT_AR5416
124 int8_t rs_rssi_ctl[3]; /* rx frame RSSI [ctl, chain 0-2] */
125 int8_t rs_rssi_ext[3]; /* rx frame RSSI [ext, chain 0-2] */
126 uint8_t rs_isaggr; /* is part of the aggregate */
127 uint8_t rs_moreaggr; /* more frames in aggr to follow */
128 uint16_t rs_flags; /* misc flags */
129 uint8_t rs_num_delims; /* number of delims in aggr */
130 uint8_t rs_spare0; /* padding */
131 uint32_t rs_evm0; /* evm bytes */
134 uint32_t rs_evm3; /* needed for ar9300 and later */
135 uint32_t rs_evm4; /* needed for ar9300 and later */
136 #endif /* AH_SUPPORT_AR5416 */
139 /* bits found in rs_status */
140 #define HAL_RXERR_CRC 0x01 /* CRC error on frame */
141 #define HAL_RXERR_PHY 0x02 /* PHY error, rs_phyerr is valid */
142 #define HAL_RXERR_FIFO 0x04 /* fifo overrun */
143 #define HAL_RXERR_DECRYPT 0x08 /* non-Michael decrypt error */
144 #define HAL_RXERR_MIC 0x10 /* Michael MIC decrypt error */
145 #define HAL_RXERR_INCOMP 0x20 /* Rx Desc processing is incomplete */
146 #define HAL_RXERR_KEYMISS 0x40 /* Key not found in keycache */
148 /* bits found in rs_flags */
149 #define HAL_RX_MORE 0x0001 /* more descriptors follow */
150 #define HAL_RX_MORE_AGGR 0x0002 /* more frames in aggr */
151 #define HAL_RX_GI 0x0004 /* full gi */
152 #define HAL_RX_2040 0x0008 /* 40 Mhz */
153 #define HAL_RX_DELIM_CRC_PRE 0x0010 /* crc error in delimiter pre */
154 #define HAL_RX_DELIM_CRC_POST 0x0020 /* crc error in delim after */
155 #define HAL_RX_DECRYPT_BUSY 0x0040 /* decrypt was too slow */
156 #define HAL_RX_HI_RX_CHAIN 0x0080 /* SM power save: hi Rx chain control */
157 #define HAL_RX_IS_APSD 0x0100 /* Is ASPD trigger frame */
158 #define HAL_RX_STBC 0x0200 /* Is an STBC frame */
161 * This is the format of RSSI[2] on the AR9285/AR9485.
162 * It encodes the LNA configuration information.
164 * For boards with an external diversity antenna switch,
165 * HAL_RX_LNA_EXTCFG encodes which configuration was
166 * used (antenna 1 or antenna 2.) This feeds into the
167 * switch table and ensures that the given antenna was
168 * connected to an LNA.
170 #define HAL_RX_LNA_LNACFG 0x80 /* 1 = main LNA config used, 0 = ALT */
171 #define HAL_RX_LNA_EXTCFG 0x40 /* 0 = external diversity ant1, 1 = ant2 */
172 #define HAL_RX_LNA_CFG_USED 0x30 /* 2 bits; LNA config used on RX */
173 #define HAL_RX_LNA_CFG_USED_S 4
174 #define HAL_RX_LNA_CFG_MAIN 0x0c /* 2 bits; "Main" LNA config */
175 #define HAL_RX_LNA_CFG_ALT 0x02 /* 2 bits; "Alt" LNA config */
178 * This is the format of RSSI_EXT[2] on the AR9285/AR9485.
179 * It encodes the switch table configuration and fast diversity
182 #define HAL_RX_LNA_FASTDIV 0x40 /* 1 = fast diversity measurement done */
183 #define HAL_RX_LNA_SWITCH_0 0x30 /* 2 bits; sw_0[1:0] */
184 #define HAL_RX_LNA_SWITCH_COM 0x0f /* 4 bits, sw_com[3:0] */
187 HAL_PHYERR_UNDERRUN = 0, /* Transmit underrun */
188 HAL_PHYERR_TIMING = 1, /* Timing error */
189 HAL_PHYERR_PARITY = 2, /* Illegal parity */
190 HAL_PHYERR_RATE = 3, /* Illegal rate */
191 HAL_PHYERR_LENGTH = 4, /* Illegal length */
192 HAL_PHYERR_RADAR = 5, /* Radar detect */
193 HAL_PHYERR_SERVICE = 6, /* Illegal service */
194 HAL_PHYERR_TOR = 7, /* Transmit override receive */
195 /* NB: these are specific to the 5212 and later */
196 HAL_PHYERR_OFDM_TIMING = 17, /* */
197 HAL_PHYERR_OFDM_SIGNAL_PARITY = 18, /* */
198 HAL_PHYERR_OFDM_RATE_ILLEGAL = 19, /* */
199 HAL_PHYERR_OFDM_LENGTH_ILLEGAL = 20, /* */
200 HAL_PHYERR_OFDM_POWER_DROP = 21, /* */
201 HAL_PHYERR_OFDM_SERVICE = 22, /* */
202 HAL_PHYERR_OFDM_RESTART = 23, /* */
203 HAL_PHYERR_FALSE_RADAR_EXT = 24, /* */
204 HAL_PHYERR_CCK_TIMING = 25, /* */
205 HAL_PHYERR_CCK_HEADER_CRC = 26, /* */
206 HAL_PHYERR_CCK_RATE_ILLEGAL = 27, /* */
207 HAL_PHYERR_CCK_SERVICE = 30, /* */
208 HAL_PHYERR_CCK_RESTART = 31, /* */
209 HAL_PHYERR_CCK_LENGTH_ILLEGAL = 32, /* */
210 HAL_PHYERR_CCK_POWER_DROP = 33, /* */
211 /* AR5416 and later */
212 HAL_PHYERR_HT_CRC_ERROR = 34, /* */
213 HAL_PHYERR_HT_LENGTH_ILLEGAL = 35, /* */
214 HAL_PHYERR_HT_RATE_ILLEGAL = 36, /* */
216 HAL_PHYERR_SPECTRAL = 38,
219 /* value found in rs_keyix to mark invalid entries */
220 #define HAL_RXKEYIX_INVALID ((uint8_t) -1)
221 /* value used to specify no encryption key for xmit */
222 #define HAL_TXKEYIX_INVALID ((u_int) -1)
224 /* XXX rs_antenna definitions */
227 * Definitions for the software frame/packet descriptors used by
228 * the Atheros HAL. This definition obscures hardware-specific
229 * details from the driver. Drivers are expected to fillin the
230 * portions of a descriptor that are not opaque then use HAL calls
231 * to complete the work. Status for completed frames is returned
232 * in a device-independent format.
234 #ifdef AH_SUPPORT_AR5416
235 #define HAL_DESC_HW_SIZE 20
237 #define HAL_DESC_HW_SIZE 4
238 #endif /* AH_SUPPORT_AR5416 */
242 * The following definitions are passed directly
243 * the hardware and managed by the HAL. Drivers
244 * should not touch those elements marked opaque.
246 uint32_t ds_link; /* phys address of next descriptor */
247 uint32_t ds_data; /* phys address of data buffer */
248 uint32_t ds_ctl0; /* opaque DMA control 0 */
249 uint32_t ds_ctl1; /* opaque DMA control 1 */
250 uint32_t ds_hw[HAL_DESC_HW_SIZE]; /* opaque h/w region */
253 struct ath_desc_txedma {
256 uint32_t ds_hw[21]; /* includes buf/len */
259 struct ath_desc_status {
261 struct ath_tx_status tx;/* xmit status */
262 struct ath_rx_status rx;/* recv status */
266 #define ds_txstat ds_us.tx
267 #define ds_rxstat ds_us.rx
269 /* flags passed to tx descriptor setup methods */
270 /* This is a uint16_t field in ath_buf, just be warned! */
271 #define HAL_TXDESC_CLRDMASK 0x0001 /* clear destination filter mask */
272 #define HAL_TXDESC_NOACK 0x0002 /* don't wait for ACK */
273 #define HAL_TXDESC_RTSENA 0x0004 /* enable RTS */
274 #define HAL_TXDESC_CTSENA 0x0008 /* enable CTS */
275 #define HAL_TXDESC_INTREQ 0x0010 /* enable per-descriptor interrupt */
276 #define HAL_TXDESC_VEOL 0x0020 /* mark virtual EOL */
277 /* NB: this only affects frame, not any RTS/CTS */
278 #define HAL_TXDESC_DURENA 0x0040 /* enable h/w write of duration field */
279 #define HAL_TXDESC_EXT_ONLY 0x0080 /* send on ext channel only (11n) */
280 #define HAL_TXDESC_EXT_AND_CTL 0x0100 /* send on ext + ctl channels (11n) */
281 #define HAL_TXDESC_VMF 0x0200 /* virtual more frag */
282 #define HAL_TXDESC_LOWRXCHAIN 0x0400 /* switch to low RX chain */
283 #define HAL_TXDESC_LDPC 0x1000
285 /* flags passed to rx descriptor setup methods */
286 #define HAL_RXDESC_INTREQ 0x0020 /* enable per-descriptor interrupt */
287 #endif /* _DEV_ATH_DESC_H */