2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2005-2006 Atheros Communications, Inc.
6 * Permission to use, copy, modify, and/or distribute this software for any
7 * purpose with or without fee is hereby granted, provided that the above
8 * copyright notice and this permission notice appear in all copies.
10 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
11 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
13 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
14 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
15 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
16 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 #ifndef __AH_REGDOMAIN_DOMAINS_H__
22 #define __AH_REGDOMAIN_DOMAINS_H__
25 * BMLEN defines the size of the bitmask used to hold frequency
26 * band specifications. Note this must agree with the BM macro
27 * definition that's used to setup initializers. See also further
30 /* BMLEN is now defined in ah_regdomain.h */
32 (((_a) >= 0 && (_a) < 64 ? (((uint64_t) 1)<<(_a)) : (uint64_t) 0))
34 (((_a) > 63 && (_a) < 128 ? (((uint64_t) 1)<<((_a)-64)) : (uint64_t) 0))
35 #define BM1(_fa) { W0(_fa), W1(_fa) }
36 #define BM2(_fa, _fb) { W0(_fa) | W0(_fb), W1(_fa) | W1(_fb) }
37 #define BM3(_fa, _fb, _fc) \
38 { W0(_fa) | W0(_fb) | W0(_fc), W1(_fa) | W1(_fb) | W1(_fc) }
39 #define BM4(_fa, _fb, _fc, _fd) \
40 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd), \
41 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) }
42 #define BM5(_fa, _fb, _fc, _fd, _fe) \
43 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe), \
44 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) }
45 #define BM6(_fa, _fb, _fc, _fd, _fe, _ff) \
46 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff), \
47 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) }
48 #define BM7(_fa, _fb, _fc, _fd, _fe, _ff, _fg) \
49 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \
51 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \
53 #define BM8(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh) \
54 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \
56 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \
58 #define BM9(_fa, _fb, _fc, _fd, _fe, _ff, _fg, _fh, _fi) \
59 { W0(_fa) | W0(_fb) | W0(_fc) | W0(_fd) | W0(_fe) | W0(_ff) | \
60 W0(_fg) | W0(_fh) | W0(_fi) , \
61 W1(_fa) | W1(_fb) | W1(_fc) | W1(_fd) | W1(_fe) | W1(_ff) | \
62 W1(_fg) | W1(_fh) | W1(_fi) }
64 static REG_DOMAIN regDomains[] = {
66 {.regDmnEnum = DEBUG_REG_DMN,
67 .conformanceTestLimit = FCC,
69 .chan11a = BM4(F1_4950_4980,
73 .chan11a_half = BM4(F1_4945_4985,
77 .chan11a_quarter = BM4(F1_4942_4987,
81 .chan11a_turbo = BM8(T1_5130_5210,
89 .chan11a_dyn_turbo = BM4(T1_5200_5240,
93 .chan11b = BM4(F1_2312_2372,
97 .chan11g = BM3(G1_2312_2372, G1_2412_2472, G1_2512_2732),
98 .chan11g_turbo = BM3(T1_2312_2372, T1_2437_2437, T1_2512_2732),
99 .chan11g_half = BM3(G2_2312_2372, G4_2412_2472, G2_2512_2732),
100 .chan11g_quarter = BM3(G3_2312_2372, G5_2412_2472, G3_2512_2732),
104 .conformanceTestLimit = FCC,
105 .chan11a = BM1(F4_5745_5825),
109 .conformanceTestLimit = FCC,
110 .chan11a = BM1(F1_5745_5805),
114 .conformanceTestLimit = FCC,
115 .chan11a = BM2(F1_5280_5320, F2_5745_5805),
119 .conformanceTestLimit = FCC,
120 .chan11a = BM2(F4_5180_5240, F3_5745_5825),
124 .conformanceTestLimit = FCC,
125 .chan11a = BM1(F2_5745_5825),
129 .conformanceTestLimit = ETSI,
131 .pscan = PSCAN_FCC_T | PSCAN_FCC,
132 .chan11a = BM3(F4_5180_5240, F2_5260_5320, F3_5745_5825),
133 .chan11a_turbo = BM3(T2_5210_5210, T1_5250_5290, T1_5760_5800),
137 .conformanceTestLimit = ETSI,
138 .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB,
139 .chan11a = BM2(F6_5260_5320, F4_5745_5825),
143 .conformanceTestLimit = ETSI,
146 .flags = DISALLOW_ADHOC_11A|DISALLOW_ADHOC_11A_TURB,
147 .chan11a = BM3(F1_5180_5320, F1_5500_5620, F3_5745_5805),
150 {.regDmnEnum = ETSI1,
151 .conformanceTestLimit = ETSI,
154 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
155 .chan11a = BM3(W2_5180_5240, F2_5260_5320, F2_5500_5700),
158 {.regDmnEnum = ETSI2,
159 .conformanceTestLimit = ETSI,
162 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
163 .chan11a = BM1(F3_5180_5240),
166 {.regDmnEnum = ETSI3,
167 .conformanceTestLimit = ETSI,
170 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
171 .chan11a = BM2(W2_5180_5240, F2_5260_5320),
174 {.regDmnEnum = ETSI4,
175 .conformanceTestLimit = ETSI,
178 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
179 .chan11a = BM2(F3_5180_5240, F1_5260_5320),
182 {.regDmnEnum = ETSI5,
183 .conformanceTestLimit = ETSI,
186 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
187 .chan11a = BM1(F1_5180_5240),
190 {.regDmnEnum = ETSI6,
191 .conformanceTestLimit = ETSI,
194 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
195 .chan11a = BM3(F5_5180_5240, F1_5260_5280, F3_5500_5700),
199 .conformanceTestLimit = FCC,
200 .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825),
201 .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800),
202 .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805),
206 .conformanceTestLimit = FCC,
207 .chan11a = BM3(F6_5180_5240, F5_5260_5320, F6_5745_5825),
208 .chan11a_dyn_turbo = BM3(T2_5200_5240, T1_5280_5280, T1_5765_5805),
212 .conformanceTestLimit = FCC,
214 .pscan = PSCAN_FCC | PSCAN_FCC_T,
215 .chan11a = BM4(F2_5180_5240,
219 .chan11a_turbo = BM4(T1_5210_5210,
223 .chan11a_dyn_turbo = BM3(T1_5200_5240, T2_5280_5280, T1_5540_5660),
227 .conformanceTestLimit = FCC,
229 .pscan = PSCAN_FCC | PSCAN_FCC_T,
230 .chan11a = BM1(F1_4950_4980),
231 .chan11a_half = BM1(F1_4945_4985),
232 .chan11a_quarter = BM1(F1_4942_4987),
235 /* FCC1 w/ 1/2 and 1/4 width channels */
237 .conformanceTestLimit = FCC,
238 .chan11a = BM3(F2_5180_5240, F4_5260_5320, F5_5745_5825),
239 .chan11a_turbo = BM3(T1_5210_5210, T2_5250_5290, T2_5760_5800),
240 .chan11a_dyn_turbo = BM3(T1_5200_5240, T1_5280_5280, T1_5765_5805),
241 .chan11a_half = BM3(F7_5180_5240, F7_5260_5320, F9_5745_5825),
242 .chan11a_quarter = BM3(F8_5180_5240, F8_5260_5320,F10_5745_5825),
246 .conformanceTestLimit = MKK,
248 .flags = DISALLOW_ADHOC_11A_TURB,
249 .chan11a = BM1(F1_5170_5230),
253 .conformanceTestLimit = MKK,
255 .flags = DISALLOW_ADHOC_11A_TURB,
256 .chan11a = BM3(F1_4920_4980, F1_5040_5080, F1_5170_5230),
257 .chan11a_half = BM4(F1_4915_4925,
265 .conformanceTestLimit = MKK,
267 .flags = DISALLOW_ADHOC_11A_TURB,
268 .chan11a = BM1(F4_5180_5240),
271 /* UNI-1 even + UNI-2 */
273 .conformanceTestLimit = MKK,
276 .flags = DISALLOW_ADHOC_11A_TURB,
277 .chan11a = BM2(F4_5180_5240, F2_5260_5320),
280 /* UNI-1 even + UNI-2 + mid-band */
282 .conformanceTestLimit = MKK,
285 .flags = DISALLOW_ADHOC_11A_TURB,
286 .chan11a = BM3(F4_5180_5240, F2_5260_5320, F4_5500_5700),
289 /* UNI-1 odd + even */
291 .conformanceTestLimit = MKK,
293 .flags = DISALLOW_ADHOC_11A_TURB,
294 .chan11a = BM2(F2_5170_5230, F4_5180_5240),
297 /* UNI-1 odd + UNI-1 even + UNI-2 */
299 .conformanceTestLimit = MKK,
301 .pscan = PSCAN_MKK1 | PSCAN_MKK3,
302 .flags = DISALLOW_ADHOC_11A_TURB,
303 .chan11a = BM3(F1_5170_5230, F4_5180_5240, F2_5260_5320),
306 /* UNI-1 odd + UNI-1 even + UNI-2 + mid-band */
308 .conformanceTestLimit = MKK,
310 .pscan = PSCAN_MKK1 | PSCAN_MKK3,
311 .flags = DISALLOW_ADHOC_11A_TURB,
312 .chan11a = BM4(F1_5170_5230,
318 /* UNI-1 even + 4.9 GHZ */
320 .conformanceTestLimit = MKK,
322 .flags = DISALLOW_ADHOC_11A_TURB,
323 .chan11a = BM7(F1_4915_4925,
332 /* UNI-1 even + UNI-2 + 4.9 GHZ */
333 {.regDmnEnum = MKK10,
334 .conformanceTestLimit = MKK,
337 .flags = DISALLOW_ADHOC_11A_TURB,
338 .chan11a = BM8(F1_4915_4925,
348 /* Defined here to use when 2G channels are authorised for country K2 */
350 .conformanceTestLimit = NO_CTL,
351 .chan11b = BM2(F2_2312_2372,F2_2412_2472),
352 .chan11g = BM2(G2_2312_2372,G2_2412_2472),
355 {.regDmnEnum = ETSIA,
356 .conformanceTestLimit = NO_CTL,
357 .pscan = PSCAN_ETSIA,
358 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
359 .chan11b = BM1(F1_2457_2472),
360 .chan11g = BM1(G1_2457_2472),
361 .chan11g_turbo = BM1(T2_2437_2437)
364 {.regDmnEnum = ETSIB,
365 .conformanceTestLimit = ETSI,
366 .pscan = PSCAN_ETSIB,
367 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
368 .chan11b = BM1(F1_2432_2442),
369 .chan11g = BM1(G1_2432_2442),
370 .chan11g_turbo = BM1(T2_2437_2437)
373 {.regDmnEnum = ETSIC,
374 .conformanceTestLimit = ETSI,
375 .pscan = PSCAN_ETSIC,
376 .flags = DISALLOW_ADHOC_11A | DISALLOW_ADHOC_11A_TURB,
377 .chan11b = BM1(F3_2412_2472),
378 .chan11g = BM1(G3_2412_2472),
379 .chan11g_turbo = BM1(T2_2437_2437)
383 .conformanceTestLimit = FCC,
384 .chan11b = BM1(F1_2412_2462),
385 .chan11g = BM1(G1_2412_2462),
386 .chan11g_turbo = BM1(T2_2437_2437),
389 /* FCCA w/ 1/2 and 1/4 width channels */
391 .conformanceTestLimit = FCC,
392 .chan11b = BM1(F1_2412_2462),
393 .chan11g = BM1(G1_2412_2462),
394 .chan11g_turbo = BM1(T2_2437_2437),
395 .chan11g_half = BM1(G3_2412_2462),
396 .chan11g_quarter = BM1(G4_2412_2462),
400 .conformanceTestLimit = MKK,
401 .pscan = PSCAN_MKKA | PSCAN_MKKA_G
402 | PSCAN_MKKA1 | PSCAN_MKKA1_G
403 | PSCAN_MKKA2 | PSCAN_MKKA2_G,
404 .flags = DISALLOW_ADHOC_11A_TURB,
405 .chan11b = BM3(F2_2412_2462, F1_2467_2472, F2_2484_2484),
406 .chan11g = BM2(G2_2412_2462, G1_2467_2472),
407 .chan11g_turbo = BM1(T2_2437_2437)
411 .conformanceTestLimit = MKK,
412 .chan11b = BM1(F2_2412_2472),
413 .chan11g = BM1(G2_2412_2472),
414 .chan11g_turbo = BM1(T2_2437_2437)
417 {.regDmnEnum = WORLD,
418 .conformanceTestLimit = ETSI,
419 .chan11b = BM1(F2_2412_2472),
420 .chan11g = BM1(G2_2412_2472),
421 .chan11g_turbo = BM1(T2_2437_2437)
424 {.regDmnEnum = WOR0_WORLD,
425 .conformanceTestLimit = NO_CTL,
426 .dfsMask = DFS_FCC3 | DFS_ETSI,
428 .flags = ADHOC_PER_11D,
429 .chan11a = BM5(W1_5260_5320,
434 .chan11a_turbo = BM3(WT1_5210_5250,
437 .chan11b = BM8(W1_2412_2412,
445 .chan11g = BM7(WG1_2412_2412,
452 .chan11g_turbo = BM1(T3_2437_2437)
455 {.regDmnEnum = WOR01_WORLD,
456 .conformanceTestLimit = NO_CTL,
457 .dfsMask = DFS_FCC3 | DFS_ETSI,
459 .flags = ADHOC_PER_11D,
460 .chan11a = BM5(W1_5260_5320,
465 .chan11a_turbo = BM3(WT1_5210_5250,
468 .chan11b = BM5(W1_2412_2412,
473 .chan11g = BM5(WG1_2412_2412,
478 .chan11g_turbo = BM1(T3_2437_2437)},
480 {.regDmnEnum = WOR02_WORLD,
481 .conformanceTestLimit = NO_CTL,
482 .dfsMask = DFS_FCC3 | DFS_ETSI,
484 .flags = ADHOC_PER_11D,
485 .chan11a = BM5(W1_5260_5320,
490 .chan11a_turbo = BM3(WT1_5210_5250,
493 .chan11b = BM7(W1_2412_2412,
500 .chan11g = BM7(WG1_2412_2412,
507 .chan11g_turbo = BM1(T3_2437_2437)},
509 {.regDmnEnum = EU1_WORLD,
510 .conformanceTestLimit = NO_CTL,
511 .dfsMask = DFS_FCC3 | DFS_ETSI,
513 .flags = ADHOC_PER_11D,
514 .chan11a = BM5(W1_5260_5320,
519 .chan11a_turbo = BM3(WT1_5210_5250,
522 .chan11b = BM7(W1_2412_2412,
529 .chan11g = BM7(WG1_2412_2412,
536 .chan11g_turbo = BM1(T3_2437_2437)},
538 {.regDmnEnum = WOR1_WORLD,
539 .conformanceTestLimit = NO_CTL,
540 .dfsMask = DFS_FCC3 | DFS_ETSI,
542 .flags = DISALLOW_ADHOC_11A,
543 .chan11a = BM5(W1_5260_5320,
548 .chan11b = BM8(W1_2412_2412,
556 .chan11g = BM7(WG1_2412_2412,
563 .chan11g_turbo = BM1(T3_2437_2437)
566 {.regDmnEnum = WOR2_WORLD,
567 .conformanceTestLimit = NO_CTL,
568 .dfsMask = DFS_FCC3 | DFS_ETSI,
570 .flags = DISALLOW_ADHOC_11A,
571 .chan11a = BM5(W1_5260_5320,
576 .chan11a_turbo = BM3(WT1_5210_5250,
579 .chan11b = BM8(W1_2412_2412,
587 .chan11g = BM7(WG1_2412_2412,
594 .chan11g_turbo = BM1(T3_2437_2437)},
596 {.regDmnEnum = WOR3_WORLD,
597 .conformanceTestLimit = NO_CTL,
598 .dfsMask = DFS_FCC3 | DFS_ETSI,
600 .flags = ADHOC_PER_11D,
601 .chan11a = BM4(W1_5260_5320,
605 .chan11a_turbo = BM3(WT1_5210_5250,
608 .chan11b = BM7(W1_2412_2412,
615 .chan11g = BM7(WG1_2412_2412,
622 .chan11g_turbo = BM1(T3_2437_2437)},
624 {.regDmnEnum = WOR4_WORLD,
625 .conformanceTestLimit = NO_CTL,
626 .dfsMask = DFS_FCC3 | DFS_ETSI,
628 .flags = DISALLOW_ADHOC_11A,
629 .chan11a = BM4(W2_5260_5320,
633 .chan11a_turbo = BM3(WT1_5210_5250,
636 .chan11b = BM5(W1_2412_2412,
641 .chan11g = BM5(WG1_2412_2412,
646 .chan11g_turbo = BM1(T3_2437_2437)},
648 {.regDmnEnum = WOR5_ETSIC,
649 .conformanceTestLimit = NO_CTL,
650 .dfsMask = DFS_FCC3 | DFS_ETSI,
652 .flags = DISALLOW_ADHOC_11A,
653 .chan11a = BM3(W1_5260_5320, W2_5180_5240, F6_5745_5825),
654 .chan11b = BM7(W1_2412_2412,
661 .chan11g = BM7(WG1_2412_2412,
668 .chan11g_turbo = BM1(T3_2437_2437)},
670 {.regDmnEnum = WOR9_WORLD,
671 .conformanceTestLimit = NO_CTL,
672 .dfsMask = DFS_FCC3 | DFS_ETSI,
674 .flags = DISALLOW_ADHOC_11A,
675 .chan11a = BM4(W1_5260_5320,
679 .chan11a_turbo = BM3(WT1_5210_5250,
682 .chan11b = BM5(W1_2412_2412,
687 .chan11g = BM5(WG1_2412_2412,
692 .chan11g_turbo = BM1(T3_2437_2437)},
694 {.regDmnEnum = WORA_WORLD,
695 .conformanceTestLimit = NO_CTL,
696 .dfsMask = DFS_FCC3 | DFS_ETSI,
698 .flags = DISALLOW_ADHOC_11A,
699 .chan11a = BM4(W1_5260_5320,
703 .chan11b = BM7(W1_2412_2412,
710 .chan11g = BM7(WG1_2412_2412,
717 .chan11g_turbo = BM1(T3_2437_2437)},
719 {.regDmnEnum = WORB_WORLD,
720 .conformanceTestLimit = NO_CTL,
721 .dfsMask = DFS_FCC3 | DFS_ETSI,
723 .flags = DISALLOW_ADHOC_11A,
724 .chan11a = BM4(W1_5260_5320,
728 .chan11b = BM7(W1_2412_2412,
735 .chan11g = BM7(WG1_2412_2412,
742 .chan11g_turbo = BM1(T3_2437_2437)},
744 {.regDmnEnum = WORC_WORLD,
745 .conformanceTestLimit = NO_CTL,
746 .dfsMask = DFS_FCC3 | DFS_ETSI,
748 .flags = ADHOC_PER_11D,
749 .chan11a = BM4(W1_5260_5320,
753 .chan11b = BM7(W1_2412_2412,
760 .chan11g = BM7(WG1_2412_2412,
767 .chan11g_turbo = BM1(T3_2437_2437)},
769 {.regDmnEnum = NULL1,
770 .conformanceTestLimit = NO_CTL,