2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2004 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include "ah_internal.h"
24 #include "ar5210/ar5210.h"
25 #include "ar5210/ar5210reg.h"
26 #include "ar5210/ar5210phy.h"
28 #include "ah_eeprom_v1.h"
35 static const REGISTER_VAL ar5k0007_init[] = {
36 #include "ar5210/ar5k_0007.ini"
39 /* Default Power Settings for channels outside of EEPROM range */
40 static const uint8_t ar5k0007_pwrSettings[17] = {
41 /* gain delta pc dac */
42 /* 54 48 36 24 18 12 9 54 48 36 24 18 12 9 6 ob db */
43 9, 9, 0, 0, 0, 0, 0, 2, 2, 6, 6, 6, 6, 6, 6, 2, 2
47 * The delay, in usecs, between writing AR_RC with a reset
48 * request and waiting for the chip to settle. If this is
49 * too short then the chip does not come out of sleep state.
50 * Note this value was empirically derived and may be dependent
51 * on the host machine (don't know--the problem was identified
52 * on an IBM 570e laptop; 10us delays worked on other systems).
54 #define AR_RC_SETTLE_TIME 20000
56 static HAL_BOOL ar5210SetResetReg(struct ath_hal *,
57 uint32_t resetMask, u_int delay);
58 static HAL_BOOL ar5210SetChannel(struct ath_hal *, struct ieee80211_channel *);
59 static void ar5210SetOperatingMode(struct ath_hal *, int opmode);
62 * Places the device in and out of reset and then places sane
63 * values in the registers based on EEPROM config, initialization
64 * vectors (as determined by the mode), and station configuration
66 * bChannelChange is used to preserve DMA/PCU registers across
67 * a HW Reset during channel change.
70 ar5210Reset(struct ath_hal *ah, HAL_OPMODE opmode,
71 struct ieee80211_channel *chan, HAL_BOOL bChannelChange,
74 #define N(a) (sizeof (a) /sizeof (a[0]))
75 #define FAIL(_code) do { ecode = _code; goto bad; } while (0)
76 struct ath_hal_5210 *ahp = AH5210(ah);
77 const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
78 HAL_CHANNEL_INTERNAL *ichan;
83 HALDEBUG(ah, HAL_DEBUG_RESET,
84 "%s: opmode %u channel %u/0x%x %s channel\n", __func__,
85 opmode, chan->ic_freq, chan->ic_flags,
86 bChannelChange ? "change" : "same");
88 if (!IEEE80211_IS_CHAN_5GHZ(chan)) {
90 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: channel not 5GHz\n", __func__);
94 * Map public channel to private.
96 ichan = ath_hal_checkchannel(ah, chan);
97 if (ichan == AH_NULL) {
98 HALDEBUG(ah, HAL_DEBUG_ANY,
99 "%s: invalid channel %u/0x%x; no mapping\n",
100 __func__, chan->ic_freq, chan->ic_flags);
110 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid operating mode %u\n",
116 ledstate = OS_REG_READ(ah, AR_PCICFG) &
117 (AR_PCICFG_LED_PEND | AR_PCICFG_LED_ACT);
119 if (!ar5210ChipReset(ah, chan)) {
120 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: chip reset failed\n",
125 OS_REG_WRITE(ah, AR_STA_ID0, LE_READ_4(ahp->ah_macaddr));
126 OS_REG_WRITE(ah, AR_STA_ID1, LE_READ_2(ahp->ah_macaddr + 4));
127 ar5210SetOperatingMode(ah, opmode);
131 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
132 OS_REG_WRITE(ah, AR_PCICFG,
133 AR_PCICFG_LED_ACT | AR_PCICFG_LED_BCTL);
136 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG | AR_BCR_BCMD);
137 OS_REG_WRITE(ah, AR_PCICFG,
138 AR_PCICFG_CLKRUNEN | AR_PCICFG_LED_PEND | AR_PCICFG_LED_BCTL);
141 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
142 OS_REG_WRITE(ah, AR_PCICFG,
143 AR_PCICFG_CLKRUNEN | AR_PCICFG_LED_PEND | AR_PCICFG_LED_BCTL);
146 OS_REG_WRITE(ah, AR_BCR, INIT_BCON_CNTRL_REG);
147 OS_REG_WRITE(ah, AR_PCICFG,
148 AR_PCICFG_LED_ACT | AR_PCICFG_LED_BCTL);
152 /* Restore previous led state */
153 OS_REG_WRITE(ah, AR_PCICFG, OS_REG_READ(ah, AR_PCICFG) | ledstate);
155 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
156 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid + 4));
158 OS_REG_WRITE(ah, AR_TXDP0, 0);
159 OS_REG_WRITE(ah, AR_TXDP1, 0);
160 OS_REG_WRITE(ah, AR_RXDP, 0);
163 * Initialize interrupt state.
165 (void) OS_REG_READ(ah, AR_ISR); /* cleared on read */
166 OS_REG_WRITE(ah, AR_IMR, 0);
167 OS_REG_WRITE(ah, AR_IER, AR_IER_DISABLE);
170 (void) OS_REG_READ(ah, AR_BSR); /* cleared on read */
171 OS_REG_WRITE(ah, AR_TXCFG, AR_DMASIZE_128B);
172 OS_REG_WRITE(ah, AR_RXCFG, AR_DMASIZE_128B);
174 OS_REG_WRITE(ah, AR_TOPS, 8); /* timeout prescale */
175 OS_REG_WRITE(ah, AR_RXNOFRM, 8); /* RX no frame timeout */
176 OS_REG_WRITE(ah, AR_RPGTO, 0); /* RX frame gap timeout */
177 OS_REG_WRITE(ah, AR_TXNOFRM, 0); /* TX no frame timeout */
179 OS_REG_WRITE(ah, AR_SFR, 0);
180 OS_REG_WRITE(ah, AR_MIBC, 0); /* unfreeze ctrs + clr state */
181 OS_REG_WRITE(ah, AR_RSSI_THR, ahp->ah_rssiThr);
182 OS_REG_WRITE(ah, AR_CFP_DUR, 0);
184 ar5210SetRxFilter(ah, 0); /* nothing for now */
185 OS_REG_WRITE(ah, AR_MCAST_FIL0, 0); /* multicast filter */
186 OS_REG_WRITE(ah, AR_MCAST_FIL1, 0); /* XXX was 2 */
188 OS_REG_WRITE(ah, AR_TX_MASK0, 0);
189 OS_REG_WRITE(ah, AR_TX_MASK1, 0);
190 OS_REG_WRITE(ah, AR_CLR_TMASK, 1);
191 OS_REG_WRITE(ah, AR_TRIG_LEV, 1); /* minimum */
193 OS_REG_WRITE(ah, AR_DIAG_SW, 0);
195 OS_REG_WRITE(ah, AR_CFP_PERIOD, 0);
196 OS_REG_WRITE(ah, AR_TIMER0, 0); /* next beacon time */
197 OS_REG_WRITE(ah, AR_TSF_L32, 0); /* local clock */
198 OS_REG_WRITE(ah, AR_TIMER1, ~0); /* next DMA beacon alert */
199 OS_REG_WRITE(ah, AR_TIMER2, ~0); /* next SW beacon alert */
200 OS_REG_WRITE(ah, AR_TIMER3, 1); /* next ATIM window */
202 /* Write the INI values for PHYreg initialization */
203 for (i = 0; i < N(ar5k0007_init); i++) {
204 uint32_t reg = ar5k0007_init[i].Offset;
205 /* On channel change, don't reset the PCU registers */
206 if (!(bChannelChange && (0x8000 <= reg && reg < 0x9000)))
207 OS_REG_WRITE(ah, reg, ar5k0007_init[i].Value);
210 /* Setup the transmit power values for cards since 0x0[0-2]05 */
211 if (!ar5210SetTransmitPower(ah, chan)) {
212 HALDEBUG(ah, HAL_DEBUG_ANY,
213 "%s: error init'ing transmit power\n", __func__);
217 OS_REG_WRITE(ah, AR_PHY(10),
218 (OS_REG_READ(ah, AR_PHY(10)) & 0xFFFF00FF) |
219 (ee->ee_xlnaOn << 8));
220 OS_REG_WRITE(ah, AR_PHY(13),
221 (ee->ee_xpaOff << 24) | (ee->ee_xpaOff << 16) |
222 (ee->ee_xpaOn << 8) | ee->ee_xpaOn);
223 OS_REG_WRITE(ah, AR_PHY(17),
224 (OS_REG_READ(ah, AR_PHY(17)) & 0xFFFFC07F) |
225 ((ee->ee_antenna >> 1) & 0x3F80));
226 OS_REG_WRITE(ah, AR_PHY(18),
227 (OS_REG_READ(ah, AR_PHY(18)) & 0xFFFC0FFF) |
228 ((ee->ee_antenna << 10) & 0x3F000));
229 OS_REG_WRITE(ah, AR_PHY(25),
230 (OS_REG_READ(ah, AR_PHY(25)) & 0xFFF80FFF) |
231 ((ee->ee_thresh62 << 12) & 0x7F000));
232 OS_REG_WRITE(ah, AR_PHY(68),
233 (OS_REG_READ(ah, AR_PHY(68)) & 0xFFFFFFFC) |
234 (ee->ee_antenna & 0x3));
236 if (!ar5210SetChannel(ah, chan)) {
237 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unable to set channel\n",
241 if (bChannelChange && !IEEE80211_IS_CHAN_DFS(chan))
242 chan->ic_state &= ~IEEE80211_CHANSTATE_CWINT;
244 /* Activate the PHY */
245 OS_REG_WRITE(ah, AR_PHY_ACTIVE, AR_PHY_ENABLE);
247 OS_DELAY(1000); /* Wait a bit (1 msec) */
249 /* calibrate the HW and poll the bit going to 0 for completion */
250 OS_REG_WRITE(ah, AR_PHY_AGCCTL,
251 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL);
252 (void) ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0);
254 /* Perform noise floor calibration and set status */
255 if (!ar5210CalNoiseFloor(ah, ichan)) {
256 chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
257 HALDEBUG(ah, HAL_DEBUG_ANY,
258 "%s: noise floor calibration failed\n", __func__);
262 for (q = 0; q < HAL_NUM_TX_QUEUES; q++)
263 ar5210ResetTxQueue(ah, q);
265 if (AH_PRIVATE(ah)->ah_rfkillEnabled)
266 ar5210EnableRfKill(ah);
269 * Writing to AR_BEACON will start timers. Hence it should be
270 * the last register to be written. Do not reset tsf, do not
271 * enable beacons at this point, but preserve other values
272 * like beaconInterval.
274 OS_REG_WRITE(ah, AR_BEACON,
275 (OS_REG_READ(ah, AR_BEACON) &
276 ~(AR_BEACON_EN | AR_BEACON_RESET_TSF)));
278 /* Restore user-specified slot time and timeouts */
279 if (ahp->ah_sifstime != (u_int) -1)
280 ar5210SetSifsTime(ah, ahp->ah_sifstime);
281 if (ahp->ah_slottime != (u_int) -1)
282 ar5210SetSlotTime(ah, ahp->ah_slottime);
283 if (ahp->ah_acktimeout != (u_int) -1)
284 ar5210SetAckTimeout(ah, ahp->ah_acktimeout);
285 if (ahp->ah_ctstimeout != (u_int) -1)
286 ar5210SetCTSTimeout(ah, ahp->ah_ctstimeout);
287 if (AH_PRIVATE(ah)->ah_diagreg != 0)
288 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
290 AH_PRIVATE(ah)->ah_opmode = opmode; /* record operating mode */
292 HALDEBUG(ah, HAL_DEBUG_RESET, "%s: done\n", __func__);
296 if (status != AH_NULL)
304 ar5210SetOperatingMode(struct ath_hal *ah, int opmode)
306 struct ath_hal_5210 *ahp = AH5210(ah);
309 val = OS_REG_READ(ah, AR_STA_ID1) & 0xffff;
312 OS_REG_WRITE(ah, AR_STA_ID1, val
314 | AR_STA_ID1_NO_PSPOLL
315 | AR_STA_ID1_DESC_ANTENNA
316 | ahp->ah_staId1Defaults);
319 OS_REG_WRITE(ah, AR_STA_ID1, val
321 | AR_STA_ID1_NO_PSPOLL
322 | AR_STA_ID1_DESC_ANTENNA
323 | ahp->ah_staId1Defaults);
326 OS_REG_WRITE(ah, AR_STA_ID1, val
327 | AR_STA_ID1_NO_PSPOLL
329 | ahp->ah_staId1Defaults);
332 OS_REG_WRITE(ah, AR_STA_ID1, val
333 | AR_STA_ID1_NO_PSPOLL
334 | ahp->ah_staId1Defaults);
340 ar5210SetPCUConfig(struct ath_hal *ah)
342 ar5210SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
346 * Places the PHY and Radio chips into reset. A full reset
347 * must be called to leave this state. The PCI/MAC/PCU are
348 * not placed into reset as we must receive interrupt to
349 * re-enable the hardware.
352 ar5210PhyDisable(struct ath_hal *ah)
354 return ar5210SetResetReg(ah, AR_RC_RPHY, 10);
358 * Places all of hardware into reset
361 ar5210Disable(struct ath_hal *ah)
363 #define AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC)
364 if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
368 * Reset the HW - PCI must be reset after the rest of the
369 * device has been reset
371 if (!ar5210SetResetReg(ah, AR_RC_HW, AR_RC_SETTLE_TIME))
374 (void) ar5210SetResetReg(ah, AR_RC_HW | AR_RC_RPCI, AR_RC_SETTLE_TIME);
375 OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */
382 * Places the hardware into reset and then pulls it out of reset
385 ar5210ChipReset(struct ath_hal *ah, struct ieee80211_channel *chan)
387 #define AR_RC_HW (AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC)
389 HALDEBUG(ah, HAL_DEBUG_RESET, "%s turbo %s\n", __func__,
390 chan && IEEE80211_IS_CHAN_TURBO(chan) ?
391 "enabled" : "disabled");
393 if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
396 /* Place chip in turbo before reset to cleanly reset clocks */
397 OS_REG_WRITE(ah, AR_PHY_FRCTL,
398 chan && IEEE80211_IS_CHAN_TURBO(chan) ? AR_PHY_TURBO_MODE : 0);
402 * PCI must be reset after the rest of the device has been reset.
404 if (!ar5210SetResetReg(ah, AR_RC_HW, AR_RC_SETTLE_TIME))
407 if (!ar5210SetResetReg(ah, AR_RC_HW | AR_RC_RPCI, AR_RC_SETTLE_TIME))
409 OS_DELAY(2100); /* 8245 @ 96Mhz hangs with 2000us. */
412 * Bring out of sleep mode (AGAIN)
414 * WARNING WARNING WARNING
416 * There is a problem with the chip where it doesn't always indicate
417 * that it's awake, so initializePowerUp() will fail.
419 if (!ar5210SetPowerMode(ah, HAL_PM_AWAKE, AH_TRUE))
422 /* Clear warm reset reg */
423 return ar5210SetResetReg(ah, 0, 10);
428 FIRPWR_M = 0x03fc0000,
430 KCOARSEHIGH_M = 0x003f8000,
432 KCOARSELOW_M = 0x00007f80,
434 ADCSAT_ICOUNT_M = 0x0001f800,
435 ADCSAT_ICOUNT_S = 11,
436 ADCSAT_THRESH_M = 0x000007e0,
441 * Recalibrate the lower PHY chips to account for temperature/environment
445 ar5210PerCalibrationN(struct ath_hal *ah,
446 struct ieee80211_channel *chan, u_int chainMask,
447 HAL_BOOL longCal, HAL_BOOL *isCalDone)
450 uint32_t reg9858, reg985c, reg9868;
451 HAL_CHANNEL_INTERNAL *ichan;
453 ichan = ath_hal_checkchannel(ah, chan);
454 if (ichan == AH_NULL)
456 /* Disable tx and rx */
457 OS_REG_WRITE(ah, AR_DIAG_SW,
458 OS_REG_READ(ah, AR_DIAG_SW) | (AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX));
460 /* Disable Beacon Enable */
461 regBeacon = OS_REG_READ(ah, AR_BEACON);
462 OS_REG_WRITE(ah, AR_BEACON, regBeacon & ~AR_BEACON_EN);
464 /* Delay 4ms to ensure that all tx and rx activity has ceased */
467 /* Disable AGC to radio traffic */
468 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000);
469 /* Wait for the AGC traffic to cease. */
472 /* Change Channel to relock synth */
473 if (!ar5210SetChannel(ah, chan))
476 /* wait for the synthesizer lock to stabilize */
479 /* Re-enable AGC to radio traffic */
480 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000));
483 * Configure the AGC so that it is highly unlikely (if not
484 * impossible) for it to send any gain changes to the analog
485 * chip. We store off the current values so that they can
486 * be rewritten below. Setting the following values:
493 reg9858 = OS_REG_READ(ah, 0x9858);
494 reg985c = OS_REG_READ(ah, 0x985c);
495 reg9868 = OS_REG_READ(ah, 0x9868);
497 OS_REG_WRITE(ah, 0x9858, (reg9858 & ~FIRPWR_M) |
498 ((-1 << FIRPWR_S) & FIRPWR_M));
499 OS_REG_WRITE(ah, 0x985c,
500 (reg985c & ~(KCOARSEHIGH_M | KCOARSELOW_M)) |
501 ((-1 << KCOARSEHIGH_S) & KCOARSEHIGH_M) |
502 ((-127 << KCOARSELOW_S) & KCOARSELOW_M));
503 OS_REG_WRITE(ah, 0x9868,
504 (reg9868 & ~(ADCSAT_ICOUNT_M | ADCSAT_THRESH_M)) |
505 ((2 << ADCSAT_ICOUNT_S) & ADCSAT_ICOUNT_M) |
506 ((12 << ADCSAT_THRESH_S) & ADCSAT_THRESH_M));
508 /* Wait for AGC changes to be enacted */
512 * We disable RF mix/gain stages for the PGA to avoid a
513 * race condition that will occur with receiving a frame
514 * and performing the AGC calibration. This will be
515 * re-enabled at the end of offset cal. We turn off AGC
516 * writes during this write as it will go over the analog bus.
518 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) | 0x08000000);
519 OS_DELAY(10); /* wait for the AGC traffic to cease */
520 OS_REG_WRITE(ah, 0x98D4, 0x21);
521 OS_REG_WRITE(ah, 0x9808, OS_REG_READ(ah, 0x9808) & (~0x08000000));
523 /* wait to make sure that additional AGC traffic has quiesced */
526 /* AGC calibration (this was added to make the NF threshold check work) */
527 OS_REG_WRITE(ah, AR_PHY_AGCCTL,
528 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_CAL);
529 if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_CAL, 0)) {
530 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: AGC calibration timeout\n",
534 /* Rewrite our AGC values we stored off earlier (return AGC to normal operation) */
535 OS_REG_WRITE(ah, 0x9858, reg9858);
536 OS_REG_WRITE(ah, 0x985c, reg985c);
537 OS_REG_WRITE(ah, 0x9868, reg9868);
539 /* Perform noise floor and set status */
540 if (!ar5210CalNoiseFloor(ah, ichan)) {
542 * Delay 5ms before retrying the noise floor -
543 * just to make sure. We're in an error
546 HALDEBUG(ah, HAL_DEBUG_NFCAL | HAL_DEBUG_PERCAL,
547 "%s: Performing 2nd Noise Cal\n", __func__);
549 if (!ar5210CalNoiseFloor(ah, ichan))
550 chan->ic_state |= IEEE80211_CHANSTATE_CWINT;
553 /* Clear tx and rx disable bit */
554 OS_REG_WRITE(ah, AR_DIAG_SW,
555 OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_TX | AR_DIAG_SW_DIS_RX));
557 /* Re-enable Beacons */
558 OS_REG_WRITE(ah, AR_BEACON, regBeacon);
560 *isCalDone = AH_TRUE;
566 ar5210PerCalibration(struct ath_hal *ah, struct ieee80211_channel *chan,
569 return ar5210PerCalibrationN(ah, chan, 0x1, AH_TRUE, isIQdone);
573 ar5210ResetCalValid(struct ath_hal *ah, const struct ieee80211_channel *chan)
579 * Writes the given reset bit mask into the reset register
582 ar5210SetResetReg(struct ath_hal *ah, uint32_t resetMask, u_int delay)
584 uint32_t mask = resetMask ? resetMask : ~0;
587 OS_REG_WRITE(ah, AR_RC, resetMask);
588 /* need to wait at least 128 clocks when reseting PCI before read */
591 resetMask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC;
592 mask &= AR_RC_RPCU | AR_RC_RDMA | AR_RC_RPHY | AR_RC_RMAC;
593 rt = ath_hal_wait(ah, AR_RC, mask, resetMask);
594 if ((resetMask & AR_RC_RMAC) == 0) {
597 * Set CFG, little-endian for register
598 * and descriptor accesses.
600 mask = INIT_CONFIG_STATUS |
601 AR_CFG_SWTD | AR_CFG_SWRD | AR_CFG_SWRG;
602 OS_REG_WRITE(ah, AR_CFG, LE_READ_4(&mask));
604 OS_REG_WRITE(ah, AR_CFG, INIT_CONFIG_STATUS);
611 * Returns: the pcdac value
614 getPcdac(struct ath_hal *ah, const struct tpcMap *pRD, uint8_t dBm)
617 int useNextEntry = AH_FALSE;
620 for (i = AR_TP_SCALING_ENTRIES - 1; i >= 0; i--) {
621 /* Check for exact entry */
622 if (dBm == AR_I2DBM(i)) {
623 if (pRD->pcdac[i] != 63)
624 return pRD->pcdac[i];
625 useNextEntry = AH_TRUE;
626 } else if (dBm + 1 == AR_I2DBM(i) && i > 0) {
627 /* Interpolate for between entry with a logish scale */
628 if (pRD->pcdac[i] != 63 && pRD->pcdac[i-1] != 63) {
629 interp = (350 * (pRD->pcdac[i] - pRD->pcdac[i-1])) + 999;
630 interp = (interp / 1000) + pRD->pcdac[i-1];
633 useNextEntry = AH_TRUE;
634 } else if (useNextEntry == AH_TRUE) {
635 /* Grab the next lowest */
636 if (pRD->pcdac[i] != 63)
637 return pRD->pcdac[i];
641 /* Return the lowest Entry if we haven't returned */
642 for (i = 0; i < AR_TP_SCALING_ENTRIES; i++)
643 if (pRD->pcdac[i] != 63)
644 return pRD->pcdac[i];
646 /* No value to return from table */
648 ath_hal_printf(ah, "%s: empty transmit power table?\n", __func__);
654 * Find or interpolates the gainF value from the table ptr.
657 getGainF(struct ath_hal *ah, const struct tpcMap *pRD,
658 uint8_t pcdac, uint8_t *dBm)
665 for (i = 0; i < AR_TP_SCALING_ENTRIES; i++) {
666 if(pRD->pcdac[i] == 63)
668 if (pcdac == pRD->pcdac[i]) {
670 return pRD->gainF[i]; /* Exact Match */
672 if (pcdac > pRD->pcdac[i])
674 if (pcdac < pRD->pcdac[i]) {
678 /* PCDAC is lower than lowest setting */
679 return pRD->gainF[i];
684 if (i >= AR_TP_SCALING_ENTRIES && low == -1) {
685 /* No settings were found */
688 "%s: no valid entries in the pcdac table: %d\n",
693 if (i >= AR_TP_SCALING_ENTRIES) {
694 /* PCDAC setting was above the max setting in the table */
695 *dBm = AR_I2DBM(low);
696 return pRD->gainF[low];
698 /* Only exact if table has no missing entries */
699 *dBm = (low + high) + 3;
702 * Perform interpolation between low and high values to find gainF
703 * linearly scale the pcdac between low and high
705 interp = ((pcdac - pRD->pcdac[low]) * 1000) /
706 (pRD->pcdac[high] - pRD->pcdac[low]);
708 * Multiply the scale ratio by the gainF difference
709 * (plus a rnd up factor)
711 interp = ((interp * (pRD->gainF[high] - pRD->gainF[low])) + 999) / 1000;
713 /* Add ratioed gain_f to low gain_f value */
714 return interp + pRD->gainF[low];
718 ar5210SetTxPowerLimit(struct ath_hal *ah, uint32_t limit)
720 AH_PRIVATE(ah)->ah_powerLimit = AH_MIN(limit, AR5210_MAX_RATE_POWER);
721 /* XXX flush to h/w */
726 * Get TXPower values and set them in the radio
729 setupPowerSettings(struct ath_hal *ah, const struct ieee80211_channel *chan,
732 uint16_t freq = ath_hal_gethwchannel(ah, chan);
733 const HAL_EEPROM_v1 *ee = AH_PRIVATE(ah)->ah_eeprom;
734 uint8_t gainFRD, gainF36, gainF48, gainF54;
735 uint8_t dBmRD, dBm36, dBm48, dBm54, dontcare;
737 const struct tpcMap *pRD;
739 /* Set OB/DB Values regardless of channel */
740 cp[15] = (ee->ee_biasCurrents >> 4) & 0x7;
741 cp[16] = ee->ee_biasCurrents & 0x7;
743 if (freq < 5170 || freq > 5320) {
744 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: invalid channel %u\n",
749 HALASSERT(ee->ee_version >= AR_EEPROM_VER1 &&
750 ee->ee_version < AR_EEPROM_VER3);
752 /* Match regulatory domain */
753 for (rd = 0; rd < AR_REG_DOMAINS_MAX; rd++)
754 if (AH_PRIVATE(ah)->ah_currentRD == ee->ee_regDomain[rd])
756 if (rd == AR_REG_DOMAINS_MAX) {
759 "%s: no calibrated regulatory domain matches the "
760 "current regularly domain (0x%0x)\n", __func__,
761 AH_PRIVATE(ah)->ah_currentRD);
765 group = ((freq - 5170) / 10);
768 /* Pull 5.29 into the 5.27 group */
772 /* Integer divide will set group from 0 to 4 */
774 pRD = &ee->ee_tpc[group];
776 /* Set PC DAC Values */
777 cp[14] = pRD->regdmn[rd];
778 cp[9] = AH_MIN(pRD->regdmn[rd], pRD->rate36);
779 cp[8] = AH_MIN(pRD->regdmn[rd], pRD->rate48);
780 cp[7] = AH_MIN(pRD->regdmn[rd], pRD->rate54);
782 /* Find Corresponding gainF values for RD, 36, 48, 54 */
783 gainFRD = getGainF(ah, pRD, pRD->regdmn[rd], &dBmRD);
784 gainF36 = getGainF(ah, pRD, cp[9], &dBm36);
785 gainF48 = getGainF(ah, pRD, cp[8], &dBm48);
786 gainF54 = getGainF(ah, pRD, cp[7], &dBm54);
788 /* Power Scale if requested */
789 if (AH_PRIVATE(ah)->ah_tpScale != HAL_TP_SCALE_MAX) {
790 static const uint16_t tpcScaleReductionTable[5] =
791 { 0, 3, 6, 9, AR5210_MAX_RATE_POWER };
794 tpScale = tpcScaleReductionTable[AH_PRIVATE(ah)->ah_tpScale];
795 if (dBmRD < tpScale+3)
799 cp[14] = getPcdac(ah, pRD, dBmRD);
800 gainFRD = getGainF(ah, pRD, cp[14], &dontcare);
801 dBm36 = AH_MIN(dBm36, dBmRD);
802 cp[9] = getPcdac(ah, pRD, dBm36);
803 gainF36 = getGainF(ah, pRD, cp[9], &dontcare);
804 dBm48 = AH_MIN(dBm48, dBmRD);
805 cp[8] = getPcdac(ah, pRD, dBm48);
806 gainF48 = getGainF(ah, pRD, cp[8], &dontcare);
807 dBm54 = AH_MIN(dBm54, dBmRD);
808 cp[7] = getPcdac(ah, pRD, dBm54);
809 gainF54 = getGainF(ah, pRD, cp[7], &dontcare);
811 /* Record current dBm at rate 6 */
812 AH_PRIVATE(ah)->ah_maxPowerLevel = 2*dBmRD;
814 cp[13] = cp[12] = cp[11] = cp[10] = cp[14];
816 /* Set GainF Values */
817 cp[0] = gainFRD - gainF54;
818 cp[1] = gainFRD - gainF48;
819 cp[2] = gainFRD - gainF36;
820 /* 9, 12, 18, 24 have no gain_delta from 6 */
821 cp[3] = cp[4] = cp[5] = cp[6] = 0;
826 * Places the device in and out of reset and then places sane
827 * values in the registers based on EEPROM config, initialization
828 * vectors (as determined by the mode), and station configuration
831 ar5210SetTransmitPower(struct ath_hal *ah, const struct ieee80211_channel *chan)
833 #define N(a) (sizeof (a) / sizeof (a[0]))
834 static const uint32_t pwr_regs_start[17] = {
835 0x00000000, 0x00000000, 0x00000000,
836 0x00000000, 0x00000000, 0xf0000000,
837 0xcc000000, 0x00000000, 0x00000000,
838 0x00000000, 0x0a000000, 0x000000e2,
839 0x0a000020, 0x01000002, 0x01000018,
840 0x40000000, 0x00000418
843 uint8_t cp[sizeof(ar5k0007_pwrSettings)];
844 uint32_t pwr_regs[17];
846 OS_MEMCPY(pwr_regs, pwr_regs_start, sizeof(pwr_regs));
847 OS_MEMCPY(cp, ar5k0007_pwrSettings, sizeof(cp));
849 /* Check the EEPROM tx power calibration settings */
850 if (!setupPowerSettings(ah, chan, cp)) {
852 ath_hal_printf(ah, "%s: unable to setup power settings\n",
857 if (cp[15] < 1 || cp[15] > 5) {
859 ath_hal_printf(ah, "%s: OB out of range (%u)\n",
864 if (cp[16] < 1 || cp[16] > 5) {
866 ath_hal_printf(ah, "%s: DB out of range (%u)\n",
872 /* reverse bits of the transmit power array */
873 for (i = 0; i < 7; i++)
874 cp[i] = ath_hal_reverseBits(cp[i], 5);
875 for (i = 7; i < 15; i++)
876 cp[i] = ath_hal_reverseBits(cp[i], 6);
878 /* merge transmit power values into the register - quite gross */
879 pwr_regs[0] |= ((cp[1] << 5) & 0xE0) | (cp[0] & 0x1F);
880 pwr_regs[1] |= ((cp[3] << 7) & 0x80) | ((cp[2] << 2) & 0x7C) |
881 ((cp[1] >> 3) & 0x03);
882 pwr_regs[2] |= ((cp[4] << 4) & 0xF0) | ((cp[3] >> 1) & 0x0F);
883 pwr_regs[3] |= ((cp[6] << 6) & 0xC0) | ((cp[5] << 1) & 0x3E) |
884 ((cp[4] >> 4) & 0x01);
885 pwr_regs[4] |= ((cp[7] << 3) & 0xF8) | ((cp[6] >> 2) & 0x07);
886 pwr_regs[5] |= ((cp[9] << 7) & 0x80) | ((cp[8] << 1) & 0x7E) |
887 ((cp[7] >> 5) & 0x01);
888 pwr_regs[6] |= ((cp[10] << 5) & 0xE0) | ((cp[9] >> 1) & 0x1F);
889 pwr_regs[7] |= ((cp[11] << 3) & 0xF8) | ((cp[10] >> 3) & 0x07);
890 pwr_regs[8] |= ((cp[12] << 1) & 0x7E) | ((cp[11] >> 5) & 0x01);
891 pwr_regs[9] |= ((cp[13] << 5) & 0xE0);
892 pwr_regs[10] |= ((cp[14] << 3) & 0xF8) | ((cp[13] >> 3) & 0x07);
893 pwr_regs[11] |= ((cp[14] >> 5) & 0x01);
896 pwr_regs[8] |= (ath_hal_reverseBits(cp[15], 3) << 7) & 0x80;
897 pwr_regs[9] |= (ath_hal_reverseBits(cp[15], 3) >> 1) & 0x03;
900 pwr_regs[9] |= (ath_hal_reverseBits(cp[16], 3) << 2) & 0x1C;
902 /* Write the registers */
903 for (i = 0; i < N(pwr_regs)-1; i++)
904 OS_REG_WRITE(ah, 0x0000989c, pwr_regs[i]);
905 /* last write is a flush */
906 OS_REG_WRITE(ah, 0x000098d4, pwr_regs[i]);
913 * Takes the MHz channel value and sets the Channel value
915 * ASSUMES: Writes enabled to analog bus before AGC is active
916 * or by disabling the AGC.
919 ar5210SetChannel(struct ath_hal *ah, struct ieee80211_channel *chan)
921 uint16_t freq = ath_hal_gethwchannel(ah, chan);
924 /* Set the Channel */
925 data = ath_hal_reverseBits((freq - 5120)/10, 5);
926 data = (data << 1) | 0x41;
927 OS_REG_WRITE(ah, AR_PHY(0x27), data);
928 OS_REG_WRITE(ah, AR_PHY(0x30), 0);
929 AH_PRIVATE(ah)->ah_curchan = chan;
934 ar5210GetNoiseFloor(struct ath_hal *ah)
938 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
940 nf = 0 - ((nf ^ 0x1ff) + 1);
944 #define NORMAL_NF_THRESH (-72)
946 * Peform the noisefloor calibration and check for
947 * any constant channel interference
949 * Returns: TRUE for a successful noise floor calibration; else FALSE
952 ar5210CalNoiseFloor(struct ath_hal *ah, HAL_CHANNEL_INTERNAL *ichan)
956 /* Calibrate the noise floor */
957 OS_REG_WRITE(ah, AR_PHY_AGCCTL,
958 OS_REG_READ(ah, AR_PHY_AGCCTL) | AR_PHY_AGC_NF);
960 /* Do not read noise floor until it has done the first update */
961 if (!ath_hal_wait(ah, AR_PHY_AGCCTL, AR_PHY_AGC_NF, 0)) {
963 ath_hal_printf(ah, " -PHY NF Reg state: 0x%x\n",
964 OS_REG_READ(ah, AR_PHY_AGCCTL));
965 ath_hal_printf(ah, " -MAC Reset Reg state: 0x%x\n",
966 OS_REG_READ(ah, AR_RC));
967 ath_hal_printf(ah, " -PHY Active Reg state: 0x%x\n",
968 OS_REG_READ(ah, AR_PHY_ACTIVE));
969 #endif /* ATH_HAL_DEBUG */
974 /* Keep checking until the floor is below the threshold or the nf is done */
975 for (nfLoops = 0; ((nfLoops < 21) && (nf > NORMAL_NF_THRESH)); nfLoops++) {
976 OS_DELAY(1000); /* Sleep for 1 ms */
977 nf = ar5210GetNoiseFloor(ah);
980 if (nf > NORMAL_NF_THRESH) {
981 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: Bad noise cal %d\n",
983 ichan->rawNoiseFloor = 0;
986 ichan->rawNoiseFloor = nf;
991 * Adjust NF based on statistical values for 5GHz frequencies.
994 ar5210GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
1000 ar5210GetRfgain(struct ath_hal *ah)
1002 return HAL_RFGAIN_INACTIVE;