2 * Copyright (c) 2002-2009 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include "ah_internal.h"
24 #include "ah_desc.h" /* NB: for HAL_PHYERR* */
26 #include "ar5212/ar5212.h"
27 #include "ar5212/ar5212reg.h"
28 #include "ar5212/ar5212phy.h"
30 #include "ah_eeprom_v3.h"
32 #define AR_NUM_GPIO 6 /* 6 GPIO pins */
33 #define AR_GPIOD_MASK 0x0000002F /* GPIO data reg r/w mask */
36 ar5212GetMacAddress(struct ath_hal *ah, uint8_t *mac)
38 struct ath_hal_5212 *ahp = AH5212(ah);
40 OS_MEMCPY(mac, ahp->ah_macaddr, IEEE80211_ADDR_LEN);
44 ar5212SetMacAddress(struct ath_hal *ah, const uint8_t *mac)
46 struct ath_hal_5212 *ahp = AH5212(ah);
48 OS_MEMCPY(ahp->ah_macaddr, mac, IEEE80211_ADDR_LEN);
53 ar5212GetBssIdMask(struct ath_hal *ah, uint8_t *mask)
55 struct ath_hal_5212 *ahp = AH5212(ah);
57 OS_MEMCPY(mask, ahp->ah_bssidmask, IEEE80211_ADDR_LEN);
61 ar5212SetBssIdMask(struct ath_hal *ah, const uint8_t *mask)
63 struct ath_hal_5212 *ahp = AH5212(ah);
65 /* save it since it must be rewritten on reset */
66 OS_MEMCPY(ahp->ah_bssidmask, mask, IEEE80211_ADDR_LEN);
68 OS_REG_WRITE(ah, AR_BSSMSKL, LE_READ_4(ahp->ah_bssidmask));
69 OS_REG_WRITE(ah, AR_BSSMSKU, LE_READ_2(ahp->ah_bssidmask + 4));
74 * Attempt to change the cards operating regulatory domain to the given value
77 ar5212SetRegulatoryDomain(struct ath_hal *ah,
78 uint16_t regDomain, HAL_STATUS *status)
82 if (AH_PRIVATE(ah)->ah_currentRD == regDomain) {
86 if (ath_hal_eepromGetFlag(ah, AR_EEP_WRITEPROTECT)) {
90 #ifdef AH_SUPPORT_WRITE_REGDOMAIN
91 if (ath_hal_eepromWrite(ah, AR_EEPROM_REG_DOMAIN, regDomain)) {
92 HALDEBUG(ah, HAL_DEBUG_ANY,
93 "%s: set regulatory domain to %u (0x%x)\n",
94 __func__, regDomain, regDomain);
95 AH_PRIVATE(ah)->ah_currentRD = regDomain;
107 * Return the wireless modes (a,b,g,t) supported by hardware.
109 * This value is what is actually supported by the hardware
110 * and is unaffected by regulatory/country code settings.
113 ar5212GetWirelessModes(struct ath_hal *ah)
117 if (ath_hal_eepromGetFlag(ah, AR_EEP_AMODE)) {
119 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO5DISABLE))
120 mode |= HAL_MODE_TURBO | HAL_MODE_108A;
121 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
122 mode |= HAL_MODE_11A_HALF_RATE;
123 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
124 mode |= HAL_MODE_11A_QUARTER_RATE;
126 if (ath_hal_eepromGetFlag(ah, AR_EEP_BMODE))
127 mode |= HAL_MODE_11B;
128 if (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) &&
129 AH_PRIVATE(ah)->ah_subvendorid != AR_SUBVENDOR_ID_NOG) {
130 mode |= HAL_MODE_11G;
131 if (!ath_hal_eepromGetFlag(ah, AR_EEP_TURBO2DISABLE))
132 mode |= HAL_MODE_108G;
133 if (AH_PRIVATE(ah)->ah_caps.halChanHalfRate)
134 mode |= HAL_MODE_11G_HALF_RATE;
135 if (AH_PRIVATE(ah)->ah_caps.halChanQuarterRate)
136 mode |= HAL_MODE_11G_QUARTER_RATE;
142 * Set the interrupt and GPIO values so the ISR can disable RF
143 * on a switch signal. Assumes GPIO port and interrupt polarity
144 * are set prior to call.
147 ar5212EnableRfKill(struct ath_hal *ah)
149 uint16_t rfsilent = AH_PRIVATE(ah)->ah_rfsilent;
150 int select = MS(rfsilent, AR_EEPROM_RFSILENT_GPIO_SEL);
151 int polarity = MS(rfsilent, AR_EEPROM_RFSILENT_POLARITY);
154 * Configure the desired GPIO port for input
155 * and enable baseband rf silence.
157 ath_hal_gpioCfgInput(ah, select);
158 OS_REG_SET_BIT(ah, AR_PHY(0), 0x00002000);
160 * If radio disable switch connection to GPIO bit x is enabled
161 * program GPIO interrupt.
162 * If rfkill bit on eeprom is 1, setupeeprommap routine has already
163 * verified that it is a later version of eeprom, it has a place for
164 * rfkill bit and it is set to 1, indicating that GPIO bit x hardware
165 * connection is present.
167 ath_hal_gpioSetIntr(ah, select,
168 (ath_hal_gpioGet(ah, select) == polarity ? !polarity : polarity));
172 * Change the LED blinking pattern to correspond to the connectivity
175 ar5212SetLedState(struct ath_hal *ah, HAL_LED_STATE state)
177 static const uint32_t ledbits[8] = {
178 AR_PCICFG_LEDCTL_NONE, /* HAL_LED_INIT */
179 AR_PCICFG_LEDCTL_PEND, /* HAL_LED_SCAN */
180 AR_PCICFG_LEDCTL_PEND, /* HAL_LED_AUTH */
181 AR_PCICFG_LEDCTL_ASSOC, /* HAL_LED_ASSOC*/
182 AR_PCICFG_LEDCTL_ASSOC, /* HAL_LED_RUN */
183 AR_PCICFG_LEDCTL_NONE,
184 AR_PCICFG_LEDCTL_NONE,
185 AR_PCICFG_LEDCTL_NONE,
189 bits = OS_REG_READ(ah, AR_PCICFG);
192 * Enable LED for Nala. There is a bit marked reserved
193 * that must be set and we also turn on the power led.
194 * Because we mark s/w LED control setting the control
195 * status bits below is meangless (the driver must flash
196 * the LED(s) using the GPIO lines).
198 bits = (bits &~ AR_PCICFG_LEDMODE)
199 | SM(AR_PCICFG_LEDMODE_POWON, AR_PCICFG_LEDMODE)
201 | SM(AR_PCICFG_LEDMODE_NETON, AR_PCICFG_LEDMODE)
205 bits = (bits &~ AR_PCICFG_LEDCTL)
206 | SM(ledbits[state & 0x7], AR_PCICFG_LEDCTL);
207 OS_REG_WRITE(ah, AR_PCICFG, bits);
211 * Change association related fields programmed into the hardware.
212 * Writing a valid BSSID to the hardware effectively enables the hardware
213 * to synchronize its TSF to the correct beacons and receive frames coming
214 * from that BSSID. It is called by the SME JOIN operation.
217 ar5212WriteAssocid(struct ath_hal *ah, const uint8_t *bssid, uint16_t assocId)
219 struct ath_hal_5212 *ahp = AH5212(ah);
221 /* XXX save bssid for possible re-use on reset */
222 OS_MEMCPY(ahp->ah_bssid, bssid, IEEE80211_ADDR_LEN);
223 OS_REG_WRITE(ah, AR_BSS_ID0, LE_READ_4(ahp->ah_bssid));
224 OS_REG_WRITE(ah, AR_BSS_ID1, LE_READ_2(ahp->ah_bssid+4) |
225 ((assocId & 0x3fff)<<AR_BSS_ID1_AID_S));
229 * Get the current hardware tsf for stamlme
232 ar5212GetTsf64(struct ath_hal *ah)
234 uint32_t low1, low2, u32;
236 /* sync multi-word read */
237 low1 = OS_REG_READ(ah, AR_TSF_L32);
238 u32 = OS_REG_READ(ah, AR_TSF_U32);
239 low2 = OS_REG_READ(ah, AR_TSF_L32);
240 if (low2 < low1) { /* roll over */
242 * If we are not preempted this will work. If we are
243 * then we re-reading AR_TSF_U32 does no good as the
244 * low bits will be meaningless. Likewise reading
245 * L32, U32, U32, then comparing the last two reads
246 * to check for rollover doesn't help if preempted--so
247 * we take this approach as it costs one less PCI read
248 * which can be noticeable when doing things like
249 * timestamping packets in monitor mode.
253 return (((uint64_t) u32) << 32) | ((uint64_t) low2);
257 * Get the current hardware tsf for stamlme
260 ar5212GetTsf32(struct ath_hal *ah)
262 return OS_REG_READ(ah, AR_TSF_L32);
266 ar5212SetTsf64(struct ath_hal *ah, uint64_t tsf64)
268 OS_REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
269 OS_REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
273 * Reset the current hardware tsf for stamlme.
276 ar5212ResetTsf(struct ath_hal *ah)
279 uint32_t val = OS_REG_READ(ah, AR_BEACON);
281 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
283 * When resetting the TSF, write twice to the
284 * corresponding register; each write to the RESET_TSF bit toggles
285 * the internal signal to cause a reset of the TSF - but if the signal
286 * is left high, it will reset the TSF on the next chip reset also!
287 * writing the bit an even number of times fixes this issue
289 OS_REG_WRITE(ah, AR_BEACON, val | AR_BEACON_RESET_TSF);
293 * Set or clear hardware basic rate bit
294 * Set hardware basic rate set if basic rate is found
295 * and basic rate is equal or less than 2Mbps
298 ar5212SetBasicRate(struct ath_hal *ah, HAL_RATE_SET *rs)
300 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
305 if (chan == AH_NULL || !IEEE80211_IS_CHAN_CCK(chan))
308 for (i = 0; i < rs->rs_count; i++) {
309 uint8_t rset = rs->rs_rates[i];
310 /* Basic rate defined? */
311 if ((rset & 0x80) && (rset &= 0x7f) >= xset)
315 * Set the h/w bit to reflect whether or not the basic
316 * rate is found to be equal or less than 2Mbps.
318 reg = OS_REG_READ(ah, AR_STA_ID1);
319 if (xset && xset/2 <= 2)
320 OS_REG_WRITE(ah, AR_STA_ID1, reg | AR_STA_ID1_BASE_RATE_11B);
322 OS_REG_WRITE(ah, AR_STA_ID1, reg &~ AR_STA_ID1_BASE_RATE_11B);
326 * Grab a semi-random value from hardware registers - may not
330 ar5212GetRandomSeed(struct ath_hal *ah)
334 nf = (OS_REG_READ(ah, AR_PHY(25)) >> 19) & 0x1ff;
336 nf = 0 - ((nf ^ 0x1ff) + 1);
337 return (OS_REG_READ(ah, AR_TSF_U32) ^
338 OS_REG_READ(ah, AR_TSF_L32) ^ nf);
342 * Detect if our card is present
345 ar5212DetectCardPresent(struct ath_hal *ah)
347 uint16_t macVersion, macRev;
351 * Read the Silicon Revision register and compare that
352 * to what we read at attach time. If the same, we say
353 * a card/device is present.
355 v = OS_REG_READ(ah, AR_SREV) & AR_SREV_ID;
356 macVersion = v >> AR_SREV_ID_S;
357 macRev = v & AR_SREV_REVISION;
358 return (AH_PRIVATE(ah)->ah_macVersion == macVersion &&
359 AH_PRIVATE(ah)->ah_macRev == macRev);
363 ar5212EnableMibCounters(struct ath_hal *ah)
365 /* NB: this just resets the mib counter machinery */
366 OS_REG_WRITE(ah, AR_MIBC,
367 ~(AR_MIBC_COW | AR_MIBC_FMC | AR_MIBC_CMC | AR_MIBC_MCS) & 0x0f);
371 ar5212DisableMibCounters(struct ath_hal *ah)
373 OS_REG_WRITE(ah, AR_MIBC, AR_MIBC | AR_MIBC_CMC);
377 * Update MIB Counters
380 ar5212UpdateMibCounters(struct ath_hal *ah, HAL_MIB_STATS* stats)
382 stats->ackrcv_bad += OS_REG_READ(ah, AR_ACK_FAIL);
383 stats->rts_bad += OS_REG_READ(ah, AR_RTS_FAIL);
384 stats->fcs_bad += OS_REG_READ(ah, AR_FCS_FAIL);
385 stats->rts_good += OS_REG_READ(ah, AR_RTS_OK);
386 stats->beacons += OS_REG_READ(ah, AR_BEACON_CNT);
390 * Detect if the HW supports spreading a CCK signal on channel 14
393 ar5212IsJapanChannelSpreadSupported(struct ath_hal *ah)
399 * Get the rssi of frame curently being received.
402 ar5212GetCurRssi(struct ath_hal *ah)
404 return (OS_REG_READ(ah, AR_PHY_CURRENT_RSSI) & 0xff);
408 ar5212GetDefAntenna(struct ath_hal *ah)
410 return (OS_REG_READ(ah, AR_DEF_ANTENNA) & 0x7);
414 ar5212SetDefAntenna(struct ath_hal *ah, u_int antenna)
416 OS_REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
420 ar5212GetAntennaSwitch(struct ath_hal *ah)
422 return AH5212(ah)->ah_antControl;
426 ar5212SetAntennaSwitch(struct ath_hal *ah, HAL_ANT_SETTING setting)
428 struct ath_hal_5212 *ahp = AH5212(ah);
429 const struct ieee80211_channel *chan = AH_PRIVATE(ah)->ah_curchan;
431 if (!ahp->ah_phyPowerOn || chan == AH_NULL) {
432 /* PHY powered off, just stash settings */
433 ahp->ah_antControl = setting;
434 ahp->ah_diversity = (setting == HAL_ANT_VARIABLE);
437 return ar5212SetAntennaSwitchInternal(ah, setting, chan);
441 ar5212IsSleepAfterBeaconBroken(struct ath_hal *ah)
447 ar5212SetSifsTime(struct ath_hal *ah, u_int us)
449 struct ath_hal_5212 *ahp = AH5212(ah);
451 if (us > ath_hal_mac_usec(ah, 0xffff)) {
452 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad SIFS time %u\n",
454 ahp->ah_sifstime = (u_int) -1; /* restore default handling */
457 /* convert to system clocks */
458 OS_REG_WRITE(ah, AR_D_GBL_IFS_SIFS, ath_hal_mac_clks(ah, us-2));
459 ahp->ah_sifstime = us;
465 ar5212GetSifsTime(struct ath_hal *ah)
467 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SIFS) & 0xffff;
468 return ath_hal_mac_usec(ah, clks)+2; /* convert from system clocks */
472 ar5212SetSlotTime(struct ath_hal *ah, u_int us)
474 struct ath_hal_5212 *ahp = AH5212(ah);
476 if (us < HAL_SLOT_TIME_6 || us > ath_hal_mac_usec(ah, 0xffff)) {
477 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad slot time %u\n",
479 ahp->ah_slottime = (u_int) -1; /* restore default handling */
482 /* convert to system clocks */
483 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, ath_hal_mac_clks(ah, us));
484 ahp->ah_slottime = us;
490 ar5212GetSlotTime(struct ath_hal *ah)
492 u_int clks = OS_REG_READ(ah, AR_D_GBL_IFS_SLOT) & 0xffff;
493 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
497 ar5212SetAckTimeout(struct ath_hal *ah, u_int us)
499 struct ath_hal_5212 *ahp = AH5212(ah);
501 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_ACK))) {
502 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad ack timeout %u\n",
504 ahp->ah_acktimeout = (u_int) -1; /* restore default handling */
507 /* convert to system clocks */
508 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
509 AR_TIME_OUT_ACK, ath_hal_mac_clks(ah, us));
510 ahp->ah_acktimeout = us;
516 ar5212GetAckTimeout(struct ath_hal *ah)
518 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_ACK);
519 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
523 ar5212GetAckCTSRate(struct ath_hal *ah)
525 return ((AH5212(ah)->ah_staId1Defaults & AR_STA_ID1_ACKCTS_6MB) == 0);
529 ar5212SetAckCTSRate(struct ath_hal *ah, u_int high)
531 struct ath_hal_5212 *ahp = AH5212(ah);
534 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
535 ahp->ah_staId1Defaults &= ~AR_STA_ID1_ACKCTS_6MB;
537 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_ACKCTS_6MB);
538 ahp->ah_staId1Defaults |= AR_STA_ID1_ACKCTS_6MB;
544 ar5212SetCTSTimeout(struct ath_hal *ah, u_int us)
546 struct ath_hal_5212 *ahp = AH5212(ah);
548 if (us > ath_hal_mac_usec(ah, MS(0xffffffff, AR_TIME_OUT_CTS))) {
549 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: bad cts timeout %u\n",
551 ahp->ah_ctstimeout = (u_int) -1; /* restore default handling */
554 /* convert to system clocks */
555 OS_REG_RMW_FIELD(ah, AR_TIME_OUT,
556 AR_TIME_OUT_CTS, ath_hal_mac_clks(ah, us));
557 ahp->ah_ctstimeout = us;
563 ar5212GetCTSTimeout(struct ath_hal *ah)
565 u_int clks = MS(OS_REG_READ(ah, AR_TIME_OUT), AR_TIME_OUT_CTS);
566 return ath_hal_mac_usec(ah, clks); /* convert from system clocks */
569 /* Setup decompression for given key index */
571 ar5212SetDecompMask(struct ath_hal *ah, uint16_t keyidx, int en)
573 struct ath_hal_5212 *ahp = AH5212(ah);
575 if (keyidx >= HAL_DECOMP_MASK_SIZE)
577 OS_REG_WRITE(ah, AR_DCM_A, keyidx);
578 OS_REG_WRITE(ah, AR_DCM_D, en ? AR_DCM_D_EN : 0);
579 ahp->ah_decompMask[keyidx] = en;
584 /* Setup coverage class */
586 ar5212SetCoverageClass(struct ath_hal *ah, uint8_t coverageclass, int now)
588 uint32_t slot, timeout, eifs;
591 AH_PRIVATE(ah)->ah_coverageClass = coverageclass;
594 if (AH_PRIVATE(ah)->ah_coverageClass == 0)
597 /* Don't apply coverage class to non A channels */
598 if (!IEEE80211_IS_CHAN_A(AH_PRIVATE(ah)->ah_curchan))
601 /* Get core clock rate */
602 clkRate = ath_hal_mac_clks(ah, 1);
605 slot = coverageclass * 3 * clkRate;
606 eifs = coverageclass * 6 * clkRate;
607 if (IEEE80211_IS_CHAN_HALF(AH_PRIVATE(ah)->ah_curchan)) {
608 slot += IFS_SLOT_HALF_RATE;
609 eifs += IFS_EIFS_HALF_RATE;
610 } else if (IEEE80211_IS_CHAN_QUARTER(AH_PRIVATE(ah)->ah_curchan)) {
611 slot += IFS_SLOT_QUARTER_RATE;
612 eifs += IFS_EIFS_QUARTER_RATE;
613 } else { /* full rate */
614 slot += IFS_SLOT_FULL_RATE;
615 eifs += IFS_EIFS_FULL_RATE;
619 * Add additional time for air propagation for ACK and CTS
620 * timeouts. This value is in core clocks.
622 timeout = ACK_CTS_TIMEOUT_11A + (coverageclass * 3 * clkRate);
625 * Write the values: slot, eifs, ack/cts timeouts.
627 OS_REG_WRITE(ah, AR_D_GBL_IFS_SLOT, slot);
628 OS_REG_WRITE(ah, AR_D_GBL_IFS_EIFS, eifs);
629 OS_REG_WRITE(ah, AR_TIME_OUT,
630 SM(timeout, AR_TIME_OUT_CTS)
631 | SM(timeout, AR_TIME_OUT_ACK));
636 ar5212SetQuiet(struct ath_hal *ah, uint32_t period, uint32_t duration,
637 uint32_t nextStart, HAL_QUIET_FLAG flag)
639 OS_REG_WRITE(ah, AR_QUIET2, period | (duration << AR_QUIET2_QUIET_DUR_S));
640 if (flag & HAL_QUIET_ENABLE) {
641 OS_REG_WRITE(ah, AR_QUIET1, nextStart | (1 << 16));
644 OS_REG_WRITE(ah, AR_QUIET1, nextStart);
650 ar5212SetPCUConfig(struct ath_hal *ah)
652 ar5212SetOperatingMode(ah, AH_PRIVATE(ah)->ah_opmode);
656 * Return whether an external 32KHz crystal should be used
657 * to reduce power consumption when sleeping. We do so if
658 * the crystal is present (obtained from EEPROM) and if we
659 * are not running as an AP and are configured to use it.
662 ar5212Use32KHzclock(struct ath_hal *ah, HAL_OPMODE opmode)
664 if (opmode != HAL_M_HOSTAP) {
665 struct ath_hal_5212 *ahp = AH5212(ah);
666 return ath_hal_eepromGetFlag(ah, AR_EEP_32KHZCRYSTAL) &&
667 (ahp->ah_enable32kHzClock == USE_32KHZ ||
668 ahp->ah_enable32kHzClock == AUTO_32KHZ);
674 * If 32KHz clock exists, use it to lower power consumption during sleep
676 * Note: If clock is set to 32 KHz, delays on accessing certain
677 * baseband registers (27-31, 124-127) are required.
680 ar5212SetupClock(struct ath_hal *ah, HAL_OPMODE opmode)
682 if (ar5212Use32KHzclock(ah, opmode)) {
684 * Enable clocks to be turned OFF in BB during sleep
685 * and also enable turning OFF 32MHz/40MHz Refclk
688 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
689 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
690 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);
691 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32, 1);
692 OS_REG_WRITE(ah, AR_TSF_PARM, 61); /* 32 KHz TSF incr */
693 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 1);
695 if (IS_2413(ah) || IS_5413(ah) || IS_2417(ah)) {
696 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x26);
697 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0d);
698 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x07);
699 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x3f);
700 /* # Set sleep clock rate to 32 KHz. */
701 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x2);
703 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x0a);
704 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0c);
705 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x03);
706 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0x20);
707 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x3);
710 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0x0);
711 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
713 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32MHz TSF inc */
715 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
716 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
719 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0a);
720 else if (IS_HB63(ah))
721 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x32);
723 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
724 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
725 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
726 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
727 IS_RAD5112_ANY(ah) || IS_5413(ah) || IS_2417(ah) ? 0x14 : 0x18);
728 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
729 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
734 * If 32KHz clock exists, turn it off and turn back on the 32Mhz
737 ar5212RestoreClock(struct ath_hal *ah, HAL_OPMODE opmode)
739 if (ar5212Use32KHzclock(ah, opmode)) {
740 /* # Set sleep clock rate back to 32 MHz. */
741 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_RATE_IND, 0);
742 OS_REG_RMW_FIELD(ah, AR_PCICFG, AR_PCICFG_SCLK_SEL, 0);
744 OS_REG_WRITE(ah, AR_TSF_PARM, 1); /* 32 MHz TSF incr */
745 OS_REG_RMW_FIELD(ah, AR_USEC, AR_USEC_USEC32,
746 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 39 : 31);
749 * Restore BB registers to power-on defaults
751 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_CONTROL, 0x1f);
752 OS_REG_WRITE(ah, AR_PHY_SLEEP_CTR_LIMIT, 0x7f);
753 OS_REG_WRITE(ah, AR_PHY_SLEEP_SCAL, 0x0e);
754 OS_REG_WRITE(ah, AR_PHY_M_SLEEP, 0x0c);
755 OS_REG_WRITE(ah, AR_PHY_REFCLKDLY, 0xff);
756 OS_REG_WRITE(ah, AR_PHY_REFCLKPD,
757 IS_RAD5112_ANY(ah) || IS_5413(ah) ? 0x14 : 0x18);
762 * Adjust NF based on statistical values for 5GHz frequencies.
763 * Default method: this may be overridden by the rf backend.
766 ar5212GetNfAdjust(struct ath_hal *ah, const HAL_CHANNEL_INTERNAL *c)
768 static const struct {
772 { 5790, 11 }, /* NB: ordered high -> low */
786 for (i = 0; c->channel <= adjustDef[i].freqLow; i++)
788 return adjustDef[i].adjust;
792 ar5212GetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
793 uint32_t capability, uint32_t *result)
795 #define MACVERSION(ah) AH_PRIVATE(ah)->ah_macVersion
796 struct ath_hal_5212 *ahp = AH5212(ah);
797 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
798 const struct ar5212AniState *ani;
801 case HAL_CAP_CIPHER: /* cipher handled in hardware */
802 switch (capability) {
803 case HAL_CIPHER_AES_CCM:
804 return pCap->halCipherAesCcmSupport ?
805 HAL_OK : HAL_ENOTSUPP;
806 case HAL_CIPHER_AES_OCB:
807 case HAL_CIPHER_TKIP:
815 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
816 switch (capability) {
817 case 0: /* hardware capability */
820 return (ahp->ah_staId1Defaults &
821 AR_STA_ID1_CRPT_MIC_ENABLE) ? HAL_OK : HAL_ENXIO;
824 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
825 switch (capability) {
826 case 0: /* hardware capability */
827 return pCap->halTkipMicTxRxKeySupport ?
829 case 1: /* current setting */
830 return (ahp->ah_miscMode &
831 AR_MISC_MODE_MIC_NEW_LOC_ENABLE) ? HAL_ENXIO : HAL_OK;
834 case HAL_CAP_WME_TKIPMIC: /* hardware can do TKIP MIC w/ WMM */
835 /* XXX move to capability bit */
836 return MACVERSION(ah) > AR_SREV_VERSION_VENICE ||
837 (MACVERSION(ah) == AR_SREV_VERSION_VENICE &&
838 AH_PRIVATE(ah)->ah_macRev >= 8) ? HAL_OK : HAL_ENOTSUPP;
839 case HAL_CAP_DIVERSITY: /* hardware supports fast diversity */
840 switch (capability) {
841 case 0: /* hardware capability */
843 case 1: /* current setting */
844 return ahp->ah_diversity ? HAL_OK : HAL_ENXIO;
848 *result = AH_PRIVATE(ah)->ah_diagreg;
851 switch (capability) {
852 case 0: /* hardware capability */
855 return ahp->ah_tpcEnabled ? HAL_OK : HAL_ENXIO;
858 case HAL_CAP_PHYDIAG: /* radar pulse detection capability */
859 switch (capability) {
861 return ath_hal_eepromGetFlag(ah, AR_EEP_AMODE) ?
864 return (ath_hal_eepromGetFlag(ah, AR_EEP_GMODE) ||
865 ath_hal_eepromGetFlag(ah, AR_EEP_BMODE)) ?
869 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
870 switch (capability) {
871 case 0: /* hardware capability */
872 return pCap->halMcastKeySrchSupport ? HAL_OK : HAL_ENXIO;
874 return (ahp->ah_staId1Defaults &
875 AR_STA_ID1_MCAST_KSRCH) ? HAL_OK : HAL_ENXIO;
878 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
879 switch (capability) {
880 case 0: /* hardware capability */
881 return pCap->halTsfAddSupport ? HAL_OK : HAL_ENOTSUPP;
883 return (ahp->ah_miscMode & AR_MISC_MODE_TX_ADD_TSF) ?
887 case HAL_CAP_TPC_ACK:
888 *result = MS(ahp->ah_macTPC, AR_TPC_ACK);
890 case HAL_CAP_TPC_CTS:
891 *result = MS(ahp->ah_macTPC, AR_TPC_CTS);
893 case HAL_CAP_INTMIT: /* interference mitigation */
894 switch (capability) {
895 case HAL_CAP_INTMIT_PRESENT: /* hardware capability */
897 case HAL_CAP_INTMIT_ENABLE:
898 return (ahp->ah_procPhyErr & HAL_ANI_ENA) ?
900 case HAL_CAP_INTMIT_NOISE_IMMUNITY_LEVEL:
901 case HAL_CAP_INTMIT_OFDM_WEAK_SIGNAL_LEVEL:
902 case HAL_CAP_INTMIT_CCK_WEAK_SIGNAL_THR:
903 case HAL_CAP_INTMIT_FIRSTEP_LEVEL:
904 case HAL_CAP_INTMIT_SPUR_IMMUNITY_LEVEL:
905 ani = ar5212AniGetCurrentState(ah);
908 switch (capability) {
909 case 2: *result = ani->noiseImmunityLevel; break;
910 case 3: *result = !ani->ofdmWeakSigDetectOff; break;
911 case 4: *result = ani->cckWeakSigThreshold; break;
912 case 5: *result = ani->firstepLevel; break;
913 case 6: *result = ani->spurImmunityLevel; break;
919 return ath_hal_getcapability(ah, type, capability, result);
925 ar5212SetCapability(struct ath_hal *ah, HAL_CAPABILITY_TYPE type,
926 uint32_t capability, uint32_t setting, HAL_STATUS *status)
928 #define N(a) (sizeof(a)/sizeof(a[0]))
929 struct ath_hal_5212 *ahp = AH5212(ah);
930 const HAL_CAPABILITIES *pCap = &AH_PRIVATE(ah)->ah_caps;
934 case HAL_CAP_TKIP_MIC: /* handle TKIP MIC in hardware */
936 ahp->ah_staId1Defaults |= AR_STA_ID1_CRPT_MIC_ENABLE;
938 ahp->ah_staId1Defaults &= ~AR_STA_ID1_CRPT_MIC_ENABLE;
940 case HAL_CAP_TKIP_SPLIT: /* hardware TKIP uses split keys */
941 if (!pCap->halTkipMicTxRxKeySupport)
943 /* NB: true =>'s use split key cache layout */
945 ahp->ah_miscMode &= ~AR_MISC_MODE_MIC_NEW_LOC_ENABLE;
947 ahp->ah_miscMode |= AR_MISC_MODE_MIC_NEW_LOC_ENABLE;
948 /* NB: write here so keys can be setup w/o a reset */
949 OS_REG_WRITE(ah, AR_MISC_MODE, OS_REG_READ(ah, AR_MISC_MODE) | ahp->ah_miscMode);
951 case HAL_CAP_DIVERSITY:
952 if (ahp->ah_phyPowerOn) {
953 v = OS_REG_READ(ah, AR_PHY_CCK_DETECT);
955 v |= AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
957 v &= ~AR_PHY_CCK_DETECT_BB_ENABLE_ANT_FAST_DIV;
958 OS_REG_WRITE(ah, AR_PHY_CCK_DETECT, v);
960 ahp->ah_diversity = (setting != 0);
962 case HAL_CAP_DIAG: /* hardware diagnostic support */
964 * NB: could split this up into virtual capabilities,
965 * (e.g. 1 => ACK, 2 => CTS, etc.) but it hardly
966 * seems worth the additional complexity.
968 AH_PRIVATE(ah)->ah_diagreg = setting;
969 OS_REG_WRITE(ah, AR_DIAG_SW, AH_PRIVATE(ah)->ah_diagreg);
972 ahp->ah_tpcEnabled = (setting != 0);
974 case HAL_CAP_MCAST_KEYSRCH: /* multicast frame keycache search */
976 ahp->ah_staId1Defaults |= AR_STA_ID1_MCAST_KSRCH;
978 ahp->ah_staId1Defaults &= ~AR_STA_ID1_MCAST_KSRCH;
980 case HAL_CAP_TPC_ACK:
981 case HAL_CAP_TPC_CTS:
982 setting += ahp->ah_txPowerIndexOffset;
985 if (type == HAL_CAP_TPC_ACK) {
986 ahp->ah_macTPC &= AR_TPC_ACK;
987 ahp->ah_macTPC |= MS(setting, AR_TPC_ACK);
989 ahp->ah_macTPC &= AR_TPC_CTS;
990 ahp->ah_macTPC |= MS(setting, AR_TPC_CTS);
992 OS_REG_WRITE(ah, AR_TPC, ahp->ah_macTPC);
994 case HAL_CAP_INTMIT: { /* interference mitigation */
995 /* This maps the public ANI commands to the internal ANI commands */
996 /* Private: HAL_ANI_CMD; Public: HAL_CAP_INTMIT_CMD */
997 static const HAL_ANI_CMD cmds[] = {
1000 HAL_ANI_NOISE_IMMUNITY_LEVEL,
1001 HAL_ANI_OFDM_WEAK_SIGNAL_DETECTION,
1002 HAL_ANI_CCK_WEAK_SIGNAL_THR,
1003 HAL_ANI_FIRSTEP_LEVEL,
1004 HAL_ANI_SPUR_IMMUNITY_LEVEL,
1006 return capability < N(cmds) ?
1007 AH5212(ah)->ah_aniControl(ah, cmds[capability], setting) :
1010 case HAL_CAP_TSF_ADJUST: /* hardware has beacon tsf adjust */
1011 if (pCap->halTsfAddSupport) {
1013 ahp->ah_miscMode |= AR_MISC_MODE_TX_ADD_TSF;
1015 ahp->ah_miscMode &= ~AR_MISC_MODE_TX_ADD_TSF;
1020 return ath_hal_setcapability(ah, type, capability,
1027 ar5212GetDiagState(struct ath_hal *ah, int request,
1028 const void *args, uint32_t argsize,
1029 void **result, uint32_t *resultsize)
1031 struct ath_hal_5212 *ahp = AH5212(ah);
1034 if (ath_hal_getdiagstate(ah, request, args, argsize, result, resultsize))
1037 case HAL_DIAG_EEPROM:
1038 case HAL_DIAG_EEPROM_EXP_11A:
1039 case HAL_DIAG_EEPROM_EXP_11B:
1040 case HAL_DIAG_EEPROM_EXP_11G:
1041 case HAL_DIAG_RFGAIN:
1042 return ath_hal_eepromDiag(ah, request,
1043 args, argsize, result, resultsize);
1044 case HAL_DIAG_RFGAIN_CURSTEP:
1045 *result = __DECONST(void *, ahp->ah_gainValues.currStep);
1046 *resultsize = (*result == AH_NULL) ?
1047 0 : sizeof(GAIN_OPTIMIZATION_STEP);
1049 case HAL_DIAG_PCDAC:
1050 *result = ahp->ah_pcdacTable;
1051 *resultsize = ahp->ah_pcdacTableSize;
1053 case HAL_DIAG_TXRATES:
1054 *result = &ahp->ah_ratesArray[0];
1055 *resultsize = sizeof(ahp->ah_ratesArray);
1057 case HAL_DIAG_ANI_CURRENT:
1058 *result = ar5212AniGetCurrentState(ah);
1059 *resultsize = (*result == AH_NULL) ?
1060 0 : sizeof(struct ar5212AniState);
1062 case HAL_DIAG_ANI_STATS:
1063 *result = ar5212AniGetCurrentStats(ah);
1064 *resultsize = (*result == AH_NULL) ?
1065 0 : sizeof(struct ar5212Stats);
1067 case HAL_DIAG_ANI_CMD:
1068 if (argsize != 2*sizeof(uint32_t))
1070 AH5212(ah)->ah_aniControl(ah, ((const uint32_t *)args)[0],
1071 ((const uint32_t *)args)[1]);
1073 case HAL_DIAG_ANI_PARAMS:
1075 * NB: We assume struct ar5212AniParams is identical
1076 * to HAL_ANI_PARAMS; if they diverge then we'll need
1079 if (argsize == 0 && args == AH_NULL) {
1080 struct ar5212AniState *aniState =
1081 ar5212AniGetCurrentState(ah);
1082 if (aniState == AH_NULL)
1084 *result = __DECONST(void *, aniState->params);
1085 *resultsize = sizeof(struct ar5212AniParams);
1088 if (argsize != sizeof(struct ar5212AniParams))
1090 return ar5212AniSetParams(ah, args, args);
1097 * Check whether there's an in-progress NF completion.
1099 * Returns AH_TRUE if there's a in-progress NF calibration, AH_FALSE
1103 ar5212IsNFCalInProgress(struct ath_hal *ah)
1105 if (OS_REG_READ(ah, AR_PHY_AGC_CONTROL) & AR_PHY_AGC_CONTROL_NF)
1111 * Wait for an in-progress NF calibration to complete.
1113 * The completion function waits "i" times 10uS.
1114 * It returns AH_TRUE if the NF calibration completed (or was never
1115 * in progress); AH_FALSE if it was still in progress after "i" checks.
1118 ar5212WaitNFCalComplete(struct ath_hal *ah, int i)
1122 i = 1; /* it should run at least once */
1123 for (j = 0; j < i; j++) {
1124 if (! ar5212IsNFCalInProgress(ah))
1132 ar5212EnableDfs(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
1135 val = OS_REG_READ(ah, AR_PHY_RADAR_0);
1137 if (pe->pe_firpwr != HAL_PHYERR_PARAM_NOVAL) {
1138 val &= ~AR_PHY_RADAR_0_FIRPWR;
1139 val |= SM(pe->pe_firpwr, AR_PHY_RADAR_0_FIRPWR);
1141 if (pe->pe_rrssi != HAL_PHYERR_PARAM_NOVAL) {
1142 val &= ~AR_PHY_RADAR_0_RRSSI;
1143 val |= SM(pe->pe_rrssi, AR_PHY_RADAR_0_RRSSI);
1145 if (pe->pe_height != HAL_PHYERR_PARAM_NOVAL) {
1146 val &= ~AR_PHY_RADAR_0_HEIGHT;
1147 val |= SM(pe->pe_height, AR_PHY_RADAR_0_HEIGHT);
1149 if (pe->pe_prssi != HAL_PHYERR_PARAM_NOVAL) {
1150 val &= ~AR_PHY_RADAR_0_PRSSI;
1151 val |= SM(pe->pe_prssi, AR_PHY_RADAR_0_PRSSI);
1153 if (pe->pe_inband != HAL_PHYERR_PARAM_NOVAL) {
1154 val &= ~AR_PHY_RADAR_0_INBAND;
1155 val |= SM(pe->pe_inband, AR_PHY_RADAR_0_INBAND);
1157 OS_REG_WRITE(ah, AR_PHY_RADAR_0, val | AR_PHY_RADAR_0_ENA);
1161 ar5212GetDfsThresh(struct ath_hal *ah, HAL_PHYERR_PARAM *pe)
1165 val = OS_REG_READ(ah, AR_PHY_RADAR_0);
1167 temp = MS(val,AR_PHY_RADAR_0_FIRPWR);
1169 pe->pe_firpwr = temp;
1170 pe->pe_rrssi = MS(val, AR_PHY_RADAR_0_RRSSI);
1171 pe->pe_height = MS(val, AR_PHY_RADAR_0_HEIGHT);
1172 pe->pe_prssi = MS(val, AR_PHY_RADAR_0_PRSSI);
1173 pe->pe_inband = MS(val, AR_PHY_RADAR_0_INBAND);
1178 pe->pe_extchannel = AH_FALSE;
1182 * Process the radar phy error and extract the pulse duration.
1185 ar5212ProcessRadarEvent(struct ath_hal *ah, struct ath_rx_status *rxs,
1186 uint64_t fulltsf, const char *buf, HAL_DFS_EVENT *event)
1191 /* Check whether the given phy error is a radar event */
1192 if ((rxs->rs_phyerr != HAL_PHYERR_RADAR) &&
1193 (rxs->rs_phyerr != HAL_PHYERR_FALSE_RADAR_EXT))
1197 * The first byte is the pulse width - if there's
1198 * no data, simply set the duration to 0
1200 if (rxs->rs_datalen >= 1)
1201 /* The pulse width is byte 0 of the data */
1202 dur = ((uint8_t) buf[0]) & 0xff;
1206 /* Pulse RSSI is the normal reported RSSI */
1207 rssi = (uint8_t) rxs->rs_rssi;
1209 /* 0 duration/rssi is not a valid radar event */
1210 if (dur == 0 && rssi == 0)
1213 HALDEBUG(ah, HAL_DEBUG_DFS, "%s: rssi=%d, dur=%d\n",
1214 __func__, rssi, dur);
1216 /* Record the event */
1217 event->re_full_ts = fulltsf;
1218 event->re_ts = rxs->rs_tstamp;
1219 event->re_rssi = rssi;
1220 event->re_dur = dur;
1221 event->re_flags = HAL_DFS_EVENT_PRICH;
1227 * Return whether 5GHz fast-clock (44MHz) is enabled.
1228 * It's always disabled for AR5212 series NICs.
1231 ar5212IsFastClockEnabled(struct ath_hal *ah)