2 * Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
3 * Copyright (c) 2002-2008 Atheros Communications, Inc.
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
22 #include "ah_internal.h"
24 #include "ar5212/ar5212.h"
25 #include "ar5212/ar5212reg.h"
26 #include "ar5212/ar5212desc.h"
29 * Notify Power Mgt is enabled in self-generated frames.
30 * If requested, force chip awake.
32 * Returns A_OK if chip is awake or successfully forced awake.
34 * WARNING WARNING WARNING
35 * There is a problem with the chip where sometimes it will not wake up.
38 ar5212SetPowerModeAwake(struct ath_hal *ah, int setChip)
41 (AR_SCR_SLDUR|AR_SCR_SLE|AR_SCR_SLDTP|AR_SCR_SLDWP|\
42 AR_SCR_SLEPOL|AR_SCR_MIBIE|AR_SCR_UNKNOWN)
43 #define POWER_UP_TIME 2000
49 * Be careful setting the AWAKE mode. When we are called
50 * with the chip powered down the read returns 0xffffffff
51 * which when blindly written back with OS_REG_RMW_FIELD
52 * enables the MIB interrupt for the sleep performance
53 * counters. This can result in an interrupt storm when
54 * ANI is in operation as noone knows to turn off the MIB
57 scr = OS_REG_READ(ah, AR_SCR);
58 if (scr & ~AR_SCR_MASK) {
59 HALDEBUG(ah, HAL_DEBUG_ANY,
60 "%s: bogus SCR 0x%x, PCICFG 0x%x\n",
61 __func__, scr, OS_REG_READ(ah, AR_PCICFG));
64 scr = (scr &~ AR_SCR_SLE) | AR_SCR_SLE_WAKE;
65 OS_REG_WRITE(ah, AR_SCR, scr);
66 OS_DELAY(10); /* Give chip the chance to awake */
68 for (i = POWER_UP_TIME / 50; i != 0; i--) {
69 val = OS_REG_READ(ah, AR_PCICFG);
70 if ((val & AR_PCICFG_SPWR_DN) == 0)
73 OS_REG_WRITE(ah, AR_SCR, scr);
77 ath_hal_printf(ah, "%s: Failed to wakeup in %ums\n",
78 __func__, POWER_UP_TIME/50);
84 OS_REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
91 * Notify Power Mgt is disabled in self-generated frames.
92 * If requested, force chip to sleep.
95 ar5212SetPowerModeSleep(struct ath_hal *ah, int setChip)
97 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
99 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_SLP);
103 * Notify Power Management is enabled in self-generating
104 * fames. If request, set power mode of chip to
105 * auto/normal. Duration in units of 128us (1/8 TU).
108 ar5212SetPowerModeNetworkSleep(struct ath_hal *ah, int setChip)
110 OS_REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
112 OS_REG_RMW_FIELD(ah, AR_SCR, AR_SCR_SLE, AR_SCR_SLE_NORM);
116 * Set power mgt to the requested mode, and conditionally set
120 ar5212SetPowerMode(struct ath_hal *ah, HAL_POWER_MODE mode, int setChip)
122 struct ath_hal_5212 *ahp = AH5212(ah);
124 static const char* modes[] = {
131 int status = AH_TRUE;
133 HALDEBUG(ah, HAL_DEBUG_POWER, "%s: %s -> %s (%s)\n", __func__,
134 modes[ahp->ah_powerMode], modes[mode],
135 setChip ? "set chip " : "");
138 status = ar5212SetPowerModeAwake(ah, setChip);
140 case HAL_PM_FULL_SLEEP:
141 ar5212SetPowerModeSleep(ah, setChip);
143 case HAL_PM_NETWORK_SLEEP:
144 ar5212SetPowerModeNetworkSleep(ah, setChip);
147 HALDEBUG(ah, HAL_DEBUG_ANY, "%s: unknown power mode %u\n",
151 ahp->ah_powerMode = mode;
156 * Return the current sleep mode of the chip
159 ar5212GetPowerMode(struct ath_hal *ah)
161 /* Just so happens the h/w maps directly to the abstracted value */
162 return MS(OS_REG_READ(ah, AR_SCR), AR_SCR_SLE);
167 * Return the current sleep state of the chip
171 ar5212GetPowerStatus(struct ath_hal *ah)
173 return (OS_REG_READ(ah, AR_PCICFG) & AR_PCICFG_SPWR_DN) != 0;