2 * Copyright (c) 2012 Adrian Chadd <adrian@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification.
11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any
13 * redistribution must be conditioned upon including a substantially
14 * similar Disclaimer requirement for further binary redistribution.
17 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
19 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY
20 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
21 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY,
22 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER
25 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
27 * THE POSSIBILITY OF SUCH DAMAGES.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
34 * Driver for the Atheros Wireless LAN controller.
36 * This software is derived from work of Atsushi Onoe; his contribution
37 * is greatly appreciated.
43 * This is needed for register operations which are performed
44 * by the driver - eg, calls to ath_hal_gettsf32().
46 * It's also required for any AH_DEBUG checks in here, eg the
47 * module dependencies.
52 #include <sys/param.h>
53 #include <sys/systm.h>
54 #include <sys/sysctl.h>
56 #include <sys/malloc.h>
58 #include <sys/mutex.h>
59 #include <sys/kernel.h>
60 #include <sys/socket.h>
61 #include <sys/sockio.h>
62 #include <sys/errno.h>
63 #include <sys/callout.h>
65 #include <sys/endian.h>
66 #include <sys/kthread.h>
67 #include <sys/taskqueue.h>
69 #include <sys/module.h>
71 #include <sys/smp.h> /* for mp_ncpus */
73 #include <machine/bus.h>
76 #include <net/if_dl.h>
77 #include <net/if_media.h>
78 #include <net/if_types.h>
79 #include <net/if_arp.h>
80 #include <net/ethernet.h>
81 #include <net/if_llc.h>
83 #include <net80211/ieee80211_var.h>
84 #include <net80211/ieee80211_regdomain.h>
85 #ifdef IEEE80211_SUPPORT_SUPERG
86 #include <net80211/ieee80211_superg.h>
88 #ifdef IEEE80211_SUPPORT_TDMA
89 #include <net80211/ieee80211_tdma.h>
95 #include <netinet/in.h>
96 #include <netinet/if_ether.h>
99 #include <dev/ath/if_athvar.h>
100 #include <dev/ath/ath_hal/ah_devid.h> /* XXX for softled */
101 #include <dev/ath/ath_hal/ah_diagcodes.h>
103 #include <dev/ath/if_ath_debug.h>
104 #include <dev/ath/if_ath_misc.h>
105 #include <dev/ath/if_ath_tsf.h>
106 #include <dev/ath/if_ath_tx.h>
107 #include <dev/ath/if_ath_sysctl.h>
108 #include <dev/ath/if_ath_led.h>
109 #include <dev/ath/if_ath_keycache.h>
110 #include <dev/ath/if_ath_rx.h>
111 #include <dev/ath/if_ath_beacon.h>
112 #include <dev/ath/if_athdfs.h>
115 #include <dev/ath/ath_tx99/ath_tx99.h>
118 #include <dev/ath/if_ath_tx_edma.h>
121 #include <dev/ath/if_ath_alq.h>
125 * some general macros
127 #define INCR(_l, _sz) (_l) ++; (_l) &= ((_sz) - 1)
128 #define DECR(_l, _sz) (_l) --; (_l) &= ((_sz) - 1)
131 * XXX doesn't belong here, and should be tunable
133 #define ATH_TXSTATUS_RING_SIZE 512
135 MALLOC_DECLARE(M_ATHDEV);
137 static void ath_edma_tx_processq(struct ath_softc *sc, int dosched);
140 * Push some frames into the TX FIFO if we have space.
143 ath_edma_tx_fifo_fill(struct ath_softc *sc, struct ath_txq *txq)
145 struct ath_buf *bf, *bf_last;
148 ATH_TXQ_LOCK_ASSERT(txq);
150 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: Q%d: called\n",
154 TAILQ_FOREACH(bf, &txq->axq_q, bf_list) {
155 if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH)
159 * We have space in the FIFO - so let's push a frame
164 * Remove it from the normal list
166 ATH_TXQ_REMOVE(txq, bf, bf_list);
169 * XXX for now, we only dequeue a frame at a time, so
170 * that's only one buffer. Later on when we just
171 * push this staging _list_ into the queue, we'll
172 * set bf_last to the end pointer in the list.
175 DPRINTF(sc, ATH_DEBUG_TX_PROC,
176 "%s: Q%d: depth=%d; pushing %p->%p\n",
184 * Append it to the FIFO staging list
186 ATH_TXQ_INSERT_TAIL(&txq->fifo, bf, bf_list);
189 * Set fifo start / fifo end flags appropriately
192 bf->bf_flags |= ATH_BUF_FIFOPTR;
193 bf_last->bf_flags |= ATH_BUF_FIFOEND;
196 * Push _into_ the FIFO.
198 ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr);
200 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
201 ath_printtxbuf(sc, bf, txq->axq_qnum, i, 0);
202 #endif/* ATH_DEBUG */
204 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
205 ath_tx_alq_post(sc, bf);
206 #endif /* ATH_DEBUG_ALQ */
207 txq->axq_fifo_depth++;
211 ath_hal_txstart(sc->sc_ah, txq->axq_qnum);
215 * Re-initialise the DMA FIFO with the current contents of
218 * This should only be called as part of the chip reset path, as it
219 * assumes the FIFO is currently empty.
222 ath_edma_dma_restart(struct ath_softc *sc, struct ath_txq *txq)
229 DPRINTF(sc, ATH_DEBUG_RESET, "%s: Q%d: called\n",
233 ATH_TXQ_LOCK_ASSERT(txq);
236 * Let's log if the tracked FIFO depth doesn't match
237 * what we actually push in.
239 old_fifo_depth = txq->axq_fifo_depth;
240 txq->axq_fifo_depth = 0;
243 * Walk the FIFO staging list, looking for "head" entries.
244 * Since we may have a partially completed list of frames,
245 * we push the first frame we see into the FIFO and re-mark
246 * it as the head entry. We then skip entries until we see
247 * FIFO end, at which point we get ready to push another
248 * entry into the FIFO.
250 TAILQ_FOREACH(bf, &txq->fifo.axq_q, bf_list) {
252 * If we're looking for FIFOEND and we haven't found
255 * If we're looking for FIFOEND and we've found it,
256 * reset for another descriptor.
259 if (sc->sc_debug & ATH_DEBUG_XMIT_DESC)
260 ath_printtxbuf(sc, bf, txq->axq_qnum, i, 0);
261 #endif/* ATH_DEBUG */
263 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
264 ath_tx_alq_post(sc, bf);
265 #endif /* ATH_DEBUG_ALQ */
267 if (fifostart == 0) {
268 if (bf->bf_flags & ATH_BUF_FIFOEND)
273 /* Make sure we're not overflowing the FIFO! */
274 if (txq->axq_fifo_depth >= HAL_TXFIFO_DEPTH) {
275 device_printf(sc->sc_dev,
276 "%s: Q%d: more frames in the queue; FIFO depth=%d?!\n",
279 txq->axq_fifo_depth);
283 DPRINTF(sc, ATH_DEBUG_RESET,
284 "%s: Q%d: depth=%d: pushing bf=%p; start=%d, end=%d\n",
289 !! (bf->bf_flags & ATH_BUF_FIFOPTR),
290 !! (bf->bf_flags & ATH_BUF_FIFOEND));
294 * Set this to be the first buffer in the FIFO
295 * list - even if it's also the last buffer in
298 bf->bf_flags |= ATH_BUF_FIFOPTR;
300 /* Push it into the FIFO and bump the FIFO count */
301 ath_hal_puttxbuf(sc->sc_ah, txq->axq_qnum, bf->bf_daddr);
302 txq->axq_fifo_depth++;
305 * If this isn't the last entry either, let's
306 * clear fifostart so we continue looking for
309 if (! (bf->bf_flags & ATH_BUF_FIFOEND))
314 /* Only bother starting the queue if there's something in it */
316 ath_hal_txstart(sc->sc_ah, txq->axq_qnum);
318 DPRINTF(sc, ATH_DEBUG_RESET, "%s: Q%d: FIFO depth was %d, is %d\n",
322 txq->axq_fifo_depth);
324 /* And now, let's check! */
325 if (txq->axq_fifo_depth != old_fifo_depth) {
326 device_printf(sc->sc_dev,
327 "%s: Q%d: FIFO depth should be %d, is %d\n",
331 txq->axq_fifo_depth);
336 * Hand off this frame to a hardware queue.
338 * Things are a bit hairy in the EDMA world. The TX FIFO is only
339 * 8 entries deep, so we need to keep track of exactly what we've
340 * pushed into the FIFO and what's just sitting in the TX queue,
343 * So this is split into two halves - frames get appended to the
344 * TXQ; then a scheduler is called to push some frames into the
348 ath_edma_xmit_handoff_hw(struct ath_softc *sc, struct ath_txq *txq,
354 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
355 ("%s: busy status 0x%x", __func__, bf->bf_flags));
358 * XXX TODO: write a hard-coded check to ensure that
359 * the queue id in the TX descriptor matches txq->axq_qnum.
362 /* Update aggr stats */
363 if (bf->bf_state.bfs_aggr)
364 txq->axq_aggr_depth++;
366 /* Push and update frame stats */
367 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
369 /* For now, set the link pointer in the last descriptor
372 * Later on, when it comes time to handling multiple descriptors
373 * in one FIFO push, we can link descriptors together this way.
377 * Finally, call the FIFO schedule routine to schedule some
378 * frames to the FIFO.
380 ath_edma_tx_fifo_fill(sc, txq);
385 * Hand off this frame to a multicast software queue.
387 * The EDMA TX CABQ will get a list of chained frames, chained
388 * together using the next pointer. The single head of that
389 * particular queue is pushed to the hardware CABQ.
392 ath_edma_xmit_handoff_mcast(struct ath_softc *sc, struct ath_txq *txq,
396 ATH_TX_LOCK_ASSERT(sc);
397 KASSERT((bf->bf_flags & ATH_BUF_BUSY) == 0,
398 ("%s: busy status 0x%x", __func__, bf->bf_flags));
402 * XXX this is mostly duplicated in ath_tx_handoff_mcast().
404 if (ATH_TXQ_LAST(txq, axq_q_s) != NULL) {
405 struct ath_buf *bf_last = ATH_TXQ_LAST(txq, axq_q_s);
406 struct ieee80211_frame *wh;
408 /* mark previous frame */
409 wh = mtod(bf_last->bf_m, struct ieee80211_frame *);
410 wh->i_fc[1] |= IEEE80211_FC1_MORE_DATA;
412 /* re-sync buffer to memory */
413 bus_dmamap_sync(sc->sc_dmat, bf_last->bf_dmamap,
414 BUS_DMASYNC_PREWRITE);
416 /* link descriptor */
417 ath_hal_settxdesclink(sc->sc_ah,
422 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXDESC))
423 ath_tx_alq_post(sc, bf);
424 #endif /* ATH_DEBUG_ALQ */
425 ATH_TXQ_INSERT_TAIL(txq, bf, bf_list);
430 * Handoff this frame to the hardware.
432 * For the multicast queue, this will treat it as a software queue
433 * and append it to the list, after updating the MORE_DATA flag
434 * in the previous frame. The cabq processing code will ensure
435 * that the queue contents gets transferred over.
437 * For the hardware queues, this will queue a frame to the queue
438 * like before, then populate the FIFO from that. Since the
439 * EDMA hardware has 8 FIFO slots per TXQ, this ensures that
440 * frames such as management frames don't get prematurely dropped.
442 * This does imply that a similar flush-hwq-to-fifoq method will
443 * need to be called from the processq function, before the
444 * per-node software scheduler is called.
447 ath_edma_xmit_handoff(struct ath_softc *sc, struct ath_txq *txq,
451 DPRINTF(sc, ATH_DEBUG_XMIT_DESC,
452 "%s: called; bf=%p, txq=%p, qnum=%d\n",
458 if (txq->axq_qnum == ATH_TXQ_SWQ)
459 ath_edma_xmit_handoff_mcast(sc, txq, bf);
461 ath_edma_xmit_handoff_hw(sc, txq, bf);
465 ath_edma_setup_txfifo(struct ath_softc *sc, int qnum)
467 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum];
469 te->m_fifo = malloc(sizeof(struct ath_buf *) * HAL_TXFIFO_DEPTH,
472 if (te->m_fifo == NULL) {
473 device_printf(sc->sc_dev, "%s: malloc failed\n",
479 * Set initial "empty" state.
481 te->m_fifo_head = te->m_fifo_tail = te->m_fifo_depth = 0;
487 ath_edma_free_txfifo(struct ath_softc *sc, int qnum)
489 struct ath_tx_edma_fifo *te = &sc->sc_txedma[qnum];
491 /* XXX TODO: actually deref the ath_buf entries? */
492 free(te->m_fifo, M_ATHDEV);
497 ath_edma_dma_txsetup(struct ath_softc *sc)
502 error = ath_descdma_alloc_desc(sc, &sc->sc_txsdma,
503 NULL, "txcomp", sc->sc_tx_statuslen, ATH_TXSTATUS_RING_SIZE);
507 ath_hal_setuptxstatusring(sc->sc_ah,
508 (void *) sc->sc_txsdma.dd_desc,
509 sc->sc_txsdma.dd_desc_paddr,
510 ATH_TXSTATUS_RING_SIZE);
512 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
513 ath_edma_setup_txfifo(sc, i);
520 ath_edma_dma_txteardown(struct ath_softc *sc)
524 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
525 ath_edma_free_txfifo(sc, i);
528 ath_descdma_cleanup(sc, &sc->sc_txsdma, NULL);
533 * Drain all TXQs, potentially after completing the existing completed
537 ath_edma_tx_drain(struct ath_softc *sc, ATH_RESET_TYPE reset_type)
539 struct ifnet *ifp = sc->sc_ifp;
542 DPRINTF(sc, ATH_DEBUG_RESET, "%s: called\n", __func__);
544 (void) ath_stoptxdma(sc);
547 * If reset type is noloss, the TX FIFO needs to be serviced
548 * and those frames need to be handled.
550 * Otherwise, just toss everything in each TX queue.
552 if (reset_type == ATH_RESET_NOLOSS) {
553 ath_edma_tx_processq(sc, 0);
554 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
555 if (ATH_TXQ_SETUP(sc, i)) {
556 ATH_TXQ_LOCK(&sc->sc_txq[i]);
558 * Free the holding buffer; DMA is now
561 ath_txq_freeholdingbuf(sc, &sc->sc_txq[i]);
563 * Reset the link pointer to NULL; there's
564 * no frames to chain DMA to.
566 sc->sc_txq[i].axq_link = NULL;
567 ATH_TXQ_UNLOCK(&sc->sc_txq[i]);
571 for (i = 0; i < HAL_NUM_TX_QUEUES; i++) {
572 if (ATH_TXQ_SETUP(sc, i))
573 ath_tx_draintxq(sc, &sc->sc_txq[i]);
577 /* XXX dump out the TX completion FIFO contents */
579 /* XXX dump out the frames */
581 IF_LOCK(&ifp->if_snd);
582 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
583 IF_UNLOCK(&ifp->if_snd);
588 * TX completion tasklet.
592 ath_edma_tx_proc(void *arg, int npending)
594 struct ath_softc *sc = (struct ath_softc *) arg;
597 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: called, npending=%d\n",
600 ath_edma_tx_processq(sc, 1);
604 * Process the TX status queue.
607 ath_edma_tx_processq(struct ath_softc *sc, int dosched)
609 struct ath_hal *ah = sc->sc_ah;
611 struct ath_tx_status ts;
614 struct ieee80211_node *ni;
620 uint32_t txstatus[32];
623 for (idx = 0; ; idx++) {
624 bzero(&ts, sizeof(ts));
626 ATH_TXSTATUS_LOCK(sc);
628 ath_hal_gettxrawtxdesc(ah, txstatus);
630 status = ath_hal_txprocdesc(ah, NULL, (void *) &ts);
631 ATH_TXSTATUS_UNLOCK(sc);
633 if (status == HAL_EINPROGRESS)
637 if (sc->sc_debug & ATH_DEBUG_TX_PROC)
638 if (ts.ts_queue_id != sc->sc_bhalq)
639 ath_printtxstatbuf(sc, NULL, txstatus, ts.ts_queue_id,
640 idx, (status == HAL_OK));
644 * If there is an error with this descriptor, continue
647 * XXX TBD: log some statistics?
649 if (status == HAL_EIO) {
650 device_printf(sc->sc_dev, "%s: invalid TX status?\n",
655 #if defined(ATH_DEBUG_ALQ) && defined(ATH_DEBUG)
656 if (if_ath_alq_checkdebug(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS))
657 if_ath_alq_post(&sc->sc_alq, ATH_ALQ_EDMA_TXSTATUS,
660 #endif /* ATH_DEBUG_ALQ */
663 * At this point we have a valid status descriptor.
664 * The QID and descriptor ID (which currently isn't set)
665 * is part of the status.
667 * We then assume that the descriptor in question is the
668 * -head- of the given QID. Eventually we should verify
669 * this by using the descriptor ID.
673 * The beacon queue is not currently a "real" queue.
674 * Frames aren't pushed onto it and the lock isn't setup.
675 * So skip it for now; the beacon handling code will
676 * free and alloc more beacon buffers as appropriate.
678 if (ts.ts_queue_id == sc->sc_bhalq)
681 txq = &sc->sc_txq[ts.ts_queue_id];
684 bf = ATH_TXQ_FIRST(&txq->fifo);
687 * Work around the situation where I'm seeing notifications
688 * for Q1 when no frames are available. That needs to be
689 * debugged but not by crashing _here_.
692 device_printf(sc->sc_dev, "%s: Q%d: empty?\n",
699 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: Q%d, bf=%p, start=%d, end=%d\n",
702 !! (bf->bf_flags & ATH_BUF_FIFOPTR),
703 !! (bf->bf_flags & ATH_BUF_FIFOEND));
705 /* XXX TODO: actually output debugging info about this */
708 /* XXX assert the buffer/descriptor matches the status descid */
709 if (ts.ts_desc_id != bf->bf_descid) {
710 device_printf(sc->sc_dev,
711 "%s: mismatched descid (qid=%d, tsdescid=%d, "
720 /* This removes the buffer and decrements the queue depth */
721 ATH_TXQ_REMOVE(&txq->fifo, bf, bf_list);
722 if (bf->bf_state.bfs_aggr)
723 txq->axq_aggr_depth--;
726 * If this was the end of a FIFO set, decrement FIFO depth
728 if (bf->bf_flags & ATH_BUF_FIFOEND)
729 txq->axq_fifo_depth--;
732 * If this isn't the final buffer in a FIFO set, mark
733 * the buffer as busy so it goes onto the holding queue.
735 if (! (bf->bf_flags & ATH_BUF_FIFOEND))
736 bf->bf_flags |= ATH_BUF_BUSY;
738 DPRINTF(sc, ATH_DEBUG_TX_PROC, "%s: Q%d: FIFO depth is now %d (%d)\n",
742 txq->fifo.axq_depth);
744 /* XXX assert FIFO depth >= 0 */
748 * Outside of the TX lock - if the buffer is end
749 * end buffer in this FIFO, we don't need a holding
752 if (bf->bf_flags & ATH_BUF_FIFOEND) {
754 ath_txq_freeholdingbuf(sc, txq);
759 * First we need to make sure ts_rate is valid.
761 * Pre-EDMA chips pass the whole TX descriptor to
762 * the proctxdesc function which will then fill out
763 * ts_rate based on the ts_finaltsi (final TX index)
764 * in the TX descriptor. However the TX completion
765 * FIFO doesn't have this information. So here we
766 * do a separate HAL call to populate that information.
768 * The same problem exists with ts_longretry.
769 * The FreeBSD HAL corrects ts_longretry in the HAL layer;
770 * the AR9380 HAL currently doesn't. So until the HAL
771 * is imported and this can be added, we correct for it
775 /* XXX faked for now. Ew. */
776 if (ts.ts_finaltsi < 4) {
778 bf->bf_state.bfs_rc[ts.ts_finaltsi].ratecode;
779 switch (ts.ts_finaltsi) {
780 case 3: ts.ts_longretry +=
781 bf->bf_state.bfs_rc[2].tries;
782 case 2: ts.ts_longretry +=
783 bf->bf_state.bfs_rc[1].tries;
784 case 1: ts.ts_longretry +=
785 bf->bf_state.bfs_rc[0].tries;
788 device_printf(sc->sc_dev, "%s: finaltsi=%d\n",
791 ts.ts_rate = bf->bf_state.bfs_rc[0].ratecode;
795 * XXX This is terrible.
797 * Right now, some code uses the TX status that is
798 * passed in here, but the completion handlers in the
799 * software TX path also use bf_status.ds_txstat.
800 * Ew. That should all go away.
802 * XXX It's also possible the rate control completion
803 * routine is called twice.
805 memcpy(&bf->bf_status, &ts, sizeof(ts));
810 /* XXX duplicate from ath_tx_processq */
811 if (ni != NULL && ts.ts_status == 0 &&
812 ((bf->bf_state.bfs_txflags & HAL_TXDESC_NOACK) == 0)) {
814 sc->sc_stats.ast_tx_rssi = ts.ts_rssi;
815 ATH_RSSI_LPF(sc->sc_halstats.ns_avgtxrssi,
819 /* Handle frame completion and rate control update */
820 ath_tx_process_buf_completion(sc, txq, &ts, bf);
822 /* bf is invalid at this point */
825 * Now that there's space in the FIFO, let's push some
826 * more frames into it.
830 ath_edma_tx_fifo_fill(sc, txq);
837 IF_LOCK(&sc->sc_ifp->if_snd);
838 sc->sc_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
839 IF_UNLOCK(&sc->sc_ifp->if_snd);
842 /* Kick software scheduler */
844 * XXX It's inefficient to do this if the FIFO queue is full,
845 * but there's no easy way right now to only populate
846 * the txq task for _one_ TXQ. This should be fixed.
853 ath_edma_attach_comp_func(struct ath_softc *sc)
856 TASK_INIT(&sc->sc_txtask, 0, ath_edma_tx_proc, sc);
860 ath_xmit_setup_edma(struct ath_softc *sc)
863 /* Fetch EDMA field and buffer sizes */
864 (void) ath_hal_gettxdesclen(sc->sc_ah, &sc->sc_tx_desclen);
865 (void) ath_hal_gettxstatuslen(sc->sc_ah, &sc->sc_tx_statuslen);
866 (void) ath_hal_getntxmaps(sc->sc_ah, &sc->sc_tx_nmaps);
868 device_printf(sc->sc_dev, "TX descriptor length: %d\n",
870 device_printf(sc->sc_dev, "TX status length: %d\n",
871 sc->sc_tx_statuslen);
872 device_printf(sc->sc_dev, "TX buffers per descriptor: %d\n",
875 sc->sc_tx.xmit_setup = ath_edma_dma_txsetup;
876 sc->sc_tx.xmit_teardown = ath_edma_dma_txteardown;
877 sc->sc_tx.xmit_attach_comp_func = ath_edma_attach_comp_func;
879 sc->sc_tx.xmit_dma_restart = ath_edma_dma_restart;
880 sc->sc_tx.xmit_handoff = ath_edma_xmit_handoff;
881 sc->sc_tx.xmit_drain = ath_edma_tx_drain;