sys/dev/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2010 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 /*
  35  * The following controllers are supported by this driver:
  36  *   BCM5706C A2, A3
  37  *   BCM5706S A2, A3
  38  *   BCM5708C B1, B2
  39  *   BCM5708S B1, B2
  40  *   BCM5709C A1, C0
  41  *   BCM5709S A1, C0
  42  *   BCM5716C C0
  43  *   BCM5716S C0
  44  *
  45  * The following controllers are not supported by this driver:
  46  *   BCM5706C A0, A1 (pre-production)
  47  *   BCM5706S A0, A1 (pre-production)
  48  *   BCM5708C A0, B0 (pre-production)
  49  *   BCM5708S A0, B0 (pre-production)
  50  *   BCM5709C A0  B0, B1, B2 (pre-production)
  51  *   BCM5709S A0, B0, B1, B2 (pre-production)
  52  */
  53
  54 #include "opt_bce.h"
  55
  56 #include <dev/bce/if_bcereg.h>
  57 #include <dev/bce/if_bcefw.h>
  58
  59 /****************************************************************************/
  60 /* BCE Debug Options                                                        */
  61 /****************************************************************************/
  62 #ifdef BCE_DEBUG
  63         u32 bce_debug = BCE_WARN;
  64
  65         /*          0 = Never              */
  66         /*          1 = 1 in 2,147,483,648 */
  67         /*        256 = 1 in     8,388,608 */
  68         /*       2048 = 1 in     1,048,576 */
  69         /*      65536 = 1 in        32,768 */
  70         /*    1048576 = 1 in         2,048 */
  71         /*  268435456 = 1 in             8 */
  72         /*  536870912 = 1 in             4 */
  73         /* 1073741824 = 1 in             2 */
  74
  75         /* Controls how often the l2_fhdr frame error check will fail. */
  76         int l2fhdr_error_sim_control = 0;
  77
  78         /* Controls how often the unexpected attention check will fail. */
  79         int unexpected_attention_sim_control = 0;
  80
  81         /* Controls how often to simulate an mbuf allocation failure. */
  82         int mbuf_alloc_failed_sim_control = 0;
  83
  84         /* Controls how often to simulate a DMA mapping failure. */
  85         int dma_map_addr_failed_sim_control = 0;
  86
  87         /* Controls how often to simulate a bootcode failure. */
  88         int bootcode_running_failure_sim_control = 0;
  89 #endif
  90
  91 /****************************************************************************/
  92 /* PCI Device ID Table                                                      */
  93 /*                                                                          */
  94 /* Used by bce_probe() to identify the devices supported by this driver.    */
  95 /****************************************************************************/
  96 #define BCE_DEVDESC_MAX         64
  97
  98 static const struct bce_type bce_devs[] = {
  99         /* BCM5706C Controllers and OEM boards. */
 100         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 101                 "HP NC370T Multifunction Gigabit Server Adapter" },
 102         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 103                 "HP NC370i Multifunction Gigabit Server Adapter" },
 104         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 105                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 106         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 107                 "HP NC371i Multifunction Gigabit Server Adapter" },
 108         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 109                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 110
 111         /* BCM5706S controllers and OEM boards. */
 112         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 113                 "HP NC370F Multifunction Gigabit Server Adapter" },
 114         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 115                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 116
 117         /* BCM5708C controllers and OEM boards. */
 118         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 119                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 120         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 121                 "HP NC373i Multifunction Gigabit Server Adapter" },
 122         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 123                 "HP NC374m PCIe Multifunction Adapter" },
 124         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 125                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 126
 127         /* BCM5708S controllers and OEM boards. */
 128         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 129                 "HP NC373m Multifunction Gigabit Server Adapter" },
 130         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 131                 "HP NC373i Multifunction Gigabit Server Adapter" },
 132         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 133                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 134         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 135                 "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 136
 137         /* BCM5709C controllers and OEM boards. */
 138         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 139                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 140         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 141                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 142         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 143                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 144
 145         /* BCM5709S controllers and OEM boards. */
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 147                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 149                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 151                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 152
 153         /* BCM5716 controllers and OEM boards. */
 154         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,  PCI_ANY_ID,  PCI_ANY_ID,
 155                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 156
 157         { 0, 0, 0, 0, NULL }
 158 };
 159
 160
 161 /****************************************************************************/
 162 /* Supported Flash NVRAM device data.                                       */
 163 /****************************************************************************/
 164 static const struct flash_spec flash_table[] =
 165 {
 166 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 167 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 168
 169         /* Slow EEPROM */
 170         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 171          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 172          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 173          "EEPROM - slow"},
 174         /* Expansion entry 0001 */
 175         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 176          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 177          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 178          "Entry 0001"},
 179         /* Saifun SA25F010 (non-buffered flash) */
 180         /* strap, cfg1, & write1 need updates */
 181         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 182          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 183          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 184          "Non-buffered flash (128kB)"},
 185         /* Saifun SA25F020 (non-buffered flash) */
 186         /* strap, cfg1, & write1 need updates */
 187         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 189          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 190          "Non-buffered flash (256kB)"},
 191         /* Expansion entry 0100 */
 192         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 193          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 194          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 195          "Entry 0100"},
 196         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 197         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 198          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 199          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 200          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 201         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 202         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 203          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 204          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 205          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 206         /* Saifun SA25F005 (non-buffered flash) */
 207         /* strap, cfg1, & write1 need updates */
 208         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 209          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 210          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 211          "Non-buffered flash (64kB)"},
 212         /* Fast EEPROM */
 213         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 214          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 215          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 216          "EEPROM - fast"},
 217         /* Expansion entry 1001 */
 218         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 219          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 220          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 221          "Entry 1001"},
 222         /* Expansion entry 1010 */
 223         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 224          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 225          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 226          "Entry 1010"},
 227         /* ATMEL AT45DB011B (buffered flash) */
 228         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 229          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 230          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 231          "Buffered flash (128kB)"},
 232         /* Expansion entry 1100 */
 233         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 234          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 235          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 236          "Entry 1100"},
 237         /* Expansion entry 1101 */
 238         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 239          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 240          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 241          "Entry 1101"},
 242         /* Ateml Expansion entry 1110 */
 243         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 244          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 245          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 246          "Entry 1110 (Atmel)"},
 247         /* ATMEL AT45DB021B (buffered flash) */
 248         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 249          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 250          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 251          "Buffered flash (256kB)"},
 252 };
 253
 254 /*
 255  * The BCM5709 controllers transparently handle the
 256  * differences between Atmel 264 byte pages and all
 257  * flash devices which use 256 byte pages, so no
 258  * logical-to-physical mapping is required in the
 259  * driver.
 260  */
 261 static const struct flash_spec flash_5709 = {
 262         .flags          = BCE_NV_BUFFERED,
 263         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 264         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 265         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 266         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 267         .name           = "5709/5716 buffered flash (256kB)",
 268 };
 269
 270
 271 /****************************************************************************/
 272 /* FreeBSD device entry points.                                             */
 273 /****************************************************************************/
 274 static int  bce_probe                   (device_t);
 275 static int  bce_attach                  (device_t);
 276 static int  bce_detach                  (device_t);
 277 static int  bce_shutdown                (device_t);
 278
 279
 280 /****************************************************************************/
 281 /* BCE Debug Data Structure Dump Routines                                   */
 282 /****************************************************************************/
 283 #ifdef BCE_DEBUG
 284 static u32  bce_reg_rd                          (struct bce_softc *, u32);
 285 static void bce_reg_wr                          (struct bce_softc *, u32, u32);
 286 static void bce_reg_wr16                        (struct bce_softc *, u32, u16);
 287 static u32  bce_ctx_rd                          (struct bce_softc *, u32, u32);
 288 static void bce_dump_enet                       (struct bce_softc *, struct mbuf *);
 289 static void bce_dump_mbuf                       (struct bce_softc *, struct mbuf *);
 290 static void bce_dump_tx_mbuf_chain      (struct bce_softc *, u16, int);
 291 static void bce_dump_rx_mbuf_chain      (struct bce_softc *, u16, int);
 292 static void bce_dump_pg_mbuf_chain      (struct bce_softc *, u16, int);
 293 static void bce_dump_txbd                       (struct bce_softc *,
 294     int, struct tx_bd *);
 295 static void bce_dump_rxbd                       (struct bce_softc *,
 296     int, struct rx_bd *);
 297 static void bce_dump_pgbd                       (struct bce_softc *,
 298     int, struct rx_bd *);
 299 static void bce_dump_l2fhdr             (struct bce_softc *,
 300     int, struct l2_fhdr *);
 301 static void bce_dump_ctx                        (struct bce_softc *, u16);
 302 static void bce_dump_ftqs                       (struct bce_softc *);
 303 static void bce_dump_tx_chain           (struct bce_softc *, u16, int);
 304 static void bce_dump_rx_bd_chain        (struct bce_softc *, u16, int);
 305 static void bce_dump_pg_chain           (struct bce_softc *, u16, int);
 306 static void bce_dump_status_block       (struct bce_softc *);
 307 static void bce_dump_stats_block        (struct bce_softc *);
 308 static void bce_dump_driver_state       (struct bce_softc *);
 309 static void bce_dump_hw_state           (struct bce_softc *);
 310 static void bce_dump_shmem_state        (struct bce_softc *);
 311 static void bce_dump_mq_regs            (struct bce_softc *);
 312 static void bce_dump_bc_state           (struct bce_softc *);
 313 static void bce_dump_txp_state          (struct bce_softc *, int);
 314 static void bce_dump_rxp_state          (struct bce_softc *, int);
 315 static void bce_dump_tpat_state (struct bce_softc *, int);
 316 static void bce_dump_cp_state           (struct bce_softc *, int);
 317 static void bce_dump_com_state          (struct bce_softc *, int);
 318 static void bce_dump_rv2p_state (struct bce_softc *);
 319 static void bce_breakpoint                      (struct bce_softc *);
 320 #endif /*BCE_DEBUG */
 321
 322
 323 /****************************************************************************/
 324 /* BCE Register/Memory Access Routines                                      */
 325 /****************************************************************************/
 326 static u32  bce_reg_rd_ind              (struct bce_softc *, u32);
 327 static void bce_reg_wr_ind              (struct bce_softc *, u32, u32);
 328 static void bce_shmem_wr                (struct bce_softc *, u32, u32);
 329 static u32  bce_shmem_rd                (struct bce_softc *, u32);
 330 static void bce_ctx_wr                  (struct bce_softc *, u32, u32, u32);
 331 static int  bce_miibus_read_reg         (device_t, int, int);
 332 static int  bce_miibus_write_reg        (device_t, int, int, int);
 333 static void bce_miibus_statchg          (device_t);
 334
 335 #ifdef BCE_DEBUG
 336 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS);
 337 #ifdef BCE_NVRAM_WRITE_SUPPORT
 338 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS);
 339 #endif
 340 #endif
 341
 342 /****************************************************************************/
 343 /* BCE NVRAM Access Routines                                                */
 344 /****************************************************************************/
 345 static int  bce_acquire_nvram_lock      (struct bce_softc *);
 346 static int  bce_release_nvram_lock      (struct bce_softc *);
 347 static void bce_enable_nvram_access(struct bce_softc *);
 348 static void bce_disable_nvram_access(struct bce_softc *);
 349 static int  bce_nvram_read_dword        (struct bce_softc *, u32, u8 *, u32);
 350 static int  bce_init_nvram                      (struct bce_softc *);
 351 static int  bce_nvram_read                      (struct bce_softc *, u32, u8 *, int);
 352 static int  bce_nvram_test                      (struct bce_softc *);
 353 #ifdef BCE_NVRAM_WRITE_SUPPORT
 354 static int  bce_enable_nvram_write      (struct bce_softc *);
 355 static void bce_disable_nvram_write(struct bce_softc *);
 356 static int  bce_nvram_erase_page        (struct bce_softc *, u32);
 357 static int  bce_nvram_write_dword       (struct bce_softc *, u32, u8 *, u32);
 358 static int  bce_nvram_write             (struct bce_softc *, u32, u8 *, int);
 359 #endif
 360
 361 /****************************************************************************/
 362 /*                                                                          */
 363 /****************************************************************************/
 364 static void bce_get_rx_buffer_sizes(struct bce_softc *, int);
 365 static void bce_get_media                       (struct bce_softc *);
 366 static void bce_init_media                      (struct bce_softc *);
 367 static u32 bce_get_rphy_link            (struct bce_softc *);
 368 static void bce_dma_map_addr            (void *, bus_dma_segment_t *, int, int);
 369 static int  bce_dma_alloc                       (device_t);
 370 static void bce_dma_free                        (struct bce_softc *);
 371 static void bce_release_resources       (struct bce_softc *);
 372
 373 /****************************************************************************/
 374 /* BCE Firmware Synchronization and Load                                    */
 375 /****************************************************************************/
 376 static void bce_fw_cap_init                     (struct bce_softc *);
 377 static int  bce_fw_sync                 (struct bce_softc *, u32);
 378 static void bce_load_rv2p_fw            (struct bce_softc *, const u32 *, u32,
 379     u32);
 380 static void bce_load_cpu_fw             (struct bce_softc *,
 381     struct cpu_reg *, struct fw_info *);
 382 static void bce_start_cpu                       (struct bce_softc *, struct cpu_reg *);
 383 static void bce_halt_cpu                        (struct bce_softc *, struct cpu_reg *);
 384 static void bce_start_rxp_cpu           (struct bce_softc *);
 385 static void bce_init_rxp_cpu            (struct bce_softc *);
 386 static void bce_init_txp_cpu            (struct bce_softc *);
 387 static void bce_init_tpat_cpu           (struct bce_softc *);
 388 static void bce_init_cp_cpu             (struct bce_softc *);
 389 static void bce_init_com_cpu            (struct bce_softc *);
 390 static void bce_init_cpus                       (struct bce_softc *);
 391
 392 static void bce_print_adapter_info      (struct bce_softc *);
 393 static void bce_probe_pci_caps          (device_t, struct bce_softc *);
 394 static void bce_stop                            (struct bce_softc *);
 395 static int  bce_reset                           (struct bce_softc *, u32);
 396 static int  bce_chipinit                        (struct bce_softc *);
 397 static int  bce_blockinit                       (struct bce_softc *);
 398
 399 static int  bce_init_tx_chain           (struct bce_softc *);
 400 static void bce_free_tx_chain           (struct bce_softc *);
 401
 402 static int  bce_get_rx_buf              (struct bce_softc *, u16, u16, u32 *);
 403 static int  bce_init_rx_chain           (struct bce_softc *);
 404 static void bce_fill_rx_chain           (struct bce_softc *);
 405 static void bce_free_rx_chain           (struct bce_softc *);
 406
 407 static int  bce_get_pg_buf              (struct bce_softc *, u16, u16);
 408 static int  bce_init_pg_chain           (struct bce_softc *);
 409 static void bce_fill_pg_chain           (struct bce_softc *);
 410 static void bce_free_pg_chain           (struct bce_softc *);
 411
 412 static struct mbuf *bce_tso_setup       (struct bce_softc *,
 413     struct mbuf **, u16 *);
 414 static int  bce_tx_encap                        (struct bce_softc *, struct mbuf **);
 415 static void bce_start_locked            (struct ifnet *);
 416 static void bce_start                           (struct ifnet *);
 417 static int  bce_ioctl                           (struct ifnet *, u_long, caddr_t);
 418 static void bce_watchdog                        (struct bce_softc *);
 419 static int  bce_ifmedia_upd             (struct ifnet *);
 420 static int  bce_ifmedia_upd_locked      (struct ifnet *);
 421 static void bce_ifmedia_sts             (struct ifnet *, struct ifmediareq *);
 422 static void bce_ifmedia_sts_rphy        (struct bce_softc *, struct ifmediareq *);
 423 static void bce_init_locked             (struct bce_softc *);
 424 static void bce_init                            (void *);
 425 static void bce_mgmt_init_locked        (struct bce_softc *sc);
 426
 427 static int  bce_init_ctx                        (struct bce_softc *);
 428 static void bce_get_mac_addr            (struct bce_softc *);
 429 static void bce_set_mac_addr            (struct bce_softc *);
 430 static void bce_phy_intr                        (struct bce_softc *);
 431 static inline u16 bce_get_hw_rx_cons    (struct bce_softc *);
 432 static void bce_rx_intr                 (struct bce_softc *);
 433 static void bce_tx_intr                 (struct bce_softc *);
 434 static void bce_disable_intr            (struct bce_softc *);
 435 static void bce_enable_intr             (struct bce_softc *, int);
 436
 437 static void bce_intr                            (void *);
 438 static void bce_set_rx_mode             (struct bce_softc *);
 439 static void bce_stats_update            (struct bce_softc *);
 440 static void bce_tick                            (void *);
 441 static void bce_pulse                           (void *);
 442 static void bce_add_sysctls             (struct bce_softc *);
 443
 444
 445 /****************************************************************************/
 446 /* FreeBSD device dispatch table.                                           */
 447 /****************************************************************************/
 448 static device_method_t bce_methods[] = {
 449         /* Device interface (device_if.h) */
 450         DEVMETHOD(device_probe,         bce_probe),
 451         DEVMETHOD(device_attach,        bce_attach),
 452         DEVMETHOD(device_detach,        bce_detach),
 453         DEVMETHOD(device_shutdown,      bce_shutdown),
 454 /* Supported by device interface but not used here. */
 455 /*      DEVMETHOD(device_identify,      bce_identify),      */
 456 /*      DEVMETHOD(device_suspend,       bce_suspend),       */
 457 /*      DEVMETHOD(device_resume,        bce_resume),        */
 458 /*      DEVMETHOD(device_quiesce,       bce_quiesce),       */
 459
 460         /* MII interface (miibus_if.h) */
 461         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 462         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 463         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 464 /* Supported by MII interface but not used here.       */
 465 /*      DEVMETHOD(miibus_linkchg,       bce_miibus_linkchg),   */
 466 /*      DEVMETHOD(miibus_mediainit,     bce_miibus_mediainit), */
 467
 468         DEVMETHOD_END
 469 };
 470
 471 static driver_t bce_driver = {
 472         "bce",
 473         bce_methods,
 474         sizeof(struct bce_softc)
 475 };
 476
 477 static devclass_t bce_devclass;
 478
 479 MODULE_DEPEND(bce, pci, 1, 1, 1);
 480 MODULE_DEPEND(bce, ether, 1, 1, 1);
 481 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 482
 483 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, NULL, NULL);
 484 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, NULL, NULL);
 485
 486
 487 /****************************************************************************/
 488 /* Tunable device values                                                    */
 489 /****************************************************************************/
 490 static SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters");
 491
 492 /* Allowable values are TRUE or FALSE */
 493 static int bce_verbose = TRUE;
 494 TUNABLE_INT("hw.bce.verbose", &bce_verbose);
 495 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0,
 496     "Verbose output enable/disable");
 497
 498 /* Allowable values are TRUE or FALSE */
 499 static int bce_tso_enable = TRUE;
 500 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable);
 501 SYSCTL_INT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
 502     "TSO Enable/Disable");
 503
 504 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
 505 /* ToDo: Add MSI-X support. */
 506 static int bce_msi_enable = 1;
 507 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable);
 508 SYSCTL_INT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
 509     "MSI-X|MSI|INTx selector");
 510
 511 /* Allowable values are 1, 2, 4, 8. */
 512 static int bce_rx_pages = DEFAULT_RX_PAGES;
 513 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
 514 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0,
 515     "Receive buffer descriptor pages (1 page = 255 buffer descriptors)");
 516
 517 /* Allowable values are 1, 2, 4, 8. */
 518 static int bce_tx_pages = DEFAULT_TX_PAGES;
 519 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
 520 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0,
 521     "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)");
 522
 523 /* Allowable values are TRUE or FALSE. */
 524 static int bce_hdr_split = TRUE;
 525 TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split);
 526 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0,
 527     "Frame header/payload splitting Enable/Disable");
 528
 529 /* Allowable values are TRUE or FALSE. */
 530 static int bce_strict_rx_mtu = FALSE;
 531 TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu);
 532 SYSCTL_UINT(_hw_bce, OID_AUTO, loose_rx_mtu, CTLFLAG_RDTUN,
 533     &bce_strict_rx_mtu, 0,
 534     "Enable/Disable strict RX frame size checking");
 535
 536 /* Allowable values are 0 ... 100 */
 537 #ifdef BCE_DEBUG
 538 /* Generate 1 interrupt for every transmit completion. */
 539 static int bce_tx_quick_cons_trip_int = 1;
 540 #else
 541 /* Generate 1 interrupt for every 20 transmit completions. */
 542 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT;
 543 #endif
 544 TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int);
 545 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN,
 546     &bce_tx_quick_cons_trip_int, 0,
 547     "Transmit BD trip point during interrupts");
 548
 549 /* Allowable values are 0 ... 100 */
 550 /* Generate 1 interrupt for every transmit completion. */
 551 #ifdef BCE_DEBUG
 552 static int bce_tx_quick_cons_trip = 1;
 553 #else
 554 /* Generate 1 interrupt for every 20 transmit completions. */
 555 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
 556 #endif
 557 TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip);
 558 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN,
 559     &bce_tx_quick_cons_trip, 0,
 560     "Transmit BD trip point");
 561
 562 /* Allowable values are 0 ... 100 */
 563 #ifdef BCE_DEBUG
 564 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
 565 static int bce_tx_ticks_int = 0;
 566 #else
 567 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
 568 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT;
 569 #endif
 570 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 571 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN,
 572     &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt");
 573
 574 /* Allowable values are 0 ... 100 */
 575 #ifdef BCE_DEBUG
 576 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
 577 static int bce_tx_ticks = 0;
 578 #else
 579 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
 580 static int bce_tx_ticks = DEFAULT_TX_TICKS;
 581 #endif
 582 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 583 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN,
 584     &bce_tx_ticks, 0, "Transmit ticks count");
 585
 586 /* Allowable values are 1 ... 100 */
 587 #ifdef BCE_DEBUG
 588 /* Generate 1 interrupt for every received frame. */
 589 static int bce_rx_quick_cons_trip_int = 1;
 590 #else
 591 /* Generate 1 interrupt for every 6 received frames. */
 592 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT;
 593 #endif
 594 TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int);
 595 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN,
 596     &bce_rx_quick_cons_trip_int, 0,
 597     "Receive BD trip point duirng interrupts");
 598
 599 /* Allowable values are 1 ... 100 */
 600 #ifdef BCE_DEBUG
 601 /* Generate 1 interrupt for every received frame. */
 602 static int bce_rx_quick_cons_trip = 1;
 603 #else
 604 /* Generate 1 interrupt for every 6 received frames. */
 605 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
 606 #endif
 607 TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip);
 608 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN,
 609     &bce_rx_quick_cons_trip, 0,
 610     "Receive BD trip point");
 611
 612 /* Allowable values are 0 ... 100 */
 613 #ifdef BCE_DEBUG
 614 /* Generate an int. if 0us have elapsed since the last received frame. */
 615 static int bce_rx_ticks_int = 0;
 616 #else
 617 /* Generate an int. if 18us have elapsed since the last received frame. */
 618 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
 619 #endif
 620 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 621 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN,
 622     &bce_rx_ticks_int, 0, "Receive ticks count during interrupt");
 623
 624 /* Allowable values are 0 ... 100 */
 625 #ifdef BCE_DEBUG
 626 /* Generate an int. if 0us have elapsed since the last received frame. */
 627 static int bce_rx_ticks = 0;
 628 #else
 629 /* Generate an int. if 18us have elapsed since the last received frame. */
 630 static int bce_rx_ticks = DEFAULT_RX_TICKS;
 631 #endif
 632 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 633 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN,
 634     &bce_rx_ticks, 0, "Receive ticks count");
 635
 636
 637 /****************************************************************************/
 638 /* Device probe function.                                                   */
 639 /*                                                                          */
 640 /* Compares the device to the driver's list of supported devices and        */
 641 /* reports back to the OS whether this is the right driver for the device.  */
 642 /*                                                                          */
 643 /* Returns:                                                                 */
 644 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 645 /****************************************************************************/
 646 static int
 647 bce_probe(device_t dev)
 648 {
 649         const struct bce_type *t;
 650         struct bce_softc *sc;
 651         char *descbuf;
 652         u16 vid = 0, did = 0, svid = 0, sdid = 0;
 653
 654         t = bce_devs;
 655
 656         sc = device_get_softc(dev);
 657         sc->bce_unit = device_get_unit(dev);
 658         sc->bce_dev = dev;
 659
 660         /* Get the data for the device to be probed. */
 661         vid  = pci_get_vendor(dev);
 662         did  = pci_get_device(dev);
 663         svid = pci_get_subvendor(dev);
 664         sdid = pci_get_subdevice(dev);
 665
 666         DBPRINT(sc, BCE_EXTREME_LOAD,
 667             "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
 668             "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
 669
 670         /* Look through the list of known devices for a match. */
 671         while(t->bce_name != NULL) {
 672
 673                 if ((vid == t->bce_vid) && (did == t->bce_did) &&
 674                     ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
 675                     ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
 676
 677                         descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
 678
 679                         if (descbuf == NULL)
 680                                 return(ENOMEM);
 681
 682                         /* Print out the device identity. */
 683                         snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 684                             t->bce_name, (((pci_read_config(dev,
 685                             PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
 686                             (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
 687
 688                         device_set_desc_copy(dev, descbuf);
 689                         free(descbuf, M_TEMP);
 690                         return(BUS_PROBE_DEFAULT);
 691                 }
 692                 t++;
 693         }
 694
 695         return(ENXIO);
 696 }
 697
 698
 699 /****************************************************************************/
 700 /* PCI Capabilities Probe Function.                                         */
 701 /*                                                                          */
 702 /* Walks the PCI capabiites list for the device to find what features are   */
 703 /* supported.                                                               */
 704 /*                                                                          */
 705 /* Returns:                                                                 */
 706 /*   None.                                                                  */
 707 /****************************************************************************/
 708 static void
 709 bce_print_adapter_info(struct bce_softc *sc)
 710 {
 711         int i = 0;
 712
 713         DBENTER(BCE_VERBOSE_LOAD);
 714
 715         if (bce_verbose || bootverbose) {
 716                 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
 717                 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >>
 718                     12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 719
 720
 721                 /* Bus info. */
 722                 if (sc->bce_flags & BCE_PCIE_FLAG) {
 723                         printf("Bus (PCIe x%d, ", sc->link_width);
 724                         switch (sc->link_speed) {
 725                         case 1: printf("2.5Gbps); "); break;
 726                         case 2: printf("5Gbps); "); break;
 727                         default: printf("Unknown link speed); ");
 728                         }
 729                 } else {
 730                         printf("Bus (PCI%s, %s, %dMHz); ",
 731                             ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 732                             ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
 733                             "32-bit" : "64-bit"), sc->bus_speed_mhz);
 734                 }
 735
 736                 /* Firmware version and device features. */
 737                 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (",
 738                     sc->bce_bc_ver,     sc->rx_pages, sc->tx_pages,
 739                     (bce_hdr_split == TRUE ? sc->pg_pages: 0));
 740
 741                 if (bce_hdr_split == TRUE) {
 742                         printf("SPLT");
 743                         i++;
 744                 }
 745
 746                 if (sc->bce_flags & BCE_USING_MSI_FLAG) {
 747                         if (i > 0) printf("|");
 748                         printf("MSI"); i++;
 749                 }
 750
 751                 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
 752                         if (i > 0) printf("|");
 753                         printf("MSI-X"); i++;
 754                 }
 755
 756                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
 757                         if (i > 0) printf("|");
 758                         printf("2.5G"); i++;
 759                 }
 760
 761                 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) {
 762                         if (i > 0) printf("|");
 763                         printf("Remote PHY(%s)",
 764                             sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ?
 765                             "FIBER" : "TP"); i++;
 766                 }
 767
 768                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
 769                         if (i > 0) printf("|");
 770                         printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
 771                 } else {
 772                         printf(")\n");
 773                 }
 774
 775                 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n",
 776                     sc->bce_rx_quick_cons_trip_int,
 777                     sc->bce_rx_quick_cons_trip,
 778                     sc->bce_rx_ticks_int,
 779                     sc->bce_rx_ticks,
 780                     sc->bce_tx_quick_cons_trip_int,
 781                     sc->bce_tx_quick_cons_trip,
 782                     sc->bce_tx_ticks_int,
 783                     sc->bce_tx_ticks);
 784
 785         }
 786
 787         DBEXIT(BCE_VERBOSE_LOAD);
 788 }
 789
 790
 791 /****************************************************************************/
 792 /* PCI Capabilities Probe Function.                                         */
 793 /*                                                                          */
 794 /* Walks the PCI capabiites list for the device to find what features are   */
 795 /* supported.                                                               */
 796 /*                                                                          */
 797 /* Returns:                                                                 */
 798 /*   None.                                                                  */
 799 /****************************************************************************/
 800 static void
 801 bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
 802 {
 803         u32 reg;
 804
 805         DBENTER(BCE_VERBOSE_LOAD);
 806
 807         /* Check if PCI-X capability is enabled. */
 808         if (pci_find_cap(dev, PCIY_PCIX, &reg) == 0) {
 809                 if (reg != 0)
 810                         sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 811         }
 812
 813         /* Check if PCIe capability is enabled. */
 814         if (pci_find_cap(dev, PCIY_EXPRESS, &reg) == 0) {
 815                 if (reg != 0) {
 816                         u16 link_status = pci_read_config(dev, reg + 0x12, 2);
 817                         DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = "
 818                             "0x%08X\n", link_status);
 819                         sc->link_speed = link_status & 0xf;
 820                         sc->link_width = (link_status >> 4) & 0x3f;
 821                         sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 822                         sc->bce_flags |= BCE_PCIE_FLAG;
 823                 }
 824         }
 825
 826         /* Check if MSI capability is enabled. */
 827         if (pci_find_cap(dev, PCIY_MSI, &reg) == 0) {
 828                 if (reg != 0)
 829                         sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
 830         }
 831
 832         /* Check if MSI-X capability is enabled. */
 833         if (pci_find_cap(dev, PCIY_MSIX, &reg) == 0) {
 834                 if (reg != 0)
 835                         sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
 836         }
 837
 838         DBEXIT(BCE_VERBOSE_LOAD);
 839 }
 840
 841
 842 /****************************************************************************/
 843 /* Load and validate user tunable settings.                                 */
 844 /*                                                                          */
 845 /* Returns:                                                                 */
 846 /*   Nothing.                                                               */
 847 /****************************************************************************/
 848 static void
 849 bce_set_tunables(struct bce_softc *sc)
 850 {
 851         /* Set sysctl values for RX page count. */
 852         switch (bce_rx_pages) {
 853         case 1:
 854                 /* fall-through */
 855         case 2:
 856                 /* fall-through */
 857         case 4:
 858                 /* fall-through */
 859         case 8:
 860                 sc->rx_pages = bce_rx_pages;
 861                 break;
 862         default:
 863                 sc->rx_pages = DEFAULT_RX_PAGES;
 864                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 865                     "hw.bce.rx_pages!  Setting default of %d.\n",
 866                     __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES);
 867         }
 868
 869         /* ToDo: Consider allowing user setting for pg_pages. */
 870         sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES);
 871
 872         /* Set sysctl values for TX page count. */
 873         switch (bce_tx_pages) {
 874         case 1:
 875                 /* fall-through */
 876         case 2:
 877                 /* fall-through */
 878         case 4:
 879                 /* fall-through */
 880         case 8:
 881                 sc->tx_pages = bce_tx_pages;
 882                 break;
 883         default:
 884                 sc->tx_pages = DEFAULT_TX_PAGES;
 885                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 886                     "hw.bce.tx_pages!  Setting default of %d.\n",
 887                     __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES);
 888         }
 889
 890         /*
 891          * Validate the TX trip point (i.e. the number of
 892          * TX completions before a status block update is
 893          * generated and an interrupt is asserted.
 894          */
 895         if (bce_tx_quick_cons_trip_int <= 100) {
 896                 sc->bce_tx_quick_cons_trip_int =
 897                     bce_tx_quick_cons_trip_int;
 898         } else {
 899                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 900                     "hw.bce.tx_quick_cons_trip_int!  Setting default of %d.\n",
 901                     __FILE__, __LINE__, bce_tx_quick_cons_trip_int,
 902                     DEFAULT_TX_QUICK_CONS_TRIP_INT);
 903                 sc->bce_tx_quick_cons_trip_int =
 904                     DEFAULT_TX_QUICK_CONS_TRIP_INT;
 905         }
 906
 907         if (bce_tx_quick_cons_trip <= 100) {
 908                 sc->bce_tx_quick_cons_trip =
 909                     bce_tx_quick_cons_trip;
 910         } else {
 911                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 912                     "hw.bce.tx_quick_cons_trip!  Setting default of %d.\n",
 913                     __FILE__, __LINE__, bce_tx_quick_cons_trip,
 914                     DEFAULT_TX_QUICK_CONS_TRIP);
 915                 sc->bce_tx_quick_cons_trip =
 916                     DEFAULT_TX_QUICK_CONS_TRIP;
 917         }
 918
 919         /*
 920          * Validate the TX ticks count (i.e. the maximum amount
 921          * of time to wait after the last TX completion has
 922          * occurred before a status block update is generated
 923          * and an interrupt is asserted.
 924          */
 925         if (bce_tx_ticks_int <= 100) {
 926                 sc->bce_tx_ticks_int =
 927                     bce_tx_ticks_int;
 928         } else {
 929                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 930                     "hw.bce.tx_ticks_int!  Setting default of %d.\n",
 931                     __FILE__, __LINE__, bce_tx_ticks_int,
 932                     DEFAULT_TX_TICKS_INT);
 933                 sc->bce_tx_ticks_int =
 934                     DEFAULT_TX_TICKS_INT;
 935            }
 936
 937         if (bce_tx_ticks <= 100) {
 938                 sc->bce_tx_ticks =
 939                     bce_tx_ticks;
 940         } else {
 941                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 942                     "hw.bce.tx_ticks!  Setting default of %d.\n",
 943                     __FILE__, __LINE__, bce_tx_ticks,
 944                     DEFAULT_TX_TICKS);
 945                 sc->bce_tx_ticks =
 946                     DEFAULT_TX_TICKS;
 947         }
 948
 949         /*
 950          * Validate the RX trip point (i.e. the number of
 951          * RX frames received before a status block update is
 952          * generated and an interrupt is asserted.
 953          */
 954         if (bce_rx_quick_cons_trip_int <= 100) {
 955                 sc->bce_rx_quick_cons_trip_int =
 956                     bce_rx_quick_cons_trip_int;
 957         } else {
 958                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 959                     "hw.bce.rx_quick_cons_trip_int!  Setting default of %d.\n",
 960                     __FILE__, __LINE__, bce_rx_quick_cons_trip_int,
 961                     DEFAULT_RX_QUICK_CONS_TRIP_INT);
 962                 sc->bce_rx_quick_cons_trip_int =
 963                     DEFAULT_RX_QUICK_CONS_TRIP_INT;
 964         }
 965
 966         if (bce_rx_quick_cons_trip <= 100) {
 967                 sc->bce_rx_quick_cons_trip =
 968                     bce_rx_quick_cons_trip;
 969         } else {
 970                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 971                     "hw.bce.rx_quick_cons_trip!  Setting default of %d.\n",
 972                     __FILE__, __LINE__, bce_rx_quick_cons_trip,
 973                     DEFAULT_RX_QUICK_CONS_TRIP);
 974                 sc->bce_rx_quick_cons_trip =
 975                     DEFAULT_RX_QUICK_CONS_TRIP;
 976         }
 977
 978         /*
 979          * Validate the RX ticks count (i.e. the maximum amount
 980          * of time to wait after the last RX frame has been
 981          * received before a status block update is generated
 982          * and an interrupt is asserted.
 983          */
 984         if (bce_rx_ticks_int <= 100) {
 985                 sc->bce_rx_ticks_int = bce_rx_ticks_int;
 986         } else {
 987                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 988                     "hw.bce.rx_ticks_int!  Setting default of %d.\n",
 989                     __FILE__, __LINE__, bce_rx_ticks_int,
 990                     DEFAULT_RX_TICKS_INT);
 991                 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
 992         }
 993
 994         if (bce_rx_ticks <= 100) {
 995                 sc->bce_rx_ticks = bce_rx_ticks;
 996         } else {
 997                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 998                     "hw.bce.rx_ticks!  Setting default of %d.\n",
 999                     __FILE__, __LINE__, bce_rx_ticks,
1000                     DEFAULT_RX_TICKS);
1001                 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1002         }
1003
1004         /* Disabling both RX ticks and RX trips will prevent interrupts. */
1005         if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) {
1006                 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and "
1007                     "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n",
1008                    __FILE__, __LINE__);
1009                 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1010                 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
1011         }
1012
1013         /* Disabling both TX ticks and TX trips will prevent interrupts. */
1014         if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) {
1015                 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and "
1016                     "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n",
1017                    __FILE__, __LINE__);
1018                 sc->bce_tx_ticks = DEFAULT_TX_TICKS;
1019                 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
1020         }
1021 }
1022
1023
1024 /****************************************************************************/
1025 /* Device attach function.                                                  */
1026 /*                                                                          */
1027 /* Allocates device resources, performs secondary chip identification,      */
1028 /* resets and initializes the hardware, and initializes driver instance     */
1029 /* variables.                                                               */
1030 /*                                                                          */
1031 /* Returns:                                                                 */
1032 /*   0 on success, positive value on failure.                               */
1033 /****************************************************************************/
1034 static int
1035 bce_attach(device_t dev)
1036 {
1037         struct bce_softc *sc;
1038         struct ifnet *ifp;
1039         u32 val;
1040         int count, error, rc = 0, rid;
1041
1042         sc = device_get_softc(dev);
1043         sc->bce_dev = dev;
1044
1045         DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1046
1047         sc->bce_unit = device_get_unit(dev);
1048
1049         /* Set initial device and PHY flags */
1050         sc->bce_flags = 0;
1051         sc->bce_phy_flags = 0;
1052
1053         bce_set_tunables(sc);
1054
1055         pci_enable_busmaster(dev);
1056
1057         /* Allocate PCI memory resources. */
1058         rid = PCIR_BAR(0);
1059         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1060                 &rid, RF_ACTIVE);
1061
1062         if (sc->bce_res_mem == NULL) {
1063                 BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
1064                     __FILE__, __LINE__);
1065                 rc = ENXIO;
1066                 goto bce_attach_fail;
1067         }
1068
1069         /* Get various resource handles. */
1070         sc->bce_btag    = rman_get_bustag(sc->bce_res_mem);
1071         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
1072         sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
1073
1074         bce_probe_pci_caps(dev, sc);
1075
1076         rid = 1;
1077         count = 0;
1078 #if 0
1079         /* Try allocating MSI-X interrupts. */
1080         if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
1081                 (bce_msi_enable >= 2) &&
1082                 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1083                 &rid, RF_ACTIVE)) != NULL)) {
1084
1085                 msi_needed = count = 1;
1086
1087                 if (((error = pci_alloc_msix(dev, &count)) != 0) ||
1088                         (count != msi_needed)) {
1089                         BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
1090                                 "Received = %d, error = %d\n", __FILE__, __LINE__,
1091                                 msi_needed, count, error);
1092                         count = 0;
1093                         pci_release_msi(dev);
1094                         bus_release_resource(dev, SYS_RES_MEMORY, rid,
1095                                 sc->bce_res_irq);
1096                         sc->bce_res_irq = NULL;
1097                 } else {
1098                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
1099                                 __FUNCTION__);
1100                         sc->bce_flags |= BCE_USING_MSIX_FLAG;
1101                 }
1102         }
1103 #endif
1104
1105         /* Try allocating a MSI interrupt. */
1106         if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
1107                 (bce_msi_enable >= 1) && (count == 0)) {
1108                 count = 1;
1109                 if ((error = pci_alloc_msi(dev, &count)) != 0) {
1110                         BCE_PRINTF("%s(%d): MSI allocation failed! "
1111                             "error = %d\n", __FILE__, __LINE__, error);
1112                         count = 0;
1113                         pci_release_msi(dev);
1114                 } else {
1115                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI "
1116                             "interrupt.\n", __FUNCTION__);
1117                         sc->bce_flags |= BCE_USING_MSI_FLAG;
1118                         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
1119                                 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
1120                         rid = 1;
1121                 }
1122         }
1123
1124         /* Try allocating a legacy interrupt. */
1125         if (count == 0) {
1126                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
1127                         __FUNCTION__);
1128                 rid = 0;
1129         }
1130
1131         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1132             &rid, RF_ACTIVE | (count != 0 ? 0 : RF_SHAREABLE));
1133
1134         /* Report any IRQ allocation errors. */
1135         if (sc->bce_res_irq == NULL) {
1136                 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
1137                     __FILE__, __LINE__);
1138                 rc = ENXIO;
1139                 goto bce_attach_fail;
1140         }
1141
1142         /* Initialize mutex for the current device instance. */
1143         BCE_LOCK_INIT(sc, device_get_nameunit(dev));
1144
1145         /*
1146          * Configure byte swap and enable indirect register access.
1147          * Rely on CPU to do target byte swapping on big endian systems.
1148          * Access to registers outside of PCI configurtion space are not
1149          * valid until this is done.
1150          */
1151         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
1152             BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
1153             BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
1154
1155         /* Save ASIC revsion info. */
1156         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
1157
1158         /* Weed out any non-production controller revisions. */
1159         switch(BCE_CHIP_ID(sc)) {
1160         case BCE_CHIP_ID_5706_A0:
1161         case BCE_CHIP_ID_5706_A1:
1162         case BCE_CHIP_ID_5708_A0:
1163         case BCE_CHIP_ID_5708_B0:
1164         case BCE_CHIP_ID_5709_A0:
1165         case BCE_CHIP_ID_5709_B0:
1166         case BCE_CHIP_ID_5709_B1:
1167         case BCE_CHIP_ID_5709_B2:
1168                 BCE_PRINTF("%s(%d): Unsupported controller "
1169                     "revision (%c%d)!\n", __FILE__, __LINE__,
1170                     (((pci_read_config(dev, PCIR_REVID, 4) &
1171                     0xf0) >> 4) + 'A'), (pci_read_config(dev,
1172                     PCIR_REVID, 4) & 0xf));
1173                 rc = ENODEV;
1174                 goto bce_attach_fail;
1175         }
1176
1177         /*
1178          * The embedded PCIe to PCI-X bridge (EPB)
1179          * in the 5708 cannot address memory above
1180          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
1181          */
1182         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
1183                 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
1184         else
1185                 sc->max_bus_addr = BUS_SPACE_MAXADDR;
1186
1187         /*
1188          * Find the base address for shared memory access.
1189          * Newer versions of bootcode use a signature and offset
1190          * while older versions use a fixed address.
1191          */
1192         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
1193         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
1194                 /* Multi-port devices use different offsets in shared memory. */
1195                 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
1196                     (pci_get_function(sc->bce_dev) << 2));
1197         else
1198                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
1199
1200         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
1201             __FUNCTION__, sc->bce_shmem_base);
1202
1203         /* Fetch the bootcode revision. */
1204         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
1205         for (int i = 0, j = 0; i < 3; i++) {
1206                 u8 num;
1207
1208                 num = (u8) (val >> (24 - (i * 8)));
1209                 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
1210                         if (num >= k || !skip0 || k == 1) {
1211                                 sc->bce_bc_ver[j++] = (num / k) + '0';
1212                                 skip0 = 0;
1213                         }
1214                 }
1215
1216                 if (i != 2)
1217                         sc->bce_bc_ver[j++] = '.';
1218         }
1219
1220         /* Check if any management firwmare is enabled. */
1221         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
1222         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
1223                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
1224
1225                 /* Allow time for firmware to enter the running state. */
1226                 for (int i = 0; i < 30; i++) {
1227                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1228                         if (val & BCE_CONDITION_MFW_RUN_MASK)
1229                                 break;
1230                         DELAY(10000);
1231                 }
1232
1233                 /* Check if management firmware is running. */
1234                 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1235                 val &= BCE_CONDITION_MFW_RUN_MASK;
1236                 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) &&
1237                     (val != BCE_CONDITION_MFW_RUN_NONE)) {
1238                         u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
1239                         int i = 0;
1240
1241                         /* Read the management firmware version string. */
1242                         for (int j = 0; j < 3; j++) {
1243                                 val = bce_reg_rd_ind(sc, addr + j * 4);
1244                                 val = bswap32(val);
1245                                 memcpy(&sc->bce_mfw_ver[i], &val, 4);
1246                                 i += 4;
1247                         }
1248                 } else {
1249                         /* May cause firmware synchronization timeouts. */
1250                         BCE_PRINTF("%s(%d): Management firmware enabled "
1251                             "but not running!\n", __FILE__, __LINE__);
1252                         strcpy(sc->bce_mfw_ver, "NOT RUNNING!");
1253
1254                         /* ToDo: Any action the driver should take? */
1255                 }
1256         }
1257
1258         /* Get PCI bus information (speed and type). */
1259         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
1260         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
1261                 u32 clkreg;
1262
1263                 sc->bce_flags |= BCE_PCIX_FLAG;
1264
1265                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);
1266
1267                 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
1268                 switch (clkreg) {
1269                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
1270                         sc->bus_speed_mhz = 133;
1271                         break;
1272
1273                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
1274                         sc->bus_speed_mhz = 100;
1275                         break;
1276
1277                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
1278                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
1279                         sc->bus_speed_mhz = 66;
1280                         break;
1281
1282                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
1283                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
1284                         sc->bus_speed_mhz = 50;
1285                         break;
1286
1287                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
1288                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
1289                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
1290                         sc->bus_speed_mhz = 33;
1291                         break;
1292                 }
1293         } else {
1294                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
1295                         sc->bus_speed_mhz = 66;
1296                 else
1297                         sc->bus_speed_mhz = 33;
1298         }
1299
1300         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
1301                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
1302
1303         /* Find the media type for the adapter. */
1304         bce_get_media(sc);
1305
1306         /* Reset controller and announce to bootcode that driver is present. */
1307         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
1308                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
1309                     __FILE__, __LINE__);
1310                 rc = ENXIO;
1311                 goto bce_attach_fail;
1312         }
1313
1314         /* Initialize the controller. */
1315         if (bce_chipinit(sc)) {
1316                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
1317                     __FILE__, __LINE__);
1318                 rc = ENXIO;
1319                 goto bce_attach_fail;
1320         }
1321
1322         /* Perform NVRAM test. */
1323         if (bce_nvram_test(sc)) {
1324                 BCE_PRINTF("%s(%d): NVRAM test failed!\n",
1325                     __FILE__, __LINE__);
1326                 rc = ENXIO;
1327                 goto bce_attach_fail;
1328         }
1329
1330         /* Fetch the permanent Ethernet MAC address. */
1331         bce_get_mac_addr(sc);
1332
1333         /* Update statistics once every second. */
1334         sc->bce_stats_ticks = 1000000 & 0xffff00;
1335
1336         /* Store data needed by PHY driver for backplane applications */
1337         sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1338         sc->bce_port_hw_cfg   = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1339
1340         /* Allocate DMA memory resources. */
1341         if (bce_dma_alloc(dev)) {
1342                 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
1343                     __FILE__, __LINE__);
1344                 rc = ENXIO;
1345                 goto bce_attach_fail;
1346         }
1347
1348         /* Allocate an ifnet structure. */
1349         ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
1350         if (ifp == NULL) {
1351                 BCE_PRINTF("%s(%d): Interface allocation failed!\n",
1352                     __FILE__, __LINE__);
1353                 rc = ENXIO;
1354                 goto bce_attach_fail;
1355         }
1356
1357         /* Initialize the ifnet interface. */
1358         ifp->if_softc   = sc;
1359         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1360         ifp->if_flags   = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1361         ifp->if_ioctl   = bce_ioctl;
1362         ifp->if_start   = bce_start;
1363         ifp->if_init    = bce_init;
1364         ifp->if_mtu     = ETHERMTU;
1365
1366         if (bce_tso_enable) {
1367                 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO;
1368                 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 |
1369                     IFCAP_VLAN_HWTSO;
1370         } else {
1371                 ifp->if_hwassist = BCE_IF_HWASSIST;
1372                 ifp->if_capabilities = BCE_IF_CAPABILITIES;
1373         }
1374
1375 #if __FreeBSD_version >= 800505
1376         /*
1377          * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version
1378          * so it's approximate value.
1379          */
1380         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1381                 ifp->if_capabilities |= IFCAP_LINKSTATE;
1382 #endif
1383
1384         ifp->if_capenable = ifp->if_capabilities;
1385
1386         /*
1387          * Assume standard mbuf sizes for buffer allocation.
1388          * This may change later if the MTU size is set to
1389          * something other than 1500.
1390          */
1391         bce_get_rx_buffer_sizes(sc,
1392             (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN));
1393
1394         /* Recalculate our buffer allocation sizes. */
1395         ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC;
1396         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1397         IFQ_SET_READY(&ifp->if_snd);
1398
1399         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1400                 ifp->if_baudrate = IF_Mbps(2500ULL);
1401         else
1402                 ifp->if_baudrate = IF_Mbps(1000);
1403
1404         /* Handle any special PHY initialization for SerDes PHYs. */
1405         bce_init_media(sc);
1406
1407         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
1408                 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd,
1409                     bce_ifmedia_sts);
1410                 /*
1411                  * We can't manually override remote PHY's link and assume
1412                  * PHY port configuration(Fiber or TP) is not changed after
1413                  * device attach.  This may not be correct though.
1414                  */
1415                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) {
1416                         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
1417                                 ifmedia_add(&sc->bce_ifmedia,
1418                                     IFM_ETHER | IFM_2500_SX, 0, NULL);
1419                                 ifmedia_add(&sc->bce_ifmedia,
1420                                     IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL);
1421                         }
1422                         ifmedia_add(&sc->bce_ifmedia,
1423                             IFM_ETHER | IFM_1000_SX, 0, NULL);
1424                         ifmedia_add(&sc->bce_ifmedia,
1425                             IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL);
1426                 } else {
1427                         ifmedia_add(&sc->bce_ifmedia,
1428                             IFM_ETHER | IFM_10_T, 0, NULL);
1429                         ifmedia_add(&sc->bce_ifmedia,
1430                             IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1431                         ifmedia_add(&sc->bce_ifmedia,
1432                             IFM_ETHER | IFM_100_TX, 0, NULL);
1433                         ifmedia_add(&sc->bce_ifmedia,
1434                             IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1435                         ifmedia_add(&sc->bce_ifmedia,
1436                             IFM_ETHER | IFM_1000_T, 0, NULL);
1437                         ifmedia_add(&sc->bce_ifmedia,
1438                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1439                 }
1440                 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1441                 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO);
1442                 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media;
1443         } else {
1444                 /* MII child bus by attaching the PHY. */
1445                 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd,
1446                     bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr,
1447                     MII_OFFSET_ANY, MIIF_DOPAUSE);
1448                 if (rc != 0) {
1449                         BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__,
1450                             __LINE__);
1451                         goto bce_attach_fail;
1452                 }
1453         }
1454
1455         /* Attach to the Ethernet interface list. */
1456         ether_ifattach(ifp, sc->eaddr);
1457
1458 #if __FreeBSD_version < 500000
1459         callout_init(&sc->bce_tick_callout);
1460         callout_init(&sc->bce_pulse_callout);
1461 #else
1462         callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1463         callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1464 #endif
1465
1466         /* Hookup IRQ last. */
1467         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1468                 NULL, bce_intr, sc, &sc->bce_intrhand);
1469
1470         if (rc) {
1471                 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
1472                     __FILE__, __LINE__);
1473                 bce_detach(dev);
1474                 goto bce_attach_exit;
1475         }
1476
1477         /*
1478          * At this point we've acquired all the resources
1479          * we need to run so there's no turning back, we're
1480          * cleared for launch.
1481          */
1482
1483         /* Print some important debugging info. */
1484         DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
1485
1486         /* Add the supported sysctls to the kernel. */
1487         bce_add_sysctls(sc);
1488
1489         BCE_LOCK(sc);
1490
1491         /*
1492          * The chip reset earlier notified the bootcode that
1493          * a driver is present.  We now need to start our pulse
1494          * routine so that the bootcode is reminded that we're
1495          * still running.
1496          */
1497         bce_pulse(sc);
1498
1499         bce_mgmt_init_locked(sc);
1500         BCE_UNLOCK(sc);
1501
1502         /* Finally, print some useful adapter info */
1503         bce_print_adapter_info(sc);
1504         DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
1505                 __FUNCTION__, sc);
1506
1507         goto bce_attach_exit;
1508
1509 bce_attach_fail:
1510         bce_release_resources(sc);
1511
1512 bce_attach_exit:
1513
1514         DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1515
1516         return(rc);
1517 }
1518
1519
1520 /****************************************************************************/
1521 /* Device detach function.                                                  */
1522 /*                                                                          */
1523 /* Stops the controller, resets the controller, and releases resources.     */
1524 /*                                                                          */
1525 /* Returns:                                                                 */
1526 /*   0 on success, positive value on failure.                               */
1527 /****************************************************************************/
1528 static int
1529 bce_detach(device_t dev)
1530 {
1531         struct bce_softc *sc = device_get_softc(dev);
1532         struct ifnet *ifp;
1533         u32 msg;
1534
1535         DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1536
1537         ifp = sc->bce_ifp;
1538
1539         /* Stop and reset the controller. */
1540         BCE_LOCK(sc);
1541
1542         /* Stop the pulse so the bootcode can go to driver absent state. */
1543         callout_stop(&sc->bce_pulse_callout);
1544
1545         bce_stop(sc);
1546         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1547                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1548         else
1549                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1550         bce_reset(sc, msg);
1551
1552         BCE_UNLOCK(sc);
1553
1554         ether_ifdetach(ifp);
1555
1556         /* If we have a child device on the MII bus remove it too. */
1557         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1558                 ifmedia_removeall(&sc->bce_ifmedia);
1559         else {
1560                 bus_generic_detach(dev);
1561                 device_delete_child(dev, sc->bce_miibus);
1562         }
1563
1564         /* Release all remaining resources. */
1565         bce_release_resources(sc);
1566
1567         DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1568
1569         return(0);
1570 }
1571
1572
1573 /****************************************************************************/
1574 /* Device shutdown function.                                                */
1575 /*                                                                          */
1576 /* Stops and resets the controller.                                         */
1577 /*                                                                          */
1578 /* Returns:                                                                 */
1579 /*   0 on success, positive value on failure.                               */
1580 /****************************************************************************/
1581 static int
1582 bce_shutdown(device_t dev)
1583 {
1584         struct bce_softc *sc = device_get_softc(dev);
1585         u32 msg;
1586
1587         DBENTER(BCE_VERBOSE);
1588
1589         BCE_LOCK(sc);
1590         bce_stop(sc);
1591         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1592                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1593         else
1594                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1595         bce_reset(sc, msg);
1596         BCE_UNLOCK(sc);
1597
1598         DBEXIT(BCE_VERBOSE);
1599
1600         return (0);
1601 }
1602
1603
1604 #ifdef BCE_DEBUG
1605 /****************************************************************************/
1606 /* Register read.                                                           */
1607 /*                                                                          */
1608 /* Returns:                                                                 */
1609 /*   The value of the register.                                             */
1610 /****************************************************************************/
1611 static u32
1612 bce_reg_rd(struct bce_softc *sc, u32 offset)
1613 {
1614         u32 val = REG_RD(sc, offset);
1615         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1616                 __FUNCTION__, offset, val);
1617         return val;
1618 }
1619
1620
1621 /****************************************************************************/
1622 /* Register write (16 bit).                                                 */
1623 /*                                                                          */
1624 /* Returns:                                                                 */
1625 /*   Nothing.                                                               */
1626 /****************************************************************************/
1627 static void
1628 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1629 {
1630         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1631                 __FUNCTION__, offset, val);
1632         REG_WR16(sc, offset, val);
1633 }
1634
1635
1636 /****************************************************************************/
1637 /* Register write.                                                          */
1638 /*                                                                          */
1639 /* Returns:                                                                 */
1640 /*   Nothing.                                                               */
1641 /****************************************************************************/
1642 static void
1643 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1644 {
1645         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1646                 __FUNCTION__, offset, val);
1647         REG_WR(sc, offset, val);
1648 }
1649 #endif
1650
1651 /****************************************************************************/
1652 /* Indirect register read.                                                  */
1653 /*                                                                          */
1654 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1655 /* configuration space.  Using this mechanism avoids issues with posted     */
1656 /* reads but is much slower than memory-mapped I/O.                         */
1657 /*                                                                          */
1658 /* Returns:                                                                 */
1659 /*   The value of the register.                                             */
1660 /****************************************************************************/
1661 static u32
1662 bce_reg_rd_ind(struct bce_softc *sc, u32 offset)
1663 {
1664         device_t dev;
1665         dev = sc->bce_dev;
1666
1667         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1668 #ifdef BCE_DEBUG
1669         {
1670                 u32 val;
1671                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1672                 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1673                         __FUNCTION__, offset, val);
1674                 return val;
1675         }
1676 #else
1677         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1678 #endif
1679 }
1680
1681
1682 /****************************************************************************/
1683 /* Indirect register write.                                                 */
1684 /*                                                                          */
1685 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1686 /* configuration space.  Using this mechanism avoids issues with posted     */
1687 /* writes but is muchh slower than memory-mapped I/O.                       */
1688 /*                                                                          */
1689 /* Returns:                                                                 */
1690 /*   Nothing.                                                               */
1691 /****************************************************************************/
1692 static void
1693 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1694 {
1695         device_t dev;
1696         dev = sc->bce_dev;
1697
1698         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1699                 __FUNCTION__, offset, val);
1700
1701         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1702         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1703 }
1704
1705
1706 /****************************************************************************/
1707 /* Shared memory write.                                                     */
1708 /*                                                                          */
1709 /* Writes NetXtreme II shared memory region.                                */
1710 /*                                                                          */
1711 /* Returns:                                                                 */
1712 /*   Nothing.                                                               */
1713 /****************************************************************************/
1714 static void
1715 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val)
1716 {
1717         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X  to  "
1718             "0x%08X\n", __FUNCTION__, val, offset);
1719
1720         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1721 }
1722
1723
1724 /****************************************************************************/
1725 /* Shared memory read.                                                      */
1726 /*                                                                          */
1727 /* Reads NetXtreme II shared memory region.                                 */
1728 /*                                                                          */
1729 /* Returns:                                                                 */
1730 /*   The 32 bit value read.                                                 */
1731 /****************************************************************************/
1732 static u32
1733 bce_shmem_rd(struct bce_softc *sc, u32 offset)
1734 {
1735         u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1736
1737         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from "
1738             "0x%08X\n", __FUNCTION__, val, offset);
1739
1740         return val;
1741 }
1742
1743
1744 #ifdef BCE_DEBUG
1745 /****************************************************************************/
1746 /* Context memory read.                                                     */
1747 /*                                                                          */
1748 /* The NetXtreme II controller uses context memory to track connection      */
1749 /* information for L2 and higher network protocols.                         */
1750 /*                                                                          */
1751 /* Returns:                                                                 */
1752 /*   The requested 32 bit value of context memory.                          */
1753 /****************************************************************************/
1754 static u32
1755 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset)
1756 {
1757         u32 idx, offset, retry_cnt = 5, val;
1758
1759         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 ||
1760             cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID "
1761             "address: 0x%08X.\n", __FUNCTION__, cid_addr));
1762
1763         offset = ctx_offset + cid_addr;
1764
1765         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1766
1767                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1768
1769                 for (idx = 0; idx < retry_cnt; idx++) {
1770                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1771                         if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1772                                 break;
1773                         DELAY(5);
1774                 }
1775
1776                 if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1777                         BCE_PRINTF("%s(%d); Unable to read CTX memory: "
1778                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1779                             __FILE__, __LINE__, cid_addr, ctx_offset);
1780
1781                 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1782         } else {
1783                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1784                 val = REG_RD(sc, BCE_CTX_DATA);
1785         }
1786
1787         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1788                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1789
1790         return(val);
1791 }
1792 #endif
1793
1794
1795 /****************************************************************************/
1796 /* Context memory write.                                                    */
1797 /*                                                                          */
1798 /* The NetXtreme II controller uses context memory to track connection      */
1799 /* information for L2 and higher network protocols.                         */
1800 /*                                                                          */
1801 /* Returns:                                                                 */
1802 /*   Nothing.                                                               */
1803 /****************************************************************************/
1804 static void
1805 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val)
1806 {
1807         u32 idx, offset = ctx_offset + cid_addr;
1808         u32 val, retry_cnt = 5;
1809
1810         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1811                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1812
1813         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1814                 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1815                     __FUNCTION__, cid_addr));
1816
1817         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1818
1819                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1820                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1821
1822                 for (idx = 0; idx < retry_cnt; idx++) {
1823                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1824                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1825                                 break;
1826                         DELAY(5);
1827                 }
1828
1829                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1830                         BCE_PRINTF("%s(%d); Unable to write CTX memory: "
1831                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1832                             __FILE__, __LINE__, cid_addr, ctx_offset);
1833
1834         } else {
1835                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1836                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1837         }
1838 }
1839
1840
1841 /****************************************************************************/
1842 /* PHY register read.                                                       */
1843 /*                                                                          */
1844 /* Implements register reads on the MII bus.                                */
1845 /*                                                                          */
1846 /* Returns:                                                                 */
1847 /*   The value of the register.                                             */
1848 /****************************************************************************/
1849 static int
1850 bce_miibus_read_reg(device_t dev, int phy, int reg)
1851 {
1852         struct bce_softc *sc;
1853         u32 val;
1854         int i;
1855
1856         sc = device_get_softc(dev);
1857
1858     /*
1859      * The 5709S PHY is an IEEE Clause 45 PHY
1860      * with special mappings to work with IEEE
1861      * Clause 22 register accesses.
1862      */
1863         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1864                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1865                         reg += 0x10;
1866         }
1867
1868     if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1869                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1870                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1871
1872                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1873                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1874
1875                 DELAY(40);
1876         }
1877
1878
1879         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1880             BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1881             BCE_EMAC_MDIO_COMM_START_BUSY;
1882         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1883
1884         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1885                 DELAY(10);
1886
1887                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1888                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1889                         DELAY(5);
1890
1891                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1892                         val &= BCE_EMAC_MDIO_COMM_DATA;
1893
1894                         break;
1895                 }
1896         }
1897
1898         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1899                 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, "
1900                     "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
1901                 val = 0x0;
1902         } else {
1903                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1904         }
1905
1906
1907         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1908                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1909                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1910
1911                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1912                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1913
1914                 DELAY(40);
1915         }
1916
1917         DB_PRINT_PHY_REG(reg, val);
1918         return (val & 0xffff);
1919 }
1920
1921
1922 /****************************************************************************/
1923 /* PHY register write.                                                      */
1924 /*                                                                          */
1925 /* Implements register writes on the MII bus.                               */
1926 /*                                                                          */
1927 /* Returns:                                                                 */
1928 /*   The value of the register.                                             */
1929 /****************************************************************************/
1930 static int
1931 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1932 {
1933         struct bce_softc *sc;
1934         u32 val1;
1935         int i;
1936
1937         sc = device_get_softc(dev);
1938
1939         DB_PRINT_PHY_REG(reg, val);
1940
1941         /*
1942          * The 5709S PHY is an IEEE Clause 45 PHY
1943          * with special mappings to work with IEEE
1944          * Clause 22 register accesses.
1945          */
1946         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1947                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1948                         reg += 0x10;
1949         }
1950
1951         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1952                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1953                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1954
1955                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1956                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1957
1958                 DELAY(40);
1959         }
1960
1961         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1962             BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1963             BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1964         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1965
1966         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1967                 DELAY(10);
1968
1969                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1970                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1971                         DELAY(5);
1972                         break;
1973                 }
1974         }
1975
1976         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1977                 BCE_PRINTF("%s(%d): PHY write timeout!\n",
1978                     __FILE__, __LINE__);
1979
1980         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1981                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1982                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1983
1984                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1985                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1986
1987                 DELAY(40);
1988         }
1989
1990         return 0;
1991 }
1992
1993
1994 /****************************************************************************/
1995 /* MII bus status change.                                                   */
1996 /*                                                                          */
1997 /* Called by the MII bus driver when the PHY establishes link to set the    */
1998 /* MAC interface registers.                                                 */
1999 /*                                                                          */
2000 /* Returns:                                                                 */
2001 /*   Nothing.                                                               */
2002 /****************************************************************************/
2003 static void
2004 bce_miibus_statchg(device_t dev)
2005 {
2006         struct bce_softc *sc;
2007         struct mii_data *mii;
2008         struct ifmediareq ifmr;
2009         int media_active, media_status, val;
2010
2011         sc = device_get_softc(dev);
2012
2013         DBENTER(BCE_VERBOSE_PHY);
2014
2015         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
2016                 bzero(&ifmr, sizeof(ifmr));
2017                 bce_ifmedia_sts_rphy(sc, &ifmr);
2018                 media_active = ifmr.ifm_active;
2019                 media_status = ifmr.ifm_status;
2020         } else {
2021                 mii = device_get_softc(sc->bce_miibus);
2022                 media_active = mii->mii_media_active;
2023                 media_status = mii->mii_media_status;
2024         }
2025
2026         /* Ignore invalid media status. */
2027         if ((media_status & (IFM_ACTIVE | IFM_AVALID)) !=
2028             (IFM_ACTIVE | IFM_AVALID))
2029                 goto bce_miibus_statchg_exit;
2030
2031         val = REG_RD(sc, BCE_EMAC_MODE);
2032         val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
2033             BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
2034             BCE_EMAC_MODE_25G);
2035
2036         /* Set MII or GMII interface based on the PHY speed. */
2037         switch (IFM_SUBTYPE(media_active)) {
2038         case IFM_10_T:
2039                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2040                         DBPRINT(sc, BCE_INFO_PHY,
2041                             "Enabling 10Mb interface.\n");
2042                         val |= BCE_EMAC_MODE_PORT_MII_10;
2043                         break;
2044                 }
2045                 /* fall-through */
2046         case IFM_100_TX:
2047                 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
2048                 val |= BCE_EMAC_MODE_PORT_MII;
2049                 break;
2050         case IFM_2500_SX:
2051                 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
2052                 val |= BCE_EMAC_MODE_25G;
2053                 /* fall-through */
2054         case IFM_1000_T:
2055         case IFM_1000_SX:
2056                 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
2057                 val |= BCE_EMAC_MODE_PORT_GMII;
2058                 break;
2059         default:
2060                 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
2061                     "default GMII interface.\n");
2062                 val |= BCE_EMAC_MODE_PORT_GMII;
2063         }
2064
2065         /* Set half or full duplex based on PHY settings. */
2066         if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) {
2067                 DBPRINT(sc, BCE_INFO_PHY,
2068                     "Setting Half-Duplex interface.\n");
2069                 val |= BCE_EMAC_MODE_HALF_DUPLEX;
2070         } else
2071                 DBPRINT(sc, BCE_INFO_PHY,
2072                     "Setting Full-Duplex interface.\n");
2073
2074         REG_WR(sc, BCE_EMAC_MODE, val);
2075
2076         if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) {
2077                 DBPRINT(sc, BCE_INFO_PHY,
2078                     "%s(): Enabling RX flow control.\n", __FUNCTION__);
2079                 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2080         } else {
2081                 DBPRINT(sc, BCE_INFO_PHY,
2082                     "%s(): Disabling RX flow control.\n", __FUNCTION__);
2083                 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2084         }
2085
2086         if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) {
2087                 DBPRINT(sc, BCE_INFO_PHY,
2088                     "%s(): Enabling TX flow control.\n", __FUNCTION__);
2089                 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2090                 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL;
2091         } else {
2092                 DBPRINT(sc, BCE_INFO_PHY,
2093                     "%s(): Disabling TX flow control.\n", __FUNCTION__);
2094                 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2095                 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL;
2096         }
2097
2098         /* ToDo: Update watermarks in bce_init_rx_context(). */
2099
2100 bce_miibus_statchg_exit:
2101         DBEXIT(BCE_VERBOSE_PHY);
2102 }
2103
2104
2105 /****************************************************************************/
2106 /* Acquire NVRAM lock.                                                      */
2107 /*                                                                          */
2108 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
2109 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
2110 /* for use by the driver.                                                   */
2111 /*                                                                          */
2112 /* Returns:                                                                 */
2113 /*   0 on success, positive value on failure.                               */
2114 /****************************************************************************/
2115 static int
2116 bce_acquire_nvram_lock(struct bce_softc *sc)
2117 {
2118         u32 val;
2119         int j, rc = 0;
2120
2121         DBENTER(BCE_VERBOSE_NVRAM);
2122
2123         /* Request access to the flash interface. */
2124         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
2125         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2126                 val = REG_RD(sc, BCE_NVM_SW_ARB);
2127                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
2128                         break;
2129
2130                 DELAY(5);
2131         }
2132
2133         if (j >= NVRAM_TIMEOUT_COUNT) {
2134                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
2135                 rc = EBUSY;
2136         }
2137
2138         DBEXIT(BCE_VERBOSE_NVRAM);
2139         return (rc);
2140 }
2141
2142
2143 /****************************************************************************/
2144 /* Release NVRAM lock.                                                      */
2145 /*                                                                          */
2146 /* When the caller is finished accessing NVRAM the lock must be released.   */
2147 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
2148 /* for use by the driver.                                                   */
2149 /*                                                                          */
2150 /* Returns:                                                                 */
2151 /*   0 on success, positive value on failure.                               */
2152 /****************************************************************************/
2153 static int
2154 bce_release_nvram_lock(struct bce_softc *sc)
2155 {
2156         u32 val;
2157         int j, rc = 0;
2158
2159         DBENTER(BCE_VERBOSE_NVRAM);
2160
2161         /*
2162          * Relinquish nvram interface.
2163          */
2164         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
2165
2166         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2167                 val = REG_RD(sc, BCE_NVM_SW_ARB);
2168                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
2169                         break;
2170
2171                 DELAY(5);
2172         }
2173
2174         if (j >= NVRAM_TIMEOUT_COUNT) {
2175                 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
2176                 rc = EBUSY;
2177         }
2178
2179         DBEXIT(BCE_VERBOSE_NVRAM);
2180         return (rc);
2181 }
2182
2183
2184 #ifdef BCE_NVRAM_WRITE_SUPPORT
2185 /****************************************************************************/
2186 /* Enable NVRAM write access.                                               */
2187 /*                                                                          */
2188 /* Before writing to NVRAM the caller must enable NVRAM writes.             */
2189 /*                                                                          */
2190 /* Returns:                                                                 */
2191 /*   0 on success, positive value on failure.                               */
2192 /****************************************************************************/
2193 static int
2194 bce_enable_nvram_write(struct bce_softc *sc)
2195 {
2196         u32 val;
2197         int rc = 0;
2198
2199         DBENTER(BCE_VERBOSE_NVRAM);
2200
2201         val = REG_RD(sc, BCE_MISC_CFG);
2202         REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
2203
2204         if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2205                 int j;
2206
2207                 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2208                 REG_WR(sc, BCE_NVM_COMMAND,     BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
2209
2210                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2211                         DELAY(5);
2212
2213                         val = REG_RD(sc, BCE_NVM_COMMAND);
2214                         if (val & BCE_NVM_COMMAND_DONE)
2215                                 break;
2216                 }
2217
2218                 if (j >= NVRAM_TIMEOUT_COUNT) {
2219                         DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
2220                         rc = EBUSY;
2221                 }
2222         }
2223
2224         DBENTER(BCE_VERBOSE_NVRAM);
2225         return (rc);
2226 }
2227
2228
2229 /****************************************************************************/
2230 /* Disable NVRAM write access.                                              */
2231 /*                                                                          */
2232 /* When the caller is finished writing to NVRAM write access must be        */
2233 /* disabled.                                                                */
2234 /*                                                                          */
2235 /* Returns:                                                                 */
2236 /*   Nothing.                                                               */
2237 /****************************************************************************/
2238 static void
2239 bce_disable_nvram_write(struct bce_softc *sc)
2240 {
2241         u32 val;
2242
2243         DBENTER(BCE_VERBOSE_NVRAM);
2244
2245         val = REG_RD(sc, BCE_MISC_CFG);
2246         REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
2247
2248         DBEXIT(BCE_VERBOSE_NVRAM);
2249
2250 }
2251 #endif
2252
2253
2254 /****************************************************************************/
2255 /* Enable NVRAM access.                                                     */
2256 /*                                                                          */
2257 /* Before accessing NVRAM for read or write operations the caller must      */
2258 /* enabled NVRAM access.                                                    */
2259 /*                                                                          */
2260 /* Returns:                                                                 */
2261 /*   Nothing.                                                               */
2262 /****************************************************************************/
2263 static void
2264 bce_enable_nvram_access(struct bce_softc *sc)
2265 {
2266         u32 val;
2267
2268         DBENTER(BCE_VERBOSE_NVRAM);
2269
2270         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2271         /* Enable both bits, even on read. */
2272         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
2273             BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
2274
2275         DBEXIT(BCE_VERBOSE_NVRAM);
2276 }
2277
2278
2279 /****************************************************************************/
2280 /* Disable NVRAM access.                                                    */
2281 /*                                                                          */
2282 /* When the caller is finished accessing NVRAM access must be disabled.     */
2283 /*                                                                          */
2284 /* Returns:                                                                 */
2285 /*   Nothing.                                                               */
2286 /****************************************************************************/
2287 static void
2288 bce_disable_nvram_access(struct bce_softc *sc)
2289 {
2290         u32 val;
2291
2292         DBENTER(BCE_VERBOSE_NVRAM);
2293
2294         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2295
2296         /* Disable both bits, even after read. */
2297         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
2298             ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
2299
2300         DBEXIT(BCE_VERBOSE_NVRAM);
2301 }
2302
2303
2304 #ifdef BCE_NVRAM_WRITE_SUPPORT
2305 /****************************************************************************/
2306 /* Erase NVRAM page before writing.                                         */
2307 /*                                                                          */
2308 /* Non-buffered flash parts require that a page be erased before it is      */
2309 /* written.                                                                 */
2310 /*                                                                          */
2311 /* Returns:                                                                 */
2312 /*   0 on success, positive value on failure.                               */
2313 /****************************************************************************/
2314 static int
2315 bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
2316 {
2317         u32 cmd;
2318         int j, rc = 0;
2319
2320         DBENTER(BCE_VERBOSE_NVRAM);
2321
2322         /* Buffered flash doesn't require an erase. */
2323         if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
2324                 goto bce_nvram_erase_page_exit;
2325
2326         /* Build an erase command. */
2327         cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
2328             BCE_NVM_COMMAND_DOIT;
2329
2330         /*
2331          * Clear the DONE bit separately, set the NVRAM adress to erase,
2332          * and issue the erase command.
2333          */
2334         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2335         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2336         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2337
2338         /* Wait for completion. */
2339         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2340                 u32 val;
2341
2342                 DELAY(5);
2343
2344                 val = REG_RD(sc, BCE_NVM_COMMAND);
2345                 if (val & BCE_NVM_COMMAND_DONE)
2346                         break;
2347         }
2348
2349         if (j >= NVRAM_TIMEOUT_COUNT) {
2350                 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
2351                 rc = EBUSY;
2352         }
2353
2354 bce_nvram_erase_page_exit:
2355         DBEXIT(BCE_VERBOSE_NVRAM);
2356         return (rc);
2357 }
2358 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2359
2360
2361 /****************************************************************************/
2362 /* Read a dword (32 bits) from NVRAM.                                       */
2363 /*                                                                          */
2364 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
2365 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
2366 /*                                                                          */
2367 /* Returns:                                                                 */
2368 /*   0 on success and the 32 bit value read, positive value on failure.     */
2369 /****************************************************************************/
2370 static int
2371 bce_nvram_read_dword(struct bce_softc *sc,
2372     u32 offset, u8 *ret_val, u32 cmd_flags)
2373 {
2374         u32 cmd;
2375         int i, rc = 0;
2376
2377         DBENTER(BCE_EXTREME_NVRAM);
2378
2379         /* Build the command word. */
2380         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
2381
2382         /* Calculate the offset for buffered flash if translation is used. */
2383         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2384                 offset = ((offset / sc->bce_flash_info->page_size) <<
2385                     sc->bce_flash_info->page_bits) +
2386                     (offset % sc->bce_flash_info->page_size);
2387         }
2388
2389         /*
2390          * Clear the DONE bit separately, set the address to read,
2391          * and issue the read.
2392          */
2393         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2394         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2395         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2396
2397         /* Wait for completion. */
2398         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
2399                 u32 val;
2400
2401                 DELAY(5);
2402
2403                 val = REG_RD(sc, BCE_NVM_COMMAND);
2404                 if (val & BCE_NVM_COMMAND_DONE) {
2405                         val = REG_RD(sc, BCE_NVM_READ);
2406
2407                         val = bce_be32toh(val);
2408                         memcpy(ret_val, &val, 4);
2409                         break;
2410                 }
2411         }
2412
2413         /* Check for errors. */
2414         if (i >= NVRAM_TIMEOUT_COUNT) {
2415                 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at "
2416                     "offset 0x%08X!\n", __FILE__, __LINE__, offset);
2417                 rc = EBUSY;
2418         }
2419
2420         DBEXIT(BCE_EXTREME_NVRAM);
2421         return(rc);
2422 }
2423
2424
2425 #ifdef BCE_NVRAM_WRITE_SUPPORT
2426 /****************************************************************************/
2427 /* Write a dword (32 bits) to NVRAM.                                        */
2428 /*                                                                          */
2429 /* Write a 32 bit word to NVRAM.  The caller is assumed to have already     */
2430 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and    */
2431 /* enabled NVRAM write access.                                              */
2432 /*                                                                          */
2433 /* Returns:                                                                 */
2434 /*   0 on success, positive value on failure.                               */
2435 /****************************************************************************/
2436 static int
2437 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
2438         u32 cmd_flags)
2439 {
2440         u32 cmd, val32;
2441         int j, rc = 0;
2442
2443         DBENTER(BCE_VERBOSE_NVRAM);
2444
2445         /* Build the command word. */
2446         cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
2447
2448         /* Calculate the offset for buffered flash if translation is used. */
2449         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2450                 offset = ((offset / sc->bce_flash_info->page_size) <<
2451                     sc->bce_flash_info->page_bits) +
2452                     (offset % sc->bce_flash_info->page_size);
2453         }
2454
2455         /*
2456          * Clear the DONE bit separately, convert NVRAM data to big-endian,
2457          * set the NVRAM address to write, and issue the write command
2458          */
2459         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2460         memcpy(&val32, val, 4);
2461         val32 = htobe32(val32);
2462         REG_WR(sc, BCE_NVM_WRITE, val32);
2463         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2464         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2465
2466         /* Wait for completion. */
2467         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2468                 DELAY(5);
2469
2470                 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
2471                         break;
2472         }
2473         if (j >= NVRAM_TIMEOUT_COUNT) {
2474                 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at "
2475                     "offset 0x%08X\n", __FILE__, __LINE__, offset);
2476                 rc = EBUSY;
2477         }
2478
2479         DBEXIT(BCE_VERBOSE_NVRAM);
2480         return (rc);
2481 }
2482 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2483
2484
2485 /****************************************************************************/
2486 /* Initialize NVRAM access.                                                 */
2487 /*                                                                          */
2488 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
2489 /* access that device.                                                      */
2490 /*                                                                          */
2491 /* Returns:                                                                 */
2492 /*   0 on success, positive value on failure.                               */
2493 /****************************************************************************/
2494 static int
2495 bce_init_nvram(struct bce_softc *sc)
2496 {
2497         u32 val;
2498         int j, entry_count, rc = 0;
2499         const struct flash_spec *flash;
2500
2501         DBENTER(BCE_VERBOSE_NVRAM);
2502
2503         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2504                 sc->bce_flash_info = &flash_5709;
2505                 goto bce_init_nvram_get_flash_size;
2506         }
2507
2508         /* Determine the selected interface. */
2509         val = REG_RD(sc, BCE_NVM_CFG1);
2510
2511         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2512
2513         /*
2514          * Flash reconfiguration is required to support additional
2515          * NVRAM devices not directly supported in hardware.
2516          * Check if the flash interface was reconfigured
2517          * by the bootcode.
2518          */
2519
2520         if (val & 0x40000000) {
2521                 /* Flash interface reconfigured by bootcode. */
2522
2523                 DBPRINT(sc,BCE_INFO_LOAD,
2524                         "bce_init_nvram(): Flash WAS reconfigured.\n");
2525
2526                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2527                      j++, flash++) {
2528                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
2529                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2530                                 sc->bce_flash_info = flash;
2531                                 break;
2532                         }
2533                 }
2534         } else {
2535                 /* Flash interface not yet reconfigured. */
2536                 u32 mask;
2537
2538                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n",
2539                         __FUNCTION__);
2540
2541                 if (val & (1 << 23))
2542                         mask = FLASH_BACKUP_STRAP_MASK;
2543                 else
2544                         mask = FLASH_STRAP_MASK;
2545
2546                 /* Look for the matching NVRAM device configuration data. */
2547                 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {
2548
2549                         /* Check if the device matches any of the known devices. */
2550                         if ((val & mask) == (flash->strapping & mask)) {
2551                                 /* Found a device match. */
2552                                 sc->bce_flash_info = flash;
2553
2554                                 /* Request access to the flash interface. */
2555                                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2556                                         return rc;
2557
2558                                 /* Reconfigure the flash interface. */
2559                                 bce_enable_nvram_access(sc);
2560                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2561                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2562                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2563                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
2564                                 bce_disable_nvram_access(sc);
2565                                 bce_release_nvram_lock(sc);
2566
2567                                 break;
2568                         }
2569                 }
2570         }
2571
2572         /* Check if a matching device was found. */
2573         if (j == entry_count) {
2574                 sc->bce_flash_info = NULL;
2575                 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
2576                     __FILE__, __LINE__);
2577                 DBEXIT(BCE_VERBOSE_NVRAM);
2578                 return (ENODEV);
2579         }
2580
2581 bce_init_nvram_get_flash_size:
2582         /* Write the flash config data to the shared memory interface. */
2583         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2);
2584         val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2585         if (val)
2586                 sc->bce_flash_size = val;
2587         else
2588                 sc->bce_flash_size = sc->bce_flash_info->total_size;
2589
2590         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2591             __FUNCTION__, sc->bce_flash_info->name,
2592             sc->bce_flash_info->total_size);
2593
2594         DBEXIT(BCE_VERBOSE_NVRAM);
2595         return rc;
2596 }
2597
2598
2599 /****************************************************************************/
2600 /* Read an arbitrary range of data from NVRAM.                              */
2601 /*                                                                          */
2602 /* Prepares the NVRAM interface for access and reads the requested data     */
2603 /* into the supplied buffer.                                                */
2604 /*                                                                          */
2605 /* Returns:                                                                 */
2606 /*   0 on success and the data read, positive value on failure.             */
2607 /****************************************************************************/
2608 static int
2609 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
2610         int buf_size)
2611 {
2612         int rc = 0;
2613         u32 cmd_flags, offset32, len32, extra;
2614
2615         DBENTER(BCE_VERBOSE_NVRAM);
2616
2617         if (buf_size == 0)
2618                 goto bce_nvram_read_exit;
2619
2620         /* Request access to the flash interface. */
2621         if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2622                 goto bce_nvram_read_exit;
2623
2624         /* Enable access to flash interface */
2625         bce_enable_nvram_access(sc);
2626
2627         len32 = buf_size;
2628         offset32 = offset;
2629         extra = 0;
2630
2631         cmd_flags = 0;
2632
2633         if (offset32 & 3) {
2634                 u8 buf[4];
2635                 u32 pre_len;
2636
2637                 offset32 &= ~3;
2638                 pre_len = 4 - (offset & 3);
2639
2640                 if (pre_len >= len32) {
2641                         pre_len = len32;
2642                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
2643                 }
2644                 else {
2645                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2646                 }
2647
2648                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2649
2650                 if (rc)
2651                         return rc;
2652
2653                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2654
2655                 offset32 += 4;
2656                 ret_buf += pre_len;
2657                 len32 -= pre_len;
2658         }
2659
2660         if (len32 & 3) {
2661                 extra = 4 - (len32 & 3);
2662                 len32 = (len32 + 4) & ~3;
2663         }
2664
2665         if (len32 == 4) {
2666                 u8 buf[4];
2667
2668                 if (cmd_flags)
2669                         cmd_flags = BCE_NVM_COMMAND_LAST;
2670                 else
2671                         cmd_flags = BCE_NVM_COMMAND_FIRST |
2672                                     BCE_NVM_COMMAND_LAST;
2673
2674                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2675
2676                 memcpy(ret_buf, buf, 4 - extra);
2677         }
2678         else if (len32 > 0) {
2679                 u8 buf[4];
2680
2681                 /* Read the first word. */
2682                 if (cmd_flags)
2683                         cmd_flags = 0;
2684                 else
2685                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2686
2687                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
2688
2689                 /* Advance to the next dword. */
2690                 offset32 += 4;
2691                 ret_buf += 4;
2692                 len32 -= 4;
2693
2694                 while (len32 > 4 && rc == 0) {
2695                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
2696
2697                         /* Advance to the next dword. */
2698                         offset32 += 4;
2699                         ret_buf += 4;
2700                         len32 -= 4;
2701                 }
2702
2703                 if (rc)
2704                         goto bce_nvram_read_locked_exit;
2705
2706                 cmd_flags = BCE_NVM_COMMAND_LAST;
2707                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2708
2709                 memcpy(ret_buf, buf, 4 - extra);
2710         }
2711
2712 bce_nvram_read_locked_exit:
2713         /* Disable access to flash interface and release the lock. */
2714         bce_disable_nvram_access(sc);
2715         bce_release_nvram_lock(sc);
2716
2717 bce_nvram_read_exit:
2718         DBEXIT(BCE_VERBOSE_NVRAM);
2719         return rc;
2720 }
2721
2722
2723 #ifdef BCE_NVRAM_WRITE_SUPPORT
2724 /****************************************************************************/
2725 /* Write an arbitrary range of data from NVRAM.                             */
2726 /*                                                                          */
2727 /* Prepares the NVRAM interface for write access and writes the requested   */
2728 /* data from the supplied buffer.  The caller is responsible for            */
2729 /* calculating any appropriate CRCs.                                        */
2730 /*                                                                          */
2731 /* Returns:                                                                 */
2732 /*   0 on success, positive value on failure.                               */
2733 /****************************************************************************/
2734 static int
2735 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
2736         int buf_size)
2737 {
2738         u32 written, offset32, len32;
2739         u8 *buf, start[4], end[4];
2740         int rc = 0;
2741         int align_start, align_end;
2742
2743         DBENTER(BCE_VERBOSE_NVRAM);
2744
2745         buf = data_buf;
2746         offset32 = offset;
2747         len32 = buf_size;
2748         align_start = align_end = 0;
2749
2750         if ((align_start = (offset32 & 3))) {
2751                 offset32 &= ~3;
2752                 len32 += align_start;
2753                 if ((rc = bce_nvram_read(sc, offset32, start, 4)))
2754                         goto bce_nvram_write_exit;
2755         }
2756
2757         if (len32 & 3) {
2758                 if ((len32 > 4) || !align_start) {
2759                         align_end = 4 - (len32 & 3);
2760                         len32 += align_end;
2761                         if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2762                                 end, 4))) {
2763                                 goto bce_nvram_write_exit;
2764                         }
2765                 }
2766         }
2767
2768         if (align_start || align_end) {
2769                 buf = malloc(len32, M_DEVBUF, M_NOWAIT);
2770                 if (buf == 0) {
2771                         rc = ENOMEM;
2772                         goto bce_nvram_write_exit;
2773                 }
2774
2775                 if (align_start) {
2776                         memcpy(buf, start, 4);
2777                 }
2778
2779                 if (align_end) {
2780                         memcpy(buf + len32 - 4, end, 4);
2781                 }
2782                 memcpy(buf + align_start, data_buf, buf_size);
2783         }
2784
2785         written = 0;
2786         while ((written < len32) && (rc == 0)) {
2787                 u32 page_start, page_end, data_start, data_end;
2788                 u32 addr, cmd_flags;
2789                 int i;
2790                 u8 flash_buffer[264];
2791
2792             /* Find the page_start addr */
2793                 page_start = offset32 + written;
2794                 page_start -= (page_start % sc->bce_flash_info->page_size);
2795                 /* Find the page_end addr */
2796                 page_end = page_start + sc->bce_flash_info->page_size;
2797                 /* Find the data_start addr */
2798                 data_start = (written == 0) ? offset32 : page_start;
2799                 /* Find the data_end addr */
2800                 data_end = (page_end > offset32 + len32) ?
2801                         (offset32 + len32) : page_end;
2802
2803                 /* Request access to the flash interface. */
2804                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2805                         goto bce_nvram_write_exit;
2806
2807                 /* Enable access to flash interface */
2808                 bce_enable_nvram_access(sc);
2809
2810                 cmd_flags = BCE_NVM_COMMAND_FIRST;
2811                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2812                         int j;
2813
2814                         /* Read the whole page into the buffer
2815                          * (non-buffer flash only) */
2816                         for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2817                                 if (j == (sc->bce_flash_info->page_size - 4)) {
2818                                         cmd_flags |= BCE_NVM_COMMAND_LAST;
2819                                 }
2820                                 rc = bce_nvram_read_dword(sc,
2821                                         page_start + j,
2822                                         &flash_buffer[j],
2823                                         cmd_flags);
2824
2825                                 if (rc)
2826                                         goto bce_nvram_write_locked_exit;
2827
2828                                 cmd_flags = 0;
2829                         }
2830                 }
2831
2832                 /* Enable writes to flash interface (unlock write-protect) */
2833                 if ((rc = bce_enable_nvram_write(sc)) != 0)
2834                         goto bce_nvram_write_locked_exit;
2835
2836                 /* Erase the page */
2837                 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2838                         goto bce_nvram_write_locked_exit;
2839
2840                 /* Re-enable the write again for the actual write */
2841                 bce_enable_nvram_write(sc);
2842
2843                 /* Loop to write back the buffer data from page_start to
2844                  * data_start */
2845                 i = 0;
2846                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2847                         for (addr = page_start; addr < data_start;
2848                                 addr += 4, i += 4) {
2849
2850                                 rc = bce_nvram_write_dword(sc, addr,
2851                                         &flash_buffer[i], cmd_flags);
2852
2853                                 if (rc != 0)
2854                                         goto bce_nvram_write_locked_exit;
2855
2856                                 cmd_flags = 0;
2857                         }
2858                 }
2859
2860                 /* Loop to write the new data from data_start to data_end */
2861                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2862                         if ((addr == page_end - 4) ||
2863                                 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2864                                 (addr == data_end - 4))) {
2865
2866                                 cmd_flags |= BCE_NVM_COMMAND_LAST;
2867                         }
2868                         rc = bce_nvram_write_dword(sc, addr, buf,
2869                                 cmd_flags);
2870
2871                         if (rc != 0)
2872                                 goto bce_nvram_write_locked_exit;
2873
2874                         cmd_flags = 0;
2875                         buf += 4;
2876                 }
2877
2878                 /* Loop to write back the buffer data from data_end
2879                  * to page_end */
2880                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2881                         for (addr = data_end; addr < page_end;
2882                                 addr += 4, i += 4) {
2883
2884                                 if (addr == page_end-4) {
2885                                         cmd_flags = BCE_NVM_COMMAND_LAST;
2886                                 }
2887                                 rc = bce_nvram_write_dword(sc, addr,
2888                                         &flash_buffer[i], cmd_flags);
2889
2890                                 if (rc != 0)
2891                                         goto bce_nvram_write_locked_exit;
2892
2893                                 cmd_flags = 0;
2894                         }
2895                 }
2896
2897                 /* Disable writes to flash interface (lock write-protect) */
2898                 bce_disable_nvram_write(sc);
2899
2900                 /* Disable access to flash interface */
2901                 bce_disable_nvram_access(sc);
2902                 bce_release_nvram_lock(sc);
2903
2904                 /* Increment written */
2905                 written += data_end - data_start;
2906         }
2907
2908         goto bce_nvram_write_exit;
2909
2910 bce_nvram_write_locked_exit:
2911         bce_disable_nvram_write(sc);
2912         bce_disable_nvram_access(sc);
2913         bce_release_nvram_lock(sc);
2914
2915 bce_nvram_write_exit:
2916         if (align_start || align_end)
2917                 free(buf, M_DEVBUF);
2918
2919         DBEXIT(BCE_VERBOSE_NVRAM);
2920         return (rc);
2921 }
2922 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2923
2924
2925 /****************************************************************************/
2926 /* Verifies that NVRAM is accessible and contains valid data.               */
2927 /*                                                                          */
2928 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
2929 /* correct.                                                                 */
2930 /*                                                                          */
2931 /* Returns:                                                                 */
2932 /*   0 on success, positive value on failure.                               */
2933 /****************************************************************************/
2934 static int
2935 bce_nvram_test(struct bce_softc *sc)
2936 {
2937         u32 buf[BCE_NVRAM_SIZE / 4];
2938         u8 *data = (u8 *) buf;
2939         int rc = 0;
2940         u32 magic, csum;
2941
2942         DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2943
2944         /*
2945          * Check that the device NVRAM is valid by reading
2946          * the magic value at offset 0.
2947          */
2948         if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2949                 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n",
2950                     __FILE__, __LINE__);
2951                 goto bce_nvram_test_exit;
2952         }
2953
2954         /*
2955          * Verify that offset 0 of the NVRAM contains
2956          * a valid magic number.
2957          */
2958         magic = bce_be32toh(buf[0]);
2959         if (magic != BCE_NVRAM_MAGIC) {
2960                 rc = ENODEV;
2961                 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! "
2962                     "Expected: 0x%08X, Found: 0x%08X\n",
2963                     __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
2964                 goto bce_nvram_test_exit;
2965         }
2966
2967         /*
2968          * Verify that the device NVRAM includes valid
2969          * configuration data.
2970          */
2971         if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
2972                 BCE_PRINTF("%s(%d): Unable to read manufacturing "
2973                     "Information from  NVRAM!\n", __FILE__, __LINE__);
2974                 goto bce_nvram_test_exit;
2975         }
2976
2977         csum = ether_crc32_le(data, 0x100);
2978         if (csum != BCE_CRC32_RESIDUAL) {
2979                 rc = ENODEV;
2980                 BCE_PRINTF("%s(%d): Invalid manufacturing information "
2981                     "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
2982                     __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
2983                 goto bce_nvram_test_exit;
2984         }
2985
2986         csum = ether_crc32_le(data + 0x100, 0x100);
2987         if (csum != BCE_CRC32_RESIDUAL) {
2988                 rc = ENODEV;
2989                 BCE_PRINTF("%s(%d): Invalid feature configuration "
2990                     "information NVRAM CRC! Expected: 0x%08X, "
2991                     "Found: 08%08X\n", __FILE__, __LINE__,
2992                     BCE_CRC32_RESIDUAL, csum);
2993         }
2994
2995 bce_nvram_test_exit:
2996         DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2997         return rc;
2998 }
2999
3000
3001 /****************************************************************************/
3002 /* Calculates the size of the buffers to allocate based on the MTU.         */
3003 /*                                                                          */
3004 /* Returns:                                                                 */
3005 /*   Nothing.                                                               */
3006 /****************************************************************************/
3007 static void
3008 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu)
3009 {
3010         DBENTER(BCE_VERBOSE_LOAD);
3011
3012         /* Use a single allocation type when header splitting enabled. */
3013         if (bce_hdr_split == TRUE) {
3014                 sc->rx_bd_mbuf_alloc_size = MHLEN;
3015                 /* Make sure offset is 16 byte aligned for hardware. */
3016                 sc->rx_bd_mbuf_align_pad =
3017                         roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN);
3018                 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
3019                         sc->rx_bd_mbuf_align_pad;
3020         } else {
3021                 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
3022                     ETHER_CRC_LEN) > MCLBYTES) {
3023                         /* Setup for jumbo RX buffer allocations. */
3024                         sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
3025                         sc->rx_bd_mbuf_align_pad  =
3026                                 roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
3027                         sc->rx_bd_mbuf_data_len =
3028                             sc->rx_bd_mbuf_alloc_size -
3029                             sc->rx_bd_mbuf_align_pad;
3030                 } else {
3031                         /* Setup for standard RX buffer allocations. */
3032                         sc->rx_bd_mbuf_alloc_size = MCLBYTES;
3033                         sc->rx_bd_mbuf_align_pad  =
3034                             roundup2(MCLBYTES, 16) - MCLBYTES;
3035                         sc->rx_bd_mbuf_data_len =
3036                             sc->rx_bd_mbuf_alloc_size -
3037                             sc->rx_bd_mbuf_align_pad;
3038                 }
3039         }
3040
3041 //      DBPRINT(sc, BCE_INFO_LOAD,
3042         DBPRINT(sc, BCE_WARN,
3043            "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, "
3044            "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
3045            sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
3046            sc->rx_bd_mbuf_align_pad);
3047
3048         DBEXIT(BCE_VERBOSE_LOAD);
3049 }
3050
3051 /****************************************************************************/
3052 /* Identifies the current media type of the controller and sets the PHY     */
3053 /* address.                                                                 */
3054 /*                                                                          */
3055 /* Returns:                                                                 */
3056 /*   Nothing.                                                               */
3057 /****************************************************************************/
3058 static void
3059 bce_get_media(struct bce_softc *sc)
3060 {
3061         u32 val;
3062
3063         DBENTER(BCE_VERBOSE_PHY);
3064
3065         /* Assume PHY address for copper controllers. */
3066         sc->bce_phy_addr = 1;
3067
3068         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3069                 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
3070                 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
3071                 u32 strap;
3072
3073                 /*
3074                  * The BCM5709S is software configurable
3075                  * for Copper or SerDes operation.
3076                  */
3077                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
3078                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3079                             "for copper.\n");
3080                         goto bce_get_media_exit;
3081                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
3082                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3083                             "for dual media.\n");
3084                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3085                         goto bce_get_media_exit;
3086                 }
3087
3088                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
3089                         strap = (val &
3090                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
3091                 else
3092                         strap = (val &
3093                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
3094
3095                 if (pci_get_function(sc->bce_dev) == 0) {
3096                         switch (strap) {
3097                         case 0x4:
3098                         case 0x5:
3099                         case 0x6:
3100                                 DBPRINT(sc, BCE_INFO_LOAD,
3101                                     "BCM5709 s/w configured for SerDes.\n");
3102                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3103                                 break;
3104                         default:
3105                                 DBPRINT(sc, BCE_INFO_LOAD,
3106                                     "BCM5709 s/w configured for Copper.\n");
3107                                 break;
3108                         }
3109                 } else {
3110                         switch (strap) {
3111                         case 0x1:
3112                         case 0x2:
3113                         case 0x4:
3114                                 DBPRINT(sc, BCE_INFO_LOAD,
3115                                     "BCM5709 s/w configured for SerDes.\n");
3116                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3117                                 break;
3118                         default:
3119                                 DBPRINT(sc, BCE_INFO_LOAD,
3120                                     "BCM5709 s/w configured for Copper.\n");
3121                                 break;
3122                         }
3123                 }
3124
3125         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
3126                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3127
3128         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
3129
3130                 sc->bce_flags |= BCE_NO_WOL_FLAG;
3131
3132                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
3133                         sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG;
3134
3135                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
3136                         /* 5708S/09S/16S use a separate PHY for SerDes. */
3137                         sc->bce_phy_addr = 2;
3138
3139                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
3140                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
3141                                 sc->bce_phy_flags |=
3142                                     BCE_PHY_2_5G_CAPABLE_FLAG;
3143                                 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb "
3144                                     "capable adapter\n");
3145                         }
3146                 }
3147         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
3148             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708))
3149                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
3150
3151 bce_get_media_exit:
3152         DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
3153                 "Using PHY address %d.\n", sc->bce_phy_addr);
3154
3155         DBEXIT(BCE_VERBOSE_PHY);
3156 }
3157
3158
3159 /****************************************************************************/
3160 /* Performs PHY initialization required before MII drivers access the       */
3161 /* device.                                                                  */
3162 /*                                                                          */
3163 /* Returns:                                                                 */
3164 /*   Nothing.                                                               */
3165 /****************************************************************************/
3166 static void
3167 bce_init_media(struct bce_softc *sc)
3168 {
3169         if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG |
3170             BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) {
3171                 /*
3172                  * Configure 5709S/5716S PHYs to use traditional IEEE
3173                  * Clause 22 method. Otherwise we have no way to attach
3174                  * the PHY in mii(4) layer. PHY specific configuration
3175                  * is done in mii layer.
3176                  */
3177
3178                 /* Select auto-negotiation MMD of the PHY. */
3179                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3180                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT);
3181                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3182                     BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD);
3183
3184                 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */
3185                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3186                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
3187         }
3188 }
3189
3190
3191 /****************************************************************************/
3192 /* Free any DMA memory owned by the driver.                                 */
3193 /*                                                                          */
3194 /* Scans through each data structre that requires DMA memory and frees      */
3195 /* the memory if allocated.                                                 */
3196 /*                                                                          */
3197 /* Returns:                                                                 */
3198 /*   Nothing.                                                               */
3199 /****************************************************************************/
3200 static void
3201 bce_dma_free(struct bce_softc *sc)
3202 {
3203         int i;
3204
3205         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3206
3207         /* Free, unmap, and destroy the status block. */
3208         if (sc->status_block != NULL) {
3209                 bus_dmamem_free(
3210                    sc->status_tag,
3211                     sc->status_block,
3212                     sc->status_map);
3213                 sc->status_block = NULL;
3214         }
3215
3216         if (sc->status_map != NULL) {
3217                 bus_dmamap_unload(
3218                     sc->status_tag,
3219                     sc->status_map);
3220                 bus_dmamap_destroy(sc->status_tag,
3221                     sc->status_map);
3222                 sc->status_map = NULL;
3223         }
3224
3225         if (sc->status_tag != NULL) {
3226                 bus_dma_tag_destroy(sc->status_tag);
3227                 sc->status_tag = NULL;
3228         }
3229
3230
3231         /* Free, unmap, and destroy the statistics block. */
3232         if (sc->stats_block != NULL) {
3233                 bus_dmamem_free(
3234                     sc->stats_tag,
3235                     sc->stats_block,
3236                     sc->stats_map);
3237                 sc->stats_block = NULL;
3238         }
3239
3240         if (sc->stats_map != NULL) {
3241                 bus_dmamap_unload(
3242                     sc->stats_tag,
3243                     sc->stats_map);
3244                 bus_dmamap_destroy(sc->stats_tag,
3245                     sc->stats_map);
3246                 sc->stats_map = NULL;
3247         }
3248
3249         if (sc->stats_tag != NULL) {
3250                 bus_dma_tag_destroy(sc->stats_tag);
3251                 sc->stats_tag = NULL;
3252         }
3253
3254
3255         /* Free, unmap and destroy all context memory pages. */
3256         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3257                 for (i = 0; i < sc->ctx_pages; i++ ) {
3258                         if (sc->ctx_block[i] != NULL) {
3259                                 bus_dmamem_free(
3260                                     sc->ctx_tag,
3261                                     sc->ctx_block[i],
3262                                     sc->ctx_map[i]);
3263                                 sc->ctx_block[i] = NULL;
3264                         }
3265
3266                         if (sc->ctx_map[i] != NULL) {
3267                                 bus_dmamap_unload(
3268                                     sc->ctx_tag,
3269                                     sc->ctx_map[i]);
3270                                 bus_dmamap_destroy(
3271                                     sc->ctx_tag,
3272                                     sc->ctx_map[i]);
3273                                 sc->ctx_map[i] = NULL;
3274                         }
3275                 }
3276
3277                 /* Destroy the context memory tag. */
3278                 if (sc->ctx_tag != NULL) {
3279                         bus_dma_tag_destroy(sc->ctx_tag);
3280                         sc->ctx_tag = NULL;
3281                 }
3282         }
3283
3284
3285         /* Free, unmap and destroy all TX buffer descriptor chain pages. */
3286         for (i = 0; i < sc->tx_pages; i++ ) {
3287                 if (sc->tx_bd_chain[i] != NULL) {
3288                         bus_dmamem_free(
3289                             sc->tx_bd_chain_tag,
3290                             sc->tx_bd_chain[i],
3291                             sc->tx_bd_chain_map[i]);
3292                         sc->tx_bd_chain[i] = NULL;
3293                 }
3294
3295                 if (sc->tx_bd_chain_map[i] != NULL) {
3296                         bus_dmamap_unload(
3297                             sc->tx_bd_chain_tag,
3298                             sc->tx_bd_chain_map[i]);
3299                         bus_dmamap_destroy(
3300                             sc->tx_bd_chain_tag,
3301                             sc->tx_bd_chain_map[i]);
3302                         sc->tx_bd_chain_map[i] = NULL;
3303                 }
3304         }
3305
3306         /* Destroy the TX buffer descriptor tag. */
3307         if (sc->tx_bd_chain_tag != NULL) {
3308                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
3309                 sc->tx_bd_chain_tag = NULL;
3310         }
3311
3312
3313         /* Free, unmap and destroy all RX buffer descriptor chain pages. */
3314         for (i = 0; i < sc->rx_pages; i++ ) {
3315                 if (sc->rx_bd_chain[i] != NULL) {
3316                         bus_dmamem_free(
3317                             sc->rx_bd_chain_tag,
3318                             sc->rx_bd_chain[i],
3319                             sc->rx_bd_chain_map[i]);
3320                         sc->rx_bd_chain[i] = NULL;
3321                 }
3322
3323                 if (sc->rx_bd_chain_map[i] != NULL) {
3324                         bus_dmamap_unload(
3325                             sc->rx_bd_chain_tag,
3326                             sc->rx_bd_chain_map[i]);
3327                         bus_dmamap_destroy(
3328                             sc->rx_bd_chain_tag,
3329                             sc->rx_bd_chain_map[i]);
3330                         sc->rx_bd_chain_map[i] = NULL;
3331                 }
3332         }
3333
3334         /* Destroy the RX buffer descriptor tag. */
3335         if (sc->rx_bd_chain_tag != NULL) {
3336                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
3337                 sc->rx_bd_chain_tag = NULL;
3338         }
3339
3340
3341         /* Free, unmap and destroy all page buffer descriptor chain pages. */
3342         if (bce_hdr_split == TRUE) {
3343                 for (i = 0; i < sc->pg_pages; i++ ) {
3344                         if (sc->pg_bd_chain[i] != NULL) {
3345                                 bus_dmamem_free(
3346                                     sc->pg_bd_chain_tag,
3347                                     sc->pg_bd_chain[i],
3348                                     sc->pg_bd_chain_map[i]);
3349                                 sc->pg_bd_chain[i] = NULL;
3350                         }
3351
3352                         if (sc->pg_bd_chain_map[i] != NULL) {
3353                                 bus_dmamap_unload(
3354                                     sc->pg_bd_chain_tag,
3355                                     sc->pg_bd_chain_map[i]);
3356                                 bus_dmamap_destroy(
3357                                     sc->pg_bd_chain_tag,
3358                                     sc->pg_bd_chain_map[i]);
3359                                 sc->pg_bd_chain_map[i] = NULL;
3360                         }
3361                 }
3362
3363                 /* Destroy the page buffer descriptor tag. */
3364                 if (sc->pg_bd_chain_tag != NULL) {
3365                         bus_dma_tag_destroy(sc->pg_bd_chain_tag);
3366                         sc->pg_bd_chain_tag = NULL;
3367                 }
3368         }
3369
3370
3371         /* Unload and destroy the TX mbuf maps. */
3372         for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
3373                 if (sc->tx_mbuf_map[i] != NULL) {
3374                         bus_dmamap_unload(sc->tx_mbuf_tag,
3375                             sc->tx_mbuf_map[i]);
3376                         bus_dmamap_destroy(sc->tx_mbuf_tag,
3377                             sc->tx_mbuf_map[i]);
3378                         sc->tx_mbuf_map[i] = NULL;
3379                 }
3380         }
3381
3382         /* Destroy the TX mbuf tag. */
3383         if (sc->tx_mbuf_tag != NULL) {
3384                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
3385                 sc->tx_mbuf_tag = NULL;
3386         }
3387
3388         /* Unload and destroy the RX mbuf maps. */
3389         for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
3390                 if (sc->rx_mbuf_map[i] != NULL) {
3391                         bus_dmamap_unload(sc->rx_mbuf_tag,
3392                             sc->rx_mbuf_map[i]);
3393                         bus_dmamap_destroy(sc->rx_mbuf_tag,
3394                             sc->rx_mbuf_map[i]);
3395                         sc->rx_mbuf_map[i] = NULL;
3396                 }
3397         }
3398
3399         /* Destroy the RX mbuf tag. */
3400         if (sc->rx_mbuf_tag != NULL) {
3401                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
3402                 sc->rx_mbuf_tag = NULL;
3403         }
3404
3405         /* Unload and destroy the page mbuf maps. */
3406         if (bce_hdr_split == TRUE) {
3407                 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
3408                         if (sc->pg_mbuf_map[i] != NULL) {
3409                                 bus_dmamap_unload(sc->pg_mbuf_tag,
3410                                     sc->pg_mbuf_map[i]);
3411                                 bus_dmamap_destroy(sc->pg_mbuf_tag,
3412                                     sc->pg_mbuf_map[i]);
3413                                 sc->pg_mbuf_map[i] = NULL;
3414                         }
3415                 }
3416
3417                 /* Destroy the page mbuf tag. */
3418                 if (sc->pg_mbuf_tag != NULL) {
3419                         bus_dma_tag_destroy(sc->pg_mbuf_tag);
3420                         sc->pg_mbuf_tag = NULL;
3421                 }
3422         }
3423
3424         /* Destroy the parent tag */
3425         if (sc->parent_tag != NULL) {
3426                 bus_dma_tag_destroy(sc->parent_tag);
3427                 sc->parent_tag = NULL;
3428         }
3429
3430         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3431 }
3432
3433
3434 /****************************************************************************/
3435 /* Get DMA memory from the OS.                                              */
3436 /*                                                                          */
3437 /* Validates that the OS has provided DMA buffers in response to a          */
3438 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
3439 /* When the callback is used the OS will return 0 for the mapping function  */
3440 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
3441 /* failures back to the caller.                                             */
3442 /*                                                                          */
3443 /* Returns:                                                                 */
3444 /*   Nothing.                                                               */
3445 /****************************************************************************/
3446 static void
3447 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3448 {
3449         bus_addr_t *busaddr = arg;
3450
3451         KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!",
3452             __FUNCTION__, nseg));
3453         /* Simulate a mapping failure. */
3454         DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control),
3455             error = ENOMEM);
3456
3457         /* ToDo: How to increment debug sim_count variable here? */
3458
3459         /* Check for an error and signal the caller that an error occurred. */
3460         if (error) {
3461                 *busaddr = 0;
3462         } else {
3463                 *busaddr = segs->ds_addr;
3464         }
3465 }
3466
3467
3468 /****************************************************************************/
3469 /* Allocate any DMA memory needed by the driver.                            */
3470 /*                                                                          */
3471 /* Allocates DMA memory needed for the various global structures needed by  */
3472 /* hardware.                                                                */
3473 /*                                                                          */
3474 /* Memory alignment requirements:                                           */
3475 /* +-----------------+----------+----------+----------+----------+          */
3476 /* |                 |   5706   |   5708   |   5709   |   5716   |          */
3477 /* +-----------------+----------+----------+----------+----------+          */
3478 /* |Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3479 /* |Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3480 /* |RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |          */
3481 /* |PG Buffers       |   none   |   none   |   none   |   none   |          */
3482 /* |TX Buffers       |   none   |   none   |   none   |   none   |          */
3483 /* |Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |          */
3484 /* |Context Memory   |          |          |          |          |          */
3485 /* +-----------------+----------+----------+----------+----------+          */
3486 /*                                                                          */
3487 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
3488 /*                                                                          */
3489 /* Returns:                                                                 */
3490 /*   0 for success, positive value for failure.                             */
3491 /****************************************************************************/
3492 static int
3493 bce_dma_alloc(device_t dev)
3494 {
3495         struct bce_softc *sc;
3496         int i, error, rc = 0;
3497         bus_size_t max_size, max_seg_size;
3498         int max_segments;
3499
3500         sc = device_get_softc(dev);
3501
3502         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3503
3504         /*
3505          * Allocate the parent bus DMA tag appropriate for PCI.
3506          */
3507         if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY,
3508             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3509             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3510             &sc->parent_tag)) {
3511                 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
3512                     __FILE__, __LINE__);
3513                 rc = ENOMEM;
3514                 goto bce_dma_alloc_exit;
3515         }
3516
3517         /*
3518          * Create a DMA tag for the status block, allocate and clear the
3519          * memory, map the memory into DMA space, and fetch the physical
3520          * address of the block.
3521          */
3522         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3523             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3524             NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
3525             0, NULL, NULL, &sc->status_tag)) {
3526                 BCE_PRINTF("%s(%d): Could not allocate status block "
3527                     "DMA tag!\n", __FILE__, __LINE__);
3528                 rc = ENOMEM;
3529                 goto bce_dma_alloc_exit;
3530         }
3531
3532         if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
3533             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3534             &sc->status_map)) {
3535                 BCE_PRINTF("%s(%d): Could not allocate status block "
3536                     "DMA memory!\n", __FILE__, __LINE__);
3537                 rc = ENOMEM;
3538                 goto bce_dma_alloc_exit;
3539         }
3540
3541         error = bus_dmamap_load(sc->status_tag, sc->status_map,
3542             sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr,
3543             &sc->status_block_paddr, BUS_DMA_NOWAIT);
3544
3545         if (error || sc->status_block_paddr == 0) {
3546                 BCE_PRINTF("%s(%d): Could not map status block "
3547                     "DMA memory!\n", __FILE__, __LINE__);
3548                 rc = ENOMEM;
3549                 goto bce_dma_alloc_exit;
3550         }
3551
3552         DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n",
3553             __FUNCTION__, (uintmax_t) sc->status_block_paddr);
3554
3555         /*
3556          * Create a DMA tag for the statistics block, allocate and clear the
3557          * memory, map the memory into DMA space, and fetch the physical
3558          * address of the block.
3559          */
3560         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3561             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3562             NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
3563             0, NULL, NULL, &sc->stats_tag)) {
3564                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3565                     "DMA tag!\n", __FILE__, __LINE__);
3566                 rc = ENOMEM;
3567                 goto bce_dma_alloc_exit;
3568         }
3569
3570         if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
3571             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) {
3572                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3573                     "DMA memory!\n", __FILE__, __LINE__);
3574                 rc = ENOMEM;
3575                 goto bce_dma_alloc_exit;
3576         }
3577
3578         error = bus_dmamap_load(sc->stats_tag, sc->stats_map,
3579             sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr,
3580             &sc->stats_block_paddr, BUS_DMA_NOWAIT);
3581
3582         if (error || sc->stats_block_paddr == 0) {
3583                 BCE_PRINTF("%s(%d): Could not map statistics block "
3584                     "DMA memory!\n", __FILE__, __LINE__);
3585                 rc = ENOMEM;
3586                 goto bce_dma_alloc_exit;
3587         }
3588
3589         DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n",
3590             __FUNCTION__, (uintmax_t) sc->stats_block_paddr);
3591
3592         /* BCM5709 uses host memory as cache for context memory. */
3593         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3594                 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3595                 if (sc->ctx_pages == 0)
3596                         sc->ctx_pages = 1;
3597
3598                 DBRUNIF((sc->ctx_pages > 512),
3599                     BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n",
3600                     __FILE__, __LINE__, sc->ctx_pages));
3601
3602                 /*
3603                  * Create a DMA tag for the context pages,
3604                  * allocate and clear the memory, map the
3605                  * memory into DMA space, and fetch the
3606                  * physical address of the block.
3607                  */
3608                 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3609                     BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3610                     NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
3611                     0, NULL, NULL, &sc->ctx_tag)) {
3612                         BCE_PRINTF("%s(%d): Could not allocate CTX "
3613                             "DMA tag!\n", __FILE__, __LINE__);
3614                         rc = ENOMEM;
3615                         goto bce_dma_alloc_exit;
3616                 }
3617
3618                 for (i = 0; i < sc->ctx_pages; i++) {
3619
3620                         if(bus_dmamem_alloc(sc->ctx_tag,
3621                             (void **)&sc->ctx_block[i],
3622                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3623                             &sc->ctx_map[i])) {
3624                                 BCE_PRINTF("%s(%d): Could not allocate CTX "
3625                                     "DMA memory!\n", __FILE__, __LINE__);
3626                                 rc = ENOMEM;
3627                                 goto bce_dma_alloc_exit;
3628                         }
3629
3630                         error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
3631                             sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr,
3632                             &sc->ctx_paddr[i], BUS_DMA_NOWAIT);
3633
3634                         if (error || sc->ctx_paddr[i] == 0) {
3635                                 BCE_PRINTF("%s(%d): Could not map CTX "
3636                                     "DMA memory!\n", __FILE__, __LINE__);
3637                                 rc = ENOMEM;
3638                                 goto bce_dma_alloc_exit;
3639                         }
3640
3641                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] "
3642                             "= 0x%jX\n", __FUNCTION__, i,
3643                             (uintmax_t) sc->ctx_paddr[i]);
3644                 }
3645         }
3646
3647         /*
3648          * Create a DMA tag for the TX buffer descriptor chain,
3649          * allocate and clear the  memory, and fetch the
3650          * physical address of the block.
3651          */
3652         if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
3653             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3654             BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0,
3655             NULL, NULL, &sc->tx_bd_chain_tag)) {
3656                 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3657                     "chain DMA tag!\n", __FILE__, __LINE__);
3658                 rc = ENOMEM;
3659                 goto bce_dma_alloc_exit;
3660         }
3661
3662         for (i = 0; i < sc->tx_pages; i++) {
3663
3664                 if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
3665                     (void **)&sc->tx_bd_chain[i],
3666                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3667                     &sc->tx_bd_chain_map[i])) {
3668                         BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3669                             "chain DMA memory!\n", __FILE__, __LINE__);
3670                         rc = ENOMEM;
3671                         goto bce_dma_alloc_exit;
3672                 }
3673
3674                 error = bus_dmamap_load(sc->tx_bd_chain_tag,
3675                     sc->tx_bd_chain_map[i], sc->tx_bd_chain[i],
3676                     BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3677                     &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3678
3679                 if (error || sc->tx_bd_chain_paddr[i] == 0) {
3680                         BCE_PRINTF("%s(%d): Could not map TX descriptor "
3681                             "chain DMA memory!\n", __FILE__, __LINE__);
3682                         rc = ENOMEM;
3683                         goto bce_dma_alloc_exit;
3684                 }
3685
3686                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = "
3687                     "0x%jX\n", __FUNCTION__, i,
3688                     (uintmax_t) sc->tx_bd_chain_paddr[i]);
3689         }
3690
3691         /* Check the required size before mapping to conserve resources. */
3692         if (bce_tso_enable) {
3693                 max_size     = BCE_TSO_MAX_SIZE;
3694                 max_segments = BCE_MAX_SEGMENTS;
3695                 max_seg_size = BCE_TSO_MAX_SEG_SIZE;
3696         } else {
3697                 max_size     = MCLBYTES * BCE_MAX_SEGMENTS;
3698                 max_segments = BCE_MAX_SEGMENTS;
3699                 max_seg_size = MCLBYTES;
3700         }
3701
3702         /* Create a DMA tag for TX mbufs. */
3703         if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3704             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
3705             max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) {
3706                 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
3707                     __FILE__, __LINE__);
3708                 rc = ENOMEM;
3709                 goto bce_dma_alloc_exit;
3710         }
3711
3712         /* Create DMA maps for the TX mbufs clusters. */
3713         for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) {
3714                 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3715                         &sc->tx_mbuf_map[i])) {
3716                         BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA "
3717                             "map!\n", __FILE__, __LINE__);
3718                         rc = ENOMEM;
3719                         goto bce_dma_alloc_exit;
3720                 }
3721         }
3722
3723         /*
3724          * Create a DMA tag for the RX buffer descriptor chain,
3725          * allocate and clear the memory, and fetch the physical
3726          * address of the blocks.
3727          */
3728         if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3729                         BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
3730                         sc->max_bus_addr, NULL, NULL,
3731                         BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
3732                         0, NULL, NULL, &sc->rx_bd_chain_tag)) {
3733                 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain "
3734                     "DMA tag!\n", __FILE__, __LINE__);
3735                 rc = ENOMEM;
3736                 goto bce_dma_alloc_exit;
3737         }
3738
3739         for (i = 0; i < sc->rx_pages; i++) {
3740
3741                 if (bus_dmamem_alloc(sc->rx_bd_chain_tag,
3742                     (void **)&sc->rx_bd_chain[i],
3743                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3744                     &sc->rx_bd_chain_map[i])) {
3745                         BCE_PRINTF("%s(%d): Could not allocate RX descriptor "
3746                             "chain DMA memory!\n", __FILE__, __LINE__);
3747                         rc = ENOMEM;
3748                         goto bce_dma_alloc_exit;
3749                 }
3750
3751                 error = bus_dmamap_load(sc->rx_bd_chain_tag,
3752                     sc->rx_bd_chain_map[i], sc->rx_bd_chain[i],
3753                     BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3754                     &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3755
3756                 if (error || sc->rx_bd_chain_paddr[i] == 0) {
3757                         BCE_PRINTF("%s(%d): Could not map RX descriptor "
3758                             "chain DMA memory!\n", __FILE__, __LINE__);
3759                         rc = ENOMEM;
3760                         goto bce_dma_alloc_exit;
3761                 }
3762
3763                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = "
3764                     "0x%jX\n", __FUNCTION__, i,
3765                     (uintmax_t) sc->rx_bd_chain_paddr[i]);
3766         }
3767
3768         /*
3769          * Create a DMA tag for RX mbufs.
3770          */
3771         if (bce_hdr_split == TRUE)
3772                 max_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3773                     MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3774         else
3775                 max_size = MJUM9BYTES;
3776
3777         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
3778             "(max size = 0x%jX)\n", __FUNCTION__, (uintmax_t)max_size);
3779
3780         if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN,
3781             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3782             max_size, 1, max_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) {
3783                 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3784                     __FILE__, __LINE__);
3785                 rc = ENOMEM;
3786                 goto bce_dma_alloc_exit;
3787         }
3788
3789         /* Create DMA maps for the RX mbuf clusters. */
3790         for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) {
3791                 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT,
3792                     &sc->rx_mbuf_map[i])) {
3793                         BCE_PRINTF("%s(%d): Unable to create RX mbuf "
3794                             "DMA map!\n", __FILE__, __LINE__);
3795                         rc = ENOMEM;
3796                         goto bce_dma_alloc_exit;
3797                 }
3798         }
3799
3800         if (bce_hdr_split == TRUE) {
3801                 /*
3802                  * Create a DMA tag for the page buffer descriptor chain,
3803                  * allocate and clear the memory, and fetch the physical
3804                  * address of the blocks.
3805                  */
3806                 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3807                             BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr,
3808                             NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ,
3809                             0, NULL, NULL, &sc->pg_bd_chain_tag)) {
3810                         BCE_PRINTF("%s(%d): Could not allocate page descriptor "
3811                             "chain DMA tag!\n", __FILE__, __LINE__);
3812                         rc = ENOMEM;
3813                         goto bce_dma_alloc_exit;
3814                 }
3815
3816                 for (i = 0; i < sc->pg_pages; i++) {
3817                         if (bus_dmamem_alloc(sc->pg_bd_chain_tag,
3818                             (void **)&sc->pg_bd_chain[i],
3819                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3820                             &sc->pg_bd_chain_map[i])) {
3821                                 BCE_PRINTF("%s(%d): Could not allocate page "
3822                                     "descriptor chain DMA memory!\n",
3823                                     __FILE__, __LINE__);
3824                                 rc = ENOMEM;
3825                                 goto bce_dma_alloc_exit;
3826                         }
3827
3828                         error = bus_dmamap_load(sc->pg_bd_chain_tag,
3829                             sc->pg_bd_chain_map[i], sc->pg_bd_chain[i],
3830                             BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr,
3831                             &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3832
3833                         if (error || sc->pg_bd_chain_paddr[i] == 0) {
3834                                 BCE_PRINTF("%s(%d): Could not map page descriptor "
3835                                         "chain DMA memory!\n", __FILE__, __LINE__);
3836                                 rc = ENOMEM;
3837                                 goto bce_dma_alloc_exit;
3838                         }
3839
3840                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
3841                                 "0x%jX\n", __FUNCTION__, i,
3842                                 (uintmax_t) sc->pg_bd_chain_paddr[i]);
3843                 }
3844
3845                 /*
3846                  * Create a DMA tag for page mbufs.
3847                  */
3848                 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3849                     sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES,
3850                     1, MCLBYTES, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3851                         BCE_PRINTF("%s(%d): Could not allocate page mbuf "
3852                                 "DMA tag!\n", __FILE__, __LINE__);
3853                         rc = ENOMEM;
3854                         goto bce_dma_alloc_exit;
3855                 }
3856
3857                 /* Create DMA maps for the page mbuf clusters. */
3858                 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) {
3859                         if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT,
3860                                 &sc->pg_mbuf_map[i])) {
3861                                 BCE_PRINTF("%s(%d): Unable to create page mbuf "
3862                                         "DMA map!\n", __FILE__, __LINE__);
3863                                 rc = ENOMEM;
3864                                 goto bce_dma_alloc_exit;
3865                         }
3866                 }
3867         }
3868
3869 bce_dma_alloc_exit:
3870         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3871         return(rc);
3872 }
3873
3874
3875 /****************************************************************************/
3876 /* Release all resources used by the driver.                                */
3877 /*                                                                          */
3878 /* Releases all resources acquired by the driver including interrupts,      */
3879 /* interrupt handler, interfaces, mutexes, and DMA memory.                  */
3880 /*                                                                          */
3881 /* Returns:                                                                 */
3882 /*   Nothing.                                                               */
3883 /****************************************************************************/
3884 static void
3885 bce_release_resources(struct bce_softc *sc)
3886 {
3887         device_t dev;
3888
3889         DBENTER(BCE_VERBOSE_RESET);
3890
3891         dev = sc->bce_dev;
3892
3893         bce_dma_free(sc);
3894
3895         if (sc->bce_intrhand != NULL) {
3896                 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
3897                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3898         }
3899
3900         if (sc->bce_res_irq != NULL) {
3901                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
3902                 bus_release_resource(dev, SYS_RES_IRQ,
3903                     rman_get_rid(sc->bce_res_irq), sc->bce_res_irq);
3904         }
3905
3906         if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3907                 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
3908                 pci_release_msi(dev);
3909         }
3910
3911         if (sc->bce_res_mem != NULL) {
3912                 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
3913                     bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
3914                     sc->bce_res_mem);
3915         }
3916
3917         if (sc->bce_ifp != NULL) {
3918                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
3919                 if_free(sc->bce_ifp);
3920         }
3921
3922         if (mtx_initialized(&sc->bce_mtx))
3923                 BCE_LOCK_DESTROY(sc);
3924
3925         DBEXIT(BCE_VERBOSE_RESET);
3926 }
3927
3928
3929 /****************************************************************************/
3930 /* Firmware synchronization.                                                */
3931 /*                                                                          */
3932 /* Before performing certain events such as a chip reset, synchronize with  */
3933 /* the firmware first.                                                      */
3934 /*                                                                          */
3935 /* Returns:                                                                 */
3936 /*   0 for success, positive value for failure.                             */
3937 /****************************************************************************/
3938 static int
3939 bce_fw_sync(struct bce_softc *sc, u32 msg_data)
3940 {
3941         int i, rc = 0;
3942         u32 val;
3943
3944         DBENTER(BCE_VERBOSE_RESET);
3945
3946         /* Don't waste any time if we've timed out before. */
3947         if (sc->bce_fw_timed_out == TRUE) {
3948                 rc = EBUSY;
3949                 goto bce_fw_sync_exit;
3950         }
3951
3952         /* Increment the message sequence number. */
3953         sc->bce_fw_wr_seq++;
3954         msg_data |= sc->bce_fw_wr_seq;
3955
3956         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = "
3957             "0x%08X\n", msg_data);
3958
3959         /* Send the message to the bootcode driver mailbox. */
3960         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3961
3962         /* Wait for the bootcode to acknowledge the message. */
3963         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
3964                 /* Check for a response in the bootcode firmware mailbox. */
3965                 val = bce_shmem_rd(sc, BCE_FW_MB);
3966                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
3967                         break;
3968                 DELAY(1000);
3969         }
3970
3971         /* If we've timed out, tell bootcode that we've stopped waiting. */
3972         if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
3973             ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) {
3974
3975                 BCE_PRINTF("%s(%d): Firmware synchronization timeout! "
3976                     "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data);
3977
3978                 msg_data &= ~BCE_DRV_MSG_CODE;
3979                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
3980
3981                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3982
3983                 sc->bce_fw_timed_out = TRUE;
3984                 rc = EBUSY;
3985         }
3986
3987 bce_fw_sync_exit:
3988         DBEXIT(BCE_VERBOSE_RESET);
3989         return (rc);
3990 }
3991
3992
3993 /****************************************************************************/
3994 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
3995 /*                                                                          */
3996 /* Returns:                                                                 */
3997 /*   Nothing.                                                               */
3998 /****************************************************************************/
3999 static void
4000 bce_load_rv2p_fw(struct bce_softc *sc, const u32 *rv2p_code,
4001         u32 rv2p_code_len, u32 rv2p_proc)
4002 {
4003         int i;
4004         u32 val;
4005
4006         DBENTER(BCE_VERBOSE_RESET);
4007
4008         /* Set the page size used by RV2P. */
4009         if (rv2p_proc == RV2P_PROC2) {
4010                 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
4011         }
4012
4013         for (i = 0; i < rv2p_code_len; i += 8) {
4014                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
4015                 rv2p_code++;
4016                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
4017                 rv2p_code++;
4018
4019                 if (rv2p_proc == RV2P_PROC1) {
4020                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
4021                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
4022                 }
4023                 else {
4024                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
4025                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
4026                 }
4027         }
4028
4029         /* Reset the processor, un-stall is done later. */
4030         if (rv2p_proc == RV2P_PROC1) {
4031                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
4032         }
4033         else {
4034                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
4035         }
4036
4037         DBEXIT(BCE_VERBOSE_RESET);
4038 }
4039
4040
4041 /****************************************************************************/
4042 /* Load RISC processor firmware.                                            */
4043 /*                                                                          */
4044 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
4045 /* associated with a particular processor.                                  */
4046 /*                                                                          */
4047 /* Returns:                                                                 */
4048 /*   Nothing.                                                               */
4049 /****************************************************************************/
4050 static void
4051 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
4052         struct fw_info *fw)
4053 {
4054         u32 offset;
4055
4056         DBENTER(BCE_VERBOSE_RESET);
4057
4058     bce_halt_cpu(sc, cpu_reg);
4059
4060         /* Load the Text area. */
4061         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
4062         if (fw->text) {
4063                 int j;
4064
4065                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
4066                         REG_WR_IND(sc, offset, fw->text[j]);
4067                 }
4068         }
4069
4070         /* Load the Data area. */
4071         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
4072         if (fw->data) {
4073                 int j;
4074
4075                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
4076                         REG_WR_IND(sc, offset, fw->data[j]);
4077                 }
4078         }
4079
4080         /* Load the SBSS area. */
4081         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
4082         if (fw->sbss) {
4083                 int j;
4084
4085                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
4086                         REG_WR_IND(sc, offset, fw->sbss[j]);
4087                 }
4088         }
4089
4090         /* Load the BSS area. */
4091         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
4092         if (fw->bss) {
4093                 int j;
4094
4095                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
4096                         REG_WR_IND(sc, offset, fw->bss[j]);
4097                 }
4098         }
4099
4100         /* Load the Read-Only area. */
4101         offset = cpu_reg->spad_base +
4102                 (fw->rodata_addr - cpu_reg->mips_view_base);
4103         if (fw->rodata) {
4104                 int j;
4105
4106                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
4107                         REG_WR_IND(sc, offset, fw->rodata[j]);
4108                 }
4109         }
4110
4111         /* Clear the pre-fetch instruction and set the FW start address. */
4112         REG_WR_IND(sc, cpu_reg->inst, 0);
4113         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
4114
4115         DBEXIT(BCE_VERBOSE_RESET);
4116 }
4117
4118
4119 /****************************************************************************/
4120 /* Starts the RISC processor.                                               */
4121 /*                                                                          */
4122 /* Assumes the CPU starting address has already been set.                   */
4123 /*                                                                          */
4124 /* Returns:                                                                 */
4125 /*   Nothing.                                                               */
4126 /****************************************************************************/
4127 static void
4128 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4129 {
4130         u32 val;
4131
4132         DBENTER(BCE_VERBOSE_RESET);
4133
4134         /* Start the CPU. */
4135         val = REG_RD_IND(sc, cpu_reg->mode);
4136         val &= ~cpu_reg->mode_value_halt;
4137         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4138         REG_WR_IND(sc, cpu_reg->mode, val);
4139
4140         DBEXIT(BCE_VERBOSE_RESET);
4141 }
4142
4143
4144 /****************************************************************************/
4145 /* Halts the RISC processor.                                                */
4146 /*                                                                          */
4147 /* Returns:                                                                 */
4148 /*   Nothing.                                                               */
4149 /****************************************************************************/
4150 static void
4151 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4152 {
4153         u32 val;
4154
4155         DBENTER(BCE_VERBOSE_RESET);
4156
4157         /* Halt the CPU. */
4158         val = REG_RD_IND(sc, cpu_reg->mode);
4159         val |= cpu_reg->mode_value_halt;
4160         REG_WR_IND(sc, cpu_reg->mode, val);
4161         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4162
4163         DBEXIT(BCE_VERBOSE_RESET);
4164 }
4165
4166
4167 /****************************************************************************/
4168 /* Initialize the RX CPU.                                                   */
4169 /*                                                                          */
4170 /* Returns:                                                                 */
4171 /*   Nothing.                                                               */
4172 /****************************************************************************/
4173 static void
4174 bce_start_rxp_cpu(struct bce_softc *sc)
4175 {
4176         struct cpu_reg cpu_reg;
4177
4178         DBENTER(BCE_VERBOSE_RESET);
4179
4180         cpu_reg.mode = BCE_RXP_CPU_MODE;
4181         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4182         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4183         cpu_reg.state = BCE_RXP_CPU_STATE;
4184         cpu_reg.state_value_clear = 0xffffff;
4185         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4186         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4187         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4188         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4189         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4190         cpu_reg.spad_base = BCE_RXP_SCRATCH;
4191         cpu_reg.mips_view_base = 0x8000000;
4192
4193         DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n");
4194         bce_start_cpu(sc, &cpu_reg);
4195
4196         DBEXIT(BCE_VERBOSE_RESET);
4197 }
4198
4199
4200 /****************************************************************************/
4201 /* Initialize the RX CPU.                                                   */
4202 /*                                                                          */
4203 /* Returns:                                                                 */
4204 /*   Nothing.                                                               */
4205 /****************************************************************************/
4206 static void
4207 bce_init_rxp_cpu(struct bce_softc *sc)
4208 {
4209         struct cpu_reg cpu_reg;
4210         struct fw_info fw;
4211
4212         DBENTER(BCE_VERBOSE_RESET);
4213
4214         cpu_reg.mode = BCE_RXP_CPU_MODE;
4215         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4216         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4217         cpu_reg.state = BCE_RXP_CPU_STATE;
4218         cpu_reg.state_value_clear = 0xffffff;
4219         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4220         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4221         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4222         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4223         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4224         cpu_reg.spad_base = BCE_RXP_SCRATCH;
4225         cpu_reg.mips_view_base = 0x8000000;
4226
4227         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4228                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
4229                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
4230                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
4231                 fw.start_addr = bce_RXP_b09FwStartAddr;
4232
4233                 fw.text_addr = bce_RXP_b09FwTextAddr;
4234                 fw.text_len = bce_RXP_b09FwTextLen;
4235                 fw.text_index = 0;
4236                 fw.text = bce_RXP_b09FwText;
4237
4238                 fw.data_addr = bce_RXP_b09FwDataAddr;
4239                 fw.data_len = bce_RXP_b09FwDataLen;
4240                 fw.data_index = 0;
4241                 fw.data = bce_RXP_b09FwData;
4242
4243                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
4244                 fw.sbss_len = bce_RXP_b09FwSbssLen;
4245                 fw.sbss_index = 0;
4246                 fw.sbss = bce_RXP_b09FwSbss;
4247
4248                 fw.bss_addr = bce_RXP_b09FwBssAddr;
4249                 fw.bss_len = bce_RXP_b09FwBssLen;
4250                 fw.bss_index = 0;
4251                 fw.bss = bce_RXP_b09FwBss;
4252
4253                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
4254                 fw.rodata_len = bce_RXP_b09FwRodataLen;
4255                 fw.rodata_index = 0;
4256                 fw.rodata = bce_RXP_b09FwRodata;
4257         } else {
4258                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
4259                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
4260                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
4261                 fw.start_addr = bce_RXP_b06FwStartAddr;
4262
4263                 fw.text_addr = bce_RXP_b06FwTextAddr;
4264                 fw.text_len = bce_RXP_b06FwTextLen;
4265                 fw.text_index = 0;
4266                 fw.text = bce_RXP_b06FwText;
4267
4268                 fw.data_addr = bce_RXP_b06FwDataAddr;
4269                 fw.data_len = bce_RXP_b06FwDataLen;
4270                 fw.data_index = 0;
4271                 fw.data = bce_RXP_b06FwData;
4272
4273                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
4274                 fw.sbss_len = bce_RXP_b06FwSbssLen;
4275                 fw.sbss_index = 0;
4276                 fw.sbss = bce_RXP_b06FwSbss;
4277
4278                 fw.bss_addr = bce_RXP_b06FwBssAddr;
4279                 fw.bss_len = bce_RXP_b06FwBssLen;
4280                 fw.bss_index = 0;
4281                 fw.bss = bce_RXP_b06FwBss;
4282
4283                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
4284                 fw.rodata_len = bce_RXP_b06FwRodataLen;
4285                 fw.rodata_index = 0;
4286                 fw.rodata = bce_RXP_b06FwRodata;
4287         }
4288
4289         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
4290         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4291
4292     /* Delay RXP start until initialization is complete. */
4293
4294         DBEXIT(BCE_VERBOSE_RESET);
4295 }
4296
4297
4298 /****************************************************************************/
4299 /* Initialize the TX CPU.                                                   */
4300 /*                                                                          */
4301 /* Returns:                                                                 */
4302 /*   Nothing.                                                               */
4303 /****************************************************************************/
4304 static void
4305 bce_init_txp_cpu(struct bce_softc *sc)
4306 {
4307         struct cpu_reg cpu_reg;
4308         struct fw_info fw;
4309
4310         DBENTER(BCE_VERBOSE_RESET);
4311
4312         cpu_reg.mode = BCE_TXP_CPU_MODE;
4313         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
4314         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
4315         cpu_reg.state = BCE_TXP_CPU_STATE;
4316         cpu_reg.state_value_clear = 0xffffff;
4317         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
4318         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
4319         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
4320         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
4321         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
4322         cpu_reg.spad_base = BCE_TXP_SCRATCH;
4323         cpu_reg.mips_view_base = 0x8000000;
4324
4325         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4326                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
4327                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
4328                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
4329                 fw.start_addr = bce_TXP_b09FwStartAddr;
4330
4331                 fw.text_addr = bce_TXP_b09FwTextAddr;
4332                 fw.text_len = bce_TXP_b09FwTextLen;
4333                 fw.text_index = 0;
4334                 fw.text = bce_TXP_b09FwText;
4335
4336                 fw.data_addr = bce_TXP_b09FwDataAddr;
4337                 fw.data_len = bce_TXP_b09FwDataLen;
4338                 fw.data_index = 0;
4339                 fw.data = bce_TXP_b09FwData;
4340
4341                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
4342                 fw.sbss_len = bce_TXP_b09FwSbssLen;
4343                 fw.sbss_index = 0;
4344                 fw.sbss = bce_TXP_b09FwSbss;
4345
4346                 fw.bss_addr = bce_TXP_b09FwBssAddr;
4347                 fw.bss_len = bce_TXP_b09FwBssLen;
4348                 fw.bss_index = 0;
4349                 fw.bss = bce_TXP_b09FwBss;
4350
4351                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
4352                 fw.rodata_len = bce_TXP_b09FwRodataLen;
4353                 fw.rodata_index = 0;
4354                 fw.rodata = bce_TXP_b09FwRodata;
4355         } else {
4356                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
4357                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
4358                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
4359                 fw.start_addr = bce_TXP_b06FwStartAddr;
4360
4361                 fw.text_addr = bce_TXP_b06FwTextAddr;
4362                 fw.text_len = bce_TXP_b06FwTextLen;
4363                 fw.text_index = 0;
4364                 fw.text = bce_TXP_b06FwText;
4365
4366                 fw.data_addr = bce_TXP_b06FwDataAddr;
4367                 fw.data_len = bce_TXP_b06FwDataLen;
4368                 fw.data_index = 0;
4369                 fw.data = bce_TXP_b06FwData;
4370
4371                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
4372                 fw.sbss_len = bce_TXP_b06FwSbssLen;
4373                 fw.sbss_index = 0;
4374                 fw.sbss = bce_TXP_b06FwSbss;
4375
4376                 fw.bss_addr = bce_TXP_b06FwBssAddr;
4377                 fw.bss_len = bce_TXP_b06FwBssLen;
4378                 fw.bss_index = 0;
4379                 fw.bss = bce_TXP_b06FwBss;
4380
4381                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
4382                 fw.rodata_len = bce_TXP_b06FwRodataLen;
4383                 fw.rodata_index = 0;
4384                 fw.rodata = bce_TXP_b06FwRodata;
4385         }
4386
4387         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
4388         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4389     bce_start_cpu(sc, &cpu_reg);
4390
4391         DBEXIT(BCE_VERBOSE_RESET);
4392 }
4393
4394
4395 /****************************************************************************/
4396 /* Initialize the TPAT CPU.                                                 */
4397 /*                                                                          */
4398 /* Returns:                                                                 */
4399 /*   Nothing.                                                               */
4400 /****************************************************************************/
4401 static void
4402 bce_init_tpat_cpu(struct bce_softc *sc)
4403 {
4404         struct cpu_reg cpu_reg;
4405         struct fw_info fw;
4406
4407         DBENTER(BCE_VERBOSE_RESET);
4408
4409         cpu_reg.mode = BCE_TPAT_CPU_MODE;
4410         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4411         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4412         cpu_reg.state = BCE_TPAT_CPU_STATE;
4413         cpu_reg.state_value_clear = 0xffffff;
4414         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4415         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4416         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4417         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4418         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4419         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4420         cpu_reg.mips_view_base = 0x8000000;
4421
4422         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4423                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
4424                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
4425                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
4426                 fw.start_addr = bce_TPAT_b09FwStartAddr;
4427
4428                 fw.text_addr = bce_TPAT_b09FwTextAddr;
4429                 fw.text_len = bce_TPAT_b09FwTextLen;
4430                 fw.text_index = 0;
4431                 fw.text = bce_TPAT_b09FwText;
4432
4433                 fw.data_addr = bce_TPAT_b09FwDataAddr;
4434                 fw.data_len = bce_TPAT_b09FwDataLen;
4435                 fw.data_index = 0;
4436                 fw.data = bce_TPAT_b09FwData;
4437
4438                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
4439                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
4440                 fw.sbss_index = 0;
4441                 fw.sbss = bce_TPAT_b09FwSbss;
4442
4443                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
4444                 fw.bss_len = bce_TPAT_b09FwBssLen;
4445                 fw.bss_index = 0;
4446                 fw.bss = bce_TPAT_b09FwBss;
4447
4448                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
4449                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
4450                 fw.rodata_index = 0;
4451                 fw.rodata = bce_TPAT_b09FwRodata;
4452         } else {
4453                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
4454                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
4455                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
4456                 fw.start_addr = bce_TPAT_b06FwStartAddr;
4457
4458                 fw.text_addr = bce_TPAT_b06FwTextAddr;
4459                 fw.text_len = bce_TPAT_b06FwTextLen;
4460                 fw.text_index = 0;
4461                 fw.text = bce_TPAT_b06FwText;
4462
4463                 fw.data_addr = bce_TPAT_b06FwDataAddr;
4464                 fw.data_len = bce_TPAT_b06FwDataLen;
4465                 fw.data_index = 0;
4466                 fw.data = bce_TPAT_b06FwData;
4467
4468                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
4469                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
4470                 fw.sbss_index = 0;
4471                 fw.sbss = bce_TPAT_b06FwSbss;
4472
4473                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
4474                 fw.bss_len = bce_TPAT_b06FwBssLen;
4475                 fw.bss_index = 0;
4476                 fw.bss = bce_TPAT_b06FwBss;
4477
4478                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
4479                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
4480                 fw.rodata_index = 0;
4481                 fw.rodata = bce_TPAT_b06FwRodata;
4482         }
4483
4484         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
4485         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4486         bce_start_cpu(sc, &cpu_reg);
4487
4488         DBEXIT(BCE_VERBOSE_RESET);
4489 }
4490
4491
4492 /****************************************************************************/
4493 /* Initialize the CP CPU.                                                   */
4494 /*                                                                          */
4495 /* Returns:                                                                 */
4496 /*   Nothing.                                                               */
4497 /****************************************************************************/
4498 static void
4499 bce_init_cp_cpu(struct bce_softc *sc)
4500 {
4501         struct cpu_reg cpu_reg;
4502         struct fw_info fw;
4503
4504         DBENTER(BCE_VERBOSE_RESET);
4505
4506         cpu_reg.mode = BCE_CP_CPU_MODE;
4507         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4508         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4509         cpu_reg.state = BCE_CP_CPU_STATE;
4510         cpu_reg.state_value_clear = 0xffffff;
4511         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4512         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4513         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4514         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4515         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4516         cpu_reg.spad_base = BCE_CP_SCRATCH;
4517         cpu_reg.mips_view_base = 0x8000000;
4518
4519         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4520                 fw.ver_major = bce_CP_b09FwReleaseMajor;
4521                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
4522                 fw.ver_fix = bce_CP_b09FwReleaseFix;
4523                 fw.start_addr = bce_CP_b09FwStartAddr;
4524
4525                 fw.text_addr = bce_CP_b09FwTextAddr;
4526                 fw.text_len = bce_CP_b09FwTextLen;
4527                 fw.text_index = 0;
4528                 fw.text = bce_CP_b09FwText;
4529
4530                 fw.data_addr = bce_CP_b09FwDataAddr;
4531                 fw.data_len = bce_CP_b09FwDataLen;
4532                 fw.data_index = 0;
4533                 fw.data = bce_CP_b09FwData;
4534
4535                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
4536                 fw.sbss_len = bce_CP_b09FwSbssLen;
4537                 fw.sbss_index = 0;
4538                 fw.sbss = bce_CP_b09FwSbss;
4539
4540                 fw.bss_addr = bce_CP_b09FwBssAddr;
4541                 fw.bss_len = bce_CP_b09FwBssLen;
4542                 fw.bss_index = 0;
4543                 fw.bss = bce_CP_b09FwBss;
4544
4545                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
4546                 fw.rodata_len = bce_CP_b09FwRodataLen;
4547                 fw.rodata_index = 0;
4548                 fw.rodata = bce_CP_b09FwRodata;
4549         } else {
4550                 fw.ver_major = bce_CP_b06FwReleaseMajor;
4551                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
4552                 fw.ver_fix = bce_CP_b06FwReleaseFix;
4553                 fw.start_addr = bce_CP_b06FwStartAddr;
4554
4555                 fw.text_addr = bce_CP_b06FwTextAddr;
4556                 fw.text_len = bce_CP_b06FwTextLen;
4557                 fw.text_index = 0;
4558                 fw.text = bce_CP_b06FwText;
4559
4560                 fw.data_addr = bce_CP_b06FwDataAddr;
4561                 fw.data_len = bce_CP_b06FwDataLen;
4562                 fw.data_index = 0;
4563                 fw.data = bce_CP_b06FwData;
4564
4565                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
4566                 fw.sbss_len = bce_CP_b06FwSbssLen;
4567                 fw.sbss_index = 0;
4568                 fw.sbss = bce_CP_b06FwSbss;
4569
4570                 fw.bss_addr = bce_CP_b06FwBssAddr;
4571                 fw.bss_len = bce_CP_b06FwBssLen;
4572                 fw.bss_index = 0;
4573                 fw.bss = bce_CP_b06FwBss;
4574
4575                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
4576                 fw.rodata_len = bce_CP_b06FwRodataLen;
4577                 fw.rodata_index = 0;
4578                 fw.rodata = bce_CP_b06FwRodata;
4579         }
4580
4581         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
4582         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4583         bce_start_cpu(sc, &cpu_reg);
4584
4585         DBEXIT(BCE_VERBOSE_RESET);
4586 }
4587
4588
4589 /****************************************************************************/
4590 /* Initialize the COM CPU.                                                 */
4591 /*                                                                          */
4592 /* Returns:                                                                 */
4593 /*   Nothing.                                                               */
4594 /****************************************************************************/
4595 static void
4596 bce_init_com_cpu(struct bce_softc *sc)
4597 {
4598         struct cpu_reg cpu_reg;
4599         struct fw_info fw;
4600
4601         DBENTER(BCE_VERBOSE_RESET);
4602
4603         cpu_reg.mode = BCE_COM_CPU_MODE;
4604         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4605         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4606         cpu_reg.state = BCE_COM_CPU_STATE;
4607         cpu_reg.state_value_clear = 0xffffff;
4608         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4609         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4610         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4611         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4612         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4613         cpu_reg.spad_base = BCE_COM_SCRATCH;
4614         cpu_reg.mips_view_base = 0x8000000;
4615
4616         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4617                 fw.ver_major = bce_COM_b09FwReleaseMajor;
4618                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
4619                 fw.ver_fix = bce_COM_b09FwReleaseFix;
4620                 fw.start_addr = bce_COM_b09FwStartAddr;
4621
4622                 fw.text_addr = bce_COM_b09FwTextAddr;
4623                 fw.text_len = bce_COM_b09FwTextLen;
4624                 fw.text_index = 0;
4625                 fw.text = bce_COM_b09FwText;
4626
4627                 fw.data_addr = bce_COM_b09FwDataAddr;
4628                 fw.data_len = bce_COM_b09FwDataLen;
4629                 fw.data_index = 0;
4630                 fw.data = bce_COM_b09FwData;
4631
4632                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
4633                 fw.sbss_len = bce_COM_b09FwSbssLen;
4634                 fw.sbss_index = 0;
4635                 fw.sbss = bce_COM_b09FwSbss;
4636
4637                 fw.bss_addr = bce_COM_b09FwBssAddr;
4638                 fw.bss_len = bce_COM_b09FwBssLen;
4639                 fw.bss_index = 0;
4640                 fw.bss = bce_COM_b09FwBss;
4641
4642                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
4643                 fw.rodata_len = bce_COM_b09FwRodataLen;
4644                 fw.rodata_index = 0;
4645                 fw.rodata = bce_COM_b09FwRodata;
4646         } else {
4647                 fw.ver_major = bce_COM_b06FwReleaseMajor;
4648                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
4649                 fw.ver_fix = bce_COM_b06FwReleaseFix;
4650                 fw.start_addr = bce_COM_b06FwStartAddr;
4651
4652                 fw.text_addr = bce_COM_b06FwTextAddr;
4653                 fw.text_len = bce_COM_b06FwTextLen;
4654                 fw.text_index = 0;
4655                 fw.text = bce_COM_b06FwText;
4656
4657                 fw.data_addr = bce_COM_b06FwDataAddr;
4658                 fw.data_len = bce_COM_b06FwDataLen;
4659                 fw.data_index = 0;
4660                 fw.data = bce_COM_b06FwData;
4661
4662                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
4663                 fw.sbss_len = bce_COM_b06FwSbssLen;
4664                 fw.sbss_index = 0;
4665                 fw.sbss = bce_COM_b06FwSbss;
4666
4667                 fw.bss_addr = bce_COM_b06FwBssAddr;
4668                 fw.bss_len = bce_COM_b06FwBssLen;
4669                 fw.bss_index = 0;
4670                 fw.bss = bce_COM_b06FwBss;
4671
4672                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
4673                 fw.rodata_len = bce_COM_b06FwRodataLen;
4674                 fw.rodata_index = 0;
4675                 fw.rodata = bce_COM_b06FwRodata;
4676         }
4677
4678         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
4679         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4680         bce_start_cpu(sc, &cpu_reg);
4681
4682         DBEXIT(BCE_VERBOSE_RESET);
4683 }
4684
4685
4686 /****************************************************************************/
4687 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
4688 /*                                                                          */
4689 /* Loads the firmware for each CPU and starts the CPU.                      */
4690 /*                                                                          */
4691 /* Returns:                                                                 */
4692 /*   Nothing.                                                               */
4693 /****************************************************************************/
4694 static void
4695 bce_init_cpus(struct bce_softc *sc)
4696 {
4697         DBENTER(BCE_VERBOSE_RESET);
4698
4699         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4700
4701                 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) {
4702                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
4703                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
4704                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
4705                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
4706                 } else {
4707                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
4708                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
4709                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
4710                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
4711                 }
4712
4713         } else {
4714                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
4715                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
4716                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
4717                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
4718         }
4719
4720         bce_init_rxp_cpu(sc);
4721         bce_init_txp_cpu(sc);
4722         bce_init_tpat_cpu(sc);
4723         bce_init_com_cpu(sc);
4724         bce_init_cp_cpu(sc);
4725
4726         DBEXIT(BCE_VERBOSE_RESET);
4727 }
4728
4729
4730 /****************************************************************************/
4731 /* Initialize context memory.                                               */
4732 /*                                                                          */
4733 /* Clears the memory associated with each Context ID (CID).                 */
4734 /*                                                                          */
4735 /* Returns:                                                                 */
4736 /*   Nothing.                                                               */
4737 /****************************************************************************/
4738 static int
4739 bce_init_ctx(struct bce_softc *sc)
4740 {
4741         u32 offset, val, vcid_addr;
4742         int i, j, rc, retry_cnt;
4743
4744         rc = 0;
4745         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4746
4747         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4748                 retry_cnt = CTX_INIT_RETRY_COUNT;
4749
4750                 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n");
4751
4752                 /*
4753                  * BCM5709 context memory may be cached
4754                  * in host memory so prepare the host memory
4755                  * for access.
4756                  */
4757                 val = BCE_CTX_COMMAND_ENABLED |
4758                     BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
4759                 val |= (BCM_PAGE_BITS - 8) << 16;
4760                 REG_WR(sc, BCE_CTX_COMMAND, val);
4761
4762                 /* Wait for mem init command to complete. */
4763                 for (i = 0; i < retry_cnt; i++) {
4764                         val = REG_RD(sc, BCE_CTX_COMMAND);
4765                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4766                                 break;
4767                         DELAY(2);
4768                 }
4769                 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) {
4770                         BCE_PRINTF("%s(): Context memory initialization failed!\n",
4771                             __FUNCTION__);
4772                         rc = EBUSY;
4773                         goto init_ctx_fail;
4774                 }
4775
4776                 for (i = 0; i < sc->ctx_pages; i++) {
4777                         /* Set the physical address of the context memory. */
4778                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4779                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4780                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
4781                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4782                             BCE_ADDR_HI(sc->ctx_paddr[i]));
4783                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4784                             BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4785
4786                         /* Verify the context memory write was successful. */
4787                         for (j = 0; j < retry_cnt; j++) {
4788                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4789                                 if ((val &
4790                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4791                                         break;
4792                                 DELAY(5);
4793                         }
4794                         if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) {
4795                                 BCE_PRINTF("%s(): Failed to initialize "
4796                                     "context page %d!\n", __FUNCTION__, i);
4797                                 rc = EBUSY;
4798                                 goto init_ctx_fail;
4799                         }
4800                 }
4801         } else {
4802
4803                 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n");
4804
4805                 /*
4806                  * For the 5706/5708, context memory is local to
4807                  * the controller, so initialize the controller
4808                  * context memory.
4809                  */
4810
4811                 vcid_addr = GET_CID_ADDR(96);
4812                 while (vcid_addr) {
4813
4814                         vcid_addr -= PHY_CTX_SIZE;
4815
4816                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4817                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4818
4819                         for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4820                                 CTX_WR(sc, 0x00, offset, 0);
4821                         }
4822
4823                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4824                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4825                 }
4826
4827         }
4828 init_ctx_fail:
4829         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4830         return (rc);
4831 }
4832
4833
4834 /****************************************************************************/
4835 /* Fetch the permanent MAC address of the controller.                       */
4836 /*                                                                          */
4837 /* Returns:                                                                 */
4838 /*   Nothing.                                                               */
4839 /****************************************************************************/
4840 static void
4841 bce_get_mac_addr(struct bce_softc *sc)
4842 {
4843         u32 mac_lo = 0, mac_hi = 0;
4844
4845         DBENTER(BCE_VERBOSE_RESET);
4846
4847         /*
4848          * The NetXtreme II bootcode populates various NIC
4849          * power-on and runtime configuration items in a
4850          * shared memory area.  The factory configured MAC
4851          * address is available from both NVRAM and the
4852          * shared memory area so we'll read the value from
4853          * shared memory for speed.
4854          */
4855
4856         mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
4857         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
4858
4859         if ((mac_lo == 0) && (mac_hi == 0)) {
4860                 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
4861                     __FILE__, __LINE__);
4862         } else {
4863                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4864                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4865                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
4866                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
4867                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
4868                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4869         }
4870
4871         DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet "
4872             "address = %6D\n", sc->eaddr, ":");
4873         DBEXIT(BCE_VERBOSE_RESET);
4874 }
4875
4876
4877 /****************************************************************************/
4878 /* Program the MAC address.                                                 */
4879 /*                                                                          */
4880 /* Returns:                                                                 */
4881 /*   Nothing.                                                               */
4882 /****************************************************************************/
4883 static void
4884 bce_set_mac_addr(struct bce_softc *sc)
4885 {
4886         u32 val;
4887         u8 *mac_addr = sc->eaddr;
4888
4889         /* ToDo: Add support for setting multiple MAC addresses. */
4890
4891         DBENTER(BCE_VERBOSE_RESET);
4892         DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = "
4893             "%6D\n", sc->eaddr, ":");
4894
4895         val = (mac_addr[0] << 8) | mac_addr[1];
4896
4897         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4898
4899         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4900             (mac_addr[4] << 8) | mac_addr[5];
4901
4902         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4903
4904         DBEXIT(BCE_VERBOSE_RESET);
4905 }
4906
4907
4908 /****************************************************************************/
4909 /* Stop the controller.                                                     */
4910 /*                                                                          */
4911 /* Returns:                                                                 */
4912 /*   Nothing.                                                               */
4913 /****************************************************************************/
4914 static void
4915 bce_stop(struct bce_softc *sc)
4916 {
4917         struct ifnet *ifp;
4918
4919         DBENTER(BCE_VERBOSE_RESET);
4920
4921         BCE_LOCK_ASSERT(sc);
4922
4923         ifp = sc->bce_ifp;
4924
4925         callout_stop(&sc->bce_tick_callout);
4926
4927         /* Disable the transmit/receive blocks. */
4928         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
4929         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4930         DELAY(20);
4931
4932         bce_disable_intr(sc);
4933
4934         /* Free RX buffers. */
4935         if (bce_hdr_split == TRUE) {
4936                 bce_free_pg_chain(sc);
4937         }
4938         bce_free_rx_chain(sc);
4939
4940         /* Free TX buffers. */
4941         bce_free_tx_chain(sc);
4942
4943         sc->watchdog_timer = 0;
4944
4945         sc->bce_link_up = FALSE;
4946
4947         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4948
4949         DBEXIT(BCE_VERBOSE_RESET);
4950 }
4951
4952
4953 static int
4954 bce_reset(struct bce_softc *sc, u32 reset_code)
4955 {
4956         u32 emac_mode_save, val;
4957         int i, rc = 0;
4958         static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT |
4959             BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G;
4960
4961         DBENTER(BCE_VERBOSE_RESET);
4962
4963         DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
4964             __FUNCTION__, reset_code);
4965
4966         /*
4967          * If ASF/IPMI is operational, then the EMAC Mode register already
4968          * contains appropriate values for the link settings that have
4969          * been auto-negotiated.  Resetting the chip will clobber those
4970          * values.  Save the important bits so we can restore them after
4971          * the reset.
4972          */
4973         emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask;
4974
4975         /* Wait for pending PCI transactions to complete. */
4976         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
4977             BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4978             BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4979             BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4980             BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4981         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4982         DELAY(5);
4983
4984         /* Disable DMA */
4985         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4986                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
4987                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
4988                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
4989         }
4990
4991         /* Assume bootcode is running. */
4992         sc->bce_fw_timed_out = FALSE;
4993         sc->bce_drv_cardiac_arrest = FALSE;
4994
4995         /* Give the firmware a chance to prepare for the reset. */
4996         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
4997         if (rc)
4998                 goto bce_reset_exit;
4999
5000         /* Set a firmware reminder that this is a soft reset. */
5001         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC);
5002
5003         /* Dummy read to force the chip to complete all current transactions. */
5004         val = REG_RD(sc, BCE_MISC_ID);
5005
5006         /* Chip reset. */
5007         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5008                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
5009                 REG_RD(sc, BCE_MISC_COMMAND);
5010                 DELAY(5);
5011
5012                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5013                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5014
5015                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
5016         } else {
5017                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5018                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5019                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5020                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
5021
5022                 /* Allow up to 30us for reset to complete. */
5023                 for (i = 0; i < 10; i++) {
5024                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
5025                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5026                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
5027                                 break;
5028                         }
5029                         DELAY(10);
5030                 }
5031
5032                 /* Check that reset completed successfully. */
5033                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5034                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
5035                         BCE_PRINTF("%s(%d): Reset failed!\n",
5036                             __FILE__, __LINE__);
5037                         rc = EBUSY;
5038                         goto bce_reset_exit;
5039                 }
5040         }
5041
5042         /* Make sure byte swapping is properly configured. */
5043         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
5044         if (val != 0x01020304) {
5045                 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
5046                     __FILE__, __LINE__);
5047                 rc = ENODEV;
5048                 goto bce_reset_exit;
5049         }
5050
5051         /* Just completed a reset, assume that firmware is running again. */
5052         sc->bce_fw_timed_out = FALSE;
5053         sc->bce_drv_cardiac_arrest = FALSE;
5054
5055         /* Wait for the firmware to finish its initialization. */
5056         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
5057         if (rc)
5058                 BCE_PRINTF("%s(%d): Firmware did not complete "
5059                     "initialization!\n", __FILE__, __LINE__);
5060         /* Get firmware capabilities. */
5061         bce_fw_cap_init(sc);
5062
5063 bce_reset_exit:
5064         /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */
5065         val = REG_RD(sc, BCE_EMAC_MODE);
5066         val = (val & ~emac_mode_mask) | emac_mode_save;
5067         REG_WR(sc, BCE_EMAC_MODE, val);
5068
5069         DBEXIT(BCE_VERBOSE_RESET);
5070         return (rc);
5071 }
5072
5073
5074 static int
5075 bce_chipinit(struct bce_softc *sc)
5076 {
5077         u32 val;
5078         int rc = 0;
5079
5080         DBENTER(BCE_VERBOSE_RESET);
5081
5082         bce_disable_intr(sc);
5083
5084         /*
5085          * Initialize DMA byte/word swapping, configure the number of DMA
5086          * channels and PCI clock compensation delay.
5087          */
5088         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
5089             BCE_DMA_CONFIG_DATA_WORD_SWAP |
5090 #if BYTE_ORDER == BIG_ENDIAN
5091             BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
5092 #endif
5093             BCE_DMA_CONFIG_CNTL_WORD_SWAP |
5094             DMA_READ_CHANS << 12 |
5095             DMA_WRITE_CHANS << 16;
5096
5097         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
5098
5099         if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
5100                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
5101
5102         /*
5103          * This setting resolves a problem observed on certain Intel PCI
5104          * chipsets that cannot handle multiple outstanding DMA operations.
5105          * See errata E9_5706A1_65.
5106          */
5107         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5108             (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
5109             !(sc->bce_flags & BCE_PCIX_FLAG))
5110                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
5111
5112         REG_WR(sc, BCE_DMA_CONFIG, val);
5113
5114         /* Enable the RX_V2P and Context state machines before access. */
5115         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5116             BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
5117             BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
5118             BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
5119
5120         /* Initialize context mapping and zero out the quick contexts. */
5121         if ((rc = bce_init_ctx(sc)) != 0)
5122                 goto bce_chipinit_exit;
5123
5124         /* Initialize the on-boards CPUs */
5125         bce_init_cpus(sc);
5126
5127         /* Enable management frames (NC-SI) to flow to the MCP. */
5128         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5129                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5130                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5131         }
5132
5133         /* Prepare NVRAM for access. */
5134         if ((rc = bce_init_nvram(sc)) != 0)
5135                 goto bce_chipinit_exit;
5136
5137         /* Set the kernel bypass block size */
5138         val = REG_RD(sc, BCE_MQ_CONFIG);
5139         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
5140         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
5141
5142         /* Enable bins used on the 5709. */
5143         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5144                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
5145                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
5146                         val |= BCE_MQ_CONFIG_HALT_DIS;
5147         }
5148
5149         REG_WR(sc, BCE_MQ_CONFIG, val);
5150
5151         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
5152         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
5153         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
5154
5155         /* Set the page size and clear the RV2P processor stall bits. */
5156         val = (BCM_PAGE_BITS - 8) << 24;
5157         REG_WR(sc, BCE_RV2P_CONFIG, val);
5158
5159         /* Configure page size. */
5160         val = REG_RD(sc, BCE_TBDR_CONFIG);
5161         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
5162         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
5163         REG_WR(sc, BCE_TBDR_CONFIG, val);
5164
5165         /* Set the perfect match control register to default. */
5166         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
5167
5168 bce_chipinit_exit:
5169         DBEXIT(BCE_VERBOSE_RESET);
5170
5171         return(rc);
5172 }
5173
5174
5175 /****************************************************************************/
5176 /* Initialize the controller in preparation to send/receive traffic.        */
5177 /*                                                                          */
5178 /* Returns:                                                                 */
5179 /*   0 for success, positive value for failure.                             */
5180 /****************************************************************************/
5181 static int
5182 bce_blockinit(struct bce_softc *sc)
5183 {
5184         u32 reg, val;
5185         int rc = 0;
5186
5187         DBENTER(BCE_VERBOSE_RESET);
5188
5189         /* Load the hardware default MAC address. */
5190         bce_set_mac_addr(sc);
5191
5192         /* Set the Ethernet backoff seed value */
5193         val = sc->eaddr[0]         + (sc->eaddr[1] << 8) +
5194               (sc->eaddr[2] << 16) + (sc->eaddr[3]     ) +
5195               (sc->eaddr[4] << 8)  + (sc->eaddr[5] << 16);
5196         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
5197
5198         sc->last_status_idx = 0;
5199         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
5200
5201         /* Set up link change interrupt generation. */
5202         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
5203
5204         /* Program the physical address of the status block. */
5205         REG_WR(sc, BCE_HC_STATUS_ADDR_L,
5206             BCE_ADDR_LO(sc->status_block_paddr));
5207         REG_WR(sc, BCE_HC_STATUS_ADDR_H,
5208             BCE_ADDR_HI(sc->status_block_paddr));
5209
5210         /* Program the physical address of the statistics block. */
5211         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
5212             BCE_ADDR_LO(sc->stats_block_paddr));
5213         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
5214             BCE_ADDR_HI(sc->stats_block_paddr));
5215
5216         /*
5217          * Program various host coalescing parameters.
5218          * Trip points control how many BDs should be ready before generating
5219          * an interrupt while ticks control how long a BD can sit in the chain
5220          * before generating an interrupt.
5221          */
5222         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5223             (sc->bce_tx_quick_cons_trip_int << 16) |
5224             sc->bce_tx_quick_cons_trip);
5225         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5226             (sc->bce_rx_quick_cons_trip_int << 16) |
5227             sc->bce_rx_quick_cons_trip);
5228         REG_WR(sc, BCE_HC_TX_TICKS,
5229             (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
5230         REG_WR(sc, BCE_HC_RX_TICKS,
5231             (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
5232         REG_WR(sc, BCE_HC_STATS_TICKS, sc->bce_stats_ticks & 0xffff00);
5233         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
5234         /* Not used for L2. */
5235         REG_WR(sc, BCE_HC_COMP_PROD_TRIP, 0);
5236         REG_WR(sc, BCE_HC_COM_TICKS, 0);
5237         REG_WR(sc, BCE_HC_CMD_TICKS, 0);
5238
5239         /* Configure the Host Coalescing block. */
5240         val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
5241             BCE_HC_CONFIG_COLLECT_STATS;
5242
5243 #if 0
5244         /* ToDo: Add MSI-X support. */
5245         if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
5246                 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
5247                     BCE_HC_SB_CONFIG_1;
5248
5249                 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
5250
5251                 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
5252                     BCE_HC_SB_CONFIG_1_ONE_SHOT);
5253
5254                 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
5255                     (sc->tx_quick_cons_trip_int << 16) |
5256                      sc->tx_quick_cons_trip);
5257
5258                 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
5259                     (sc->tx_ticks_int << 16) | sc->tx_ticks);
5260
5261                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5262         }
5263
5264         /*
5265          * Tell the HC block to automatically set the
5266          * INT_MASK bit after an MSI/MSI-X interrupt
5267          * is generated so the driver doesn't have to.
5268          */
5269         if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
5270                 val |= BCE_HC_CONFIG_ONE_SHOT;
5271
5272         /* Set the MSI-X status blocks to 128 byte boundaries. */
5273         if (sc->bce_flags & BCE_USING_MSIX_FLAG)
5274                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5275 #endif
5276
5277         REG_WR(sc, BCE_HC_CONFIG, val);
5278
5279         /* Clear the internal statistics counters. */
5280         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
5281
5282         /* Verify that bootcode is running. */
5283         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
5284
5285         DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control),
5286             BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
5287             __FILE__, __LINE__);
5288             reg = 0);
5289
5290         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5291             BCE_DEV_INFO_SIGNATURE_MAGIC) {
5292                 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
5293                     "Expected: 08%08X\n", __FILE__, __LINE__,
5294                     (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
5295                     BCE_DEV_INFO_SIGNATURE_MAGIC);
5296                 rc = ENODEV;
5297                 goto bce_blockinit_exit;
5298         }
5299
5300         /* Enable DMA */
5301         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5302                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5303                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5304                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5305         }
5306
5307         /* Allow bootcode to apply additional fixes before enabling MAC. */
5308         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 |
5309             BCE_DRV_MSG_CODE_RESET);
5310
5311         /* Enable link state change interrupt generation. */
5312         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
5313
5314         /* Enable the RXP. */
5315         bce_start_rxp_cpu(sc);
5316
5317         /* Disable management frames (NC-SI) from flowing to the MCP. */
5318         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5319                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
5320                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5321                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5322         }
5323
5324         /* Enable all remaining blocks in the MAC. */
5325         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
5326                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5327                     BCE_MISC_ENABLE_DEFAULT_XI);
5328         else
5329                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5330                     BCE_MISC_ENABLE_DEFAULT);
5331
5332         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
5333         DELAY(20);
5334
5335         /* Save the current host coalescing block settings. */
5336         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
5337
5338 bce_blockinit_exit:
5339         DBEXIT(BCE_VERBOSE_RESET);
5340
5341         return (rc);
5342 }
5343
5344
5345 /****************************************************************************/
5346 /* Encapsulate an mbuf into the rx_bd chain.                                */
5347 /*                                                                          */
5348 /* Returns:                                                                 */
5349 /*   0 for success, positive value for failure.                             */
5350 /****************************************************************************/
5351 static int
5352 bce_get_rx_buf(struct bce_softc *sc, u16 prod, u16 chain_prod, u32 *prod_bseq)
5353 {
5354         bus_dma_segment_t segs[1];
5355         struct mbuf *m_new = NULL;
5356         struct rx_bd *rxbd;
5357         int nsegs, error, rc = 0;
5358 #ifdef BCE_DEBUG
5359         u16 debug_chain_prod = chain_prod;
5360 #endif
5361
5362         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5363
5364         /* Make sure the inputs are valid. */
5365         DBRUNIF((chain_prod > MAX_RX_BD_ALLOC),
5366             BCE_PRINTF("%s(%d): RX producer out of range: "
5367             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5368             chain_prod, (u16)MAX_RX_BD_ALLOC));
5369
5370         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5371             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__,
5372             prod, chain_prod, *prod_bseq);
5373
5374         /* Update some debug statistic counters */
5375         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5376             sc->rx_low_watermark = sc->free_rx_bd);
5377         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
5378             sc->rx_empty_count++);
5379
5380         /* Simulate an mbuf allocation failure. */
5381         DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5382             sc->mbuf_alloc_failed_count++;
5383             sc->mbuf_alloc_failed_sim_count++;
5384             rc = ENOBUFS;
5385             goto bce_get_rx_buf_exit);
5386
5387         /* This is a new mbuf allocation. */
5388         if (bce_hdr_split == TRUE)
5389                 MGETHDR(m_new, M_NOWAIT, MT_DATA);
5390         else
5391                 m_new = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR,
5392                     sc->rx_bd_mbuf_alloc_size);
5393
5394         if (m_new == NULL) {
5395                 sc->mbuf_alloc_failed_count++;
5396                 rc = ENOBUFS;
5397                 goto bce_get_rx_buf_exit;
5398         }
5399
5400         DBRUN(sc->debug_rx_mbuf_alloc++);
5401
5402         /* Make sure we have a valid packet header. */
5403         M_ASSERTPKTHDR(m_new);
5404
5405         /* Initialize the mbuf size and pad if necessary for alignment. */
5406         m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size;
5407         m_adj(m_new, sc->rx_bd_mbuf_align_pad);
5408
5409         /* ToDo: Consider calling m_fragment() to test error handling. */
5410
5411         /* Map the mbuf cluster into device memory. */
5412         error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag,
5413             sc->rx_mbuf_map[chain_prod], m_new, segs, &nsegs, BUS_DMA_NOWAIT);
5414
5415         /* Handle any mapping errors. */
5416         if (error) {
5417                 BCE_PRINTF("%s(%d): Error mapping mbuf into RX "
5418                     "chain (%d)!\n", __FILE__, __LINE__, error);
5419
5420                 sc->dma_map_addr_rx_failed_count++;
5421                 m_freem(m_new);
5422
5423                 DBRUN(sc->debug_rx_mbuf_alloc--);
5424
5425                 rc = ENOBUFS;
5426                 goto bce_get_rx_buf_exit;
5427         }
5428
5429         /* All mbufs must map to a single segment. */
5430         KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5431             __FUNCTION__, nsegs));
5432
5433         /* Setup the rx_bd for the segment. */
5434         rxbd = &sc->rx_bd_chain[RX_PAGE(chain_prod)][RX_IDX(chain_prod)];
5435
5436         rxbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5437         rxbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5438         rxbd->rx_bd_len       = htole32(segs[0].ds_len);
5439         rxbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5440         *prod_bseq += segs[0].ds_len;
5441
5442         /* Save the mbuf and update our counter. */
5443         sc->rx_mbuf_ptr[chain_prod] = m_new;
5444         sc->free_rx_bd -= nsegs;
5445
5446         DBRUNMSG(BCE_INSANE_RECV,
5447             bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs));
5448
5449         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5450             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__, prod,
5451             chain_prod, *prod_bseq);
5452
5453 bce_get_rx_buf_exit:
5454         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5455
5456         return(rc);
5457 }
5458
5459
5460 /****************************************************************************/
5461 /* Encapsulate an mbuf cluster into the page chain.                         */
5462 /*                                                                          */
5463 /* Returns:                                                                 */
5464 /*   0 for success, positive value for failure.                             */
5465 /****************************************************************************/
5466 static int
5467 bce_get_pg_buf(struct bce_softc *sc, u16 prod, u16 prod_idx)
5468 {
5469         bus_addr_t busaddr;
5470         struct mbuf *m_new = NULL;
5471         struct rx_bd *pgbd;
5472         int error, rc = 0;
5473 #ifdef BCE_DEBUG
5474         u16 debug_prod_idx = prod_idx;
5475 #endif
5476
5477         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5478
5479         /* Make sure the inputs are valid. */
5480         DBRUNIF((prod_idx > MAX_PG_BD_ALLOC),
5481             BCE_PRINTF("%s(%d): page producer out of range: "
5482             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5483             prod_idx, (u16)MAX_PG_BD_ALLOC));
5484
5485         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5486             "chain_prod = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5487
5488         /* Update counters if we've hit a new low or run out of pages. */
5489         DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
5490             sc->pg_low_watermark = sc->free_pg_bd);
5491         DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
5492
5493         /* Simulate an mbuf allocation failure. */
5494         DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5495             sc->mbuf_alloc_failed_count++;
5496             sc->mbuf_alloc_failed_sim_count++;
5497             rc = ENOBUFS;
5498             goto bce_get_pg_buf_exit);
5499
5500         /* This is a new mbuf allocation. */
5501         m_new = m_getcl(M_NOWAIT, MT_DATA, 0);
5502         if (m_new == NULL) {
5503                 sc->mbuf_alloc_failed_count++;
5504                 rc = ENOBUFS;
5505                 goto bce_get_pg_buf_exit;
5506         }
5507
5508         DBRUN(sc->debug_pg_mbuf_alloc++);
5509
5510         m_new->m_len = MCLBYTES;
5511
5512         /* ToDo: Consider calling m_fragment() to test error handling. */
5513
5514         /* Map the mbuf cluster into device memory. */
5515         error = bus_dmamap_load(sc->pg_mbuf_tag, sc->pg_mbuf_map[prod_idx],
5516             mtod(m_new, void *), MCLBYTES, bce_dma_map_addr, &busaddr,
5517             BUS_DMA_NOWAIT);
5518
5519         /* Handle any mapping errors. */
5520         if (error || busaddr == 0) {
5521                 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
5522                     __FILE__, __LINE__);
5523
5524                 m_freem(m_new);
5525                 DBRUN(sc->debug_pg_mbuf_alloc--);
5526
5527                 rc = ENOBUFS;
5528                 goto bce_get_pg_buf_exit;
5529         }
5530
5531         /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */
5532
5533         /*
5534          * The page chain uses the same rx_bd data structure
5535          * as the receive chain but doesn't require a byte sequence (bseq).
5536          */
5537         pgbd = &sc->pg_bd_chain[PG_PAGE(prod_idx)][PG_IDX(prod_idx)];
5538
5539         pgbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(busaddr));
5540         pgbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(busaddr));
5541         pgbd->rx_bd_len       = htole32(MCLBYTES);
5542         pgbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5543
5544         /* Save the mbuf and update our counter. */
5545         sc->pg_mbuf_ptr[prod_idx] = m_new;
5546         sc->free_pg_bd--;
5547
5548         DBRUNMSG(BCE_INSANE_RECV,
5549             bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1));
5550
5551         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5552             "prod_idx = 0x%04X\n", __FUNCTION__, prod, prod_idx);
5553
5554 bce_get_pg_buf_exit:
5555         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5556
5557         return(rc);
5558 }
5559
5560
5561 /****************************************************************************/
5562 /* Initialize the TX context memory.                                        */
5563 /*                                                                          */
5564 /* Returns:                                                                 */
5565 /*   Nothing                                                                */
5566 /****************************************************************************/
5567 static void
5568 bce_init_tx_context(struct bce_softc *sc)
5569 {
5570         u32 val;
5571
5572         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5573
5574         /* Initialize the context ID for an L2 TX chain. */
5575         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5576                 /* Set the CID type to support an L2 connection. */
5577                 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI |
5578                     BCE_L2CTX_TX_TYPE_SIZE_L2_XI;
5579                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
5580                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16);
5581                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5582                     BCE_L2CTX_TX_CMD_TYPE_XI, val);
5583
5584                 /* Point the hardware to the first page in the chain. */
5585                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5586                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5587                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
5588                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5589                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5590                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
5591         } else {
5592                 /* Set the CID type to support an L2 connection. */
5593                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
5594                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
5595                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
5596                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
5597
5598                 /* Point the hardware to the first page in the chain. */
5599                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5600                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5601                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
5602                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5603                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5604                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
5605         }
5606
5607         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5608 }
5609
5610
5611 /****************************************************************************/
5612 /* Allocate memory and initialize the TX data structures.                   */
5613 /*                                                                          */
5614 /* Returns:                                                                 */
5615 /*   0 for success, positive value for failure.                             */
5616 /****************************************************************************/
5617 static int
5618 bce_init_tx_chain(struct bce_softc *sc)
5619 {
5620         struct tx_bd *txbd;
5621         int i, rc = 0;
5622
5623         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5624
5625         /* Set the initial TX producer/consumer indices. */
5626         sc->tx_prod        = 0;
5627         sc->tx_cons        = 0;
5628         sc->tx_prod_bseq   = 0;
5629         sc->used_tx_bd     = 0;
5630         sc->max_tx_bd      = USABLE_TX_BD_ALLOC;
5631         DBRUN(sc->tx_hi_watermark = 0);
5632         DBRUN(sc->tx_full_count = 0);
5633
5634         /*
5635          * The NetXtreme II supports a linked-list structre called
5636          * a Buffer Descriptor Chain (or BD chain).  A BD chain
5637          * consists of a series of 1 or more chain pages, each of which
5638          * consists of a fixed number of BD entries.
5639          * The last BD entry on each page is a pointer to the next page
5640          * in the chain, and the last pointer in the BD chain
5641          * points back to the beginning of the chain.
5642          */
5643
5644         /* Set the TX next pointer chain entries. */
5645         for (i = 0; i < sc->tx_pages; i++) {
5646                 int j;
5647
5648                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
5649
5650                 /* Check if we've reached the last page. */
5651                 if (i == (sc->tx_pages - 1))
5652                         j = 0;
5653                 else
5654                         j = i + 1;
5655
5656                 txbd->tx_bd_haddr_hi =
5657                     htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5658                 txbd->tx_bd_haddr_lo =
5659                     htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5660         }
5661
5662         bce_init_tx_context(sc);
5663
5664         DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC));
5665         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5666
5667         return(rc);
5668 }
5669
5670
5671 /****************************************************************************/
5672 /* Free memory and clear the TX data structures.                            */
5673 /*                                                                          */
5674 /* Returns:                                                                 */
5675 /*   Nothing.                                                               */
5676 /****************************************************************************/
5677 static void
5678 bce_free_tx_chain(struct bce_softc *sc)
5679 {
5680         int i;
5681
5682         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5683
5684         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
5685         for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
5686                 if (sc->tx_mbuf_ptr[i] != NULL) {
5687                         if (sc->tx_mbuf_map[i] != NULL)
5688                                 bus_dmamap_sync(sc->tx_mbuf_tag,
5689                                     sc->tx_mbuf_map[i],
5690                                     BUS_DMASYNC_POSTWRITE);
5691                         m_freem(sc->tx_mbuf_ptr[i]);
5692                         sc->tx_mbuf_ptr[i] = NULL;
5693                         DBRUN(sc->debug_tx_mbuf_alloc--);
5694                 }
5695         }
5696
5697         /* Clear each TX chain page. */
5698         for (i = 0; i < sc->tx_pages; i++)
5699                 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5700
5701         sc->used_tx_bd = 0;
5702
5703         /* Check if we lost any mbufs in the process. */
5704         DBRUNIF((sc->debug_tx_mbuf_alloc),
5705             BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
5706             "from tx chain!\n", __FILE__, __LINE__,
5707             sc->debug_tx_mbuf_alloc));
5708
5709         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5710 }
5711
5712
5713 /****************************************************************************/
5714 /* Initialize the RX context memory.                                        */
5715 /*                                                                          */
5716 /* Returns:                                                                 */
5717 /*   Nothing                                                                */
5718 /****************************************************************************/
5719 static void
5720 bce_init_rx_context(struct bce_softc *sc)
5721 {
5722         u32 val;
5723
5724         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5725
5726         /* Init the type, size, and BD cache levels for the RX context. */
5727         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5728             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 |
5729             (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT);
5730
5731         /*
5732          * Set the level for generating pause frames
5733          * when the number of available rx_bd's gets
5734          * too low (the low watermark) and the level
5735          * when pause frames can be stopped (the high
5736          * watermark).
5737          */
5738         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5739                 u32 lo_water, hi_water;
5740
5741                 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) {
5742                         lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
5743                 } else {
5744                         lo_water = 0;
5745                 }
5746
5747                 if (lo_water >= USABLE_RX_BD_ALLOC) {
5748                         lo_water = 0;
5749                 }
5750
5751                 hi_water = USABLE_RX_BD_ALLOC / 4;
5752
5753                 if (hi_water <= lo_water) {
5754                         lo_water = 0;
5755                 }
5756
5757                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
5758                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
5759
5760                 if (hi_water > 0xf)
5761                         hi_water = 0xf;
5762                 else if (hi_water == 0)
5763                         lo_water = 0;
5764
5765                 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) |
5766                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
5767         }
5768
5769         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
5770
5771         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
5772         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5773                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5774                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5775         }
5776
5777         /* Point the hardware to the first page in the chain. */
5778         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5779         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
5780         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5781         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
5782
5783         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5784 }
5785
5786
5787 /****************************************************************************/
5788 /* Allocate memory and initialize the RX data structures.                   */
5789 /*                                                                          */
5790 /* Returns:                                                                 */
5791 /*   0 for success, positive value for failure.                             */
5792 /****************************************************************************/
5793 static int
5794 bce_init_rx_chain(struct bce_softc *sc)
5795 {
5796         struct rx_bd *rxbd;
5797         int i, rc = 0;
5798
5799         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5800             BCE_VERBOSE_CTX);
5801
5802         /* Initialize the RX producer and consumer indices. */
5803         sc->rx_prod        = 0;
5804         sc->rx_cons        = 0;
5805         sc->rx_prod_bseq   = 0;
5806         sc->free_rx_bd     = USABLE_RX_BD_ALLOC;
5807         sc->max_rx_bd      = USABLE_RX_BD_ALLOC;
5808
5809         /* Initialize the RX next pointer chain entries. */
5810         for (i = 0; i < sc->rx_pages; i++) {
5811                 int j;
5812
5813                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
5814
5815                 /* Check if we've reached the last page. */
5816                 if (i == (sc->rx_pages - 1))
5817                         j = 0;
5818                 else
5819                         j = i + 1;
5820
5821                 /* Setup the chain page pointers. */
5822                 rxbd->rx_bd_haddr_hi =
5823                     htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5824                 rxbd->rx_bd_haddr_lo =
5825                     htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5826         }
5827
5828         /* Fill up the RX chain. */
5829         bce_fill_rx_chain(sc);
5830
5831         DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC);
5832         DBRUN(sc->rx_empty_count = 0);
5833         for (i = 0; i < sc->rx_pages; i++) {
5834                 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
5835                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5836         }
5837
5838         bce_init_rx_context(sc);
5839
5840         DBRUNMSG(BCE_EXTREME_RECV,
5841             bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC));
5842         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5843             BCE_VERBOSE_CTX);
5844
5845         /* ToDo: Are there possible failure modes here? */
5846
5847         return(rc);
5848 }
5849
5850
5851 /****************************************************************************/
5852 /* Add mbufs to the RX chain until its full or an mbuf allocation error     */
5853 /* occurs.                                                                  */
5854 /*                                                                          */
5855 /* Returns:                                                                 */
5856 /*   Nothing                                                                */
5857 /****************************************************************************/
5858 static void
5859 bce_fill_rx_chain(struct bce_softc *sc)
5860 {
5861         u16 prod, prod_idx;
5862         u32 prod_bseq;
5863
5864         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5865             BCE_VERBOSE_CTX);
5866
5867         /* Get the RX chain producer indices. */
5868         prod      = sc->rx_prod;
5869         prod_bseq = sc->rx_prod_bseq;
5870
5871         /* Keep filling the RX chain until it's full. */
5872         while (sc->free_rx_bd > 0) {
5873                 prod_idx = RX_CHAIN_IDX(prod);
5874                 if (bce_get_rx_buf(sc, prod, prod_idx, &prod_bseq)) {
5875                         /* Bail out if we can't add an mbuf to the chain. */
5876                         break;
5877                 }
5878                 prod = NEXT_RX_BD(prod);
5879         }
5880
5881         /* Save the RX chain producer indices. */
5882         sc->rx_prod      = prod;
5883         sc->rx_prod_bseq = prod_bseq;
5884
5885         /* We should never end up pointing to a next page pointer. */
5886         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5887             BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5888             __FUNCTION__, rx_prod));
5889
5890         /* Write the mailbox and tell the chip about the waiting rx_bd's. */
5891         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BDIDX, prod);
5892         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_BSEQ, prod_bseq);
5893
5894         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5895             BCE_VERBOSE_CTX);
5896 }
5897
5898
5899 /****************************************************************************/
5900 /* Free memory and clear the RX data structures.                            */
5901 /*                                                                          */
5902 /* Returns:                                                                 */
5903 /*   Nothing.                                                               */
5904 /****************************************************************************/
5905 static void
5906 bce_free_rx_chain(struct bce_softc *sc)
5907 {
5908         int i;
5909
5910         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5911
5912         /* Free any mbufs still in the RX mbuf chain. */
5913         for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
5914                 if (sc->rx_mbuf_ptr[i] != NULL) {
5915                         if (sc->rx_mbuf_map[i] != NULL)
5916                                 bus_dmamap_sync(sc->rx_mbuf_tag,
5917                                     sc->rx_mbuf_map[i],
5918                                     BUS_DMASYNC_POSTREAD);
5919                         m_freem(sc->rx_mbuf_ptr[i]);
5920                         sc->rx_mbuf_ptr[i] = NULL;
5921                         DBRUN(sc->debug_rx_mbuf_alloc--);
5922                 }
5923         }
5924
5925         /* Clear each RX chain page. */
5926         for (i = 0; i < sc->rx_pages; i++)
5927                 if (sc->rx_bd_chain[i] != NULL)
5928                         bzero((char *)sc->rx_bd_chain[i],
5929                             BCE_RX_CHAIN_PAGE_SZ);
5930
5931         sc->free_rx_bd = sc->max_rx_bd;
5932
5933         /* Check if we lost any mbufs in the process. */
5934         DBRUNIF((sc->debug_rx_mbuf_alloc),
5935             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5936             __FUNCTION__, sc->debug_rx_mbuf_alloc));
5937
5938         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5939 }
5940
5941
5942 /****************************************************************************/
5943 /* Allocate memory and initialize the page data structures.                 */
5944 /* Assumes that bce_init_rx_chain() has not already been called.            */
5945 /*                                                                          */
5946 /* Returns:                                                                 */
5947 /*   0 for success, positive value for failure.                             */
5948 /****************************************************************************/
5949 static int
5950 bce_init_pg_chain(struct bce_softc *sc)
5951 {
5952         struct rx_bd *pgbd;
5953         int i, rc = 0;
5954         u32 val;
5955
5956         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5957                 BCE_VERBOSE_CTX);
5958
5959         /* Initialize the page producer and consumer indices. */
5960         sc->pg_prod        = 0;
5961         sc->pg_cons        = 0;
5962         sc->free_pg_bd     = USABLE_PG_BD_ALLOC;
5963         sc->max_pg_bd      = USABLE_PG_BD_ALLOC;
5964         DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
5965         DBRUN(sc->pg_empty_count = 0);
5966
5967         /* Initialize the page next pointer chain entries. */
5968         for (i = 0; i < sc->pg_pages; i++) {
5969                 int j;
5970
5971                 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE];
5972
5973                 /* Check if we've reached the last page. */
5974                 if (i == (sc->pg_pages - 1))
5975                         j = 0;
5976                 else
5977                         j = i + 1;
5978
5979                 /* Setup the chain page pointers. */
5980                 pgbd->rx_bd_haddr_hi =
5981                     htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
5982                 pgbd->rx_bd_haddr_lo =
5983                     htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
5984         }
5985
5986         /* Setup the MQ BIN mapping for host_pg_bidx. */
5987         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
5988                 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
5989
5990         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
5991
5992         /* Configure the rx_bd and page chain mbuf cluster size. */
5993         val = (sc->rx_bd_mbuf_data_len << 16) | MCLBYTES;
5994         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
5995
5996         /* Configure the context reserved for jumbo support. */
5997         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
5998                 BCE_L2CTX_RX_RBDC_JUMBO_KEY);
5999
6000         /* Point the hardware to the first page in the page chain. */
6001         val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
6002         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val);
6003         val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
6004         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val);
6005
6006         /* Fill up the page chain. */
6007         bce_fill_pg_chain(sc);
6008
6009         for (i = 0; i < sc->pg_pages; i++) {
6010                 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i],
6011                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6012         }
6013
6014         DBRUNMSG(BCE_EXTREME_RECV,
6015             bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC));
6016         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
6017                 BCE_VERBOSE_CTX);
6018         return(rc);
6019 }
6020
6021
6022 /****************************************************************************/
6023 /* Add mbufs to the page chain until its full or an mbuf allocation error   */
6024 /* occurs.                                                                  */
6025 /*                                                                          */
6026 /* Returns:                                                                 */
6027 /*   Nothing                                                                */
6028 /****************************************************************************/
6029 static void
6030 bce_fill_pg_chain(struct bce_softc *sc)
6031 {
6032         u16 prod, prod_idx;
6033
6034         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6035             BCE_VERBOSE_CTX);
6036
6037         /* Get the page chain prodcuer index. */
6038         prod = sc->pg_prod;
6039
6040         /* Keep filling the page chain until it's full. */
6041         while (sc->free_pg_bd > 0) {
6042                 prod_idx = PG_CHAIN_IDX(prod);
6043                 if (bce_get_pg_buf(sc, prod, prod_idx)) {
6044                         /* Bail out if we can't add an mbuf to the chain. */
6045                         break;
6046                 }
6047                 prod = NEXT_PG_BD(prod);
6048         }
6049
6050         /* Save the page chain producer index. */
6051         sc->pg_prod = prod;
6052
6053         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
6054             BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
6055             __FUNCTION__, pg_prod));
6056
6057         /*
6058          * Write the mailbox and tell the chip about
6059          * the new rx_bd's in the page chain.
6060          */
6061         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) + BCE_L2MQ_RX_HOST_PG_BDIDX,
6062             prod);
6063
6064         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6065             BCE_VERBOSE_CTX);
6066 }
6067
6068
6069 /****************************************************************************/
6070 /* Free memory and clear the RX data structures.                            */
6071 /*                                                                          */
6072 /* Returns:                                                                 */
6073 /*   Nothing.                                                               */
6074 /****************************************************************************/
6075 static void
6076 bce_free_pg_chain(struct bce_softc *sc)
6077 {
6078         int i;
6079
6080         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6081
6082         /* Free any mbufs still in the mbuf page chain. */
6083         for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
6084                 if (sc->pg_mbuf_ptr[i] != NULL) {
6085                         if (sc->pg_mbuf_map[i] != NULL)
6086                                 bus_dmamap_sync(sc->pg_mbuf_tag,
6087                                     sc->pg_mbuf_map[i],
6088                                     BUS_DMASYNC_POSTREAD);
6089                         m_freem(sc->pg_mbuf_ptr[i]);
6090                         sc->pg_mbuf_ptr[i] = NULL;
6091                         DBRUN(sc->debug_pg_mbuf_alloc--);
6092                 }
6093         }
6094
6095         /* Clear each page chain pages. */
6096         for (i = 0; i < sc->pg_pages; i++)
6097                 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
6098
6099         sc->free_pg_bd = sc->max_pg_bd;
6100
6101         /* Check if we lost any mbufs in the process. */
6102         DBRUNIF((sc->debug_pg_mbuf_alloc),
6103             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
6104             __FUNCTION__, sc->debug_pg_mbuf_alloc));
6105
6106         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6107 }
6108
6109
6110 static u32
6111 bce_get_rphy_link(struct bce_softc *sc)
6112 {
6113         u32 advertise, link;
6114         int fdpx;
6115
6116         advertise = 0;
6117         fdpx = 0;
6118         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0)
6119                 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK);
6120         else
6121                 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK);
6122         if (link & BCE_NETLINK_ANEG_ENB)
6123                 advertise |= BCE_NETLINK_ANEG_ENB;
6124         if (link & BCE_NETLINK_SPEED_10HALF)
6125                 advertise |= BCE_NETLINK_SPEED_10HALF;
6126         if (link & BCE_NETLINK_SPEED_10FULL) {
6127                 advertise |= BCE_NETLINK_SPEED_10FULL;
6128                 fdpx++;
6129         }
6130         if (link & BCE_NETLINK_SPEED_100HALF)
6131                 advertise |= BCE_NETLINK_SPEED_100HALF;
6132         if (link & BCE_NETLINK_SPEED_100FULL) {
6133                 advertise |= BCE_NETLINK_SPEED_100FULL;
6134                 fdpx++;
6135         }
6136         if (link & BCE_NETLINK_SPEED_1000HALF)
6137                 advertise |= BCE_NETLINK_SPEED_1000HALF;
6138         if (link & BCE_NETLINK_SPEED_1000FULL) {
6139                 advertise |= BCE_NETLINK_SPEED_1000FULL;
6140                 fdpx++;
6141         }
6142         if (link & BCE_NETLINK_SPEED_2500HALF)
6143                 advertise |= BCE_NETLINK_SPEED_2500HALF;
6144         if (link & BCE_NETLINK_SPEED_2500FULL) {
6145                 advertise |= BCE_NETLINK_SPEED_2500FULL;
6146                 fdpx++;
6147         }
6148         if (fdpx)
6149                 advertise |= BCE_NETLINK_FC_PAUSE_SYM |
6150                     BCE_NETLINK_FC_PAUSE_ASYM;
6151         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6152                 advertise |= BCE_NETLINK_PHY_APP_REMOTE |
6153                     BCE_NETLINK_ETH_AT_WIRESPEED;
6154
6155         return (advertise);
6156 }
6157
6158
6159 /****************************************************************************/
6160 /* Set media options.                                                       */
6161 /*                                                                          */
6162 /* Returns:                                                                 */
6163 /*   0 for success, positive value for failure.                             */
6164 /****************************************************************************/
6165 static int
6166 bce_ifmedia_upd(struct ifnet *ifp)
6167 {
6168         struct bce_softc *sc = ifp->if_softc;
6169         int error;
6170
6171         DBENTER(BCE_VERBOSE);
6172
6173         BCE_LOCK(sc);
6174         error = bce_ifmedia_upd_locked(ifp);
6175         BCE_UNLOCK(sc);
6176
6177         DBEXIT(BCE_VERBOSE);
6178         return (error);
6179 }
6180
6181
6182 /****************************************************************************/
6183 /* Set media options.                                                       */
6184 /*                                                                          */
6185 /* Returns:                                                                 */
6186 /*   Nothing.                                                               */
6187 /****************************************************************************/
6188 static int
6189 bce_ifmedia_upd_locked(struct ifnet *ifp)
6190 {
6191         struct bce_softc *sc = ifp->if_softc;
6192         struct mii_data *mii;
6193         struct mii_softc *miisc;
6194         struct ifmedia *ifm;
6195         u32 link;
6196         int error, fdx;
6197
6198         DBENTER(BCE_VERBOSE_PHY);
6199
6200         error = 0;
6201         BCE_LOCK_ASSERT(sc);
6202
6203         sc->bce_link_up = FALSE;
6204         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6205                 ifm = &sc->bce_ifmedia;
6206                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
6207                         return (EINVAL);
6208                 link = 0;
6209                 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX;
6210                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
6211                 case IFM_AUTO:
6212                         /*
6213                          * Check advertised link of remote PHY by reading
6214                          * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK.
6215                          * Always use the same link type of remote PHY.
6216                          */
6217                         link = bce_get_rphy_link(sc);
6218                         break;
6219                 case IFM_2500_SX:
6220                         if ((sc->bce_phy_flags &
6221                             (BCE_PHY_REMOTE_PORT_FIBER_FLAG |
6222                             BCE_PHY_2_5G_CAPABLE_FLAG)) == 0)
6223                                 return (EINVAL);
6224                         /*
6225                          * XXX
6226                          * Have to enable forced 2.5Gbps configuration.
6227                          */
6228                         if (fdx != 0)
6229                                 link |= BCE_NETLINK_SPEED_2500FULL;
6230                         else
6231                                 link |= BCE_NETLINK_SPEED_2500HALF;
6232                         break;
6233                 case IFM_1000_SX:
6234                         if ((sc->bce_phy_flags &
6235                             BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6236                                 return (EINVAL);
6237                         /*
6238                          * XXX
6239                          * Have to disable 2.5Gbps configuration.
6240                          */
6241                         if (fdx != 0)
6242                                 link = BCE_NETLINK_SPEED_1000FULL;
6243                         else
6244                                 link = BCE_NETLINK_SPEED_1000HALF;
6245                         break;
6246                 case IFM_1000_T:
6247                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6248                                 return (EINVAL);
6249                         if (fdx != 0)
6250                                 link = BCE_NETLINK_SPEED_1000FULL;
6251                         else
6252                                 link = BCE_NETLINK_SPEED_1000HALF;
6253                         break;
6254                 case IFM_100_TX:
6255                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6256                                 return (EINVAL);
6257                         if (fdx != 0)
6258                                 link = BCE_NETLINK_SPEED_100FULL;
6259                         else
6260                                 link = BCE_NETLINK_SPEED_100HALF;
6261                         break;
6262                 case IFM_10_T:
6263                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6264                                 return (EINVAL);
6265                         if (fdx != 0)
6266                                 link = BCE_NETLINK_SPEED_10FULL;
6267                         else
6268                                 link = BCE_NETLINK_SPEED_10HALF;
6269                         break;
6270                 default:
6271                         return (EINVAL);
6272                 }
6273                 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) {
6274                         /*
6275                          * XXX
6276                          * Advertise pause capability for full-duplex media.
6277                          */
6278                         if (fdx != 0)
6279                                 link |= BCE_NETLINK_FC_PAUSE_SYM |
6280                                     BCE_NETLINK_FC_PAUSE_ASYM;
6281                         if ((sc->bce_phy_flags &
6282                             BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6283                                 link |= BCE_NETLINK_PHY_APP_REMOTE |
6284                                     BCE_NETLINK_ETH_AT_WIRESPEED;
6285                 }
6286
6287                 bce_shmem_wr(sc, BCE_MB_ARGS_0, link);
6288                 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK);
6289         } else {
6290                 mii = device_get_softc(sc->bce_miibus);
6291
6292                 /* Make sure the MII bus has been enumerated. */
6293                 if (mii) {
6294                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
6295                                 PHY_RESET(miisc);
6296                         error = mii_mediachg(mii);
6297                 }
6298         }
6299
6300         DBEXIT(BCE_VERBOSE_PHY);
6301         return (error);
6302 }
6303
6304
6305 static void
6306 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr)
6307 {
6308         struct ifnet *ifp;
6309         u32 link;
6310
6311         ifp = sc->bce_ifp;
6312         BCE_LOCK_ASSERT(sc);
6313
6314         ifmr->ifm_status = IFM_AVALID;
6315         ifmr->ifm_active = IFM_ETHER;
6316         link = bce_shmem_rd(sc, BCE_LINK_STATUS);
6317         /* XXX Handle heart beat status? */
6318         if ((link & BCE_LINK_STATUS_LINK_UP) != 0)
6319                 ifmr->ifm_status |= IFM_ACTIVE;
6320         else {
6321                 ifmr->ifm_active |= IFM_NONE;
6322                 ifp->if_baudrate = 0;
6323                 return;
6324         }
6325         switch (link & BCE_LINK_STATUS_SPEED_MASK) {
6326         case BCE_LINK_STATUS_10HALF:
6327                 ifmr->ifm_active |= IFM_10_T | IFM_HDX;
6328                 ifp->if_baudrate = IF_Mbps(10UL);
6329                 break;
6330         case BCE_LINK_STATUS_10FULL:
6331                 ifmr->ifm_active |= IFM_10_T | IFM_FDX;
6332                 ifp->if_baudrate = IF_Mbps(10UL);
6333                 break;
6334         case BCE_LINK_STATUS_100HALF:
6335                 ifmr->ifm_active |= IFM_100_TX | IFM_HDX;
6336                 ifp->if_baudrate = IF_Mbps(100UL);
6337                 break;
6338         case BCE_LINK_STATUS_100FULL:
6339                 ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
6340                 ifp->if_baudrate = IF_Mbps(100UL);
6341                 break;
6342         case BCE_LINK_STATUS_1000HALF:
6343                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6344                         ifmr->ifm_active |= IFM_1000_T | IFM_HDX;
6345                 else
6346                         ifmr->ifm_active |= IFM_1000_SX | IFM_HDX;
6347                 ifp->if_baudrate = IF_Mbps(1000UL);
6348                 break;
6349         case BCE_LINK_STATUS_1000FULL:
6350                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6351                         ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
6352                 else
6353                         ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
6354                 ifp->if_baudrate = IF_Mbps(1000UL);
6355                 break;
6356         case BCE_LINK_STATUS_2500HALF:
6357                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6358                         ifmr->ifm_active |= IFM_NONE;
6359                         return;
6360                 } else
6361                         ifmr->ifm_active |= IFM_2500_SX | IFM_HDX;
6362                 ifp->if_baudrate = IF_Mbps(2500UL);
6363                 break;
6364         case BCE_LINK_STATUS_2500FULL:
6365                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6366                         ifmr->ifm_active |= IFM_NONE;
6367                         return;
6368                 } else
6369                         ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
6370                 ifp->if_baudrate = IF_Mbps(2500UL);
6371                 break;
6372         default:
6373                 ifmr->ifm_active |= IFM_NONE;
6374                 return;
6375         }
6376
6377         if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0)
6378                 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
6379         if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0)
6380                 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
6381 }
6382
6383
6384 /****************************************************************************/
6385 /* Reports current media status.                                            */
6386 /*                                                                          */
6387 /* Returns:                                                                 */
6388 /*   Nothing.                                                               */
6389 /****************************************************************************/
6390 static void
6391 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
6392 {
6393         struct bce_softc *sc = ifp->if_softc;
6394         struct mii_data *mii;
6395
6396         DBENTER(BCE_VERBOSE_PHY);
6397
6398         BCE_LOCK(sc);
6399
6400         if ((ifp->if_flags & IFF_UP) == 0) {
6401                 BCE_UNLOCK(sc);
6402                 return;
6403         }
6404
6405         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
6406                 bce_ifmedia_sts_rphy(sc, ifmr);
6407         else {
6408                 mii = device_get_softc(sc->bce_miibus);
6409                 mii_pollstat(mii);
6410                 ifmr->ifm_active = mii->mii_media_active;
6411                 ifmr->ifm_status = mii->mii_media_status;
6412         }
6413
6414         BCE_UNLOCK(sc);
6415
6416         DBEXIT(BCE_VERBOSE_PHY);
6417 }
6418
6419
6420 /****************************************************************************/
6421 /* Handles PHY generated interrupt events.                                  */
6422 /*                                                                          */
6423 /* Returns:                                                                 */
6424 /*   Nothing.                                                               */
6425 /****************************************************************************/
6426 static void
6427 bce_phy_intr(struct bce_softc *sc)
6428 {
6429         u32 new_link_state, old_link_state;
6430
6431         DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6432
6433         DBRUN(sc->phy_interrupts++);
6434
6435         new_link_state = sc->status_block->status_attn_bits &
6436             STATUS_ATTN_BITS_LINK_STATE;
6437         old_link_state = sc->status_block->status_attn_bits_ack &
6438             STATUS_ATTN_BITS_LINK_STATE;
6439
6440         /* Handle any changes if the link state has changed. */
6441         if (new_link_state != old_link_state) {
6442
6443                 /* Update the status_attn_bits_ack field. */
6444                 if (new_link_state) {
6445                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
6446                             STATUS_ATTN_BITS_LINK_STATE);
6447                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n",
6448                             __FUNCTION__);
6449                 } else {
6450                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
6451                             STATUS_ATTN_BITS_LINK_STATE);
6452                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
6453                             __FUNCTION__);
6454                 }
6455
6456                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6457                         if (new_link_state) {
6458                                 if (bootverbose)
6459                                         if_printf(sc->bce_ifp, "link UP\n");
6460                                 if_link_state_change(sc->bce_ifp,
6461                                     LINK_STATE_UP);
6462                         } else {
6463                                 if (bootverbose)
6464                                         if_printf(sc->bce_ifp, "link DOWN\n");
6465                                 if_link_state_change(sc->bce_ifp,
6466                                     LINK_STATE_DOWN);
6467                         }
6468                 }
6469                 /*
6470                  * Assume link is down and allow
6471                  * tick routine to update the state
6472                  * based on the actual media state.
6473                  */
6474                 sc->bce_link_up = FALSE;
6475                 callout_stop(&sc->bce_tick_callout);
6476                 bce_tick(sc);
6477         }
6478
6479         /* Acknowledge the link change interrupt. */
6480         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
6481
6482         DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6483 }
6484
6485
6486 /****************************************************************************/
6487 /* Reads the receive consumer value from the status block (skipping over    */
6488 /* chain page pointer if necessary).                                        */
6489 /*                                                                          */
6490 /* Returns:                                                                 */
6491 /*   hw_cons                                                                */
6492 /****************************************************************************/
6493 static inline u16
6494 bce_get_hw_rx_cons(struct bce_softc *sc)
6495 {
6496         u16 hw_cons;
6497
6498         rmb();
6499         hw_cons = sc->status_block->status_rx_quick_consumer_index0;
6500         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
6501                 hw_cons++;
6502
6503         return hw_cons;
6504 }
6505
6506 /****************************************************************************/
6507 /* Handles received frame interrupt events.                                 */
6508 /*                                                                          */
6509 /* Returns:                                                                 */
6510 /*   Nothing.                                                               */
6511 /****************************************************************************/
6512 static void
6513 bce_rx_intr(struct bce_softc *sc)
6514 {
6515         struct ifnet *ifp = sc->bce_ifp;
6516         struct l2_fhdr *l2fhdr;
6517         struct ether_vlan_header *vh;
6518         unsigned int pkt_len;
6519         u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
6520         u32 status;
6521         unsigned int rem_len;
6522         u16 sw_pg_cons, sw_pg_cons_idx;
6523
6524         DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6525         DBRUN(sc->interrupts_rx++);
6526         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
6527             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6528             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6529
6530         /* Prepare the RX chain pages to be accessed by the host CPU. */
6531         for (int i = 0; i < sc->rx_pages; i++)
6532                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6533                     sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6534
6535         /* Prepare the page chain pages to be accessed by the host CPU. */
6536         if (bce_hdr_split == TRUE) {
6537                 for (int i = 0; i < sc->pg_pages; i++)
6538                         bus_dmamap_sync(sc->pg_bd_chain_tag,
6539                             sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6540         }
6541
6542         /* Get the hardware's view of the RX consumer index. */
6543         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6544
6545         /* Get working copies of the driver's view of the consumer indices. */
6546         sw_rx_cons = sc->rx_cons;
6547         sw_pg_cons = sc->pg_cons;
6548
6549         /* Update some debug statistics counters */
6550         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
6551             sc->rx_low_watermark = sc->free_rx_bd);
6552         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
6553             sc->rx_empty_count++);
6554
6555         /* Scan through the receive chain as long as there is work to do */
6556         /* ToDo: Consider setting a limit on the number of packets processed. */
6557         rmb();
6558         while (sw_rx_cons != hw_rx_cons) {
6559                 struct mbuf *m0;
6560
6561                 /* Convert the producer/consumer indices to an actual rx_bd index. */
6562                 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
6563
6564                 /* Unmap the mbuf from DMA space. */
6565                 bus_dmamap_sync(sc->rx_mbuf_tag,
6566                     sc->rx_mbuf_map[sw_rx_cons_idx],
6567                     BUS_DMASYNC_POSTREAD);
6568                 bus_dmamap_unload(sc->rx_mbuf_tag,
6569                     sc->rx_mbuf_map[sw_rx_cons_idx]);
6570
6571                 /* Remove the mbuf from the RX chain. */
6572                 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
6573                 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
6574                 DBRUN(sc->debug_rx_mbuf_alloc--);
6575                 sc->free_rx_bd++;
6576
6577                 /*
6578                  * Frames received on the NetXteme II are prepended
6579                  * with an l2_fhdr structure which provides status
6580                  * information about the received frame (including
6581                  * VLAN tags and checksum info).  The frames are
6582                  * also automatically adjusted to word align the IP
6583                  * header (i.e. two null bytes are inserted before
6584                  * the Ethernet header).  As a result the data
6585                  * DMA'd by the controller into the mbuf looks
6586                  * like this:
6587                  *
6588                  * +---------+-----+---------------------+-----+
6589                  * | l2_fhdr | pad | packet data         | FCS |
6590                  * +---------+-----+---------------------+-----+
6591                  *
6592                  * The l2_fhdr needs to be checked and skipped and
6593                  * the FCS needs to be stripped before sending the
6594                  * packet up the stack.
6595                  */
6596                 l2fhdr  = mtod(m0, struct l2_fhdr *);
6597
6598                 /* Get the packet data + FCS length and the status. */
6599                 pkt_len = l2fhdr->l2_fhdr_pkt_len;
6600                 status  = l2fhdr->l2_fhdr_status;
6601
6602                 /*
6603                  * Skip over the l2_fhdr and pad, resulting in the
6604                  * following data in the mbuf:
6605                  * +---------------------+-----+
6606                  * | packet data         | FCS |
6607                  * +---------------------+-----+
6608                  */
6609                 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
6610
6611                 /*
6612                  * When split header mode is used, an ethernet frame
6613                  * may be split across the receive chain and the
6614                  * page chain. If that occurs an mbuf cluster must be
6615                  * reassembled from the individual mbuf pieces.
6616                  */
6617                 if (bce_hdr_split == TRUE) {
6618                         /*
6619                          * Check whether the received frame fits in a single
6620                          * mbuf or not (i.e. packet data + FCS <=
6621                          * sc->rx_bd_mbuf_data_len bytes).
6622                          */
6623                         if (pkt_len > m0->m_len) {
6624                                 /*
6625                                  * The received frame is larger than a single mbuf.
6626                                  * If the frame was a TCP frame then only the TCP
6627                                  * header is placed in the mbuf, the remaining
6628                                  * payload (including FCS) is placed in the page
6629                                  * chain, the SPLIT flag is set, and the header
6630                                  * length is placed in the IP checksum field.
6631                                  * If the frame is not a TCP frame then the mbuf
6632                                  * is filled and the remaining bytes are placed
6633                                  * in the page chain.
6634                                  */
6635
6636                                 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large "
6637                                         "packet.\n", __FUNCTION__);
6638                                 DBRUN(sc->split_header_frames_rcvd++);
6639
6640                                 /*
6641                                  * When the page chain is enabled and the TCP
6642                                  * header has been split from the TCP payload,
6643                                  * the ip_xsum structure will reflect the length
6644                                  * of the TCP header, not the IP checksum.  Set
6645                                  * the packet length of the mbuf accordingly.
6646                                  */
6647                                 if (status & L2_FHDR_STATUS_SPLIT) {
6648                                         m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
6649                                         DBRUN(sc->split_header_tcp_frames_rcvd++);
6650                                 }
6651
6652                                 rem_len = pkt_len - m0->m_len;
6653
6654                                 /* Pull mbufs off the page chain for any remaining data. */
6655                                 while (rem_len > 0) {
6656                                         struct mbuf *m_pg;
6657
6658                                         sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
6659
6660                                         /* Remove the mbuf from the page chain. */
6661                                         m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
6662                                         sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
6663                                         DBRUN(sc->debug_pg_mbuf_alloc--);
6664                                         sc->free_pg_bd++;
6665
6666                                         /* Unmap the page chain mbuf from DMA space. */
6667                                         bus_dmamap_sync(sc->pg_mbuf_tag,
6668                                                 sc->pg_mbuf_map[sw_pg_cons_idx],
6669                                                 BUS_DMASYNC_POSTREAD);
6670                                         bus_dmamap_unload(sc->pg_mbuf_tag,
6671                                                 sc->pg_mbuf_map[sw_pg_cons_idx]);
6672
6673                                         /* Adjust the mbuf length. */
6674                                         if (rem_len < m_pg->m_len) {
6675                                                 /* The mbuf chain is complete. */
6676                                                 m_pg->m_len = rem_len;
6677                                                 rem_len = 0;
6678                                         } else {
6679                                                 /* More packet data is waiting. */
6680                                                 rem_len -= m_pg->m_len;
6681                                         }
6682
6683                                         /* Concatenate the mbuf cluster to the mbuf. */
6684                                         m_cat(m0, m_pg);
6685
6686                                         sw_pg_cons = NEXT_PG_BD(sw_pg_cons);
6687                                 }
6688
6689                                 /* Set the total packet length. */
6690                                 m0->m_pkthdr.len = pkt_len;
6691
6692                         } else {
6693                                 /*
6694                                  * The received packet is small and fits in a
6695                                  * single mbuf (i.e. the l2_fhdr + pad + packet +
6696                                  * FCS <= MHLEN).  In other words, the packet is
6697                                  * 154 bytes or less in size.
6698                                  */
6699
6700                                 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small "
6701                                         "packet.\n", __FUNCTION__);
6702
6703                                 /* Set the total packet length. */
6704                                 m0->m_pkthdr.len = m0->m_len = pkt_len;
6705                         }
6706                 } else
6707                         /* Set the total packet length. */
6708                         m0->m_pkthdr.len = m0->m_len = pkt_len;
6709
6710                 /* Remove the trailing Ethernet FCS. */
6711                 m_adj(m0, -ETHER_CRC_LEN);
6712
6713                 /* Check that the resulting mbuf chain is valid. */
6714                 DBRUN(m_sanity(m0, FALSE));
6715                 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
6716                     (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
6717                     BCE_PRINTF("Invalid Ethernet frame size!\n");
6718                     m_print(m0, 128));
6719
6720                 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control),
6721                     sc->l2fhdr_error_sim_count++;
6722                     status = status | L2_FHDR_ERRORS_PHY_DECODE);
6723
6724                 /* Check the received frame for errors. */
6725                 if (status & (L2_FHDR_ERRORS_BAD_CRC |
6726                     L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
6727                     L2_FHDR_ERRORS_TOO_SHORT  | L2_FHDR_ERRORS_GIANT_FRAME)) {
6728
6729                         /* Log the error and release the mbuf. */
6730                         ifp->if_ierrors++;
6731                         sc->l2fhdr_error_count++;
6732
6733                         m_freem(m0);
6734                         m0 = NULL;
6735                         goto bce_rx_intr_next_rx;
6736                 }
6737
6738                 /* Send the packet to the appropriate interface. */
6739                 m0->m_pkthdr.rcvif = ifp;
6740
6741                 /* Assume no hardware checksum. */
6742                 m0->m_pkthdr.csum_flags = 0;
6743
6744                 /* Validate the checksum if offload enabled. */
6745                 if (ifp->if_capenable & IFCAP_RXCSUM) {
6746                         /* Check for an IP datagram. */
6747                         if (!(status & L2_FHDR_STATUS_SPLIT) &&
6748                             (status & L2_FHDR_STATUS_IP_DATAGRAM)) {
6749                                 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
6750                                 DBRUN(sc->csum_offload_ip++);
6751                                 /* Check if the IP checksum is valid. */
6752                                 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
6753                                         m0->m_pkthdr.csum_flags |=
6754                                             CSUM_IP_VALID;
6755                         }
6756
6757                         /* Check for a valid TCP/UDP frame. */
6758                         if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
6759                             L2_FHDR_STATUS_UDP_DATAGRAM)) {
6760
6761                                 /* Check for a good TCP/UDP checksum. */
6762                                 if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
6763                                     L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
6764                                         DBRUN(sc->csum_offload_tcp_udp++);
6765                                         m0->m_pkthdr.csum_data =
6766                                             l2fhdr->l2_fhdr_tcp_udp_xsum;
6767                                         m0->m_pkthdr.csum_flags |=
6768                                             (CSUM_DATA_VALID
6769                                             | CSUM_PSEUDO_HDR);
6770                                 }
6771                         }
6772                 }
6773
6774                 /* Attach the VLAN tag. */
6775                 if ((status & L2_FHDR_STATUS_L2_VLAN_TAG) &&
6776                     !(sc->rx_mode & BCE_EMAC_RX_MODE_KEEP_VLAN_TAG)) {
6777                         DBRUN(sc->vlan_tagged_frames_rcvd++);
6778                         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
6779                                 DBRUN(sc->vlan_tagged_frames_stripped++);
6780 #if __FreeBSD_version < 700000
6781                                 VLAN_INPUT_TAG(ifp, m0,
6782                                     l2fhdr->l2_fhdr_vlan_tag, continue);
6783 #else
6784                                 m0->m_pkthdr.ether_vtag =
6785                                     l2fhdr->l2_fhdr_vlan_tag;
6786                                 m0->m_flags |= M_VLANTAG;
6787 #endif
6788                         } else {
6789                                 /*
6790                                  * bce(4) controllers can't disable VLAN
6791                                  * tag stripping if management firmware
6792                                  * (ASF/IPMI/UMP) is running. So we always
6793                                  * strip VLAN tag and manually reconstruct
6794                                  * the VLAN frame by appending stripped
6795                                  * VLAN tag in driver if VLAN tag stripping
6796                                  * was disabled.
6797                                  *
6798                                  * TODO: LLC SNAP handling.
6799                                  */
6800                                 bcopy(mtod(m0, uint8_t *),
6801                                     mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN,
6802                                     ETHER_ADDR_LEN * 2);
6803                                 m0->m_data -= ETHER_VLAN_ENCAP_LEN;
6804                                 vh = mtod(m0, struct ether_vlan_header *);
6805                                 vh->evl_encap_proto = htons(ETHERTYPE_VLAN);
6806                                 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag);
6807                                 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN;
6808                                 m0->m_len += ETHER_VLAN_ENCAP_LEN;
6809                         }
6810                 }
6811
6812                 /* Increment received packet statistics. */
6813                 ifp->if_ipackets++;
6814
6815 bce_rx_intr_next_rx:
6816                 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
6817
6818                 /* If we have a packet, pass it up the stack */
6819                 if (m0) {
6820                         /* Make sure we don't lose our place when we release the lock. */
6821                         sc->rx_cons = sw_rx_cons;
6822                         sc->pg_cons = sw_pg_cons;
6823
6824                         BCE_UNLOCK(sc);
6825                         (*ifp->if_input)(ifp, m0);
6826                         BCE_LOCK(sc);
6827
6828                         /* Recover our place. */
6829                         sw_rx_cons = sc->rx_cons;
6830                         sw_pg_cons = sc->pg_cons;
6831                 }
6832
6833                 /* Refresh hw_cons to see if there's new work */
6834                 if (sw_rx_cons == hw_rx_cons)
6835                         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6836         }
6837
6838         /* No new packets.  Refill the page chain. */
6839         if (bce_hdr_split == TRUE) {
6840                 sc->pg_cons = sw_pg_cons;
6841                 bce_fill_pg_chain(sc);
6842         }
6843
6844         /* No new packets.  Refill the RX chain. */
6845         sc->rx_cons = sw_rx_cons;
6846         bce_fill_rx_chain(sc);
6847
6848         /* Prepare the page chain pages to be accessed by the NIC. */
6849         for (int i = 0; i < sc->rx_pages; i++)
6850                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6851                     sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6852
6853         if (bce_hdr_split == TRUE) {
6854                 for (int i = 0; i < sc->pg_pages; i++)
6855                         bus_dmamap_sync(sc->pg_bd_chain_tag,
6856                             sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6857         }
6858
6859         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
6860             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6861             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6862         DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6863 }
6864
6865
6866 /****************************************************************************/
6867 /* Reads the transmit consumer value from the status block (skipping over   */
6868 /* chain page pointer if necessary).                                        */
6869 /*                                                                          */
6870 /* Returns:                                                                 */
6871 /*   hw_cons                                                                */
6872 /****************************************************************************/
6873 static inline u16
6874 bce_get_hw_tx_cons(struct bce_softc *sc)
6875 {
6876         u16 hw_cons;
6877
6878         mb();
6879         hw_cons = sc->status_block->status_tx_quick_consumer_index0;
6880         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
6881                 hw_cons++;
6882
6883         return hw_cons;
6884 }
6885
6886
6887 /****************************************************************************/
6888 /* Handles transmit completion interrupt events.                            */
6889 /*                                                                          */
6890 /* Returns:                                                                 */
6891 /*   Nothing.                                                               */
6892 /****************************************************************************/
6893 static void
6894 bce_tx_intr(struct bce_softc *sc)
6895 {
6896         struct ifnet *ifp = sc->bce_ifp;
6897         u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
6898
6899         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6900         DBRUN(sc->interrupts_tx++);
6901         DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6902             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6903             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6904
6905         BCE_LOCK_ASSERT(sc);
6906
6907         /* Get the hardware's view of the TX consumer index. */
6908         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6909         sw_tx_cons = sc->tx_cons;
6910
6911         /* Prevent speculative reads of the status block. */
6912         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6913             BUS_SPACE_BARRIER_READ);
6914
6915         /* Cycle through any completed TX chain page entries. */
6916         while (sw_tx_cons != hw_tx_cons) {
6917 #ifdef BCE_DEBUG
6918                 struct tx_bd *txbd = NULL;
6919 #endif
6920                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
6921
6922                 DBPRINT(sc, BCE_INFO_SEND,
6923                     "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
6924                     "sw_tx_chain_cons = 0x%04X\n",
6925                     __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
6926
6927                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC),
6928                     BCE_PRINTF("%s(%d): TX chain consumer out of range! "
6929                     " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
6930                     (int) MAX_TX_BD_ALLOC);
6931                     bce_breakpoint(sc));
6932
6933                 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
6934                     [TX_IDX(sw_tx_chain_cons)]);
6935
6936                 DBRUNIF((txbd == NULL),
6937                     BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
6938                     __FILE__, __LINE__, sw_tx_chain_cons);
6939                     bce_breakpoint(sc));
6940
6941                 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
6942                     bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
6943
6944                 /*
6945                  * Free the associated mbuf. Remember
6946                  * that only the last tx_bd of a packet
6947                  * has an mbuf pointer and DMA map.
6948                  */
6949                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
6950
6951                         /* Validate that this is the last tx_bd. */
6952                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
6953                             BCE_PRINTF("%s(%d): tx_bd END flag not set but "
6954                             "txmbuf == NULL!\n", __FILE__, __LINE__);
6955                             bce_breakpoint(sc));
6956
6957                         DBRUNMSG(BCE_INFO_SEND,
6958                             BCE_PRINTF("%s(): Unloading map/freeing mbuf "
6959                             "from tx_bd[0x%04X]\n", __FUNCTION__,
6960                             sw_tx_chain_cons));
6961
6962                         /* Unmap the mbuf. */
6963                         bus_dmamap_unload(sc->tx_mbuf_tag,
6964                             sc->tx_mbuf_map[sw_tx_chain_cons]);
6965
6966                         /* Free the mbuf. */
6967                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
6968                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
6969                         DBRUN(sc->debug_tx_mbuf_alloc--);
6970
6971                         ifp->if_opackets++;
6972                 }
6973
6974                 sc->used_tx_bd--;
6975                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
6976
6977                 /* Refresh hw_cons to see if there's new work. */
6978                 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6979
6980                 /* Prevent speculative reads of the status block. */
6981                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6982                     BUS_SPACE_BARRIER_READ);
6983         }
6984
6985         /* Clear the TX timeout timer. */
6986         sc->watchdog_timer = 0;
6987
6988         /* Clear the tx hardware queue full flag. */
6989         if (sc->used_tx_bd < sc->max_tx_bd) {
6990                 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
6991                     DBPRINT(sc, BCE_INFO_SEND,
6992                     "%s(): Open TX chain! %d/%d (used/total)\n",
6993                     __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
6994                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
6995         }
6996
6997         sc->tx_cons = sw_tx_cons;
6998
6999         DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
7000             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
7001             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
7002         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
7003 }
7004
7005
7006 /****************************************************************************/
7007 /* Disables interrupt generation.                                           */
7008 /*                                                                          */
7009 /* Returns:                                                                 */
7010 /*   Nothing.                                                               */
7011 /****************************************************************************/
7012 static void
7013 bce_disable_intr(struct bce_softc *sc)
7014 {
7015         DBENTER(BCE_VERBOSE_INTR);
7016
7017         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7018         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
7019
7020         DBEXIT(BCE_VERBOSE_INTR);
7021 }
7022
7023
7024 /****************************************************************************/
7025 /* Enables interrupt generation.                                            */
7026 /*                                                                          */
7027 /* Returns:                                                                 */
7028 /*   Nothing.                                                               */
7029 /****************************************************************************/
7030 static void
7031 bce_enable_intr(struct bce_softc *sc, int coal_now)
7032 {
7033         DBENTER(BCE_VERBOSE_INTR);
7034
7035         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7036             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
7037             BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
7038
7039         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7040             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
7041
7042         /* Force an immediate interrupt (whether there is new data or not). */
7043         if (coal_now)
7044                 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
7045
7046         DBEXIT(BCE_VERBOSE_INTR);
7047 }
7048
7049
7050 /****************************************************************************/
7051 /* Handles controller initialization.                                       */
7052 /*                                                                          */
7053 /* Returns:                                                                 */
7054 /*   Nothing.                                                               */
7055 /****************************************************************************/
7056 static void
7057 bce_init_locked(struct bce_softc *sc)
7058 {
7059         struct ifnet *ifp;
7060         u32 ether_mtu = 0;
7061
7062         DBENTER(BCE_VERBOSE_RESET);
7063
7064         BCE_LOCK_ASSERT(sc);
7065
7066         ifp = sc->bce_ifp;
7067
7068         /* Check if the driver is still running and bail out if it is. */
7069         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7070                 goto bce_init_locked_exit;
7071
7072         bce_stop(sc);
7073
7074         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
7075                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
7076                     __FILE__, __LINE__);
7077                 goto bce_init_locked_exit;
7078         }
7079
7080         if (bce_chipinit(sc)) {
7081                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
7082                     __FILE__, __LINE__);
7083                 goto bce_init_locked_exit;
7084         }
7085
7086         if (bce_blockinit(sc)) {
7087                 BCE_PRINTF("%s(%d): Block initialization failed!\n",
7088                     __FILE__, __LINE__);
7089                 goto bce_init_locked_exit;
7090         }
7091
7092         /* Load our MAC address. */
7093         bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
7094         bce_set_mac_addr(sc);
7095
7096         if (bce_hdr_split == FALSE)
7097                 bce_get_rx_buffer_sizes(sc, ifp->if_mtu);
7098         /*
7099          * Calculate and program the hardware Ethernet MTU
7100          * size. Be generous on the receive if we have room
7101          * and allowed by the user.
7102          */
7103         if (bce_strict_rx_mtu == TRUE)
7104                 ether_mtu = ifp->if_mtu;
7105         else {
7106                 if (bce_hdr_split == TRUE) {
7107                         if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len + MCLBYTES)
7108                                 ether_mtu = sc->rx_bd_mbuf_data_len +
7109                                     MCLBYTES;
7110                         else
7111                                 ether_mtu = ifp->if_mtu;
7112                 } else {
7113                         if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
7114                                 ether_mtu = sc->rx_bd_mbuf_data_len;
7115                         else
7116                                 ether_mtu = ifp->if_mtu;
7117                 }
7118         }
7119
7120         ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
7121
7122         DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n",
7123             __FUNCTION__, ether_mtu);
7124
7125         /* Program the mtu, enabling jumbo frame support if necessary. */
7126         if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
7127                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
7128                     min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
7129                     BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
7130         else
7131                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
7132
7133         /* Program appropriate promiscuous/multicast filtering. */
7134         bce_set_rx_mode(sc);
7135
7136         if (bce_hdr_split == TRUE) {
7137                 /* Init page buffer descriptor chain. */
7138                 bce_init_pg_chain(sc);
7139         }
7140
7141         /* Init RX buffer descriptor chain. */
7142         bce_init_rx_chain(sc);
7143
7144         /* Init TX buffer descriptor chain. */
7145         bce_init_tx_chain(sc);
7146
7147         /* Enable host interrupts. */
7148         bce_enable_intr(sc, 1);
7149
7150         bce_ifmedia_upd_locked(ifp);
7151
7152         /* Let the OS know the driver is up and running. */
7153         ifp->if_drv_flags |= IFF_DRV_RUNNING;
7154         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7155
7156         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7157
7158 bce_init_locked_exit:
7159         DBEXIT(BCE_VERBOSE_RESET);
7160 }
7161
7162
7163 /****************************************************************************/
7164 /* Initialize the controller just enough so that any management firmware    */
7165 /* running on the device will continue to operate correctly.                */
7166 /*                                                                          */
7167 /* Returns:                                                                 */
7168 /*   Nothing.                                                               */
7169 /****************************************************************************/
7170 static void
7171 bce_mgmt_init_locked(struct bce_softc *sc)
7172 {
7173         struct ifnet *ifp;
7174
7175         DBENTER(BCE_VERBOSE_RESET);
7176
7177         BCE_LOCK_ASSERT(sc);
7178
7179         /* Bail out if management firmware is not running. */
7180         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
7181                 DBPRINT(sc, BCE_VERBOSE_SPECIAL,
7182                     "No management firmware running...\n");
7183                 goto bce_mgmt_init_locked_exit;
7184         }
7185
7186         ifp = sc->bce_ifp;
7187
7188         /* Enable all critical blocks in the MAC. */
7189         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
7190         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
7191         DELAY(20);
7192
7193         bce_ifmedia_upd_locked(ifp);
7194
7195 bce_mgmt_init_locked_exit:
7196         DBEXIT(BCE_VERBOSE_RESET);
7197 }
7198
7199
7200 /****************************************************************************/
7201 /* Handles controller initialization when called from an unlocked routine.  */
7202 /*                                                                          */
7203 /* Returns:                                                                 */
7204 /*   Nothing.                                                               */
7205 /****************************************************************************/
7206 static void
7207 bce_init(void *xsc)
7208 {
7209         struct bce_softc *sc = xsc;
7210
7211         DBENTER(BCE_VERBOSE_RESET);
7212
7213         BCE_LOCK(sc);
7214         bce_init_locked(sc);
7215         BCE_UNLOCK(sc);
7216
7217         DBEXIT(BCE_VERBOSE_RESET);
7218 }
7219
7220
7221 /****************************************************************************/
7222 /* Modifies an mbuf for TSO on the hardware.                                */
7223 /*                                                                          */
7224 /* Returns:                                                                 */
7225 /*   Pointer to a modified mbuf.                                            */
7226 /****************************************************************************/
7227 static struct mbuf *
7228 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags)
7229 {
7230         struct mbuf *m;
7231         struct ether_header *eh;
7232         struct ip *ip;
7233         struct tcphdr *th;
7234         u16 etype;
7235         int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0;
7236
7237         DBRUN(sc->tso_frames_requested++);
7238
7239         /* Controller may modify mbuf chains. */
7240         if (M_WRITABLE(*m_head) == 0) {
7241                 m = m_dup(*m_head, M_NOWAIT);
7242                 m_freem(*m_head);
7243                 if (m == NULL) {
7244                         sc->mbuf_alloc_failed_count++;
7245                         *m_head = NULL;
7246                         return (NULL);
7247                 }
7248                 *m_head = m;
7249         }
7250
7251         /*
7252          * For TSO the controller needs two pieces of info,
7253          * the MSS and the IP+TCP options length.
7254          */
7255         m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip));
7256         if (m == NULL) {
7257                 *m_head = NULL;
7258                 return (NULL);
7259         }
7260         eh = mtod(m, struct ether_header *);
7261         etype = ntohs(eh->ether_type);
7262
7263         /* Check for supported TSO Ethernet types (only IPv4 for now) */
7264         switch (etype) {
7265         case ETHERTYPE_IP:
7266                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7267                 /* TSO only supported for TCP protocol. */
7268                 if (ip->ip_p != IPPROTO_TCP) {
7269                         BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
7270                             __FILE__, __LINE__);
7271                         m_freem(*m_head);
7272                         *m_head = NULL;
7273                         return (NULL);
7274                 }
7275
7276                 /* Get IP header length in bytes (min 20) */
7277                 ip_hlen = ip->ip_hl << 2;
7278                 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen +
7279                     sizeof(struct tcphdr));
7280                 if (m == NULL) {
7281                         *m_head = NULL;
7282                         return (NULL);
7283                 }
7284
7285                 /* Get the TCP header length in bytes (min 20) */
7286                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7287                 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
7288                 tcp_hlen = (th->th_off << 2);
7289
7290                 /* Make sure all IP/TCP options live in the same buffer. */
7291                 m = m_pullup(*m_head,  sizeof(struct ether_header)+ ip_hlen +
7292                     tcp_hlen);
7293                 if (m == NULL) {
7294                         *m_head = NULL;
7295                         return (NULL);
7296                 }
7297
7298                 /* Clear IP header length and checksum, will be calc'd by h/w. */
7299                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7300                 ip_len = ip->ip_len;
7301                 ip->ip_len = 0;
7302                 ip->ip_sum = 0;
7303                 break;
7304         case ETHERTYPE_IPV6:
7305                 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n",
7306                     __FILE__, __LINE__);
7307                 m_freem(*m_head);
7308                 *m_head = NULL;
7309                 return (NULL);
7310                 /* NOT REACHED */
7311         default:
7312                 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
7313                     __FILE__, __LINE__);
7314                 m_freem(*m_head);
7315                 *m_head = NULL;
7316                 return (NULL);
7317         }
7318
7319         hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen;
7320
7321         DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, "
7322             "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
7323             __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen,
7324             tcp_hlen, ip_len);
7325
7326         /* Set the LSO flag in the TX BD */
7327         *flags |= TX_BD_FLAGS_SW_LSO;
7328
7329         /* Set the length of IP + TCP options (in 32 bit words) */
7330         *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) -
7331             sizeof(struct tcphdr)) >> 2) << 8);
7332
7333         DBRUN(sc->tso_frames_completed++);
7334         return (*m_head);
7335 }
7336
7337
7338 /****************************************************************************/
7339 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
7340 /* memory visible to the controller.                                        */
7341 /*                                                                          */
7342 /* Returns:                                                                 */
7343 /*   0 for success, positive value for failure.                             */
7344 /* Modified:                                                                */
7345 /*   m_head: May be set to NULL if MBUF is excessively fragmented.          */
7346 /****************************************************************************/
7347 static int
7348 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head)
7349 {
7350         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
7351         bus_dmamap_t map;
7352         struct tx_bd *txbd = NULL;
7353         struct mbuf *m0;
7354         u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0;
7355         u32 prod_bseq;
7356
7357 #ifdef BCE_DEBUG
7358         u16 debug_prod;
7359 #endif
7360
7361         int i, error, nsegs, rc = 0;
7362
7363         DBENTER(BCE_VERBOSE_SEND);
7364
7365         /* Make sure we have room in the TX chain. */
7366         if (sc->used_tx_bd >= sc->max_tx_bd)
7367                 goto bce_tx_encap_exit;
7368
7369         /* Transfer any checksum offload flags to the bd. */
7370         m0 = *m_head;
7371         if (m0->m_pkthdr.csum_flags) {
7372                 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
7373                         m0 = bce_tso_setup(sc, m_head, &flags);
7374                         if (m0 == NULL) {
7375                                 DBRUN(sc->tso_frames_failed++);
7376                                 goto bce_tx_encap_exit;
7377                         }
7378                         mss = htole16(m0->m_pkthdr.tso_segsz);
7379                 } else {
7380                         if (m0->m_pkthdr.csum_flags & CSUM_IP)
7381                                 flags |= TX_BD_FLAGS_IP_CKSUM;
7382                         if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
7383                                 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
7384                 }
7385         }
7386
7387         /* Transfer any VLAN tags to the bd. */
7388         if (m0->m_flags & M_VLANTAG) {
7389                 flags |= TX_BD_FLAGS_VLAN_TAG;
7390                 vlan_tag = m0->m_pkthdr.ether_vtag;
7391         }
7392
7393         /* Map the mbuf into DMAable memory. */
7394         prod = sc->tx_prod;
7395         chain_prod = TX_CHAIN_IDX(prod);
7396         map = sc->tx_mbuf_map[chain_prod];
7397
7398         /* Map the mbuf into our DMA address space. */
7399         error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
7400             segs, &nsegs, BUS_DMA_NOWAIT);
7401
7402         /* Check if the DMA mapping was successful */
7403         if (error == EFBIG) {
7404                 sc->mbuf_frag_count++;
7405
7406                 /* Try to defrag the mbuf. */
7407                 m0 = m_collapse(*m_head, M_NOWAIT, BCE_MAX_SEGMENTS);
7408                 if (m0 == NULL) {
7409                         /* Defrag was unsuccessful */
7410                         m_freem(*m_head);
7411                         *m_head = NULL;
7412                         sc->mbuf_alloc_failed_count++;
7413                         rc = ENOBUFS;
7414                         goto bce_tx_encap_exit;
7415                 }
7416
7417                 /* Defrag was successful, try mapping again */
7418                 *m_head = m0;
7419                 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag,
7420                     map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
7421
7422                 /* Still getting an error after a defrag. */
7423                 if (error == ENOMEM) {
7424                         /* Insufficient DMA buffers available. */
7425                         sc->dma_map_addr_tx_failed_count++;
7426                         rc = error;
7427                         goto bce_tx_encap_exit;
7428                 } else if (error != 0) {
7429                         /* Release it and return an error. */
7430                         BCE_PRINTF("%s(%d): Unknown error mapping mbuf into "
7431                             "TX chain!\n", __FILE__, __LINE__);
7432                         m_freem(m0);
7433                         *m_head = NULL;
7434                         sc->dma_map_addr_tx_failed_count++;
7435                         rc = ENOBUFS;
7436                         goto bce_tx_encap_exit;
7437                 }
7438         } else if (error == ENOMEM) {
7439                 /* Insufficient DMA buffers available. */
7440                 sc->dma_map_addr_tx_failed_count++;
7441                 rc = error;
7442                 goto bce_tx_encap_exit;
7443         } else if (error != 0) {
7444                 m_freem(m0);
7445                 *m_head = NULL;
7446                 sc->dma_map_addr_tx_failed_count++;
7447                 rc = error;
7448                 goto bce_tx_encap_exit;
7449         }
7450
7451         /* Make sure there's room in the chain */
7452         if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
7453                 bus_dmamap_unload(sc->tx_mbuf_tag, map);
7454                 rc = ENOBUFS;
7455                 goto bce_tx_encap_exit;
7456         }
7457
7458         /* prod points to an empty tx_bd at this point. */
7459         prod_bseq  = sc->tx_prod_bseq;
7460
7461 #ifdef BCE_DEBUG
7462         debug_prod = chain_prod;
7463 #endif
7464
7465         DBPRINT(sc, BCE_INFO_SEND,
7466             "%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
7467             "prod_bseq = 0x%08X\n",
7468             __FUNCTION__, prod, chain_prod, prod_bseq);
7469
7470         /*
7471          * Cycle through each mbuf segment that makes up
7472          * the outgoing frame, gathering the mapping info
7473          * for that segment and creating a tx_bd for
7474          * the mbuf.
7475          */
7476         for (i = 0; i < nsegs ; i++) {
7477
7478                 chain_prod = TX_CHAIN_IDX(prod);
7479                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)]
7480                     [TX_IDX(chain_prod)];
7481
7482                 txbd->tx_bd_haddr_lo =
7483                     htole32(BCE_ADDR_LO(segs[i].ds_addr));
7484                 txbd->tx_bd_haddr_hi =
7485                     htole32(BCE_ADDR_HI(segs[i].ds_addr));
7486                 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
7487                     htole16(segs[i].ds_len);
7488                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
7489                 txbd->tx_bd_flags = htole16(flags);
7490                 prod_bseq += segs[i].ds_len;
7491                 if (i == 0)
7492                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
7493                 prod = NEXT_TX_BD(prod);
7494         }
7495
7496         /* Set the END flag on the last TX buffer descriptor. */
7497         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
7498
7499         DBRUNMSG(BCE_EXTREME_SEND,
7500             bce_dump_tx_chain(sc, debug_prod, nsegs));
7501
7502         /*
7503          * Ensure that the mbuf pointer for this transmission
7504          * is placed at the array index of the last
7505          * descriptor in this chain.  This is done
7506          * because a single map is used for all
7507          * segments of the mbuf and we don't want to
7508          * unload the map before all of the segments
7509          * have been freed.
7510          */
7511         sc->tx_mbuf_ptr[chain_prod] = m0;
7512         sc->used_tx_bd += nsegs;
7513
7514         /* Update some debug statistic counters */
7515         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
7516             sc->tx_hi_watermark = sc->used_tx_bd);
7517         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
7518         DBRUNIF(sc->debug_tx_mbuf_alloc++);
7519
7520         DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
7521
7522         /* prod points to the next free tx_bd at this point. */
7523         sc->tx_prod = prod;
7524         sc->tx_prod_bseq = prod_bseq;
7525
7526         /* Tell the chip about the waiting TX frames. */
7527         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) +
7528             BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
7529         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +
7530             BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
7531
7532 bce_tx_encap_exit:
7533         DBEXIT(BCE_VERBOSE_SEND);
7534         return(rc);
7535 }
7536
7537
7538 /****************************************************************************/
7539 /* Main transmit routine when called from another routine with a lock.      */
7540 /*                                                                          */
7541 /* Returns:                                                                 */
7542 /*   Nothing.                                                               */
7543 /****************************************************************************/
7544 static void
7545 bce_start_locked(struct ifnet *ifp)
7546 {
7547         struct bce_softc *sc = ifp->if_softc;
7548         struct mbuf *m_head = NULL;
7549         int count = 0;
7550         u16 tx_prod, tx_chain_prod;
7551
7552         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7553
7554         BCE_LOCK_ASSERT(sc);
7555
7556         /* prod points to the next free tx_bd. */
7557         tx_prod = sc->tx_prod;
7558         tx_chain_prod = TX_CHAIN_IDX(tx_prod);
7559
7560         DBPRINT(sc, BCE_INFO_SEND,
7561             "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
7562             "tx_prod_bseq = 0x%08X\n",
7563             __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
7564
7565         /* If there's no link or the transmit queue is empty then just exit. */
7566         if (sc->bce_link_up == FALSE) {
7567                 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
7568                     __FUNCTION__);
7569                 goto bce_start_locked_exit;
7570         }
7571
7572         if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7573                 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
7574                     __FUNCTION__);
7575                 goto bce_start_locked_exit;
7576         }
7577
7578         /*
7579          * Keep adding entries while there is space in the ring.
7580          */
7581         while (sc->used_tx_bd < sc->max_tx_bd) {
7582
7583                 /* Check for any frames to send. */
7584                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
7585
7586                 /* Stop when the transmit queue is empty. */
7587                 if (m_head == NULL)
7588                         break;
7589
7590                 /*
7591                  * Pack the data into the transmit ring. If we
7592                  * don't have room, place the mbuf back at the
7593                  * head of the queue and set the OACTIVE flag
7594                  * to wait for the NIC to drain the chain.
7595                  */
7596                 if (bce_tx_encap(sc, &m_head)) {
7597                         if (m_head != NULL)
7598                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
7599                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
7600                         DBPRINT(sc, BCE_INFO_SEND,
7601                             "TX chain is closed for business! Total "
7602                             "tx_bd used = %d\n", sc->used_tx_bd);
7603                         break;
7604                 }
7605
7606                 count++;
7607
7608                 /* Send a copy of the frame to any BPF listeners. */
7609                 ETHER_BPF_MTAP(ifp, m_head);
7610         }
7611
7612         /* Exit if no packets were dequeued. */
7613         if (count == 0) {
7614                 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were "
7615                     "dequeued\n", __FUNCTION__);
7616                 goto bce_start_locked_exit;
7617         }
7618
7619         DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into "
7620             "send queue.\n", __FUNCTION__, count);
7621
7622         /* Set the tx timeout. */
7623         sc->watchdog_timer = BCE_TX_TIMEOUT;
7624
7625         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
7626         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
7627
7628 bce_start_locked_exit:
7629         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7630 }
7631
7632
7633 /****************************************************************************/
7634 /* Main transmit routine when called from another routine without a lock.   */
7635 /*                                                                          */
7636 /* Returns:                                                                 */
7637 /*   Nothing.                                                               */
7638 /****************************************************************************/
7639 static void
7640 bce_start(struct ifnet *ifp)
7641 {
7642         struct bce_softc *sc = ifp->if_softc;
7643
7644         DBENTER(BCE_VERBOSE_SEND);
7645
7646         BCE_LOCK(sc);
7647         bce_start_locked(ifp);
7648         BCE_UNLOCK(sc);
7649
7650         DBEXIT(BCE_VERBOSE_SEND);
7651 }
7652
7653
7654 /****************************************************************************/
7655 /* Handles any IOCTL calls from the operating system.                       */
7656 /*                                                                          */
7657 /* Returns:                                                                 */
7658 /*   0 for success, positive value for failure.                             */
7659 /****************************************************************************/
7660 static int
7661 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
7662 {
7663         struct bce_softc *sc = ifp->if_softc;
7664         struct ifreq *ifr = (struct ifreq *) data;
7665         struct mii_data *mii;
7666         int mask, error = 0;
7667
7668         DBENTER(BCE_VERBOSE_MISC);
7669
7670         switch(command) {
7671
7672         /* Set the interface MTU. */
7673         case SIOCSIFMTU:
7674                 /* Check that the MTU setting is supported. */
7675                 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
7676                         (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
7677                         error = EINVAL;
7678                         break;
7679                 }
7680
7681                 DBPRINT(sc, BCE_INFO_MISC,
7682                     "SIOCSIFMTU: Changing MTU from %d to %d\n",
7683                     (int) ifp->if_mtu, (int) ifr->ifr_mtu);
7684
7685                 BCE_LOCK(sc);
7686                 ifp->if_mtu = ifr->ifr_mtu;
7687                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7688                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7689                         bce_init_locked(sc);
7690                 }
7691                 BCE_UNLOCK(sc);
7692                 break;
7693
7694         /* Set interface flags. */
7695         case SIOCSIFFLAGS:
7696                 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n");
7697
7698                 BCE_LOCK(sc);
7699
7700                 /* Check if the interface is up. */
7701                 if (ifp->if_flags & IFF_UP) {
7702                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7703                                 /* Change promiscuous/multicast flags as necessary. */
7704                                 bce_set_rx_mode(sc);
7705                         } else {
7706                                 /* Start the HW */
7707                                 bce_init_locked(sc);
7708                         }
7709                 } else {
7710                         /* The interface is down, check if driver is running. */
7711                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7712                                 bce_stop(sc);
7713
7714                                 /* If MFW is running, restart the controller a bit. */
7715                                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
7716                                         bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
7717                                         bce_chipinit(sc);
7718                                         bce_mgmt_init_locked(sc);
7719                                 }
7720                         }
7721                 }
7722
7723                 BCE_UNLOCK(sc);
7724                 break;
7725
7726         /* Add/Delete multicast address */
7727         case SIOCADDMULTI:
7728         case SIOCDELMULTI:
7729                 DBPRINT(sc, BCE_VERBOSE_MISC,
7730                     "Received SIOCADDMULTI/SIOCDELMULTI\n");
7731
7732                 BCE_LOCK(sc);
7733                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7734                         bce_set_rx_mode(sc);
7735                 BCE_UNLOCK(sc);
7736
7737                 break;
7738
7739         /* Set/Get Interface media */
7740         case SIOCSIFMEDIA:
7741         case SIOCGIFMEDIA:
7742                 DBPRINT(sc, BCE_VERBOSE_MISC,
7743                     "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n");
7744                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
7745                         error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia,
7746                             command);
7747                 else {
7748                         mii = device_get_softc(sc->bce_miibus);
7749                         error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
7750                             command);
7751                 }
7752                 break;
7753
7754         /* Set interface capability */
7755         case SIOCSIFCAP:
7756                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
7757                 DBPRINT(sc, BCE_INFO_MISC,
7758                     "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
7759
7760                 /* Toggle the TX checksum capabilities enable flag. */
7761                 if (mask & IFCAP_TXCSUM &&
7762                     ifp->if_capabilities & IFCAP_TXCSUM) {
7763                         ifp->if_capenable ^= IFCAP_TXCSUM;
7764                         if (IFCAP_TXCSUM & ifp->if_capenable)
7765                                 ifp->if_hwassist |= BCE_IF_HWASSIST;
7766                         else
7767                                 ifp->if_hwassist &= ~BCE_IF_HWASSIST;
7768                 }
7769
7770                 /* Toggle the RX checksum capabilities enable flag. */
7771                 if (mask & IFCAP_RXCSUM &&
7772                     ifp->if_capabilities & IFCAP_RXCSUM)
7773                         ifp->if_capenable ^= IFCAP_RXCSUM;
7774
7775                 /* Toggle the TSO capabilities enable flag. */
7776                 if (bce_tso_enable && (mask & IFCAP_TSO4) &&
7777                     ifp->if_capabilities & IFCAP_TSO4) {
7778                         ifp->if_capenable ^= IFCAP_TSO4;
7779                         if (IFCAP_TSO4 & ifp->if_capenable)
7780                                 ifp->if_hwassist |= CSUM_TSO;
7781                         else
7782                                 ifp->if_hwassist &= ~CSUM_TSO;
7783                 }
7784
7785                 if (mask & IFCAP_VLAN_HWCSUM &&
7786                     ifp->if_capabilities & IFCAP_VLAN_HWCSUM)
7787                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
7788
7789                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
7790                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
7791                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
7792                 /*
7793                  * Don't actually disable VLAN tag stripping as
7794                  * management firmware (ASF/IPMI/UMP) requires the
7795                  * feature. If VLAN tag stripping is disabled driver
7796                  * will manually reconstruct the VLAN frame by
7797                  * appending stripped VLAN tag.
7798                  */
7799                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
7800                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) {
7801                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
7802                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
7803                             == 0)
7804                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
7805                 }
7806                 VLAN_CAPABILITIES(ifp);
7807                 break;
7808         default:
7809                 /* We don't know how to handle the IOCTL, pass it on. */
7810                 error = ether_ioctl(ifp, command, data);
7811                 break;
7812         }
7813
7814         DBEXIT(BCE_VERBOSE_MISC);
7815         return(error);
7816 }
7817
7818
7819 /****************************************************************************/
7820 /* Transmit timeout handler.                                                */
7821 /*                                                                          */
7822 /* Returns:                                                                 */
7823 /*   Nothing.                                                               */
7824 /****************************************************************************/
7825 static void
7826 bce_watchdog(struct bce_softc *sc)
7827 {
7828         DBENTER(BCE_EXTREME_SEND);
7829
7830         BCE_LOCK_ASSERT(sc);
7831
7832         /* If the watchdog timer hasn't expired then just exit. */
7833         if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
7834                 goto bce_watchdog_exit;
7835
7836         /* If pause frames are active then don't reset the hardware. */
7837         /* ToDo: Should we reset the timer here? */
7838         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
7839                 goto bce_watchdog_exit;
7840
7841         BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
7842             __FILE__, __LINE__);
7843
7844         DBRUNMSG(BCE_INFO,
7845             bce_dump_driver_state(sc);
7846             bce_dump_status_block(sc);
7847             bce_dump_stats_block(sc);
7848             bce_dump_ftqs(sc);
7849             bce_dump_txp_state(sc, 0);
7850             bce_dump_rxp_state(sc, 0);
7851             bce_dump_tpat_state(sc, 0);
7852             bce_dump_cp_state(sc, 0);
7853             bce_dump_com_state(sc, 0));
7854
7855         DBRUN(bce_breakpoint(sc));
7856
7857         sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7858
7859         bce_init_locked(sc);
7860         sc->bce_ifp->if_oerrors++;
7861
7862 bce_watchdog_exit:
7863         DBEXIT(BCE_EXTREME_SEND);
7864 }
7865
7866
7867 /*
7868  * Interrupt handler.
7869  */
7870 /****************************************************************************/
7871 /* Main interrupt entry point.  Verifies that the controller generated the  */
7872 /* interrupt and then calls a separate routine for handle the various       */
7873 /* interrupt causes (PHY, TX, RX).                                          */
7874 /*                                                                          */
7875 /* Returns:                                                                 */
7876 /*   Nothing.                                                               */
7877 /****************************************************************************/
7878 static void
7879 bce_intr(void *xsc)
7880 {
7881         struct bce_softc *sc;
7882         struct ifnet *ifp;
7883         u32 status_attn_bits;
7884         u16 hw_rx_cons, hw_tx_cons;
7885
7886         sc = xsc;
7887         ifp = sc->bce_ifp;
7888
7889         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7890         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
7891         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc));
7892
7893         BCE_LOCK(sc);
7894
7895         DBRUN(sc->interrupts_generated++);
7896
7897         /* Synchnorize before we read from interface's status block */
7898         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
7899
7900         /*
7901          * If the hardware status block index matches the last value read
7902          * by the driver and we haven't asserted our interrupt then there's
7903          * nothing to do.  This may only happen in case of INTx due to the
7904          * interrupt arriving at the CPU before the status block is updated.
7905          */
7906         if ((sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) == 0 &&
7907             sc->status_block->status_idx == sc->last_status_idx &&
7908             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
7909              BCE_PCICFG_MISC_STATUS_INTA_VALUE)) {
7910                 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n",
7911                     __FUNCTION__);
7912                 goto bce_intr_exit;
7913         }
7914
7915         /* Ack the interrupt and stop others from occuring. */
7916         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7917             BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
7918             BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7919
7920         /* Check if the hardware has finished any work. */
7921         hw_rx_cons = bce_get_hw_rx_cons(sc);
7922         hw_tx_cons = bce_get_hw_tx_cons(sc);
7923
7924         /* Keep processing data as long as there is work to do. */
7925         for (;;) {
7926
7927                 status_attn_bits = sc->status_block->status_attn_bits;
7928
7929                 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control),
7930                     BCE_PRINTF("Simulating unexpected status attention "
7931                     "bit set.");
7932                     sc->unexpected_attention_sim_count++;
7933                     status_attn_bits = status_attn_bits |
7934                     STATUS_ATTN_BITS_PARITY_ERROR);
7935
7936                 /* Was it a link change interrupt? */
7937                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
7938                     (sc->status_block->status_attn_bits_ack &
7939                      STATUS_ATTN_BITS_LINK_STATE)) {
7940                         bce_phy_intr(sc);
7941
7942                         /* Clear transient updates during link state change. */
7943                         REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |
7944                             BCE_HC_COMMAND_COAL_NOW_WO_INT);
7945                         REG_RD(sc, BCE_HC_COMMAND);
7946                 }
7947
7948                 /* If any other attention is asserted, the chip is toast. */
7949                 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
7950                     (sc->status_block->status_attn_bits_ack &
7951                     ~STATUS_ATTN_BITS_LINK_STATE))) {
7952
7953                         sc->unexpected_attention_count++;
7954
7955                         BCE_PRINTF("%s(%d): Fatal attention detected: "
7956                             "0x%08X\n", __FILE__, __LINE__,
7957                             sc->status_block->status_attn_bits);
7958
7959                         DBRUNMSG(BCE_FATAL,
7960                             if (unexpected_attention_sim_control == 0)
7961                                 bce_breakpoint(sc));
7962
7963                         bce_init_locked(sc);
7964                         goto bce_intr_exit;
7965                 }
7966
7967                 /* Check for any completed RX frames. */
7968                 if (hw_rx_cons != sc->hw_rx_cons)
7969                         bce_rx_intr(sc);
7970
7971                 /* Check for any completed TX frames. */
7972                 if (hw_tx_cons != sc->hw_tx_cons)
7973                         bce_tx_intr(sc);
7974
7975                 /* Save status block index value for the next interrupt. */
7976                 sc->last_status_idx = sc->status_block->status_idx;
7977
7978                 /*
7979                  * Prevent speculative reads from getting
7980                  * ahead of the status block.
7981                  */
7982                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
7983                     BUS_SPACE_BARRIER_READ);
7984
7985                 /*
7986                  * If there's no work left then exit the
7987                  * interrupt service routine.
7988                  */
7989                 hw_rx_cons = bce_get_hw_rx_cons(sc);
7990                 hw_tx_cons = bce_get_hw_tx_cons(sc);
7991
7992                 if ((hw_rx_cons == sc->hw_rx_cons) &&
7993                     (hw_tx_cons == sc->hw_tx_cons))
7994                         break;
7995         }
7996
7997         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_PREREAD);
7998
7999         /* Re-enable interrupts. */
8000         bce_enable_intr(sc, 0);
8001
8002         /* Handle any frames that arrived while handling the interrupt. */
8003         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
8004             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
8005                 bce_start_locked(ifp);
8006
8007 bce_intr_exit:
8008         BCE_UNLOCK(sc);
8009
8010         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
8011 }
8012
8013
8014 /****************************************************************************/
8015 /* Programs the various packet receive modes (broadcast and multicast).     */
8016 /*                                                                          */
8017 /* Returns:                                                                 */
8018 /*   Nothing.                                                               */
8019 /****************************************************************************/
8020 static void
8021 bce_set_rx_mode(struct bce_softc *sc)
8022 {
8023         struct ifnet *ifp;
8024         struct ifmultiaddr *ifma;
8025         u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
8026         u32 rx_mode, sort_mode;
8027         int h, i;
8028
8029         DBENTER(BCE_VERBOSE_MISC);
8030
8031         BCE_LOCK_ASSERT(sc);
8032
8033         ifp = sc->bce_ifp;
8034
8035         /* Initialize receive mode default settings. */
8036         rx_mode   = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
8037             BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
8038         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
8039
8040         /*
8041          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
8042          * be enbled.
8043          */
8044         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
8045             (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)))
8046                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
8047
8048         /*
8049          * Check for promiscuous, all multicast, or selected
8050          * multicast address filtering.
8051          */
8052         if (ifp->if_flags & IFF_PROMISC) {
8053                 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n");
8054
8055                 /* Enable promiscuous mode. */
8056                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
8057                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
8058         } else if (ifp->if_flags & IFF_ALLMULTI) {
8059                 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n");
8060
8061                 /* Enable all multicast addresses. */
8062                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
8063                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4),
8064                             0xffffffff);
8065                 }
8066                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
8067         } else {
8068                 /* Accept one or more multicast(s). */
8069                 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n");
8070
8071                 if_maddr_rlock(ifp);
8072                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
8073                         if (ifma->ifma_addr->sa_family != AF_LINK)
8074                                 continue;
8075                         h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
8076                             ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
8077                             hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
8078                 }
8079                 if_maddr_runlock(ifp);
8080
8081                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
8082                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
8083
8084                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
8085         }
8086
8087         /* Only make changes if the recive mode has actually changed. */
8088         if (rx_mode != sc->rx_mode) {
8089                 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: "
8090                     "0x%08X\n", rx_mode);
8091
8092                 sc->rx_mode = rx_mode;
8093                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
8094         }
8095
8096         /* Disable and clear the exisitng sort before enabling a new sort. */
8097         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
8098         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
8099         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
8100
8101         DBEXIT(BCE_VERBOSE_MISC);
8102 }
8103
8104
8105 /****************************************************************************/
8106 /* Called periodically to updates statistics from the controllers           */
8107 /* statistics block.                                                        */
8108 /*                                                                          */
8109 /* Returns:                                                                 */
8110 /*   Nothing.                                                               */
8111 /****************************************************************************/
8112 static void
8113 bce_stats_update(struct bce_softc *sc)
8114 {
8115         struct ifnet *ifp;
8116         struct statistics_block *stats;
8117
8118         DBENTER(BCE_EXTREME_MISC);
8119
8120         ifp = sc->bce_ifp;
8121
8122         bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
8123
8124         stats = (struct statistics_block *) sc->stats_block;
8125
8126         /*
8127          * Certain controllers don't report
8128          * carrier sense errors correctly.
8129          * See errata E11_5708CA0_1165.
8130          */
8131         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
8132             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
8133                 ifp->if_oerrors +=
8134                     (u_long) stats->stat_Dot3StatsCarrierSenseErrors;
8135
8136         /*
8137          * Update the sysctl statistics from the
8138          * hardware statistics.
8139          */
8140         sc->stat_IfHCInOctets =
8141             ((u64) stats->stat_IfHCInOctets_hi << 32) +
8142              (u64) stats->stat_IfHCInOctets_lo;
8143
8144         sc->stat_IfHCInBadOctets =
8145             ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
8146              (u64) stats->stat_IfHCInBadOctets_lo;
8147
8148         sc->stat_IfHCOutOctets =
8149             ((u64) stats->stat_IfHCOutOctets_hi << 32) +
8150              (u64) stats->stat_IfHCOutOctets_lo;
8151
8152         sc->stat_IfHCOutBadOctets =
8153             ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
8154              (u64) stats->stat_IfHCOutBadOctets_lo;
8155
8156         sc->stat_IfHCInUcastPkts =
8157             ((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
8158              (u64) stats->stat_IfHCInUcastPkts_lo;
8159
8160         sc->stat_IfHCInMulticastPkts =
8161             ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
8162              (u64) stats->stat_IfHCInMulticastPkts_lo;
8163
8164         sc->stat_IfHCInBroadcastPkts =
8165             ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
8166              (u64) stats->stat_IfHCInBroadcastPkts_lo;
8167
8168         sc->stat_IfHCOutUcastPkts =
8169             ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
8170              (u64) stats->stat_IfHCOutUcastPkts_lo;
8171
8172         sc->stat_IfHCOutMulticastPkts =
8173             ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
8174              (u64) stats->stat_IfHCOutMulticastPkts_lo;
8175
8176         sc->stat_IfHCOutBroadcastPkts =
8177             ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
8178              (u64) stats->stat_IfHCOutBroadcastPkts_lo;
8179
8180         /* ToDo: Preserve counters beyond 32 bits? */
8181         /* ToDo: Read the statistics from auto-clear regs? */
8182
8183         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
8184             stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
8185
8186         sc->stat_Dot3StatsCarrierSenseErrors =
8187             stats->stat_Dot3StatsCarrierSenseErrors;
8188
8189         sc->stat_Dot3StatsFCSErrors =
8190             stats->stat_Dot3StatsFCSErrors;
8191
8192         sc->stat_Dot3StatsAlignmentErrors =
8193             stats->stat_Dot3StatsAlignmentErrors;
8194
8195         sc->stat_Dot3StatsSingleCollisionFrames =
8196             stats->stat_Dot3StatsSingleCollisionFrames;
8197
8198         sc->stat_Dot3StatsMultipleCollisionFrames =
8199             stats->stat_Dot3StatsMultipleCollisionFrames;
8200
8201         sc->stat_Dot3StatsDeferredTransmissions =
8202             stats->stat_Dot3StatsDeferredTransmissions;
8203
8204         sc->stat_Dot3StatsExcessiveCollisions =
8205             stats->stat_Dot3StatsExcessiveCollisions;
8206
8207         sc->stat_Dot3StatsLateCollisions =
8208             stats->stat_Dot3StatsLateCollisions;
8209
8210         sc->stat_EtherStatsCollisions =
8211             stats->stat_EtherStatsCollisions;
8212
8213         sc->stat_EtherStatsFragments =
8214             stats->stat_EtherStatsFragments;
8215
8216         sc->stat_EtherStatsJabbers =
8217             stats->stat_EtherStatsJabbers;
8218
8219         sc->stat_EtherStatsUndersizePkts =
8220             stats->stat_EtherStatsUndersizePkts;
8221
8222         sc->stat_EtherStatsOversizePkts =
8223              stats->stat_EtherStatsOversizePkts;
8224
8225         sc->stat_EtherStatsPktsRx64Octets =
8226             stats->stat_EtherStatsPktsRx64Octets;
8227
8228         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
8229             stats->stat_EtherStatsPktsRx65Octetsto127Octets;
8230
8231         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
8232             stats->stat_EtherStatsPktsRx128Octetsto255Octets;
8233
8234         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
8235             stats->stat_EtherStatsPktsRx256Octetsto511Octets;
8236
8237         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
8238             stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
8239
8240         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
8241             stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
8242
8243         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
8244             stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
8245
8246         sc->stat_EtherStatsPktsTx64Octets =
8247             stats->stat_EtherStatsPktsTx64Octets;
8248
8249         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
8250             stats->stat_EtherStatsPktsTx65Octetsto127Octets;
8251
8252         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
8253             stats->stat_EtherStatsPktsTx128Octetsto255Octets;
8254
8255         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
8256             stats->stat_EtherStatsPktsTx256Octetsto511Octets;
8257
8258         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
8259             stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
8260
8261         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
8262             stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
8263
8264         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
8265             stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
8266
8267         sc->stat_XonPauseFramesReceived =
8268             stats->stat_XonPauseFramesReceived;
8269
8270         sc->stat_XoffPauseFramesReceived =
8271             stats->stat_XoffPauseFramesReceived;
8272
8273         sc->stat_OutXonSent =
8274             stats->stat_OutXonSent;
8275
8276         sc->stat_OutXoffSent =
8277             stats->stat_OutXoffSent;
8278
8279         sc->stat_FlowControlDone =
8280             stats->stat_FlowControlDone;
8281
8282         sc->stat_MacControlFramesReceived =
8283             stats->stat_MacControlFramesReceived;
8284
8285         sc->stat_XoffStateEntered =
8286             stats->stat_XoffStateEntered;
8287
8288         sc->stat_IfInFramesL2FilterDiscards =
8289             stats->stat_IfInFramesL2FilterDiscards;
8290
8291         sc->stat_IfInRuleCheckerDiscards =
8292             stats->stat_IfInRuleCheckerDiscards;
8293
8294         sc->stat_IfInFTQDiscards =
8295             stats->stat_IfInFTQDiscards;
8296
8297         sc->stat_IfInMBUFDiscards =
8298             stats->stat_IfInMBUFDiscards;
8299
8300         sc->stat_IfInRuleCheckerP4Hit =
8301             stats->stat_IfInRuleCheckerP4Hit;
8302
8303         sc->stat_CatchupInRuleCheckerDiscards =
8304             stats->stat_CatchupInRuleCheckerDiscards;
8305
8306         sc->stat_CatchupInFTQDiscards =
8307             stats->stat_CatchupInFTQDiscards;
8308
8309         sc->stat_CatchupInMBUFDiscards =
8310             stats->stat_CatchupInMBUFDiscards;
8311
8312         sc->stat_CatchupInRuleCheckerP4Hit =
8313             stats->stat_CatchupInRuleCheckerP4Hit;
8314
8315         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
8316
8317         /*
8318          * Update the interface statistics from the
8319          * hardware statistics.
8320          */
8321         ifp->if_collisions =
8322             (u_long) sc->stat_EtherStatsCollisions;
8323
8324         /* ToDo: This method loses soft errors. */
8325         ifp->if_ierrors =
8326             (u_long) sc->stat_EtherStatsUndersizePkts +
8327             (u_long) sc->stat_EtherStatsOversizePkts +
8328             (u_long) sc->stat_IfInMBUFDiscards +
8329             (u_long) sc->stat_Dot3StatsAlignmentErrors +
8330             (u_long) sc->stat_Dot3StatsFCSErrors +
8331             (u_long) sc->stat_IfInRuleCheckerDiscards +
8332             (u_long) sc->stat_IfInFTQDiscards +
8333             (u_long) sc->com_no_buffers;
8334
8335         /* ToDo: This method loses soft errors. */
8336         ifp->if_oerrors =
8337             (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
8338             (u_long) sc->stat_Dot3StatsExcessiveCollisions +
8339             (u_long) sc->stat_Dot3StatsLateCollisions;
8340
8341         /* ToDo: Add additional statistics? */
8342
8343         DBEXIT(BCE_EXTREME_MISC);
8344 }
8345
8346
8347 /****************************************************************************/
8348 /* Periodic function to notify the bootcode that the driver is still        */
8349 /* present.                                                                 */
8350 /*                                                                          */
8351 /* Returns:                                                                 */
8352 /*   Nothing.                                                               */
8353 /****************************************************************************/
8354 static void
8355 bce_pulse(void *xsc)
8356 {
8357         struct bce_softc *sc = xsc;
8358         u32 msg;
8359
8360         DBENTER(BCE_EXTREME_MISC);
8361
8362         BCE_LOCK_ASSERT(sc);
8363
8364         /* Tell the firmware that the driver is still running. */
8365         msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
8366         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
8367
8368         /* Update the bootcode condition. */
8369         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
8370
8371         /* Report whether the bootcode still knows the driver is running. */
8372         if (bce_verbose || bootverbose) {
8373                 if (sc->bce_drv_cardiac_arrest == FALSE) {
8374                         if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
8375                                 sc->bce_drv_cardiac_arrest = TRUE;
8376                                 BCE_PRINTF("%s(): Warning: bootcode "
8377                                     "thinks driver is absent! "
8378                                     "(bc_state = 0x%08X)\n",
8379                                     __FUNCTION__, sc->bc_state);
8380                         }
8381                 } else {
8382                         /*
8383                          * Not supported by all bootcode versions.
8384                          * (v5.0.11+ and v5.2.1+)  Older bootcode
8385                          * will require the driver to reset the
8386                          * controller to clear this condition.
8387                          */
8388                         if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
8389                                 sc->bce_drv_cardiac_arrest = FALSE;
8390                                 BCE_PRINTF("%s(): Bootcode found the "
8391                                     "driver pulse! (bc_state = 0x%08X)\n",
8392                                     __FUNCTION__, sc->bc_state);
8393                         }
8394                 }
8395         }
8396
8397
8398         /* Schedule the next pulse. */
8399         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
8400
8401         DBEXIT(BCE_EXTREME_MISC);
8402 }
8403
8404
8405 /****************************************************************************/
8406 /* Periodic function to perform maintenance tasks.                          */
8407 /*                                                                          */
8408 /* Returns:                                                                 */
8409 /*   Nothing.                                                               */
8410 /****************************************************************************/
8411 static void
8412 bce_tick(void *xsc)
8413 {
8414         struct bce_softc *sc = xsc;
8415         struct mii_data *mii;
8416         struct ifnet *ifp;
8417         struct ifmediareq ifmr;
8418
8419         ifp = sc->bce_ifp;
8420
8421         DBENTER(BCE_EXTREME_MISC);
8422
8423         BCE_LOCK_ASSERT(sc);
8424
8425         /* Schedule the next tick. */
8426         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
8427
8428         /* Update the statistics from the hardware statistics block. */
8429         bce_stats_update(sc);
8430
8431         /* Ensure page and RX chains get refilled in low-memory situations. */
8432         if (bce_hdr_split == TRUE)
8433                 bce_fill_pg_chain(sc);
8434         bce_fill_rx_chain(sc);
8435
8436         /* Check that chip hasn't hung. */
8437         bce_watchdog(sc);
8438
8439         /* If link is up already up then we're done. */
8440         if (sc->bce_link_up == TRUE)
8441                 goto bce_tick_exit;
8442
8443         /* Link is down.  Check what the PHY's doing. */
8444         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
8445                 bzero(&ifmr, sizeof(ifmr));
8446                 bce_ifmedia_sts_rphy(sc, &ifmr);
8447                 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) ==
8448                     (IFM_ACTIVE | IFM_AVALID)) {
8449                         sc->bce_link_up = TRUE;
8450                         bce_miibus_statchg(sc->bce_dev);
8451                 }
8452         } else {
8453                 mii = device_get_softc(sc->bce_miibus);
8454                 mii_tick(mii);
8455                 /* Check if the link has come up. */
8456                 if ((mii->mii_media_status & IFM_ACTIVE) &&
8457                     (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
8458                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n",
8459                             __FUNCTION__);
8460                         sc->bce_link_up = TRUE;
8461                         if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
8462                             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
8463                             IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
8464                             (bce_verbose || bootverbose))
8465                                 BCE_PRINTF("Gigabit link up!\n");
8466                 }
8467
8468         }
8469         if (sc->bce_link_up == TRUE) {
8470                 /* Now that link is up, handle any outstanding TX traffic. */
8471                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
8472                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
8473                             "pending TX traffic.\n", __FUNCTION__);
8474                         bce_start_locked(ifp);
8475                 }
8476         }
8477
8478 bce_tick_exit:
8479         DBEXIT(BCE_EXTREME_MISC);
8480 }
8481
8482 static void
8483 bce_fw_cap_init(struct bce_softc *sc)
8484 {
8485         u32 ack, cap, link;
8486
8487         ack = 0;
8488         cap = bce_shmem_rd(sc, BCE_FW_CAP_MB);
8489         if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) !=
8490             BCE_FW_CAP_SIGNATURE_MAGIC)
8491                 return;
8492         if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) ==
8493             (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN))
8494                 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8495                     BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN;
8496         if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 &&
8497             (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) {
8498                 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8499                 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG;
8500                 link = bce_shmem_rd(sc, BCE_LINK_STATUS);
8501                 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0)
8502                         sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8503                 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8504                     BCE_FW_CAP_REMOTE_PHY_CAP;
8505         }
8506
8507         if (ack != 0)
8508                 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack);
8509 }
8510
8511
8512 #ifdef BCE_DEBUG
8513 /****************************************************************************/
8514 /* Allows the driver state to be dumped through the sysctl interface.       */
8515 /*                                                                          */
8516 /* Returns:                                                                 */
8517 /*   0 for success, positive value for failure.                             */
8518 /****************************************************************************/
8519 static int
8520 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
8521 {
8522         int error;
8523         int result;
8524         struct bce_softc *sc;
8525
8526         result = -1;
8527         error = sysctl_handle_int(oidp, &result, 0, req);
8528
8529         if (error || !req->newptr)
8530                 return (error);
8531
8532         if (result == 1) {
8533                 sc = (struct bce_softc *)arg1;
8534                 bce_dump_driver_state(sc);
8535         }
8536
8537         return error;
8538 }
8539
8540
8541 /****************************************************************************/
8542 /* Allows the hardware state to be dumped through the sysctl interface.     */
8543 /*                                                                          */
8544 /* Returns:                                                                 */
8545 /*   0 for success, positive value for failure.                             */
8546 /****************************************************************************/
8547 static int
8548 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
8549 {
8550         int error;
8551         int result;
8552         struct bce_softc *sc;
8553
8554         result = -1;
8555         error = sysctl_handle_int(oidp, &result, 0, req);
8556
8557         if (error || !req->newptr)
8558                 return (error);
8559
8560         if (result == 1) {
8561                 sc = (struct bce_softc *)arg1;
8562                 bce_dump_hw_state(sc);
8563         }
8564
8565         return error;
8566 }
8567
8568
8569 /****************************************************************************/
8570 /* Allows the status block to be dumped through the sysctl interface.       */
8571 /*                                                                          */
8572 /* Returns:                                                                 */
8573 /*   0 for success, positive value for failure.                             */
8574 /****************************************************************************/
8575 static int
8576 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS)
8577 {
8578         int error;
8579         int result;
8580         struct bce_softc *sc;
8581
8582         result = -1;
8583         error = sysctl_handle_int(oidp, &result, 0, req);
8584
8585         if (error || !req->newptr)
8586                 return (error);
8587
8588         if (result == 1) {
8589                 sc = (struct bce_softc *)arg1;
8590                 bce_dump_status_block(sc);
8591         }
8592
8593         return error;
8594 }
8595
8596
8597 /****************************************************************************/
8598 /* Allows the stats block to be dumped through the sysctl interface.        */
8599 /*                                                                          */
8600 /* Returns:                                                                 */
8601 /*   0 for success, positive value for failure.                             */
8602 /****************************************************************************/
8603 static int
8604 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS)
8605 {
8606         int error;
8607         int result;
8608         struct bce_softc *sc;
8609
8610         result = -1;
8611         error = sysctl_handle_int(oidp, &result, 0, req);
8612
8613         if (error || !req->newptr)
8614                 return (error);
8615
8616         if (result == 1) {
8617                 sc = (struct bce_softc *)arg1;
8618                 bce_dump_stats_block(sc);
8619         }
8620
8621         return error;
8622 }
8623
8624
8625 /****************************************************************************/
8626 /* Allows the stat counters to be cleared without unloading/reloading the   */
8627 /* driver.                                                                  */
8628 /*                                                                          */
8629 /* Returns:                                                                 */
8630 /*   0 for success, positive value for failure.                             */
8631 /****************************************************************************/
8632 static int
8633 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS)
8634 {
8635         int error;
8636         int result;
8637         struct bce_softc *sc;
8638
8639         result = -1;
8640         error = sysctl_handle_int(oidp, &result, 0, req);
8641
8642         if (error || !req->newptr)
8643                 return (error);
8644
8645         if (result == 1) {
8646                 sc = (struct bce_softc *)arg1;
8647                 struct statistics_block *stats;
8648
8649                 stats = (struct statistics_block *) sc->stats_block;
8650                 bzero(stats, sizeof(struct statistics_block));
8651                 bus_dmamap_sync(sc->stats_tag, sc->stats_map,
8652                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
8653
8654                 /* Clear the internal H/W statistics counters. */
8655                 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
8656
8657                 /* Reset the driver maintained statistics. */
8658                 sc->interrupts_rx =
8659                     sc->interrupts_tx = 0;
8660                 sc->tso_frames_requested =
8661                     sc->tso_frames_completed =
8662                     sc->tso_frames_failed = 0;
8663                 sc->rx_empty_count =
8664                     sc->tx_full_count = 0;
8665                 sc->rx_low_watermark = USABLE_RX_BD_ALLOC;
8666                 sc->tx_hi_watermark = 0;
8667                 sc->l2fhdr_error_count =
8668                     sc->l2fhdr_error_sim_count = 0;
8669                 sc->mbuf_alloc_failed_count =
8670                     sc->mbuf_alloc_failed_sim_count = 0;
8671                 sc->dma_map_addr_rx_failed_count =
8672                     sc->dma_map_addr_tx_failed_count = 0;
8673                 sc->mbuf_frag_count = 0;
8674                 sc->csum_offload_tcp_udp =
8675                     sc->csum_offload_ip = 0;
8676                 sc->vlan_tagged_frames_rcvd =
8677                     sc->vlan_tagged_frames_stripped = 0;
8678                 sc->split_header_frames_rcvd =
8679                     sc->split_header_tcp_frames_rcvd = 0;
8680
8681                 /* Clear firmware maintained statistics. */
8682                 REG_WR_IND(sc, 0x120084, 0);
8683         }
8684
8685         return error;
8686 }
8687
8688
8689 /****************************************************************************/
8690 /* Allows the shared memory contents to be dumped through the sysctl  .     */
8691 /* interface.                                                               */
8692 /*                                                                          */
8693 /* Returns:                                                                 */
8694 /*   0 for success, positive value for failure.                             */
8695 /****************************************************************************/
8696 static int
8697 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS)
8698 {
8699         int error;
8700         int result;
8701         struct bce_softc *sc;
8702
8703         result = -1;
8704         error = sysctl_handle_int(oidp, &result, 0, req);
8705
8706         if (error || !req->newptr)
8707                 return (error);
8708
8709         if (result == 1) {
8710                 sc = (struct bce_softc *)arg1;
8711                 bce_dump_shmem_state(sc);
8712         }
8713
8714         return error;
8715 }
8716
8717
8718 /****************************************************************************/
8719 /* Allows the bootcode state to be dumped through the sysctl interface.     */
8720 /*                                                                          */
8721 /* Returns:                                                                 */
8722 /*   0 for success, positive value for failure.                             */
8723 /****************************************************************************/
8724 static int
8725 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS)
8726 {
8727         int error;
8728         int result;
8729         struct bce_softc *sc;
8730
8731         result = -1;
8732         error = sysctl_handle_int(oidp, &result, 0, req);
8733
8734         if (error || !req->newptr)
8735                 return (error);
8736
8737         if (result == 1) {
8738                 sc = (struct bce_softc *)arg1;
8739                 bce_dump_bc_state(sc);
8740         }
8741
8742         return error;
8743 }
8744
8745
8746 /****************************************************************************/
8747 /* Provides a sysctl interface to allow dumping the RX BD chain.            */
8748 /*                                                                          */
8749 /* Returns:                                                                 */
8750 /*   0 for success, positive value for failure.                             */
8751 /****************************************************************************/
8752 static int
8753 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS)
8754 {
8755         int error;
8756         int result;
8757         struct bce_softc *sc;
8758
8759         result = -1;
8760         error = sysctl_handle_int(oidp, &result, 0, req);
8761
8762         if (error || !req->newptr)
8763                 return (error);
8764
8765         if (result == 1) {
8766                 sc = (struct bce_softc *)arg1;
8767                 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC);
8768         }
8769
8770         return error;
8771 }
8772
8773
8774 /****************************************************************************/
8775 /* Provides a sysctl interface to allow dumping the RX MBUF chain.          */
8776 /*                                                                          */
8777 /* Returns:                                                                 */
8778 /*   0 for success, positive value for failure.                             */
8779 /****************************************************************************/
8780 static int
8781 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS)
8782 {
8783         int error;
8784         int result;
8785         struct bce_softc *sc;
8786
8787         result = -1;
8788         error = sysctl_handle_int(oidp, &result, 0, req);
8789
8790         if (error || !req->newptr)
8791                 return (error);
8792
8793         if (result == 1) {
8794                 sc = (struct bce_softc *)arg1;
8795                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
8796         }
8797
8798         return error;
8799 }
8800
8801
8802 /****************************************************************************/
8803 /* Provides a sysctl interface to allow dumping the TX chain.               */
8804 /*                                                                          */
8805 /* Returns:                                                                 */
8806 /*   0 for success, positive value for failure.                             */
8807 /****************************************************************************/
8808 static int
8809 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
8810 {
8811         int error;
8812         int result;
8813         struct bce_softc *sc;
8814
8815         result = -1;
8816         error = sysctl_handle_int(oidp, &result, 0, req);
8817
8818         if (error || !req->newptr)
8819                 return (error);
8820
8821         if (result == 1) {
8822                 sc = (struct bce_softc *)arg1;
8823                 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC);
8824         }
8825
8826         return error;
8827 }
8828
8829
8830 /****************************************************************************/
8831 /* Provides a sysctl interface to allow dumping the page chain.             */
8832 /*                                                                          */
8833 /* Returns:                                                                 */
8834 /*   0 for success, positive value for failure.                             */
8835 /****************************************************************************/
8836 static int
8837 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS)
8838 {
8839         int error;
8840         int result;
8841         struct bce_softc *sc;
8842
8843         result = -1;
8844         error = sysctl_handle_int(oidp, &result, 0, req);
8845
8846         if (error || !req->newptr)
8847                 return (error);
8848
8849         if (result == 1) {
8850                 sc = (struct bce_softc *)arg1;
8851                 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC);
8852         }
8853
8854         return error;
8855 }
8856
8857 /****************************************************************************/
8858 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in  */
8859 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8860 /*                                                                          */
8861 /* Returns:                                                                 */
8862 /*   0 for success, positive value for failure.                             */
8863 /****************************************************************************/
8864 static int
8865 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)
8866 {
8867         struct bce_softc *sc = (struct bce_softc *)arg1;
8868         int error;
8869         u32 result;
8870         u32 val[1];
8871         u8 *data = (u8 *) val;
8872
8873         result = -1;
8874         error = sysctl_handle_int(oidp, &result, 0, req);
8875         if (error || (req->newptr == NULL))
8876                 return (error);
8877
8878         error = bce_nvram_read(sc, result, data, 4);
8879
8880         BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
8881
8882         return (error);
8883 }
8884
8885
8886 /****************************************************************************/
8887 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
8888 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
8889 /*                                                                          */
8890 /* Returns:                                                                 */
8891 /*   0 for success, positive value for failure.                             */
8892 /****************************************************************************/
8893 static int
8894 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
8895 {
8896         struct bce_softc *sc = (struct bce_softc *)arg1;
8897         int error;
8898         u32 val, result;
8899
8900         result = -1;
8901         error = sysctl_handle_int(oidp, &result, 0, req);
8902         if (error || (req->newptr == NULL))
8903                 return (error);
8904
8905         /* Make sure the register is accessible. */
8906         if (result < 0x8000) {
8907                 val = REG_RD(sc, result);
8908                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8909         } else if (result < 0x0280000) {
8910                 val = REG_RD_IND(sc, result);
8911                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8912         }
8913
8914         return (error);
8915 }
8916
8917
8918 /****************************************************************************/
8919 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
8920 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8921 /*                                                                          */
8922 /* Returns:                                                                 */
8923 /*   0 for success, positive value for failure.                             */
8924 /****************************************************************************/
8925 static int
8926 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
8927 {
8928         struct bce_softc *sc;
8929         device_t dev;
8930         int error, result;
8931         u16 val;
8932
8933         result = -1;
8934         error = sysctl_handle_int(oidp, &result, 0, req);
8935         if (error || (req->newptr == NULL))
8936                 return (error);
8937
8938         /* Make sure the register is accessible. */
8939         if (result < 0x20) {
8940                 sc = (struct bce_softc *)arg1;
8941                 dev = sc->bce_dev;
8942                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
8943                 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
8944         }
8945         return (error);
8946 }
8947
8948
8949 /****************************************************************************/
8950 /* Provides a sysctl interface for dumping the nvram contents.              */
8951 /* DO NOT ENABLE ON PRODUCTION SYSTEMS!                                     */
8952 /*                                                                          */
8953 /* Returns:                                                                 */
8954 /*   0 for success, positive errno for failure.                             */
8955 /****************************************************************************/
8956 static int
8957 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS)
8958 {
8959         struct bce_softc *sc = (struct bce_softc *)arg1;
8960         int error, i;
8961
8962         if (sc->nvram_buf == NULL)
8963                 sc->nvram_buf = malloc(sc->bce_flash_size,
8964                                     M_TEMP, M_ZERO | M_WAITOK);
8965
8966         error = 0;
8967         if (req->oldlen == sc->bce_flash_size) {
8968                 for (i = 0; i < sc->bce_flash_size && error == 0; i++)
8969                         error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1);
8970         }
8971
8972         if (error == 0)
8973                 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size);
8974
8975         return error;
8976 }
8977
8978 #ifdef BCE_NVRAM_WRITE_SUPPORT
8979 /****************************************************************************/
8980 /* Provides a sysctl interface for writing to nvram.                        */
8981 /* DO NOT ENABLE ON PRODUCTION SYSTEMS!                                     */
8982 /*                                                                          */
8983 /* Returns:                                                                 */
8984 /*   0 for success, positive errno for failure.                             */
8985 /****************************************************************************/
8986 static int
8987 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS)
8988 {
8989         struct bce_softc *sc = (struct bce_softc *)arg1;
8990         int error;
8991
8992         if (sc->nvram_buf == NULL)
8993                 sc->nvram_buf = malloc(sc->bce_flash_size,
8994                                     M_TEMP, M_ZERO | M_WAITOK);
8995         else
8996                 bzero(sc->nvram_buf, sc->bce_flash_size);
8997
8998         error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size);
8999         if (error == 0)
9000                 return (error);
9001
9002         if (req->newlen == sc->bce_flash_size)
9003                 error = bce_nvram_write(sc, 0, sc->nvram_buf,
9004                             sc->bce_flash_size);
9005
9006
9007         return error;
9008 }
9009 #endif
9010
9011
9012 /****************************************************************************/
9013 /* Provides a sysctl interface to allow reading a CID.                      */
9014 /*                                                                          */
9015 /* Returns:                                                                 */
9016 /*   0 for success, positive value for failure.                             */
9017 /****************************************************************************/
9018 static int
9019 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)
9020 {
9021         struct bce_softc *sc;
9022         int error, result;
9023
9024         result = -1;
9025         error = sysctl_handle_int(oidp, &result, 0, req);
9026         if (error || (req->newptr == NULL))
9027                 return (error);
9028
9029         /* Make sure the register is accessible. */
9030         if (result <= TX_CID) {
9031                 sc = (struct bce_softc *)arg1;
9032                 bce_dump_ctx(sc, result);
9033         }
9034
9035         return (error);
9036 }
9037
9038
9039 /****************************************************************************/
9040 /* Provides a sysctl interface to forcing the driver to dump state and      */
9041 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
9042 /*                                                                          */
9043 /* Returns:                                                                 */
9044 /*   0 for success, positive value for failure.                             */
9045 /****************************************************************************/
9046 static int
9047 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
9048 {
9049         int error;
9050         int result;
9051         struct bce_softc *sc;
9052
9053         result = -1;
9054         error = sysctl_handle_int(oidp, &result, 0, req);
9055
9056         if (error || !req->newptr)
9057                 return (error);
9058
9059         if (result == 1) {
9060                 sc = (struct bce_softc *)arg1;
9061                 bce_breakpoint(sc);
9062         }
9063
9064         return error;
9065 }
9066 #endif
9067
9068 /****************************************************************************/
9069 /* Adds any sysctl parameters for tuning or debugging purposes.             */
9070 /*                                                                          */
9071 /* Returns:                                                                 */
9072 /*   0 for success, positive value for failure.                             */
9073 /****************************************************************************/
9074 static void
9075 bce_add_sysctls(struct bce_softc *sc)
9076 {
9077         struct sysctl_ctx_list *ctx;
9078         struct sysctl_oid_list *children;
9079
9080         DBENTER(BCE_VERBOSE_MISC);
9081
9082         ctx = device_get_sysctl_ctx(sc->bce_dev);
9083         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
9084
9085 #ifdef BCE_DEBUG
9086         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9087             "l2fhdr_error_sim_control",
9088             CTLFLAG_RW, &l2fhdr_error_sim_control,
9089             0, "Debug control to force l2fhdr errors");
9090
9091         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9092             "l2fhdr_error_sim_count",
9093             CTLFLAG_RD, &sc->l2fhdr_error_sim_count,
9094             0, "Number of simulated l2_fhdr errors");
9095 #endif
9096
9097         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9098             "l2fhdr_error_count",
9099             CTLFLAG_RD, &sc->l2fhdr_error_count,
9100             0, "Number of l2_fhdr errors");
9101
9102 #ifdef BCE_DEBUG
9103         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9104             "mbuf_alloc_failed_sim_control",
9105             CTLFLAG_RW, &mbuf_alloc_failed_sim_control,
9106             0, "Debug control to force mbuf allocation failures");
9107
9108         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9109             "mbuf_alloc_failed_sim_count",
9110             CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count,
9111             0, "Number of simulated mbuf cluster allocation failures");
9112 #endif
9113
9114         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9115             "mbuf_alloc_failed_count",
9116             CTLFLAG_RD, &sc->mbuf_alloc_failed_count,
9117             0, "Number of mbuf allocation failures");
9118
9119         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9120             "mbuf_frag_count",
9121             CTLFLAG_RD, &sc->mbuf_frag_count,
9122             0, "Number of fragmented mbufs");
9123
9124 #ifdef BCE_DEBUG
9125         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9126             "dma_map_addr_failed_sim_control",
9127             CTLFLAG_RW, &dma_map_addr_failed_sim_control,
9128             0, "Debug control to force DMA mapping failures");
9129
9130         /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */
9131         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9132             "dma_map_addr_failed_sim_count",
9133             CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count,
9134             0, "Number of simulated DMA mapping failures");
9135
9136 #endif
9137
9138         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9139             "dma_map_addr_rx_failed_count",
9140             CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count,
9141             0, "Number of RX DMA mapping failures");
9142
9143         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9144             "dma_map_addr_tx_failed_count",
9145             CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count,
9146             0, "Number of TX DMA mapping failures");
9147
9148 #ifdef BCE_DEBUG
9149         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9150             "unexpected_attention_sim_control",
9151             CTLFLAG_RW, &unexpected_attention_sim_control,
9152             0, "Debug control to simulate unexpected attentions");
9153
9154         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9155             "unexpected_attention_sim_count",
9156             CTLFLAG_RW, &sc->unexpected_attention_sim_count,
9157             0, "Number of simulated unexpected attentions");
9158 #endif
9159
9160         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9161             "unexpected_attention_count",
9162             CTLFLAG_RW, &sc->unexpected_attention_count,
9163             0, "Number of unexpected attentions");
9164
9165 #ifdef BCE_DEBUG
9166         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9167             "debug_bootcode_running_failure",
9168             CTLFLAG_RW, &bootcode_running_failure_sim_control,
9169             0, "Debug control to force bootcode running failures");
9170
9171         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9172             "rx_low_watermark",
9173             CTLFLAG_RD, &sc->rx_low_watermark,
9174             0, "Lowest level of free rx_bd's");
9175
9176         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9177             "rx_empty_count",
9178             CTLFLAG_RD, &sc->rx_empty_count,
9179             "Number of times the RX chain was empty");
9180
9181         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9182             "tx_hi_watermark",
9183             CTLFLAG_RD, &sc->tx_hi_watermark,
9184             0, "Highest level of used tx_bd's");
9185
9186         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9187             "tx_full_count",
9188             CTLFLAG_RD, &sc->tx_full_count,
9189             "Number of times the TX chain was full");
9190
9191         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9192             "tso_frames_requested",
9193             CTLFLAG_RD, &sc->tso_frames_requested,
9194             "Number of TSO frames requested");
9195
9196         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9197             "tso_frames_completed",
9198             CTLFLAG_RD, &sc->tso_frames_completed,
9199             "Number of TSO frames completed");
9200
9201         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9202             "tso_frames_failed",
9203             CTLFLAG_RD, &sc->tso_frames_failed,
9204             "Number of TSO frames failed");
9205
9206         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9207             "csum_offload_ip",
9208             CTLFLAG_RD, &sc->csum_offload_ip,
9209             "Number of IP checksum offload frames");
9210
9211         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9212             "csum_offload_tcp_udp",
9213             CTLFLAG_RD, &sc->csum_offload_tcp_udp,
9214             "Number of TCP/UDP checksum offload frames");
9215
9216         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9217             "vlan_tagged_frames_rcvd",
9218             CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd,
9219             "Number of VLAN tagged frames received");
9220
9221         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9222             "vlan_tagged_frames_stripped",
9223             CTLFLAG_RD, &sc->vlan_tagged_frames_stripped,
9224             "Number of VLAN tagged frames stripped");
9225
9226         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9227             "interrupts_rx",
9228             CTLFLAG_RD, &sc->interrupts_rx,
9229             "Number of RX interrupts");
9230
9231         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9232             "interrupts_tx",
9233             CTLFLAG_RD, &sc->interrupts_tx,
9234             "Number of TX interrupts");
9235
9236         if (bce_hdr_split == TRUE) {
9237                 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9238                     "split_header_frames_rcvd",
9239                     CTLFLAG_RD, &sc->split_header_frames_rcvd,
9240                     "Number of split header frames received");
9241
9242                 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9243                     "split_header_tcp_frames_rcvd",
9244                     CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd,
9245                     "Number of split header TCP frames received");
9246         }
9247
9248         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9249             "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD,
9250             (void *)sc, 0,
9251             bce_sysctl_nvram_dump, "S", "");
9252
9253 #ifdef BCE_NVRAM_WRITE_SUPPORT
9254         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9255             "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR,
9256             (void *)sc, 0,
9257             bce_sysctl_nvram_write, "S", "");
9258 #endif
9259 #endif /* BCE_DEBUG */
9260
9261         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9262             "stat_IfHcInOctets",
9263             CTLFLAG_RD, &sc->stat_IfHCInOctets,
9264             "Bytes received");
9265
9266         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9267             "stat_IfHCInBadOctets",
9268             CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
9269             "Bad bytes received");
9270
9271         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9272             "stat_IfHCOutOctets",
9273             CTLFLAG_RD, &sc->stat_IfHCOutOctets,
9274             "Bytes sent");
9275
9276         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9277             "stat_IfHCOutBadOctets",
9278             CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
9279             "Bad bytes sent");
9280
9281         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9282             "stat_IfHCInUcastPkts",
9283             CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
9284             "Unicast packets received");
9285
9286         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9287             "stat_IfHCInMulticastPkts",
9288             CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
9289             "Multicast packets received");
9290
9291         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9292             "stat_IfHCInBroadcastPkts",
9293             CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
9294             "Broadcast packets received");
9295
9296         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9297             "stat_IfHCOutUcastPkts",
9298             CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
9299             "Unicast packets sent");
9300
9301         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9302             "stat_IfHCOutMulticastPkts",
9303             CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
9304             "Multicast packets sent");
9305
9306         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9307             "stat_IfHCOutBroadcastPkts",
9308             CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
9309             "Broadcast packets sent");
9310
9311         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9312             "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
9313             CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
9314             0, "Internal MAC transmit errors");
9315
9316         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9317             "stat_Dot3StatsCarrierSenseErrors",
9318             CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
9319             0, "Carrier sense errors");
9320
9321         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9322             "stat_Dot3StatsFCSErrors",
9323             CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
9324             0, "Frame check sequence errors");
9325
9326         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9327             "stat_Dot3StatsAlignmentErrors",
9328             CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
9329             0, "Alignment errors");
9330
9331         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9332             "stat_Dot3StatsSingleCollisionFrames",
9333             CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
9334             0, "Single Collision Frames");
9335
9336         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9337             "stat_Dot3StatsMultipleCollisionFrames",
9338             CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
9339             0, "Multiple Collision Frames");
9340
9341         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9342             "stat_Dot3StatsDeferredTransmissions",
9343             CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
9344             0, "Deferred Transmissions");
9345
9346         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9347             "stat_Dot3StatsExcessiveCollisions",
9348             CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
9349             0, "Excessive Collisions");
9350
9351         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9352             "stat_Dot3StatsLateCollisions",
9353             CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
9354             0, "Late Collisions");
9355
9356         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9357             "stat_EtherStatsCollisions",
9358             CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
9359             0, "Collisions");
9360
9361         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9362             "stat_EtherStatsFragments",
9363             CTLFLAG_RD, &sc->stat_EtherStatsFragments,
9364             0, "Fragments");
9365
9366         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9367             "stat_EtherStatsJabbers",
9368             CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
9369             0, "Jabbers");
9370
9371         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9372             "stat_EtherStatsUndersizePkts",
9373             CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
9374             0, "Undersize packets");
9375
9376         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9377             "stat_EtherStatsOversizePkts",
9378             CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts,
9379             0, "stat_EtherStatsOversizePkts");
9380
9381         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9382             "stat_EtherStatsPktsRx64Octets",
9383             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
9384             0, "Bytes received in 64 byte packets");
9385
9386         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9387             "stat_EtherStatsPktsRx65Octetsto127Octets",
9388             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
9389             0, "Bytes received in 65 to 127 byte packets");
9390
9391         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9392             "stat_EtherStatsPktsRx128Octetsto255Octets",
9393             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
9394             0, "Bytes received in 128 to 255 byte packets");
9395
9396         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9397             "stat_EtherStatsPktsRx256Octetsto511Octets",
9398             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
9399             0, "Bytes received in 256 to 511 byte packets");
9400
9401         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9402             "stat_EtherStatsPktsRx512Octetsto1023Octets",
9403             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
9404             0, "Bytes received in 512 to 1023 byte packets");
9405
9406         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9407             "stat_EtherStatsPktsRx1024Octetsto1522Octets",
9408             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
9409             0, "Bytes received in 1024 t0 1522 byte packets");
9410
9411         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9412             "stat_EtherStatsPktsRx1523Octetsto9022Octets",
9413             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
9414             0, "Bytes received in 1523 to 9022 byte packets");
9415
9416         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9417             "stat_EtherStatsPktsTx64Octets",
9418             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
9419             0, "Bytes sent in 64 byte packets");
9420
9421         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9422             "stat_EtherStatsPktsTx65Octetsto127Octets",
9423             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
9424             0, "Bytes sent in 65 to 127 byte packets");
9425
9426         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9427             "stat_EtherStatsPktsTx128Octetsto255Octets",
9428             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
9429             0, "Bytes sent in 128 to 255 byte packets");
9430
9431         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9432             "stat_EtherStatsPktsTx256Octetsto511Octets",
9433             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
9434             0, "Bytes sent in 256 to 511 byte packets");
9435
9436         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9437             "stat_EtherStatsPktsTx512Octetsto1023Octets",
9438             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
9439             0, "Bytes sent in 512 to 1023 byte packets");
9440
9441         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9442             "stat_EtherStatsPktsTx1024Octetsto1522Octets",
9443             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
9444             0, "Bytes sent in 1024 to 1522 byte packets");
9445
9446         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9447             "stat_EtherStatsPktsTx1523Octetsto9022Octets",
9448             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
9449             0, "Bytes sent in 1523 to 9022 byte packets");
9450
9451         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9452             "stat_XonPauseFramesReceived",
9453             CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
9454             0, "XON pause frames receved");
9455
9456         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9457             "stat_XoffPauseFramesReceived",
9458             CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
9459             0, "XOFF pause frames received");
9460
9461         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9462             "stat_OutXonSent",
9463             CTLFLAG_RD, &sc->stat_OutXonSent,
9464             0, "XON pause frames sent");
9465
9466         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9467             "stat_OutXoffSent",
9468             CTLFLAG_RD, &sc->stat_OutXoffSent,
9469             0, "XOFF pause frames sent");
9470
9471         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9472             "stat_FlowControlDone",
9473             CTLFLAG_RD, &sc->stat_FlowControlDone,
9474             0, "Flow control done");
9475
9476         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9477             "stat_MacControlFramesReceived",
9478             CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
9479             0, "MAC control frames received");
9480
9481         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9482             "stat_XoffStateEntered",
9483             CTLFLAG_RD, &sc->stat_XoffStateEntered,
9484             0, "XOFF state entered");
9485
9486         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9487             "stat_IfInFramesL2FilterDiscards",
9488             CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
9489             0, "Received L2 packets discarded");
9490
9491         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9492             "stat_IfInRuleCheckerDiscards",
9493             CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
9494             0, "Received packets discarded by rule");
9495
9496         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9497             "stat_IfInFTQDiscards",
9498             CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
9499             0, "Received packet FTQ discards");
9500
9501         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9502             "stat_IfInMBUFDiscards",
9503             CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
9504             0, "Received packets discarded due to lack "
9505             "of controller buffer memory");
9506
9507         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9508             "stat_IfInRuleCheckerP4Hit",
9509             CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
9510             0, "Received packets rule checker hits");
9511
9512         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9513             "stat_CatchupInRuleCheckerDiscards",
9514             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
9515             0, "Received packets discarded in Catchup path");
9516
9517         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9518             "stat_CatchupInFTQDiscards",
9519             CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
9520             0, "Received packets discarded in FTQ in Catchup path");
9521
9522         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9523             "stat_CatchupInMBUFDiscards",
9524             CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
9525             0, "Received packets discarded in controller "
9526             "buffer memory in Catchup path");
9527
9528         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9529             "stat_CatchupInRuleCheckerP4Hit",
9530             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
9531             0, "Received packets rule checker hits in Catchup path");
9532
9533         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9534             "com_no_buffers",
9535             CTLFLAG_RD, &sc->com_no_buffers,
9536             0, "Valid packets received but no RX buffers available");
9537
9538 #ifdef BCE_DEBUG
9539         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9540             "driver_state", CTLTYPE_INT | CTLFLAG_RW,
9541             (void *)sc, 0,
9542             bce_sysctl_driver_state, "I", "Drive state information");
9543
9544         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9545             "hw_state", CTLTYPE_INT | CTLFLAG_RW,
9546             (void *)sc, 0,
9547             bce_sysctl_hw_state, "I", "Hardware state information");
9548
9549         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9550             "status_block", CTLTYPE_INT | CTLFLAG_RW,
9551             (void *)sc, 0,
9552             bce_sysctl_status_block, "I", "Dump status block");
9553
9554         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9555             "stats_block", CTLTYPE_INT | CTLFLAG_RW,
9556             (void *)sc, 0,
9557             bce_sysctl_stats_block, "I", "Dump statistics block");
9558
9559         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9560             "stats_clear", CTLTYPE_INT | CTLFLAG_RW,
9561             (void *)sc, 0,
9562             bce_sysctl_stats_clear, "I", "Clear statistics block");
9563
9564         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9565             "shmem_state", CTLTYPE_INT | CTLFLAG_RW,
9566             (void *)sc, 0,
9567             bce_sysctl_shmem_state, "I", "Shared memory state information");
9568
9569         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9570             "bc_state", CTLTYPE_INT | CTLFLAG_RW,
9571             (void *)sc, 0,
9572             bce_sysctl_bc_state, "I", "Bootcode state information");
9573
9574         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9575             "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW,
9576             (void *)sc, 0,
9577             bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain");
9578
9579         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9580             "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW,
9581             (void *)sc, 0,
9582             bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain");
9583
9584         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9585             "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
9586             (void *)sc, 0,
9587             bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
9588
9589         if (bce_hdr_split == TRUE) {
9590                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9591                     "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW,
9592                     (void *)sc, 0,
9593                     bce_sysctl_dump_pg_chain, "I", "Dump page chain");
9594         }
9595
9596         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9597             "dump_ctx", CTLTYPE_INT | CTLFLAG_RW,
9598             (void *)sc, 0,
9599             bce_sysctl_dump_ctx, "I", "Dump context memory");
9600
9601         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9602             "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
9603             (void *)sc, 0,
9604             bce_sysctl_breakpoint, "I", "Driver breakpoint");
9605
9606         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9607             "reg_read", CTLTYPE_INT | CTLFLAG_RW,
9608             (void *)sc, 0,
9609             bce_sysctl_reg_read, "I", "Register read");
9610
9611         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9612             "nvram_read", CTLTYPE_INT | CTLFLAG_RW,
9613             (void *)sc, 0,
9614             bce_sysctl_nvram_read, "I", "NVRAM read");
9615
9616         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9617             "phy_read", CTLTYPE_INT | CTLFLAG_RW,
9618             (void *)sc, 0,
9619             bce_sysctl_phy_read, "I", "PHY register read");
9620
9621 #endif
9622
9623         DBEXIT(BCE_VERBOSE_MISC);
9624 }
9625
9626
9627 /****************************************************************************/
9628 /* BCE Debug Routines                                                       */
9629 /****************************************************************************/
9630 #ifdef BCE_DEBUG
9631
9632 /****************************************************************************/
9633 /* Freezes the controller to allow for a cohesive state dump.               */
9634 /*                                                                          */
9635 /* Returns:                                                                 */
9636 /*   Nothing.                                                               */
9637 /****************************************************************************/
9638 static __attribute__ ((noinline)) void
9639 bce_freeze_controller(struct bce_softc *sc)
9640 {
9641         u32 val;
9642         val = REG_RD(sc, BCE_MISC_COMMAND);
9643         val |= BCE_MISC_COMMAND_DISABLE_ALL;
9644         REG_WR(sc, BCE_MISC_COMMAND, val);
9645 }
9646
9647
9648 /****************************************************************************/
9649 /* Unfreezes the controller after a freeze operation.  This may not always  */
9650 /* work and the controller will require a reset!                            */
9651 /*                                                                          */
9652 /* Returns:                                                                 */
9653 /*   Nothing.                                                               */
9654 /****************************************************************************/
9655 static __attribute__ ((noinline)) void
9656 bce_unfreeze_controller(struct bce_softc *sc)
9657 {
9658         u32 val;
9659         val = REG_RD(sc, BCE_MISC_COMMAND);
9660         val |= BCE_MISC_COMMAND_ENABLE_ALL;
9661         REG_WR(sc, BCE_MISC_COMMAND, val);
9662 }
9663
9664
9665 /****************************************************************************/
9666 /* Prints out Ethernet frame information from an mbuf.                      */
9667 /*                                                                          */
9668 /* Partially decode an Ethernet frame to look at some important headers.    */
9669 /*                                                                          */
9670 /* Returns:                                                                 */
9671 /*   Nothing.                                                               */
9672 /****************************************************************************/
9673 static __attribute__ ((noinline)) void
9674 bce_dump_enet(struct bce_softc *sc, struct mbuf *m)
9675 {
9676         struct ether_vlan_header *eh;
9677         u16 etype;
9678         int ehlen;
9679         struct ip *ip;
9680         struct tcphdr *th;
9681         struct udphdr *uh;
9682         struct arphdr *ah;
9683
9684         BCE_PRINTF(
9685             "-----------------------------"
9686             " Frame Decode "
9687             "-----------------------------\n");
9688
9689         eh = mtod(m, struct ether_vlan_header *);
9690
9691         /* Handle VLAN encapsulation if present. */
9692         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
9693                 etype = ntohs(eh->evl_proto);
9694                 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
9695         } else {
9696                 etype = ntohs(eh->evl_encap_proto);
9697                 ehlen = ETHER_HDR_LEN;
9698         }
9699
9700         /* ToDo: Add VLAN output. */
9701         BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n",
9702             eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen);
9703
9704         switch (etype) {
9705         case ETHERTYPE_IP:
9706                 ip = (struct ip *)(m->m_data + ehlen);
9707                 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, "
9708                     "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n",
9709                     ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
9710                     ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum));
9711
9712                 switch (ip->ip_p) {
9713                 case IPPROTO_TCP:
9714                         th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9715                         BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = "
9716                             "%d bytes, flags = 0x%b, csum = 0x%04X\n",
9717                             ntohs(th->th_dport), ntohs(th->th_sport),
9718                             (th->th_off << 2), th->th_flags,
9719                             "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST"
9720                             "\02SYN\01FIN", ntohs(th->th_sum));
9721                         break;
9722                 case IPPROTO_UDP:
9723                         uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9724                         BCE_PRINTF("-udp: dest = %d, src = %d, len = %d "
9725                             "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport),
9726                             ntohs(uh->uh_sport), ntohs(uh->uh_ulen),
9727                             ntohs(uh->uh_sum));
9728                         break;
9729                 case IPPROTO_ICMP:
9730                         BCE_PRINTF("icmp:\n");
9731                         break;
9732                 default:
9733                         BCE_PRINTF("----: Other IP protocol.\n");
9734                         }
9735                 break;
9736         case ETHERTYPE_IPV6:
9737                 BCE_PRINTF("ipv6: No decode supported.\n");
9738                 break;
9739         case ETHERTYPE_ARP:
9740                 BCE_PRINTF("-arp: ");
9741                 ah = (struct arphdr *) (m->m_data + ehlen);
9742                 switch (ntohs(ah->ar_op)) {
9743                 case ARPOP_REVREQUEST:
9744                         printf("reverse ARP request\n");
9745                         break;
9746                 case ARPOP_REVREPLY:
9747                         printf("reverse ARP reply\n");
9748                         break;
9749                 case ARPOP_REQUEST:
9750                         printf("ARP request\n");
9751                         break;
9752                 case ARPOP_REPLY:
9753                         printf("ARP reply\n");
9754                         break;
9755                 default:
9756                         printf("other ARP operation\n");
9757                 }
9758                 break;
9759         default:
9760                 BCE_PRINTF("----: Other protocol.\n");
9761         }
9762
9763         BCE_PRINTF(
9764                 "-----------------------------"
9765                 "--------------"
9766                 "-----------------------------\n");
9767 }
9768
9769
9770 /****************************************************************************/
9771 /* Prints out information about an mbuf.                                    */
9772 /*                                                                          */
9773 /* Returns:                                                                 */
9774 /*   Nothing.                                                               */
9775 /****************************************************************************/
9776 static __attribute__ ((noinline)) void
9777 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
9778 {
9779         struct mbuf *mp = m;
9780
9781         if (m == NULL) {
9782                 BCE_PRINTF("mbuf: null pointer\n");
9783                 return;
9784         }
9785
9786         while (mp) {
9787                 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, "
9788                     "m_data = %p\n", mp, mp->m_len, mp->m_flags,
9789                     "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data);
9790
9791                 if (mp->m_flags & M_PKTHDR) {
9792                         BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
9793                             "csum_flags = %b\n", mp->m_pkthdr.len,
9794                             mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG"
9795                             "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG"
9796                             "\22M_PROMISC\23M_NOFREE",
9797                             mp->m_pkthdr.csum_flags,
9798                             "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
9799                             "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
9800                             "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
9801                             "\14CSUM_PSEUDO_HDR");
9802                 }
9803
9804                 if (mp->m_flags & M_EXT) {
9805                         BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
9806                             mp->m_ext.ext_buf, mp->m_ext.ext_size);
9807                         switch (mp->m_ext.ext_type) {
9808                         case EXT_CLUSTER:
9809                                 printf("EXT_CLUSTER\n"); break;
9810                         case EXT_SFBUF:
9811                                 printf("EXT_SFBUF\n"); break;
9812                         case EXT_JUMBO9:
9813                                 printf("EXT_JUMBO9\n"); break;
9814                         case EXT_JUMBO16:
9815                                 printf("EXT_JUMBO16\n"); break;
9816                         case EXT_PACKET:
9817                                 printf("EXT_PACKET\n"); break;
9818                         case EXT_MBUF:
9819                                 printf("EXT_MBUF\n"); break;
9820                         case EXT_NET_DRV:
9821                                 printf("EXT_NET_DRV\n"); break;
9822                         case EXT_MOD_TYPE:
9823                                 printf("EXT_MDD_TYPE\n"); break;
9824                         case EXT_DISPOSABLE:
9825                                 printf("EXT_DISPOSABLE\n"); break;
9826                         case EXT_EXTREF:
9827                                 printf("EXT_EXTREF\n"); break;
9828                         default:
9829                                 printf("UNKNOWN\n");
9830                         }
9831                 }
9832
9833                 mp = mp->m_next;
9834         }
9835 }
9836
9837
9838 /****************************************************************************/
9839 /* Prints out the mbufs in the TX mbuf chain.                               */
9840 /*                                                                          */
9841 /* Returns:                                                                 */
9842 /*   Nothing.                                                               */
9843 /****************************************************************************/
9844 static __attribute__ ((noinline)) void
9845 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9846 {
9847         struct mbuf *m;
9848
9849         BCE_PRINTF(
9850                 "----------------------------"
9851                 "  tx mbuf data  "
9852                 "----------------------------\n");
9853
9854         for (int i = 0; i < count; i++) {
9855                 m = sc->tx_mbuf_ptr[chain_prod];
9856                 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod);
9857                 bce_dump_mbuf(sc, m);
9858                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
9859         }
9860
9861         BCE_PRINTF(
9862                 "----------------------------"
9863                 "----------------"
9864                 "----------------------------\n");
9865 }
9866
9867
9868 /****************************************************************************/
9869 /* Prints out the mbufs in the RX mbuf chain.                               */
9870 /*                                                                          */
9871 /* Returns:                                                                 */
9872 /*   Nothing.                                                               */
9873 /****************************************************************************/
9874 static __attribute__ ((noinline)) void
9875 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9876 {
9877         struct mbuf *m;
9878
9879         BCE_PRINTF(
9880                 "----------------------------"
9881                 "  rx mbuf data  "
9882                 "----------------------------\n");
9883
9884         for (int i = 0; i < count; i++) {
9885                 m = sc->rx_mbuf_ptr[chain_prod];
9886                 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
9887                 bce_dump_mbuf(sc, m);
9888                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
9889         }
9890
9891
9892         BCE_PRINTF(
9893                 "----------------------------"
9894                 "----------------"
9895                 "----------------------------\n");
9896 }
9897
9898
9899 /****************************************************************************/
9900 /* Prints out the mbufs in the mbuf page chain.                             */
9901 /*                                                                          */
9902 /* Returns:                                                                 */
9903 /*   Nothing.                                                               */
9904 /****************************************************************************/
9905 static __attribute__ ((noinline)) void
9906 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9907 {
9908         struct mbuf *m;
9909
9910         BCE_PRINTF(
9911                 "----------------------------"
9912                 "  pg mbuf data  "
9913                 "----------------------------\n");
9914
9915         for (int i = 0; i < count; i++) {
9916                 m = sc->pg_mbuf_ptr[chain_prod];
9917                 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod);
9918                 bce_dump_mbuf(sc, m);
9919                 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod));
9920         }
9921
9922
9923         BCE_PRINTF(
9924                 "----------------------------"
9925                 "----------------"
9926                 "----------------------------\n");
9927 }
9928
9929
9930 /****************************************************************************/
9931 /* Prints out a tx_bd structure.                                            */
9932 /*                                                                          */
9933 /* Returns:                                                                 */
9934 /*   Nothing.                                                               */
9935 /****************************************************************************/
9936 static __attribute__ ((noinline)) void
9937 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
9938 {
9939         int i = 0;
9940
9941         if (idx > MAX_TX_BD_ALLOC)
9942                 /* Index out of range. */
9943                 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
9944         else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
9945                 /* TX Chain page pointer. */
9946                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
9947                     "pointer\n", idx, txbd->tx_bd_haddr_hi,
9948                     txbd->tx_bd_haddr_lo);
9949         else {
9950                 /* Normal tx_bd entry. */
9951                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
9952                     "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = "
9953                     "0x%04X (", idx, txbd->tx_bd_haddr_hi,
9954                     txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes,
9955                     txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
9956
9957                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) {
9958                         if (i>0)
9959                                 printf("|");
9960                         printf("CONN_FAULT");
9961                         i++;
9962                 }
9963
9964                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) {
9965                         if (i>0)
9966                                 printf("|");
9967                         printf("TCP_UDP_CKSUM");
9968                         i++;
9969                 }
9970
9971                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) {
9972                         if (i>0)
9973                                 printf("|");
9974                         printf("IP_CKSUM");
9975                         i++;
9976                 }
9977
9978                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) {
9979                         if (i>0)
9980                                 printf("|");
9981                         printf("VLAN");
9982                         i++;
9983                 }
9984
9985                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) {
9986                         if (i>0)
9987                                 printf("|");
9988                         printf("COAL_NOW");
9989                         i++;
9990                 }
9991
9992                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) {
9993                         if (i>0)
9994                                 printf("|");
9995                         printf("DONT_GEN_CRC");
9996                         i++;
9997                 }
9998
9999                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) {
10000                         if (i>0)
10001                                 printf("|");
10002                         printf("START");
10003                         i++;
10004                 }
10005
10006                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) {
10007                         if (i>0)
10008                                 printf("|");
10009                         printf("END");
10010                         i++;
10011                 }
10012
10013                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) {
10014                         if (i>0)
10015                                 printf("|");
10016                         printf("LSO");
10017                         i++;
10018                 }
10019
10020                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) {
10021                         if (i>0)
10022                                 printf("|");
10023                         printf("SW_OPTION=%d", ((txbd->tx_bd_flags &
10024                             TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++;
10025                 }
10026
10027                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) {
10028                         if (i>0)
10029                                 printf("|");
10030                         printf("SW_FLAGS");
10031                         i++;
10032                 }
10033
10034                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) {
10035                         if (i>0)
10036                                 printf("|");
10037                         printf("SNAP)");
10038                 } else {
10039                         printf(")\n");
10040                 }
10041         }
10042 }
10043
10044
10045 /****************************************************************************/
10046 /* Prints out a rx_bd structure.                                            */
10047 /*                                                                          */
10048 /* Returns:                                                                 */
10049 /*   Nothing.                                                               */
10050 /****************************************************************************/
10051 static __attribute__ ((noinline)) void
10052 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
10053 {
10054         if (idx > MAX_RX_BD_ALLOC)
10055                 /* Index out of range. */
10056                 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
10057         else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
10058                 /* RX Chain page pointer. */
10059                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
10060                     "pointer\n", idx, rxbd->rx_bd_haddr_hi,
10061                     rxbd->rx_bd_haddr_lo);
10062         else
10063                 /* Normal rx_bd entry. */
10064                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
10065                     "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi,
10066                     rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len,
10067                     rxbd->rx_bd_flags);
10068 }
10069
10070
10071 /****************************************************************************/
10072 /* Prints out a rx_bd structure in the page chain.                          */
10073 /*                                                                          */
10074 /* Returns:                                                                 */
10075 /*   Nothing.                                                               */
10076 /****************************************************************************/
10077 static __attribute__ ((noinline)) void
10078 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
10079 {
10080         if (idx > MAX_PG_BD_ALLOC)
10081                 /* Index out of range. */
10082                 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
10083         else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
10084                 /* Page Chain page pointer. */
10085                 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
10086                         idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
10087         else
10088                 /* Normal rx_bd entry. */
10089                 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
10090                         "flags = 0x%08X\n", idx,
10091                         pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
10092                         pgbd->rx_bd_len, pgbd->rx_bd_flags);
10093 }
10094
10095
10096 /****************************************************************************/
10097 /* Prints out a l2_fhdr structure.                                          */
10098 /*                                                                          */
10099 /* Returns:                                                                 */
10100 /*   Nothing.                                                               */
10101 /****************************************************************************/
10102 static __attribute__ ((noinline)) void
10103 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
10104 {
10105         BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
10106                 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
10107                 "tcp_udp_xsum = 0x%04X\n", idx,
10108                 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
10109                 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
10110                 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
10111 }
10112
10113
10114 /****************************************************************************/
10115 /* Prints out context memory info.  (Only useful for CID 0 to 16.)          */
10116 /*                                                                          */
10117 /* Returns:                                                                 */
10118 /*   Nothing.                                                               */
10119 /****************************************************************************/
10120 static __attribute__ ((noinline)) void
10121 bce_dump_ctx(struct bce_softc *sc, u16 cid)
10122 {
10123         if (cid > TX_CID) {
10124                 BCE_PRINTF(" Unknown CID\n");
10125                 return;
10126         }
10127
10128         BCE_PRINTF(
10129             "----------------------------"
10130             "    CTX Data    "
10131             "----------------------------\n");
10132
10133         BCE_PRINTF("     0x%04X - (CID) Context ID\n", cid);
10134
10135         if (cid == RX_CID) {
10136                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
10137                    "producer index\n",
10138                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX));
10139                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host "
10140                     "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10141                     BCE_L2CTX_RX_HOST_BSEQ));
10142                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
10143                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ));
10144                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
10145                     "descriptor address\n",
10146                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI));
10147                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
10148                     "descriptor address\n",
10149                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO));
10150                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer "
10151                     "index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10152                     BCE_L2CTX_RX_NX_BDIDX));
10153                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
10154                     "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10155                     BCE_L2CTX_RX_HOST_PG_BDIDX));
10156                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
10157                     "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid),
10158                     BCE_L2CTX_RX_PG_BUF_SIZE));
10159                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
10160                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10161                     BCE_L2CTX_RX_NX_PG_BDHADDR_HI));
10162                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
10163                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10164                     BCE_L2CTX_RX_NX_PG_BDHADDR_LO));
10165                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
10166                     "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10167                     BCE_L2CTX_RX_NX_PG_BDIDX));
10168         } else if (cid == TX_CID) {
10169                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10170                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
10171                             CTX_RD(sc, GET_CID_ADDR(cid),
10172                             BCE_L2CTX_TX_TYPE_XI));
10173                         BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx "
10174                             "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid),
10175                             BCE_L2CTX_TX_CMD_TYPE_XI));
10176                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) "
10177                             "h/w buffer descriptor address\n",
10178                             CTX_RD(sc, GET_CID_ADDR(cid),
10179                             BCE_L2CTX_TX_TBDR_BHADDR_HI_XI));
10180                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) "
10181                             "h/w buffer descriptor address\n",
10182                             CTX_RD(sc, GET_CID_ADDR(cid),
10183                             BCE_L2CTX_TX_TBDR_BHADDR_LO_XI));
10184                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) "
10185                             "host producer index\n",
10186                             CTX_RD(sc, GET_CID_ADDR(cid),
10187                             BCE_L2CTX_TX_HOST_BIDX_XI));
10188                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) "
10189                             "host byte sequence\n",
10190                             CTX_RD(sc, GET_CID_ADDR(cid),
10191                             BCE_L2CTX_TX_HOST_BSEQ_XI));
10192                 } else {
10193                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
10194                             CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE));
10195                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
10196                             CTX_RD(sc, GET_CID_ADDR(cid),
10197                             BCE_L2CTX_TX_CMD_TYPE));
10198                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) "
10199                             "h/w buffer descriptor address\n",
10200                             CTX_RD(sc, GET_CID_ADDR(cid),
10201                             BCE_L2CTX_TX_TBDR_BHADDR_HI));
10202                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) "
10203                             "h/w buffer descriptor address\n",
10204                             CTX_RD(sc, GET_CID_ADDR(cid),
10205                             BCE_L2CTX_TX_TBDR_BHADDR_LO));
10206                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host "
10207                             "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10208                             BCE_L2CTX_TX_HOST_BIDX));
10209                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
10210                             "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10211                             BCE_L2CTX_TX_HOST_BSEQ));
10212                 }
10213         }
10214
10215         BCE_PRINTF(
10216            "----------------------------"
10217            "    Raw CTX     "
10218            "----------------------------\n");
10219
10220         for (int i = 0x0; i < 0x300; i += 0x10) {
10221                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
10222                    CTX_RD(sc, GET_CID_ADDR(cid), i),
10223                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
10224                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
10225                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
10226         }
10227
10228
10229         BCE_PRINTF(
10230            "----------------------------"
10231            "----------------"
10232            "----------------------------\n");
10233 }
10234
10235
10236 /****************************************************************************/
10237 /* Prints out the FTQ data.                                                 */
10238 /*                                                                          */
10239 /* Returns:                                                                */
10240 /*   Nothing.                                                               */
10241 /****************************************************************************/
10242 static __attribute__ ((noinline)) void
10243 bce_dump_ftqs(struct bce_softc *sc)
10244 {
10245         u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
10246
10247         BCE_PRINTF(
10248             "----------------------------"
10249             "    FTQ Data    "
10250             "----------------------------\n");
10251
10252         BCE_PRINTF("   FTQ    Command    Control   Depth_Now  "
10253             "Max_Depth  Valid_Cnt \n");
10254         BCE_PRINTF(" ------- ---------- ---------- ---------- "
10255             "---------- ----------\n");
10256
10257         /* Setup the generic statistic counters for the FTQ valid count. */
10258         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
10259             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT  << 16) |
10260             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT   <<  8) |
10261             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT);
10262         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10263
10264         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT  << 24) |
10265             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT  << 16) |
10266             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT <<  8) |
10267             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT);
10268         REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
10269
10270         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT  << 24) |
10271             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT  << 16) |
10272             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT   <<  8) |
10273             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT);
10274         REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
10275
10276         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT   << 24) |
10277             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT  << 16) |
10278             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT  <<  8) |
10279             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT);
10280         REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
10281
10282         /* Input queue to the Receive Lookup state machine */
10283         cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
10284         ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
10285         cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
10286         max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
10287         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10288         BCE_PRINTF(" RLUP    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10289             cmd, ctl, cur_depth, max_depth, valid_cnt);
10290
10291         /* Input queue to the Receive Processor */
10292         cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
10293         ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
10294         cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
10295         max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
10296         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10297         BCE_PRINTF(" RXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10298             cmd, ctl, cur_depth, max_depth, valid_cnt);
10299
10300         /* Input queue to the Recevie Processor */
10301         cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
10302         ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
10303         cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
10304         max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
10305         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10306         BCE_PRINTF(" RXPC    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10307             cmd, ctl, cur_depth, max_depth, valid_cnt);
10308
10309         /* Input queue to the Receive Virtual to Physical state machine */
10310         cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
10311         ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
10312         cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
10313         max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
10314         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10315         BCE_PRINTF(" RV2PP   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10316             cmd, ctl, cur_depth, max_depth, valid_cnt);
10317
10318         /* Input queue to the Recevie Virtual to Physical state machine */
10319         cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
10320         ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
10321         cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
10322         max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
10323         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
10324         BCE_PRINTF(" RV2PM   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10325             cmd, ctl, cur_depth, max_depth, valid_cnt);
10326
10327         /* Input queue to the Receive Virtual to Physical state machine */
10328         cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
10329         ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
10330         cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
10331         max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
10332         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
10333         BCE_PRINTF(" RV2PT   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10334             cmd, ctl, cur_depth, max_depth, valid_cnt);
10335
10336         /* Input queue to the Receive DMA state machine */
10337         cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
10338         ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
10339         cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10340         max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10341         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
10342         BCE_PRINTF(" RDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10343             cmd, ctl, cur_depth, max_depth, valid_cnt);
10344
10345         /* Input queue to the Transmit Scheduler state machine */
10346         cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
10347         ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
10348         cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
10349         max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
10350         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
10351         BCE_PRINTF(" TSCH    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10352             cmd, ctl, cur_depth, max_depth, valid_cnt);
10353
10354         /* Input queue to the Transmit Buffer Descriptor state machine */
10355         cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
10356         ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
10357         cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
10358         max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
10359         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
10360         BCE_PRINTF(" TBDR    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10361             cmd, ctl, cur_depth, max_depth, valid_cnt);
10362
10363         /* Input queue to the Transmit Processor */
10364         cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
10365         ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
10366         cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
10367         max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
10368         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
10369         BCE_PRINTF(" TXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10370             cmd, ctl, cur_depth, max_depth, valid_cnt);
10371
10372         /* Input queue to the Transmit DMA state machine */
10373         cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
10374         ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
10375         cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10376         max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10377         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
10378         BCE_PRINTF(" TDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10379             cmd, ctl, cur_depth, max_depth, valid_cnt);
10380
10381         /* Input queue to the Transmit Patch-Up Processor */
10382         cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
10383         ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
10384         cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
10385         max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
10386         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
10387         BCE_PRINTF(" TPAT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10388             cmd, ctl, cur_depth, max_depth, valid_cnt);
10389
10390         /* Input queue to the Transmit Assembler state machine */
10391         cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
10392         ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
10393         cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
10394         max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
10395         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
10396         BCE_PRINTF(" TAS     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10397             cmd, ctl, cur_depth, max_depth, valid_cnt);
10398
10399         /* Input queue to the Completion Processor */
10400         cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
10401         ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
10402         cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
10403         max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
10404         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
10405         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10406             cmd, ctl, cur_depth, max_depth, valid_cnt);
10407
10408         /* Input queue to the Completion Processor */
10409         cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
10410         ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
10411         cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
10412         max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
10413         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
10414         BCE_PRINTF(" COMT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10415             cmd, ctl, cur_depth, max_depth, valid_cnt);
10416
10417         /* Input queue to the Completion Processor */
10418         cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
10419         ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
10420         cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
10421         max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
10422         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
10423         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10424             cmd, ctl, cur_depth, max_depth, valid_cnt);
10425
10426         /* Setup the generic statistic counters for the FTQ valid count. */
10427         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT  << 16) |
10428             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT  <<  8) |
10429             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT);
10430
10431         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
10432                 val = val |
10433                     (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI <<
10434                      24);
10435         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10436
10437         /* Input queue to the Management Control Processor */
10438         cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
10439         ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
10440         cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10441         max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10442         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10443         BCE_PRINTF(" MCP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10444             cmd, ctl, cur_depth, max_depth, valid_cnt);
10445
10446         /* Input queue to the Command Processor */
10447         cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
10448         ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
10449         cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10450         max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10451         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10452         BCE_PRINTF(" CP      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10453             cmd, ctl, cur_depth, max_depth, valid_cnt);
10454
10455         /* Input queue to the Completion Scheduler state machine */
10456         cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
10457         ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
10458         cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
10459         max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
10460         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10461         BCE_PRINTF(" CS      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10462             cmd, ctl, cur_depth, max_depth, valid_cnt);
10463
10464         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10465                 /* Input queue to the RV2P Command Scheduler */
10466                 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);
10467                 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);
10468                 cur_depth = (ctl & 0xFFC00000) >> 22;
10469                 max_depth = (ctl & 0x003FF000) >> 12;
10470                 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10471                 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10472                     cmd, ctl, cur_depth, max_depth, valid_cnt);
10473         }
10474
10475         BCE_PRINTF(
10476             "----------------------------"
10477             "----------------"
10478             "----------------------------\n");
10479 }
10480
10481
10482 /****************************************************************************/
10483 /* Prints out the TX chain.                                                 */
10484 /*                                                                          */
10485 /* Returns:                                                                 */
10486 /*   Nothing.                                                               */
10487 /****************************************************************************/
10488 static __attribute__ ((noinline)) void
10489 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
10490 {
10491         struct tx_bd *txbd;
10492
10493         /* First some info about the tx_bd chain structure. */
10494         BCE_PRINTF(
10495             "----------------------------"
10496             "  tx_bd  chain  "
10497             "----------------------------\n");
10498
10499         BCE_PRINTF("page size      = 0x%08X, tx chain pages        = 0x%08X\n",
10500             (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages);
10501         BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
10502             (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE);
10503         BCE_PRINTF("total tx_bd    = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC);
10504
10505         BCE_PRINTF(
10506             "----------------------------"
10507             "   tx_bd data   "
10508             "----------------------------\n");
10509
10510         /* Now print out a decoded list of TX buffer descriptors. */
10511         for (int i = 0; i < count; i++) {
10512                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
10513                 bce_dump_txbd(sc, tx_prod, txbd);
10514                 tx_prod++;
10515         }
10516
10517         BCE_PRINTF(
10518             "----------------------------"
10519             "----------------"
10520             "----------------------------\n");
10521 }
10522
10523
10524 /****************************************************************************/
10525 /* Prints out the RX chain.                                                 */
10526 /*                                                                          */
10527 /* Returns:                                                                 */
10528 /*   Nothing.                                                               */
10529 /****************************************************************************/
10530 static __attribute__ ((noinline)) void
10531 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count)
10532 {
10533         struct rx_bd *rxbd;
10534
10535         /* First some info about the rx_bd chain structure. */
10536         BCE_PRINTF(
10537             "----------------------------"
10538             "  rx_bd  chain  "
10539             "----------------------------\n");
10540
10541         BCE_PRINTF("page size      = 0x%08X, rx chain pages        = 0x%08X\n",
10542             (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages);
10543
10544         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10545             (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE);
10546
10547         BCE_PRINTF("total rx_bd    = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC);
10548
10549         BCE_PRINTF(
10550             "----------------------------"
10551             "   rx_bd data   "
10552             "----------------------------\n");
10553
10554         /* Now print out the rx_bd's themselves. */
10555         for (int i = 0; i < count; i++) {
10556                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
10557                 bce_dump_rxbd(sc, rx_prod, rxbd);
10558                 rx_prod = RX_CHAIN_IDX(rx_prod + 1);
10559         }
10560
10561         BCE_PRINTF(
10562             "----------------------------"
10563             "----------------"
10564             "----------------------------\n");
10565 }
10566
10567
10568 /****************************************************************************/
10569 /* Prints out the page chain.                                               */
10570 /*                                                                          */
10571 /* Returns:                                                                 */
10572 /*   Nothing.                                                               */
10573 /****************************************************************************/
10574 static __attribute__ ((noinline)) void
10575 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
10576 {
10577         struct rx_bd *pgbd;
10578
10579         /* First some info about the page chain structure. */
10580         BCE_PRINTF(
10581             "----------------------------"
10582             "   page chain   "
10583             "----------------------------\n");
10584
10585         BCE_PRINTF("page size      = 0x%08X, pg chain pages        = 0x%08X\n",
10586             (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages);
10587
10588         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10589             (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE);
10590
10591         BCE_PRINTF("total pg_bd             = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC);
10592
10593         BCE_PRINTF(
10594             "----------------------------"
10595             "   page data    "
10596             "----------------------------\n");
10597
10598         /* Now print out the rx_bd's themselves. */
10599         for (int i = 0; i < count; i++) {
10600                 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)];
10601                 bce_dump_pgbd(sc, pg_prod, pgbd);
10602                 pg_prod = PG_CHAIN_IDX(pg_prod + 1);
10603         }
10604
10605         BCE_PRINTF(
10606             "----------------------------"
10607             "----------------"
10608             "----------------------------\n");
10609 }
10610
10611
10612 #define BCE_PRINT_RX_CONS(arg)                                          \
10613 if (sblk->status_rx_quick_consumer_index##arg)                          \
10614         BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n",      \
10615             sblk->status_rx_quick_consumer_index##arg, (u16)            \
10616             RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg),    \
10617             arg);
10618
10619
10620 #define BCE_PRINT_TX_CONS(arg)                                          \
10621 if (sblk->status_tx_quick_consumer_index##arg)                          \
10622         BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n",      \
10623             sblk->status_tx_quick_consumer_index##arg, (u16)            \
10624             TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg),    \
10625             arg);
10626
10627 /****************************************************************************/
10628 /* Prints out the status block from host memory.                            */
10629 /*                                                                          */
10630 /* Returns:                                                                 */
10631 /*   Nothing.                                                               */
10632 /****************************************************************************/
10633 static __attribute__ ((noinline)) void
10634 bce_dump_status_block(struct bce_softc *sc)
10635 {
10636         struct status_block *sblk;
10637
10638         bus_dmamap_sync(sc->status_tag, sc->status_map, BUS_DMASYNC_POSTREAD);
10639
10640         sblk = sc->status_block;
10641
10642         BCE_PRINTF(
10643             "----------------------------"
10644             "  Status Block  "
10645             "----------------------------\n");
10646
10647         /* Theses indices are used for normal L2 drivers. */
10648         BCE_PRINTF("    0x%08X - attn_bits\n",
10649             sblk->status_attn_bits);
10650
10651         BCE_PRINTF("    0x%08X - attn_bits_ack\n",
10652             sblk->status_attn_bits_ack);
10653
10654         BCE_PRINT_RX_CONS(0);
10655         BCE_PRINT_TX_CONS(0)
10656
10657         BCE_PRINTF("        0x%04X - status_idx\n", sblk->status_idx);
10658
10659         /* Theses indices are not used for normal L2 drivers. */
10660         BCE_PRINT_RX_CONS(1);   BCE_PRINT_RX_CONS(2);   BCE_PRINT_RX_CONS(3);
10661         BCE_PRINT_RX_CONS(4);   BCE_PRINT_RX_CONS(5);   BCE_PRINT_RX_CONS(6);
10662         BCE_PRINT_RX_CONS(7);   BCE_PRINT_RX_CONS(8);   BCE_PRINT_RX_CONS(9);
10663         BCE_PRINT_RX_CONS(10);  BCE_PRINT_RX_CONS(11);  BCE_PRINT_RX_CONS(12);
10664         BCE_PRINT_RX_CONS(13);  BCE_PRINT_RX_CONS(14);  BCE_PRINT_RX_CONS(15);
10665
10666         BCE_PRINT_TX_CONS(1);   BCE_PRINT_TX_CONS(2);   BCE_PRINT_TX_CONS(3);
10667
10668         if (sblk->status_completion_producer_index ||
10669             sblk->status_cmd_consumer_index)
10670                 BCE_PRINTF("com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
10671                     sblk->status_completion_producer_index,
10672                     sblk->status_cmd_consumer_index);
10673
10674         BCE_PRINTF(
10675             "----------------------------"
10676             "----------------"
10677             "----------------------------\n");
10678 }
10679
10680
10681 #define BCE_PRINT_64BIT_STAT(arg)                               \
10682 if (sblk->arg##_lo || sblk->arg##_hi)                           \
10683         BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi,        \
10684             sblk->arg##_lo, #arg);
10685
10686 #define BCE_PRINT_32BIT_STAT(arg)                               \
10687 if (sblk->arg)                                                  \
10688         BCE_PRINTF("         0x%08X : %s\n",                    \
10689             sblk->arg, #arg);
10690
10691 /****************************************************************************/
10692 /* Prints out the statistics block from host memory.                        */
10693 /*                                                                          */
10694 /* Returns:                                                                 */
10695 /*   Nothing.                                                               */
10696 /****************************************************************************/
10697 static __attribute__ ((noinline)) void
10698 bce_dump_stats_block(struct bce_softc *sc)
10699 {
10700         struct statistics_block *sblk;
10701
10702         bus_dmamap_sync(sc->stats_tag, sc->stats_map, BUS_DMASYNC_POSTREAD);
10703
10704         sblk = sc->stats_block;
10705
10706         BCE_PRINTF(
10707             "---------------"
10708             " Stats Block  (All Stats Not Shown Are 0) "
10709             "---------------\n");
10710
10711         BCE_PRINT_64BIT_STAT(stat_IfHCInOctets);
10712         BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets);
10713         BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets);
10714         BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets);
10715         BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts);
10716         BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts);
10717         BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts);
10718         BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts);
10719         BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts);
10720         BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts);
10721         BCE_PRINT_32BIT_STAT(
10722             stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
10723         BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors);
10724         BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors);
10725         BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors);
10726         BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames);
10727         BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames);
10728         BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions);
10729         BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions);
10730         BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions);
10731         BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions);
10732         BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments);
10733         BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers);
10734         BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts);
10735         BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts);
10736         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets);
10737         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets);
10738         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets);
10739         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets);
10740         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets);
10741         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets);
10742         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets);
10743         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets);
10744         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets);
10745         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets);
10746         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets);
10747         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets);
10748         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets);
10749         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets);
10750         BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived);
10751         BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived);
10752         BCE_PRINT_32BIT_STAT(stat_OutXonSent);
10753         BCE_PRINT_32BIT_STAT(stat_OutXoffSent);
10754         BCE_PRINT_32BIT_STAT(stat_FlowControlDone);
10755         BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived);
10756         BCE_PRINT_32BIT_STAT(stat_XoffStateEntered);
10757         BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards);
10758         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards);
10759         BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards);
10760         BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards);
10761         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit);
10762         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards);
10763         BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards);
10764         BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards);
10765         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit);
10766
10767         BCE_PRINTF(
10768             "----------------------------"
10769             "----------------"
10770             "----------------------------\n");
10771 }
10772
10773
10774 /****************************************************************************/
10775 /* Prints out a summary of the driver state.                                */
10776 /*                                                                          */
10777 /* Returns:                                                                 */
10778 /*   Nothing.                                                               */
10779 /****************************************************************************/
10780 static __attribute__ ((noinline)) void
10781 bce_dump_driver_state(struct bce_softc *sc)
10782 {
10783         u32 val_hi, val_lo;
10784
10785         BCE_PRINTF(
10786             "-----------------------------"
10787             " Driver State "
10788             "-----------------------------\n");
10789
10790         val_hi = BCE_ADDR_HI(sc);
10791         val_lo = BCE_ADDR_LO(sc);
10792         BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual "
10793             "address\n", val_hi, val_lo);
10794
10795         val_hi = BCE_ADDR_HI(sc->bce_vhandle);
10796         val_lo = BCE_ADDR_LO(sc->bce_vhandle);
10797         BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual "
10798             "address\n", val_hi, val_lo);
10799
10800         val_hi = BCE_ADDR_HI(sc->status_block);
10801         val_lo = BCE_ADDR_LO(sc->status_block);
10802         BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block "
10803             "virtual address\n",        val_hi, val_lo);
10804
10805         val_hi = BCE_ADDR_HI(sc->stats_block);
10806         val_lo = BCE_ADDR_LO(sc->stats_block);
10807         BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block "
10808             "virtual address\n", val_hi, val_lo);
10809
10810         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
10811         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
10812         BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
10813             "virtual adddress\n", val_hi, val_lo);
10814
10815         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
10816         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
10817         BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
10818             "virtual address\n", val_hi, val_lo);
10819
10820         if (bce_hdr_split == TRUE) {
10821                 val_hi = BCE_ADDR_HI(sc->pg_bd_chain);
10822                 val_lo = BCE_ADDR_LO(sc->pg_bd_chain);
10823                 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain "
10824                     "virtual address\n", val_hi, val_lo);
10825         }
10826
10827         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
10828         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
10829         BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
10830             "virtual address\n",        val_hi, val_lo);
10831
10832         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
10833         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
10834         BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
10835             "virtual address\n", val_hi, val_lo);
10836
10837         if (bce_hdr_split == TRUE) {
10838                 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
10839                 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
10840                 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain "
10841                     "virtual address\n", val_hi, val_lo);
10842         }
10843
10844         BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) "
10845             "h/w intrs\n",
10846             (long long unsigned int) sc->interrupts_generated);
10847
10848         BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) "
10849             "rx interrupts handled\n",
10850             (long long unsigned int) sc->interrupts_rx);
10851
10852         BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) "
10853             "tx interrupts handled\n",
10854             (long long unsigned int) sc->interrupts_tx);
10855
10856         BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) "
10857             "phy interrupts handled\n",
10858             (long long unsigned int) sc->phy_interrupts);
10859
10860         BCE_PRINTF("         0x%08X - (sc->last_status_idx) "
10861             "status block index\n", sc->last_status_idx);
10862
10863         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_prod) tx producer "
10864             "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod));
10865
10866         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_cons) tx consumer "
10867             "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons));
10868
10869         BCE_PRINTF("         0x%08X - (sc->tx_prod_bseq) tx producer "
10870             "byte seq index\n", sc->tx_prod_bseq);
10871
10872         BCE_PRINTF("         0x%08X - (sc->debug_tx_mbuf_alloc) tx "
10873             "mbufs allocated\n", sc->debug_tx_mbuf_alloc);
10874
10875         BCE_PRINTF("         0x%08X - (sc->used_tx_bd) used "
10876             "tx_bd's\n", sc->used_tx_bd);
10877
10878         BCE_PRINTF("      0x%04X/0x%04X - (sc->tx_hi_watermark)/"
10879             "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd);
10880
10881         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_prod) rx producer "
10882             "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod));
10883
10884         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_cons) rx consumer "
10885             "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons));
10886
10887         BCE_PRINTF("         0x%08X - (sc->rx_prod_bseq) rx producer "
10888             "byte seq index\n", sc->rx_prod_bseq);
10889
10890         BCE_PRINTF("      0x%04X/0x%04X - (sc->rx_low_watermark)/"
10891                    "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd);
10892
10893         BCE_PRINTF("         0x%08X - (sc->debug_rx_mbuf_alloc) rx "
10894             "mbufs allocated\n", sc->debug_rx_mbuf_alloc);
10895
10896         BCE_PRINTF("         0x%08X - (sc->free_rx_bd) free "
10897             "rx_bd's\n", sc->free_rx_bd);
10898
10899         if (bce_hdr_split == TRUE) {
10900                 BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_prod) page producer "
10901                     "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod));
10902
10903                 BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_cons) page consumer "
10904                     "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons));
10905
10906                 BCE_PRINTF("         0x%08X - (sc->debug_pg_mbuf_alloc) page "
10907                     "mbufs allocated\n", sc->debug_pg_mbuf_alloc);
10908         }
10909
10910         BCE_PRINTF("         0x%08X - (sc->free_pg_bd) free page "
10911             "rx_bd's\n", sc->free_pg_bd);
10912
10913         BCE_PRINTF("      0x%04X/0x%04X - (sc->pg_low_watermark)/"
10914             "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd);
10915
10916         BCE_PRINTF("         0x%08X - (sc->mbuf_alloc_failed_count) "
10917             "mbuf alloc failures\n", sc->mbuf_alloc_failed_count);
10918
10919         BCE_PRINTF("         0x%08X - (sc->bce_flags) "
10920             "bce mac flags\n", sc->bce_flags);
10921
10922         BCE_PRINTF("         0x%08X - (sc->bce_phy_flags) "
10923             "bce phy flags\n", sc->bce_phy_flags);
10924
10925         BCE_PRINTF(
10926             "----------------------------"
10927             "----------------"
10928             "----------------------------\n");
10929 }
10930
10931
10932 /****************************************************************************/
10933 /* Prints out the hardware state through a summary of important register,   */
10934 /* followed by a complete register dump.                                    */
10935 /*                                                                          */
10936 /* Returns:                                                                 */
10937 /*   Nothing.                                                               */
10938 /****************************************************************************/
10939 static __attribute__ ((noinline)) void
10940 bce_dump_hw_state(struct bce_softc *sc)
10941 {
10942         u32 val;
10943
10944         BCE_PRINTF(
10945             "----------------------------"
10946             " Hardware State "
10947             "----------------------------\n");
10948
10949         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
10950
10951         val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
10952         BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
10953             val, BCE_MISC_ENABLE_STATUS_BITS);
10954
10955         val = REG_RD(sc, BCE_DMA_STATUS);
10956         BCE_PRINTF("0x%08X - (0x%06X) dma_status\n",
10957             val, BCE_DMA_STATUS);
10958
10959         val = REG_RD(sc, BCE_CTX_STATUS);
10960         BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n",
10961             val, BCE_CTX_STATUS);
10962
10963         val = REG_RD(sc, BCE_EMAC_STATUS);
10964         BCE_PRINTF("0x%08X - (0x%06X) emac_status\n",
10965             val, BCE_EMAC_STATUS);
10966
10967         val = REG_RD(sc, BCE_RPM_STATUS);
10968         BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n",
10969             val, BCE_RPM_STATUS);
10970
10971         /* ToDo: Create a #define for this constant. */
10972         val = REG_RD(sc, 0x2004);
10973         BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n",
10974             val, 0x2004);
10975
10976         val = REG_RD(sc, BCE_RV2P_STATUS);
10977         BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n",
10978             val, BCE_RV2P_STATUS);
10979
10980         /* ToDo: Create a #define for this constant. */
10981         val = REG_RD(sc, 0x2c04);
10982         BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n",
10983             val, 0x2c04);
10984
10985         val = REG_RD(sc, BCE_TBDR_STATUS);
10986         BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n",
10987             val, BCE_TBDR_STATUS);
10988
10989         val = REG_RD(sc, BCE_TDMA_STATUS);
10990         BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n",
10991             val, BCE_TDMA_STATUS);
10992
10993         val = REG_RD(sc, BCE_HC_STATUS);
10994         BCE_PRINTF("0x%08X - (0x%06X) hc_status\n",
10995             val, BCE_HC_STATUS);
10996
10997         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
10998         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
10999             val, BCE_TXP_CPU_STATE);
11000
11001         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11002         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11003             val, BCE_TPAT_CPU_STATE);
11004
11005         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11006         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11007             val, BCE_RXP_CPU_STATE);
11008
11009         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11010         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11011             val, BCE_COM_CPU_STATE);
11012
11013         val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
11014         BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n",
11015             val, BCE_MCP_CPU_STATE);
11016
11017         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11018         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11019             val, BCE_CP_CPU_STATE);
11020
11021         BCE_PRINTF(
11022             "----------------------------"
11023             "----------------"
11024             "----------------------------\n");
11025
11026         BCE_PRINTF(
11027             "----------------------------"
11028             " Register  Dump "
11029             "----------------------------\n");
11030
11031         for (int i = 0x400; i < 0x8000; i += 0x10) {
11032                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11033                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11034                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11035         }
11036
11037         BCE_PRINTF(
11038             "----------------------------"
11039             "----------------"
11040             "----------------------------\n");
11041 }
11042
11043
11044 /****************************************************************************/
11045 /* Prints out the contentst of shared memory which is used for host driver  */
11046 /* to bootcode firmware communication.                                      */
11047 /*                                                                          */
11048 /* Returns:                                                                 */
11049 /*   Nothing.                                                               */
11050 /****************************************************************************/
11051 static __attribute__ ((noinline)) void
11052 bce_dump_shmem_state(struct bce_softc *sc)
11053 {
11054         BCE_PRINTF(
11055             "----------------------------"
11056             " Hardware State "
11057             "----------------------------\n");
11058
11059         BCE_PRINTF("0x%08X - Shared memory base address\n",
11060             sc->bce_shmem_base);
11061         BCE_PRINTF("%s - bootcode version\n",
11062             sc->bce_bc_ver);
11063
11064         BCE_PRINTF(
11065             "----------------------------"
11066             "   Shared Mem   "
11067             "----------------------------\n");
11068
11069         for (int i = 0x0; i < 0x200; i += 0x10) {
11070                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11071                     i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4),
11072                     bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC));
11073         }
11074
11075         BCE_PRINTF(
11076             "----------------------------"
11077             "----------------"
11078             "----------------------------\n");
11079 }
11080
11081
11082 /****************************************************************************/
11083 /* Prints out the mailbox queue registers.                                  */
11084 /*                                                                          */
11085 /* Returns:                                                                 */
11086 /*   Nothing.                                                               */
11087 /****************************************************************************/
11088 static __attribute__ ((noinline)) void
11089 bce_dump_mq_regs(struct bce_softc *sc)
11090 {
11091         BCE_PRINTF(
11092             "----------------------------"
11093             "    MQ Regs     "
11094             "----------------------------\n");
11095
11096         BCE_PRINTF(
11097             "----------------------------"
11098             "----------------"
11099             "----------------------------\n");
11100
11101         for (int i = 0x3c00; i < 0x4000; i += 0x10) {
11102                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11103                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11104                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11105         }
11106
11107         BCE_PRINTF(
11108             "----------------------------"
11109             "----------------"
11110             "----------------------------\n");
11111 }
11112
11113
11114 /****************************************************************************/
11115 /* Prints out the bootcode state.                                           */
11116 /*                                                                          */
11117 /* Returns:                                                                 */
11118 /*   Nothing.                                                               */
11119 /****************************************************************************/
11120 static __attribute__ ((noinline)) void
11121 bce_dump_bc_state(struct bce_softc *sc)
11122 {
11123         u32 val;
11124
11125         BCE_PRINTF(
11126             "----------------------------"
11127             " Bootcode State "
11128             "----------------------------\n");
11129
11130         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
11131
11132         val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE);
11133         BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
11134             val, BCE_BC_RESET_TYPE);
11135
11136         val = bce_shmem_rd(sc, BCE_BC_STATE);
11137         BCE_PRINTF("0x%08X - (0x%06X) state\n",
11138             val, BCE_BC_STATE);
11139
11140         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
11141         BCE_PRINTF("0x%08X - (0x%06X) condition\n",
11142             val, BCE_BC_STATE_CONDITION);
11143
11144         val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD);
11145         BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
11146             val, BCE_BC_STATE_DEBUG_CMD);
11147
11148         BCE_PRINTF(
11149             "----------------------------"
11150             "----------------"
11151             "----------------------------\n");
11152 }
11153
11154
11155 /****************************************************************************/
11156 /* Prints out the TXP processor state.                                      */
11157 /*                                                                          */
11158 /* Returns:                                                                 */
11159 /*   Nothing.                                                               */
11160 /****************************************************************************/
11161 static __attribute__ ((noinline)) void
11162 bce_dump_txp_state(struct bce_softc *sc, int regs)
11163 {
11164         u32 val;
11165         u32 fw_version[3];
11166
11167         BCE_PRINTF(
11168             "----------------------------"
11169             "   TXP  State   "
11170             "----------------------------\n");
11171
11172         for (int i = 0; i < 3; i++)
11173                 fw_version[i] = htonl(REG_RD_IND(sc,
11174                     (BCE_TXP_SCRATCH + 0x10 + i * 4)));
11175         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11176
11177         val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
11178         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n",
11179             val, BCE_TXP_CPU_MODE);
11180
11181         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11182         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11183             val, BCE_TXP_CPU_STATE);
11184
11185         val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
11186         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n",
11187             val, BCE_TXP_CPU_EVENT_MASK);
11188
11189         if (regs) {
11190                 BCE_PRINTF(
11191                     "----------------------------"
11192                     " Register  Dump "
11193                     "----------------------------\n");
11194
11195                 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
11196                         /* Skip the big blank spaces */
11197                         if (i < 0x454000 && i > 0x5ffff)
11198                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11199                                     "0x%08X 0x%08X\n", i,
11200                                     REG_RD_IND(sc, i),
11201                                     REG_RD_IND(sc, i + 0x4),
11202                                     REG_RD_IND(sc, i + 0x8),
11203                                     REG_RD_IND(sc, i + 0xC));
11204                 }
11205         }
11206
11207         BCE_PRINTF(
11208             "----------------------------"
11209             "----------------"
11210             "----------------------------\n");
11211 }
11212
11213
11214 /****************************************************************************/
11215 /* Prints out the RXP processor state.                                      */
11216 /*                                                                          */
11217 /* Returns:                                                                 */
11218 /*   Nothing.                                                               */
11219 /****************************************************************************/
11220 static __attribute__ ((noinline)) void
11221 bce_dump_rxp_state(struct bce_softc *sc, int regs)
11222 {
11223         u32 val;
11224         u32 fw_version[3];
11225
11226         BCE_PRINTF(
11227             "----------------------------"
11228             "   RXP  State   "
11229             "----------------------------\n");
11230
11231         for (int i = 0; i < 3; i++)
11232                 fw_version[i] = htonl(REG_RD_IND(sc,
11233                     (BCE_RXP_SCRATCH + 0x10 + i * 4)));
11234
11235         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11236
11237         val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
11238         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n",
11239             val, BCE_RXP_CPU_MODE);
11240
11241         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11242         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11243             val, BCE_RXP_CPU_STATE);
11244
11245         val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
11246         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n",
11247             val, BCE_RXP_CPU_EVENT_MASK);
11248
11249         if (regs) {
11250                 BCE_PRINTF(
11251                     "----------------------------"
11252                     " Register  Dump "
11253                     "----------------------------\n");
11254
11255                 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
11256                         /* Skip the big blank sapces */
11257                         if (i < 0xc5400 && i > 0xdffff)
11258                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11259                                     "0x%08X 0x%08X\n", i,
11260                                     REG_RD_IND(sc, i),
11261                                     REG_RD_IND(sc, i + 0x4),
11262                                     REG_RD_IND(sc, i + 0x8),
11263                                     REG_RD_IND(sc, i + 0xC));
11264                 }
11265         }
11266
11267         BCE_PRINTF(
11268             "----------------------------"
11269             "----------------"
11270             "----------------------------\n");
11271 }
11272
11273
11274 /****************************************************************************/
11275 /* Prints out the TPAT processor state.                                     */
11276 /*                                                                          */
11277 /* Returns:                                                                 */
11278 /*   Nothing.                                                               */
11279 /****************************************************************************/
11280 static __attribute__ ((noinline)) void
11281 bce_dump_tpat_state(struct bce_softc *sc, int regs)
11282 {
11283         u32 val;
11284         u32 fw_version[3];
11285
11286         BCE_PRINTF(
11287             "----------------------------"
11288             "   TPAT State   "
11289             "----------------------------\n");
11290
11291         for (int i = 0; i < 3; i++)
11292                 fw_version[i] = htonl(REG_RD_IND(sc,
11293                     (BCE_TPAT_SCRATCH + 0x410 + i * 4)));
11294
11295         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11296
11297         val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
11298         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n",
11299             val, BCE_TPAT_CPU_MODE);
11300
11301         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11302         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11303             val, BCE_TPAT_CPU_STATE);
11304
11305         val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
11306         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n",
11307             val, BCE_TPAT_CPU_EVENT_MASK);
11308
11309         if (regs) {
11310                 BCE_PRINTF(
11311                     "----------------------------"
11312                     " Register  Dump "
11313                     "----------------------------\n");
11314
11315                 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
11316                         /* Skip the big blank spaces */
11317                         if (i < 0x854000 && i > 0x9ffff)
11318                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11319                                     "0x%08X 0x%08X\n", i,
11320                                     REG_RD_IND(sc, i),
11321                                     REG_RD_IND(sc, i + 0x4),
11322                                     REG_RD_IND(sc, i + 0x8),
11323                                     REG_RD_IND(sc, i + 0xC));
11324                 }
11325         }
11326
11327         BCE_PRINTF(
11328                 "----------------------------"
11329                 "----------------"
11330                 "----------------------------\n");
11331 }
11332
11333
11334 /****************************************************************************/
11335 /* Prints out the Command Procesor (CP) state.                              */
11336 /*                                                                          */
11337 /* Returns:                                                                 */
11338 /*   Nothing.                                                               */
11339 /****************************************************************************/
11340 static __attribute__ ((noinline)) void
11341 bce_dump_cp_state(struct bce_softc *sc, int regs)
11342 {
11343         u32 val;
11344         u32 fw_version[3];
11345
11346         BCE_PRINTF(
11347             "----------------------------"
11348             "    CP State    "
11349             "----------------------------\n");
11350
11351         for (int i = 0; i < 3; i++)
11352                 fw_version[i] = htonl(REG_RD_IND(sc,
11353                     (BCE_CP_SCRATCH + 0x10 + i * 4)));
11354
11355         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11356
11357         val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
11358         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n",
11359             val, BCE_CP_CPU_MODE);
11360
11361         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11362         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11363             val, BCE_CP_CPU_STATE);
11364
11365         val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
11366         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
11367             BCE_CP_CPU_EVENT_MASK);
11368
11369         if (regs) {
11370                 BCE_PRINTF(
11371                     "----------------------------"
11372                     " Register  Dump "
11373                     "----------------------------\n");
11374
11375                 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
11376                         /* Skip the big blank spaces */
11377                         if (i < 0x185400 && i > 0x19ffff)
11378                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11379                                     "0x%08X 0x%08X\n", i,
11380                                     REG_RD_IND(sc, i),
11381                                     REG_RD_IND(sc, i + 0x4),
11382                                     REG_RD_IND(sc, i + 0x8),
11383                                     REG_RD_IND(sc, i + 0xC));
11384                 }
11385         }
11386
11387         BCE_PRINTF(
11388             "----------------------------"
11389             "----------------"
11390             "----------------------------\n");
11391 }
11392
11393
11394 /****************************************************************************/
11395 /* Prints out the Completion Procesor (COM) state.                          */
11396 /*                                                                          */
11397 /* Returns:                                                                 */
11398 /*   Nothing.                                                               */
11399 /****************************************************************************/
11400 static __attribute__ ((noinline)) void
11401 bce_dump_com_state(struct bce_softc *sc, int regs)
11402 {
11403         u32 val;
11404         u32 fw_version[4];
11405
11406         BCE_PRINTF(
11407             "----------------------------"
11408             "   COM State    "
11409             "----------------------------\n");
11410
11411         for (int i = 0; i < 3; i++)
11412                 fw_version[i] = htonl(REG_RD_IND(sc,
11413                     (BCE_COM_SCRATCH + 0x10 + i * 4)));
11414
11415         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11416
11417         val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
11418         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n",
11419             val, BCE_COM_CPU_MODE);
11420
11421         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11422         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11423             val, BCE_COM_CPU_STATE);
11424
11425         val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
11426         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
11427             BCE_COM_CPU_EVENT_MASK);
11428
11429         if (regs) {
11430                 BCE_PRINTF(
11431                     "----------------------------"
11432                     " Register  Dump "
11433                     "----------------------------\n");
11434
11435                 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
11436                         BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11437                             "0x%08X 0x%08X\n", i,
11438                             REG_RD_IND(sc, i),
11439                             REG_RD_IND(sc, i + 0x4),
11440                             REG_RD_IND(sc, i + 0x8),
11441                             REG_RD_IND(sc, i + 0xC));
11442                 }
11443         }
11444
11445         BCE_PRINTF(
11446                 "----------------------------"
11447                 "----------------"
11448                 "----------------------------\n");
11449 }
11450
11451
11452 /****************************************************************************/
11453 /* Prints out the Receive Virtual 2 Physical (RV2P) state.                  */
11454 /*                                                                          */
11455 /* Returns:                                                                 */
11456 /*   Nothing.                                                               */
11457 /****************************************************************************/
11458 static __attribute__ ((noinline)) void
11459 bce_dump_rv2p_state(struct bce_softc *sc)
11460 {
11461         u32 val, pc1, pc2, fw_ver_high, fw_ver_low;
11462
11463         BCE_PRINTF(
11464             "----------------------------"
11465             "   RV2P State   "
11466             "----------------------------\n");
11467
11468         /* Stall the RV2P processors. */
11469         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11470         val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2;
11471         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11472
11473         /* Read the firmware version. */
11474         val = 0x00000001;
11475         REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
11476         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11477         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11478             BCE_RV2P_INSTR_HIGH_HIGH;
11479         BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n",
11480             fw_ver_high, fw_ver_low);
11481
11482         val = 0x00000001;
11483         REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
11484         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11485         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11486             BCE_RV2P_INSTR_HIGH_HIGH;
11487         BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n",
11488             fw_ver_high, fw_ver_low);
11489
11490         /* Resume the RV2P processors. */
11491         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11492         val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2);
11493         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11494
11495         /* Fetch the program counter value. */
11496         val = 0x68007800;
11497         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11498         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11499         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11500         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11501         BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1);
11502         BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2);
11503
11504         /* Fetch the program counter value again to see if it is advancing. */
11505         val = 0x68007800;
11506         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11507         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11508         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11509         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11510         BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1);
11511         BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2);
11512
11513         BCE_PRINTF(
11514             "----------------------------"
11515             "----------------"
11516             "----------------------------\n");
11517 }
11518
11519
11520 /****************************************************************************/
11521 /* Prints out the driver state and then enters the debugger.                */
11522 /*                                                                          */
11523 /* Returns:                                                                 */
11524 /*   Nothing.                                                               */
11525 /****************************************************************************/
11526 static __attribute__ ((noinline)) void
11527 bce_breakpoint(struct bce_softc *sc)
11528 {
11529
11530         /*
11531          * Unreachable code to silence compiler warnings
11532          * about unused functions.
11533          */
11534         if (0) {
11535                 bce_freeze_controller(sc);
11536                 bce_unfreeze_controller(sc);
11537                 bce_dump_enet(sc, NULL);
11538                 bce_dump_txbd(sc, 0, NULL);
11539                 bce_dump_rxbd(sc, 0, NULL);
11540                 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC);
11541                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
11542                 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC);
11543                 bce_dump_l2fhdr(sc, 0, NULL);
11544                 bce_dump_ctx(sc, RX_CID);
11545                 bce_dump_ftqs(sc);
11546                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC);
11547                 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC);
11548                 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC);
11549                 bce_dump_status_block(sc);
11550                 bce_dump_stats_block(sc);
11551                 bce_dump_driver_state(sc);
11552                 bce_dump_hw_state(sc);
11553                 bce_dump_bc_state(sc);
11554                 bce_dump_txp_state(sc, 0);
11555                 bce_dump_rxp_state(sc, 0);
11556                 bce_dump_tpat_state(sc, 0);
11557                 bce_dump_cp_state(sc, 0);
11558                 bce_dump_com_state(sc, 0);
11559                 bce_dump_rv2p_state(sc);
11560                 bce_dump_pgbd(sc, 0, NULL);
11561         }
11562
11563         bce_dump_status_block(sc);
11564         bce_dump_driver_state(sc);
11565
11566         /* Call the debugger. */
11567         breakpoint();
11568 }
11569 #endif