sys/dev/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2010 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 /*
  35  * The following controllers are supported by this driver:
  36  *   BCM5706C A2, A3
  37  *   BCM5706S A2, A3
  38  *   BCM5708C B1, B2
  39  *   BCM5708S B1, B2
  40  *   BCM5709C A1, C0
  41  *   BCM5709S A1, C0
  42  *   BCM5716C C0
  43  *   BCM5716S C0
  44  *
  45  * The following controllers are not supported by this driver:
  46  *   BCM5706C A0, A1 (pre-production)
  47  *   BCM5706S A0, A1 (pre-production)
  48  *   BCM5708C A0, B0 (pre-production)
  49  *   BCM5708S A0, B0 (pre-production)
  50  *   BCM5709C A0  B0, B1, B2 (pre-production)
  51  *   BCM5709S A0, B0, B1, B2 (pre-production)
  52  */
  53
  54 #include "opt_bce.h"
  55
  56 #include <dev/bce/if_bcereg.h>
  57 #include <dev/bce/if_bcefw.h>
  58
  59 /****************************************************************************/
  60 /* BCE Debug Options                                                        */
  61 /****************************************************************************/
  62 #ifdef BCE_DEBUG
  63         u32 bce_debug = BCE_WARN;
  64
  65         /*          0 = Never              */
  66         /*          1 = 1 in 2,147,483,648 */
  67         /*        256 = 1 in     8,388,608 */
  68         /*       2048 = 1 in     1,048,576 */
  69         /*      65536 = 1 in        32,768 */
  70         /*    1048576 = 1 in         2,048 */
  71         /*  268435456 = 1 in             8 */
  72         /*  536870912 = 1 in             4 */
  73         /* 1073741824 = 1 in             2 */
  74
  75         /* Controls how often the l2_fhdr frame error check will fail. */
  76         int l2fhdr_error_sim_control = 0;
  77
  78         /* Controls how often the unexpected attention check will fail. */
  79         int unexpected_attention_sim_control = 0;
  80
  81         /* Controls how often to simulate an mbuf allocation failure. */
  82         int mbuf_alloc_failed_sim_control = 0;
  83
  84         /* Controls how often to simulate a DMA mapping failure. */
  85         int dma_map_addr_failed_sim_control = 0;
  86
  87         /* Controls how often to simulate a bootcode failure. */
  88         int bootcode_running_failure_sim_control = 0;
  89 #endif
  90
  91 /****************************************************************************/
  92 /* PCI Device ID Table                                                      */
  93 /*                                                                          */
  94 /* Used by bce_probe() to identify the devices supported by this driver.    */
  95 /****************************************************************************/
  96 #define BCE_DEVDESC_MAX         64
  97
  98 static struct bce_type bce_devs[] = {
  99         /* BCM5706C Controllers and OEM boards. */
 100         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 101                 "HP NC370T Multifunction Gigabit Server Adapter" },
 102         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 103                 "HP NC370i Multifunction Gigabit Server Adapter" },
 104         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 105                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 106         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 107                 "HP NC371i Multifunction Gigabit Server Adapter" },
 108         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 109                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 110
 111         /* BCM5706S controllers and OEM boards. */
 112         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 113                 "HP NC370F Multifunction Gigabit Server Adapter" },
 114         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 115                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 116
 117         /* BCM5708C controllers and OEM boards. */
 118         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 119                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 120         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 121                 "HP NC373i Multifunction Gigabit Server Adapter" },
 122         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 123                 "HP NC374m PCIe Multifunction Adapter" },
 124         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 125                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 126
 127         /* BCM5708S controllers and OEM boards. */
 128         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 129                 "HP NC373m Multifunction Gigabit Server Adapter" },
 130         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 131                 "HP NC373i Multifunction Gigabit Server Adapter" },
 132         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 133                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 134         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 135                 "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 136
 137         /* BCM5709C controllers and OEM boards. */
 138         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 139                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 140         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 141                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 142         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 143                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 144
 145         /* BCM5709S controllers and OEM boards. */
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 147                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 149                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 150         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 151                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 152
 153         /* BCM5716 controllers and OEM boards. */
 154         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,  PCI_ANY_ID,  PCI_ANY_ID,
 155                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 156
 157         { 0, 0, 0, 0, NULL }
 158 };
 159
 160
 161 /****************************************************************************/
 162 /* Supported Flash NVRAM device data.                                       */
 163 /****************************************************************************/
 164 static struct flash_spec flash_table[] =
 165 {
 166 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 167 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 168
 169         /* Slow EEPROM */
 170         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 171          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 172          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 173          "EEPROM - slow"},
 174         /* Expansion entry 0001 */
 175         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 176          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 177          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 178          "Entry 0001"},
 179         /* Saifun SA25F010 (non-buffered flash) */
 180         /* strap, cfg1, & write1 need updates */
 181         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 182          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 183          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 184          "Non-buffered flash (128kB)"},
 185         /* Saifun SA25F020 (non-buffered flash) */
 186         /* strap, cfg1, & write1 need updates */
 187         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 189          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 190          "Non-buffered flash (256kB)"},
 191         /* Expansion entry 0100 */
 192         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 193          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 194          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 195          "Entry 0100"},
 196         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 197         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 198          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 199          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 200          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 201         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 202         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 203          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 204          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 205          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 206         /* Saifun SA25F005 (non-buffered flash) */
 207         /* strap, cfg1, & write1 need updates */
 208         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 209          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 210          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 211          "Non-buffered flash (64kB)"},
 212         /* Fast EEPROM */
 213         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 214          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 215          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 216          "EEPROM - fast"},
 217         /* Expansion entry 1001 */
 218         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 219          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 220          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 221          "Entry 1001"},
 222         /* Expansion entry 1010 */
 223         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 224          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 225          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 226          "Entry 1010"},
 227         /* ATMEL AT45DB011B (buffered flash) */
 228         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 229          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 230          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 231          "Buffered flash (128kB)"},
 232         /* Expansion entry 1100 */
 233         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 234          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 235          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 236          "Entry 1100"},
 237         /* Expansion entry 1101 */
 238         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 239          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 240          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 241          "Entry 1101"},
 242         /* Ateml Expansion entry 1110 */
 243         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 244          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 245          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 246          "Entry 1110 (Atmel)"},
 247         /* ATMEL AT45DB021B (buffered flash) */
 248         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 249          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 250          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 251          "Buffered flash (256kB)"},
 252 };
 253
 254 /*
 255  * The BCM5709 controllers transparently handle the
 256  * differences between Atmel 264 byte pages and all
 257  * flash devices which use 256 byte pages, so no
 258  * logical-to-physical mapping is required in the
 259  * driver.
 260  */
 261 static struct flash_spec flash_5709 = {
 262         .flags          = BCE_NV_BUFFERED,
 263         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 264         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 265         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 266         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 267         .name           = "5709/5716 buffered flash (256kB)",
 268 };
 269
 270
 271 /****************************************************************************/
 272 /* FreeBSD device entry points.                                             */
 273 /****************************************************************************/
 274 static int  bce_probe                   (device_t);
 275 static int  bce_attach                  (device_t);
 276 static int  bce_detach                  (device_t);
 277 static int  bce_shutdown                (device_t);
 278
 279
 280 /****************************************************************************/
 281 /* BCE Debug Data Structure Dump Routines                                   */
 282 /****************************************************************************/
 283 #ifdef BCE_DEBUG
 284 static u32  bce_reg_rd                          (struct bce_softc *, u32);
 285 static void bce_reg_wr                          (struct bce_softc *, u32, u32);
 286 static void bce_reg_wr16                        (struct bce_softc *, u32, u16);
 287 static u32  bce_ctx_rd                          (struct bce_softc *, u32, u32);
 288 static void bce_dump_enet                       (struct bce_softc *, struct mbuf *);
 289 static void bce_dump_mbuf                       (struct bce_softc *, struct mbuf *);
 290 static void bce_dump_tx_mbuf_chain      (struct bce_softc *, u16, int);
 291 static void bce_dump_rx_mbuf_chain      (struct bce_softc *, u16, int);
 292 static void bce_dump_pg_mbuf_chain      (struct bce_softc *, u16, int);
 293 static void bce_dump_txbd                       (struct bce_softc *,
 294     int, struct tx_bd *);
 295 static void bce_dump_rxbd                       (struct bce_softc *,
 296     int, struct rx_bd *);
 297 static void bce_dump_pgbd                       (struct bce_softc *,
 298     int, struct rx_bd *);
 299 static void bce_dump_l2fhdr             (struct bce_softc *,
 300     int, struct l2_fhdr *);
 301 static void bce_dump_ctx                        (struct bce_softc *, u16);
 302 static void bce_dump_ftqs                       (struct bce_softc *);
 303 static void bce_dump_tx_chain           (struct bce_softc *, u16, int);
 304 static void bce_dump_rx_bd_chain        (struct bce_softc *, u16, int);
 305 static void bce_dump_pg_chain           (struct bce_softc *, u16, int);
 306 static void bce_dump_status_block       (struct bce_softc *);
 307 static void bce_dump_stats_block        (struct bce_softc *);
 308 static void bce_dump_driver_state       (struct bce_softc *);
 309 static void bce_dump_hw_state           (struct bce_softc *);
 310 static void bce_dump_shmem_state        (struct bce_softc *);
 311 static void bce_dump_mq_regs            (struct bce_softc *);
 312 static void bce_dump_bc_state           (struct bce_softc *);
 313 static void bce_dump_txp_state          (struct bce_softc *, int);
 314 static void bce_dump_rxp_state          (struct bce_softc *, int);
 315 static void bce_dump_tpat_state (struct bce_softc *, int);
 316 static void bce_dump_cp_state           (struct bce_softc *, int);
 317 static void bce_dump_com_state          (struct bce_softc *, int);
 318 static void bce_dump_rv2p_state (struct bce_softc *);
 319 static void bce_breakpoint                      (struct bce_softc *);
 320 #endif /*BCE_DEBUG */
 321
 322
 323 /****************************************************************************/
 324 /* BCE Register/Memory Access Routines                                      */
 325 /****************************************************************************/
 326 static u32  bce_reg_rd_ind              (struct bce_softc *, u32);
 327 static void bce_reg_wr_ind              (struct bce_softc *, u32, u32);
 328 static void bce_shmem_wr                (struct bce_softc *, u32, u32);
 329 static u32  bce_shmem_rd                (struct bce_softc *, u32);
 330 static void bce_ctx_wr                  (struct bce_softc *, u32, u32, u32);
 331 static int  bce_miibus_read_reg         (device_t, int, int);
 332 static int  bce_miibus_write_reg        (device_t, int, int, int);
 333 static void bce_miibus_statchg          (device_t);
 334
 335 #ifdef BCE_DEBUG
 336 static int bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS);
 337 #ifdef BCE_NVRAM_WRITE_SUPPORT
 338 static int bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS);
 339 #endif
 340 #endif
 341
 342 /****************************************************************************/
 343 /* BCE NVRAM Access Routines                                                */
 344 /****************************************************************************/
 345 static int  bce_acquire_nvram_lock      (struct bce_softc *);
 346 static int  bce_release_nvram_lock      (struct bce_softc *);
 347 static void bce_enable_nvram_access(struct bce_softc *);
 348 static void bce_disable_nvram_access(struct bce_softc *);
 349 static int  bce_nvram_read_dword        (struct bce_softc *, u32, u8 *, u32);
 350 static int  bce_init_nvram                      (struct bce_softc *);
 351 static int  bce_nvram_read                      (struct bce_softc *, u32, u8 *, int);
 352 static int  bce_nvram_test                      (struct bce_softc *);
 353 #ifdef BCE_NVRAM_WRITE_SUPPORT
 354 static int  bce_enable_nvram_write      (struct bce_softc *);
 355 static void bce_disable_nvram_write(struct bce_softc *);
 356 static int  bce_nvram_erase_page        (struct bce_softc *, u32);
 357 static int  bce_nvram_write_dword       (struct bce_softc *, u32, u8 *, u32);
 358 static int  bce_nvram_write             (struct bce_softc *, u32, u8 *, int);
 359 #endif
 360
 361 /****************************************************************************/
 362 /*                                                                          */
 363 /****************************************************************************/
 364 static void bce_get_rx_buffer_sizes(struct bce_softc *, int);
 365 static void bce_get_media                       (struct bce_softc *);
 366 static void bce_init_media                      (struct bce_softc *);
 367 static u32 bce_get_rphy_link            (struct bce_softc *);
 368 static void bce_dma_map_addr            (void *, bus_dma_segment_t *, int, int);
 369 static int  bce_dma_alloc                       (device_t);
 370 static void bce_dma_free                        (struct bce_softc *);
 371 static void bce_release_resources       (struct bce_softc *);
 372
 373 /****************************************************************************/
 374 /* BCE Firmware Synchronization and Load                                    */
 375 /****************************************************************************/
 376 static void bce_fw_cap_init                     (struct bce_softc *);
 377 static int  bce_fw_sync                 (struct bce_softc *, u32);
 378 static void bce_load_rv2p_fw            (struct bce_softc *, u32 *, u32, u32);
 379 static void bce_load_cpu_fw             (struct bce_softc *,
 380     struct cpu_reg *, struct fw_info *);
 381 static void bce_start_cpu                       (struct bce_softc *, struct cpu_reg *);
 382 static void bce_halt_cpu                        (struct bce_softc *, struct cpu_reg *);
 383 static void bce_start_rxp_cpu           (struct bce_softc *);
 384 static void bce_init_rxp_cpu            (struct bce_softc *);
 385 static void bce_init_txp_cpu            (struct bce_softc *);
 386 static void bce_init_tpat_cpu           (struct bce_softc *);
 387 static void bce_init_cp_cpu             (struct bce_softc *);
 388 static void bce_init_com_cpu            (struct bce_softc *);
 389 static void bce_init_cpus                       (struct bce_softc *);
 390
 391 static void bce_print_adapter_info      (struct bce_softc *);
 392 static void bce_probe_pci_caps          (device_t, struct bce_softc *);
 393 static void bce_stop                            (struct bce_softc *);
 394 static int  bce_reset                           (struct bce_softc *, u32);
 395 static int  bce_chipinit                        (struct bce_softc *);
 396 static int  bce_blockinit                       (struct bce_softc *);
 397
 398 static int  bce_init_tx_chain           (struct bce_softc *);
 399 static void bce_free_tx_chain           (struct bce_softc *);
 400
 401 static int  bce_get_rx_buf                      (struct bce_softc *,
 402     struct mbuf *, u16 *, u16 *, u32 *);
 403 static int  bce_init_rx_chain           (struct bce_softc *);
 404 static void bce_fill_rx_chain           (struct bce_softc *);
 405 static void bce_free_rx_chain           (struct bce_softc *);
 406
 407 static int  bce_get_pg_buf                      (struct bce_softc *,
 408     struct mbuf *, u16 *, u16 *);
 409 static int  bce_init_pg_chain           (struct bce_softc *);
 410 static void bce_fill_pg_chain           (struct bce_softc *);
 411 static void bce_free_pg_chain           (struct bce_softc *);
 412
 413 static struct mbuf *bce_tso_setup       (struct bce_softc *,
 414     struct mbuf **, u16 *);
 415 static int  bce_tx_encap                        (struct bce_softc *, struct mbuf **);
 416 static void bce_start_locked            (struct ifnet *);
 417 static void bce_start                           (struct ifnet *);
 418 static int  bce_ioctl                           (struct ifnet *, u_long, caddr_t);
 419 static void bce_watchdog                        (struct bce_softc *);
 420 static int  bce_ifmedia_upd             (struct ifnet *);
 421 static int  bce_ifmedia_upd_locked      (struct ifnet *);
 422 static void bce_ifmedia_sts             (struct ifnet *, struct ifmediareq *);
 423 static void bce_ifmedia_sts_rphy        (struct bce_softc *, struct ifmediareq *);
 424 static void bce_init_locked             (struct bce_softc *);
 425 static void bce_init                            (void *);
 426 static void bce_mgmt_init_locked        (struct bce_softc *sc);
 427
 428 static int  bce_init_ctx                        (struct bce_softc *);
 429 static void bce_get_mac_addr            (struct bce_softc *);
 430 static void bce_set_mac_addr            (struct bce_softc *);
 431 static void bce_phy_intr                        (struct bce_softc *);
 432 static inline u16 bce_get_hw_rx_cons    (struct bce_softc *);
 433 static void bce_rx_intr                 (struct bce_softc *);
 434 static void bce_tx_intr                 (struct bce_softc *);
 435 static void bce_disable_intr            (struct bce_softc *);
 436 static void bce_enable_intr             (struct bce_softc *, int);
 437
 438 static void bce_intr                            (void *);
 439 static void bce_set_rx_mode             (struct bce_softc *);
 440 static void bce_stats_update            (struct bce_softc *);
 441 static void bce_tick                            (void *);
 442 static void bce_pulse                           (void *);
 443 static void bce_add_sysctls             (struct bce_softc *);
 444
 445
 446 /****************************************************************************/
 447 /* FreeBSD device dispatch table.                                           */
 448 /****************************************************************************/
 449 static device_method_t bce_methods[] = {
 450         /* Device interface (device_if.h) */
 451         DEVMETHOD(device_probe,         bce_probe),
 452         DEVMETHOD(device_attach,        bce_attach),
 453         DEVMETHOD(device_detach,        bce_detach),
 454         DEVMETHOD(device_shutdown,      bce_shutdown),
 455 /* Supported by device interface but not used here. */
 456 /*      DEVMETHOD(device_identify,      bce_identify),      */
 457 /*      DEVMETHOD(device_suspend,       bce_suspend),       */
 458 /*      DEVMETHOD(device_resume,        bce_resume),        */
 459 /*      DEVMETHOD(device_quiesce,       bce_quiesce),       */
 460
 461         /* MII interface (miibus_if.h) */
 462         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 463         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 464         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 465 /* Supported by MII interface but not used here.       */
 466 /*      DEVMETHOD(miibus_linkchg,       bce_miibus_linkchg),   */
 467 /*      DEVMETHOD(miibus_mediainit,     bce_miibus_mediainit), */
 468
 469         DEVMETHOD_END
 470 };
 471
 472 static driver_t bce_driver = {
 473         "bce",
 474         bce_methods,
 475         sizeof(struct bce_softc)
 476 };
 477
 478 static devclass_t bce_devclass;
 479
 480 MODULE_DEPEND(bce, pci, 1, 1, 1);
 481 MODULE_DEPEND(bce, ether, 1, 1, 1);
 482 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 483
 484 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0);
 485 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0);
 486
 487
 488 /****************************************************************************/
 489 /* Tunable device values                                                    */
 490 /****************************************************************************/
 491 SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters");
 492
 493 /* Allowable values are TRUE or FALSE */
 494 static int bce_verbose = TRUE;
 495 TUNABLE_INT("hw.bce.verbose", &bce_verbose);
 496 SYSCTL_INT(_hw_bce, OID_AUTO, verbose, CTLFLAG_RDTUN, &bce_verbose, 0,
 497     "Verbose output enable/disable");
 498
 499 /* Allowable values are TRUE or FALSE */
 500 static int bce_tso_enable = TRUE;
 501 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable);
 502 SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
 503     "TSO Enable/Disable");
 504
 505 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
 506 /* ToDo: Add MSI-X support. */
 507 static int bce_msi_enable = 1;
 508 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable);
 509 SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
 510     "MSI-X|MSI|INTx selector");
 511
 512 /* Allowable values are 1, 2, 4, 8. */
 513 static int bce_rx_pages = DEFAULT_RX_PAGES;
 514 TUNABLE_INT("hw.bce.rx_pages", &bce_rx_pages);
 515 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_pages, CTLFLAG_RDTUN, &bce_rx_pages, 0,
 516     "Receive buffer descriptor pages (1 page = 255 buffer descriptors)");
 517
 518 /* Allowable values are 1, 2, 4, 8. */
 519 static int bce_tx_pages = DEFAULT_TX_PAGES;
 520 TUNABLE_INT("hw.bce.tx_pages", &bce_tx_pages);
 521 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_pages, CTLFLAG_RDTUN, &bce_tx_pages, 0,
 522     "Transmit buffer descriptor pages (1 page = 255 buffer descriptors)");
 523
 524 /* Allowable values are TRUE or FALSE. */
 525 static int bce_hdr_split = TRUE;
 526 TUNABLE_INT("hw.bce.hdr_split", &bce_hdr_split);
 527 SYSCTL_UINT(_hw_bce, OID_AUTO, hdr_split, CTLFLAG_RDTUN, &bce_hdr_split, 0,
 528     "Frame header/payload splitting Enable/Disable");
 529
 530 /* Allowable values are TRUE or FALSE. */
 531 static int bce_strict_rx_mtu = FALSE;
 532 TUNABLE_INT("hw.bce.strict_rx_mtu", &bce_strict_rx_mtu);
 533 SYSCTL_UINT(_hw_bce, OID_AUTO, loose_rx_mtu, CTLFLAG_RDTUN,
 534     &bce_strict_rx_mtu, 0,
 535     "Enable/Disable strict RX frame size checking");
 536
 537 /* Allowable values are 0 ... 100 */
 538 #ifdef BCE_DEBUG
 539 /* Generate 1 interrupt for every transmit completion. */
 540 static int bce_tx_quick_cons_trip_int = 1;
 541 #else
 542 /* Generate 1 interrupt for every 20 transmit completions. */
 543 static int bce_tx_quick_cons_trip_int = DEFAULT_TX_QUICK_CONS_TRIP_INT;
 544 #endif
 545 TUNABLE_INT("hw.bce.tx_quick_cons_trip_int", &bce_tx_quick_cons_trip_int);
 546 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip_int, CTLFLAG_RDTUN,
 547     &bce_tx_quick_cons_trip_int, 0,
 548     "Transmit BD trip point during interrupts");
 549
 550 /* Allowable values are 0 ... 100 */
 551 /* Generate 1 interrupt for every transmit completion. */
 552 #ifdef BCE_DEBUG
 553 static int bce_tx_quick_cons_trip = 1;
 554 #else
 555 /* Generate 1 interrupt for every 20 transmit completions. */
 556 static int bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
 557 #endif
 558 TUNABLE_INT("hw.bce.tx_quick_cons_trip", &bce_tx_quick_cons_trip);
 559 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_quick_cons_trip, CTLFLAG_RDTUN,
 560     &bce_tx_quick_cons_trip, 0,
 561     "Transmit BD trip point");
 562
 563 /* Allowable values are 0 ... 100 */
 564 #ifdef BCE_DEBUG
 565 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
 566 static int bce_tx_ticks_int = 0;
 567 #else
 568 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
 569 static int bce_tx_ticks_int = DEFAULT_TX_TICKS_INT;
 570 #endif
 571 TUNABLE_INT("hw.bce.tx_ticks_int", &bce_tx_ticks_int);
 572 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks_int, CTLFLAG_RDTUN,
 573     &bce_tx_ticks_int, 0, "Transmit ticks count during interrupt");
 574
 575 /* Allowable values are 0 ... 100 */
 576 #ifdef BCE_DEBUG
 577 /* Generate an interrupt if 0us have elapsed since the last TX completion. */
 578 static int bce_tx_ticks = 0;
 579 #else
 580 /* Generate an interrupt if 80us have elapsed since the last TX completion. */
 581 static int bce_tx_ticks = DEFAULT_TX_TICKS;
 582 #endif
 583 TUNABLE_INT("hw.bce.tx_ticks", &bce_tx_ticks);
 584 SYSCTL_UINT(_hw_bce, OID_AUTO, tx_ticks, CTLFLAG_RDTUN,
 585     &bce_tx_ticks, 0, "Transmit ticks count");
 586
 587 /* Allowable values are 1 ... 100 */
 588 #ifdef BCE_DEBUG
 589 /* Generate 1 interrupt for every received frame. */
 590 static int bce_rx_quick_cons_trip_int = 1;
 591 #else
 592 /* Generate 1 interrupt for every 6 received frames. */
 593 static int bce_rx_quick_cons_trip_int = DEFAULT_RX_QUICK_CONS_TRIP_INT;
 594 #endif
 595 TUNABLE_INT("hw.bce.rx_quick_cons_trip_int", &bce_rx_quick_cons_trip_int);
 596 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip_int, CTLFLAG_RDTUN,
 597     &bce_rx_quick_cons_trip_int, 0,
 598     "Receive BD trip point duirng interrupts");
 599
 600 /* Allowable values are 1 ... 100 */
 601 #ifdef BCE_DEBUG
 602 /* Generate 1 interrupt for every received frame. */
 603 static int bce_rx_quick_cons_trip = 1;
 604 #else
 605 /* Generate 1 interrupt for every 6 received frames. */
 606 static int bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
 607 #endif
 608 TUNABLE_INT("hw.bce.rx_quick_cons_trip", &bce_rx_quick_cons_trip);
 609 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_quick_cons_trip, CTLFLAG_RDTUN,
 610     &bce_rx_quick_cons_trip, 0,
 611     "Receive BD trip point");
 612
 613 /* Allowable values are 0 ... 100 */
 614 #ifdef BCE_DEBUG
 615 /* Generate an int. if 0us have elapsed since the last received frame. */
 616 static int bce_rx_ticks_int = 0;
 617 #else
 618 /* Generate an int. if 18us have elapsed since the last received frame. */
 619 static int bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
 620 #endif
 621 TUNABLE_INT("hw.bce.rx_ticks_int", &bce_rx_ticks_int);
 622 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks_int, CTLFLAG_RDTUN,
 623     &bce_rx_ticks_int, 0, "Receive ticks count during interrupt");
 624
 625 /* Allowable values are 0 ... 100 */
 626 #ifdef BCE_DEBUG
 627 /* Generate an int. if 0us have elapsed since the last received frame. */
 628 static int bce_rx_ticks = 0;
 629 #else
 630 /* Generate an int. if 18us have elapsed since the last received frame. */
 631 static int bce_rx_ticks = DEFAULT_RX_TICKS;
 632 #endif
 633 TUNABLE_INT("hw.bce.rx_ticks", &bce_rx_ticks);
 634 SYSCTL_UINT(_hw_bce, OID_AUTO, rx_ticks, CTLFLAG_RDTUN,
 635     &bce_rx_ticks, 0, "Receive ticks count");
 636
 637
 638 /****************************************************************************/
 639 /* Device probe function.                                                   */
 640 /*                                                                          */
 641 /* Compares the device to the driver's list of supported devices and        */
 642 /* reports back to the OS whether this is the right driver for the device.  */
 643 /*                                                                          */
 644 /* Returns:                                                                 */
 645 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 646 /****************************************************************************/
 647 static int
 648 bce_probe(device_t dev)
 649 {
 650         struct bce_type *t;
 651         struct bce_softc *sc;
 652         char *descbuf;
 653         u16 vid = 0, did = 0, svid = 0, sdid = 0;
 654
 655         t = bce_devs;
 656
 657         sc = device_get_softc(dev);
 658         bzero(sc, sizeof(struct bce_softc));
 659         sc->bce_unit = device_get_unit(dev);
 660         sc->bce_dev = dev;
 661
 662         /* Get the data for the device to be probed. */
 663         vid  = pci_get_vendor(dev);
 664         did  = pci_get_device(dev);
 665         svid = pci_get_subvendor(dev);
 666         sdid = pci_get_subdevice(dev);
 667
 668         DBPRINT(sc, BCE_EXTREME_LOAD,
 669             "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
 670             "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
 671
 672         /* Look through the list of known devices for a match. */
 673         while(t->bce_name != NULL) {
 674
 675                 if ((vid == t->bce_vid) && (did == t->bce_did) &&
 676                     ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
 677                     ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
 678
 679                         descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
 680
 681                         if (descbuf == NULL)
 682                                 return(ENOMEM);
 683
 684                         /* Print out the device identity. */
 685                         snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 686                             t->bce_name, (((pci_read_config(dev,
 687                             PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
 688                             (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
 689
 690                         device_set_desc_copy(dev, descbuf);
 691                         free(descbuf, M_TEMP);
 692                         return(BUS_PROBE_DEFAULT);
 693                 }
 694                 t++;
 695         }
 696
 697         return(ENXIO);
 698 }
 699
 700
 701 /****************************************************************************/
 702 /* PCI Capabilities Probe Function.                                         */
 703 /*                                                                          */
 704 /* Walks the PCI capabiites list for the device to find what features are   */
 705 /* supported.                                                               */
 706 /*                                                                          */
 707 /* Returns:                                                                 */
 708 /*   None.                                                                  */
 709 /****************************************************************************/
 710 static void
 711 bce_print_adapter_info(struct bce_softc *sc)
 712 {
 713         int i = 0;
 714
 715         DBENTER(BCE_VERBOSE_LOAD);
 716
 717         if (bce_verbose || bootverbose) {
 718                 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
 719                 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >>
 720                     12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 721
 722
 723                 /* Bus info. */
 724                 if (sc->bce_flags & BCE_PCIE_FLAG) {
 725                         printf("Bus (PCIe x%d, ", sc->link_width);
 726                         switch (sc->link_speed) {
 727                         case 1: printf("2.5Gbps); "); break;
 728                         case 2: printf("5Gbps); "); break;
 729                         default: printf("Unknown link speed); ");
 730                         }
 731                 } else {
 732                         printf("Bus (PCI%s, %s, %dMHz); ",
 733                             ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 734                             ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
 735                             "32-bit" : "64-bit"), sc->bus_speed_mhz);
 736                 }
 737
 738                 /* Firmware version and device features. */
 739                 printf("B/C (%s); Bufs (RX:%d;TX:%d;PG:%d); Flags (",
 740                     sc->bce_bc_ver,     sc->rx_pages, sc->tx_pages,
 741                     (bce_hdr_split == TRUE ? sc->pg_pages: 0));
 742
 743                 if (bce_hdr_split == TRUE) {
 744                         printf("SPLT");
 745                         i++;
 746                 }
 747
 748                 if (sc->bce_flags & BCE_USING_MSI_FLAG) {
 749                         if (i > 0) printf("|");
 750                         printf("MSI"); i++;
 751                 }
 752
 753                 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
 754                         if (i > 0) printf("|");
 755                         printf("MSI-X"); i++;
 756                 }
 757
 758                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
 759                         if (i > 0) printf("|");
 760                         printf("2.5G"); i++;
 761                 }
 762
 763                 if (sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) {
 764                         if (i > 0) printf("|");
 765                         printf("Remote PHY(%s)",
 766                             sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG ?
 767                             "FIBER" : "TP"); i++;
 768                 }
 769
 770                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
 771                         if (i > 0) printf("|");
 772                         printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
 773                 } else {
 774                         printf(")\n");
 775                 }
 776
 777                 printf("Coal (RX:%d,%d,%d,%d; TX:%d,%d,%d,%d)\n",
 778                     sc->bce_rx_quick_cons_trip_int,
 779                     sc->bce_rx_quick_cons_trip,
 780                     sc->bce_rx_ticks_int,
 781                     sc->bce_rx_ticks,
 782                     sc->bce_tx_quick_cons_trip_int,
 783                     sc->bce_tx_quick_cons_trip,
 784                     sc->bce_tx_ticks_int,
 785                     sc->bce_tx_ticks);
 786
 787         }
 788
 789         DBEXIT(BCE_VERBOSE_LOAD);
 790 }
 791
 792
 793 /****************************************************************************/
 794 /* PCI Capabilities Probe Function.                                         */
 795 /*                                                                          */
 796 /* Walks the PCI capabiites list for the device to find what features are   */
 797 /* supported.                                                               */
 798 /*                                                                          */
 799 /* Returns:                                                                 */
 800 /*   None.                                                                  */
 801 /****************************************************************************/
 802 static void
 803 bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
 804 {
 805         u32 reg;
 806
 807         DBENTER(BCE_VERBOSE_LOAD);
 808
 809         /* Check if PCI-X capability is enabled. */
 810         if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0) {
 811                 if (reg != 0)
 812                         sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 813         }
 814
 815         /* Check if PCIe capability is enabled. */
 816         if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
 817                 if (reg != 0) {
 818                         u16 link_status = pci_read_config(dev, reg + 0x12, 2);
 819                         DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = "
 820                             "0x%08X\n", link_status);
 821                         sc->link_speed = link_status & 0xf;
 822                         sc->link_width = (link_status >> 4) & 0x3f;
 823                         sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 824                         sc->bce_flags |= BCE_PCIE_FLAG;
 825                 }
 826         }
 827
 828         /* Check if MSI capability is enabled. */
 829         if (pci_find_extcap(dev, PCIY_MSI, &reg) == 0) {
 830                 if (reg != 0)
 831                         sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
 832         }
 833
 834         /* Check if MSI-X capability is enabled. */
 835         if (pci_find_extcap(dev, PCIY_MSIX, &reg) == 0) {
 836                 if (reg != 0)
 837                         sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
 838         }
 839
 840         DBEXIT(BCE_VERBOSE_LOAD);
 841 }
 842
 843
 844 /****************************************************************************/
 845 /* Load and validate user tunable settings.                                 */
 846 /*                                                                          */
 847 /* Returns:                                                                 */
 848 /*   Nothing.                                                               */
 849 /****************************************************************************/
 850 static void
 851 bce_set_tunables(struct bce_softc *sc)
 852 {
 853         /* Set sysctl values for RX page count. */
 854         switch (bce_rx_pages) {
 855         case 1:
 856                 /* fall-through */
 857         case 2:
 858                 /* fall-through */
 859         case 4:
 860                 /* fall-through */
 861         case 8:
 862                 sc->rx_pages = bce_rx_pages;
 863                 break;
 864         default:
 865                 sc->rx_pages = DEFAULT_RX_PAGES;
 866                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 867                     "hw.bce.rx_pages!  Setting default of %d.\n",
 868                     __FILE__, __LINE__, bce_rx_pages, DEFAULT_RX_PAGES);
 869         }
 870
 871         /* ToDo: Consider allowing user setting for pg_pages. */
 872         sc->pg_pages = min((sc->rx_pages * 4), MAX_PG_PAGES);
 873
 874         /* Set sysctl values for TX page count. */
 875         switch (bce_tx_pages) {
 876         case 1:
 877                 /* fall-through */
 878         case 2:
 879                 /* fall-through */
 880         case 4:
 881                 /* fall-through */
 882         case 8:
 883                 sc->tx_pages = bce_tx_pages;
 884                 break;
 885         default:
 886                 sc->tx_pages = DEFAULT_TX_PAGES;
 887                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 888                     "hw.bce.tx_pages!  Setting default of %d.\n",
 889                     __FILE__, __LINE__, bce_tx_pages, DEFAULT_TX_PAGES);
 890         }
 891
 892         /*
 893          * Validate the TX trip point (i.e. the number of
 894          * TX completions before a status block update is
 895          * generated and an interrupt is asserted.
 896          */
 897         if (bce_tx_quick_cons_trip_int <= 100) {
 898                 sc->bce_tx_quick_cons_trip_int =
 899                     bce_tx_quick_cons_trip_int;
 900         } else {
 901                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 902                     "hw.bce.tx_quick_cons_trip_int!  Setting default of %d.\n",
 903                     __FILE__, __LINE__, bce_tx_quick_cons_trip_int,
 904                     DEFAULT_TX_QUICK_CONS_TRIP_INT);
 905                 sc->bce_tx_quick_cons_trip_int =
 906                     DEFAULT_TX_QUICK_CONS_TRIP_INT;
 907         }
 908
 909         if (bce_tx_quick_cons_trip <= 100) {
 910                 sc->bce_tx_quick_cons_trip =
 911                     bce_tx_quick_cons_trip;
 912         } else {
 913                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 914                     "hw.bce.tx_quick_cons_trip!  Setting default of %d.\n",
 915                     __FILE__, __LINE__, bce_tx_quick_cons_trip,
 916                     DEFAULT_TX_QUICK_CONS_TRIP);
 917                 sc->bce_tx_quick_cons_trip =
 918                     DEFAULT_TX_QUICK_CONS_TRIP;
 919         }
 920
 921         /*
 922          * Validate the TX ticks count (i.e. the maximum amount
 923          * of time to wait after the last TX completion has
 924          * occurred before a status block update is generated
 925          * and an interrupt is asserted.
 926          */
 927         if (bce_tx_ticks_int <= 100) {
 928                 sc->bce_tx_ticks_int =
 929                     bce_tx_ticks_int;
 930         } else {
 931                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 932                     "hw.bce.tx_ticks_int!  Setting default of %d.\n",
 933                     __FILE__, __LINE__, bce_tx_ticks_int,
 934                     DEFAULT_TX_TICKS_INT);
 935                 sc->bce_tx_ticks_int =
 936                     DEFAULT_TX_TICKS_INT;
 937            }
 938
 939         if (bce_tx_ticks <= 100) {
 940                 sc->bce_tx_ticks =
 941                     bce_tx_ticks;
 942         } else {
 943                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 944                     "hw.bce.tx_ticks!  Setting default of %d.\n",
 945                     __FILE__, __LINE__, bce_tx_ticks,
 946                     DEFAULT_TX_TICKS);
 947                 sc->bce_tx_ticks =
 948                     DEFAULT_TX_TICKS;
 949         }
 950
 951         /*
 952          * Validate the RX trip point (i.e. the number of
 953          * RX frames received before a status block update is
 954          * generated and an interrupt is asserted.
 955          */
 956         if (bce_rx_quick_cons_trip_int <= 100) {
 957                 sc->bce_rx_quick_cons_trip_int =
 958                     bce_rx_quick_cons_trip_int;
 959         } else {
 960                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 961                     "hw.bce.rx_quick_cons_trip_int!  Setting default of %d.\n",
 962                     __FILE__, __LINE__, bce_rx_quick_cons_trip_int,
 963                     DEFAULT_RX_QUICK_CONS_TRIP_INT);
 964                 sc->bce_rx_quick_cons_trip_int =
 965                     DEFAULT_RX_QUICK_CONS_TRIP_INT;
 966         }
 967
 968         if (bce_rx_quick_cons_trip <= 100) {
 969                 sc->bce_rx_quick_cons_trip =
 970                     bce_rx_quick_cons_trip;
 971         } else {
 972                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 973                     "hw.bce.rx_quick_cons_trip!  Setting default of %d.\n",
 974                     __FILE__, __LINE__, bce_rx_quick_cons_trip,
 975                     DEFAULT_RX_QUICK_CONS_TRIP);
 976                 sc->bce_rx_quick_cons_trip =
 977                     DEFAULT_RX_QUICK_CONS_TRIP;
 978         }
 979
 980         /*
 981          * Validate the RX ticks count (i.e. the maximum amount
 982          * of time to wait after the last RX frame has been
 983          * received before a status block update is generated
 984          * and an interrupt is asserted.
 985          */
 986         if (bce_rx_ticks_int <= 100) {
 987                 sc->bce_rx_ticks_int = bce_rx_ticks_int;
 988         } else {
 989                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
 990                     "hw.bce.rx_ticks_int!  Setting default of %d.\n",
 991                     __FILE__, __LINE__, bce_rx_ticks_int,
 992                     DEFAULT_RX_TICKS_INT);
 993                 sc->bce_rx_ticks_int = DEFAULT_RX_TICKS_INT;
 994         }
 995
 996         if (bce_rx_ticks <= 100) {
 997                 sc->bce_rx_ticks = bce_rx_ticks;
 998         } else {
 999                 BCE_PRINTF("%s(%d): Illegal value (%d) specified for "
1000                     "hw.bce.rx_ticks!  Setting default of %d.\n",
1001                     __FILE__, __LINE__, bce_rx_ticks,
1002                     DEFAULT_RX_TICKS);
1003                 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1004         }
1005
1006         /* Disabling both RX ticks and RX trips will prevent interrupts. */
1007         if ((bce_rx_quick_cons_trip == 0) && (bce_rx_ticks == 0)) {
1008                 BCE_PRINTF("%s(%d): Cannot set both hw.bce.rx_ticks and "
1009                     "hw.bce.rx_quick_cons_trip to 0. Setting default values.\n",
1010                    __FILE__, __LINE__);
1011                 sc->bce_rx_ticks = DEFAULT_RX_TICKS;
1012                 sc->bce_rx_quick_cons_trip = DEFAULT_RX_QUICK_CONS_TRIP;
1013         }
1014
1015         /* Disabling both TX ticks and TX trips will prevent interrupts. */
1016         if ((bce_tx_quick_cons_trip == 0) && (bce_tx_ticks == 0)) {
1017                 BCE_PRINTF("%s(%d): Cannot set both hw.bce.tx_ticks and "
1018                     "hw.bce.tx_quick_cons_trip to 0. Setting default values.\n",
1019                    __FILE__, __LINE__);
1020                 sc->bce_tx_ticks = DEFAULT_TX_TICKS;
1021                 sc->bce_tx_quick_cons_trip = DEFAULT_TX_QUICK_CONS_TRIP;
1022         }
1023
1024 }
1025
1026
1027 /****************************************************************************/
1028 /* Device attach function.                                                  */
1029 /*                                                                          */
1030 /* Allocates device resources, performs secondary chip identification,      */
1031 /* resets and initializes the hardware, and initializes driver instance     */
1032 /* variables.                                                               */
1033 /*                                                                          */
1034 /* Returns:                                                                 */
1035 /*   0 on success, positive value on failure.                               */
1036 /****************************************************************************/
1037 static int
1038 bce_attach(device_t dev)
1039 {
1040         struct bce_softc *sc;
1041         struct ifnet *ifp;
1042         u32 val;
1043         int error, rid, rc = 0;
1044
1045         sc = device_get_softc(dev);
1046         sc->bce_dev = dev;
1047
1048         DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1049
1050         sc->bce_unit = device_get_unit(dev);
1051
1052         /* Set initial device and PHY flags */
1053         sc->bce_flags = 0;
1054         sc->bce_phy_flags = 0;
1055
1056         bce_set_tunables(sc);
1057
1058         pci_enable_busmaster(dev);
1059
1060         /* Allocate PCI memory resources. */
1061         rid = PCIR_BAR(0);
1062         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1063                 &rid, RF_ACTIVE);
1064
1065         if (sc->bce_res_mem == NULL) {
1066                 BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
1067                     __FILE__, __LINE__);
1068                 rc = ENXIO;
1069                 goto bce_attach_fail;
1070         }
1071
1072         /* Get various resource handles. */
1073         sc->bce_btag    = rman_get_bustag(sc->bce_res_mem);
1074         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
1075         sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
1076
1077         bce_probe_pci_caps(dev, sc);
1078
1079         rid = 1;
1080 #if 0
1081         /* Try allocating MSI-X interrupts. */
1082         if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
1083                 (bce_msi_enable >= 2) &&
1084                 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
1085                 &rid, RF_ACTIVE)) != NULL)) {
1086
1087                 msi_needed = sc->bce_msi_count = 1;
1088
1089                 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) ||
1090                         (sc->bce_msi_count != msi_needed)) {
1091                         BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
1092                                 "Received = %d, error = %d\n", __FILE__, __LINE__,
1093                                 msi_needed, sc->bce_msi_count, error);
1094                         sc->bce_msi_count = 0;
1095                         pci_release_msi(dev);
1096                         bus_release_resource(dev, SYS_RES_MEMORY, rid,
1097                                 sc->bce_res_irq);
1098                         sc->bce_res_irq = NULL;
1099                 } else {
1100                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
1101                                 __FUNCTION__);
1102                         sc->bce_flags |= BCE_USING_MSIX_FLAG;
1103                         sc->bce_intr = bce_intr;
1104                 }
1105         }
1106 #endif
1107
1108         /* Try allocating a MSI interrupt. */
1109         if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
1110                 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) {
1111                 sc->bce_msi_count = 1;
1112                 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) {
1113                         BCE_PRINTF("%s(%d): MSI allocation failed! "
1114                             "error = %d\n", __FILE__, __LINE__, error);
1115                         sc->bce_msi_count = 0;
1116                         pci_release_msi(dev);
1117                 } else {
1118                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI "
1119                             "interrupt.\n", __FUNCTION__);
1120                         sc->bce_flags |= BCE_USING_MSI_FLAG;
1121                         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
1122                                 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
1123                         sc->bce_irq_rid = 1;
1124                         sc->bce_intr = bce_intr;
1125                 }
1126         }
1127
1128         /* Try allocating a legacy interrupt. */
1129         if (sc->bce_msi_count == 0) {
1130                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
1131                         __FUNCTION__);
1132                 rid = 0;
1133                 sc->bce_intr = bce_intr;
1134         }
1135
1136         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
1137             &rid, RF_SHAREABLE | RF_ACTIVE);
1138
1139         sc->bce_irq_rid = rid;
1140
1141         /* Report any IRQ allocation errors. */
1142         if (sc->bce_res_irq == NULL) {
1143                 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
1144                     __FILE__, __LINE__);
1145                 rc = ENXIO;
1146                 goto bce_attach_fail;
1147         }
1148
1149         /* Initialize mutex for the current device instance. */
1150         BCE_LOCK_INIT(sc, device_get_nameunit(dev));
1151
1152         /*
1153          * Configure byte swap and enable indirect register access.
1154          * Rely on CPU to do target byte swapping on big endian systems.
1155          * Access to registers outside of PCI configurtion space are not
1156          * valid until this is done.
1157          */
1158         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
1159             BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
1160             BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
1161
1162         /* Save ASIC revsion info. */
1163         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
1164
1165         /* Weed out any non-production controller revisions. */
1166         switch(BCE_CHIP_ID(sc)) {
1167         case BCE_CHIP_ID_5706_A0:
1168         case BCE_CHIP_ID_5706_A1:
1169         case BCE_CHIP_ID_5708_A0:
1170         case BCE_CHIP_ID_5708_B0:
1171         case BCE_CHIP_ID_5709_A0:
1172         case BCE_CHIP_ID_5709_B0:
1173         case BCE_CHIP_ID_5709_B1:
1174         case BCE_CHIP_ID_5709_B2:
1175                 BCE_PRINTF("%s(%d): Unsupported controller "
1176                     "revision (%c%d)!\n", __FILE__, __LINE__,
1177                     (((pci_read_config(dev, PCIR_REVID, 4) &
1178                     0xf0) >> 4) + 'A'), (pci_read_config(dev,
1179                     PCIR_REVID, 4) & 0xf));
1180                 rc = ENODEV;
1181                 goto bce_attach_fail;
1182         }
1183
1184         /*
1185          * The embedded PCIe to PCI-X bridge (EPB)
1186          * in the 5708 cannot address memory above
1187          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
1188          */
1189         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
1190                 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
1191         else
1192                 sc->max_bus_addr = BUS_SPACE_MAXADDR;
1193
1194         /*
1195          * Find the base address for shared memory access.
1196          * Newer versions of bootcode use a signature and offset
1197          * while older versions use a fixed address.
1198          */
1199         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
1200         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
1201                 /* Multi-port devices use different offsets in shared memory. */
1202                 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
1203                     (pci_get_function(sc->bce_dev) << 2));
1204         else
1205                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
1206
1207         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
1208             __FUNCTION__, sc->bce_shmem_base);
1209
1210         /* Fetch the bootcode revision. */
1211         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
1212         for (int i = 0, j = 0; i < 3; i++) {
1213                 u8 num;
1214
1215                 num = (u8) (val >> (24 - (i * 8)));
1216                 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
1217                         if (num >= k || !skip0 || k == 1) {
1218                                 sc->bce_bc_ver[j++] = (num / k) + '0';
1219                                 skip0 = 0;
1220                         }
1221                 }
1222
1223                 if (i != 2)
1224                         sc->bce_bc_ver[j++] = '.';
1225         }
1226
1227         /* Check if any management firwmare is enabled. */
1228         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
1229         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
1230                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
1231
1232                 /* Allow time for firmware to enter the running state. */
1233                 for (int i = 0; i < 30; i++) {
1234                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1235                         if (val & BCE_CONDITION_MFW_RUN_MASK)
1236                                 break;
1237                         DELAY(10000);
1238                 }
1239
1240                 /* Check if management firmware is running. */
1241                 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
1242                 val &= BCE_CONDITION_MFW_RUN_MASK;
1243                 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) &&
1244                     (val != BCE_CONDITION_MFW_RUN_NONE)) {
1245                         u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
1246                         int i = 0;
1247
1248                         /* Read the management firmware version string. */
1249                         for (int j = 0; j < 3; j++) {
1250                                 val = bce_reg_rd_ind(sc, addr + j * 4);
1251                                 val = bswap32(val);
1252                                 memcpy(&sc->bce_mfw_ver[i], &val, 4);
1253                                 i += 4;
1254                         }
1255                 } else {
1256                         /* May cause firmware synchronization timeouts. */
1257                         BCE_PRINTF("%s(%d): Management firmware enabled "
1258                             "but not running!\n", __FILE__, __LINE__);
1259                         strcpy(sc->bce_mfw_ver, "NOT RUNNING!");
1260
1261                         /* ToDo: Any action the driver should take? */
1262                 }
1263         }
1264
1265         /* Get PCI bus information (speed and type). */
1266         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
1267         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
1268                 u32 clkreg;
1269
1270                 sc->bce_flags |= BCE_PCIX_FLAG;
1271
1272                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);
1273
1274                 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
1275                 switch (clkreg) {
1276                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
1277                         sc->bus_speed_mhz = 133;
1278                         break;
1279
1280                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
1281                         sc->bus_speed_mhz = 100;
1282                         break;
1283
1284                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
1285                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
1286                         sc->bus_speed_mhz = 66;
1287                         break;
1288
1289                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
1290                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
1291                         sc->bus_speed_mhz = 50;
1292                         break;
1293
1294                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
1295                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
1296                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
1297                         sc->bus_speed_mhz = 33;
1298                         break;
1299                 }
1300         } else {
1301                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
1302                         sc->bus_speed_mhz = 66;
1303                 else
1304                         sc->bus_speed_mhz = 33;
1305         }
1306
1307         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
1308                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
1309
1310         /* Find the media type for the adapter. */
1311         bce_get_media(sc);
1312
1313         /* Reset controller and announce to bootcode that driver is present. */
1314         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
1315                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
1316                     __FILE__, __LINE__);
1317                 rc = ENXIO;
1318                 goto bce_attach_fail;
1319         }
1320
1321         /* Initialize the controller. */
1322         if (bce_chipinit(sc)) {
1323                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
1324                     __FILE__, __LINE__);
1325                 rc = ENXIO;
1326                 goto bce_attach_fail;
1327         }
1328
1329         /* Perform NVRAM test. */
1330         if (bce_nvram_test(sc)) {
1331                 BCE_PRINTF("%s(%d): NVRAM test failed!\n",
1332                     __FILE__, __LINE__);
1333                 rc = ENXIO;
1334                 goto bce_attach_fail;
1335         }
1336
1337         /* Fetch the permanent Ethernet MAC address. */
1338         bce_get_mac_addr(sc);
1339
1340         /*
1341          * Trip points control how many BDs
1342          * should be ready before generating an
1343          * interrupt while ticks control how long
1344          * a BD can sit in the chain before
1345          * generating an interrupt.  Set the default
1346          * values for the RX and TX chains.
1347          */
1348
1349         /* Not used for L2. */
1350         sc->bce_comp_prod_trip_int     = 0;
1351         sc->bce_comp_prod_trip         = 0;
1352         sc->bce_com_ticks_int          = 0;
1353         sc->bce_com_ticks              = 0;
1354         sc->bce_cmd_ticks_int          = 0;
1355         sc->bce_cmd_ticks              = 0;
1356
1357         /* Update statistics once every second. */
1358         sc->bce_stats_ticks = 1000000 & 0xffff00;
1359
1360         /* Store data needed by PHY driver for backplane applications */
1361         sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1362         sc->bce_port_hw_cfg   = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1363
1364         /* Allocate DMA memory resources. */
1365         if (bce_dma_alloc(dev)) {
1366                 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
1367                     __FILE__, __LINE__);
1368                 rc = ENXIO;
1369                 goto bce_attach_fail;
1370         }
1371
1372         /* Allocate an ifnet structure. */
1373         ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
1374         if (ifp == NULL) {
1375                 BCE_PRINTF("%s(%d): Interface allocation failed!\n",
1376                     __FILE__, __LINE__);
1377                 rc = ENXIO;
1378                 goto bce_attach_fail;
1379         }
1380
1381         /* Initialize the ifnet interface. */
1382         ifp->if_softc   = sc;
1383         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1384         ifp->if_flags   = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1385         ifp->if_ioctl   = bce_ioctl;
1386         ifp->if_start   = bce_start;
1387         ifp->if_init    = bce_init;
1388         ifp->if_mtu     = ETHERMTU;
1389
1390         if (bce_tso_enable) {
1391                 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO;
1392                 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 |
1393                     IFCAP_VLAN_HWTSO;
1394         } else {
1395                 ifp->if_hwassist = BCE_IF_HWASSIST;
1396                 ifp->if_capabilities = BCE_IF_CAPABILITIES;
1397         }
1398
1399 #if __FreeBSD_version >= 800505
1400         /*
1401          * Introducing IFCAP_LINKSTATE didn't bump __FreeBSD_version
1402          * so it's approximate value.
1403          */
1404         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1405                 ifp->if_capabilities |= IFCAP_LINKSTATE;
1406 #endif
1407
1408         ifp->if_capenable = ifp->if_capabilities;
1409
1410         /*
1411          * Assume standard mbuf sizes for buffer allocation.
1412          * This may change later if the MTU size is set to
1413          * something other than 1500.
1414          */
1415         bce_get_rx_buffer_sizes(sc,
1416             (ETHER_MAX_LEN - ETHER_HDR_LEN - ETHER_CRC_LEN));
1417
1418         /* Recalculate our buffer allocation sizes. */
1419         ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD_ALLOC;
1420         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1421         IFQ_SET_READY(&ifp->if_snd);
1422
1423         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1424                 ifp->if_baudrate = IF_Mbps(2500ULL);
1425         else
1426                 ifp->if_baudrate = IF_Mbps(1000);
1427
1428         /* Handle any special PHY initialization for SerDes PHYs. */
1429         bce_init_media(sc);
1430
1431         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
1432                 ifmedia_init(&sc->bce_ifmedia, IFM_IMASK, bce_ifmedia_upd,
1433                     bce_ifmedia_sts);
1434                 /*
1435                  * We can't manually override remote PHY's link and assume
1436                  * PHY port configuration(Fiber or TP) is not changed after
1437                  * device attach.  This may not be correct though.
1438                  */
1439                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0) {
1440                         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
1441                                 ifmedia_add(&sc->bce_ifmedia,
1442                                     IFM_ETHER | IFM_2500_SX, 0, NULL);
1443                                 ifmedia_add(&sc->bce_ifmedia,
1444                                     IFM_ETHER | IFM_2500_SX | IFM_FDX, 0, NULL);
1445                         }
1446                         ifmedia_add(&sc->bce_ifmedia,
1447                             IFM_ETHER | IFM_1000_SX, 0, NULL);
1448                         ifmedia_add(&sc->bce_ifmedia,
1449                             IFM_ETHER | IFM_1000_SX | IFM_FDX, 0, NULL);
1450                 } else {
1451                         ifmedia_add(&sc->bce_ifmedia,
1452                             IFM_ETHER | IFM_10_T, 0, NULL);
1453                         ifmedia_add(&sc->bce_ifmedia,
1454                             IFM_ETHER | IFM_10_T | IFM_FDX, 0, NULL);
1455                         ifmedia_add(&sc->bce_ifmedia,
1456                             IFM_ETHER | IFM_100_TX, 0, NULL);
1457                         ifmedia_add(&sc->bce_ifmedia,
1458                             IFM_ETHER | IFM_100_TX | IFM_FDX, 0, NULL);
1459                         ifmedia_add(&sc->bce_ifmedia,
1460                             IFM_ETHER | IFM_1000_T, 0, NULL);
1461                         ifmedia_add(&sc->bce_ifmedia,
1462                             IFM_ETHER | IFM_1000_T | IFM_FDX, 0, NULL);
1463                 }
1464                 ifmedia_add(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL);
1465                 ifmedia_set(&sc->bce_ifmedia, IFM_ETHER | IFM_AUTO);
1466                 sc->bce_ifmedia.ifm_media = sc->bce_ifmedia.ifm_cur->ifm_media;
1467         } else {
1468                 /* MII child bus by attaching the PHY. */
1469                 rc = mii_attach(dev, &sc->bce_miibus, ifp, bce_ifmedia_upd,
1470                     bce_ifmedia_sts, BMSR_DEFCAPMASK, sc->bce_phy_addr,
1471                     MII_OFFSET_ANY, MIIF_DOPAUSE | MIIF_FORCEPAUSE);
1472                 if (rc != 0) {
1473                         BCE_PRINTF("%s(%d): attaching PHYs failed\n", __FILE__,
1474                             __LINE__);
1475                         goto bce_attach_fail;
1476                 }
1477         }
1478
1479         /* Attach to the Ethernet interface list. */
1480         ether_ifattach(ifp, sc->eaddr);
1481
1482 #if __FreeBSD_version < 500000
1483         callout_init(&sc->bce_tick_callout);
1484         callout_init(&sc->bce_pulse_callout);
1485 #else
1486         callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1487         callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1488 #endif
1489
1490         /* Hookup IRQ last. */
1491         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1492                 NULL, bce_intr, sc, &sc->bce_intrhand);
1493
1494         if (rc) {
1495                 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
1496                     __FILE__, __LINE__);
1497                 bce_detach(dev);
1498                 goto bce_attach_exit;
1499         }
1500
1501         /*
1502          * At this point we've acquired all the resources
1503          * we need to run so there's no turning back, we're
1504          * cleared for launch.
1505          */
1506
1507         /* Print some important debugging info. */
1508         DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
1509
1510         /* Add the supported sysctls to the kernel. */
1511         bce_add_sysctls(sc);
1512
1513         BCE_LOCK(sc);
1514
1515         /*
1516          * The chip reset earlier notified the bootcode that
1517          * a driver is present.  We now need to start our pulse
1518          * routine so that the bootcode is reminded that we're
1519          * still running.
1520          */
1521         bce_pulse(sc);
1522
1523         bce_mgmt_init_locked(sc);
1524         BCE_UNLOCK(sc);
1525
1526         /* Finally, print some useful adapter info */
1527         bce_print_adapter_info(sc);
1528         DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
1529                 __FUNCTION__, sc);
1530
1531         goto bce_attach_exit;
1532
1533 bce_attach_fail:
1534         bce_release_resources(sc);
1535
1536 bce_attach_exit:
1537
1538         DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1539
1540         return(rc);
1541 }
1542
1543
1544 /****************************************************************************/
1545 /* Device detach function.                                                  */
1546 /*                                                                          */
1547 /* Stops the controller, resets the controller, and releases resources.     */
1548 /*                                                                          */
1549 /* Returns:                                                                 */
1550 /*   0 on success, positive value on failure.                               */
1551 /****************************************************************************/
1552 static int
1553 bce_detach(device_t dev)
1554 {
1555         struct bce_softc *sc = device_get_softc(dev);
1556         struct ifnet *ifp;
1557         u32 msg;
1558
1559         DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1560
1561         ifp = sc->bce_ifp;
1562
1563         /* Stop and reset the controller. */
1564         BCE_LOCK(sc);
1565
1566         /* Stop the pulse so the bootcode can go to driver absent state. */
1567         callout_stop(&sc->bce_pulse_callout);
1568
1569         bce_stop(sc);
1570         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1571                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1572         else
1573                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1574         bce_reset(sc, msg);
1575
1576         BCE_UNLOCK(sc);
1577
1578         ether_ifdetach(ifp);
1579
1580         /* If we have a child device on the MII bus remove it too. */
1581         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
1582                 ifmedia_removeall(&sc->bce_ifmedia);
1583         else {
1584                 bus_generic_detach(dev);
1585                 device_delete_child(dev, sc->bce_miibus);
1586         }
1587
1588         /* Release all remaining resources. */
1589         bce_release_resources(sc);
1590
1591         DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1592
1593         return(0);
1594 }
1595
1596
1597 /****************************************************************************/
1598 /* Device shutdown function.                                                */
1599 /*                                                                          */
1600 /* Stops and resets the controller.                                         */
1601 /*                                                                          */
1602 /* Returns:                                                                 */
1603 /*   0 on success, positive value on failure.                               */
1604 /****************************************************************************/
1605 static int
1606 bce_shutdown(device_t dev)
1607 {
1608         struct bce_softc *sc = device_get_softc(dev);
1609         u32 msg;
1610
1611         DBENTER(BCE_VERBOSE);
1612
1613         BCE_LOCK(sc);
1614         bce_stop(sc);
1615         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1616                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1617         else
1618                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1619         bce_reset(sc, msg);
1620         BCE_UNLOCK(sc);
1621
1622         DBEXIT(BCE_VERBOSE);
1623
1624         return (0);
1625 }
1626
1627
1628 #ifdef BCE_DEBUG
1629 /****************************************************************************/
1630 /* Register read.                                                           */
1631 /*                                                                          */
1632 /* Returns:                                                                 */
1633 /*   The value of the register.                                             */
1634 /****************************************************************************/
1635 static u32
1636 bce_reg_rd(struct bce_softc *sc, u32 offset)
1637 {
1638         u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset);
1639         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1640                 __FUNCTION__, offset, val);
1641         return val;
1642 }
1643
1644
1645 /****************************************************************************/
1646 /* Register write (16 bit).                                                 */
1647 /*                                                                          */
1648 /* Returns:                                                                 */
1649 /*   Nothing.                                                               */
1650 /****************************************************************************/
1651 static void
1652 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1653 {
1654         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1655                 __FUNCTION__, offset, val);
1656         bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val);
1657 }
1658
1659
1660 /****************************************************************************/
1661 /* Register write.                                                          */
1662 /*                                                                          */
1663 /* Returns:                                                                 */
1664 /*   Nothing.                                                               */
1665 /****************************************************************************/
1666 static void
1667 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1668 {
1669         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1670                 __FUNCTION__, offset, val);
1671         bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val);
1672 }
1673 #endif
1674
1675 /****************************************************************************/
1676 /* Indirect register read.                                                  */
1677 /*                                                                          */
1678 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1679 /* configuration space.  Using this mechanism avoids issues with posted     */
1680 /* reads but is much slower than memory-mapped I/O.                         */
1681 /*                                                                          */
1682 /* Returns:                                                                 */
1683 /*   The value of the register.                                             */
1684 /****************************************************************************/
1685 static u32
1686 bce_reg_rd_ind(struct bce_softc *sc, u32 offset)
1687 {
1688         device_t dev;
1689         dev = sc->bce_dev;
1690
1691         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1692 #ifdef BCE_DEBUG
1693         {
1694                 u32 val;
1695                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1696                 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1697                         __FUNCTION__, offset, val);
1698                 return val;
1699         }
1700 #else
1701         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1702 #endif
1703 }
1704
1705
1706 /****************************************************************************/
1707 /* Indirect register write.                                                 */
1708 /*                                                                          */
1709 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1710 /* configuration space.  Using this mechanism avoids issues with posted     */
1711 /* writes but is muchh slower than memory-mapped I/O.                       */
1712 /*                                                                          */
1713 /* Returns:                                                                 */
1714 /*   Nothing.                                                               */
1715 /****************************************************************************/
1716 static void
1717 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1718 {
1719         device_t dev;
1720         dev = sc->bce_dev;
1721
1722         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1723                 __FUNCTION__, offset, val);
1724
1725         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1726         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1727 }
1728
1729
1730 /****************************************************************************/
1731 /* Shared memory write.                                                     */
1732 /*                                                                          */
1733 /* Writes NetXtreme II shared memory region.                                */
1734 /*                                                                          */
1735 /* Returns:                                                                 */
1736 /*   Nothing.                                                               */
1737 /****************************************************************************/
1738 static void
1739 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val)
1740 {
1741         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X  to  "
1742             "0x%08X\n", __FUNCTION__, val, offset);
1743
1744         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1745 }
1746
1747
1748 /****************************************************************************/
1749 /* Shared memory read.                                                      */
1750 /*                                                                          */
1751 /* Reads NetXtreme II shared memory region.                                 */
1752 /*                                                                          */
1753 /* Returns:                                                                 */
1754 /*   The 32 bit value read.                                                 */
1755 /****************************************************************************/
1756 static u32
1757 bce_shmem_rd(struct bce_softc *sc, u32 offset)
1758 {
1759         u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1760
1761         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from "
1762             "0x%08X\n", __FUNCTION__, val, offset);
1763
1764         return val;
1765 }
1766
1767
1768 #ifdef BCE_DEBUG
1769 /****************************************************************************/
1770 /* Context memory read.                                                     */
1771 /*                                                                          */
1772 /* The NetXtreme II controller uses context memory to track connection      */
1773 /* information for L2 and higher network protocols.                         */
1774 /*                                                                          */
1775 /* Returns:                                                                 */
1776 /*   The requested 32 bit value of context memory.                          */
1777 /****************************************************************************/
1778 static u32
1779 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset)
1780 {
1781         u32 idx, offset, retry_cnt = 5, val;
1782
1783         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 ||
1784             cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID "
1785             "address: 0x%08X.\n", __FUNCTION__, cid_addr));
1786
1787         offset = ctx_offset + cid_addr;
1788
1789         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1790
1791                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1792
1793                 for (idx = 0; idx < retry_cnt; idx++) {
1794                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1795                         if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1796                                 break;
1797                         DELAY(5);
1798                 }
1799
1800                 if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1801                         BCE_PRINTF("%s(%d); Unable to read CTX memory: "
1802                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1803                             __FILE__, __LINE__, cid_addr, ctx_offset);
1804
1805                 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1806         } else {
1807                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1808                 val = REG_RD(sc, BCE_CTX_DATA);
1809         }
1810
1811         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1812                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1813
1814         return(val);
1815 }
1816 #endif
1817
1818
1819 /****************************************************************************/
1820 /* Context memory write.                                                    */
1821 /*                                                                          */
1822 /* The NetXtreme II controller uses context memory to track connection      */
1823 /* information for L2 and higher network protocols.                         */
1824 /*                                                                          */
1825 /* Returns:                                                                 */
1826 /*   Nothing.                                                               */
1827 /****************************************************************************/
1828 static void
1829 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val)
1830 {
1831         u32 idx, offset = ctx_offset + cid_addr;
1832         u32 val, retry_cnt = 5;
1833
1834         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1835                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1836
1837         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1838                 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1839                     __FUNCTION__, cid_addr));
1840
1841         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
1842
1843                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1844                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1845
1846                 for (idx = 0; idx < retry_cnt; idx++) {
1847                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1848                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1849                                 break;
1850                         DELAY(5);
1851                 }
1852
1853                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1854                         BCE_PRINTF("%s(%d); Unable to write CTX memory: "
1855                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1856                             __FILE__, __LINE__, cid_addr, ctx_offset);
1857
1858         } else {
1859                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1860                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1861         }
1862 }
1863
1864
1865 /****************************************************************************/
1866 /* PHY register read.                                                       */
1867 /*                                                                          */
1868 /* Implements register reads on the MII bus.                                */
1869 /*                                                                          */
1870 /* Returns:                                                                 */
1871 /*   The value of the register.                                             */
1872 /****************************************************************************/
1873 static int
1874 bce_miibus_read_reg(device_t dev, int phy, int reg)
1875 {
1876         struct bce_softc *sc;
1877         u32 val;
1878         int i;
1879
1880         sc = device_get_softc(dev);
1881
1882         /* Make sure we are accessing the correct PHY address. */
1883         if (phy != sc->bce_phy_addr) {
1884                 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d "
1885                     "for PHY read!\n", phy);
1886                 return(0);
1887         }
1888
1889     /*
1890      * The 5709S PHY is an IEEE Clause 45 PHY
1891      * with special mappings to work with IEEE
1892      * Clause 22 register accesses.
1893      */
1894         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1895                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1896                         reg += 0x10;
1897         }
1898
1899     if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1900                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1901                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1902
1903                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1904                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1905
1906                 DELAY(40);
1907         }
1908
1909
1910         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1911             BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1912             BCE_EMAC_MDIO_COMM_START_BUSY;
1913         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1914
1915         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1916                 DELAY(10);
1917
1918                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1919                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1920                         DELAY(5);
1921
1922                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1923                         val &= BCE_EMAC_MDIO_COMM_DATA;
1924
1925                         break;
1926                 }
1927         }
1928
1929         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1930                 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, "
1931                     "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
1932                 val = 0x0;
1933         } else {
1934                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1935         }
1936
1937
1938         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1939                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1940                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1941
1942                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1943                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1944
1945                 DELAY(40);
1946         }
1947
1948         DB_PRINT_PHY_REG(reg, val);
1949         return (val & 0xffff);
1950
1951 }
1952
1953
1954 /****************************************************************************/
1955 /* PHY register write.                                                      */
1956 /*                                                                          */
1957 /* Implements register writes on the MII bus.                               */
1958 /*                                                                          */
1959 /* Returns:                                                                 */
1960 /*   The value of the register.                                             */
1961 /****************************************************************************/
1962 static int
1963 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1964 {
1965         struct bce_softc *sc;
1966         u32 val1;
1967         int i;
1968
1969         sc = device_get_softc(dev);
1970
1971         /* Make sure we are accessing the correct PHY address. */
1972         if (phy != sc->bce_phy_addr) {
1973                 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d "
1974                     "for PHY write!\n", phy);
1975                 return(0);
1976         }
1977
1978         DB_PRINT_PHY_REG(reg, val);
1979
1980         /*
1981          * The 5709S PHY is an IEEE Clause 45 PHY
1982          * with special mappings to work with IEEE
1983          * Clause 22 register accesses.
1984          */
1985         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1986                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1987                         reg += 0x10;
1988         }
1989
1990         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1991                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1992                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1993
1994                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1995                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1996
1997                 DELAY(40);
1998         }
1999
2000         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
2001             BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
2002             BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
2003         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
2004
2005         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
2006                 DELAY(10);
2007
2008                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
2009                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
2010                         DELAY(5);
2011                         break;
2012                 }
2013         }
2014
2015         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
2016                 BCE_PRINTF("%s(%d): PHY write timeout!\n",
2017                     __FILE__, __LINE__);
2018
2019         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
2020                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
2021                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
2022
2023                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
2024                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
2025
2026                 DELAY(40);
2027         }
2028
2029         return 0;
2030 }
2031
2032
2033 /****************************************************************************/
2034 /* MII bus status change.                                                   */
2035 /*                                                                          */
2036 /* Called by the MII bus driver when the PHY establishes link to set the    */
2037 /* MAC interface registers.                                                 */
2038 /*                                                                          */
2039 /* Returns:                                                                 */
2040 /*   Nothing.                                                               */
2041 /****************************************************************************/
2042 static void
2043 bce_miibus_statchg(device_t dev)
2044 {
2045         struct bce_softc *sc;
2046         struct mii_data *mii;
2047         struct ifmediareq ifmr;
2048         int media_active, media_status, val;
2049
2050         sc = device_get_softc(dev);
2051
2052         DBENTER(BCE_VERBOSE_PHY);
2053
2054         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
2055                 bzero(&ifmr, sizeof(ifmr));
2056                 bce_ifmedia_sts_rphy(sc, &ifmr);
2057                 media_active = ifmr.ifm_active;
2058                 media_status = ifmr.ifm_status;
2059         } else {
2060                 mii = device_get_softc(sc->bce_miibus);
2061                 media_active = mii->mii_media_active;
2062                 media_status = mii->mii_media_status;
2063         }
2064
2065         /* Ignore invalid media status. */
2066         if ((media_status & (IFM_ACTIVE | IFM_AVALID)) !=
2067             (IFM_ACTIVE | IFM_AVALID))
2068                 goto bce_miibus_statchg_exit;
2069
2070         val = REG_RD(sc, BCE_EMAC_MODE);
2071         val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
2072             BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
2073             BCE_EMAC_MODE_25G);
2074
2075         /* Set MII or GMII interface based on the PHY speed. */
2076         switch (IFM_SUBTYPE(media_active)) {
2077         case IFM_10_T:
2078                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2079                         DBPRINT(sc, BCE_INFO_PHY,
2080                             "Enabling 10Mb interface.\n");
2081                         val |= BCE_EMAC_MODE_PORT_MII_10;
2082                         break;
2083                 }
2084                 /* fall-through */
2085         case IFM_100_TX:
2086                 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
2087                 val |= BCE_EMAC_MODE_PORT_MII;
2088                 break;
2089         case IFM_2500_SX:
2090                 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
2091                 val |= BCE_EMAC_MODE_25G;
2092                 /* fall-through */
2093         case IFM_1000_T:
2094         case IFM_1000_SX:
2095                 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
2096                 val |= BCE_EMAC_MODE_PORT_GMII;
2097                 break;
2098         default:
2099                 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
2100                     "default GMII interface.\n");
2101                 val |= BCE_EMAC_MODE_PORT_GMII;
2102         }
2103
2104         /* Set half or full duplex based on PHY settings. */
2105         if ((IFM_OPTIONS(media_active) & IFM_FDX) == 0) {
2106                 DBPRINT(sc, BCE_INFO_PHY,
2107                     "Setting Half-Duplex interface.\n");
2108                 val |= BCE_EMAC_MODE_HALF_DUPLEX;
2109         } else
2110                 DBPRINT(sc, BCE_INFO_PHY,
2111                     "Setting Full-Duplex interface.\n");
2112
2113         REG_WR(sc, BCE_EMAC_MODE, val);
2114
2115         if ((IFM_OPTIONS(media_active) & IFM_ETH_RXPAUSE) != 0) {
2116                 DBPRINT(sc, BCE_INFO_PHY,
2117                     "%s(): Enabling RX flow control.\n", __FUNCTION__);
2118                 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2119         } else {
2120                 DBPRINT(sc, BCE_INFO_PHY,
2121                     "%s(): Disabling RX flow control.\n", __FUNCTION__);
2122                 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
2123         }
2124
2125         if ((IFM_OPTIONS(media_active) & IFM_ETH_TXPAUSE) != 0) {
2126                 DBPRINT(sc, BCE_INFO_PHY,
2127                     "%s(): Enabling TX flow control.\n", __FUNCTION__);
2128                 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2129                 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL;
2130         } else {
2131                 DBPRINT(sc, BCE_INFO_PHY,
2132                     "%s(): Disabling TX flow control.\n", __FUNCTION__);
2133                 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
2134                 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL;
2135         }
2136
2137         /* ToDo: Update watermarks in bce_init_rx_context(). */
2138
2139 bce_miibus_statchg_exit:
2140         DBEXIT(BCE_VERBOSE_PHY);
2141 }
2142
2143
2144 /****************************************************************************/
2145 /* Acquire NVRAM lock.                                                      */
2146 /*                                                                          */
2147 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
2148 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
2149 /* for use by the driver.                                                   */
2150 /*                                                                          */
2151 /* Returns:                                                                 */
2152 /*   0 on success, positive value on failure.                               */
2153 /****************************************************************************/
2154 static int
2155 bce_acquire_nvram_lock(struct bce_softc *sc)
2156 {
2157         u32 val;
2158         int j, rc = 0;
2159
2160         DBENTER(BCE_VERBOSE_NVRAM);
2161
2162         /* Request access to the flash interface. */
2163         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
2164         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2165                 val = REG_RD(sc, BCE_NVM_SW_ARB);
2166                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
2167                         break;
2168
2169                 DELAY(5);
2170         }
2171
2172         if (j >= NVRAM_TIMEOUT_COUNT) {
2173                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
2174                 rc = EBUSY;
2175         }
2176
2177         DBEXIT(BCE_VERBOSE_NVRAM);
2178         return (rc);
2179 }
2180
2181
2182 /****************************************************************************/
2183 /* Release NVRAM lock.                                                      */
2184 /*                                                                          */
2185 /* When the caller is finished accessing NVRAM the lock must be released.   */
2186 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
2187 /* for use by the driver.                                                   */
2188 /*                                                                          */
2189 /* Returns:                                                                 */
2190 /*   0 on success, positive value on failure.                               */
2191 /****************************************************************************/
2192 static int
2193 bce_release_nvram_lock(struct bce_softc *sc)
2194 {
2195         u32 val;
2196         int j, rc = 0;
2197
2198         DBENTER(BCE_VERBOSE_NVRAM);
2199
2200         /*
2201          * Relinquish nvram interface.
2202          */
2203         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
2204
2205         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2206                 val = REG_RD(sc, BCE_NVM_SW_ARB);
2207                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
2208                         break;
2209
2210                 DELAY(5);
2211         }
2212
2213         if (j >= NVRAM_TIMEOUT_COUNT) {
2214                 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
2215                 rc = EBUSY;
2216         }
2217
2218         DBEXIT(BCE_VERBOSE_NVRAM);
2219         return (rc);
2220 }
2221
2222
2223 #ifdef BCE_NVRAM_WRITE_SUPPORT
2224 /****************************************************************************/
2225 /* Enable NVRAM write access.                                               */
2226 /*                                                                          */
2227 /* Before writing to NVRAM the caller must enable NVRAM writes.             */
2228 /*                                                                          */
2229 /* Returns:                                                                 */
2230 /*   0 on success, positive value on failure.                               */
2231 /****************************************************************************/
2232 static int
2233 bce_enable_nvram_write(struct bce_softc *sc)
2234 {
2235         u32 val;
2236         int rc = 0;
2237
2238         DBENTER(BCE_VERBOSE_NVRAM);
2239
2240         val = REG_RD(sc, BCE_MISC_CFG);
2241         REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
2242
2243         if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2244                 int j;
2245
2246                 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2247                 REG_WR(sc, BCE_NVM_COMMAND,     BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
2248
2249                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2250                         DELAY(5);
2251
2252                         val = REG_RD(sc, BCE_NVM_COMMAND);
2253                         if (val & BCE_NVM_COMMAND_DONE)
2254                                 break;
2255                 }
2256
2257                 if (j >= NVRAM_TIMEOUT_COUNT) {
2258                         DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
2259                         rc = EBUSY;
2260                 }
2261         }
2262
2263         DBENTER(BCE_VERBOSE_NVRAM);
2264         return (rc);
2265 }
2266
2267
2268 /****************************************************************************/
2269 /* Disable NVRAM write access.                                              */
2270 /*                                                                          */
2271 /* When the caller is finished writing to NVRAM write access must be        */
2272 /* disabled.                                                                */
2273 /*                                                                          */
2274 /* Returns:                                                                 */
2275 /*   Nothing.                                                               */
2276 /****************************************************************************/
2277 static void
2278 bce_disable_nvram_write(struct bce_softc *sc)
2279 {
2280         u32 val;
2281
2282         DBENTER(BCE_VERBOSE_NVRAM);
2283
2284         val = REG_RD(sc, BCE_MISC_CFG);
2285         REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
2286
2287         DBEXIT(BCE_VERBOSE_NVRAM);
2288
2289 }
2290 #endif
2291
2292
2293 /****************************************************************************/
2294 /* Enable NVRAM access.                                                     */
2295 /*                                                                          */
2296 /* Before accessing NVRAM for read or write operations the caller must      */
2297 /* enabled NVRAM access.                                                    */
2298 /*                                                                          */
2299 /* Returns:                                                                 */
2300 /*   Nothing.                                                               */
2301 /****************************************************************************/
2302 static void
2303 bce_enable_nvram_access(struct bce_softc *sc)
2304 {
2305         u32 val;
2306
2307         DBENTER(BCE_VERBOSE_NVRAM);
2308
2309         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2310         /* Enable both bits, even on read. */
2311         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
2312             BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
2313
2314         DBEXIT(BCE_VERBOSE_NVRAM);
2315 }
2316
2317
2318 /****************************************************************************/
2319 /* Disable NVRAM access.                                                    */
2320 /*                                                                          */
2321 /* When the caller is finished accessing NVRAM access must be disabled.     */
2322 /*                                                                          */
2323 /* Returns:                                                                 */
2324 /*   Nothing.                                                               */
2325 /****************************************************************************/
2326 static void
2327 bce_disable_nvram_access(struct bce_softc *sc)
2328 {
2329         u32 val;
2330
2331         DBENTER(BCE_VERBOSE_NVRAM);
2332
2333         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
2334
2335         /* Disable both bits, even after read. */
2336         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
2337             ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
2338
2339         DBEXIT(BCE_VERBOSE_NVRAM);
2340 }
2341
2342
2343 #ifdef BCE_NVRAM_WRITE_SUPPORT
2344 /****************************************************************************/
2345 /* Erase NVRAM page before writing.                                         */
2346 /*                                                                          */
2347 /* Non-buffered flash parts require that a page be erased before it is      */
2348 /* written.                                                                 */
2349 /*                                                                          */
2350 /* Returns:                                                                 */
2351 /*   0 on success, positive value on failure.                               */
2352 /****************************************************************************/
2353 static int
2354 bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
2355 {
2356         u32 cmd;
2357         int j, rc = 0;
2358
2359         DBENTER(BCE_VERBOSE_NVRAM);
2360
2361         /* Buffered flash doesn't require an erase. */
2362         if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
2363                 goto bce_nvram_erase_page_exit;
2364
2365         /* Build an erase command. */
2366         cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
2367             BCE_NVM_COMMAND_DOIT;
2368
2369         /*
2370          * Clear the DONE bit separately, set the NVRAM adress to erase,
2371          * and issue the erase command.
2372          */
2373         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2374         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2375         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2376
2377         /* Wait for completion. */
2378         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2379                 u32 val;
2380
2381                 DELAY(5);
2382
2383                 val = REG_RD(sc, BCE_NVM_COMMAND);
2384                 if (val & BCE_NVM_COMMAND_DONE)
2385                         break;
2386         }
2387
2388         if (j >= NVRAM_TIMEOUT_COUNT) {
2389                 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
2390                 rc = EBUSY;
2391         }
2392
2393 bce_nvram_erase_page_exit:
2394         DBEXIT(BCE_VERBOSE_NVRAM);
2395         return (rc);
2396 }
2397 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2398
2399
2400 /****************************************************************************/
2401 /* Read a dword (32 bits) from NVRAM.                                       */
2402 /*                                                                          */
2403 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
2404 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
2405 /*                                                                          */
2406 /* Returns:                                                                 */
2407 /*   0 on success and the 32 bit value read, positive value on failure.     */
2408 /****************************************************************************/
2409 static int
2410 bce_nvram_read_dword(struct bce_softc *sc,
2411     u32 offset, u8 *ret_val, u32 cmd_flags)
2412 {
2413         u32 cmd;
2414         int i, rc = 0;
2415
2416         DBENTER(BCE_EXTREME_NVRAM);
2417
2418         /* Build the command word. */
2419         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
2420
2421         /* Calculate the offset for buffered flash if translation is used. */
2422         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2423                 offset = ((offset / sc->bce_flash_info->page_size) <<
2424                     sc->bce_flash_info->page_bits) +
2425                     (offset % sc->bce_flash_info->page_size);
2426         }
2427
2428         /*
2429          * Clear the DONE bit separately, set the address to read,
2430          * and issue the read.
2431          */
2432         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2433         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2434         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2435
2436         /* Wait for completion. */
2437         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
2438                 u32 val;
2439
2440                 DELAY(5);
2441
2442                 val = REG_RD(sc, BCE_NVM_COMMAND);
2443                 if (val & BCE_NVM_COMMAND_DONE) {
2444                         val = REG_RD(sc, BCE_NVM_READ);
2445
2446                         val = bce_be32toh(val);
2447                         memcpy(ret_val, &val, 4);
2448                         break;
2449                 }
2450         }
2451
2452         /* Check for errors. */
2453         if (i >= NVRAM_TIMEOUT_COUNT) {
2454                 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at "
2455                     "offset 0x%08X!\n", __FILE__, __LINE__, offset);
2456                 rc = EBUSY;
2457         }
2458
2459         DBEXIT(BCE_EXTREME_NVRAM);
2460         return(rc);
2461 }
2462
2463
2464 #ifdef BCE_NVRAM_WRITE_SUPPORT
2465 /****************************************************************************/
2466 /* Write a dword (32 bits) to NVRAM.                                        */
2467 /*                                                                          */
2468 /* Write a 32 bit word to NVRAM.  The caller is assumed to have already     */
2469 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and    */
2470 /* enabled NVRAM write access.                                              */
2471 /*                                                                          */
2472 /* Returns:                                                                 */
2473 /*   0 on success, positive value on failure.                               */
2474 /****************************************************************************/
2475 static int
2476 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
2477         u32 cmd_flags)
2478 {
2479         u32 cmd, val32;
2480         int j, rc = 0;
2481
2482         DBENTER(BCE_VERBOSE_NVRAM);
2483
2484         /* Build the command word. */
2485         cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
2486
2487         /* Calculate the offset for buffered flash if translation is used. */
2488         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2489                 offset = ((offset / sc->bce_flash_info->page_size) <<
2490                     sc->bce_flash_info->page_bits) +
2491                     (offset % sc->bce_flash_info->page_size);
2492         }
2493
2494         /*
2495          * Clear the DONE bit separately, convert NVRAM data to big-endian,
2496          * set the NVRAM address to write, and issue the write command
2497          */
2498         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2499         memcpy(&val32, val, 4);
2500         val32 = htobe32(val32);
2501         REG_WR(sc, BCE_NVM_WRITE, val32);
2502         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2503         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2504
2505         /* Wait for completion. */
2506         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2507                 DELAY(5);
2508
2509                 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
2510                         break;
2511         }
2512         if (j >= NVRAM_TIMEOUT_COUNT) {
2513                 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at "
2514                     "offset 0x%08X\n", __FILE__, __LINE__, offset);
2515                 rc = EBUSY;
2516         }
2517
2518         DBEXIT(BCE_VERBOSE_NVRAM);
2519         return (rc);
2520 }
2521 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2522
2523
2524 /****************************************************************************/
2525 /* Initialize NVRAM access.                                                 */
2526 /*                                                                          */
2527 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
2528 /* access that device.                                                      */
2529 /*                                                                          */
2530 /* Returns:                                                                 */
2531 /*   0 on success, positive value on failure.                               */
2532 /****************************************************************************/
2533 static int
2534 bce_init_nvram(struct bce_softc *sc)
2535 {
2536         u32 val;
2537         int j, entry_count, rc = 0;
2538         struct flash_spec *flash;
2539
2540         DBENTER(BCE_VERBOSE_NVRAM);
2541
2542         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2543                 sc->bce_flash_info = &flash_5709;
2544                 goto bce_init_nvram_get_flash_size;
2545         }
2546
2547         /* Determine the selected interface. */
2548         val = REG_RD(sc, BCE_NVM_CFG1);
2549
2550         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2551
2552         /*
2553          * Flash reconfiguration is required to support additional
2554          * NVRAM devices not directly supported in hardware.
2555          * Check if the flash interface was reconfigured
2556          * by the bootcode.
2557          */
2558
2559         if (val & 0x40000000) {
2560                 /* Flash interface reconfigured by bootcode. */
2561
2562                 DBPRINT(sc,BCE_INFO_LOAD,
2563                         "bce_init_nvram(): Flash WAS reconfigured.\n");
2564
2565                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2566                      j++, flash++) {
2567                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
2568                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2569                                 sc->bce_flash_info = flash;
2570                                 break;
2571                         }
2572                 }
2573         } else {
2574                 /* Flash interface not yet reconfigured. */
2575                 u32 mask;
2576
2577                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n",
2578                         __FUNCTION__);
2579
2580                 if (val & (1 << 23))
2581                         mask = FLASH_BACKUP_STRAP_MASK;
2582                 else
2583                         mask = FLASH_STRAP_MASK;
2584
2585                 /* Look for the matching NVRAM device configuration data. */
2586                 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {
2587
2588                         /* Check if the device matches any of the known devices. */
2589                         if ((val & mask) == (flash->strapping & mask)) {
2590                                 /* Found a device match. */
2591                                 sc->bce_flash_info = flash;
2592
2593                                 /* Request access to the flash interface. */
2594                                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2595                                         return rc;
2596
2597                                 /* Reconfigure the flash interface. */
2598                                 bce_enable_nvram_access(sc);
2599                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2600                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2601                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2602                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
2603                                 bce_disable_nvram_access(sc);
2604                                 bce_release_nvram_lock(sc);
2605
2606                                 break;
2607                         }
2608                 }
2609         }
2610
2611         /* Check if a matching device was found. */
2612         if (j == entry_count) {
2613                 sc->bce_flash_info = NULL;
2614                 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
2615                     __FILE__, __LINE__);
2616                 DBEXIT(BCE_VERBOSE_NVRAM);
2617                 return (ENODEV);
2618         }
2619
2620 bce_init_nvram_get_flash_size:
2621         /* Write the flash config data to the shared memory interface. */
2622         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2);
2623         val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2624         if (val)
2625                 sc->bce_flash_size = val;
2626         else
2627                 sc->bce_flash_size = sc->bce_flash_info->total_size;
2628
2629         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2630             __FUNCTION__, sc->bce_flash_info->name,
2631             sc->bce_flash_info->total_size);
2632
2633         DBEXIT(BCE_VERBOSE_NVRAM);
2634         return rc;
2635 }
2636
2637
2638 /****************************************************************************/
2639 /* Read an arbitrary range of data from NVRAM.                              */
2640 /*                                                                          */
2641 /* Prepares the NVRAM interface for access and reads the requested data     */
2642 /* into the supplied buffer.                                                */
2643 /*                                                                          */
2644 /* Returns:                                                                 */
2645 /*   0 on success and the data read, positive value on failure.             */
2646 /****************************************************************************/
2647 static int
2648 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
2649         int buf_size)
2650 {
2651         int rc = 0;
2652         u32 cmd_flags, offset32, len32, extra;
2653
2654         DBENTER(BCE_VERBOSE_NVRAM);
2655
2656         if (buf_size == 0)
2657                 goto bce_nvram_read_exit;
2658
2659         /* Request access to the flash interface. */
2660         if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2661                 goto bce_nvram_read_exit;
2662
2663         /* Enable access to flash interface */
2664         bce_enable_nvram_access(sc);
2665
2666         len32 = buf_size;
2667         offset32 = offset;
2668         extra = 0;
2669
2670         cmd_flags = 0;
2671
2672         if (offset32 & 3) {
2673                 u8 buf[4];
2674                 u32 pre_len;
2675
2676                 offset32 &= ~3;
2677                 pre_len = 4 - (offset & 3);
2678
2679                 if (pre_len >= len32) {
2680                         pre_len = len32;
2681                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
2682                 }
2683                 else {
2684                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2685                 }
2686
2687                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2688
2689                 if (rc)
2690                         return rc;
2691
2692                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2693
2694                 offset32 += 4;
2695                 ret_buf += pre_len;
2696                 len32 -= pre_len;
2697         }
2698
2699         if (len32 & 3) {
2700                 extra = 4 - (len32 & 3);
2701                 len32 = (len32 + 4) & ~3;
2702         }
2703
2704         if (len32 == 4) {
2705                 u8 buf[4];
2706
2707                 if (cmd_flags)
2708                         cmd_flags = BCE_NVM_COMMAND_LAST;
2709                 else
2710                         cmd_flags = BCE_NVM_COMMAND_FIRST |
2711                                     BCE_NVM_COMMAND_LAST;
2712
2713                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2714
2715                 memcpy(ret_buf, buf, 4 - extra);
2716         }
2717         else if (len32 > 0) {
2718                 u8 buf[4];
2719
2720                 /* Read the first word. */
2721                 if (cmd_flags)
2722                         cmd_flags = 0;
2723                 else
2724                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2725
2726                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
2727
2728                 /* Advance to the next dword. */
2729                 offset32 += 4;
2730                 ret_buf += 4;
2731                 len32 -= 4;
2732
2733                 while (len32 > 4 && rc == 0) {
2734                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
2735
2736                         /* Advance to the next dword. */
2737                         offset32 += 4;
2738                         ret_buf += 4;
2739                         len32 -= 4;
2740                 }
2741
2742                 if (rc)
2743                         goto bce_nvram_read_locked_exit;
2744
2745                 cmd_flags = BCE_NVM_COMMAND_LAST;
2746                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2747
2748                 memcpy(ret_buf, buf, 4 - extra);
2749         }
2750
2751 bce_nvram_read_locked_exit:
2752         /* Disable access to flash interface and release the lock. */
2753         bce_disable_nvram_access(sc);
2754         bce_release_nvram_lock(sc);
2755
2756 bce_nvram_read_exit:
2757         DBEXIT(BCE_VERBOSE_NVRAM);
2758         return rc;
2759 }
2760
2761
2762 #ifdef BCE_NVRAM_WRITE_SUPPORT
2763 /****************************************************************************/
2764 /* Write an arbitrary range of data from NVRAM.                             */
2765 /*                                                                          */
2766 /* Prepares the NVRAM interface for write access and writes the requested   */
2767 /* data from the supplied buffer.  The caller is responsible for            */
2768 /* calculating any appropriate CRCs.                                        */
2769 /*                                                                          */
2770 /* Returns:                                                                 */
2771 /*   0 on success, positive value on failure.                               */
2772 /****************************************************************************/
2773 static int
2774 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
2775         int buf_size)
2776 {
2777         u32 written, offset32, len32;
2778         u8 *buf, start[4], end[4];
2779         int rc = 0;
2780         int align_start, align_end;
2781
2782         DBENTER(BCE_VERBOSE_NVRAM);
2783
2784         buf = data_buf;
2785         offset32 = offset;
2786         len32 = buf_size;
2787         align_start = align_end = 0;
2788
2789         if ((align_start = (offset32 & 3))) {
2790                 offset32 &= ~3;
2791                 len32 += align_start;
2792                 if ((rc = bce_nvram_read(sc, offset32, start, 4)))
2793                         goto bce_nvram_write_exit;
2794         }
2795
2796         if (len32 & 3) {
2797                 if ((len32 > 4) || !align_start) {
2798                         align_end = 4 - (len32 & 3);
2799                         len32 += align_end;
2800                         if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2801                                 end, 4))) {
2802                                 goto bce_nvram_write_exit;
2803                         }
2804                 }
2805         }
2806
2807         if (align_start || align_end) {
2808                 buf = malloc(len32, M_DEVBUF, M_NOWAIT);
2809                 if (buf == 0) {
2810                         rc = ENOMEM;
2811                         goto bce_nvram_write_exit;
2812                 }
2813
2814                 if (align_start) {
2815                         memcpy(buf, start, 4);
2816                 }
2817
2818                 if (align_end) {
2819                         memcpy(buf + len32 - 4, end, 4);
2820                 }
2821                 memcpy(buf + align_start, data_buf, buf_size);
2822         }
2823
2824         written = 0;
2825         while ((written < len32) && (rc == 0)) {
2826                 u32 page_start, page_end, data_start, data_end;
2827                 u32 addr, cmd_flags;
2828                 int i;
2829                 u8 flash_buffer[264];
2830
2831             /* Find the page_start addr */
2832                 page_start = offset32 + written;
2833                 page_start -= (page_start % sc->bce_flash_info->page_size);
2834                 /* Find the page_end addr */
2835                 page_end = page_start + sc->bce_flash_info->page_size;
2836                 /* Find the data_start addr */
2837                 data_start = (written == 0) ? offset32 : page_start;
2838                 /* Find the data_end addr */
2839                 data_end = (page_end > offset32 + len32) ?
2840                         (offset32 + len32) : page_end;
2841
2842                 /* Request access to the flash interface. */
2843                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2844                         goto bce_nvram_write_exit;
2845
2846                 /* Enable access to flash interface */
2847                 bce_enable_nvram_access(sc);
2848
2849                 cmd_flags = BCE_NVM_COMMAND_FIRST;
2850                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2851                         int j;
2852
2853                         /* Read the whole page into the buffer
2854                          * (non-buffer flash only) */
2855                         for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2856                                 if (j == (sc->bce_flash_info->page_size - 4)) {
2857                                         cmd_flags |= BCE_NVM_COMMAND_LAST;
2858                                 }
2859                                 rc = bce_nvram_read_dword(sc,
2860                                         page_start + j,
2861                                         &flash_buffer[j],
2862                                         cmd_flags);
2863
2864                                 if (rc)
2865                                         goto bce_nvram_write_locked_exit;
2866
2867                                 cmd_flags = 0;
2868                         }
2869                 }
2870
2871                 /* Enable writes to flash interface (unlock write-protect) */
2872                 if ((rc = bce_enable_nvram_write(sc)) != 0)
2873                         goto bce_nvram_write_locked_exit;
2874
2875                 /* Erase the page */
2876                 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2877                         goto bce_nvram_write_locked_exit;
2878
2879                 /* Re-enable the write again for the actual write */
2880                 bce_enable_nvram_write(sc);
2881
2882                 /* Loop to write back the buffer data from page_start to
2883                  * data_start */
2884                 i = 0;
2885                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2886                         for (addr = page_start; addr < data_start;
2887                                 addr += 4, i += 4) {
2888
2889                                 rc = bce_nvram_write_dword(sc, addr,
2890                                         &flash_buffer[i], cmd_flags);
2891
2892                                 if (rc != 0)
2893                                         goto bce_nvram_write_locked_exit;
2894
2895                                 cmd_flags = 0;
2896                         }
2897                 }
2898
2899                 /* Loop to write the new data from data_start to data_end */
2900                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2901                         if ((addr == page_end - 4) ||
2902                                 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2903                                 (addr == data_end - 4))) {
2904
2905                                 cmd_flags |= BCE_NVM_COMMAND_LAST;
2906                         }
2907                         rc = bce_nvram_write_dword(sc, addr, buf,
2908                                 cmd_flags);
2909
2910                         if (rc != 0)
2911                                 goto bce_nvram_write_locked_exit;
2912
2913                         cmd_flags = 0;
2914                         buf += 4;
2915                 }
2916
2917                 /* Loop to write back the buffer data from data_end
2918                  * to page_end */
2919                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2920                         for (addr = data_end; addr < page_end;
2921                                 addr += 4, i += 4) {
2922
2923                                 if (addr == page_end-4) {
2924                                         cmd_flags = BCE_NVM_COMMAND_LAST;
2925                                 }
2926                                 rc = bce_nvram_write_dword(sc, addr,
2927                                         &flash_buffer[i], cmd_flags);
2928
2929                                 if (rc != 0)
2930                                         goto bce_nvram_write_locked_exit;
2931
2932                                 cmd_flags = 0;
2933                         }
2934                 }
2935
2936                 /* Disable writes to flash interface (lock write-protect) */
2937                 bce_disable_nvram_write(sc);
2938
2939                 /* Disable access to flash interface */
2940                 bce_disable_nvram_access(sc);
2941                 bce_release_nvram_lock(sc);
2942
2943                 /* Increment written */
2944                 written += data_end - data_start;
2945         }
2946
2947         goto bce_nvram_write_exit;
2948
2949 bce_nvram_write_locked_exit:
2950         bce_disable_nvram_write(sc);
2951         bce_disable_nvram_access(sc);
2952         bce_release_nvram_lock(sc);
2953
2954 bce_nvram_write_exit:
2955         if (align_start || align_end)
2956                 free(buf, M_DEVBUF);
2957
2958         DBEXIT(BCE_VERBOSE_NVRAM);
2959         return (rc);
2960 }
2961 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2962
2963
2964 /****************************************************************************/
2965 /* Verifies that NVRAM is accessible and contains valid data.               */
2966 /*                                                                          */
2967 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
2968 /* correct.                                                                 */
2969 /*                                                                          */
2970 /* Returns:                                                                 */
2971 /*   0 on success, positive value on failure.                               */
2972 /****************************************************************************/
2973 static int
2974 bce_nvram_test(struct bce_softc *sc)
2975 {
2976         u32 buf[BCE_NVRAM_SIZE / 4];
2977         u8 *data = (u8 *) buf;
2978         int rc = 0;
2979         u32 magic, csum;
2980
2981         DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2982
2983         /*
2984          * Check that the device NVRAM is valid by reading
2985          * the magic value at offset 0.
2986          */
2987         if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2988                 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n",
2989                     __FILE__, __LINE__);
2990                 goto bce_nvram_test_exit;
2991         }
2992
2993         /*
2994          * Verify that offset 0 of the NVRAM contains
2995          * a valid magic number.
2996          */
2997         magic = bce_be32toh(buf[0]);
2998         if (magic != BCE_NVRAM_MAGIC) {
2999                 rc = ENODEV;
3000                 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! "
3001                     "Expected: 0x%08X, Found: 0x%08X\n",
3002                     __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
3003                 goto bce_nvram_test_exit;
3004         }
3005
3006         /*
3007          * Verify that the device NVRAM includes valid
3008          * configuration data.
3009          */
3010         if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
3011                 BCE_PRINTF("%s(%d): Unable to read manufacturing "
3012                     "Information from  NVRAM!\n", __FILE__, __LINE__);
3013                 goto bce_nvram_test_exit;
3014         }
3015
3016         csum = ether_crc32_le(data, 0x100);
3017         if (csum != BCE_CRC32_RESIDUAL) {
3018                 rc = ENODEV;
3019                 BCE_PRINTF("%s(%d): Invalid manufacturing information "
3020                     "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
3021                     __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
3022                 goto bce_nvram_test_exit;
3023         }
3024
3025         csum = ether_crc32_le(data + 0x100, 0x100);
3026         if (csum != BCE_CRC32_RESIDUAL) {
3027                 rc = ENODEV;
3028                 BCE_PRINTF("%s(%d): Invalid feature configuration "
3029                     "information NVRAM CRC! Expected: 0x%08X, "
3030                     "Found: 08%08X\n", __FILE__, __LINE__,
3031                     BCE_CRC32_RESIDUAL, csum);
3032         }
3033
3034 bce_nvram_test_exit:
3035         DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
3036         return rc;
3037 }
3038
3039
3040 /****************************************************************************/
3041 /* Calculates the size of the buffers to allocate based on the MTU.         */
3042 /*                                                                          */
3043 /* Returns:                                                                 */
3044 /*   Nothing.                                                               */
3045 /****************************************************************************/
3046 static void
3047 bce_get_rx_buffer_sizes(struct bce_softc *sc, int mtu)
3048 {
3049         DBENTER(BCE_VERBOSE_LOAD);
3050
3051         /* Use a single allocation type when header splitting enabled. */
3052         if (bce_hdr_split == TRUE) {
3053                 sc->rx_bd_mbuf_alloc_size = MHLEN;
3054                 /* Make sure offset is 16 byte aligned for hardware. */
3055                 sc->rx_bd_mbuf_align_pad =
3056                         roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN);
3057                 sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
3058                         sc->rx_bd_mbuf_align_pad;
3059                 sc->pg_bd_mbuf_alloc_size = MCLBYTES;
3060         } else {
3061                 if ((mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
3062                     ETHER_CRC_LEN) > MCLBYTES) {
3063                         /* Setup for jumbo RX buffer allocations. */
3064                         sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
3065                         sc->rx_bd_mbuf_align_pad  =
3066                                 roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
3067                         sc->rx_bd_mbuf_data_len =
3068                             sc->rx_bd_mbuf_alloc_size -
3069                             sc->rx_bd_mbuf_align_pad;
3070                 } else {
3071                         /* Setup for standard RX buffer allocations. */
3072                         sc->rx_bd_mbuf_alloc_size = MCLBYTES;
3073                         sc->rx_bd_mbuf_align_pad  =
3074                             roundup2(MCLBYTES, 16) - MCLBYTES;
3075                         sc->rx_bd_mbuf_data_len =
3076                             sc->rx_bd_mbuf_alloc_size -
3077                             sc->rx_bd_mbuf_align_pad;
3078                 }
3079         }
3080
3081 //      DBPRINT(sc, BCE_INFO_LOAD,
3082         DBPRINT(sc, BCE_WARN,
3083            "%s(): rx_bd_mbuf_alloc_size = %d, rx_bd_mbuf_data_len = %d, "
3084            "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
3085            sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
3086            sc->rx_bd_mbuf_align_pad);
3087
3088         DBEXIT(BCE_VERBOSE_LOAD);
3089
3090 }
3091
3092 /****************************************************************************/
3093 /* Identifies the current media type of the controller and sets the PHY     */
3094 /* address.                                                                 */
3095 /*                                                                          */
3096 /* Returns:                                                                 */
3097 /*   Nothing.                                                               */
3098 /****************************************************************************/
3099 static void
3100 bce_get_media(struct bce_softc *sc)
3101 {
3102         u32 val;
3103
3104         DBENTER(BCE_VERBOSE_PHY);
3105
3106         /* Assume PHY address for copper controllers. */
3107         sc->bce_phy_addr = 1;
3108
3109         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3110                 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
3111                 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
3112                 u32 strap;
3113
3114                 /*
3115                  * The BCM5709S is software configurable
3116                  * for Copper or SerDes operation.
3117                  */
3118                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
3119                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3120                             "for copper.\n");
3121                         goto bce_get_media_exit;
3122                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
3123                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
3124                             "for dual media.\n");
3125                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3126                         goto bce_get_media_exit;
3127                 }
3128
3129                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
3130                         strap = (val &
3131                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
3132                 else
3133                         strap = (val &
3134                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
3135
3136                 if (pci_get_function(sc->bce_dev) == 0) {
3137                         switch (strap) {
3138                         case 0x4:
3139                         case 0x5:
3140                         case 0x6:
3141                                 DBPRINT(sc, BCE_INFO_LOAD,
3142                                     "BCM5709 s/w configured for SerDes.\n");
3143                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3144                                 break;
3145                         default:
3146                                 DBPRINT(sc, BCE_INFO_LOAD,
3147                                     "BCM5709 s/w configured for Copper.\n");
3148                                 break;
3149                         }
3150                 } else {
3151                         switch (strap) {
3152                         case 0x1:
3153                         case 0x2:
3154                         case 0x4:
3155                                 DBPRINT(sc, BCE_INFO_LOAD,
3156                                     "BCM5709 s/w configured for SerDes.\n");
3157                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3158                                 break;
3159                         default:
3160                                 DBPRINT(sc, BCE_INFO_LOAD,
3161                                     "BCM5709 s/w configured for Copper.\n");
3162                                 break;
3163                         }
3164                 }
3165
3166         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
3167                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
3168
3169         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
3170
3171                 sc->bce_flags |= BCE_NO_WOL_FLAG;
3172
3173                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
3174                         sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG;
3175
3176                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
3177                         /* 5708S/09S/16S use a separate PHY for SerDes. */
3178                         sc->bce_phy_addr = 2;
3179
3180                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
3181                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
3182                                 sc->bce_phy_flags |=
3183                                     BCE_PHY_2_5G_CAPABLE_FLAG;
3184                                 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb "
3185                                     "capable adapter\n");
3186                         }
3187                 }
3188         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
3189             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708))
3190                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
3191
3192 bce_get_media_exit:
3193         DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
3194                 "Using PHY address %d.\n", sc->bce_phy_addr);
3195
3196         DBEXIT(BCE_VERBOSE_PHY);
3197 }
3198
3199
3200 /****************************************************************************/
3201 /* Performs PHY initialization required before MII drivers access the       */
3202 /* device.                                                                  */
3203 /*                                                                          */
3204 /* Returns:                                                                 */
3205 /*   Nothing.                                                               */
3206 /****************************************************************************/
3207 static void
3208 bce_init_media(struct bce_softc *sc)
3209 {
3210         if ((sc->bce_phy_flags & (BCE_PHY_IEEE_CLAUSE_45_FLAG |
3211             BCE_PHY_REMOTE_CAP_FLAG)) == BCE_PHY_IEEE_CLAUSE_45_FLAG) {
3212                 /*
3213                  * Configure 5709S/5716S PHYs to use traditional IEEE
3214                  * Clause 22 method. Otherwise we have no way to attach
3215                  * the PHY in mii(4) layer. PHY specific configuration
3216                  * is done in mii layer.
3217                  */
3218
3219                 /* Select auto-negotiation MMD of the PHY. */
3220                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3221                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT);
3222                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3223                     BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD);
3224
3225                 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */
3226                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
3227                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
3228         }
3229 }
3230
3231
3232 /****************************************************************************/
3233 /* Free any DMA memory owned by the driver.                                 */
3234 /*                                                                          */
3235 /* Scans through each data structre that requires DMA memory and frees      */
3236 /* the memory if allocated.                                                 */
3237 /*                                                                          */
3238 /* Returns:                                                                 */
3239 /*   Nothing.                                                               */
3240 /****************************************************************************/
3241 static void
3242 bce_dma_free(struct bce_softc *sc)
3243 {
3244         int i;
3245
3246         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3247
3248         /* Free, unmap, and destroy the status block. */
3249         if (sc->status_block != NULL) {
3250                 bus_dmamem_free(
3251                    sc->status_tag,
3252                     sc->status_block,
3253                     sc->status_map);
3254                 sc->status_block = NULL;
3255         }
3256
3257         if (sc->status_map != NULL) {
3258                 bus_dmamap_unload(
3259                     sc->status_tag,
3260                     sc->status_map);
3261                 bus_dmamap_destroy(sc->status_tag,
3262                     sc->status_map);
3263                 sc->status_map = NULL;
3264         }
3265
3266         if (sc->status_tag != NULL) {
3267                 bus_dma_tag_destroy(sc->status_tag);
3268                 sc->status_tag = NULL;
3269         }
3270
3271
3272         /* Free, unmap, and destroy the statistics block. */
3273         if (sc->stats_block != NULL) {
3274                 bus_dmamem_free(
3275                     sc->stats_tag,
3276                     sc->stats_block,
3277                     sc->stats_map);
3278                 sc->stats_block = NULL;
3279         }
3280
3281         if (sc->stats_map != NULL) {
3282                 bus_dmamap_unload(
3283                     sc->stats_tag,
3284                     sc->stats_map);
3285                 bus_dmamap_destroy(sc->stats_tag,
3286                     sc->stats_map);
3287                 sc->stats_map = NULL;
3288         }
3289
3290         if (sc->stats_tag != NULL) {
3291                 bus_dma_tag_destroy(sc->stats_tag);
3292                 sc->stats_tag = NULL;
3293         }
3294
3295
3296         /* Free, unmap and destroy all context memory pages. */
3297         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3298                 for (i = 0; i < sc->ctx_pages; i++ ) {
3299                         if (sc->ctx_block[i] != NULL) {
3300                                 bus_dmamem_free(
3301                                     sc->ctx_tag,
3302                                     sc->ctx_block[i],
3303                                     sc->ctx_map[i]);
3304                                 sc->ctx_block[i] = NULL;
3305                         }
3306
3307                         if (sc->ctx_map[i] != NULL) {
3308                                 bus_dmamap_unload(
3309                                     sc->ctx_tag,
3310                                     sc->ctx_map[i]);
3311                                 bus_dmamap_destroy(
3312                                     sc->ctx_tag,
3313                                     sc->ctx_map[i]);
3314                                 sc->ctx_map[i] = NULL;
3315                         }
3316                 }
3317
3318                 /* Destroy the context memory tag. */
3319                 if (sc->ctx_tag != NULL) {
3320                         bus_dma_tag_destroy(sc->ctx_tag);
3321                         sc->ctx_tag = NULL;
3322                 }
3323         }
3324
3325
3326         /* Free, unmap and destroy all TX buffer descriptor chain pages. */
3327         for (i = 0; i < sc->tx_pages; i++ ) {
3328                 if (sc->tx_bd_chain[i] != NULL) {
3329                         bus_dmamem_free(
3330                             sc->tx_bd_chain_tag,
3331                             sc->tx_bd_chain[i],
3332                             sc->tx_bd_chain_map[i]);
3333                         sc->tx_bd_chain[i] = NULL;
3334                 }
3335
3336                 if (sc->tx_bd_chain_map[i] != NULL) {
3337                         bus_dmamap_unload(
3338                             sc->tx_bd_chain_tag,
3339                             sc->tx_bd_chain_map[i]);
3340                         bus_dmamap_destroy(
3341                             sc->tx_bd_chain_tag,
3342                             sc->tx_bd_chain_map[i]);
3343                         sc->tx_bd_chain_map[i] = NULL;
3344                 }
3345         }
3346
3347         /* Destroy the TX buffer descriptor tag. */
3348         if (sc->tx_bd_chain_tag != NULL) {
3349                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
3350                 sc->tx_bd_chain_tag = NULL;
3351         }
3352
3353
3354         /* Free, unmap and destroy all RX buffer descriptor chain pages. */
3355         for (i = 0; i < sc->rx_pages; i++ ) {
3356                 if (sc->rx_bd_chain[i] != NULL) {
3357                         bus_dmamem_free(
3358                             sc->rx_bd_chain_tag,
3359                             sc->rx_bd_chain[i],
3360                             sc->rx_bd_chain_map[i]);
3361                         sc->rx_bd_chain[i] = NULL;
3362                 }
3363
3364                 if (sc->rx_bd_chain_map[i] != NULL) {
3365                         bus_dmamap_unload(
3366                             sc->rx_bd_chain_tag,
3367                             sc->rx_bd_chain_map[i]);
3368                         bus_dmamap_destroy(
3369                             sc->rx_bd_chain_tag,
3370                             sc->rx_bd_chain_map[i]);
3371                         sc->rx_bd_chain_map[i] = NULL;
3372                 }
3373         }
3374
3375         /* Destroy the RX buffer descriptor tag. */
3376         if (sc->rx_bd_chain_tag != NULL) {
3377                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
3378                 sc->rx_bd_chain_tag = NULL;
3379         }
3380
3381
3382         /* Free, unmap and destroy all page buffer descriptor chain pages. */
3383         if (bce_hdr_split == TRUE) {
3384                 for (i = 0; i < sc->pg_pages; i++ ) {
3385                         if (sc->pg_bd_chain[i] != NULL) {
3386                                 bus_dmamem_free(
3387                                     sc->pg_bd_chain_tag,
3388                                     sc->pg_bd_chain[i],
3389                                     sc->pg_bd_chain_map[i]);
3390                                 sc->pg_bd_chain[i] = NULL;
3391                         }
3392
3393                         if (sc->pg_bd_chain_map[i] != NULL) {
3394                                 bus_dmamap_unload(
3395                                     sc->pg_bd_chain_tag,
3396                                     sc->pg_bd_chain_map[i]);
3397                                 bus_dmamap_destroy(
3398                                     sc->pg_bd_chain_tag,
3399                                     sc->pg_bd_chain_map[i]);
3400                                 sc->pg_bd_chain_map[i] = NULL;
3401                         }
3402                 }
3403
3404                 /* Destroy the page buffer descriptor tag. */
3405                 if (sc->pg_bd_chain_tag != NULL) {
3406                         bus_dma_tag_destroy(sc->pg_bd_chain_tag);
3407                         sc->pg_bd_chain_tag = NULL;
3408                 }
3409         }
3410
3411
3412         /* Unload and destroy the TX mbuf maps. */
3413         for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
3414                 if (sc->tx_mbuf_map[i] != NULL) {
3415                         bus_dmamap_unload(sc->tx_mbuf_tag,
3416                             sc->tx_mbuf_map[i]);
3417                         bus_dmamap_destroy(sc->tx_mbuf_tag,
3418                             sc->tx_mbuf_map[i]);
3419                         sc->tx_mbuf_map[i] = NULL;
3420                 }
3421         }
3422
3423         /* Destroy the TX mbuf tag. */
3424         if (sc->tx_mbuf_tag != NULL) {
3425                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
3426                 sc->tx_mbuf_tag = NULL;
3427         }
3428
3429         /* Unload and destroy the RX mbuf maps. */
3430         for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
3431                 if (sc->rx_mbuf_map[i] != NULL) {
3432                         bus_dmamap_unload(sc->rx_mbuf_tag,
3433                             sc->rx_mbuf_map[i]);
3434                         bus_dmamap_destroy(sc->rx_mbuf_tag,
3435                             sc->rx_mbuf_map[i]);
3436                         sc->rx_mbuf_map[i] = NULL;
3437                 }
3438         }
3439
3440         /* Destroy the RX mbuf tag. */
3441         if (sc->rx_mbuf_tag != NULL) {
3442                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
3443                 sc->rx_mbuf_tag = NULL;
3444         }
3445
3446         /* Unload and destroy the page mbuf maps. */
3447         if (bce_hdr_split == TRUE) {
3448                 for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
3449                         if (sc->pg_mbuf_map[i] != NULL) {
3450                                 bus_dmamap_unload(sc->pg_mbuf_tag,
3451                                     sc->pg_mbuf_map[i]);
3452                                 bus_dmamap_destroy(sc->pg_mbuf_tag,
3453                                     sc->pg_mbuf_map[i]);
3454                                 sc->pg_mbuf_map[i] = NULL;
3455                         }
3456                 }
3457
3458                 /* Destroy the page mbuf tag. */
3459                 if (sc->pg_mbuf_tag != NULL) {
3460                         bus_dma_tag_destroy(sc->pg_mbuf_tag);
3461                         sc->pg_mbuf_tag = NULL;
3462                 }
3463         }
3464
3465         /* Destroy the parent tag */
3466         if (sc->parent_tag != NULL) {
3467                 bus_dma_tag_destroy(sc->parent_tag);
3468                 sc->parent_tag = NULL;
3469         }
3470
3471         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3472 }
3473
3474
3475 /****************************************************************************/
3476 /* Get DMA memory from the OS.                                              */
3477 /*                                                                          */
3478 /* Validates that the OS has provided DMA buffers in response to a          */
3479 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
3480 /* When the callback is used the OS will return 0 for the mapping function  */
3481 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
3482 /* failures back to the caller.                                             */
3483 /*                                                                          */
3484 /* Returns:                                                                 */
3485 /*   Nothing.                                                               */
3486 /****************************************************************************/
3487 static void
3488 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3489 {
3490         bus_addr_t *busaddr = arg;
3491
3492         KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!",
3493             __FUNCTION__, nseg));
3494         /* Simulate a mapping failure. */
3495         DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control),
3496             error = ENOMEM);
3497
3498         /* ToDo: How to increment debug sim_count variable here? */
3499
3500         /* Check for an error and signal the caller that an error occurred. */
3501         if (error) {
3502                 *busaddr = 0;
3503         } else {
3504                 *busaddr = segs->ds_addr;
3505         }
3506
3507         return;
3508 }
3509
3510
3511 /****************************************************************************/
3512 /* Allocate any DMA memory needed by the driver.                            */
3513 /*                                                                          */
3514 /* Allocates DMA memory needed for the various global structures needed by  */
3515 /* hardware.                                                                */
3516 /*                                                                          */
3517 /* Memory alignment requirements:                                           */
3518 /* +-----------------+----------+----------+----------+----------+          */
3519 /* |                 |   5706   |   5708   |   5709   |   5716   |          */
3520 /* +-----------------+----------+----------+----------+----------+          */
3521 /* |Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3522 /* |Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3523 /* |RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |          */
3524 /* |PG Buffers       |   none   |   none   |   none   |   none   |          */
3525 /* |TX Buffers       |   none   |   none   |   none   |   none   |          */
3526 /* |Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |          */
3527 /* |Context Memory   |          |          |          |          |          */
3528 /* +-----------------+----------+----------+----------+----------+          */
3529 /*                                                                          */
3530 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
3531 /*                                                                          */
3532 /* Returns:                                                                 */
3533 /*   0 for success, positive value for failure.                             */
3534 /****************************************************************************/
3535 static int
3536 bce_dma_alloc(device_t dev)
3537 {
3538         struct bce_softc *sc;
3539         int i, error, rc = 0;
3540         bus_size_t max_size, max_seg_size;
3541         int max_segments;
3542
3543         sc = device_get_softc(dev);
3544
3545         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3546
3547         /*
3548          * Allocate the parent bus DMA tag appropriate for PCI.
3549          */
3550         if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY,
3551             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3552             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3553             &sc->parent_tag)) {
3554                 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
3555                     __FILE__, __LINE__);
3556                 rc = ENOMEM;
3557                 goto bce_dma_alloc_exit;
3558         }
3559
3560         /*
3561          * Create a DMA tag for the status block, allocate and clear the
3562          * memory, map the memory into DMA space, and fetch the physical
3563          * address of the block.
3564          */
3565         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3566             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3567             NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
3568             0, NULL, NULL, &sc->status_tag)) {
3569                 BCE_PRINTF("%s(%d): Could not allocate status block "
3570                     "DMA tag!\n", __FILE__, __LINE__);
3571                 rc = ENOMEM;
3572                 goto bce_dma_alloc_exit;
3573         }
3574
3575         if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
3576             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3577             &sc->status_map)) {
3578                 BCE_PRINTF("%s(%d): Could not allocate status block "
3579                     "DMA memory!\n", __FILE__, __LINE__);
3580                 rc = ENOMEM;
3581                 goto bce_dma_alloc_exit;
3582         }
3583
3584         error = bus_dmamap_load(sc->status_tag, sc->status_map,
3585             sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr,
3586             &sc->status_block_paddr, BUS_DMA_NOWAIT);
3587
3588         if (error) {
3589                 BCE_PRINTF("%s(%d): Could not map status block "
3590                     "DMA memory!\n", __FILE__, __LINE__);
3591                 rc = ENOMEM;
3592                 goto bce_dma_alloc_exit;
3593         }
3594
3595         DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n",
3596             __FUNCTION__, (uintmax_t) sc->status_block_paddr);
3597
3598         /*
3599          * Create a DMA tag for the statistics block, allocate and clear the
3600          * memory, map the memory into DMA space, and fetch the physical
3601          * address of the block.
3602          */
3603         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3604             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3605             NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
3606             0, NULL, NULL, &sc->stats_tag)) {
3607                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3608                     "DMA tag!\n", __FILE__, __LINE__);
3609                 rc = ENOMEM;
3610                 goto bce_dma_alloc_exit;
3611         }
3612
3613         if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
3614             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) {
3615                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3616                     "DMA memory!\n", __FILE__, __LINE__);
3617                 rc = ENOMEM;
3618                 goto bce_dma_alloc_exit;
3619         }
3620
3621         error = bus_dmamap_load(sc->stats_tag, sc->stats_map,
3622             sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr,
3623             &sc->stats_block_paddr, BUS_DMA_NOWAIT);
3624
3625         if(error) {
3626                 BCE_PRINTF("%s(%d): Could not map statistics block "
3627                     "DMA memory!\n", __FILE__, __LINE__);
3628                 rc = ENOMEM;
3629                 goto bce_dma_alloc_exit;
3630         }
3631
3632         DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n",
3633             __FUNCTION__, (uintmax_t) sc->stats_block_paddr);
3634
3635         /* BCM5709 uses host memory as cache for context memory. */
3636         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
3637                 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3638                 if (sc->ctx_pages == 0)
3639                         sc->ctx_pages = 1;
3640
3641                 DBRUNIF((sc->ctx_pages > 512),
3642                     BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n",
3643                     __FILE__, __LINE__, sc->ctx_pages));
3644
3645                 /*
3646                  * Create a DMA tag for the context pages,
3647                  * allocate and clear the memory, map the
3648                  * memory into DMA space, and fetch the
3649                  * physical address of the block.
3650                  */
3651                 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3652                     BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3653                     NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
3654                     0, NULL, NULL, &sc->ctx_tag)) {
3655                         BCE_PRINTF("%s(%d): Could not allocate CTX "
3656                             "DMA tag!\n", __FILE__, __LINE__);
3657                         rc = ENOMEM;
3658                         goto bce_dma_alloc_exit;
3659                 }
3660
3661                 for (i = 0; i < sc->ctx_pages; i++) {
3662
3663                         if(bus_dmamem_alloc(sc->ctx_tag,
3664                             (void **)&sc->ctx_block[i],
3665                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3666                             &sc->ctx_map[i])) {
3667                                 BCE_PRINTF("%s(%d): Could not allocate CTX "
3668                                     "DMA memory!\n", __FILE__, __LINE__);
3669                                 rc = ENOMEM;
3670                                 goto bce_dma_alloc_exit;
3671                         }
3672
3673                         error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
3674                             sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr,
3675                             &sc->ctx_paddr[i], BUS_DMA_NOWAIT);
3676
3677                         if (error) {
3678                                 BCE_PRINTF("%s(%d): Could not map CTX "
3679                                     "DMA memory!\n", __FILE__, __LINE__);
3680                                 rc = ENOMEM;
3681                                 goto bce_dma_alloc_exit;
3682                         }
3683
3684                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] "
3685                             "= 0x%jX\n", __FUNCTION__, i,
3686                             (uintmax_t) sc->ctx_paddr[i]);
3687                 }
3688         }
3689
3690         /*
3691          * Create a DMA tag for the TX buffer descriptor chain,
3692          * allocate and clear the  memory, and fetch the
3693          * physical address of the block.
3694          */
3695         if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
3696             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3697             BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0,
3698             NULL, NULL, &sc->tx_bd_chain_tag)) {
3699                 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3700                     "chain DMA tag!\n", __FILE__, __LINE__);
3701                 rc = ENOMEM;
3702                 goto bce_dma_alloc_exit;
3703         }
3704
3705         for (i = 0; i < sc->tx_pages; i++) {
3706
3707                 if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
3708                     (void **)&sc->tx_bd_chain[i],
3709                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3710                     &sc->tx_bd_chain_map[i])) {
3711                         BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3712                             "chain DMA memory!\n", __FILE__, __LINE__);
3713                         rc = ENOMEM;
3714                         goto bce_dma_alloc_exit;
3715                 }
3716
3717                 error = bus_dmamap_load(sc->tx_bd_chain_tag,
3718                     sc->tx_bd_chain_map[i], sc->tx_bd_chain[i],
3719                     BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3720                     &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3721
3722                 if (error) {
3723                         BCE_PRINTF("%s(%d): Could not map TX descriptor "
3724                             "chain DMA memory!\n", __FILE__, __LINE__);
3725                         rc = ENOMEM;
3726                         goto bce_dma_alloc_exit;
3727                 }
3728
3729                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = "
3730                     "0x%jX\n", __FUNCTION__, i,
3731                     (uintmax_t) sc->tx_bd_chain_paddr[i]);
3732         }
3733
3734         /* Check the required size before mapping to conserve resources. */
3735         if (bce_tso_enable) {
3736                 max_size     = BCE_TSO_MAX_SIZE;
3737                 max_segments = BCE_MAX_SEGMENTS;
3738                 max_seg_size = BCE_TSO_MAX_SEG_SIZE;
3739         } else {
3740                 max_size     = MCLBYTES * BCE_MAX_SEGMENTS;
3741                 max_segments = BCE_MAX_SEGMENTS;
3742                 max_seg_size = MCLBYTES;
3743         }
3744
3745         /* Create a DMA tag for TX mbufs. */
3746         if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3747             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
3748             max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) {
3749                 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
3750                     __FILE__, __LINE__);
3751                 rc = ENOMEM;
3752                 goto bce_dma_alloc_exit;
3753         }
3754
3755         /* Create DMA maps for the TX mbufs clusters. */
3756         for (i = 0; i < TOTAL_TX_BD_ALLOC; i++) {
3757                 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3758                         &sc->tx_mbuf_map[i])) {
3759                         BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA "
3760                             "map!\n", __FILE__, __LINE__);
3761                         rc = ENOMEM;
3762                         goto bce_dma_alloc_exit;
3763                 }
3764         }
3765
3766         /*
3767          * Create a DMA tag for the RX buffer descriptor chain,
3768          * allocate and clear the memory, and fetch the physical
3769          * address of the blocks.
3770          */
3771         if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3772                         BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
3773                         sc->max_bus_addr, NULL, NULL,
3774                         BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
3775                         0, NULL, NULL, &sc->rx_bd_chain_tag)) {
3776                 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain "
3777                     "DMA tag!\n", __FILE__, __LINE__);
3778                 rc = ENOMEM;
3779                 goto bce_dma_alloc_exit;
3780         }
3781
3782         for (i = 0; i < sc->rx_pages; i++) {
3783
3784                 if (bus_dmamem_alloc(sc->rx_bd_chain_tag,
3785                     (void **)&sc->rx_bd_chain[i],
3786                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3787                     &sc->rx_bd_chain_map[i])) {
3788                         BCE_PRINTF("%s(%d): Could not allocate RX descriptor "
3789                             "chain DMA memory!\n", __FILE__, __LINE__);
3790                         rc = ENOMEM;
3791                         goto bce_dma_alloc_exit;
3792                 }
3793
3794                 error = bus_dmamap_load(sc->rx_bd_chain_tag,
3795                     sc->rx_bd_chain_map[i], sc->rx_bd_chain[i],
3796                     BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3797                     &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3798
3799                 if (error) {
3800                         BCE_PRINTF("%s(%d): Could not map RX descriptor "
3801                             "chain DMA memory!\n", __FILE__, __LINE__);
3802                         rc = ENOMEM;
3803                         goto bce_dma_alloc_exit;
3804                 }
3805
3806                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = "
3807                     "0x%jX\n", __FUNCTION__, i,
3808                     (uintmax_t) sc->rx_bd_chain_paddr[i]);
3809         }
3810
3811         /*
3812          * Create a DMA tag for RX mbufs.
3813          */
3814         if (bce_hdr_split == TRUE)
3815                 max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3816                     MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3817         else
3818                 max_size = max_seg_size = MJUM9BYTES;
3819         max_segments = 1;
3820
3821         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
3822             "(max size = 0x%jX max segments = %d, max segment "
3823             "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size,
3824              max_segments, (uintmax_t) max_seg_size);
3825
3826         if (bus_dma_tag_create(sc->parent_tag, BCE_RX_BUF_ALIGN,
3827             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3828             max_size, max_segments, max_seg_size, 0, NULL, NULL,
3829             &sc->rx_mbuf_tag)) {
3830                 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3831                     __FILE__, __LINE__);
3832                 rc = ENOMEM;
3833                 goto bce_dma_alloc_exit;
3834         }
3835
3836         /* Create DMA maps for the RX mbuf clusters. */
3837         for (i = 0; i < TOTAL_RX_BD_ALLOC; i++) {
3838                 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT,
3839                     &sc->rx_mbuf_map[i])) {
3840                         BCE_PRINTF("%s(%d): Unable to create RX mbuf "
3841                             "DMA map!\n", __FILE__, __LINE__);
3842                         rc = ENOMEM;
3843                         goto bce_dma_alloc_exit;
3844                 }
3845         }
3846
3847         if (bce_hdr_split == TRUE) {
3848                 /*
3849                  * Create a DMA tag for the page buffer descriptor chain,
3850                  * allocate and clear the memory, and fetch the physical
3851                  * address of the blocks.
3852                  */
3853                 if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3854                             BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr,
3855                             NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ,
3856                             0, NULL, NULL, &sc->pg_bd_chain_tag)) {
3857                         BCE_PRINTF("%s(%d): Could not allocate page descriptor "
3858                             "chain DMA tag!\n", __FILE__, __LINE__);
3859                         rc = ENOMEM;
3860                         goto bce_dma_alloc_exit;
3861                 }
3862
3863                 for (i = 0; i < sc->pg_pages; i++) {
3864                         if (bus_dmamem_alloc(sc->pg_bd_chain_tag,
3865                             (void **)&sc->pg_bd_chain[i],
3866                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3867                             &sc->pg_bd_chain_map[i])) {
3868                                 BCE_PRINTF("%s(%d): Could not allocate page "
3869                                     "descriptor chain DMA memory!\n",
3870                                     __FILE__, __LINE__);
3871                                 rc = ENOMEM;
3872                                 goto bce_dma_alloc_exit;
3873                         }
3874
3875                         error = bus_dmamap_load(sc->pg_bd_chain_tag,
3876                             sc->pg_bd_chain_map[i], sc->pg_bd_chain[i],
3877                             BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr,
3878                             &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3879
3880                         if (error) {
3881                                 BCE_PRINTF("%s(%d): Could not map page descriptor "
3882                                         "chain DMA memory!\n", __FILE__, __LINE__);
3883                                 rc = ENOMEM;
3884                                 goto bce_dma_alloc_exit;
3885                         }
3886
3887                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
3888                                 "0x%jX\n", __FUNCTION__, i,
3889                                 (uintmax_t) sc->pg_bd_chain_paddr[i]);
3890                 }
3891
3892                 /*
3893                  * Create a DMA tag for page mbufs.
3894                  */
3895                 max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ?
3896                         MCLBYTES : sc->pg_bd_mbuf_alloc_size);
3897
3898                 if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3899                         sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3900                         max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3901                         BCE_PRINTF("%s(%d): Could not allocate page mbuf "
3902                                 "DMA tag!\n", __FILE__, __LINE__);
3903                         rc = ENOMEM;
3904                         goto bce_dma_alloc_exit;
3905                 }
3906
3907                 /* Create DMA maps for the page mbuf clusters. */
3908                 for (i = 0; i < TOTAL_PG_BD_ALLOC; i++) {
3909                         if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT,
3910                                 &sc->pg_mbuf_map[i])) {
3911                                 BCE_PRINTF("%s(%d): Unable to create page mbuf "
3912                                         "DMA map!\n", __FILE__, __LINE__);
3913                                 rc = ENOMEM;
3914                                 goto bce_dma_alloc_exit;
3915                         }
3916                 }
3917         }
3918
3919 bce_dma_alloc_exit:
3920         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3921         return(rc);
3922 }
3923
3924
3925 /****************************************************************************/
3926 /* Release all resources used by the driver.                                */
3927 /*                                                                          */
3928 /* Releases all resources acquired by the driver including interrupts,      */
3929 /* interrupt handler, interfaces, mutexes, and DMA memory.                  */
3930 /*                                                                          */
3931 /* Returns:                                                                 */
3932 /*   Nothing.                                                               */
3933 /****************************************************************************/
3934 static void
3935 bce_release_resources(struct bce_softc *sc)
3936 {
3937         device_t dev;
3938
3939         DBENTER(BCE_VERBOSE_RESET);
3940
3941         dev = sc->bce_dev;
3942
3943         bce_dma_free(sc);
3944
3945         if (sc->bce_intrhand != NULL) {
3946                 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
3947                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3948         }
3949
3950         if (sc->bce_res_irq != NULL) {
3951                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
3952                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
3953                     sc->bce_res_irq);
3954         }
3955
3956         if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3957                 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
3958                 pci_release_msi(dev);
3959         }
3960
3961         if (sc->bce_res_mem != NULL) {
3962                 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
3963                     bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
3964                     sc->bce_res_mem);
3965         }
3966
3967         if (sc->bce_ifp != NULL) {
3968                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
3969                 if_free(sc->bce_ifp);
3970         }
3971
3972         if (mtx_initialized(&sc->bce_mtx))
3973                 BCE_LOCK_DESTROY(sc);
3974
3975         DBEXIT(BCE_VERBOSE_RESET);
3976 }
3977
3978
3979 /****************************************************************************/
3980 /* Firmware synchronization.                                                */
3981 /*                                                                          */
3982 /* Before performing certain events such as a chip reset, synchronize with  */
3983 /* the firmware first.                                                      */
3984 /*                                                                          */
3985 /* Returns:                                                                 */
3986 /*   0 for success, positive value for failure.                             */
3987 /****************************************************************************/
3988 static int
3989 bce_fw_sync(struct bce_softc *sc, u32 msg_data)
3990 {
3991         int i, rc = 0;
3992         u32 val;
3993
3994         DBENTER(BCE_VERBOSE_RESET);
3995
3996         /* Don't waste any time if we've timed out before. */
3997         if (sc->bce_fw_timed_out == TRUE) {
3998                 rc = EBUSY;
3999                 goto bce_fw_sync_exit;
4000         }
4001
4002         /* Increment the message sequence number. */
4003         sc->bce_fw_wr_seq++;
4004         msg_data |= sc->bce_fw_wr_seq;
4005
4006         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = "
4007             "0x%08X\n", msg_data);
4008
4009         /* Send the message to the bootcode driver mailbox. */
4010         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
4011
4012         /* Wait for the bootcode to acknowledge the message. */
4013         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
4014                 /* Check for a response in the bootcode firmware mailbox. */
4015                 val = bce_shmem_rd(sc, BCE_FW_MB);
4016                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
4017                         break;
4018                 DELAY(1000);
4019         }
4020
4021         /* If we've timed out, tell bootcode that we've stopped waiting. */
4022         if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
4023             ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) {
4024
4025                 BCE_PRINTF("%s(%d): Firmware synchronization timeout! "
4026                     "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data);
4027
4028                 msg_data &= ~BCE_DRV_MSG_CODE;
4029                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
4030
4031                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
4032
4033                 sc->bce_fw_timed_out = TRUE;
4034                 rc = EBUSY;
4035         }
4036
4037 bce_fw_sync_exit:
4038         DBEXIT(BCE_VERBOSE_RESET);
4039         return (rc);
4040 }
4041
4042
4043 /****************************************************************************/
4044 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
4045 /*                                                                          */
4046 /* Returns:                                                                 */
4047 /*   Nothing.                                                               */
4048 /****************************************************************************/
4049 static void
4050 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code,
4051         u32 rv2p_code_len, u32 rv2p_proc)
4052 {
4053         int i;
4054         u32 val;
4055
4056         DBENTER(BCE_VERBOSE_RESET);
4057
4058         /* Set the page size used by RV2P. */
4059         if (rv2p_proc == RV2P_PROC2) {
4060                 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
4061         }
4062
4063         for (i = 0; i < rv2p_code_len; i += 8) {
4064                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
4065                 rv2p_code++;
4066                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
4067                 rv2p_code++;
4068
4069                 if (rv2p_proc == RV2P_PROC1) {
4070                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
4071                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
4072                 }
4073                 else {
4074                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
4075                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
4076                 }
4077         }
4078
4079         /* Reset the processor, un-stall is done later. */
4080         if (rv2p_proc == RV2P_PROC1) {
4081                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
4082         }
4083         else {
4084                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
4085         }
4086
4087         DBEXIT(BCE_VERBOSE_RESET);
4088 }
4089
4090
4091 /****************************************************************************/
4092 /* Load RISC processor firmware.                                            */
4093 /*                                                                          */
4094 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
4095 /* associated with a particular processor.                                  */
4096 /*                                                                          */
4097 /* Returns:                                                                 */
4098 /*   Nothing.                                                               */
4099 /****************************************************************************/
4100 static void
4101 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
4102         struct fw_info *fw)
4103 {
4104         u32 offset;
4105
4106         DBENTER(BCE_VERBOSE_RESET);
4107
4108     bce_halt_cpu(sc, cpu_reg);
4109
4110         /* Load the Text area. */
4111         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
4112         if (fw->text) {
4113                 int j;
4114
4115                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
4116                         REG_WR_IND(sc, offset, fw->text[j]);
4117                 }
4118         }
4119
4120         /* Load the Data area. */
4121         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
4122         if (fw->data) {
4123                 int j;
4124
4125                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
4126                         REG_WR_IND(sc, offset, fw->data[j]);
4127                 }
4128         }
4129
4130         /* Load the SBSS area. */
4131         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
4132         if (fw->sbss) {
4133                 int j;
4134
4135                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
4136                         REG_WR_IND(sc, offset, fw->sbss[j]);
4137                 }
4138         }
4139
4140         /* Load the BSS area. */
4141         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
4142         if (fw->bss) {
4143                 int j;
4144
4145                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
4146                         REG_WR_IND(sc, offset, fw->bss[j]);
4147                 }
4148         }
4149
4150         /* Load the Read-Only area. */
4151         offset = cpu_reg->spad_base +
4152                 (fw->rodata_addr - cpu_reg->mips_view_base);
4153         if (fw->rodata) {
4154                 int j;
4155
4156                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
4157                         REG_WR_IND(sc, offset, fw->rodata[j]);
4158                 }
4159         }
4160
4161         /* Clear the pre-fetch instruction and set the FW start address. */
4162         REG_WR_IND(sc, cpu_reg->inst, 0);
4163         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
4164
4165         DBEXIT(BCE_VERBOSE_RESET);
4166 }
4167
4168
4169 /****************************************************************************/
4170 /* Starts the RISC processor.                                               */
4171 /*                                                                          */
4172 /* Assumes the CPU starting address has already been set.                   */
4173 /*                                                                          */
4174 /* Returns:                                                                 */
4175 /*   Nothing.                                                               */
4176 /****************************************************************************/
4177 static void
4178 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4179 {
4180         u32 val;
4181
4182         DBENTER(BCE_VERBOSE_RESET);
4183
4184         /* Start the CPU. */
4185         val = REG_RD_IND(sc, cpu_reg->mode);
4186         val &= ~cpu_reg->mode_value_halt;
4187         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4188         REG_WR_IND(sc, cpu_reg->mode, val);
4189
4190         DBEXIT(BCE_VERBOSE_RESET);
4191 }
4192
4193
4194 /****************************************************************************/
4195 /* Halts the RISC processor.                                                */
4196 /*                                                                          */
4197 /* Returns:                                                                 */
4198 /*   Nothing.                                                               */
4199 /****************************************************************************/
4200 static void
4201 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
4202 {
4203         u32 val;
4204
4205         DBENTER(BCE_VERBOSE_RESET);
4206
4207         /* Halt the CPU. */
4208         val = REG_RD_IND(sc, cpu_reg->mode);
4209         val |= cpu_reg->mode_value_halt;
4210         REG_WR_IND(sc, cpu_reg->mode, val);
4211         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
4212
4213         DBEXIT(BCE_VERBOSE_RESET);
4214 }
4215
4216
4217 /****************************************************************************/
4218 /* Initialize the RX CPU.                                                   */
4219 /*                                                                          */
4220 /* Returns:                                                                 */
4221 /*   Nothing.                                                               */
4222 /****************************************************************************/
4223 static void
4224 bce_start_rxp_cpu(struct bce_softc *sc)
4225 {
4226         struct cpu_reg cpu_reg;
4227
4228         DBENTER(BCE_VERBOSE_RESET);
4229
4230         cpu_reg.mode = BCE_RXP_CPU_MODE;
4231         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4232         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4233         cpu_reg.state = BCE_RXP_CPU_STATE;
4234         cpu_reg.state_value_clear = 0xffffff;
4235         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4236         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4237         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4238         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4239         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4240         cpu_reg.spad_base = BCE_RXP_SCRATCH;
4241         cpu_reg.mips_view_base = 0x8000000;
4242
4243         DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n");
4244         bce_start_cpu(sc, &cpu_reg);
4245
4246         DBEXIT(BCE_VERBOSE_RESET);
4247 }
4248
4249
4250 /****************************************************************************/
4251 /* Initialize the RX CPU.                                                   */
4252 /*                                                                          */
4253 /* Returns:                                                                 */
4254 /*   Nothing.                                                               */
4255 /****************************************************************************/
4256 static void
4257 bce_init_rxp_cpu(struct bce_softc *sc)
4258 {
4259         struct cpu_reg cpu_reg;
4260         struct fw_info fw;
4261
4262         DBENTER(BCE_VERBOSE_RESET);
4263
4264         cpu_reg.mode = BCE_RXP_CPU_MODE;
4265         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
4266         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
4267         cpu_reg.state = BCE_RXP_CPU_STATE;
4268         cpu_reg.state_value_clear = 0xffffff;
4269         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
4270         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
4271         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
4272         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
4273         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
4274         cpu_reg.spad_base = BCE_RXP_SCRATCH;
4275         cpu_reg.mips_view_base = 0x8000000;
4276
4277         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4278                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
4279                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
4280                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
4281                 fw.start_addr = bce_RXP_b09FwStartAddr;
4282
4283                 fw.text_addr = bce_RXP_b09FwTextAddr;
4284                 fw.text_len = bce_RXP_b09FwTextLen;
4285                 fw.text_index = 0;
4286                 fw.text = bce_RXP_b09FwText;
4287
4288                 fw.data_addr = bce_RXP_b09FwDataAddr;
4289                 fw.data_len = bce_RXP_b09FwDataLen;
4290                 fw.data_index = 0;
4291                 fw.data = bce_RXP_b09FwData;
4292
4293                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
4294                 fw.sbss_len = bce_RXP_b09FwSbssLen;
4295                 fw.sbss_index = 0;
4296                 fw.sbss = bce_RXP_b09FwSbss;
4297
4298                 fw.bss_addr = bce_RXP_b09FwBssAddr;
4299                 fw.bss_len = bce_RXP_b09FwBssLen;
4300                 fw.bss_index = 0;
4301                 fw.bss = bce_RXP_b09FwBss;
4302
4303                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
4304                 fw.rodata_len = bce_RXP_b09FwRodataLen;
4305                 fw.rodata_index = 0;
4306                 fw.rodata = bce_RXP_b09FwRodata;
4307         } else {
4308                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
4309                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
4310                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
4311                 fw.start_addr = bce_RXP_b06FwStartAddr;
4312
4313                 fw.text_addr = bce_RXP_b06FwTextAddr;
4314                 fw.text_len = bce_RXP_b06FwTextLen;
4315                 fw.text_index = 0;
4316                 fw.text = bce_RXP_b06FwText;
4317
4318                 fw.data_addr = bce_RXP_b06FwDataAddr;
4319                 fw.data_len = bce_RXP_b06FwDataLen;
4320                 fw.data_index = 0;
4321                 fw.data = bce_RXP_b06FwData;
4322
4323                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
4324                 fw.sbss_len = bce_RXP_b06FwSbssLen;
4325                 fw.sbss_index = 0;
4326                 fw.sbss = bce_RXP_b06FwSbss;
4327
4328                 fw.bss_addr = bce_RXP_b06FwBssAddr;
4329                 fw.bss_len = bce_RXP_b06FwBssLen;
4330                 fw.bss_index = 0;
4331                 fw.bss = bce_RXP_b06FwBss;
4332
4333                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
4334                 fw.rodata_len = bce_RXP_b06FwRodataLen;
4335                 fw.rodata_index = 0;
4336                 fw.rodata = bce_RXP_b06FwRodata;
4337         }
4338
4339         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
4340         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4341
4342     /* Delay RXP start until initialization is complete. */
4343
4344         DBEXIT(BCE_VERBOSE_RESET);
4345 }
4346
4347
4348 /****************************************************************************/
4349 /* Initialize the TX CPU.                                                   */
4350 /*                                                                          */
4351 /* Returns:                                                                 */
4352 /*   Nothing.                                                               */
4353 /****************************************************************************/
4354 static void
4355 bce_init_txp_cpu(struct bce_softc *sc)
4356 {
4357         struct cpu_reg cpu_reg;
4358         struct fw_info fw;
4359
4360         DBENTER(BCE_VERBOSE_RESET);
4361
4362         cpu_reg.mode = BCE_TXP_CPU_MODE;
4363         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
4364         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
4365         cpu_reg.state = BCE_TXP_CPU_STATE;
4366         cpu_reg.state_value_clear = 0xffffff;
4367         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
4368         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
4369         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
4370         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
4371         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
4372         cpu_reg.spad_base = BCE_TXP_SCRATCH;
4373         cpu_reg.mips_view_base = 0x8000000;
4374
4375         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4376                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
4377                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
4378                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
4379                 fw.start_addr = bce_TXP_b09FwStartAddr;
4380
4381                 fw.text_addr = bce_TXP_b09FwTextAddr;
4382                 fw.text_len = bce_TXP_b09FwTextLen;
4383                 fw.text_index = 0;
4384                 fw.text = bce_TXP_b09FwText;
4385
4386                 fw.data_addr = bce_TXP_b09FwDataAddr;
4387                 fw.data_len = bce_TXP_b09FwDataLen;
4388                 fw.data_index = 0;
4389                 fw.data = bce_TXP_b09FwData;
4390
4391                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
4392                 fw.sbss_len = bce_TXP_b09FwSbssLen;
4393                 fw.sbss_index = 0;
4394                 fw.sbss = bce_TXP_b09FwSbss;
4395
4396                 fw.bss_addr = bce_TXP_b09FwBssAddr;
4397                 fw.bss_len = bce_TXP_b09FwBssLen;
4398                 fw.bss_index = 0;
4399                 fw.bss = bce_TXP_b09FwBss;
4400
4401                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
4402                 fw.rodata_len = bce_TXP_b09FwRodataLen;
4403                 fw.rodata_index = 0;
4404                 fw.rodata = bce_TXP_b09FwRodata;
4405         } else {
4406                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
4407                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
4408                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
4409                 fw.start_addr = bce_TXP_b06FwStartAddr;
4410
4411                 fw.text_addr = bce_TXP_b06FwTextAddr;
4412                 fw.text_len = bce_TXP_b06FwTextLen;
4413                 fw.text_index = 0;
4414                 fw.text = bce_TXP_b06FwText;
4415
4416                 fw.data_addr = bce_TXP_b06FwDataAddr;
4417                 fw.data_len = bce_TXP_b06FwDataLen;
4418                 fw.data_index = 0;
4419                 fw.data = bce_TXP_b06FwData;
4420
4421                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
4422                 fw.sbss_len = bce_TXP_b06FwSbssLen;
4423                 fw.sbss_index = 0;
4424                 fw.sbss = bce_TXP_b06FwSbss;
4425
4426                 fw.bss_addr = bce_TXP_b06FwBssAddr;
4427                 fw.bss_len = bce_TXP_b06FwBssLen;
4428                 fw.bss_index = 0;
4429                 fw.bss = bce_TXP_b06FwBss;
4430
4431                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
4432                 fw.rodata_len = bce_TXP_b06FwRodataLen;
4433                 fw.rodata_index = 0;
4434                 fw.rodata = bce_TXP_b06FwRodata;
4435         }
4436
4437         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
4438         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4439     bce_start_cpu(sc, &cpu_reg);
4440
4441         DBEXIT(BCE_VERBOSE_RESET);
4442 }
4443
4444
4445 /****************************************************************************/
4446 /* Initialize the TPAT CPU.                                                 */
4447 /*                                                                          */
4448 /* Returns:                                                                 */
4449 /*   Nothing.                                                               */
4450 /****************************************************************************/
4451 static void
4452 bce_init_tpat_cpu(struct bce_softc *sc)
4453 {
4454         struct cpu_reg cpu_reg;
4455         struct fw_info fw;
4456
4457         DBENTER(BCE_VERBOSE_RESET);
4458
4459         cpu_reg.mode = BCE_TPAT_CPU_MODE;
4460         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4461         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4462         cpu_reg.state = BCE_TPAT_CPU_STATE;
4463         cpu_reg.state_value_clear = 0xffffff;
4464         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4465         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4466         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4467         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4468         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4469         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4470         cpu_reg.mips_view_base = 0x8000000;
4471
4472         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4473                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
4474                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
4475                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
4476                 fw.start_addr = bce_TPAT_b09FwStartAddr;
4477
4478                 fw.text_addr = bce_TPAT_b09FwTextAddr;
4479                 fw.text_len = bce_TPAT_b09FwTextLen;
4480                 fw.text_index = 0;
4481                 fw.text = bce_TPAT_b09FwText;
4482
4483                 fw.data_addr = bce_TPAT_b09FwDataAddr;
4484                 fw.data_len = bce_TPAT_b09FwDataLen;
4485                 fw.data_index = 0;
4486                 fw.data = bce_TPAT_b09FwData;
4487
4488                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
4489                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
4490                 fw.sbss_index = 0;
4491                 fw.sbss = bce_TPAT_b09FwSbss;
4492
4493                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
4494                 fw.bss_len = bce_TPAT_b09FwBssLen;
4495                 fw.bss_index = 0;
4496                 fw.bss = bce_TPAT_b09FwBss;
4497
4498                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
4499                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
4500                 fw.rodata_index = 0;
4501                 fw.rodata = bce_TPAT_b09FwRodata;
4502         } else {
4503                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
4504                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
4505                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
4506                 fw.start_addr = bce_TPAT_b06FwStartAddr;
4507
4508                 fw.text_addr = bce_TPAT_b06FwTextAddr;
4509                 fw.text_len = bce_TPAT_b06FwTextLen;
4510                 fw.text_index = 0;
4511                 fw.text = bce_TPAT_b06FwText;
4512
4513                 fw.data_addr = bce_TPAT_b06FwDataAddr;
4514                 fw.data_len = bce_TPAT_b06FwDataLen;
4515                 fw.data_index = 0;
4516                 fw.data = bce_TPAT_b06FwData;
4517
4518                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
4519                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
4520                 fw.sbss_index = 0;
4521                 fw.sbss = bce_TPAT_b06FwSbss;
4522
4523                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
4524                 fw.bss_len = bce_TPAT_b06FwBssLen;
4525                 fw.bss_index = 0;
4526                 fw.bss = bce_TPAT_b06FwBss;
4527
4528                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
4529                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
4530                 fw.rodata_index = 0;
4531                 fw.rodata = bce_TPAT_b06FwRodata;
4532         }
4533
4534         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
4535         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4536         bce_start_cpu(sc, &cpu_reg);
4537
4538         DBEXIT(BCE_VERBOSE_RESET);
4539 }
4540
4541
4542 /****************************************************************************/
4543 /* Initialize the CP CPU.                                                   */
4544 /*                                                                          */
4545 /* Returns:                                                                 */
4546 /*   Nothing.                                                               */
4547 /****************************************************************************/
4548 static void
4549 bce_init_cp_cpu(struct bce_softc *sc)
4550 {
4551         struct cpu_reg cpu_reg;
4552         struct fw_info fw;
4553
4554         DBENTER(BCE_VERBOSE_RESET);
4555
4556         cpu_reg.mode = BCE_CP_CPU_MODE;
4557         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4558         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4559         cpu_reg.state = BCE_CP_CPU_STATE;
4560         cpu_reg.state_value_clear = 0xffffff;
4561         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4562         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4563         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4564         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4565         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4566         cpu_reg.spad_base = BCE_CP_SCRATCH;
4567         cpu_reg.mips_view_base = 0x8000000;
4568
4569         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4570                 fw.ver_major = bce_CP_b09FwReleaseMajor;
4571                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
4572                 fw.ver_fix = bce_CP_b09FwReleaseFix;
4573                 fw.start_addr = bce_CP_b09FwStartAddr;
4574
4575                 fw.text_addr = bce_CP_b09FwTextAddr;
4576                 fw.text_len = bce_CP_b09FwTextLen;
4577                 fw.text_index = 0;
4578                 fw.text = bce_CP_b09FwText;
4579
4580                 fw.data_addr = bce_CP_b09FwDataAddr;
4581                 fw.data_len = bce_CP_b09FwDataLen;
4582                 fw.data_index = 0;
4583                 fw.data = bce_CP_b09FwData;
4584
4585                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
4586                 fw.sbss_len = bce_CP_b09FwSbssLen;
4587                 fw.sbss_index = 0;
4588                 fw.sbss = bce_CP_b09FwSbss;
4589
4590                 fw.bss_addr = bce_CP_b09FwBssAddr;
4591                 fw.bss_len = bce_CP_b09FwBssLen;
4592                 fw.bss_index = 0;
4593                 fw.bss = bce_CP_b09FwBss;
4594
4595                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
4596                 fw.rodata_len = bce_CP_b09FwRodataLen;
4597                 fw.rodata_index = 0;
4598                 fw.rodata = bce_CP_b09FwRodata;
4599         } else {
4600                 fw.ver_major = bce_CP_b06FwReleaseMajor;
4601                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
4602                 fw.ver_fix = bce_CP_b06FwReleaseFix;
4603                 fw.start_addr = bce_CP_b06FwStartAddr;
4604
4605                 fw.text_addr = bce_CP_b06FwTextAddr;
4606                 fw.text_len = bce_CP_b06FwTextLen;
4607                 fw.text_index = 0;
4608                 fw.text = bce_CP_b06FwText;
4609
4610                 fw.data_addr = bce_CP_b06FwDataAddr;
4611                 fw.data_len = bce_CP_b06FwDataLen;
4612                 fw.data_index = 0;
4613                 fw.data = bce_CP_b06FwData;
4614
4615                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
4616                 fw.sbss_len = bce_CP_b06FwSbssLen;
4617                 fw.sbss_index = 0;
4618                 fw.sbss = bce_CP_b06FwSbss;
4619
4620                 fw.bss_addr = bce_CP_b06FwBssAddr;
4621                 fw.bss_len = bce_CP_b06FwBssLen;
4622                 fw.bss_index = 0;
4623                 fw.bss = bce_CP_b06FwBss;
4624
4625                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
4626                 fw.rodata_len = bce_CP_b06FwRodataLen;
4627                 fw.rodata_index = 0;
4628                 fw.rodata = bce_CP_b06FwRodata;
4629         }
4630
4631         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
4632         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4633         bce_start_cpu(sc, &cpu_reg);
4634
4635         DBEXIT(BCE_VERBOSE_RESET);
4636 }
4637
4638
4639 /****************************************************************************/
4640 /* Initialize the COM CPU.                                                 */
4641 /*                                                                          */
4642 /* Returns:                                                                 */
4643 /*   Nothing.                                                               */
4644 /****************************************************************************/
4645 static void
4646 bce_init_com_cpu(struct bce_softc *sc)
4647 {
4648         struct cpu_reg cpu_reg;
4649         struct fw_info fw;
4650
4651         DBENTER(BCE_VERBOSE_RESET);
4652
4653         cpu_reg.mode = BCE_COM_CPU_MODE;
4654         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4655         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4656         cpu_reg.state = BCE_COM_CPU_STATE;
4657         cpu_reg.state_value_clear = 0xffffff;
4658         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4659         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4660         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4661         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4662         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4663         cpu_reg.spad_base = BCE_COM_SCRATCH;
4664         cpu_reg.mips_view_base = 0x8000000;
4665
4666         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4667                 fw.ver_major = bce_COM_b09FwReleaseMajor;
4668                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
4669                 fw.ver_fix = bce_COM_b09FwReleaseFix;
4670                 fw.start_addr = bce_COM_b09FwStartAddr;
4671
4672                 fw.text_addr = bce_COM_b09FwTextAddr;
4673                 fw.text_len = bce_COM_b09FwTextLen;
4674                 fw.text_index = 0;
4675                 fw.text = bce_COM_b09FwText;
4676
4677                 fw.data_addr = bce_COM_b09FwDataAddr;
4678                 fw.data_len = bce_COM_b09FwDataLen;
4679                 fw.data_index = 0;
4680                 fw.data = bce_COM_b09FwData;
4681
4682                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
4683                 fw.sbss_len = bce_COM_b09FwSbssLen;
4684                 fw.sbss_index = 0;
4685                 fw.sbss = bce_COM_b09FwSbss;
4686
4687                 fw.bss_addr = bce_COM_b09FwBssAddr;
4688                 fw.bss_len = bce_COM_b09FwBssLen;
4689                 fw.bss_index = 0;
4690                 fw.bss = bce_COM_b09FwBss;
4691
4692                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
4693                 fw.rodata_len = bce_COM_b09FwRodataLen;
4694                 fw.rodata_index = 0;
4695                 fw.rodata = bce_COM_b09FwRodata;
4696         } else {
4697                 fw.ver_major = bce_COM_b06FwReleaseMajor;
4698                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
4699                 fw.ver_fix = bce_COM_b06FwReleaseFix;
4700                 fw.start_addr = bce_COM_b06FwStartAddr;
4701
4702                 fw.text_addr = bce_COM_b06FwTextAddr;
4703                 fw.text_len = bce_COM_b06FwTextLen;
4704                 fw.text_index = 0;
4705                 fw.text = bce_COM_b06FwText;
4706
4707                 fw.data_addr = bce_COM_b06FwDataAddr;
4708                 fw.data_len = bce_COM_b06FwDataLen;
4709                 fw.data_index = 0;
4710                 fw.data = bce_COM_b06FwData;
4711
4712                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
4713                 fw.sbss_len = bce_COM_b06FwSbssLen;
4714                 fw.sbss_index = 0;
4715                 fw.sbss = bce_COM_b06FwSbss;
4716
4717                 fw.bss_addr = bce_COM_b06FwBssAddr;
4718                 fw.bss_len = bce_COM_b06FwBssLen;
4719                 fw.bss_index = 0;
4720                 fw.bss = bce_COM_b06FwBss;
4721
4722                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
4723                 fw.rodata_len = bce_COM_b06FwRodataLen;
4724                 fw.rodata_index = 0;
4725                 fw.rodata = bce_COM_b06FwRodata;
4726         }
4727
4728         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
4729         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4730         bce_start_cpu(sc, &cpu_reg);
4731
4732         DBEXIT(BCE_VERBOSE_RESET);
4733 }
4734
4735
4736 /****************************************************************************/
4737 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
4738 /*                                                                          */
4739 /* Loads the firmware for each CPU and starts the CPU.                      */
4740 /*                                                                          */
4741 /* Returns:                                                                 */
4742 /*   Nothing.                                                               */
4743 /****************************************************************************/
4744 static void
4745 bce_init_cpus(struct bce_softc *sc)
4746 {
4747         DBENTER(BCE_VERBOSE_RESET);
4748
4749         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4750
4751                 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) {
4752                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
4753                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
4754                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
4755                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
4756                 } else {
4757                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
4758                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
4759                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
4760                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
4761                 }
4762
4763         } else {
4764                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
4765                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
4766                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
4767                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
4768         }
4769
4770         bce_init_rxp_cpu(sc);
4771         bce_init_txp_cpu(sc);
4772         bce_init_tpat_cpu(sc);
4773         bce_init_com_cpu(sc);
4774         bce_init_cp_cpu(sc);
4775
4776         DBEXIT(BCE_VERBOSE_RESET);
4777 }
4778
4779
4780 /****************************************************************************/
4781 /* Initialize context memory.                                               */
4782 /*                                                                          */
4783 /* Clears the memory associated with each Context ID (CID).                 */
4784 /*                                                                          */
4785 /* Returns:                                                                 */
4786 /*   Nothing.                                                               */
4787 /****************************************************************************/
4788 static int
4789 bce_init_ctx(struct bce_softc *sc)
4790 {
4791         u32 offset, val, vcid_addr;
4792         int i, j, rc, retry_cnt;
4793
4794         rc = 0;
4795         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4796
4797         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
4798                 retry_cnt = CTX_INIT_RETRY_COUNT;
4799
4800                 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n");
4801
4802                 /*
4803                  * BCM5709 context memory may be cached
4804                  * in host memory so prepare the host memory
4805                  * for access.
4806                  */
4807                 val = BCE_CTX_COMMAND_ENABLED |
4808                     BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
4809                 val |= (BCM_PAGE_BITS - 8) << 16;
4810                 REG_WR(sc, BCE_CTX_COMMAND, val);
4811
4812                 /* Wait for mem init command to complete. */
4813                 for (i = 0; i < retry_cnt; i++) {
4814                         val = REG_RD(sc, BCE_CTX_COMMAND);
4815                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4816                                 break;
4817                         DELAY(2);
4818                 }
4819                 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) {
4820                         BCE_PRINTF("%s(): Context memory initialization failed!\n",
4821                             __FUNCTION__);
4822                         rc = EBUSY;
4823                         goto init_ctx_fail;
4824                 }
4825
4826                 for (i = 0; i < sc->ctx_pages; i++) {
4827                         /* Set the physical address of the context memory. */
4828                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4829                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4830                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
4831                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4832                             BCE_ADDR_HI(sc->ctx_paddr[i]));
4833                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4834                             BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4835
4836                         /* Verify the context memory write was successful. */
4837                         for (j = 0; j < retry_cnt; j++) {
4838                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4839                                 if ((val &
4840                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4841                                         break;
4842                                 DELAY(5);
4843                         }
4844                         if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) {
4845                                 BCE_PRINTF("%s(): Failed to initialize "
4846                                     "context page %d!\n", __FUNCTION__, i);
4847                                 rc = EBUSY;
4848                                 goto init_ctx_fail;
4849                         }
4850                 }
4851         } else {
4852
4853                 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n");
4854
4855                 /*
4856                  * For the 5706/5708, context memory is local to
4857                  * the controller, so initialize the controller
4858                  * context memory.
4859                  */
4860
4861                 vcid_addr = GET_CID_ADDR(96);
4862                 while (vcid_addr) {
4863
4864                         vcid_addr -= PHY_CTX_SIZE;
4865
4866                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4867                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4868
4869                         for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4870                                 CTX_WR(sc, 0x00, offset, 0);
4871                         }
4872
4873                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4874                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4875                 }
4876
4877         }
4878 init_ctx_fail:
4879         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4880         return (rc);
4881 }
4882
4883
4884 /****************************************************************************/
4885 /* Fetch the permanent MAC address of the controller.                       */
4886 /*                                                                          */
4887 /* Returns:                                                                 */
4888 /*   Nothing.                                                               */
4889 /****************************************************************************/
4890 static void
4891 bce_get_mac_addr(struct bce_softc *sc)
4892 {
4893         u32 mac_lo = 0, mac_hi = 0;
4894
4895         DBENTER(BCE_VERBOSE_RESET);
4896
4897         /*
4898          * The NetXtreme II bootcode populates various NIC
4899          * power-on and runtime configuration items in a
4900          * shared memory area.  The factory configured MAC
4901          * address is available from both NVRAM and the
4902          * shared memory area so we'll read the value from
4903          * shared memory for speed.
4904          */
4905
4906         mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
4907         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
4908
4909         if ((mac_lo == 0) && (mac_hi == 0)) {
4910                 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
4911                     __FILE__, __LINE__);
4912         } else {
4913                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4914                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4915                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
4916                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
4917                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
4918                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4919         }
4920
4921         DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet "
4922             "address = %6D\n", sc->eaddr, ":");
4923         DBEXIT(BCE_VERBOSE_RESET);
4924 }
4925
4926
4927 /****************************************************************************/
4928 /* Program the MAC address.                                                 */
4929 /*                                                                          */
4930 /* Returns:                                                                 */
4931 /*   Nothing.                                                               */
4932 /****************************************************************************/
4933 static void
4934 bce_set_mac_addr(struct bce_softc *sc)
4935 {
4936         u32 val;
4937         u8 *mac_addr = sc->eaddr;
4938
4939         /* ToDo: Add support for setting multiple MAC addresses. */
4940
4941         DBENTER(BCE_VERBOSE_RESET);
4942         DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = "
4943             "%6D\n", sc->eaddr, ":");
4944
4945         val = (mac_addr[0] << 8) | mac_addr[1];
4946
4947         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4948
4949         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4950             (mac_addr[4] << 8) | mac_addr[5];
4951
4952         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4953
4954         DBEXIT(BCE_VERBOSE_RESET);
4955 }
4956
4957
4958 /****************************************************************************/
4959 /* Stop the controller.                                                     */
4960 /*                                                                          */
4961 /* Returns:                                                                 */
4962 /*   Nothing.                                                               */
4963 /****************************************************************************/
4964 static void
4965 bce_stop(struct bce_softc *sc)
4966 {
4967         struct ifnet *ifp;
4968
4969         DBENTER(BCE_VERBOSE_RESET);
4970
4971         BCE_LOCK_ASSERT(sc);
4972
4973         ifp = sc->bce_ifp;
4974
4975         callout_stop(&sc->bce_tick_callout);
4976
4977         /* Disable the transmit/receive blocks. */
4978         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
4979         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4980         DELAY(20);
4981
4982         bce_disable_intr(sc);
4983
4984         /* Free RX buffers. */
4985         if (bce_hdr_split == TRUE) {
4986                 bce_free_pg_chain(sc);
4987         }
4988         bce_free_rx_chain(sc);
4989
4990         /* Free TX buffers. */
4991         bce_free_tx_chain(sc);
4992
4993         sc->watchdog_timer = 0;
4994
4995         sc->bce_link_up = FALSE;
4996
4997         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4998
4999         DBEXIT(BCE_VERBOSE_RESET);
5000 }
5001
5002
5003 static int
5004 bce_reset(struct bce_softc *sc, u32 reset_code)
5005 {
5006         u32 emac_mode_save, val;
5007         int i, rc = 0;
5008         static const u32 emac_mode_mask = BCE_EMAC_MODE_PORT |
5009             BCE_EMAC_MODE_HALF_DUPLEX | BCE_EMAC_MODE_25G;
5010
5011         DBENTER(BCE_VERBOSE_RESET);
5012
5013         DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
5014             __FUNCTION__, reset_code);
5015
5016         /*
5017          * If ASF/IPMI is operational, then the EMAC Mode register already
5018          * contains appropriate values for the link settings that have
5019          * been auto-negotiated.  Resetting the chip will clobber those
5020          * values.  Save the important bits so we can restore them after
5021          * the reset.
5022          */
5023         emac_mode_save = REG_RD(sc, BCE_EMAC_MODE) & emac_mode_mask;
5024
5025         /* Wait for pending PCI transactions to complete. */
5026         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
5027             BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
5028             BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
5029             BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
5030             BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
5031         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
5032         DELAY(5);
5033
5034         /* Disable DMA */
5035         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5036                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5037                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5038                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5039         }
5040
5041         /* Assume bootcode is running. */
5042         sc->bce_fw_timed_out = FALSE;
5043         sc->bce_drv_cardiac_arrest = FALSE;
5044
5045         /* Give the firmware a chance to prepare for the reset. */
5046         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
5047         if (rc)
5048                 goto bce_reset_exit;
5049
5050         /* Set a firmware reminder that this is a soft reset. */
5051         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC);
5052
5053         /* Dummy read to force the chip to complete all current transactions. */
5054         val = REG_RD(sc, BCE_MISC_ID);
5055
5056         /* Chip reset. */
5057         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5058                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
5059                 REG_RD(sc, BCE_MISC_COMMAND);
5060                 DELAY(5);
5061
5062                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5063                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5064
5065                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
5066         } else {
5067                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5068                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
5069                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
5070                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
5071
5072                 /* Allow up to 30us for reset to complete. */
5073                 for (i = 0; i < 10; i++) {
5074                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
5075                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5076                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
5077                                 break;
5078                         }
5079                         DELAY(10);
5080                 }
5081
5082                 /* Check that reset completed successfully. */
5083                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
5084                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
5085                         BCE_PRINTF("%s(%d): Reset failed!\n",
5086                             __FILE__, __LINE__);
5087                         rc = EBUSY;
5088                         goto bce_reset_exit;
5089                 }
5090         }
5091
5092         /* Make sure byte swapping is properly configured. */
5093         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
5094         if (val != 0x01020304) {
5095                 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
5096                     __FILE__, __LINE__);
5097                 rc = ENODEV;
5098                 goto bce_reset_exit;
5099         }
5100
5101         /* Just completed a reset, assume that firmware is running again. */
5102         sc->bce_fw_timed_out = FALSE;
5103         sc->bce_drv_cardiac_arrest = FALSE;
5104
5105         /* Wait for the firmware to finish its initialization. */
5106         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
5107         if (rc)
5108                 BCE_PRINTF("%s(%d): Firmware did not complete "
5109                     "initialization!\n", __FILE__, __LINE__);
5110         /* Get firmware capabilities. */
5111         bce_fw_cap_init(sc);
5112
5113 bce_reset_exit:
5114         /* Restore EMAC Mode bits needed to keep ASF/IPMI running. */
5115         val = REG_RD(sc, BCE_EMAC_MODE);
5116         val = (val & ~emac_mode_mask) | emac_mode_save;
5117         REG_WR(sc, BCE_EMAC_MODE, val);
5118
5119         DBEXIT(BCE_VERBOSE_RESET);
5120         return (rc);
5121 }
5122
5123
5124 static int
5125 bce_chipinit(struct bce_softc *sc)
5126 {
5127         u32 val;
5128         int rc = 0;
5129
5130         DBENTER(BCE_VERBOSE_RESET);
5131
5132         bce_disable_intr(sc);
5133
5134         /*
5135          * Initialize DMA byte/word swapping, configure the number of DMA
5136          * channels and PCI clock compensation delay.
5137          */
5138         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
5139             BCE_DMA_CONFIG_DATA_WORD_SWAP |
5140 #if BYTE_ORDER == BIG_ENDIAN
5141             BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
5142 #endif
5143             BCE_DMA_CONFIG_CNTL_WORD_SWAP |
5144             DMA_READ_CHANS << 12 |
5145             DMA_WRITE_CHANS << 16;
5146
5147         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
5148
5149         if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
5150                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
5151
5152         /*
5153          * This setting resolves a problem observed on certain Intel PCI
5154          * chipsets that cannot handle multiple outstanding DMA operations.
5155          * See errata E9_5706A1_65.
5156          */
5157         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
5158             (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
5159             !(sc->bce_flags & BCE_PCIX_FLAG))
5160                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
5161
5162         REG_WR(sc, BCE_DMA_CONFIG, val);
5163
5164         /* Enable the RX_V2P and Context state machines before access. */
5165         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5166             BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
5167             BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
5168             BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
5169
5170         /* Initialize context mapping and zero out the quick contexts. */
5171         if ((rc = bce_init_ctx(sc)) != 0)
5172                 goto bce_chipinit_exit;
5173
5174         /* Initialize the on-boards CPUs */
5175         bce_init_cpus(sc);
5176
5177         /* Enable management frames (NC-SI) to flow to the MCP. */
5178         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5179                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5180                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5181         }
5182
5183         /* Prepare NVRAM for access. */
5184         if ((rc = bce_init_nvram(sc)) != 0)
5185                 goto bce_chipinit_exit;
5186
5187         /* Set the kernel bypass block size */
5188         val = REG_RD(sc, BCE_MQ_CONFIG);
5189         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
5190         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
5191
5192         /* Enable bins used on the 5709. */
5193         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5194                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
5195                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
5196                         val |= BCE_MQ_CONFIG_HALT_DIS;
5197         }
5198
5199         REG_WR(sc, BCE_MQ_CONFIG, val);
5200
5201         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
5202         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
5203         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
5204
5205         /* Set the page size and clear the RV2P processor stall bits. */
5206         val = (BCM_PAGE_BITS - 8) << 24;
5207         REG_WR(sc, BCE_RV2P_CONFIG, val);
5208
5209         /* Configure page size. */
5210         val = REG_RD(sc, BCE_TBDR_CONFIG);
5211         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
5212         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
5213         REG_WR(sc, BCE_TBDR_CONFIG, val);
5214
5215         /* Set the perfect match control register to default. */
5216         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
5217
5218 bce_chipinit_exit:
5219         DBEXIT(BCE_VERBOSE_RESET);
5220
5221         return(rc);
5222 }
5223
5224
5225 /****************************************************************************/
5226 /* Initialize the controller in preparation to send/receive traffic.        */
5227 /*                                                                          */
5228 /* Returns:                                                                 */
5229 /*   0 for success, positive value for failure.                             */
5230 /****************************************************************************/
5231 static int
5232 bce_blockinit(struct bce_softc *sc)
5233 {
5234         u32 reg, val;
5235         int rc = 0;
5236
5237         DBENTER(BCE_VERBOSE_RESET);
5238
5239         /* Load the hardware default MAC address. */
5240         bce_set_mac_addr(sc);
5241
5242         /* Set the Ethernet backoff seed value */
5243         val = sc->eaddr[0]         + (sc->eaddr[1] << 8) +
5244               (sc->eaddr[2] << 16) + (sc->eaddr[3]     ) +
5245               (sc->eaddr[4] << 8)  + (sc->eaddr[5] << 16);
5246         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
5247
5248         sc->last_status_idx = 0;
5249         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
5250
5251         /* Set up link change interrupt generation. */
5252         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
5253
5254         /* Program the physical address of the status block. */
5255         REG_WR(sc, BCE_HC_STATUS_ADDR_L,
5256             BCE_ADDR_LO(sc->status_block_paddr));
5257         REG_WR(sc, BCE_HC_STATUS_ADDR_H,
5258             BCE_ADDR_HI(sc->status_block_paddr));
5259
5260         /* Program the physical address of the statistics block. */
5261         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
5262             BCE_ADDR_LO(sc->stats_block_paddr));
5263         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
5264             BCE_ADDR_HI(sc->stats_block_paddr));
5265
5266         /* Program various host coalescing parameters. */
5267         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
5268             (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip);
5269         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
5270             (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip);
5271         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
5272             (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
5273         REG_WR(sc, BCE_HC_TX_TICKS,
5274             (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
5275         REG_WR(sc, BCE_HC_RX_TICKS,
5276             (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
5277         REG_WR(sc, BCE_HC_COM_TICKS,
5278             (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
5279         REG_WR(sc, BCE_HC_CMD_TICKS,
5280             (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
5281         REG_WR(sc, BCE_HC_STATS_TICKS,
5282             (sc->bce_stats_ticks & 0xffff00));
5283         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
5284
5285         /* Configure the Host Coalescing block. */
5286         val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
5287             BCE_HC_CONFIG_COLLECT_STATS;
5288
5289 #if 0
5290         /* ToDo: Add MSI-X support. */
5291         if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
5292                 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
5293                     BCE_HC_SB_CONFIG_1;
5294
5295                 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
5296
5297                 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
5298                     BCE_HC_SB_CONFIG_1_ONE_SHOT);
5299
5300                 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
5301                     (sc->tx_quick_cons_trip_int << 16) |
5302                      sc->tx_quick_cons_trip);
5303
5304                 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
5305                     (sc->tx_ticks_int << 16) | sc->tx_ticks);
5306
5307                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5308         }
5309
5310         /*
5311          * Tell the HC block to automatically set the
5312          * INT_MASK bit after an MSI/MSI-X interrupt
5313          * is generated so the driver doesn't have to.
5314          */
5315         if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
5316                 val |= BCE_HC_CONFIG_ONE_SHOT;
5317
5318         /* Set the MSI-X status blocks to 128 byte boundaries. */
5319         if (sc->bce_flags & BCE_USING_MSIX_FLAG)
5320                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
5321 #endif
5322
5323         REG_WR(sc, BCE_HC_CONFIG, val);
5324
5325         /* Clear the internal statistics counters. */
5326         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
5327
5328         /* Verify that bootcode is running. */
5329         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
5330
5331         DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control),
5332             BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
5333             __FILE__, __LINE__);
5334             reg = 0);
5335
5336         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
5337             BCE_DEV_INFO_SIGNATURE_MAGIC) {
5338                 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
5339                     "Expected: 08%08X\n", __FILE__, __LINE__,
5340                     (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
5341                     BCE_DEV_INFO_SIGNATURE_MAGIC);
5342                 rc = ENODEV;
5343                 goto bce_blockinit_exit;
5344         }
5345
5346         /* Enable DMA */
5347         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5348                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
5349                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
5350                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
5351         }
5352
5353         /* Allow bootcode to apply additional fixes before enabling MAC. */
5354         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 |
5355             BCE_DRV_MSG_CODE_RESET);
5356
5357         /* Enable link state change interrupt generation. */
5358         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
5359
5360         /* Enable the RXP. */
5361         bce_start_rxp_cpu(sc);
5362
5363         /* Disable management frames (NC-SI) from flowing to the MCP. */
5364         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
5365                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
5366                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
5367                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
5368         }
5369
5370         /* Enable all remaining blocks in the MAC. */
5371         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
5372                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5373                     BCE_MISC_ENABLE_DEFAULT_XI);
5374         else
5375                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
5376                     BCE_MISC_ENABLE_DEFAULT);
5377
5378         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
5379         DELAY(20);
5380
5381         /* Save the current host coalescing block settings. */
5382         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
5383
5384 bce_blockinit_exit:
5385         DBEXIT(BCE_VERBOSE_RESET);
5386
5387         return (rc);
5388 }
5389
5390
5391 /****************************************************************************/
5392 /* Encapsulate an mbuf into the rx_bd chain.                                */
5393 /*                                                                          */
5394 /* Returns:                                                                 */
5395 /*   0 for success, positive value for failure.                             */
5396 /****************************************************************************/
5397 static int
5398 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod,
5399     u16 *chain_prod, u32 *prod_bseq)
5400 {
5401         bus_dmamap_t map;
5402         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
5403         struct mbuf *m_new = NULL;
5404         struct rx_bd *rxbd;
5405         int nsegs, error, rc = 0;
5406 #ifdef BCE_DEBUG
5407         u16 debug_chain_prod = *chain_prod;
5408 #endif
5409
5410         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5411
5412         /* Make sure the inputs are valid. */
5413         DBRUNIF((*chain_prod > MAX_RX_BD_ALLOC),
5414             BCE_PRINTF("%s(%d): RX producer out of range: "
5415             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5416             *chain_prod, (u16) MAX_RX_BD_ALLOC));
5417
5418         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5419             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__,
5420             *prod, *chain_prod, *prod_bseq);
5421
5422         /* Update some debug statistic counters */
5423         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5424             sc->rx_low_watermark = sc->free_rx_bd);
5425         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
5426             sc->rx_empty_count++);
5427
5428         /* Check whether this is a new mbuf allocation. */
5429         if (m == NULL) {
5430
5431                 /* Simulate an mbuf allocation failure. */
5432                 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5433                     sc->mbuf_alloc_failed_count++;
5434                     sc->mbuf_alloc_failed_sim_count++;
5435                     rc = ENOBUFS;
5436                     goto bce_get_rx_buf_exit);
5437
5438                 /* This is a new mbuf allocation. */
5439                 if (bce_hdr_split == TRUE)
5440                         MGETHDR(m_new, M_DONTWAIT, MT_DATA);
5441                 else
5442                         m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR,
5443                             sc->rx_bd_mbuf_alloc_size);
5444
5445                 if (m_new == NULL) {
5446                         sc->mbuf_alloc_failed_count++;
5447                         rc = ENOBUFS;
5448                         goto bce_get_rx_buf_exit;
5449                 }
5450
5451                 DBRUN(sc->debug_rx_mbuf_alloc++);
5452         } else {
5453                 /* Reuse an existing mbuf. */
5454                 m_new = m;
5455         }
5456
5457         /* Make sure we have a valid packet header. */
5458         M_ASSERTPKTHDR(m_new);
5459
5460         /* Initialize the mbuf size and pad if necessary for alignment. */
5461         m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size;
5462         m_adj(m_new, sc->rx_bd_mbuf_align_pad);
5463
5464         /* ToDo: Consider calling m_fragment() to test error handling. */
5465
5466         /* Map the mbuf cluster into device memory. */
5467         map = sc->rx_mbuf_map[*chain_prod];
5468         error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new,
5469             segs, &nsegs, BUS_DMA_NOWAIT);
5470
5471         /* Handle any mapping errors. */
5472         if (error) {
5473                 BCE_PRINTF("%s(%d): Error mapping mbuf into RX "
5474                     "chain (%d)!\n", __FILE__, __LINE__, error);
5475
5476                 sc->dma_map_addr_rx_failed_count++;
5477                 m_freem(m_new);
5478
5479                 DBRUN(sc->debug_rx_mbuf_alloc--);
5480
5481                 rc = ENOBUFS;
5482                 goto bce_get_rx_buf_exit;
5483         }
5484
5485         /* All mbufs must map to a single segment. */
5486         KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5487             __FUNCTION__, nsegs));
5488
5489         /* Setup the rx_bd for the segment. */
5490         rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
5491
5492         rxbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5493         rxbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5494         rxbd->rx_bd_len       = htole32(segs[0].ds_len);
5495         rxbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5496         *prod_bseq += segs[0].ds_len;
5497
5498         /* Save the mbuf and update our counter. */
5499         sc->rx_mbuf_ptr[*chain_prod] = m_new;
5500         sc->free_rx_bd -= nsegs;
5501
5502         DBRUNMSG(BCE_INSANE_RECV,
5503             bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs));
5504
5505         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5506             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n",
5507             __FUNCTION__, *prod, *chain_prod, *prod_bseq);
5508
5509 bce_get_rx_buf_exit:
5510         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5511
5512         return(rc);
5513 }
5514
5515
5516 /****************************************************************************/
5517 /* Encapsulate an mbuf cluster into the page chain.                         */
5518 /*                                                                          */
5519 /* Returns:                                                                 */
5520 /*   0 for success, positive value for failure.                             */
5521 /****************************************************************************/
5522 static int
5523 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod,
5524         u16 *prod_idx)
5525 {
5526         bus_dmamap_t map;
5527         bus_addr_t busaddr;
5528         struct mbuf *m_new = NULL;
5529         struct rx_bd *pgbd;
5530         int error, rc = 0;
5531 #ifdef BCE_DEBUG
5532         u16 debug_prod_idx = *prod_idx;
5533 #endif
5534
5535         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5536
5537         /* Make sure the inputs are valid. */
5538         DBRUNIF((*prod_idx > MAX_PG_BD_ALLOC),
5539             BCE_PRINTF("%s(%d): page producer out of range: "
5540             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5541             *prod_idx, (u16) MAX_PG_BD_ALLOC));
5542
5543         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5544             "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
5545
5546         /* Update counters if we've hit a new low or run out of pages. */
5547         DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
5548             sc->pg_low_watermark = sc->free_pg_bd);
5549         DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
5550
5551         /* Check whether this is a new mbuf allocation. */
5552         if (m == NULL) {
5553
5554                 /* Simulate an mbuf allocation failure. */
5555                 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5556                     sc->mbuf_alloc_failed_count++;
5557                     sc->mbuf_alloc_failed_sim_count++;
5558                     rc = ENOBUFS;
5559                     goto bce_get_pg_buf_exit);
5560
5561                 /* This is a new mbuf allocation. */
5562                 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0);
5563                 if (m_new == NULL) {
5564                         sc->mbuf_alloc_failed_count++;
5565                         rc = ENOBUFS;
5566                         goto bce_get_pg_buf_exit;
5567                 }
5568
5569                 DBRUN(sc->debug_pg_mbuf_alloc++);
5570         } else {
5571                 /* Reuse an existing mbuf. */
5572                 m_new = m;
5573                 m_new->m_data = m_new->m_ext.ext_buf;
5574         }
5575
5576         m_new->m_len = sc->pg_bd_mbuf_alloc_size;
5577
5578         /* ToDo: Consider calling m_fragment() to test error handling. */
5579
5580         /* Map the mbuf cluster into device memory. */
5581         map = sc->pg_mbuf_map[*prod_idx];
5582         error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *),
5583             sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr,
5584             &busaddr, BUS_DMA_NOWAIT);
5585
5586         /* Handle any mapping errors. */
5587         if (error) {
5588                 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
5589                     __FILE__, __LINE__);
5590
5591                 m_freem(m_new);
5592                 DBRUN(sc->debug_pg_mbuf_alloc--);
5593
5594                 rc = ENOBUFS;
5595                 goto bce_get_pg_buf_exit;
5596         }
5597
5598         /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */
5599
5600         /*
5601          * The page chain uses the same rx_bd data structure
5602          * as the receive chain but doesn't require a byte sequence (bseq).
5603          */
5604         pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)];
5605
5606         pgbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(busaddr));
5607         pgbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(busaddr));
5608         pgbd->rx_bd_len       = htole32(sc->pg_bd_mbuf_alloc_size);
5609         pgbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5610
5611         /* Save the mbuf and update our counter. */
5612         sc->pg_mbuf_ptr[*prod_idx] = m_new;
5613         sc->free_pg_bd--;
5614
5615         DBRUNMSG(BCE_INSANE_RECV,
5616             bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1));
5617
5618         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5619             "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
5620
5621 bce_get_pg_buf_exit:
5622         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5623
5624         return(rc);
5625 }
5626
5627
5628 /****************************************************************************/
5629 /* Initialize the TX context memory.                                        */
5630 /*                                                                          */
5631 /* Returns:                                                                 */
5632 /*   Nothing                                                                */
5633 /****************************************************************************/
5634 static void
5635 bce_init_tx_context(struct bce_softc *sc)
5636 {
5637         u32 val;
5638
5639         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5640
5641         /* Initialize the context ID for an L2 TX chain. */
5642         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5643                 /* Set the CID type to support an L2 connection. */
5644                 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI |
5645                     BCE_L2CTX_TX_TYPE_SIZE_L2_XI;
5646                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
5647                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16);
5648                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5649                     BCE_L2CTX_TX_CMD_TYPE_XI, val);
5650
5651                 /* Point the hardware to the first page in the chain. */
5652                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5653                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5654                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
5655                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5656                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5657                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
5658         } else {
5659                 /* Set the CID type to support an L2 connection. */
5660                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
5661                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
5662                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
5663                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
5664
5665                 /* Point the hardware to the first page in the chain. */
5666                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5667                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5668                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
5669                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5670                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5671                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
5672         }
5673
5674         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5675 }
5676
5677
5678 /****************************************************************************/
5679 /* Allocate memory and initialize the TX data structures.                   */
5680 /*                                                                          */
5681 /* Returns:                                                                 */
5682 /*   0 for success, positive value for failure.                             */
5683 /****************************************************************************/
5684 static int
5685 bce_init_tx_chain(struct bce_softc *sc)
5686 {
5687         struct tx_bd *txbd;
5688         int i, rc = 0;
5689
5690         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5691
5692         /* Set the initial TX producer/consumer indices. */
5693         sc->tx_prod        = 0;
5694         sc->tx_cons        = 0;
5695         sc->tx_prod_bseq   = 0;
5696         sc->used_tx_bd     = 0;
5697         sc->max_tx_bd      = USABLE_TX_BD_ALLOC;
5698         DBRUN(sc->tx_hi_watermark = 0);
5699         DBRUN(sc->tx_full_count = 0);
5700
5701         /*
5702          * The NetXtreme II supports a linked-list structre called
5703          * a Buffer Descriptor Chain (or BD chain).  A BD chain
5704          * consists of a series of 1 or more chain pages, each of which
5705          * consists of a fixed number of BD entries.
5706          * The last BD entry on each page is a pointer to the next page
5707          * in the chain, and the last pointer in the BD chain
5708          * points back to the beginning of the chain.
5709          */
5710
5711         /* Set the TX next pointer chain entries. */
5712         for (i = 0; i < sc->tx_pages; i++) {
5713                 int j;
5714
5715                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
5716
5717                 /* Check if we've reached the last page. */
5718                 if (i == (sc->tx_pages - 1))
5719                         j = 0;
5720                 else
5721                         j = i + 1;
5722
5723                 txbd->tx_bd_haddr_hi =
5724                     htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5725                 txbd->tx_bd_haddr_lo =
5726                     htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5727         }
5728
5729         bce_init_tx_context(sc);
5730
5731         DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC));
5732         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5733
5734         return(rc);
5735 }
5736
5737
5738 /****************************************************************************/
5739 /* Free memory and clear the TX data structures.                            */
5740 /*                                                                          */
5741 /* Returns:                                                                 */
5742 /*   Nothing.                                                               */
5743 /****************************************************************************/
5744 static void
5745 bce_free_tx_chain(struct bce_softc *sc)
5746 {
5747         int i;
5748
5749         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5750
5751         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
5752         for (i = 0; i < MAX_TX_BD_AVAIL; i++) {
5753                 if (sc->tx_mbuf_ptr[i] != NULL) {
5754                         if (sc->tx_mbuf_map[i] != NULL)
5755                                 bus_dmamap_sync(sc->tx_mbuf_tag,
5756                                     sc->tx_mbuf_map[i],
5757                                     BUS_DMASYNC_POSTWRITE);
5758                         m_freem(sc->tx_mbuf_ptr[i]);
5759                         sc->tx_mbuf_ptr[i] = NULL;
5760                         DBRUN(sc->debug_tx_mbuf_alloc--);
5761                 }
5762         }
5763
5764         /* Clear each TX chain page. */
5765         for (i = 0; i < sc->tx_pages; i++)
5766                 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5767
5768         sc->used_tx_bd = 0;
5769
5770         /* Check if we lost any mbufs in the process. */
5771         DBRUNIF((sc->debug_tx_mbuf_alloc),
5772             BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
5773             "from tx chain!\n", __FILE__, __LINE__,
5774             sc->debug_tx_mbuf_alloc));
5775
5776         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5777 }
5778
5779
5780 /****************************************************************************/
5781 /* Initialize the RX context memory.                                        */
5782 /*                                                                          */
5783 /* Returns:                                                                 */
5784 /*   Nothing                                                                */
5785 /****************************************************************************/
5786 static void
5787 bce_init_rx_context(struct bce_softc *sc)
5788 {
5789         u32 val;
5790
5791         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5792
5793         /* Init the type, size, and BD cache levels for the RX context. */
5794         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5795             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 |
5796             (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT);
5797
5798         /*
5799          * Set the level for generating pause frames
5800          * when the number of available rx_bd's gets
5801          * too low (the low watermark) and the level
5802          * when pause frames can be stopped (the high
5803          * watermark).
5804          */
5805         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5806                 u32 lo_water, hi_water;
5807
5808                 if (sc->bce_flags & BCE_USING_TX_FLOW_CONTROL) {
5809                         lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
5810                 } else {
5811                         lo_water = 0;
5812                 }
5813
5814                 if (lo_water >= USABLE_RX_BD_ALLOC) {
5815                         lo_water = 0;
5816                 }
5817
5818                 hi_water = USABLE_RX_BD_ALLOC / 4;
5819
5820                 if (hi_water <= lo_water) {
5821                         lo_water = 0;
5822                 }
5823
5824                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
5825                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
5826
5827                 if (hi_water > 0xf)
5828                         hi_water = 0xf;
5829                 else if (hi_water == 0)
5830                         lo_water = 0;
5831
5832                 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) |
5833                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
5834         }
5835
5836         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
5837
5838         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
5839         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
5840                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5841                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5842         }
5843
5844         /* Point the hardware to the first page in the chain. */
5845         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5846         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
5847         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5848         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
5849
5850         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5851 }
5852
5853
5854 /****************************************************************************/
5855 /* Allocate memory and initialize the RX data structures.                   */
5856 /*                                                                          */
5857 /* Returns:                                                                 */
5858 /*   0 for success, positive value for failure.                             */
5859 /****************************************************************************/
5860 static int
5861 bce_init_rx_chain(struct bce_softc *sc)
5862 {
5863         struct rx_bd *rxbd;
5864         int i, rc = 0;
5865
5866         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5867             BCE_VERBOSE_CTX);
5868
5869         /* Initialize the RX producer and consumer indices. */
5870         sc->rx_prod        = 0;
5871         sc->rx_cons        = 0;
5872         sc->rx_prod_bseq   = 0;
5873         sc->free_rx_bd     = USABLE_RX_BD_ALLOC;
5874         sc->max_rx_bd      = USABLE_RX_BD_ALLOC;
5875
5876         /* Initialize the RX next pointer chain entries. */
5877         for (i = 0; i < sc->rx_pages; i++) {
5878                 int j;
5879
5880                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
5881
5882                 /* Check if we've reached the last page. */
5883                 if (i == (sc->rx_pages - 1))
5884                         j = 0;
5885                 else
5886                         j = i + 1;
5887
5888                 /* Setup the chain page pointers. */
5889                 rxbd->rx_bd_haddr_hi =
5890                     htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5891                 rxbd->rx_bd_haddr_lo =
5892                     htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5893         }
5894
5895         /* Fill up the RX chain. */
5896         bce_fill_rx_chain(sc);
5897
5898         DBRUN(sc->rx_low_watermark = USABLE_RX_BD_ALLOC);
5899         DBRUN(sc->rx_empty_count = 0);
5900         for (i = 0; i < sc->rx_pages; i++) {
5901                 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
5902                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5903         }
5904
5905         bce_init_rx_context(sc);
5906
5907         DBRUNMSG(BCE_EXTREME_RECV,
5908             bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC));
5909         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5910             BCE_VERBOSE_CTX);
5911
5912         /* ToDo: Are there possible failure modes here? */
5913
5914         return(rc);
5915 }
5916
5917
5918 /****************************************************************************/
5919 /* Add mbufs to the RX chain until its full or an mbuf allocation error     */
5920 /* occurs.                                                                  */
5921 /*                                                                          */
5922 /* Returns:                                                                 */
5923 /*   Nothing                                                                */
5924 /****************************************************************************/
5925 static void
5926 bce_fill_rx_chain(struct bce_softc *sc)
5927 {
5928         u16 prod, prod_idx;
5929         u32 prod_bseq;
5930
5931         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5932             BCE_VERBOSE_CTX);
5933
5934         /* Get the RX chain producer indices. */
5935         prod      = sc->rx_prod;
5936         prod_bseq = sc->rx_prod_bseq;
5937
5938         /* Keep filling the RX chain until it's full. */
5939         while (sc->free_rx_bd > 0) {
5940                 prod_idx = RX_CHAIN_IDX(prod);
5941                 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) {
5942                         /* Bail out if we can't add an mbuf to the chain. */
5943                         break;
5944                 }
5945                 prod = NEXT_RX_BD(prod);
5946         }
5947
5948         /* Save the RX chain producer indices. */
5949         sc->rx_prod      = prod;
5950         sc->rx_prod_bseq = prod_bseq;
5951
5952         /* We should never end up pointing to a next page pointer. */
5953         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5954             BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5955             __FUNCTION__, sc->rx_prod));
5956
5957         /* Write the mailbox and tell the chip about the waiting rx_bd's. */
5958         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) +
5959             BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod);
5960         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) +
5961             BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq);
5962
5963         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5964             BCE_VERBOSE_CTX);
5965 }
5966
5967
5968 /****************************************************************************/
5969 /* Free memory and clear the RX data structures.                            */
5970 /*                                                                          */
5971 /* Returns:                                                                 */
5972 /*   Nothing.                                                               */
5973 /****************************************************************************/
5974 static void
5975 bce_free_rx_chain(struct bce_softc *sc)
5976 {
5977         int i;
5978
5979         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5980
5981         /* Free any mbufs still in the RX mbuf chain. */
5982         for (i = 0; i < MAX_RX_BD_AVAIL; i++) {
5983                 if (sc->rx_mbuf_ptr[i] != NULL) {
5984                         if (sc->rx_mbuf_map[i] != NULL)
5985                                 bus_dmamap_sync(sc->rx_mbuf_tag,
5986                                     sc->rx_mbuf_map[i],
5987                                     BUS_DMASYNC_POSTREAD);
5988                         m_freem(sc->rx_mbuf_ptr[i]);
5989                         sc->rx_mbuf_ptr[i] = NULL;
5990                         DBRUN(sc->debug_rx_mbuf_alloc--);
5991                 }
5992         }
5993
5994         /* Clear each RX chain page. */
5995         for (i = 0; i < sc->rx_pages; i++)
5996                 if (sc->rx_bd_chain[i] != NULL) {
5997                         bzero((char *)sc->rx_bd_chain[i],
5998                             BCE_RX_CHAIN_PAGE_SZ);
5999                 }
6000
6001         sc->free_rx_bd = sc->max_rx_bd;
6002
6003         /* Check if we lost any mbufs in the process. */
6004         DBRUNIF((sc->debug_rx_mbuf_alloc),
6005             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
6006             __FUNCTION__, sc->debug_rx_mbuf_alloc));
6007
6008         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6009 }
6010
6011
6012 /****************************************************************************/
6013 /* Allocate memory and initialize the page data structures.                 */
6014 /* Assumes that bce_init_rx_chain() has not already been called.            */
6015 /*                                                                          */
6016 /* Returns:                                                                 */
6017 /*   0 for success, positive value for failure.                             */
6018 /****************************************************************************/
6019 static int
6020 bce_init_pg_chain(struct bce_softc *sc)
6021 {
6022         struct rx_bd *pgbd;
6023         int i, rc = 0;
6024         u32 val;
6025
6026         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
6027                 BCE_VERBOSE_CTX);
6028
6029         /* Initialize the page producer and consumer indices. */
6030         sc->pg_prod        = 0;
6031         sc->pg_cons        = 0;
6032         sc->free_pg_bd     = USABLE_PG_BD_ALLOC;
6033         sc->max_pg_bd      = USABLE_PG_BD_ALLOC;
6034         DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
6035         DBRUN(sc->pg_empty_count = 0);
6036
6037         /* Initialize the page next pointer chain entries. */
6038         for (i = 0; i < sc->pg_pages; i++) {
6039                 int j;
6040
6041                 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE];
6042
6043                 /* Check if we've reached the last page. */
6044                 if (i == (sc->pg_pages - 1))
6045                         j = 0;
6046                 else
6047                         j = i + 1;
6048
6049                 /* Setup the chain page pointers. */
6050                 pgbd->rx_bd_haddr_hi =
6051                     htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
6052                 pgbd->rx_bd_haddr_lo =
6053                     htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
6054         }
6055
6056         /* Setup the MQ BIN mapping for host_pg_bidx. */
6057         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
6058                 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
6059
6060         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
6061
6062         /* Configure the rx_bd and page chain mbuf cluster size. */
6063         val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size;
6064         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
6065
6066         /* Configure the context reserved for jumbo support. */
6067         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
6068                 BCE_L2CTX_RX_RBDC_JUMBO_KEY);
6069
6070         /* Point the hardware to the first page in the page chain. */
6071         val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
6072         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val);
6073         val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
6074         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val);
6075
6076         /* Fill up the page chain. */
6077         bce_fill_pg_chain(sc);
6078
6079         for (i = 0; i < sc->pg_pages; i++) {
6080                 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i],
6081                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
6082         }
6083
6084         DBRUNMSG(BCE_EXTREME_RECV,
6085             bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC));
6086         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
6087                 BCE_VERBOSE_CTX);
6088         return(rc);
6089 }
6090
6091
6092 /****************************************************************************/
6093 /* Add mbufs to the page chain until its full or an mbuf allocation error   */
6094 /* occurs.                                                                  */
6095 /*                                                                          */
6096 /* Returns:                                                                 */
6097 /*   Nothing                                                                */
6098 /****************************************************************************/
6099 static void
6100 bce_fill_pg_chain(struct bce_softc *sc)
6101 {
6102         u16 prod, prod_idx;
6103
6104         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6105             BCE_VERBOSE_CTX);
6106
6107         /* Get the page chain prodcuer index. */
6108         prod = sc->pg_prod;
6109
6110         /* Keep filling the page chain until it's full. */
6111         while (sc->free_pg_bd > 0) {
6112                 prod_idx = PG_CHAIN_IDX(prod);
6113                 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) {
6114                         /* Bail out if we can't add an mbuf to the chain. */
6115                         break;
6116                 }
6117                 prod = NEXT_PG_BD(prod);
6118         }
6119
6120         /* Save the page chain producer index. */
6121         sc->pg_prod = prod;
6122
6123         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
6124             BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
6125             __FUNCTION__, sc->pg_prod));
6126
6127         /*
6128          * Write the mailbox and tell the chip about
6129          * the new rx_bd's in the page chain.
6130          */
6131         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) +
6132             BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod);
6133
6134         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
6135             BCE_VERBOSE_CTX);
6136 }
6137
6138
6139 /****************************************************************************/
6140 /* Free memory and clear the RX data structures.                            */
6141 /*                                                                          */
6142 /* Returns:                                                                 */
6143 /*   Nothing.                                                               */
6144 /****************************************************************************/
6145 static void
6146 bce_free_pg_chain(struct bce_softc *sc)
6147 {
6148         int i;
6149
6150         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6151
6152         /* Free any mbufs still in the mbuf page chain. */
6153         for (i = 0; i < MAX_PG_BD_AVAIL; i++) {
6154                 if (sc->pg_mbuf_ptr[i] != NULL) {
6155                         if (sc->pg_mbuf_map[i] != NULL)
6156                                 bus_dmamap_sync(sc->pg_mbuf_tag,
6157                                     sc->pg_mbuf_map[i],
6158                                     BUS_DMASYNC_POSTREAD);
6159                         m_freem(sc->pg_mbuf_ptr[i]);
6160                         sc->pg_mbuf_ptr[i] = NULL;
6161                         DBRUN(sc->debug_pg_mbuf_alloc--);
6162                 }
6163         }
6164
6165         /* Clear each page chain pages. */
6166         for (i = 0; i < sc->pg_pages; i++)
6167                 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
6168
6169         sc->free_pg_bd = sc->max_pg_bd;
6170
6171         /* Check if we lost any mbufs in the process. */
6172         DBRUNIF((sc->debug_pg_mbuf_alloc),
6173             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
6174             __FUNCTION__, sc->debug_pg_mbuf_alloc));
6175
6176         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
6177 }
6178
6179
6180 static u32
6181 bce_get_rphy_link(struct bce_softc *sc)
6182 {
6183         u32 advertise, link;
6184         int fdpx;
6185
6186         advertise = 0;
6187         fdpx = 0;
6188         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) != 0)
6189                 link = bce_shmem_rd(sc, BCE_RPHY_SERDES_LINK);
6190         else
6191                 link = bce_shmem_rd(sc, BCE_RPHY_COPPER_LINK);
6192         if (link & BCE_NETLINK_ANEG_ENB)
6193                 advertise |= BCE_NETLINK_ANEG_ENB;
6194         if (link & BCE_NETLINK_SPEED_10HALF)
6195                 advertise |= BCE_NETLINK_SPEED_10HALF;
6196         if (link & BCE_NETLINK_SPEED_10FULL) {
6197                 advertise |= BCE_NETLINK_SPEED_10FULL;
6198                 fdpx++;
6199         }
6200         if (link & BCE_NETLINK_SPEED_100HALF)
6201                 advertise |= BCE_NETLINK_SPEED_100HALF;
6202         if (link & BCE_NETLINK_SPEED_100FULL) {
6203                 advertise |= BCE_NETLINK_SPEED_100FULL;
6204                 fdpx++;
6205         }
6206         if (link & BCE_NETLINK_SPEED_1000HALF)
6207                 advertise |= BCE_NETLINK_SPEED_1000HALF;
6208         if (link & BCE_NETLINK_SPEED_1000FULL) {
6209                 advertise |= BCE_NETLINK_SPEED_1000FULL;
6210                 fdpx++;
6211         }
6212         if (link & BCE_NETLINK_SPEED_2500HALF)
6213                 advertise |= BCE_NETLINK_SPEED_2500HALF;
6214         if (link & BCE_NETLINK_SPEED_2500FULL) {
6215                 advertise |= BCE_NETLINK_SPEED_2500FULL;
6216                 fdpx++;
6217         }
6218         if (fdpx)
6219                 advertise |= BCE_NETLINK_FC_PAUSE_SYM |
6220                     BCE_NETLINK_FC_PAUSE_ASYM;
6221         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6222                 advertise |= BCE_NETLINK_PHY_APP_REMOTE |
6223                     BCE_NETLINK_ETH_AT_WIRESPEED;
6224
6225         return (advertise);
6226 }
6227
6228
6229 /****************************************************************************/
6230 /* Set media options.                                                       */
6231 /*                                                                          */
6232 /* Returns:                                                                 */
6233 /*   0 for success, positive value for failure.                             */
6234 /****************************************************************************/
6235 static int
6236 bce_ifmedia_upd(struct ifnet *ifp)
6237 {
6238         struct bce_softc *sc = ifp->if_softc;
6239         int error;
6240
6241         DBENTER(BCE_VERBOSE);
6242
6243         BCE_LOCK(sc);
6244         error = bce_ifmedia_upd_locked(ifp);
6245         BCE_UNLOCK(sc);
6246
6247         DBEXIT(BCE_VERBOSE);
6248         return (error);
6249 }
6250
6251
6252 /****************************************************************************/
6253 /* Set media options.                                                       */
6254 /*                                                                          */
6255 /* Returns:                                                                 */
6256 /*   Nothing.                                                               */
6257 /****************************************************************************/
6258 static int
6259 bce_ifmedia_upd_locked(struct ifnet *ifp)
6260 {
6261         struct bce_softc *sc = ifp->if_softc;
6262         struct mii_data *mii;
6263         struct mii_softc *miisc;
6264         struct ifmedia *ifm;
6265         u32 link;
6266         int error, fdx;
6267
6268         DBENTER(BCE_VERBOSE_PHY);
6269
6270         error = 0;
6271         BCE_LOCK_ASSERT(sc);
6272
6273         sc->bce_link_up = FALSE;
6274         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6275                 ifm = &sc->bce_ifmedia;
6276                 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER)
6277                         return (EINVAL);
6278                 link = 0;
6279                 fdx = IFM_OPTIONS(ifm->ifm_media) & IFM_FDX;
6280                 switch(IFM_SUBTYPE(ifm->ifm_media)) {
6281                 case IFM_AUTO:
6282                         /*
6283                          * Check advertised link of remote PHY by reading
6284                          * BCE_RPHY_SERDES_LINK or BCE_RPHY_COPPER_LINK.
6285                          * Always use the same link type of remote PHY.
6286                          */
6287                         link = bce_get_rphy_link(sc);
6288                         break;
6289                 case IFM_2500_SX:
6290                         if ((sc->bce_phy_flags &
6291                             (BCE_PHY_REMOTE_PORT_FIBER_FLAG |
6292                             BCE_PHY_2_5G_CAPABLE_FLAG)) == 0)
6293                                 return (EINVAL);
6294                         /*
6295                          * XXX
6296                          * Have to enable forced 2.5Gbps configuration.
6297                          */
6298                         if (fdx != 0)
6299                                 link |= BCE_NETLINK_SPEED_2500FULL;
6300                         else
6301                                 link |= BCE_NETLINK_SPEED_2500HALF;
6302                         break;
6303                 case IFM_1000_SX:
6304                         if ((sc->bce_phy_flags &
6305                             BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6306                                 return (EINVAL);
6307                         /*
6308                          * XXX
6309                          * Have to disable 2.5Gbps configuration.
6310                          */
6311                         if (fdx != 0)
6312                                 link = BCE_NETLINK_SPEED_1000FULL;
6313                         else
6314                                 link = BCE_NETLINK_SPEED_1000HALF;
6315                         break;
6316                 case IFM_1000_T:
6317                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6318                                 return (EINVAL);
6319                         if (fdx != 0)
6320                                 link = BCE_NETLINK_SPEED_1000FULL;
6321                         else
6322                                 link = BCE_NETLINK_SPEED_1000HALF;
6323                         break;
6324                 case IFM_100_TX:
6325                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6326                                 return (EINVAL);
6327                         if (fdx != 0)
6328                                 link = BCE_NETLINK_SPEED_100FULL;
6329                         else
6330                                 link = BCE_NETLINK_SPEED_100HALF;
6331                         break;
6332                 case IFM_10_T:
6333                         if (sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG)
6334                                 return (EINVAL);
6335                         if (fdx != 0)
6336                                 link = BCE_NETLINK_SPEED_10FULL;
6337                         else
6338                                 link = BCE_NETLINK_SPEED_10HALF;
6339                         break;
6340                 default:
6341                         return (EINVAL);
6342                 }
6343                 if (IFM_SUBTYPE(ifm->ifm_media) != IFM_AUTO) {
6344                         /*
6345                          * XXX
6346                          * Advertise pause capability for full-duplex media.
6347                          */
6348                         if (fdx != 0)
6349                                 link |= BCE_NETLINK_FC_PAUSE_SYM |
6350                                     BCE_NETLINK_FC_PAUSE_ASYM;
6351                         if ((sc->bce_phy_flags &
6352                             BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6353                                 link |= BCE_NETLINK_PHY_APP_REMOTE |
6354                                     BCE_NETLINK_ETH_AT_WIRESPEED;
6355                 }
6356
6357                 bce_shmem_wr(sc, BCE_MB_ARGS_0, link);
6358                 error = bce_fw_sync(sc, BCE_DRV_MSG_CODE_CMD_SET_LINK);
6359         } else {
6360                 mii = device_get_softc(sc->bce_miibus);
6361
6362                 /* Make sure the MII bus has been enumerated. */
6363                 if (mii) {
6364                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
6365                                 mii_phy_reset(miisc);
6366                         error = mii_mediachg(mii);
6367                 }
6368         }
6369
6370         DBEXIT(BCE_VERBOSE_PHY);
6371         return (error);
6372 }
6373
6374
6375 static void
6376 bce_ifmedia_sts_rphy(struct bce_softc *sc, struct ifmediareq *ifmr)
6377 {
6378         struct ifnet *ifp;
6379         u32 link;
6380
6381         ifp = sc->bce_ifp;
6382         BCE_LOCK_ASSERT(sc);
6383
6384         ifmr->ifm_status = IFM_AVALID;
6385         ifmr->ifm_active = IFM_ETHER;
6386         link = bce_shmem_rd(sc, BCE_LINK_STATUS);
6387         /* XXX Handle heart beat status? */
6388         if ((link & BCE_LINK_STATUS_LINK_UP) != 0)
6389                 ifmr->ifm_status |= IFM_ACTIVE;
6390         else {
6391                 ifmr->ifm_active |= IFM_NONE;
6392                 ifp->if_baudrate = 0;
6393                 return;
6394         }
6395         switch (link & BCE_LINK_STATUS_SPEED_MASK) {
6396         case BCE_LINK_STATUS_10HALF:
6397                 ifmr->ifm_active |= IFM_10_T | IFM_HDX;
6398                 ifp->if_baudrate = IF_Mbps(10UL);
6399                 break;
6400         case BCE_LINK_STATUS_10FULL:
6401                 ifmr->ifm_active |= IFM_10_T | IFM_FDX;
6402                 ifp->if_baudrate = IF_Mbps(10UL);
6403                 break;
6404         case BCE_LINK_STATUS_100HALF:
6405                 ifmr->ifm_active |= IFM_100_TX | IFM_HDX;
6406                 ifp->if_baudrate = IF_Mbps(100UL);
6407                 break;
6408         case BCE_LINK_STATUS_100FULL:
6409                 ifmr->ifm_active |= IFM_100_TX | IFM_FDX;
6410                 ifp->if_baudrate = IF_Mbps(100UL);
6411                 break;
6412         case BCE_LINK_STATUS_1000HALF:
6413                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6414                         ifmr->ifm_active |= IFM_1000_T | IFM_HDX;
6415                 else
6416                         ifmr->ifm_active |= IFM_1000_SX | IFM_HDX;
6417                 ifp->if_baudrate = IF_Mbps(1000UL);
6418                 break;
6419         case BCE_LINK_STATUS_1000FULL:
6420                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0)
6421                         ifmr->ifm_active |= IFM_1000_T | IFM_FDX;
6422                 else
6423                         ifmr->ifm_active |= IFM_1000_SX | IFM_FDX;
6424                 ifp->if_baudrate = IF_Mbps(1000UL);
6425                 break;
6426         case BCE_LINK_STATUS_2500HALF:
6427                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6428                         ifmr->ifm_active |= IFM_NONE;
6429                         return;
6430                 } else
6431                         ifmr->ifm_active |= IFM_2500_SX | IFM_HDX;
6432                 ifp->if_baudrate = IF_Mbps(2500UL);
6433                 break;
6434         case BCE_LINK_STATUS_2500FULL:
6435                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_PORT_FIBER_FLAG) == 0) {
6436                         ifmr->ifm_active |= IFM_NONE;
6437                         return;
6438                 } else
6439                         ifmr->ifm_active |= IFM_2500_SX | IFM_FDX;
6440                 ifp->if_baudrate = IF_Mbps(2500UL);
6441                 break;
6442         default:
6443                 ifmr->ifm_active |= IFM_NONE;
6444                 return;
6445         }
6446
6447         if ((link & BCE_LINK_STATUS_RX_FC_ENABLED) != 0)
6448                 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
6449         if ((link & BCE_LINK_STATUS_TX_FC_ENABLED) != 0)
6450                 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
6451 }
6452
6453
6454 /****************************************************************************/
6455 /* Reports current media status.                                            */
6456 /*                                                                          */
6457 /* Returns:                                                                 */
6458 /*   Nothing.                                                               */
6459 /****************************************************************************/
6460 static void
6461 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
6462 {
6463         struct bce_softc *sc = ifp->if_softc;
6464         struct mii_data *mii;
6465
6466         DBENTER(BCE_VERBOSE_PHY);
6467
6468         BCE_LOCK(sc);
6469
6470         if ((ifp->if_flags & IFF_UP) == 0) {
6471                 BCE_UNLOCK(sc);
6472                 return;
6473         }
6474
6475         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
6476                 bce_ifmedia_sts_rphy(sc, ifmr);
6477         else {
6478                 mii = device_get_softc(sc->bce_miibus);
6479                 mii_pollstat(mii);
6480                 ifmr->ifm_active = mii->mii_media_active;
6481                 ifmr->ifm_status = mii->mii_media_status;
6482         }
6483
6484         BCE_UNLOCK(sc);
6485
6486         DBEXIT(BCE_VERBOSE_PHY);
6487 }
6488
6489
6490 /****************************************************************************/
6491 /* Handles PHY generated interrupt events.                                  */
6492 /*                                                                          */
6493 /* Returns:                                                                 */
6494 /*   Nothing.                                                               */
6495 /****************************************************************************/
6496 static void
6497 bce_phy_intr(struct bce_softc *sc)
6498 {
6499         u32 new_link_state, old_link_state;
6500
6501         DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6502
6503         DBRUN(sc->phy_interrupts++);
6504
6505         new_link_state = sc->status_block->status_attn_bits &
6506             STATUS_ATTN_BITS_LINK_STATE;
6507         old_link_state = sc->status_block->status_attn_bits_ack &
6508             STATUS_ATTN_BITS_LINK_STATE;
6509
6510         /* Handle any changes if the link state has changed. */
6511         if (new_link_state != old_link_state) {
6512
6513                 /* Update the status_attn_bits_ack field. */
6514                 if (new_link_state) {
6515                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
6516                             STATUS_ATTN_BITS_LINK_STATE);
6517                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n",
6518                             __FUNCTION__);
6519                 } else {
6520                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
6521                             STATUS_ATTN_BITS_LINK_STATE);
6522                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
6523                             __FUNCTION__);
6524                 }
6525
6526                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
6527                         if (new_link_state) {
6528                                 if (bootverbose)
6529                                         if_printf(sc->bce_ifp, "link UP\n");
6530                                 if_link_state_change(sc->bce_ifp,
6531                                     LINK_STATE_UP);
6532                         } else {
6533                                 if (bootverbose)
6534                                         if_printf(sc->bce_ifp, "link DOWN\n");
6535                                 if_link_state_change(sc->bce_ifp,
6536                                     LINK_STATE_DOWN);
6537                         }
6538                 }
6539                 /*
6540                  * Assume link is down and allow
6541                  * tick routine to update the state
6542                  * based on the actual media state.
6543                  */
6544                 sc->bce_link_up = FALSE;
6545                 callout_stop(&sc->bce_tick_callout);
6546                 bce_tick(sc);
6547         }
6548
6549         /* Acknowledge the link change interrupt. */
6550         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
6551
6552         DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
6553 }
6554
6555
6556 /****************************************************************************/
6557 /* Reads the receive consumer value from the status block (skipping over    */
6558 /* chain page pointer if necessary).                                        */
6559 /*                                                                          */
6560 /* Returns:                                                                 */
6561 /*   hw_cons                                                                */
6562 /****************************************************************************/
6563 static inline u16
6564 bce_get_hw_rx_cons(struct bce_softc *sc)
6565 {
6566         u16 hw_cons;
6567
6568         rmb();
6569         hw_cons = sc->status_block->status_rx_quick_consumer_index0;
6570         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
6571                 hw_cons++;
6572
6573         return hw_cons;
6574 }
6575
6576 /****************************************************************************/
6577 /* Handles received frame interrupt events.                                 */
6578 /*                                                                          */
6579 /* Returns:                                                                 */
6580 /*   Nothing.                                                               */
6581 /****************************************************************************/
6582 static void
6583 bce_rx_intr(struct bce_softc *sc)
6584 {
6585         struct ifnet *ifp = sc->bce_ifp;
6586         struct l2_fhdr *l2fhdr;
6587         struct ether_vlan_header *vh;
6588         unsigned int pkt_len;
6589         u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
6590         u32 status;
6591         unsigned int rem_len;
6592         u16 sw_pg_cons, sw_pg_cons_idx;
6593
6594         DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6595         DBRUN(sc->interrupts_rx++);
6596         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
6597             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6598             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6599
6600         /* Prepare the RX chain pages to be accessed by the host CPU. */
6601         for (int i = 0; i < sc->rx_pages; i++)
6602                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6603                     sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6604
6605         /* Prepare the page chain pages to be accessed by the host CPU. */
6606         if (bce_hdr_split == TRUE) {
6607                 for (int i = 0; i < sc->pg_pages; i++)
6608                         bus_dmamap_sync(sc->pg_bd_chain_tag,
6609                             sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
6610         }
6611
6612         /* Get the hardware's view of the RX consumer index. */
6613         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6614
6615         /* Get working copies of the driver's view of the consumer indices. */
6616         sw_rx_cons = sc->rx_cons;
6617         sw_pg_cons = sc->pg_cons;
6618
6619         /* Update some debug statistics counters */
6620         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
6621             sc->rx_low_watermark = sc->free_rx_bd);
6622         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
6623             sc->rx_empty_count++);
6624
6625         /* Scan through the receive chain as long as there is work to do */
6626         /* ToDo: Consider setting a limit on the number of packets processed. */
6627         rmb();
6628         while (sw_rx_cons != hw_rx_cons) {
6629                 struct mbuf *m0;
6630
6631                 /* Convert the producer/consumer indices to an actual rx_bd index. */
6632                 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
6633
6634                 /* Unmap the mbuf from DMA space. */
6635                 bus_dmamap_sync(sc->rx_mbuf_tag,
6636                     sc->rx_mbuf_map[sw_rx_cons_idx],
6637                     BUS_DMASYNC_POSTREAD);
6638                 bus_dmamap_unload(sc->rx_mbuf_tag,
6639                     sc->rx_mbuf_map[sw_rx_cons_idx]);
6640
6641                 /* Remove the mbuf from the RX chain. */
6642                 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
6643                 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
6644                 DBRUN(sc->debug_rx_mbuf_alloc--);
6645                 sc->free_rx_bd++;
6646
6647                 if(m0 == NULL) {
6648                         DBPRINT(sc, BCE_EXTREME_RECV,
6649                             "%s(): Oops! Empty mbuf pointer "
6650                             "found in sc->rx_mbuf_ptr[0x%04X]!\n",
6651                             __FUNCTION__, sw_rx_cons_idx);
6652                         goto bce_rx_int_next_rx;
6653                 }
6654
6655                 /*
6656                  * Frames received on the NetXteme II are prepended
6657                  * with an l2_fhdr structure which provides status
6658                  * information about the received frame (including
6659                  * VLAN tags and checksum info).  The frames are
6660                  * also automatically adjusted to word align the IP
6661                  * header (i.e. two null bytes are inserted before
6662                  * the Ethernet header).  As a result the data
6663                  * DMA'd by the controller into the mbuf looks
6664                  * like this:
6665                  *
6666                  * +---------+-----+---------------------+-----+
6667                  * | l2_fhdr | pad | packet data         | FCS |
6668                  * +---------+-----+---------------------+-----+
6669                  *
6670                  * The l2_fhdr needs to be checked and skipped and
6671                  * the FCS needs to be stripped before sending the
6672                  * packet up the stack.
6673                  */
6674                 l2fhdr  = mtod(m0, struct l2_fhdr *);
6675
6676                 /* Get the packet data + FCS length and the status. */
6677                 pkt_len = l2fhdr->l2_fhdr_pkt_len;
6678                 status  = l2fhdr->l2_fhdr_status;
6679
6680                 /*
6681                  * Skip over the l2_fhdr and pad, resulting in the
6682                  * following data in the mbuf:
6683                  * +---------------------+-----+
6684                  * | packet data         | FCS |
6685                  * +---------------------+-----+
6686                  */
6687                 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
6688
6689                 /*
6690                  * When split header mode is used, an ethernet frame
6691                  * may be split across the receive chain and the
6692                  * page chain. If that occurs an mbuf cluster must be
6693                  * reassembled from the individual mbuf pieces.
6694                  */
6695                 if (bce_hdr_split == TRUE) {
6696                         /*
6697                          * Check whether the received frame fits in a single
6698                          * mbuf or not (i.e. packet data + FCS <=
6699                          * sc->rx_bd_mbuf_data_len bytes).
6700                          */
6701                         if (pkt_len > m0->m_len) {
6702                                 /*
6703                                  * The received frame is larger than a single mbuf.
6704                                  * If the frame was a TCP frame then only the TCP
6705                                  * header is placed in the mbuf, the remaining
6706                                  * payload (including FCS) is placed in the page
6707                                  * chain, the SPLIT flag is set, and the header
6708                                  * length is placed in the IP checksum field.
6709                                  * If the frame is not a TCP frame then the mbuf
6710                                  * is filled and the remaining bytes are placed
6711                                  * in the page chain.
6712                                  */
6713
6714                                 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large "
6715                                         "packet.\n", __FUNCTION__);
6716                                 DBRUN(sc->split_header_frames_rcvd++);
6717
6718                                 /*
6719                                  * When the page chain is enabled and the TCP
6720                                  * header has been split from the TCP payload,
6721                                  * the ip_xsum structure will reflect the length
6722                                  * of the TCP header, not the IP checksum.  Set
6723                                  * the packet length of the mbuf accordingly.
6724                                  */
6725                                 if (status & L2_FHDR_STATUS_SPLIT) {
6726                                         m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
6727                                         DBRUN(sc->split_header_tcp_frames_rcvd++);
6728                                 }
6729
6730                                 rem_len = pkt_len - m0->m_len;
6731
6732                                 /* Pull mbufs off the page chain for any remaining data. */
6733                                 while (rem_len > 0) {
6734                                         struct mbuf *m_pg;
6735
6736                                         sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
6737
6738                                         /* Remove the mbuf from the page chain. */
6739                                         m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
6740                                         sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
6741                                         DBRUN(sc->debug_pg_mbuf_alloc--);
6742                                         sc->free_pg_bd++;
6743
6744                                         /* Unmap the page chain mbuf from DMA space. */
6745                                         bus_dmamap_sync(sc->pg_mbuf_tag,
6746                                                 sc->pg_mbuf_map[sw_pg_cons_idx],
6747                                                 BUS_DMASYNC_POSTREAD);
6748                                         bus_dmamap_unload(sc->pg_mbuf_tag,
6749                                                 sc->pg_mbuf_map[sw_pg_cons_idx]);
6750
6751                                         /* Adjust the mbuf length. */
6752                                         if (rem_len < m_pg->m_len) {
6753                                                 /* The mbuf chain is complete. */
6754                                                 m_pg->m_len = rem_len;
6755                                                 rem_len = 0;
6756                                         } else {
6757                                                 /* More packet data is waiting. */
6758                                                 rem_len -= m_pg->m_len;
6759                                         }
6760
6761                                         /* Concatenate the mbuf cluster to the mbuf. */
6762                                         m_cat(m0, m_pg);
6763
6764                                         sw_pg_cons = NEXT_PG_BD(sw_pg_cons);
6765                                 }
6766
6767                                 /* Set the total packet length. */
6768                                 m0->m_pkthdr.len = pkt_len;
6769
6770                         } else {
6771                                 /*
6772                                  * The received packet is small and fits in a
6773                                  * single mbuf (i.e. the l2_fhdr + pad + packet +
6774                                  * FCS <= MHLEN).  In other words, the packet is
6775                                  * 154 bytes or less in size.
6776                                  */
6777
6778                                 DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small "
6779                                         "packet.\n", __FUNCTION__);
6780
6781                                 /* Set the total packet length. */
6782                                 m0->m_pkthdr.len = m0->m_len = pkt_len;
6783                         }
6784                 } else
6785                         /* Set the total packet length. */
6786                         m0->m_pkthdr.len = m0->m_len = pkt_len;
6787
6788                 /* Remove the trailing Ethernet FCS. */
6789                 m_adj(m0, -ETHER_CRC_LEN);
6790
6791                 /* Check that the resulting mbuf chain is valid. */
6792                 DBRUN(m_sanity(m0, FALSE));
6793                 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
6794                     (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
6795                     BCE_PRINTF("Invalid Ethernet frame size!\n");
6796                     m_print(m0, 128));
6797
6798                 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control),
6799                     sc->l2fhdr_error_sim_count++;
6800                     status = status | L2_FHDR_ERRORS_PHY_DECODE);
6801
6802                 /* Check the received frame for errors. */
6803                 if (status & (L2_FHDR_ERRORS_BAD_CRC |
6804                     L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
6805                     L2_FHDR_ERRORS_TOO_SHORT  | L2_FHDR_ERRORS_GIANT_FRAME)) {
6806
6807                         /* Log the error and release the mbuf. */
6808                         ifp->if_ierrors++;
6809                         sc->l2fhdr_error_count++;
6810
6811                         m_freem(m0);
6812                         m0 = NULL;
6813                         goto bce_rx_int_next_rx;
6814                 }
6815
6816                 /* Send the packet to the appropriate interface. */
6817                 m0->m_pkthdr.rcvif = ifp;
6818
6819                 /* Assume no hardware checksum. */
6820                 m0->m_pkthdr.csum_flags = 0;
6821
6822                 /* Validate the checksum if offload enabled. */
6823                 if (ifp->if_capenable & IFCAP_RXCSUM) {
6824
6825                         /* Check for an IP datagram. */
6826                         if (!(status & L2_FHDR_STATUS_SPLIT) &&
6827                             (status & L2_FHDR_STATUS_IP_DATAGRAM)) {
6828                                 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
6829                                 DBRUN(sc->csum_offload_ip++);
6830                                 /* Check if the IP checksum is valid. */
6831                                 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
6832                                         m0->m_pkthdr.csum_flags |=
6833                                             CSUM_IP_VALID;
6834                         }
6835
6836                         /* Check for a valid TCP/UDP frame. */
6837                         if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
6838                             L2_FHDR_STATUS_UDP_DATAGRAM)) {
6839
6840                                 /* Check for a good TCP/UDP checksum. */
6841                                 if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
6842                                     L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
6843                                         DBRUN(sc->csum_offload_tcp_udp++);
6844                                         m0->m_pkthdr.csum_data =
6845                                             l2fhdr->l2_fhdr_tcp_udp_xsum;
6846                                         m0->m_pkthdr.csum_flags |=
6847                                             (CSUM_DATA_VALID
6848                                             | CSUM_PSEUDO_HDR);
6849                                 }
6850                         }
6851                 }
6852
6853                 /* Attach the VLAN tag. */
6854                 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
6855                         DBRUN(sc->vlan_tagged_frames_rcvd++);
6856                         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
6857                                 DBRUN(sc->vlan_tagged_frames_stripped++);
6858 #if __FreeBSD_version < 700000
6859                                 VLAN_INPUT_TAG(ifp, m0,
6860                                     l2fhdr->l2_fhdr_vlan_tag, continue);
6861 #else
6862                                 m0->m_pkthdr.ether_vtag =
6863                                     l2fhdr->l2_fhdr_vlan_tag;
6864                                 m0->m_flags |= M_VLANTAG;
6865 #endif
6866                         } else {
6867                                 /*
6868                                  * bce(4) controllers can't disable VLAN
6869                                  * tag stripping if management firmware
6870                                  * (ASF/IPMI/UMP) is running. So we always
6871                                  * strip VLAN tag and manually reconstruct
6872                                  * the VLAN frame by appending stripped
6873                                  * VLAN tag in driver if VLAN tag stripping
6874                                  * was disabled.
6875                                  *
6876                                  * TODO: LLC SNAP handling.
6877                                  */
6878                                 bcopy(mtod(m0, uint8_t *),
6879                                     mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN,
6880                                     ETHER_ADDR_LEN * 2);
6881                                 m0->m_data -= ETHER_VLAN_ENCAP_LEN;
6882                                 vh = mtod(m0, struct ether_vlan_header *);
6883                                 vh->evl_encap_proto = htons(ETHERTYPE_VLAN);
6884                                 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag);
6885                                 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN;
6886                                 m0->m_len += ETHER_VLAN_ENCAP_LEN;
6887                         }
6888                 }
6889
6890                 /* Increment received packet statistics. */
6891                 ifp->if_ipackets++;
6892
6893 bce_rx_int_next_rx:
6894                 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
6895
6896                 /* If we have a packet, pass it up the stack */
6897                 if (m0) {
6898                         /* Make sure we don't lose our place when we release the lock. */
6899                         sc->rx_cons = sw_rx_cons;
6900                         sc->pg_cons = sw_pg_cons;
6901
6902                         BCE_UNLOCK(sc);
6903                         (*ifp->if_input)(ifp, m0);
6904                         BCE_LOCK(sc);
6905
6906                         /* Recover our place. */
6907                         sw_rx_cons = sc->rx_cons;
6908                         sw_pg_cons = sc->pg_cons;
6909                 }
6910
6911                 /* Refresh hw_cons to see if there's new work */
6912                 if (sw_rx_cons == hw_rx_cons)
6913                         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6914         }
6915
6916         /* No new packets.  Refill the page chain. */
6917         if (bce_hdr_split == TRUE) {
6918                 sc->pg_cons = sw_pg_cons;
6919                 bce_fill_pg_chain(sc);
6920         }
6921
6922         /* No new packets.  Refill the RX chain. */
6923         sc->rx_cons = sw_rx_cons;
6924         bce_fill_rx_chain(sc);
6925
6926         /* Prepare the page chain pages to be accessed by the NIC. */
6927         for (int i = 0; i < sc->rx_pages; i++)
6928                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6929                     sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6930
6931         if (bce_hdr_split == TRUE) {
6932                 for (int i = 0; i < sc->pg_pages; i++)
6933                         bus_dmamap_sync(sc->pg_bd_chain_tag,
6934                             sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6935         }
6936
6937         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
6938             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6939             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6940         DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6941 }
6942
6943
6944 /****************************************************************************/
6945 /* Reads the transmit consumer value from the status block (skipping over   */
6946 /* chain page pointer if necessary).                                        */
6947 /*                                                                          */
6948 /* Returns:                                                                 */
6949 /*   hw_cons                                                                */
6950 /****************************************************************************/
6951 static inline u16
6952 bce_get_hw_tx_cons(struct bce_softc *sc)
6953 {
6954         u16 hw_cons;
6955
6956         mb();
6957         hw_cons = sc->status_block->status_tx_quick_consumer_index0;
6958         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
6959                 hw_cons++;
6960
6961         return hw_cons;
6962 }
6963
6964
6965 /****************************************************************************/
6966 /* Handles transmit completion interrupt events.                            */
6967 /*                                                                          */
6968 /* Returns:                                                                 */
6969 /*   Nothing.                                                               */
6970 /****************************************************************************/
6971 static void
6972 bce_tx_intr(struct bce_softc *sc)
6973 {
6974         struct ifnet *ifp = sc->bce_ifp;
6975         u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
6976
6977         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6978         DBRUN(sc->interrupts_tx++);
6979         DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6980             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6981             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6982
6983         BCE_LOCK_ASSERT(sc);
6984
6985         /* Get the hardware's view of the TX consumer index. */
6986         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6987         sw_tx_cons = sc->tx_cons;
6988
6989         /* Prevent speculative reads of the status block. */
6990         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6991             BUS_SPACE_BARRIER_READ);
6992
6993         /* Cycle through any completed TX chain page entries. */
6994         while (sw_tx_cons != hw_tx_cons) {
6995 #ifdef BCE_DEBUG
6996                 struct tx_bd *txbd = NULL;
6997 #endif
6998                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
6999
7000                 DBPRINT(sc, BCE_INFO_SEND,
7001                     "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
7002                     "sw_tx_chain_cons = 0x%04X\n",
7003                     __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
7004
7005                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD_ALLOC),
7006                     BCE_PRINTF("%s(%d): TX chain consumer out of range! "
7007                     " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
7008                     (int) MAX_TX_BD_ALLOC);
7009                     bce_breakpoint(sc));
7010
7011                 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
7012                     [TX_IDX(sw_tx_chain_cons)]);
7013
7014                 DBRUNIF((txbd == NULL),
7015                     BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
7016                     __FILE__, __LINE__, sw_tx_chain_cons);
7017                     bce_breakpoint(sc));
7018
7019                 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
7020                     bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
7021
7022                 /*
7023                  * Free the associated mbuf. Remember
7024                  * that only the last tx_bd of a packet
7025                  * has an mbuf pointer and DMA map.
7026                  */
7027                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
7028
7029                         /* Validate that this is the last tx_bd. */
7030                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
7031                             BCE_PRINTF("%s(%d): tx_bd END flag not set but "
7032                             "txmbuf == NULL!\n", __FILE__, __LINE__);
7033                             bce_breakpoint(sc));
7034
7035                         DBRUNMSG(BCE_INFO_SEND,
7036                             BCE_PRINTF("%s(): Unloading map/freeing mbuf "
7037                             "from tx_bd[0x%04X]\n", __FUNCTION__,
7038                             sw_tx_chain_cons));
7039
7040                         /* Unmap the mbuf. */
7041                         bus_dmamap_unload(sc->tx_mbuf_tag,
7042                             sc->tx_mbuf_map[sw_tx_chain_cons]);
7043
7044                         /* Free the mbuf. */
7045                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
7046                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
7047                         DBRUN(sc->debug_tx_mbuf_alloc--);
7048
7049                         ifp->if_opackets++;
7050                 }
7051
7052                 sc->used_tx_bd--;
7053                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
7054
7055                 /* Refresh hw_cons to see if there's new work. */
7056                 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
7057
7058                 /* Prevent speculative reads of the status block. */
7059                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
7060                     BUS_SPACE_BARRIER_READ);
7061         }
7062
7063         /* Clear the TX timeout timer. */
7064         sc->watchdog_timer = 0;
7065
7066         /* Clear the tx hardware queue full flag. */
7067         if (sc->used_tx_bd < sc->max_tx_bd) {
7068                 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
7069                     DBPRINT(sc, BCE_INFO_SEND,
7070                     "%s(): Open TX chain! %d/%d (used/total)\n",
7071                     __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
7072                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7073         }
7074
7075         sc->tx_cons = sw_tx_cons;
7076
7077         DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
7078             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
7079             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
7080         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
7081 }
7082
7083
7084 /****************************************************************************/
7085 /* Disables interrupt generation.                                           */
7086 /*                                                                          */
7087 /* Returns:                                                                 */
7088 /*   Nothing.                                                               */
7089 /****************************************************************************/
7090 static void
7091 bce_disable_intr(struct bce_softc *sc)
7092 {
7093         DBENTER(BCE_VERBOSE_INTR);
7094
7095         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7096         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
7097
7098         DBEXIT(BCE_VERBOSE_INTR);
7099 }
7100
7101
7102 /****************************************************************************/
7103 /* Enables interrupt generation.                                            */
7104 /*                                                                          */
7105 /* Returns:                                                                 */
7106 /*   Nothing.                                                               */
7107 /****************************************************************************/
7108 static void
7109 bce_enable_intr(struct bce_softc *sc, int coal_now)
7110 {
7111         DBENTER(BCE_VERBOSE_INTR);
7112
7113         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7114             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
7115             BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
7116
7117         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7118             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
7119
7120         /* Force an immediate interrupt (whether there is new data or not). */
7121         if (coal_now)
7122                 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
7123
7124         DBEXIT(BCE_VERBOSE_INTR);
7125 }
7126
7127
7128 /****************************************************************************/
7129 /* Handles controller initialization.                                       */
7130 /*                                                                          */
7131 /* Returns:                                                                 */
7132 /*   Nothing.                                                               */
7133 /****************************************************************************/
7134 static void
7135 bce_init_locked(struct bce_softc *sc)
7136 {
7137         struct ifnet *ifp;
7138         u32 ether_mtu = 0;
7139
7140         DBENTER(BCE_VERBOSE_RESET);
7141
7142         BCE_LOCK_ASSERT(sc);
7143
7144         ifp = sc->bce_ifp;
7145
7146         /* Check if the driver is still running and bail out if it is. */
7147         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7148                 goto bce_init_locked_exit;
7149
7150         bce_stop(sc);
7151
7152         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
7153                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
7154                     __FILE__, __LINE__);
7155                 goto bce_init_locked_exit;
7156         }
7157
7158         if (bce_chipinit(sc)) {
7159                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
7160                     __FILE__, __LINE__);
7161                 goto bce_init_locked_exit;
7162         }
7163
7164         if (bce_blockinit(sc)) {
7165                 BCE_PRINTF("%s(%d): Block initialization failed!\n",
7166                     __FILE__, __LINE__);
7167                 goto bce_init_locked_exit;
7168         }
7169
7170         /* Load our MAC address. */
7171         bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
7172         bce_set_mac_addr(sc);
7173
7174         if (bce_hdr_split == FALSE)
7175                 bce_get_rx_buffer_sizes(sc, ifp->if_mtu);
7176         /*
7177          * Calculate and program the hardware Ethernet MTU
7178          * size. Be generous on the receive if we have room
7179          * and allowed by the user.
7180          */
7181         if (bce_strict_rx_mtu == TRUE)
7182                 ether_mtu = ifp->if_mtu;
7183         else {
7184                 if (bce_hdr_split == TRUE) {
7185                         if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len +
7186                                    sc->pg_bd_mbuf_alloc_size))
7187                                         ether_mtu = sc->rx_bd_mbuf_data_len +
7188                                            sc->pg_bd_mbuf_alloc_size;
7189                         else
7190                                 ether_mtu = ifp->if_mtu;
7191                 } else {
7192                         if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
7193                                 ether_mtu = sc->rx_bd_mbuf_data_len;
7194                         else
7195                                 ether_mtu = ifp->if_mtu;
7196                 }
7197         }
7198
7199         ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
7200
7201         DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n",
7202             __FUNCTION__, ether_mtu);
7203
7204         /* Program the mtu, enabling jumbo frame support if necessary. */
7205         if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
7206                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
7207                     min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
7208                     BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
7209         else
7210                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
7211
7212         /* Program appropriate promiscuous/multicast filtering. */
7213         bce_set_rx_mode(sc);
7214
7215         if (bce_hdr_split == TRUE) {
7216                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n",
7217                         __FUNCTION__, sc->pg_bd_mbuf_alloc_size);
7218
7219                 /* Init page buffer descriptor chain. */
7220                 bce_init_pg_chain(sc);
7221         }
7222
7223         /* Init RX buffer descriptor chain. */
7224         bce_init_rx_chain(sc);
7225
7226         /* Init TX buffer descriptor chain. */
7227         bce_init_tx_chain(sc);
7228
7229         /* Enable host interrupts. */
7230         bce_enable_intr(sc, 1);
7231
7232         bce_ifmedia_upd_locked(ifp);
7233
7234         /* Let the OS know the driver is up and running. */
7235         ifp->if_drv_flags |= IFF_DRV_RUNNING;
7236         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
7237
7238         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7239
7240 bce_init_locked_exit:
7241         DBEXIT(BCE_VERBOSE_RESET);
7242 }
7243
7244
7245 /****************************************************************************/
7246 /* Initialize the controller just enough so that any management firmware    */
7247 /* running on the device will continue to operate correctly.                */
7248 /*                                                                          */
7249 /* Returns:                                                                 */
7250 /*   Nothing.                                                               */
7251 /****************************************************************************/
7252 static void
7253 bce_mgmt_init_locked(struct bce_softc *sc)
7254 {
7255         struct ifnet *ifp;
7256
7257         DBENTER(BCE_VERBOSE_RESET);
7258
7259         BCE_LOCK_ASSERT(sc);
7260
7261         /* Bail out if management firmware is not running. */
7262         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
7263                 DBPRINT(sc, BCE_VERBOSE_SPECIAL,
7264                     "No management firmware running...\n");
7265                 goto bce_mgmt_init_locked_exit;
7266         }
7267
7268         ifp = sc->bce_ifp;
7269
7270         /* Enable all critical blocks in the MAC. */
7271         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
7272         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
7273         DELAY(20);
7274
7275         bce_ifmedia_upd_locked(ifp);
7276
7277 bce_mgmt_init_locked_exit:
7278         DBEXIT(BCE_VERBOSE_RESET);
7279 }
7280
7281
7282 /****************************************************************************/
7283 /* Handles controller initialization when called from an unlocked routine.  */
7284 /*                                                                          */
7285 /* Returns:                                                                 */
7286 /*   Nothing.                                                               */
7287 /****************************************************************************/
7288 static void
7289 bce_init(void *xsc)
7290 {
7291         struct bce_softc *sc = xsc;
7292
7293         DBENTER(BCE_VERBOSE_RESET);
7294
7295         BCE_LOCK(sc);
7296         bce_init_locked(sc);
7297         BCE_UNLOCK(sc);
7298
7299         DBEXIT(BCE_VERBOSE_RESET);
7300 }
7301
7302
7303 /****************************************************************************/
7304 /* Modifies an mbuf for TSO on the hardware.                                */
7305 /*                                                                          */
7306 /* Returns:                                                                 */
7307 /*   Pointer to a modified mbuf.                                            */
7308 /****************************************************************************/
7309 static struct mbuf *
7310 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags)
7311 {
7312         struct mbuf *m;
7313         struct ether_header *eh;
7314         struct ip *ip;
7315         struct tcphdr *th;
7316         u16 etype;
7317         int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0;
7318
7319         DBRUN(sc->tso_frames_requested++);
7320
7321         /* Controller may modify mbuf chains. */
7322         if (M_WRITABLE(*m_head) == 0) {
7323                 m = m_dup(*m_head, M_DONTWAIT);
7324                 m_freem(*m_head);
7325                 if (m == NULL) {
7326                         sc->mbuf_alloc_failed_count++;
7327                         *m_head = NULL;
7328                         return (NULL);
7329                 }
7330                 *m_head = m;
7331         }
7332
7333         /*
7334          * For TSO the controller needs two pieces of info,
7335          * the MSS and the IP+TCP options length.
7336          */
7337         m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip));
7338         if (m == NULL) {
7339                 *m_head = NULL;
7340                 return (NULL);
7341         }
7342         eh = mtod(m, struct ether_header *);
7343         etype = ntohs(eh->ether_type);
7344
7345         /* Check for supported TSO Ethernet types (only IPv4 for now) */
7346         switch (etype) {
7347         case ETHERTYPE_IP:
7348                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7349                 /* TSO only supported for TCP protocol. */
7350                 if (ip->ip_p != IPPROTO_TCP) {
7351                         BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
7352                             __FILE__, __LINE__);
7353                         m_freem(*m_head);
7354                         *m_head = NULL;
7355                         return (NULL);
7356                 }
7357
7358                 /* Get IP header length in bytes (min 20) */
7359                 ip_hlen = ip->ip_hl << 2;
7360                 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen +
7361                     sizeof(struct tcphdr));
7362                 if (m == NULL) {
7363                         *m_head = NULL;
7364                         return (NULL);
7365                 }
7366
7367                 /* Get the TCP header length in bytes (min 20) */
7368                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7369                 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
7370                 tcp_hlen = (th->th_off << 2);
7371
7372                 /* Make sure all IP/TCP options live in the same buffer. */
7373                 m = m_pullup(*m_head,  sizeof(struct ether_header)+ ip_hlen +
7374                     tcp_hlen);
7375                 if (m == NULL) {
7376                         *m_head = NULL;
7377                         return (NULL);
7378                 }
7379
7380                 /* Clear IP header length and checksum, will be calc'd by h/w. */
7381                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
7382                 ip_len = ip->ip_len;
7383                 ip->ip_len = 0;
7384                 ip->ip_sum = 0;
7385                 break;
7386         case ETHERTYPE_IPV6:
7387                 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n",
7388                     __FILE__, __LINE__);
7389                 m_freem(*m_head);
7390                 *m_head = NULL;
7391                 return (NULL);
7392                 /* NOT REACHED */
7393         default:
7394                 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
7395                     __FILE__, __LINE__);
7396                 m_freem(*m_head);
7397                 *m_head = NULL;
7398                 return (NULL);
7399         }
7400
7401         hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen;
7402
7403         DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, "
7404             "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
7405             __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen,
7406             tcp_hlen, ip_len);
7407
7408         /* Set the LSO flag in the TX BD */
7409         *flags |= TX_BD_FLAGS_SW_LSO;
7410
7411         /* Set the length of IP + TCP options (in 32 bit words) */
7412         *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) -
7413             sizeof(struct tcphdr)) >> 2) << 8);
7414
7415         DBRUN(sc->tso_frames_completed++);
7416         return (*m_head);
7417 }
7418
7419
7420 /****************************************************************************/
7421 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
7422 /* memory visible to the controller.                                        */
7423 /*                                                                          */
7424 /* Returns:                                                                 */
7425 /*   0 for success, positive value for failure.                             */
7426 /* Modified:                                                                */
7427 /*   m_head: May be set to NULL if MBUF is excessively fragmented.          */
7428 /****************************************************************************/
7429 static int
7430 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head)
7431 {
7432         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
7433         bus_dmamap_t map;
7434         struct tx_bd *txbd = NULL;
7435         struct mbuf *m0;
7436         u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0;
7437         u32 prod_bseq;
7438
7439 #ifdef BCE_DEBUG
7440         u16 debug_prod;
7441 #endif
7442
7443         int i, error, nsegs, rc = 0;
7444
7445         DBENTER(BCE_VERBOSE_SEND);
7446
7447         /* Make sure we have room in the TX chain. */
7448         if (sc->used_tx_bd >= sc->max_tx_bd)
7449                 goto bce_tx_encap_exit;
7450
7451         /* Transfer any checksum offload flags to the bd. */
7452         m0 = *m_head;
7453         if (m0->m_pkthdr.csum_flags) {
7454                 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
7455                         m0 = bce_tso_setup(sc, m_head, &flags);
7456                         if (m0 == NULL) {
7457                                 DBRUN(sc->tso_frames_failed++);
7458                                 goto bce_tx_encap_exit;
7459                         }
7460                         mss = htole16(m0->m_pkthdr.tso_segsz);
7461                 } else {
7462                         if (m0->m_pkthdr.csum_flags & CSUM_IP)
7463                                 flags |= TX_BD_FLAGS_IP_CKSUM;
7464                         if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
7465                                 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
7466                 }
7467         }
7468
7469         /* Transfer any VLAN tags to the bd. */
7470         if (m0->m_flags & M_VLANTAG) {
7471                 flags |= TX_BD_FLAGS_VLAN_TAG;
7472                 vlan_tag = m0->m_pkthdr.ether_vtag;
7473         }
7474
7475         /* Map the mbuf into DMAable memory. */
7476         prod = sc->tx_prod;
7477         chain_prod = TX_CHAIN_IDX(prod);
7478         map = sc->tx_mbuf_map[chain_prod];
7479
7480         /* Map the mbuf into our DMA address space. */
7481         error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
7482             segs, &nsegs, BUS_DMA_NOWAIT);
7483
7484         /* Check if the DMA mapping was successful */
7485         if (error == EFBIG) {
7486                 sc->mbuf_frag_count++;
7487
7488                 /* Try to defrag the mbuf. */
7489                 m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS);
7490                 if (m0 == NULL) {
7491                         /* Defrag was unsuccessful */
7492                         m_freem(*m_head);
7493                         *m_head = NULL;
7494                         sc->mbuf_alloc_failed_count++;
7495                         rc = ENOBUFS;
7496                         goto bce_tx_encap_exit;
7497                 }
7498
7499                 /* Defrag was successful, try mapping again */
7500                 *m_head = m0;
7501                 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag,
7502                     map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
7503
7504                 /* Still getting an error after a defrag. */
7505                 if (error == ENOMEM) {
7506                         /* Insufficient DMA buffers available. */
7507                         sc->dma_map_addr_tx_failed_count++;
7508                         rc = error;
7509                         goto bce_tx_encap_exit;
7510                 } else if (error != 0) {
7511                         /* Release it and return an error. */
7512                         BCE_PRINTF("%s(%d): Unknown error mapping mbuf into "
7513                             "TX chain!\n", __FILE__, __LINE__);
7514                         m_freem(m0);
7515                         *m_head = NULL;
7516                         sc->dma_map_addr_tx_failed_count++;
7517                         rc = ENOBUFS;
7518                         goto bce_tx_encap_exit;
7519                 }
7520         } else if (error == ENOMEM) {
7521                 /* Insufficient DMA buffers available. */
7522                 sc->dma_map_addr_tx_failed_count++;
7523                 rc = error;
7524                 goto bce_tx_encap_exit;
7525         } else if (error != 0) {
7526                 m_freem(m0);
7527                 *m_head = NULL;
7528                 sc->dma_map_addr_tx_failed_count++;
7529                 rc = error;
7530                 goto bce_tx_encap_exit;
7531         }
7532
7533         /* Make sure there's room in the chain */
7534         if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
7535                 bus_dmamap_unload(sc->tx_mbuf_tag, map);
7536                 rc = ENOBUFS;
7537                 goto bce_tx_encap_exit;
7538         }
7539
7540         /* prod points to an empty tx_bd at this point. */
7541         prod_bseq  = sc->tx_prod_bseq;
7542
7543 #ifdef BCE_DEBUG
7544         debug_prod = chain_prod;
7545 #endif
7546
7547         DBPRINT(sc, BCE_INFO_SEND,
7548             "%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
7549             "prod_bseq = 0x%08X\n",
7550             __FUNCTION__, prod, chain_prod, prod_bseq);
7551
7552         /*
7553          * Cycle through each mbuf segment that makes up
7554          * the outgoing frame, gathering the mapping info
7555          * for that segment and creating a tx_bd for
7556          * the mbuf.
7557          */
7558         for (i = 0; i < nsegs ; i++) {
7559
7560                 chain_prod = TX_CHAIN_IDX(prod);
7561                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)]
7562                     [TX_IDX(chain_prod)];
7563
7564                 txbd->tx_bd_haddr_lo =
7565                     htole32(BCE_ADDR_LO(segs[i].ds_addr));
7566                 txbd->tx_bd_haddr_hi =
7567                     htole32(BCE_ADDR_HI(segs[i].ds_addr));
7568                 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
7569                     htole16(segs[i].ds_len);
7570                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
7571                 txbd->tx_bd_flags = htole16(flags);
7572                 prod_bseq += segs[i].ds_len;
7573                 if (i == 0)
7574                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
7575                 prod = NEXT_TX_BD(prod);
7576         }
7577
7578         /* Set the END flag on the last TX buffer descriptor. */
7579         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
7580
7581         DBRUNMSG(BCE_EXTREME_SEND,
7582             bce_dump_tx_chain(sc, debug_prod, nsegs));
7583
7584         /*
7585          * Ensure that the mbuf pointer for this transmission
7586          * is placed at the array index of the last
7587          * descriptor in this chain.  This is done
7588          * because a single map is used for all
7589          * segments of the mbuf and we don't want to
7590          * unload the map before all of the segments
7591          * have been freed.
7592          */
7593         sc->tx_mbuf_ptr[chain_prod] = m0;
7594         sc->used_tx_bd += nsegs;
7595
7596         /* Update some debug statistic counters */
7597         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
7598             sc->tx_hi_watermark = sc->used_tx_bd);
7599         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
7600         DBRUNIF(sc->debug_tx_mbuf_alloc++);
7601
7602         DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
7603
7604         /* prod points to the next free tx_bd at this point. */
7605         sc->tx_prod = prod;
7606         sc->tx_prod_bseq = prod_bseq;
7607
7608         /* Tell the chip about the waiting TX frames. */
7609         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) +
7610             BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
7611         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +
7612             BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
7613
7614 bce_tx_encap_exit:
7615         DBEXIT(BCE_VERBOSE_SEND);
7616         return(rc);
7617 }
7618
7619
7620 /****************************************************************************/
7621 /* Main transmit routine when called from another routine with a lock.      */
7622 /*                                                                          */
7623 /* Returns:                                                                 */
7624 /*   Nothing.                                                               */
7625 /****************************************************************************/
7626 static void
7627 bce_start_locked(struct ifnet *ifp)
7628 {
7629         struct bce_softc *sc = ifp->if_softc;
7630         struct mbuf *m_head = NULL;
7631         int count = 0;
7632         u16 tx_prod, tx_chain_prod;
7633
7634         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7635
7636         BCE_LOCK_ASSERT(sc);
7637
7638         /* prod points to the next free tx_bd. */
7639         tx_prod = sc->tx_prod;
7640         tx_chain_prod = TX_CHAIN_IDX(tx_prod);
7641
7642         DBPRINT(sc, BCE_INFO_SEND,
7643             "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
7644             "tx_prod_bseq = 0x%08X\n",
7645             __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
7646
7647         /* If there's no link or the transmit queue is empty then just exit. */
7648         if (sc->bce_link_up == FALSE) {
7649                 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
7650                     __FUNCTION__);
7651                 goto bce_start_locked_exit;
7652         }
7653
7654         if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7655                 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
7656                     __FUNCTION__);
7657                 goto bce_start_locked_exit;
7658         }
7659
7660         /*
7661          * Keep adding entries while there is space in the ring.
7662          */
7663         while (sc->used_tx_bd < sc->max_tx_bd) {
7664
7665                 /* Check for any frames to send. */
7666                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
7667
7668                 /* Stop when the transmit queue is empty. */
7669                 if (m_head == NULL)
7670                         break;
7671
7672                 /*
7673                  * Pack the data into the transmit ring. If we
7674                  * don't have room, place the mbuf back at the
7675                  * head of the queue and set the OACTIVE flag
7676                  * to wait for the NIC to drain the chain.
7677                  */
7678                 if (bce_tx_encap(sc, &m_head)) {
7679                         if (m_head != NULL)
7680                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
7681                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
7682                         DBPRINT(sc, BCE_INFO_SEND,
7683                             "TX chain is closed for business! Total "
7684                             "tx_bd used = %d\n", sc->used_tx_bd);
7685                         break;
7686                 }
7687
7688                 count++;
7689
7690                 /* Send a copy of the frame to any BPF listeners. */
7691                 ETHER_BPF_MTAP(ifp, m_head);
7692         }
7693
7694         /* Exit if no packets were dequeued. */
7695         if (count == 0) {
7696                 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were "
7697                     "dequeued\n", __FUNCTION__);
7698                 goto bce_start_locked_exit;
7699         }
7700
7701         DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into "
7702             "send queue.\n", __FUNCTION__, count);
7703
7704         /* Set the tx timeout. */
7705         sc->watchdog_timer = BCE_TX_TIMEOUT;
7706
7707         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
7708         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
7709
7710 bce_start_locked_exit:
7711         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7712         return;
7713 }
7714
7715
7716 /****************************************************************************/
7717 /* Main transmit routine when called from another routine without a lock.   */
7718 /*                                                                          */
7719 /* Returns:                                                                 */
7720 /*   Nothing.                                                               */
7721 /****************************************************************************/
7722 static void
7723 bce_start(struct ifnet *ifp)
7724 {
7725         struct bce_softc *sc = ifp->if_softc;
7726
7727         DBENTER(BCE_VERBOSE_SEND);
7728
7729         BCE_LOCK(sc);
7730         bce_start_locked(ifp);
7731         BCE_UNLOCK(sc);
7732
7733         DBEXIT(BCE_VERBOSE_SEND);
7734 }
7735
7736
7737 /****************************************************************************/
7738 /* Handles any IOCTL calls from the operating system.                       */
7739 /*                                                                          */
7740 /* Returns:                                                                 */
7741 /*   0 for success, positive value for failure.                             */
7742 /****************************************************************************/
7743 static int
7744 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
7745 {
7746         struct bce_softc *sc = ifp->if_softc;
7747         struct ifreq *ifr = (struct ifreq *) data;
7748         struct mii_data *mii;
7749         int mask, error = 0;
7750
7751         DBENTER(BCE_VERBOSE_MISC);
7752
7753         switch(command) {
7754
7755         /* Set the interface MTU. */
7756         case SIOCSIFMTU:
7757                 /* Check that the MTU setting is supported. */
7758                 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
7759                         (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
7760                         error = EINVAL;
7761                         break;
7762                 }
7763
7764                 DBPRINT(sc, BCE_INFO_MISC,
7765                     "SIOCSIFMTU: Changing MTU from %d to %d\n",
7766                     (int) ifp->if_mtu, (int) ifr->ifr_mtu);
7767
7768                 BCE_LOCK(sc);
7769                 ifp->if_mtu = ifr->ifr_mtu;
7770                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7771                         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7772                         bce_init_locked(sc);
7773                 }
7774                 BCE_UNLOCK(sc);
7775                 break;
7776
7777         /* Set interface flags. */
7778         case SIOCSIFFLAGS:
7779                 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n");
7780
7781                 BCE_LOCK(sc);
7782
7783                 /* Check if the interface is up. */
7784                 if (ifp->if_flags & IFF_UP) {
7785                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7786                                 /* Change promiscuous/multicast flags as necessary. */
7787                                 bce_set_rx_mode(sc);
7788                         } else {
7789                                 /* Start the HW */
7790                                 bce_init_locked(sc);
7791                         }
7792                 } else {
7793                         /* The interface is down, check if driver is running. */
7794                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7795                                 bce_stop(sc);
7796
7797                                 /* If MFW is running, restart the controller a bit. */
7798                                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
7799                                         bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
7800                                         bce_chipinit(sc);
7801                                         bce_mgmt_init_locked(sc);
7802                                 }
7803                         }
7804                 }
7805
7806                 BCE_UNLOCK(sc);
7807                 break;
7808
7809         /* Add/Delete multicast address */
7810         case SIOCADDMULTI:
7811         case SIOCDELMULTI:
7812                 DBPRINT(sc, BCE_VERBOSE_MISC,
7813                     "Received SIOCADDMULTI/SIOCDELMULTI\n");
7814
7815                 BCE_LOCK(sc);
7816                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7817                         bce_set_rx_mode(sc);
7818                 BCE_UNLOCK(sc);
7819
7820                 break;
7821
7822         /* Set/Get Interface media */
7823         case SIOCSIFMEDIA:
7824         case SIOCGIFMEDIA:
7825                 DBPRINT(sc, BCE_VERBOSE_MISC,
7826                     "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n");
7827                 if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0)
7828                         error = ifmedia_ioctl(ifp, ifr, &sc->bce_ifmedia,
7829                             command);
7830                 else {
7831                         mii = device_get_softc(sc->bce_miibus);
7832                         error = ifmedia_ioctl(ifp, ifr, &mii->mii_media,
7833                             command);
7834                 }
7835                 break;
7836
7837         /* Set interface capability */
7838         case SIOCSIFCAP:
7839                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
7840                 DBPRINT(sc, BCE_INFO_MISC,
7841                     "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
7842
7843                 /* Toggle the TX checksum capabilities enable flag. */
7844                 if (mask & IFCAP_TXCSUM &&
7845                     ifp->if_capabilities & IFCAP_TXCSUM) {
7846                         ifp->if_capenable ^= IFCAP_TXCSUM;
7847                         if (IFCAP_TXCSUM & ifp->if_capenable)
7848                                 ifp->if_hwassist |= BCE_IF_HWASSIST;
7849                         else
7850                                 ifp->if_hwassist &= ~BCE_IF_HWASSIST;
7851                 }
7852
7853                 /* Toggle the RX checksum capabilities enable flag. */
7854                 if (mask & IFCAP_RXCSUM &&
7855                     ifp->if_capabilities & IFCAP_RXCSUM)
7856                         ifp->if_capenable ^= IFCAP_RXCSUM;
7857
7858                 /* Toggle the TSO capabilities enable flag. */
7859                 if (bce_tso_enable && (mask & IFCAP_TSO4) &&
7860                     ifp->if_capabilities & IFCAP_TSO4) {
7861                         ifp->if_capenable ^= IFCAP_TSO4;
7862                         if (IFCAP_TSO4 & ifp->if_capenable)
7863                                 ifp->if_hwassist |= CSUM_TSO;
7864                         else
7865                                 ifp->if_hwassist &= ~CSUM_TSO;
7866                 }
7867
7868                 if (mask & IFCAP_VLAN_HWCSUM &&
7869                     ifp->if_capabilities & IFCAP_VLAN_HWCSUM)
7870                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
7871
7872                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
7873                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
7874                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
7875                 /*
7876                  * Don't actually disable VLAN tag stripping as
7877                  * management firmware (ASF/IPMI/UMP) requires the
7878                  * feature. If VLAN tag stripping is disabled driver
7879                  * will manually reconstruct the VLAN frame by
7880                  * appending stripped VLAN tag.
7881                  */
7882                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
7883                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) {
7884                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
7885                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
7886                             == 0)
7887                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
7888                 }
7889                 VLAN_CAPABILITIES(ifp);
7890                 break;
7891         default:
7892                 /* We don't know how to handle the IOCTL, pass it on. */
7893                 error = ether_ioctl(ifp, command, data);
7894                 break;
7895         }
7896
7897         DBEXIT(BCE_VERBOSE_MISC);
7898         return(error);
7899 }
7900
7901
7902 /****************************************************************************/
7903 /* Transmit timeout handler.                                                */
7904 /*                                                                          */
7905 /* Returns:                                                                 */
7906 /*   Nothing.                                                               */
7907 /****************************************************************************/
7908 static void
7909 bce_watchdog(struct bce_softc *sc)
7910 {
7911         DBENTER(BCE_EXTREME_SEND);
7912
7913         BCE_LOCK_ASSERT(sc);
7914
7915         /* If the watchdog timer hasn't expired then just exit. */
7916         if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
7917                 goto bce_watchdog_exit;
7918
7919         /* If pause frames are active then don't reset the hardware. */
7920         /* ToDo: Should we reset the timer here? */
7921         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
7922                 goto bce_watchdog_exit;
7923
7924         BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
7925             __FILE__, __LINE__);
7926
7927         DBRUNMSG(BCE_INFO,
7928             bce_dump_driver_state(sc);
7929             bce_dump_status_block(sc);
7930             bce_dump_stats_block(sc);
7931             bce_dump_ftqs(sc);
7932             bce_dump_txp_state(sc, 0);
7933             bce_dump_rxp_state(sc, 0);
7934             bce_dump_tpat_state(sc, 0);
7935             bce_dump_cp_state(sc, 0);
7936             bce_dump_com_state(sc, 0));
7937
7938         DBRUN(bce_breakpoint(sc));
7939
7940         sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7941
7942         bce_init_locked(sc);
7943         sc->bce_ifp->if_oerrors++;
7944
7945 bce_watchdog_exit:
7946         DBEXIT(BCE_EXTREME_SEND);
7947 }
7948
7949
7950 /*
7951  * Interrupt handler.
7952  */
7953 /****************************************************************************/
7954 /* Main interrupt entry point.  Verifies that the controller generated the  */
7955 /* interrupt and then calls a separate routine for handle the various       */
7956 /* interrupt causes (PHY, TX, RX).                                          */
7957 /*                                                                          */
7958 /* Returns:                                                                 */
7959 /*   0 for success, positive value for failure.                             */
7960 /****************************************************************************/
7961 static void
7962 bce_intr(void *xsc)
7963 {
7964         struct bce_softc *sc;
7965         struct ifnet *ifp;
7966         u32 status_attn_bits;
7967         u16 hw_rx_cons, hw_tx_cons;
7968
7969         sc = xsc;
7970         ifp = sc->bce_ifp;
7971
7972         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7973         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
7974         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc));
7975
7976         BCE_LOCK(sc);
7977
7978         DBRUN(sc->interrupts_generated++);
7979
7980         /* Synchnorize before we read from interface's status block */
7981         bus_dmamap_sync(sc->status_tag, sc->status_map,
7982             BUS_DMASYNC_POSTREAD);
7983
7984         /*
7985          * If the hardware status block index
7986          * matches the last value read by the
7987          * driver and we haven't asserted our
7988          * interrupt then there's nothing to do.
7989          */
7990         if ((sc->status_block->status_idx == sc->last_status_idx) &&
7991             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
7992              BCE_PCICFG_MISC_STATUS_INTA_VALUE)) {
7993                 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n",
7994                     __FUNCTION__);
7995                 goto bce_intr_exit;
7996         }
7997
7998         /* Ack the interrupt and stop others from occuring. */
7999         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
8000             BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
8001             BCE_PCICFG_INT_ACK_CMD_MASK_INT);
8002
8003         /* Check if the hardware has finished any work. */
8004         hw_rx_cons = bce_get_hw_rx_cons(sc);
8005         hw_tx_cons = bce_get_hw_tx_cons(sc);
8006
8007         /* Keep processing data as long as there is work to do. */
8008         for (;;) {
8009
8010                 status_attn_bits = sc->status_block->status_attn_bits;
8011
8012                 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control),
8013                     BCE_PRINTF("Simulating unexpected status attention "
8014                     "bit set.");
8015                     sc->unexpected_attention_sim_count++;
8016                     status_attn_bits = status_attn_bits |
8017                     STATUS_ATTN_BITS_PARITY_ERROR);
8018
8019                 /* Was it a link change interrupt? */
8020                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
8021                     (sc->status_block->status_attn_bits_ack &
8022                      STATUS_ATTN_BITS_LINK_STATE)) {
8023                         bce_phy_intr(sc);
8024
8025                         /* Clear transient updates during link state change. */
8026                         REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |
8027                             BCE_HC_COMMAND_COAL_NOW_WO_INT);
8028                         REG_RD(sc, BCE_HC_COMMAND);
8029                 }
8030
8031                 /* If any other attention is asserted, the chip is toast. */
8032                 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
8033                     (sc->status_block->status_attn_bits_ack &
8034                     ~STATUS_ATTN_BITS_LINK_STATE))) {
8035
8036                         sc->unexpected_attention_count++;
8037
8038                         BCE_PRINTF("%s(%d): Fatal attention detected: "
8039                             "0x%08X\n", __FILE__, __LINE__,
8040                             sc->status_block->status_attn_bits);
8041
8042                         DBRUNMSG(BCE_FATAL,
8043                             if (unexpected_attention_sim_control == 0)
8044                                 bce_breakpoint(sc));
8045
8046                         bce_init_locked(sc);
8047                         goto bce_intr_exit;
8048                 }
8049
8050                 /* Check for any completed RX frames. */
8051                 if (hw_rx_cons != sc->hw_rx_cons)
8052                         bce_rx_intr(sc);
8053
8054                 /* Check for any completed TX frames. */
8055                 if (hw_tx_cons != sc->hw_tx_cons)
8056                         bce_tx_intr(sc);
8057
8058                 /* Save status block index value for the next interrupt. */
8059                 sc->last_status_idx = sc->status_block->status_idx;
8060
8061                 /*
8062                  * Prevent speculative reads from getting
8063                  * ahead of the status block.
8064                  */
8065                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
8066                     BUS_SPACE_BARRIER_READ);
8067
8068                 /*
8069                  * If there's no work left then exit the
8070                  * interrupt service routine.
8071                  */
8072                 hw_rx_cons = bce_get_hw_rx_cons(sc);
8073                 hw_tx_cons = bce_get_hw_tx_cons(sc);
8074
8075                 if ((hw_rx_cons == sc->hw_rx_cons) &&
8076                     (hw_tx_cons == sc->hw_tx_cons))
8077                         break;
8078
8079         }
8080
8081         bus_dmamap_sync(sc->status_tag, sc->status_map,
8082             BUS_DMASYNC_PREREAD);
8083
8084         /* Re-enable interrupts. */
8085         bce_enable_intr(sc, 0);
8086
8087         /* Handle any frames that arrived while handling the interrupt. */
8088         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
8089             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
8090                 bce_start_locked(ifp);
8091
8092 bce_intr_exit:
8093         BCE_UNLOCK(sc);
8094
8095         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
8096 }
8097
8098
8099 /****************************************************************************/
8100 /* Programs the various packet receive modes (broadcast and multicast).     */
8101 /*                                                                          */
8102 /* Returns:                                                                 */
8103 /*   Nothing.                                                               */
8104 /****************************************************************************/
8105 static void
8106 bce_set_rx_mode(struct bce_softc *sc)
8107 {
8108         struct ifnet *ifp;
8109         struct ifmultiaddr *ifma;
8110         u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
8111         u32 rx_mode, sort_mode;
8112         int h, i;
8113
8114         DBENTER(BCE_VERBOSE_MISC);
8115
8116         BCE_LOCK_ASSERT(sc);
8117
8118         ifp = sc->bce_ifp;
8119
8120         /* Initialize receive mode default settings. */
8121         rx_mode   = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
8122             BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
8123         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
8124
8125         /*
8126          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
8127          * be enbled.
8128          */
8129         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
8130             (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)))
8131                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
8132
8133         /*
8134          * Check for promiscuous, all multicast, or selected
8135          * multicast address filtering.
8136          */
8137         if (ifp->if_flags & IFF_PROMISC) {
8138                 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n");
8139
8140                 /* Enable promiscuous mode. */
8141                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
8142                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
8143         } else if (ifp->if_flags & IFF_ALLMULTI) {
8144                 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n");
8145
8146                 /* Enable all multicast addresses. */
8147                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
8148                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff);
8149         }
8150                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
8151         } else {
8152                 /* Accept one or more multicast(s). */
8153                 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n");
8154
8155                 if_maddr_rlock(ifp);
8156                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
8157                         if (ifma->ifma_addr->sa_family != AF_LINK)
8158                                 continue;
8159                         h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
8160                             ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
8161                             hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
8162                 }
8163                 if_maddr_runlock(ifp);
8164
8165                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
8166                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
8167
8168                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
8169         }
8170
8171         /* Only make changes if the recive mode has actually changed. */
8172         if (rx_mode != sc->rx_mode) {
8173                 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: "
8174                     "0x%08X\n", rx_mode);
8175
8176                 sc->rx_mode = rx_mode;
8177                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
8178         }
8179
8180         /* Disable and clear the exisitng sort before enabling a new sort. */
8181         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
8182         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
8183         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
8184
8185         DBEXIT(BCE_VERBOSE_MISC);
8186 }
8187
8188
8189 /****************************************************************************/
8190 /* Called periodically to updates statistics from the controllers           */
8191 /* statistics block.                                                        */
8192 /*                                                                          */
8193 /* Returns:                                                                 */
8194 /*   Nothing.                                                               */
8195 /****************************************************************************/
8196 static void
8197 bce_stats_update(struct bce_softc *sc)
8198 {
8199         struct ifnet *ifp;
8200         struct statistics_block *stats;
8201
8202         DBENTER(BCE_EXTREME_MISC);
8203
8204         ifp = sc->bce_ifp;
8205
8206         stats = (struct statistics_block *) sc->stats_block;
8207
8208         /*
8209          * Certain controllers don't report
8210          * carrier sense errors correctly.
8211          * See errata E11_5708CA0_1165.
8212          */
8213         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
8214             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
8215                 ifp->if_oerrors +=
8216                     (u_long) stats->stat_Dot3StatsCarrierSenseErrors;
8217
8218         /*
8219          * Update the sysctl statistics from the
8220          * hardware statistics.
8221          */
8222         sc->stat_IfHCInOctets =
8223             ((u64) stats->stat_IfHCInOctets_hi << 32) +
8224              (u64) stats->stat_IfHCInOctets_lo;
8225
8226         sc->stat_IfHCInBadOctets =
8227             ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
8228              (u64) stats->stat_IfHCInBadOctets_lo;
8229
8230         sc->stat_IfHCOutOctets =
8231             ((u64) stats->stat_IfHCOutOctets_hi << 32) +
8232              (u64) stats->stat_IfHCOutOctets_lo;
8233
8234         sc->stat_IfHCOutBadOctets =
8235             ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
8236              (u64) stats->stat_IfHCOutBadOctets_lo;
8237
8238         sc->stat_IfHCInUcastPkts =
8239             ((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
8240              (u64) stats->stat_IfHCInUcastPkts_lo;
8241
8242         sc->stat_IfHCInMulticastPkts =
8243             ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
8244              (u64) stats->stat_IfHCInMulticastPkts_lo;
8245
8246         sc->stat_IfHCInBroadcastPkts =
8247             ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
8248              (u64) stats->stat_IfHCInBroadcastPkts_lo;
8249
8250         sc->stat_IfHCOutUcastPkts =
8251             ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
8252              (u64) stats->stat_IfHCOutUcastPkts_lo;
8253
8254         sc->stat_IfHCOutMulticastPkts =
8255             ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
8256              (u64) stats->stat_IfHCOutMulticastPkts_lo;
8257
8258         sc->stat_IfHCOutBroadcastPkts =
8259             ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
8260              (u64) stats->stat_IfHCOutBroadcastPkts_lo;
8261
8262         /* ToDo: Preserve counters beyond 32 bits? */
8263         /* ToDo: Read the statistics from auto-clear regs? */
8264
8265         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
8266             stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
8267
8268         sc->stat_Dot3StatsCarrierSenseErrors =
8269             stats->stat_Dot3StatsCarrierSenseErrors;
8270
8271         sc->stat_Dot3StatsFCSErrors =
8272             stats->stat_Dot3StatsFCSErrors;
8273
8274         sc->stat_Dot3StatsAlignmentErrors =
8275             stats->stat_Dot3StatsAlignmentErrors;
8276
8277         sc->stat_Dot3StatsSingleCollisionFrames =
8278             stats->stat_Dot3StatsSingleCollisionFrames;
8279
8280         sc->stat_Dot3StatsMultipleCollisionFrames =
8281             stats->stat_Dot3StatsMultipleCollisionFrames;
8282
8283         sc->stat_Dot3StatsDeferredTransmissions =
8284             stats->stat_Dot3StatsDeferredTransmissions;
8285
8286         sc->stat_Dot3StatsExcessiveCollisions =
8287             stats->stat_Dot3StatsExcessiveCollisions;
8288
8289         sc->stat_Dot3StatsLateCollisions =
8290             stats->stat_Dot3StatsLateCollisions;
8291
8292         sc->stat_EtherStatsCollisions =
8293             stats->stat_EtherStatsCollisions;
8294
8295         sc->stat_EtherStatsFragments =
8296             stats->stat_EtherStatsFragments;
8297
8298         sc->stat_EtherStatsJabbers =
8299             stats->stat_EtherStatsJabbers;
8300
8301         sc->stat_EtherStatsUndersizePkts =
8302             stats->stat_EtherStatsUndersizePkts;
8303
8304         sc->stat_EtherStatsOversizePkts =
8305              stats->stat_EtherStatsOversizePkts;
8306
8307         sc->stat_EtherStatsPktsRx64Octets =
8308             stats->stat_EtherStatsPktsRx64Octets;
8309
8310         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
8311             stats->stat_EtherStatsPktsRx65Octetsto127Octets;
8312
8313         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
8314             stats->stat_EtherStatsPktsRx128Octetsto255Octets;
8315
8316         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
8317             stats->stat_EtherStatsPktsRx256Octetsto511Octets;
8318
8319         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
8320             stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
8321
8322         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
8323             stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
8324
8325         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
8326             stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
8327
8328         sc->stat_EtherStatsPktsTx64Octets =
8329             stats->stat_EtherStatsPktsTx64Octets;
8330
8331         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
8332             stats->stat_EtherStatsPktsTx65Octetsto127Octets;
8333
8334         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
8335             stats->stat_EtherStatsPktsTx128Octetsto255Octets;
8336
8337         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
8338             stats->stat_EtherStatsPktsTx256Octetsto511Octets;
8339
8340         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
8341             stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
8342
8343         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
8344             stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
8345
8346         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
8347             stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
8348
8349         sc->stat_XonPauseFramesReceived =
8350             stats->stat_XonPauseFramesReceived;
8351
8352         sc->stat_XoffPauseFramesReceived =
8353             stats->stat_XoffPauseFramesReceived;
8354
8355         sc->stat_OutXonSent =
8356             stats->stat_OutXonSent;
8357
8358         sc->stat_OutXoffSent =
8359             stats->stat_OutXoffSent;
8360
8361         sc->stat_FlowControlDone =
8362             stats->stat_FlowControlDone;
8363
8364         sc->stat_MacControlFramesReceived =
8365             stats->stat_MacControlFramesReceived;
8366
8367         sc->stat_XoffStateEntered =
8368             stats->stat_XoffStateEntered;
8369
8370         sc->stat_IfInFramesL2FilterDiscards =
8371             stats->stat_IfInFramesL2FilterDiscards;
8372
8373         sc->stat_IfInRuleCheckerDiscards =
8374             stats->stat_IfInRuleCheckerDiscards;
8375
8376         sc->stat_IfInFTQDiscards =
8377             stats->stat_IfInFTQDiscards;
8378
8379         sc->stat_IfInMBUFDiscards =
8380             stats->stat_IfInMBUFDiscards;
8381
8382         sc->stat_IfInRuleCheckerP4Hit =
8383             stats->stat_IfInRuleCheckerP4Hit;
8384
8385         sc->stat_CatchupInRuleCheckerDiscards =
8386             stats->stat_CatchupInRuleCheckerDiscards;
8387
8388         sc->stat_CatchupInFTQDiscards =
8389             stats->stat_CatchupInFTQDiscards;
8390
8391         sc->stat_CatchupInMBUFDiscards =
8392             stats->stat_CatchupInMBUFDiscards;
8393
8394         sc->stat_CatchupInRuleCheckerP4Hit =
8395             stats->stat_CatchupInRuleCheckerP4Hit;
8396
8397         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
8398
8399         /*
8400          * Update the interface statistics from the
8401          * hardware statistics.
8402          */
8403         ifp->if_collisions =
8404             (u_long) sc->stat_EtherStatsCollisions;
8405
8406         /* ToDo: This method loses soft errors. */
8407         ifp->if_ierrors =
8408             (u_long) sc->stat_EtherStatsUndersizePkts +
8409             (u_long) sc->stat_EtherStatsOversizePkts +
8410             (u_long) sc->stat_IfInMBUFDiscards +
8411             (u_long) sc->stat_Dot3StatsAlignmentErrors +
8412             (u_long) sc->stat_Dot3StatsFCSErrors +
8413             (u_long) sc->stat_IfInRuleCheckerDiscards +
8414             (u_long) sc->stat_IfInFTQDiscards +
8415             (u_long) sc->com_no_buffers;
8416
8417         /* ToDo: This method loses soft errors. */
8418         ifp->if_oerrors =
8419             (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
8420             (u_long) sc->stat_Dot3StatsExcessiveCollisions +
8421             (u_long) sc->stat_Dot3StatsLateCollisions;
8422
8423         /* ToDo: Add additional statistics? */
8424
8425         DBEXIT(BCE_EXTREME_MISC);
8426 }
8427
8428
8429 /****************************************************************************/
8430 /* Periodic function to notify the bootcode that the driver is still        */
8431 /* present.                                                                 */
8432 /*                                                                          */
8433 /* Returns:                                                                 */
8434 /*   Nothing.                                                               */
8435 /****************************************************************************/
8436 static void
8437 bce_pulse(void *xsc)
8438 {
8439         struct bce_softc *sc = xsc;
8440         u32 msg;
8441
8442         DBENTER(BCE_EXTREME_MISC);
8443
8444         BCE_LOCK_ASSERT(sc);
8445
8446         /* Tell the firmware that the driver is still running. */
8447         msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
8448         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
8449
8450         /* Update the bootcode condition. */
8451         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
8452
8453         /* Report whether the bootcode still knows the driver is running. */
8454         if (bce_verbose || bootverbose) {
8455                 if (sc->bce_drv_cardiac_arrest == FALSE) {
8456                         if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
8457                                 sc->bce_drv_cardiac_arrest = TRUE;
8458                                 BCE_PRINTF("%s(): Warning: bootcode "
8459                                     "thinks driver is absent! "
8460                                     "(bc_state = 0x%08X)\n",
8461                                     __FUNCTION__, sc->bc_state);
8462                         }
8463                 } else {
8464                         /*
8465                          * Not supported by all bootcode versions.
8466                          * (v5.0.11+ and v5.2.1+)  Older bootcode
8467                          * will require the driver to reset the
8468                          * controller to clear this condition.
8469                          */
8470                         if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
8471                                 sc->bce_drv_cardiac_arrest = FALSE;
8472                                 BCE_PRINTF("%s(): Bootcode found the "
8473                                     "driver pulse! (bc_state = 0x%08X)\n",
8474                                     __FUNCTION__, sc->bc_state);
8475                         }
8476                 }
8477         }
8478
8479
8480         /* Schedule the next pulse. */
8481         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
8482
8483         DBEXIT(BCE_EXTREME_MISC);
8484 }
8485
8486
8487 /****************************************************************************/
8488 /* Periodic function to perform maintenance tasks.                          */
8489 /*                                                                          */
8490 /* Returns:                                                                 */
8491 /*   Nothing.                                                               */
8492 /****************************************************************************/
8493 static void
8494 bce_tick(void *xsc)
8495 {
8496         struct bce_softc *sc = xsc;
8497         struct mii_data *mii;
8498         struct ifnet *ifp;
8499         struct ifmediareq ifmr;
8500
8501         ifp = sc->bce_ifp;
8502
8503         DBENTER(BCE_EXTREME_MISC);
8504
8505         BCE_LOCK_ASSERT(sc);
8506
8507         /* Schedule the next tick. */
8508         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
8509
8510         /* Update the statistics from the hardware statistics block. */
8511         bce_stats_update(sc);
8512
8513         /*
8514          * ToDo: This is a safety measure.  Need to re-evaluate
8515          * high level processing logic and eliminate this code.
8516          */
8517         /* Top off the receive and page chains. */
8518         if (bce_hdr_split == TRUE)
8519                 bce_fill_pg_chain(sc);
8520         bce_fill_rx_chain(sc);
8521
8522         /* Check that chip hasn't hung. */
8523         bce_watchdog(sc);
8524
8525         /* If link is up already up then we're done. */
8526         if (sc->bce_link_up == TRUE)
8527                 goto bce_tick_exit;
8528
8529         /* Link is down.  Check what the PHY's doing. */
8530         if ((sc->bce_phy_flags & BCE_PHY_REMOTE_CAP_FLAG) != 0) {
8531                 bzero(&ifmr, sizeof(ifmr));
8532                 bce_ifmedia_sts_rphy(sc, &ifmr);
8533                 if ((ifmr.ifm_status & (IFM_ACTIVE | IFM_AVALID)) ==
8534                     (IFM_ACTIVE | IFM_AVALID)) {
8535                         sc->bce_link_up = TRUE;
8536                         bce_miibus_statchg(sc->bce_dev);
8537                 }
8538         } else {
8539                 mii = device_get_softc(sc->bce_miibus);
8540                 mii_tick(mii);
8541                 /* Check if the link has come up. */
8542                 if ((mii->mii_media_status & IFM_ACTIVE) &&
8543                     (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
8544                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Link up!\n",
8545                             __FUNCTION__);
8546                         sc->bce_link_up = TRUE;
8547                         if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
8548                             IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
8549                             IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
8550                             (bce_verbose || bootverbose))
8551                                 BCE_PRINTF("Gigabit link up!\n");
8552                 }
8553
8554         }
8555         if (sc->bce_link_up == TRUE) {
8556                 /* Now that link is up, handle any outstanding TX traffic. */
8557                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
8558                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
8559                             "pending TX traffic.\n", __FUNCTION__);
8560                         bce_start_locked(ifp);
8561                 }
8562         }
8563
8564 bce_tick_exit:
8565         DBEXIT(BCE_EXTREME_MISC);
8566         return;
8567 }
8568
8569 static void
8570 bce_fw_cap_init(struct bce_softc *sc)
8571 {
8572         u32 ack, cap, link;
8573
8574         ack = 0;
8575         cap = bce_shmem_rd(sc, BCE_FW_CAP_MB);
8576         if ((cap & BCE_FW_CAP_SIGNATURE_MAGIC_MASK) !=
8577             BCE_FW_CAP_SIGNATURE_MAGIC)
8578                 return;
8579         if ((cap & (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN)) ==
8580             (BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN))
8581                 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8582                     BCE_FW_CAP_MFW_KEEP_VLAN | BCE_FW_CAP_BC_KEEP_VLAN;
8583         if ((sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) != 0 &&
8584             (cap & BCE_FW_CAP_REMOTE_PHY_CAP) != 0) {
8585                 sc->bce_phy_flags &= ~BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8586                 sc->bce_phy_flags |= BCE_PHY_REMOTE_CAP_FLAG;
8587                 link = bce_shmem_rd(sc, BCE_LINK_STATUS);
8588                 if ((link & BCE_LINK_STATUS_SERDES_LINK) != 0)
8589                         sc->bce_phy_flags |= BCE_PHY_REMOTE_PORT_FIBER_FLAG;
8590                 ack |= BCE_DRV_ACK_CAP_SIGNATURE_MAGIC |
8591                     BCE_FW_CAP_REMOTE_PHY_CAP;
8592         }
8593
8594         if (ack != 0)
8595                 bce_shmem_wr(sc, BCE_DRV_ACK_CAP_MB, ack);
8596 }
8597
8598
8599 #ifdef BCE_DEBUG
8600 /****************************************************************************/
8601 /* Allows the driver state to be dumped through the sysctl interface.       */
8602 /*                                                                          */
8603 /* Returns:                                                                 */
8604 /*   0 for success, positive value for failure.                             */
8605 /****************************************************************************/
8606 static int
8607 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
8608 {
8609         int error;
8610         int result;
8611         struct bce_softc *sc;
8612
8613         result = -1;
8614         error = sysctl_handle_int(oidp, &result, 0, req);
8615
8616         if (error || !req->newptr)
8617                 return (error);
8618
8619         if (result == 1) {
8620                 sc = (struct bce_softc *)arg1;
8621                 bce_dump_driver_state(sc);
8622         }
8623
8624         return error;
8625 }
8626
8627
8628 /****************************************************************************/
8629 /* Allows the hardware state to be dumped through the sysctl interface.     */
8630 /*                                                                          */
8631 /* Returns:                                                                 */
8632 /*   0 for success, positive value for failure.                             */
8633 /****************************************************************************/
8634 static int
8635 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
8636 {
8637         int error;
8638         int result;
8639         struct bce_softc *sc;
8640
8641         result = -1;
8642         error = sysctl_handle_int(oidp, &result, 0, req);
8643
8644         if (error || !req->newptr)
8645                 return (error);
8646
8647         if (result == 1) {
8648                 sc = (struct bce_softc *)arg1;
8649                 bce_dump_hw_state(sc);
8650         }
8651
8652         return error;
8653 }
8654
8655
8656 /****************************************************************************/
8657 /* Allows the status block to be dumped through the sysctl interface.       */
8658 /*                                                                          */
8659 /* Returns:                                                                 */
8660 /*   0 for success, positive value for failure.                             */
8661 /****************************************************************************/
8662 static int
8663 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS)
8664 {
8665         int error;
8666         int result;
8667         struct bce_softc *sc;
8668
8669         result = -1;
8670         error = sysctl_handle_int(oidp, &result, 0, req);
8671
8672         if (error || !req->newptr)
8673                 return (error);
8674
8675         if (result == 1) {
8676                 sc = (struct bce_softc *)arg1;
8677                 bce_dump_status_block(sc);
8678         }
8679
8680         return error;
8681 }
8682
8683
8684 /****************************************************************************/
8685 /* Allows the stats block to be dumped through the sysctl interface.        */
8686 /*                                                                          */
8687 /* Returns:                                                                 */
8688 /*   0 for success, positive value for failure.                             */
8689 /****************************************************************************/
8690 static int
8691 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS)
8692 {
8693         int error;
8694         int result;
8695         struct bce_softc *sc;
8696
8697         result = -1;
8698         error = sysctl_handle_int(oidp, &result, 0, req);
8699
8700         if (error || !req->newptr)
8701                 return (error);
8702
8703         if (result == 1) {
8704                 sc = (struct bce_softc *)arg1;
8705                 bce_dump_stats_block(sc);
8706         }
8707
8708         return error;
8709 }
8710
8711
8712 /****************************************************************************/
8713 /* Allows the stat counters to be cleared without unloading/reloading the   */
8714 /* driver.                                                                  */
8715 /*                                                                          */
8716 /* Returns:                                                                 */
8717 /*   0 for success, positive value for failure.                             */
8718 /****************************************************************************/
8719 static int
8720 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS)
8721 {
8722         int error;
8723         int result;
8724         struct bce_softc *sc;
8725
8726         result = -1;
8727         error = sysctl_handle_int(oidp, &result, 0, req);
8728
8729         if (error || !req->newptr)
8730                 return (error);
8731
8732         if (result == 1) {
8733                 sc = (struct bce_softc *)arg1;
8734                 struct statistics_block *stats;
8735
8736                 stats = (struct statistics_block *) sc->stats_block;
8737                 bzero(stats, sizeof(struct statistics_block));
8738
8739                 /* Clear the internal H/W statistics counters. */
8740                 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
8741
8742                 /* Reset the driver maintained statistics. */
8743                 sc->interrupts_rx =
8744                     sc->interrupts_tx = 0;
8745                 sc->tso_frames_requested =
8746                     sc->tso_frames_completed =
8747                     sc->tso_frames_failed = 0;
8748                 sc->rx_empty_count =
8749                     sc->tx_full_count = 0;
8750                 sc->rx_low_watermark = USABLE_RX_BD_ALLOC;
8751                 sc->tx_hi_watermark = 0;
8752                 sc->l2fhdr_error_count =
8753                     sc->l2fhdr_error_sim_count = 0;
8754                 sc->mbuf_alloc_failed_count =
8755                     sc->mbuf_alloc_failed_sim_count = 0;
8756                 sc->dma_map_addr_rx_failed_count =
8757                     sc->dma_map_addr_tx_failed_count = 0;
8758                 sc->mbuf_frag_count = 0;
8759                 sc->csum_offload_tcp_udp =
8760                     sc->csum_offload_ip = 0;
8761                 sc->vlan_tagged_frames_rcvd =
8762                     sc->vlan_tagged_frames_stripped = 0;
8763                 sc->split_header_frames_rcvd =
8764                     sc->split_header_tcp_frames_rcvd = 0;
8765
8766                 /* Clear firmware maintained statistics. */
8767                 REG_WR_IND(sc, 0x120084, 0);
8768         }
8769
8770         return error;
8771 }
8772
8773
8774 /****************************************************************************/
8775 /* Allows the shared memory contents to be dumped through the sysctl  .     */
8776 /* interface.                                                               */
8777 /*                                                                          */
8778 /* Returns:                                                                 */
8779 /*   0 for success, positive value for failure.                             */
8780 /****************************************************************************/
8781 static int
8782 bce_sysctl_shmem_state(SYSCTL_HANDLER_ARGS)
8783 {
8784         int error;
8785         int result;
8786         struct bce_softc *sc;
8787
8788         result = -1;
8789         error = sysctl_handle_int(oidp, &result, 0, req);
8790
8791         if (error || !req->newptr)
8792                 return (error);
8793
8794         if (result == 1) {
8795                 sc = (struct bce_softc *)arg1;
8796                 bce_dump_shmem_state(sc);
8797         }
8798
8799         return error;
8800 }
8801
8802
8803 /****************************************************************************/
8804 /* Allows the bootcode state to be dumped through the sysctl interface.     */
8805 /*                                                                          */
8806 /* Returns:                                                                 */
8807 /*   0 for success, positive value for failure.                             */
8808 /****************************************************************************/
8809 static int
8810 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS)
8811 {
8812         int error;
8813         int result;
8814         struct bce_softc *sc;
8815
8816         result = -1;
8817         error = sysctl_handle_int(oidp, &result, 0, req);
8818
8819         if (error || !req->newptr)
8820                 return (error);
8821
8822         if (result == 1) {
8823                 sc = (struct bce_softc *)arg1;
8824                 bce_dump_bc_state(sc);
8825         }
8826
8827         return error;
8828 }
8829
8830
8831 /****************************************************************************/
8832 /* Provides a sysctl interface to allow dumping the RX BD chain.            */
8833 /*                                                                          */
8834 /* Returns:                                                                 */
8835 /*   0 for success, positive value for failure.                             */
8836 /****************************************************************************/
8837 static int
8838 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS)
8839 {
8840         int error;
8841         int result;
8842         struct bce_softc *sc;
8843
8844         result = -1;
8845         error = sysctl_handle_int(oidp, &result, 0, req);
8846
8847         if (error || !req->newptr)
8848                 return (error);
8849
8850         if (result == 1) {
8851                 sc = (struct bce_softc *)arg1;
8852                 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD_ALLOC);
8853         }
8854
8855         return error;
8856 }
8857
8858
8859 /****************************************************************************/
8860 /* Provides a sysctl interface to allow dumping the RX MBUF chain.          */
8861 /*                                                                          */
8862 /* Returns:                                                                 */
8863 /*   0 for success, positive value for failure.                             */
8864 /****************************************************************************/
8865 static int
8866 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS)
8867 {
8868         int error;
8869         int result;
8870         struct bce_softc *sc;
8871
8872         result = -1;
8873         error = sysctl_handle_int(oidp, &result, 0, req);
8874
8875         if (error || !req->newptr)
8876                 return (error);
8877
8878         if (result == 1) {
8879                 sc = (struct bce_softc *)arg1;
8880                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
8881         }
8882
8883         return error;
8884 }
8885
8886
8887 /****************************************************************************/
8888 /* Provides a sysctl interface to allow dumping the TX chain.               */
8889 /*                                                                          */
8890 /* Returns:                                                                 */
8891 /*   0 for success, positive value for failure.                             */
8892 /****************************************************************************/
8893 static int
8894 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
8895 {
8896         int error;
8897         int result;
8898         struct bce_softc *sc;
8899
8900         result = -1;
8901         error = sysctl_handle_int(oidp, &result, 0, req);
8902
8903         if (error || !req->newptr)
8904                 return (error);
8905
8906         if (result == 1) {
8907                 sc = (struct bce_softc *)arg1;
8908                 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD_ALLOC);
8909         }
8910
8911         return error;
8912 }
8913
8914
8915 /****************************************************************************/
8916 /* Provides a sysctl interface to allow dumping the page chain.             */
8917 /*                                                                          */
8918 /* Returns:                                                                 */
8919 /*   0 for success, positive value for failure.                             */
8920 /****************************************************************************/
8921 static int
8922 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS)
8923 {
8924         int error;
8925         int result;
8926         struct bce_softc *sc;
8927
8928         result = -1;
8929         error = sysctl_handle_int(oidp, &result, 0, req);
8930
8931         if (error || !req->newptr)
8932                 return (error);
8933
8934         if (result == 1) {
8935                 sc = (struct bce_softc *)arg1;
8936                 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD_ALLOC);
8937         }
8938
8939         return error;
8940 }
8941
8942 /****************************************************************************/
8943 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in  */
8944 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8945 /*                                                                          */
8946 /* Returns:                                                                 */
8947 /*   0 for success, positive value for failure.                             */
8948 /****************************************************************************/
8949 static int
8950 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)
8951 {
8952         struct bce_softc *sc = (struct bce_softc *)arg1;
8953         int error;
8954         u32 result;
8955         u32 val[1];
8956         u8 *data = (u8 *) val;
8957
8958         result = -1;
8959         error = sysctl_handle_int(oidp, &result, 0, req);
8960         if (error || (req->newptr == NULL))
8961                 return (error);
8962
8963         error = bce_nvram_read(sc, result, data, 4);
8964
8965         BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
8966
8967         return (error);
8968 }
8969
8970
8971 /****************************************************************************/
8972 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
8973 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
8974 /*                                                                          */
8975 /* Returns:                                                                 */
8976 /*   0 for success, positive value for failure.                             */
8977 /****************************************************************************/
8978 static int
8979 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
8980 {
8981         struct bce_softc *sc = (struct bce_softc *)arg1;
8982         int error;
8983         u32 val, result;
8984
8985         result = -1;
8986         error = sysctl_handle_int(oidp, &result, 0, req);
8987         if (error || (req->newptr == NULL))
8988                 return (error);
8989
8990         /* Make sure the register is accessible. */
8991         if (result < 0x8000) {
8992                 val = REG_RD(sc, result);
8993                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8994         } else if (result < 0x0280000) {
8995                 val = REG_RD_IND(sc, result);
8996                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8997         }
8998
8999         return (error);
9000 }
9001
9002
9003 /****************************************************************************/
9004 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
9005 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
9006 /*                                                                          */
9007 /* Returns:                                                                 */
9008 /*   0 for success, positive value for failure.                             */
9009 /****************************************************************************/
9010 static int
9011 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
9012 {
9013         struct bce_softc *sc;
9014         device_t dev;
9015         int error, result;
9016         u16 val;
9017
9018         result = -1;
9019         error = sysctl_handle_int(oidp, &result, 0, req);
9020         if (error || (req->newptr == NULL))
9021                 return (error);
9022
9023         /* Make sure the register is accessible. */
9024         if (result < 0x20) {
9025                 sc = (struct bce_softc *)arg1;
9026                 dev = sc->bce_dev;
9027                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
9028                 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
9029         }
9030         return (error);
9031 }
9032
9033
9034 /****************************************************************************/
9035 /* Provides a sysctl interface for dumping the nvram contents.              */
9036 /* DO NOT ENABLE ON PRODUCTION SYSTEMS!                                     */
9037 /*                                                                          */
9038 /* Returns:                                                                 */
9039 /*   0 for success, positive errno for failure.                             */
9040 /****************************************************************************/
9041 static int
9042 bce_sysctl_nvram_dump(SYSCTL_HANDLER_ARGS)
9043 {
9044         struct bce_softc *sc = (struct bce_softc *)arg1;
9045         int error, i;
9046
9047         if (sc->nvram_buf == NULL)
9048                 sc->nvram_buf = malloc(sc->bce_flash_size,
9049                                     M_TEMP, M_ZERO | M_WAITOK);
9050
9051         error = 0;
9052         if (req->oldlen == sc->bce_flash_size) {
9053                 for (i = 0; i < sc->bce_flash_size && error == 0; i++)
9054                         error = bce_nvram_read(sc, i, &sc->nvram_buf[i], 1);
9055         }
9056
9057         if (error == 0)
9058                 error = SYSCTL_OUT(req, sc->nvram_buf, sc->bce_flash_size);
9059
9060         return error;
9061 }
9062
9063 #ifdef BCE_NVRAM_WRITE_SUPPORT
9064 /****************************************************************************/
9065 /* Provides a sysctl interface for writing to nvram.                        */
9066 /* DO NOT ENABLE ON PRODUCTION SYSTEMS!                                     */
9067 /*                                                                          */
9068 /* Returns:                                                                 */
9069 /*   0 for success, positive errno for failure.                             */
9070 /****************************************************************************/
9071 static int
9072 bce_sysctl_nvram_write(SYSCTL_HANDLER_ARGS)
9073 {
9074         struct bce_softc *sc = (struct bce_softc *)arg1;
9075         int error;
9076
9077         if (sc->nvram_buf == NULL)
9078                 sc->nvram_buf = malloc(sc->bce_flash_size,
9079                                     M_TEMP, M_ZERO | M_WAITOK);
9080         else
9081                 bzero(sc->nvram_buf, sc->bce_flash_size);
9082
9083         error = SYSCTL_IN(req, sc->nvram_buf, sc->bce_flash_size);
9084         if (error == 0)
9085                 return (error);
9086
9087         if (req->newlen == sc->bce_flash_size)
9088                 error = bce_nvram_write(sc, 0, sc->nvram_buf,
9089                             sc->bce_flash_size);
9090
9091
9092         return error;
9093 }
9094 #endif
9095
9096
9097 /****************************************************************************/
9098 /* Provides a sysctl interface to allow reading a CID.                      */
9099 /*                                                                          */
9100 /* Returns:                                                                 */
9101 /*   0 for success, positive value for failure.                             */
9102 /****************************************************************************/
9103 static int
9104 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)
9105 {
9106         struct bce_softc *sc;
9107         int error, result;
9108
9109         result = -1;
9110         error = sysctl_handle_int(oidp, &result, 0, req);
9111         if (error || (req->newptr == NULL))
9112                 return (error);
9113
9114         /* Make sure the register is accessible. */
9115         if (result <= TX_CID) {
9116                 sc = (struct bce_softc *)arg1;
9117                 bce_dump_ctx(sc, result);
9118         }
9119
9120         return (error);
9121 }
9122
9123
9124 /****************************************************************************/
9125 /* Provides a sysctl interface to forcing the driver to dump state and      */
9126 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
9127 /*                                                                          */
9128 /* Returns:                                                                 */
9129 /*   0 for success, positive value for failure.                             */
9130 /****************************************************************************/
9131 static int
9132 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
9133 {
9134         int error;
9135         int result;
9136         struct bce_softc *sc;
9137
9138         result = -1;
9139         error = sysctl_handle_int(oidp, &result, 0, req);
9140
9141         if (error || !req->newptr)
9142                 return (error);
9143
9144         if (result == 1) {
9145                 sc = (struct bce_softc *)arg1;
9146                 bce_breakpoint(sc);
9147         }
9148
9149         return error;
9150 }
9151 #endif
9152
9153 /****************************************************************************/
9154 /* Adds any sysctl parameters for tuning or debugging purposes.             */
9155 /*                                                                          */
9156 /* Returns:                                                                 */
9157 /*   0 for success, positive value for failure.                             */
9158 /****************************************************************************/
9159 static void
9160 bce_add_sysctls(struct bce_softc *sc)
9161 {
9162         struct sysctl_ctx_list *ctx;
9163         struct sysctl_oid_list *children;
9164
9165         DBENTER(BCE_VERBOSE_MISC);
9166
9167         ctx = device_get_sysctl_ctx(sc->bce_dev);
9168         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
9169
9170 #ifdef BCE_DEBUG
9171         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9172             "l2fhdr_error_sim_control",
9173             CTLFLAG_RW, &l2fhdr_error_sim_control,
9174             0, "Debug control to force l2fhdr errors");
9175
9176         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9177             "l2fhdr_error_sim_count",
9178             CTLFLAG_RD, &sc->l2fhdr_error_sim_count,
9179             0, "Number of simulated l2_fhdr errors");
9180 #endif
9181
9182         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9183             "l2fhdr_error_count",
9184             CTLFLAG_RD, &sc->l2fhdr_error_count,
9185             0, "Number of l2_fhdr errors");
9186
9187 #ifdef BCE_DEBUG
9188         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9189             "mbuf_alloc_failed_sim_control",
9190             CTLFLAG_RW, &mbuf_alloc_failed_sim_control,
9191             0, "Debug control to force mbuf allocation failures");
9192
9193         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9194             "mbuf_alloc_failed_sim_count",
9195             CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count,
9196             0, "Number of simulated mbuf cluster allocation failures");
9197 #endif
9198
9199         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9200             "mbuf_alloc_failed_count",
9201             CTLFLAG_RD, &sc->mbuf_alloc_failed_count,
9202             0, "Number of mbuf allocation failures");
9203
9204         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9205             "mbuf_frag_count",
9206             CTLFLAG_RD, &sc->mbuf_frag_count,
9207             0, "Number of fragmented mbufs");
9208
9209 #ifdef BCE_DEBUG
9210         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9211             "dma_map_addr_failed_sim_control",
9212             CTLFLAG_RW, &dma_map_addr_failed_sim_control,
9213             0, "Debug control to force DMA mapping failures");
9214
9215         /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */
9216         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9217             "dma_map_addr_failed_sim_count",
9218             CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count,
9219             0, "Number of simulated DMA mapping failures");
9220
9221 #endif
9222
9223         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9224             "dma_map_addr_rx_failed_count",
9225             CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count,
9226             0, "Number of RX DMA mapping failures");
9227
9228         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9229             "dma_map_addr_tx_failed_count",
9230             CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count,
9231             0, "Number of TX DMA mapping failures");
9232
9233 #ifdef BCE_DEBUG
9234         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9235             "unexpected_attention_sim_control",
9236             CTLFLAG_RW, &unexpected_attention_sim_control,
9237             0, "Debug control to simulate unexpected attentions");
9238
9239         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9240             "unexpected_attention_sim_count",
9241             CTLFLAG_RW, &sc->unexpected_attention_sim_count,
9242             0, "Number of simulated unexpected attentions");
9243 #endif
9244
9245         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9246             "unexpected_attention_count",
9247             CTLFLAG_RW, &sc->unexpected_attention_count,
9248             0, "Number of unexpected attentions");
9249
9250 #ifdef BCE_DEBUG
9251         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9252             "debug_bootcode_running_failure",
9253             CTLFLAG_RW, &bootcode_running_failure_sim_control,
9254             0, "Debug control to force bootcode running failures");
9255
9256         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9257             "rx_low_watermark",
9258             CTLFLAG_RD, &sc->rx_low_watermark,
9259             0, "Lowest level of free rx_bd's");
9260
9261         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9262             "rx_empty_count",
9263             CTLFLAG_RD, &sc->rx_empty_count,
9264             "Number of times the RX chain was empty");
9265
9266         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
9267             "tx_hi_watermark",
9268             CTLFLAG_RD, &sc->tx_hi_watermark,
9269             0, "Highest level of used tx_bd's");
9270
9271         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9272             "tx_full_count",
9273             CTLFLAG_RD, &sc->tx_full_count,
9274             "Number of times the TX chain was full");
9275
9276         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9277             "tso_frames_requested",
9278             CTLFLAG_RD, &sc->tso_frames_requested,
9279             "Number of TSO frames requested");
9280
9281         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9282             "tso_frames_completed",
9283             CTLFLAG_RD, &sc->tso_frames_completed,
9284             "Number of TSO frames completed");
9285
9286         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9287             "tso_frames_failed",
9288             CTLFLAG_RD, &sc->tso_frames_failed,
9289             "Number of TSO frames failed");
9290
9291         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9292             "csum_offload_ip",
9293             CTLFLAG_RD, &sc->csum_offload_ip,
9294             "Number of IP checksum offload frames");
9295
9296         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9297             "csum_offload_tcp_udp",
9298             CTLFLAG_RD, &sc->csum_offload_tcp_udp,
9299             "Number of TCP/UDP checksum offload frames");
9300
9301         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9302             "vlan_tagged_frames_rcvd",
9303             CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd,
9304             "Number of VLAN tagged frames received");
9305
9306         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9307             "vlan_tagged_frames_stripped",
9308             CTLFLAG_RD, &sc->vlan_tagged_frames_stripped,
9309             "Number of VLAN tagged frames stripped");
9310
9311         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9312             "interrupts_rx",
9313             CTLFLAG_RD, &sc->interrupts_rx,
9314             "Number of RX interrupts");
9315
9316         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9317             "interrupts_tx",
9318             CTLFLAG_RD, &sc->interrupts_tx,
9319             "Number of TX interrupts");
9320
9321         if (bce_hdr_split == TRUE) {
9322                 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9323                     "split_header_frames_rcvd",
9324                     CTLFLAG_RD, &sc->split_header_frames_rcvd,
9325                     "Number of split header frames received");
9326
9327                 SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9328                     "split_header_tcp_frames_rcvd",
9329                     CTLFLAG_RD, &sc->split_header_tcp_frames_rcvd,
9330                     "Number of split header TCP frames received");
9331         }
9332
9333         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9334             "nvram_dump", CTLTYPE_OPAQUE | CTLFLAG_RD,
9335             (void *)sc, 0,
9336             bce_sysctl_nvram_dump, "S", "");
9337
9338 #ifdef BCE_NVRAM_WRITE_SUPPORT
9339         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9340             "nvram_write", CTLTYPE_OPAQUE | CTLFLAG_WR,
9341             (void *)sc, 0,
9342             bce_sysctl_nvram_write, "S", "");
9343 #endif
9344 #endif /* BCE_DEBUG */
9345
9346         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9347             "stat_IfHcInOctets",
9348             CTLFLAG_RD, &sc->stat_IfHCInOctets,
9349             "Bytes received");
9350
9351         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9352             "stat_IfHCInBadOctets",
9353             CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
9354             "Bad bytes received");
9355
9356         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9357             "stat_IfHCOutOctets",
9358             CTLFLAG_RD, &sc->stat_IfHCOutOctets,
9359             "Bytes sent");
9360
9361         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9362             "stat_IfHCOutBadOctets",
9363             CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
9364             "Bad bytes sent");
9365
9366         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9367             "stat_IfHCInUcastPkts",
9368             CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
9369             "Unicast packets received");
9370
9371         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9372             "stat_IfHCInMulticastPkts",
9373             CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
9374             "Multicast packets received");
9375
9376         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9377             "stat_IfHCInBroadcastPkts",
9378             CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
9379             "Broadcast packets received");
9380
9381         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9382             "stat_IfHCOutUcastPkts",
9383             CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
9384             "Unicast packets sent");
9385
9386         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9387             "stat_IfHCOutMulticastPkts",
9388             CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
9389             "Multicast packets sent");
9390
9391         SYSCTL_ADD_QUAD(ctx, children, OID_AUTO,
9392             "stat_IfHCOutBroadcastPkts",
9393             CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
9394             "Broadcast packets sent");
9395
9396         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9397             "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
9398             CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
9399             0, "Internal MAC transmit errors");
9400
9401         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9402             "stat_Dot3StatsCarrierSenseErrors",
9403             CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
9404             0, "Carrier sense errors");
9405
9406         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9407             "stat_Dot3StatsFCSErrors",
9408             CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
9409             0, "Frame check sequence errors");
9410
9411         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9412             "stat_Dot3StatsAlignmentErrors",
9413             CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
9414             0, "Alignment errors");
9415
9416         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9417             "stat_Dot3StatsSingleCollisionFrames",
9418             CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
9419             0, "Single Collision Frames");
9420
9421         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9422             "stat_Dot3StatsMultipleCollisionFrames",
9423             CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
9424             0, "Multiple Collision Frames");
9425
9426         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9427             "stat_Dot3StatsDeferredTransmissions",
9428             CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
9429             0, "Deferred Transmissions");
9430
9431         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9432             "stat_Dot3StatsExcessiveCollisions",
9433             CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
9434             0, "Excessive Collisions");
9435
9436         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9437             "stat_Dot3StatsLateCollisions",
9438             CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
9439             0, "Late Collisions");
9440
9441         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9442             "stat_EtherStatsCollisions",
9443             CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
9444             0, "Collisions");
9445
9446         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9447             "stat_EtherStatsFragments",
9448             CTLFLAG_RD, &sc->stat_EtherStatsFragments,
9449             0, "Fragments");
9450
9451         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9452             "stat_EtherStatsJabbers",
9453             CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
9454             0, "Jabbers");
9455
9456         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9457             "stat_EtherStatsUndersizePkts",
9458             CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
9459             0, "Undersize packets");
9460
9461         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9462             "stat_EtherStatsOversizePkts",
9463             CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts,
9464             0, "stat_EtherStatsOversizePkts");
9465
9466         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9467             "stat_EtherStatsPktsRx64Octets",
9468             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
9469             0, "Bytes received in 64 byte packets");
9470
9471         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9472             "stat_EtherStatsPktsRx65Octetsto127Octets",
9473             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
9474             0, "Bytes received in 65 to 127 byte packets");
9475
9476         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9477             "stat_EtherStatsPktsRx128Octetsto255Octets",
9478             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
9479             0, "Bytes received in 128 to 255 byte packets");
9480
9481         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9482             "stat_EtherStatsPktsRx256Octetsto511Octets",
9483             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
9484             0, "Bytes received in 256 to 511 byte packets");
9485
9486         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9487             "stat_EtherStatsPktsRx512Octetsto1023Octets",
9488             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
9489             0, "Bytes received in 512 to 1023 byte packets");
9490
9491         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9492             "stat_EtherStatsPktsRx1024Octetsto1522Octets",
9493             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
9494             0, "Bytes received in 1024 t0 1522 byte packets");
9495
9496         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9497             "stat_EtherStatsPktsRx1523Octetsto9022Octets",
9498             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
9499             0, "Bytes received in 1523 to 9022 byte packets");
9500
9501         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9502             "stat_EtherStatsPktsTx64Octets",
9503             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
9504             0, "Bytes sent in 64 byte packets");
9505
9506         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9507             "stat_EtherStatsPktsTx65Octetsto127Octets",
9508             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
9509             0, "Bytes sent in 65 to 127 byte packets");
9510
9511         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9512             "stat_EtherStatsPktsTx128Octetsto255Octets",
9513             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
9514             0, "Bytes sent in 128 to 255 byte packets");
9515
9516         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9517             "stat_EtherStatsPktsTx256Octetsto511Octets",
9518             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
9519             0, "Bytes sent in 256 to 511 byte packets");
9520
9521         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9522             "stat_EtherStatsPktsTx512Octetsto1023Octets",
9523             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
9524             0, "Bytes sent in 512 to 1023 byte packets");
9525
9526         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9527             "stat_EtherStatsPktsTx1024Octetsto1522Octets",
9528             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
9529             0, "Bytes sent in 1024 to 1522 byte packets");
9530
9531         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9532             "stat_EtherStatsPktsTx1523Octetsto9022Octets",
9533             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
9534             0, "Bytes sent in 1523 to 9022 byte packets");
9535
9536         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9537             "stat_XonPauseFramesReceived",
9538             CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
9539             0, "XON pause frames receved");
9540
9541         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9542             "stat_XoffPauseFramesReceived",
9543             CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
9544             0, "XOFF pause frames received");
9545
9546         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9547             "stat_OutXonSent",
9548             CTLFLAG_RD, &sc->stat_OutXonSent,
9549             0, "XON pause frames sent");
9550
9551         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9552             "stat_OutXoffSent",
9553             CTLFLAG_RD, &sc->stat_OutXoffSent,
9554             0, "XOFF pause frames sent");
9555
9556         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9557             "stat_FlowControlDone",
9558             CTLFLAG_RD, &sc->stat_FlowControlDone,
9559             0, "Flow control done");
9560
9561         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9562             "stat_MacControlFramesReceived",
9563             CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
9564             0, "MAC control frames received");
9565
9566         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9567             "stat_XoffStateEntered",
9568             CTLFLAG_RD, &sc->stat_XoffStateEntered,
9569             0, "XOFF state entered");
9570
9571         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9572             "stat_IfInFramesL2FilterDiscards",
9573             CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
9574             0, "Received L2 packets discarded");
9575
9576         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9577             "stat_IfInRuleCheckerDiscards",
9578             CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
9579             0, "Received packets discarded by rule");
9580
9581         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9582             "stat_IfInFTQDiscards",
9583             CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
9584             0, "Received packet FTQ discards");
9585
9586         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9587             "stat_IfInMBUFDiscards",
9588             CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
9589             0, "Received packets discarded due to lack "
9590             "of controller buffer memory");
9591
9592         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9593             "stat_IfInRuleCheckerP4Hit",
9594             CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
9595             0, "Received packets rule checker hits");
9596
9597         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9598             "stat_CatchupInRuleCheckerDiscards",
9599             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
9600             0, "Received packets discarded in Catchup path");
9601
9602         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9603             "stat_CatchupInFTQDiscards",
9604             CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
9605             0, "Received packets discarded in FTQ in Catchup path");
9606
9607         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9608             "stat_CatchupInMBUFDiscards",
9609             CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
9610             0, "Received packets discarded in controller "
9611             "buffer memory in Catchup path");
9612
9613         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9614             "stat_CatchupInRuleCheckerP4Hit",
9615             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
9616             0, "Received packets rule checker hits in Catchup path");
9617
9618         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
9619             "com_no_buffers",
9620             CTLFLAG_RD, &sc->com_no_buffers,
9621             0, "Valid packets received but no RX buffers available");
9622
9623 #ifdef BCE_DEBUG
9624         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9625             "driver_state", CTLTYPE_INT | CTLFLAG_RW,
9626             (void *)sc, 0,
9627             bce_sysctl_driver_state, "I", "Drive state information");
9628
9629         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9630             "hw_state", CTLTYPE_INT | CTLFLAG_RW,
9631             (void *)sc, 0,
9632             bce_sysctl_hw_state, "I", "Hardware state information");
9633
9634         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9635             "status_block", CTLTYPE_INT | CTLFLAG_RW,
9636             (void *)sc, 0,
9637             bce_sysctl_status_block, "I", "Dump status block");
9638
9639         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9640             "stats_block", CTLTYPE_INT | CTLFLAG_RW,
9641             (void *)sc, 0,
9642             bce_sysctl_stats_block, "I", "Dump statistics block");
9643
9644         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9645             "stats_clear", CTLTYPE_INT | CTLFLAG_RW,
9646             (void *)sc, 0,
9647             bce_sysctl_stats_clear, "I", "Clear statistics block");
9648
9649         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9650             "shmem_state", CTLTYPE_INT | CTLFLAG_RW,
9651             (void *)sc, 0,
9652             bce_sysctl_shmem_state, "I", "Shared memory state information");
9653
9654         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9655             "bc_state", CTLTYPE_INT | CTLFLAG_RW,
9656             (void *)sc, 0,
9657             bce_sysctl_bc_state, "I", "Bootcode state information");
9658
9659         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9660             "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW,
9661             (void *)sc, 0,
9662             bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain");
9663
9664         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9665             "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW,
9666             (void *)sc, 0,
9667             bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain");
9668
9669         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9670             "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
9671             (void *)sc, 0,
9672             bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
9673
9674         if (bce_hdr_split == TRUE) {
9675                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9676                     "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW,
9677                     (void *)sc, 0,
9678                     bce_sysctl_dump_pg_chain, "I", "Dump page chain");
9679         }
9680
9681         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9682             "dump_ctx", CTLTYPE_INT | CTLFLAG_RW,
9683             (void *)sc, 0,
9684             bce_sysctl_dump_ctx, "I", "Dump context memory");
9685
9686         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9687             "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
9688             (void *)sc, 0,
9689             bce_sysctl_breakpoint, "I", "Driver breakpoint");
9690
9691         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9692             "reg_read", CTLTYPE_INT | CTLFLAG_RW,
9693             (void *)sc, 0,
9694             bce_sysctl_reg_read, "I", "Register read");
9695
9696         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9697             "nvram_read", CTLTYPE_INT | CTLFLAG_RW,
9698             (void *)sc, 0,
9699             bce_sysctl_nvram_read, "I", "NVRAM read");
9700
9701         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
9702             "phy_read", CTLTYPE_INT | CTLFLAG_RW,
9703             (void *)sc, 0,
9704             bce_sysctl_phy_read, "I", "PHY register read");
9705
9706 #endif
9707
9708         DBEXIT(BCE_VERBOSE_MISC);
9709 }
9710
9711
9712 /****************************************************************************/
9713 /* BCE Debug Routines                                                       */
9714 /****************************************************************************/
9715 #ifdef BCE_DEBUG
9716
9717 /****************************************************************************/
9718 /* Freezes the controller to allow for a cohesive state dump.               */
9719 /*                                                                          */
9720 /* Returns:                                                                 */
9721 /*   Nothing.                                                               */
9722 /****************************************************************************/
9723 static __attribute__ ((noinline)) void
9724 bce_freeze_controller(struct bce_softc *sc)
9725 {
9726         u32 val;
9727         val = REG_RD(sc, BCE_MISC_COMMAND);
9728         val |= BCE_MISC_COMMAND_DISABLE_ALL;
9729         REG_WR(sc, BCE_MISC_COMMAND, val);
9730 }
9731
9732
9733 /****************************************************************************/
9734 /* Unfreezes the controller after a freeze operation.  This may not always  */
9735 /* work and the controller will require a reset!                            */
9736 /*                                                                          */
9737 /* Returns:                                                                 */
9738 /*   Nothing.                                                               */
9739 /****************************************************************************/
9740 static __attribute__ ((noinline)) void
9741 bce_unfreeze_controller(struct bce_softc *sc)
9742 {
9743         u32 val;
9744         val = REG_RD(sc, BCE_MISC_COMMAND);
9745         val |= BCE_MISC_COMMAND_ENABLE_ALL;
9746         REG_WR(sc, BCE_MISC_COMMAND, val);
9747 }
9748
9749
9750 /****************************************************************************/
9751 /* Prints out Ethernet frame information from an mbuf.                      */
9752 /*                                                                          */
9753 /* Partially decode an Ethernet frame to look at some important headers.    */
9754 /*                                                                          */
9755 /* Returns:                                                                 */
9756 /*   Nothing.                                                               */
9757 /****************************************************************************/
9758 static __attribute__ ((noinline)) void
9759 bce_dump_enet(struct bce_softc *sc, struct mbuf *m)
9760 {
9761         struct ether_vlan_header *eh;
9762         u16 etype;
9763         int ehlen;
9764         struct ip *ip;
9765         struct tcphdr *th;
9766         struct udphdr *uh;
9767         struct arphdr *ah;
9768
9769         BCE_PRINTF(
9770             "-----------------------------"
9771             " Frame Decode "
9772             "-----------------------------\n");
9773
9774         eh = mtod(m, struct ether_vlan_header *);
9775
9776         /* Handle VLAN encapsulation if present. */
9777         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
9778                 etype = ntohs(eh->evl_proto);
9779                 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
9780         } else {
9781                 etype = ntohs(eh->evl_encap_proto);
9782                 ehlen = ETHER_HDR_LEN;
9783         }
9784
9785         /* ToDo: Add VLAN output. */
9786         BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n",
9787             eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen);
9788
9789         switch (etype) {
9790         case ETHERTYPE_IP:
9791                 ip = (struct ip *)(m->m_data + ehlen);
9792                 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, "
9793                     "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n",
9794                     ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
9795                     ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum));
9796
9797                 switch (ip->ip_p) {
9798                 case IPPROTO_TCP:
9799                         th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9800                         BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = "
9801                             "%d bytes, flags = 0x%b, csum = 0x%04X\n",
9802                             ntohs(th->th_dport), ntohs(th->th_sport),
9803                             (th->th_off << 2), th->th_flags,
9804                             "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST"
9805                             "\02SYN\01FIN", ntohs(th->th_sum));
9806                         break;
9807                 case IPPROTO_UDP:
9808                         uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9809                         BCE_PRINTF("-udp: dest = %d, src = %d, len = %d "
9810                             "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport),
9811                             ntohs(uh->uh_sport), ntohs(uh->uh_ulen),
9812                             ntohs(uh->uh_sum));
9813                         break;
9814                 case IPPROTO_ICMP:
9815                         BCE_PRINTF("icmp:\n");
9816                         break;
9817                 default:
9818                         BCE_PRINTF("----: Other IP protocol.\n");
9819                         }
9820                 break;
9821         case ETHERTYPE_IPV6:
9822                 BCE_PRINTF("ipv6: No decode supported.\n");
9823                 break;
9824         case ETHERTYPE_ARP:
9825                 BCE_PRINTF("-arp: ");
9826                 ah = (struct arphdr *) (m->m_data + ehlen);
9827                 switch (ntohs(ah->ar_op)) {
9828                 case ARPOP_REVREQUEST:
9829                         printf("reverse ARP request\n");
9830                         break;
9831                 case ARPOP_REVREPLY:
9832                         printf("reverse ARP reply\n");
9833                         break;
9834                 case ARPOP_REQUEST:
9835                         printf("ARP request\n");
9836                         break;
9837                 case ARPOP_REPLY:
9838                         printf("ARP reply\n");
9839                         break;
9840                 default:
9841                         printf("other ARP operation\n");
9842                 }
9843                 break;
9844         default:
9845                 BCE_PRINTF("----: Other protocol.\n");
9846         }
9847
9848         BCE_PRINTF(
9849                 "-----------------------------"
9850                 "--------------"
9851                 "-----------------------------\n");
9852 }
9853
9854
9855 /****************************************************************************/
9856 /* Prints out information about an mbuf.                                    */
9857 /*                                                                          */
9858 /* Returns:                                                                 */
9859 /*   Nothing.                                                               */
9860 /****************************************************************************/
9861 static __attribute__ ((noinline)) void
9862 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
9863 {
9864         struct mbuf *mp = m;
9865
9866         if (m == NULL) {
9867                 BCE_PRINTF("mbuf: null pointer\n");
9868                 return;
9869         }
9870
9871         while (mp) {
9872                 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, "
9873                     "m_data = %p\n", mp, mp->m_len, mp->m_flags,
9874                     "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data);
9875
9876                 if (mp->m_flags & M_PKTHDR) {
9877                         BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
9878                             "csum_flags = %b\n", mp->m_pkthdr.len,
9879                             mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG"
9880                             "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG"
9881                             "\22M_PROMISC\23M_NOFREE",
9882                             mp->m_pkthdr.csum_flags,
9883                             "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
9884                             "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
9885                             "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
9886                             "\14CSUM_PSEUDO_HDR");
9887                 }
9888
9889                 if (mp->m_flags & M_EXT) {
9890                         BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
9891                             mp->m_ext.ext_buf, mp->m_ext.ext_size);
9892                         switch (mp->m_ext.ext_type) {
9893                         case EXT_CLUSTER:
9894                                 printf("EXT_CLUSTER\n"); break;
9895                         case EXT_SFBUF:
9896                                 printf("EXT_SFBUF\n"); break;
9897                         case EXT_JUMBO9:
9898                                 printf("EXT_JUMBO9\n"); break;
9899                         case EXT_JUMBO16:
9900                                 printf("EXT_JUMBO16\n"); break;
9901                         case EXT_PACKET:
9902                                 printf("EXT_PACKET\n"); break;
9903                         case EXT_MBUF:
9904                                 printf("EXT_MBUF\n"); break;
9905                         case EXT_NET_DRV:
9906                                 printf("EXT_NET_DRV\n"); break;
9907                         case EXT_MOD_TYPE:
9908                                 printf("EXT_MDD_TYPE\n"); break;
9909                         case EXT_DISPOSABLE:
9910                                 printf("EXT_DISPOSABLE\n"); break;
9911                         case EXT_EXTREF:
9912                                 printf("EXT_EXTREF\n"); break;
9913                         default:
9914                                 printf("UNKNOWN\n");
9915                         }
9916                 }
9917
9918                 mp = mp->m_next;
9919         }
9920 }
9921
9922
9923 /****************************************************************************/
9924 /* Prints out the mbufs in the TX mbuf chain.                               */
9925 /*                                                                          */
9926 /* Returns:                                                                 */
9927 /*   Nothing.                                                               */
9928 /****************************************************************************/
9929 static __attribute__ ((noinline)) void
9930 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9931 {
9932         struct mbuf *m;
9933
9934         BCE_PRINTF(
9935                 "----------------------------"
9936                 "  tx mbuf data  "
9937                 "----------------------------\n");
9938
9939         for (int i = 0; i < count; i++) {
9940                 m = sc->tx_mbuf_ptr[chain_prod];
9941                 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod);
9942                 bce_dump_mbuf(sc, m);
9943                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
9944         }
9945
9946         BCE_PRINTF(
9947                 "----------------------------"
9948                 "----------------"
9949                 "----------------------------\n");
9950 }
9951
9952
9953 /****************************************************************************/
9954 /* Prints out the mbufs in the RX mbuf chain.                               */
9955 /*                                                                          */
9956 /* Returns:                                                                 */
9957 /*   Nothing.                                                               */
9958 /****************************************************************************/
9959 static __attribute__ ((noinline)) void
9960 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9961 {
9962         struct mbuf *m;
9963
9964         BCE_PRINTF(
9965                 "----------------------------"
9966                 "  rx mbuf data  "
9967                 "----------------------------\n");
9968
9969         for (int i = 0; i < count; i++) {
9970                 m = sc->rx_mbuf_ptr[chain_prod];
9971                 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
9972                 bce_dump_mbuf(sc, m);
9973                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
9974         }
9975
9976
9977         BCE_PRINTF(
9978                 "----------------------------"
9979                 "----------------"
9980                 "----------------------------\n");
9981 }
9982
9983
9984 /****************************************************************************/
9985 /* Prints out the mbufs in the mbuf page chain.                             */
9986 /*                                                                          */
9987 /* Returns:                                                                 */
9988 /*   Nothing.                                                               */
9989 /****************************************************************************/
9990 static __attribute__ ((noinline)) void
9991 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9992 {
9993         struct mbuf *m;
9994
9995         BCE_PRINTF(
9996                 "----------------------------"
9997                 "  pg mbuf data  "
9998                 "----------------------------\n");
9999
10000         for (int i = 0; i < count; i++) {
10001                 m = sc->pg_mbuf_ptr[chain_prod];
10002                 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod);
10003                 bce_dump_mbuf(sc, m);
10004                 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod));
10005         }
10006
10007
10008         BCE_PRINTF(
10009                 "----------------------------"
10010                 "----------------"
10011                 "----------------------------\n");
10012 }
10013
10014
10015 /****************************************************************************/
10016 /* Prints out a tx_bd structure.                                            */
10017 /*                                                                          */
10018 /* Returns:                                                                 */
10019 /*   Nothing.                                                               */
10020 /****************************************************************************/
10021 static __attribute__ ((noinline)) void
10022 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
10023 {
10024         int i = 0;
10025
10026         if (idx > MAX_TX_BD_ALLOC)
10027                 /* Index out of range. */
10028                 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
10029         else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
10030                 /* TX Chain page pointer. */
10031                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
10032                     "pointer\n", idx, txbd->tx_bd_haddr_hi,
10033                     txbd->tx_bd_haddr_lo);
10034         else {
10035                 /* Normal tx_bd entry. */
10036                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
10037                     "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = "
10038                     "0x%04X (", idx, txbd->tx_bd_haddr_hi,
10039                     txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes,
10040                     txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
10041
10042                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) {
10043                         if (i>0)
10044                                 printf("|");
10045                         printf("CONN_FAULT");
10046                         i++;
10047                 }
10048
10049                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) {
10050                         if (i>0)
10051                                 printf("|");
10052                         printf("TCP_UDP_CKSUM");
10053                         i++;
10054                 }
10055
10056                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) {
10057                         if (i>0)
10058                                 printf("|");
10059                         printf("IP_CKSUM");
10060                         i++;
10061                 }
10062
10063                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) {
10064                         if (i>0)
10065                                 printf("|");
10066                         printf("VLAN");
10067                         i++;
10068                 }
10069
10070                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) {
10071                         if (i>0)
10072                                 printf("|");
10073                         printf("COAL_NOW");
10074                         i++;
10075                 }
10076
10077                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) {
10078                         if (i>0)
10079                                 printf("|");
10080                         printf("DONT_GEN_CRC");
10081                         i++;
10082                 }
10083
10084                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) {
10085                         if (i>0)
10086                                 printf("|");
10087                         printf("START");
10088                         i++;
10089                 }
10090
10091                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) {
10092                         if (i>0)
10093                                 printf("|");
10094                         printf("END");
10095                         i++;
10096                 }
10097
10098                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) {
10099                         if (i>0)
10100                                 printf("|");
10101                         printf("LSO");
10102                         i++;
10103                 }
10104
10105                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) {
10106                         if (i>0)
10107                                 printf("|");
10108                         printf("SW_OPTION=%d", ((txbd->tx_bd_flags &
10109                             TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++;
10110                 }
10111
10112                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) {
10113                         if (i>0)
10114                                 printf("|");
10115                         printf("SW_FLAGS");
10116                         i++;
10117                 }
10118
10119                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) {
10120                         if (i>0)
10121                                 printf("|");
10122                         printf("SNAP)");
10123                 } else {
10124                         printf(")\n");
10125                 }
10126         }
10127 }
10128
10129
10130 /****************************************************************************/
10131 /* Prints out a rx_bd structure.                                            */
10132 /*                                                                          */
10133 /* Returns:                                                                 */
10134 /*   Nothing.                                                               */
10135 /****************************************************************************/
10136 static __attribute__ ((noinline)) void
10137 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
10138 {
10139         if (idx > MAX_RX_BD_ALLOC)
10140                 /* Index out of range. */
10141                 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
10142         else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
10143                 /* RX Chain page pointer. */
10144                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
10145                     "pointer\n", idx, rxbd->rx_bd_haddr_hi,
10146                     rxbd->rx_bd_haddr_lo);
10147         else
10148                 /* Normal rx_bd entry. */
10149                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
10150                     "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi,
10151                     rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len,
10152                     rxbd->rx_bd_flags);
10153 }
10154
10155
10156 /****************************************************************************/
10157 /* Prints out a rx_bd structure in the page chain.                          */
10158 /*                                                                          */
10159 /* Returns:                                                                 */
10160 /*   Nothing.                                                               */
10161 /****************************************************************************/
10162 static __attribute__ ((noinline)) void
10163 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
10164 {
10165         if (idx > MAX_PG_BD_ALLOC)
10166                 /* Index out of range. */
10167                 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
10168         else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
10169                 /* Page Chain page pointer. */
10170                 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
10171                         idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
10172         else
10173                 /* Normal rx_bd entry. */
10174                 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
10175                         "flags = 0x%08X\n", idx,
10176                         pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
10177                         pgbd->rx_bd_len, pgbd->rx_bd_flags);
10178 }
10179
10180
10181 /****************************************************************************/
10182 /* Prints out a l2_fhdr structure.                                          */
10183 /*                                                                          */
10184 /* Returns:                                                                 */
10185 /*   Nothing.                                                               */
10186 /****************************************************************************/
10187 static __attribute__ ((noinline)) void
10188 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
10189 {
10190         BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
10191                 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
10192                 "tcp_udp_xsum = 0x%04X\n", idx,
10193                 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
10194                 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
10195                 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
10196 }
10197
10198
10199 /****************************************************************************/
10200 /* Prints out context memory info.  (Only useful for CID 0 to 16.)          */
10201 /*                                                                          */
10202 /* Returns:                                                                 */
10203 /*   Nothing.                                                               */
10204 /****************************************************************************/
10205 static __attribute__ ((noinline)) void
10206 bce_dump_ctx(struct bce_softc *sc, u16 cid)
10207 {
10208         if (cid > TX_CID) {
10209                 BCE_PRINTF(" Unknown CID\n");
10210                 return;
10211         }
10212
10213         BCE_PRINTF(
10214             "----------------------------"
10215             "    CTX Data    "
10216             "----------------------------\n");
10217
10218         BCE_PRINTF("     0x%04X - (CID) Context ID\n", cid);
10219
10220         if (cid == RX_CID) {
10221                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
10222                    "producer index\n",
10223                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX));
10224                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host "
10225                     "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10226                     BCE_L2CTX_RX_HOST_BSEQ));
10227                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
10228                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ));
10229                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
10230                     "descriptor address\n",
10231                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI));
10232                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
10233                     "descriptor address\n",
10234                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO));
10235                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer "
10236                     "index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10237                     BCE_L2CTX_RX_NX_BDIDX));
10238                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
10239                     "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10240                     BCE_L2CTX_RX_HOST_PG_BDIDX));
10241                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
10242                     "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid),
10243                     BCE_L2CTX_RX_PG_BUF_SIZE));
10244                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
10245                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10246                     BCE_L2CTX_RX_NX_PG_BDHADDR_HI));
10247                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
10248                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
10249                     BCE_L2CTX_RX_NX_PG_BDHADDR_LO));
10250                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
10251                     "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10252                     BCE_L2CTX_RX_NX_PG_BDIDX));
10253         } else if (cid == TX_CID) {
10254                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10255                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
10256                             CTX_RD(sc, GET_CID_ADDR(cid),
10257                             BCE_L2CTX_TX_TYPE_XI));
10258                         BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx "
10259                             "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid),
10260                             BCE_L2CTX_TX_CMD_TYPE_XI));
10261                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) "
10262                             "h/w buffer descriptor address\n",
10263                             CTX_RD(sc, GET_CID_ADDR(cid),
10264                             BCE_L2CTX_TX_TBDR_BHADDR_HI_XI));
10265                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) "
10266                             "h/w buffer descriptor address\n",
10267                             CTX_RD(sc, GET_CID_ADDR(cid),
10268                             BCE_L2CTX_TX_TBDR_BHADDR_LO_XI));
10269                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) "
10270                             "host producer index\n",
10271                             CTX_RD(sc, GET_CID_ADDR(cid),
10272                             BCE_L2CTX_TX_HOST_BIDX_XI));
10273                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) "
10274                             "host byte sequence\n",
10275                             CTX_RD(sc, GET_CID_ADDR(cid),
10276                             BCE_L2CTX_TX_HOST_BSEQ_XI));
10277                 } else {
10278                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
10279                             CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE));
10280                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
10281                             CTX_RD(sc, GET_CID_ADDR(cid),
10282                             BCE_L2CTX_TX_CMD_TYPE));
10283                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) "
10284                             "h/w buffer descriptor address\n",
10285                             CTX_RD(sc, GET_CID_ADDR(cid),
10286                             BCE_L2CTX_TX_TBDR_BHADDR_HI));
10287                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) "
10288                             "h/w buffer descriptor address\n",
10289                             CTX_RD(sc, GET_CID_ADDR(cid),
10290                             BCE_L2CTX_TX_TBDR_BHADDR_LO));
10291                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host "
10292                             "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
10293                             BCE_L2CTX_TX_HOST_BIDX));
10294                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
10295                             "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
10296                             BCE_L2CTX_TX_HOST_BSEQ));
10297                 }
10298         }
10299
10300         BCE_PRINTF(
10301            "----------------------------"
10302            "    Raw CTX     "
10303            "----------------------------\n");
10304
10305         for (int i = 0x0; i < 0x300; i += 0x10) {
10306                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
10307                    CTX_RD(sc, GET_CID_ADDR(cid), i),
10308                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
10309                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
10310                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
10311         }
10312
10313
10314         BCE_PRINTF(
10315            "----------------------------"
10316            "----------------"
10317            "----------------------------\n");
10318 }
10319
10320
10321 /****************************************************************************/
10322 /* Prints out the FTQ data.                                                 */
10323 /*                                                                          */
10324 /* Returns:                                                                */
10325 /*   Nothing.                                                               */
10326 /****************************************************************************/
10327 static __attribute__ ((noinline)) void
10328 bce_dump_ftqs(struct bce_softc *sc)
10329 {
10330         u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
10331
10332         BCE_PRINTF(
10333             "----------------------------"
10334             "    FTQ Data    "
10335             "----------------------------\n");
10336
10337         BCE_PRINTF("   FTQ    Command    Control   Depth_Now  "
10338             "Max_Depth  Valid_Cnt \n");
10339         BCE_PRINTF(" ------- ---------- ---------- ---------- "
10340             "---------- ----------\n");
10341
10342         /* Setup the generic statistic counters for the FTQ valid count. */
10343         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
10344             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT  << 16) |
10345             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT   <<  8) |
10346             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT);
10347         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10348
10349         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT  << 24) |
10350             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT  << 16) |
10351             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT <<  8) |
10352             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT);
10353         REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
10354
10355         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT  << 24) |
10356             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT  << 16) |
10357             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT   <<  8) |
10358             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT);
10359         REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
10360
10361         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT   << 24) |
10362             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT  << 16) |
10363             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT  <<  8) |
10364             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT);
10365         REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
10366
10367         /* Input queue to the Receive Lookup state machine */
10368         cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
10369         ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
10370         cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
10371         max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
10372         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10373         BCE_PRINTF(" RLUP    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10374             cmd, ctl, cur_depth, max_depth, valid_cnt);
10375
10376         /* Input queue to the Receive Processor */
10377         cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
10378         ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
10379         cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
10380         max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
10381         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10382         BCE_PRINTF(" RXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10383             cmd, ctl, cur_depth, max_depth, valid_cnt);
10384
10385         /* Input queue to the Recevie Processor */
10386         cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
10387         ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
10388         cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
10389         max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
10390         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10391         BCE_PRINTF(" RXPC    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10392             cmd, ctl, cur_depth, max_depth, valid_cnt);
10393
10394         /* Input queue to the Receive Virtual to Physical state machine */
10395         cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
10396         ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
10397         cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
10398         max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
10399         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10400         BCE_PRINTF(" RV2PP   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10401             cmd, ctl, cur_depth, max_depth, valid_cnt);
10402
10403         /* Input queue to the Recevie Virtual to Physical state machine */
10404         cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
10405         ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
10406         cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
10407         max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
10408         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
10409         BCE_PRINTF(" RV2PM   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10410             cmd, ctl, cur_depth, max_depth, valid_cnt);
10411
10412         /* Input queue to the Receive Virtual to Physical state machine */
10413         cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
10414         ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
10415         cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
10416         max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
10417         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
10418         BCE_PRINTF(" RV2PT   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10419             cmd, ctl, cur_depth, max_depth, valid_cnt);
10420
10421         /* Input queue to the Receive DMA state machine */
10422         cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
10423         ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
10424         cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10425         max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10426         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
10427         BCE_PRINTF(" RDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10428             cmd, ctl, cur_depth, max_depth, valid_cnt);
10429
10430         /* Input queue to the Transmit Scheduler state machine */
10431         cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
10432         ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
10433         cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
10434         max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
10435         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
10436         BCE_PRINTF(" TSCH    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10437             cmd, ctl, cur_depth, max_depth, valid_cnt);
10438
10439         /* Input queue to the Transmit Buffer Descriptor state machine */
10440         cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
10441         ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
10442         cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
10443         max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
10444         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
10445         BCE_PRINTF(" TBDR    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10446             cmd, ctl, cur_depth, max_depth, valid_cnt);
10447
10448         /* Input queue to the Transmit Processor */
10449         cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
10450         ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
10451         cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
10452         max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
10453         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
10454         BCE_PRINTF(" TXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10455             cmd, ctl, cur_depth, max_depth, valid_cnt);
10456
10457         /* Input queue to the Transmit DMA state machine */
10458         cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
10459         ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
10460         cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
10461         max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
10462         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
10463         BCE_PRINTF(" TDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10464             cmd, ctl, cur_depth, max_depth, valid_cnt);
10465
10466         /* Input queue to the Transmit Patch-Up Processor */
10467         cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
10468         ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
10469         cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
10470         max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
10471         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
10472         BCE_PRINTF(" TPAT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10473             cmd, ctl, cur_depth, max_depth, valid_cnt);
10474
10475         /* Input queue to the Transmit Assembler state machine */
10476         cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
10477         ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
10478         cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
10479         max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
10480         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
10481         BCE_PRINTF(" TAS     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10482             cmd, ctl, cur_depth, max_depth, valid_cnt);
10483
10484         /* Input queue to the Completion Processor */
10485         cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
10486         ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
10487         cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
10488         max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
10489         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
10490         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10491             cmd, ctl, cur_depth, max_depth, valid_cnt);
10492
10493         /* Input queue to the Completion Processor */
10494         cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
10495         ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
10496         cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
10497         max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
10498         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
10499         BCE_PRINTF(" COMT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10500             cmd, ctl, cur_depth, max_depth, valid_cnt);
10501
10502         /* Input queue to the Completion Processor */
10503         cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
10504         ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
10505         cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
10506         max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
10507         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
10508         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10509             cmd, ctl, cur_depth, max_depth, valid_cnt);
10510
10511         /* Setup the generic statistic counters for the FTQ valid count. */
10512         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT  << 16) |
10513             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT  <<  8) |
10514             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT);
10515
10516         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
10517                 val = val |
10518                     (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI <<
10519                      24);
10520         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
10521
10522         /* Input queue to the Management Control Processor */
10523         cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
10524         ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
10525         cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10526         max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10527         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
10528         BCE_PRINTF(" MCP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10529             cmd, ctl, cur_depth, max_depth, valid_cnt);
10530
10531         /* Input queue to the Command Processor */
10532         cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
10533         ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
10534         cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
10535         max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
10536         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
10537         BCE_PRINTF(" CP      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10538             cmd, ctl, cur_depth, max_depth, valid_cnt);
10539
10540         /* Input queue to the Completion Scheduler state machine */
10541         cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
10542         ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
10543         cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
10544         max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
10545         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
10546         BCE_PRINTF(" CS      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10547             cmd, ctl, cur_depth, max_depth, valid_cnt);
10548
10549         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
10550                 /* Input queue to the RV2P Command Scheduler */
10551                 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);
10552                 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);
10553                 cur_depth = (ctl & 0xFFC00000) >> 22;
10554                 max_depth = (ctl & 0x003FF000) >> 12;
10555                 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
10556                 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
10557                     cmd, ctl, cur_depth, max_depth, valid_cnt);
10558         }
10559
10560         BCE_PRINTF(
10561             "----------------------------"
10562             "----------------"
10563             "----------------------------\n");
10564 }
10565
10566
10567 /****************************************************************************/
10568 /* Prints out the TX chain.                                                 */
10569 /*                                                                          */
10570 /* Returns:                                                                 */
10571 /*   Nothing.                                                               */
10572 /****************************************************************************/
10573 static __attribute__ ((noinline)) void
10574 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
10575 {
10576         struct tx_bd *txbd;
10577
10578         /* First some info about the tx_bd chain structure. */
10579         BCE_PRINTF(
10580             "----------------------------"
10581             "  tx_bd  chain  "
10582             "----------------------------\n");
10583
10584         BCE_PRINTF("page size      = 0x%08X, tx chain pages        = 0x%08X\n",
10585             (u32) BCM_PAGE_SIZE, (u32) sc->tx_pages);
10586         BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
10587             (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE);
10588         BCE_PRINTF("total tx_bd    = 0x%08X\n", (u32) TOTAL_TX_BD_ALLOC);
10589
10590         BCE_PRINTF(
10591             "----------------------------"
10592             "   tx_bd data   "
10593             "----------------------------\n");
10594
10595         /* Now print out a decoded list of TX buffer descriptors. */
10596         for (int i = 0; i < count; i++) {
10597                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
10598                 bce_dump_txbd(sc, tx_prod, txbd);
10599                 tx_prod++;
10600         }
10601
10602         BCE_PRINTF(
10603             "----------------------------"
10604             "----------------"
10605             "----------------------------\n");
10606 }
10607
10608
10609 /****************************************************************************/
10610 /* Prints out the RX chain.                                                 */
10611 /*                                                                          */
10612 /* Returns:                                                                 */
10613 /*   Nothing.                                                               */
10614 /****************************************************************************/
10615 static __attribute__ ((noinline)) void
10616 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count)
10617 {
10618         struct rx_bd *rxbd;
10619
10620         /* First some info about the rx_bd chain structure. */
10621         BCE_PRINTF(
10622             "----------------------------"
10623             "  rx_bd  chain  "
10624             "----------------------------\n");
10625
10626         BCE_PRINTF("page size      = 0x%08X, rx chain pages        = 0x%08X\n",
10627             (u32) BCM_PAGE_SIZE, (u32) sc->rx_pages);
10628
10629         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10630             (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE);
10631
10632         BCE_PRINTF("total rx_bd    = 0x%08X\n", (u32) TOTAL_RX_BD_ALLOC);
10633
10634         BCE_PRINTF(
10635             "----------------------------"
10636             "   rx_bd data   "
10637             "----------------------------\n");
10638
10639         /* Now print out the rx_bd's themselves. */
10640         for (int i = 0; i < count; i++) {
10641                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
10642                 bce_dump_rxbd(sc, rx_prod, rxbd);
10643                 rx_prod = RX_CHAIN_IDX(rx_prod + 1);
10644         }
10645
10646         BCE_PRINTF(
10647             "----------------------------"
10648             "----------------"
10649             "----------------------------\n");
10650 }
10651
10652
10653 /****************************************************************************/
10654 /* Prints out the page chain.                                               */
10655 /*                                                                          */
10656 /* Returns:                                                                 */
10657 /*   Nothing.                                                               */
10658 /****************************************************************************/
10659 static __attribute__ ((noinline)) void
10660 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
10661 {
10662         struct rx_bd *pgbd;
10663
10664         /* First some info about the page chain structure. */
10665         BCE_PRINTF(
10666             "----------------------------"
10667             "   page chain   "
10668             "----------------------------\n");
10669
10670         BCE_PRINTF("page size      = 0x%08X, pg chain pages        = 0x%08X\n",
10671             (u32) BCM_PAGE_SIZE, (u32) sc->pg_pages);
10672
10673         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
10674             (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE);
10675
10676         BCE_PRINTF("total pg_bd             = 0x%08X\n", (u32) TOTAL_PG_BD_ALLOC);
10677
10678         BCE_PRINTF(
10679             "----------------------------"
10680             "   page data    "
10681             "----------------------------\n");
10682
10683         /* Now print out the rx_bd's themselves. */
10684         for (int i = 0; i < count; i++) {
10685                 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)];
10686                 bce_dump_pgbd(sc, pg_prod, pgbd);
10687                 pg_prod = PG_CHAIN_IDX(pg_prod + 1);
10688         }
10689
10690         BCE_PRINTF(
10691             "----------------------------"
10692             "----------------"
10693             "----------------------------\n");
10694 }
10695
10696
10697 #define BCE_PRINT_RX_CONS(arg)                                          \
10698 if (sblk->status_rx_quick_consumer_index##arg)                          \
10699         BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n",      \
10700             sblk->status_rx_quick_consumer_index##arg, (u16)            \
10701             RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg),    \
10702             arg);
10703
10704
10705 #define BCE_PRINT_TX_CONS(arg)                                          \
10706 if (sblk->status_tx_quick_consumer_index##arg)                          \
10707         BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n",      \
10708             sblk->status_tx_quick_consumer_index##arg, (u16)            \
10709             TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg),    \
10710             arg);
10711
10712 /****************************************************************************/
10713 /* Prints out the status block from host memory.                            */
10714 /*                                                                          */
10715 /* Returns:                                                                 */
10716 /*   Nothing.                                                               */
10717 /****************************************************************************/
10718 static __attribute__ ((noinline)) void
10719 bce_dump_status_block(struct bce_softc *sc)
10720 {
10721         struct status_block *sblk;
10722
10723         sblk = sc->status_block;
10724
10725         BCE_PRINTF(
10726             "----------------------------"
10727             "  Status Block  "
10728             "----------------------------\n");
10729
10730         /* Theses indices are used for normal L2 drivers. */
10731         BCE_PRINTF("    0x%08X - attn_bits\n",
10732             sblk->status_attn_bits);
10733
10734         BCE_PRINTF("    0x%08X - attn_bits_ack\n",
10735             sblk->status_attn_bits_ack);
10736
10737         BCE_PRINT_RX_CONS(0);
10738         BCE_PRINT_TX_CONS(0)
10739
10740         BCE_PRINTF("        0x%04X - status_idx\n", sblk->status_idx);
10741
10742         /* Theses indices are not used for normal L2 drivers. */
10743         BCE_PRINT_RX_CONS(1);   BCE_PRINT_RX_CONS(2);   BCE_PRINT_RX_CONS(3);
10744         BCE_PRINT_RX_CONS(4);   BCE_PRINT_RX_CONS(5);   BCE_PRINT_RX_CONS(6);
10745         BCE_PRINT_RX_CONS(7);   BCE_PRINT_RX_CONS(8);   BCE_PRINT_RX_CONS(9);
10746         BCE_PRINT_RX_CONS(10);  BCE_PRINT_RX_CONS(11);  BCE_PRINT_RX_CONS(12);
10747         BCE_PRINT_RX_CONS(13);  BCE_PRINT_RX_CONS(14);  BCE_PRINT_RX_CONS(15);
10748
10749         BCE_PRINT_TX_CONS(1);   BCE_PRINT_TX_CONS(2);   BCE_PRINT_TX_CONS(3);
10750
10751         if (sblk->status_completion_producer_index ||
10752             sblk->status_cmd_consumer_index)
10753                 BCE_PRINTF("com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
10754                     sblk->status_completion_producer_index,
10755                     sblk->status_cmd_consumer_index);
10756
10757         BCE_PRINTF(
10758             "----------------------------"
10759             "----------------"
10760             "----------------------------\n");
10761 }
10762
10763
10764 #define BCE_PRINT_64BIT_STAT(arg)                               \
10765 if (sblk->arg##_lo || sblk->arg##_hi)                           \
10766         BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi,        \
10767             sblk->arg##_lo, #arg);
10768
10769 #define BCE_PRINT_32BIT_STAT(arg)                               \
10770 if (sblk->arg)                                                  \
10771         BCE_PRINTF("         0x%08X : %s\n",                    \
10772             sblk->arg, #arg);
10773
10774 /****************************************************************************/
10775 /* Prints out the statistics block from host memory.                        */
10776 /*                                                                          */
10777 /* Returns:                                                                 */
10778 /*   Nothing.                                                               */
10779 /****************************************************************************/
10780 static __attribute__ ((noinline)) void
10781 bce_dump_stats_block(struct bce_softc *sc)
10782 {
10783         struct statistics_block *sblk;
10784
10785         sblk = sc->stats_block;
10786
10787         BCE_PRINTF(
10788             "---------------"
10789             " Stats Block  (All Stats Not Shown Are 0) "
10790             "---------------\n");
10791
10792         BCE_PRINT_64BIT_STAT(stat_IfHCInOctets);
10793         BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets);
10794         BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets);
10795         BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets);
10796         BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts);
10797         BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts);
10798         BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts);
10799         BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts);
10800         BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts);
10801         BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts);
10802         BCE_PRINT_32BIT_STAT(
10803             stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
10804         BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors);
10805         BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors);
10806         BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors);
10807         BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames);
10808         BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames);
10809         BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions);
10810         BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions);
10811         BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions);
10812         BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions);
10813         BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments);
10814         BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers);
10815         BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts);
10816         BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts);
10817         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets);
10818         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets);
10819         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets);
10820         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets);
10821         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets);
10822         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets);
10823         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets);
10824         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets);
10825         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets);
10826         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets);
10827         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets);
10828         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets);
10829         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets);
10830         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets);
10831         BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived);
10832         BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived);
10833         BCE_PRINT_32BIT_STAT(stat_OutXonSent);
10834         BCE_PRINT_32BIT_STAT(stat_OutXoffSent);
10835         BCE_PRINT_32BIT_STAT(stat_FlowControlDone);
10836         BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived);
10837         BCE_PRINT_32BIT_STAT(stat_XoffStateEntered);
10838         BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards);
10839         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards);
10840         BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards);
10841         BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards);
10842         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit);
10843         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards);
10844         BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards);
10845         BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards);
10846         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit);
10847
10848         BCE_PRINTF(
10849             "----------------------------"
10850             "----------------"
10851             "----------------------------\n");
10852 }
10853
10854
10855 /****************************************************************************/
10856 /* Prints out a summary of the driver state.                                */
10857 /*                                                                          */
10858 /* Returns:                                                                 */
10859 /*   Nothing.                                                               */
10860 /****************************************************************************/
10861 static __attribute__ ((noinline)) void
10862 bce_dump_driver_state(struct bce_softc *sc)
10863 {
10864         u32 val_hi, val_lo;
10865
10866         BCE_PRINTF(
10867             "-----------------------------"
10868             " Driver State "
10869             "-----------------------------\n");
10870
10871         val_hi = BCE_ADDR_HI(sc);
10872         val_lo = BCE_ADDR_LO(sc);
10873         BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual "
10874             "address\n", val_hi, val_lo);
10875
10876         val_hi = BCE_ADDR_HI(sc->bce_vhandle);
10877         val_lo = BCE_ADDR_LO(sc->bce_vhandle);
10878         BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual "
10879             "address\n", val_hi, val_lo);
10880
10881         val_hi = BCE_ADDR_HI(sc->status_block);
10882         val_lo = BCE_ADDR_LO(sc->status_block);
10883         BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block "
10884             "virtual address\n",        val_hi, val_lo);
10885
10886         val_hi = BCE_ADDR_HI(sc->stats_block);
10887         val_lo = BCE_ADDR_LO(sc->stats_block);
10888         BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block "
10889             "virtual address\n", val_hi, val_lo);
10890
10891         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
10892         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
10893         BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
10894             "virtual adddress\n", val_hi, val_lo);
10895
10896         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
10897         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
10898         BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
10899             "virtual address\n", val_hi, val_lo);
10900
10901         if (bce_hdr_split == TRUE) {
10902                 val_hi = BCE_ADDR_HI(sc->pg_bd_chain);
10903                 val_lo = BCE_ADDR_LO(sc->pg_bd_chain);
10904                 BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain "
10905                     "virtual address\n", val_hi, val_lo);
10906         }
10907
10908         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
10909         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
10910         BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
10911             "virtual address\n",        val_hi, val_lo);
10912
10913         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
10914         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
10915         BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
10916             "virtual address\n", val_hi, val_lo);
10917
10918         if (bce_hdr_split == TRUE) {
10919                 val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
10920                 val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
10921                 BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain "
10922                     "virtual address\n", val_hi, val_lo);
10923         }
10924
10925         BCE_PRINTF(" 0x%016llX - (sc->interrupts_generated) "
10926             "h/w intrs\n",
10927             (long long unsigned int) sc->interrupts_generated);
10928
10929         BCE_PRINTF(" 0x%016llX - (sc->interrupts_rx) "
10930             "rx interrupts handled\n",
10931             (long long unsigned int) sc->interrupts_rx);
10932
10933         BCE_PRINTF(" 0x%016llX - (sc->interrupts_tx) "
10934             "tx interrupts handled\n",
10935             (long long unsigned int) sc->interrupts_tx);
10936
10937         BCE_PRINTF(" 0x%016llX - (sc->phy_interrupts) "
10938             "phy interrupts handled\n",
10939             (long long unsigned int) sc->phy_interrupts);
10940
10941         BCE_PRINTF("         0x%08X - (sc->last_status_idx) "
10942             "status block index\n", sc->last_status_idx);
10943
10944         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_prod) tx producer "
10945             "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod));
10946
10947         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_cons) tx consumer "
10948             "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons));
10949
10950         BCE_PRINTF("         0x%08X - (sc->tx_prod_bseq) tx producer "
10951             "byte seq index\n", sc->tx_prod_bseq);
10952
10953         BCE_PRINTF("         0x%08X - (sc->debug_tx_mbuf_alloc) tx "
10954             "mbufs allocated\n", sc->debug_tx_mbuf_alloc);
10955
10956         BCE_PRINTF("         0x%08X - (sc->used_tx_bd) used "
10957             "tx_bd's\n", sc->used_tx_bd);
10958
10959         BCE_PRINTF("      0x%04X/0x%04X - (sc->tx_hi_watermark)/"
10960             "(sc->max_tx_bd)\n", sc->tx_hi_watermark, sc->max_tx_bd);
10961
10962         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_prod) rx producer "
10963             "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod));
10964
10965         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_cons) rx consumer "
10966             "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons));
10967
10968         BCE_PRINTF("         0x%08X - (sc->rx_prod_bseq) rx producer "
10969             "byte seq index\n", sc->rx_prod_bseq);
10970
10971         BCE_PRINTF("      0x%04X/0x%04X - (sc->rx_low_watermark)/"
10972                    "(sc->max_rx_bd)\n", sc->rx_low_watermark, sc->max_rx_bd);
10973
10974         BCE_PRINTF("         0x%08X - (sc->debug_rx_mbuf_alloc) rx "
10975             "mbufs allocated\n", sc->debug_rx_mbuf_alloc);
10976
10977         BCE_PRINTF("         0x%08X - (sc->free_rx_bd) free "
10978             "rx_bd's\n", sc->free_rx_bd);
10979
10980         if (bce_hdr_split == TRUE) {
10981                 BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_prod) page producer "
10982                     "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod));
10983
10984                 BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_cons) page consumer "
10985                     "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons));
10986
10987                 BCE_PRINTF("         0x%08X - (sc->debug_pg_mbuf_alloc) page "
10988                     "mbufs allocated\n", sc->debug_pg_mbuf_alloc);
10989         }
10990
10991         BCE_PRINTF("         0x%08X - (sc->free_pg_bd) free page "
10992             "rx_bd's\n", sc->free_pg_bd);
10993
10994         BCE_PRINTF("      0x%04X/0x%04X - (sc->pg_low_watermark)/"
10995             "(sc->max_pg_bd)\n", sc->pg_low_watermark, sc->max_pg_bd);
10996
10997         BCE_PRINTF("         0x%08X - (sc->mbuf_alloc_failed_count) "
10998             "mbuf alloc failures\n", sc->mbuf_alloc_failed_count);
10999
11000         BCE_PRINTF("         0x%08X - (sc->bce_flags) "
11001             "bce mac flags\n", sc->bce_flags);
11002
11003         BCE_PRINTF("         0x%08X - (sc->bce_phy_flags) "
11004             "bce phy flags\n", sc->bce_phy_flags);
11005
11006         BCE_PRINTF(
11007             "----------------------------"
11008             "----------------"
11009             "----------------------------\n");
11010 }
11011
11012
11013 /****************************************************************************/
11014 /* Prints out the hardware state through a summary of important register,   */
11015 /* followed by a complete register dump.                                    */
11016 /*                                                                          */
11017 /* Returns:                                                                 */
11018 /*   Nothing.                                                               */
11019 /****************************************************************************/
11020 static __attribute__ ((noinline)) void
11021 bce_dump_hw_state(struct bce_softc *sc)
11022 {
11023         u32 val;
11024
11025         BCE_PRINTF(
11026             "----------------------------"
11027             " Hardware State "
11028             "----------------------------\n");
11029
11030         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
11031
11032         val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
11033         BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
11034             val, BCE_MISC_ENABLE_STATUS_BITS);
11035
11036         val = REG_RD(sc, BCE_DMA_STATUS);
11037         BCE_PRINTF("0x%08X - (0x%06X) dma_status\n",
11038             val, BCE_DMA_STATUS);
11039
11040         val = REG_RD(sc, BCE_CTX_STATUS);
11041         BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n",
11042             val, BCE_CTX_STATUS);
11043
11044         val = REG_RD(sc, BCE_EMAC_STATUS);
11045         BCE_PRINTF("0x%08X - (0x%06X) emac_status\n",
11046             val, BCE_EMAC_STATUS);
11047
11048         val = REG_RD(sc, BCE_RPM_STATUS);
11049         BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n",
11050             val, BCE_RPM_STATUS);
11051
11052         /* ToDo: Create a #define for this constant. */
11053         val = REG_RD(sc, 0x2004);
11054         BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n",
11055             val, 0x2004);
11056
11057         val = REG_RD(sc, BCE_RV2P_STATUS);
11058         BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n",
11059             val, BCE_RV2P_STATUS);
11060
11061         /* ToDo: Create a #define for this constant. */
11062         val = REG_RD(sc, 0x2c04);
11063         BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n",
11064             val, 0x2c04);
11065
11066         val = REG_RD(sc, BCE_TBDR_STATUS);
11067         BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n",
11068             val, BCE_TBDR_STATUS);
11069
11070         val = REG_RD(sc, BCE_TDMA_STATUS);
11071         BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n",
11072             val, BCE_TDMA_STATUS);
11073
11074         val = REG_RD(sc, BCE_HC_STATUS);
11075         BCE_PRINTF("0x%08X - (0x%06X) hc_status\n",
11076             val, BCE_HC_STATUS);
11077
11078         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11079         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11080             val, BCE_TXP_CPU_STATE);
11081
11082         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11083         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11084             val, BCE_TPAT_CPU_STATE);
11085
11086         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11087         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11088             val, BCE_RXP_CPU_STATE);
11089
11090         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11091         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11092             val, BCE_COM_CPU_STATE);
11093
11094         val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
11095         BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n",
11096             val, BCE_MCP_CPU_STATE);
11097
11098         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11099         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11100             val, BCE_CP_CPU_STATE);
11101
11102         BCE_PRINTF(
11103             "----------------------------"
11104             "----------------"
11105             "----------------------------\n");
11106
11107         BCE_PRINTF(
11108             "----------------------------"
11109             " Register  Dump "
11110             "----------------------------\n");
11111
11112         for (int i = 0x400; i < 0x8000; i += 0x10) {
11113                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11114                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11115                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11116         }
11117
11118         BCE_PRINTF(
11119             "----------------------------"
11120             "----------------"
11121             "----------------------------\n");
11122 }
11123
11124
11125 /****************************************************************************/
11126 /* Prints out the contentst of shared memory which is used for host driver  */
11127 /* to bootcode firmware communication.                                      */
11128 /*                                                                          */
11129 /* Returns:                                                                 */
11130 /*   Nothing.                                                               */
11131 /****************************************************************************/
11132 static __attribute__ ((noinline)) void
11133 bce_dump_shmem_state(struct bce_softc *sc)
11134 {
11135         BCE_PRINTF(
11136             "----------------------------"
11137             " Hardware State "
11138             "----------------------------\n");
11139
11140         BCE_PRINTF("0x%08X - Shared memory base address\n",
11141             sc->bce_shmem_base);
11142         BCE_PRINTF("%s - bootcode version\n",
11143             sc->bce_bc_ver);
11144
11145         BCE_PRINTF(
11146             "----------------------------"
11147             "   Shared Mem   "
11148             "----------------------------\n");
11149
11150         for (int i = 0x0; i < 0x200; i += 0x10) {
11151                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11152                     i, bce_shmem_rd(sc, i), bce_shmem_rd(sc, i + 0x4),
11153                     bce_shmem_rd(sc, i + 0x8), bce_shmem_rd(sc, i + 0xC));
11154         }
11155
11156         BCE_PRINTF(
11157             "----------------------------"
11158             "----------------"
11159             "----------------------------\n");
11160 }
11161
11162
11163 /****************************************************************************/
11164 /* Prints out the mailbox queue registers.                                  */
11165 /*                                                                          */
11166 /* Returns:                                                                 */
11167 /*   Nothing.                                                               */
11168 /****************************************************************************/
11169 static __attribute__ ((noinline)) void
11170 bce_dump_mq_regs(struct bce_softc *sc)
11171 {
11172         BCE_PRINTF(
11173             "----------------------------"
11174             "    MQ Regs     "
11175             "----------------------------\n");
11176
11177         BCE_PRINTF(
11178             "----------------------------"
11179             "----------------"
11180             "----------------------------\n");
11181
11182         for (int i = 0x3c00; i < 0x4000; i += 0x10) {
11183                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
11184                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
11185                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
11186         }
11187
11188         BCE_PRINTF(
11189             "----------------------------"
11190             "----------------"
11191             "----------------------------\n");
11192 }
11193
11194
11195 /****************************************************************************/
11196 /* Prints out the bootcode state.                                           */
11197 /*                                                                          */
11198 /* Returns:                                                                 */
11199 /*   Nothing.                                                               */
11200 /****************************************************************************/
11201 static __attribute__ ((noinline)) void
11202 bce_dump_bc_state(struct bce_softc *sc)
11203 {
11204         u32 val;
11205
11206         BCE_PRINTF(
11207             "----------------------------"
11208             " Bootcode State "
11209             "----------------------------\n");
11210
11211         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
11212
11213         val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE);
11214         BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
11215             val, BCE_BC_RESET_TYPE);
11216
11217         val = bce_shmem_rd(sc, BCE_BC_STATE);
11218         BCE_PRINTF("0x%08X - (0x%06X) state\n",
11219             val, BCE_BC_STATE);
11220
11221         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
11222         BCE_PRINTF("0x%08X - (0x%06X) condition\n",
11223             val, BCE_BC_STATE_CONDITION);
11224
11225         val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD);
11226         BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
11227             val, BCE_BC_STATE_DEBUG_CMD);
11228
11229         BCE_PRINTF(
11230             "----------------------------"
11231             "----------------"
11232             "----------------------------\n");
11233 }
11234
11235
11236 /****************************************************************************/
11237 /* Prints out the TXP processor state.                                      */
11238 /*                                                                          */
11239 /* Returns:                                                                 */
11240 /*   Nothing.                                                               */
11241 /****************************************************************************/
11242 static __attribute__ ((noinline)) void
11243 bce_dump_txp_state(struct bce_softc *sc, int regs)
11244 {
11245         u32 val;
11246         u32 fw_version[3];
11247
11248         BCE_PRINTF(
11249             "----------------------------"
11250             "   TXP  State   "
11251             "----------------------------\n");
11252
11253         for (int i = 0; i < 3; i++)
11254                 fw_version[i] = htonl(REG_RD_IND(sc,
11255                     (BCE_TXP_SCRATCH + 0x10 + i * 4)));
11256         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11257
11258         val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
11259         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n",
11260             val, BCE_TXP_CPU_MODE);
11261
11262         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
11263         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
11264             val, BCE_TXP_CPU_STATE);
11265
11266         val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
11267         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n",
11268             val, BCE_TXP_CPU_EVENT_MASK);
11269
11270         if (regs) {
11271                 BCE_PRINTF(
11272                     "----------------------------"
11273                     " Register  Dump "
11274                     "----------------------------\n");
11275
11276                 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
11277                         /* Skip the big blank spaces */
11278                         if (i < 0x454000 && i > 0x5ffff)
11279                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11280                                     "0x%08X 0x%08X\n", i,
11281                                     REG_RD_IND(sc, i),
11282                                     REG_RD_IND(sc, i + 0x4),
11283                                     REG_RD_IND(sc, i + 0x8),
11284                                     REG_RD_IND(sc, i + 0xC));
11285                 }
11286         }
11287
11288         BCE_PRINTF(
11289             "----------------------------"
11290             "----------------"
11291             "----------------------------\n");
11292 }
11293
11294
11295 /****************************************************************************/
11296 /* Prints out the RXP processor state.                                      */
11297 /*                                                                          */
11298 /* Returns:                                                                 */
11299 /*   Nothing.                                                               */
11300 /****************************************************************************/
11301 static __attribute__ ((noinline)) void
11302 bce_dump_rxp_state(struct bce_softc *sc, int regs)
11303 {
11304         u32 val;
11305         u32 fw_version[3];
11306
11307         BCE_PRINTF(
11308             "----------------------------"
11309             "   RXP  State   "
11310             "----------------------------\n");
11311
11312         for (int i = 0; i < 3; i++)
11313                 fw_version[i] = htonl(REG_RD_IND(sc,
11314                     (BCE_RXP_SCRATCH + 0x10 + i * 4)));
11315
11316         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11317
11318         val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
11319         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n",
11320             val, BCE_RXP_CPU_MODE);
11321
11322         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
11323         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
11324             val, BCE_RXP_CPU_STATE);
11325
11326         val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
11327         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n",
11328             val, BCE_RXP_CPU_EVENT_MASK);
11329
11330         if (regs) {
11331                 BCE_PRINTF(
11332                     "----------------------------"
11333                     " Register  Dump "
11334                     "----------------------------\n");
11335
11336                 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
11337                         /* Skip the big blank sapces */
11338                         if (i < 0xc5400 && i > 0xdffff)
11339                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11340                                     "0x%08X 0x%08X\n", i,
11341                                     REG_RD_IND(sc, i),
11342                                     REG_RD_IND(sc, i + 0x4),
11343                                     REG_RD_IND(sc, i + 0x8),
11344                                     REG_RD_IND(sc, i + 0xC));
11345                 }
11346         }
11347
11348         BCE_PRINTF(
11349             "----------------------------"
11350             "----------------"
11351             "----------------------------\n");
11352 }
11353
11354
11355 /****************************************************************************/
11356 /* Prints out the TPAT processor state.                                     */
11357 /*                                                                          */
11358 /* Returns:                                                                 */
11359 /*   Nothing.                                                               */
11360 /****************************************************************************/
11361 static __attribute__ ((noinline)) void
11362 bce_dump_tpat_state(struct bce_softc *sc, int regs)
11363 {
11364         u32 val;
11365         u32 fw_version[3];
11366
11367         BCE_PRINTF(
11368             "----------------------------"
11369             "   TPAT State   "
11370             "----------------------------\n");
11371
11372         for (int i = 0; i < 3; i++)
11373                 fw_version[i] = htonl(REG_RD_IND(sc,
11374                     (BCE_TPAT_SCRATCH + 0x410 + i * 4)));
11375
11376         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11377
11378         val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
11379         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n",
11380             val, BCE_TPAT_CPU_MODE);
11381
11382         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
11383         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
11384             val, BCE_TPAT_CPU_STATE);
11385
11386         val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
11387         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n",
11388             val, BCE_TPAT_CPU_EVENT_MASK);
11389
11390         if (regs) {
11391                 BCE_PRINTF(
11392                     "----------------------------"
11393                     " Register  Dump "
11394                     "----------------------------\n");
11395
11396                 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
11397                         /* Skip the big blank spaces */
11398                         if (i < 0x854000 && i > 0x9ffff)
11399                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11400                                     "0x%08X 0x%08X\n", i,
11401                                     REG_RD_IND(sc, i),
11402                                     REG_RD_IND(sc, i + 0x4),
11403                                     REG_RD_IND(sc, i + 0x8),
11404                                     REG_RD_IND(sc, i + 0xC));
11405                 }
11406         }
11407
11408         BCE_PRINTF(
11409                 "----------------------------"
11410                 "----------------"
11411                 "----------------------------\n");
11412 }
11413
11414
11415 /****************************************************************************/
11416 /* Prints out the Command Procesor (CP) state.                              */
11417 /*                                                                          */
11418 /* Returns:                                                                 */
11419 /*   Nothing.                                                               */
11420 /****************************************************************************/
11421 static __attribute__ ((noinline)) void
11422 bce_dump_cp_state(struct bce_softc *sc, int regs)
11423 {
11424         u32 val;
11425         u32 fw_version[3];
11426
11427         BCE_PRINTF(
11428             "----------------------------"
11429             "    CP State    "
11430             "----------------------------\n");
11431
11432         for (int i = 0; i < 3; i++)
11433                 fw_version[i] = htonl(REG_RD_IND(sc,
11434                     (BCE_CP_SCRATCH + 0x10 + i * 4)));
11435
11436         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11437
11438         val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
11439         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n",
11440             val, BCE_CP_CPU_MODE);
11441
11442         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
11443         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
11444             val, BCE_CP_CPU_STATE);
11445
11446         val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
11447         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
11448             BCE_CP_CPU_EVENT_MASK);
11449
11450         if (regs) {
11451                 BCE_PRINTF(
11452                     "----------------------------"
11453                     " Register  Dump "
11454                     "----------------------------\n");
11455
11456                 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
11457                         /* Skip the big blank spaces */
11458                         if (i < 0x185400 && i > 0x19ffff)
11459                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11460                                     "0x%08X 0x%08X\n", i,
11461                                     REG_RD_IND(sc, i),
11462                                     REG_RD_IND(sc, i + 0x4),
11463                                     REG_RD_IND(sc, i + 0x8),
11464                                     REG_RD_IND(sc, i + 0xC));
11465                 }
11466         }
11467
11468         BCE_PRINTF(
11469             "----------------------------"
11470             "----------------"
11471             "----------------------------\n");
11472 }
11473
11474
11475 /****************************************************************************/
11476 /* Prints out the Completion Procesor (COM) state.                          */
11477 /*                                                                          */
11478 /* Returns:                                                                 */
11479 /*   Nothing.                                                               */
11480 /****************************************************************************/
11481 static __attribute__ ((noinline)) void
11482 bce_dump_com_state(struct bce_softc *sc, int regs)
11483 {
11484         u32 val;
11485         u32 fw_version[4];
11486
11487         BCE_PRINTF(
11488             "----------------------------"
11489             "   COM State    "
11490             "----------------------------\n");
11491
11492         for (int i = 0; i < 3; i++)
11493                 fw_version[i] = htonl(REG_RD_IND(sc,
11494                     (BCE_COM_SCRATCH + 0x10 + i * 4)));
11495
11496         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
11497
11498         val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
11499         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n",
11500             val, BCE_COM_CPU_MODE);
11501
11502         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
11503         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
11504             val, BCE_COM_CPU_STATE);
11505
11506         val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
11507         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
11508             BCE_COM_CPU_EVENT_MASK);
11509
11510         if (regs) {
11511                 BCE_PRINTF(
11512                     "----------------------------"
11513                     " Register  Dump "
11514                     "----------------------------\n");
11515
11516                 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
11517                         BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
11518                             "0x%08X 0x%08X\n", i,
11519                             REG_RD_IND(sc, i),
11520                             REG_RD_IND(sc, i + 0x4),
11521                             REG_RD_IND(sc, i + 0x8),
11522                             REG_RD_IND(sc, i + 0xC));
11523                 }
11524         }
11525
11526         BCE_PRINTF(
11527                 "----------------------------"
11528                 "----------------"
11529                 "----------------------------\n");
11530 }
11531
11532
11533 /****************************************************************************/
11534 /* Prints out the Receive Virtual 2 Physical (RV2P) state.                  */
11535 /*                                                                          */
11536 /* Returns:                                                                 */
11537 /*   Nothing.                                                               */
11538 /****************************************************************************/
11539 static __attribute__ ((noinline)) void
11540 bce_dump_rv2p_state(struct bce_softc *sc)
11541 {
11542         u32 val, pc1, pc2, fw_ver_high, fw_ver_low;
11543
11544         BCE_PRINTF(
11545             "----------------------------"
11546             "   RV2P State   "
11547             "----------------------------\n");
11548
11549         /* Stall the RV2P processors. */
11550         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11551         val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2;
11552         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11553
11554         /* Read the firmware version. */
11555         val = 0x00000001;
11556         REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
11557         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11558         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11559             BCE_RV2P_INSTR_HIGH_HIGH;
11560         BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n",
11561             fw_ver_high, fw_ver_low);
11562
11563         val = 0x00000001;
11564         REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
11565         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
11566         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
11567             BCE_RV2P_INSTR_HIGH_HIGH;
11568         BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n",
11569             fw_ver_high, fw_ver_low);
11570
11571         /* Resume the RV2P processors. */
11572         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
11573         val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2);
11574         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
11575
11576         /* Fetch the program counter value. */
11577         val = 0x68007800;
11578         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11579         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11580         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11581         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11582         BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1);
11583         BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2);
11584
11585         /* Fetch the program counter value again to see if it is advancing. */
11586         val = 0x68007800;
11587         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
11588         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
11589         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
11590         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
11591         BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1);
11592         BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2);
11593
11594         BCE_PRINTF(
11595             "----------------------------"
11596             "----------------"
11597             "----------------------------\n");
11598 }
11599
11600
11601 /****************************************************************************/
11602 /* Prints out the driver state and then enters the debugger.                */
11603 /*                                                                          */
11604 /* Returns:                                                                 */
11605 /*   Nothing.                                                               */
11606 /****************************************************************************/
11607 static __attribute__ ((noinline)) void
11608 bce_breakpoint(struct bce_softc *sc)
11609 {
11610
11611         /*
11612          * Unreachable code to silence compiler warnings
11613          * about unused functions.
11614          */
11615         if (0) {
11616                 bce_freeze_controller(sc);
11617                 bce_unfreeze_controller(sc);
11618                 bce_dump_enet(sc, NULL);
11619                 bce_dump_txbd(sc, 0, NULL);
11620                 bce_dump_rxbd(sc, 0, NULL);
11621                 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD_ALLOC);
11622                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD_ALLOC);
11623                 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD_ALLOC);
11624                 bce_dump_l2fhdr(sc, 0, NULL);
11625                 bce_dump_ctx(sc, RX_CID);
11626                 bce_dump_ftqs(sc);
11627                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD_ALLOC);
11628                 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD_ALLOC);
11629                 bce_dump_pg_chain(sc, 0, USABLE_PG_BD_ALLOC);
11630                 bce_dump_status_block(sc);
11631                 bce_dump_stats_block(sc);
11632                 bce_dump_driver_state(sc);
11633                 bce_dump_hw_state(sc);
11634                 bce_dump_bc_state(sc);
11635                 bce_dump_txp_state(sc, 0);
11636                 bce_dump_rxp_state(sc, 0);
11637                 bce_dump_tpat_state(sc, 0);
11638                 bce_dump_cp_state(sc, 0);
11639                 bce_dump_com_state(sc, 0);
11640                 bce_dump_rv2p_state(sc);
11641                 bce_dump_pgbd(sc, 0, NULL);
11642         }
11643
11644         bce_dump_status_block(sc);
11645         bce_dump_driver_state(sc);
11646
11647         /* Call the debugger. */
11648         breakpoint();
11649
11650         return;
11651 }
11652 #endif
11653