sys/dev/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2010 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 /*
  35  * The following controllers are supported by this driver:
  36  *   BCM5706C A2, A3
  37  *   BCM5706S A2, A3
  38  *   BCM5708C B1, B2
  39  *   BCM5708S B1, B2
  40  *   BCM5709C A1, C0
  41  *   BCM5709S A1, C0
  42  *   BCM5716C C0
  43  *   BCM5716S C0
  44  *
  45  * The following controllers are not supported by this driver:
  46  *   BCM5706C A0, A1 (pre-production)
  47  *   BCM5706S A0, A1 (pre-production)
  48  *   BCM5708C A0, B0 (pre-production)
  49  *   BCM5708S A0, B0 (pre-production)
  50  *   BCM5709C A0  B0, B1, B2 (pre-production)
  51  *   BCM5709S A0, B0, B1, B2 (pre-production)
  52  */
  53
  54 #include "opt_bce.h"
  55
  56 #include <dev/bce/if_bcereg.h>
  57 #include <dev/bce/if_bcefw.h>
  58
  59 /****************************************************************************/
  60 /* BCE Debug Options                                                        */
  61 /****************************************************************************/
  62 #ifdef BCE_DEBUG
  63         u32 bce_debug = BCE_WARN;
  64
  65         /*          0 = Never              */
  66         /*          1 = 1 in 2,147,483,648 */
  67         /*        256 = 1 in     8,388,608 */
  68         /*       2048 = 1 in     1,048,576 */
  69         /*      65536 = 1 in        32,768 */
  70         /*    1048576 = 1 in         2,048 */
  71         /*  268435456 = 1 in             8 */
  72         /*  536870912 = 1 in             4 */
  73         /* 1073741824 = 1 in             2 */
  74
  75         /* Controls how often the l2_fhdr frame error check will fail. */
  76         int l2fhdr_error_sim_control = 0;
  77
  78         /* Controls how often the unexpected attention check will fail. */
  79         int unexpected_attention_sim_control = 0;
  80
  81         /* Controls how often to simulate an mbuf allocation failure. */
  82         int mbuf_alloc_failed_sim_control = 0;
  83
  84         /* Controls how often to simulate a DMA mapping failure. */
  85         int dma_map_addr_failed_sim_control = 0;
  86
  87         /* Controls how often to simulate a bootcode failure. */
  88         int bootcode_running_failure_sim_control = 0;
  89 #endif
  90
  91 /****************************************************************************/
  92 /* BCE Build Time Options                                                   */
  93 /****************************************************************************/
  94 /* #define BCE_NVRAM_WRITE_SUPPORT 1 */
  95
  96
  97 /****************************************************************************/
  98 /* PCI Device ID Table                                                      */
  99 /*                                                                          */
 100 /* Used by bce_probe() to identify the devices supported by this driver.    */
 101 /****************************************************************************/
 102 #define BCE_DEVDESC_MAX         64
 103
 104 static struct bce_type bce_devs[] = {
 105         /* BCM5706C Controllers and OEM boards. */
 106         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 107                 "HP NC370T Multifunction Gigabit Server Adapter" },
 108         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 109                 "HP NC370i Multifunction Gigabit Server Adapter" },
 110         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 111                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 112         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 113                 "HP NC371i Multifunction Gigabit Server Adapter" },
 114         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 115                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 116
 117         /* BCM5706S controllers and OEM boards. */
 118         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 119                 "HP NC370F Multifunction Gigabit Server Adapter" },
 120         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 121                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 122
 123         /* BCM5708C controllers and OEM boards. */
 124         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 125                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 126         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 127                 "HP NC373i Multifunction Gigabit Server Adapter" },
 128         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 129                 "HP NC374m PCIe Multifunction Adapter" },
 130         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 131                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 132
 133         /* BCM5708S controllers and OEM boards. */
 134         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 135                 "HP NC373m Multifunction Gigabit Server Adapter" },
 136         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 137                 "HP NC373i Multifunction Gigabit Server Adapter" },
 138         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 139                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 140         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 141                 "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 142
 143         /* BCM5709C controllers and OEM boards. */
 144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 145                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 147                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 149                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 150
 151         /* BCM5709S controllers and OEM boards. */
 152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 153                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 154         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 155                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 156         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 157                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 158
 159         /* BCM5716 controllers and OEM boards. */
 160         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,  PCI_ANY_ID,  PCI_ANY_ID,
 161                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 162
 163         { 0, 0, 0, 0, NULL }
 164 };
 165
 166
 167 /****************************************************************************/
 168 /* Supported Flash NVRAM device data.                                       */
 169 /****************************************************************************/
 170 static struct flash_spec flash_table[] =
 171 {
 172 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 173 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 174
 175         /* Slow EEPROM */
 176         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 177          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 178          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 179          "EEPROM - slow"},
 180         /* Expansion entry 0001 */
 181         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 182          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 183          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 184          "Entry 0001"},
 185         /* Saifun SA25F010 (non-buffered flash) */
 186         /* strap, cfg1, & write1 need updates */
 187         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 189          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 190          "Non-buffered flash (128kB)"},
 191         /* Saifun SA25F020 (non-buffered flash) */
 192         /* strap, cfg1, & write1 need updates */
 193         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 194          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 195          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 196          "Non-buffered flash (256kB)"},
 197         /* Expansion entry 0100 */
 198         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 199          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 200          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 201          "Entry 0100"},
 202         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 203         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 204          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 205          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 206          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 207         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 208         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 209          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 210          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 211          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 212         /* Saifun SA25F005 (non-buffered flash) */
 213         /* strap, cfg1, & write1 need updates */
 214         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 215          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 216          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 217          "Non-buffered flash (64kB)"},
 218         /* Fast EEPROM */
 219         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 220          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 221          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 222          "EEPROM - fast"},
 223         /* Expansion entry 1001 */
 224         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 225          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 226          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 227          "Entry 1001"},
 228         /* Expansion entry 1010 */
 229         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 230          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 231          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 232          "Entry 1010"},
 233         /* ATMEL AT45DB011B (buffered flash) */
 234         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 235          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 236          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 237          "Buffered flash (128kB)"},
 238         /* Expansion entry 1100 */
 239         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 240          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 241          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 242          "Entry 1100"},
 243         /* Expansion entry 1101 */
 244         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 245          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 246          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 247          "Entry 1101"},
 248         /* Ateml Expansion entry 1110 */
 249         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 250          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 251          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 252          "Entry 1110 (Atmel)"},
 253         /* ATMEL AT45DB021B (buffered flash) */
 254         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 255          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 256          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 257          "Buffered flash (256kB)"},
 258 };
 259
 260 /*
 261  * The BCM5709 controllers transparently handle the
 262  * differences between Atmel 264 byte pages and all
 263  * flash devices which use 256 byte pages, so no
 264  * logical-to-physical mapping is required in the
 265  * driver.
 266  */
 267 static struct flash_spec flash_5709 = {
 268         .flags          = BCE_NV_BUFFERED,
 269         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 270         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 271         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 272         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 273         .name           = "5709/5716 buffered flash (256kB)",
 274 };
 275
 276
 277 /****************************************************************************/
 278 /* FreeBSD device entry points.                                             */
 279 /****************************************************************************/
 280 static int  bce_probe                   (device_t);
 281 static int  bce_attach                  (device_t);
 282 static int  bce_detach                  (device_t);
 283 static int  bce_shutdown                (device_t);
 284
 285
 286 /****************************************************************************/
 287 /* BCE Debug Data Structure Dump Routines                                   */
 288 /****************************************************************************/
 289 #ifdef BCE_DEBUG
 290 static u32  bce_reg_rd                  (struct bce_softc *, u32);
 291 static void bce_reg_wr                  (struct bce_softc *, u32, u32);
 292 static void bce_reg_wr16                (struct bce_softc *, u32, u16);
 293 static u32  bce_ctx_rd                  (struct bce_softc *, u32, u32);
 294 static void bce_dump_enet               (struct bce_softc *, struct mbuf *);
 295 static void bce_dump_mbuf               (struct bce_softc *, struct mbuf *);
 296 static void bce_dump_tx_mbuf_chain      (struct bce_softc *, u16, int);
 297 static void bce_dump_rx_mbuf_chain      (struct bce_softc *, u16, int);
 298 #ifdef BCE_JUMBO_HDRSPLIT
 299 static void bce_dump_pg_mbuf_chain      (struct bce_softc *, u16, int);
 300 #endif
 301 static void bce_dump_txbd               (struct bce_softc *,
 302     int, struct tx_bd *);
 303 static void bce_dump_rxbd               (struct bce_softc *,
 304     int, struct rx_bd *);
 305 #ifdef BCE_JUMBO_HDRSPLIT
 306 static void bce_dump_pgbd               (struct bce_softc *,
 307     int, struct rx_bd *);
 308 #endif
 309 static void bce_dump_l2fhdr             (struct bce_softc *,
 310     int, struct l2_fhdr *);
 311 static void bce_dump_ctx                (struct bce_softc *, u16);
 312 static void bce_dump_ftqs               (struct bce_softc *);
 313 static void bce_dump_tx_chain           (struct bce_softc *, u16, int);
 314 static void bce_dump_rx_bd_chain        (struct bce_softc *, u16, int);
 315 #ifdef BCE_JUMBO_HDRSPLIT
 316 static void bce_dump_pg_chain           (struct bce_softc *, u16, int);
 317 #endif
 318 static void bce_dump_status_block       (struct bce_softc *);
 319 static void bce_dump_stats_block        (struct bce_softc *);
 320 static void bce_dump_driver_state       (struct bce_softc *);
 321 static void bce_dump_hw_state           (struct bce_softc *);
 322 static void bce_dump_mq_regs            (struct bce_softc *);
 323 static void bce_dump_bc_state           (struct bce_softc *);
 324 static void bce_dump_txp_state          (struct bce_softc *, int);
 325 static void bce_dump_rxp_state          (struct bce_softc *, int);
 326 static void bce_dump_tpat_state         (struct bce_softc *, int);
 327 static void bce_dump_cp_state           (struct bce_softc *, int);
 328 static void bce_dump_com_state          (struct bce_softc *, int);
 329 static void bce_dump_rv2p_state         (struct bce_softc *);
 330 static void bce_breakpoint              (struct bce_softc *);
 331 #endif
 332
 333
 334 /****************************************************************************/
 335 /* BCE Register/Memory Access Routines                                      */
 336 /****************************************************************************/
 337 static u32  bce_reg_rd_ind              (struct bce_softc *, u32);
 338 static void bce_reg_wr_ind              (struct bce_softc *, u32, u32);
 339 static void bce_shmem_wr                (struct bce_softc *, u32, u32);
 340 static u32  bce_shmem_rd                (struct bce_softc *, u32);
 341 static void bce_ctx_wr                  (struct bce_softc *, u32, u32, u32);
 342 static int  bce_miibus_read_reg         (device_t, int, int);
 343 static int  bce_miibus_write_reg        (device_t, int, int, int);
 344 static void bce_miibus_statchg          (device_t);
 345
 346
 347 /****************************************************************************/
 348 /* BCE NVRAM Access Routines                                                */
 349 /****************************************************************************/
 350 static int  bce_acquire_nvram_lock      (struct bce_softc *);
 351 static int  bce_release_nvram_lock      (struct bce_softc *);
 352 static void bce_enable_nvram_access     (struct bce_softc *);
 353 static void bce_disable_nvram_access    (struct bce_softc *);
 354 static int  bce_nvram_read_dword        (struct bce_softc *, u32, u8 *, u32);
 355 static int  bce_init_nvram              (struct bce_softc *);
 356 static int  bce_nvram_read              (struct bce_softc *, u32, u8 *, int);
 357 static int  bce_nvram_test              (struct bce_softc *);
 358 #ifdef BCE_NVRAM_WRITE_SUPPORT
 359 static int  bce_enable_nvram_write      (struct bce_softc *);
 360 static void bce_disable_nvram_write     (struct bce_softc *);
 361 static int  bce_nvram_erase_page        (struct bce_softc *, u32);
 362 static int  bce_nvram_write_dword       (struct bce_softc *, u32, u8 *, u32);
 363 static int  bce_nvram_write             (struct bce_softc *, u32, u8 *, int);
 364 #endif
 365
 366 /****************************************************************************/
 367 /*                                                                          */
 368 /****************************************************************************/
 369 static void bce_get_media               (struct bce_softc *);
 370 static void bce_init_media              (struct bce_softc *);
 371 static void bce_dma_map_addr            (void *,
 372     bus_dma_segment_t *, int, int);
 373 static int  bce_dma_alloc               (device_t);
 374 static void bce_dma_free                (struct bce_softc *);
 375 static void bce_release_resources       (struct bce_softc *);
 376
 377 /****************************************************************************/
 378 /* BCE Firmware Synchronization and Load                                    */
 379 /****************************************************************************/
 380 static int  bce_fw_sync                 (struct bce_softc *, u32);
 381 static void bce_load_rv2p_fw            (struct bce_softc *, u32 *, u32, u32);
 382 static void bce_load_cpu_fw             (struct bce_softc *,
 383     struct cpu_reg *, struct fw_info *);
 384 static void bce_start_cpu               (struct bce_softc *, struct cpu_reg *);
 385 static void bce_halt_cpu                (struct bce_softc *, struct cpu_reg *);
 386 static void bce_start_rxp_cpu           (struct bce_softc *);
 387 static void bce_init_rxp_cpu            (struct bce_softc *);
 388 static void bce_init_txp_cpu            (struct bce_softc *);
 389 static void bce_init_tpat_cpu           (struct bce_softc *);
 390 static void bce_init_cp_cpu             (struct bce_softc *);
 391 static void bce_init_com_cpu            (struct bce_softc *);
 392 static void bce_init_cpus               (struct bce_softc *);
 393
 394 static void     bce_print_adapter_info  (struct bce_softc *);
 395 static void bce_probe_pci_caps          (device_t, struct bce_softc *);
 396 static void bce_stop                    (struct bce_softc *);
 397 static int  bce_reset                   (struct bce_softc *, u32);
 398 static int  bce_chipinit                (struct bce_softc *);
 399 static int  bce_blockinit               (struct bce_softc *);
 400
 401 static int  bce_init_tx_chain           (struct bce_softc *);
 402 static void bce_free_tx_chain           (struct bce_softc *);
 403
 404 static int  bce_get_rx_buf              (struct bce_softc *,
 405     struct mbuf *, u16 *, u16 *, u32 *);
 406 static int  bce_init_rx_chain           (struct bce_softc *);
 407 static void bce_fill_rx_chain           (struct bce_softc *);
 408 static void bce_free_rx_chain           (struct bce_softc *);
 409
 410 #ifdef BCE_JUMBO_HDRSPLIT
 411 static int  bce_get_pg_buf              (struct bce_softc *,
 412     struct mbuf *, u16 *, u16 *);
 413 static int  bce_init_pg_chain           (struct bce_softc *);
 414 static void bce_fill_pg_chain           (struct bce_softc *);
 415 static void bce_free_pg_chain           (struct bce_softc *);
 416 #endif
 417
 418 static struct mbuf *bce_tso_setup       (struct bce_softc *,
 419     struct mbuf **, u16 *);
 420 static int  bce_tx_encap                (struct bce_softc *, struct mbuf **);
 421 static void bce_start_locked            (struct ifnet *);
 422 static void bce_start                   (struct ifnet *);
 423 static int  bce_ioctl                   (struct ifnet *, u_long, caddr_t);
 424 static void bce_watchdog                (struct bce_softc *);
 425 static int  bce_ifmedia_upd             (struct ifnet *);
 426 static int  bce_ifmedia_upd_locked      (struct ifnet *);
 427 static void bce_ifmedia_sts             (struct ifnet *, struct ifmediareq *);
 428 static void bce_init_locked             (struct bce_softc *);
 429 static void bce_init                    (void *);
 430 static void bce_mgmt_init_locked        (struct bce_softc *sc);
 431
 432 static int  bce_init_ctx                (struct bce_softc *);
 433 static void bce_get_mac_addr            (struct bce_softc *);
 434 static void bce_set_mac_addr            (struct bce_softc *);
 435 static void bce_phy_intr                (struct bce_softc *);
 436 static inline u16 bce_get_hw_rx_cons    (struct bce_softc *);
 437 static void bce_rx_intr                 (struct bce_softc *);
 438 static void bce_tx_intr                 (struct bce_softc *);
 439 static void bce_disable_intr            (struct bce_softc *);
 440 static void bce_enable_intr             (struct bce_softc *, int);
 441
 442 static void bce_intr                    (void *);
 443 static void bce_set_rx_mode             (struct bce_softc *);
 444 static void bce_stats_update            (struct bce_softc *);
 445 static void bce_tick                    (void *);
 446 static void bce_pulse                   (void *);
 447 static void bce_add_sysctls             (struct bce_softc *);
 448
 449
 450 /****************************************************************************/
 451 /* FreeBSD device dispatch table.                                           */
 452 /****************************************************************************/
 453 static device_method_t bce_methods[] = {
 454         /* Device interface (device_if.h) */
 455         DEVMETHOD(device_probe,         bce_probe),
 456         DEVMETHOD(device_attach,        bce_attach),
 457         DEVMETHOD(device_detach,        bce_detach),
 458         DEVMETHOD(device_shutdown,      bce_shutdown),
 459 /* Supported by device interface but not used here. */
 460 /*      DEVMETHOD(device_identify,      bce_identify),      */
 461 /*      DEVMETHOD(device_suspend,       bce_suspend),       */
 462 /*      DEVMETHOD(device_resume,        bce_resume),        */
 463 /*      DEVMETHOD(device_quiesce,       bce_quiesce),       */
 464
 465         /* Bus interface (bus_if.h) */
 466         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 467         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 468
 469         /* MII interface (miibus_if.h) */
 470         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 471         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 472         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 473 /* Supported by MII interface but not used here.       */
 474 /*      DEVMETHOD(miibus_linkchg,       bce_miibus_linkchg),   */
 475 /*      DEVMETHOD(miibus_mediainit,     bce_miibus_mediainit), */
 476
 477         { 0, 0 }
 478 };
 479
 480 static driver_t bce_driver = {
 481         "bce",
 482         bce_methods,
 483         sizeof(struct bce_softc)
 484 };
 485
 486 static devclass_t bce_devclass;
 487
 488 MODULE_DEPEND(bce, pci, 1, 1, 1);
 489 MODULE_DEPEND(bce, ether, 1, 1, 1);
 490 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 491
 492 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0);
 493 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0);
 494
 495
 496 /****************************************************************************/
 497 /* Tunable device values                                                    */
 498 /****************************************************************************/
 499 SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters");
 500
 501 /* Allowable values are TRUE or FALSE */
 502 static int bce_tso_enable = TRUE;
 503 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable);
 504 SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
 505 "TSO Enable/Disable");
 506
 507 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
 508 /* ToDo: Add MSI-X support. */
 509 static int bce_msi_enable = 1;
 510 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable);
 511 SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
 512 "MSI-X|MSI|INTx selector");
 513
 514 /* ToDo: Add tunable to enable/disable strict MTU handling. */
 515 /* Currently allows "loose" RX MTU checking (i.e. sets the  */
 516 /* H/W RX MTU to the size of the largest receive buffer, or */
 517 /* 2048 bytes). This will cause a UNH failure but is more   */
 518 /* desireable from a functional perspective.                */
 519
 520
 521 /****************************************************************************/
 522 /* Device probe function.                                                   */
 523 /*                                                                          */
 524 /* Compares the device to the driver's list of supported devices and        */
 525 /* reports back to the OS whether this is the right driver for the device.  */
 526 /*                                                                          */
 527 /* Returns:                                                                 */
 528 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 529 /****************************************************************************/
 530 static int
 531 bce_probe(device_t dev)
 532 {
 533         struct bce_type *t;
 534         struct bce_softc *sc;
 535         char *descbuf;
 536         u16 vid = 0, did = 0, svid = 0, sdid = 0;
 537
 538         t = bce_devs;
 539
 540         sc = device_get_softc(dev);
 541         bzero(sc, sizeof(struct bce_softc));
 542         sc->bce_unit = device_get_unit(dev);
 543         sc->bce_dev = dev;
 544
 545         /* Get the data for the device to be probed. */
 546         vid  = pci_get_vendor(dev);
 547         did  = pci_get_device(dev);
 548         svid = pci_get_subvendor(dev);
 549         sdid = pci_get_subdevice(dev);
 550
 551         DBPRINT(sc, BCE_EXTREME_LOAD,
 552             "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
 553             "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
 554
 555         /* Look through the list of known devices for a match. */
 556         while(t->bce_name != NULL) {
 557
 558                 if ((vid == t->bce_vid) && (did == t->bce_did) &&
 559                     ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
 560                     ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
 561
 562                         descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
 563
 564                         if (descbuf == NULL)
 565                                 return(ENOMEM);
 566
 567                         /* Print out the device identity. */
 568                         snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 569                             t->bce_name, (((pci_read_config(dev,
 570                             PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
 571                             (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
 572
 573                         device_set_desc_copy(dev, descbuf);
 574                         free(descbuf, M_TEMP);
 575                         return(BUS_PROBE_DEFAULT);
 576                 }
 577                 t++;
 578         }
 579
 580         return(ENXIO);
 581 }
 582
 583
 584 /****************************************************************************/
 585 /* PCI Capabilities Probe Function.                                         */
 586 /*                                                                          */
 587 /* Walks the PCI capabiites list for the device to find what features are   */
 588 /* supported.                                                               */
 589 /*                                                                          */
 590 /* Returns:                                                                 */
 591 /*   None.                                                                  */
 592 /****************************************************************************/
 593 static void
 594 bce_print_adapter_info(struct bce_softc *sc)
 595 {
 596         int i = 0;
 597
 598         DBENTER(BCE_VERBOSE_LOAD);
 599
 600         if (bootverbose) {
 601                 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
 602                 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >>
 603                     12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 604
 605
 606                 /* Bus info. */
 607                 if (sc->bce_flags & BCE_PCIE_FLAG) {
 608                         printf("Bus (PCIe x%d, ", sc->link_width);
 609                         switch (sc->link_speed) {
 610                         case 1: printf("2.5Gbps); "); break;
 611                         case 2: printf("5Gbps); "); break;
 612                         default: printf("Unknown link speed); ");
 613                         }
 614                 } else {
 615                         printf("Bus (PCI%s, %s, %dMHz); ",
 616                             ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 617                             ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
 618                             "32-bit" : "64-bit"), sc->bus_speed_mhz);
 619                 }
 620
 621                 /* Firmware version and device features. */
 622                 printf("B/C (%s); Flags (", sc->bce_bc_ver);
 623
 624         #ifdef BCE_JUMBO_HDRSPLIT
 625                 printf("SPLT");
 626                 i++;
 627         #endif
 628
 629                 if (sc->bce_flags & BCE_USING_MSI_FLAG) {
 630                         if (i > 0) printf("|");
 631                         printf("MSI"); i++;
 632                 }
 633
 634                 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
 635                         if (i > 0) printf("|");
 636                         printf("MSI-X"); i++;
 637                 }
 638
 639                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
 640                         if (i > 0) printf("|");
 641                         printf("2.5G"); i++;
 642                 }
 643
 644                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
 645                         if (i > 0) printf("|");
 646                         printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
 647                 } else {
 648                         printf(")\n");
 649                 }
 650         }
 651
 652         DBEXIT(BCE_VERBOSE_LOAD);
 653 }
 654
 655
 656 /****************************************************************************/
 657 /* PCI Capabilities Probe Function.                                         */
 658 /*                                                                          */
 659 /* Walks the PCI capabiites list for the device to find what features are   */
 660 /* supported.                                                               */
 661 /*                                                                          */
 662 /* Returns:                                                                 */
 663 /*   None.                                                                  */
 664 /****************************************************************************/
 665 static void
 666 bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
 667 {
 668         u32 reg;
 669
 670         DBENTER(BCE_VERBOSE_LOAD);
 671
 672         /* Check if PCI-X capability is enabled. */
 673         if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0) {
 674                 if (reg != 0)
 675                         sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 676         }
 677
 678         /* Check if PCIe capability is enabled. */
 679         if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
 680                 if (reg != 0) {
 681                         u16 link_status = pci_read_config(dev, reg + 0x12, 2);
 682                         DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = "
 683                             "0x%08X\n", link_status);
 684                         sc->link_speed = link_status & 0xf;
 685                         sc->link_width = (link_status >> 4) & 0x3f;
 686                         sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 687                         sc->bce_flags |= BCE_PCIE_FLAG;
 688                 }
 689         }
 690
 691         /* Check if MSI capability is enabled. */
 692         if (pci_find_extcap(dev, PCIY_MSI, &reg) == 0) {
 693                 if (reg != 0)
 694                         sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
 695         }
 696
 697         /* Check if MSI-X capability is enabled. */
 698         if (pci_find_extcap(dev, PCIY_MSIX, &reg) == 0) {
 699                 if (reg != 0)
 700                         sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
 701         }
 702
 703         DBEXIT(BCE_VERBOSE_LOAD);
 704 }
 705
 706
 707 /****************************************************************************/
 708 /* Device attach function.                                                  */
 709 /*                                                                          */
 710 /* Allocates device resources, performs secondary chip identification,      */
 711 /* resets and initializes the hardware, and initializes driver instance     */
 712 /* variables.                                                               */
 713 /*                                                                          */
 714 /* Returns:                                                                 */
 715 /*   0 on success, positive value on failure.                               */
 716 /****************************************************************************/
 717 static int
 718 bce_attach(device_t dev)
 719 {
 720         struct bce_softc *sc;
 721         struct ifnet *ifp;
 722         u32 val;
 723         int error, rid, rc = 0;
 724
 725         sc = device_get_softc(dev);
 726         sc->bce_dev = dev;
 727
 728         DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
 729
 730         sc->bce_unit = device_get_unit(dev);
 731
 732         /* Set initial device and PHY flags */
 733         sc->bce_flags = 0;
 734         sc->bce_phy_flags = 0;
 735
 736         pci_enable_busmaster(dev);
 737
 738         /* Allocate PCI memory resources. */
 739         rid = PCIR_BAR(0);
 740         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 741                 &rid, RF_ACTIVE);
 742
 743         if (sc->bce_res_mem == NULL) {
 744                 BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
 745                     __FILE__, __LINE__);
 746                 rc = ENXIO;
 747                 goto bce_attach_fail;
 748         }
 749
 750         /* Get various resource handles. */
 751         sc->bce_btag    = rman_get_bustag(sc->bce_res_mem);
 752         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 753         sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
 754
 755         bce_probe_pci_caps(dev, sc);
 756
 757         rid = 1;
 758 #if 0
 759         /* Try allocating MSI-X interrupts. */
 760         if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
 761                 (bce_msi_enable >= 2) &&
 762                 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 763                 &rid, RF_ACTIVE)) != NULL)) {
 764
 765                 msi_needed = sc->bce_msi_count = 1;
 766
 767                 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) ||
 768                         (sc->bce_msi_count != msi_needed)) {
 769                         BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
 770                                 "Received = %d, error = %d\n", __FILE__, __LINE__,
 771                                 msi_needed, sc->bce_msi_count, error);
 772                         sc->bce_msi_count = 0;
 773                         pci_release_msi(dev);
 774                         bus_release_resource(dev, SYS_RES_MEMORY, rid,
 775                                 sc->bce_res_irq);
 776                         sc->bce_res_irq = NULL;
 777                 } else {
 778                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
 779                                 __FUNCTION__);
 780                         sc->bce_flags |= BCE_USING_MSIX_FLAG;
 781                         sc->bce_intr = bce_intr;
 782                 }
 783         }
 784 #endif
 785
 786         /* Try allocating a MSI interrupt. */
 787         if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
 788                 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) {
 789                 sc->bce_msi_count = 1;
 790                 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) {
 791                         BCE_PRINTF("%s(%d): MSI allocation failed! "
 792                             "error = %d\n", __FILE__, __LINE__, error);
 793                         sc->bce_msi_count = 0;
 794                         pci_release_msi(dev);
 795                 } else {
 796                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI "
 797                             "interrupt.\n", __FUNCTION__);
 798                         sc->bce_flags |= BCE_USING_MSI_FLAG;
 799                         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
 800                                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
 801                                 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
 802                         sc->bce_irq_rid = 1;
 803                         sc->bce_intr = bce_intr;
 804                 }
 805         }
 806
 807         /* Try allocating a legacy interrupt. */
 808         if (sc->bce_msi_count == 0) {
 809                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
 810                         __FUNCTION__);
 811                 rid = 0;
 812                 sc->bce_intr = bce_intr;
 813         }
 814
 815         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 816             &rid, RF_SHAREABLE | RF_ACTIVE);
 817
 818         sc->bce_irq_rid = rid;
 819
 820         /* Report any IRQ allocation errors. */
 821         if (sc->bce_res_irq == NULL) {
 822                 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
 823                     __FILE__, __LINE__);
 824                 rc = ENXIO;
 825                 goto bce_attach_fail;
 826         }
 827
 828         /* Initialize mutex for the current device instance. */
 829         BCE_LOCK_INIT(sc, device_get_nameunit(dev));
 830
 831         /*
 832          * Configure byte swap and enable indirect register access.
 833          * Rely on CPU to do target byte swapping on big endian systems.
 834          * Access to registers outside of PCI configurtion space are not
 835          * valid until this is done.
 836          */
 837         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 838             BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 839             BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 840
 841         /* Save ASIC revsion info. */
 842         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 843
 844         /* Weed out any non-production controller revisions. */
 845         switch(BCE_CHIP_ID(sc)) {
 846         case BCE_CHIP_ID_5706_A0:
 847         case BCE_CHIP_ID_5706_A1:
 848         case BCE_CHIP_ID_5708_A0:
 849         case BCE_CHIP_ID_5708_B0:
 850         case BCE_CHIP_ID_5709_A0:
 851         case BCE_CHIP_ID_5709_B0:
 852         case BCE_CHIP_ID_5709_B1:
 853         case BCE_CHIP_ID_5709_B2:
 854                 BCE_PRINTF("%s(%d): Unsupported controller "
 855                     "revision (%c%d)!\n", __FILE__, __LINE__,
 856                     (((pci_read_config(dev, PCIR_REVID, 4) &
 857                     0xf0) >> 4) + 'A'), (pci_read_config(dev,
 858                     PCIR_REVID, 4) & 0xf));
 859                 rc = ENODEV;
 860                 goto bce_attach_fail;
 861         }
 862
 863         /*
 864          * The embedded PCIe to PCI-X bridge (EPB)
 865          * in the 5708 cannot address memory above
 866          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
 867          */
 868         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
 869                 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
 870         else
 871                 sc->max_bus_addr = BUS_SPACE_MAXADDR;
 872
 873         /*
 874          * Find the base address for shared memory access.
 875          * Newer versions of bootcode use a signature and offset
 876          * while older versions use a fixed address.
 877          */
 878         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 879         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
 880                 /* Multi-port devices use different offsets in shared memory. */
 881                 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
 882                     (pci_get_function(sc->bce_dev) << 2));
 883         else
 884                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 885
 886         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
 887             __FUNCTION__, sc->bce_shmem_base);
 888
 889         /* Fetch the bootcode revision. */
 890         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
 891         for (int i = 0, j = 0; i < 3; i++) {
 892                 u8 num;
 893
 894                 num = (u8) (val >> (24 - (i * 8)));
 895                 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
 896                         if (num >= k || !skip0 || k == 1) {
 897                                 sc->bce_bc_ver[j++] = (num / k) + '0';
 898                                 skip0 = 0;
 899                         }
 900                 }
 901
 902                 if (i != 2)
 903                         sc->bce_bc_ver[j++] = '.';
 904         }
 905
 906         /* Check if any management firwmare is enabled. */
 907         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
 908         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
 909                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
 910
 911                 /* Allow time for firmware to enter the running state. */
 912                 for (int i = 0; i < 30; i++) {
 913                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
 914                         if (val & BCE_CONDITION_MFW_RUN_MASK)
 915                                 break;
 916                         DELAY(10000);
 917                 }
 918
 919                 /* Check if management firmware is running. */
 920                 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
 921                 val &= BCE_CONDITION_MFW_RUN_MASK;
 922                 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) &&
 923                     (val != BCE_CONDITION_MFW_RUN_NONE)) {
 924                         u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
 925                         int i = 0;
 926
 927                         /* Read the management firmware version string. */
 928                         for (int j = 0; j < 3; j++) {
 929                                 val = bce_reg_rd_ind(sc, addr + j * 4);
 930                                 val = bswap32(val);
 931                                 memcpy(&sc->bce_mfw_ver[i], &val, 4);
 932                                 i += 4;
 933                         }
 934                 } else {
 935                         /* May cause firmware synchronization timeouts. */
 936                         BCE_PRINTF("%s(%d): Management firmware enabled "
 937                             "but not running!\n", __FILE__, __LINE__);
 938                         strcpy(sc->bce_mfw_ver, "NOT RUNNING!");
 939
 940                         /* ToDo: Any action the driver should take? */
 941                 }
 942         }
 943
 944         /* Get PCI bus information (speed and type). */
 945         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 946         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 947                 u32 clkreg;
 948
 949                 sc->bce_flags |= BCE_PCIX_FLAG;
 950
 951                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);
 952
 953                 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 954                 switch (clkreg) {
 955                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 956                         sc->bus_speed_mhz = 133;
 957                         break;
 958
 959                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 960                         sc->bus_speed_mhz = 100;
 961                         break;
 962
 963                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 964                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 965                         sc->bus_speed_mhz = 66;
 966                         break;
 967
 968                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 969                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 970                         sc->bus_speed_mhz = 50;
 971                         break;
 972
 973                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 974                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 975                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 976                         sc->bus_speed_mhz = 33;
 977                         break;
 978                 }
 979         } else {
 980                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 981                         sc->bus_speed_mhz = 66;
 982                 else
 983                         sc->bus_speed_mhz = 33;
 984         }
 985
 986         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 987                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 988
 989         /* Reset controller and announce to bootcode that driver is present. */
 990         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
 991                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
 992                     __FILE__, __LINE__);
 993                 rc = ENXIO;
 994                 goto bce_attach_fail;
 995         }
 996
 997         /* Initialize the controller. */
 998         if (bce_chipinit(sc)) {
 999                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
1000                     __FILE__, __LINE__);
1001                 rc = ENXIO;
1002                 goto bce_attach_fail;
1003         }
1004
1005         /* Perform NVRAM test. */
1006         if (bce_nvram_test(sc)) {
1007                 BCE_PRINTF("%s(%d): NVRAM test failed!\n",
1008                     __FILE__, __LINE__);
1009                 rc = ENXIO;
1010                 goto bce_attach_fail;
1011         }
1012
1013         /* Fetch the permanent Ethernet MAC address. */
1014         bce_get_mac_addr(sc);
1015
1016         /*
1017          * Trip points control how many BDs
1018          * should be ready before generating an
1019          * interrupt while ticks control how long
1020          * a BD can sit in the chain before
1021          * generating an interrupt.  Set the default
1022          * values for the RX and TX chains.
1023          */
1024
1025 #ifdef BCE_DEBUG
1026         /* Force more frequent interrupts. */
1027         sc->bce_tx_quick_cons_trip_int = 1;
1028         sc->bce_tx_quick_cons_trip     = 1;
1029         sc->bce_tx_ticks_int           = 0;
1030         sc->bce_tx_ticks               = 0;
1031
1032         sc->bce_rx_quick_cons_trip_int = 1;
1033         sc->bce_rx_quick_cons_trip     = 1;
1034         sc->bce_rx_ticks_int           = 0;
1035         sc->bce_rx_ticks               = 0;
1036 #else
1037         /* Improve throughput at the expense of increased latency. */
1038         sc->bce_tx_quick_cons_trip_int = 20;
1039         sc->bce_tx_quick_cons_trip     = 20;
1040         sc->bce_tx_ticks_int           = 80;
1041         sc->bce_tx_ticks               = 80;
1042
1043         sc->bce_rx_quick_cons_trip_int = 6;
1044         sc->bce_rx_quick_cons_trip     = 6;
1045         sc->bce_rx_ticks_int           = 18;
1046         sc->bce_rx_ticks               = 18;
1047 #endif
1048
1049         /* Not used for L2. */
1050         sc->bce_comp_prod_trip_int = 0;
1051         sc->bce_comp_prod_trip = 0;
1052         sc->bce_com_ticks_int = 0;
1053         sc->bce_com_ticks = 0;
1054         sc->bce_cmd_ticks_int = 0;
1055         sc->bce_cmd_ticks = 0;
1056
1057         /* Update statistics once every second. */
1058         sc->bce_stats_ticks = 1000000 & 0xffff00;
1059
1060         /* Find the media type for the adapter. */
1061         bce_get_media(sc);
1062
1063         /* Store data needed by PHY driver for backplane applications */
1064         sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1065         sc->bce_port_hw_cfg   = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1066
1067         /* Allocate DMA memory resources. */
1068         if (bce_dma_alloc(dev)) {
1069                 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
1070                     __FILE__, __LINE__);
1071                 rc = ENXIO;
1072                 goto bce_attach_fail;
1073         }
1074
1075         /* Allocate an ifnet structure. */
1076         ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
1077         if (ifp == NULL) {
1078                 BCE_PRINTF("%s(%d): Interface allocation failed!\n",
1079                     __FILE__, __LINE__);
1080                 rc = ENXIO;
1081                 goto bce_attach_fail;
1082         }
1083
1084         /* Initialize the ifnet interface. */
1085         ifp->if_softc   = sc;
1086         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1087         ifp->if_flags   = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1088         ifp->if_ioctl   = bce_ioctl;
1089         ifp->if_start   = bce_start;
1090         ifp->if_init    = bce_init;
1091         ifp->if_mtu     = ETHERMTU;
1092
1093         if (bce_tso_enable) {
1094                 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO;
1095                 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 |
1096                     IFCAP_VLAN_HWTSO;
1097         } else {
1098                 ifp->if_hwassist = BCE_IF_HWASSIST;
1099                 ifp->if_capabilities = BCE_IF_CAPABILITIES;
1100         }
1101
1102         ifp->if_capenable = ifp->if_capabilities;
1103
1104         /*
1105          * Assume standard mbuf sizes for buffer allocation.
1106          * This may change later if the MTU size is set to
1107          * something other than 1500.
1108          */
1109 #ifdef BCE_JUMBO_HDRSPLIT
1110         sc->rx_bd_mbuf_alloc_size = MHLEN;
1111         /* Make sure offset is 16 byte aligned for hardware. */
1112         sc->rx_bd_mbuf_align_pad =
1113             roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN);
1114         sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
1115             sc->rx_bd_mbuf_align_pad;
1116         sc->pg_bd_mbuf_alloc_size = MCLBYTES;
1117 #else
1118         sc->rx_bd_mbuf_alloc_size = MCLBYTES;
1119         sc->rx_bd_mbuf_align_pad =
1120             roundup2(MCLBYTES, 16) - MCLBYTES;
1121         sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
1122             sc->rx_bd_mbuf_align_pad;
1123 #endif
1124
1125         ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD;
1126         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1127         IFQ_SET_READY(&ifp->if_snd);
1128
1129         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1130                 ifp->if_baudrate = IF_Mbps(2500ULL);
1131         else
1132                 ifp->if_baudrate = IF_Mbps(1000);
1133
1134         /* Handle any special PHY initialization for SerDes PHYs. */
1135         bce_init_media(sc);
1136
1137         /* MII child bus by probing the PHY. */
1138         if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd,
1139                 bce_ifmedia_sts)) {
1140                 BCE_PRINTF("%s(%d): No PHY found on child MII bus!\n",
1141                     __FILE__, __LINE__);
1142                 rc = ENXIO;
1143                 goto bce_attach_fail;
1144         }
1145
1146         /* Attach to the Ethernet interface list. */
1147         ether_ifattach(ifp, sc->eaddr);
1148
1149 #if __FreeBSD_version < 500000
1150         callout_init(&sc->bce_tick_callout);
1151         callout_init(&sc->bce_pulse_callout);
1152 #else
1153         callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1154         callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1155 #endif
1156
1157         /* Hookup IRQ last. */
1158         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1159                 NULL, bce_intr, sc, &sc->bce_intrhand);
1160
1161         if (rc) {
1162                 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
1163                     __FILE__, __LINE__);
1164                 bce_detach(dev);
1165                 goto bce_attach_exit;
1166         }
1167
1168         /*
1169          * At this point we've acquired all the resources
1170          * we need to run so there's no turning back, we're
1171          * cleared for launch.
1172          */
1173
1174         /* Print some important debugging info. */
1175         DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
1176
1177         /* Add the supported sysctls to the kernel. */
1178         bce_add_sysctls(sc);
1179
1180         BCE_LOCK(sc);
1181
1182         /*
1183          * The chip reset earlier notified the bootcode that
1184          * a driver is present.  We now need to start our pulse
1185          * routine so that the bootcode is reminded that we're
1186          * still running.
1187          */
1188         bce_pulse(sc);
1189
1190         bce_mgmt_init_locked(sc);
1191         BCE_UNLOCK(sc);
1192
1193         /* Finally, print some useful adapter info */
1194         bce_print_adapter_info(sc);
1195         DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
1196                 __FUNCTION__, sc);
1197
1198         goto bce_attach_exit;
1199
1200 bce_attach_fail:
1201         bce_release_resources(sc);
1202
1203 bce_attach_exit:
1204
1205         DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1206
1207         return(rc);
1208 }
1209
1210
1211 /****************************************************************************/
1212 /* Device detach function.                                                  */
1213 /*                                                                          */
1214 /* Stops the controller, resets the controller, and releases resources.     */
1215 /*                                                                          */
1216 /* Returns:                                                                 */
1217 /*   0 on success, positive value on failure.                               */
1218 /****************************************************************************/
1219 static int
1220 bce_detach(device_t dev)
1221 {
1222         struct bce_softc *sc = device_get_softc(dev);
1223         struct ifnet *ifp;
1224         u32 msg;
1225
1226         DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1227
1228         ifp = sc->bce_ifp;
1229
1230         /* Stop and reset the controller. */
1231         BCE_LOCK(sc);
1232
1233         /* Stop the pulse so the bootcode can go to driver absent state. */
1234         callout_stop(&sc->bce_pulse_callout);
1235
1236         bce_stop(sc);
1237         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1238                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1239         else
1240                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1241         bce_reset(sc, msg);
1242
1243         BCE_UNLOCK(sc);
1244
1245         ether_ifdetach(ifp);
1246
1247         /* If we have a child device on the MII bus remove it too. */
1248         bus_generic_detach(dev);
1249         device_delete_child(dev, sc->bce_miibus);
1250
1251         /* Release all remaining resources. */
1252         bce_release_resources(sc);
1253
1254         DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1255
1256         return(0);
1257 }
1258
1259
1260 /****************************************************************************/
1261 /* Device shutdown function.                                                */
1262 /*                                                                          */
1263 /* Stops and resets the controller.                                         */
1264 /*                                                                          */
1265 /* Returns:                                                                 */
1266 /*   0 on success, positive value on failure.                               */
1267 /****************************************************************************/
1268 static int
1269 bce_shutdown(device_t dev)
1270 {
1271         struct bce_softc *sc = device_get_softc(dev);
1272         u32 msg;
1273
1274         DBENTER(BCE_VERBOSE);
1275
1276         BCE_LOCK(sc);
1277         bce_stop(sc);
1278         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1279                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1280         else
1281                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1282         bce_reset(sc, msg);
1283         BCE_UNLOCK(sc);
1284
1285         DBEXIT(BCE_VERBOSE);
1286
1287         return (0);
1288 }
1289
1290
1291 #ifdef BCE_DEBUG
1292 /****************************************************************************/
1293 /* Register read.                                                           */
1294 /*                                                                          */
1295 /* Returns:                                                                 */
1296 /*   The value of the register.                                             */
1297 /****************************************************************************/
1298 static u32
1299 bce_reg_rd(struct bce_softc *sc, u32 offset)
1300 {
1301         u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset);
1302         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1303                 __FUNCTION__, offset, val);
1304         return val;
1305 }
1306
1307
1308 /****************************************************************************/
1309 /* Register write (16 bit).                                                 */
1310 /*                                                                          */
1311 /* Returns:                                                                 */
1312 /*   Nothing.                                                               */
1313 /****************************************************************************/
1314 static void
1315 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1316 {
1317         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1318                 __FUNCTION__, offset, val);
1319         bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val);
1320 }
1321
1322
1323 /****************************************************************************/
1324 /* Register write.                                                          */
1325 /*                                                                          */
1326 /* Returns:                                                                 */
1327 /*   Nothing.                                                               */
1328 /****************************************************************************/
1329 static void
1330 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1331 {
1332         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1333                 __FUNCTION__, offset, val);
1334         bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val);
1335 }
1336 #endif
1337
1338 /****************************************************************************/
1339 /* Indirect register read.                                                  */
1340 /*                                                                          */
1341 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1342 /* configuration space.  Using this mechanism avoids issues with posted     */
1343 /* reads but is much slower than memory-mapped I/O.                         */
1344 /*                                                                          */
1345 /* Returns:                                                                 */
1346 /*   The value of the register.                                             */
1347 /****************************************************************************/
1348 static u32
1349 bce_reg_rd_ind(struct bce_softc *sc, u32 offset)
1350 {
1351         device_t dev;
1352         dev = sc->bce_dev;
1353
1354         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1355 #ifdef BCE_DEBUG
1356         {
1357                 u32 val;
1358                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1359                 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1360                         __FUNCTION__, offset, val);
1361                 return val;
1362         }
1363 #else
1364         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1365 #endif
1366 }
1367
1368
1369 /****************************************************************************/
1370 /* Indirect register write.                                                 */
1371 /*                                                                          */
1372 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1373 /* configuration space.  Using this mechanism avoids issues with posted     */
1374 /* writes but is muchh slower than memory-mapped I/O.                       */
1375 /*                                                                          */
1376 /* Returns:                                                                 */
1377 /*   Nothing.                                                               */
1378 /****************************************************************************/
1379 static void
1380 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1381 {
1382         device_t dev;
1383         dev = sc->bce_dev;
1384
1385         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1386                 __FUNCTION__, offset, val);
1387
1388         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1389         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1390 }
1391
1392
1393 /****************************************************************************/
1394 /* Shared memory write.                                                     */
1395 /*                                                                          */
1396 /* Writes NetXtreme II shared memory region.                                */
1397 /*                                                                          */
1398 /* Returns:                                                                 */
1399 /*   Nothing.                                                               */
1400 /****************************************************************************/
1401 static void
1402 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val)
1403 {
1404         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X  to  "
1405             "0x%08X\n", __FUNCTION__, val, offset);
1406
1407         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1408 }
1409
1410
1411 /****************************************************************************/
1412 /* Shared memory read.                                                      */
1413 /*                                                                          */
1414 /* Reads NetXtreme II shared memory region.                                 */
1415 /*                                                                          */
1416 /* Returns:                                                                 */
1417 /*   The 32 bit value read.                                                 */
1418 /****************************************************************************/
1419 static u32
1420 bce_shmem_rd(struct bce_softc *sc, u32 offset)
1421 {
1422         u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1423
1424         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from "
1425             "0x%08X\n", __FUNCTION__, val, offset);
1426
1427         return val;
1428 }
1429
1430
1431 #ifdef BCE_DEBUG
1432 /****************************************************************************/
1433 /* Context memory read.                                                     */
1434 /*                                                                          */
1435 /* The NetXtreme II controller uses context memory to track connection      */
1436 /* information for L2 and higher network protocols.                         */
1437 /*                                                                          */
1438 /* Returns:                                                                 */
1439 /*   The requested 32 bit value of context memory.                          */
1440 /****************************************************************************/
1441 static u32
1442 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset)
1443 {
1444         u32 idx, offset, retry_cnt = 5, val;
1445
1446         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 ||
1447             cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID "
1448             "address: 0x%08X.\n", __FUNCTION__, cid_addr));
1449
1450         offset = ctx_offset + cid_addr;
1451
1452         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
1453                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
1454
1455                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1456
1457                 for (idx = 0; idx < retry_cnt; idx++) {
1458                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1459                         if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1460                                 break;
1461                         DELAY(5);
1462                 }
1463
1464                 if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1465                         BCE_PRINTF("%s(%d); Unable to read CTX memory: "
1466                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1467                             __FILE__, __LINE__, cid_addr, ctx_offset);
1468
1469                 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1470         } else {
1471                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1472                 val = REG_RD(sc, BCE_CTX_DATA);
1473         }
1474
1475         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1476                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1477
1478         return(val);
1479 }
1480 #endif
1481
1482
1483 /****************************************************************************/
1484 /* Context memory write.                                                    */
1485 /*                                                                          */
1486 /* The NetXtreme II controller uses context memory to track connection      */
1487 /* information for L2 and higher network protocols.                         */
1488 /*                                                                          */
1489 /* Returns:                                                                 */
1490 /*   Nothing.                                                               */
1491 /****************************************************************************/
1492 static void
1493 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val)
1494 {
1495         u32 idx, offset = ctx_offset + cid_addr;
1496         u32 val, retry_cnt = 5;
1497
1498         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1499                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1500
1501         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1502                 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1503                     __FUNCTION__, cid_addr));
1504
1505         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
1506                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
1507
1508                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1509                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1510
1511                 for (idx = 0; idx < retry_cnt; idx++) {
1512                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1513                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1514                                 break;
1515                         DELAY(5);
1516                 }
1517
1518                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1519                         BCE_PRINTF("%s(%d); Unable to write CTX memory: "
1520                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1521                             __FILE__, __LINE__, cid_addr, ctx_offset);
1522
1523         } else {
1524                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1525                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1526         }
1527 }
1528
1529
1530 /****************************************************************************/
1531 /* PHY register read.                                                       */
1532 /*                                                                          */
1533 /* Implements register reads on the MII bus.                                */
1534 /*                                                                          */
1535 /* Returns:                                                                 */
1536 /*   The value of the register.                                             */
1537 /****************************************************************************/
1538 static int
1539 bce_miibus_read_reg(device_t dev, int phy, int reg)
1540 {
1541         struct bce_softc *sc;
1542         u32 val;
1543         int i;
1544
1545         sc = device_get_softc(dev);
1546
1547         /* Make sure we are accessing the correct PHY address. */
1548         if (phy != sc->bce_phy_addr) {
1549                 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d "
1550                     "for PHY read!\n", phy);
1551                 return(0);
1552         }
1553
1554     /*
1555      * The 5709S PHY is an IEEE Clause 45 PHY
1556      * with special mappings to work with IEEE
1557      * Clause 22 register accesses.
1558      */
1559         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1560                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1561                         reg += 0x10;
1562         }
1563
1564     if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1565                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1566                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1567
1568                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1569                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1570
1571                 DELAY(40);
1572         }
1573
1574
1575         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1576             BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1577             BCE_EMAC_MDIO_COMM_START_BUSY;
1578         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1579
1580         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1581                 DELAY(10);
1582
1583                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1584                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1585                         DELAY(5);
1586
1587                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1588                         val &= BCE_EMAC_MDIO_COMM_DATA;
1589
1590                         break;
1591                 }
1592         }
1593
1594         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1595                 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, "
1596                     "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
1597                 val = 0x0;
1598         } else {
1599                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1600         }
1601
1602
1603         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1604                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1605                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1606
1607                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1608                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1609
1610                 DELAY(40);
1611         }
1612
1613         DB_PRINT_PHY_REG(reg, val);
1614         return (val & 0xffff);
1615
1616 }
1617
1618
1619 /****************************************************************************/
1620 /* PHY register write.                                                      */
1621 /*                                                                          */
1622 /* Implements register writes on the MII bus.                               */
1623 /*                                                                          */
1624 /* Returns:                                                                 */
1625 /*   The value of the register.                                             */
1626 /****************************************************************************/
1627 static int
1628 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1629 {
1630         struct bce_softc *sc;
1631         u32 val1;
1632         int i;
1633
1634         sc = device_get_softc(dev);
1635
1636         /* Make sure we are accessing the correct PHY address. */
1637         if (phy != sc->bce_phy_addr) {
1638                 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d "
1639                     "for PHY write!\n", phy);
1640                 return(0);
1641         }
1642
1643         DB_PRINT_PHY_REG(reg, val);
1644
1645         /*
1646          * The 5709S PHY is an IEEE Clause 45 PHY
1647          * with special mappings to work with IEEE
1648          * Clause 22 register accesses.
1649          */
1650         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1651                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1652                         reg += 0x10;
1653         }
1654
1655         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1656                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1657                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1658
1659                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1660                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1661
1662                 DELAY(40);
1663         }
1664
1665         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1666             BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1667             BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1668         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1669
1670         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1671                 DELAY(10);
1672
1673                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1674                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1675                         DELAY(5);
1676                         break;
1677                 }
1678         }
1679
1680         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1681                 BCE_PRINTF("%s(%d): PHY write timeout!\n",
1682                     __FILE__, __LINE__);
1683
1684         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1685                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1686                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1687
1688                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1689                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1690
1691                 DELAY(40);
1692         }
1693
1694         return 0;
1695 }
1696
1697
1698 /****************************************************************************/
1699 /* MII bus status change.                                                   */
1700 /*                                                                          */
1701 /* Called by the MII bus driver when the PHY establishes link to set the    */
1702 /* MAC interface registers.                                                 */
1703 /*                                                                          */
1704 /* Returns:                                                                 */
1705 /*   Nothing.                                                               */
1706 /****************************************************************************/
1707 static void
1708 bce_miibus_statchg(device_t dev)
1709 {
1710         struct bce_softc *sc;
1711         struct mii_data *mii;
1712         int val;
1713
1714         sc = device_get_softc(dev);
1715
1716         DBENTER(BCE_VERBOSE_PHY);
1717
1718         mii = device_get_softc(sc->bce_miibus);
1719
1720         val = REG_RD(sc, BCE_EMAC_MODE);
1721         val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
1722             BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
1723             BCE_EMAC_MODE_25G);
1724
1725         /* Set MII or GMII interface based on the PHY speed. */
1726         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1727         case IFM_10_T:
1728                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1729                         DBPRINT(sc, BCE_INFO_PHY,
1730                             "Enabling 10Mb interface.\n");
1731                         val |= BCE_EMAC_MODE_PORT_MII_10;
1732                         break;
1733                 }
1734                 /* fall-through */
1735         case IFM_100_TX:
1736                 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
1737                 val |= BCE_EMAC_MODE_PORT_MII;
1738                 break;
1739         case IFM_2500_SX:
1740                 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
1741                 val |= BCE_EMAC_MODE_25G;
1742                 /* fall-through */
1743         case IFM_1000_T:
1744         case IFM_1000_SX:
1745                 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
1746                 val |= BCE_EMAC_MODE_PORT_GMII;
1747                 break;
1748         default:
1749                 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
1750                     "default GMII interface.\n");
1751                 val |= BCE_EMAC_MODE_PORT_GMII;
1752         }
1753
1754         /* Set half or full duplex based on PHY settings. */
1755         if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
1756                 DBPRINT(sc, BCE_INFO_PHY,
1757                     "Setting Half-Duplex interface.\n");
1758                 val |= BCE_EMAC_MODE_HALF_DUPLEX;
1759         } else
1760                 DBPRINT(sc, BCE_INFO_PHY,
1761                     "Setting Full-Duplex interface.\n");
1762
1763         REG_WR(sc, BCE_EMAC_MODE, val);
1764
1765         /* FLAG0 is set if RX is enabled and FLAG1 if TX is enabled */
1766         if (mii->mii_media_active & IFM_FLAG0) {
1767                 DBPRINT(sc, BCE_INFO_PHY,
1768                     "%s(): Enabling RX flow control.\n", __FUNCTION__);
1769                 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
1770         } else {
1771                 DBPRINT(sc, BCE_INFO_PHY,
1772                     "%s(): Disabling RX flow control.\n", __FUNCTION__);
1773                 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
1774         }
1775
1776         if (mii->mii_media_active & IFM_FLAG1) {
1777                 DBPRINT(sc, BCE_INFO_PHY,
1778                     "%s(): Enabling TX flow control.\n", __FUNCTION__);
1779                 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
1780                 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL;
1781         } else {
1782                 DBPRINT(sc, BCE_INFO_PHY,
1783                     "%s(): Disabling TX flow control.\n", __FUNCTION__);
1784                 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
1785                 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL;
1786         }
1787
1788         /* ToDo: Update watermarks in bce_init_rx_context(). */
1789
1790         DBEXIT(BCE_VERBOSE_PHY);
1791 }
1792
1793
1794 /****************************************************************************/
1795 /* Acquire NVRAM lock.                                                      */
1796 /*                                                                          */
1797 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1798 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1799 /* for use by the driver.                                                   */
1800 /*                                                                          */
1801 /* Returns:                                                                 */
1802 /*   0 on success, positive value on failure.                               */
1803 /****************************************************************************/
1804 static int
1805 bce_acquire_nvram_lock(struct bce_softc *sc)
1806 {
1807         u32 val;
1808         int j, rc = 0;
1809
1810         DBENTER(BCE_VERBOSE_NVRAM);
1811
1812         /* Request access to the flash interface. */
1813         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1814         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1815                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1816                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1817                         break;
1818
1819                 DELAY(5);
1820         }
1821
1822         if (j >= NVRAM_TIMEOUT_COUNT) {
1823                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1824                 rc = EBUSY;
1825         }
1826
1827         DBEXIT(BCE_VERBOSE_NVRAM);
1828         return (rc);
1829 }
1830
1831
1832 /****************************************************************************/
1833 /* Release NVRAM lock.                                                      */
1834 /*                                                                          */
1835 /* When the caller is finished accessing NVRAM the lock must be released.   */
1836 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1837 /* for use by the driver.                                                   */
1838 /*                                                                          */
1839 /* Returns:                                                                 */
1840 /*   0 on success, positive value on failure.                               */
1841 /****************************************************************************/
1842 static int
1843 bce_release_nvram_lock(struct bce_softc *sc)
1844 {
1845         u32 val;
1846         int j, rc = 0;
1847
1848         DBENTER(BCE_VERBOSE_NVRAM);
1849
1850         /*
1851          * Relinquish nvram interface.
1852          */
1853         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1854
1855         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1856                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1857                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1858                         break;
1859
1860                 DELAY(5);
1861         }
1862
1863         if (j >= NVRAM_TIMEOUT_COUNT) {
1864                 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
1865                 rc = EBUSY;
1866         }
1867
1868         DBEXIT(BCE_VERBOSE_NVRAM);
1869         return (rc);
1870 }
1871
1872
1873 #ifdef BCE_NVRAM_WRITE_SUPPORT
1874 /****************************************************************************/
1875 /* Enable NVRAM write access.                                               */
1876 /*                                                                          */
1877 /* Before writing to NVRAM the caller must enable NVRAM writes.             */
1878 /*                                                                          */
1879 /* Returns:                                                                 */
1880 /*   0 on success, positive value on failure.                               */
1881 /****************************************************************************/
1882 static int
1883 bce_enable_nvram_write(struct bce_softc *sc)
1884 {
1885         u32 val;
1886         int rc = 0;
1887
1888         DBENTER(BCE_VERBOSE_NVRAM);
1889
1890         val = REG_RD(sc, BCE_MISC_CFG);
1891         REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
1892
1893         if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
1894                 int j;
1895
1896                 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1897                 REG_WR(sc, BCE_NVM_COMMAND,     BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
1898
1899                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1900                         DELAY(5);
1901
1902                         val = REG_RD(sc, BCE_NVM_COMMAND);
1903                         if (val & BCE_NVM_COMMAND_DONE)
1904                                 break;
1905                 }
1906
1907                 if (j >= NVRAM_TIMEOUT_COUNT) {
1908                         DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
1909                         rc = EBUSY;
1910                 }
1911         }
1912
1913         DBENTER(BCE_VERBOSE_NVRAM);
1914         return (rc);
1915 }
1916
1917
1918 /****************************************************************************/
1919 /* Disable NVRAM write access.                                              */
1920 /*                                                                          */
1921 /* When the caller is finished writing to NVRAM write access must be        */
1922 /* disabled.                                                                */
1923 /*                                                                          */
1924 /* Returns:                                                                 */
1925 /*   Nothing.                                                               */
1926 /****************************************************************************/
1927 static void
1928 bce_disable_nvram_write(struct bce_softc *sc)
1929 {
1930         u32 val;
1931
1932         DBENTER(BCE_VERBOSE_NVRAM);
1933
1934         val = REG_RD(sc, BCE_MISC_CFG);
1935         REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
1936
1937         DBEXIT(BCE_VERBOSE_NVRAM);
1938
1939 }
1940 #endif
1941
1942
1943 /****************************************************************************/
1944 /* Enable NVRAM access.                                                     */
1945 /*                                                                          */
1946 /* Before accessing NVRAM for read or write operations the caller must      */
1947 /* enabled NVRAM access.                                                    */
1948 /*                                                                          */
1949 /* Returns:                                                                 */
1950 /*   Nothing.                                                               */
1951 /****************************************************************************/
1952 static void
1953 bce_enable_nvram_access(struct bce_softc *sc)
1954 {
1955         u32 val;
1956
1957         DBENTER(BCE_VERBOSE_NVRAM);
1958
1959         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1960         /* Enable both bits, even on read. */
1961         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
1962             BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1963
1964         DBEXIT(BCE_VERBOSE_NVRAM);
1965 }
1966
1967
1968 /****************************************************************************/
1969 /* Disable NVRAM access.                                                    */
1970 /*                                                                          */
1971 /* When the caller is finished accessing NVRAM access must be disabled.     */
1972 /*                                                                          */
1973 /* Returns:                                                                 */
1974 /*   Nothing.                                                               */
1975 /****************************************************************************/
1976 static void
1977 bce_disable_nvram_access(struct bce_softc *sc)
1978 {
1979         u32 val;
1980
1981         DBENTER(BCE_VERBOSE_NVRAM);
1982
1983         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1984
1985         /* Disable both bits, even after read. */
1986         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
1987             ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1988
1989         DBEXIT(BCE_VERBOSE_NVRAM);
1990 }
1991
1992
1993 #ifdef BCE_NVRAM_WRITE_SUPPORT
1994 /****************************************************************************/
1995 /* Erase NVRAM page before writing.                                         */
1996 /*                                                                          */
1997 /* Non-buffered flash parts require that a page be erased before it is      */
1998 /* written.                                                                 */
1999 /*                                                                          */
2000 /* Returns:                                                                 */
2001 /*   0 on success, positive value on failure.                               */
2002 /****************************************************************************/
2003 static int
2004 bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
2005 {
2006         u32 cmd;
2007         int j, rc = 0;
2008
2009         DBENTER(BCE_VERBOSE_NVRAM);
2010
2011         /* Buffered flash doesn't require an erase. */
2012         if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
2013                 goto bce_nvram_erase_page_exit;
2014
2015         /* Build an erase command. */
2016         cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
2017             BCE_NVM_COMMAND_DOIT;
2018
2019         /*
2020          * Clear the DONE bit separately, set the NVRAM adress to erase,
2021          * and issue the erase command.
2022          */
2023         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2024         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2025         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2026
2027         /* Wait for completion. */
2028         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2029                 u32 val;
2030
2031                 DELAY(5);
2032
2033                 val = REG_RD(sc, BCE_NVM_COMMAND);
2034                 if (val & BCE_NVM_COMMAND_DONE)
2035                         break;
2036         }
2037
2038         if (j >= NVRAM_TIMEOUT_COUNT) {
2039                 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
2040                 rc = EBUSY;
2041         }
2042
2043 bce_nvram_erase_page_exit:
2044         DBEXIT(BCE_VERBOSE_NVRAM);
2045         return (rc);
2046 }
2047 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2048
2049
2050 /****************************************************************************/
2051 /* Read a dword (32 bits) from NVRAM.                                       */
2052 /*                                                                          */
2053 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
2054 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
2055 /*                                                                          */
2056 /* Returns:                                                                 */
2057 /*   0 on success and the 32 bit value read, positive value on failure.     */
2058 /****************************************************************************/
2059 static int
2060 bce_nvram_read_dword(struct bce_softc *sc,
2061     u32 offset, u8 *ret_val, u32 cmd_flags)
2062 {
2063         u32 cmd;
2064         int i, rc = 0;
2065
2066         DBENTER(BCE_EXTREME_NVRAM);
2067
2068         /* Build the command word. */
2069         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
2070
2071         /* Calculate the offset for buffered flash if translation is used. */
2072         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2073                 offset = ((offset / sc->bce_flash_info->page_size) <<
2074                     sc->bce_flash_info->page_bits) +
2075                     (offset % sc->bce_flash_info->page_size);
2076         }
2077
2078         /*
2079          * Clear the DONE bit separately, set the address to read,
2080          * and issue the read.
2081          */
2082         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2083         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2084         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2085
2086         /* Wait for completion. */
2087         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
2088                 u32 val;
2089
2090                 DELAY(5);
2091
2092                 val = REG_RD(sc, BCE_NVM_COMMAND);
2093                 if (val & BCE_NVM_COMMAND_DONE) {
2094                         val = REG_RD(sc, BCE_NVM_READ);
2095
2096                         val = bce_be32toh(val);
2097                         memcpy(ret_val, &val, 4);
2098                         break;
2099                 }
2100         }
2101
2102         /* Check for errors. */
2103         if (i >= NVRAM_TIMEOUT_COUNT) {
2104                 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at "
2105                     "offset 0x%08X!\n", __FILE__, __LINE__, offset);
2106                 rc = EBUSY;
2107         }
2108
2109         DBEXIT(BCE_EXTREME_NVRAM);
2110         return(rc);
2111 }
2112
2113
2114 #ifdef BCE_NVRAM_WRITE_SUPPORT
2115 /****************************************************************************/
2116 /* Write a dword (32 bits) to NVRAM.                                        */
2117 /*                                                                          */
2118 /* Write a 32 bit word to NVRAM.  The caller is assumed to have already     */
2119 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and    */
2120 /* enabled NVRAM write access.                                              */
2121 /*                                                                          */
2122 /* Returns:                                                                 */
2123 /*   0 on success, positive value on failure.                               */
2124 /****************************************************************************/
2125 static int
2126 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
2127         u32 cmd_flags)
2128 {
2129         u32 cmd, val32;
2130         int j, rc = 0;
2131
2132         DBENTER(BCE_VERBOSE_NVRAM);
2133
2134         /* Build the command word. */
2135         cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
2136
2137         /* Calculate the offset for buffered flash if translation is used. */
2138         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2139                 offset = ((offset / sc->bce_flash_info->page_size) <<
2140                     sc->bce_flash_info->page_bits) +
2141                     (offset % sc->bce_flash_info->page_size);
2142         }
2143
2144         /*
2145          * Clear the DONE bit separately, convert NVRAM data to big-endian,
2146          * set the NVRAM address to write, and issue the write command
2147          */
2148         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2149         memcpy(&val32, val, 4);
2150         val32 = htobe32(val32);
2151         REG_WR(sc, BCE_NVM_WRITE, val32);
2152         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2153         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2154
2155         /* Wait for completion. */
2156         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2157                 DELAY(5);
2158
2159                 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
2160                         break;
2161         }
2162         if (j >= NVRAM_TIMEOUT_COUNT) {
2163                 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at "
2164                     "offset 0x%08X\n", __FILE__, __LINE__, offset);
2165                 rc = EBUSY;
2166         }
2167
2168         DBEXIT(BCE_VERBOSE_NVRAM);
2169         return (rc);
2170 }
2171 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2172
2173
2174 /****************************************************************************/
2175 /* Initialize NVRAM access.                                                 */
2176 /*                                                                          */
2177 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
2178 /* access that device.                                                      */
2179 /*                                                                          */
2180 /* Returns:                                                                 */
2181 /*   0 on success, positive value on failure.                               */
2182 /****************************************************************************/
2183 static int
2184 bce_init_nvram(struct bce_softc *sc)
2185 {
2186         u32 val;
2187         int j, entry_count, rc = 0;
2188         struct flash_spec *flash;
2189
2190         DBENTER(BCE_VERBOSE_NVRAM);
2191
2192         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
2193                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
2194                 sc->bce_flash_info = &flash_5709;
2195                 goto bce_init_nvram_get_flash_size;
2196         }
2197
2198         /* Determine the selected interface. */
2199         val = REG_RD(sc, BCE_NVM_CFG1);
2200
2201         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2202
2203         /*
2204          * Flash reconfiguration is required to support additional
2205          * NVRAM devices not directly supported in hardware.
2206          * Check if the flash interface was reconfigured
2207          * by the bootcode.
2208          */
2209
2210         if (val & 0x40000000) {
2211                 /* Flash interface reconfigured by bootcode. */
2212
2213                 DBPRINT(sc,BCE_INFO_LOAD,
2214                         "bce_init_nvram(): Flash WAS reconfigured.\n");
2215
2216                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2217                      j++, flash++) {
2218                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
2219                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2220                                 sc->bce_flash_info = flash;
2221                                 break;
2222                         }
2223                 }
2224         } else {
2225                 /* Flash interface not yet reconfigured. */
2226                 u32 mask;
2227
2228                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n",
2229                         __FUNCTION__);
2230
2231                 if (val & (1 << 23))
2232                         mask = FLASH_BACKUP_STRAP_MASK;
2233                 else
2234                         mask = FLASH_STRAP_MASK;
2235
2236                 /* Look for the matching NVRAM device configuration data. */
2237                 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {
2238
2239                         /* Check if the device matches any of the known devices. */
2240                         if ((val & mask) == (flash->strapping & mask)) {
2241                                 /* Found a device match. */
2242                                 sc->bce_flash_info = flash;
2243
2244                                 /* Request access to the flash interface. */
2245                                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2246                                         return rc;
2247
2248                                 /* Reconfigure the flash interface. */
2249                                 bce_enable_nvram_access(sc);
2250                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2251                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2252                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2253                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
2254                                 bce_disable_nvram_access(sc);
2255                                 bce_release_nvram_lock(sc);
2256
2257                                 break;
2258                         }
2259                 }
2260         }
2261
2262         /* Check if a matching device was found. */
2263         if (j == entry_count) {
2264                 sc->bce_flash_info = NULL;
2265                 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
2266                     __FILE__, __LINE__);
2267                 DBEXIT(BCE_VERBOSE_NVRAM);
2268                 return (ENODEV);
2269         }
2270
2271 bce_init_nvram_get_flash_size:
2272         /* Write the flash config data to the shared memory interface. */
2273         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2);
2274         val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2275         if (val)
2276                 sc->bce_flash_size = val;
2277         else
2278                 sc->bce_flash_size = sc->bce_flash_info->total_size;
2279
2280         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2281             __FUNCTION__, sc->bce_flash_info->name,
2282             sc->bce_flash_info->total_size);
2283
2284         DBEXIT(BCE_VERBOSE_NVRAM);
2285         return rc;
2286 }
2287
2288
2289 /****************************************************************************/
2290 /* Read an arbitrary range of data from NVRAM.                              */
2291 /*                                                                          */
2292 /* Prepares the NVRAM interface for access and reads the requested data     */
2293 /* into the supplied buffer.                                                */
2294 /*                                                                          */
2295 /* Returns:                                                                 */
2296 /*   0 on success and the data read, positive value on failure.             */
2297 /****************************************************************************/
2298 static int
2299 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
2300         int buf_size)
2301 {
2302         int rc = 0;
2303         u32 cmd_flags, offset32, len32, extra;
2304
2305         DBENTER(BCE_VERBOSE_NVRAM);
2306
2307         if (buf_size == 0)
2308                 goto bce_nvram_read_exit;
2309
2310         /* Request access to the flash interface. */
2311         if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2312                 goto bce_nvram_read_exit;
2313
2314         /* Enable access to flash interface */
2315         bce_enable_nvram_access(sc);
2316
2317         len32 = buf_size;
2318         offset32 = offset;
2319         extra = 0;
2320
2321         cmd_flags = 0;
2322
2323         if (offset32 & 3) {
2324                 u8 buf[4];
2325                 u32 pre_len;
2326
2327                 offset32 &= ~3;
2328                 pre_len = 4 - (offset & 3);
2329
2330                 if (pre_len >= len32) {
2331                         pre_len = len32;
2332                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
2333                 }
2334                 else {
2335                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2336                 }
2337
2338                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2339
2340                 if (rc)
2341                         return rc;
2342
2343                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2344
2345                 offset32 += 4;
2346                 ret_buf += pre_len;
2347                 len32 -= pre_len;
2348         }
2349
2350         if (len32 & 3) {
2351                 extra = 4 - (len32 & 3);
2352                 len32 = (len32 + 4) & ~3;
2353         }
2354
2355         if (len32 == 4) {
2356                 u8 buf[4];
2357
2358                 if (cmd_flags)
2359                         cmd_flags = BCE_NVM_COMMAND_LAST;
2360                 else
2361                         cmd_flags = BCE_NVM_COMMAND_FIRST |
2362                                     BCE_NVM_COMMAND_LAST;
2363
2364                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2365
2366                 memcpy(ret_buf, buf, 4 - extra);
2367         }
2368         else if (len32 > 0) {
2369                 u8 buf[4];
2370
2371                 /* Read the first word. */
2372                 if (cmd_flags)
2373                         cmd_flags = 0;
2374                 else
2375                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2376
2377                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
2378
2379                 /* Advance to the next dword. */
2380                 offset32 += 4;
2381                 ret_buf += 4;
2382                 len32 -= 4;
2383
2384                 while (len32 > 4 && rc == 0) {
2385                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
2386
2387                         /* Advance to the next dword. */
2388                         offset32 += 4;
2389                         ret_buf += 4;
2390                         len32 -= 4;
2391                 }
2392
2393                 if (rc)
2394                         goto bce_nvram_read_locked_exit;
2395
2396                 cmd_flags = BCE_NVM_COMMAND_LAST;
2397                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2398
2399                 memcpy(ret_buf, buf, 4 - extra);
2400         }
2401
2402 bce_nvram_read_locked_exit:
2403         /* Disable access to flash interface and release the lock. */
2404         bce_disable_nvram_access(sc);
2405         bce_release_nvram_lock(sc);
2406
2407 bce_nvram_read_exit:
2408         DBEXIT(BCE_VERBOSE_NVRAM);
2409         return rc;
2410 }
2411
2412
2413 #ifdef BCE_NVRAM_WRITE_SUPPORT
2414 /****************************************************************************/
2415 /* Write an arbitrary range of data from NVRAM.                             */
2416 /*                                                                          */
2417 /* Prepares the NVRAM interface for write access and writes the requested   */
2418 /* data from the supplied buffer.  The caller is responsible for            */
2419 /* calculating any appropriate CRCs.                                        */
2420 /*                                                                          */
2421 /* Returns:                                                                 */
2422 /*   0 on success, positive value on failure.                               */
2423 /****************************************************************************/
2424 static int
2425 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
2426         int buf_size)
2427 {
2428         u32 written, offset32, len32;
2429         u8 *buf, start[4], end[4];
2430         int rc = 0;
2431         int align_start, align_end;
2432
2433         DBENTER(BCE_VERBOSE_NVRAM);
2434
2435         buf = data_buf;
2436         offset32 = offset;
2437         len32 = buf_size;
2438         align_start = align_end = 0;
2439
2440         if ((align_start = (offset32 & 3))) {
2441                 offset32 &= ~3;
2442                 len32 += align_start;
2443                 if ((rc = bce_nvram_read(sc, offset32, start, 4)))
2444                         goto bce_nvram_write_exit;
2445         }
2446
2447         if (len32 & 3) {
2448                 if ((len32 > 4) || !align_start) {
2449                         align_end = 4 - (len32 & 3);
2450                         len32 += align_end;
2451                         if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2452                                 end, 4))) {
2453                                 goto bce_nvram_write_exit;
2454                         }
2455                 }
2456         }
2457
2458         if (align_start || align_end) {
2459                 buf = malloc(len32, M_DEVBUF, M_NOWAIT);
2460                 if (buf == 0) {
2461                         rc = ENOMEM;
2462                         goto bce_nvram_write_exit;
2463                 }
2464
2465                 if (align_start) {
2466                         memcpy(buf, start, 4);
2467                 }
2468
2469                 if (align_end) {
2470                         memcpy(buf + len32 - 4, end, 4);
2471                 }
2472                 memcpy(buf + align_start, data_buf, buf_size);
2473         }
2474
2475         written = 0;
2476         while ((written < len32) && (rc == 0)) {
2477                 u32 page_start, page_end, data_start, data_end;
2478                 u32 addr, cmd_flags;
2479                 int i;
2480                 u8 flash_buffer[264];
2481
2482             /* Find the page_start addr */
2483                 page_start = offset32 + written;
2484                 page_start -= (page_start % sc->bce_flash_info->page_size);
2485                 /* Find the page_end addr */
2486                 page_end = page_start + sc->bce_flash_info->page_size;
2487                 /* Find the data_start addr */
2488                 data_start = (written == 0) ? offset32 : page_start;
2489                 /* Find the data_end addr */
2490                 data_end = (page_end > offset32 + len32) ?
2491                         (offset32 + len32) : page_end;
2492
2493                 /* Request access to the flash interface. */
2494                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2495                         goto bce_nvram_write_exit;
2496
2497                 /* Enable access to flash interface */
2498                 bce_enable_nvram_access(sc);
2499
2500                 cmd_flags = BCE_NVM_COMMAND_FIRST;
2501                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2502                         int j;
2503
2504                         /* Read the whole page into the buffer
2505                          * (non-buffer flash only) */
2506                         for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2507                                 if (j == (sc->bce_flash_info->page_size - 4)) {
2508                                         cmd_flags |= BCE_NVM_COMMAND_LAST;
2509                                 }
2510                                 rc = bce_nvram_read_dword(sc,
2511                                         page_start + j,
2512                                         &flash_buffer[j],
2513                                         cmd_flags);
2514
2515                                 if (rc)
2516                                         goto bce_nvram_write_locked_exit;
2517
2518                                 cmd_flags = 0;
2519                         }
2520                 }
2521
2522                 /* Enable writes to flash interface (unlock write-protect) */
2523                 if ((rc = bce_enable_nvram_write(sc)) != 0)
2524                         goto bce_nvram_write_locked_exit;
2525
2526                 /* Erase the page */
2527                 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2528                         goto bce_nvram_write_locked_exit;
2529
2530                 /* Re-enable the write again for the actual write */
2531                 bce_enable_nvram_write(sc);
2532
2533                 /* Loop to write back the buffer data from page_start to
2534                  * data_start */
2535                 i = 0;
2536                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2537                         for (addr = page_start; addr < data_start;
2538                                 addr += 4, i += 4) {
2539
2540                                 rc = bce_nvram_write_dword(sc, addr,
2541                                         &flash_buffer[i], cmd_flags);
2542
2543                                 if (rc != 0)
2544                                         goto bce_nvram_write_locked_exit;
2545
2546                                 cmd_flags = 0;
2547                         }
2548                 }
2549
2550                 /* Loop to write the new data from data_start to data_end */
2551                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2552                         if ((addr == page_end - 4) ||
2553                                 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2554                                 (addr == data_end - 4))) {
2555
2556                                 cmd_flags |= BCE_NVM_COMMAND_LAST;
2557                         }
2558                         rc = bce_nvram_write_dword(sc, addr, buf,
2559                                 cmd_flags);
2560
2561                         if (rc != 0)
2562                                 goto bce_nvram_write_locked_exit;
2563
2564                         cmd_flags = 0;
2565                         buf += 4;
2566                 }
2567
2568                 /* Loop to write back the buffer data from data_end
2569                  * to page_end */
2570                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2571                         for (addr = data_end; addr < page_end;
2572                                 addr += 4, i += 4) {
2573
2574                                 if (addr == page_end-4) {
2575                                         cmd_flags = BCE_NVM_COMMAND_LAST;
2576                                 }
2577                                 rc = bce_nvram_write_dword(sc, addr,
2578                                         &flash_buffer[i], cmd_flags);
2579
2580                                 if (rc != 0)
2581                                         goto bce_nvram_write_locked_exit;
2582
2583                                 cmd_flags = 0;
2584                         }
2585                 }
2586
2587                 /* Disable writes to flash interface (lock write-protect) */
2588                 bce_disable_nvram_write(sc);
2589
2590                 /* Disable access to flash interface */
2591                 bce_disable_nvram_access(sc);
2592                 bce_release_nvram_lock(sc);
2593
2594                 /* Increment written */
2595                 written += data_end - data_start;
2596         }
2597
2598         goto bce_nvram_write_exit;
2599
2600 bce_nvram_write_locked_exit:
2601                 bce_disable_nvram_write(sc);
2602                 bce_disable_nvram_access(sc);
2603                 bce_release_nvram_lock(sc);
2604
2605 bce_nvram_write_exit:
2606         if (align_start || align_end)
2607                 free(buf, M_DEVBUF);
2608
2609         DBEXIT(BCE_VERBOSE_NVRAM);
2610         return (rc);
2611 }
2612 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2613
2614
2615 /****************************************************************************/
2616 /* Verifies that NVRAM is accessible and contains valid data.               */
2617 /*                                                                          */
2618 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
2619 /* correct.                                                                 */
2620 /*                                                                          */
2621 /* Returns:                                                                 */
2622 /*   0 on success, positive value on failure.                               */
2623 /****************************************************************************/
2624 static int
2625 bce_nvram_test(struct bce_softc *sc)
2626 {
2627         u32 buf[BCE_NVRAM_SIZE / 4];
2628         u8 *data = (u8 *) buf;
2629         int rc = 0;
2630         u32 magic, csum;
2631
2632         DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2633
2634         /*
2635          * Check that the device NVRAM is valid by reading
2636          * the magic value at offset 0.
2637          */
2638         if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2639                 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n",
2640                     __FILE__, __LINE__);
2641                 goto bce_nvram_test_exit;
2642         }
2643
2644         /*
2645          * Verify that offset 0 of the NVRAM contains
2646          * a valid magic number.
2647          */
2648     magic = bce_be32toh(buf[0]);
2649         if (magic != BCE_NVRAM_MAGIC) {
2650                 rc = ENODEV;
2651                 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! "
2652                     "Expected: 0x%08X, Found: 0x%08X\n",
2653                     __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
2654                 goto bce_nvram_test_exit;
2655         }
2656
2657         /*
2658          * Verify that the device NVRAM includes valid
2659          * configuration data.
2660          */
2661         if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
2662                 BCE_PRINTF("%s(%d): Unable to read manufacturing "
2663                     "Information from  NVRAM!\n", __FILE__, __LINE__);
2664                 goto bce_nvram_test_exit;
2665         }
2666
2667         csum = ether_crc32_le(data, 0x100);
2668         if (csum != BCE_CRC32_RESIDUAL) {
2669                 rc = ENODEV;
2670                 BCE_PRINTF("%s(%d): Invalid manufacturing information "
2671                     "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
2672                     __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
2673                 goto bce_nvram_test_exit;
2674         }
2675
2676         csum = ether_crc32_le(data + 0x100, 0x100);
2677         if (csum != BCE_CRC32_RESIDUAL) {
2678                 rc = ENODEV;
2679                 BCE_PRINTF("%s(%d): Invalid feature configuration "
2680                     "information NVRAM CRC! Expected: 0x%08X, "
2681                     "Found: 08%08X\n", __FILE__, __LINE__,
2682                     BCE_CRC32_RESIDUAL, csum);
2683         }
2684
2685 bce_nvram_test_exit:
2686         DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2687         return rc;
2688 }
2689
2690
2691 /****************************************************************************/
2692 /* Identifies the current media type of the controller and sets the PHY     */
2693 /* address.                                                                 */
2694 /*                                                                          */
2695 /* Returns:                                                                 */
2696 /*   Nothing.                                                               */
2697 /****************************************************************************/
2698 static void
2699 bce_get_media(struct bce_softc *sc)
2700 {
2701         u32 val;
2702
2703         DBENTER(BCE_VERBOSE_PHY);
2704
2705         /* Assume PHY address for copper controllers. */
2706         sc->bce_phy_addr = 1;
2707
2708         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2709                 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
2710                 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
2711                 u32 strap;
2712
2713                 /*
2714                  * The BCM5709S is software configurable
2715                  * for Copper or SerDes operation.
2716                  */
2717                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
2718                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
2719                             "for copper.\n");
2720                         goto bce_get_media_exit;
2721                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
2722                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
2723                             "for dual media.\n");
2724                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2725                         goto bce_get_media_exit;
2726                 }
2727
2728                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
2729                         strap = (val &
2730                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
2731                 else
2732                         strap = (val &
2733                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
2734
2735                 if (pci_get_function(sc->bce_dev) == 0) {
2736                         switch (strap) {
2737                         case 0x4:
2738                         case 0x5:
2739                         case 0x6:
2740                                 DBPRINT(sc, BCE_INFO_LOAD,
2741                                     "BCM5709 s/w configured for SerDes.\n");
2742                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2743                                 break;
2744                         default:
2745                                 DBPRINT(sc, BCE_INFO_LOAD,
2746                                     "BCM5709 s/w configured for Copper.\n");
2747                                 break;
2748                         }
2749                 } else {
2750                         switch (strap) {
2751                         case 0x1:
2752                         case 0x2:
2753                         case 0x4:
2754                                 DBPRINT(sc, BCE_INFO_LOAD,
2755                                     "BCM5709 s/w configured for SerDes.\n");
2756                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2757                                 break;
2758                         default:
2759                                 DBPRINT(sc, BCE_INFO_LOAD,
2760                                     "BCM5709 s/w configured for Copper.\n");
2761                                 break;
2762                         }
2763                 }
2764
2765         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
2766                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2767
2768         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2769
2770                 sc->bce_flags |= BCE_NO_WOL_FLAG;
2771
2772                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
2773                         sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG;
2774
2775                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2776                         /* 5708S/09S/16S use a separate PHY for SerDes. */
2777                         sc->bce_phy_addr = 2;
2778
2779                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2780                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
2781                                 sc->bce_phy_flags |=
2782                                     BCE_PHY_2_5G_CAPABLE_FLAG;
2783                                 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb "
2784                                     "capable adapter\n");
2785                         }
2786                 }
2787         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2788             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708))
2789                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2790
2791 bce_get_media_exit:
2792         DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
2793                 "Using PHY address %d.\n", sc->bce_phy_addr);
2794
2795         DBEXIT(BCE_VERBOSE_PHY);
2796 }
2797
2798
2799 /****************************************************************************/
2800 /* Performs PHY initialization required before MII drivers access the       */
2801 /* device.                                                                  */
2802 /*                                                                          */
2803 /* Returns:                                                                 */
2804 /*   Nothing.                                                               */
2805 /****************************************************************************/
2806 static void
2807 bce_init_media(struct bce_softc *sc)
2808 {
2809         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
2810                 /*
2811                  * Configure 5709S/5716S PHYs to use traditional IEEE
2812                  * Clause 22 method. Otherwise we have no way to attach
2813                  * the PHY in mii(4) layer. PHY specific configuration
2814                  * is done in mii layer.
2815                  */
2816
2817                 /* Select auto-negotiation MMD of the PHY. */
2818                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
2819                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT);
2820                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
2821                     BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD);
2822
2823                 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */
2824                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
2825                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
2826         }
2827 }
2828
2829
2830 /****************************************************************************/
2831 /* Free any DMA memory owned by the driver.                                 */
2832 /*                                                                          */
2833 /* Scans through each data structre that requires DMA memory and frees      */
2834 /* the memory if allocated.                                                 */
2835 /*                                                                          */
2836 /* Returns:                                                                 */
2837 /*   Nothing.                                                               */
2838 /****************************************************************************/
2839 static void
2840 bce_dma_free(struct bce_softc *sc)
2841 {
2842         int i;
2843
2844         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
2845
2846         /* Free, unmap, and destroy the status block. */
2847         if (sc->status_block != NULL) {
2848                 bus_dmamem_free(
2849                    sc->status_tag,
2850                     sc->status_block,
2851                     sc->status_map);
2852                 sc->status_block = NULL;
2853         }
2854
2855         if (sc->status_map != NULL) {
2856                 bus_dmamap_unload(
2857                     sc->status_tag,
2858                     sc->status_map);
2859                 bus_dmamap_destroy(sc->status_tag,
2860                     sc->status_map);
2861                 sc->status_map = NULL;
2862         }
2863
2864         if (sc->status_tag != NULL) {
2865                 bus_dma_tag_destroy(sc->status_tag);
2866                 sc->status_tag = NULL;
2867         }
2868
2869
2870         /* Free, unmap, and destroy the statistics block. */
2871         if (sc->stats_block != NULL) {
2872                 bus_dmamem_free(
2873                     sc->stats_tag,
2874                     sc->stats_block,
2875                     sc->stats_map);
2876                 sc->stats_block = NULL;
2877         }
2878
2879         if (sc->stats_map != NULL) {
2880                 bus_dmamap_unload(
2881                     sc->stats_tag,
2882                     sc->stats_map);
2883                 bus_dmamap_destroy(sc->stats_tag,
2884                     sc->stats_map);
2885                 sc->stats_map = NULL;
2886         }
2887
2888         if (sc->stats_tag != NULL) {
2889                 bus_dma_tag_destroy(sc->stats_tag);
2890                 sc->stats_tag = NULL;
2891         }
2892
2893
2894         /* Free, unmap and destroy all context memory pages. */
2895         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
2896                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
2897                 for (i = 0; i < sc->ctx_pages; i++ ) {
2898                         if (sc->ctx_block[i] != NULL) {
2899                                 bus_dmamem_free(
2900                                     sc->ctx_tag,
2901                                     sc->ctx_block[i],
2902                                     sc->ctx_map[i]);
2903                                 sc->ctx_block[i] = NULL;
2904                         }
2905
2906                         if (sc->ctx_map[i] != NULL) {
2907                                 bus_dmamap_unload(
2908                                     sc->ctx_tag,
2909                                     sc->ctx_map[i]);
2910                                 bus_dmamap_destroy(
2911                                     sc->ctx_tag,
2912                                     sc->ctx_map[i]);
2913                                 sc->ctx_map[i] = NULL;
2914                         }
2915                 }
2916
2917                 /* Destroy the context memory tag. */
2918                 if (sc->ctx_tag != NULL) {
2919                         bus_dma_tag_destroy(sc->ctx_tag);
2920                         sc->ctx_tag = NULL;
2921                 }
2922         }
2923
2924
2925         /* Free, unmap and destroy all TX buffer descriptor chain pages. */
2926         for (i = 0; i < TX_PAGES; i++ ) {
2927                 if (sc->tx_bd_chain[i] != NULL) {
2928                         bus_dmamem_free(
2929                             sc->tx_bd_chain_tag,
2930                             sc->tx_bd_chain[i],
2931                             sc->tx_bd_chain_map[i]);
2932                         sc->tx_bd_chain[i] = NULL;
2933                 }
2934
2935                 if (sc->tx_bd_chain_map[i] != NULL) {
2936                         bus_dmamap_unload(
2937                             sc->tx_bd_chain_tag,
2938                             sc->tx_bd_chain_map[i]);
2939                         bus_dmamap_destroy(
2940                             sc->tx_bd_chain_tag,
2941                             sc->tx_bd_chain_map[i]);
2942                         sc->tx_bd_chain_map[i] = NULL;
2943                 }
2944         }
2945
2946         /* Destroy the TX buffer descriptor tag. */
2947         if (sc->tx_bd_chain_tag != NULL) {
2948                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2949                 sc->tx_bd_chain_tag = NULL;
2950         }
2951
2952
2953         /* Free, unmap and destroy all RX buffer descriptor chain pages. */
2954         for (i = 0; i < RX_PAGES; i++ ) {
2955                 if (sc->rx_bd_chain[i] != NULL) {
2956                         bus_dmamem_free(
2957                             sc->rx_bd_chain_tag,
2958                             sc->rx_bd_chain[i],
2959                             sc->rx_bd_chain_map[i]);
2960                         sc->rx_bd_chain[i] = NULL;
2961                 }
2962
2963                 if (sc->rx_bd_chain_map[i] != NULL) {
2964                         bus_dmamap_unload(
2965                             sc->rx_bd_chain_tag,
2966                             sc->rx_bd_chain_map[i]);
2967                         bus_dmamap_destroy(
2968                             sc->rx_bd_chain_tag,
2969                             sc->rx_bd_chain_map[i]);
2970                         sc->rx_bd_chain_map[i] = NULL;
2971                 }
2972         }
2973
2974         /* Destroy the RX buffer descriptor tag. */
2975         if (sc->rx_bd_chain_tag != NULL) {
2976                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2977                 sc->rx_bd_chain_tag = NULL;
2978         }
2979
2980
2981 #ifdef BCE_JUMBO_HDRSPLIT
2982         /* Free, unmap and destroy all page buffer descriptor chain pages. */
2983         for (i = 0; i < PG_PAGES; i++ ) {
2984                 if (sc->pg_bd_chain[i] != NULL) {
2985                         bus_dmamem_free(
2986                             sc->pg_bd_chain_tag,
2987                             sc->pg_bd_chain[i],
2988                             sc->pg_bd_chain_map[i]);
2989                         sc->pg_bd_chain[i] = NULL;
2990                 }
2991
2992                 if (sc->pg_bd_chain_map[i] != NULL) {
2993                         bus_dmamap_unload(
2994                             sc->pg_bd_chain_tag,
2995                             sc->pg_bd_chain_map[i]);
2996                         bus_dmamap_destroy(
2997                             sc->pg_bd_chain_tag,
2998                             sc->pg_bd_chain_map[i]);
2999                         sc->pg_bd_chain_map[i] = NULL;
3000                 }
3001         }
3002
3003         /* Destroy the page buffer descriptor tag. */
3004         if (sc->pg_bd_chain_tag != NULL) {
3005                 bus_dma_tag_destroy(sc->pg_bd_chain_tag);
3006                 sc->pg_bd_chain_tag = NULL;
3007         }
3008 #endif
3009
3010
3011         /* Unload and destroy the TX mbuf maps. */
3012         for (i = 0; i < TOTAL_TX_BD; i++) {
3013                 if (sc->tx_mbuf_map[i] != NULL) {
3014                         bus_dmamap_unload(sc->tx_mbuf_tag,
3015                             sc->tx_mbuf_map[i]);
3016                         bus_dmamap_destroy(sc->tx_mbuf_tag,
3017                             sc->tx_mbuf_map[i]);
3018                         sc->tx_mbuf_map[i] = NULL;
3019                 }
3020         }
3021
3022         /* Destroy the TX mbuf tag. */
3023         if (sc->tx_mbuf_tag != NULL) {
3024                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
3025                 sc->tx_mbuf_tag = NULL;
3026         }
3027
3028         /* Unload and destroy the RX mbuf maps. */
3029         for (i = 0; i < TOTAL_RX_BD; i++) {
3030                 if (sc->rx_mbuf_map[i] != NULL) {
3031                         bus_dmamap_unload(sc->rx_mbuf_tag,
3032                             sc->rx_mbuf_map[i]);
3033                         bus_dmamap_destroy(sc->rx_mbuf_tag,
3034                             sc->rx_mbuf_map[i]);
3035                         sc->rx_mbuf_map[i] = NULL;
3036                 }
3037         }
3038
3039         /* Destroy the RX mbuf tag. */
3040         if (sc->rx_mbuf_tag != NULL) {
3041                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
3042                 sc->rx_mbuf_tag = NULL;
3043         }
3044
3045 #ifdef BCE_JUMBO_HDRSPLIT
3046         /* Unload and destroy the page mbuf maps. */
3047         for (i = 0; i < TOTAL_PG_BD; i++) {
3048                 if (sc->pg_mbuf_map[i] != NULL) {
3049                         bus_dmamap_unload(sc->pg_mbuf_tag,
3050                             sc->pg_mbuf_map[i]);
3051                         bus_dmamap_destroy(sc->pg_mbuf_tag,
3052                             sc->pg_mbuf_map[i]);
3053                         sc->pg_mbuf_map[i] = NULL;
3054                 }
3055         }
3056
3057         /* Destroy the page mbuf tag. */
3058         if (sc->pg_mbuf_tag != NULL) {
3059                 bus_dma_tag_destroy(sc->pg_mbuf_tag);
3060                 sc->pg_mbuf_tag = NULL;
3061         }
3062 #endif
3063
3064         /* Destroy the parent tag */
3065         if (sc->parent_tag != NULL) {
3066                 bus_dma_tag_destroy(sc->parent_tag);
3067                 sc->parent_tag = NULL;
3068         }
3069
3070         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3071 }
3072
3073
3074 /****************************************************************************/
3075 /* Get DMA memory from the OS.                                              */
3076 /*                                                                          */
3077 /* Validates that the OS has provided DMA buffers in response to a          */
3078 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
3079 /* When the callback is used the OS will return 0 for the mapping function  */
3080 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
3081 /* failures back to the caller.                                             */
3082 /*                                                                          */
3083 /* Returns:                                                                 */
3084 /*   Nothing.                                                               */
3085 /****************************************************************************/
3086 static void
3087 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3088 {
3089         bus_addr_t *busaddr = arg;
3090
3091         /* Simulate a mapping failure. */
3092         DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control),
3093             error = ENOMEM);
3094
3095         /* ToDo: How to increment debug sim_count variable here? */
3096
3097         /* Check for an error and signal the caller that an error occurred. */
3098         if (error) {
3099                 *busaddr = 0;
3100         } else {
3101                 *busaddr = segs->ds_addr;
3102         }
3103
3104         return;
3105 }
3106
3107
3108 /****************************************************************************/
3109 /* Allocate any DMA memory needed by the driver.                            */
3110 /*                                                                          */
3111 /* Allocates DMA memory needed for the various global structures needed by  */
3112 /* hardware.                                                                */
3113 /*                                                                          */
3114 /* Memory alignment requirements:                                           */
3115 /* +-----------------+----------+----------+----------+----------+          */
3116 /* |                 |   5706   |   5708   |   5709   |   5716   |          */
3117 /* +-----------------+----------+----------+----------+----------+          */
3118 /* |Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3119 /* |Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3120 /* |RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |          */
3121 /* |PG Buffers       |   none   |   none   |   none   |   none   |          */
3122 /* |TX Buffers       |   none   |   none   |   none   |   none   |          */
3123 /* |Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |          */
3124 /* |Context Memory   |          |          |          |          |          */
3125 /* +-----------------+----------+----------+----------+----------+          */
3126 /*                                                                          */
3127 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
3128 /*                                                                          */
3129 /* Returns:                                                                 */
3130 /*   0 for success, positive value for failure.                             */
3131 /****************************************************************************/
3132 static int
3133 bce_dma_alloc(device_t dev)
3134 {
3135         struct bce_softc *sc;
3136         int i, error, rc = 0;
3137         bus_size_t max_size, max_seg_size;
3138         int max_segments;
3139
3140         sc = device_get_softc(dev);
3141
3142         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3143
3144         /*
3145          * Allocate the parent bus DMA tag appropriate for PCI.
3146          */
3147         if (bus_dma_tag_create(NULL, 1, BCE_DMA_BOUNDARY,
3148             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3149             MAXBSIZE, BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE_32BIT,
3150             0, NULL, NULL, &sc->parent_tag)) {
3151                 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
3152                     __FILE__, __LINE__);
3153                 rc = ENOMEM;
3154                 goto bce_dma_alloc_exit;
3155         }
3156
3157         /*
3158          * Create a DMA tag for the status block, allocate and clear the
3159          * memory, map the memory into DMA space, and fetch the physical
3160          * address of the block.
3161          */
3162         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3163             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3164             NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
3165             0, NULL, NULL, &sc->status_tag)) {
3166                 BCE_PRINTF("%s(%d): Could not allocate status block "
3167                     "DMA tag!\n", __FILE__, __LINE__);
3168                 rc = ENOMEM;
3169                 goto bce_dma_alloc_exit;
3170         }
3171
3172         if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
3173             BUS_DMA_NOWAIT, &sc->status_map)) {
3174                 BCE_PRINTF("%s(%d): Could not allocate status block "
3175                     "DMA memory!\n", __FILE__, __LINE__);
3176                 rc = ENOMEM;
3177                 goto bce_dma_alloc_exit;
3178         }
3179
3180         bzero((char *)sc->status_block, BCE_STATUS_BLK_SZ);
3181
3182         error = bus_dmamap_load(sc->status_tag, sc->status_map,
3183             sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr,
3184             &sc->status_block_paddr, BUS_DMA_NOWAIT);
3185
3186         if (error) {
3187                 BCE_PRINTF("%s(%d): Could not map status block "
3188                     "DMA memory!\n", __FILE__, __LINE__);
3189                 rc = ENOMEM;
3190                 goto bce_dma_alloc_exit;
3191         }
3192
3193         DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n",
3194             __FUNCTION__, (uintmax_t) sc->status_block_paddr);
3195
3196         /*
3197          * Create a DMA tag for the statistics block, allocate and clear the
3198          * memory, map the memory into DMA space, and fetch the physical
3199          * address of the block.
3200          */
3201         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3202             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3203             NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
3204             0, NULL, NULL, &sc->stats_tag)) {
3205                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3206                     "DMA tag!\n", __FILE__, __LINE__);
3207                 rc = ENOMEM;
3208                 goto bce_dma_alloc_exit;
3209         }
3210
3211         if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
3212             BUS_DMA_NOWAIT,     &sc->stats_map)) {
3213                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3214                     "DMA memory!\n", __FILE__, __LINE__);
3215                 rc = ENOMEM;
3216                 goto bce_dma_alloc_exit;
3217         }
3218
3219         bzero((char *)sc->stats_block, BCE_STATS_BLK_SZ);
3220
3221         error = bus_dmamap_load(sc->stats_tag, sc->stats_map,
3222             sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr,
3223             &sc->stats_block_paddr, BUS_DMA_NOWAIT);
3224
3225         if(error) {
3226                 BCE_PRINTF("%s(%d): Could not map statistics block "
3227                     "DMA memory!\n", __FILE__, __LINE__);
3228                 rc = ENOMEM;
3229                 goto bce_dma_alloc_exit;
3230         }
3231
3232         DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n",
3233             __FUNCTION__, (uintmax_t) sc->stats_block_paddr);
3234
3235         /* BCM5709 uses host memory as cache for context memory. */
3236         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
3237             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
3238                 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3239                 if (sc->ctx_pages == 0)
3240                         sc->ctx_pages = 1;
3241
3242                 DBRUNIF((sc->ctx_pages > 512),
3243                     BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n",
3244                     __FILE__, __LINE__, sc->ctx_pages));
3245
3246                 /*
3247                  * Create a DMA tag for the context pages,
3248                  * allocate and clear the memory, map the
3249                  * memory into DMA space, and fetch the
3250                  * physical address of the block.
3251                  */
3252                 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3253                     BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3254                     NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
3255                     0, NULL, NULL, &sc->ctx_tag)) {
3256                         BCE_PRINTF("%s(%d): Could not allocate CTX "
3257                             "DMA tag!\n", __FILE__, __LINE__);
3258                         rc = ENOMEM;
3259                         goto bce_dma_alloc_exit;
3260                 }
3261
3262                 for (i = 0; i < sc->ctx_pages; i++) {
3263
3264                         if(bus_dmamem_alloc(sc->ctx_tag,
3265                             (void **)&sc->ctx_block[i],
3266                             BUS_DMA_NOWAIT,
3267                             &sc->ctx_map[i])) {
3268                                 BCE_PRINTF("%s(%d): Could not allocate CTX "
3269                                     "DMA memory!\n", __FILE__, __LINE__);
3270                                 rc = ENOMEM;
3271                                 goto bce_dma_alloc_exit;
3272                         }
3273
3274                         bzero((char *)sc->ctx_block[i], BCM_PAGE_SIZE);
3275
3276                         error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
3277                             sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr,
3278                             &sc->ctx_paddr[i], BUS_DMA_NOWAIT);
3279
3280                         if (error) {
3281                                 BCE_PRINTF("%s(%d): Could not map CTX "
3282                                     "DMA memory!\n", __FILE__, __LINE__);
3283                                 rc = ENOMEM;
3284                                 goto bce_dma_alloc_exit;
3285                         }
3286
3287                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] "
3288                             "= 0x%jX\n", __FUNCTION__, i,
3289                             (uintmax_t) sc->ctx_paddr[i]);
3290                 }
3291         }
3292
3293         /*
3294          * Create a DMA tag for the TX buffer descriptor chain,
3295          * allocate and clear the  memory, and fetch the
3296          * physical address of the block.
3297          */
3298         if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
3299             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3300             BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0,
3301             NULL, NULL, &sc->tx_bd_chain_tag)) {
3302                 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3303                     "chain DMA tag!\n", __FILE__, __LINE__);
3304                 rc = ENOMEM;
3305                 goto bce_dma_alloc_exit;
3306         }
3307
3308         for (i = 0; i < TX_PAGES; i++) {
3309
3310                 if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
3311                     (void **)&sc->tx_bd_chain[i], BUS_DMA_NOWAIT,
3312                     &sc->tx_bd_chain_map[i])) {
3313                         BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3314                             "chain DMA memory!\n", __FILE__, __LINE__);
3315                         rc = ENOMEM;
3316                         goto bce_dma_alloc_exit;
3317                 }
3318
3319                 error = bus_dmamap_load(sc->tx_bd_chain_tag,
3320                     sc->tx_bd_chain_map[i], sc->tx_bd_chain[i],
3321                     BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3322                     &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3323
3324                 if (error) {
3325                         BCE_PRINTF("%s(%d): Could not map TX descriptor "
3326                             "chain DMA memory!\n", __FILE__, __LINE__);
3327                         rc = ENOMEM;
3328                         goto bce_dma_alloc_exit;
3329                 }
3330
3331                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = "
3332                     "0x%jX\n", __FUNCTION__, i,
3333                     (uintmax_t) sc->tx_bd_chain_paddr[i]);
3334         }
3335
3336         /* Check the required size before mapping to conserve resources. */
3337         if (bce_tso_enable) {
3338                 max_size     = BCE_TSO_MAX_SIZE;
3339                 max_segments = BCE_MAX_SEGMENTS;
3340                 max_seg_size = BCE_TSO_MAX_SEG_SIZE;
3341         } else {
3342                 max_size     = MCLBYTES * BCE_MAX_SEGMENTS;
3343                 max_segments = BCE_MAX_SEGMENTS;
3344                 max_seg_size = MCLBYTES;
3345         }
3346
3347         /* Create a DMA tag for TX mbufs. */
3348         if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3349             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
3350             max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) {
3351                 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
3352                     __FILE__, __LINE__);
3353                 rc = ENOMEM;
3354                 goto bce_dma_alloc_exit;
3355         }
3356
3357         /* Create DMA maps for the TX mbufs clusters. */
3358         for (i = 0; i < TOTAL_TX_BD; i++) {
3359                 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3360                         &sc->tx_mbuf_map[i])) {
3361                         BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA "
3362                             "map!\n", __FILE__, __LINE__);
3363                         rc = ENOMEM;
3364                         goto bce_dma_alloc_exit;
3365                 }
3366         }
3367
3368         /*
3369          * Create a DMA tag for the RX buffer descriptor chain,
3370          * allocate and clear the memory, and fetch the physical
3371          * address of the blocks.
3372          */
3373         if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3374                         BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
3375                         sc->max_bus_addr, NULL, NULL,
3376                         BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
3377                         0, NULL, NULL, &sc->rx_bd_chain_tag)) {
3378                 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain "
3379                     "DMA tag!\n", __FILE__, __LINE__);
3380                 rc = ENOMEM;
3381                 goto bce_dma_alloc_exit;
3382         }
3383
3384         for (i = 0; i < RX_PAGES; i++) {
3385
3386                 if (bus_dmamem_alloc(sc->rx_bd_chain_tag,
3387                     (void **)&sc->rx_bd_chain[i], BUS_DMA_NOWAIT,
3388                     &sc->rx_bd_chain_map[i])) {
3389                         BCE_PRINTF("%s(%d): Could not allocate RX descriptor "
3390                             "chain DMA memory!\n", __FILE__, __LINE__);
3391                         rc = ENOMEM;
3392                         goto bce_dma_alloc_exit;
3393                 }
3394
3395                 bzero((char *)sc->rx_bd_chain[i], BCE_RX_CHAIN_PAGE_SZ);
3396
3397                 error = bus_dmamap_load(sc->rx_bd_chain_tag,
3398                     sc->rx_bd_chain_map[i], sc->rx_bd_chain[i],
3399                     BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3400                     &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3401
3402                 if (error) {
3403                         BCE_PRINTF("%s(%d): Could not map RX descriptor "
3404                             "chain DMA memory!\n", __FILE__, __LINE__);
3405                         rc = ENOMEM;
3406                         goto bce_dma_alloc_exit;
3407                 }
3408
3409                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = "
3410                     "0x%jX\n", __FUNCTION__, i,
3411                     (uintmax_t) sc->rx_bd_chain_paddr[i]);
3412         }
3413
3414         /*
3415          * Create a DMA tag for RX mbufs.
3416          */
3417 #ifdef BCE_JUMBO_HDRSPLIT
3418         max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3419                 MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3420 #else
3421         max_size = max_seg_size = MJUM9BYTES;
3422 #endif
3423         max_segments = 1;
3424
3425         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
3426             "(max size = 0x%jX max segments = %d, max segment "
3427             "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size,
3428              max_segments, (uintmax_t) max_seg_size);
3429
3430         if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3431             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
3432            max_segments, max_seg_size, 0, NULL, NULL, &sc->rx_mbuf_tag)) {
3433                 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3434                     __FILE__, __LINE__);
3435                 rc = ENOMEM;
3436                 goto bce_dma_alloc_exit;
3437         }
3438
3439         /* Create DMA maps for the RX mbuf clusters. */
3440         for (i = 0; i < TOTAL_RX_BD; i++) {
3441                 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT,
3442                     &sc->rx_mbuf_map[i])) {
3443                         BCE_PRINTF("%s(%d): Unable to create RX mbuf "
3444                             "DMA map!\n", __FILE__, __LINE__);
3445                         rc = ENOMEM;
3446                         goto bce_dma_alloc_exit;
3447                 }
3448         }
3449
3450 #ifdef BCE_JUMBO_HDRSPLIT
3451         /*
3452          * Create a DMA tag for the page buffer descriptor chain,
3453          * allocate and clear the memory, and fetch the physical
3454          * address of the blocks.
3455          */
3456         if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3457             BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr,
3458             NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ,
3459             0, NULL, NULL, &sc->pg_bd_chain_tag)) {
3460                 BCE_PRINTF("%s(%d): Could not allocate page descriptor "
3461                     "chain DMA tag!\n", __FILE__, __LINE__);
3462                 rc = ENOMEM;
3463                 goto bce_dma_alloc_exit;
3464         }
3465
3466         for (i = 0; i < PG_PAGES; i++) {
3467
3468                 if (bus_dmamem_alloc(sc->pg_bd_chain_tag,
3469                     (void **)&sc->pg_bd_chain[i], BUS_DMA_NOWAIT,
3470                     &sc->pg_bd_chain_map[i])) {
3471                         BCE_PRINTF("%s(%d): Could not allocate page "
3472                             "descriptor chain DMA memory!\n",
3473                             __FILE__, __LINE__);
3474                         rc = ENOMEM;
3475                         goto bce_dma_alloc_exit;
3476                 }
3477
3478                 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
3479
3480                 error = bus_dmamap_load(sc->pg_bd_chain_tag,
3481                     sc->pg_bd_chain_map[i], sc->pg_bd_chain[i],
3482                     BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr,
3483                     &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3484
3485                 if (error) {
3486                         BCE_PRINTF("%s(%d): Could not map page descriptor "
3487                             "chain DMA memory!\n", __FILE__, __LINE__);
3488                         rc = ENOMEM;
3489                         goto bce_dma_alloc_exit;
3490                 }
3491
3492                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
3493                     "0x%jX\n", __FUNCTION__, i,
3494                     (uintmax_t) sc->pg_bd_chain_paddr[i]);
3495         }
3496
3497         /*
3498          * Create a DMA tag for page mbufs.
3499          */
3500         max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ?
3501             MCLBYTES : sc->pg_bd_mbuf_alloc_size);
3502
3503         if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3504             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3505             max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3506                 BCE_PRINTF("%s(%d): Could not allocate page mbuf "
3507                     "DMA tag!\n", __FILE__, __LINE__);
3508                 rc = ENOMEM;
3509                 goto bce_dma_alloc_exit;
3510         }
3511
3512         /* Create DMA maps for the page mbuf clusters. */
3513         for (i = 0; i < TOTAL_PG_BD; i++) {
3514                 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT,
3515                     &sc->pg_mbuf_map[i])) {
3516                         BCE_PRINTF("%s(%d): Unable to create page mbuf "
3517                             "DMA map!\n", __FILE__, __LINE__);
3518                         rc = ENOMEM;
3519                         goto bce_dma_alloc_exit;
3520                 }
3521         }
3522 #endif
3523
3524 bce_dma_alloc_exit:
3525         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3526         return(rc);
3527 }
3528
3529
3530 /****************************************************************************/
3531 /* Release all resources used by the driver.                                */
3532 /*                                                                          */
3533 /* Releases all resources acquired by the driver including interrupts,      */
3534 /* interrupt handler, interfaces, mutexes, and DMA memory.                  */
3535 /*                                                                          */
3536 /* Returns:                                                                 */
3537 /*   Nothing.                                                               */
3538 /****************************************************************************/
3539 static void
3540 bce_release_resources(struct bce_softc *sc)
3541 {
3542         device_t dev;
3543
3544         DBENTER(BCE_VERBOSE_RESET);
3545
3546         dev = sc->bce_dev;
3547
3548         bce_dma_free(sc);
3549
3550         if (sc->bce_intrhand != NULL) {
3551                 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
3552                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3553         }
3554
3555         if (sc->bce_res_irq != NULL) {
3556                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
3557                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
3558                     sc->bce_res_irq);
3559         }
3560
3561         if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3562                 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
3563                 pci_release_msi(dev);
3564         }
3565
3566         if (sc->bce_res_mem != NULL) {
3567                 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
3568                     bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
3569                     sc->bce_res_mem);
3570         }
3571
3572         if (sc->bce_ifp != NULL) {
3573                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
3574                 if_free(sc->bce_ifp);
3575         }
3576
3577         if (mtx_initialized(&sc->bce_mtx))
3578                 BCE_LOCK_DESTROY(sc);
3579
3580         DBEXIT(BCE_VERBOSE_RESET);
3581 }
3582
3583
3584 /****************************************************************************/
3585 /* Firmware synchronization.                                                */
3586 /*                                                                          */
3587 /* Before performing certain events such as a chip reset, synchronize with  */
3588 /* the firmware first.                                                      */
3589 /*                                                                          */
3590 /* Returns:                                                                 */
3591 /*   0 for success, positive value for failure.                             */
3592 /****************************************************************************/
3593 static int
3594 bce_fw_sync(struct bce_softc *sc, u32 msg_data)
3595 {
3596         int i, rc = 0;
3597         u32 val;
3598
3599         DBENTER(BCE_VERBOSE_RESET);
3600
3601         /* Don't waste any time if we've timed out before. */
3602         if (sc->bce_fw_timed_out == TRUE) {
3603                 rc = EBUSY;
3604                 goto bce_fw_sync_exit;
3605         }
3606
3607         /* Increment the message sequence number. */
3608         sc->bce_fw_wr_seq++;
3609         msg_data |= sc->bce_fw_wr_seq;
3610
3611         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = "
3612             "0x%08X\n", msg_data);
3613
3614         /* Send the message to the bootcode driver mailbox. */
3615         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3616
3617         /* Wait for the bootcode to acknowledge the message. */
3618         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
3619                 /* Check for a response in the bootcode firmware mailbox. */
3620                 val = bce_shmem_rd(sc, BCE_FW_MB);
3621                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
3622                         break;
3623                 DELAY(1000);
3624         }
3625
3626         /* If we've timed out, tell bootcode that we've stopped waiting. */
3627         if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
3628             ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) {
3629
3630                 BCE_PRINTF("%s(%d): Firmware synchronization timeout! "
3631                     "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data);
3632
3633                 msg_data &= ~BCE_DRV_MSG_CODE;
3634                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
3635
3636                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3637
3638                 sc->bce_fw_timed_out = TRUE;
3639                 rc = EBUSY;
3640         }
3641
3642 bce_fw_sync_exit:
3643         DBEXIT(BCE_VERBOSE_RESET);
3644         return (rc);
3645 }
3646
3647
3648 /****************************************************************************/
3649 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
3650 /*                                                                          */
3651 /* Returns:                                                                 */
3652 /*   Nothing.                                                               */
3653 /****************************************************************************/
3654 static void
3655 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code,
3656         u32 rv2p_code_len, u32 rv2p_proc)
3657 {
3658         int i;
3659         u32 val;
3660
3661         DBENTER(BCE_VERBOSE_RESET);
3662
3663         /* Set the page size used by RV2P. */
3664         if (rv2p_proc == RV2P_PROC2) {
3665                 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
3666         }
3667
3668         for (i = 0; i < rv2p_code_len; i += 8) {
3669                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
3670                 rv2p_code++;
3671                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
3672                 rv2p_code++;
3673
3674                 if (rv2p_proc == RV2P_PROC1) {
3675                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
3676                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
3677                 }
3678                 else {
3679                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
3680                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
3681                 }
3682         }
3683
3684         /* Reset the processor, un-stall is done later. */
3685         if (rv2p_proc == RV2P_PROC1) {
3686                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
3687         }
3688         else {
3689                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
3690         }
3691
3692         DBEXIT(BCE_VERBOSE_RESET);
3693 }
3694
3695
3696 /****************************************************************************/
3697 /* Load RISC processor firmware.                                            */
3698 /*                                                                          */
3699 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
3700 /* associated with a particular processor.                                  */
3701 /*                                                                          */
3702 /* Returns:                                                                 */
3703 /*   Nothing.                                                               */
3704 /****************************************************************************/
3705 static void
3706 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
3707         struct fw_info *fw)
3708 {
3709         u32 offset;
3710
3711         DBENTER(BCE_VERBOSE_RESET);
3712
3713     bce_halt_cpu(sc, cpu_reg);
3714
3715         /* Load the Text area. */
3716         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3717         if (fw->text) {
3718                 int j;
3719
3720                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3721                         REG_WR_IND(sc, offset, fw->text[j]);
3722                 }
3723         }
3724
3725         /* Load the Data area. */
3726         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3727         if (fw->data) {
3728                 int j;
3729
3730                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3731                         REG_WR_IND(sc, offset, fw->data[j]);
3732                 }
3733         }
3734
3735         /* Load the SBSS area. */
3736         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3737         if (fw->sbss) {
3738                 int j;
3739
3740                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3741                         REG_WR_IND(sc, offset, fw->sbss[j]);
3742                 }
3743         }
3744
3745         /* Load the BSS area. */
3746         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3747         if (fw->bss) {
3748                 int j;
3749
3750                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3751                         REG_WR_IND(sc, offset, fw->bss[j]);
3752                 }
3753         }
3754
3755         /* Load the Read-Only area. */
3756         offset = cpu_reg->spad_base +
3757                 (fw->rodata_addr - cpu_reg->mips_view_base);
3758         if (fw->rodata) {
3759                 int j;
3760
3761                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3762                         REG_WR_IND(sc, offset, fw->rodata[j]);
3763                 }
3764         }
3765
3766         /* Clear the pre-fetch instruction and set the FW start address. */
3767         REG_WR_IND(sc, cpu_reg->inst, 0);
3768         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
3769
3770         DBEXIT(BCE_VERBOSE_RESET);
3771 }
3772
3773
3774 /****************************************************************************/
3775 /* Starts the RISC processor.                                               */
3776 /*                                                                          */
3777 /* Assumes the CPU starting address has already been set.                   */
3778 /*                                                                          */
3779 /* Returns:                                                                 */
3780 /*   Nothing.                                                               */
3781 /****************************************************************************/
3782 static void
3783 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
3784 {
3785         u32 val;
3786
3787         DBENTER(BCE_VERBOSE_RESET);
3788
3789         /* Start the CPU. */
3790         val = REG_RD_IND(sc, cpu_reg->mode);
3791         val &= ~cpu_reg->mode_value_halt;
3792         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
3793         REG_WR_IND(sc, cpu_reg->mode, val);
3794
3795         DBEXIT(BCE_VERBOSE_RESET);
3796 }
3797
3798
3799 /****************************************************************************/
3800 /* Halts the RISC processor.                                                */
3801 /*                                                                          */
3802 /* Returns:                                                                 */
3803 /*   Nothing.                                                               */
3804 /****************************************************************************/
3805 static void
3806 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
3807 {
3808         u32 val;
3809
3810         DBENTER(BCE_VERBOSE_RESET);
3811
3812         /* Halt the CPU. */
3813         val = REG_RD_IND(sc, cpu_reg->mode);
3814         val |= cpu_reg->mode_value_halt;
3815         REG_WR_IND(sc, cpu_reg->mode, val);
3816         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
3817
3818         DBEXIT(BCE_VERBOSE_RESET);
3819 }
3820
3821
3822 /****************************************************************************/
3823 /* Initialize the RX CPU.                                                   */
3824 /*                                                                          */
3825 /* Returns:                                                                 */
3826 /*   Nothing.                                                               */
3827 /****************************************************************************/
3828 static void
3829 bce_start_rxp_cpu(struct bce_softc *sc)
3830 {
3831         struct cpu_reg cpu_reg;
3832
3833         DBENTER(BCE_VERBOSE_RESET);
3834
3835         cpu_reg.mode = BCE_RXP_CPU_MODE;
3836         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
3837         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
3838         cpu_reg.state = BCE_RXP_CPU_STATE;
3839         cpu_reg.state_value_clear = 0xffffff;
3840         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
3841         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
3842         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
3843         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
3844         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
3845         cpu_reg.spad_base = BCE_RXP_SCRATCH;
3846         cpu_reg.mips_view_base = 0x8000000;
3847
3848         DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n");
3849         bce_start_cpu(sc, &cpu_reg);
3850
3851         DBEXIT(BCE_VERBOSE_RESET);
3852 }
3853
3854
3855 /****************************************************************************/
3856 /* Initialize the RX CPU.                                                   */
3857 /*                                                                          */
3858 /* Returns:                                                                 */
3859 /*   Nothing.                                                               */
3860 /****************************************************************************/
3861 static void
3862 bce_init_rxp_cpu(struct bce_softc *sc)
3863 {
3864         struct cpu_reg cpu_reg;
3865         struct fw_info fw;
3866
3867         DBENTER(BCE_VERBOSE_RESET);
3868
3869         cpu_reg.mode = BCE_RXP_CPU_MODE;
3870         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
3871         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
3872         cpu_reg.state = BCE_RXP_CPU_STATE;
3873         cpu_reg.state_value_clear = 0xffffff;
3874         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
3875         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
3876         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
3877         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
3878         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
3879         cpu_reg.spad_base = BCE_RXP_SCRATCH;
3880         cpu_reg.mips_view_base = 0x8000000;
3881
3882         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
3883                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
3884                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
3885                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
3886                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
3887                 fw.start_addr = bce_RXP_b09FwStartAddr;
3888
3889                 fw.text_addr = bce_RXP_b09FwTextAddr;
3890                 fw.text_len = bce_RXP_b09FwTextLen;
3891                 fw.text_index = 0;
3892                 fw.text = bce_RXP_b09FwText;
3893
3894                 fw.data_addr = bce_RXP_b09FwDataAddr;
3895                 fw.data_len = bce_RXP_b09FwDataLen;
3896                 fw.data_index = 0;
3897                 fw.data = bce_RXP_b09FwData;
3898
3899                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
3900                 fw.sbss_len = bce_RXP_b09FwSbssLen;
3901                 fw.sbss_index = 0;
3902                 fw.sbss = bce_RXP_b09FwSbss;
3903
3904                 fw.bss_addr = bce_RXP_b09FwBssAddr;
3905                 fw.bss_len = bce_RXP_b09FwBssLen;
3906                 fw.bss_index = 0;
3907                 fw.bss = bce_RXP_b09FwBss;
3908
3909                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
3910                 fw.rodata_len = bce_RXP_b09FwRodataLen;
3911                 fw.rodata_index = 0;
3912                 fw.rodata = bce_RXP_b09FwRodata;
3913         } else {
3914                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
3915                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
3916                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
3917                 fw.start_addr = bce_RXP_b06FwStartAddr;
3918
3919                 fw.text_addr = bce_RXP_b06FwTextAddr;
3920                 fw.text_len = bce_RXP_b06FwTextLen;
3921                 fw.text_index = 0;
3922                 fw.text = bce_RXP_b06FwText;
3923
3924                 fw.data_addr = bce_RXP_b06FwDataAddr;
3925                 fw.data_len = bce_RXP_b06FwDataLen;
3926                 fw.data_index = 0;
3927                 fw.data = bce_RXP_b06FwData;
3928
3929                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
3930                 fw.sbss_len = bce_RXP_b06FwSbssLen;
3931                 fw.sbss_index = 0;
3932                 fw.sbss = bce_RXP_b06FwSbss;
3933
3934                 fw.bss_addr = bce_RXP_b06FwBssAddr;
3935                 fw.bss_len = bce_RXP_b06FwBssLen;
3936                 fw.bss_index = 0;
3937                 fw.bss = bce_RXP_b06FwBss;
3938
3939                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
3940                 fw.rodata_len = bce_RXP_b06FwRodataLen;
3941                 fw.rodata_index = 0;
3942                 fw.rodata = bce_RXP_b06FwRodata;
3943         }
3944
3945         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
3946         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3947
3948     /* Delay RXP start until initialization is complete. */
3949
3950         DBEXIT(BCE_VERBOSE_RESET);
3951 }
3952
3953
3954 /****************************************************************************/
3955 /* Initialize the TX CPU.                                                   */
3956 /*                                                                          */
3957 /* Returns:                                                                 */
3958 /*   Nothing.                                                               */
3959 /****************************************************************************/
3960 static void
3961 bce_init_txp_cpu(struct bce_softc *sc)
3962 {
3963         struct cpu_reg cpu_reg;
3964         struct fw_info fw;
3965
3966         DBENTER(BCE_VERBOSE_RESET);
3967
3968         cpu_reg.mode = BCE_TXP_CPU_MODE;
3969         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
3970         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
3971         cpu_reg.state = BCE_TXP_CPU_STATE;
3972         cpu_reg.state_value_clear = 0xffffff;
3973         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
3974         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
3975         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
3976         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
3977         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
3978         cpu_reg.spad_base = BCE_TXP_SCRATCH;
3979         cpu_reg.mips_view_base = 0x8000000;
3980
3981         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
3982                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
3983                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
3984                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
3985                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
3986                 fw.start_addr = bce_TXP_b09FwStartAddr;
3987
3988                 fw.text_addr = bce_TXP_b09FwTextAddr;
3989                 fw.text_len = bce_TXP_b09FwTextLen;
3990                 fw.text_index = 0;
3991                 fw.text = bce_TXP_b09FwText;
3992
3993                 fw.data_addr = bce_TXP_b09FwDataAddr;
3994                 fw.data_len = bce_TXP_b09FwDataLen;
3995                 fw.data_index = 0;
3996                 fw.data = bce_TXP_b09FwData;
3997
3998                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
3999                 fw.sbss_len = bce_TXP_b09FwSbssLen;
4000                 fw.sbss_index = 0;
4001                 fw.sbss = bce_TXP_b09FwSbss;
4002
4003                 fw.bss_addr = bce_TXP_b09FwBssAddr;
4004                 fw.bss_len = bce_TXP_b09FwBssLen;
4005                 fw.bss_index = 0;
4006                 fw.bss = bce_TXP_b09FwBss;
4007
4008                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
4009                 fw.rodata_len = bce_TXP_b09FwRodataLen;
4010                 fw.rodata_index = 0;
4011                 fw.rodata = bce_TXP_b09FwRodata;
4012         } else {
4013                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
4014                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
4015                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
4016                 fw.start_addr = bce_TXP_b06FwStartAddr;
4017
4018                 fw.text_addr = bce_TXP_b06FwTextAddr;
4019                 fw.text_len = bce_TXP_b06FwTextLen;
4020                 fw.text_index = 0;
4021                 fw.text = bce_TXP_b06FwText;
4022
4023                 fw.data_addr = bce_TXP_b06FwDataAddr;
4024                 fw.data_len = bce_TXP_b06FwDataLen;
4025                 fw.data_index = 0;
4026                 fw.data = bce_TXP_b06FwData;
4027
4028                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
4029                 fw.sbss_len = bce_TXP_b06FwSbssLen;
4030                 fw.sbss_index = 0;
4031                 fw.sbss = bce_TXP_b06FwSbss;
4032
4033                 fw.bss_addr = bce_TXP_b06FwBssAddr;
4034                 fw.bss_len = bce_TXP_b06FwBssLen;
4035                 fw.bss_index = 0;
4036                 fw.bss = bce_TXP_b06FwBss;
4037
4038                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
4039                 fw.rodata_len = bce_TXP_b06FwRodataLen;
4040                 fw.rodata_index = 0;
4041                 fw.rodata = bce_TXP_b06FwRodata;
4042         }
4043
4044         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
4045         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4046     bce_start_cpu(sc, &cpu_reg);
4047
4048         DBEXIT(BCE_VERBOSE_RESET);
4049 }
4050
4051
4052 /****************************************************************************/
4053 /* Initialize the TPAT CPU.                                                 */
4054 /*                                                                          */
4055 /* Returns:                                                                 */
4056 /*   Nothing.                                                               */
4057 /****************************************************************************/
4058 static void
4059 bce_init_tpat_cpu(struct bce_softc *sc)
4060 {
4061         struct cpu_reg cpu_reg;
4062         struct fw_info fw;
4063
4064         DBENTER(BCE_VERBOSE_RESET);
4065
4066         cpu_reg.mode = BCE_TPAT_CPU_MODE;
4067         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4068         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4069         cpu_reg.state = BCE_TPAT_CPU_STATE;
4070         cpu_reg.state_value_clear = 0xffffff;
4071         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4072         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4073         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4074         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4075         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4076         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4077         cpu_reg.mips_view_base = 0x8000000;
4078
4079         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4080                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4081                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
4082                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
4083                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
4084                 fw.start_addr = bce_TPAT_b09FwStartAddr;
4085
4086                 fw.text_addr = bce_TPAT_b09FwTextAddr;
4087                 fw.text_len = bce_TPAT_b09FwTextLen;
4088                 fw.text_index = 0;
4089                 fw.text = bce_TPAT_b09FwText;
4090
4091                 fw.data_addr = bce_TPAT_b09FwDataAddr;
4092                 fw.data_len = bce_TPAT_b09FwDataLen;
4093                 fw.data_index = 0;
4094                 fw.data = bce_TPAT_b09FwData;
4095
4096                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
4097                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
4098                 fw.sbss_index = 0;
4099                 fw.sbss = bce_TPAT_b09FwSbss;
4100
4101                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
4102                 fw.bss_len = bce_TPAT_b09FwBssLen;
4103                 fw.bss_index = 0;
4104                 fw.bss = bce_TPAT_b09FwBss;
4105
4106                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
4107                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
4108                 fw.rodata_index = 0;
4109                 fw.rodata = bce_TPAT_b09FwRodata;
4110         } else {
4111                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
4112                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
4113                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
4114                 fw.start_addr = bce_TPAT_b06FwStartAddr;
4115
4116                 fw.text_addr = bce_TPAT_b06FwTextAddr;
4117                 fw.text_len = bce_TPAT_b06FwTextLen;
4118                 fw.text_index = 0;
4119                 fw.text = bce_TPAT_b06FwText;
4120
4121                 fw.data_addr = bce_TPAT_b06FwDataAddr;
4122                 fw.data_len = bce_TPAT_b06FwDataLen;
4123                 fw.data_index = 0;
4124                 fw.data = bce_TPAT_b06FwData;
4125
4126                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
4127                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
4128                 fw.sbss_index = 0;
4129                 fw.sbss = bce_TPAT_b06FwSbss;
4130
4131                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
4132                 fw.bss_len = bce_TPAT_b06FwBssLen;
4133                 fw.bss_index = 0;
4134                 fw.bss = bce_TPAT_b06FwBss;
4135
4136                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
4137                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
4138                 fw.rodata_index = 0;
4139                 fw.rodata = bce_TPAT_b06FwRodata;
4140         }
4141
4142         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
4143         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4144         bce_start_cpu(sc, &cpu_reg);
4145
4146         DBEXIT(BCE_VERBOSE_RESET);
4147 }
4148
4149
4150 /****************************************************************************/
4151 /* Initialize the CP CPU.                                                   */
4152 /*                                                                          */
4153 /* Returns:                                                                 */
4154 /*   Nothing.                                                               */
4155 /****************************************************************************/
4156 static void
4157 bce_init_cp_cpu(struct bce_softc *sc)
4158 {
4159         struct cpu_reg cpu_reg;
4160         struct fw_info fw;
4161
4162         DBENTER(BCE_VERBOSE_RESET);
4163
4164         cpu_reg.mode = BCE_CP_CPU_MODE;
4165         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4166         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4167         cpu_reg.state = BCE_CP_CPU_STATE;
4168         cpu_reg.state_value_clear = 0xffffff;
4169         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4170         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4171         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4172         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4173         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4174         cpu_reg.spad_base = BCE_CP_SCRATCH;
4175         cpu_reg.mips_view_base = 0x8000000;
4176
4177         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4178                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4179                 fw.ver_major = bce_CP_b09FwReleaseMajor;
4180                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
4181                 fw.ver_fix = bce_CP_b09FwReleaseFix;
4182                 fw.start_addr = bce_CP_b09FwStartAddr;
4183
4184                 fw.text_addr = bce_CP_b09FwTextAddr;
4185                 fw.text_len = bce_CP_b09FwTextLen;
4186                 fw.text_index = 0;
4187                 fw.text = bce_CP_b09FwText;
4188
4189                 fw.data_addr = bce_CP_b09FwDataAddr;
4190                 fw.data_len = bce_CP_b09FwDataLen;
4191                 fw.data_index = 0;
4192                 fw.data = bce_CP_b09FwData;
4193
4194                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
4195                 fw.sbss_len = bce_CP_b09FwSbssLen;
4196                 fw.sbss_index = 0;
4197                 fw.sbss = bce_CP_b09FwSbss;
4198
4199                 fw.bss_addr = bce_CP_b09FwBssAddr;
4200                 fw.bss_len = bce_CP_b09FwBssLen;
4201                 fw.bss_index = 0;
4202                 fw.bss = bce_CP_b09FwBss;
4203
4204                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
4205                 fw.rodata_len = bce_CP_b09FwRodataLen;
4206                 fw.rodata_index = 0;
4207                 fw.rodata = bce_CP_b09FwRodata;
4208         } else {
4209                 fw.ver_major = bce_CP_b06FwReleaseMajor;
4210                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
4211                 fw.ver_fix = bce_CP_b06FwReleaseFix;
4212                 fw.start_addr = bce_CP_b06FwStartAddr;
4213
4214                 fw.text_addr = bce_CP_b06FwTextAddr;
4215                 fw.text_len = bce_CP_b06FwTextLen;
4216                 fw.text_index = 0;
4217                 fw.text = bce_CP_b06FwText;
4218
4219                 fw.data_addr = bce_CP_b06FwDataAddr;
4220                 fw.data_len = bce_CP_b06FwDataLen;
4221                 fw.data_index = 0;
4222                 fw.data = bce_CP_b06FwData;
4223
4224                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
4225                 fw.sbss_len = bce_CP_b06FwSbssLen;
4226                 fw.sbss_index = 0;
4227                 fw.sbss = bce_CP_b06FwSbss;
4228
4229                 fw.bss_addr = bce_CP_b06FwBssAddr;
4230                 fw.bss_len = bce_CP_b06FwBssLen;
4231                 fw.bss_index = 0;
4232                 fw.bss = bce_CP_b06FwBss;
4233
4234                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
4235                 fw.rodata_len = bce_CP_b06FwRodataLen;
4236                 fw.rodata_index = 0;
4237                 fw.rodata = bce_CP_b06FwRodata;
4238         }
4239
4240         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
4241         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4242         bce_start_cpu(sc, &cpu_reg);
4243
4244         DBEXIT(BCE_VERBOSE_RESET);
4245 }
4246
4247
4248 /****************************************************************************/
4249 /* Initialize the COM CPU.                                                 */
4250 /*                                                                          */
4251 /* Returns:                                                                 */
4252 /*   Nothing.                                                               */
4253 /****************************************************************************/
4254 static void
4255 bce_init_com_cpu(struct bce_softc *sc)
4256 {
4257         struct cpu_reg cpu_reg;
4258         struct fw_info fw;
4259
4260         DBENTER(BCE_VERBOSE_RESET);
4261
4262         cpu_reg.mode = BCE_COM_CPU_MODE;
4263         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4264         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4265         cpu_reg.state = BCE_COM_CPU_STATE;
4266         cpu_reg.state_value_clear = 0xffffff;
4267         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4268         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4269         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4270         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4271         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4272         cpu_reg.spad_base = BCE_COM_SCRATCH;
4273         cpu_reg.mips_view_base = 0x8000000;
4274
4275         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4276                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4277                 fw.ver_major = bce_COM_b09FwReleaseMajor;
4278                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
4279                 fw.ver_fix = bce_COM_b09FwReleaseFix;
4280                 fw.start_addr = bce_COM_b09FwStartAddr;
4281
4282                 fw.text_addr = bce_COM_b09FwTextAddr;
4283                 fw.text_len = bce_COM_b09FwTextLen;
4284                 fw.text_index = 0;
4285                 fw.text = bce_COM_b09FwText;
4286
4287                 fw.data_addr = bce_COM_b09FwDataAddr;
4288                 fw.data_len = bce_COM_b09FwDataLen;
4289                 fw.data_index = 0;
4290                 fw.data = bce_COM_b09FwData;
4291
4292                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
4293                 fw.sbss_len = bce_COM_b09FwSbssLen;
4294                 fw.sbss_index = 0;
4295                 fw.sbss = bce_COM_b09FwSbss;
4296
4297                 fw.bss_addr = bce_COM_b09FwBssAddr;
4298                 fw.bss_len = bce_COM_b09FwBssLen;
4299                 fw.bss_index = 0;
4300                 fw.bss = bce_COM_b09FwBss;
4301
4302                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
4303                 fw.rodata_len = bce_COM_b09FwRodataLen;
4304                 fw.rodata_index = 0;
4305                 fw.rodata = bce_COM_b09FwRodata;
4306         } else {
4307                 fw.ver_major = bce_COM_b06FwReleaseMajor;
4308                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
4309                 fw.ver_fix = bce_COM_b06FwReleaseFix;
4310                 fw.start_addr = bce_COM_b06FwStartAddr;
4311
4312                 fw.text_addr = bce_COM_b06FwTextAddr;
4313                 fw.text_len = bce_COM_b06FwTextLen;
4314                 fw.text_index = 0;
4315                 fw.text = bce_COM_b06FwText;
4316
4317                 fw.data_addr = bce_COM_b06FwDataAddr;
4318                 fw.data_len = bce_COM_b06FwDataLen;
4319                 fw.data_index = 0;
4320                 fw.data = bce_COM_b06FwData;
4321
4322                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
4323                 fw.sbss_len = bce_COM_b06FwSbssLen;
4324                 fw.sbss_index = 0;
4325                 fw.sbss = bce_COM_b06FwSbss;
4326
4327                 fw.bss_addr = bce_COM_b06FwBssAddr;
4328                 fw.bss_len = bce_COM_b06FwBssLen;
4329                 fw.bss_index = 0;
4330                 fw.bss = bce_COM_b06FwBss;
4331
4332                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
4333                 fw.rodata_len = bce_COM_b06FwRodataLen;
4334                 fw.rodata_index = 0;
4335                 fw.rodata = bce_COM_b06FwRodata;
4336         }
4337
4338         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
4339         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4340         bce_start_cpu(sc, &cpu_reg);
4341
4342         DBEXIT(BCE_VERBOSE_RESET);
4343 }
4344
4345
4346 /****************************************************************************/
4347 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
4348 /*                                                                          */
4349 /* Loads the firmware for each CPU and starts the CPU.                      */
4350 /*                                                                          */
4351 /* Returns:                                                                 */
4352 /*   Nothing.                                                               */
4353 /****************************************************************************/
4354 static void
4355 bce_init_cpus(struct bce_softc *sc)
4356 {
4357         DBENTER(BCE_VERBOSE_RESET);
4358
4359         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4360                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4361
4362                 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) {
4363                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
4364                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
4365                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
4366                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
4367                 } else {
4368                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
4369                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
4370                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
4371                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
4372                 }
4373
4374         } else {
4375                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
4376                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
4377                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
4378                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
4379         }
4380
4381         bce_init_rxp_cpu(sc);
4382         bce_init_txp_cpu(sc);
4383         bce_init_tpat_cpu(sc);
4384         bce_init_com_cpu(sc);
4385         bce_init_cp_cpu(sc);
4386
4387         DBEXIT(BCE_VERBOSE_RESET);
4388 }
4389
4390
4391 /****************************************************************************/
4392 /* Initialize context memory.                                               */
4393 /*                                                                          */
4394 /* Clears the memory associated with each Context ID (CID).                 */
4395 /*                                                                          */
4396 /* Returns:                                                                 */
4397 /*   Nothing.                                                               */
4398 /****************************************************************************/
4399 static int
4400 bce_init_ctx(struct bce_softc *sc)
4401 {
4402         u32 offset, val, vcid_addr;
4403         int i, j, rc, retry_cnt;
4404
4405         rc = 0;
4406         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4407
4408         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4409             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4410                 retry_cnt = CTX_INIT_RETRY_COUNT;
4411
4412                 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n");
4413
4414                 /*
4415                  * BCM5709 context memory may be cached
4416                  * in host memory so prepare the host memory
4417                  * for access.
4418                  */
4419                 val = BCE_CTX_COMMAND_ENABLED |
4420                     BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
4421                 val |= (BCM_PAGE_BITS - 8) << 16;
4422                 REG_WR(sc, BCE_CTX_COMMAND, val);
4423
4424                 /* Wait for mem init command to complete. */
4425                 for (i = 0; i < retry_cnt; i++) {
4426                         val = REG_RD(sc, BCE_CTX_COMMAND);
4427                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4428                                 break;
4429                         DELAY(2);
4430                 }
4431                 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) {
4432                         BCE_PRINTF("%s(): Context memory initialization failed!\n",
4433                             __FUNCTION__);
4434                         rc = EBUSY;
4435                         goto init_ctx_fail;
4436                 }
4437
4438                 for (i = 0; i < sc->ctx_pages; i++) {
4439                         /* Set the physical address of the context memory. */
4440                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4441                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4442                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
4443                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4444                             BCE_ADDR_HI(sc->ctx_paddr[i]));
4445                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4446                             BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4447
4448                         /* Verify the context memory write was successful. */
4449                         for (j = 0; j < retry_cnt; j++) {
4450                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4451                                 if ((val &
4452                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4453                                         break;
4454                                 DELAY(5);
4455                         }
4456                         if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) {
4457                                 BCE_PRINTF("%s(): Failed to initialize "
4458                                     "context page %d!\n", __FUNCTION__, i);
4459                                 rc = EBUSY;
4460                                 goto init_ctx_fail;
4461                         }
4462                 }
4463         } else {
4464
4465                 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n");
4466
4467                 /*
4468                  * For the 5706/5708, context memory is local to
4469                  * the controller, so initialize the controller
4470                  * context memory.
4471                  */
4472
4473                 vcid_addr = GET_CID_ADDR(96);
4474                 while (vcid_addr) {
4475
4476                         vcid_addr -= PHY_CTX_SIZE;
4477
4478                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4479                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4480
4481                         for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4482                                 CTX_WR(sc, 0x00, offset, 0);
4483                         }
4484
4485                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4486                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4487                 }
4488
4489         }
4490 init_ctx_fail:
4491         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4492         return (rc);
4493 }
4494
4495
4496 /****************************************************************************/
4497 /* Fetch the permanent MAC address of the controller.                       */
4498 /*                                                                          */
4499 /* Returns:                                                                 */
4500 /*   Nothing.                                                               */
4501 /****************************************************************************/
4502 static void
4503 bce_get_mac_addr(struct bce_softc *sc)
4504 {
4505         u32 mac_lo = 0, mac_hi = 0;
4506
4507         DBENTER(BCE_VERBOSE_RESET);
4508
4509         /*
4510          * The NetXtreme II bootcode populates various NIC
4511          * power-on and runtime configuration items in a
4512          * shared memory area.  The factory configured MAC
4513          * address is available from both NVRAM and the
4514          * shared memory area so we'll read the value from
4515          * shared memory for speed.
4516          */
4517
4518         mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
4519         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
4520
4521         if ((mac_lo == 0) && (mac_hi == 0)) {
4522                 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
4523                     __FILE__, __LINE__);
4524         } else {
4525                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4526                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4527                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
4528                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
4529                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
4530                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4531         }
4532
4533         DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet "
4534             "address = %6D\n", sc->eaddr, ":");
4535         DBEXIT(BCE_VERBOSE_RESET);
4536 }
4537
4538
4539 /****************************************************************************/
4540 /* Program the MAC address.                                                 */
4541 /*                                                                          */
4542 /* Returns:                                                                 */
4543 /*   Nothing.                                                               */
4544 /****************************************************************************/
4545 static void
4546 bce_set_mac_addr(struct bce_softc *sc)
4547 {
4548         u32 val;
4549         u8 *mac_addr = sc->eaddr;
4550
4551         /* ToDo: Add support for setting multiple MAC addresses. */
4552
4553         DBENTER(BCE_VERBOSE_RESET);
4554         DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = "
4555             "%6D\n", sc->eaddr, ":");
4556
4557         val = (mac_addr[0] << 8) | mac_addr[1];
4558
4559         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4560
4561         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4562             (mac_addr[4] << 8) | mac_addr[5];
4563
4564         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4565
4566         DBEXIT(BCE_VERBOSE_RESET);
4567 }
4568
4569
4570 /****************************************************************************/
4571 /* Stop the controller.                                                     */
4572 /*                                                                          */
4573 /* Returns:                                                                 */
4574 /*   Nothing.                                                               */
4575 /****************************************************************************/
4576 static void
4577 bce_stop(struct bce_softc *sc)
4578 {
4579         struct ifnet *ifp;
4580
4581         DBENTER(BCE_VERBOSE_RESET);
4582
4583         BCE_LOCK_ASSERT(sc);
4584
4585         ifp = sc->bce_ifp;
4586
4587         callout_stop(&sc->bce_tick_callout);
4588
4589         /* Disable the transmit/receive blocks. */
4590         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
4591         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4592         DELAY(20);
4593
4594         bce_disable_intr(sc);
4595
4596         /* Free RX buffers. */
4597 #ifdef BCE_JUMBO_HDRSPLIT
4598         bce_free_pg_chain(sc);
4599 #endif
4600         bce_free_rx_chain(sc);
4601
4602         /* Free TX buffers. */
4603         bce_free_tx_chain(sc);
4604
4605         sc->watchdog_timer = 0;
4606
4607         sc->bce_link_up = FALSE;
4608
4609         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4610
4611         DBEXIT(BCE_VERBOSE_RESET);
4612 }
4613
4614
4615 static int
4616 bce_reset(struct bce_softc *sc, u32 reset_code)
4617 {
4618         u32 val;
4619         int i, rc = 0;
4620
4621         DBENTER(BCE_VERBOSE_RESET);
4622
4623         DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
4624             __FUNCTION__, reset_code);
4625
4626         /* Wait for pending PCI transactions to complete. */
4627         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
4628             BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4629             BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4630             BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4631             BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4632         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4633         DELAY(5);
4634
4635         /* Disable DMA */
4636         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4637             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4638                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
4639                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
4640                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
4641         }
4642
4643         /* Assume bootcode is running. */
4644         sc->bce_fw_timed_out = FALSE;
4645         sc->bce_drv_cardiac_arrest = FALSE;
4646
4647         /* Give the firmware a chance to prepare for the reset. */
4648         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
4649         if (rc)
4650                 goto bce_reset_exit;
4651
4652         /* Set a firmware reminder that this is a soft reset. */
4653         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC);
4654
4655         /* Dummy read to force the chip to complete all current transactions. */
4656         val = REG_RD(sc, BCE_MISC_ID);
4657
4658         /* Chip reset. */
4659         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4660             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4661                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
4662                 REG_RD(sc, BCE_MISC_COMMAND);
4663                 DELAY(5);
4664
4665                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4666                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4667
4668                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
4669         } else {
4670                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4671                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4672                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4673                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
4674
4675                 /* Allow up to 30us for reset to complete. */
4676                 for (i = 0; i < 10; i++) {
4677                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
4678                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4679                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
4680                                 break;
4681                         }
4682                         DELAY(10);
4683                 }
4684
4685                 /* Check that reset completed successfully. */
4686                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4687                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4688                         BCE_PRINTF("%s(%d): Reset failed!\n",
4689                             __FILE__, __LINE__);
4690                         rc = EBUSY;
4691                         goto bce_reset_exit;
4692                 }
4693         }
4694
4695         /* Make sure byte swapping is properly configured. */
4696         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
4697         if (val != 0x01020304) {
4698                 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
4699                     __FILE__, __LINE__);
4700                 rc = ENODEV;
4701                 goto bce_reset_exit;
4702         }
4703
4704         /* Just completed a reset, assume that firmware is running again. */
4705         sc->bce_fw_timed_out = FALSE;
4706         sc->bce_drv_cardiac_arrest = FALSE;
4707
4708         /* Wait for the firmware to finish its initialization. */
4709         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
4710         if (rc)
4711                 BCE_PRINTF("%s(%d): Firmware did not complete "
4712                     "initialization!\n", __FILE__, __LINE__);
4713
4714 bce_reset_exit:
4715         DBEXIT(BCE_VERBOSE_RESET);
4716         return (rc);
4717 }
4718
4719
4720 static int
4721 bce_chipinit(struct bce_softc *sc)
4722 {
4723         u32 val;
4724         int rc = 0;
4725
4726         DBENTER(BCE_VERBOSE_RESET);
4727
4728         bce_disable_intr(sc);
4729
4730         /*
4731          * Initialize DMA byte/word swapping, configure the number of DMA
4732          * channels and PCI clock compensation delay.
4733          */
4734         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
4735             BCE_DMA_CONFIG_DATA_WORD_SWAP |
4736 #if BYTE_ORDER == BIG_ENDIAN
4737             BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
4738 #endif
4739             BCE_DMA_CONFIG_CNTL_WORD_SWAP |
4740             DMA_READ_CHANS << 12 |
4741             DMA_WRITE_CHANS << 16;
4742
4743         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
4744
4745         if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
4746                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
4747
4748         /*
4749          * This setting resolves a problem observed on certain Intel PCI
4750          * chipsets that cannot handle multiple outstanding DMA operations.
4751          * See errata E9_5706A1_65.
4752          */
4753         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
4754             (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
4755             !(sc->bce_flags & BCE_PCIX_FLAG))
4756                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
4757
4758         REG_WR(sc, BCE_DMA_CONFIG, val);
4759
4760         /* Enable the RX_V2P and Context state machines before access. */
4761         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4762             BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4763             BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4764             BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4765
4766         /* Initialize context mapping and zero out the quick contexts. */
4767         if ((rc = bce_init_ctx(sc)) != 0)
4768                 goto bce_chipinit_exit;
4769
4770         /* Initialize the on-boards CPUs */
4771         bce_init_cpus(sc);
4772
4773         /* Enable management frames (NC-SI) to flow to the MCP. */
4774         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
4775                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
4776                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
4777         }
4778
4779         /* Prepare NVRAM for access. */
4780         if ((rc = bce_init_nvram(sc)) != 0)
4781                 goto bce_chipinit_exit;
4782
4783         /* Set the kernel bypass block size */
4784         val = REG_RD(sc, BCE_MQ_CONFIG);
4785         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4786         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4787
4788         /* Enable bins used on the 5709. */
4789         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4790             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4791                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
4792                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
4793                         val |= BCE_MQ_CONFIG_HALT_DIS;
4794         }
4795
4796         REG_WR(sc, BCE_MQ_CONFIG, val);
4797
4798         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4799         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
4800         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
4801
4802         /* Set the page size and clear the RV2P processor stall bits. */
4803         val = (BCM_PAGE_BITS - 8) << 24;
4804         REG_WR(sc, BCE_RV2P_CONFIG, val);
4805
4806         /* Configure page size. */
4807         val = REG_RD(sc, BCE_TBDR_CONFIG);
4808         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
4809         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4810         REG_WR(sc, BCE_TBDR_CONFIG, val);
4811
4812         /* Set the perfect match control register to default. */
4813         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
4814
4815 bce_chipinit_exit:
4816         DBEXIT(BCE_VERBOSE_RESET);
4817
4818         return(rc);
4819 }
4820
4821
4822 /****************************************************************************/
4823 /* Initialize the controller in preparation to send/receive traffic.        */
4824 /*                                                                          */
4825 /* Returns:                                                                 */
4826 /*   0 for success, positive value for failure.                             */
4827 /****************************************************************************/
4828 static int
4829 bce_blockinit(struct bce_softc *sc)
4830 {
4831         u32 reg, val;
4832         int rc = 0;
4833
4834         DBENTER(BCE_VERBOSE_RESET);
4835
4836         /* Load the hardware default MAC address. */
4837         bce_set_mac_addr(sc);
4838
4839         /* Set the Ethernet backoff seed value */
4840         val = sc->eaddr[0]         + (sc->eaddr[1] << 8) +
4841               (sc->eaddr[2] << 16) + (sc->eaddr[3]     ) +
4842               (sc->eaddr[4] << 8)  + (sc->eaddr[5] << 16);
4843         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
4844
4845         sc->last_status_idx = 0;
4846         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
4847
4848         /* Set up link change interrupt generation. */
4849         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
4850
4851         /* Program the physical address of the status block. */
4852         REG_WR(sc, BCE_HC_STATUS_ADDR_L,
4853             BCE_ADDR_LO(sc->status_block_paddr));
4854         REG_WR(sc, BCE_HC_STATUS_ADDR_H,
4855             BCE_ADDR_HI(sc->status_block_paddr));
4856
4857         /* Program the physical address of the statistics block. */
4858         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
4859             BCE_ADDR_LO(sc->stats_block_paddr));
4860         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
4861             BCE_ADDR_HI(sc->stats_block_paddr));
4862
4863         /* Program various host coalescing parameters. */
4864         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4865             (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip);
4866         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4867             (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip);
4868         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
4869             (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
4870         REG_WR(sc, BCE_HC_TX_TICKS,
4871             (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
4872         REG_WR(sc, BCE_HC_RX_TICKS,
4873             (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
4874         REG_WR(sc, BCE_HC_COM_TICKS,
4875             (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
4876         REG_WR(sc, BCE_HC_CMD_TICKS,
4877             (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
4878         REG_WR(sc, BCE_HC_STATS_TICKS,
4879             (sc->bce_stats_ticks & 0xffff00));
4880         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4881
4882         /* Configure the Host Coalescing block. */
4883         val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
4884             BCE_HC_CONFIG_COLLECT_STATS;
4885
4886 #if 0
4887         /* ToDo: Add MSI-X support. */
4888         if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
4889                 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
4890                     BCE_HC_SB_CONFIG_1;
4891
4892                 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
4893
4894                 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
4895                     BCE_HC_SB_CONFIG_1_ONE_SHOT);
4896
4897                 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
4898                     (sc->tx_quick_cons_trip_int << 16) |
4899                      sc->tx_quick_cons_trip);
4900
4901                 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
4902                     (sc->tx_ticks_int << 16) | sc->tx_ticks);
4903
4904                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
4905         }
4906
4907         /*
4908          * Tell the HC block to automatically set the
4909          * INT_MASK bit after an MSI/MSI-X interrupt
4910          * is generated so the driver doesn't have to.
4911          */
4912         if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
4913                 val |= BCE_HC_CONFIG_ONE_SHOT;
4914
4915         /* Set the MSI-X status blocks to 128 byte boundaries. */
4916         if (sc->bce_flags & BCE_USING_MSIX_FLAG)
4917                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
4918 #endif
4919
4920         REG_WR(sc, BCE_HC_CONFIG, val);
4921
4922         /* Clear the internal statistics counters. */
4923         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
4924
4925         /* Verify that bootcode is running. */
4926         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
4927
4928         DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control),
4929             BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
4930             __FILE__, __LINE__);
4931             reg = 0);
4932
4933         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
4934             BCE_DEV_INFO_SIGNATURE_MAGIC) {
4935                 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
4936                     "Expected: 08%08X\n", __FILE__, __LINE__,
4937                     (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
4938                     BCE_DEV_INFO_SIGNATURE_MAGIC);
4939                 rc = ENODEV;
4940                 goto bce_blockinit_exit;
4941         }
4942
4943         /* Enable DMA */
4944         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4945             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4946                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
4947                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
4948                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
4949         }
4950
4951         /* Allow bootcode to apply additional fixes before enabling MAC. */
4952         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 |
4953             BCE_DRV_MSG_CODE_RESET);
4954
4955         /* Enable link state change interrupt generation. */
4956         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
4957
4958         /* Enable the RXP. */
4959         bce_start_rxp_cpu(sc);
4960
4961         /* Disable management frames (NC-SI) from flowing to the MCP. */
4962         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
4963                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
4964                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
4965                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
4966         }
4967
4968         /* Enable all remaining blocks in the MAC. */
4969         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4970             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
4971                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4972                     BCE_MISC_ENABLE_DEFAULT_XI);
4973         else
4974                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4975                     BCE_MISC_ENABLE_DEFAULT);
4976
4977         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4978         DELAY(20);
4979
4980         /* Save the current host coalescing block settings. */
4981         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
4982
4983 bce_blockinit_exit:
4984         DBEXIT(BCE_VERBOSE_RESET);
4985
4986         return (rc);
4987 }
4988
4989
4990 /****************************************************************************/
4991 /* Encapsulate an mbuf into the rx_bd chain.                                */
4992 /*                                                                          */
4993 /* Returns:                                                                 */
4994 /*   0 for success, positive value for failure.                             */
4995 /****************************************************************************/
4996 static int
4997 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod,
4998     u16 *chain_prod, u32 *prod_bseq)
4999 {
5000         bus_dmamap_t map;
5001         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
5002         struct mbuf *m_new = NULL;
5003         struct rx_bd *rxbd;
5004         int nsegs, error, rc = 0;
5005 #ifdef BCE_DEBUG
5006         u16 debug_chain_prod = *chain_prod;
5007 #endif
5008
5009         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5010
5011         /* Make sure the inputs are valid. */
5012         DBRUNIF((*chain_prod > MAX_RX_BD),
5013             BCE_PRINTF("%s(%d): RX producer out of range: "
5014             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5015             *chain_prod, (u16) MAX_RX_BD));
5016
5017         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5018             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__,
5019             *prod, *chain_prod, *prod_bseq);
5020
5021         /* Update some debug statistic counters */
5022         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5023             sc->rx_low_watermark = sc->free_rx_bd);
5024         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
5025             sc->rx_empty_count++);
5026
5027         /* Check whether this is a new mbuf allocation. */
5028         if (m == NULL) {
5029
5030                 /* Simulate an mbuf allocation failure. */
5031                 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5032                     sc->mbuf_alloc_failed_count++;
5033                     sc->mbuf_alloc_failed_sim_count++;
5034                     rc = ENOBUFS;
5035                     goto bce_get_rx_buf_exit);
5036
5037                 /* This is a new mbuf allocation. */
5038 #ifdef BCE_JUMBO_HDRSPLIT
5039                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
5040 #else
5041                 if (sc->rx_bd_mbuf_alloc_size <= MCLBYTES)
5042                         m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
5043                 else
5044                         m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR,
5045                             sc->rx_bd_mbuf_alloc_size);
5046 #endif
5047
5048                 if (m_new == NULL) {
5049                         sc->mbuf_alloc_failed_count++;
5050                         rc = ENOBUFS;
5051                         goto bce_get_rx_buf_exit;
5052                 }
5053
5054                 DBRUN(sc->debug_rx_mbuf_alloc++);
5055         } else {
5056                 /* Reuse an existing mbuf. */
5057                 m_new = m;
5058         }
5059
5060         /* Make sure we have a valid packet header. */
5061         M_ASSERTPKTHDR(m_new);
5062
5063         /* Initialize the mbuf size and pad if necessary for alignment. */
5064         m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size;
5065         m_adj(m_new, sc->rx_bd_mbuf_align_pad);
5066
5067         /* ToDo: Consider calling m_fragment() to test error handling. */
5068
5069         /* Map the mbuf cluster into device memory. */
5070         map = sc->rx_mbuf_map[*chain_prod];
5071         error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new,
5072             segs, &nsegs, BUS_DMA_NOWAIT);
5073
5074         /* Handle any mapping errors. */
5075         if (error) {
5076                 BCE_PRINTF("%s(%d): Error mapping mbuf into RX "
5077                     "chain (%d)!\n", __FILE__, __LINE__, error);
5078
5079                 sc->dma_map_addr_rx_failed_count++;
5080                 m_freem(m_new);
5081
5082                 DBRUN(sc->debug_rx_mbuf_alloc--);
5083
5084                 rc = ENOBUFS;
5085                 goto bce_get_rx_buf_exit;
5086         }
5087
5088         /* All mbufs must map to a single segment. */
5089         KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5090             __FUNCTION__, nsegs));
5091
5092         /* Setup the rx_bd for the segment. */
5093         rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
5094
5095         rxbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5096         rxbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5097         rxbd->rx_bd_len       = htole32(segs[0].ds_len);
5098         rxbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5099         *prod_bseq += segs[0].ds_len;
5100
5101         /* Save the mbuf and update our counter. */
5102         sc->rx_mbuf_ptr[*chain_prod] = m_new;
5103         sc->free_rx_bd -= nsegs;
5104
5105         DBRUNMSG(BCE_INSANE_RECV,
5106             bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs));
5107
5108         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5109             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n",
5110             __FUNCTION__, *prod, *chain_prod, *prod_bseq);
5111
5112 bce_get_rx_buf_exit:
5113         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5114
5115         return(rc);
5116 }
5117
5118
5119 #ifdef BCE_JUMBO_HDRSPLIT
5120 /****************************************************************************/
5121 /* Encapsulate an mbuf cluster into the page chain.                         */
5122 /*                                                                          */
5123 /* Returns:                                                                 */
5124 /*   0 for success, positive value for failure.                             */
5125 /****************************************************************************/
5126 static int
5127 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod,
5128         u16 *prod_idx)
5129 {
5130         bus_dmamap_t map;
5131         bus_addr_t busaddr;
5132         struct mbuf *m_new = NULL;
5133         struct rx_bd *pgbd;
5134         int error, rc = 0;
5135 #ifdef BCE_DEBUG
5136         u16 debug_prod_idx = *prod_idx;
5137 #endif
5138
5139         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5140
5141         /* Make sure the inputs are valid. */
5142         DBRUNIF((*prod_idx > MAX_PG_BD),
5143             BCE_PRINTF("%s(%d): page producer out of range: "
5144             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5145             *prod_idx, (u16) MAX_PG_BD));
5146
5147         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5148             "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
5149
5150         /* Update counters if we've hit a new low or run out of pages. */
5151         DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
5152             sc->pg_low_watermark = sc->free_pg_bd);
5153         DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
5154
5155         /* Check whether this is a new mbuf allocation. */
5156         if (m == NULL) {
5157
5158                 /* Simulate an mbuf allocation failure. */
5159                 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5160                     sc->mbuf_alloc_failed_count++;
5161                     sc->mbuf_alloc_failed_sim_count++;
5162                     rc = ENOBUFS;
5163                     goto bce_get_pg_buf_exit);
5164
5165                 /* This is a new mbuf allocation. */
5166                 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0);
5167                 if (m_new == NULL) {
5168                         sc->mbuf_alloc_failed_count++;
5169                         rc = ENOBUFS;
5170                         goto bce_get_pg_buf_exit;
5171                 }
5172
5173                 DBRUN(sc->debug_pg_mbuf_alloc++);
5174         } else {
5175                 /* Reuse an existing mbuf. */
5176                 m_new = m;
5177                 m_new->m_data = m_new->m_ext.ext_buf;
5178         }
5179
5180         m_new->m_len = sc->pg_bd_mbuf_alloc_size;
5181
5182         /* ToDo: Consider calling m_fragment() to test error handling. */
5183
5184         /* Map the mbuf cluster into device memory. */
5185         map = sc->pg_mbuf_map[*prod_idx];
5186         error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *),
5187             sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr,
5188             &busaddr, BUS_DMA_NOWAIT);
5189
5190         /* Handle any mapping errors. */
5191         if (error) {
5192                 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
5193                     __FILE__, __LINE__);
5194
5195                 m_freem(m_new);
5196                 DBRUN(sc->debug_pg_mbuf_alloc--);
5197
5198                 rc = ENOBUFS;
5199                 goto bce_get_pg_buf_exit;
5200         }
5201
5202         /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */
5203
5204         /*
5205          * The page chain uses the same rx_bd data structure
5206          * as the receive chain but doesn't require a byte sequence (bseq).
5207          */
5208         pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)];
5209
5210         pgbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(busaddr));
5211         pgbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(busaddr));
5212         pgbd->rx_bd_len       = htole32(sc->pg_bd_mbuf_alloc_size);
5213         pgbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5214
5215         /* Save the mbuf and update our counter. */
5216         sc->pg_mbuf_ptr[*prod_idx] = m_new;
5217         sc->free_pg_bd--;
5218
5219         DBRUNMSG(BCE_INSANE_RECV,
5220             bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1));
5221
5222         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5223             "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
5224
5225 bce_get_pg_buf_exit:
5226         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5227
5228         return(rc);
5229 }
5230 #endif /* BCE_JUMBO_HDRSPLIT */
5231
5232
5233 /****************************************************************************/
5234 /* Initialize the TX context memory.                                        */
5235 /*                                                                          */
5236 /* Returns:                                                                 */
5237 /*   Nothing                                                                */
5238 /****************************************************************************/
5239 static void
5240 bce_init_tx_context(struct bce_softc *sc)
5241 {
5242         u32 val;
5243
5244         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5245
5246         /* Initialize the context ID for an L2 TX chain. */
5247         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
5248                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
5249                 /* Set the CID type to support an L2 connection. */
5250                 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI |
5251                     BCE_L2CTX_TX_TYPE_SIZE_L2_XI;
5252                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
5253                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16);
5254                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5255                     BCE_L2CTX_TX_CMD_TYPE_XI, val);
5256
5257                 /* Point the hardware to the first page in the chain. */
5258                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5259                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5260                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
5261                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5262                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5263                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
5264         } else {
5265                 /* Set the CID type to support an L2 connection. */
5266                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
5267                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
5268                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
5269                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
5270
5271                 /* Point the hardware to the first page in the chain. */
5272                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5273                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5274                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
5275                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5276                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5277                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
5278         }
5279
5280         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5281 }
5282
5283
5284 /****************************************************************************/
5285 /* Allocate memory and initialize the TX data structures.                   */
5286 /*                                                                          */
5287 /* Returns:                                                                 */
5288 /*   0 for success, positive value for failure.                             */
5289 /****************************************************************************/
5290 static int
5291 bce_init_tx_chain(struct bce_softc *sc)
5292 {
5293         struct tx_bd *txbd;
5294         int i, rc = 0;
5295
5296         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5297
5298         /* Set the initial TX producer/consumer indices. */
5299         sc->tx_prod        = 0;
5300         sc->tx_cons        = 0;
5301         sc->tx_prod_bseq   = 0;
5302         sc->used_tx_bd     = 0;
5303         sc->max_tx_bd      = USABLE_TX_BD;
5304         DBRUN(sc->tx_hi_watermark = 0);
5305         DBRUN(sc->tx_full_count = 0);
5306
5307         /*
5308          * The NetXtreme II supports a linked-list structre called
5309          * a Buffer Descriptor Chain (or BD chain).  A BD chain
5310          * consists of a series of 1 or more chain pages, each of which
5311          * consists of a fixed number of BD entries.
5312          * The last BD entry on each page is a pointer to the next page
5313          * in the chain, and the last pointer in the BD chain
5314          * points back to the beginning of the chain.
5315          */
5316
5317         /* Set the TX next pointer chain entries. */
5318         for (i = 0; i < TX_PAGES; i++) {
5319                 int j;
5320
5321                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
5322
5323                 /* Check if we've reached the last page. */
5324                 if (i == (TX_PAGES - 1))
5325                         j = 0;
5326                 else
5327                         j = i + 1;
5328
5329                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5330                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5331         }
5332
5333         bce_init_tx_context(sc);
5334
5335         DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD));
5336         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5337
5338         return(rc);
5339 }
5340
5341
5342 /****************************************************************************/
5343 /* Free memory and clear the TX data structures.                            */
5344 /*                                                                          */
5345 /* Returns:                                                                 */
5346 /*   Nothing.                                                               */
5347 /****************************************************************************/
5348 static void
5349 bce_free_tx_chain(struct bce_softc *sc)
5350 {
5351         int i;
5352
5353         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5354
5355         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
5356         for (i = 0; i < TOTAL_TX_BD; i++) {
5357                 if (sc->tx_mbuf_ptr[i] != NULL) {
5358                         if (sc->tx_mbuf_map[i] != NULL)
5359                                 bus_dmamap_sync(sc->tx_mbuf_tag,
5360                                     sc->tx_mbuf_map[i],
5361                                     BUS_DMASYNC_POSTWRITE);
5362                         m_freem(sc->tx_mbuf_ptr[i]);
5363                         sc->tx_mbuf_ptr[i] = NULL;
5364                         DBRUN(sc->debug_tx_mbuf_alloc--);
5365                 }
5366         }
5367
5368         /* Clear each TX chain page. */
5369         for (i = 0; i < TX_PAGES; i++)
5370                 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5371
5372         sc->used_tx_bd = 0;
5373
5374         /* Check if we lost any mbufs in the process. */
5375         DBRUNIF((sc->debug_tx_mbuf_alloc),
5376             BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
5377             "from tx chain!\n", __FILE__, __LINE__,
5378             sc->debug_tx_mbuf_alloc));
5379
5380         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5381 }
5382
5383
5384 /****************************************************************************/
5385 /* Initialize the RX context memory.                                        */
5386 /*                                                                          */
5387 /* Returns:                                                                 */
5388 /*   Nothing                                                                */
5389 /****************************************************************************/
5390 static void
5391 bce_init_rx_context(struct bce_softc *sc)
5392 {
5393         u32 val;
5394
5395         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5396
5397         /* Init the type, size, and BD cache levels for the RX context. */
5398         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5399             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 |
5400             (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT);
5401
5402         /*
5403          * Set the level for generating pause frames
5404          * when the number of available rx_bd's gets
5405          * too low (the low watermark) and the level
5406          * when pause frames can be stopped (the high
5407          * watermark).
5408          */
5409         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
5410             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
5411                 u32 lo_water, hi_water;
5412
5413                 if (sc->bce_flags && BCE_USING_TX_FLOW_CONTROL) {
5414                         lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
5415                 } else {
5416                         lo_water = 0;
5417                 }
5418
5419                 if (lo_water >= USABLE_RX_BD) {
5420                         lo_water = 0;
5421                 }
5422
5423                 hi_water = USABLE_RX_BD / 4;
5424
5425                 if (hi_water <= lo_water) {
5426                         lo_water = 0;
5427                 }
5428
5429                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
5430                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
5431
5432                 if (hi_water > 0xf)
5433                         hi_water = 0xf;
5434                 else if (hi_water == 0)
5435                         lo_water = 0;
5436
5437                 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) |
5438                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
5439         }
5440
5441         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
5442
5443         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
5444         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
5445             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
5446                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5447                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5448         }
5449
5450         /* Point the hardware to the first page in the chain. */
5451         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5452         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
5453         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5454         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
5455
5456         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5457 }
5458
5459
5460 /****************************************************************************/
5461 /* Allocate memory and initialize the RX data structures.                   */
5462 /*                                                                          */
5463 /* Returns:                                                                 */
5464 /*   0 for success, positive value for failure.                             */
5465 /****************************************************************************/
5466 static int
5467 bce_init_rx_chain(struct bce_softc *sc)
5468 {
5469         struct rx_bd *rxbd;
5470         int i, rc = 0;
5471
5472         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5473             BCE_VERBOSE_CTX);
5474
5475         /* Initialize the RX producer and consumer indices. */
5476         sc->rx_prod        = 0;
5477         sc->rx_cons        = 0;
5478         sc->rx_prod_bseq   = 0;
5479         sc->free_rx_bd     = USABLE_RX_BD;
5480         sc->max_rx_bd      = USABLE_RX_BD;
5481
5482         /* Initialize the RX next pointer chain entries. */
5483         for (i = 0; i < RX_PAGES; i++) {
5484                 int j;
5485
5486                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
5487
5488                 /* Check if we've reached the last page. */
5489                 if (i == (RX_PAGES - 1))
5490                         j = 0;
5491                 else
5492                         j = i + 1;
5493
5494                 /* Setup the chain page pointers. */
5495                 rxbd->rx_bd_haddr_hi =
5496                     htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5497                 rxbd->rx_bd_haddr_lo =
5498                     htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5499         }
5500
5501         /* Fill up the RX chain. */
5502         bce_fill_rx_chain(sc);
5503
5504         DBRUN(sc->rx_low_watermark = USABLE_RX_BD);
5505         DBRUN(sc->rx_empty_count = 0);
5506         for (i = 0; i < RX_PAGES; i++) {
5507                 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
5508                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5509         }
5510
5511         bce_init_rx_context(sc);
5512
5513         DBRUNMSG(BCE_EXTREME_RECV, bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD));
5514         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5515             BCE_VERBOSE_CTX);
5516
5517         /* ToDo: Are there possible failure modes here? */
5518
5519         return(rc);
5520 }
5521
5522
5523 /****************************************************************************/
5524 /* Add mbufs to the RX chain until its full or an mbuf allocation error     */
5525 /* occurs.                                                                  */
5526 /*                                                                          */
5527 /* Returns:                                                                 */
5528 /*   Nothing                                                                */
5529 /****************************************************************************/
5530 static void
5531 bce_fill_rx_chain(struct bce_softc *sc)
5532 {
5533         u16 prod, prod_idx;
5534         u32 prod_bseq;
5535
5536         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5537             BCE_VERBOSE_CTX);
5538
5539         /* Get the RX chain producer indices. */
5540         prod      = sc->rx_prod;
5541         prod_bseq = sc->rx_prod_bseq;
5542
5543         /* Keep filling the RX chain until it's full. */
5544         while (sc->free_rx_bd > 0) {
5545                 prod_idx = RX_CHAIN_IDX(prod);
5546                 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) {
5547                         /* Bail out if we can't add an mbuf to the chain. */
5548                         break;
5549                 }
5550                 prod = NEXT_RX_BD(prod);
5551         }
5552
5553         /* Save the RX chain producer indices. */
5554         sc->rx_prod      = prod;
5555         sc->rx_prod_bseq = prod_bseq;
5556
5557         /* We should never end up pointing to a next page pointer. */
5558         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5559             BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5560             __FUNCTION__, sc->rx_prod));
5561
5562         /* Write the mailbox and tell the chip about the waiting rx_bd's. */
5563         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) +
5564             BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod);
5565         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) +
5566             BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq);
5567
5568         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5569             BCE_VERBOSE_CTX);
5570 }
5571
5572
5573 /****************************************************************************/
5574 /* Free memory and clear the RX data structures.                            */
5575 /*                                                                          */
5576 /* Returns:                                                                 */
5577 /*   Nothing.                                                               */
5578 /****************************************************************************/
5579 static void
5580 bce_free_rx_chain(struct bce_softc *sc)
5581 {
5582         int i;
5583
5584         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5585
5586         /* Free any mbufs still in the RX mbuf chain. */
5587         for (i = 0; i < TOTAL_RX_BD; i++) {
5588                 if (sc->rx_mbuf_ptr[i] != NULL) {
5589                         if (sc->rx_mbuf_map[i] != NULL)
5590                                 bus_dmamap_sync(sc->rx_mbuf_tag,
5591                                     sc->rx_mbuf_map[i],
5592                                     BUS_DMASYNC_POSTREAD);
5593                         m_freem(sc->rx_mbuf_ptr[i]);
5594                         sc->rx_mbuf_ptr[i] = NULL;
5595                         DBRUN(sc->debug_rx_mbuf_alloc--);
5596                 }
5597         }
5598
5599         /* Clear each RX chain page. */
5600         for (i = 0; i < RX_PAGES; i++)
5601                 if (sc->rx_bd_chain[i] != NULL) {
5602                         bzero((char *)sc->rx_bd_chain[i],
5603                             BCE_RX_CHAIN_PAGE_SZ);
5604                 }
5605
5606         sc->free_rx_bd = sc->max_rx_bd;
5607
5608         /* Check if we lost any mbufs in the process. */
5609         DBRUNIF((sc->debug_rx_mbuf_alloc),
5610             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5611             __FUNCTION__, sc->debug_rx_mbuf_alloc));
5612
5613         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5614 }
5615
5616
5617 #ifdef BCE_JUMBO_HDRSPLIT
5618 /****************************************************************************/
5619 /* Allocate memory and initialize the page data structures.                 */
5620 /* Assumes that bce_init_rx_chain() has not already been called.            */
5621 /*                                                                          */
5622 /* Returns:                                                                 */
5623 /*   0 for success, positive value for failure.                             */
5624 /****************************************************************************/
5625 static int
5626 bce_init_pg_chain(struct bce_softc *sc)
5627 {
5628         struct rx_bd *pgbd;
5629         int i, rc = 0;
5630         u32 val;
5631
5632         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5633                 BCE_VERBOSE_CTX);
5634
5635         /* Initialize the page producer and consumer indices. */
5636         sc->pg_prod        = 0;
5637         sc->pg_cons        = 0;
5638         sc->free_pg_bd     = USABLE_PG_BD;
5639         sc->max_pg_bd      = USABLE_PG_BD;
5640         DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
5641         DBRUN(sc->pg_empty_count = 0);
5642
5643         /* Initialize the page next pointer chain entries. */
5644         for (i = 0; i < PG_PAGES; i++) {
5645                 int j;
5646
5647                 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE];
5648
5649                 /* Check if we've reached the last page. */
5650                 if (i == (PG_PAGES - 1))
5651                         j = 0;
5652                 else
5653                         j = i + 1;
5654
5655                 /* Setup the chain page pointers. */
5656                 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
5657                 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
5658         }
5659
5660         /* Setup the MQ BIN mapping for host_pg_bidx. */
5661         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)     ||
5662                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
5663                 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
5664
5665         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
5666
5667         /* Configure the rx_bd and page chain mbuf cluster size. */
5668         val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size;
5669         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
5670
5671         /* Configure the context reserved for jumbo support. */
5672         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
5673                 BCE_L2CTX_RX_RBDC_JUMBO_KEY);
5674
5675         /* Point the hardware to the first page in the page chain. */
5676         val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
5677         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val);
5678         val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
5679         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val);
5680
5681         /* Fill up the page chain. */
5682         bce_fill_pg_chain(sc);
5683
5684         for (i = 0; i < PG_PAGES; i++) {
5685                 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i],
5686                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5687         }
5688
5689         DBRUNMSG(BCE_EXTREME_RECV, bce_dump_pg_chain(sc, 0, TOTAL_PG_BD));
5690         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5691                 BCE_VERBOSE_CTX);
5692         return(rc);
5693 }
5694
5695
5696 /****************************************************************************/
5697 /* Add mbufs to the page chain until its full or an mbuf allocation error   */
5698 /* occurs.                                                                  */
5699 /*                                                                          */
5700 /* Returns:                                                                 */
5701 /*   Nothing                                                                */
5702 /****************************************************************************/
5703 static void
5704 bce_fill_pg_chain(struct bce_softc *sc)
5705 {
5706         u16 prod, prod_idx;
5707
5708         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5709             BCE_VERBOSE_CTX);
5710
5711         /* Get the page chain prodcuer index. */
5712         prod = sc->pg_prod;
5713
5714         /* Keep filling the page chain until it's full. */
5715         while (sc->free_pg_bd > 0) {
5716                 prod_idx = PG_CHAIN_IDX(prod);
5717                 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) {
5718                         /* Bail out if we can't add an mbuf to the chain. */
5719                         break;
5720                 }
5721                 prod = NEXT_PG_BD(prod);
5722         }
5723
5724         /* Save the page chain producer index. */
5725         sc->pg_prod = prod;
5726
5727         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5728             BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
5729             __FUNCTION__, sc->pg_prod));
5730
5731         /*
5732          * Write the mailbox and tell the chip about
5733          * the new rx_bd's in the page chain.
5734          */
5735         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) +
5736             BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod);
5737
5738         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5739             BCE_VERBOSE_CTX);
5740 }
5741
5742
5743 /****************************************************************************/
5744 /* Free memory and clear the RX data structures.                            */
5745 /*                                                                          */
5746 /* Returns:                                                                 */
5747 /*   Nothing.                                                               */
5748 /****************************************************************************/
5749 static void
5750 bce_free_pg_chain(struct bce_softc *sc)
5751 {
5752         int i;
5753
5754         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5755
5756         /* Free any mbufs still in the mbuf page chain. */
5757         for (i = 0; i < TOTAL_PG_BD; i++) {
5758                 if (sc->pg_mbuf_ptr[i] != NULL) {
5759                         if (sc->pg_mbuf_map[i] != NULL)
5760                                 bus_dmamap_sync(sc->pg_mbuf_tag,
5761                                     sc->pg_mbuf_map[i],
5762                                     BUS_DMASYNC_POSTREAD);
5763                         m_freem(sc->pg_mbuf_ptr[i]);
5764                         sc->pg_mbuf_ptr[i] = NULL;
5765                         DBRUN(sc->debug_pg_mbuf_alloc--);
5766                 }
5767         }
5768
5769         /* Clear each page chain pages. */
5770         for (i = 0; i < PG_PAGES; i++)
5771                 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
5772
5773         sc->free_pg_bd = sc->max_pg_bd;
5774
5775         /* Check if we lost any mbufs in the process. */
5776         DBRUNIF((sc->debug_pg_mbuf_alloc),
5777             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
5778             __FUNCTION__, sc->debug_pg_mbuf_alloc));
5779
5780         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5781 }
5782 #endif /* BCE_JUMBO_HDRSPLIT */
5783
5784
5785 /****************************************************************************/
5786 /* Set media options.                                                       */
5787 /*                                                                          */
5788 /* Returns:                                                                 */
5789 /*   0 for success, positive value for failure.                             */
5790 /****************************************************************************/
5791 static int
5792 bce_ifmedia_upd(struct ifnet *ifp)
5793 {
5794         struct bce_softc *sc = ifp->if_softc;
5795         int error;
5796
5797         DBENTER(BCE_VERBOSE);
5798
5799         BCE_LOCK(sc);
5800         error = bce_ifmedia_upd_locked(ifp);
5801         BCE_UNLOCK(sc);
5802
5803         DBEXIT(BCE_VERBOSE);
5804         return (error);
5805 }
5806
5807
5808 /****************************************************************************/
5809 /* Set media options.                                                       */
5810 /*                                                                          */
5811 /* Returns:                                                                 */
5812 /*   Nothing.                                                               */
5813 /****************************************************************************/
5814 static int
5815 bce_ifmedia_upd_locked(struct ifnet *ifp)
5816 {
5817         struct bce_softc *sc = ifp->if_softc;
5818         struct mii_data *mii;
5819         int error;
5820
5821         DBENTER(BCE_VERBOSE_PHY);
5822
5823         error = 0;
5824         BCE_LOCK_ASSERT(sc);
5825
5826         mii = device_get_softc(sc->bce_miibus);
5827
5828         /* Make sure the MII bus has been enumerated. */
5829         if (mii) {
5830                 sc->bce_link_up = FALSE;
5831                 if (mii->mii_instance) {
5832                         struct mii_softc *miisc;
5833
5834                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5835                             mii_phy_reset(miisc);
5836                 }
5837                 error = mii_mediachg(mii);
5838         }
5839
5840         DBEXIT(BCE_VERBOSE_PHY);
5841         return (error);
5842 }
5843
5844
5845 /****************************************************************************/
5846 /* Reports current media status.                                            */
5847 /*                                                                          */
5848 /* Returns:                                                                 */
5849 /*   Nothing.                                                               */
5850 /****************************************************************************/
5851 static void
5852 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
5853 {
5854         struct bce_softc *sc = ifp->if_softc;
5855         struct mii_data *mii;
5856
5857         DBENTER(BCE_VERBOSE_PHY);
5858
5859         BCE_LOCK(sc);
5860
5861         mii = device_get_softc(sc->bce_miibus);
5862
5863         mii_pollstat(mii);
5864         ifmr->ifm_active = mii->mii_media_active;
5865         ifmr->ifm_status = mii->mii_media_status;
5866
5867         BCE_UNLOCK(sc);
5868
5869         DBEXIT(BCE_VERBOSE_PHY);
5870 }
5871
5872
5873 /****************************************************************************/
5874 /* Handles PHY generated interrupt events.                                  */
5875 /*                                                                          */
5876 /* Returns:                                                                 */
5877 /*   Nothing.                                                               */
5878 /****************************************************************************/
5879 static void
5880 bce_phy_intr(struct bce_softc *sc)
5881 {
5882         u32 new_link_state, old_link_state;
5883
5884         DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
5885
5886         DBRUN(sc->phy_interrupts++);
5887
5888         new_link_state = sc->status_block->status_attn_bits &
5889             STATUS_ATTN_BITS_LINK_STATE;
5890         old_link_state = sc->status_block->status_attn_bits_ack &
5891             STATUS_ATTN_BITS_LINK_STATE;
5892
5893         /* Handle any changes if the link state has changed. */
5894         if (new_link_state != old_link_state) {
5895
5896                 /* Update the status_attn_bits_ack field. */
5897                 if (new_link_state) {
5898                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
5899                             STATUS_ATTN_BITS_LINK_STATE);
5900                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n",
5901                             __FUNCTION__);
5902                 }
5903                 else {
5904                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
5905                             STATUS_ATTN_BITS_LINK_STATE);
5906                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
5907                             __FUNCTION__);
5908                 }
5909
5910                 /*
5911                  * Assume link is down and allow
5912                  * tick routine to update the state
5913                  * based on the actual media state.
5914                  */
5915                 sc->bce_link_up = FALSE;
5916                 callout_stop(&sc->bce_tick_callout);
5917                 bce_tick(sc);
5918         }
5919
5920         /* Acknowledge the link change interrupt. */
5921         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
5922
5923         DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
5924 }
5925
5926
5927 /****************************************************************************/
5928 /* Reads the receive consumer value from the status block (skipping over    */
5929 /* chain page pointer if necessary).                                        */
5930 /*                                                                          */
5931 /* Returns:                                                                 */
5932 /*   hw_cons                                                                */
5933 /****************************************************************************/
5934 static inline u16
5935 bce_get_hw_rx_cons(struct bce_softc *sc)
5936 {
5937         u16 hw_cons;
5938
5939         rmb();
5940         hw_cons = sc->status_block->status_rx_quick_consumer_index0;
5941         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
5942                 hw_cons++;
5943
5944         return hw_cons;
5945 }
5946
5947 /****************************************************************************/
5948 /* Handles received frame interrupt events.                                 */
5949 /*                                                                          */
5950 /* Returns:                                                                 */
5951 /*   Nothing.                                                               */
5952 /****************************************************************************/
5953 static void
5954 bce_rx_intr(struct bce_softc *sc)
5955 {
5956         struct ifnet *ifp = sc->bce_ifp;
5957         struct l2_fhdr *l2fhdr;
5958         struct ether_vlan_header *vh;
5959         unsigned int pkt_len;
5960         u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
5961         u32 status;
5962 #ifdef BCE_JUMBO_HDRSPLIT
5963         unsigned int rem_len;
5964         u16 sw_pg_cons, sw_pg_cons_idx;
5965 #endif
5966
5967         DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
5968         DBRUN(sc->interrupts_rx++);
5969         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
5970             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
5971             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
5972
5973         /* Prepare the RX chain pages to be accessed by the host CPU. */
5974         for (int i = 0; i < RX_PAGES; i++)
5975                 bus_dmamap_sync(sc->rx_bd_chain_tag,
5976                     sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
5977
5978 #ifdef BCE_JUMBO_HDRSPLIT
5979         /* Prepare the page chain pages to be accessed by the host CPU. */
5980         for (int i = 0; i < PG_PAGES; i++)
5981                 bus_dmamap_sync(sc->pg_bd_chain_tag,
5982                     sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
5983 #endif
5984
5985         /* Get the hardware's view of the RX consumer index. */
5986         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
5987
5988         /* Get working copies of the driver's view of the consumer indices. */
5989         sw_rx_cons = sc->rx_cons;
5990
5991 #ifdef BCE_JUMBO_HDRSPLIT
5992         sw_pg_cons = sc->pg_cons;
5993 #endif
5994
5995         /* Update some debug statistics counters */
5996         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5997             sc->rx_low_watermark = sc->free_rx_bd);
5998         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
5999             sc->rx_empty_count++);
6000
6001         /* Scan through the receive chain as long as there is work to do */
6002         /* ToDo: Consider setting a limit on the number of packets processed. */
6003         rmb();
6004         while (sw_rx_cons != hw_rx_cons) {
6005                 struct mbuf *m0;
6006
6007                 /* Convert the producer/consumer indices to an actual rx_bd index. */
6008                 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
6009
6010                 /* Unmap the mbuf from DMA space. */
6011                 bus_dmamap_sync(sc->rx_mbuf_tag,
6012                     sc->rx_mbuf_map[sw_rx_cons_idx],
6013                     BUS_DMASYNC_POSTREAD);
6014                 bus_dmamap_unload(sc->rx_mbuf_tag,
6015                     sc->rx_mbuf_map[sw_rx_cons_idx]);
6016
6017                 /* Remove the mbuf from the RX chain. */
6018                 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
6019                 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
6020                 DBRUN(sc->debug_rx_mbuf_alloc--);
6021                 sc->free_rx_bd++;
6022
6023                 if(m0 == NULL) {
6024                         DBPRINT(sc, BCE_EXTREME_RECV,
6025                             "%s(): Oops! Empty mbuf pointer "
6026                             "found in sc->rx_mbuf_ptr[0x%04X]!\n",
6027                             __FUNCTION__, sw_rx_cons_idx);
6028                         goto bce_rx_int_next_rx;
6029                 }
6030
6031                 /*
6032                  * Frames received on the NetXteme II are prepended
6033                  * with an l2_fhdr structure which provides status
6034                  * information about the received frame (including
6035                  * VLAN tags and checksum info).  The frames are
6036                  * also automatically adjusted to align the IP
6037                  * header (i.e. two null bytes are inserted before
6038                  * the Ethernet header).  As a result the data
6039                  * DMA'd by the controller into the mbuf looks
6040                  * like this:
6041                  *
6042                  * +---------+-----+---------------------+-----+
6043                  * | l2_fhdr | pad | packet data         | FCS |
6044                  * +---------+-----+---------------------+-----+
6045                  *
6046                  * The l2_fhdr needs to be checked and skipped and
6047                  * the FCS needs to be stripped before sending the
6048                  * packet up the stack.
6049                  */
6050                 l2fhdr  = mtod(m0, struct l2_fhdr *);
6051
6052                 /* Get the packet data + FCS length and the status. */
6053                 pkt_len = l2fhdr->l2_fhdr_pkt_len;
6054                 status  = l2fhdr->l2_fhdr_status;
6055
6056                 /*
6057                  * Skip over the l2_fhdr and pad, resulting in the
6058                  * following data in the mbuf:
6059                  * +---------------------+-----+
6060                  * | packet data         | FCS |
6061                  * +---------------------+-----+
6062                  */
6063                 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
6064
6065 #ifdef BCE_JUMBO_HDRSPLIT
6066                 /*
6067                  * Check whether the received frame fits in a single
6068                  * mbuf or not (i.e. packet data + FCS <=
6069                  * sc->rx_bd_mbuf_data_len bytes).
6070                  */
6071                 if (pkt_len > m0->m_len) {
6072                         /*
6073                          * The received frame is larger than a single mbuf.
6074                          * If the frame was a TCP frame then only the TCP
6075                          * header is placed in the mbuf, the remaining
6076                          * payload (including FCS) is placed in the page
6077                          * chain, the SPLIT flag is set, and the header
6078                          * length is placed in the IP checksum field.
6079                          * If the frame is not a TCP frame then the mbuf
6080                          * is filled and the remaining bytes are placed
6081                          * in the page chain.
6082                          */
6083
6084                         DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large "
6085                             "packet.\n", __FUNCTION__);
6086
6087                         /*
6088                          * When the page chain is enabled and the TCP
6089                          * header has been split from the TCP payload,
6090                          * the ip_xsum structure will reflect the length
6091                          * of the TCP header, not the IP checksum.  Set
6092                          * the packet length of the mbuf accordingly.
6093                          */
6094                         if (status & L2_FHDR_STATUS_SPLIT)
6095                                 m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
6096
6097                         rem_len = pkt_len - m0->m_len;
6098
6099                         /* Pull mbufs off the page chain for the remaining data. */
6100                         while (rem_len > 0) {
6101                                 struct mbuf *m_pg;
6102
6103                                 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
6104
6105                                 /* Remove the mbuf from the page chain. */
6106                                 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
6107                                 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
6108                                 DBRUN(sc->debug_pg_mbuf_alloc--);
6109                                 sc->free_pg_bd++;
6110
6111                                 /* Unmap the page chain mbuf from DMA space. */
6112                                 bus_dmamap_sync(sc->pg_mbuf_tag,
6113                                     sc->pg_mbuf_map[sw_pg_cons_idx],
6114                                     BUS_DMASYNC_POSTREAD);
6115                                 bus_dmamap_unload(sc->pg_mbuf_tag,
6116                                     sc->pg_mbuf_map[sw_pg_cons_idx]);
6117
6118                                 /* Adjust the mbuf length. */
6119                                 if (rem_len < m_pg->m_len) {
6120                                         /* The mbuf chain is complete. */
6121                                         m_pg->m_len = rem_len;
6122                                         rem_len = 0;
6123                                 } else {
6124                                         /* More packet data is waiting. */
6125                                         rem_len -= m_pg->m_len;
6126                                 }
6127
6128                                 /* Concatenate the mbuf cluster to the mbuf. */
6129                                 m_cat(m0, m_pg);
6130
6131                                 sw_pg_cons = NEXT_PG_BD(sw_pg_cons);
6132                         }
6133
6134                         /* Set the total packet length. */
6135                         m0->m_pkthdr.len = pkt_len;
6136
6137                 } else {
6138                         /*
6139                          * The received packet is small and fits in a
6140                          * single mbuf (i.e. the l2_fhdr + pad + packet +
6141                          * FCS <= MHLEN).  In other words, the packet is
6142                          * 154 bytes or less in size.
6143                          */
6144
6145                         DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small "
6146                             "packet.\n", __FUNCTION__);
6147
6148                         /* Set the total packet length. */
6149                         m0->m_pkthdr.len = m0->m_len = pkt_len;
6150                 }
6151 #else
6152                 /* Set the total packet length. */
6153                 m0->m_pkthdr.len = m0->m_len = pkt_len;
6154 #endif
6155
6156                 /* Remove the trailing Ethernet FCS. */
6157                 m_adj(m0, -ETHER_CRC_LEN);
6158
6159                 /* Check that the resulting mbuf chain is valid. */
6160                 DBRUN(m_sanity(m0, FALSE));
6161                 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
6162                     (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
6163                      BCE_PRINTF("Invalid Ethernet frame size!\n");
6164                      m_print(m0, 128));
6165
6166                 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control),
6167                     sc->l2fhdr_error_sim_count++;
6168                     status = status | L2_FHDR_ERRORS_PHY_DECODE);
6169
6170                 /* Check the received frame for errors. */
6171                 if (status & (L2_FHDR_ERRORS_BAD_CRC |
6172                     L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
6173                     L2_FHDR_ERRORS_TOO_SHORT  | L2_FHDR_ERRORS_GIANT_FRAME)) {
6174
6175                         /* Log the error and release the mbuf. */
6176                         ifp->if_ierrors++;
6177                         sc->l2fhdr_error_count++;
6178
6179                         m_freem(m0);
6180                         m0 = NULL;
6181                         goto bce_rx_int_next_rx;
6182                 }
6183
6184                 /* Send the packet to the appropriate interface. */
6185                 m0->m_pkthdr.rcvif = ifp;
6186
6187                 /* Assume no hardware checksum. */
6188                 m0->m_pkthdr.csum_flags = 0;
6189
6190                 /* Validate the checksum if offload enabled. */
6191                 if (ifp->if_capenable & IFCAP_RXCSUM) {
6192
6193                         /* Check for an IP datagram. */
6194                         if (!(status & L2_FHDR_STATUS_SPLIT) &&
6195                             (status & L2_FHDR_STATUS_IP_DATAGRAM)) {
6196                                 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
6197                                 DBRUN(sc->csum_offload_ip++);
6198                                 /* Check if the IP checksum is valid. */
6199                                 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
6200                                         m0->m_pkthdr.csum_flags |=
6201                                             CSUM_IP_VALID;
6202                         }
6203
6204                         /* Check for a valid TCP/UDP frame. */
6205                         if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
6206                             L2_FHDR_STATUS_UDP_DATAGRAM)) {
6207
6208                                 /* Check for a good TCP/UDP checksum. */
6209                                 if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
6210                                     L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
6211                                         DBRUN(sc->csum_offload_tcp_udp++);
6212                                         m0->m_pkthdr.csum_data =
6213                                             l2fhdr->l2_fhdr_tcp_udp_xsum;
6214                                         m0->m_pkthdr.csum_flags |=
6215                                             (CSUM_DATA_VALID
6216                                             | CSUM_PSEUDO_HDR);
6217                                 }
6218                         }
6219                 }
6220
6221                 /* Attach the VLAN tag. */
6222                 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
6223                         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
6224 #if __FreeBSD_version < 700000
6225                                 VLAN_INPUT_TAG(ifp, m0,
6226                                     l2fhdr->l2_fhdr_vlan_tag, continue);
6227 #else
6228                                 m0->m_pkthdr.ether_vtag =
6229                                     l2fhdr->l2_fhdr_vlan_tag;
6230                                 m0->m_flags |= M_VLANTAG;
6231 #endif
6232                         } else {
6233                                 /*
6234                                  * bce(4) controllers can't disable VLAN
6235                                  * tag stripping if management firmware
6236                                  * (ASF/IPMI/UMP) is running. So we always
6237                                  * strip VLAN tag and manually reconstruct
6238                                  * the VLAN frame by appending stripped
6239                                  * VLAN tag in driver if VLAN tag stripping
6240                                  * was disabled.
6241                                  *
6242                                  * TODO: LLC SNAP handling.
6243                                  */
6244                                 bcopy(mtod(m0, uint8_t *),
6245                                     mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN,
6246                                     ETHER_ADDR_LEN * 2);
6247                                 m0->m_data -= ETHER_VLAN_ENCAP_LEN;
6248                                 vh = mtod(m0, struct ether_vlan_header *);
6249                                 vh->evl_encap_proto = htons(ETHERTYPE_VLAN);
6250                                 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag);
6251                                 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN;
6252                                 m0->m_len += ETHER_VLAN_ENCAP_LEN;
6253                         }
6254                 }
6255
6256                 /* Increment received packet statistics. */
6257                 ifp->if_ipackets++;
6258
6259 bce_rx_int_next_rx:
6260                 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
6261
6262                 /* If we have a packet, pass it up the stack */
6263                 if (m0) {
6264                         /* Make sure we don't lose our place when we release the lock. */
6265                         sc->rx_cons = sw_rx_cons;
6266 #ifdef BCE_JUMBO_HDRSPLIT
6267                         sc->pg_cons = sw_pg_cons;
6268 #endif
6269
6270                         BCE_UNLOCK(sc);
6271                         (*ifp->if_input)(ifp, m0);
6272                         BCE_LOCK(sc);
6273
6274                         /* Recover our place. */
6275                         sw_rx_cons = sc->rx_cons;
6276 #ifdef BCE_JUMBO_HDRSPLIT
6277                         sw_pg_cons = sc->pg_cons;
6278 #endif
6279                 }
6280
6281                 /* Refresh hw_cons to see if there's new work */
6282                 if (sw_rx_cons == hw_rx_cons)
6283                         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6284         }
6285
6286 #ifdef BCE_JUMBO_HDRSPLIT
6287         /* No new packets.  Refill the page chain. */
6288         sc->pg_cons = sw_pg_cons;
6289         bce_fill_pg_chain(sc);
6290 #endif
6291
6292         /* No new packets.  Refill the RX chain. */
6293         sc->rx_cons = sw_rx_cons;
6294         bce_fill_rx_chain(sc);
6295
6296         /* Prepare the page chain pages to be accessed by the NIC. */
6297         for (int i = 0; i < RX_PAGES; i++)
6298                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6299                     sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6300
6301 #ifdef BCE_JUMBO_HDRSPLIT
6302         for (int i = 0; i < PG_PAGES; i++)
6303                 bus_dmamap_sync(sc->pg_bd_chain_tag,
6304                     sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6305 #endif
6306
6307         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
6308             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6309             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6310         DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6311 }
6312
6313
6314 /****************************************************************************/
6315 /* Reads the transmit consumer value from the status block (skipping over   */
6316 /* chain page pointer if necessary).                                        */
6317 /*                                                                          */
6318 /* Returns:                                                                 */
6319 /*   hw_cons                                                                */
6320 /****************************************************************************/
6321 static inline u16
6322 bce_get_hw_tx_cons(struct bce_softc *sc)
6323 {
6324         u16 hw_cons;
6325
6326         mb();
6327         hw_cons = sc->status_block->status_tx_quick_consumer_index0;
6328         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
6329                 hw_cons++;
6330
6331         return hw_cons;
6332 }
6333
6334
6335 /****************************************************************************/
6336 /* Handles transmit completion interrupt events.                            */
6337 /*                                                                          */
6338 /* Returns:                                                                 */
6339 /*   Nothing.                                                               */
6340 /****************************************************************************/
6341 static void
6342 bce_tx_intr(struct bce_softc *sc)
6343 {
6344         struct ifnet *ifp = sc->bce_ifp;
6345         u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
6346
6347         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6348         DBRUN(sc->interrupts_tx++);
6349         DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6350             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6351             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6352
6353         BCE_LOCK_ASSERT(sc);
6354
6355         /* Get the hardware's view of the TX consumer index. */
6356         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6357         sw_tx_cons = sc->tx_cons;
6358
6359         /* Prevent speculative reads of the status block. */
6360         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6361             BUS_SPACE_BARRIER_READ);
6362
6363         /* Cycle through any completed TX chain page entries. */
6364         while (sw_tx_cons != hw_tx_cons) {
6365 #ifdef BCE_DEBUG
6366                 struct tx_bd *txbd = NULL;
6367 #endif
6368                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
6369
6370                 DBPRINT(sc, BCE_INFO_SEND,
6371                     "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
6372                     "sw_tx_chain_cons = 0x%04X\n",
6373                     __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
6374
6375                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
6376                     BCE_PRINTF("%s(%d): TX chain consumer out of range! "
6377                     " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
6378                     (int) MAX_TX_BD);
6379                     bce_breakpoint(sc));
6380
6381                 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
6382                     [TX_IDX(sw_tx_chain_cons)]);
6383
6384                 DBRUNIF((txbd == NULL),
6385                     BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
6386                     __FILE__, __LINE__, sw_tx_chain_cons);
6387                     bce_breakpoint(sc));
6388
6389                 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
6390                     bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
6391
6392                 /*
6393                  * Free the associated mbuf. Remember
6394                  * that only the last tx_bd of a packet
6395                  * has an mbuf pointer and DMA map.
6396                  */
6397                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
6398
6399                         /* Validate that this is the last tx_bd. */
6400                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
6401                             BCE_PRINTF("%s(%d): tx_bd END flag not set but "
6402                             "txmbuf == NULL!\n", __FILE__, __LINE__);
6403                             bce_breakpoint(sc));
6404
6405                         DBRUNMSG(BCE_INFO_SEND,
6406                             BCE_PRINTF("%s(): Unloading map/freeing mbuf "
6407                             "from tx_bd[0x%04X]\n", __FUNCTION__,
6408                             sw_tx_chain_cons));
6409
6410                         /* Unmap the mbuf. */
6411                         bus_dmamap_unload(sc->tx_mbuf_tag,
6412                             sc->tx_mbuf_map[sw_tx_chain_cons]);
6413
6414                         /* Free the mbuf. */
6415                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
6416                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
6417                         DBRUN(sc->debug_tx_mbuf_alloc--);
6418
6419                         ifp->if_opackets++;
6420                 }
6421
6422                 sc->used_tx_bd--;
6423                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
6424
6425                 /* Refresh hw_cons to see if there's new work. */
6426                 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6427
6428                 /* Prevent speculative reads of the status block. */
6429                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6430                     BUS_SPACE_BARRIER_READ);
6431         }
6432
6433         /* Clear the TX timeout timer. */
6434         sc->watchdog_timer = 0;
6435
6436         /* Clear the tx hardware queue full flag. */
6437         if (sc->used_tx_bd < sc->max_tx_bd) {
6438                 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
6439                     DBPRINT(sc, BCE_INFO_SEND,
6440                     "%s(): Open TX chain! %d/%d (used/total)\n",
6441                     __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
6442                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
6443         }
6444
6445         sc->tx_cons = sw_tx_cons;
6446
6447         DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
6448             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6449             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6450         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6451 }
6452
6453
6454 /****************************************************************************/
6455 /* Disables interrupt generation.                                           */
6456 /*                                                                          */
6457 /* Returns:                                                                 */
6458 /*   Nothing.                                                               */
6459 /****************************************************************************/
6460 static void
6461 bce_disable_intr(struct bce_softc *sc)
6462 {
6463         DBENTER(BCE_VERBOSE_INTR);
6464
6465         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
6466         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
6467
6468         DBEXIT(BCE_VERBOSE_INTR);
6469 }
6470
6471
6472 /****************************************************************************/
6473 /* Enables interrupt generation.                                            */
6474 /*                                                                          */
6475 /* Returns:                                                                 */
6476 /*   Nothing.                                                               */
6477 /****************************************************************************/
6478 static void
6479 bce_enable_intr(struct bce_softc *sc, int coal_now)
6480 {
6481         DBENTER(BCE_VERBOSE_INTR);
6482
6483         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
6484             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
6485             BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
6486
6487         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
6488             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
6489
6490         /* Force an immediate interrupt (whether there is new data or not). */
6491         if (coal_now)
6492                 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
6493
6494         DBEXIT(BCE_VERBOSE_INTR);
6495 }
6496
6497
6498 /****************************************************************************/
6499 /* Handles controller initialization.                                       */
6500 /*                                                                          */
6501 /* Returns:                                                                 */
6502 /*   Nothing.                                                               */
6503 /****************************************************************************/
6504 static void
6505 bce_init_locked(struct bce_softc *sc)
6506 {
6507         struct ifnet *ifp;
6508         u32 ether_mtu = 0;
6509
6510         DBENTER(BCE_VERBOSE_RESET);
6511
6512         BCE_LOCK_ASSERT(sc);
6513
6514         ifp = sc->bce_ifp;
6515
6516         /* Check if the driver is still running and bail out if it is. */
6517         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
6518                 goto bce_init_locked_exit;
6519
6520         bce_stop(sc);
6521
6522         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
6523                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
6524                     __FILE__, __LINE__);
6525                 goto bce_init_locked_exit;
6526         }
6527
6528         if (bce_chipinit(sc)) {
6529                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
6530                     __FILE__, __LINE__);
6531                 goto bce_init_locked_exit;
6532         }
6533
6534         if (bce_blockinit(sc)) {
6535                 BCE_PRINTF("%s(%d): Block initialization failed!\n",
6536                     __FILE__, __LINE__);
6537                 goto bce_init_locked_exit;
6538         }
6539
6540         /* Load our MAC address. */
6541         bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
6542         bce_set_mac_addr(sc);
6543
6544         /*
6545          * Calculate and program the hardware Ethernet MTU
6546          * size. Be generous on the receive if we have room.
6547          */
6548 #ifdef BCE_JUMBO_HDRSPLIT
6549         if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len +
6550             sc->pg_bd_mbuf_alloc_size))
6551                 ether_mtu = sc->rx_bd_mbuf_data_len +
6552                     sc->pg_bd_mbuf_alloc_size;
6553 #else
6554         if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
6555                 ether_mtu = sc->rx_bd_mbuf_data_len;
6556 #endif
6557         else
6558                 ether_mtu = ifp->if_mtu;
6559
6560         ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
6561
6562         DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n",
6563             __FUNCTION__, ether_mtu);
6564
6565         /* Program the mtu, enabling jumbo frame support if necessary. */
6566         if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
6567                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
6568                     min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
6569                     BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
6570         else
6571                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
6572
6573         DBPRINT(sc, BCE_INFO_LOAD,
6574             "%s(): rx_bd_mbuf_alloc_size = %d, rx_bce_mbuf_data_len = %d, "
6575             "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
6576             sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
6577             sc->rx_bd_mbuf_align_pad);
6578
6579         /* Program appropriate promiscuous/multicast filtering. */
6580         bce_set_rx_mode(sc);
6581
6582 #ifdef BCE_JUMBO_HDRSPLIT
6583         DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n",
6584             __FUNCTION__, sc->pg_bd_mbuf_alloc_size);
6585
6586         /* Init page buffer descriptor chain. */
6587         bce_init_pg_chain(sc);
6588 #endif
6589
6590         /* Init RX buffer descriptor chain. */
6591         bce_init_rx_chain(sc);
6592
6593         /* Init TX buffer descriptor chain. */
6594         bce_init_tx_chain(sc);
6595
6596         /* Enable host interrupts. */
6597         bce_enable_intr(sc, 1);
6598
6599         bce_ifmedia_upd_locked(ifp);
6600
6601         /* Let the OS know the driver is up and running. */
6602         ifp->if_drv_flags |= IFF_DRV_RUNNING;
6603         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
6604
6605         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
6606
6607 bce_init_locked_exit:
6608         DBEXIT(BCE_VERBOSE_RESET);
6609 }
6610
6611
6612 /****************************************************************************/
6613 /* Initialize the controller just enough so that any management firmware    */
6614 /* running on the device will continue to operate correctly.                */
6615 /*                                                                          */
6616 /* Returns:                                                                 */
6617 /*   Nothing.                                                               */
6618 /****************************************************************************/
6619 static void
6620 bce_mgmt_init_locked(struct bce_softc *sc)
6621 {
6622         struct ifnet *ifp;
6623
6624         DBENTER(BCE_VERBOSE_RESET);
6625
6626         BCE_LOCK_ASSERT(sc);
6627
6628         /* Bail out if management firmware is not running. */
6629         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
6630                 DBPRINT(sc, BCE_VERBOSE_SPECIAL,
6631                     "No management firmware running...\n");
6632                 goto bce_mgmt_init_locked_exit;
6633         }
6634
6635         ifp = sc->bce_ifp;
6636
6637         /* Enable all critical blocks in the MAC. */
6638         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
6639         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
6640         DELAY(20);
6641
6642         bce_ifmedia_upd_locked(ifp);
6643
6644 bce_mgmt_init_locked_exit:
6645         DBEXIT(BCE_VERBOSE_RESET);
6646 }
6647
6648
6649 /****************************************************************************/
6650 /* Handles controller initialization when called from an unlocked routine.  */
6651 /*                                                                          */
6652 /* Returns:                                                                 */
6653 /*   Nothing.                                                               */
6654 /****************************************************************************/
6655 static void
6656 bce_init(void *xsc)
6657 {
6658         struct bce_softc *sc = xsc;
6659
6660         DBENTER(BCE_VERBOSE_RESET);
6661
6662         BCE_LOCK(sc);
6663         bce_init_locked(sc);
6664         BCE_UNLOCK(sc);
6665
6666         DBEXIT(BCE_VERBOSE_RESET);
6667 }
6668
6669
6670 /****************************************************************************/
6671 /* Modifies an mbuf for TSO on the hardware.                                */
6672 /*                                                                          */
6673 /* Returns:                                                                 */
6674 /*   Pointer to a modified mbuf.                                            */
6675 /****************************************************************************/
6676 static struct mbuf *
6677 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags)
6678 {
6679         struct mbuf *m;
6680         struct ether_header *eh;
6681         struct ip *ip;
6682         struct tcphdr *th;
6683         u16 etype;
6684         int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0;
6685
6686         DBRUN(sc->tso_frames_requested++);
6687
6688         /* Controller may modify mbuf chains. */
6689         if (M_WRITABLE(*m_head) == 0) {
6690                 m = m_dup(*m_head, M_DONTWAIT);
6691                 m_freem(*m_head);
6692                 if (m == NULL) {
6693                         sc->mbuf_alloc_failed_count++;
6694                         *m_head = NULL;
6695                         return (NULL);
6696                 }
6697                 *m_head = m;
6698         }
6699
6700         /*
6701          * For TSO the controller needs two pieces of info,
6702          * the MSS and the IP+TCP options length.
6703          */
6704         m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip));
6705         if (m == NULL) {
6706                 *m_head = NULL;
6707                 return (NULL);
6708         }
6709         eh = mtod(m, struct ether_header *);
6710         etype = ntohs(eh->ether_type);
6711
6712         /* Check for supported TSO Ethernet types (only IPv4 for now) */
6713         switch (etype) {
6714         case ETHERTYPE_IP:
6715                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
6716                 /* TSO only supported for TCP protocol. */
6717                 if (ip->ip_p != IPPROTO_TCP) {
6718                         BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
6719                             __FILE__, __LINE__);
6720                         m_freem(*m_head);
6721                         *m_head = NULL;
6722                         return (NULL);
6723                 }
6724
6725                 /* Get IP header length in bytes (min 20) */
6726                 ip_hlen = ip->ip_hl << 2;
6727                 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen +
6728                     sizeof(struct tcphdr));
6729                 if (m == NULL) {
6730                         *m_head = NULL;
6731                         return (NULL);
6732                 }
6733
6734                 /* Get the TCP header length in bytes (min 20) */
6735                 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
6736                 tcp_hlen = (th->th_off << 2);
6737
6738                 /* Make sure all IP/TCP options live in the same buffer. */
6739                 m = m_pullup(*m_head,  sizeof(struct ether_header)+ ip_hlen +
6740                     tcp_hlen);
6741                 if (m == NULL) {
6742                         *m_head = NULL;
6743                         return (NULL);
6744                 }
6745
6746                 /* IP header length and checksum will be calc'd by hardware */
6747                 ip_len = ip->ip_len;
6748                 ip->ip_len = 0;
6749                 ip->ip_sum = 0;
6750                 break;
6751         case ETHERTYPE_IPV6:
6752                 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n",
6753                     __FILE__, __LINE__);
6754                 m_freem(*m_head);
6755                 *m_head = NULL;
6756                 return (NULL);
6757                 /* NOT REACHED */
6758         default:
6759                 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
6760                     __FILE__, __LINE__);
6761                 m_freem(*m_head);
6762                 *m_head = NULL;
6763                 return (NULL);
6764         }
6765
6766         hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen;
6767
6768         DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, "
6769             "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
6770             __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen,
6771             tcp_hlen, ip_len);
6772
6773         /* Set the LSO flag in the TX BD */
6774         *flags |= TX_BD_FLAGS_SW_LSO;
6775
6776         /* Set the length of IP + TCP options (in 32 bit words) */
6777         *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) -
6778             sizeof(struct tcphdr)) >> 2) << 8);
6779
6780         DBRUN(sc->tso_frames_completed++);
6781         return (*m_head);
6782 }
6783
6784
6785 /****************************************************************************/
6786 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
6787 /* memory visible to the controller.                                        */
6788 /*                                                                          */
6789 /* Returns:                                                                 */
6790 /*   0 for success, positive value for failure.                             */
6791 /* Modified:                                                                */
6792 /*   m_head: May be set to NULL if MBUF is excessively fragmented.          */
6793 /****************************************************************************/
6794 static int
6795 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head)
6796 {
6797         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
6798         bus_dmamap_t map;
6799         struct tx_bd *txbd = NULL;
6800         struct mbuf *m0;
6801         u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0;
6802         u32 prod_bseq;
6803
6804 #ifdef BCE_DEBUG
6805         u16 debug_prod;
6806 #endif
6807
6808         int i, error, nsegs, rc = 0;
6809
6810         DBENTER(BCE_VERBOSE_SEND);
6811
6812         /* Make sure we have room in the TX chain. */
6813         if (sc->used_tx_bd >= sc->max_tx_bd)
6814                 goto bce_tx_encap_exit;
6815
6816         /* Transfer any checksum offload flags to the bd. */
6817         m0 = *m_head;
6818         if (m0->m_pkthdr.csum_flags) {
6819                 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
6820                         m0 = bce_tso_setup(sc, m_head, &flags);
6821                         if (m0 == NULL) {
6822                                 DBRUN(sc->tso_frames_failed++);
6823                                 goto bce_tx_encap_exit;
6824                         }
6825                         mss = htole16(m0->m_pkthdr.tso_segsz);
6826                 } else {
6827                         if (m0->m_pkthdr.csum_flags & CSUM_IP)
6828                                 flags |= TX_BD_FLAGS_IP_CKSUM;
6829                         if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
6830                                 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6831                 }
6832         }
6833
6834         /* Transfer any VLAN tags to the bd. */
6835         if (m0->m_flags & M_VLANTAG) {
6836                 flags |= TX_BD_FLAGS_VLAN_TAG;
6837                 vlan_tag = m0->m_pkthdr.ether_vtag;
6838         }
6839
6840         /* Map the mbuf into DMAable memory. */
6841         prod = sc->tx_prod;
6842         chain_prod = TX_CHAIN_IDX(prod);
6843         map = sc->tx_mbuf_map[chain_prod];
6844
6845         /* Map the mbuf into our DMA address space. */
6846         error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
6847             segs, &nsegs, BUS_DMA_NOWAIT);
6848
6849         /* Check if the DMA mapping was successful */
6850         if (error == EFBIG) {
6851                 sc->mbuf_frag_count++;
6852
6853                 /* Try to defrag the mbuf. */
6854                 m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS);
6855                 if (m0 == NULL) {
6856                         /* Defrag was unsuccessful */
6857                         m_freem(*m_head);
6858                         *m_head = NULL;
6859                         sc->mbuf_alloc_failed_count++;
6860                         rc = ENOBUFS;
6861                         goto bce_tx_encap_exit;
6862                 }
6863
6864                 /* Defrag was successful, try mapping again */
6865                 *m_head = m0;
6866                 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag,
6867                     map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
6868
6869                 /* Still getting an error after a defrag. */
6870                 if (error == ENOMEM) {
6871                         /* Insufficient DMA buffers available. */
6872                         sc->dma_map_addr_tx_failed_count++;
6873                         rc = error;
6874                         goto bce_tx_encap_exit;
6875                 } else if (error != 0) {
6876                         /* Release it and return an error. */
6877                         BCE_PRINTF("%s(%d): Unknown error mapping mbuf into "
6878                             "TX chain!\n", __FILE__, __LINE__);
6879                         m_freem(m0);
6880                         *m_head = NULL;
6881                         sc->dma_map_addr_tx_failed_count++;
6882                         rc = ENOBUFS;
6883                         goto bce_tx_encap_exit;
6884                 }
6885         } else if (error == ENOMEM) {
6886                 /* Insufficient DMA buffers available. */
6887                 sc->dma_map_addr_tx_failed_count++;
6888                 rc = error;
6889                 goto bce_tx_encap_exit;
6890         } else if (error != 0) {
6891                 m_freem(m0);
6892                 *m_head = NULL;
6893                 sc->dma_map_addr_tx_failed_count++;
6894                 rc = error;
6895                 goto bce_tx_encap_exit;
6896         }
6897
6898         /* Make sure there's room in the chain */
6899         if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
6900                 bus_dmamap_unload(sc->tx_mbuf_tag, map);
6901                 rc = ENOBUFS;
6902                 goto bce_tx_encap_exit;
6903         }
6904
6905         /* prod points to an empty tx_bd at this point. */
6906         prod_bseq  = sc->tx_prod_bseq;
6907
6908 #ifdef BCE_DEBUG
6909         debug_prod = chain_prod;
6910 #endif
6911
6912         DBPRINT(sc, BCE_INFO_SEND,
6913             "%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
6914             "prod_bseq = 0x%08X\n",
6915             __FUNCTION__, prod, chain_prod, prod_bseq);
6916
6917         /*
6918          * Cycle through each mbuf segment that makes up
6919          * the outgoing frame, gathering the mapping info
6920          * for that segment and creating a tx_bd for
6921          * the mbuf.
6922          */
6923         for (i = 0; i < nsegs ; i++) {
6924
6925                 chain_prod = TX_CHAIN_IDX(prod);
6926                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)]
6927                     [TX_IDX(chain_prod)];
6928
6929                 txbd->tx_bd_haddr_lo =
6930                     htole32(BCE_ADDR_LO(segs[i].ds_addr));
6931                 txbd->tx_bd_haddr_hi =
6932                     htole32(BCE_ADDR_HI(segs[i].ds_addr));
6933                 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
6934                     htole16(segs[i].ds_len);
6935                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
6936                 txbd->tx_bd_flags = htole16(flags);
6937                 prod_bseq += segs[i].ds_len;
6938                 if (i == 0)
6939                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
6940                 prod = NEXT_TX_BD(prod);
6941         }
6942
6943         /* Set the END flag on the last TX buffer descriptor. */
6944         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
6945
6946         DBRUNMSG(BCE_EXTREME_SEND,
6947             bce_dump_tx_chain(sc, debug_prod, nsegs));
6948
6949         /*
6950          * Ensure that the mbuf pointer for this transmission
6951          * is placed at the array index of the last
6952          * descriptor in this chain.  This is done
6953          * because a single map is used for all
6954          * segments of the mbuf and we don't want to
6955          * unload the map before all of the segments
6956          * have been freed.
6957          */
6958         sc->tx_mbuf_ptr[chain_prod] = m0;
6959         sc->used_tx_bd += nsegs;
6960
6961         /* Update some debug statistic counters */
6962         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
6963             sc->tx_hi_watermark = sc->used_tx_bd);
6964         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
6965         DBRUNIF(sc->debug_tx_mbuf_alloc++);
6966
6967         DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
6968
6969         /* prod points to the next free tx_bd at this point. */
6970         sc->tx_prod = prod;
6971         sc->tx_prod_bseq = prod_bseq;
6972
6973         /* Tell the chip about the waiting TX frames. */
6974         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) +
6975             BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
6976         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +
6977             BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
6978
6979 bce_tx_encap_exit:
6980         DBEXIT(BCE_VERBOSE_SEND);
6981         return(rc);
6982 }
6983
6984
6985 /****************************************************************************/
6986 /* Main transmit routine when called from another routine with a lock.      */
6987 /*                                                                          */
6988 /* Returns:                                                                 */
6989 /*   Nothing.                                                               */
6990 /****************************************************************************/
6991 static void
6992 bce_start_locked(struct ifnet *ifp)
6993 {
6994         struct bce_softc *sc = ifp->if_softc;
6995         struct mbuf *m_head = NULL;
6996         int count = 0;
6997         u16 tx_prod, tx_chain_prod;
6998
6999         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7000
7001         BCE_LOCK_ASSERT(sc);
7002
7003         /* prod points to the next free tx_bd. */
7004         tx_prod = sc->tx_prod;
7005         tx_chain_prod = TX_CHAIN_IDX(tx_prod);
7006
7007         DBPRINT(sc, BCE_INFO_SEND,
7008             "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
7009             "tx_prod_bseq = 0x%08X\n",
7010             __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
7011
7012         /* If there's no link or the transmit queue is empty then just exit. */
7013         if (sc->bce_link_up == FALSE) {
7014                 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
7015                     __FUNCTION__);
7016                 goto bce_start_locked_exit;
7017         }
7018
7019         if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7020                 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
7021                     __FUNCTION__);
7022                 goto bce_start_locked_exit;
7023         }
7024
7025         /*
7026          * Keep adding entries while there is space in the ring.
7027          */
7028         while (sc->used_tx_bd < sc->max_tx_bd) {
7029
7030                 /* Check for any frames to send. */
7031                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
7032
7033                 /* Stop when the transmit queue is empty. */
7034                 if (m_head == NULL)
7035                         break;
7036
7037                 /*
7038                  * Pack the data into the transmit ring. If we
7039                  * don't have room, place the mbuf back at the
7040                  * head of the queue and set the OACTIVE flag
7041                  * to wait for the NIC to drain the chain.
7042                  */
7043                 if (bce_tx_encap(sc, &m_head)) {
7044                         if (m_head != NULL)
7045                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
7046                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
7047                         DBPRINT(sc, BCE_INFO_SEND,
7048                             "TX chain is closed for business! Total "
7049                             "tx_bd used = %d\n", sc->used_tx_bd);
7050                         break;
7051                 }
7052
7053                 count++;
7054
7055                 /* Send a copy of the frame to any BPF listeners. */
7056                 ETHER_BPF_MTAP(ifp, m_head);
7057         }
7058
7059         /* Exit if no packets were dequeued. */
7060         if (count == 0) {
7061                 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were "
7062                     "dequeued\n", __FUNCTION__);
7063                 goto bce_start_locked_exit;
7064         }
7065
7066         DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into "
7067             "send queue.\n", __FUNCTION__, count);
7068
7069         /* Set the tx timeout. */
7070         sc->watchdog_timer = BCE_TX_TIMEOUT;
7071
7072         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
7073         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
7074
7075 bce_start_locked_exit:
7076         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7077         return;
7078 }
7079
7080
7081 /****************************************************************************/
7082 /* Main transmit routine when called from another routine without a lock.   */
7083 /*                                                                          */
7084 /* Returns:                                                                 */
7085 /*   Nothing.                                                               */
7086 /****************************************************************************/
7087 static void
7088 bce_start(struct ifnet *ifp)
7089 {
7090         struct bce_softc *sc = ifp->if_softc;
7091
7092         DBENTER(BCE_VERBOSE_SEND);
7093
7094         BCE_LOCK(sc);
7095         bce_start_locked(ifp);
7096         BCE_UNLOCK(sc);
7097
7098         DBEXIT(BCE_VERBOSE_SEND);
7099 }
7100
7101
7102 /****************************************************************************/
7103 /* Handles any IOCTL calls from the operating system.                       */
7104 /*                                                                          */
7105 /* Returns:                                                                 */
7106 /*   0 for success, positive value for failure.                             */
7107 /****************************************************************************/
7108 static int
7109 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
7110 {
7111         struct bce_softc *sc = ifp->if_softc;
7112         struct ifreq *ifr = (struct ifreq *) data;
7113         struct mii_data *mii;
7114         int mask, error = 0, reinit;
7115
7116         DBENTER(BCE_VERBOSE_MISC);
7117
7118         switch(command) {
7119
7120         /* Set the interface MTU. */
7121         case SIOCSIFMTU:
7122                 /* Check that the MTU setting is supported. */
7123                 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
7124                         (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
7125                         error = EINVAL;
7126                         break;
7127                 }
7128
7129                 DBPRINT(sc, BCE_INFO_MISC,
7130                     "SIOCSIFMTU: Changing MTU from %d to %d\n",
7131                     (int) ifp->if_mtu, (int) ifr->ifr_mtu);
7132
7133                 BCE_LOCK(sc);
7134                 ifp->if_mtu = ifr->ifr_mtu;
7135                 reinit = 0;
7136                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7137                         /*
7138                          * Because allocation size is used in RX
7139                          * buffer allocation, stop controller if
7140                          * it is already running.
7141                          */
7142                         bce_stop(sc);
7143                         reinit = 1;
7144                 }
7145 #ifdef BCE_JUMBO_HDRSPLIT
7146                 /* No buffer allocation size changes are necessary. */
7147 #else
7148                 /* Recalculate our buffer allocation sizes. */
7149                 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
7150                      ETHER_CRC_LEN) > MCLBYTES) {
7151                         sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
7152                         sc->rx_bd_mbuf_align_pad  =
7153                             roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
7154                         sc->rx_bd_mbuf_data_len =
7155                             sc->rx_bd_mbuf_alloc_size -
7156                             sc->rx_bd_mbuf_align_pad;
7157                 } else {
7158                         sc->rx_bd_mbuf_alloc_size = MCLBYTES;
7159                         sc->rx_bd_mbuf_align_pad  =
7160                             roundup2(MCLBYTES, 16) - MCLBYTES;
7161                         sc->rx_bd_mbuf_data_len =
7162                             sc->rx_bd_mbuf_alloc_size -
7163                             sc->rx_bd_mbuf_align_pad;
7164                 }
7165 #endif
7166
7167                 if (reinit != 0)
7168                         bce_init_locked(sc);
7169                 BCE_UNLOCK(sc);
7170                 break;
7171
7172         /* Set interface flags. */
7173         case SIOCSIFFLAGS:
7174                 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n");
7175
7176                 BCE_LOCK(sc);
7177
7178                 /* Check if the interface is up. */
7179                 if (ifp->if_flags & IFF_UP) {
7180                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7181                                 /* Change promiscuous/multicast flags as necessary. */
7182                                 bce_set_rx_mode(sc);
7183                         } else {
7184                                 /* Start the HW */
7185                                 bce_init_locked(sc);
7186                         }
7187                 } else {
7188                         /* The interface is down, check if driver is running. */
7189                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7190                                 bce_stop(sc);
7191
7192                                 /* If MFW is running, restart the controller a bit. */
7193                                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
7194                                         bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
7195                                         bce_chipinit(sc);
7196                                         bce_mgmt_init_locked(sc);
7197                                 }
7198                         }
7199                 }
7200
7201                 BCE_UNLOCK(sc);
7202                 break;
7203
7204         /* Add/Delete multicast address */
7205         case SIOCADDMULTI:
7206         case SIOCDELMULTI:
7207                 DBPRINT(sc, BCE_VERBOSE_MISC,
7208                     "Received SIOCADDMULTI/SIOCDELMULTI\n");
7209
7210                 BCE_LOCK(sc);
7211                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7212                         bce_set_rx_mode(sc);
7213                 BCE_UNLOCK(sc);
7214
7215                 break;
7216
7217         /* Set/Get Interface media */
7218         case SIOCSIFMEDIA:
7219         case SIOCGIFMEDIA:
7220                 DBPRINT(sc, BCE_VERBOSE_MISC,
7221                     "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n");
7222
7223                 mii = device_get_softc(sc->bce_miibus);
7224                 error = ifmedia_ioctl(ifp, ifr,
7225                     &mii->mii_media, command);
7226                 break;
7227
7228         /* Set interface capability */
7229         case SIOCSIFCAP:
7230                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
7231                 DBPRINT(sc, BCE_INFO_MISC,
7232                     "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
7233
7234                 /* Toggle the TX checksum capabilities enable flag. */
7235                 if (mask & IFCAP_TXCSUM &&
7236                     ifp->if_capabilities & IFCAP_TXCSUM) {
7237                         ifp->if_capenable ^= IFCAP_TXCSUM;
7238                         if (IFCAP_TXCSUM & ifp->if_capenable)
7239                                 ifp->if_hwassist |= BCE_IF_HWASSIST;
7240                         else
7241                                 ifp->if_hwassist &= ~BCE_IF_HWASSIST;
7242                 }
7243
7244                 /* Toggle the RX checksum capabilities enable flag. */
7245                 if (mask & IFCAP_RXCSUM &&
7246                     ifp->if_capabilities & IFCAP_RXCSUM)
7247                         ifp->if_capenable ^= IFCAP_RXCSUM;
7248
7249                 /* Toggle the TSO capabilities enable flag. */
7250                 if (bce_tso_enable && (mask & IFCAP_TSO4) &&
7251                     ifp->if_capabilities & IFCAP_TSO4) {
7252                         ifp->if_capenable ^= IFCAP_TSO4;
7253                         if (IFCAP_TSO4 & ifp->if_capenable)
7254                                 ifp->if_hwassist |= CSUM_TSO;
7255                         else
7256                                 ifp->if_hwassist &= ~CSUM_TSO;
7257                 }
7258
7259                 if (mask & IFCAP_VLAN_HWCSUM &&
7260                     ifp->if_capabilities & IFCAP_VLAN_HWCSUM)
7261                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
7262
7263                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
7264                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
7265                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
7266                 /*
7267                  * Don't actually disable VLAN tag stripping as
7268                  * management firmware (ASF/IPMI/UMP) requires the
7269                  * feature. If VLAN tag stripping is disabled driver
7270                  * will manually reconstruct the VLAN frame by
7271                  * appending stripped VLAN tag.
7272                  */
7273                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
7274                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) {
7275                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
7276                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
7277                             == 0)
7278                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
7279                 }
7280                 VLAN_CAPABILITIES(ifp);
7281                 break;
7282         default:
7283                 /* We don't know how to handle the IOCTL, pass it on. */
7284                 error = ether_ioctl(ifp, command, data);
7285                 break;
7286         }
7287
7288         DBEXIT(BCE_VERBOSE_MISC);
7289         return(error);
7290 }
7291
7292
7293 /****************************************************************************/
7294 /* Transmit timeout handler.                                                */
7295 /*                                                                          */
7296 /* Returns:                                                                 */
7297 /*   Nothing.                                                               */
7298 /****************************************************************************/
7299 static void
7300 bce_watchdog(struct bce_softc *sc)
7301 {
7302         DBENTER(BCE_EXTREME_SEND);
7303
7304         BCE_LOCK_ASSERT(sc);
7305
7306         /* If the watchdog timer hasn't expired then just exit. */
7307         if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
7308                 goto bce_watchdog_exit;
7309
7310         /* If pause frames are active then don't reset the hardware. */
7311         /* ToDo: Should we reset the timer here? */
7312         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
7313                 goto bce_watchdog_exit;
7314
7315         BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
7316             __FILE__, __LINE__);
7317
7318         DBRUNMSG(BCE_INFO,
7319             bce_dump_driver_state(sc);
7320             bce_dump_status_block(sc);
7321             bce_dump_stats_block(sc);
7322             bce_dump_ftqs(sc);
7323             bce_dump_txp_state(sc, 0);
7324             bce_dump_rxp_state(sc, 0);
7325             bce_dump_tpat_state(sc, 0);
7326             bce_dump_cp_state(sc, 0);
7327             bce_dump_com_state(sc, 0));
7328
7329         DBRUN(bce_breakpoint(sc));
7330
7331         sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7332
7333         bce_init_locked(sc);
7334         sc->bce_ifp->if_oerrors++;
7335
7336 bce_watchdog_exit:
7337         DBEXIT(BCE_EXTREME_SEND);
7338 }
7339
7340
7341 /*
7342  * Interrupt handler.
7343  */
7344 /****************************************************************************/
7345 /* Main interrupt entry point.  Verifies that the controller generated the  */
7346 /* interrupt and then calls a separate routine for handle the various       */
7347 /* interrupt causes (PHY, TX, RX).                                          */
7348 /*                                                                          */
7349 /* Returns:                                                                 */
7350 /*   0 for success, positive value for failure.                             */
7351 /****************************************************************************/
7352 static void
7353 bce_intr(void *xsc)
7354 {
7355         struct bce_softc *sc;
7356         struct ifnet *ifp;
7357         u32 status_attn_bits;
7358         u16 hw_rx_cons, hw_tx_cons;
7359
7360         sc = xsc;
7361         ifp = sc->bce_ifp;
7362
7363         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7364         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
7365         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc));
7366
7367         BCE_LOCK(sc);
7368
7369         DBRUN(sc->interrupts_generated++);
7370
7371         /* Synchnorize before we read from interface's status block */
7372         bus_dmamap_sync(sc->status_tag, sc->status_map,
7373             BUS_DMASYNC_POSTREAD);
7374
7375         /*
7376          * If the hardware status block index
7377          * matches the last value read by the
7378          * driver and we haven't asserted our
7379          * interrupt then there's nothing to do.
7380          */
7381         if ((sc->status_block->status_idx == sc->last_status_idx) &&
7382             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
7383              BCE_PCICFG_MISC_STATUS_INTA_VALUE)) {
7384                 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n",
7385                     __FUNCTION__);
7386                 goto bce_intr_exit;
7387         }
7388
7389         /* Ack the interrupt and stop others from occuring. */
7390         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7391             BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
7392             BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7393
7394         /* Check if the hardware has finished any work. */
7395         hw_rx_cons = bce_get_hw_rx_cons(sc);
7396         hw_tx_cons = bce_get_hw_tx_cons(sc);
7397
7398         /* Keep processing data as long as there is work to do. */
7399         for (;;) {
7400
7401                 status_attn_bits = sc->status_block->status_attn_bits;
7402
7403                 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control),
7404                     BCE_PRINTF("Simulating unexpected status attention "
7405                     "bit set.");
7406                     sc->unexpected_attention_sim_count++;
7407                     status_attn_bits = status_attn_bits |
7408                     STATUS_ATTN_BITS_PARITY_ERROR);
7409
7410                 /* Was it a link change interrupt? */
7411                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
7412                     (sc->status_block->status_attn_bits_ack &
7413                      STATUS_ATTN_BITS_LINK_STATE)) {
7414                         bce_phy_intr(sc);
7415
7416                         /* Clear transient updates during link state change. */
7417                         REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |
7418                             BCE_HC_COMMAND_COAL_NOW_WO_INT);
7419                         REG_RD(sc, BCE_HC_COMMAND);
7420                 }
7421
7422                 /* If any other attention is asserted, the chip is toast. */
7423                 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
7424                     (sc->status_block->status_attn_bits_ack &
7425                     ~STATUS_ATTN_BITS_LINK_STATE))) {
7426
7427                         sc->unexpected_attention_count++;
7428
7429                         BCE_PRINTF("%s(%d): Fatal attention detected: "
7430                             "0x%08X\n", __FILE__, __LINE__,
7431                             sc->status_block->status_attn_bits);
7432
7433                         DBRUNMSG(BCE_FATAL,
7434                             if (unexpected_attention_sim_control == 0)
7435                                 bce_breakpoint(sc));
7436
7437                         bce_init_locked(sc);
7438                         goto bce_intr_exit;
7439                 }
7440
7441                 /* Check for any completed RX frames. */
7442                 if (hw_rx_cons != sc->hw_rx_cons)
7443                         bce_rx_intr(sc);
7444
7445                 /* Check for any completed TX frames. */
7446                 if (hw_tx_cons != sc->hw_tx_cons)
7447                         bce_tx_intr(sc);
7448
7449                 /* Save status block index value for the next interrupt. */
7450                 sc->last_status_idx = sc->status_block->status_idx;
7451
7452                 /*
7453                  * Prevent speculative reads from getting
7454                  * ahead of the status block.
7455                  */
7456                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
7457                     BUS_SPACE_BARRIER_READ);
7458
7459                 /*
7460                  * If there's no work left then exit the
7461                  * interrupt service routine.
7462                  */
7463                 hw_rx_cons = bce_get_hw_rx_cons(sc);
7464                 hw_tx_cons = bce_get_hw_tx_cons(sc);
7465
7466                 if ((hw_rx_cons == sc->hw_rx_cons) &&
7467                     (hw_tx_cons == sc->hw_tx_cons))
7468                         break;
7469
7470         }
7471
7472         bus_dmamap_sync(sc->status_tag, sc->status_map,
7473             BUS_DMASYNC_PREREAD);
7474
7475         /* Re-enable interrupts. */
7476         bce_enable_intr(sc, 0);
7477
7478         /* Handle any frames that arrived while handling the interrupt. */
7479         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
7480             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
7481                 bce_start_locked(ifp);
7482
7483 bce_intr_exit:
7484         BCE_UNLOCK(sc);
7485
7486         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7487 }
7488
7489
7490 /****************************************************************************/
7491 /* Programs the various packet receive modes (broadcast and multicast).     */
7492 /*                                                                          */
7493 /* Returns:                                                                 */
7494 /*   Nothing.                                                               */
7495 /****************************************************************************/
7496 static void
7497 bce_set_rx_mode(struct bce_softc *sc)
7498 {
7499         struct ifnet *ifp;
7500         struct ifmultiaddr *ifma;
7501         u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
7502         u32 rx_mode, sort_mode;
7503         int h, i;
7504
7505         DBENTER(BCE_VERBOSE_MISC);
7506
7507         BCE_LOCK_ASSERT(sc);
7508
7509         ifp = sc->bce_ifp;
7510
7511         /* Initialize receive mode default settings. */
7512         rx_mode   = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
7513             BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
7514         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
7515
7516         /*
7517          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
7518          * be enbled.
7519          */
7520         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
7521             (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)))
7522                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
7523
7524         /*
7525          * Check for promiscuous, all multicast, or selected
7526          * multicast address filtering.
7527          */
7528         if (ifp->if_flags & IFF_PROMISC) {
7529                 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n");
7530
7531                 /* Enable promiscuous mode. */
7532                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
7533                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
7534         } else if (ifp->if_flags & IFF_ALLMULTI) {
7535                 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n");
7536
7537                 /* Enable all multicast addresses. */
7538                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
7539                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff);
7540         }
7541                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
7542         } else {
7543                 /* Accept one or more multicast(s). */
7544                 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n");
7545
7546                 if_maddr_rlock(ifp);
7547                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
7548                         if (ifma->ifma_addr->sa_family != AF_LINK)
7549                                 continue;
7550                         h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
7551                             ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
7552                             hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
7553                 }
7554                 if_maddr_runlock(ifp);
7555
7556                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
7557                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
7558
7559                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
7560         }
7561
7562         /* Only make changes if the recive mode has actually changed. */
7563         if (rx_mode != sc->rx_mode) {
7564                 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: "
7565                     "0x%08X\n", rx_mode);
7566
7567                 sc->rx_mode = rx_mode;
7568                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
7569         }
7570
7571         /* Disable and clear the exisitng sort before enabling a new sort. */
7572         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
7573         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
7574         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
7575
7576         DBEXIT(BCE_VERBOSE_MISC);
7577 }
7578
7579
7580 /****************************************************************************/
7581 /* Called periodically to updates statistics from the controllers           */
7582 /* statistics block.                                                        */
7583 /*                                                                          */
7584 /* Returns:                                                                 */
7585 /*   Nothing.                                                               */
7586 /****************************************************************************/
7587 static void
7588 bce_stats_update(struct bce_softc *sc)
7589 {
7590         struct ifnet *ifp;
7591         struct statistics_block *stats;
7592
7593         DBENTER(BCE_EXTREME_MISC);
7594
7595         ifp = sc->bce_ifp;
7596
7597         stats = (struct statistics_block *) sc->stats_block;
7598
7599         /*
7600          * Certain controllers don't report
7601          * carrier sense errors correctly.
7602          * See errata E11_5708CA0_1165.
7603          */
7604         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
7605             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
7606                 ifp->if_oerrors +=
7607                     (u_long) stats->stat_Dot3StatsCarrierSenseErrors;
7608
7609         /*
7610          * Update the sysctl statistics from the
7611          * hardware statistics.
7612          */
7613         sc->stat_IfHCInOctets =
7614             ((u64) stats->stat_IfHCInOctets_hi << 32) +
7615              (u64) stats->stat_IfHCInOctets_lo;
7616
7617         sc->stat_IfHCInBadOctets =
7618             ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
7619              (u64) stats->stat_IfHCInBadOctets_lo;
7620
7621         sc->stat_IfHCOutOctets =
7622             ((u64) stats->stat_IfHCOutOctets_hi << 32) +
7623              (u64) stats->stat_IfHCOutOctets_lo;
7624
7625         sc->stat_IfHCOutBadOctets =
7626             ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
7627              (u64) stats->stat_IfHCOutBadOctets_lo;
7628
7629         sc->stat_IfHCInUcastPkts =
7630             ((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
7631              (u64) stats->stat_IfHCInUcastPkts_lo;
7632
7633         sc->stat_IfHCInMulticastPkts =
7634             ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
7635              (u64) stats->stat_IfHCInMulticastPkts_lo;
7636
7637         sc->stat_IfHCInBroadcastPkts =
7638             ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
7639              (u64) stats->stat_IfHCInBroadcastPkts_lo;
7640
7641         sc->stat_IfHCOutUcastPkts =
7642             ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
7643              (u64) stats->stat_IfHCOutUcastPkts_lo;
7644
7645         sc->stat_IfHCOutMulticastPkts =
7646             ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
7647              (u64) stats->stat_IfHCOutMulticastPkts_lo;
7648
7649         sc->stat_IfHCOutBroadcastPkts =
7650             ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
7651              (u64) stats->stat_IfHCOutBroadcastPkts_lo;
7652
7653         /* ToDo: Preserve counters beyond 32 bits? */
7654         /* ToDo: Read the statistics from auto-clear regs? */
7655
7656         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
7657             stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
7658
7659         sc->stat_Dot3StatsCarrierSenseErrors =
7660             stats->stat_Dot3StatsCarrierSenseErrors;
7661
7662         sc->stat_Dot3StatsFCSErrors =
7663             stats->stat_Dot3StatsFCSErrors;
7664
7665         sc->stat_Dot3StatsAlignmentErrors =
7666             stats->stat_Dot3StatsAlignmentErrors;
7667
7668         sc->stat_Dot3StatsSingleCollisionFrames =
7669             stats->stat_Dot3StatsSingleCollisionFrames;
7670
7671         sc->stat_Dot3StatsMultipleCollisionFrames =
7672             stats->stat_Dot3StatsMultipleCollisionFrames;
7673
7674         sc->stat_Dot3StatsDeferredTransmissions =
7675             stats->stat_Dot3StatsDeferredTransmissions;
7676
7677         sc->stat_Dot3StatsExcessiveCollisions =
7678             stats->stat_Dot3StatsExcessiveCollisions;
7679
7680         sc->stat_Dot3StatsLateCollisions =
7681             stats->stat_Dot3StatsLateCollisions;
7682
7683         sc->stat_EtherStatsCollisions =
7684             stats->stat_EtherStatsCollisions;
7685
7686         sc->stat_EtherStatsFragments =
7687             stats->stat_EtherStatsFragments;
7688
7689         sc->stat_EtherStatsJabbers =
7690             stats->stat_EtherStatsJabbers;
7691
7692         sc->stat_EtherStatsUndersizePkts =
7693             stats->stat_EtherStatsUndersizePkts;
7694
7695         sc->stat_EtherStatsOversizePkts =
7696              stats->stat_EtherStatsOversizePkts;
7697
7698         sc->stat_EtherStatsPktsRx64Octets =
7699             stats->stat_EtherStatsPktsRx64Octets;
7700
7701         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
7702             stats->stat_EtherStatsPktsRx65Octetsto127Octets;
7703
7704         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
7705             stats->stat_EtherStatsPktsRx128Octetsto255Octets;
7706
7707         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
7708             stats->stat_EtherStatsPktsRx256Octetsto511Octets;
7709
7710         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
7711             stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
7712
7713         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
7714             stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
7715
7716         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
7717             stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
7718
7719         sc->stat_EtherStatsPktsTx64Octets =
7720             stats->stat_EtherStatsPktsTx64Octets;
7721
7722         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
7723             stats->stat_EtherStatsPktsTx65Octetsto127Octets;
7724
7725         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
7726             stats->stat_EtherStatsPktsTx128Octetsto255Octets;
7727
7728         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
7729             stats->stat_EtherStatsPktsTx256Octetsto511Octets;
7730
7731         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
7732             stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
7733
7734         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
7735             stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
7736
7737         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
7738             stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
7739
7740         sc->stat_XonPauseFramesReceived =
7741             stats->stat_XonPauseFramesReceived;
7742
7743         sc->stat_XoffPauseFramesReceived =
7744             stats->stat_XoffPauseFramesReceived;
7745
7746         sc->stat_OutXonSent =
7747             stats->stat_OutXonSent;
7748
7749         sc->stat_OutXoffSent =
7750             stats->stat_OutXoffSent;
7751
7752         sc->stat_FlowControlDone =
7753             stats->stat_FlowControlDone;
7754
7755         sc->stat_MacControlFramesReceived =
7756             stats->stat_MacControlFramesReceived;
7757
7758         sc->stat_XoffStateEntered =
7759             stats->stat_XoffStateEntered;
7760
7761         sc->stat_IfInFramesL2FilterDiscards =
7762             stats->stat_IfInFramesL2FilterDiscards;
7763
7764         sc->stat_IfInRuleCheckerDiscards =
7765             stats->stat_IfInRuleCheckerDiscards;
7766
7767         sc->stat_IfInFTQDiscards =
7768             stats->stat_IfInFTQDiscards;
7769
7770         sc->stat_IfInMBUFDiscards =
7771             stats->stat_IfInMBUFDiscards;
7772
7773         sc->stat_IfInRuleCheckerP4Hit =
7774             stats->stat_IfInRuleCheckerP4Hit;
7775
7776         sc->stat_CatchupInRuleCheckerDiscards =
7777             stats->stat_CatchupInRuleCheckerDiscards;
7778
7779         sc->stat_CatchupInFTQDiscards =
7780             stats->stat_CatchupInFTQDiscards;
7781
7782         sc->stat_CatchupInMBUFDiscards =
7783             stats->stat_CatchupInMBUFDiscards;
7784
7785         sc->stat_CatchupInRuleCheckerP4Hit =
7786             stats->stat_CatchupInRuleCheckerP4Hit;
7787
7788         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
7789
7790         /*
7791          * Update the interface statistics from the
7792          * hardware statistics.
7793          */
7794         ifp->if_collisions =
7795             (u_long) sc->stat_EtherStatsCollisions;
7796
7797         /* ToDo: This method loses soft errors. */
7798         ifp->if_ierrors =
7799             (u_long) sc->stat_EtherStatsUndersizePkts +
7800             (u_long) sc->stat_EtherStatsOversizePkts +
7801             (u_long) sc->stat_IfInMBUFDiscards +
7802             (u_long) sc->stat_Dot3StatsAlignmentErrors +
7803             (u_long) sc->stat_Dot3StatsFCSErrors +
7804             (u_long) sc->stat_IfInRuleCheckerDiscards +
7805             (u_long) sc->stat_IfInFTQDiscards +
7806             (u_long) sc->com_no_buffers;
7807
7808         /* ToDo: This method loses soft errors. */
7809         ifp->if_oerrors =
7810             (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
7811             (u_long) sc->stat_Dot3StatsExcessiveCollisions +
7812             (u_long) sc->stat_Dot3StatsLateCollisions;
7813
7814         /* ToDo: Add additional statistics? */
7815
7816         DBEXIT(BCE_EXTREME_MISC);
7817 }
7818
7819
7820 /****************************************************************************/
7821 /* Periodic function to notify the bootcode that the driver is still        */
7822 /* present.                                                                 */
7823 /*                                                                          */
7824 /* Returns:                                                                 */
7825 /*   Nothing.                                                               */
7826 /****************************************************************************/
7827 static void
7828 bce_pulse(void *xsc)
7829 {
7830         struct bce_softc *sc = xsc;
7831         u32 msg;
7832
7833         DBENTER(BCE_EXTREME_MISC);
7834
7835         BCE_LOCK_ASSERT(sc);
7836
7837         /* Tell the firmware that the driver is still running. */
7838         msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
7839         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
7840
7841         /* Update the bootcode condition. */
7842         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
7843
7844         /* Report whether the bootcode still knows the driver is running. */
7845         if (bootverbose) {
7846                 if (sc->bce_drv_cardiac_arrest == FALSE) {
7847                         if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
7848                                 sc->bce_drv_cardiac_arrest = TRUE;
7849                                 BCE_PRINTF("%s(): Warning: bootcode "
7850                                     "thinks driver is absent! "
7851                                     "(bc_state = 0x%08X)\n",
7852                                     __FUNCTION__, sc->bc_state);
7853                         }
7854                 } else {
7855                         /*
7856                          * Not supported by all bootcode versions.
7857                          * (v5.0.11+ and v5.2.1+)  Older bootcode
7858                          * will require the driver to reset the
7859                          * controller to clear this condition.
7860                          */
7861                         if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
7862                                 sc->bce_drv_cardiac_arrest = FALSE;
7863                                 BCE_PRINTF("%s(): Bootcode found the "
7864                                     "driver pulse! (bc_state = 0x%08X)\n",
7865                                     __FUNCTION__, sc->bc_state);
7866                         }
7867                 }
7868         }
7869
7870
7871         /* Schedule the next pulse. */
7872         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
7873
7874         DBEXIT(BCE_EXTREME_MISC);
7875 }
7876
7877
7878 /****************************************************************************/
7879 /* Periodic function to perform maintenance tasks.                          */
7880 /*                                                                          */
7881 /* Returns:                                                                 */
7882 /*   Nothing.                                                               */
7883 /****************************************************************************/
7884 static void
7885 bce_tick(void *xsc)
7886 {
7887         struct bce_softc *sc = xsc;
7888         struct mii_data *mii;
7889         struct ifnet *ifp;
7890
7891         ifp = sc->bce_ifp;
7892
7893         DBENTER(BCE_EXTREME_MISC);
7894
7895         BCE_LOCK_ASSERT(sc);
7896
7897         /* Schedule the next tick. */
7898         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7899
7900         /* Update the statistics from the hardware statistics block. */
7901         bce_stats_update(sc);
7902
7903         /* Top off the receive and page chains. */
7904 #ifdef BCE_JUMBO_HDRSPLIT
7905         bce_fill_pg_chain(sc);
7906 #endif
7907         bce_fill_rx_chain(sc);
7908
7909         /* Check that chip hasn't hung. */
7910         bce_watchdog(sc);
7911
7912         /* If link is up already up then we're done. */
7913         if (sc->bce_link_up == TRUE)
7914                 goto bce_tick_exit;
7915
7916         /* Link is down.  Check what the PHY's doing. */
7917         mii = device_get_softc(sc->bce_miibus);
7918         mii_tick(mii);
7919
7920         /* Check if the link has come up. */
7921         if ((mii->mii_media_status & IFM_ACTIVE) &&
7922             (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
7923                 DBPRINT(sc, BCE_VERBOSE_MISC,
7924                     "%s(): Link up!\n", __FUNCTION__);
7925                 sc->bce_link_up = TRUE;
7926                 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
7927                     IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
7928                     IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
7929                     bootverbose)
7930                         BCE_PRINTF("Gigabit link up!\n");
7931
7932                 /* Now that link is up, handle any outstanding TX traffic. */
7933                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7934                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
7935                             "pending TX traffic.\n", __FUNCTION__);
7936                         bce_start_locked(ifp);
7937                 }
7938         }
7939
7940 bce_tick_exit:
7941         DBEXIT(BCE_EXTREME_MISC);
7942         return;
7943 }
7944
7945
7946 #ifdef BCE_DEBUG
7947 /****************************************************************************/
7948 /* Allows the driver state to be dumped through the sysctl interface.       */
7949 /*                                                                          */
7950 /* Returns:                                                                 */
7951 /*   0 for success, positive value for failure.                             */
7952 /****************************************************************************/
7953 static int
7954 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
7955 {
7956         int error;
7957         int result;
7958         struct bce_softc *sc;
7959
7960         result = -1;
7961         error = sysctl_handle_int(oidp, &result, 0, req);
7962
7963         if (error || !req->newptr)
7964                 return (error);
7965
7966         if (result == 1) {
7967                 sc = (struct bce_softc *)arg1;
7968                 bce_dump_driver_state(sc);
7969         }
7970
7971         return error;
7972 }
7973
7974
7975 /****************************************************************************/
7976 /* Allows the hardware state to be dumped through the sysctl interface.     */
7977 /*                                                                          */
7978 /* Returns:                                                                 */
7979 /*   0 for success, positive value for failure.                             */
7980 /****************************************************************************/
7981 static int
7982 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
7983 {
7984         int error;
7985         int result;
7986         struct bce_softc *sc;
7987
7988         result = -1;
7989         error = sysctl_handle_int(oidp, &result, 0, req);
7990
7991         if (error || !req->newptr)
7992                 return (error);
7993
7994         if (result == 1) {
7995                 sc = (struct bce_softc *)arg1;
7996                 bce_dump_hw_state(sc);
7997         }
7998
7999         return error;
8000 }
8001
8002
8003 /****************************************************************************/
8004 /* Allows the status block to be dumped through the sysctl interface.       */
8005 /*                                                                          */
8006 /* Returns:                                                                 */
8007 /*   0 for success, positive value for failure.                             */
8008 /****************************************************************************/
8009 static int
8010 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS)
8011 {
8012         int error;
8013         int result;
8014         struct bce_softc *sc;
8015
8016         result = -1;
8017         error = sysctl_handle_int(oidp, &result, 0, req);
8018
8019         if (error || !req->newptr)
8020                 return (error);
8021
8022         if (result == 1) {
8023                 sc = (struct bce_softc *)arg1;
8024                 bce_dump_status_block(sc);
8025         }
8026
8027         return error;
8028 }
8029
8030
8031 /****************************************************************************/
8032 /* Allows the stats block to be dumped through the sysctl interface.        */
8033 /*                                                                          */
8034 /* Returns:                                                                 */
8035 /*   0 for success, positive value for failure.                             */
8036 /****************************************************************************/
8037 static int
8038 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS)
8039 {
8040         int error;
8041         int result;
8042         struct bce_softc *sc;
8043
8044         result = -1;
8045         error = sysctl_handle_int(oidp, &result, 0, req);
8046
8047         if (error || !req->newptr)
8048                 return (error);
8049
8050         if (result == 1) {
8051                 sc = (struct bce_softc *)arg1;
8052                 bce_dump_stats_block(sc);
8053         }
8054
8055         return error;
8056 }
8057
8058
8059 /****************************************************************************/
8060 /* Allows the stat counters to be cleared without unloading/reloading the   */
8061 /* driver.                                                                  */
8062 /*                                                                          */
8063 /* Returns:                                                                 */
8064 /*   0 for success, positive value for failure.                             */
8065 /****************************************************************************/
8066 static int
8067 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS)
8068 {
8069         int error;
8070         int result;
8071         struct bce_softc *sc;
8072
8073         result = -1;
8074         error = sysctl_handle_int(oidp, &result, 0, req);
8075
8076         if (error || !req->newptr)
8077                 return (error);
8078
8079         if (result == 1) {
8080                 sc = (struct bce_softc *)arg1;
8081
8082                 /* Clear the internal H/W statistics counters. */
8083                 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
8084
8085                 /* Reset the driver maintained statistics. */
8086                 sc->interrupts_rx =
8087                     sc->interrupts_tx = 0;
8088                 sc->tso_frames_requested =
8089                     sc->tso_frames_completed =
8090                     sc->tso_frames_failed = 0;
8091                 sc->rx_empty_count =
8092                     sc->tx_full_count = 0;
8093                 sc->rx_low_watermark = USABLE_RX_BD;
8094                 sc->tx_hi_watermark = 0;
8095                 sc->l2fhdr_error_count =
8096                     sc->l2fhdr_error_sim_count = 0;
8097                 sc->mbuf_alloc_failed_count =
8098                     sc->mbuf_alloc_failed_sim_count = 0;
8099                 sc->dma_map_addr_rx_failed_count =
8100                     sc->dma_map_addr_tx_failed_count = 0;
8101                 sc->mbuf_frag_count = 0;
8102                 sc->csum_offload_tcp_udp =
8103                    sc->csum_offload_ip = 0;
8104                 sc->vlan_tagged_frames_rcvd =
8105                    sc->vlan_tagged_frames_stripped = 0;
8106
8107                 /* Clear firmware maintained statistics. */
8108                 REG_WR_IND(sc, 0x120084, 0);
8109         }
8110
8111         return error;
8112 }
8113
8114
8115 /****************************************************************************/
8116 /* Allows the bootcode state to be dumped through the sysctl interface.     */
8117 /*                                                                          */
8118 /* Returns:                                                                 */
8119 /*   0 for success, positive value for failure.                             */
8120 /****************************************************************************/
8121 static int
8122 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS)
8123 {
8124         int error;
8125         int result;
8126         struct bce_softc *sc;
8127
8128         result = -1;
8129         error = sysctl_handle_int(oidp, &result, 0, req);
8130
8131         if (error || !req->newptr)
8132                 return (error);
8133
8134         if (result == 1) {
8135                 sc = (struct bce_softc *)arg1;
8136                 bce_dump_bc_state(sc);
8137         }
8138
8139         return error;
8140 }
8141
8142
8143 /****************************************************************************/
8144 /* Provides a sysctl interface to allow dumping the RX BD chain.            */
8145 /*                                                                          */
8146 /* Returns:                                                                 */
8147 /*   0 for success, positive value for failure.                             */
8148 /****************************************************************************/
8149 static int
8150 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS)
8151 {
8152         int error;
8153         int result;
8154         struct bce_softc *sc;
8155
8156         result = -1;
8157         error = sysctl_handle_int(oidp, &result, 0, req);
8158
8159         if (error || !req->newptr)
8160                 return (error);
8161
8162         if (result == 1) {
8163                 sc = (struct bce_softc *)arg1;
8164                 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD);
8165         }
8166
8167         return error;
8168 }
8169
8170
8171 /****************************************************************************/
8172 /* Provides a sysctl interface to allow dumping the RX MBUF chain.          */
8173 /*                                                                          */
8174 /* Returns:                                                                 */
8175 /*   0 for success, positive value for failure.                             */
8176 /****************************************************************************/
8177 static int
8178 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS)
8179 {
8180         int error;
8181         int result;
8182         struct bce_softc *sc;
8183
8184         result = -1;
8185         error = sysctl_handle_int(oidp, &result, 0, req);
8186
8187         if (error || !req->newptr)
8188                 return (error);
8189
8190         if (result == 1) {
8191                 sc = (struct bce_softc *)arg1;
8192                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD);
8193         }
8194
8195         return error;
8196 }
8197
8198
8199 /****************************************************************************/
8200 /* Provides a sysctl interface to allow dumping the TX chain.               */
8201 /*                                                                          */
8202 /* Returns:                                                                 */
8203 /*   0 for success, positive value for failure.                             */
8204 /****************************************************************************/
8205 static int
8206 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
8207 {
8208         int error;
8209         int result;
8210         struct bce_softc *sc;
8211
8212         result = -1;
8213         error = sysctl_handle_int(oidp, &result, 0, req);
8214
8215         if (error || !req->newptr)
8216                 return (error);
8217
8218         if (result == 1) {
8219                 sc = (struct bce_softc *)arg1;
8220                 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
8221         }
8222
8223         return error;
8224 }
8225
8226
8227 #ifdef BCE_JUMBO_HDRSPLIT
8228 /****************************************************************************/
8229 /* Provides a sysctl interface to allow dumping the page chain.             */
8230 /*                                                                          */
8231 /* Returns:                                                                 */
8232 /*   0 for success, positive value for failure.                             */
8233 /****************************************************************************/
8234 static int
8235 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS)
8236 {
8237         int error;
8238         int result;
8239         struct bce_softc *sc;
8240
8241         result = -1;
8242         error = sysctl_handle_int(oidp, &result, 0, req);
8243
8244         if (error || !req->newptr)
8245                 return (error);
8246
8247         if (result == 1) {
8248                 sc = (struct bce_softc *)arg1;
8249                 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD);
8250         }
8251
8252         return error;
8253 }
8254 #endif
8255
8256 /****************************************************************************/
8257 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in  */
8258 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8259 /*                                                                          */
8260 /* Returns:                                                                 */
8261 /*   0 for success, positive value for failure.                             */
8262 /****************************************************************************/
8263 static int
8264 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)
8265 {
8266         struct bce_softc *sc = (struct bce_softc *)arg1;
8267         int error;
8268         u32 result;
8269         u32 val[1];
8270         u8 *data = (u8 *) val;
8271
8272         result = -1;
8273         error = sysctl_handle_int(oidp, &result, 0, req);
8274         if (error || (req->newptr == NULL))
8275                 return (error);
8276
8277         bce_nvram_read(sc, result, data, 4);
8278         BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
8279
8280         return (error);
8281 }
8282
8283
8284 /****************************************************************************/
8285 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
8286 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
8287 /*                                                                          */
8288 /* Returns:                                                                 */
8289 /*   0 for success, positive value for failure.                             */
8290 /****************************************************************************/
8291 static int
8292 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
8293 {
8294         struct bce_softc *sc = (struct bce_softc *)arg1;
8295         int error;
8296         u32 val, result;
8297
8298         result = -1;
8299         error = sysctl_handle_int(oidp, &result, 0, req);
8300         if (error || (req->newptr == NULL))
8301                 return (error);
8302
8303         /* Make sure the register is accessible. */
8304         if (result < 0x8000) {
8305                 val = REG_RD(sc, result);
8306                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8307         } else if (result < 0x0280000) {
8308                 val = REG_RD_IND(sc, result);
8309                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8310         }
8311
8312         return (error);
8313 }
8314
8315
8316 /****************************************************************************/
8317 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
8318 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8319 /*                                                                          */
8320 /* Returns:                                                                 */
8321 /*   0 for success, positive value for failure.                             */
8322 /****************************************************************************/
8323 static int
8324 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
8325 {
8326         struct bce_softc *sc;
8327         device_t dev;
8328         int error, result;
8329         u16 val;
8330
8331         result = -1;
8332         error = sysctl_handle_int(oidp, &result, 0, req);
8333         if (error || (req->newptr == NULL))
8334                 return (error);
8335
8336         /* Make sure the register is accessible. */
8337         if (result < 0x20) {
8338                 sc = (struct bce_softc *)arg1;
8339                 dev = sc->bce_dev;
8340                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
8341                 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
8342         }
8343         return (error);
8344 }
8345
8346
8347 /****************************************************************************/
8348 /* Provides a sysctl interface to allow reading a CID.                      */
8349 /*                                                                          */
8350 /* Returns:                                                                 */
8351 /*   0 for success, positive value for failure.                             */
8352 /****************************************************************************/
8353 static int
8354 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)
8355 {
8356         struct bce_softc *sc;
8357         int error, result;
8358
8359         result = -1;
8360         error = sysctl_handle_int(oidp, &result, 0, req);
8361         if (error || (req->newptr == NULL))
8362                 return (error);
8363
8364         /* Make sure the register is accessible. */
8365         if (result <= TX_CID) {
8366                 sc = (struct bce_softc *)arg1;
8367                 bce_dump_ctx(sc, result);
8368         }
8369
8370         return (error);
8371 }
8372
8373
8374  /****************************************************************************/
8375 /* Provides a sysctl interface to forcing the driver to dump state and      */
8376 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
8377 /*                                                                          */
8378 /* Returns:                                                                 */
8379 /*   0 for success, positive value for failure.                             */
8380 /****************************************************************************/
8381 static int
8382 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
8383 {
8384         int error;
8385         int result;
8386         struct bce_softc *sc;
8387
8388         result = -1;
8389         error = sysctl_handle_int(oidp, &result, 0, req);
8390
8391         if (error || !req->newptr)
8392                 return (error);
8393
8394         if (result == 1) {
8395                 sc = (struct bce_softc *)arg1;
8396                 bce_breakpoint(sc);
8397         }
8398
8399         return error;
8400 }
8401 #endif
8402
8403
8404 /****************************************************************************/
8405 /* Adds any sysctl parameters for tuning or debugging purposes.             */
8406 /*                                                                          */
8407 /* Returns:                                                                 */
8408 /*   0 for success, positive value for failure.                             */
8409 /****************************************************************************/
8410 static void
8411 bce_add_sysctls(struct bce_softc *sc)
8412 {
8413         struct sysctl_ctx_list *ctx;
8414         struct sysctl_oid_list *children;
8415
8416         DBENTER(BCE_VERBOSE_MISC);
8417
8418         ctx = device_get_sysctl_ctx(sc->bce_dev);
8419         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
8420
8421 #ifdef BCE_DEBUG
8422         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8423             "l2fhdr_error_sim_control",
8424             CTLFLAG_RW, &l2fhdr_error_sim_control,
8425             0, "Debug control to force l2fhdr errors");
8426
8427         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8428             "l2fhdr_error_sim_count",
8429             CTLFLAG_RD, &sc->l2fhdr_error_sim_count,
8430             0, "Number of simulated l2_fhdr errors");
8431 #endif
8432
8433         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8434             "l2fhdr_error_count",
8435             CTLFLAG_RD, &sc->l2fhdr_error_count,
8436             0, "Number of l2_fhdr errors");
8437
8438 #ifdef BCE_DEBUG
8439         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8440             "mbuf_alloc_failed_sim_control",
8441             CTLFLAG_RW, &mbuf_alloc_failed_sim_control,
8442             0, "Debug control to force mbuf allocation failures");
8443
8444         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8445             "mbuf_alloc_failed_sim_count",
8446             CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count,
8447             0, "Number of simulated mbuf cluster allocation failures");
8448 #endif
8449
8450         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8451             "mbuf_alloc_failed_count",
8452             CTLFLAG_RD, &sc->mbuf_alloc_failed_count,
8453             0, "Number of mbuf allocation failures");
8454
8455         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8456             "mbuf_frag_count",
8457             CTLFLAG_RD, &sc->mbuf_frag_count,
8458             0, "Number of fragmented mbufs");
8459
8460 #ifdef BCE_DEBUG
8461         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8462             "dma_map_addr_failed_sim_control",
8463             CTLFLAG_RW, &dma_map_addr_failed_sim_control,
8464             0, "Debug control to force DMA mapping failures");
8465
8466         /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */
8467         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8468             "dma_map_addr_failed_sim_count",
8469             CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count,
8470             0, "Number of simulated DMA mapping failures");
8471
8472 #endif
8473
8474         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8475             "dma_map_addr_rx_failed_count",
8476             CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count,
8477             0, "Number of RX DMA mapping failures");
8478
8479         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8480             "dma_map_addr_tx_failed_count",
8481             CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count,
8482             0, "Number of TX DMA mapping failures");
8483
8484 #ifdef BCE_DEBUG
8485         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8486             "unexpected_attention_sim_control",
8487             CTLFLAG_RW, &unexpected_attention_sim_control,
8488             0, "Debug control to simulate unexpected attentions");
8489
8490         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8491             "unexpected_attention_sim_count",
8492             CTLFLAG_RW, &sc->unexpected_attention_sim_count,
8493             0, "Number of simulated unexpected attentions");
8494 #endif
8495
8496         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8497             "unexpected_attention_count",
8498             CTLFLAG_RW, &sc->unexpected_attention_count,
8499             0, "Number of unexpected attentions");
8500
8501 #ifdef BCE_DEBUG
8502         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8503             "debug_bootcode_running_failure",
8504             CTLFLAG_RW, &bootcode_running_failure_sim_control,
8505             0, "Debug control to force bootcode running failures");
8506
8507         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8508             "rx_low_watermark",
8509             CTLFLAG_RD, &sc->rx_low_watermark,
8510             0, "Lowest level of free rx_bd's");
8511
8512         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8513             "rx_empty_count",
8514             CTLFLAG_RD, &sc->rx_empty_count,
8515             0, "Number of times the RX chain was empty");
8516
8517         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8518             "tx_hi_watermark",
8519             CTLFLAG_RD, &sc->tx_hi_watermark,
8520             0, "Highest level of used tx_bd's");
8521
8522         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8523             "tx_full_count",
8524             CTLFLAG_RD, &sc->tx_full_count,
8525             0, "Number of times the TX chain was full");
8526
8527         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8528             "tso_frames_requested",
8529             CTLFLAG_RD, &sc->tso_frames_requested,
8530             0, "Number of TSO frames requested");
8531
8532         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8533             "tso_frames_completed",
8534             CTLFLAG_RD, &sc->tso_frames_completed,
8535             0, "Number of TSO frames completed");
8536
8537         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8538             "tso_frames_failed",
8539             CTLFLAG_RD, &sc->tso_frames_failed,
8540             0, "Number of TSO frames failed");
8541
8542         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8543             "csum_offload_ip",
8544             CTLFLAG_RD, &sc->csum_offload_ip,
8545             0, "Number of IP checksum offload frames");
8546
8547         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8548             "csum_offload_tcp_udp",
8549             CTLFLAG_RD, &sc->csum_offload_tcp_udp,
8550             0, "Number of TCP/UDP checksum offload frames");
8551
8552         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8553             "vlan_tagged_frames_rcvd",
8554             CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd,
8555             0, "Number of VLAN tagged frames received");
8556
8557         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8558             "vlan_tagged_frames_stripped",
8559             CTLFLAG_RD, &sc->vlan_tagged_frames_stripped,
8560             0, "Number of VLAN tagged frames stripped");
8561
8562         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8563             "interrupts_rx",
8564             CTLFLAG_RD, &sc->interrupts_rx,
8565             0, "Number of RX interrupts");
8566
8567         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8568             "interrupts_tx",
8569             CTLFLAG_RD, &sc->interrupts_tx,
8570             0, "Number of TX interrupts");
8571 #endif
8572
8573         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8574             "stat_IfHcInOctets",
8575             CTLFLAG_RD, &sc->stat_IfHCInOctets,
8576             "Bytes received");
8577
8578         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8579             "stat_IfHCInBadOctets",
8580             CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
8581             "Bad bytes received");
8582
8583         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8584             "stat_IfHCOutOctets",
8585             CTLFLAG_RD, &sc->stat_IfHCOutOctets,
8586             "Bytes sent");
8587
8588         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8589             "stat_IfHCOutBadOctets",
8590             CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
8591             "Bad bytes sent");
8592
8593         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8594             "stat_IfHCInUcastPkts",
8595             CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
8596             "Unicast packets received");
8597
8598         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8599             "stat_IfHCInMulticastPkts",
8600             CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
8601             "Multicast packets received");
8602
8603         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8604             "stat_IfHCInBroadcastPkts",
8605             CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
8606             "Broadcast packets received");
8607
8608         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8609             "stat_IfHCOutUcastPkts",
8610             CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
8611             "Unicast packets sent");
8612
8613         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8614             "stat_IfHCOutMulticastPkts",
8615             CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
8616             "Multicast packets sent");
8617
8618         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8619             "stat_IfHCOutBroadcastPkts",
8620             CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
8621             "Broadcast packets sent");
8622
8623         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8624             "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
8625             CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
8626             0, "Internal MAC transmit errors");
8627
8628         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8629             "stat_Dot3StatsCarrierSenseErrors",
8630             CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
8631             0, "Carrier sense errors");
8632
8633         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8634             "stat_Dot3StatsFCSErrors",
8635             CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
8636             0, "Frame check sequence errors");
8637
8638         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8639             "stat_Dot3StatsAlignmentErrors",
8640             CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
8641             0, "Alignment errors");
8642
8643         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8644             "stat_Dot3StatsSingleCollisionFrames",
8645             CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
8646             0, "Single Collision Frames");
8647
8648         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8649             "stat_Dot3StatsMultipleCollisionFrames",
8650             CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
8651             0, "Multiple Collision Frames");
8652
8653         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8654             "stat_Dot3StatsDeferredTransmissions",
8655             CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
8656             0, "Deferred Transmissions");
8657
8658         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8659             "stat_Dot3StatsExcessiveCollisions",
8660             CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
8661             0, "Excessive Collisions");
8662
8663         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8664             "stat_Dot3StatsLateCollisions",
8665             CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
8666             0, "Late Collisions");
8667
8668         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8669             "stat_EtherStatsCollisions",
8670             CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
8671             0, "Collisions");
8672
8673         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8674             "stat_EtherStatsFragments",
8675             CTLFLAG_RD, &sc->stat_EtherStatsFragments,
8676             0, "Fragments");
8677
8678         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8679             "stat_EtherStatsJabbers",
8680             CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
8681             0, "Jabbers");
8682
8683         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8684             "stat_EtherStatsUndersizePkts",
8685             CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
8686             0, "Undersize packets");
8687
8688         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8689             "stat_EtherStatsOversizePkts",
8690             CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts,
8691             0, "stat_EtherStatsOversizePkts");
8692
8693         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8694             "stat_EtherStatsPktsRx64Octets",
8695             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
8696             0, "Bytes received in 64 byte packets");
8697
8698         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8699             "stat_EtherStatsPktsRx65Octetsto127Octets",
8700             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
8701             0, "Bytes received in 65 to 127 byte packets");
8702
8703         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8704             "stat_EtherStatsPktsRx128Octetsto255Octets",
8705             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
8706             0, "Bytes received in 128 to 255 byte packets");
8707
8708         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8709             "stat_EtherStatsPktsRx256Octetsto511Octets",
8710             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
8711             0, "Bytes received in 256 to 511 byte packets");
8712
8713         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8714             "stat_EtherStatsPktsRx512Octetsto1023Octets",
8715             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
8716             0, "Bytes received in 512 to 1023 byte packets");
8717
8718         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8719             "stat_EtherStatsPktsRx1024Octetsto1522Octets",
8720             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
8721             0, "Bytes received in 1024 t0 1522 byte packets");
8722
8723         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8724             "stat_EtherStatsPktsRx1523Octetsto9022Octets",
8725             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
8726             0, "Bytes received in 1523 to 9022 byte packets");
8727
8728         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8729             "stat_EtherStatsPktsTx64Octets",
8730             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
8731             0, "Bytes sent in 64 byte packets");
8732
8733         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8734             "stat_EtherStatsPktsTx65Octetsto127Octets",
8735             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
8736             0, "Bytes sent in 65 to 127 byte packets");
8737
8738         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8739             "stat_EtherStatsPktsTx128Octetsto255Octets",
8740             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
8741             0, "Bytes sent in 128 to 255 byte packets");
8742
8743         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8744             "stat_EtherStatsPktsTx256Octetsto511Octets",
8745             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
8746             0, "Bytes sent in 256 to 511 byte packets");
8747
8748         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8749             "stat_EtherStatsPktsTx512Octetsto1023Octets",
8750             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
8751             0, "Bytes sent in 512 to 1023 byte packets");
8752
8753         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8754             "stat_EtherStatsPktsTx1024Octetsto1522Octets",
8755             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
8756             0, "Bytes sent in 1024 to 1522 byte packets");
8757
8758         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8759             "stat_EtherStatsPktsTx1523Octetsto9022Octets",
8760             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
8761             0, "Bytes sent in 1523 to 9022 byte packets");
8762
8763         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8764             "stat_XonPauseFramesReceived",
8765             CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
8766             0, "XON pause frames receved");
8767
8768         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8769             "stat_XoffPauseFramesReceived",
8770             CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
8771             0, "XOFF pause frames received");
8772
8773         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8774             "stat_OutXonSent",
8775             CTLFLAG_RD, &sc->stat_OutXonSent,
8776             0, "XON pause frames sent");
8777
8778         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8779             "stat_OutXoffSent",
8780             CTLFLAG_RD, &sc->stat_OutXoffSent,
8781             0, "XOFF pause frames sent");
8782
8783         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8784             "stat_FlowControlDone",
8785             CTLFLAG_RD, &sc->stat_FlowControlDone,
8786             0, "Flow control done");
8787
8788         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8789             "stat_MacControlFramesReceived",
8790             CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
8791             0, "MAC control frames received");
8792
8793         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8794             "stat_XoffStateEntered",
8795             CTLFLAG_RD, &sc->stat_XoffStateEntered,
8796             0, "XOFF state entered");
8797
8798         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8799             "stat_IfInFramesL2FilterDiscards",
8800             CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
8801             0, "Received L2 packets discarded");
8802
8803         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8804             "stat_IfInRuleCheckerDiscards",
8805             CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
8806             0, "Received packets discarded by rule");
8807
8808         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8809             "stat_IfInFTQDiscards",
8810             CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
8811             0, "Received packet FTQ discards");
8812
8813         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8814             "stat_IfInMBUFDiscards",
8815             CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
8816             0, "Received packets discarded due to lack "
8817             "of controller buffer memory");
8818
8819         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8820             "stat_IfInRuleCheckerP4Hit",
8821             CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
8822             0, "Received packets rule checker hits");
8823
8824         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8825             "stat_CatchupInRuleCheckerDiscards",
8826             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
8827             0, "Received packets discarded in Catchup path");
8828
8829         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8830             "stat_CatchupInFTQDiscards",
8831             CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
8832             0, "Received packets discarded in FTQ in Catchup path");
8833
8834         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8835             "stat_CatchupInMBUFDiscards",
8836             CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
8837             0, "Received packets discarded in controller "
8838             "buffer memory in Catchup path");
8839
8840         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8841             "stat_CatchupInRuleCheckerP4Hit",
8842             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
8843             0, "Received packets rule checker hits in Catchup path");
8844
8845         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8846             "com_no_buffers",
8847             CTLFLAG_RD, &sc->com_no_buffers,
8848             0, "Valid packets received but no RX buffers available");
8849
8850 #ifdef BCE_DEBUG
8851         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8852             "driver_state", CTLTYPE_INT | CTLFLAG_RW,
8853             (void *)sc, 0,
8854             bce_sysctl_driver_state, "I", "Drive state information");
8855
8856         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8857             "hw_state", CTLTYPE_INT | CTLFLAG_RW,
8858             (void *)sc, 0,
8859             bce_sysctl_hw_state, "I", "Hardware state information");
8860
8861         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8862             "status_block", CTLTYPE_INT | CTLFLAG_RW,
8863             (void *)sc, 0,
8864             bce_sysctl_status_block, "I", "Dump status block");
8865
8866         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8867             "stats_block", CTLTYPE_INT | CTLFLAG_RW,
8868             (void *)sc, 0,
8869             bce_sysctl_stats_block, "I", "Dump statistics block");
8870
8871         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8872             "stats_clear", CTLTYPE_INT | CTLFLAG_RW,
8873             (void *)sc, 0,
8874             bce_sysctl_stats_clear, "I", "Clear statistics block");
8875
8876         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8877             "bc_state", CTLTYPE_INT | CTLFLAG_RW,
8878             (void *)sc, 0,
8879             bce_sysctl_bc_state, "I", "Bootcode state information");
8880
8881         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8882             "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW,
8883             (void *)sc, 0,
8884             bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain");
8885
8886         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8887             "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW,
8888             (void *)sc, 0,
8889             bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain");
8890
8891         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8892             "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
8893             (void *)sc, 0,
8894             bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
8895
8896 #ifdef BCE_JUMBO_HDRSPLIT
8897         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8898             "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW,
8899             (void *)sc, 0,
8900             bce_sysctl_dump_pg_chain, "I", "Dump page chain");
8901 #endif
8902         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8903             "dump_ctx", CTLTYPE_INT | CTLFLAG_RW,
8904             (void *)sc, 0,
8905             bce_sysctl_dump_ctx, "I", "Dump context memory");
8906
8907         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8908             "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
8909             (void *)sc, 0,
8910             bce_sysctl_breakpoint, "I", "Driver breakpoint");
8911
8912         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8913             "reg_read", CTLTYPE_INT | CTLFLAG_RW,
8914             (void *)sc, 0,
8915             bce_sysctl_reg_read, "I", "Register read");
8916
8917         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8918             "nvram_read", CTLTYPE_INT | CTLFLAG_RW,
8919             (void *)sc, 0,
8920             bce_sysctl_nvram_read, "I", "NVRAM read");
8921
8922         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8923             "phy_read", CTLTYPE_INT | CTLFLAG_RW,
8924             (void *)sc, 0,
8925             bce_sysctl_phy_read, "I", "PHY register read");
8926
8927 #endif
8928
8929         DBEXIT(BCE_VERBOSE_MISC);
8930 }
8931
8932
8933 /****************************************************************************/
8934 /* BCE Debug Routines                                                       */
8935 /****************************************************************************/
8936 #ifdef BCE_DEBUG
8937
8938 /****************************************************************************/
8939 /* Freezes the controller to allow for a cohesive state dump.               */
8940 /*                                                                          */
8941 /* Returns:                                                                 */
8942 /*   Nothing.                                                               */
8943 /****************************************************************************/
8944 static __attribute__ ((noinline)) void
8945 bce_freeze_controller(struct bce_softc *sc)
8946 {
8947         u32 val;
8948         val = REG_RD(sc, BCE_MISC_COMMAND);
8949         val |= BCE_MISC_COMMAND_DISABLE_ALL;
8950         REG_WR(sc, BCE_MISC_COMMAND, val);
8951 }
8952
8953
8954 /****************************************************************************/
8955 /* Unfreezes the controller after a freeze operation.  This may not always  */
8956 /* work and the controller will require a reset!                            */
8957 /*                                                                          */
8958 /* Returns:                                                                 */
8959 /*   Nothing.                                                               */
8960 /****************************************************************************/
8961 static __attribute__ ((noinline)) void
8962 bce_unfreeze_controller(struct bce_softc *sc)
8963 {
8964         u32 val;
8965         val = REG_RD(sc, BCE_MISC_COMMAND);
8966         val |= BCE_MISC_COMMAND_ENABLE_ALL;
8967         REG_WR(sc, BCE_MISC_COMMAND, val);
8968 }
8969
8970
8971 /****************************************************************************/
8972 /* Prints out Ethernet frame information from an mbuf.                      */
8973 /*                                                                          */
8974 /* Partially decode an Ethernet frame to look at some important headers.    */
8975 /*                                                                          */
8976 /* Returns:                                                                 */
8977 /*   Nothing.                                                               */
8978 /****************************************************************************/
8979 static __attribute__ ((noinline)) void
8980 bce_dump_enet(struct bce_softc *sc, struct mbuf *m)
8981 {
8982         struct ether_vlan_header *eh;
8983         u16 etype;
8984         int ehlen;
8985         struct ip *ip;
8986         struct tcphdr *th;
8987         struct udphdr *uh;
8988         struct arphdr *ah;
8989
8990         BCE_PRINTF(
8991             "-----------------------------"
8992             " Frame Decode "
8993             "-----------------------------\n");
8994
8995         eh = mtod(m, struct ether_vlan_header *);
8996
8997         /* Handle VLAN encapsulation if present. */
8998         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
8999                 etype = ntohs(eh->evl_proto);
9000                 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
9001         } else {
9002                 etype = ntohs(eh->evl_encap_proto);
9003                 ehlen = ETHER_HDR_LEN;
9004         }
9005
9006         /* ToDo: Add VLAN output. */
9007         BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n",
9008             eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen);
9009
9010         switch (etype) {
9011         case ETHERTYPE_IP:
9012                 ip = (struct ip *)(m->m_data + ehlen);
9013                 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, "
9014                     "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n",
9015                     ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
9016                     ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum));
9017
9018                 switch (ip->ip_p) {
9019                 case IPPROTO_TCP:
9020                         th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9021                         BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = "
9022                             "%d bytes, flags = 0x%b, csum = 0x%04X\n",
9023                             ntohs(th->th_dport), ntohs(th->th_sport),
9024                             (th->th_off << 2), th->th_flags,
9025                             "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST"
9026                             "\02SYN\01FIN", ntohs(th->th_sum));
9027                         break;
9028                 case IPPROTO_UDP:
9029                         uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9030                         BCE_PRINTF("-udp: dest = %d, src = %d, len = %d "
9031                             "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport),
9032                             ntohs(uh->uh_sport), ntohs(uh->uh_ulen),
9033                             ntohs(uh->uh_sum));
9034                         break;
9035                 case IPPROTO_ICMP:
9036                         BCE_PRINTF("icmp:\n");
9037                         break;
9038                 default:
9039                         BCE_PRINTF("----: Other IP protocol.\n");
9040                         }
9041                 break;
9042         case ETHERTYPE_IPV6:
9043                 BCE_PRINTF("ipv6: No decode supported.\n");
9044                 break;
9045         case ETHERTYPE_ARP:
9046                 BCE_PRINTF("-arp: ");
9047                 ah = (struct arphdr *) (m->m_data + ehlen);
9048                 switch (ntohs(ah->ar_op)) {
9049                 case ARPOP_REVREQUEST:
9050                         printf("reverse ARP request\n");
9051                         break;
9052                 case ARPOP_REVREPLY:
9053                         printf("reverse ARP reply\n");
9054                         break;
9055                 case ARPOP_REQUEST:
9056                         printf("ARP request\n");
9057                         break;
9058                 case ARPOP_REPLY:
9059                         printf("ARP reply\n");
9060                         break;
9061                 default:
9062                         printf("other ARP operation\n");
9063                 }
9064                 break;
9065         default:
9066                 BCE_PRINTF("----: Other protocol.\n");
9067         }
9068
9069         BCE_PRINTF(
9070                 "-----------------------------"
9071                 "--------------"
9072                 "-----------------------------\n");
9073 }
9074
9075
9076 /****************************************************************************/
9077 /* Prints out information about an mbuf.                                    */
9078 /*                                                                          */
9079 /* Returns:                                                                 */
9080 /*   Nothing.                                                               */
9081 /****************************************************************************/
9082 static __attribute__ ((noinline)) void
9083 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
9084 {
9085         struct mbuf *mp = m;
9086
9087         if (m == NULL) {
9088                 BCE_PRINTF("mbuf: null pointer\n");
9089                 return;
9090         }
9091
9092         while (mp) {
9093                 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, "
9094                     "m_data = %p\n", mp, mp->m_len, mp->m_flags,
9095                     "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data);
9096
9097                 if (mp->m_flags & M_PKTHDR) {
9098                         BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
9099                             "csum_flags = %b\n", mp->m_pkthdr.len,
9100                             mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG"
9101                             "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG"
9102                             "\22M_PROMISC\23M_NOFREE",
9103                             mp->m_pkthdr.csum_flags,
9104                             "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
9105                             "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
9106                             "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
9107                             "\14CSUM_PSEUDO_HDR");
9108                 }
9109
9110                 if (mp->m_flags & M_EXT) {
9111                         BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
9112                             mp->m_ext.ext_buf, mp->m_ext.ext_size);
9113                         switch (mp->m_ext.ext_type) {
9114                         case EXT_CLUSTER:
9115                                 printf("EXT_CLUSTER\n"); break;
9116                         case EXT_SFBUF:
9117                                 printf("EXT_SFBUF\n"); break;
9118                         case EXT_JUMBO9:
9119                                 printf("EXT_JUMBO9\n"); break;
9120                         case EXT_JUMBO16:
9121                                 printf("EXT_JUMBO16\n"); break;
9122                         case EXT_PACKET:
9123                                 printf("EXT_PACKET\n"); break;
9124                         case EXT_MBUF:
9125                                 printf("EXT_MBUF\n"); break;
9126                         case EXT_NET_DRV:
9127                                 printf("EXT_NET_DRV\n"); break;
9128                         case EXT_MOD_TYPE:
9129                                 printf("EXT_MDD_TYPE\n"); break;
9130                         case EXT_DISPOSABLE:
9131                                 printf("EXT_DISPOSABLE\n"); break;
9132                         case EXT_EXTREF:
9133                                 printf("EXT_EXTREF\n"); break;
9134                         default:
9135                                 printf("UNKNOWN\n");
9136                         }
9137                 }
9138
9139                 mp = mp->m_next;
9140         }
9141 }
9142
9143
9144 /****************************************************************************/
9145 /* Prints out the mbufs in the TX mbuf chain.                               */
9146 /*                                                                          */
9147 /* Returns:                                                                 */
9148 /*   Nothing.                                                               */
9149 /****************************************************************************/
9150 static __attribute__ ((noinline)) void
9151 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9152 {
9153         struct mbuf *m;
9154
9155         BCE_PRINTF(
9156                 "----------------------------"
9157                 "  tx mbuf data  "
9158                 "----------------------------\n");
9159
9160         for (int i = 0; i < count; i++) {
9161                 m = sc->tx_mbuf_ptr[chain_prod];
9162                 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod);
9163                 bce_dump_mbuf(sc, m);
9164                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
9165         }
9166
9167         BCE_PRINTF(
9168                 "----------------------------"
9169                 "----------------"
9170                 "----------------------------\n");
9171 }
9172
9173
9174 /****************************************************************************/
9175 /* Prints out the mbufs in the RX mbuf chain.                               */
9176 /*                                                                          */
9177 /* Returns:                                                                 */
9178 /*   Nothing.                                                               */
9179 /****************************************************************************/
9180 static __attribute__ ((noinline)) void
9181 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9182 {
9183         struct mbuf *m;
9184
9185         BCE_PRINTF(
9186                 "----------------------------"
9187                 "  rx mbuf data  "
9188                 "----------------------------\n");
9189
9190         for (int i = 0; i < count; i++) {
9191                 m = sc->rx_mbuf_ptr[chain_prod];
9192                 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
9193                 bce_dump_mbuf(sc, m);
9194                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
9195         }
9196
9197
9198         BCE_PRINTF(
9199                 "----------------------------"
9200                 "----------------"
9201                 "----------------------------\n");
9202 }
9203
9204
9205 #ifdef BCE_JUMBO_HDRSPLIT
9206 /****************************************************************************/
9207 /* Prints out the mbufs in the mbuf page chain.                             */
9208 /*                                                                          */
9209 /* Returns:                                                                 */
9210 /*   Nothing.                                                               */
9211 /****************************************************************************/
9212 static __attribute__ ((noinline)) void
9213 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9214 {
9215         struct mbuf *m;
9216
9217         BCE_PRINTF(
9218                 "----------------------------"
9219                 "  pg mbuf data  "
9220                 "----------------------------\n");
9221
9222         for (int i = 0; i < count; i++) {
9223                 m = sc->pg_mbuf_ptr[chain_prod];
9224                 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod);
9225                 bce_dump_mbuf(sc, m);
9226                 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod));
9227         }
9228
9229
9230         BCE_PRINTF(
9231                 "----------------------------"
9232                 "----------------"
9233                 "----------------------------\n");
9234 }
9235 #endif
9236
9237
9238 /****************************************************************************/
9239 /* Prints out a tx_bd structure.                                            */
9240 /*                                                                          */
9241 /* Returns:                                                                 */
9242 /*   Nothing.                                                               */
9243 /****************************************************************************/
9244 static __attribute__ ((noinline)) void
9245 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
9246 {
9247         int i = 0;
9248
9249         if (idx > MAX_TX_BD)
9250                 /* Index out of range. */
9251                 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
9252         else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
9253                 /* TX Chain page pointer. */
9254                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
9255                     "pointer\n", idx, txbd->tx_bd_haddr_hi,
9256                     txbd->tx_bd_haddr_lo);
9257         else {
9258                 /* Normal tx_bd entry. */
9259                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
9260                     "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = "
9261                     "0x%04X (", idx, txbd->tx_bd_haddr_hi,
9262                     txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes,
9263                     txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
9264
9265                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) {
9266                         if (i>0)
9267                                 printf("|");
9268                         printf("CONN_FAULT");
9269                         i++;
9270                 }
9271
9272                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) {
9273                         if (i>0)
9274                                 printf("|");
9275                         printf("TCP_UDP_CKSUM");
9276                         i++;
9277                 }
9278
9279                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) {
9280                         if (i>0)
9281                                 printf("|");
9282                         printf("IP_CKSUM");
9283                         i++;
9284                 }
9285
9286                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) {
9287                         if (i>0)
9288                                 printf("|");
9289                         printf("VLAN");
9290                         i++;
9291                 }
9292
9293                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) {
9294                         if (i>0)
9295                                 printf("|");
9296                         printf("COAL_NOW");
9297                         i++;
9298                 }
9299
9300                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) {
9301                         if (i>0)
9302                                 printf("|");
9303                         printf("DONT_GEN_CRC");
9304                         i++;
9305                 }
9306
9307                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) {
9308                         if (i>0)
9309                                 printf("|");
9310                         printf("START");
9311                         i++;
9312                 }
9313
9314                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) {
9315                         if (i>0)
9316                                 printf("|");
9317                         printf("END");
9318                         i++;
9319                 }
9320
9321                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) {
9322                         if (i>0)
9323                                 printf("|");
9324                         printf("LSO");
9325                         i++;
9326                 }
9327
9328                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) {
9329                         if (i>0)
9330                                 printf("|");
9331                         printf("SW_OPTION=%d", ((txbd->tx_bd_flags &
9332                             TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++;
9333                 }
9334
9335                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) {
9336                         if (i>0)
9337                                 printf("|");
9338                         printf("SW_FLAGS");
9339                         i++;
9340                 }
9341
9342                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) {
9343                         if (i>0)
9344                                 printf("|");
9345                         printf("SNAP)");
9346                 } else {
9347                         printf(")\n");
9348                 }
9349         }
9350 }
9351
9352
9353 /****************************************************************************/
9354 /* Prints out a rx_bd structure.                                            */
9355 /*                                                                          */
9356 /* Returns:                                                                 */
9357 /*   Nothing.                                                               */
9358 /****************************************************************************/
9359 static __attribute__ ((noinline)) void
9360 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
9361 {
9362         if (idx > MAX_RX_BD)
9363                 /* Index out of range. */
9364                 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
9365         else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
9366                 /* RX Chain page pointer. */
9367                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
9368                     "pointer\n", idx, rxbd->rx_bd_haddr_hi,
9369                     rxbd->rx_bd_haddr_lo);
9370         else
9371                 /* Normal rx_bd entry. */
9372                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
9373                     "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi,
9374                     rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len,
9375                     rxbd->rx_bd_flags);
9376 }
9377
9378
9379 #ifdef BCE_JUMBO_HDRSPLIT
9380 /****************************************************************************/
9381 /* Prints out a rx_bd structure in the page chain.                          */
9382 /*                                                                          */
9383 /* Returns:                                                                 */
9384 /*   Nothing.                                                               */
9385 /****************************************************************************/
9386 static __attribute__ ((noinline)) void
9387 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
9388 {
9389         if (idx > MAX_PG_BD)
9390                 /* Index out of range. */
9391                 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
9392         else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
9393                 /* Page Chain page pointer. */
9394                 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
9395                         idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
9396         else
9397                 /* Normal rx_bd entry. */
9398                 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
9399                         "flags = 0x%08X\n", idx,
9400                         pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
9401                         pgbd->rx_bd_len, pgbd->rx_bd_flags);
9402 }
9403 #endif
9404
9405
9406 /****************************************************************************/
9407 /* Prints out a l2_fhdr structure.                                          */
9408 /*                                                                          */
9409 /* Returns:                                                                 */
9410 /*   Nothing.                                                               */
9411 /****************************************************************************/
9412 static __attribute__ ((noinline)) void
9413 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
9414 {
9415         BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
9416                 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
9417                 "tcp_udp_xsum = 0x%04X\n", idx,
9418                 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
9419                 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
9420                 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
9421 }
9422
9423
9424 /****************************************************************************/
9425 /* Prints out context memory info.  (Only useful for CID 0 to 16.)          */
9426 /*                                                                          */
9427 /* Returns:                                                                 */
9428 /*   Nothing.                                                               */
9429 /****************************************************************************/
9430 static __attribute__ ((noinline)) void
9431 bce_dump_ctx(struct bce_softc *sc, u16 cid)
9432 {
9433         if (cid > TX_CID) {
9434                 BCE_PRINTF(" Unknown CID\n");
9435                 return;
9436         }
9437
9438         BCE_PRINTF(
9439             "----------------------------"
9440             "    CTX Data    "
9441             "----------------------------\n");
9442
9443         BCE_PRINTF("     0x%04X - (CID) Context ID\n", cid);
9444
9445         if (cid == RX_CID) {
9446                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
9447                    "producer index\n",
9448                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX));
9449                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host "
9450                     "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
9451                     BCE_L2CTX_RX_HOST_BSEQ));
9452                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
9453                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ));
9454                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
9455                     "descriptor address\n",
9456                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI));
9457                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
9458                     "descriptor address\n",
9459                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO));
9460                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer "
9461                     "index\n", CTX_RD(sc, GET_CID_ADDR(cid),
9462                     BCE_L2CTX_RX_NX_BDIDX));
9463                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
9464                     "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
9465                     BCE_L2CTX_RX_HOST_PG_BDIDX));
9466                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
9467                     "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid),
9468                     BCE_L2CTX_RX_PG_BUF_SIZE));
9469                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
9470                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
9471                     BCE_L2CTX_RX_NX_PG_BDHADDR_HI));
9472                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
9473                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
9474                     BCE_L2CTX_RX_NX_PG_BDHADDR_LO));
9475                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
9476                     "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
9477                     BCE_L2CTX_RX_NX_PG_BDIDX));
9478         } else if (cid == TX_CID) {
9479                 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
9480                     (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
9481                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
9482                             CTX_RD(sc, GET_CID_ADDR(cid),
9483                             BCE_L2CTX_TX_TYPE_XI));
9484                         BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx "
9485                             "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid),
9486                             BCE_L2CTX_TX_CMD_TYPE_XI));
9487                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) "
9488                             "h/w buffer descriptor address\n",
9489                             CTX_RD(sc, GET_CID_ADDR(cid),
9490                             BCE_L2CTX_TX_TBDR_BHADDR_HI_XI));
9491                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) "
9492                             "h/w buffer descriptor address\n",
9493                             CTX_RD(sc, GET_CID_ADDR(cid),
9494                             BCE_L2CTX_TX_TBDR_BHADDR_LO_XI));
9495                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) "
9496                             "host producer index\n",
9497                             CTX_RD(sc, GET_CID_ADDR(cid),
9498                             BCE_L2CTX_TX_HOST_BIDX_XI));
9499                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) "
9500                             "host byte sequence\n",
9501                             CTX_RD(sc, GET_CID_ADDR(cid),
9502                             BCE_L2CTX_TX_HOST_BSEQ_XI));
9503                 } else {
9504                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
9505                             CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE));
9506                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
9507                             CTX_RD(sc, GET_CID_ADDR(cid),
9508                             BCE_L2CTX_TX_CMD_TYPE));
9509                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) "
9510                             "h/w buffer descriptor address\n",
9511                             CTX_RD(sc, GET_CID_ADDR(cid),
9512                             BCE_L2CTX_TX_TBDR_BHADDR_HI));
9513                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) "
9514                             "h/w buffer descriptor address\n",
9515                             CTX_RD(sc, GET_CID_ADDR(cid),
9516                             BCE_L2CTX_TX_TBDR_BHADDR_LO));
9517                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host "
9518                             "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
9519                             BCE_L2CTX_TX_HOST_BIDX));
9520                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
9521                             "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
9522                             BCE_L2CTX_TX_HOST_BSEQ));
9523                 }
9524         }
9525
9526         BCE_PRINTF(
9527            "----------------------------"
9528            "    Raw CTX     "
9529            "----------------------------\n");
9530
9531         for (int i = 0x0; i < 0x300; i += 0x10) {
9532                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
9533                    CTX_RD(sc, GET_CID_ADDR(cid), i),
9534                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
9535                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
9536                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
9537         }
9538
9539
9540         BCE_PRINTF(
9541            "----------------------------"
9542            "----------------"
9543            "----------------------------\n");
9544 }
9545
9546
9547 /****************************************************************************/
9548 /* Prints out the FTQ data.                                                 */
9549 /*                                                                          */
9550 /* Returns:                                                                */
9551 /*   Nothing.                                                               */
9552 /****************************************************************************/
9553 static __attribute__ ((noinline)) void
9554 bce_dump_ftqs(struct bce_softc *sc)
9555 {
9556         u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
9557
9558         BCE_PRINTF(
9559             "----------------------------"
9560             "    FTQ Data    "
9561             "----------------------------\n");
9562
9563         BCE_PRINTF("   FTQ    Command    Control   Depth_Now  "
9564             "Max_Depth  Valid_Cnt \n");
9565         BCE_PRINTF(" ------- ---------- ---------- ---------- "
9566             "---------- ----------\n");
9567
9568         /* Setup the generic statistic counters for the FTQ valid count. */
9569         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
9570             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT  << 16) |
9571             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT   <<  8) |
9572             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT);
9573         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
9574
9575         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT  << 24) |
9576             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT  << 16) |
9577             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT <<  8) |
9578             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT);
9579         REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
9580
9581         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT  << 24) |
9582             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT  << 16) |
9583             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT   <<  8) |
9584             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT);
9585         REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
9586
9587         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT   << 24) |
9588             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT  << 16) |
9589             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT  <<  8) |
9590             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT);
9591         REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
9592
9593         /* Input queue to the Receive Lookup state machine */
9594         cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
9595         ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
9596         cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
9597         max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
9598         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
9599         BCE_PRINTF(" RLUP    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9600             cmd, ctl, cur_depth, max_depth, valid_cnt);
9601
9602         /* Input queue to the Receive Processor */
9603         cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
9604         ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
9605         cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
9606         max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
9607         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
9608         BCE_PRINTF(" RXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9609             cmd, ctl, cur_depth, max_depth, valid_cnt);
9610
9611         /* Input queue to the Recevie Processor */
9612         cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
9613         ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
9614         cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
9615         max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
9616         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
9617         BCE_PRINTF(" RXPC    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9618             cmd, ctl, cur_depth, max_depth, valid_cnt);
9619
9620         /* Input queue to the Receive Virtual to Physical state machine */
9621         cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
9622         ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
9623         cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
9624         max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
9625         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
9626         BCE_PRINTF(" RV2PP   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9627             cmd, ctl, cur_depth, max_depth, valid_cnt);
9628
9629         /* Input queue to the Recevie Virtual to Physical state machine */
9630         cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
9631         ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
9632         cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
9633         max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
9634         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
9635         BCE_PRINTF(" RV2PM   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9636             cmd, ctl, cur_depth, max_depth, valid_cnt);
9637
9638         /* Input queue to the Receive Virtual to Physical state machine */
9639         cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
9640         ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
9641         cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
9642         max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
9643         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
9644         BCE_PRINTF(" RV2PT   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9645             cmd, ctl, cur_depth, max_depth, valid_cnt);
9646
9647         /* Input queue to the Receive DMA state machine */
9648         cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
9649         ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
9650         cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
9651         max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
9652         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
9653         BCE_PRINTF(" RDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9654             cmd, ctl, cur_depth, max_depth, valid_cnt);
9655
9656         /* Input queue to the Transmit Scheduler state machine */
9657         cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
9658         ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
9659         cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
9660         max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
9661         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
9662         BCE_PRINTF(" TSCH    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9663             cmd, ctl, cur_depth, max_depth, valid_cnt);
9664
9665         /* Input queue to the Transmit Buffer Descriptor state machine */
9666         cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
9667         ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
9668         cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
9669         max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
9670         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
9671         BCE_PRINTF(" TBDR    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9672             cmd, ctl, cur_depth, max_depth, valid_cnt);
9673
9674         /* Input queue to the Transmit Processor */
9675         cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
9676         ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
9677         cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
9678         max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
9679         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
9680         BCE_PRINTF(" TXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9681             cmd, ctl, cur_depth, max_depth, valid_cnt);
9682
9683         /* Input queue to the Transmit DMA state machine */
9684         cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
9685         ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
9686         cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
9687         max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
9688         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
9689         BCE_PRINTF(" TDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9690             cmd, ctl, cur_depth, max_depth, valid_cnt);
9691
9692         /* Input queue to the Transmit Patch-Up Processor */
9693         cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
9694         ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
9695         cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
9696         max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
9697         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
9698         BCE_PRINTF(" TPAT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9699             cmd, ctl, cur_depth, max_depth, valid_cnt);
9700
9701         /* Input queue to the Transmit Assembler state machine */
9702         cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
9703         ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
9704         cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
9705         max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
9706         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
9707         BCE_PRINTF(" TAS     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9708             cmd, ctl, cur_depth, max_depth, valid_cnt);
9709
9710         /* Input queue to the Completion Processor */
9711         cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
9712         ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
9713         cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
9714         max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
9715         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
9716         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9717             cmd, ctl, cur_depth, max_depth, valid_cnt);
9718
9719         /* Input queue to the Completion Processor */
9720         cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
9721         ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
9722         cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
9723         max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
9724         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
9725         BCE_PRINTF(" COMT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9726             cmd, ctl, cur_depth, max_depth, valid_cnt);
9727
9728         /* Input queue to the Completion Processor */
9729         cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
9730         ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
9731         cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
9732         max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
9733         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
9734         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9735             cmd, ctl, cur_depth, max_depth, valid_cnt);
9736
9737         /* Setup the generic statistic counters for the FTQ valid count. */
9738         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT  << 16) |
9739             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT  <<  8) |
9740             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT);
9741
9742         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
9743             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
9744                 val = val |
9745                     (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI <<
9746                      24);
9747         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
9748
9749         /* Input queue to the Management Control Processor */
9750         cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
9751         ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
9752         cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
9753         max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
9754         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
9755         BCE_PRINTF(" MCP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9756             cmd, ctl, cur_depth, max_depth, valid_cnt);
9757
9758         /* Input queue to the Command Processor */
9759         cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
9760         ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
9761         cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
9762         max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
9763         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
9764         BCE_PRINTF(" CP      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9765             cmd, ctl, cur_depth, max_depth, valid_cnt);
9766
9767         /* Input queue to the Completion Scheduler state machine */
9768         cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
9769         ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
9770         cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
9771         max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
9772         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
9773         BCE_PRINTF(" CS      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9774             cmd, ctl, cur_depth, max_depth, valid_cnt);
9775
9776         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
9777             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
9778                 /* Input queue to the RV2P Command Scheduler */
9779                 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);
9780                 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);
9781                 cur_depth = (ctl & 0xFFC00000) >> 22;
9782                 max_depth = (ctl & 0x003FF000) >> 12;
9783                 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
9784                 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9785                     cmd, ctl, cur_depth, max_depth, valid_cnt);
9786         }
9787
9788         BCE_PRINTF(
9789             "----------------------------"
9790             "----------------"
9791             "----------------------------\n");
9792 }
9793
9794
9795 /****************************************************************************/
9796 /* Prints out the TX chain.                                                 */
9797 /*                                                                          */
9798 /* Returns:                                                                 */
9799 /*   Nothing.                                                               */
9800 /****************************************************************************/
9801 static __attribute__ ((noinline)) void
9802 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
9803 {
9804         struct tx_bd *txbd;
9805
9806         /* First some info about the tx_bd chain structure. */
9807         BCE_PRINTF(
9808             "----------------------------"
9809             "  tx_bd  chain  "
9810             "----------------------------\n");
9811
9812         BCE_PRINTF("page size      = 0x%08X, tx chain pages        = 0x%08X\n",
9813             (u32) BCM_PAGE_SIZE, (u32) TX_PAGES);
9814         BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
9815             (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE);
9816         BCE_PRINTF("total tx_bd    = 0x%08X\n", (u32) TOTAL_TX_BD);
9817
9818         BCE_PRINTF(
9819             "----------------------------"
9820             "   tx_bd data   "
9821             "----------------------------\n");
9822
9823         /* Now print out a decoded list of TX buffer descriptors. */
9824         for (int i = 0; i < count; i++) {
9825                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
9826                 bce_dump_txbd(sc, tx_prod, txbd);
9827                 tx_prod++;
9828         }
9829
9830         BCE_PRINTF(
9831             "----------------------------"
9832             "----------------"
9833             "----------------------------\n");
9834 }
9835
9836
9837 /****************************************************************************/
9838 /* Prints out the RX chain.                                                 */
9839 /*                                                                          */
9840 /* Returns:                                                                 */
9841 /*   Nothing.                                                               */
9842 /****************************************************************************/
9843 static __attribute__ ((noinline)) void
9844 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count)
9845 {
9846         struct rx_bd *rxbd;
9847
9848         /* First some info about the rx_bd chain structure. */
9849         BCE_PRINTF(
9850             "----------------------------"
9851             "  rx_bd  chain  "
9852             "----------------------------\n");
9853
9854         BCE_PRINTF("page size      = 0x%08X, rx chain pages        = 0x%08X\n",
9855             (u32) BCM_PAGE_SIZE, (u32) RX_PAGES);
9856
9857         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
9858             (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE);
9859
9860         BCE_PRINTF("total rx_bd    = 0x%08X\n", (u32) TOTAL_RX_BD);
9861
9862         BCE_PRINTF(
9863             "----------------------------"
9864             "   rx_bd data   "
9865             "----------------------------\n");
9866
9867         /* Now print out the rx_bd's themselves. */
9868         for (int i = 0; i < count; i++) {
9869                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
9870                 bce_dump_rxbd(sc, rx_prod, rxbd);
9871                 rx_prod = RX_CHAIN_IDX(rx_prod + 1);
9872         }
9873
9874         BCE_PRINTF(
9875             "----------------------------"
9876             "----------------"
9877             "----------------------------\n");
9878 }
9879
9880
9881 #ifdef BCE_JUMBO_HDRSPLIT
9882 /****************************************************************************/
9883 /* Prints out the page chain.                                               */
9884 /*                                                                          */
9885 /* Returns:                                                                 */
9886 /*   Nothing.                                                               */
9887 /****************************************************************************/
9888 static __attribute__ ((noinline)) void
9889 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
9890 {
9891         struct rx_bd *pgbd;
9892
9893         /* First some info about the page chain structure. */
9894         BCE_PRINTF(
9895             "----------------------------"
9896             "   page chain   "
9897             "----------------------------\n");
9898
9899         BCE_PRINTF("page size      = 0x%08X, pg chain pages        = 0x%08X\n",
9900             (u32) BCM_PAGE_SIZE, (u32) PG_PAGES);
9901
9902         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
9903             (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE);
9904
9905         BCE_PRINTF("total rx_bd    = 0x%08X, max_pg_bd             = 0x%08X\n",
9906             (u32) TOTAL_PG_BD, (u32) MAX_PG_BD);
9907
9908         BCE_PRINTF(
9909             "----------------------------"
9910             "   page data    "
9911             "----------------------------\n");
9912
9913         /* Now print out the rx_bd's themselves. */
9914         for (int i = 0; i < count; i++) {
9915                 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)];
9916                 bce_dump_pgbd(sc, pg_prod, pgbd);
9917                 pg_prod = PG_CHAIN_IDX(pg_prod + 1);
9918         }
9919
9920         BCE_PRINTF(
9921             "----------------------------"
9922             "----------------"
9923             "----------------------------\n");
9924 }
9925 #endif
9926
9927
9928 #define BCE_PRINT_RX_CONS(arg)                                          \
9929 if (sblk->status_rx_quick_consumer_index##arg)                          \
9930         BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n",      \
9931             sblk->status_rx_quick_consumer_index##arg, (u16)            \
9932             RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg),    \
9933             arg);
9934
9935
9936 #define BCE_PRINT_TX_CONS(arg)                                          \
9937 if (sblk->status_tx_quick_consumer_index##arg)                          \
9938         BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n",      \
9939             sblk->status_tx_quick_consumer_index##arg, (u16)            \
9940             TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg),    \
9941             arg);
9942
9943 /****************************************************************************/
9944 /* Prints out the status block from host memory.                            */
9945 /*                                                                          */
9946 /* Returns:                                                                 */
9947 /*   Nothing.                                                               */
9948 /****************************************************************************/
9949 static __attribute__ ((noinline)) void
9950 bce_dump_status_block(struct bce_softc *sc)
9951 {
9952         struct status_block *sblk;
9953
9954         sblk = sc->status_block;
9955
9956         BCE_PRINTF(
9957             "----------------------------"
9958             "  Status Block  "
9959             "----------------------------\n");
9960
9961         /* Theses indices are used for normal L2 drivers. */
9962         BCE_PRINTF("    0x%08X - attn_bits\n",
9963             sblk->status_attn_bits);
9964
9965         BCE_PRINTF("    0x%08X - attn_bits_ack\n",
9966             sblk->status_attn_bits_ack);
9967
9968         BCE_PRINT_RX_CONS(0);
9969         BCE_PRINT_TX_CONS(0)
9970
9971         BCE_PRINTF("        0x%04X - status_idx\n", sblk->status_idx);
9972
9973         /* Theses indices are not used for normal L2 drivers. */
9974         BCE_PRINT_RX_CONS(1);   BCE_PRINT_RX_CONS(2);   BCE_PRINT_RX_CONS(3);
9975         BCE_PRINT_RX_CONS(4);   BCE_PRINT_RX_CONS(5);   BCE_PRINT_RX_CONS(6);
9976         BCE_PRINT_RX_CONS(7);   BCE_PRINT_RX_CONS(8);   BCE_PRINT_RX_CONS(9);
9977         BCE_PRINT_RX_CONS(10);  BCE_PRINT_RX_CONS(11);  BCE_PRINT_RX_CONS(12);
9978         BCE_PRINT_RX_CONS(13);  BCE_PRINT_RX_CONS(14);  BCE_PRINT_RX_CONS(15);
9979
9980         BCE_PRINT_TX_CONS(1);   BCE_PRINT_TX_CONS(2);   BCE_PRINT_TX_CONS(3);
9981
9982         if (sblk->status_completion_producer_index ||
9983             sblk->status_cmd_consumer_index)
9984                 BCE_PRINTF("com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
9985                     sblk->status_completion_producer_index,
9986                     sblk->status_cmd_consumer_index);
9987
9988         BCE_PRINTF(
9989             "----------------------------"
9990             "----------------"
9991             "----------------------------\n");
9992 }
9993
9994
9995 #define BCE_PRINT_64BIT_STAT(arg)                               \
9996 if (sblk->arg##_lo || sblk->arg##_hi)                           \
9997         BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi,        \
9998             sblk->arg##_lo, #arg);
9999
10000 #define BCE_PRINT_32BIT_STAT(arg)                               \
10001 if (sblk->arg)                                                  \
10002         BCE_PRINTF("         0x%08X : %s\n",                    \
10003             sblk->arg, #arg);
10004
10005 /****************************************************************************/
10006 /* Prints out the statistics block from host memory.                        */
10007 /*                                                                          */
10008 /* Returns:                                                                 */
10009 /*   Nothing.                                                               */
10010 /****************************************************************************/
10011 static __attribute__ ((noinline)) void
10012 bce_dump_stats_block(struct bce_softc *sc)
10013 {
10014         struct statistics_block *sblk;
10015
10016         sblk = sc->stats_block;
10017
10018         BCE_PRINTF(
10019             "---------------"
10020             " Stats Block  (All Stats Not Shown Are 0) "
10021             "---------------\n");
10022
10023         BCE_PRINT_64BIT_STAT(stat_IfHCInOctets);
10024         BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets);
10025         BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets);
10026         BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets);
10027         BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts);
10028         BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts);
10029         BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts);
10030         BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts);
10031         BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts);
10032         BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts);
10033         BCE_PRINT_32BIT_STAT(
10034             stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
10035         BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors);
10036         BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors);
10037         BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors);
10038         BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames);
10039         BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames);
10040         BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions);
10041         BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions);
10042         BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions);
10043         BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions);
10044         BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments);
10045         BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers);
10046         BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts);
10047         BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts);
10048         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets);
10049         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets);
10050         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets);
10051         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets);
10052         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets);
10053         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets);
10054         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets);
10055         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets);
10056         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets);
10057         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets);
10058         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets);
10059         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets);
10060         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets);
10061         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets);
10062         BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived);
10063         BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived);
10064         BCE_PRINT_32BIT_STAT(stat_OutXonSent);
10065         BCE_PRINT_32BIT_STAT(stat_OutXoffSent);
10066         BCE_PRINT_32BIT_STAT(stat_FlowControlDone);
10067         BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived);
10068         BCE_PRINT_32BIT_STAT(stat_XoffStateEntered);
10069         BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards);
10070         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards);
10071         BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards);
10072         BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards);
10073         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit);
10074         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards);
10075         BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards);
10076         BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards);
10077         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit);
10078
10079         BCE_PRINTF(
10080             "----------------------------"
10081             "----------------"
10082             "----------------------------\n");
10083 }
10084
10085
10086 /****************************************************************************/
10087 /* Prints out a summary of the driver state.                                */
10088 /*                                                                          */
10089 /* Returns:                                                                 */
10090 /*   Nothing.                                                               */
10091 /****************************************************************************/
10092 static __attribute__ ((noinline)) void
10093 bce_dump_driver_state(struct bce_softc *sc)
10094 {
10095         u32 val_hi, val_lo;
10096
10097         BCE_PRINTF(
10098             "-----------------------------"
10099             " Driver State "
10100             "-----------------------------\n");
10101
10102         val_hi = BCE_ADDR_HI(sc);
10103         val_lo = BCE_ADDR_LO(sc);
10104         BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual "
10105             "address\n", val_hi, val_lo);
10106
10107         val_hi = BCE_ADDR_HI(sc->bce_vhandle);
10108         val_lo = BCE_ADDR_LO(sc->bce_vhandle);
10109         BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual "
10110             "address\n", val_hi, val_lo);
10111
10112         val_hi = BCE_ADDR_HI(sc->status_block);
10113         val_lo = BCE_ADDR_LO(sc->status_block);
10114         BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block "
10115             "virtual address\n",        val_hi, val_lo);
10116
10117         val_hi = BCE_ADDR_HI(sc->stats_block);
10118         val_lo = BCE_ADDR_LO(sc->stats_block);
10119         BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block "
10120             "virtual address\n", val_hi, val_lo);
10121
10122         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
10123         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
10124         BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
10125             "virtual adddress\n", val_hi, val_lo);
10126
10127         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
10128         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
10129         BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
10130             "virtual address\n", val_hi, val_lo);
10131
10132 #ifdef BCE_JUMBO_HDRSPLIT
10133         val_hi = BCE_ADDR_HI(sc->pg_bd_chain);
10134         val_lo = BCE_ADDR_LO(sc->pg_bd_chain);
10135         BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain "
10136             "virtual address\n", val_hi, val_lo);
10137 #endif
10138
10139         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
10140         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
10141         BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
10142             "virtual address\n",        val_hi, val_lo);
10143
10144         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
10145         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
10146         BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
10147             "virtual address\n", val_hi, val_lo);
10148
10149 #ifdef BCE_JUMBO_HDRSPLIT
10150         val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
10151         val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
10152         BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain "
10153             "virtual address\n", val_hi, val_lo);
10154 #endif
10155
10156         BCE_PRINTF("         0x%08X - (sc->interrupts_generated) "
10157             "h/w intrs\n", sc->interrupts_generated);
10158
10159         BCE_PRINTF("         0x%08X - (sc->interrupts_rx) "
10160             "rx interrupts handled\n", sc->interrupts_rx);
10161
10162         BCE_PRINTF("         0x%08X - (sc->interrupts_tx) "
10163             "tx interrupts handled\n", sc->interrupts_tx);
10164
10165         BCE_PRINTF("         0x%08X - (sc->phy_interrupts) "
10166             "phy interrupts handled\n", sc->phy_interrupts);
10167
10168         BCE_PRINTF("         0x%08X - (sc->last_status_idx) "
10169             "status block index\n", sc->last_status_idx);
10170
10171         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_prod) tx producer "
10172             "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod));
10173
10174         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_cons) tx consumer "
10175             "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons));
10176
10177         BCE_PRINTF("         0x%08X - (sc->tx_prod_bseq) tx producer "
10178             "byte seq index\n", sc->tx_prod_bseq);
10179
10180         BCE_PRINTF("         0x%08X - (sc->debug_tx_mbuf_alloc) tx "
10181             "mbufs allocated\n", sc->debug_tx_mbuf_alloc);
10182
10183         BCE_PRINTF("         0x%08X - (sc->used_tx_bd) used "
10184             "tx_bd's\n", sc->used_tx_bd);
10185
10186         BCE_PRINTF("0x%08X/%08X - (sc->tx_hi_watermark) tx hi "
10187             "watermark\n", sc->tx_hi_watermark, sc->max_tx_bd);
10188
10189         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_prod) rx producer "
10190             "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod));
10191
10192         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_cons) rx consumer "
10193             "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons));
10194
10195         BCE_PRINTF("         0x%08X - (sc->rx_prod_bseq) rx producer "
10196             "byte seq index\n", sc->rx_prod_bseq);
10197
10198         BCE_PRINTF("         0x%08X - (sc->debug_rx_mbuf_alloc) rx "
10199             "mbufs allocated\n", sc->debug_rx_mbuf_alloc);
10200
10201         BCE_PRINTF("         0x%08X - (sc->free_rx_bd) free "
10202             "rx_bd's\n", sc->free_rx_bd);
10203
10204 #ifdef BCE_JUMBO_HDRSPLIT
10205         BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_prod) page producer "
10206             "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod));
10207
10208         BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_cons) page consumer "
10209             "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons));
10210
10211         BCE_PRINTF("         0x%08X - (sc->debug_pg_mbuf_alloc) page "
10212             "mbufs allocated\n", sc->debug_pg_mbuf_alloc);
10213
10214         BCE_PRINTF("         0x%08X - (sc->free_pg_bd) free page "
10215             "rx_bd's\n", sc->free_pg_bd);
10216
10217         BCE_PRINTF("0x%08X/%08X - (sc->pg_low_watermark) page low "
10218             "watermark\n", sc->pg_low_watermark, sc->max_pg_bd);
10219 #endif
10220
10221         BCE_PRINTF("         0x%08X - (sc->mbuf_alloc_failed_count) "
10222             "mbuf alloc failures\n", sc->mbuf_alloc_failed_count);
10223
10224         BCE_PRINTF("         0x%08X - (sc->bce_flags) "
10225             "bce mac flags\n", sc->bce_flags);
10226
10227         BCE_PRINTF("         0x%08X - (sc->bce_phy_flags) "
10228             "bce phy flags\n", sc->bce_phy_flags);
10229
10230         BCE_PRINTF(
10231             "----------------------------"
10232             "----------------"
10233             "----------------------------\n");
10234 }
10235
10236
10237 /****************************************************************************/
10238 /* Prints out the hardware state through a summary of important register,   */
10239 /* followed by a complete register dump.                                    */
10240 /*                                                                          */
10241 /* Returns:                                                                 */
10242 /*   Nothing.                                                               */
10243 /****************************************************************************/
10244 static __attribute__ ((noinline)) void
10245 bce_dump_hw_state(struct bce_softc *sc)
10246 {
10247         u32 val;
10248
10249         BCE_PRINTF(
10250             "----------------------------"
10251             " Hardware State "
10252             "----------------------------\n");
10253
10254         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
10255
10256         val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
10257         BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
10258             val, BCE_MISC_ENABLE_STATUS_BITS);
10259
10260         val = REG_RD(sc, BCE_DMA_STATUS);
10261         BCE_PRINTF("0x%08X - (0x%06X) dma_status\n",
10262             val, BCE_DMA_STATUS);
10263
10264         val = REG_RD(sc, BCE_CTX_STATUS);
10265         BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n",
10266             val, BCE_CTX_STATUS);
10267
10268         val = REG_RD(sc, BCE_EMAC_STATUS);
10269         BCE_PRINTF("0x%08X - (0x%06X) emac_status\n",
10270             val, BCE_EMAC_STATUS);
10271
10272         val = REG_RD(sc, BCE_RPM_STATUS);
10273         BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n",
10274             val, BCE_RPM_STATUS);
10275
10276         /* ToDo: Create a #define for this constant. */
10277         val = REG_RD(sc, 0x2004);
10278         BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n",
10279             val, 0x2004);
10280
10281         val = REG_RD(sc, BCE_RV2P_STATUS);
10282         BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n",
10283             val, BCE_RV2P_STATUS);
10284
10285         /* ToDo: Create a #define for this constant. */
10286         val = REG_RD(sc, 0x2c04);
10287         BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n",
10288             val, 0x2c04);
10289
10290         val = REG_RD(sc, BCE_TBDR_STATUS);
10291         BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n",
10292             val, BCE_TBDR_STATUS);
10293
10294         val = REG_RD(sc, BCE_TDMA_STATUS);
10295         BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n",
10296             val, BCE_TDMA_STATUS);
10297
10298         val = REG_RD(sc, BCE_HC_STATUS);
10299         BCE_PRINTF("0x%08X - (0x%06X) hc_status\n",
10300             val, BCE_HC_STATUS);
10301
10302         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
10303         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
10304             val, BCE_TXP_CPU_STATE);
10305
10306         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
10307         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
10308             val, BCE_TPAT_CPU_STATE);
10309
10310         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
10311         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
10312             val, BCE_RXP_CPU_STATE);
10313
10314         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
10315         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
10316             val, BCE_COM_CPU_STATE);
10317
10318         val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
10319         BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n",
10320             val, BCE_MCP_CPU_STATE);
10321
10322         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
10323         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
10324             val, BCE_CP_CPU_STATE);
10325
10326         BCE_PRINTF(
10327             "----------------------------"
10328             "----------------"
10329             "----------------------------\n");
10330
10331         BCE_PRINTF(
10332             "----------------------------"
10333             " Register  Dump "
10334             "----------------------------\n");
10335
10336         for (int i = 0x400; i < 0x8000; i += 0x10) {
10337                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
10338                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
10339                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
10340         }
10341
10342         BCE_PRINTF(
10343             "----------------------------"
10344             "----------------"
10345             "----------------------------\n");
10346 }
10347
10348
10349 /****************************************************************************/
10350 /* Prints out the mailbox queue registers.                                  */
10351 /*                                                                          */
10352 /* Returns:                                                                 */
10353 /*   Nothing.                                                               */
10354 /****************************************************************************/
10355 static __attribute__ ((noinline)) void
10356 bce_dump_mq_regs(struct bce_softc *sc)
10357 {
10358         BCE_PRINTF(
10359             "----------------------------"
10360             "    MQ Regs     "
10361             "----------------------------\n");
10362
10363         BCE_PRINTF(
10364             "----------------------------"
10365             "----------------"
10366             "----------------------------\n");
10367
10368         for (int i = 0x3c00; i < 0x4000; i += 0x10) {
10369                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
10370                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
10371                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
10372         }
10373
10374         BCE_PRINTF(
10375             "----------------------------"
10376             "----------------"
10377             "----------------------------\n");
10378 }
10379
10380
10381 /****************************************************************************/
10382 /* Prints out the bootcode state.                                           */
10383 /*                                                                          */
10384 /* Returns:                                                                 */
10385 /*   Nothing.                                                               */
10386 /****************************************************************************/
10387 static __attribute__ ((noinline)) void
10388 bce_dump_bc_state(struct bce_softc *sc)
10389 {
10390         u32 val;
10391
10392         BCE_PRINTF(
10393             "----------------------------"
10394             " Bootcode State "
10395             "----------------------------\n");
10396
10397         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
10398
10399         val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE);
10400         BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
10401             val, BCE_BC_RESET_TYPE);
10402
10403         val = bce_shmem_rd(sc, BCE_BC_STATE);
10404         BCE_PRINTF("0x%08X - (0x%06X) state\n",
10405             val, BCE_BC_STATE);
10406
10407         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
10408         BCE_PRINTF("0x%08X - (0x%06X) condition\n",
10409             val, BCE_BC_STATE_CONDITION);
10410
10411         val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD);
10412         BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
10413             val, BCE_BC_STATE_DEBUG_CMD);
10414
10415         BCE_PRINTF(
10416             "----------------------------"
10417             "----------------"
10418             "----------------------------\n");
10419 }
10420
10421
10422 /****************************************************************************/
10423 /* Prints out the TXP processor state.                                      */
10424 /*                                                                          */
10425 /* Returns:                                                                 */
10426 /*   Nothing.                                                               */
10427 /****************************************************************************/
10428 static __attribute__ ((noinline)) void
10429 bce_dump_txp_state(struct bce_softc *sc, int regs)
10430 {
10431         u32 val;
10432         u32 fw_version[3];
10433
10434         BCE_PRINTF(
10435             "----------------------------"
10436             "   TXP  State   "
10437             "----------------------------\n");
10438
10439         for (int i = 0; i < 3; i++)
10440                 fw_version[i] = htonl(REG_RD_IND(sc,
10441                     (BCE_TXP_SCRATCH + 0x10 + i * 4)));
10442         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
10443
10444         val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
10445         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n",
10446             val, BCE_TXP_CPU_MODE);
10447
10448         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
10449         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
10450             val, BCE_TXP_CPU_STATE);
10451
10452         val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
10453         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n",
10454             val, BCE_TXP_CPU_EVENT_MASK);
10455
10456         if (regs) {
10457                 BCE_PRINTF(
10458                     "----------------------------"
10459                     " Register  Dump "
10460                     "----------------------------\n");
10461
10462                 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
10463                         /* Skip the big blank spaces */
10464                         if (i < 0x454000 && i > 0x5ffff)
10465                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
10466                                     "0x%08X 0x%08X\n", i,
10467                                     REG_RD_IND(sc, i),
10468                                     REG_RD_IND(sc, i + 0x4),
10469                                     REG_RD_IND(sc, i + 0x8),
10470                                     REG_RD_IND(sc, i + 0xC));
10471                 }
10472         }
10473
10474         BCE_PRINTF(
10475             "----------------------------"
10476             "----------------"
10477             "----------------------------\n");
10478 }
10479
10480
10481 /****************************************************************************/
10482 /* Prints out the RXP processor state.                                      */
10483 /*                                                                          */
10484 /* Returns:                                                                 */
10485 /*   Nothing.                                                               */
10486 /****************************************************************************/
10487 static __attribute__ ((noinline)) void
10488 bce_dump_rxp_state(struct bce_softc *sc, int regs)
10489 {
10490         u32 val;
10491         u32 fw_version[3];
10492
10493         BCE_PRINTF(
10494             "----------------------------"
10495             "   RXP  State   "
10496             "----------------------------\n");
10497
10498         for (int i = 0; i < 3; i++)
10499                 fw_version[i] = htonl(REG_RD_IND(sc,
10500                     (BCE_RXP_SCRATCH + 0x10 + i * 4)));
10501
10502         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
10503
10504         val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
10505         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n",
10506             val, BCE_RXP_CPU_MODE);
10507
10508         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
10509         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
10510             val, BCE_RXP_CPU_STATE);
10511
10512         val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
10513         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n",
10514             val, BCE_RXP_CPU_EVENT_MASK);
10515
10516         if (regs) {
10517                 BCE_PRINTF(
10518                     "----------------------------"
10519                     " Register  Dump "
10520                     "----------------------------\n");
10521
10522                 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
10523                         /* Skip the big blank sapces */
10524                         if (i < 0xc5400 && i > 0xdffff)
10525                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
10526                                     "0x%08X 0x%08X\n", i,
10527                                     REG_RD_IND(sc, i),
10528                                     REG_RD_IND(sc, i + 0x4),
10529                                     REG_RD_IND(sc, i + 0x8),
10530                                     REG_RD_IND(sc, i + 0xC));
10531                 }
10532         }
10533
10534         BCE_PRINTF(
10535             "----------------------------"
10536             "----------------"
10537             "----------------------------\n");
10538 }
10539
10540
10541 /****************************************************************************/
10542 /* Prints out the TPAT processor state.                                     */
10543 /*                                                                          */
10544 /* Returns:                                                                 */
10545 /*   Nothing.                                                               */
10546 /****************************************************************************/
10547 static __attribute__ ((noinline)) void
10548 bce_dump_tpat_state(struct bce_softc *sc, int regs)
10549 {
10550         u32 val;
10551         u32 fw_version[3];
10552
10553         BCE_PRINTF(
10554             "----------------------------"
10555             "   TPAT State   "
10556             "----------------------------\n");
10557
10558         for (int i = 0; i < 3; i++)
10559                 fw_version[i] = htonl(REG_RD_IND(sc,
10560                     (BCE_TPAT_SCRATCH + 0x410 + i * 4)));
10561
10562         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
10563
10564         val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
10565         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n",
10566             val, BCE_TPAT_CPU_MODE);
10567
10568         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
10569         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
10570             val, BCE_TPAT_CPU_STATE);
10571
10572         val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
10573         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n",
10574             val, BCE_TPAT_CPU_EVENT_MASK);
10575
10576         if (regs) {
10577                 BCE_PRINTF(
10578                     "----------------------------"
10579                     " Register  Dump "
10580                     "----------------------------\n");
10581
10582                 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
10583                         /* Skip the big blank spaces */
10584                         if (i < 0x854000 && i > 0x9ffff)
10585                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
10586                                     "0x%08X 0x%08X\n", i,
10587                                     REG_RD_IND(sc, i),
10588                                     REG_RD_IND(sc, i + 0x4),
10589                                     REG_RD_IND(sc, i + 0x8),
10590                                     REG_RD_IND(sc, i + 0xC));
10591                 }
10592         }
10593
10594         BCE_PRINTF(
10595                 "----------------------------"
10596                 "----------------"
10597                 "----------------------------\n");
10598 }
10599
10600
10601 /****************************************************************************/
10602 /* Prints out the Command Procesor (CP) state.                              */
10603 /*                                                                          */
10604 /* Returns:                                                                 */
10605 /*   Nothing.                                                               */
10606 /****************************************************************************/
10607 static __attribute__ ((noinline)) void
10608 bce_dump_cp_state(struct bce_softc *sc, int regs)
10609 {
10610         u32 val;
10611         u32 fw_version[3];
10612
10613         BCE_PRINTF(
10614             "----------------------------"
10615             "    CP State    "
10616             "----------------------------\n");
10617
10618         for (int i = 0; i < 3; i++)
10619                 fw_version[i] = htonl(REG_RD_IND(sc,
10620                     (BCE_CP_SCRATCH + 0x10 + i * 4)));
10621
10622         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
10623
10624         val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
10625         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n",
10626             val, BCE_CP_CPU_MODE);
10627
10628         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
10629         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
10630             val, BCE_CP_CPU_STATE);
10631
10632         val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
10633         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
10634             BCE_CP_CPU_EVENT_MASK);
10635
10636         if (regs) {
10637                 BCE_PRINTF(
10638                     "----------------------------"
10639                     " Register  Dump "
10640                     "----------------------------\n");
10641
10642                 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
10643                         /* Skip the big blank spaces */
10644                         if (i < 0x185400 && i > 0x19ffff)
10645                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
10646                                     "0x%08X 0x%08X\n", i,
10647                                     REG_RD_IND(sc, i),
10648                                     REG_RD_IND(sc, i + 0x4),
10649                                     REG_RD_IND(sc, i + 0x8),
10650                                     REG_RD_IND(sc, i + 0xC));
10651                 }
10652         }
10653
10654         BCE_PRINTF(
10655             "----------------------------"
10656             "----------------"
10657             "----------------------------\n");
10658 }
10659
10660
10661 /****************************************************************************/
10662 /* Prints out the Completion Procesor (COM) state.                          */
10663 /*                                                                          */
10664 /* Returns:                                                                 */
10665 /*   Nothing.                                                               */
10666 /****************************************************************************/
10667 static __attribute__ ((noinline)) void
10668 bce_dump_com_state(struct bce_softc *sc, int regs)
10669 {
10670         u32 val;
10671         u32 fw_version[4];
10672
10673         BCE_PRINTF(
10674             "----------------------------"
10675             "   COM State    "
10676             "----------------------------\n");
10677
10678         for (int i = 0; i < 3; i++)
10679                 fw_version[i] = htonl(REG_RD_IND(sc,
10680                     (BCE_COM_SCRATCH + 0x10 + i * 4)));
10681
10682         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
10683
10684         val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
10685         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n",
10686             val, BCE_COM_CPU_MODE);
10687
10688         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
10689         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
10690             val, BCE_COM_CPU_STATE);
10691
10692         val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
10693         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
10694             BCE_COM_CPU_EVENT_MASK);
10695
10696         if (regs) {
10697                 BCE_PRINTF(
10698                     "----------------------------"
10699                     " Register  Dump "
10700                     "----------------------------\n");
10701
10702                 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
10703                         BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
10704                             "0x%08X 0x%08X\n", i,
10705                             REG_RD_IND(sc, i),
10706                             REG_RD_IND(sc, i + 0x4),
10707                             REG_RD_IND(sc, i + 0x8),
10708                             REG_RD_IND(sc, i + 0xC));
10709                 }
10710         }
10711
10712         BCE_PRINTF(
10713                 "----------------------------"
10714                 "----------------"
10715                 "----------------------------\n");
10716 }
10717
10718
10719 /****************************************************************************/
10720 /* Prints out the Receive Virtual 2 Physical (RV2P) state.                  */
10721 /*                                                                          */
10722 /* Returns:                                                                 */
10723 /*   Nothing.                                                               */
10724 /****************************************************************************/
10725 static __attribute__ ((noinline)) void
10726 bce_dump_rv2p_state(struct bce_softc *sc)
10727 {
10728         u32 val, pc1, pc2, fw_ver_high, fw_ver_low;
10729
10730         BCE_PRINTF(
10731             "----------------------------"
10732             "   RV2P State   "
10733             "----------------------------\n");
10734
10735         /* Stall the RV2P processors. */
10736         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
10737         val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2;
10738         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
10739
10740         /* Read the firmware version. */
10741         val = 0x00000001;
10742         REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
10743         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
10744         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
10745             BCE_RV2P_INSTR_HIGH_HIGH;
10746         BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n",
10747             fw_ver_high, fw_ver_low);
10748
10749         val = 0x00000001;
10750         REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
10751         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
10752         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
10753             BCE_RV2P_INSTR_HIGH_HIGH;
10754         BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n",
10755             fw_ver_high, fw_ver_low);
10756
10757         /* Resume the RV2P processors. */
10758         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
10759         val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2);
10760         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
10761
10762         /* Fetch the program counter value. */
10763         val = 0x68007800;
10764         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
10765         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
10766         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
10767         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
10768         BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1);
10769         BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2);
10770
10771         /* Fetch the program counter value again to see if it is advancing. */
10772         val = 0x68007800;
10773         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
10774         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
10775         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
10776         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
10777         BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1);
10778         BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2);
10779
10780         BCE_PRINTF(
10781             "----------------------------"
10782             "----------------"
10783             "----------------------------\n");
10784 }
10785
10786
10787 /****************************************************************************/
10788 /* Prints out the driver state and then enters the debugger.                */
10789 /*                                                                          */
10790 /* Returns:                                                                 */
10791 /*   Nothing.                                                               */
10792 /****************************************************************************/
10793 static __attribute__ ((noinline)) void
10794 bce_breakpoint(struct bce_softc *sc)
10795 {
10796
10797         /*
10798          * Unreachable code to silence compiler warnings
10799          * about unused functions.
10800          */
10801         if (0) {
10802                 bce_freeze_controller(sc);
10803                 bce_unfreeze_controller(sc);
10804                 bce_dump_enet(sc, NULL);
10805                 bce_dump_txbd(sc, 0, NULL);
10806                 bce_dump_rxbd(sc, 0, NULL);
10807                 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD);
10808                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD);
10809                 bce_dump_l2fhdr(sc, 0, NULL);
10810                 bce_dump_ctx(sc, RX_CID);
10811                 bce_dump_ftqs(sc);
10812                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
10813                 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD);
10814                 bce_dump_status_block(sc);
10815                 bce_dump_stats_block(sc);
10816                 bce_dump_driver_state(sc);
10817                 bce_dump_hw_state(sc);
10818                 bce_dump_bc_state(sc);
10819                 bce_dump_txp_state(sc, 0);
10820                 bce_dump_rxp_state(sc, 0);
10821                 bce_dump_tpat_state(sc, 0);
10822                 bce_dump_cp_state(sc, 0);
10823                 bce_dump_com_state(sc, 0);
10824                 bce_dump_rv2p_state(sc);
10825
10826 #ifdef BCE_JUMBO_HDRSPLIT
10827                 bce_dump_pgbd(sc, 0, NULL);
10828                 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD);
10829                 bce_dump_pg_chain(sc, 0, USABLE_PG_BD);
10830 #endif
10831         }
10832
10833         bce_dump_status_block(sc);
10834         bce_dump_driver_state(sc);
10835
10836         /* Call the debugger. */
10837         breakpoint();
10838
10839         return;
10840 }
10841 #endif
10842