sys/dev/bce/if_bce.c

   1 /*-
   2  * Copyright (c) 2006-2010 Broadcom Corporation
   3  *      David Christensen <davidch@broadcom.com>.  All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  *
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  * 3. Neither the name of Broadcom Corporation nor the name of its contributors
  15  *    may be used to endorse or promote products derived from this software
  16  *    without specific prior written consent.
  17  *
  18  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
  19  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  20  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  21  * ARE DISCLAIMED.  IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
  22  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  23  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  24  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  25  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  26  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  27  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
  28  * THE POSSIBILITY OF SUCH DAMAGE.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 /*
  35  * The following controllers are supported by this driver:
  36  *   BCM5706C A2, A3
  37  *   BCM5706S A2, A3
  38  *   BCM5708C B1, B2
  39  *   BCM5708S B1, B2
  40  *   BCM5709C A1, C0
  41  *   BCM5709S A1, C0
  42  *   BCM5716C C0
  43  *   BCM5716S C0
  44  *
  45  * The following controllers are not supported by this driver:
  46  *   BCM5706C A0, A1 (pre-production)
  47  *   BCM5706S A0, A1 (pre-production)
  48  *   BCM5708C A0, B0 (pre-production)
  49  *   BCM5708S A0, B0 (pre-production)
  50  *   BCM5709C A0  B0, B1, B2 (pre-production)
  51  *   BCM5709S A0, B0, B1, B2 (pre-production)
  52  */
  53
  54 #include "opt_bce.h"
  55
  56 #include <dev/bce/if_bcereg.h>
  57 #include <dev/bce/if_bcefw.h>
  58
  59 /****************************************************************************/
  60 /* BCE Debug Options                                                        */
  61 /****************************************************************************/
  62 #ifdef BCE_DEBUG
  63         u32 bce_debug = BCE_WARN;
  64
  65         /*          0 = Never              */
  66         /*          1 = 1 in 2,147,483,648 */
  67         /*        256 = 1 in     8,388,608 */
  68         /*       2048 = 1 in     1,048,576 */
  69         /*      65536 = 1 in        32,768 */
  70         /*    1048576 = 1 in         2,048 */
  71         /*  268435456 = 1 in             8 */
  72         /*  536870912 = 1 in             4 */
  73         /* 1073741824 = 1 in             2 */
  74
  75         /* Controls how often the l2_fhdr frame error check will fail. */
  76         int l2fhdr_error_sim_control = 0;
  77
  78         /* Controls how often the unexpected attention check will fail. */
  79         int unexpected_attention_sim_control = 0;
  80
  81         /* Controls how often to simulate an mbuf allocation failure. */
  82         int mbuf_alloc_failed_sim_control = 0;
  83
  84         /* Controls how often to simulate a DMA mapping failure. */
  85         int dma_map_addr_failed_sim_control = 0;
  86
  87         /* Controls how often to simulate a bootcode failure. */
  88         int bootcode_running_failure_sim_control = 0;
  89 #endif
  90
  91 /****************************************************************************/
  92 /* BCE Build Time Options                                                   */
  93 /****************************************************************************/
  94 /* #define BCE_NVRAM_WRITE_SUPPORT 1 */
  95
  96
  97 /****************************************************************************/
  98 /* PCI Device ID Table                                                      */
  99 /*                                                                          */
 100 /* Used by bce_probe() to identify the devices supported by this driver.    */
 101 /****************************************************************************/
 102 #define BCE_DEVDESC_MAX         64
 103
 104 static struct bce_type bce_devs[] = {
 105         /* BCM5706C Controllers and OEM boards. */
 106         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3101,
 107                 "HP NC370T Multifunction Gigabit Server Adapter" },
 108         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3106,
 109                 "HP NC370i Multifunction Gigabit Server Adapter" },
 110         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x3070,
 111                 "HP NC380T PCIe DP Multifunc Gig Server Adapter" },
 112         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  HP_VENDORID, 0x1709,
 113                 "HP NC371i Multifunction Gigabit Server Adapter" },
 114         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706,  PCI_ANY_ID,  PCI_ANY_ID,
 115                 "Broadcom NetXtreme II BCM5706 1000Base-T" },
 116
 117         /* BCM5706S controllers and OEM boards. */
 118         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, HP_VENDORID, 0x3102,
 119                 "HP NC370F Multifunction Gigabit Server Adapter" },
 120         { BRCM_VENDORID, BRCM_DEVICEID_BCM5706S, PCI_ANY_ID,  PCI_ANY_ID,
 121                 "Broadcom NetXtreme II BCM5706 1000Base-SX" },
 122
 123         /* BCM5708C controllers and OEM boards. */
 124         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7037,
 125                 "HP NC373T PCIe Multifunction Gig Server Adapter" },
 126         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7038,
 127                 "HP NC373i Multifunction Gigabit Server Adapter" },
 128         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  HP_VENDORID, 0x7045,
 129                 "HP NC374m PCIe Multifunction Adapter" },
 130         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708,  PCI_ANY_ID,  PCI_ANY_ID,
 131                 "Broadcom NetXtreme II BCM5708 1000Base-T" },
 132
 133         /* BCM5708S controllers and OEM boards. */
 134         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x1706,
 135                 "HP NC373m Multifunction Gigabit Server Adapter" },
 136         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703b,
 137                 "HP NC373i Multifunction Gigabit Server Adapter" },
 138         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  HP_VENDORID, 0x703d,
 139                 "HP NC373F PCIe Multifunc Giga Server Adapter" },
 140         { BRCM_VENDORID, BRCM_DEVICEID_BCM5708S,  PCI_ANY_ID,  PCI_ANY_ID,
 141                 "Broadcom NetXtreme II BCM5708 1000Base-SX" },
 142
 143         /* BCM5709C controllers and OEM boards. */
 144         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7055,
 145                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 146         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  HP_VENDORID, 0x7059,
 147                 "HP NC382T PCIe DP Multifunction Gigabit Server Adapter" },
 148         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709,  PCI_ANY_ID,  PCI_ANY_ID,
 149                 "Broadcom NetXtreme II BCM5709 1000Base-T" },
 150
 151         /* BCM5709S controllers and OEM boards. */
 152         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x171d,
 153                 "HP NC382m DP 1GbE Multifunction BL-c Adapter" },
 154         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  HP_VENDORID, 0x7056,
 155                 "HP NC382i DP Multifunction Gigabit Server Adapter" },
 156         { BRCM_VENDORID, BRCM_DEVICEID_BCM5709S,  PCI_ANY_ID,  PCI_ANY_ID,
 157                 "Broadcom NetXtreme II BCM5709 1000Base-SX" },
 158
 159         /* BCM5716 controllers and OEM boards. */
 160         { BRCM_VENDORID, BRCM_DEVICEID_BCM5716,  PCI_ANY_ID,  PCI_ANY_ID,
 161                 "Broadcom NetXtreme II BCM5716 1000Base-T" },
 162
 163         { 0, 0, 0, 0, NULL }
 164 };
 165
 166
 167 /****************************************************************************/
 168 /* Supported Flash NVRAM device data.                                       */
 169 /****************************************************************************/
 170 static struct flash_spec flash_table[] =
 171 {
 172 #define BUFFERED_FLAGS          (BCE_NV_BUFFERED | BCE_NV_TRANSLATE)
 173 #define NONBUFFERED_FLAGS       (BCE_NV_WREN)
 174
 175         /* Slow EEPROM */
 176         {0x00000000, 0x40830380, 0x009f0081, 0xa184a053, 0xaf000400,
 177          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 178          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 179          "EEPROM - slow"},
 180         /* Expansion entry 0001 */
 181         {0x08000002, 0x4b808201, 0x00050081, 0x03840253, 0xaf020406,
 182          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 183          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 184          "Entry 0001"},
 185         /* Saifun SA25F010 (non-buffered flash) */
 186         /* strap, cfg1, & write1 need updates */
 187         {0x04000001, 0x47808201, 0x00050081, 0x03840253, 0xaf020406,
 188          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 189          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*2,
 190          "Non-buffered flash (128kB)"},
 191         /* Saifun SA25F020 (non-buffered flash) */
 192         /* strap, cfg1, & write1 need updates */
 193         {0x0c000003, 0x4f808201, 0x00050081, 0x03840253, 0xaf020406,
 194          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 195          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE*4,
 196          "Non-buffered flash (256kB)"},
 197         /* Expansion entry 0100 */
 198         {0x11000000, 0x53808201, 0x00050081, 0x03840253, 0xaf020406,
 199          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 200          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 201          "Entry 0100"},
 202         /* Entry 0101: ST M45PE10 (non-buffered flash, TetonII B0) */
 203         {0x19000002, 0x5b808201, 0x000500db, 0x03840253, 0xaf020406,
 204          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 205          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*2,
 206          "Entry 0101: ST M45PE10 (128kB non-bufferred)"},
 207         /* Entry 0110: ST M45PE20 (non-buffered flash)*/
 208         {0x15000001, 0x57808201, 0x000500db, 0x03840253, 0xaf020406,
 209          NONBUFFERED_FLAGS, ST_MICRO_FLASH_PAGE_BITS, ST_MICRO_FLASH_PAGE_SIZE,
 210          ST_MICRO_FLASH_BYTE_ADDR_MASK, ST_MICRO_FLASH_BASE_TOTAL_SIZE*4,
 211          "Entry 0110: ST M45PE20 (256kB non-bufferred)"},
 212         /* Saifun SA25F005 (non-buffered flash) */
 213         /* strap, cfg1, & write1 need updates */
 214         {0x1d000003, 0x5f808201, 0x00050081, 0x03840253, 0xaf020406,
 215          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 216          SAIFUN_FLASH_BYTE_ADDR_MASK, SAIFUN_FLASH_BASE_TOTAL_SIZE,
 217          "Non-buffered flash (64kB)"},
 218         /* Fast EEPROM */
 219         {0x22000000, 0x62808380, 0x009f0081, 0xa184a053, 0xaf000400,
 220          BUFFERED_FLAGS, SEEPROM_PAGE_BITS, SEEPROM_PAGE_SIZE,
 221          SEEPROM_BYTE_ADDR_MASK, SEEPROM_TOTAL_SIZE,
 222          "EEPROM - fast"},
 223         /* Expansion entry 1001 */
 224         {0x2a000002, 0x6b808201, 0x00050081, 0x03840253, 0xaf020406,
 225          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 226          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 227          "Entry 1001"},
 228         /* Expansion entry 1010 */
 229         {0x26000001, 0x67808201, 0x00050081, 0x03840253, 0xaf020406,
 230          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 231          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 232          "Entry 1010"},
 233         /* ATMEL AT45DB011B (buffered flash) */
 234         {0x2e000003, 0x6e808273, 0x00570081, 0x68848353, 0xaf000400,
 235          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 236          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE,
 237          "Buffered flash (128kB)"},
 238         /* Expansion entry 1100 */
 239         {0x33000000, 0x73808201, 0x00050081, 0x03840253, 0xaf020406,
 240          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 241          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 242          "Entry 1100"},
 243         /* Expansion entry 1101 */
 244         {0x3b000002, 0x7b808201, 0x00050081, 0x03840253, 0xaf020406,
 245          NONBUFFERED_FLAGS, SAIFUN_FLASH_PAGE_BITS, SAIFUN_FLASH_PAGE_SIZE,
 246          SAIFUN_FLASH_BYTE_ADDR_MASK, 0,
 247          "Entry 1101"},
 248         /* Ateml Expansion entry 1110 */
 249         {0x37000001, 0x76808273, 0x00570081, 0x68848353, 0xaf000400,
 250          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 251          BUFFERED_FLASH_BYTE_ADDR_MASK, 0,
 252          "Entry 1110 (Atmel)"},
 253         /* ATMEL AT45DB021B (buffered flash) */
 254         {0x3f000003, 0x7e808273, 0x00570081, 0x68848353, 0xaf000400,
 255          BUFFERED_FLAGS, BUFFERED_FLASH_PAGE_BITS, BUFFERED_FLASH_PAGE_SIZE,
 256          BUFFERED_FLASH_BYTE_ADDR_MASK, BUFFERED_FLASH_TOTAL_SIZE*2,
 257          "Buffered flash (256kB)"},
 258 };
 259
 260 /*
 261  * The BCM5709 controllers transparently handle the
 262  * differences between Atmel 264 byte pages and all
 263  * flash devices which use 256 byte pages, so no
 264  * logical-to-physical mapping is required in the
 265  * driver.
 266  */
 267 static struct flash_spec flash_5709 = {
 268         .flags          = BCE_NV_BUFFERED,
 269         .page_bits      = BCM5709_FLASH_PAGE_BITS,
 270         .page_size      = BCM5709_FLASH_PAGE_SIZE,
 271         .addr_mask      = BCM5709_FLASH_BYTE_ADDR_MASK,
 272         .total_size     = BUFFERED_FLASH_TOTAL_SIZE * 2,
 273         .name           = "5709/5716 buffered flash (256kB)",
 274 };
 275
 276
 277 /****************************************************************************/
 278 /* FreeBSD device entry points.                                             */
 279 /****************************************************************************/
 280 static int  bce_probe                   (device_t);
 281 static int  bce_attach                  (device_t);
 282 static int  bce_detach                  (device_t);
 283 static int  bce_shutdown                (device_t);
 284
 285
 286 /****************************************************************************/
 287 /* BCE Debug Data Structure Dump Routines                                   */
 288 /****************************************************************************/
 289 #ifdef BCE_DEBUG
 290 static u32  bce_reg_rd                  (struct bce_softc *, u32);
 291 static void bce_reg_wr                  (struct bce_softc *, u32, u32);
 292 static void bce_reg_wr16                (struct bce_softc *, u32, u16);
 293 static u32  bce_ctx_rd                  (struct bce_softc *, u32, u32);
 294 static void bce_dump_enet               (struct bce_softc *, struct mbuf *);
 295 static void bce_dump_mbuf               (struct bce_softc *, struct mbuf *);
 296 static void bce_dump_tx_mbuf_chain      (struct bce_softc *, u16, int);
 297 static void bce_dump_rx_mbuf_chain      (struct bce_softc *, u16, int);
 298 #ifdef BCE_JUMBO_HDRSPLIT
 299 static void bce_dump_pg_mbuf_chain      (struct bce_softc *, u16, int);
 300 #endif
 301 static void bce_dump_txbd               (struct bce_softc *,
 302     int, struct tx_bd *);
 303 static void bce_dump_rxbd               (struct bce_softc *,
 304     int, struct rx_bd *);
 305 #ifdef BCE_JUMBO_HDRSPLIT
 306 static void bce_dump_pgbd               (struct bce_softc *,
 307     int, struct rx_bd *);
 308 #endif
 309 static void bce_dump_l2fhdr             (struct bce_softc *,
 310     int, struct l2_fhdr *);
 311 static void bce_dump_ctx                (struct bce_softc *, u16);
 312 static void bce_dump_ftqs               (struct bce_softc *);
 313 static void bce_dump_tx_chain           (struct bce_softc *, u16, int);
 314 static void bce_dump_rx_bd_chain        (struct bce_softc *, u16, int);
 315 #ifdef BCE_JUMBO_HDRSPLIT
 316 static void bce_dump_pg_chain           (struct bce_softc *, u16, int);
 317 #endif
 318 static void bce_dump_status_block       (struct bce_softc *);
 319 static void bce_dump_stats_block        (struct bce_softc *);
 320 static void bce_dump_driver_state       (struct bce_softc *);
 321 static void bce_dump_hw_state           (struct bce_softc *);
 322 static void bce_dump_mq_regs            (struct bce_softc *);
 323 static void bce_dump_bc_state           (struct bce_softc *);
 324 static void bce_dump_txp_state          (struct bce_softc *, int);
 325 static void bce_dump_rxp_state          (struct bce_softc *, int);
 326 static void bce_dump_tpat_state         (struct bce_softc *, int);
 327 static void bce_dump_cp_state           (struct bce_softc *, int);
 328 static void bce_dump_com_state          (struct bce_softc *, int);
 329 static void bce_dump_rv2p_state         (struct bce_softc *);
 330 static void bce_breakpoint              (struct bce_softc *);
 331 #endif
 332
 333
 334 /****************************************************************************/
 335 /* BCE Register/Memory Access Routines                                      */
 336 /****************************************************************************/
 337 static u32  bce_reg_rd_ind              (struct bce_softc *, u32);
 338 static void bce_reg_wr_ind              (struct bce_softc *, u32, u32);
 339 static void bce_shmem_wr                (struct bce_softc *, u32, u32);
 340 static u32  bce_shmem_rd                (struct bce_softc *, u32);
 341 static void bce_ctx_wr                  (struct bce_softc *, u32, u32, u32);
 342 static int  bce_miibus_read_reg         (device_t, int, int);
 343 static int  bce_miibus_write_reg        (device_t, int, int, int);
 344 static void bce_miibus_statchg          (device_t);
 345
 346
 347 /****************************************************************************/
 348 /* BCE NVRAM Access Routines                                                */
 349 /****************************************************************************/
 350 static int  bce_acquire_nvram_lock      (struct bce_softc *);
 351 static int  bce_release_nvram_lock      (struct bce_softc *);
 352 static void bce_enable_nvram_access     (struct bce_softc *);
 353 static void bce_disable_nvram_access    (struct bce_softc *);
 354 static int  bce_nvram_read_dword        (struct bce_softc *, u32, u8 *, u32);
 355 static int  bce_init_nvram              (struct bce_softc *);
 356 static int  bce_nvram_read              (struct bce_softc *, u32, u8 *, int);
 357 static int  bce_nvram_test              (struct bce_softc *);
 358 #ifdef BCE_NVRAM_WRITE_SUPPORT
 359 static int  bce_enable_nvram_write      (struct bce_softc *);
 360 static void bce_disable_nvram_write     (struct bce_softc *);
 361 static int  bce_nvram_erase_page        (struct bce_softc *, u32);
 362 static int  bce_nvram_write_dword       (struct bce_softc *, u32, u8 *, u32);
 363 static int  bce_nvram_write             (struct bce_softc *, u32, u8 *, int);
 364 #endif
 365
 366 /****************************************************************************/
 367 /*                                                                          */
 368 /****************************************************************************/
 369 static void bce_get_media               (struct bce_softc *);
 370 static void bce_init_media              (struct bce_softc *);
 371 static void bce_dma_map_addr            (void *,
 372     bus_dma_segment_t *, int, int);
 373 static int  bce_dma_alloc               (device_t);
 374 static void bce_dma_free                (struct bce_softc *);
 375 static void bce_release_resources       (struct bce_softc *);
 376
 377 /****************************************************************************/
 378 /* BCE Firmware Synchronization and Load                                    */
 379 /****************************************************************************/
 380 static int  bce_fw_sync                 (struct bce_softc *, u32);
 381 static void bce_load_rv2p_fw            (struct bce_softc *, u32 *, u32, u32);
 382 static void bce_load_cpu_fw             (struct bce_softc *,
 383     struct cpu_reg *, struct fw_info *);
 384 static void bce_start_cpu               (struct bce_softc *, struct cpu_reg *);
 385 static void bce_halt_cpu                (struct bce_softc *, struct cpu_reg *);
 386 static void bce_start_rxp_cpu           (struct bce_softc *);
 387 static void bce_init_rxp_cpu            (struct bce_softc *);
 388 static void bce_init_txp_cpu            (struct bce_softc *);
 389 static void bce_init_tpat_cpu           (struct bce_softc *);
 390 static void bce_init_cp_cpu             (struct bce_softc *);
 391 static void bce_init_com_cpu            (struct bce_softc *);
 392 static void bce_init_cpus               (struct bce_softc *);
 393
 394 static void     bce_print_adapter_info  (struct bce_softc *);
 395 static void bce_probe_pci_caps          (device_t, struct bce_softc *);
 396 static void bce_stop                    (struct bce_softc *);
 397 static int  bce_reset                   (struct bce_softc *, u32);
 398 static int  bce_chipinit                (struct bce_softc *);
 399 static int  bce_blockinit               (struct bce_softc *);
 400
 401 static int  bce_init_tx_chain           (struct bce_softc *);
 402 static void bce_free_tx_chain           (struct bce_softc *);
 403
 404 static int  bce_get_rx_buf              (struct bce_softc *,
 405     struct mbuf *, u16 *, u16 *, u32 *);
 406 static int  bce_init_rx_chain           (struct bce_softc *);
 407 static void bce_fill_rx_chain           (struct bce_softc *);
 408 static void bce_free_rx_chain           (struct bce_softc *);
 409
 410 #ifdef BCE_JUMBO_HDRSPLIT
 411 static int  bce_get_pg_buf              (struct bce_softc *,
 412     struct mbuf *, u16 *, u16 *);
 413 static int  bce_init_pg_chain           (struct bce_softc *);
 414 static void bce_fill_pg_chain           (struct bce_softc *);
 415 static void bce_free_pg_chain           (struct bce_softc *);
 416 #endif
 417
 418 static struct mbuf *bce_tso_setup       (struct bce_softc *,
 419     struct mbuf **, u16 *);
 420 static int  bce_tx_encap                (struct bce_softc *, struct mbuf **);
 421 static void bce_start_locked            (struct ifnet *);
 422 static void bce_start                   (struct ifnet *);
 423 static int  bce_ioctl                   (struct ifnet *, u_long, caddr_t);
 424 static void bce_watchdog                (struct bce_softc *);
 425 static int  bce_ifmedia_upd             (struct ifnet *);
 426 static int  bce_ifmedia_upd_locked      (struct ifnet *);
 427 static void bce_ifmedia_sts             (struct ifnet *, struct ifmediareq *);
 428 static void bce_init_locked             (struct bce_softc *);
 429 static void bce_init                    (void *);
 430 static void bce_mgmt_init_locked        (struct bce_softc *sc);
 431
 432 static int  bce_init_ctx                (struct bce_softc *);
 433 static void bce_get_mac_addr            (struct bce_softc *);
 434 static void bce_set_mac_addr            (struct bce_softc *);
 435 static void bce_phy_intr                (struct bce_softc *);
 436 static inline u16 bce_get_hw_rx_cons    (struct bce_softc *);
 437 static void bce_rx_intr                 (struct bce_softc *);
 438 static void bce_tx_intr                 (struct bce_softc *);
 439 static void bce_disable_intr            (struct bce_softc *);
 440 static void bce_enable_intr             (struct bce_softc *, int);
 441
 442 static void bce_intr                    (void *);
 443 static void bce_set_rx_mode             (struct bce_softc *);
 444 static void bce_stats_update            (struct bce_softc *);
 445 static void bce_tick                    (void *);
 446 static void bce_pulse                   (void *);
 447 static void bce_add_sysctls             (struct bce_softc *);
 448
 449
 450 /****************************************************************************/
 451 /* FreeBSD device dispatch table.                                           */
 452 /****************************************************************************/
 453 static device_method_t bce_methods[] = {
 454         /* Device interface (device_if.h) */
 455         DEVMETHOD(device_probe,         bce_probe),
 456         DEVMETHOD(device_attach,        bce_attach),
 457         DEVMETHOD(device_detach,        bce_detach),
 458         DEVMETHOD(device_shutdown,      bce_shutdown),
 459 /* Supported by device interface but not used here. */
 460 /*      DEVMETHOD(device_identify,      bce_identify),      */
 461 /*      DEVMETHOD(device_suspend,       bce_suspend),       */
 462 /*      DEVMETHOD(device_resume,        bce_resume),        */
 463 /*      DEVMETHOD(device_quiesce,       bce_quiesce),       */
 464
 465         /* Bus interface (bus_if.h) */
 466         DEVMETHOD(bus_print_child,      bus_generic_print_child),
 467         DEVMETHOD(bus_driver_added,     bus_generic_driver_added),
 468
 469         /* MII interface (miibus_if.h) */
 470         DEVMETHOD(miibus_readreg,       bce_miibus_read_reg),
 471         DEVMETHOD(miibus_writereg,      bce_miibus_write_reg),
 472         DEVMETHOD(miibus_statchg,       bce_miibus_statchg),
 473 /* Supported by MII interface but not used here.       */
 474 /*      DEVMETHOD(miibus_linkchg,       bce_miibus_linkchg),   */
 475 /*      DEVMETHOD(miibus_mediainit,     bce_miibus_mediainit), */
 476
 477         { 0, 0 }
 478 };
 479
 480 static driver_t bce_driver = {
 481         "bce",
 482         bce_methods,
 483         sizeof(struct bce_softc)
 484 };
 485
 486 static devclass_t bce_devclass;
 487
 488 MODULE_DEPEND(bce, pci, 1, 1, 1);
 489 MODULE_DEPEND(bce, ether, 1, 1, 1);
 490 MODULE_DEPEND(bce, miibus, 1, 1, 1);
 491
 492 DRIVER_MODULE(bce, pci, bce_driver, bce_devclass, 0, 0);
 493 DRIVER_MODULE(miibus, bce, miibus_driver, miibus_devclass, 0, 0);
 494
 495
 496 /****************************************************************************/
 497 /* Tunable device values                                                    */
 498 /****************************************************************************/
 499 SYSCTL_NODE(_hw, OID_AUTO, bce, CTLFLAG_RD, 0, "bce driver parameters");
 500
 501 /* Allowable values are TRUE or FALSE */
 502 static int bce_tso_enable = TRUE;
 503 TUNABLE_INT("hw.bce.tso_enable", &bce_tso_enable);
 504 SYSCTL_UINT(_hw_bce, OID_AUTO, tso_enable, CTLFLAG_RDTUN, &bce_tso_enable, 0,
 505 "TSO Enable/Disable");
 506
 507 /* Allowable values are 0 (IRQ), 1 (MSI/IRQ), and 2 (MSI-X/MSI/IRQ) */
 508 /* ToDo: Add MSI-X support. */
 509 static int bce_msi_enable = 1;
 510 TUNABLE_INT("hw.bce.msi_enable", &bce_msi_enable);
 511 SYSCTL_UINT(_hw_bce, OID_AUTO, msi_enable, CTLFLAG_RDTUN, &bce_msi_enable, 0,
 512 "MSI-X|MSI|INTx selector");
 513
 514 /* ToDo: Add tunable to enable/disable strict MTU handling. */
 515 /* Currently allows "loose" RX MTU checking (i.e. sets the  */
 516 /* H/W RX MTU to the size of the largest receive buffer, or */
 517 /* 2048 bytes). This will cause a UNH failure but is more   */
 518 /* desireable from a functional perspective.                */
 519
 520
 521 /****************************************************************************/
 522 /* Device probe function.                                                   */
 523 /*                                                                          */
 524 /* Compares the device to the driver's list of supported devices and        */
 525 /* reports back to the OS whether this is the right driver for the device.  */
 526 /*                                                                          */
 527 /* Returns:                                                                 */
 528 /*   BUS_PROBE_DEFAULT on success, positive value on failure.               */
 529 /****************************************************************************/
 530 static int
 531 bce_probe(device_t dev)
 532 {
 533         struct bce_type *t;
 534         struct bce_softc *sc;
 535         char *descbuf;
 536         u16 vid = 0, did = 0, svid = 0, sdid = 0;
 537
 538         t = bce_devs;
 539
 540         sc = device_get_softc(dev);
 541         bzero(sc, sizeof(struct bce_softc));
 542         sc->bce_unit = device_get_unit(dev);
 543         sc->bce_dev = dev;
 544
 545         /* Get the data for the device to be probed. */
 546         vid  = pci_get_vendor(dev);
 547         did  = pci_get_device(dev);
 548         svid = pci_get_subvendor(dev);
 549         sdid = pci_get_subdevice(dev);
 550
 551         DBPRINT(sc, BCE_EXTREME_LOAD,
 552             "%s(); VID = 0x%04X, DID = 0x%04X, SVID = 0x%04X, "
 553             "SDID = 0x%04X\n", __FUNCTION__, vid, did, svid, sdid);
 554
 555         /* Look through the list of known devices for a match. */
 556         while(t->bce_name != NULL) {
 557
 558                 if ((vid == t->bce_vid) && (did == t->bce_did) &&
 559                     ((svid == t->bce_svid) || (t->bce_svid == PCI_ANY_ID)) &&
 560                     ((sdid == t->bce_sdid) || (t->bce_sdid == PCI_ANY_ID))) {
 561
 562                         descbuf = malloc(BCE_DEVDESC_MAX, M_TEMP, M_NOWAIT);
 563
 564                         if (descbuf == NULL)
 565                                 return(ENOMEM);
 566
 567                         /* Print out the device identity. */
 568                         snprintf(descbuf, BCE_DEVDESC_MAX, "%s (%c%d)",
 569                             t->bce_name, (((pci_read_config(dev,
 570                             PCIR_REVID, 4) & 0xf0) >> 4) + 'A'),
 571                             (pci_read_config(dev, PCIR_REVID, 4) & 0xf));
 572
 573                         device_set_desc_copy(dev, descbuf);
 574                         free(descbuf, M_TEMP);
 575                         return(BUS_PROBE_DEFAULT);
 576                 }
 577                 t++;
 578         }
 579
 580         return(ENXIO);
 581 }
 582
 583
 584 /****************************************************************************/
 585 /* PCI Capabilities Probe Function.                                         */
 586 /*                                                                          */
 587 /* Walks the PCI capabiites list for the device to find what features are   */
 588 /* supported.                                                               */
 589 /*                                                                          */
 590 /* Returns:                                                                 */
 591 /*   None.                                                                  */
 592 /****************************************************************************/
 593 static void
 594 bce_print_adapter_info(struct bce_softc *sc)
 595 {
 596         int i = 0;
 597
 598         DBENTER(BCE_VERBOSE_LOAD);
 599
 600         if (bootverbose) {
 601                 BCE_PRINTF("ASIC (0x%08X); ", sc->bce_chipid);
 602                 printf("Rev (%c%d); ", ((BCE_CHIP_ID(sc) & 0xf000) >>
 603                     12) + 'A', ((BCE_CHIP_ID(sc) & 0x0ff0) >> 4));
 604
 605
 606                 /* Bus info. */
 607                 if (sc->bce_flags & BCE_PCIE_FLAG) {
 608                         printf("Bus (PCIe x%d, ", sc->link_width);
 609                         switch (sc->link_speed) {
 610                         case 1: printf("2.5Gbps); "); break;
 611                         case 2: printf("5Gbps); "); break;
 612                         default: printf("Unknown link speed); ");
 613                         }
 614                 } else {
 615                         printf("Bus (PCI%s, %s, %dMHz); ",
 616                             ((sc->bce_flags & BCE_PCIX_FLAG) ? "-X" : ""),
 617                             ((sc->bce_flags & BCE_PCI_32BIT_FLAG) ?
 618                             "32-bit" : "64-bit"), sc->bus_speed_mhz);
 619                 }
 620
 621                 /* Firmware version and device features. */
 622                 printf("B/C (%s); Flags (", sc->bce_bc_ver);
 623
 624         #ifdef BCE_JUMBO_HDRSPLIT
 625                 printf("SPLT");
 626                 i++;
 627         #endif
 628
 629                 if (sc->bce_flags & BCE_USING_MSI_FLAG) {
 630                         if (i > 0) printf("|");
 631                         printf("MSI"); i++;
 632                 }
 633
 634                 if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
 635                         if (i > 0) printf("|");
 636                         printf("MSI-X"); i++;
 637                 }
 638
 639                 if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG) {
 640                         if (i > 0) printf("|");
 641                         printf("2.5G"); i++;
 642                 }
 643
 644                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
 645                         if (i > 0) printf("|");
 646                         printf("MFW); MFW (%s)\n", sc->bce_mfw_ver);
 647                 } else {
 648                         printf(")\n");
 649                 }
 650         }
 651
 652         DBEXIT(BCE_VERBOSE_LOAD);
 653 }
 654
 655
 656 /****************************************************************************/
 657 /* PCI Capabilities Probe Function.                                         */
 658 /*                                                                          */
 659 /* Walks the PCI capabiites list for the device to find what features are   */
 660 /* supported.                                                               */
 661 /*                                                                          */
 662 /* Returns:                                                                 */
 663 /*   None.                                                                  */
 664 /****************************************************************************/
 665 static void
 666 bce_probe_pci_caps(device_t dev, struct bce_softc *sc)
 667 {
 668         u32 reg;
 669
 670         DBENTER(BCE_VERBOSE_LOAD);
 671
 672         /* Check if PCI-X capability is enabled. */
 673         if (pci_find_extcap(dev, PCIY_PCIX, &reg) == 0) {
 674                 if (reg != 0)
 675                         sc->bce_cap_flags |= BCE_PCIX_CAPABLE_FLAG;
 676         }
 677
 678         /* Check if PCIe capability is enabled. */
 679         if (pci_find_extcap(dev, PCIY_EXPRESS, &reg) == 0) {
 680                 if (reg != 0) {
 681                         u16 link_status = pci_read_config(dev, reg + 0x12, 2);
 682                         DBPRINT(sc, BCE_INFO_LOAD, "PCIe link_status = "
 683                             "0x%08X\n", link_status);
 684                         sc->link_speed = link_status & 0xf;
 685                         sc->link_width = (link_status >> 4) & 0x3f;
 686                         sc->bce_cap_flags |= BCE_PCIE_CAPABLE_FLAG;
 687                         sc->bce_flags |= BCE_PCIE_FLAG;
 688                 }
 689         }
 690
 691         /* Check if MSI capability is enabled. */
 692         if (pci_find_extcap(dev, PCIY_MSI, &reg) == 0) {
 693                 if (reg != 0)
 694                         sc->bce_cap_flags |= BCE_MSI_CAPABLE_FLAG;
 695         }
 696
 697         /* Check if MSI-X capability is enabled. */
 698         if (pci_find_extcap(dev, PCIY_MSIX, &reg) == 0) {
 699                 if (reg != 0)
 700                         sc->bce_cap_flags |= BCE_MSIX_CAPABLE_FLAG;
 701         }
 702
 703         DBEXIT(BCE_VERBOSE_LOAD);
 704 }
 705
 706
 707 /****************************************************************************/
 708 /* Device attach function.                                                  */
 709 /*                                                                          */
 710 /* Allocates device resources, performs secondary chip identification,      */
 711 /* resets and initializes the hardware, and initializes driver instance     */
 712 /* variables.                                                               */
 713 /*                                                                          */
 714 /* Returns:                                                                 */
 715 /*   0 on success, positive value on failure.                               */
 716 /****************************************************************************/
 717 static int
 718 bce_attach(device_t dev)
 719 {
 720         struct bce_softc *sc;
 721         struct ifnet *ifp;
 722         u32 val;
 723         int error, rid, rc = 0;
 724
 725         sc = device_get_softc(dev);
 726         sc->bce_dev = dev;
 727
 728         DBENTER(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
 729
 730         sc->bce_unit = device_get_unit(dev);
 731
 732         /* Set initial device and PHY flags */
 733         sc->bce_flags = 0;
 734         sc->bce_phy_flags = 0;
 735
 736         pci_enable_busmaster(dev);
 737
 738         /* Allocate PCI memory resources. */
 739         rid = PCIR_BAR(0);
 740         sc->bce_res_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 741                 &rid, RF_ACTIVE);
 742
 743         if (sc->bce_res_mem == NULL) {
 744                 BCE_PRINTF("%s(%d): PCI memory allocation failed\n",
 745                     __FILE__, __LINE__);
 746                 rc = ENXIO;
 747                 goto bce_attach_fail;
 748         }
 749
 750         /* Get various resource handles. */
 751         sc->bce_btag    = rman_get_bustag(sc->bce_res_mem);
 752         sc->bce_bhandle = rman_get_bushandle(sc->bce_res_mem);
 753         sc->bce_vhandle = (vm_offset_t) rman_get_virtual(sc->bce_res_mem);
 754
 755         bce_probe_pci_caps(dev, sc);
 756
 757         rid = 1;
 758 #if 0
 759         /* Try allocating MSI-X interrupts. */
 760         if ((sc->bce_cap_flags & BCE_MSIX_CAPABLE_FLAG) &&
 761                 (bce_msi_enable >= 2) &&
 762                 ((sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
 763                 &rid, RF_ACTIVE)) != NULL)) {
 764
 765                 msi_needed = sc->bce_msi_count = 1;
 766
 767                 if (((error = pci_alloc_msix(dev, &sc->bce_msi_count)) != 0) ||
 768                         (sc->bce_msi_count != msi_needed)) {
 769                         BCE_PRINTF("%s(%d): MSI-X allocation failed! Requested = %d,"
 770                                 "Received = %d, error = %d\n", __FILE__, __LINE__,
 771                                 msi_needed, sc->bce_msi_count, error);
 772                         sc->bce_msi_count = 0;
 773                         pci_release_msi(dev);
 774                         bus_release_resource(dev, SYS_RES_MEMORY, rid,
 775                                 sc->bce_res_irq);
 776                         sc->bce_res_irq = NULL;
 777                 } else {
 778                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI-X interrupt.\n",
 779                                 __FUNCTION__);
 780                         sc->bce_flags |= BCE_USING_MSIX_FLAG;
 781                         sc->bce_intr = bce_intr;
 782                 }
 783         }
 784 #endif
 785
 786         /* Try allocating a MSI interrupt. */
 787         if ((sc->bce_cap_flags & BCE_MSI_CAPABLE_FLAG) &&
 788                 (bce_msi_enable >= 1) && (sc->bce_msi_count == 0)) {
 789                 sc->bce_msi_count = 1;
 790                 if ((error = pci_alloc_msi(dev, &sc->bce_msi_count)) != 0) {
 791                         BCE_PRINTF("%s(%d): MSI allocation failed! "
 792                             "error = %d\n", __FILE__, __LINE__, error);
 793                         sc->bce_msi_count = 0;
 794                         pci_release_msi(dev);
 795                 } else {
 796                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using MSI "
 797                             "interrupt.\n", __FUNCTION__);
 798                         sc->bce_flags |= BCE_USING_MSI_FLAG;
 799                         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
 800                                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
 801                                 sc->bce_flags |= BCE_ONE_SHOT_MSI_FLAG;
 802                         sc->bce_irq_rid = 1;
 803                         sc->bce_intr = bce_intr;
 804                 }
 805         }
 806
 807         /* Try allocating a legacy interrupt. */
 808         if (sc->bce_msi_count == 0) {
 809                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Using INTx interrupt.\n",
 810                         __FUNCTION__);
 811                 rid = 0;
 812                 sc->bce_intr = bce_intr;
 813         }
 814
 815         sc->bce_res_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
 816             &rid, RF_SHAREABLE | RF_ACTIVE);
 817
 818         sc->bce_irq_rid = rid;
 819
 820         /* Report any IRQ allocation errors. */
 821         if (sc->bce_res_irq == NULL) {
 822                 BCE_PRINTF("%s(%d): PCI map interrupt failed!\n",
 823                     __FILE__, __LINE__);
 824                 rc = ENXIO;
 825                 goto bce_attach_fail;
 826         }
 827
 828         /* Initialize mutex for the current device instance. */
 829         BCE_LOCK_INIT(sc, device_get_nameunit(dev));
 830
 831         /*
 832          * Configure byte swap and enable indirect register access.
 833          * Rely on CPU to do target byte swapping on big endian systems.
 834          * Access to registers outside of PCI configurtion space are not
 835          * valid until this is done.
 836          */
 837         pci_write_config(dev, BCE_PCICFG_MISC_CONFIG,
 838             BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
 839             BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP, 4);
 840
 841         /* Save ASIC revsion info. */
 842         sc->bce_chipid =  REG_RD(sc, BCE_MISC_ID);
 843
 844         /* Weed out any non-production controller revisions. */
 845         switch(BCE_CHIP_ID(sc)) {
 846         case BCE_CHIP_ID_5706_A0:
 847         case BCE_CHIP_ID_5706_A1:
 848         case BCE_CHIP_ID_5708_A0:
 849         case BCE_CHIP_ID_5708_B0:
 850         case BCE_CHIP_ID_5709_A0:
 851         case BCE_CHIP_ID_5709_B0:
 852         case BCE_CHIP_ID_5709_B1:
 853         case BCE_CHIP_ID_5709_B2:
 854                 BCE_PRINTF("%s(%d): Unsupported controller "
 855                     "revision (%c%d)!\n", __FILE__, __LINE__,
 856                     (((pci_read_config(dev, PCIR_REVID, 4) &
 857                     0xf0) >> 4) + 'A'), (pci_read_config(dev,
 858                     PCIR_REVID, 4) & 0xf));
 859                 rc = ENODEV;
 860                 goto bce_attach_fail;
 861         }
 862
 863         /*
 864          * The embedded PCIe to PCI-X bridge (EPB)
 865          * in the 5708 cannot address memory above
 866          * 40 bits (E7_5708CB1_23043 & E6_5708SB1_23043).
 867          */
 868         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708)
 869                 sc->max_bus_addr = BCE_BUS_SPACE_MAXADDR;
 870         else
 871                 sc->max_bus_addr = BUS_SPACE_MAXADDR;
 872
 873         /*
 874          * Find the base address for shared memory access.
 875          * Newer versions of bootcode use a signature and offset
 876          * while older versions use a fixed address.
 877          */
 878         val = REG_RD_IND(sc, BCE_SHM_HDR_SIGNATURE);
 879         if ((val & BCE_SHM_HDR_SIGNATURE_SIG_MASK) == BCE_SHM_HDR_SIGNATURE_SIG)
 880                 /* Multi-port devices use different offsets in shared memory. */
 881                 sc->bce_shmem_base = REG_RD_IND(sc, BCE_SHM_HDR_ADDR_0 +
 882                     (pci_get_function(sc->bce_dev) << 2));
 883         else
 884                 sc->bce_shmem_base = HOST_VIEW_SHMEM_BASE;
 885
 886         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): bce_shmem_base = 0x%08X\n",
 887             __FUNCTION__, sc->bce_shmem_base);
 888
 889         /* Fetch the bootcode revision. */
 890         val = bce_shmem_rd(sc, BCE_DEV_INFO_BC_REV);
 891         for (int i = 0, j = 0; i < 3; i++) {
 892                 u8 num;
 893
 894                 num = (u8) (val >> (24 - (i * 8)));
 895                 for (int k = 100, skip0 = 1; k >= 1; num %= k, k /= 10) {
 896                         if (num >= k || !skip0 || k == 1) {
 897                                 sc->bce_bc_ver[j++] = (num / k) + '0';
 898                                 skip0 = 0;
 899                         }
 900                 }
 901
 902                 if (i != 2)
 903                         sc->bce_bc_ver[j++] = '.';
 904         }
 905
 906         /* Check if any management firwmare is enabled. */
 907         val = bce_shmem_rd(sc, BCE_PORT_FEATURE);
 908         if (val & BCE_PORT_FEATURE_ASF_ENABLED) {
 909                 sc->bce_flags |= BCE_MFW_ENABLE_FLAG;
 910
 911                 /* Allow time for firmware to enter the running state. */
 912                 for (int i = 0; i < 30; i++) {
 913                         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
 914                         if (val & BCE_CONDITION_MFW_RUN_MASK)
 915                                 break;
 916                         DELAY(10000);
 917                 }
 918
 919                 /* Check if management firmware is running. */
 920                 val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
 921                 val &= BCE_CONDITION_MFW_RUN_MASK;
 922                 if ((val != BCE_CONDITION_MFW_RUN_UNKNOWN) &&
 923                     (val != BCE_CONDITION_MFW_RUN_NONE)) {
 924                         u32 addr = bce_shmem_rd(sc, BCE_MFW_VER_PTR);
 925                         int i = 0;
 926
 927                         /* Read the management firmware version string. */
 928                         for (int j = 0; j < 3; j++) {
 929                                 val = bce_reg_rd_ind(sc, addr + j * 4);
 930                                 val = bswap32(val);
 931                                 memcpy(&sc->bce_mfw_ver[i], &val, 4);
 932                                 i += 4;
 933                         }
 934                 } else {
 935                         /* May cause firmware synchronization timeouts. */
 936                         BCE_PRINTF("%s(%d): Management firmware enabled "
 937                             "but not running!\n", __FILE__, __LINE__);
 938                         strcpy(sc->bce_mfw_ver, "NOT RUNNING!");
 939
 940                         /* ToDo: Any action the driver should take? */
 941                 }
 942         }
 943
 944         /* Get PCI bus information (speed and type). */
 945         val = REG_RD(sc, BCE_PCICFG_MISC_STATUS);
 946         if (val & BCE_PCICFG_MISC_STATUS_PCIX_DET) {
 947                 u32 clkreg;
 948
 949                 sc->bce_flags |= BCE_PCIX_FLAG;
 950
 951                 clkreg = REG_RD(sc, BCE_PCICFG_PCI_CLOCK_CONTROL_BITS);
 952
 953                 clkreg &= BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET;
 954                 switch (clkreg) {
 955                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_133MHZ:
 956                         sc->bus_speed_mhz = 133;
 957                         break;
 958
 959                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_95MHZ:
 960                         sc->bus_speed_mhz = 100;
 961                         break;
 962
 963                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_66MHZ:
 964                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_80MHZ:
 965                         sc->bus_speed_mhz = 66;
 966                         break;
 967
 968                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_48MHZ:
 969                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_55MHZ:
 970                         sc->bus_speed_mhz = 50;
 971                         break;
 972
 973                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_LOW:
 974                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_32MHZ:
 975                 case BCE_PCICFG_PCI_CLOCK_CONTROL_BITS_PCI_CLK_SPD_DET_38MHZ:
 976                         sc->bus_speed_mhz = 33;
 977                         break;
 978                 }
 979         } else {
 980                 if (val & BCE_PCICFG_MISC_STATUS_M66EN)
 981                         sc->bus_speed_mhz = 66;
 982                 else
 983                         sc->bus_speed_mhz = 33;
 984         }
 985
 986         if (val & BCE_PCICFG_MISC_STATUS_32BIT_DET)
 987                 sc->bce_flags |= BCE_PCI_32BIT_FLAG;
 988
 989         /* Reset controller and announce to bootcode that driver is present. */
 990         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
 991                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
 992                     __FILE__, __LINE__);
 993                 rc = ENXIO;
 994                 goto bce_attach_fail;
 995         }
 996
 997         /* Initialize the controller. */
 998         if (bce_chipinit(sc)) {
 999                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
1000                     __FILE__, __LINE__);
1001                 rc = ENXIO;
1002                 goto bce_attach_fail;
1003         }
1004
1005         /* Perform NVRAM test. */
1006         if (bce_nvram_test(sc)) {
1007                 BCE_PRINTF("%s(%d): NVRAM test failed!\n",
1008                     __FILE__, __LINE__);
1009                 rc = ENXIO;
1010                 goto bce_attach_fail;
1011         }
1012
1013         /* Fetch the permanent Ethernet MAC address. */
1014         bce_get_mac_addr(sc);
1015
1016         /*
1017          * Trip points control how many BDs
1018          * should be ready before generating an
1019          * interrupt while ticks control how long
1020          * a BD can sit in the chain before
1021          * generating an interrupt.  Set the default
1022          * values for the RX and TX chains.
1023          */
1024
1025 #ifdef BCE_DEBUG
1026         /* Force more frequent interrupts. */
1027         sc->bce_tx_quick_cons_trip_int = 1;
1028         sc->bce_tx_quick_cons_trip     = 1;
1029         sc->bce_tx_ticks_int           = 0;
1030         sc->bce_tx_ticks               = 0;
1031
1032         sc->bce_rx_quick_cons_trip_int = 1;
1033         sc->bce_rx_quick_cons_trip     = 1;
1034         sc->bce_rx_ticks_int           = 0;
1035         sc->bce_rx_ticks               = 0;
1036 #else
1037         /* Improve throughput at the expense of increased latency. */
1038         sc->bce_tx_quick_cons_trip_int = 20;
1039         sc->bce_tx_quick_cons_trip     = 20;
1040         sc->bce_tx_ticks_int           = 80;
1041         sc->bce_tx_ticks               = 80;
1042
1043         sc->bce_rx_quick_cons_trip_int = 6;
1044         sc->bce_rx_quick_cons_trip     = 6;
1045         sc->bce_rx_ticks_int           = 18;
1046         sc->bce_rx_ticks               = 18;
1047 #endif
1048
1049         /* Not used for L2. */
1050         sc->bce_comp_prod_trip_int = 0;
1051         sc->bce_comp_prod_trip = 0;
1052         sc->bce_com_ticks_int = 0;
1053         sc->bce_com_ticks = 0;
1054         sc->bce_cmd_ticks_int = 0;
1055         sc->bce_cmd_ticks = 0;
1056
1057         /* Update statistics once every second. */
1058         sc->bce_stats_ticks = 1000000 & 0xffff00;
1059
1060         /* Find the media type for the adapter. */
1061         bce_get_media(sc);
1062
1063         /* Store data needed by PHY driver for backplane applications */
1064         sc->bce_shared_hw_cfg = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
1065         sc->bce_port_hw_cfg   = bce_shmem_rd(sc, BCE_PORT_HW_CFG_CONFIG);
1066
1067         /* Allocate DMA memory resources. */
1068         if (bce_dma_alloc(dev)) {
1069                 BCE_PRINTF("%s(%d): DMA resource allocation failed!\n",
1070                     __FILE__, __LINE__);
1071                 rc = ENXIO;
1072                 goto bce_attach_fail;
1073         }
1074
1075         /* Allocate an ifnet structure. */
1076         ifp = sc->bce_ifp = if_alloc(IFT_ETHER);
1077         if (ifp == NULL) {
1078                 BCE_PRINTF("%s(%d): Interface allocation failed!\n",
1079                     __FILE__, __LINE__);
1080                 rc = ENXIO;
1081                 goto bce_attach_fail;
1082         }
1083
1084         /* Initialize the ifnet interface. */
1085         ifp->if_softc   = sc;
1086         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1087         ifp->if_flags   = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1088         ifp->if_ioctl   = bce_ioctl;
1089         ifp->if_start   = bce_start;
1090         ifp->if_init    = bce_init;
1091         ifp->if_mtu     = ETHERMTU;
1092
1093         if (bce_tso_enable) {
1094                 ifp->if_hwassist = BCE_IF_HWASSIST | CSUM_TSO;
1095                 ifp->if_capabilities = BCE_IF_CAPABILITIES | IFCAP_TSO4 |
1096                     IFCAP_VLAN_HWTSO;
1097         } else {
1098                 ifp->if_hwassist = BCE_IF_HWASSIST;
1099                 ifp->if_capabilities = BCE_IF_CAPABILITIES;
1100         }
1101
1102         ifp->if_capenable = ifp->if_capabilities;
1103
1104         /*
1105          * Assume standard mbuf sizes for buffer allocation.
1106          * This may change later if the MTU size is set to
1107          * something other than 1500.
1108          */
1109 #ifdef BCE_JUMBO_HDRSPLIT
1110         sc->rx_bd_mbuf_alloc_size = MHLEN;
1111         /* Make sure offset is 16 byte aligned for hardware. */
1112         sc->rx_bd_mbuf_align_pad =
1113             roundup2((MSIZE - MHLEN), 16) - (MSIZE - MHLEN);
1114         sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
1115             sc->rx_bd_mbuf_align_pad;
1116         sc->pg_bd_mbuf_alloc_size = MCLBYTES;
1117 #else
1118         sc->rx_bd_mbuf_alloc_size = MCLBYTES;
1119         sc->rx_bd_mbuf_align_pad =
1120             roundup2(MCLBYTES, 16) - MCLBYTES;
1121         sc->rx_bd_mbuf_data_len = sc->rx_bd_mbuf_alloc_size -
1122             sc->rx_bd_mbuf_align_pad;
1123 #endif
1124
1125         ifp->if_snd.ifq_drv_maxlen = USABLE_TX_BD;
1126         IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1127         IFQ_SET_READY(&ifp->if_snd);
1128
1129         if (sc->bce_phy_flags & BCE_PHY_2_5G_CAPABLE_FLAG)
1130                 ifp->if_baudrate = IF_Mbps(2500ULL);
1131         else
1132                 ifp->if_baudrate = IF_Mbps(1000);
1133
1134         /* Handle any special PHY initialization for SerDes PHYs. */
1135         bce_init_media(sc);
1136
1137         /* MII child bus by probing the PHY. */
1138         if (mii_phy_probe(dev, &sc->bce_miibus, bce_ifmedia_upd,
1139                 bce_ifmedia_sts)) {
1140                 BCE_PRINTF("%s(%d): No PHY found on child MII bus!\n",
1141                     __FILE__, __LINE__);
1142                 rc = ENXIO;
1143                 goto bce_attach_fail;
1144         }
1145
1146         /* Attach to the Ethernet interface list. */
1147         ether_ifattach(ifp, sc->eaddr);
1148
1149 #if __FreeBSD_version < 500000
1150         callout_init(&sc->bce_tick_callout);
1151         callout_init(&sc->bce_pulse_callout);
1152 #else
1153         callout_init_mtx(&sc->bce_tick_callout, &sc->bce_mtx, 0);
1154         callout_init_mtx(&sc->bce_pulse_callout, &sc->bce_mtx, 0);
1155 #endif
1156
1157         /* Hookup IRQ last. */
1158         rc = bus_setup_intr(dev, sc->bce_res_irq, INTR_TYPE_NET | INTR_MPSAFE,
1159                 NULL, bce_intr, sc, &sc->bce_intrhand);
1160
1161         if (rc) {
1162                 BCE_PRINTF("%s(%d): Failed to setup IRQ!\n",
1163                     __FILE__, __LINE__);
1164                 bce_detach(dev);
1165                 goto bce_attach_exit;
1166         }
1167
1168         /*
1169          * At this point we've acquired all the resources
1170          * we need to run so there's no turning back, we're
1171          * cleared for launch.
1172          */
1173
1174         /* Print some important debugging info. */
1175         DBRUNMSG(BCE_INFO, bce_dump_driver_state(sc));
1176
1177         /* Add the supported sysctls to the kernel. */
1178         bce_add_sysctls(sc);
1179
1180         BCE_LOCK(sc);
1181
1182         /*
1183          * The chip reset earlier notified the bootcode that
1184          * a driver is present.  We now need to start our pulse
1185          * routine so that the bootcode is reminded that we're
1186          * still running.
1187          */
1188         bce_pulse(sc);
1189
1190         bce_mgmt_init_locked(sc);
1191         BCE_UNLOCK(sc);
1192
1193         /* Finally, print some useful adapter info */
1194         bce_print_adapter_info(sc);
1195         DBPRINT(sc, BCE_FATAL, "%s(): sc = %p\n",
1196                 __FUNCTION__, sc);
1197
1198         goto bce_attach_exit;
1199
1200 bce_attach_fail:
1201         bce_release_resources(sc);
1202
1203 bce_attach_exit:
1204
1205         DBEXIT(BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
1206
1207         return(rc);
1208 }
1209
1210
1211 /****************************************************************************/
1212 /* Device detach function.                                                  */
1213 /*                                                                          */
1214 /* Stops the controller, resets the controller, and releases resources.     */
1215 /*                                                                          */
1216 /* Returns:                                                                 */
1217 /*   0 on success, positive value on failure.                               */
1218 /****************************************************************************/
1219 static int
1220 bce_detach(device_t dev)
1221 {
1222         struct bce_softc *sc = device_get_softc(dev);
1223         struct ifnet *ifp;
1224         u32 msg;
1225
1226         DBENTER(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1227
1228         ifp = sc->bce_ifp;
1229
1230         /* Stop and reset the controller. */
1231         BCE_LOCK(sc);
1232
1233         /* Stop the pulse so the bootcode can go to driver absent state. */
1234         callout_stop(&sc->bce_pulse_callout);
1235
1236         bce_stop(sc);
1237         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1238                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1239         else
1240                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1241         bce_reset(sc, msg);
1242
1243         BCE_UNLOCK(sc);
1244
1245         ether_ifdetach(ifp);
1246
1247         /* If we have a child device on the MII bus remove it too. */
1248         bus_generic_detach(dev);
1249         device_delete_child(dev, sc->bce_miibus);
1250
1251         /* Release all remaining resources. */
1252         bce_release_resources(sc);
1253
1254         DBEXIT(BCE_VERBOSE_UNLOAD | BCE_VERBOSE_RESET);
1255
1256         return(0);
1257 }
1258
1259
1260 /****************************************************************************/
1261 /* Device shutdown function.                                                */
1262 /*                                                                          */
1263 /* Stops and resets the controller.                                         */
1264 /*                                                                          */
1265 /* Returns:                                                                 */
1266 /*   0 on success, positive value on failure.                               */
1267 /****************************************************************************/
1268 static int
1269 bce_shutdown(device_t dev)
1270 {
1271         struct bce_softc *sc = device_get_softc(dev);
1272         u32 msg;
1273
1274         DBENTER(BCE_VERBOSE);
1275
1276         BCE_LOCK(sc);
1277         bce_stop(sc);
1278         if (sc->bce_flags & BCE_NO_WOL_FLAG)
1279                 msg = BCE_DRV_MSG_CODE_UNLOAD_LNK_DN;
1280         else
1281                 msg = BCE_DRV_MSG_CODE_UNLOAD;
1282         bce_reset(sc, msg);
1283         BCE_UNLOCK(sc);
1284
1285         DBEXIT(BCE_VERBOSE);
1286
1287         return (0);
1288 }
1289
1290
1291 #ifdef BCE_DEBUG
1292 /****************************************************************************/
1293 /* Register read.                                                           */
1294 /*                                                                          */
1295 /* Returns:                                                                 */
1296 /*   The value of the register.                                             */
1297 /****************************************************************************/
1298 static u32
1299 bce_reg_rd(struct bce_softc *sc, u32 offset)
1300 {
1301         u32 val = bus_space_read_4(sc->bce_btag, sc->bce_bhandle, offset);
1302         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1303                 __FUNCTION__, offset, val);
1304         return val;
1305 }
1306
1307
1308 /****************************************************************************/
1309 /* Register write (16 bit).                                                 */
1310 /*                                                                          */
1311 /* Returns:                                                                 */
1312 /*   Nothing.                                                               */
1313 /****************************************************************************/
1314 static void
1315 bce_reg_wr16(struct bce_softc *sc, u32 offset, u16 val)
1316 {
1317         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%04X\n",
1318                 __FUNCTION__, offset, val);
1319         bus_space_write_2(sc->bce_btag, sc->bce_bhandle, offset, val);
1320 }
1321
1322
1323 /****************************************************************************/
1324 /* Register write.                                                          */
1325 /*                                                                          */
1326 /* Returns:                                                                 */
1327 /*   Nothing.                                                               */
1328 /****************************************************************************/
1329 static void
1330 bce_reg_wr(struct bce_softc *sc, u32 offset, u32 val)
1331 {
1332         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1333                 __FUNCTION__, offset, val);
1334         bus_space_write_4(sc->bce_btag, sc->bce_bhandle, offset, val);
1335 }
1336 #endif
1337
1338 /****************************************************************************/
1339 /* Indirect register read.                                                  */
1340 /*                                                                          */
1341 /* Reads NetXtreme II registers using an index/data register pair in PCI    */
1342 /* configuration space.  Using this mechanism avoids issues with posted     */
1343 /* reads but is much slower than memory-mapped I/O.                         */
1344 /*                                                                          */
1345 /* Returns:                                                                 */
1346 /*   The value of the register.                                             */
1347 /****************************************************************************/
1348 static u32
1349 bce_reg_rd_ind(struct bce_softc *sc, u32 offset)
1350 {
1351         device_t dev;
1352         dev = sc->bce_dev;
1353
1354         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1355 #ifdef BCE_DEBUG
1356         {
1357                 u32 val;
1358                 val = pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1359                 DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1360                         __FUNCTION__, offset, val);
1361                 return val;
1362         }
1363 #else
1364         return pci_read_config(dev, BCE_PCICFG_REG_WINDOW, 4);
1365 #endif
1366 }
1367
1368
1369 /****************************************************************************/
1370 /* Indirect register write.                                                 */
1371 /*                                                                          */
1372 /* Writes NetXtreme II registers using an index/data register pair in PCI   */
1373 /* configuration space.  Using this mechanism avoids issues with posted     */
1374 /* writes but is muchh slower than memory-mapped I/O.                       */
1375 /*                                                                          */
1376 /* Returns:                                                                 */
1377 /*   Nothing.                                                               */
1378 /****************************************************************************/
1379 static void
1380 bce_reg_wr_ind(struct bce_softc *sc, u32 offset, u32 val)
1381 {
1382         device_t dev;
1383         dev = sc->bce_dev;
1384
1385         DBPRINT(sc, BCE_INSANE_REG, "%s(); offset = 0x%08X, val = 0x%08X\n",
1386                 __FUNCTION__, offset, val);
1387
1388         pci_write_config(dev, BCE_PCICFG_REG_WINDOW_ADDRESS, offset, 4);
1389         pci_write_config(dev, BCE_PCICFG_REG_WINDOW, val, 4);
1390 }
1391
1392
1393 /****************************************************************************/
1394 /* Shared memory write.                                                     */
1395 /*                                                                          */
1396 /* Writes NetXtreme II shared memory region.                                */
1397 /*                                                                          */
1398 /* Returns:                                                                 */
1399 /*   Nothing.                                                               */
1400 /****************************************************************************/
1401 static void
1402 bce_shmem_wr(struct bce_softc *sc, u32 offset, u32 val)
1403 {
1404         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Writing 0x%08X  to  "
1405             "0x%08X\n", __FUNCTION__, val, offset);
1406
1407         bce_reg_wr_ind(sc, sc->bce_shmem_base + offset, val);
1408 }
1409
1410
1411 /****************************************************************************/
1412 /* Shared memory read.                                                      */
1413 /*                                                                          */
1414 /* Reads NetXtreme II shared memory region.                                 */
1415 /*                                                                          */
1416 /* Returns:                                                                 */
1417 /*   The 32 bit value read.                                                 */
1418 /****************************************************************************/
1419 static u32
1420 bce_shmem_rd(struct bce_softc *sc, u32 offset)
1421 {
1422         u32 val = bce_reg_rd_ind(sc, sc->bce_shmem_base + offset);
1423
1424         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "%s(): Reading 0x%08X from "
1425             "0x%08X\n", __FUNCTION__, val, offset);
1426
1427         return val;
1428 }
1429
1430
1431 #ifdef BCE_DEBUG
1432 /****************************************************************************/
1433 /* Context memory read.                                                     */
1434 /*                                                                          */
1435 /* The NetXtreme II controller uses context memory to track connection      */
1436 /* information for L2 and higher network protocols.                         */
1437 /*                                                                          */
1438 /* Returns:                                                                 */
1439 /*   The requested 32 bit value of context memory.                          */
1440 /****************************************************************************/
1441 static u32
1442 bce_ctx_rd(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset)
1443 {
1444         u32 idx, offset, retry_cnt = 5, val;
1445
1446         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 ||
1447             cid_addr & CTX_MASK), BCE_PRINTF("%s(): Invalid CID "
1448             "address: 0x%08X.\n", __FUNCTION__, cid_addr));
1449
1450         offset = ctx_offset + cid_addr;
1451
1452         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
1453                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
1454
1455                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_READ_REQ));
1456
1457                 for (idx = 0; idx < retry_cnt; idx++) {
1458                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1459                         if ((val & BCE_CTX_CTX_CTRL_READ_REQ) == 0)
1460                                 break;
1461                         DELAY(5);
1462                 }
1463
1464                 if (val & BCE_CTX_CTX_CTRL_READ_REQ)
1465                         BCE_PRINTF("%s(%d); Unable to read CTX memory: "
1466                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1467                             __FILE__, __LINE__, cid_addr, ctx_offset);
1468
1469                 val = REG_RD(sc, BCE_CTX_CTX_DATA);
1470         } else {
1471                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1472                 val = REG_RD(sc, BCE_CTX_DATA);
1473         }
1474
1475         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1476                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, val);
1477
1478         return(val);
1479 }
1480 #endif
1481
1482
1483 /****************************************************************************/
1484 /* Context memory write.                                                    */
1485 /*                                                                          */
1486 /* The NetXtreme II controller uses context memory to track connection      */
1487 /* information for L2 and higher network protocols.                         */
1488 /*                                                                          */
1489 /* Returns:                                                                 */
1490 /*   Nothing.                                                               */
1491 /****************************************************************************/
1492 static void
1493 bce_ctx_wr(struct bce_softc *sc, u32 cid_addr, u32 ctx_offset, u32 ctx_val)
1494 {
1495         u32 idx, offset = ctx_offset + cid_addr;
1496         u32 val, retry_cnt = 5;
1497
1498         DBPRINT(sc, BCE_EXTREME_CTX, "%s(); cid_addr = 0x%08X, offset = 0x%08X, "
1499                 "val = 0x%08X\n", __FUNCTION__, cid_addr, ctx_offset, ctx_val);
1500
1501         DBRUNIF((cid_addr > MAX_CID_ADDR || ctx_offset & 0x3 || cid_addr & CTX_MASK),
1502                 BCE_PRINTF("%s(): Invalid CID address: 0x%08X.\n",
1503                     __FUNCTION__, cid_addr));
1504
1505         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
1506                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
1507
1508                 REG_WR(sc, BCE_CTX_CTX_DATA, ctx_val);
1509                 REG_WR(sc, BCE_CTX_CTX_CTRL, (offset | BCE_CTX_CTX_CTRL_WRITE_REQ));
1510
1511                 for (idx = 0; idx < retry_cnt; idx++) {
1512                         val = REG_RD(sc, BCE_CTX_CTX_CTRL);
1513                         if ((val & BCE_CTX_CTX_CTRL_WRITE_REQ) == 0)
1514                                 break;
1515                         DELAY(5);
1516                 }
1517
1518                 if (val & BCE_CTX_CTX_CTRL_WRITE_REQ)
1519                         BCE_PRINTF("%s(%d); Unable to write CTX memory: "
1520                             "cid_addr = 0x%08X, offset = 0x%08X!\n",
1521                             __FILE__, __LINE__, cid_addr, ctx_offset);
1522
1523         } else {
1524                 REG_WR(sc, BCE_CTX_DATA_ADR, offset);
1525                 REG_WR(sc, BCE_CTX_DATA, ctx_val);
1526         }
1527 }
1528
1529
1530 /****************************************************************************/
1531 /* PHY register read.                                                       */
1532 /*                                                                          */
1533 /* Implements register reads on the MII bus.                                */
1534 /*                                                                          */
1535 /* Returns:                                                                 */
1536 /*   The value of the register.                                             */
1537 /****************************************************************************/
1538 static int
1539 bce_miibus_read_reg(device_t dev, int phy, int reg)
1540 {
1541         struct bce_softc *sc;
1542         u32 val;
1543         int i;
1544
1545         sc = device_get_softc(dev);
1546
1547         /* Make sure we are accessing the correct PHY address. */
1548         if (phy != sc->bce_phy_addr) {
1549                 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d "
1550                     "for PHY read!\n", phy);
1551                 return(0);
1552         }
1553
1554     /*
1555      * The 5709S PHY is an IEEE Clause 45 PHY
1556      * with special mappings to work with IEEE
1557      * Clause 22 register accesses.
1558      */
1559         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1560                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1561                         reg += 0x10;
1562         }
1563
1564     if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1565                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1566                 val &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1567
1568                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1569                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1570
1571                 DELAY(40);
1572         }
1573
1574
1575         val = BCE_MIPHY(phy) | BCE_MIREG(reg) |
1576             BCE_EMAC_MDIO_COMM_COMMAND_READ | BCE_EMAC_MDIO_COMM_DISEXT |
1577             BCE_EMAC_MDIO_COMM_START_BUSY;
1578         REG_WR(sc, BCE_EMAC_MDIO_COMM, val);
1579
1580         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1581                 DELAY(10);
1582
1583                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1584                 if (!(val & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1585                         DELAY(5);
1586
1587                         val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1588                         val &= BCE_EMAC_MDIO_COMM_DATA;
1589
1590                         break;
1591                 }
1592         }
1593
1594         if (val & BCE_EMAC_MDIO_COMM_START_BUSY) {
1595                 BCE_PRINTF("%s(%d): Error: PHY read timeout! phy = %d, "
1596                     "reg = 0x%04X\n", __FILE__, __LINE__, phy, reg);
1597                 val = 0x0;
1598         } else {
1599                 val = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1600         }
1601
1602
1603         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1604                 val = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1605                 val |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1606
1607                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val);
1608                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1609
1610                 DELAY(40);
1611         }
1612
1613         DB_PRINT_PHY_REG(reg, val);
1614         return (val & 0xffff);
1615
1616 }
1617
1618
1619 /****************************************************************************/
1620 /* PHY register write.                                                      */
1621 /*                                                                          */
1622 /* Implements register writes on the MII bus.                               */
1623 /*                                                                          */
1624 /* Returns:                                                                 */
1625 /*   The value of the register.                                             */
1626 /****************************************************************************/
1627 static int
1628 bce_miibus_write_reg(device_t dev, int phy, int reg, int val)
1629 {
1630         struct bce_softc *sc;
1631         u32 val1;
1632         int i;
1633
1634         sc = device_get_softc(dev);
1635
1636         /* Make sure we are accessing the correct PHY address. */
1637         if (phy != sc->bce_phy_addr) {
1638                 DBPRINT(sc, BCE_INSANE_PHY, "Invalid PHY address %d "
1639                     "for PHY write!\n", phy);
1640                 return(0);
1641         }
1642
1643         DB_PRINT_PHY_REG(reg, val);
1644
1645         /*
1646          * The 5709S PHY is an IEEE Clause 45 PHY
1647          * with special mappings to work with IEEE
1648          * Clause 22 register accesses.
1649          */
1650         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
1651                 if (reg >= MII_BMCR && reg <= MII_ANLPRNP)
1652                         reg += 0x10;
1653         }
1654
1655         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1656                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1657                 val1 &= ~BCE_EMAC_MDIO_MODE_AUTO_POLL;
1658
1659                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1660                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1661
1662                 DELAY(40);
1663         }
1664
1665         val1 = BCE_MIPHY(phy) | BCE_MIREG(reg) | val |
1666             BCE_EMAC_MDIO_COMM_COMMAND_WRITE |
1667             BCE_EMAC_MDIO_COMM_START_BUSY | BCE_EMAC_MDIO_COMM_DISEXT;
1668         REG_WR(sc, BCE_EMAC_MDIO_COMM, val1);
1669
1670         for (i = 0; i < BCE_PHY_TIMEOUT; i++) {
1671                 DELAY(10);
1672
1673                 val1 = REG_RD(sc, BCE_EMAC_MDIO_COMM);
1674                 if (!(val1 & BCE_EMAC_MDIO_COMM_START_BUSY)) {
1675                         DELAY(5);
1676                         break;
1677                 }
1678         }
1679
1680         if (val1 & BCE_EMAC_MDIO_COMM_START_BUSY)
1681                 BCE_PRINTF("%s(%d): PHY write timeout!\n",
1682                     __FILE__, __LINE__);
1683
1684         if (sc->bce_phy_flags & BCE_PHY_INT_MODE_AUTO_POLLING_FLAG) {
1685                 val1 = REG_RD(sc, BCE_EMAC_MDIO_MODE);
1686                 val1 |= BCE_EMAC_MDIO_MODE_AUTO_POLL;
1687
1688                 REG_WR(sc, BCE_EMAC_MDIO_MODE, val1);
1689                 REG_RD(sc, BCE_EMAC_MDIO_MODE);
1690
1691                 DELAY(40);
1692         }
1693
1694         return 0;
1695 }
1696
1697
1698 /****************************************************************************/
1699 /* MII bus status change.                                                   */
1700 /*                                                                          */
1701 /* Called by the MII bus driver when the PHY establishes link to set the    */
1702 /* MAC interface registers.                                                 */
1703 /*                                                                          */
1704 /* Returns:                                                                 */
1705 /*   Nothing.                                                               */
1706 /****************************************************************************/
1707 static void
1708 bce_miibus_statchg(device_t dev)
1709 {
1710         struct bce_softc *sc;
1711         struct mii_data *mii;
1712         int val;
1713
1714         sc = device_get_softc(dev);
1715
1716         DBENTER(BCE_VERBOSE_PHY);
1717
1718         mii = device_get_softc(sc->bce_miibus);
1719
1720         val = REG_RD(sc, BCE_EMAC_MODE);
1721         val &= ~(BCE_EMAC_MODE_PORT | BCE_EMAC_MODE_HALF_DUPLEX |
1722             BCE_EMAC_MODE_MAC_LOOP | BCE_EMAC_MODE_FORCE_LINK |
1723             BCE_EMAC_MODE_25G);
1724
1725         /* Set MII or GMII interface based on the PHY speed. */
1726         switch (IFM_SUBTYPE(mii->mii_media_active)) {
1727         case IFM_10_T:
1728                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
1729                         DBPRINT(sc, BCE_INFO_PHY,
1730                             "Enabling 10Mb interface.\n");
1731                         val |= BCE_EMAC_MODE_PORT_MII_10;
1732                         break;
1733                 }
1734                 /* fall-through */
1735         case IFM_100_TX:
1736                 DBPRINT(sc, BCE_INFO_PHY, "Enabling MII interface.\n");
1737                 val |= BCE_EMAC_MODE_PORT_MII;
1738                 break;
1739         case IFM_2500_SX:
1740                 DBPRINT(sc, BCE_INFO_PHY, "Enabling 2.5G MAC mode.\n");
1741                 val |= BCE_EMAC_MODE_25G;
1742                 /* fall-through */
1743         case IFM_1000_T:
1744         case IFM_1000_SX:
1745                 DBPRINT(sc, BCE_INFO_PHY, "Enabling GMII interface.\n");
1746                 val |= BCE_EMAC_MODE_PORT_GMII;
1747                 break;
1748         default:
1749                 DBPRINT(sc, BCE_INFO_PHY, "Unknown link speed, enabling "
1750                     "default GMII interface.\n");
1751                 val |= BCE_EMAC_MODE_PORT_GMII;
1752         }
1753
1754         /* Set half or full duplex based on PHY settings. */
1755         if ((mii->mii_media_active & IFM_GMASK) == IFM_HDX) {
1756                 DBPRINT(sc, BCE_INFO_PHY,
1757                     "Setting Half-Duplex interface.\n");
1758                 val |= BCE_EMAC_MODE_HALF_DUPLEX;
1759         } else
1760                 DBPRINT(sc, BCE_INFO_PHY,
1761                     "Setting Full-Duplex interface.\n");
1762
1763         REG_WR(sc, BCE_EMAC_MODE, val);
1764
1765         /* FLAG0 is set if RX is enabled and FLAG1 if TX is enabled */
1766         if (mii->mii_media_active & IFM_FLAG0) {
1767                 DBPRINT(sc, BCE_INFO_PHY,
1768                     "%s(): Enabling RX flow control.\n", __FUNCTION__);
1769                 BCE_SETBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
1770         } else {
1771                 DBPRINT(sc, BCE_INFO_PHY,
1772                     "%s(): Disabling RX flow control.\n", __FUNCTION__);
1773                 BCE_CLRBIT(sc, BCE_EMAC_RX_MODE, BCE_EMAC_RX_MODE_FLOW_EN);
1774         }
1775
1776         if (mii->mii_media_active & IFM_FLAG1) {
1777                 DBPRINT(sc, BCE_INFO_PHY,
1778                     "%s(): Enabling TX flow control.\n", __FUNCTION__);
1779                 BCE_SETBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
1780                 sc->bce_flags |= BCE_USING_TX_FLOW_CONTROL;
1781         } else {
1782                 DBPRINT(sc, BCE_INFO_PHY,
1783                     "%s(): Disabling TX flow control.\n", __FUNCTION__);
1784                 BCE_CLRBIT(sc, BCE_EMAC_TX_MODE, BCE_EMAC_TX_MODE_FLOW_EN);
1785                 sc->bce_flags &= ~BCE_USING_TX_FLOW_CONTROL;
1786         }
1787
1788         /* ToDo: Update watermarks in bce_init_rx_context(). */
1789
1790         DBEXIT(BCE_VERBOSE_PHY);
1791 }
1792
1793
1794 /****************************************************************************/
1795 /* Acquire NVRAM lock.                                                      */
1796 /*                                                                          */
1797 /* Before the NVRAM can be accessed the caller must acquire an NVRAM lock.  */
1798 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1799 /* for use by the driver.                                                   */
1800 /*                                                                          */
1801 /* Returns:                                                                 */
1802 /*   0 on success, positive value on failure.                               */
1803 /****************************************************************************/
1804 static int
1805 bce_acquire_nvram_lock(struct bce_softc *sc)
1806 {
1807         u32 val;
1808         int j, rc = 0;
1809
1810         DBENTER(BCE_VERBOSE_NVRAM);
1811
1812         /* Request access to the flash interface. */
1813         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_SET2);
1814         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1815                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1816                 if (val & BCE_NVM_SW_ARB_ARB_ARB2)
1817                         break;
1818
1819                 DELAY(5);
1820         }
1821
1822         if (j >= NVRAM_TIMEOUT_COUNT) {
1823                 DBPRINT(sc, BCE_WARN, "Timeout acquiring NVRAM lock!\n");
1824                 rc = EBUSY;
1825         }
1826
1827         DBEXIT(BCE_VERBOSE_NVRAM);
1828         return (rc);
1829 }
1830
1831
1832 /****************************************************************************/
1833 /* Release NVRAM lock.                                                      */
1834 /*                                                                          */
1835 /* When the caller is finished accessing NVRAM the lock must be released.   */
1836 /* Locks 0 and 2 are reserved, lock 1 is used by firmware and lock 2 is     */
1837 /* for use by the driver.                                                   */
1838 /*                                                                          */
1839 /* Returns:                                                                 */
1840 /*   0 on success, positive value on failure.                               */
1841 /****************************************************************************/
1842 static int
1843 bce_release_nvram_lock(struct bce_softc *sc)
1844 {
1845         u32 val;
1846         int j, rc = 0;
1847
1848         DBENTER(BCE_VERBOSE_NVRAM);
1849
1850         /*
1851          * Relinquish nvram interface.
1852          */
1853         REG_WR(sc, BCE_NVM_SW_ARB, BCE_NVM_SW_ARB_ARB_REQ_CLR2);
1854
1855         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1856                 val = REG_RD(sc, BCE_NVM_SW_ARB);
1857                 if (!(val & BCE_NVM_SW_ARB_ARB_ARB2))
1858                         break;
1859
1860                 DELAY(5);
1861         }
1862
1863         if (j >= NVRAM_TIMEOUT_COUNT) {
1864                 DBPRINT(sc, BCE_WARN, "Timeout releasing NVRAM lock!\n");
1865                 rc = EBUSY;
1866         }
1867
1868         DBEXIT(BCE_VERBOSE_NVRAM);
1869         return (rc);
1870 }
1871
1872
1873 #ifdef BCE_NVRAM_WRITE_SUPPORT
1874 /****************************************************************************/
1875 /* Enable NVRAM write access.                                               */
1876 /*                                                                          */
1877 /* Before writing to NVRAM the caller must enable NVRAM writes.             */
1878 /*                                                                          */
1879 /* Returns:                                                                 */
1880 /*   0 on success, positive value on failure.                               */
1881 /****************************************************************************/
1882 static int
1883 bce_enable_nvram_write(struct bce_softc *sc)
1884 {
1885         u32 val;
1886         int rc = 0;
1887
1888         DBENTER(BCE_VERBOSE_NVRAM);
1889
1890         val = REG_RD(sc, BCE_MISC_CFG);
1891         REG_WR(sc, BCE_MISC_CFG, val | BCE_MISC_CFG_NVM_WR_EN_PCI);
1892
1893         if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
1894                 int j;
1895
1896                 REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
1897                 REG_WR(sc, BCE_NVM_COMMAND,     BCE_NVM_COMMAND_WREN | BCE_NVM_COMMAND_DOIT);
1898
1899                 for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
1900                         DELAY(5);
1901
1902                         val = REG_RD(sc, BCE_NVM_COMMAND);
1903                         if (val & BCE_NVM_COMMAND_DONE)
1904                                 break;
1905                 }
1906
1907                 if (j >= NVRAM_TIMEOUT_COUNT) {
1908                         DBPRINT(sc, BCE_WARN, "Timeout writing NVRAM!\n");
1909                         rc = EBUSY;
1910                 }
1911         }
1912
1913         DBENTER(BCE_VERBOSE_NVRAM);
1914         return (rc);
1915 }
1916
1917
1918 /****************************************************************************/
1919 /* Disable NVRAM write access.                                              */
1920 /*                                                                          */
1921 /* When the caller is finished writing to NVRAM write access must be        */
1922 /* disabled.                                                                */
1923 /*                                                                          */
1924 /* Returns:                                                                 */
1925 /*   Nothing.                                                               */
1926 /****************************************************************************/
1927 static void
1928 bce_disable_nvram_write(struct bce_softc *sc)
1929 {
1930         u32 val;
1931
1932         DBENTER(BCE_VERBOSE_NVRAM);
1933
1934         val = REG_RD(sc, BCE_MISC_CFG);
1935         REG_WR(sc, BCE_MISC_CFG, val & ~BCE_MISC_CFG_NVM_WR_EN);
1936
1937         DBEXIT(BCE_VERBOSE_NVRAM);
1938
1939 }
1940 #endif
1941
1942
1943 /****************************************************************************/
1944 /* Enable NVRAM access.                                                     */
1945 /*                                                                          */
1946 /* Before accessing NVRAM for read or write operations the caller must      */
1947 /* enabled NVRAM access.                                                    */
1948 /*                                                                          */
1949 /* Returns:                                                                 */
1950 /*   Nothing.                                                               */
1951 /****************************************************************************/
1952 static void
1953 bce_enable_nvram_access(struct bce_softc *sc)
1954 {
1955         u32 val;
1956
1957         DBENTER(BCE_VERBOSE_NVRAM);
1958
1959         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1960         /* Enable both bits, even on read. */
1961         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val |
1962             BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN);
1963
1964         DBEXIT(BCE_VERBOSE_NVRAM);
1965 }
1966
1967
1968 /****************************************************************************/
1969 /* Disable NVRAM access.                                                    */
1970 /*                                                                          */
1971 /* When the caller is finished accessing NVRAM access must be disabled.     */
1972 /*                                                                          */
1973 /* Returns:                                                                 */
1974 /*   Nothing.                                                               */
1975 /****************************************************************************/
1976 static void
1977 bce_disable_nvram_access(struct bce_softc *sc)
1978 {
1979         u32 val;
1980
1981         DBENTER(BCE_VERBOSE_NVRAM);
1982
1983         val = REG_RD(sc, BCE_NVM_ACCESS_ENABLE);
1984
1985         /* Disable both bits, even after read. */
1986         REG_WR(sc, BCE_NVM_ACCESS_ENABLE, val &
1987             ~(BCE_NVM_ACCESS_ENABLE_EN | BCE_NVM_ACCESS_ENABLE_WR_EN));
1988
1989         DBEXIT(BCE_VERBOSE_NVRAM);
1990 }
1991
1992
1993 #ifdef BCE_NVRAM_WRITE_SUPPORT
1994 /****************************************************************************/
1995 /* Erase NVRAM page before writing.                                         */
1996 /*                                                                          */
1997 /* Non-buffered flash parts require that a page be erased before it is      */
1998 /* written.                                                                 */
1999 /*                                                                          */
2000 /* Returns:                                                                 */
2001 /*   0 on success, positive value on failure.                               */
2002 /****************************************************************************/
2003 static int
2004 bce_nvram_erase_page(struct bce_softc *sc, u32 offset)
2005 {
2006         u32 cmd;
2007         int j, rc = 0;
2008
2009         DBENTER(BCE_VERBOSE_NVRAM);
2010
2011         /* Buffered flash doesn't require an erase. */
2012         if (sc->bce_flash_info->flags & BCE_NV_BUFFERED)
2013                 goto bce_nvram_erase_page_exit;
2014
2015         /* Build an erase command. */
2016         cmd = BCE_NVM_COMMAND_ERASE | BCE_NVM_COMMAND_WR |
2017             BCE_NVM_COMMAND_DOIT;
2018
2019         /*
2020          * Clear the DONE bit separately, set the NVRAM adress to erase,
2021          * and issue the erase command.
2022          */
2023         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2024         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2025         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2026
2027         /* Wait for completion. */
2028         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2029                 u32 val;
2030
2031                 DELAY(5);
2032
2033                 val = REG_RD(sc, BCE_NVM_COMMAND);
2034                 if (val & BCE_NVM_COMMAND_DONE)
2035                         break;
2036         }
2037
2038         if (j >= NVRAM_TIMEOUT_COUNT) {
2039                 DBPRINT(sc, BCE_WARN, "Timeout erasing NVRAM.\n");
2040                 rc = EBUSY;
2041         }
2042
2043 bce_nvram_erase_page_exit:
2044         DBEXIT(BCE_VERBOSE_NVRAM);
2045         return (rc);
2046 }
2047 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2048
2049
2050 /****************************************************************************/
2051 /* Read a dword (32 bits) from NVRAM.                                       */
2052 /*                                                                          */
2053 /* Read a 32 bit word from NVRAM.  The caller is assumed to have already    */
2054 /* obtained the NVRAM lock and enabled the controller for NVRAM access.     */
2055 /*                                                                          */
2056 /* Returns:                                                                 */
2057 /*   0 on success and the 32 bit value read, positive value on failure.     */
2058 /****************************************************************************/
2059 static int
2060 bce_nvram_read_dword(struct bce_softc *sc,
2061     u32 offset, u8 *ret_val, u32 cmd_flags)
2062 {
2063         u32 cmd;
2064         int i, rc = 0;
2065
2066         DBENTER(BCE_EXTREME_NVRAM);
2067
2068         /* Build the command word. */
2069         cmd = BCE_NVM_COMMAND_DOIT | cmd_flags;
2070
2071         /* Calculate the offset for buffered flash if translation is used. */
2072         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2073                 offset = ((offset / sc->bce_flash_info->page_size) <<
2074                     sc->bce_flash_info->page_bits) +
2075                     (offset % sc->bce_flash_info->page_size);
2076         }
2077
2078         /*
2079          * Clear the DONE bit separately, set the address to read,
2080          * and issue the read.
2081          */
2082         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2083         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2084         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2085
2086         /* Wait for completion. */
2087         for (i = 0; i < NVRAM_TIMEOUT_COUNT; i++) {
2088                 u32 val;
2089
2090                 DELAY(5);
2091
2092                 val = REG_RD(sc, BCE_NVM_COMMAND);
2093                 if (val & BCE_NVM_COMMAND_DONE) {
2094                         val = REG_RD(sc, BCE_NVM_READ);
2095
2096                         val = bce_be32toh(val);
2097                         memcpy(ret_val, &val, 4);
2098                         break;
2099                 }
2100         }
2101
2102         /* Check for errors. */
2103         if (i >= NVRAM_TIMEOUT_COUNT) {
2104                 BCE_PRINTF("%s(%d): Timeout error reading NVRAM at "
2105                     "offset 0x%08X!\n", __FILE__, __LINE__, offset);
2106                 rc = EBUSY;
2107         }
2108
2109         DBEXIT(BCE_EXTREME_NVRAM);
2110         return(rc);
2111 }
2112
2113
2114 #ifdef BCE_NVRAM_WRITE_SUPPORT
2115 /****************************************************************************/
2116 /* Write a dword (32 bits) to NVRAM.                                        */
2117 /*                                                                          */
2118 /* Write a 32 bit word to NVRAM.  The caller is assumed to have already     */
2119 /* obtained the NVRAM lock, enabled the controller for NVRAM access, and    */
2120 /* enabled NVRAM write access.                                              */
2121 /*                                                                          */
2122 /* Returns:                                                                 */
2123 /*   0 on success, positive value on failure.                               */
2124 /****************************************************************************/
2125 static int
2126 bce_nvram_write_dword(struct bce_softc *sc, u32 offset, u8 *val,
2127         u32 cmd_flags)
2128 {
2129         u32 cmd, val32;
2130         int j, rc = 0;
2131
2132         DBENTER(BCE_VERBOSE_NVRAM);
2133
2134         /* Build the command word. */
2135         cmd = BCE_NVM_COMMAND_DOIT | BCE_NVM_COMMAND_WR | cmd_flags;
2136
2137         /* Calculate the offset for buffered flash if translation is used. */
2138         if (sc->bce_flash_info->flags & BCE_NV_TRANSLATE) {
2139                 offset = ((offset / sc->bce_flash_info->page_size) <<
2140                     sc->bce_flash_info->page_bits) +
2141                     (offset % sc->bce_flash_info->page_size);
2142         }
2143
2144         /*
2145          * Clear the DONE bit separately, convert NVRAM data to big-endian,
2146          * set the NVRAM address to write, and issue the write command
2147          */
2148         REG_WR(sc, BCE_NVM_COMMAND, BCE_NVM_COMMAND_DONE);
2149         memcpy(&val32, val, 4);
2150         val32 = htobe32(val32);
2151         REG_WR(sc, BCE_NVM_WRITE, val32);
2152         REG_WR(sc, BCE_NVM_ADDR, offset & BCE_NVM_ADDR_NVM_ADDR_VALUE);
2153         REG_WR(sc, BCE_NVM_COMMAND, cmd);
2154
2155         /* Wait for completion. */
2156         for (j = 0; j < NVRAM_TIMEOUT_COUNT; j++) {
2157                 DELAY(5);
2158
2159                 if (REG_RD(sc, BCE_NVM_COMMAND) & BCE_NVM_COMMAND_DONE)
2160                         break;
2161         }
2162         if (j >= NVRAM_TIMEOUT_COUNT) {
2163                 BCE_PRINTF("%s(%d): Timeout error writing NVRAM at "
2164                     "offset 0x%08X\n", __FILE__, __LINE__, offset);
2165                 rc = EBUSY;
2166         }
2167
2168         DBEXIT(BCE_VERBOSE_NVRAM);
2169         return (rc);
2170 }
2171 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2172
2173
2174 /****************************************************************************/
2175 /* Initialize NVRAM access.                                                 */
2176 /*                                                                          */
2177 /* Identify the NVRAM device in use and prepare the NVRAM interface to      */
2178 /* access that device.                                                      */
2179 /*                                                                          */
2180 /* Returns:                                                                 */
2181 /*   0 on success, positive value on failure.                               */
2182 /****************************************************************************/
2183 static int
2184 bce_init_nvram(struct bce_softc *sc)
2185 {
2186         u32 val;
2187         int j, entry_count, rc = 0;
2188         struct flash_spec *flash;
2189
2190         DBENTER(BCE_VERBOSE_NVRAM);
2191
2192         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
2193                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
2194                 sc->bce_flash_info = &flash_5709;
2195                 goto bce_init_nvram_get_flash_size;
2196         }
2197
2198         /* Determine the selected interface. */
2199         val = REG_RD(sc, BCE_NVM_CFG1);
2200
2201         entry_count = sizeof(flash_table) / sizeof(struct flash_spec);
2202
2203         /*
2204          * Flash reconfiguration is required to support additional
2205          * NVRAM devices not directly supported in hardware.
2206          * Check if the flash interface was reconfigured
2207          * by the bootcode.
2208          */
2209
2210         if (val & 0x40000000) {
2211                 /* Flash interface reconfigured by bootcode. */
2212
2213                 DBPRINT(sc,BCE_INFO_LOAD,
2214                         "bce_init_nvram(): Flash WAS reconfigured.\n");
2215
2216                 for (j = 0, flash = &flash_table[0]; j < entry_count;
2217                      j++, flash++) {
2218                         if ((val & FLASH_BACKUP_STRAP_MASK) ==
2219                             (flash->config1 & FLASH_BACKUP_STRAP_MASK)) {
2220                                 sc->bce_flash_info = flash;
2221                                 break;
2222                         }
2223                 }
2224         } else {
2225                 /* Flash interface not yet reconfigured. */
2226                 u32 mask;
2227
2228                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): Flash was NOT reconfigured.\n",
2229                         __FUNCTION__);
2230
2231                 if (val & (1 << 23))
2232                         mask = FLASH_BACKUP_STRAP_MASK;
2233                 else
2234                         mask = FLASH_STRAP_MASK;
2235
2236                 /* Look for the matching NVRAM device configuration data. */
2237                 for (j = 0, flash = &flash_table[0]; j < entry_count; j++, flash++) {
2238
2239                         /* Check if the device matches any of the known devices. */
2240                         if ((val & mask) == (flash->strapping & mask)) {
2241                                 /* Found a device match. */
2242                                 sc->bce_flash_info = flash;
2243
2244                                 /* Request access to the flash interface. */
2245                                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2246                                         return rc;
2247
2248                                 /* Reconfigure the flash interface. */
2249                                 bce_enable_nvram_access(sc);
2250                                 REG_WR(sc, BCE_NVM_CFG1, flash->config1);
2251                                 REG_WR(sc, BCE_NVM_CFG2, flash->config2);
2252                                 REG_WR(sc, BCE_NVM_CFG3, flash->config3);
2253                                 REG_WR(sc, BCE_NVM_WRITE1, flash->write1);
2254                                 bce_disable_nvram_access(sc);
2255                                 bce_release_nvram_lock(sc);
2256
2257                                 break;
2258                         }
2259                 }
2260         }
2261
2262         /* Check if a matching device was found. */
2263         if (j == entry_count) {
2264                 sc->bce_flash_info = NULL;
2265                 BCE_PRINTF("%s(%d): Unknown Flash NVRAM found!\n",
2266                     __FILE__, __LINE__);
2267                 DBEXIT(BCE_VERBOSE_NVRAM);
2268                 return (ENODEV);
2269         }
2270
2271 bce_init_nvram_get_flash_size:
2272         /* Write the flash config data to the shared memory interface. */
2273         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG2);
2274         val &= BCE_SHARED_HW_CFG2_NVM_SIZE_MASK;
2275         if (val)
2276                 sc->bce_flash_size = val;
2277         else
2278                 sc->bce_flash_size = sc->bce_flash_info->total_size;
2279
2280         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Found %s, size = 0x%08X\n",
2281             __FUNCTION__, sc->bce_flash_info->name,
2282             sc->bce_flash_info->total_size);
2283
2284         DBEXIT(BCE_VERBOSE_NVRAM);
2285         return rc;
2286 }
2287
2288
2289 /****************************************************************************/
2290 /* Read an arbitrary range of data from NVRAM.                              */
2291 /*                                                                          */
2292 /* Prepares the NVRAM interface for access and reads the requested data     */
2293 /* into the supplied buffer.                                                */
2294 /*                                                                          */
2295 /* Returns:                                                                 */
2296 /*   0 on success and the data read, positive value on failure.             */
2297 /****************************************************************************/
2298 static int
2299 bce_nvram_read(struct bce_softc *sc, u32 offset, u8 *ret_buf,
2300         int buf_size)
2301 {
2302         int rc = 0;
2303         u32 cmd_flags, offset32, len32, extra;
2304
2305         DBENTER(BCE_VERBOSE_NVRAM);
2306
2307         if (buf_size == 0)
2308                 goto bce_nvram_read_exit;
2309
2310         /* Request access to the flash interface. */
2311         if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2312                 goto bce_nvram_read_exit;
2313
2314         /* Enable access to flash interface */
2315         bce_enable_nvram_access(sc);
2316
2317         len32 = buf_size;
2318         offset32 = offset;
2319         extra = 0;
2320
2321         cmd_flags = 0;
2322
2323         if (offset32 & 3) {
2324                 u8 buf[4];
2325                 u32 pre_len;
2326
2327                 offset32 &= ~3;
2328                 pre_len = 4 - (offset & 3);
2329
2330                 if (pre_len >= len32) {
2331                         pre_len = len32;
2332                         cmd_flags = BCE_NVM_COMMAND_FIRST | BCE_NVM_COMMAND_LAST;
2333                 }
2334                 else {
2335                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2336                 }
2337
2338                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2339
2340                 if (rc)
2341                         return rc;
2342
2343                 memcpy(ret_buf, buf + (offset & 3), pre_len);
2344
2345                 offset32 += 4;
2346                 ret_buf += pre_len;
2347                 len32 -= pre_len;
2348         }
2349
2350         if (len32 & 3) {
2351                 extra = 4 - (len32 & 3);
2352                 len32 = (len32 + 4) & ~3;
2353         }
2354
2355         if (len32 == 4) {
2356                 u8 buf[4];
2357
2358                 if (cmd_flags)
2359                         cmd_flags = BCE_NVM_COMMAND_LAST;
2360                 else
2361                         cmd_flags = BCE_NVM_COMMAND_FIRST |
2362                                     BCE_NVM_COMMAND_LAST;
2363
2364                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2365
2366                 memcpy(ret_buf, buf, 4 - extra);
2367         }
2368         else if (len32 > 0) {
2369                 u8 buf[4];
2370
2371                 /* Read the first word. */
2372                 if (cmd_flags)
2373                         cmd_flags = 0;
2374                 else
2375                         cmd_flags = BCE_NVM_COMMAND_FIRST;
2376
2377                 rc = bce_nvram_read_dword(sc, offset32, ret_buf, cmd_flags);
2378
2379                 /* Advance to the next dword. */
2380                 offset32 += 4;
2381                 ret_buf += 4;
2382                 len32 -= 4;
2383
2384                 while (len32 > 4 && rc == 0) {
2385                         rc = bce_nvram_read_dword(sc, offset32, ret_buf, 0);
2386
2387                         /* Advance to the next dword. */
2388                         offset32 += 4;
2389                         ret_buf += 4;
2390                         len32 -= 4;
2391                 }
2392
2393                 if (rc)
2394                         goto bce_nvram_read_locked_exit;
2395
2396                 cmd_flags = BCE_NVM_COMMAND_LAST;
2397                 rc = bce_nvram_read_dword(sc, offset32, buf, cmd_flags);
2398
2399                 memcpy(ret_buf, buf, 4 - extra);
2400         }
2401
2402 bce_nvram_read_locked_exit:
2403         /* Disable access to flash interface and release the lock. */
2404         bce_disable_nvram_access(sc);
2405         bce_release_nvram_lock(sc);
2406
2407 bce_nvram_read_exit:
2408         DBEXIT(BCE_VERBOSE_NVRAM);
2409         return rc;
2410 }
2411
2412
2413 #ifdef BCE_NVRAM_WRITE_SUPPORT
2414 /****************************************************************************/
2415 /* Write an arbitrary range of data from NVRAM.                             */
2416 /*                                                                          */
2417 /* Prepares the NVRAM interface for write access and writes the requested   */
2418 /* data from the supplied buffer.  The caller is responsible for            */
2419 /* calculating any appropriate CRCs.                                        */
2420 /*                                                                          */
2421 /* Returns:                                                                 */
2422 /*   0 on success, positive value on failure.                               */
2423 /****************************************************************************/
2424 static int
2425 bce_nvram_write(struct bce_softc *sc, u32 offset, u8 *data_buf,
2426         int buf_size)
2427 {
2428         u32 written, offset32, len32;
2429         u8 *buf, start[4], end[4];
2430         int rc = 0;
2431         int align_start, align_end;
2432
2433         DBENTER(BCE_VERBOSE_NVRAM);
2434
2435         buf = data_buf;
2436         offset32 = offset;
2437         len32 = buf_size;
2438         align_start = align_end = 0;
2439
2440         if ((align_start = (offset32 & 3))) {
2441                 offset32 &= ~3;
2442                 len32 += align_start;
2443                 if ((rc = bce_nvram_read(sc, offset32, start, 4)))
2444                         goto bce_nvram_write_exit;
2445         }
2446
2447         if (len32 & 3) {
2448                 if ((len32 > 4) || !align_start) {
2449                         align_end = 4 - (len32 & 3);
2450                         len32 += align_end;
2451                         if ((rc = bce_nvram_read(sc, offset32 + len32 - 4,
2452                                 end, 4))) {
2453                                 goto bce_nvram_write_exit;
2454                         }
2455                 }
2456         }
2457
2458         if (align_start || align_end) {
2459                 buf = malloc(len32, M_DEVBUF, M_NOWAIT);
2460                 if (buf == 0) {
2461                         rc = ENOMEM;
2462                         goto bce_nvram_write_exit;
2463                 }
2464
2465                 if (align_start) {
2466                         memcpy(buf, start, 4);
2467                 }
2468
2469                 if (align_end) {
2470                         memcpy(buf + len32 - 4, end, 4);
2471                 }
2472                 memcpy(buf + align_start, data_buf, buf_size);
2473         }
2474
2475         written = 0;
2476         while ((written < len32) && (rc == 0)) {
2477                 u32 page_start, page_end, data_start, data_end;
2478                 u32 addr, cmd_flags;
2479                 int i;
2480                 u8 flash_buffer[264];
2481
2482             /* Find the page_start addr */
2483                 page_start = offset32 + written;
2484                 page_start -= (page_start % sc->bce_flash_info->page_size);
2485                 /* Find the page_end addr */
2486                 page_end = page_start + sc->bce_flash_info->page_size;
2487                 /* Find the data_start addr */
2488                 data_start = (written == 0) ? offset32 : page_start;
2489                 /* Find the data_end addr */
2490                 data_end = (page_end > offset32 + len32) ?
2491                         (offset32 + len32) : page_end;
2492
2493                 /* Request access to the flash interface. */
2494                 if ((rc = bce_acquire_nvram_lock(sc)) != 0)
2495                         goto bce_nvram_write_exit;
2496
2497                 /* Enable access to flash interface */
2498                 bce_enable_nvram_access(sc);
2499
2500                 cmd_flags = BCE_NVM_COMMAND_FIRST;
2501                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2502                         int j;
2503
2504                         /* Read the whole page into the buffer
2505                          * (non-buffer flash only) */
2506                         for (j = 0; j < sc->bce_flash_info->page_size; j += 4) {
2507                                 if (j == (sc->bce_flash_info->page_size - 4)) {
2508                                         cmd_flags |= BCE_NVM_COMMAND_LAST;
2509                                 }
2510                                 rc = bce_nvram_read_dword(sc,
2511                                         page_start + j,
2512                                         &flash_buffer[j],
2513                                         cmd_flags);
2514
2515                                 if (rc)
2516                                         goto bce_nvram_write_locked_exit;
2517
2518                                 cmd_flags = 0;
2519                         }
2520                 }
2521
2522                 /* Enable writes to flash interface (unlock write-protect) */
2523                 if ((rc = bce_enable_nvram_write(sc)) != 0)
2524                         goto bce_nvram_write_locked_exit;
2525
2526                 /* Erase the page */
2527                 if ((rc = bce_nvram_erase_page(sc, page_start)) != 0)
2528                         goto bce_nvram_write_locked_exit;
2529
2530                 /* Re-enable the write again for the actual write */
2531                 bce_enable_nvram_write(sc);
2532
2533                 /* Loop to write back the buffer data from page_start to
2534                  * data_start */
2535                 i = 0;
2536                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2537                         for (addr = page_start; addr < data_start;
2538                                 addr += 4, i += 4) {
2539
2540                                 rc = bce_nvram_write_dword(sc, addr,
2541                                         &flash_buffer[i], cmd_flags);
2542
2543                                 if (rc != 0)
2544                                         goto bce_nvram_write_locked_exit;
2545
2546                                 cmd_flags = 0;
2547                         }
2548                 }
2549
2550                 /* Loop to write the new data from data_start to data_end */
2551                 for (addr = data_start; addr < data_end; addr += 4, i++) {
2552                         if ((addr == page_end - 4) ||
2553                                 ((sc->bce_flash_info->flags & BCE_NV_BUFFERED) &&
2554                                 (addr == data_end - 4))) {
2555
2556                                 cmd_flags |= BCE_NVM_COMMAND_LAST;
2557                         }
2558                         rc = bce_nvram_write_dword(sc, addr, buf,
2559                                 cmd_flags);
2560
2561                         if (rc != 0)
2562                                 goto bce_nvram_write_locked_exit;
2563
2564                         cmd_flags = 0;
2565                         buf += 4;
2566                 }
2567
2568                 /* Loop to write back the buffer data from data_end
2569                  * to page_end */
2570                 if (!(sc->bce_flash_info->flags & BCE_NV_BUFFERED)) {
2571                         for (addr = data_end; addr < page_end;
2572                                 addr += 4, i += 4) {
2573
2574                                 if (addr == page_end-4) {
2575                                         cmd_flags = BCE_NVM_COMMAND_LAST;
2576                                 }
2577                                 rc = bce_nvram_write_dword(sc, addr,
2578                                         &flash_buffer[i], cmd_flags);
2579
2580                                 if (rc != 0)
2581                                         goto bce_nvram_write_locked_exit;
2582
2583                                 cmd_flags = 0;
2584                         }
2585                 }
2586
2587                 /* Disable writes to flash interface (lock write-protect) */
2588                 bce_disable_nvram_write(sc);
2589
2590                 /* Disable access to flash interface */
2591                 bce_disable_nvram_access(sc);
2592                 bce_release_nvram_lock(sc);
2593
2594                 /* Increment written */
2595                 written += data_end - data_start;
2596         }
2597
2598         goto bce_nvram_write_exit;
2599
2600 bce_nvram_write_locked_exit:
2601                 bce_disable_nvram_write(sc);
2602                 bce_disable_nvram_access(sc);
2603                 bce_release_nvram_lock(sc);
2604
2605 bce_nvram_write_exit:
2606         if (align_start || align_end)
2607                 free(buf, M_DEVBUF);
2608
2609         DBEXIT(BCE_VERBOSE_NVRAM);
2610         return (rc);
2611 }
2612 #endif /* BCE_NVRAM_WRITE_SUPPORT */
2613
2614
2615 /****************************************************************************/
2616 /* Verifies that NVRAM is accessible and contains valid data.               */
2617 /*                                                                          */
2618 /* Reads the configuration data from NVRAM and verifies that the CRC is     */
2619 /* correct.                                                                 */
2620 /*                                                                          */
2621 /* Returns:                                                                 */
2622 /*   0 on success, positive value on failure.                               */
2623 /****************************************************************************/
2624 static int
2625 bce_nvram_test(struct bce_softc *sc)
2626 {
2627         u32 buf[BCE_NVRAM_SIZE / 4];
2628         u8 *data = (u8 *) buf;
2629         int rc = 0;
2630         u32 magic, csum;
2631
2632         DBENTER(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2633
2634         /*
2635          * Check that the device NVRAM is valid by reading
2636          * the magic value at offset 0.
2637          */
2638         if ((rc = bce_nvram_read(sc, 0, data, 4)) != 0) {
2639                 BCE_PRINTF("%s(%d): Unable to read NVRAM!\n",
2640                     __FILE__, __LINE__);
2641                 goto bce_nvram_test_exit;
2642         }
2643
2644         /*
2645          * Verify that offset 0 of the NVRAM contains
2646          * a valid magic number.
2647          */
2648     magic = bce_be32toh(buf[0]);
2649         if (magic != BCE_NVRAM_MAGIC) {
2650                 rc = ENODEV;
2651                 BCE_PRINTF("%s(%d): Invalid NVRAM magic value! "
2652                     "Expected: 0x%08X, Found: 0x%08X\n",
2653                     __FILE__, __LINE__, BCE_NVRAM_MAGIC, magic);
2654                 goto bce_nvram_test_exit;
2655         }
2656
2657         /*
2658          * Verify that the device NVRAM includes valid
2659          * configuration data.
2660          */
2661         if ((rc = bce_nvram_read(sc, 0x100, data, BCE_NVRAM_SIZE)) != 0) {
2662                 BCE_PRINTF("%s(%d): Unable to read manufacturing "
2663                     "Information from  NVRAM!\n", __FILE__, __LINE__);
2664                 goto bce_nvram_test_exit;
2665         }
2666
2667         csum = ether_crc32_le(data, 0x100);
2668         if (csum != BCE_CRC32_RESIDUAL) {
2669                 rc = ENODEV;
2670                 BCE_PRINTF("%s(%d): Invalid manufacturing information "
2671                     "NVRAM CRC! Expected: 0x%08X, Found: 0x%08X\n",
2672                     __FILE__, __LINE__, BCE_CRC32_RESIDUAL, csum);
2673                 goto bce_nvram_test_exit;
2674         }
2675
2676         csum = ether_crc32_le(data + 0x100, 0x100);
2677         if (csum != BCE_CRC32_RESIDUAL) {
2678                 rc = ENODEV;
2679                 BCE_PRINTF("%s(%d): Invalid feature configuration "
2680                     "information NVRAM CRC! Expected: 0x%08X, "
2681                     "Found: 08%08X\n", __FILE__, __LINE__,
2682                     BCE_CRC32_RESIDUAL, csum);
2683         }
2684
2685 bce_nvram_test_exit:
2686         DBEXIT(BCE_VERBOSE_NVRAM | BCE_VERBOSE_LOAD | BCE_VERBOSE_RESET);
2687         return rc;
2688 }
2689
2690
2691 /****************************************************************************/
2692 /* Identifies the current media type of the controller and sets the PHY     */
2693 /* address.                                                                 */
2694 /*                                                                          */
2695 /* Returns:                                                                 */
2696 /*   Nothing.                                                               */
2697 /****************************************************************************/
2698 static void
2699 bce_get_media(struct bce_softc *sc)
2700 {
2701         u32 val;
2702
2703         DBENTER(BCE_VERBOSE_PHY);
2704
2705         /* Assume PHY address for copper controllers. */
2706         sc->bce_phy_addr = 1;
2707
2708         if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) {
2709                 u32 val = REG_RD(sc, BCE_MISC_DUAL_MEDIA_CTRL);
2710                 u32 bond_id = val & BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID;
2711                 u32 strap;
2712
2713                 /*
2714                  * The BCM5709S is software configurable
2715                  * for Copper or SerDes operation.
2716                  */
2717                 if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_C) {
2718                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
2719                             "for copper.\n");
2720                         goto bce_get_media_exit;
2721                 } else if (bond_id == BCE_MISC_DUAL_MEDIA_CTRL_BOND_ID_S) {
2722                         DBPRINT(sc, BCE_INFO_LOAD, "5709 bonded "
2723                             "for dual media.\n");
2724                         sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2725                         goto bce_get_media_exit;
2726                 }
2727
2728                 if (val & BCE_MISC_DUAL_MEDIA_CTRL_STRAP_OVERRIDE)
2729                         strap = (val &
2730                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL) >> 21;
2731                 else
2732                         strap = (val &
2733                             BCE_MISC_DUAL_MEDIA_CTRL_PHY_CTRL_STRAP) >> 8;
2734
2735                 if (pci_get_function(sc->bce_dev) == 0) {
2736                         switch (strap) {
2737                         case 0x4:
2738                         case 0x5:
2739                         case 0x6:
2740                                 DBPRINT(sc, BCE_INFO_LOAD,
2741                                     "BCM5709 s/w configured for SerDes.\n");
2742                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2743                                 break;
2744                         default:
2745                                 DBPRINT(sc, BCE_INFO_LOAD,
2746                                     "BCM5709 s/w configured for Copper.\n");
2747                                 break;
2748                         }
2749                 } else {
2750                         switch (strap) {
2751                         case 0x1:
2752                         case 0x2:
2753                         case 0x4:
2754                                 DBPRINT(sc, BCE_INFO_LOAD,
2755                                     "BCM5709 s/w configured for SerDes.\n");
2756                                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2757                                 break;
2758                         default:
2759                                 DBPRINT(sc, BCE_INFO_LOAD,
2760                                     "BCM5709 s/w configured for Copper.\n");
2761                                 break;
2762                         }
2763                 }
2764
2765         } else if (BCE_CHIP_BOND_ID(sc) & BCE_CHIP_BOND_ID_SERDES_BIT)
2766                 sc->bce_phy_flags |= BCE_PHY_SERDES_FLAG;
2767
2768         if (sc->bce_phy_flags & BCE_PHY_SERDES_FLAG) {
2769
2770                 sc->bce_flags |= BCE_NO_WOL_FLAG;
2771
2772                 if (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)
2773                         sc->bce_phy_flags |= BCE_PHY_IEEE_CLAUSE_45_FLAG;
2774
2775                 if (BCE_CHIP_NUM(sc) != BCE_CHIP_NUM_5706) {
2776                         /* 5708S/09S/16S use a separate PHY for SerDes. */
2777                         sc->bce_phy_addr = 2;
2778
2779                         val = bce_shmem_rd(sc, BCE_SHARED_HW_CFG_CONFIG);
2780                         if (val & BCE_SHARED_HW_CFG_PHY_2_5G) {
2781                                 sc->bce_phy_flags |=
2782                                     BCE_PHY_2_5G_CAPABLE_FLAG;
2783                                 DBPRINT(sc, BCE_INFO_LOAD, "Found 2.5Gb "
2784                                     "capable adapter\n");
2785                         }
2786                 }
2787         } else if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) ||
2788             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5708))
2789                 sc->bce_phy_flags |= BCE_PHY_CRC_FIX_FLAG;
2790
2791 bce_get_media_exit:
2792         DBPRINT(sc, (BCE_INFO_LOAD | BCE_INFO_PHY),
2793                 "Using PHY address %d.\n", sc->bce_phy_addr);
2794
2795         DBEXIT(BCE_VERBOSE_PHY);
2796 }
2797
2798
2799 /****************************************************************************/
2800 /* Performs PHY initialization required before MII drivers access the       */
2801 /* device.                                                                  */
2802 /*                                                                          */
2803 /* Returns:                                                                 */
2804 /*   Nothing.                                                               */
2805 /****************************************************************************/
2806 static void
2807 bce_init_media(struct bce_softc *sc)
2808 {
2809         if ((sc->bce_phy_flags & BCE_PHY_IEEE_CLAUSE_45_FLAG) != 0) {
2810                 /*
2811                  * Configure 5709S/5716S PHYs to use traditional IEEE
2812                  * Clause 22 method. Otherwise we have no way to attach
2813                  * the PHY in mii(4) layer. PHY specific configuration
2814                  * is done in mii layer.
2815                  */
2816
2817                 /* Select auto-negotiation MMD of the PHY. */
2818                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
2819                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_ADDR_EXT);
2820                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
2821                     BRGPHY_ADDR_EXT, BRGPHY_ADDR_EXT_AN_MMD);
2822
2823                 /* Set IEEE0 block of AN MMD (assumed in brgphy(4) code). */
2824                 bce_miibus_write_reg(sc->bce_dev, sc->bce_phy_addr,
2825                     BRGPHY_BLOCK_ADDR, BRGPHY_BLOCK_ADDR_COMBO_IEEE0);
2826         }
2827 }
2828
2829
2830 /****************************************************************************/
2831 /* Free any DMA memory owned by the driver.                                 */
2832 /*                                                                          */
2833 /* Scans through each data structre that requires DMA memory and frees      */
2834 /* the memory if allocated.                                                 */
2835 /*                                                                          */
2836 /* Returns:                                                                 */
2837 /*   Nothing.                                                               */
2838 /****************************************************************************/
2839 static void
2840 bce_dma_free(struct bce_softc *sc)
2841 {
2842         int i;
2843
2844         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
2845
2846         /* Free, unmap, and destroy the status block. */
2847         if (sc->status_block != NULL) {
2848                 bus_dmamem_free(
2849                    sc->status_tag,
2850                     sc->status_block,
2851                     sc->status_map);
2852                 sc->status_block = NULL;
2853         }
2854
2855         if (sc->status_map != NULL) {
2856                 bus_dmamap_unload(
2857                     sc->status_tag,
2858                     sc->status_map);
2859                 bus_dmamap_destroy(sc->status_tag,
2860                     sc->status_map);
2861                 sc->status_map = NULL;
2862         }
2863
2864         if (sc->status_tag != NULL) {
2865                 bus_dma_tag_destroy(sc->status_tag);
2866                 sc->status_tag = NULL;
2867         }
2868
2869
2870         /* Free, unmap, and destroy the statistics block. */
2871         if (sc->stats_block != NULL) {
2872                 bus_dmamem_free(
2873                     sc->stats_tag,
2874                     sc->stats_block,
2875                     sc->stats_map);
2876                 sc->stats_block = NULL;
2877         }
2878
2879         if (sc->stats_map != NULL) {
2880                 bus_dmamap_unload(
2881                     sc->stats_tag,
2882                     sc->stats_map);
2883                 bus_dmamap_destroy(sc->stats_tag,
2884                     sc->stats_map);
2885                 sc->stats_map = NULL;
2886         }
2887
2888         if (sc->stats_tag != NULL) {
2889                 bus_dma_tag_destroy(sc->stats_tag);
2890                 sc->stats_tag = NULL;
2891         }
2892
2893
2894         /* Free, unmap and destroy all context memory pages. */
2895         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
2896                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
2897                 for (i = 0; i < sc->ctx_pages; i++ ) {
2898                         if (sc->ctx_block[i] != NULL) {
2899                                 bus_dmamem_free(
2900                                     sc->ctx_tag,
2901                                     sc->ctx_block[i],
2902                                     sc->ctx_map[i]);
2903                                 sc->ctx_block[i] = NULL;
2904                         }
2905
2906                         if (sc->ctx_map[i] != NULL) {
2907                                 bus_dmamap_unload(
2908                                     sc->ctx_tag,
2909                                     sc->ctx_map[i]);
2910                                 bus_dmamap_destroy(
2911                                     sc->ctx_tag,
2912                                     sc->ctx_map[i]);
2913                                 sc->ctx_map[i] = NULL;
2914                         }
2915                 }
2916
2917                 /* Destroy the context memory tag. */
2918                 if (sc->ctx_tag != NULL) {
2919                         bus_dma_tag_destroy(sc->ctx_tag);
2920                         sc->ctx_tag = NULL;
2921                 }
2922         }
2923
2924
2925         /* Free, unmap and destroy all TX buffer descriptor chain pages. */
2926         for (i = 0; i < TX_PAGES; i++ ) {
2927                 if (sc->tx_bd_chain[i] != NULL) {
2928                         bus_dmamem_free(
2929                             sc->tx_bd_chain_tag,
2930                             sc->tx_bd_chain[i],
2931                             sc->tx_bd_chain_map[i]);
2932                         sc->tx_bd_chain[i] = NULL;
2933                 }
2934
2935                 if (sc->tx_bd_chain_map[i] != NULL) {
2936                         bus_dmamap_unload(
2937                             sc->tx_bd_chain_tag,
2938                             sc->tx_bd_chain_map[i]);
2939                         bus_dmamap_destroy(
2940                             sc->tx_bd_chain_tag,
2941                             sc->tx_bd_chain_map[i]);
2942                         sc->tx_bd_chain_map[i] = NULL;
2943                 }
2944         }
2945
2946         /* Destroy the TX buffer descriptor tag. */
2947         if (sc->tx_bd_chain_tag != NULL) {
2948                 bus_dma_tag_destroy(sc->tx_bd_chain_tag);
2949                 sc->tx_bd_chain_tag = NULL;
2950         }
2951
2952
2953         /* Free, unmap and destroy all RX buffer descriptor chain pages. */
2954         for (i = 0; i < RX_PAGES; i++ ) {
2955                 if (sc->rx_bd_chain[i] != NULL) {
2956                         bus_dmamem_free(
2957                             sc->rx_bd_chain_tag,
2958                             sc->rx_bd_chain[i],
2959                             sc->rx_bd_chain_map[i]);
2960                         sc->rx_bd_chain[i] = NULL;
2961                 }
2962
2963                 if (sc->rx_bd_chain_map[i] != NULL) {
2964                         bus_dmamap_unload(
2965                             sc->rx_bd_chain_tag,
2966                             sc->rx_bd_chain_map[i]);
2967                         bus_dmamap_destroy(
2968                             sc->rx_bd_chain_tag,
2969                             sc->rx_bd_chain_map[i]);
2970                         sc->rx_bd_chain_map[i] = NULL;
2971                 }
2972         }
2973
2974         /* Destroy the RX buffer descriptor tag. */
2975         if (sc->rx_bd_chain_tag != NULL) {
2976                 bus_dma_tag_destroy(sc->rx_bd_chain_tag);
2977                 sc->rx_bd_chain_tag = NULL;
2978         }
2979
2980
2981 #ifdef BCE_JUMBO_HDRSPLIT
2982         /* Free, unmap and destroy all page buffer descriptor chain pages. */
2983         for (i = 0; i < PG_PAGES; i++ ) {
2984                 if (sc->pg_bd_chain[i] != NULL) {
2985                         bus_dmamem_free(
2986                             sc->pg_bd_chain_tag,
2987                             sc->pg_bd_chain[i],
2988                             sc->pg_bd_chain_map[i]);
2989                         sc->pg_bd_chain[i] = NULL;
2990                 }
2991
2992                 if (sc->pg_bd_chain_map[i] != NULL) {
2993                         bus_dmamap_unload(
2994                             sc->pg_bd_chain_tag,
2995                             sc->pg_bd_chain_map[i]);
2996                         bus_dmamap_destroy(
2997                             sc->pg_bd_chain_tag,
2998                             sc->pg_bd_chain_map[i]);
2999                         sc->pg_bd_chain_map[i] = NULL;
3000                 }
3001         }
3002
3003         /* Destroy the page buffer descriptor tag. */
3004         if (sc->pg_bd_chain_tag != NULL) {
3005                 bus_dma_tag_destroy(sc->pg_bd_chain_tag);
3006                 sc->pg_bd_chain_tag = NULL;
3007         }
3008 #endif
3009
3010
3011         /* Unload and destroy the TX mbuf maps. */
3012         for (i = 0; i < TOTAL_TX_BD; i++) {
3013                 if (sc->tx_mbuf_map[i] != NULL) {
3014                         bus_dmamap_unload(sc->tx_mbuf_tag,
3015                             sc->tx_mbuf_map[i]);
3016                         bus_dmamap_destroy(sc->tx_mbuf_tag,
3017                             sc->tx_mbuf_map[i]);
3018                         sc->tx_mbuf_map[i] = NULL;
3019                 }
3020         }
3021
3022         /* Destroy the TX mbuf tag. */
3023         if (sc->tx_mbuf_tag != NULL) {
3024                 bus_dma_tag_destroy(sc->tx_mbuf_tag);
3025                 sc->tx_mbuf_tag = NULL;
3026         }
3027
3028         /* Unload and destroy the RX mbuf maps. */
3029         for (i = 0; i < TOTAL_RX_BD; i++) {
3030                 if (sc->rx_mbuf_map[i] != NULL) {
3031                         bus_dmamap_unload(sc->rx_mbuf_tag,
3032                             sc->rx_mbuf_map[i]);
3033                         bus_dmamap_destroy(sc->rx_mbuf_tag,
3034                             sc->rx_mbuf_map[i]);
3035                         sc->rx_mbuf_map[i] = NULL;
3036                 }
3037         }
3038
3039         /* Destroy the RX mbuf tag. */
3040         if (sc->rx_mbuf_tag != NULL) {
3041                 bus_dma_tag_destroy(sc->rx_mbuf_tag);
3042                 sc->rx_mbuf_tag = NULL;
3043         }
3044
3045 #ifdef BCE_JUMBO_HDRSPLIT
3046         /* Unload and destroy the page mbuf maps. */
3047         for (i = 0; i < TOTAL_PG_BD; i++) {
3048                 if (sc->pg_mbuf_map[i] != NULL) {
3049                         bus_dmamap_unload(sc->pg_mbuf_tag,
3050                             sc->pg_mbuf_map[i]);
3051                         bus_dmamap_destroy(sc->pg_mbuf_tag,
3052                             sc->pg_mbuf_map[i]);
3053                         sc->pg_mbuf_map[i] = NULL;
3054                 }
3055         }
3056
3057         /* Destroy the page mbuf tag. */
3058         if (sc->pg_mbuf_tag != NULL) {
3059                 bus_dma_tag_destroy(sc->pg_mbuf_tag);
3060                 sc->pg_mbuf_tag = NULL;
3061         }
3062 #endif
3063
3064         /* Destroy the parent tag */
3065         if (sc->parent_tag != NULL) {
3066                 bus_dma_tag_destroy(sc->parent_tag);
3067                 sc->parent_tag = NULL;
3068         }
3069
3070         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_UNLOAD | BCE_VERBOSE_CTX);
3071 }
3072
3073
3074 /****************************************************************************/
3075 /* Get DMA memory from the OS.                                              */
3076 /*                                                                          */
3077 /* Validates that the OS has provided DMA buffers in response to a          */
3078 /* bus_dmamap_load() call and saves the physical address of those buffers.  */
3079 /* When the callback is used the OS will return 0 for the mapping function  */
3080 /* (bus_dmamap_load()) so we use the value of map_arg->maxsegs to pass any  */
3081 /* failures back to the caller.                                             */
3082 /*                                                                          */
3083 /* Returns:                                                                 */
3084 /*   Nothing.                                                               */
3085 /****************************************************************************/
3086 static void
3087 bce_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3088 {
3089         bus_addr_t *busaddr = arg;
3090
3091         KASSERT(nseg == 1, ("%s(): Too many segments returned (%d)!",
3092             __FUNCTION__, nseg));
3093         /* Simulate a mapping failure. */
3094         DBRUNIF(DB_RANDOMTRUE(dma_map_addr_failed_sim_control),
3095             error = ENOMEM);
3096
3097         /* ToDo: How to increment debug sim_count variable here? */
3098
3099         /* Check for an error and signal the caller that an error occurred. */
3100         if (error) {
3101                 *busaddr = 0;
3102         } else {
3103                 *busaddr = segs->ds_addr;
3104         }
3105
3106         return;
3107 }
3108
3109
3110 /****************************************************************************/
3111 /* Allocate any DMA memory needed by the driver.                            */
3112 /*                                                                          */
3113 /* Allocates DMA memory needed for the various global structures needed by  */
3114 /* hardware.                                                                */
3115 /*                                                                          */
3116 /* Memory alignment requirements:                                           */
3117 /* +-----------------+----------+----------+----------+----------+          */
3118 /* |                 |   5706   |   5708   |   5709   |   5716   |          */
3119 /* +-----------------+----------+----------+----------+----------+          */
3120 /* |Status Block     | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3121 /* |Statistics Block | 8 bytes  | 8 bytes  | 16 bytes | 16 bytes |          */
3122 /* |RX Buffers       | 16 bytes | 16 bytes | 16 bytes | 16 bytes |          */
3123 /* |PG Buffers       |   none   |   none   |   none   |   none   |          */
3124 /* |TX Buffers       |   none   |   none   |   none   |   none   |          */
3125 /* |Chain Pages(1)   |   4KiB   |   4KiB   |   4KiB   |   4KiB   |          */
3126 /* |Context Memory   |          |          |          |          |          */
3127 /* +-----------------+----------+----------+----------+----------+          */
3128 /*                                                                          */
3129 /* (1) Must align with CPU page size (BCM_PAGE_SZIE).                       */
3130 /*                                                                          */
3131 /* Returns:                                                                 */
3132 /*   0 for success, positive value for failure.                             */
3133 /****************************************************************************/
3134 static int
3135 bce_dma_alloc(device_t dev)
3136 {
3137         struct bce_softc *sc;
3138         int i, error, rc = 0;
3139         bus_size_t max_size, max_seg_size;
3140         int max_segments;
3141
3142         sc = device_get_softc(dev);
3143
3144         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3145
3146         /*
3147          * Allocate the parent bus DMA tag appropriate for PCI.
3148          */
3149         if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, BCE_DMA_BOUNDARY,
3150             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3151             BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, NULL, NULL,
3152             &sc->parent_tag)) {
3153                 BCE_PRINTF("%s(%d): Could not allocate parent DMA tag!\n",
3154                     __FILE__, __LINE__);
3155                 rc = ENOMEM;
3156                 goto bce_dma_alloc_exit;
3157         }
3158
3159         /*
3160          * Create a DMA tag for the status block, allocate and clear the
3161          * memory, map the memory into DMA space, and fetch the physical
3162          * address of the block.
3163          */
3164         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3165             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3166             NULL, NULL, BCE_STATUS_BLK_SZ, 1, BCE_STATUS_BLK_SZ,
3167             0, NULL, NULL, &sc->status_tag)) {
3168                 BCE_PRINTF("%s(%d): Could not allocate status block "
3169                     "DMA tag!\n", __FILE__, __LINE__);
3170                 rc = ENOMEM;
3171                 goto bce_dma_alloc_exit;
3172         }
3173
3174         if(bus_dmamem_alloc(sc->status_tag, (void **)&sc->status_block,
3175             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3176             &sc->status_map)) {
3177                 BCE_PRINTF("%s(%d): Could not allocate status block "
3178                     "DMA memory!\n", __FILE__, __LINE__);
3179                 rc = ENOMEM;
3180                 goto bce_dma_alloc_exit;
3181         }
3182
3183         error = bus_dmamap_load(sc->status_tag, sc->status_map,
3184             sc->status_block, BCE_STATUS_BLK_SZ, bce_dma_map_addr,
3185             &sc->status_block_paddr, BUS_DMA_NOWAIT);
3186
3187         if (error) {
3188                 BCE_PRINTF("%s(%d): Could not map status block "
3189                     "DMA memory!\n", __FILE__, __LINE__);
3190                 rc = ENOMEM;
3191                 goto bce_dma_alloc_exit;
3192         }
3193
3194         DBPRINT(sc, BCE_INFO_LOAD, "%s(): status_block_paddr = 0x%jX\n",
3195             __FUNCTION__, (uintmax_t) sc->status_block_paddr);
3196
3197         /*
3198          * Create a DMA tag for the statistics block, allocate and clear the
3199          * memory, map the memory into DMA space, and fetch the physical
3200          * address of the block.
3201          */
3202         if (bus_dma_tag_create(sc->parent_tag, BCE_DMA_ALIGN,
3203             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3204             NULL, NULL, BCE_STATS_BLK_SZ, 1, BCE_STATS_BLK_SZ,
3205             0, NULL, NULL, &sc->stats_tag)) {
3206                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3207                     "DMA tag!\n", __FILE__, __LINE__);
3208                 rc = ENOMEM;
3209                 goto bce_dma_alloc_exit;
3210         }
3211
3212         if (bus_dmamem_alloc(sc->stats_tag, (void **)&sc->stats_block,
3213             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->stats_map)) {
3214                 BCE_PRINTF("%s(%d): Could not allocate statistics block "
3215                     "DMA memory!\n", __FILE__, __LINE__);
3216                 rc = ENOMEM;
3217                 goto bce_dma_alloc_exit;
3218         }
3219
3220         error = bus_dmamap_load(sc->stats_tag, sc->stats_map,
3221             sc->stats_block, BCE_STATS_BLK_SZ, bce_dma_map_addr,
3222             &sc->stats_block_paddr, BUS_DMA_NOWAIT);
3223
3224         if(error) {
3225                 BCE_PRINTF("%s(%d): Could not map statistics block "
3226                     "DMA memory!\n", __FILE__, __LINE__);
3227                 rc = ENOMEM;
3228                 goto bce_dma_alloc_exit;
3229         }
3230
3231         DBPRINT(sc, BCE_INFO_LOAD, "%s(): stats_block_paddr = 0x%jX\n",
3232             __FUNCTION__, (uintmax_t) sc->stats_block_paddr);
3233
3234         /* BCM5709 uses host memory as cache for context memory. */
3235         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
3236             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
3237                 sc->ctx_pages = 0x2000 / BCM_PAGE_SIZE;
3238                 if (sc->ctx_pages == 0)
3239                         sc->ctx_pages = 1;
3240
3241                 DBRUNIF((sc->ctx_pages > 512),
3242                     BCE_PRINTF("%s(%d): Too many CTX pages! %d > 512\n",
3243                     __FILE__, __LINE__, sc->ctx_pages));
3244
3245                 /*
3246                  * Create a DMA tag for the context pages,
3247                  * allocate and clear the memory, map the
3248                  * memory into DMA space, and fetch the
3249                  * physical address of the block.
3250                  */
3251                 if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3252                     BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR,
3253                     NULL, NULL, BCM_PAGE_SIZE, 1, BCM_PAGE_SIZE,
3254                     0, NULL, NULL, &sc->ctx_tag)) {
3255                         BCE_PRINTF("%s(%d): Could not allocate CTX "
3256                             "DMA tag!\n", __FILE__, __LINE__);
3257                         rc = ENOMEM;
3258                         goto bce_dma_alloc_exit;
3259                 }
3260
3261                 for (i = 0; i < sc->ctx_pages; i++) {
3262
3263                         if(bus_dmamem_alloc(sc->ctx_tag,
3264                             (void **)&sc->ctx_block[i],
3265                             BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3266                             &sc->ctx_map[i])) {
3267                                 BCE_PRINTF("%s(%d): Could not allocate CTX "
3268                                     "DMA memory!\n", __FILE__, __LINE__);
3269                                 rc = ENOMEM;
3270                                 goto bce_dma_alloc_exit;
3271                         }
3272
3273                         error = bus_dmamap_load(sc->ctx_tag, sc->ctx_map[i],
3274                             sc->ctx_block[i], BCM_PAGE_SIZE, bce_dma_map_addr,
3275                             &sc->ctx_paddr[i], BUS_DMA_NOWAIT);
3276
3277                         if (error) {
3278                                 BCE_PRINTF("%s(%d): Could not map CTX "
3279                                     "DMA memory!\n", __FILE__, __LINE__);
3280                                 rc = ENOMEM;
3281                                 goto bce_dma_alloc_exit;
3282                         }
3283
3284                         DBPRINT(sc, BCE_INFO_LOAD, "%s(): ctx_paddr[%d] "
3285                             "= 0x%jX\n", __FUNCTION__, i,
3286                             (uintmax_t) sc->ctx_paddr[i]);
3287                 }
3288         }
3289
3290         /*
3291          * Create a DMA tag for the TX buffer descriptor chain,
3292          * allocate and clear the  memory, and fetch the
3293          * physical address of the block.
3294          */
3295         if(bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE, BCE_DMA_BOUNDARY,
3296             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3297             BCE_TX_CHAIN_PAGE_SZ, 1, BCE_TX_CHAIN_PAGE_SZ, 0,
3298             NULL, NULL, &sc->tx_bd_chain_tag)) {
3299                 BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3300                     "chain DMA tag!\n", __FILE__, __LINE__);
3301                 rc = ENOMEM;
3302                 goto bce_dma_alloc_exit;
3303         }
3304
3305         for (i = 0; i < TX_PAGES; i++) {
3306
3307                 if(bus_dmamem_alloc(sc->tx_bd_chain_tag,
3308                     (void **)&sc->tx_bd_chain[i],
3309                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3310                     &sc->tx_bd_chain_map[i])) {
3311                         BCE_PRINTF("%s(%d): Could not allocate TX descriptor "
3312                             "chain DMA memory!\n", __FILE__, __LINE__);
3313                         rc = ENOMEM;
3314                         goto bce_dma_alloc_exit;
3315                 }
3316
3317                 error = bus_dmamap_load(sc->tx_bd_chain_tag,
3318                     sc->tx_bd_chain_map[i], sc->tx_bd_chain[i],
3319                     BCE_TX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3320                     &sc->tx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3321
3322                 if (error) {
3323                         BCE_PRINTF("%s(%d): Could not map TX descriptor "
3324                             "chain DMA memory!\n", __FILE__, __LINE__);
3325                         rc = ENOMEM;
3326                         goto bce_dma_alloc_exit;
3327                 }
3328
3329                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): tx_bd_chain_paddr[%d] = "
3330                     "0x%jX\n", __FUNCTION__, i,
3331                     (uintmax_t) sc->tx_bd_chain_paddr[i]);
3332         }
3333
3334         /* Check the required size before mapping to conserve resources. */
3335         if (bce_tso_enable) {
3336                 max_size     = BCE_TSO_MAX_SIZE;
3337                 max_segments = BCE_MAX_SEGMENTS;
3338                 max_seg_size = BCE_TSO_MAX_SEG_SIZE;
3339         } else {
3340                 max_size     = MCLBYTES * BCE_MAX_SEGMENTS;
3341                 max_segments = BCE_MAX_SEGMENTS;
3342                 max_seg_size = MCLBYTES;
3343         }
3344
3345         /* Create a DMA tag for TX mbufs. */
3346         if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3347             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL, max_size,
3348             max_segments, max_seg_size, 0, NULL, NULL, &sc->tx_mbuf_tag)) {
3349                 BCE_PRINTF("%s(%d): Could not allocate TX mbuf DMA tag!\n",
3350                     __FILE__, __LINE__);
3351                 rc = ENOMEM;
3352                 goto bce_dma_alloc_exit;
3353         }
3354
3355         /* Create DMA maps for the TX mbufs clusters. */
3356         for (i = 0; i < TOTAL_TX_BD; i++) {
3357                 if (bus_dmamap_create(sc->tx_mbuf_tag, BUS_DMA_NOWAIT,
3358                         &sc->tx_mbuf_map[i])) {
3359                         BCE_PRINTF("%s(%d): Unable to create TX mbuf DMA "
3360                             "map!\n", __FILE__, __LINE__);
3361                         rc = ENOMEM;
3362                         goto bce_dma_alloc_exit;
3363                 }
3364         }
3365
3366         /*
3367          * Create a DMA tag for the RX buffer descriptor chain,
3368          * allocate and clear the memory, and fetch the physical
3369          * address of the blocks.
3370          */
3371         if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3372                         BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR,
3373                         sc->max_bus_addr, NULL, NULL,
3374                         BCE_RX_CHAIN_PAGE_SZ, 1, BCE_RX_CHAIN_PAGE_SZ,
3375                         0, NULL, NULL, &sc->rx_bd_chain_tag)) {
3376                 BCE_PRINTF("%s(%d): Could not allocate RX descriptor chain "
3377                     "DMA tag!\n", __FILE__, __LINE__);
3378                 rc = ENOMEM;
3379                 goto bce_dma_alloc_exit;
3380         }
3381
3382         for (i = 0; i < RX_PAGES; i++) {
3383
3384                 if (bus_dmamem_alloc(sc->rx_bd_chain_tag,
3385                     (void **)&sc->rx_bd_chain[i],
3386                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3387                     &sc->rx_bd_chain_map[i])) {
3388                         BCE_PRINTF("%s(%d): Could not allocate RX descriptor "
3389                             "chain DMA memory!\n", __FILE__, __LINE__);
3390                         rc = ENOMEM;
3391                         goto bce_dma_alloc_exit;
3392                 }
3393
3394                 error = bus_dmamap_load(sc->rx_bd_chain_tag,
3395                     sc->rx_bd_chain_map[i], sc->rx_bd_chain[i],
3396                     BCE_RX_CHAIN_PAGE_SZ, bce_dma_map_addr,
3397                     &sc->rx_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3398
3399                 if (error) {
3400                         BCE_PRINTF("%s(%d): Could not map RX descriptor "
3401                             "chain DMA memory!\n", __FILE__, __LINE__);
3402                         rc = ENOMEM;
3403                         goto bce_dma_alloc_exit;
3404                 }
3405
3406                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): rx_bd_chain_paddr[%d] = "
3407                     "0x%jX\n", __FUNCTION__, i,
3408                     (uintmax_t) sc->rx_bd_chain_paddr[i]);
3409         }
3410
3411         /*
3412          * Create a DMA tag for RX mbufs.
3413          */
3414 #ifdef BCE_JUMBO_HDRSPLIT
3415         max_size = max_seg_size = ((sc->rx_bd_mbuf_alloc_size < MCLBYTES) ?
3416                 MCLBYTES : sc->rx_bd_mbuf_alloc_size);
3417 #else
3418         max_size = max_seg_size = MJUM9BYTES;
3419 #endif
3420         max_segments = 1;
3421
3422         DBPRINT(sc, BCE_INFO_LOAD, "%s(): Creating rx_mbuf_tag "
3423             "(max size = 0x%jX max segments = %d, max segment "
3424             "size = 0x%jX)\n", __FUNCTION__, (uintmax_t) max_size,
3425              max_segments, (uintmax_t) max_seg_size);
3426
3427         if (bus_dma_tag_create(sc->parent_tag, 1,
3428             BCE_DMA_BOUNDARY, sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3429             max_size, max_segments, max_seg_size, 0, NULL, NULL,
3430             &sc->rx_mbuf_tag)) {
3431                 BCE_PRINTF("%s(%d): Could not allocate RX mbuf DMA tag!\n",
3432                     __FILE__, __LINE__);
3433                 rc = ENOMEM;
3434                 goto bce_dma_alloc_exit;
3435         }
3436
3437         /* Create DMA maps for the RX mbuf clusters. */
3438         for (i = 0; i < TOTAL_RX_BD; i++) {
3439                 if (bus_dmamap_create(sc->rx_mbuf_tag, BUS_DMA_NOWAIT,
3440                     &sc->rx_mbuf_map[i])) {
3441                         BCE_PRINTF("%s(%d): Unable to create RX mbuf "
3442                             "DMA map!\n", __FILE__, __LINE__);
3443                         rc = ENOMEM;
3444                         goto bce_dma_alloc_exit;
3445                 }
3446         }
3447
3448 #ifdef BCE_JUMBO_HDRSPLIT
3449         /*
3450          * Create a DMA tag for the page buffer descriptor chain,
3451          * allocate and clear the memory, and fetch the physical
3452          * address of the blocks.
3453          */
3454         if (bus_dma_tag_create(sc->parent_tag, BCM_PAGE_SIZE,
3455             BCE_DMA_BOUNDARY, BUS_SPACE_MAXADDR, sc->max_bus_addr,
3456             NULL, NULL, BCE_PG_CHAIN_PAGE_SZ, 1, BCE_PG_CHAIN_PAGE_SZ,
3457             0, NULL, NULL, &sc->pg_bd_chain_tag)) {
3458                 BCE_PRINTF("%s(%d): Could not allocate page descriptor "
3459                     "chain DMA tag!\n", __FILE__, __LINE__);
3460                 rc = ENOMEM;
3461                 goto bce_dma_alloc_exit;
3462         }
3463
3464         for (i = 0; i < PG_PAGES; i++) {
3465
3466                 if (bus_dmamem_alloc(sc->pg_bd_chain_tag,
3467                     (void **)&sc->pg_bd_chain[i],
3468                     BUS_DMA_NOWAIT | BUS_DMA_ZERO | BUS_DMA_COHERENT,
3469                     &sc->pg_bd_chain_map[i])) {
3470                         BCE_PRINTF("%s(%d): Could not allocate page "
3471                             "descriptor chain DMA memory!\n",
3472                             __FILE__, __LINE__);
3473                         rc = ENOMEM;
3474                         goto bce_dma_alloc_exit;
3475                 }
3476
3477                 error = bus_dmamap_load(sc->pg_bd_chain_tag,
3478                     sc->pg_bd_chain_map[i], sc->pg_bd_chain[i],
3479                     BCE_PG_CHAIN_PAGE_SZ, bce_dma_map_addr,
3480                     &sc->pg_bd_chain_paddr[i], BUS_DMA_NOWAIT);
3481
3482                 if (error) {
3483                         BCE_PRINTF("%s(%d): Could not map page descriptor "
3484                             "chain DMA memory!\n", __FILE__, __LINE__);
3485                         rc = ENOMEM;
3486                         goto bce_dma_alloc_exit;
3487                 }
3488
3489                 DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_chain_paddr[%d] = "
3490                     "0x%jX\n", __FUNCTION__, i,
3491                     (uintmax_t) sc->pg_bd_chain_paddr[i]);
3492         }
3493
3494         /*
3495          * Create a DMA tag for page mbufs.
3496          */
3497         max_size = max_seg_size = ((sc->pg_bd_mbuf_alloc_size < MCLBYTES) ?
3498             MCLBYTES : sc->pg_bd_mbuf_alloc_size);
3499
3500         if (bus_dma_tag_create(sc->parent_tag, 1, BCE_DMA_BOUNDARY,
3501             sc->max_bus_addr, BUS_SPACE_MAXADDR, NULL, NULL,
3502             max_size, 1, max_seg_size, 0, NULL, NULL, &sc->pg_mbuf_tag)) {
3503                 BCE_PRINTF("%s(%d): Could not allocate page mbuf "
3504                     "DMA tag!\n", __FILE__, __LINE__);
3505                 rc = ENOMEM;
3506                 goto bce_dma_alloc_exit;
3507         }
3508
3509         /* Create DMA maps for the page mbuf clusters. */
3510         for (i = 0; i < TOTAL_PG_BD; i++) {
3511                 if (bus_dmamap_create(sc->pg_mbuf_tag, BUS_DMA_NOWAIT,
3512                     &sc->pg_mbuf_map[i])) {
3513                         BCE_PRINTF("%s(%d): Unable to create page mbuf "
3514                             "DMA map!\n", __FILE__, __LINE__);
3515                         rc = ENOMEM;
3516                         goto bce_dma_alloc_exit;
3517                 }
3518         }
3519 #endif
3520
3521 bce_dma_alloc_exit:
3522         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
3523         return(rc);
3524 }
3525
3526
3527 /****************************************************************************/
3528 /* Release all resources used by the driver.                                */
3529 /*                                                                          */
3530 /* Releases all resources acquired by the driver including interrupts,      */
3531 /* interrupt handler, interfaces, mutexes, and DMA memory.                  */
3532 /*                                                                          */
3533 /* Returns:                                                                 */
3534 /*   Nothing.                                                               */
3535 /****************************************************************************/
3536 static void
3537 bce_release_resources(struct bce_softc *sc)
3538 {
3539         device_t dev;
3540
3541         DBENTER(BCE_VERBOSE_RESET);
3542
3543         dev = sc->bce_dev;
3544
3545         bce_dma_free(sc);
3546
3547         if (sc->bce_intrhand != NULL) {
3548                 DBPRINT(sc, BCE_INFO_RESET, "Removing interrupt handler.\n");
3549                 bus_teardown_intr(dev, sc->bce_res_irq, sc->bce_intrhand);
3550         }
3551
3552         if (sc->bce_res_irq != NULL) {
3553                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IRQ.\n");
3554                 bus_release_resource(dev, SYS_RES_IRQ, sc->bce_irq_rid,
3555                     sc->bce_res_irq);
3556         }
3557
3558         if (sc->bce_flags & (BCE_USING_MSI_FLAG | BCE_USING_MSIX_FLAG)) {
3559                 DBPRINT(sc, BCE_INFO_RESET, "Releasing MSI/MSI-X vector.\n");
3560                 pci_release_msi(dev);
3561         }
3562
3563         if (sc->bce_res_mem != NULL) {
3564                 DBPRINT(sc, BCE_INFO_RESET, "Releasing PCI memory.\n");
3565                     bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(0),
3566                     sc->bce_res_mem);
3567         }
3568
3569         if (sc->bce_ifp != NULL) {
3570                 DBPRINT(sc, BCE_INFO_RESET, "Releasing IF.\n");
3571                 if_free(sc->bce_ifp);
3572         }
3573
3574         if (mtx_initialized(&sc->bce_mtx))
3575                 BCE_LOCK_DESTROY(sc);
3576
3577         DBEXIT(BCE_VERBOSE_RESET);
3578 }
3579
3580
3581 /****************************************************************************/
3582 /* Firmware synchronization.                                                */
3583 /*                                                                          */
3584 /* Before performing certain events such as a chip reset, synchronize with  */
3585 /* the firmware first.                                                      */
3586 /*                                                                          */
3587 /* Returns:                                                                 */
3588 /*   0 for success, positive value for failure.                             */
3589 /****************************************************************************/
3590 static int
3591 bce_fw_sync(struct bce_softc *sc, u32 msg_data)
3592 {
3593         int i, rc = 0;
3594         u32 val;
3595
3596         DBENTER(BCE_VERBOSE_RESET);
3597
3598         /* Don't waste any time if we've timed out before. */
3599         if (sc->bce_fw_timed_out == TRUE) {
3600                 rc = EBUSY;
3601                 goto bce_fw_sync_exit;
3602         }
3603
3604         /* Increment the message sequence number. */
3605         sc->bce_fw_wr_seq++;
3606         msg_data |= sc->bce_fw_wr_seq;
3607
3608         DBPRINT(sc, BCE_VERBOSE_FIRMWARE, "bce_fw_sync(): msg_data = "
3609             "0x%08X\n", msg_data);
3610
3611         /* Send the message to the bootcode driver mailbox. */
3612         bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3613
3614         /* Wait for the bootcode to acknowledge the message. */
3615         for (i = 0; i < FW_ACK_TIME_OUT_MS; i++) {
3616                 /* Check for a response in the bootcode firmware mailbox. */
3617                 val = bce_shmem_rd(sc, BCE_FW_MB);
3618                 if ((val & BCE_FW_MSG_ACK) == (msg_data & BCE_DRV_MSG_SEQ))
3619                         break;
3620                 DELAY(1000);
3621         }
3622
3623         /* If we've timed out, tell bootcode that we've stopped waiting. */
3624         if (((val & BCE_FW_MSG_ACK) != (msg_data & BCE_DRV_MSG_SEQ)) &&
3625             ((msg_data & BCE_DRV_MSG_DATA) != BCE_DRV_MSG_DATA_WAIT0)) {
3626
3627                 BCE_PRINTF("%s(%d): Firmware synchronization timeout! "
3628                     "msg_data = 0x%08X\n", __FILE__, __LINE__, msg_data);
3629
3630                 msg_data &= ~BCE_DRV_MSG_CODE;
3631                 msg_data |= BCE_DRV_MSG_CODE_FW_TIMEOUT;
3632
3633                 bce_shmem_wr(sc, BCE_DRV_MB, msg_data);
3634
3635                 sc->bce_fw_timed_out = TRUE;
3636                 rc = EBUSY;
3637         }
3638
3639 bce_fw_sync_exit:
3640         DBEXIT(BCE_VERBOSE_RESET);
3641         return (rc);
3642 }
3643
3644
3645 /****************************************************************************/
3646 /* Load Receive Virtual 2 Physical (RV2P) processor firmware.               */
3647 /*                                                                          */
3648 /* Returns:                                                                 */
3649 /*   Nothing.                                                               */
3650 /****************************************************************************/
3651 static void
3652 bce_load_rv2p_fw(struct bce_softc *sc, u32 *rv2p_code,
3653         u32 rv2p_code_len, u32 rv2p_proc)
3654 {
3655         int i;
3656         u32 val;
3657
3658         DBENTER(BCE_VERBOSE_RESET);
3659
3660         /* Set the page size used by RV2P. */
3661         if (rv2p_proc == RV2P_PROC2) {
3662                 BCE_RV2P_PROC2_CHG_MAX_BD_PAGE(USABLE_RX_BD_PER_PAGE);
3663         }
3664
3665         for (i = 0; i < rv2p_code_len; i += 8) {
3666                 REG_WR(sc, BCE_RV2P_INSTR_HIGH, *rv2p_code);
3667                 rv2p_code++;
3668                 REG_WR(sc, BCE_RV2P_INSTR_LOW, *rv2p_code);
3669                 rv2p_code++;
3670
3671                 if (rv2p_proc == RV2P_PROC1) {
3672                         val = (i / 8) | BCE_RV2P_PROC1_ADDR_CMD_RDWR;
3673                         REG_WR(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
3674                 }
3675                 else {
3676                         val = (i / 8) | BCE_RV2P_PROC2_ADDR_CMD_RDWR;
3677                         REG_WR(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
3678                 }
3679         }
3680
3681         /* Reset the processor, un-stall is done later. */
3682         if (rv2p_proc == RV2P_PROC1) {
3683                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC1_RESET);
3684         }
3685         else {
3686                 REG_WR(sc, BCE_RV2P_COMMAND, BCE_RV2P_COMMAND_PROC2_RESET);
3687         }
3688
3689         DBEXIT(BCE_VERBOSE_RESET);
3690 }
3691
3692
3693 /****************************************************************************/
3694 /* Load RISC processor firmware.                                            */
3695 /*                                                                          */
3696 /* Loads firmware from the file if_bcefw.h into the scratchpad memory       */
3697 /* associated with a particular processor.                                  */
3698 /*                                                                          */
3699 /* Returns:                                                                 */
3700 /*   Nothing.                                                               */
3701 /****************************************************************************/
3702 static void
3703 bce_load_cpu_fw(struct bce_softc *sc, struct cpu_reg *cpu_reg,
3704         struct fw_info *fw)
3705 {
3706         u32 offset;
3707
3708         DBENTER(BCE_VERBOSE_RESET);
3709
3710     bce_halt_cpu(sc, cpu_reg);
3711
3712         /* Load the Text area. */
3713         offset = cpu_reg->spad_base + (fw->text_addr - cpu_reg->mips_view_base);
3714         if (fw->text) {
3715                 int j;
3716
3717                 for (j = 0; j < (fw->text_len / 4); j++, offset += 4) {
3718                         REG_WR_IND(sc, offset, fw->text[j]);
3719                 }
3720         }
3721
3722         /* Load the Data area. */
3723         offset = cpu_reg->spad_base + (fw->data_addr - cpu_reg->mips_view_base);
3724         if (fw->data) {
3725                 int j;
3726
3727                 for (j = 0; j < (fw->data_len / 4); j++, offset += 4) {
3728                         REG_WR_IND(sc, offset, fw->data[j]);
3729                 }
3730         }
3731
3732         /* Load the SBSS area. */
3733         offset = cpu_reg->spad_base + (fw->sbss_addr - cpu_reg->mips_view_base);
3734         if (fw->sbss) {
3735                 int j;
3736
3737                 for (j = 0; j < (fw->sbss_len / 4); j++, offset += 4) {
3738                         REG_WR_IND(sc, offset, fw->sbss[j]);
3739                 }
3740         }
3741
3742         /* Load the BSS area. */
3743         offset = cpu_reg->spad_base + (fw->bss_addr - cpu_reg->mips_view_base);
3744         if (fw->bss) {
3745                 int j;
3746
3747                 for (j = 0; j < (fw->bss_len/4); j++, offset += 4) {
3748                         REG_WR_IND(sc, offset, fw->bss[j]);
3749                 }
3750         }
3751
3752         /* Load the Read-Only area. */
3753         offset = cpu_reg->spad_base +
3754                 (fw->rodata_addr - cpu_reg->mips_view_base);
3755         if (fw->rodata) {
3756                 int j;
3757
3758                 for (j = 0; j < (fw->rodata_len / 4); j++, offset += 4) {
3759                         REG_WR_IND(sc, offset, fw->rodata[j]);
3760                 }
3761         }
3762
3763         /* Clear the pre-fetch instruction and set the FW start address. */
3764         REG_WR_IND(sc, cpu_reg->inst, 0);
3765         REG_WR_IND(sc, cpu_reg->pc, fw->start_addr);
3766
3767         DBEXIT(BCE_VERBOSE_RESET);
3768 }
3769
3770
3771 /****************************************************************************/
3772 /* Starts the RISC processor.                                               */
3773 /*                                                                          */
3774 /* Assumes the CPU starting address has already been set.                   */
3775 /*                                                                          */
3776 /* Returns:                                                                 */
3777 /*   Nothing.                                                               */
3778 /****************************************************************************/
3779 static void
3780 bce_start_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
3781 {
3782         u32 val;
3783
3784         DBENTER(BCE_VERBOSE_RESET);
3785
3786         /* Start the CPU. */
3787         val = REG_RD_IND(sc, cpu_reg->mode);
3788         val &= ~cpu_reg->mode_value_halt;
3789         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
3790         REG_WR_IND(sc, cpu_reg->mode, val);
3791
3792         DBEXIT(BCE_VERBOSE_RESET);
3793 }
3794
3795
3796 /****************************************************************************/
3797 /* Halts the RISC processor.                                                */
3798 /*                                                                          */
3799 /* Returns:                                                                 */
3800 /*   Nothing.                                                               */
3801 /****************************************************************************/
3802 static void
3803 bce_halt_cpu(struct bce_softc *sc, struct cpu_reg *cpu_reg)
3804 {
3805         u32 val;
3806
3807         DBENTER(BCE_VERBOSE_RESET);
3808
3809         /* Halt the CPU. */
3810         val = REG_RD_IND(sc, cpu_reg->mode);
3811         val |= cpu_reg->mode_value_halt;
3812         REG_WR_IND(sc, cpu_reg->mode, val);
3813         REG_WR_IND(sc, cpu_reg->state, cpu_reg->state_value_clear);
3814
3815         DBEXIT(BCE_VERBOSE_RESET);
3816 }
3817
3818
3819 /****************************************************************************/
3820 /* Initialize the RX CPU.                                                   */
3821 /*                                                                          */
3822 /* Returns:                                                                 */
3823 /*   Nothing.                                                               */
3824 /****************************************************************************/
3825 static void
3826 bce_start_rxp_cpu(struct bce_softc *sc)
3827 {
3828         struct cpu_reg cpu_reg;
3829
3830         DBENTER(BCE_VERBOSE_RESET);
3831
3832         cpu_reg.mode = BCE_RXP_CPU_MODE;
3833         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
3834         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
3835         cpu_reg.state = BCE_RXP_CPU_STATE;
3836         cpu_reg.state_value_clear = 0xffffff;
3837         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
3838         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
3839         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
3840         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
3841         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
3842         cpu_reg.spad_base = BCE_RXP_SCRATCH;
3843         cpu_reg.mips_view_base = 0x8000000;
3844
3845         DBPRINT(sc, BCE_INFO_RESET, "Starting RX firmware.\n");
3846         bce_start_cpu(sc, &cpu_reg);
3847
3848         DBEXIT(BCE_VERBOSE_RESET);
3849 }
3850
3851
3852 /****************************************************************************/
3853 /* Initialize the RX CPU.                                                   */
3854 /*                                                                          */
3855 /* Returns:                                                                 */
3856 /*   Nothing.                                                               */
3857 /****************************************************************************/
3858 static void
3859 bce_init_rxp_cpu(struct bce_softc *sc)
3860 {
3861         struct cpu_reg cpu_reg;
3862         struct fw_info fw;
3863
3864         DBENTER(BCE_VERBOSE_RESET);
3865
3866         cpu_reg.mode = BCE_RXP_CPU_MODE;
3867         cpu_reg.mode_value_halt = BCE_RXP_CPU_MODE_SOFT_HALT;
3868         cpu_reg.mode_value_sstep = BCE_RXP_CPU_MODE_STEP_ENA;
3869         cpu_reg.state = BCE_RXP_CPU_STATE;
3870         cpu_reg.state_value_clear = 0xffffff;
3871         cpu_reg.gpr0 = BCE_RXP_CPU_REG_FILE;
3872         cpu_reg.evmask = BCE_RXP_CPU_EVENT_MASK;
3873         cpu_reg.pc = BCE_RXP_CPU_PROGRAM_COUNTER;
3874         cpu_reg.inst = BCE_RXP_CPU_INSTRUCTION;
3875         cpu_reg.bp = BCE_RXP_CPU_HW_BREAKPOINT;
3876         cpu_reg.spad_base = BCE_RXP_SCRATCH;
3877         cpu_reg.mips_view_base = 0x8000000;
3878
3879         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
3880                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
3881                 fw.ver_major = bce_RXP_b09FwReleaseMajor;
3882                 fw.ver_minor = bce_RXP_b09FwReleaseMinor;
3883                 fw.ver_fix = bce_RXP_b09FwReleaseFix;
3884                 fw.start_addr = bce_RXP_b09FwStartAddr;
3885
3886                 fw.text_addr = bce_RXP_b09FwTextAddr;
3887                 fw.text_len = bce_RXP_b09FwTextLen;
3888                 fw.text_index = 0;
3889                 fw.text = bce_RXP_b09FwText;
3890
3891                 fw.data_addr = bce_RXP_b09FwDataAddr;
3892                 fw.data_len = bce_RXP_b09FwDataLen;
3893                 fw.data_index = 0;
3894                 fw.data = bce_RXP_b09FwData;
3895
3896                 fw.sbss_addr = bce_RXP_b09FwSbssAddr;
3897                 fw.sbss_len = bce_RXP_b09FwSbssLen;
3898                 fw.sbss_index = 0;
3899                 fw.sbss = bce_RXP_b09FwSbss;
3900
3901                 fw.bss_addr = bce_RXP_b09FwBssAddr;
3902                 fw.bss_len = bce_RXP_b09FwBssLen;
3903                 fw.bss_index = 0;
3904                 fw.bss = bce_RXP_b09FwBss;
3905
3906                 fw.rodata_addr = bce_RXP_b09FwRodataAddr;
3907                 fw.rodata_len = bce_RXP_b09FwRodataLen;
3908                 fw.rodata_index = 0;
3909                 fw.rodata = bce_RXP_b09FwRodata;
3910         } else {
3911                 fw.ver_major = bce_RXP_b06FwReleaseMajor;
3912                 fw.ver_minor = bce_RXP_b06FwReleaseMinor;
3913                 fw.ver_fix = bce_RXP_b06FwReleaseFix;
3914                 fw.start_addr = bce_RXP_b06FwStartAddr;
3915
3916                 fw.text_addr = bce_RXP_b06FwTextAddr;
3917                 fw.text_len = bce_RXP_b06FwTextLen;
3918                 fw.text_index = 0;
3919                 fw.text = bce_RXP_b06FwText;
3920
3921                 fw.data_addr = bce_RXP_b06FwDataAddr;
3922                 fw.data_len = bce_RXP_b06FwDataLen;
3923                 fw.data_index = 0;
3924                 fw.data = bce_RXP_b06FwData;
3925
3926                 fw.sbss_addr = bce_RXP_b06FwSbssAddr;
3927                 fw.sbss_len = bce_RXP_b06FwSbssLen;
3928                 fw.sbss_index = 0;
3929                 fw.sbss = bce_RXP_b06FwSbss;
3930
3931                 fw.bss_addr = bce_RXP_b06FwBssAddr;
3932                 fw.bss_len = bce_RXP_b06FwBssLen;
3933                 fw.bss_index = 0;
3934                 fw.bss = bce_RXP_b06FwBss;
3935
3936                 fw.rodata_addr = bce_RXP_b06FwRodataAddr;
3937                 fw.rodata_len = bce_RXP_b06FwRodataLen;
3938                 fw.rodata_index = 0;
3939                 fw.rodata = bce_RXP_b06FwRodata;
3940         }
3941
3942         DBPRINT(sc, BCE_INFO_RESET, "Loading RX firmware.\n");
3943         bce_load_cpu_fw(sc, &cpu_reg, &fw);
3944
3945     /* Delay RXP start until initialization is complete. */
3946
3947         DBEXIT(BCE_VERBOSE_RESET);
3948 }
3949
3950
3951 /****************************************************************************/
3952 /* Initialize the TX CPU.                                                   */
3953 /*                                                                          */
3954 /* Returns:                                                                 */
3955 /*   Nothing.                                                               */
3956 /****************************************************************************/
3957 static void
3958 bce_init_txp_cpu(struct bce_softc *sc)
3959 {
3960         struct cpu_reg cpu_reg;
3961         struct fw_info fw;
3962
3963         DBENTER(BCE_VERBOSE_RESET);
3964
3965         cpu_reg.mode = BCE_TXP_CPU_MODE;
3966         cpu_reg.mode_value_halt = BCE_TXP_CPU_MODE_SOFT_HALT;
3967         cpu_reg.mode_value_sstep = BCE_TXP_CPU_MODE_STEP_ENA;
3968         cpu_reg.state = BCE_TXP_CPU_STATE;
3969         cpu_reg.state_value_clear = 0xffffff;
3970         cpu_reg.gpr0 = BCE_TXP_CPU_REG_FILE;
3971         cpu_reg.evmask = BCE_TXP_CPU_EVENT_MASK;
3972         cpu_reg.pc = BCE_TXP_CPU_PROGRAM_COUNTER;
3973         cpu_reg.inst = BCE_TXP_CPU_INSTRUCTION;
3974         cpu_reg.bp = BCE_TXP_CPU_HW_BREAKPOINT;
3975         cpu_reg.spad_base = BCE_TXP_SCRATCH;
3976         cpu_reg.mips_view_base = 0x8000000;
3977
3978         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
3979                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
3980                 fw.ver_major = bce_TXP_b09FwReleaseMajor;
3981                 fw.ver_minor = bce_TXP_b09FwReleaseMinor;
3982                 fw.ver_fix = bce_TXP_b09FwReleaseFix;
3983                 fw.start_addr = bce_TXP_b09FwStartAddr;
3984
3985                 fw.text_addr = bce_TXP_b09FwTextAddr;
3986                 fw.text_len = bce_TXP_b09FwTextLen;
3987                 fw.text_index = 0;
3988                 fw.text = bce_TXP_b09FwText;
3989
3990                 fw.data_addr = bce_TXP_b09FwDataAddr;
3991                 fw.data_len = bce_TXP_b09FwDataLen;
3992                 fw.data_index = 0;
3993                 fw.data = bce_TXP_b09FwData;
3994
3995                 fw.sbss_addr = bce_TXP_b09FwSbssAddr;
3996                 fw.sbss_len = bce_TXP_b09FwSbssLen;
3997                 fw.sbss_index = 0;
3998                 fw.sbss = bce_TXP_b09FwSbss;
3999
4000                 fw.bss_addr = bce_TXP_b09FwBssAddr;
4001                 fw.bss_len = bce_TXP_b09FwBssLen;
4002                 fw.bss_index = 0;
4003                 fw.bss = bce_TXP_b09FwBss;
4004
4005                 fw.rodata_addr = bce_TXP_b09FwRodataAddr;
4006                 fw.rodata_len = bce_TXP_b09FwRodataLen;
4007                 fw.rodata_index = 0;
4008                 fw.rodata = bce_TXP_b09FwRodata;
4009         } else {
4010                 fw.ver_major = bce_TXP_b06FwReleaseMajor;
4011                 fw.ver_minor = bce_TXP_b06FwReleaseMinor;
4012                 fw.ver_fix = bce_TXP_b06FwReleaseFix;
4013                 fw.start_addr = bce_TXP_b06FwStartAddr;
4014
4015                 fw.text_addr = bce_TXP_b06FwTextAddr;
4016                 fw.text_len = bce_TXP_b06FwTextLen;
4017                 fw.text_index = 0;
4018                 fw.text = bce_TXP_b06FwText;
4019
4020                 fw.data_addr = bce_TXP_b06FwDataAddr;
4021                 fw.data_len = bce_TXP_b06FwDataLen;
4022                 fw.data_index = 0;
4023                 fw.data = bce_TXP_b06FwData;
4024
4025                 fw.sbss_addr = bce_TXP_b06FwSbssAddr;
4026                 fw.sbss_len = bce_TXP_b06FwSbssLen;
4027                 fw.sbss_index = 0;
4028                 fw.sbss = bce_TXP_b06FwSbss;
4029
4030                 fw.bss_addr = bce_TXP_b06FwBssAddr;
4031                 fw.bss_len = bce_TXP_b06FwBssLen;
4032                 fw.bss_index = 0;
4033                 fw.bss = bce_TXP_b06FwBss;
4034
4035                 fw.rodata_addr = bce_TXP_b06FwRodataAddr;
4036                 fw.rodata_len = bce_TXP_b06FwRodataLen;
4037                 fw.rodata_index = 0;
4038                 fw.rodata = bce_TXP_b06FwRodata;
4039         }
4040
4041         DBPRINT(sc, BCE_INFO_RESET, "Loading TX firmware.\n");
4042         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4043     bce_start_cpu(sc, &cpu_reg);
4044
4045         DBEXIT(BCE_VERBOSE_RESET);
4046 }
4047
4048
4049 /****************************************************************************/
4050 /* Initialize the TPAT CPU.                                                 */
4051 /*                                                                          */
4052 /* Returns:                                                                 */
4053 /*   Nothing.                                                               */
4054 /****************************************************************************/
4055 static void
4056 bce_init_tpat_cpu(struct bce_softc *sc)
4057 {
4058         struct cpu_reg cpu_reg;
4059         struct fw_info fw;
4060
4061         DBENTER(BCE_VERBOSE_RESET);
4062
4063         cpu_reg.mode = BCE_TPAT_CPU_MODE;
4064         cpu_reg.mode_value_halt = BCE_TPAT_CPU_MODE_SOFT_HALT;
4065         cpu_reg.mode_value_sstep = BCE_TPAT_CPU_MODE_STEP_ENA;
4066         cpu_reg.state = BCE_TPAT_CPU_STATE;
4067         cpu_reg.state_value_clear = 0xffffff;
4068         cpu_reg.gpr0 = BCE_TPAT_CPU_REG_FILE;
4069         cpu_reg.evmask = BCE_TPAT_CPU_EVENT_MASK;
4070         cpu_reg.pc = BCE_TPAT_CPU_PROGRAM_COUNTER;
4071         cpu_reg.inst = BCE_TPAT_CPU_INSTRUCTION;
4072         cpu_reg.bp = BCE_TPAT_CPU_HW_BREAKPOINT;
4073         cpu_reg.spad_base = BCE_TPAT_SCRATCH;
4074         cpu_reg.mips_view_base = 0x8000000;
4075
4076         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4077                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4078                 fw.ver_major = bce_TPAT_b09FwReleaseMajor;
4079                 fw.ver_minor = bce_TPAT_b09FwReleaseMinor;
4080                 fw.ver_fix = bce_TPAT_b09FwReleaseFix;
4081                 fw.start_addr = bce_TPAT_b09FwStartAddr;
4082
4083                 fw.text_addr = bce_TPAT_b09FwTextAddr;
4084                 fw.text_len = bce_TPAT_b09FwTextLen;
4085                 fw.text_index = 0;
4086                 fw.text = bce_TPAT_b09FwText;
4087
4088                 fw.data_addr = bce_TPAT_b09FwDataAddr;
4089                 fw.data_len = bce_TPAT_b09FwDataLen;
4090                 fw.data_index = 0;
4091                 fw.data = bce_TPAT_b09FwData;
4092
4093                 fw.sbss_addr = bce_TPAT_b09FwSbssAddr;
4094                 fw.sbss_len = bce_TPAT_b09FwSbssLen;
4095                 fw.sbss_index = 0;
4096                 fw.sbss = bce_TPAT_b09FwSbss;
4097
4098                 fw.bss_addr = bce_TPAT_b09FwBssAddr;
4099                 fw.bss_len = bce_TPAT_b09FwBssLen;
4100                 fw.bss_index = 0;
4101                 fw.bss = bce_TPAT_b09FwBss;
4102
4103                 fw.rodata_addr = bce_TPAT_b09FwRodataAddr;
4104                 fw.rodata_len = bce_TPAT_b09FwRodataLen;
4105                 fw.rodata_index = 0;
4106                 fw.rodata = bce_TPAT_b09FwRodata;
4107         } else {
4108                 fw.ver_major = bce_TPAT_b06FwReleaseMajor;
4109                 fw.ver_minor = bce_TPAT_b06FwReleaseMinor;
4110                 fw.ver_fix = bce_TPAT_b06FwReleaseFix;
4111                 fw.start_addr = bce_TPAT_b06FwStartAddr;
4112
4113                 fw.text_addr = bce_TPAT_b06FwTextAddr;
4114                 fw.text_len = bce_TPAT_b06FwTextLen;
4115                 fw.text_index = 0;
4116                 fw.text = bce_TPAT_b06FwText;
4117
4118                 fw.data_addr = bce_TPAT_b06FwDataAddr;
4119                 fw.data_len = bce_TPAT_b06FwDataLen;
4120                 fw.data_index = 0;
4121                 fw.data = bce_TPAT_b06FwData;
4122
4123                 fw.sbss_addr = bce_TPAT_b06FwSbssAddr;
4124                 fw.sbss_len = bce_TPAT_b06FwSbssLen;
4125                 fw.sbss_index = 0;
4126                 fw.sbss = bce_TPAT_b06FwSbss;
4127
4128                 fw.bss_addr = bce_TPAT_b06FwBssAddr;
4129                 fw.bss_len = bce_TPAT_b06FwBssLen;
4130                 fw.bss_index = 0;
4131                 fw.bss = bce_TPAT_b06FwBss;
4132
4133                 fw.rodata_addr = bce_TPAT_b06FwRodataAddr;
4134                 fw.rodata_len = bce_TPAT_b06FwRodataLen;
4135                 fw.rodata_index = 0;
4136                 fw.rodata = bce_TPAT_b06FwRodata;
4137         }
4138
4139         DBPRINT(sc, BCE_INFO_RESET, "Loading TPAT firmware.\n");
4140         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4141         bce_start_cpu(sc, &cpu_reg);
4142
4143         DBEXIT(BCE_VERBOSE_RESET);
4144 }
4145
4146
4147 /****************************************************************************/
4148 /* Initialize the CP CPU.                                                   */
4149 /*                                                                          */
4150 /* Returns:                                                                 */
4151 /*   Nothing.                                                               */
4152 /****************************************************************************/
4153 static void
4154 bce_init_cp_cpu(struct bce_softc *sc)
4155 {
4156         struct cpu_reg cpu_reg;
4157         struct fw_info fw;
4158
4159         DBENTER(BCE_VERBOSE_RESET);
4160
4161         cpu_reg.mode = BCE_CP_CPU_MODE;
4162         cpu_reg.mode_value_halt = BCE_CP_CPU_MODE_SOFT_HALT;
4163         cpu_reg.mode_value_sstep = BCE_CP_CPU_MODE_STEP_ENA;
4164         cpu_reg.state = BCE_CP_CPU_STATE;
4165         cpu_reg.state_value_clear = 0xffffff;
4166         cpu_reg.gpr0 = BCE_CP_CPU_REG_FILE;
4167         cpu_reg.evmask = BCE_CP_CPU_EVENT_MASK;
4168         cpu_reg.pc = BCE_CP_CPU_PROGRAM_COUNTER;
4169         cpu_reg.inst = BCE_CP_CPU_INSTRUCTION;
4170         cpu_reg.bp = BCE_CP_CPU_HW_BREAKPOINT;
4171         cpu_reg.spad_base = BCE_CP_SCRATCH;
4172         cpu_reg.mips_view_base = 0x8000000;
4173
4174         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4175                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4176                 fw.ver_major = bce_CP_b09FwReleaseMajor;
4177                 fw.ver_minor = bce_CP_b09FwReleaseMinor;
4178                 fw.ver_fix = bce_CP_b09FwReleaseFix;
4179                 fw.start_addr = bce_CP_b09FwStartAddr;
4180
4181                 fw.text_addr = bce_CP_b09FwTextAddr;
4182                 fw.text_len = bce_CP_b09FwTextLen;
4183                 fw.text_index = 0;
4184                 fw.text = bce_CP_b09FwText;
4185
4186                 fw.data_addr = bce_CP_b09FwDataAddr;
4187                 fw.data_len = bce_CP_b09FwDataLen;
4188                 fw.data_index = 0;
4189                 fw.data = bce_CP_b09FwData;
4190
4191                 fw.sbss_addr = bce_CP_b09FwSbssAddr;
4192                 fw.sbss_len = bce_CP_b09FwSbssLen;
4193                 fw.sbss_index = 0;
4194                 fw.sbss = bce_CP_b09FwSbss;
4195
4196                 fw.bss_addr = bce_CP_b09FwBssAddr;
4197                 fw.bss_len = bce_CP_b09FwBssLen;
4198                 fw.bss_index = 0;
4199                 fw.bss = bce_CP_b09FwBss;
4200
4201                 fw.rodata_addr = bce_CP_b09FwRodataAddr;
4202                 fw.rodata_len = bce_CP_b09FwRodataLen;
4203                 fw.rodata_index = 0;
4204                 fw.rodata = bce_CP_b09FwRodata;
4205         } else {
4206                 fw.ver_major = bce_CP_b06FwReleaseMajor;
4207                 fw.ver_minor = bce_CP_b06FwReleaseMinor;
4208                 fw.ver_fix = bce_CP_b06FwReleaseFix;
4209                 fw.start_addr = bce_CP_b06FwStartAddr;
4210
4211                 fw.text_addr = bce_CP_b06FwTextAddr;
4212                 fw.text_len = bce_CP_b06FwTextLen;
4213                 fw.text_index = 0;
4214                 fw.text = bce_CP_b06FwText;
4215
4216                 fw.data_addr = bce_CP_b06FwDataAddr;
4217                 fw.data_len = bce_CP_b06FwDataLen;
4218                 fw.data_index = 0;
4219                 fw.data = bce_CP_b06FwData;
4220
4221                 fw.sbss_addr = bce_CP_b06FwSbssAddr;
4222                 fw.sbss_len = bce_CP_b06FwSbssLen;
4223                 fw.sbss_index = 0;
4224                 fw.sbss = bce_CP_b06FwSbss;
4225
4226                 fw.bss_addr = bce_CP_b06FwBssAddr;
4227                 fw.bss_len = bce_CP_b06FwBssLen;
4228                 fw.bss_index = 0;
4229                 fw.bss = bce_CP_b06FwBss;
4230
4231                 fw.rodata_addr = bce_CP_b06FwRodataAddr;
4232                 fw.rodata_len = bce_CP_b06FwRodataLen;
4233                 fw.rodata_index = 0;
4234                 fw.rodata = bce_CP_b06FwRodata;
4235         }
4236
4237         DBPRINT(sc, BCE_INFO_RESET, "Loading CP firmware.\n");
4238         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4239         bce_start_cpu(sc, &cpu_reg);
4240
4241         DBEXIT(BCE_VERBOSE_RESET);
4242 }
4243
4244
4245 /****************************************************************************/
4246 /* Initialize the COM CPU.                                                 */
4247 /*                                                                          */
4248 /* Returns:                                                                 */
4249 /*   Nothing.                                                               */
4250 /****************************************************************************/
4251 static void
4252 bce_init_com_cpu(struct bce_softc *sc)
4253 {
4254         struct cpu_reg cpu_reg;
4255         struct fw_info fw;
4256
4257         DBENTER(BCE_VERBOSE_RESET);
4258
4259         cpu_reg.mode = BCE_COM_CPU_MODE;
4260         cpu_reg.mode_value_halt = BCE_COM_CPU_MODE_SOFT_HALT;
4261         cpu_reg.mode_value_sstep = BCE_COM_CPU_MODE_STEP_ENA;
4262         cpu_reg.state = BCE_COM_CPU_STATE;
4263         cpu_reg.state_value_clear = 0xffffff;
4264         cpu_reg.gpr0 = BCE_COM_CPU_REG_FILE;
4265         cpu_reg.evmask = BCE_COM_CPU_EVENT_MASK;
4266         cpu_reg.pc = BCE_COM_CPU_PROGRAM_COUNTER;
4267         cpu_reg.inst = BCE_COM_CPU_INSTRUCTION;
4268         cpu_reg.bp = BCE_COM_CPU_HW_BREAKPOINT;
4269         cpu_reg.spad_base = BCE_COM_SCRATCH;
4270         cpu_reg.mips_view_base = 0x8000000;
4271
4272         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4273                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4274                 fw.ver_major = bce_COM_b09FwReleaseMajor;
4275                 fw.ver_minor = bce_COM_b09FwReleaseMinor;
4276                 fw.ver_fix = bce_COM_b09FwReleaseFix;
4277                 fw.start_addr = bce_COM_b09FwStartAddr;
4278
4279                 fw.text_addr = bce_COM_b09FwTextAddr;
4280                 fw.text_len = bce_COM_b09FwTextLen;
4281                 fw.text_index = 0;
4282                 fw.text = bce_COM_b09FwText;
4283
4284                 fw.data_addr = bce_COM_b09FwDataAddr;
4285                 fw.data_len = bce_COM_b09FwDataLen;
4286                 fw.data_index = 0;
4287                 fw.data = bce_COM_b09FwData;
4288
4289                 fw.sbss_addr = bce_COM_b09FwSbssAddr;
4290                 fw.sbss_len = bce_COM_b09FwSbssLen;
4291                 fw.sbss_index = 0;
4292                 fw.sbss = bce_COM_b09FwSbss;
4293
4294                 fw.bss_addr = bce_COM_b09FwBssAddr;
4295                 fw.bss_len = bce_COM_b09FwBssLen;
4296                 fw.bss_index = 0;
4297                 fw.bss = bce_COM_b09FwBss;
4298
4299                 fw.rodata_addr = bce_COM_b09FwRodataAddr;
4300                 fw.rodata_len = bce_COM_b09FwRodataLen;
4301                 fw.rodata_index = 0;
4302                 fw.rodata = bce_COM_b09FwRodata;
4303         } else {
4304                 fw.ver_major = bce_COM_b06FwReleaseMajor;
4305                 fw.ver_minor = bce_COM_b06FwReleaseMinor;
4306                 fw.ver_fix = bce_COM_b06FwReleaseFix;
4307                 fw.start_addr = bce_COM_b06FwStartAddr;
4308
4309                 fw.text_addr = bce_COM_b06FwTextAddr;
4310                 fw.text_len = bce_COM_b06FwTextLen;
4311                 fw.text_index = 0;
4312                 fw.text = bce_COM_b06FwText;
4313
4314                 fw.data_addr = bce_COM_b06FwDataAddr;
4315                 fw.data_len = bce_COM_b06FwDataLen;
4316                 fw.data_index = 0;
4317                 fw.data = bce_COM_b06FwData;
4318
4319                 fw.sbss_addr = bce_COM_b06FwSbssAddr;
4320                 fw.sbss_len = bce_COM_b06FwSbssLen;
4321                 fw.sbss_index = 0;
4322                 fw.sbss = bce_COM_b06FwSbss;
4323
4324                 fw.bss_addr = bce_COM_b06FwBssAddr;
4325                 fw.bss_len = bce_COM_b06FwBssLen;
4326                 fw.bss_index = 0;
4327                 fw.bss = bce_COM_b06FwBss;
4328
4329                 fw.rodata_addr = bce_COM_b06FwRodataAddr;
4330                 fw.rodata_len = bce_COM_b06FwRodataLen;
4331                 fw.rodata_index = 0;
4332                 fw.rodata = bce_COM_b06FwRodata;
4333         }
4334
4335         DBPRINT(sc, BCE_INFO_RESET, "Loading COM firmware.\n");
4336         bce_load_cpu_fw(sc, &cpu_reg, &fw);
4337         bce_start_cpu(sc, &cpu_reg);
4338
4339         DBEXIT(BCE_VERBOSE_RESET);
4340 }
4341
4342
4343 /****************************************************************************/
4344 /* Initialize the RV2P, RX, TX, TPAT, COM, and CP CPUs.                     */
4345 /*                                                                          */
4346 /* Loads the firmware for each CPU and starts the CPU.                      */
4347 /*                                                                          */
4348 /* Returns:                                                                 */
4349 /*   Nothing.                                                               */
4350 /****************************************************************************/
4351 static void
4352 bce_init_cpus(struct bce_softc *sc)
4353 {
4354         DBENTER(BCE_VERBOSE_RESET);
4355
4356         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4357                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4358
4359                 if ((BCE_CHIP_REV(sc) == BCE_CHIP_REV_Ax)) {
4360                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc1,
4361                             sizeof(bce_xi90_rv2p_proc1), RV2P_PROC1);
4362                         bce_load_rv2p_fw(sc, bce_xi90_rv2p_proc2,
4363                             sizeof(bce_xi90_rv2p_proc2), RV2P_PROC2);
4364                 } else {
4365                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc1,
4366                             sizeof(bce_xi_rv2p_proc1), RV2P_PROC1);
4367                         bce_load_rv2p_fw(sc, bce_xi_rv2p_proc2,
4368                             sizeof(bce_xi_rv2p_proc2), RV2P_PROC2);
4369                 }
4370
4371         } else {
4372                 bce_load_rv2p_fw(sc, bce_rv2p_proc1,
4373                     sizeof(bce_rv2p_proc1), RV2P_PROC1);
4374                 bce_load_rv2p_fw(sc, bce_rv2p_proc2,
4375                     sizeof(bce_rv2p_proc2), RV2P_PROC2);
4376         }
4377
4378         bce_init_rxp_cpu(sc);
4379         bce_init_txp_cpu(sc);
4380         bce_init_tpat_cpu(sc);
4381         bce_init_com_cpu(sc);
4382         bce_init_cp_cpu(sc);
4383
4384         DBEXIT(BCE_VERBOSE_RESET);
4385 }
4386
4387
4388 /****************************************************************************/
4389 /* Initialize context memory.                                               */
4390 /*                                                                          */
4391 /* Clears the memory associated with each Context ID (CID).                 */
4392 /*                                                                          */
4393 /* Returns:                                                                 */
4394 /*   Nothing.                                                               */
4395 /****************************************************************************/
4396 static int
4397 bce_init_ctx(struct bce_softc *sc)
4398 {
4399         u32 offset, val, vcid_addr;
4400         int i, j, rc, retry_cnt;
4401
4402         rc = 0;
4403         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4404
4405         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4406             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4407                 retry_cnt = CTX_INIT_RETRY_COUNT;
4408
4409                 DBPRINT(sc, BCE_INFO_CTX, "Initializing 5709 context.\n");
4410
4411                 /*
4412                  * BCM5709 context memory may be cached
4413                  * in host memory so prepare the host memory
4414                  * for access.
4415                  */
4416                 val = BCE_CTX_COMMAND_ENABLED |
4417                     BCE_CTX_COMMAND_MEM_INIT | (1 << 12);
4418                 val |= (BCM_PAGE_BITS - 8) << 16;
4419                 REG_WR(sc, BCE_CTX_COMMAND, val);
4420
4421                 /* Wait for mem init command to complete. */
4422                 for (i = 0; i < retry_cnt; i++) {
4423                         val = REG_RD(sc, BCE_CTX_COMMAND);
4424                         if (!(val & BCE_CTX_COMMAND_MEM_INIT))
4425                                 break;
4426                         DELAY(2);
4427                 }
4428                 if ((val & BCE_CTX_COMMAND_MEM_INIT) != 0) {
4429                         BCE_PRINTF("%s(): Context memory initialization failed!\n",
4430                             __FUNCTION__);
4431                         rc = EBUSY;
4432                         goto init_ctx_fail;
4433                 }
4434
4435                 for (i = 0; i < sc->ctx_pages; i++) {
4436                         /* Set the physical address of the context memory. */
4437                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA0,
4438                             BCE_ADDR_LO(sc->ctx_paddr[i] & 0xfffffff0) |
4439                             BCE_CTX_HOST_PAGE_TBL_DATA0_VALID);
4440                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_DATA1,
4441                             BCE_ADDR_HI(sc->ctx_paddr[i]));
4442                         REG_WR(sc, BCE_CTX_HOST_PAGE_TBL_CTRL, i |
4443                             BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
4444
4445                         /* Verify the context memory write was successful. */
4446                         for (j = 0; j < retry_cnt; j++) {
4447                                 val = REG_RD(sc, BCE_CTX_HOST_PAGE_TBL_CTRL);
4448                                 if ((val &
4449                                     BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) == 0)
4450                                         break;
4451                                 DELAY(5);
4452                         }
4453                         if ((val & BCE_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) != 0) {
4454                                 BCE_PRINTF("%s(): Failed to initialize "
4455                                     "context page %d!\n", __FUNCTION__, i);
4456                                 rc = EBUSY;
4457                                 goto init_ctx_fail;
4458                         }
4459                 }
4460         } else {
4461
4462                 DBPRINT(sc, BCE_INFO, "Initializing 5706/5708 context.\n");
4463
4464                 /*
4465                  * For the 5706/5708, context memory is local to
4466                  * the controller, so initialize the controller
4467                  * context memory.
4468                  */
4469
4470                 vcid_addr = GET_CID_ADDR(96);
4471                 while (vcid_addr) {
4472
4473                         vcid_addr -= PHY_CTX_SIZE;
4474
4475                         REG_WR(sc, BCE_CTX_VIRT_ADDR, 0);
4476                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4477
4478                         for(offset = 0; offset < PHY_CTX_SIZE; offset += 4) {
4479                                 CTX_WR(sc, 0x00, offset, 0);
4480                         }
4481
4482                         REG_WR(sc, BCE_CTX_VIRT_ADDR, vcid_addr);
4483                         REG_WR(sc, BCE_CTX_PAGE_TBL, vcid_addr);
4484                 }
4485
4486         }
4487 init_ctx_fail:
4488         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_CTX);
4489         return (rc);
4490 }
4491
4492
4493 /****************************************************************************/
4494 /* Fetch the permanent MAC address of the controller.                       */
4495 /*                                                                          */
4496 /* Returns:                                                                 */
4497 /*   Nothing.                                                               */
4498 /****************************************************************************/
4499 static void
4500 bce_get_mac_addr(struct bce_softc *sc)
4501 {
4502         u32 mac_lo = 0, mac_hi = 0;
4503
4504         DBENTER(BCE_VERBOSE_RESET);
4505
4506         /*
4507          * The NetXtreme II bootcode populates various NIC
4508          * power-on and runtime configuration items in a
4509          * shared memory area.  The factory configured MAC
4510          * address is available from both NVRAM and the
4511          * shared memory area so we'll read the value from
4512          * shared memory for speed.
4513          */
4514
4515         mac_hi = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_UPPER);
4516         mac_lo = bce_shmem_rd(sc, BCE_PORT_HW_CFG_MAC_LOWER);
4517
4518         if ((mac_lo == 0) && (mac_hi == 0)) {
4519                 BCE_PRINTF("%s(%d): Invalid Ethernet address!\n",
4520                     __FILE__, __LINE__);
4521         } else {
4522                 sc->eaddr[0] = (u_char)(mac_hi >> 8);
4523                 sc->eaddr[1] = (u_char)(mac_hi >> 0);
4524                 sc->eaddr[2] = (u_char)(mac_lo >> 24);
4525                 sc->eaddr[3] = (u_char)(mac_lo >> 16);
4526                 sc->eaddr[4] = (u_char)(mac_lo >> 8);
4527                 sc->eaddr[5] = (u_char)(mac_lo >> 0);
4528         }
4529
4530         DBPRINT(sc, BCE_INFO_MISC, "Permanent Ethernet "
4531             "address = %6D\n", sc->eaddr, ":");
4532         DBEXIT(BCE_VERBOSE_RESET);
4533 }
4534
4535
4536 /****************************************************************************/
4537 /* Program the MAC address.                                                 */
4538 /*                                                                          */
4539 /* Returns:                                                                 */
4540 /*   Nothing.                                                               */
4541 /****************************************************************************/
4542 static void
4543 bce_set_mac_addr(struct bce_softc *sc)
4544 {
4545         u32 val;
4546         u8 *mac_addr = sc->eaddr;
4547
4548         /* ToDo: Add support for setting multiple MAC addresses. */
4549
4550         DBENTER(BCE_VERBOSE_RESET);
4551         DBPRINT(sc, BCE_INFO_MISC, "Setting Ethernet address = "
4552             "%6D\n", sc->eaddr, ":");
4553
4554         val = (mac_addr[0] << 8) | mac_addr[1];
4555
4556         REG_WR(sc, BCE_EMAC_MAC_MATCH0, val);
4557
4558         val = (mac_addr[2] << 24) | (mac_addr[3] << 16) |
4559             (mac_addr[4] << 8) | mac_addr[5];
4560
4561         REG_WR(sc, BCE_EMAC_MAC_MATCH1, val);
4562
4563         DBEXIT(BCE_VERBOSE_RESET);
4564 }
4565
4566
4567 /****************************************************************************/
4568 /* Stop the controller.                                                     */
4569 /*                                                                          */
4570 /* Returns:                                                                 */
4571 /*   Nothing.                                                               */
4572 /****************************************************************************/
4573 static void
4574 bce_stop(struct bce_softc *sc)
4575 {
4576         struct ifnet *ifp;
4577
4578         DBENTER(BCE_VERBOSE_RESET);
4579
4580         BCE_LOCK_ASSERT(sc);
4581
4582         ifp = sc->bce_ifp;
4583
4584         callout_stop(&sc->bce_tick_callout);
4585
4586         /* Disable the transmit/receive blocks. */
4587         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS, BCE_MISC_ENABLE_CLR_DEFAULT);
4588         REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4589         DELAY(20);
4590
4591         bce_disable_intr(sc);
4592
4593         /* Free RX buffers. */
4594 #ifdef BCE_JUMBO_HDRSPLIT
4595         bce_free_pg_chain(sc);
4596 #endif
4597         bce_free_rx_chain(sc);
4598
4599         /* Free TX buffers. */
4600         bce_free_tx_chain(sc);
4601
4602         sc->watchdog_timer = 0;
4603
4604         sc->bce_link_up = FALSE;
4605
4606         ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
4607
4608         DBEXIT(BCE_VERBOSE_RESET);
4609 }
4610
4611
4612 static int
4613 bce_reset(struct bce_softc *sc, u32 reset_code)
4614 {
4615         u32 val;
4616         int i, rc = 0;
4617
4618         DBENTER(BCE_VERBOSE_RESET);
4619
4620         DBPRINT(sc, BCE_VERBOSE_RESET, "%s(): reset_code = 0x%08X\n",
4621             __FUNCTION__, reset_code);
4622
4623         /* Wait for pending PCI transactions to complete. */
4624         REG_WR(sc, BCE_MISC_ENABLE_CLR_BITS,
4625             BCE_MISC_ENABLE_CLR_BITS_TX_DMA_ENABLE |
4626             BCE_MISC_ENABLE_CLR_BITS_DMA_ENGINE_ENABLE |
4627             BCE_MISC_ENABLE_CLR_BITS_RX_DMA_ENABLE |
4628             BCE_MISC_ENABLE_CLR_BITS_HOST_COALESCE_ENABLE);
4629         val = REG_RD(sc, BCE_MISC_ENABLE_CLR_BITS);
4630         DELAY(5);
4631
4632         /* Disable DMA */
4633         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4634             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4635                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
4636                 val &= ~BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
4637                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
4638         }
4639
4640         /* Assume bootcode is running. */
4641         sc->bce_fw_timed_out = FALSE;
4642         sc->bce_drv_cardiac_arrest = FALSE;
4643
4644         /* Give the firmware a chance to prepare for the reset. */
4645         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT0 | reset_code);
4646         if (rc)
4647                 goto bce_reset_exit;
4648
4649         /* Set a firmware reminder that this is a soft reset. */
4650         bce_shmem_wr(sc, BCE_DRV_RESET_SIGNATURE, BCE_DRV_RESET_SIGNATURE_MAGIC);
4651
4652         /* Dummy read to force the chip to complete all current transactions. */
4653         val = REG_RD(sc, BCE_MISC_ID);
4654
4655         /* Chip reset. */
4656         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4657             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4658                 REG_WR(sc, BCE_MISC_COMMAND, BCE_MISC_COMMAND_SW_RESET);
4659                 REG_RD(sc, BCE_MISC_COMMAND);
4660                 DELAY(5);
4661
4662                 val = BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4663                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4664
4665                 pci_write_config(sc->bce_dev, BCE_PCICFG_MISC_CONFIG, val, 4);
4666         } else {
4667                 val = BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4668                     BCE_PCICFG_MISC_CONFIG_REG_WINDOW_ENA |
4669                     BCE_PCICFG_MISC_CONFIG_TARGET_MB_WORD_SWAP;
4670                 REG_WR(sc, BCE_PCICFG_MISC_CONFIG, val);
4671
4672                 /* Allow up to 30us for reset to complete. */
4673                 for (i = 0; i < 10; i++) {
4674                         val = REG_RD(sc, BCE_PCICFG_MISC_CONFIG);
4675                         if ((val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4676                             BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) == 0) {
4677                                 break;
4678                         }
4679                         DELAY(10);
4680                 }
4681
4682                 /* Check that reset completed successfully. */
4683                 if (val & (BCE_PCICFG_MISC_CONFIG_CORE_RST_REQ |
4684                     BCE_PCICFG_MISC_CONFIG_CORE_RST_BSY)) {
4685                         BCE_PRINTF("%s(%d): Reset failed!\n",
4686                             __FILE__, __LINE__);
4687                         rc = EBUSY;
4688                         goto bce_reset_exit;
4689                 }
4690         }
4691
4692         /* Make sure byte swapping is properly configured. */
4693         val = REG_RD(sc, BCE_PCI_SWAP_DIAG0);
4694         if (val != 0x01020304) {
4695                 BCE_PRINTF("%s(%d): Byte swap is incorrect!\n",
4696                     __FILE__, __LINE__);
4697                 rc = ENODEV;
4698                 goto bce_reset_exit;
4699         }
4700
4701         /* Just completed a reset, assume that firmware is running again. */
4702         sc->bce_fw_timed_out = FALSE;
4703         sc->bce_drv_cardiac_arrest = FALSE;
4704
4705         /* Wait for the firmware to finish its initialization. */
4706         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT1 | reset_code);
4707         if (rc)
4708                 BCE_PRINTF("%s(%d): Firmware did not complete "
4709                     "initialization!\n", __FILE__, __LINE__);
4710
4711 bce_reset_exit:
4712         DBEXIT(BCE_VERBOSE_RESET);
4713         return (rc);
4714 }
4715
4716
4717 static int
4718 bce_chipinit(struct bce_softc *sc)
4719 {
4720         u32 val;
4721         int rc = 0;
4722
4723         DBENTER(BCE_VERBOSE_RESET);
4724
4725         bce_disable_intr(sc);
4726
4727         /*
4728          * Initialize DMA byte/word swapping, configure the number of DMA
4729          * channels and PCI clock compensation delay.
4730          */
4731         val = BCE_DMA_CONFIG_DATA_BYTE_SWAP |
4732             BCE_DMA_CONFIG_DATA_WORD_SWAP |
4733 #if BYTE_ORDER == BIG_ENDIAN
4734             BCE_DMA_CONFIG_CNTL_BYTE_SWAP |
4735 #endif
4736             BCE_DMA_CONFIG_CNTL_WORD_SWAP |
4737             DMA_READ_CHANS << 12 |
4738             DMA_WRITE_CHANS << 16;
4739
4740         val |= (0x2 << 20) | BCE_DMA_CONFIG_CNTL_PCI_COMP_DLY;
4741
4742         if ((sc->bce_flags & BCE_PCIX_FLAG) && (sc->bus_speed_mhz == 133))
4743                 val |= BCE_DMA_CONFIG_PCI_FAST_CLK_CMP;
4744
4745         /*
4746          * This setting resolves a problem observed on certain Intel PCI
4747          * chipsets that cannot handle multiple outstanding DMA operations.
4748          * See errata E9_5706A1_65.
4749          */
4750         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
4751             (BCE_CHIP_ID(sc) != BCE_CHIP_ID_5706_A0) &&
4752             !(sc->bce_flags & BCE_PCIX_FLAG))
4753                 val |= BCE_DMA_CONFIG_CNTL_PING_PONG_DMA;
4754
4755         REG_WR(sc, BCE_DMA_CONFIG, val);
4756
4757         /* Enable the RX_V2P and Context state machines before access. */
4758         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4759             BCE_MISC_ENABLE_SET_BITS_HOST_COALESCE_ENABLE |
4760             BCE_MISC_ENABLE_STATUS_BITS_RX_V2P_ENABLE |
4761             BCE_MISC_ENABLE_STATUS_BITS_CONTEXT_ENABLE);
4762
4763         /* Initialize context mapping and zero out the quick contexts. */
4764         if ((rc = bce_init_ctx(sc)) != 0)
4765                 goto bce_chipinit_exit;
4766
4767         /* Initialize the on-boards CPUs */
4768         bce_init_cpus(sc);
4769
4770         /* Enable management frames (NC-SI) to flow to the MCP. */
4771         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
4772                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) | BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
4773                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
4774         }
4775
4776         /* Prepare NVRAM for access. */
4777         if ((rc = bce_init_nvram(sc)) != 0)
4778                 goto bce_chipinit_exit;
4779
4780         /* Set the kernel bypass block size */
4781         val = REG_RD(sc, BCE_MQ_CONFIG);
4782         val &= ~BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE;
4783         val |= BCE_MQ_CONFIG_KNL_BYP_BLK_SIZE_256;
4784
4785         /* Enable bins used on the 5709. */
4786         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4787             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4788                 val |= BCE_MQ_CONFIG_BIN_MQ_MODE;
4789                 if (BCE_CHIP_ID(sc) == BCE_CHIP_ID_5709_A1)
4790                         val |= BCE_MQ_CONFIG_HALT_DIS;
4791         }
4792
4793         REG_WR(sc, BCE_MQ_CONFIG, val);
4794
4795         val = 0x10000 + (MAX_CID_CNT * MB_KERNEL_CTX_SIZE);
4796         REG_WR(sc, BCE_MQ_KNL_BYP_WIND_START, val);
4797         REG_WR(sc, BCE_MQ_KNL_WIND_END, val);
4798
4799         /* Set the page size and clear the RV2P processor stall bits. */
4800         val = (BCM_PAGE_BITS - 8) << 24;
4801         REG_WR(sc, BCE_RV2P_CONFIG, val);
4802
4803         /* Configure page size. */
4804         val = REG_RD(sc, BCE_TBDR_CONFIG);
4805         val &= ~BCE_TBDR_CONFIG_PAGE_SIZE;
4806         val |= (BCM_PAGE_BITS - 8) << 24 | 0x40;
4807         REG_WR(sc, BCE_TBDR_CONFIG, val);
4808
4809         /* Set the perfect match control register to default. */
4810         REG_WR_IND(sc, BCE_RXP_PM_CTRL, 0);
4811
4812 bce_chipinit_exit:
4813         DBEXIT(BCE_VERBOSE_RESET);
4814
4815         return(rc);
4816 }
4817
4818
4819 /****************************************************************************/
4820 /* Initialize the controller in preparation to send/receive traffic.        */
4821 /*                                                                          */
4822 /* Returns:                                                                 */
4823 /*   0 for success, positive value for failure.                             */
4824 /****************************************************************************/
4825 static int
4826 bce_blockinit(struct bce_softc *sc)
4827 {
4828         u32 reg, val;
4829         int rc = 0;
4830
4831         DBENTER(BCE_VERBOSE_RESET);
4832
4833         /* Load the hardware default MAC address. */
4834         bce_set_mac_addr(sc);
4835
4836         /* Set the Ethernet backoff seed value */
4837         val = sc->eaddr[0]         + (sc->eaddr[1] << 8) +
4838               (sc->eaddr[2] << 16) + (sc->eaddr[3]     ) +
4839               (sc->eaddr[4] << 8)  + (sc->eaddr[5] << 16);
4840         REG_WR(sc, BCE_EMAC_BACKOFF_SEED, val);
4841
4842         sc->last_status_idx = 0;
4843         sc->rx_mode = BCE_EMAC_RX_MODE_SORT_MODE;
4844
4845         /* Set up link change interrupt generation. */
4846         REG_WR(sc, BCE_EMAC_ATTENTION_ENA, BCE_EMAC_ATTENTION_ENA_LINK);
4847
4848         /* Program the physical address of the status block. */
4849         REG_WR(sc, BCE_HC_STATUS_ADDR_L,
4850             BCE_ADDR_LO(sc->status_block_paddr));
4851         REG_WR(sc, BCE_HC_STATUS_ADDR_H,
4852             BCE_ADDR_HI(sc->status_block_paddr));
4853
4854         /* Program the physical address of the statistics block. */
4855         REG_WR(sc, BCE_HC_STATISTICS_ADDR_L,
4856             BCE_ADDR_LO(sc->stats_block_paddr));
4857         REG_WR(sc, BCE_HC_STATISTICS_ADDR_H,
4858             BCE_ADDR_HI(sc->stats_block_paddr));
4859
4860         /* Program various host coalescing parameters. */
4861         REG_WR(sc, BCE_HC_TX_QUICK_CONS_TRIP,
4862             (sc->bce_tx_quick_cons_trip_int << 16) | sc->bce_tx_quick_cons_trip);
4863         REG_WR(sc, BCE_HC_RX_QUICK_CONS_TRIP,
4864             (sc->bce_rx_quick_cons_trip_int << 16) | sc->bce_rx_quick_cons_trip);
4865         REG_WR(sc, BCE_HC_COMP_PROD_TRIP,
4866             (sc->bce_comp_prod_trip_int << 16) | sc->bce_comp_prod_trip);
4867         REG_WR(sc, BCE_HC_TX_TICKS,
4868             (sc->bce_tx_ticks_int << 16) | sc->bce_tx_ticks);
4869         REG_WR(sc, BCE_HC_RX_TICKS,
4870             (sc->bce_rx_ticks_int << 16) | sc->bce_rx_ticks);
4871         REG_WR(sc, BCE_HC_COM_TICKS,
4872             (sc->bce_com_ticks_int << 16) | sc->bce_com_ticks);
4873         REG_WR(sc, BCE_HC_CMD_TICKS,
4874             (sc->bce_cmd_ticks_int << 16) | sc->bce_cmd_ticks);
4875         REG_WR(sc, BCE_HC_STATS_TICKS,
4876             (sc->bce_stats_ticks & 0xffff00));
4877         REG_WR(sc, BCE_HC_STAT_COLLECT_TICKS, 0xbb8);  /* 3ms */
4878
4879         /* Configure the Host Coalescing block. */
4880         val = BCE_HC_CONFIG_RX_TMR_MODE | BCE_HC_CONFIG_TX_TMR_MODE |
4881             BCE_HC_CONFIG_COLLECT_STATS;
4882
4883 #if 0
4884         /* ToDo: Add MSI-X support. */
4885         if (sc->bce_flags & BCE_USING_MSIX_FLAG) {
4886                 u32 base = ((BCE_TX_VEC - 1) * BCE_HC_SB_CONFIG_SIZE) +
4887                     BCE_HC_SB_CONFIG_1;
4888
4889                 REG_WR(sc, BCE_HC_MSIX_BIT_VECTOR, BCE_HC_MSIX_BIT_VECTOR_VAL);
4890
4891                 REG_WR(sc, base, BCE_HC_SB_CONFIG_1_TX_TMR_MODE |
4892                     BCE_HC_SB_CONFIG_1_ONE_SHOT);
4893
4894                 REG_WR(sc, base + BCE_HC_TX_QUICK_CONS_TRIP_OFF,
4895                     (sc->tx_quick_cons_trip_int << 16) |
4896                      sc->tx_quick_cons_trip);
4897
4898                 REG_WR(sc, base + BCE_HC_TX_TICKS_OFF,
4899                     (sc->tx_ticks_int << 16) | sc->tx_ticks);
4900
4901                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
4902         }
4903
4904         /*
4905          * Tell the HC block to automatically set the
4906          * INT_MASK bit after an MSI/MSI-X interrupt
4907          * is generated so the driver doesn't have to.
4908          */
4909         if (sc->bce_flags & BCE_ONE_SHOT_MSI_FLAG)
4910                 val |= BCE_HC_CONFIG_ONE_SHOT;
4911
4912         /* Set the MSI-X status blocks to 128 byte boundaries. */
4913         if (sc->bce_flags & BCE_USING_MSIX_FLAG)
4914                 val |= BCE_HC_CONFIG_SB_ADDR_INC_128B;
4915 #endif
4916
4917         REG_WR(sc, BCE_HC_CONFIG, val);
4918
4919         /* Clear the internal statistics counters. */
4920         REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
4921
4922         /* Verify that bootcode is running. */
4923         reg = bce_shmem_rd(sc, BCE_DEV_INFO_SIGNATURE);
4924
4925         DBRUNIF(DB_RANDOMTRUE(bootcode_running_failure_sim_control),
4926             BCE_PRINTF("%s(%d): Simulating bootcode failure.\n",
4927             __FILE__, __LINE__);
4928             reg = 0);
4929
4930         if ((reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK) !=
4931             BCE_DEV_INFO_SIGNATURE_MAGIC) {
4932                 BCE_PRINTF("%s(%d): Bootcode not running! Found: 0x%08X, "
4933                     "Expected: 08%08X\n", __FILE__, __LINE__,
4934                     (reg & BCE_DEV_INFO_SIGNATURE_MAGIC_MASK),
4935                     BCE_DEV_INFO_SIGNATURE_MAGIC);
4936                 rc = ENODEV;
4937                 goto bce_blockinit_exit;
4938         }
4939
4940         /* Enable DMA */
4941         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4942             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
4943                 val = REG_RD(sc, BCE_MISC_NEW_CORE_CTL);
4944                 val |= BCE_MISC_NEW_CORE_CTL_DMA_ENABLE;
4945                 REG_WR(sc, BCE_MISC_NEW_CORE_CTL, val);
4946         }
4947
4948         /* Allow bootcode to apply additional fixes before enabling MAC. */
4949         rc = bce_fw_sync(sc, BCE_DRV_MSG_DATA_WAIT2 |
4950             BCE_DRV_MSG_CODE_RESET);
4951
4952         /* Enable link state change interrupt generation. */
4953         REG_WR(sc, BCE_HC_ATTN_BITS_ENABLE, STATUS_ATTN_BITS_LINK_STATE);
4954
4955         /* Enable the RXP. */
4956         bce_start_rxp_cpu(sc);
4957
4958         /* Disable management frames (NC-SI) from flowing to the MCP. */
4959         if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
4960                 val = REG_RD(sc, BCE_RPM_MGMT_PKT_CTRL) &
4961                     ~BCE_RPM_MGMT_PKT_CTRL_MGMT_EN;
4962                 REG_WR(sc, BCE_RPM_MGMT_PKT_CTRL, val);
4963         }
4964
4965         /* Enable all remaining blocks in the MAC. */
4966         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
4967             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
4968                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4969                     BCE_MISC_ENABLE_DEFAULT_XI);
4970         else
4971                 REG_WR(sc, BCE_MISC_ENABLE_SET_BITS,
4972                     BCE_MISC_ENABLE_DEFAULT);
4973
4974         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
4975         DELAY(20);
4976
4977         /* Save the current host coalescing block settings. */
4978         sc->hc_command = REG_RD(sc, BCE_HC_COMMAND);
4979
4980 bce_blockinit_exit:
4981         DBEXIT(BCE_VERBOSE_RESET);
4982
4983         return (rc);
4984 }
4985
4986
4987 /****************************************************************************/
4988 /* Encapsulate an mbuf into the rx_bd chain.                                */
4989 /*                                                                          */
4990 /* Returns:                                                                 */
4991 /*   0 for success, positive value for failure.                             */
4992 /****************************************************************************/
4993 static int
4994 bce_get_rx_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod,
4995     u16 *chain_prod, u32 *prod_bseq)
4996 {
4997         bus_dmamap_t map;
4998         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
4999         struct mbuf *m_new = NULL;
5000         struct rx_bd *rxbd;
5001         int nsegs, error, rc = 0;
5002 #ifdef BCE_DEBUG
5003         u16 debug_chain_prod = *chain_prod;
5004 #endif
5005
5006         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5007
5008         /* Make sure the inputs are valid. */
5009         DBRUNIF((*chain_prod > MAX_RX_BD),
5010             BCE_PRINTF("%s(%d): RX producer out of range: "
5011             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5012             *chain_prod, (u16) MAX_RX_BD));
5013
5014         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5015             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n", __FUNCTION__,
5016             *prod, *chain_prod, *prod_bseq);
5017
5018         /* Update some debug statistic counters */
5019         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5020             sc->rx_low_watermark = sc->free_rx_bd);
5021         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
5022             sc->rx_empty_count++);
5023
5024         /* Check whether this is a new mbuf allocation. */
5025         if (m == NULL) {
5026
5027                 /* Simulate an mbuf allocation failure. */
5028                 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5029                     sc->mbuf_alloc_failed_count++;
5030                     sc->mbuf_alloc_failed_sim_count++;
5031                     rc = ENOBUFS;
5032                     goto bce_get_rx_buf_exit);
5033
5034                 /* This is a new mbuf allocation. */
5035 #ifdef BCE_JUMBO_HDRSPLIT
5036                 MGETHDR(m_new, M_DONTWAIT, MT_DATA);
5037 #else
5038                 if (sc->rx_bd_mbuf_alloc_size <= MCLBYTES)
5039                         m_new = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
5040                 else
5041                         m_new = m_getjcl(M_DONTWAIT, MT_DATA, M_PKTHDR,
5042                             sc->rx_bd_mbuf_alloc_size);
5043 #endif
5044
5045                 if (m_new == NULL) {
5046                         sc->mbuf_alloc_failed_count++;
5047                         rc = ENOBUFS;
5048                         goto bce_get_rx_buf_exit;
5049                 }
5050
5051                 DBRUN(sc->debug_rx_mbuf_alloc++);
5052         } else {
5053                 /* Reuse an existing mbuf. */
5054                 m_new = m;
5055         }
5056
5057         /* Make sure we have a valid packet header. */
5058         M_ASSERTPKTHDR(m_new);
5059
5060         /* Initialize the mbuf size and pad if necessary for alignment. */
5061         m_new->m_pkthdr.len = m_new->m_len = sc->rx_bd_mbuf_alloc_size;
5062         m_adj(m_new, sc->rx_bd_mbuf_align_pad);
5063
5064         /* ToDo: Consider calling m_fragment() to test error handling. */
5065
5066         /* Map the mbuf cluster into device memory. */
5067         map = sc->rx_mbuf_map[*chain_prod];
5068         error = bus_dmamap_load_mbuf_sg(sc->rx_mbuf_tag, map, m_new,
5069             segs, &nsegs, BUS_DMA_NOWAIT);
5070
5071         /* Handle any mapping errors. */
5072         if (error) {
5073                 BCE_PRINTF("%s(%d): Error mapping mbuf into RX "
5074                     "chain (%d)!\n", __FILE__, __LINE__, error);
5075
5076                 sc->dma_map_addr_rx_failed_count++;
5077                 m_freem(m_new);
5078
5079                 DBRUN(sc->debug_rx_mbuf_alloc--);
5080
5081                 rc = ENOBUFS;
5082                 goto bce_get_rx_buf_exit;
5083         }
5084
5085         /* All mbufs must map to a single segment. */
5086         KASSERT(nsegs == 1, ("%s(): Too many segments returned (%d)!",
5087             __FUNCTION__, nsegs));
5088
5089         /* Setup the rx_bd for the segment. */
5090         rxbd = &sc->rx_bd_chain[RX_PAGE(*chain_prod)][RX_IDX(*chain_prod)];
5091
5092         rxbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(segs[0].ds_addr));
5093         rxbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(segs[0].ds_addr));
5094         rxbd->rx_bd_len       = htole32(segs[0].ds_len);
5095         rxbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5096         *prod_bseq += segs[0].ds_len;
5097
5098         /* Save the mbuf and update our counter. */
5099         sc->rx_mbuf_ptr[*chain_prod] = m_new;
5100         sc->free_rx_bd -= nsegs;
5101
5102         DBRUNMSG(BCE_INSANE_RECV,
5103             bce_dump_rx_mbuf_chain(sc, debug_chain_prod, nsegs));
5104
5105         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5106             "chain_prod = 0x%04X, prod_bseq = 0x%08X\n",
5107             __FUNCTION__, *prod, *chain_prod, *prod_bseq);
5108
5109 bce_get_rx_buf_exit:
5110         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5111
5112         return(rc);
5113 }
5114
5115
5116 #ifdef BCE_JUMBO_HDRSPLIT
5117 /****************************************************************************/
5118 /* Encapsulate an mbuf cluster into the page chain.                         */
5119 /*                                                                          */
5120 /* Returns:                                                                 */
5121 /*   0 for success, positive value for failure.                             */
5122 /****************************************************************************/
5123 static int
5124 bce_get_pg_buf(struct bce_softc *sc, struct mbuf *m, u16 *prod,
5125         u16 *prod_idx)
5126 {
5127         bus_dmamap_t map;
5128         bus_addr_t busaddr;
5129         struct mbuf *m_new = NULL;
5130         struct rx_bd *pgbd;
5131         int error, rc = 0;
5132 #ifdef BCE_DEBUG
5133         u16 debug_prod_idx = *prod_idx;
5134 #endif
5135
5136         DBENTER(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5137
5138         /* Make sure the inputs are valid. */
5139         DBRUNIF((*prod_idx > MAX_PG_BD),
5140             BCE_PRINTF("%s(%d): page producer out of range: "
5141             "0x%04X > 0x%04X\n", __FILE__, __LINE__,
5142             *prod_idx, (u16) MAX_PG_BD));
5143
5144         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): prod = 0x%04X, "
5145             "chain_prod = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
5146
5147         /* Update counters if we've hit a new low or run out of pages. */
5148         DBRUNIF((sc->free_pg_bd < sc->pg_low_watermark),
5149             sc->pg_low_watermark = sc->free_pg_bd);
5150         DBRUNIF((sc->free_pg_bd == sc->max_pg_bd), sc->pg_empty_count++);
5151
5152         /* Check whether this is a new mbuf allocation. */
5153         if (m == NULL) {
5154
5155                 /* Simulate an mbuf allocation failure. */
5156                 DBRUNIF(DB_RANDOMTRUE(mbuf_alloc_failed_sim_control),
5157                     sc->mbuf_alloc_failed_count++;
5158                     sc->mbuf_alloc_failed_sim_count++;
5159                     rc = ENOBUFS;
5160                     goto bce_get_pg_buf_exit);
5161
5162                 /* This is a new mbuf allocation. */
5163                 m_new = m_getcl(M_DONTWAIT, MT_DATA, 0);
5164                 if (m_new == NULL) {
5165                         sc->mbuf_alloc_failed_count++;
5166                         rc = ENOBUFS;
5167                         goto bce_get_pg_buf_exit;
5168                 }
5169
5170                 DBRUN(sc->debug_pg_mbuf_alloc++);
5171         } else {
5172                 /* Reuse an existing mbuf. */
5173                 m_new = m;
5174                 m_new->m_data = m_new->m_ext.ext_buf;
5175         }
5176
5177         m_new->m_len = sc->pg_bd_mbuf_alloc_size;
5178
5179         /* ToDo: Consider calling m_fragment() to test error handling. */
5180
5181         /* Map the mbuf cluster into device memory. */
5182         map = sc->pg_mbuf_map[*prod_idx];
5183         error = bus_dmamap_load(sc->pg_mbuf_tag, map, mtod(m_new, void *),
5184             sc->pg_bd_mbuf_alloc_size, bce_dma_map_addr,
5185             &busaddr, BUS_DMA_NOWAIT);
5186
5187         /* Handle any mapping errors. */
5188         if (error) {
5189                 BCE_PRINTF("%s(%d): Error mapping mbuf into page chain!\n",
5190                     __FILE__, __LINE__);
5191
5192                 m_freem(m_new);
5193                 DBRUN(sc->debug_pg_mbuf_alloc--);
5194
5195                 rc = ENOBUFS;
5196                 goto bce_get_pg_buf_exit;
5197         }
5198
5199         /* ToDo: Do we need bus_dmamap_sync(,,BUS_DMASYNC_PREREAD) here? */
5200
5201         /*
5202          * The page chain uses the same rx_bd data structure
5203          * as the receive chain but doesn't require a byte sequence (bseq).
5204          */
5205         pgbd = &sc->pg_bd_chain[PG_PAGE(*prod_idx)][PG_IDX(*prod_idx)];
5206
5207         pgbd->rx_bd_haddr_lo  = htole32(BCE_ADDR_LO(busaddr));
5208         pgbd->rx_bd_haddr_hi  = htole32(BCE_ADDR_HI(busaddr));
5209         pgbd->rx_bd_len       = htole32(sc->pg_bd_mbuf_alloc_size);
5210         pgbd->rx_bd_flags     = htole32(RX_BD_FLAGS_START | RX_BD_FLAGS_END);
5211
5212         /* Save the mbuf and update our counter. */
5213         sc->pg_mbuf_ptr[*prod_idx] = m_new;
5214         sc->free_pg_bd--;
5215
5216         DBRUNMSG(BCE_INSANE_RECV,
5217             bce_dump_pg_mbuf_chain(sc, debug_prod_idx, 1));
5218
5219         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): prod = 0x%04X, "
5220             "prod_idx = 0x%04X\n", __FUNCTION__, *prod, *prod_idx);
5221
5222 bce_get_pg_buf_exit:
5223         DBEXIT(BCE_EXTREME_RESET | BCE_EXTREME_RECV | BCE_EXTREME_LOAD);
5224
5225         return(rc);
5226 }
5227 #endif /* BCE_JUMBO_HDRSPLIT */
5228
5229
5230 /****************************************************************************/
5231 /* Initialize the TX context memory.                                        */
5232 /*                                                                          */
5233 /* Returns:                                                                 */
5234 /*   Nothing                                                                */
5235 /****************************************************************************/
5236 static void
5237 bce_init_tx_context(struct bce_softc *sc)
5238 {
5239         u32 val;
5240
5241         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5242
5243         /* Initialize the context ID for an L2 TX chain. */
5244         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
5245                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
5246                 /* Set the CID type to support an L2 connection. */
5247                 val = BCE_L2CTX_TX_TYPE_TYPE_L2_XI |
5248                     BCE_L2CTX_TX_TYPE_SIZE_L2_XI;
5249                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE_XI, val);
5250                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2_XI | (8 << 16);
5251                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5252                     BCE_L2CTX_TX_CMD_TYPE_XI, val);
5253
5254                 /* Point the hardware to the first page in the chain. */
5255                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5256                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5257                     BCE_L2CTX_TX_TBDR_BHADDR_HI_XI, val);
5258                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5259                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5260                     BCE_L2CTX_TX_TBDR_BHADDR_LO_XI, val);
5261         } else {
5262                 /* Set the CID type to support an L2 connection. */
5263                 val = BCE_L2CTX_TX_TYPE_TYPE_L2 | BCE_L2CTX_TX_TYPE_SIZE_L2;
5264                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_TYPE, val);
5265                 val = BCE_L2CTX_TX_CMD_TYPE_TYPE_L2 | (8 << 16);
5266                 CTX_WR(sc, GET_CID_ADDR(TX_CID), BCE_L2CTX_TX_CMD_TYPE, val);
5267
5268                 /* Point the hardware to the first page in the chain. */
5269                 val = BCE_ADDR_HI(sc->tx_bd_chain_paddr[0]);
5270                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5271                     BCE_L2CTX_TX_TBDR_BHADDR_HI, val);
5272                 val = BCE_ADDR_LO(sc->tx_bd_chain_paddr[0]);
5273                 CTX_WR(sc, GET_CID_ADDR(TX_CID),
5274                     BCE_L2CTX_TX_TBDR_BHADDR_LO, val);
5275         }
5276
5277         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
5278 }
5279
5280
5281 /****************************************************************************/
5282 /* Allocate memory and initialize the TX data structures.                   */
5283 /*                                                                          */
5284 /* Returns:                                                                 */
5285 /*   0 for success, positive value for failure.                             */
5286 /****************************************************************************/
5287 static int
5288 bce_init_tx_chain(struct bce_softc *sc)
5289 {
5290         struct tx_bd *txbd;
5291         int i, rc = 0;
5292
5293         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5294
5295         /* Set the initial TX producer/consumer indices. */
5296         sc->tx_prod        = 0;
5297         sc->tx_cons        = 0;
5298         sc->tx_prod_bseq   = 0;
5299         sc->used_tx_bd     = 0;
5300         sc->max_tx_bd      = USABLE_TX_BD;
5301         DBRUN(sc->tx_hi_watermark = 0);
5302         DBRUN(sc->tx_full_count = 0);
5303
5304         /*
5305          * The NetXtreme II supports a linked-list structre called
5306          * a Buffer Descriptor Chain (or BD chain).  A BD chain
5307          * consists of a series of 1 or more chain pages, each of which
5308          * consists of a fixed number of BD entries.
5309          * The last BD entry on each page is a pointer to the next page
5310          * in the chain, and the last pointer in the BD chain
5311          * points back to the beginning of the chain.
5312          */
5313
5314         /* Set the TX next pointer chain entries. */
5315         for (i = 0; i < TX_PAGES; i++) {
5316                 int j;
5317
5318                 txbd = &sc->tx_bd_chain[i][USABLE_TX_BD_PER_PAGE];
5319
5320                 /* Check if we've reached the last page. */
5321                 if (i == (TX_PAGES - 1))
5322                         j = 0;
5323                 else
5324                         j = i + 1;
5325
5326                 txbd->tx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->tx_bd_chain_paddr[j]));
5327                 txbd->tx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->tx_bd_chain_paddr[j]));
5328         }
5329
5330         bce_init_tx_context(sc);
5331
5332         DBRUNMSG(BCE_INSANE_SEND, bce_dump_tx_chain(sc, 0, TOTAL_TX_BD));
5333         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_LOAD);
5334
5335         return(rc);
5336 }
5337
5338
5339 /****************************************************************************/
5340 /* Free memory and clear the TX data structures.                            */
5341 /*                                                                          */
5342 /* Returns:                                                                 */
5343 /*   Nothing.                                                               */
5344 /****************************************************************************/
5345 static void
5346 bce_free_tx_chain(struct bce_softc *sc)
5347 {
5348         int i;
5349
5350         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5351
5352         /* Unmap, unload, and free any mbufs still in the TX mbuf chain. */
5353         for (i = 0; i < TOTAL_TX_BD; i++) {
5354                 if (sc->tx_mbuf_ptr[i] != NULL) {
5355                         if (sc->tx_mbuf_map[i] != NULL)
5356                                 bus_dmamap_sync(sc->tx_mbuf_tag,
5357                                     sc->tx_mbuf_map[i],
5358                                     BUS_DMASYNC_POSTWRITE);
5359                         m_freem(sc->tx_mbuf_ptr[i]);
5360                         sc->tx_mbuf_ptr[i] = NULL;
5361                         DBRUN(sc->debug_tx_mbuf_alloc--);
5362                 }
5363         }
5364
5365         /* Clear each TX chain page. */
5366         for (i = 0; i < TX_PAGES; i++)
5367                 bzero((char *)sc->tx_bd_chain[i], BCE_TX_CHAIN_PAGE_SZ);
5368
5369         sc->used_tx_bd = 0;
5370
5371         /* Check if we lost any mbufs in the process. */
5372         DBRUNIF((sc->debug_tx_mbuf_alloc),
5373             BCE_PRINTF("%s(%d): Memory leak! Lost %d mbufs "
5374             "from tx chain!\n", __FILE__, __LINE__,
5375             sc->debug_tx_mbuf_alloc));
5376
5377         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_SEND | BCE_VERBOSE_UNLOAD);
5378 }
5379
5380
5381 /****************************************************************************/
5382 /* Initialize the RX context memory.                                        */
5383 /*                                                                          */
5384 /* Returns:                                                                 */
5385 /*   Nothing                                                                */
5386 /****************************************************************************/
5387 static void
5388 bce_init_rx_context(struct bce_softc *sc)
5389 {
5390         u32 val;
5391
5392         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5393
5394         /* Init the type, size, and BD cache levels for the RX context. */
5395         val = BCE_L2CTX_RX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
5396             BCE_L2CTX_RX_CTX_TYPE_SIZE_L2 |
5397             (0x02 << BCE_L2CTX_RX_BD_PRE_READ_SHIFT);
5398
5399         /*
5400          * Set the level for generating pause frames
5401          * when the number of available rx_bd's gets
5402          * too low (the low watermark) and the level
5403          * when pause frames can be stopped (the high
5404          * watermark).
5405          */
5406         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
5407             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
5408                 u32 lo_water, hi_water;
5409
5410                 if (sc->bce_flags && BCE_USING_TX_FLOW_CONTROL) {
5411                         lo_water = BCE_L2CTX_RX_LO_WATER_MARK_DEFAULT;
5412                 } else {
5413                         lo_water = 0;
5414                 }
5415
5416                 if (lo_water >= USABLE_RX_BD) {
5417                         lo_water = 0;
5418                 }
5419
5420                 hi_water = USABLE_RX_BD / 4;
5421
5422                 if (hi_water <= lo_water) {
5423                         lo_water = 0;
5424                 }
5425
5426                 lo_water /= BCE_L2CTX_RX_LO_WATER_MARK_SCALE;
5427                 hi_water /= BCE_L2CTX_RX_HI_WATER_MARK_SCALE;
5428
5429                 if (hi_water > 0xf)
5430                         hi_water = 0xf;
5431                 else if (hi_water == 0)
5432                         lo_water = 0;
5433
5434                 val |= (lo_water << BCE_L2CTX_RX_LO_WATER_MARK_SHIFT) |
5435                     (hi_water << BCE_L2CTX_RX_HI_WATER_MARK_SHIFT);
5436         }
5437
5438         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_CTX_TYPE, val);
5439
5440         /* Setup the MQ BIN mapping for l2_ctx_host_bseq. */
5441         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
5442             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
5443                 val = REG_RD(sc, BCE_MQ_MAP_L2_5);
5444                 REG_WR(sc, BCE_MQ_MAP_L2_5, val | BCE_MQ_MAP_L2_5_ARM);
5445         }
5446
5447         /* Point the hardware to the first page in the chain. */
5448         val = BCE_ADDR_HI(sc->rx_bd_chain_paddr[0]);
5449         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_HI, val);
5450         val = BCE_ADDR_LO(sc->rx_bd_chain_paddr[0]);
5451         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_BDHADDR_LO, val);
5452
5453         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_CTX);
5454 }
5455
5456
5457 /****************************************************************************/
5458 /* Allocate memory and initialize the RX data structures.                   */
5459 /*                                                                          */
5460 /* Returns:                                                                 */
5461 /*   0 for success, positive value for failure.                             */
5462 /****************************************************************************/
5463 static int
5464 bce_init_rx_chain(struct bce_softc *sc)
5465 {
5466         struct rx_bd *rxbd;
5467         int i, rc = 0;
5468
5469         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5470             BCE_VERBOSE_CTX);
5471
5472         /* Initialize the RX producer and consumer indices. */
5473         sc->rx_prod        = 0;
5474         sc->rx_cons        = 0;
5475         sc->rx_prod_bseq   = 0;
5476         sc->free_rx_bd     = USABLE_RX_BD;
5477         sc->max_rx_bd      = USABLE_RX_BD;
5478
5479         /* Initialize the RX next pointer chain entries. */
5480         for (i = 0; i < RX_PAGES; i++) {
5481                 int j;
5482
5483                 rxbd = &sc->rx_bd_chain[i][USABLE_RX_BD_PER_PAGE];
5484
5485                 /* Check if we've reached the last page. */
5486                 if (i == (RX_PAGES - 1))
5487                         j = 0;
5488                 else
5489                         j = i + 1;
5490
5491                 /* Setup the chain page pointers. */
5492                 rxbd->rx_bd_haddr_hi =
5493                     htole32(BCE_ADDR_HI(sc->rx_bd_chain_paddr[j]));
5494                 rxbd->rx_bd_haddr_lo =
5495                     htole32(BCE_ADDR_LO(sc->rx_bd_chain_paddr[j]));
5496         }
5497
5498         /* Fill up the RX chain. */
5499         bce_fill_rx_chain(sc);
5500
5501         DBRUN(sc->rx_low_watermark = USABLE_RX_BD);
5502         DBRUN(sc->rx_empty_count = 0);
5503         for (i = 0; i < RX_PAGES; i++) {
5504                 bus_dmamap_sync(sc->rx_bd_chain_tag, sc->rx_bd_chain_map[i],
5505                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5506         }
5507
5508         bce_init_rx_context(sc);
5509
5510         DBRUNMSG(BCE_EXTREME_RECV, bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD));
5511         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5512             BCE_VERBOSE_CTX);
5513
5514         /* ToDo: Are there possible failure modes here? */
5515
5516         return(rc);
5517 }
5518
5519
5520 /****************************************************************************/
5521 /* Add mbufs to the RX chain until its full or an mbuf allocation error     */
5522 /* occurs.                                                                  */
5523 /*                                                                          */
5524 /* Returns:                                                                 */
5525 /*   Nothing                                                                */
5526 /****************************************************************************/
5527 static void
5528 bce_fill_rx_chain(struct bce_softc *sc)
5529 {
5530         u16 prod, prod_idx;
5531         u32 prod_bseq;
5532
5533         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5534             BCE_VERBOSE_CTX);
5535
5536         /* Get the RX chain producer indices. */
5537         prod      = sc->rx_prod;
5538         prod_bseq = sc->rx_prod_bseq;
5539
5540         /* Keep filling the RX chain until it's full. */
5541         while (sc->free_rx_bd > 0) {
5542                 prod_idx = RX_CHAIN_IDX(prod);
5543                 if (bce_get_rx_buf(sc, NULL, &prod, &prod_idx, &prod_bseq)) {
5544                         /* Bail out if we can't add an mbuf to the chain. */
5545                         break;
5546                 }
5547                 prod = NEXT_RX_BD(prod);
5548         }
5549
5550         /* Save the RX chain producer indices. */
5551         sc->rx_prod      = prod;
5552         sc->rx_prod_bseq = prod_bseq;
5553
5554         /* We should never end up pointing to a next page pointer. */
5555         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5556             BCE_PRINTF("%s(): Invalid rx_prod value: 0x%04X\n",
5557             __FUNCTION__, sc->rx_prod));
5558
5559         /* Write the mailbox and tell the chip about the waiting rx_bd's. */
5560         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) +
5561             BCE_L2MQ_RX_HOST_BDIDX, sc->rx_prod);
5562         REG_WR(sc, MB_GET_CID_ADDR(RX_CID) +
5563             BCE_L2MQ_RX_HOST_BSEQ, sc->rx_prod_bseq);
5564
5565         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5566             BCE_VERBOSE_CTX);
5567 }
5568
5569
5570 /****************************************************************************/
5571 /* Free memory and clear the RX data structures.                            */
5572 /*                                                                          */
5573 /* Returns:                                                                 */
5574 /*   Nothing.                                                               */
5575 /****************************************************************************/
5576 static void
5577 bce_free_rx_chain(struct bce_softc *sc)
5578 {
5579         int i;
5580
5581         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5582
5583         /* Free any mbufs still in the RX mbuf chain. */
5584         for (i = 0; i < TOTAL_RX_BD; i++) {
5585                 if (sc->rx_mbuf_ptr[i] != NULL) {
5586                         if (sc->rx_mbuf_map[i] != NULL)
5587                                 bus_dmamap_sync(sc->rx_mbuf_tag,
5588                                     sc->rx_mbuf_map[i],
5589                                     BUS_DMASYNC_POSTREAD);
5590                         m_freem(sc->rx_mbuf_ptr[i]);
5591                         sc->rx_mbuf_ptr[i] = NULL;
5592                         DBRUN(sc->debug_rx_mbuf_alloc--);
5593                 }
5594         }
5595
5596         /* Clear each RX chain page. */
5597         for (i = 0; i < RX_PAGES; i++)
5598                 if (sc->rx_bd_chain[i] != NULL) {
5599                         bzero((char *)sc->rx_bd_chain[i],
5600                             BCE_RX_CHAIN_PAGE_SZ);
5601                 }
5602
5603         sc->free_rx_bd = sc->max_rx_bd;
5604
5605         /* Check if we lost any mbufs in the process. */
5606         DBRUNIF((sc->debug_rx_mbuf_alloc),
5607             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from rx chain!\n",
5608             __FUNCTION__, sc->debug_rx_mbuf_alloc));
5609
5610         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5611 }
5612
5613
5614 #ifdef BCE_JUMBO_HDRSPLIT
5615 /****************************************************************************/
5616 /* Allocate memory and initialize the page data structures.                 */
5617 /* Assumes that bce_init_rx_chain() has not already been called.            */
5618 /*                                                                          */
5619 /* Returns:                                                                 */
5620 /*   0 for success, positive value for failure.                             */
5621 /****************************************************************************/
5622 static int
5623 bce_init_pg_chain(struct bce_softc *sc)
5624 {
5625         struct rx_bd *pgbd;
5626         int i, rc = 0;
5627         u32 val;
5628
5629         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5630                 BCE_VERBOSE_CTX);
5631
5632         /* Initialize the page producer and consumer indices. */
5633         sc->pg_prod        = 0;
5634         sc->pg_cons        = 0;
5635         sc->free_pg_bd     = USABLE_PG_BD;
5636         sc->max_pg_bd      = USABLE_PG_BD;
5637         DBRUN(sc->pg_low_watermark = sc->max_pg_bd);
5638         DBRUN(sc->pg_empty_count = 0);
5639
5640         /* Initialize the page next pointer chain entries. */
5641         for (i = 0; i < PG_PAGES; i++) {
5642                 int j;
5643
5644                 pgbd = &sc->pg_bd_chain[i][USABLE_PG_BD_PER_PAGE];
5645
5646                 /* Check if we've reached the last page. */
5647                 if (i == (PG_PAGES - 1))
5648                         j = 0;
5649                 else
5650                         j = i + 1;
5651
5652                 /* Setup the chain page pointers. */
5653                 pgbd->rx_bd_haddr_hi = htole32(BCE_ADDR_HI(sc->pg_bd_chain_paddr[j]));
5654                 pgbd->rx_bd_haddr_lo = htole32(BCE_ADDR_LO(sc->pg_bd_chain_paddr[j]));
5655         }
5656
5657         /* Setup the MQ BIN mapping for host_pg_bidx. */
5658         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709)     ||
5659                 (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
5660                 REG_WR(sc, BCE_MQ_MAP_L2_3, BCE_MQ_MAP_L2_3_DEFAULT);
5661
5662         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, 0);
5663
5664         /* Configure the rx_bd and page chain mbuf cluster size. */
5665         val = (sc->rx_bd_mbuf_data_len << 16) | sc->pg_bd_mbuf_alloc_size;
5666         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_PG_BUF_SIZE, val);
5667
5668         /* Configure the context reserved for jumbo support. */
5669         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_RBDC_KEY,
5670                 BCE_L2CTX_RX_RBDC_JUMBO_KEY);
5671
5672         /* Point the hardware to the first page in the page chain. */
5673         val = BCE_ADDR_HI(sc->pg_bd_chain_paddr[0]);
5674         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_HI, val);
5675         val = BCE_ADDR_LO(sc->pg_bd_chain_paddr[0]);
5676         CTX_WR(sc, GET_CID_ADDR(RX_CID), BCE_L2CTX_RX_NX_PG_BDHADDR_LO, val);
5677
5678         /* Fill up the page chain. */
5679         bce_fill_pg_chain(sc);
5680
5681         for (i = 0; i < PG_PAGES; i++) {
5682                 bus_dmamap_sync(sc->pg_bd_chain_tag, sc->pg_bd_chain_map[i],
5683                     BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
5684         }
5685
5686         DBRUNMSG(BCE_EXTREME_RECV, bce_dump_pg_chain(sc, 0, TOTAL_PG_BD));
5687         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_LOAD |
5688                 BCE_VERBOSE_CTX);
5689         return(rc);
5690 }
5691
5692
5693 /****************************************************************************/
5694 /* Add mbufs to the page chain until its full or an mbuf allocation error   */
5695 /* occurs.                                                                  */
5696 /*                                                                          */
5697 /* Returns:                                                                 */
5698 /*   Nothing                                                                */
5699 /****************************************************************************/
5700 static void
5701 bce_fill_pg_chain(struct bce_softc *sc)
5702 {
5703         u16 prod, prod_idx;
5704
5705         DBENTER(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5706             BCE_VERBOSE_CTX);
5707
5708         /* Get the page chain prodcuer index. */
5709         prod = sc->pg_prod;
5710
5711         /* Keep filling the page chain until it's full. */
5712         while (sc->free_pg_bd > 0) {
5713                 prod_idx = PG_CHAIN_IDX(prod);
5714                 if (bce_get_pg_buf(sc, NULL, &prod, &prod_idx)) {
5715                         /* Bail out if we can't add an mbuf to the chain. */
5716                         break;
5717                 }
5718                 prod = NEXT_PG_BD(prod);
5719         }
5720
5721         /* Save the page chain producer index. */
5722         sc->pg_prod = prod;
5723
5724         DBRUNIF(((prod & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE),
5725             BCE_PRINTF("%s(): Invalid pg_prod value: 0x%04X\n",
5726             __FUNCTION__, sc->pg_prod));
5727
5728         /*
5729          * Write the mailbox and tell the chip about
5730          * the new rx_bd's in the page chain.
5731          */
5732         REG_WR16(sc, MB_GET_CID_ADDR(RX_CID) +
5733             BCE_L2MQ_RX_HOST_PG_BDIDX, sc->pg_prod);
5734
5735         DBEXIT(BCE_VERBOSE_RESET | BCE_EXTREME_RECV | BCE_VERBOSE_LOAD |
5736             BCE_VERBOSE_CTX);
5737 }
5738
5739
5740 /****************************************************************************/
5741 /* Free memory and clear the RX data structures.                            */
5742 /*                                                                          */
5743 /* Returns:                                                                 */
5744 /*   Nothing.                                                               */
5745 /****************************************************************************/
5746 static void
5747 bce_free_pg_chain(struct bce_softc *sc)
5748 {
5749         int i;
5750
5751         DBENTER(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5752
5753         /* Free any mbufs still in the mbuf page chain. */
5754         for (i = 0; i < TOTAL_PG_BD; i++) {
5755                 if (sc->pg_mbuf_ptr[i] != NULL) {
5756                         if (sc->pg_mbuf_map[i] != NULL)
5757                                 bus_dmamap_sync(sc->pg_mbuf_tag,
5758                                     sc->pg_mbuf_map[i],
5759                                     BUS_DMASYNC_POSTREAD);
5760                         m_freem(sc->pg_mbuf_ptr[i]);
5761                         sc->pg_mbuf_ptr[i] = NULL;
5762                         DBRUN(sc->debug_pg_mbuf_alloc--);
5763                 }
5764         }
5765
5766         /* Clear each page chain pages. */
5767         for (i = 0; i < PG_PAGES; i++)
5768                 bzero((char *)sc->pg_bd_chain[i], BCE_PG_CHAIN_PAGE_SZ);
5769
5770         sc->free_pg_bd = sc->max_pg_bd;
5771
5772         /* Check if we lost any mbufs in the process. */
5773         DBRUNIF((sc->debug_pg_mbuf_alloc),
5774             BCE_PRINTF("%s(): Memory leak! Lost %d mbufs from page chain!\n",
5775             __FUNCTION__, sc->debug_pg_mbuf_alloc));
5776
5777         DBEXIT(BCE_VERBOSE_RESET | BCE_VERBOSE_RECV | BCE_VERBOSE_UNLOAD);
5778 }
5779 #endif /* BCE_JUMBO_HDRSPLIT */
5780
5781
5782 /****************************************************************************/
5783 /* Set media options.                                                       */
5784 /*                                                                          */
5785 /* Returns:                                                                 */
5786 /*   0 for success, positive value for failure.                             */
5787 /****************************************************************************/
5788 static int
5789 bce_ifmedia_upd(struct ifnet *ifp)
5790 {
5791         struct bce_softc *sc = ifp->if_softc;
5792         int error;
5793
5794         DBENTER(BCE_VERBOSE);
5795
5796         BCE_LOCK(sc);
5797         error = bce_ifmedia_upd_locked(ifp);
5798         BCE_UNLOCK(sc);
5799
5800         DBEXIT(BCE_VERBOSE);
5801         return (error);
5802 }
5803
5804
5805 /****************************************************************************/
5806 /* Set media options.                                                       */
5807 /*                                                                          */
5808 /* Returns:                                                                 */
5809 /*   Nothing.                                                               */
5810 /****************************************************************************/
5811 static int
5812 bce_ifmedia_upd_locked(struct ifnet *ifp)
5813 {
5814         struct bce_softc *sc = ifp->if_softc;
5815         struct mii_data *mii;
5816         int error;
5817
5818         DBENTER(BCE_VERBOSE_PHY);
5819
5820         error = 0;
5821         BCE_LOCK_ASSERT(sc);
5822
5823         mii = device_get_softc(sc->bce_miibus);
5824
5825         /* Make sure the MII bus has been enumerated. */
5826         if (mii) {
5827                 sc->bce_link_up = FALSE;
5828                 if (mii->mii_instance) {
5829                         struct mii_softc *miisc;
5830
5831                         LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
5832                             mii_phy_reset(miisc);
5833                 }
5834                 error = mii_mediachg(mii);
5835         }
5836
5837         DBEXIT(BCE_VERBOSE_PHY);
5838         return (error);
5839 }
5840
5841
5842 /****************************************************************************/
5843 /* Reports current media status.                                            */
5844 /*                                                                          */
5845 /* Returns:                                                                 */
5846 /*   Nothing.                                                               */
5847 /****************************************************************************/
5848 static void
5849 bce_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
5850 {
5851         struct bce_softc *sc = ifp->if_softc;
5852         struct mii_data *mii;
5853
5854         DBENTER(BCE_VERBOSE_PHY);
5855
5856         BCE_LOCK(sc);
5857
5858         if ((ifp->if_flags & IFF_UP) == 0) {
5859                 BCE_UNLOCK(sc);
5860                 return;
5861         }
5862         mii = device_get_softc(sc->bce_miibus);
5863
5864         mii_pollstat(mii);
5865         ifmr->ifm_active = mii->mii_media_active;
5866         ifmr->ifm_status = mii->mii_media_status;
5867
5868         BCE_UNLOCK(sc);
5869
5870         DBEXIT(BCE_VERBOSE_PHY);
5871 }
5872
5873
5874 /****************************************************************************/
5875 /* Handles PHY generated interrupt events.                                  */
5876 /*                                                                          */
5877 /* Returns:                                                                 */
5878 /*   Nothing.                                                               */
5879 /****************************************************************************/
5880 static void
5881 bce_phy_intr(struct bce_softc *sc)
5882 {
5883         u32 new_link_state, old_link_state;
5884
5885         DBENTER(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
5886
5887         DBRUN(sc->phy_interrupts++);
5888
5889         new_link_state = sc->status_block->status_attn_bits &
5890             STATUS_ATTN_BITS_LINK_STATE;
5891         old_link_state = sc->status_block->status_attn_bits_ack &
5892             STATUS_ATTN_BITS_LINK_STATE;
5893
5894         /* Handle any changes if the link state has changed. */
5895         if (new_link_state != old_link_state) {
5896
5897                 /* Update the status_attn_bits_ack field. */
5898                 if (new_link_state) {
5899                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_SET_CMD,
5900                             STATUS_ATTN_BITS_LINK_STATE);
5901                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now UP.\n",
5902                             __FUNCTION__);
5903                 }
5904                 else {
5905                         REG_WR(sc, BCE_PCICFG_STATUS_BIT_CLEAR_CMD,
5906                             STATUS_ATTN_BITS_LINK_STATE);
5907                         DBPRINT(sc, BCE_INFO_PHY, "%s(): Link is now DOWN.\n",
5908                             __FUNCTION__);
5909                 }
5910
5911                 /*
5912                  * Assume link is down and allow
5913                  * tick routine to update the state
5914                  * based on the actual media state.
5915                  */
5916                 sc->bce_link_up = FALSE;
5917                 callout_stop(&sc->bce_tick_callout);
5918                 bce_tick(sc);
5919         }
5920
5921         /* Acknowledge the link change interrupt. */
5922         REG_WR(sc, BCE_EMAC_STATUS, BCE_EMAC_STATUS_LINK_CHANGE);
5923
5924         DBEXIT(BCE_VERBOSE_PHY | BCE_VERBOSE_INTR);
5925 }
5926
5927
5928 /****************************************************************************/
5929 /* Reads the receive consumer value from the status block (skipping over    */
5930 /* chain page pointer if necessary).                                        */
5931 /*                                                                          */
5932 /* Returns:                                                                 */
5933 /*   hw_cons                                                                */
5934 /****************************************************************************/
5935 static inline u16
5936 bce_get_hw_rx_cons(struct bce_softc *sc)
5937 {
5938         u16 hw_cons;
5939
5940         rmb();
5941         hw_cons = sc->status_block->status_rx_quick_consumer_index0;
5942         if ((hw_cons & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
5943                 hw_cons++;
5944
5945         return hw_cons;
5946 }
5947
5948 /****************************************************************************/
5949 /* Handles received frame interrupt events.                                 */
5950 /*                                                                          */
5951 /* Returns:                                                                 */
5952 /*   Nothing.                                                               */
5953 /****************************************************************************/
5954 static void
5955 bce_rx_intr(struct bce_softc *sc)
5956 {
5957         struct ifnet *ifp = sc->bce_ifp;
5958         struct l2_fhdr *l2fhdr;
5959         struct ether_vlan_header *vh;
5960         unsigned int pkt_len;
5961         u16 sw_rx_cons, sw_rx_cons_idx, hw_rx_cons;
5962         u32 status;
5963 #ifdef BCE_JUMBO_HDRSPLIT
5964         unsigned int rem_len;
5965         u16 sw_pg_cons, sw_pg_cons_idx;
5966 #endif
5967
5968         DBENTER(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
5969         DBRUN(sc->interrupts_rx++);
5970         DBPRINT(sc, BCE_EXTREME_RECV, "%s(enter): rx_prod = 0x%04X, "
5971             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
5972             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
5973
5974         /* Prepare the RX chain pages to be accessed by the host CPU. */
5975         for (int i = 0; i < RX_PAGES; i++)
5976                 bus_dmamap_sync(sc->rx_bd_chain_tag,
5977                     sc->rx_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
5978
5979 #ifdef BCE_JUMBO_HDRSPLIT
5980         /* Prepare the page chain pages to be accessed by the host CPU. */
5981         for (int i = 0; i < PG_PAGES; i++)
5982                 bus_dmamap_sync(sc->pg_bd_chain_tag,
5983                     sc->pg_bd_chain_map[i], BUS_DMASYNC_POSTREAD);
5984 #endif
5985
5986         /* Get the hardware's view of the RX consumer index. */
5987         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
5988
5989         /* Get working copies of the driver's view of the consumer indices. */
5990         sw_rx_cons = sc->rx_cons;
5991
5992 #ifdef BCE_JUMBO_HDRSPLIT
5993         sw_pg_cons = sc->pg_cons;
5994 #endif
5995
5996         /* Update some debug statistics counters */
5997         DBRUNIF((sc->free_rx_bd < sc->rx_low_watermark),
5998             sc->rx_low_watermark = sc->free_rx_bd);
5999         DBRUNIF((sc->free_rx_bd == sc->max_rx_bd),
6000             sc->rx_empty_count++);
6001
6002         /* Scan through the receive chain as long as there is work to do */
6003         /* ToDo: Consider setting a limit on the number of packets processed. */
6004         rmb();
6005         while (sw_rx_cons != hw_rx_cons) {
6006                 struct mbuf *m0;
6007
6008                 /* Convert the producer/consumer indices to an actual rx_bd index. */
6009                 sw_rx_cons_idx = RX_CHAIN_IDX(sw_rx_cons);
6010
6011                 /* Unmap the mbuf from DMA space. */
6012                 bus_dmamap_sync(sc->rx_mbuf_tag,
6013                     sc->rx_mbuf_map[sw_rx_cons_idx],
6014                     BUS_DMASYNC_POSTREAD);
6015                 bus_dmamap_unload(sc->rx_mbuf_tag,
6016                     sc->rx_mbuf_map[sw_rx_cons_idx]);
6017
6018                 /* Remove the mbuf from the RX chain. */
6019                 m0 = sc->rx_mbuf_ptr[sw_rx_cons_idx];
6020                 sc->rx_mbuf_ptr[sw_rx_cons_idx] = NULL;
6021                 DBRUN(sc->debug_rx_mbuf_alloc--);
6022                 sc->free_rx_bd++;
6023
6024                 if(m0 == NULL) {
6025                         DBPRINT(sc, BCE_EXTREME_RECV,
6026                             "%s(): Oops! Empty mbuf pointer "
6027                             "found in sc->rx_mbuf_ptr[0x%04X]!\n",
6028                             __FUNCTION__, sw_rx_cons_idx);
6029                         goto bce_rx_int_next_rx;
6030                 }
6031
6032                 /*
6033                  * Frames received on the NetXteme II are prepended
6034                  * with an l2_fhdr structure which provides status
6035                  * information about the received frame (including
6036                  * VLAN tags and checksum info).  The frames are
6037                  * also automatically adjusted to align the IP
6038                  * header (i.e. two null bytes are inserted before
6039                  * the Ethernet header).  As a result the data
6040                  * DMA'd by the controller into the mbuf looks
6041                  * like this:
6042                  *
6043                  * +---------+-----+---------------------+-----+
6044                  * | l2_fhdr | pad | packet data         | FCS |
6045                  * +---------+-----+---------------------+-----+
6046                  *
6047                  * The l2_fhdr needs to be checked and skipped and
6048                  * the FCS needs to be stripped before sending the
6049                  * packet up the stack.
6050                  */
6051                 l2fhdr  = mtod(m0, struct l2_fhdr *);
6052
6053                 /* Get the packet data + FCS length and the status. */
6054                 pkt_len = l2fhdr->l2_fhdr_pkt_len;
6055                 status  = l2fhdr->l2_fhdr_status;
6056
6057                 /*
6058                  * Skip over the l2_fhdr and pad, resulting in the
6059                  * following data in the mbuf:
6060                  * +---------------------+-----+
6061                  * | packet data         | FCS |
6062                  * +---------------------+-----+
6063                  */
6064                 m_adj(m0, sizeof(struct l2_fhdr) + ETHER_ALIGN);
6065
6066 #ifdef BCE_JUMBO_HDRSPLIT
6067                 /*
6068                  * Check whether the received frame fits in a single
6069                  * mbuf or not (i.e. packet data + FCS <=
6070                  * sc->rx_bd_mbuf_data_len bytes).
6071                  */
6072                 if (pkt_len > m0->m_len) {
6073                         /*
6074                          * The received frame is larger than a single mbuf.
6075                          * If the frame was a TCP frame then only the TCP
6076                          * header is placed in the mbuf, the remaining
6077                          * payload (including FCS) is placed in the page
6078                          * chain, the SPLIT flag is set, and the header
6079                          * length is placed in the IP checksum field.
6080                          * If the frame is not a TCP frame then the mbuf
6081                          * is filled and the remaining bytes are placed
6082                          * in the page chain.
6083                          */
6084
6085                         DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a large "
6086                             "packet.\n", __FUNCTION__);
6087
6088                         /*
6089                          * When the page chain is enabled and the TCP
6090                          * header has been split from the TCP payload,
6091                          * the ip_xsum structure will reflect the length
6092                          * of the TCP header, not the IP checksum.  Set
6093                          * the packet length of the mbuf accordingly.
6094                          */
6095                         if (status & L2_FHDR_STATUS_SPLIT)
6096                                 m0->m_len = l2fhdr->l2_fhdr_ip_xsum;
6097
6098                         rem_len = pkt_len - m0->m_len;
6099
6100                         /* Pull mbufs off the page chain for the remaining data. */
6101                         while (rem_len > 0) {
6102                                 struct mbuf *m_pg;
6103
6104                                 sw_pg_cons_idx = PG_CHAIN_IDX(sw_pg_cons);
6105
6106                                 /* Remove the mbuf from the page chain. */
6107                                 m_pg = sc->pg_mbuf_ptr[sw_pg_cons_idx];
6108                                 sc->pg_mbuf_ptr[sw_pg_cons_idx] = NULL;
6109                                 DBRUN(sc->debug_pg_mbuf_alloc--);
6110                                 sc->free_pg_bd++;
6111
6112                                 /* Unmap the page chain mbuf from DMA space. */
6113                                 bus_dmamap_sync(sc->pg_mbuf_tag,
6114                                     sc->pg_mbuf_map[sw_pg_cons_idx],
6115                                     BUS_DMASYNC_POSTREAD);
6116                                 bus_dmamap_unload(sc->pg_mbuf_tag,
6117                                     sc->pg_mbuf_map[sw_pg_cons_idx]);
6118
6119                                 /* Adjust the mbuf length. */
6120                                 if (rem_len < m_pg->m_len) {
6121                                         /* The mbuf chain is complete. */
6122                                         m_pg->m_len = rem_len;
6123                                         rem_len = 0;
6124                                 } else {
6125                                         /* More packet data is waiting. */
6126                                         rem_len -= m_pg->m_len;
6127                                 }
6128
6129                                 /* Concatenate the mbuf cluster to the mbuf. */
6130                                 m_cat(m0, m_pg);
6131
6132                                 sw_pg_cons = NEXT_PG_BD(sw_pg_cons);
6133                         }
6134
6135                         /* Set the total packet length. */
6136                         m0->m_pkthdr.len = pkt_len;
6137
6138                 } else {
6139                         /*
6140                          * The received packet is small and fits in a
6141                          * single mbuf (i.e. the l2_fhdr + pad + packet +
6142                          * FCS <= MHLEN).  In other words, the packet is
6143                          * 154 bytes or less in size.
6144                          */
6145
6146                         DBPRINT(sc, BCE_INFO_RECV, "%s(): Found a small "
6147                             "packet.\n", __FUNCTION__);
6148
6149                         /* Set the total packet length. */
6150                         m0->m_pkthdr.len = m0->m_len = pkt_len;
6151                 }
6152 #else
6153                 /* Set the total packet length. */
6154                 m0->m_pkthdr.len = m0->m_len = pkt_len;
6155 #endif
6156
6157                 /* Remove the trailing Ethernet FCS. */
6158                 m_adj(m0, -ETHER_CRC_LEN);
6159
6160                 /* Check that the resulting mbuf chain is valid. */
6161                 DBRUN(m_sanity(m0, FALSE));
6162                 DBRUNIF(((m0->m_len < ETHER_HDR_LEN) |
6163                     (m0->m_pkthdr.len > BCE_MAX_JUMBO_ETHER_MTU_VLAN)),
6164                      BCE_PRINTF("Invalid Ethernet frame size!\n");
6165                      m_print(m0, 128));
6166
6167                 DBRUNIF(DB_RANDOMTRUE(l2fhdr_error_sim_control),
6168                     sc->l2fhdr_error_sim_count++;
6169                     status = status | L2_FHDR_ERRORS_PHY_DECODE);
6170
6171                 /* Check the received frame for errors. */
6172                 if (status & (L2_FHDR_ERRORS_BAD_CRC |
6173                     L2_FHDR_ERRORS_PHY_DECODE | L2_FHDR_ERRORS_ALIGNMENT |
6174                     L2_FHDR_ERRORS_TOO_SHORT  | L2_FHDR_ERRORS_GIANT_FRAME)) {
6175
6176                         /* Log the error and release the mbuf. */
6177                         ifp->if_ierrors++;
6178                         sc->l2fhdr_error_count++;
6179
6180                         m_freem(m0);
6181                         m0 = NULL;
6182                         goto bce_rx_int_next_rx;
6183                 }
6184
6185                 /* Send the packet to the appropriate interface. */
6186                 m0->m_pkthdr.rcvif = ifp;
6187
6188                 /* Assume no hardware checksum. */
6189                 m0->m_pkthdr.csum_flags = 0;
6190
6191                 /* Validate the checksum if offload enabled. */
6192                 if (ifp->if_capenable & IFCAP_RXCSUM) {
6193
6194                         /* Check for an IP datagram. */
6195                         if (!(status & L2_FHDR_STATUS_SPLIT) &&
6196                             (status & L2_FHDR_STATUS_IP_DATAGRAM)) {
6197                                 m0->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
6198                                 DBRUN(sc->csum_offload_ip++);
6199                                 /* Check if the IP checksum is valid. */
6200                                 if ((l2fhdr->l2_fhdr_ip_xsum ^ 0xffff) == 0)
6201                                         m0->m_pkthdr.csum_flags |=
6202                                             CSUM_IP_VALID;
6203                         }
6204
6205                         /* Check for a valid TCP/UDP frame. */
6206                         if (status & (L2_FHDR_STATUS_TCP_SEGMENT |
6207                             L2_FHDR_STATUS_UDP_DATAGRAM)) {
6208
6209                                 /* Check for a good TCP/UDP checksum. */
6210                                 if ((status & (L2_FHDR_ERRORS_TCP_XSUM |
6211                                     L2_FHDR_ERRORS_UDP_XSUM)) == 0) {
6212                                         DBRUN(sc->csum_offload_tcp_udp++);
6213                                         m0->m_pkthdr.csum_data =
6214                                             l2fhdr->l2_fhdr_tcp_udp_xsum;
6215                                         m0->m_pkthdr.csum_flags |=
6216                                             (CSUM_DATA_VALID
6217                                             | CSUM_PSEUDO_HDR);
6218                                 }
6219                         }
6220                 }
6221
6222                 /* Attach the VLAN tag. */
6223                 if (status & L2_FHDR_STATUS_L2_VLAN_TAG) {
6224                         if (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) {
6225 #if __FreeBSD_version < 700000
6226                                 VLAN_INPUT_TAG(ifp, m0,
6227                                     l2fhdr->l2_fhdr_vlan_tag, continue);
6228 #else
6229                                 m0->m_pkthdr.ether_vtag =
6230                                     l2fhdr->l2_fhdr_vlan_tag;
6231                                 m0->m_flags |= M_VLANTAG;
6232 #endif
6233                         } else {
6234                                 /*
6235                                  * bce(4) controllers can't disable VLAN
6236                                  * tag stripping if management firmware
6237                                  * (ASF/IPMI/UMP) is running. So we always
6238                                  * strip VLAN tag and manually reconstruct
6239                                  * the VLAN frame by appending stripped
6240                                  * VLAN tag in driver if VLAN tag stripping
6241                                  * was disabled.
6242                                  *
6243                                  * TODO: LLC SNAP handling.
6244                                  */
6245                                 bcopy(mtod(m0, uint8_t *),
6246                                     mtod(m0, uint8_t *) - ETHER_VLAN_ENCAP_LEN,
6247                                     ETHER_ADDR_LEN * 2);
6248                                 m0->m_data -= ETHER_VLAN_ENCAP_LEN;
6249                                 vh = mtod(m0, struct ether_vlan_header *);
6250                                 vh->evl_encap_proto = htons(ETHERTYPE_VLAN);
6251                                 vh->evl_tag = htons(l2fhdr->l2_fhdr_vlan_tag);
6252                                 m0->m_pkthdr.len += ETHER_VLAN_ENCAP_LEN;
6253                                 m0->m_len += ETHER_VLAN_ENCAP_LEN;
6254                         }
6255                 }
6256
6257                 /* Increment received packet statistics. */
6258                 ifp->if_ipackets++;
6259
6260 bce_rx_int_next_rx:
6261                 sw_rx_cons = NEXT_RX_BD(sw_rx_cons);
6262
6263                 /* If we have a packet, pass it up the stack */
6264                 if (m0) {
6265                         /* Make sure we don't lose our place when we release the lock. */
6266                         sc->rx_cons = sw_rx_cons;
6267 #ifdef BCE_JUMBO_HDRSPLIT
6268                         sc->pg_cons = sw_pg_cons;
6269 #endif
6270
6271                         BCE_UNLOCK(sc);
6272                         (*ifp->if_input)(ifp, m0);
6273                         BCE_LOCK(sc);
6274
6275                         /* Recover our place. */
6276                         sw_rx_cons = sc->rx_cons;
6277 #ifdef BCE_JUMBO_HDRSPLIT
6278                         sw_pg_cons = sc->pg_cons;
6279 #endif
6280                 }
6281
6282                 /* Refresh hw_cons to see if there's new work */
6283                 if (sw_rx_cons == hw_rx_cons)
6284                         hw_rx_cons = sc->hw_rx_cons = bce_get_hw_rx_cons(sc);
6285         }
6286
6287 #ifdef BCE_JUMBO_HDRSPLIT
6288         /* No new packets.  Refill the page chain. */
6289         sc->pg_cons = sw_pg_cons;
6290         bce_fill_pg_chain(sc);
6291 #endif
6292
6293         /* No new packets.  Refill the RX chain. */
6294         sc->rx_cons = sw_rx_cons;
6295         bce_fill_rx_chain(sc);
6296
6297         /* Prepare the page chain pages to be accessed by the NIC. */
6298         for (int i = 0; i < RX_PAGES; i++)
6299                 bus_dmamap_sync(sc->rx_bd_chain_tag,
6300                     sc->rx_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6301
6302 #ifdef BCE_JUMBO_HDRSPLIT
6303         for (int i = 0; i < PG_PAGES; i++)
6304                 bus_dmamap_sync(sc->pg_bd_chain_tag,
6305                     sc->pg_bd_chain_map[i], BUS_DMASYNC_PREWRITE);
6306 #endif
6307
6308         DBPRINT(sc, BCE_EXTREME_RECV, "%s(exit): rx_prod = 0x%04X, "
6309             "rx_cons = 0x%04X, rx_prod_bseq = 0x%08X\n",
6310             __FUNCTION__, sc->rx_prod, sc->rx_cons, sc->rx_prod_bseq);
6311         DBEXIT(BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
6312 }
6313
6314
6315 /****************************************************************************/
6316 /* Reads the transmit consumer value from the status block (skipping over   */
6317 /* chain page pointer if necessary).                                        */
6318 /*                                                                          */
6319 /* Returns:                                                                 */
6320 /*   hw_cons                                                                */
6321 /****************************************************************************/
6322 static inline u16
6323 bce_get_hw_tx_cons(struct bce_softc *sc)
6324 {
6325         u16 hw_cons;
6326
6327         mb();
6328         hw_cons = sc->status_block->status_tx_quick_consumer_index0;
6329         if ((hw_cons & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
6330                 hw_cons++;
6331
6332         return hw_cons;
6333 }
6334
6335
6336 /****************************************************************************/
6337 /* Handles transmit completion interrupt events.                            */
6338 /*                                                                          */
6339 /* Returns:                                                                 */
6340 /*   Nothing.                                                               */
6341 /****************************************************************************/
6342 static void
6343 bce_tx_intr(struct bce_softc *sc)
6344 {
6345         struct ifnet *ifp = sc->bce_ifp;
6346         u16 hw_tx_cons, sw_tx_cons, sw_tx_chain_cons;
6347
6348         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6349         DBRUN(sc->interrupts_tx++);
6350         DBPRINT(sc, BCE_EXTREME_SEND, "%s(enter): tx_prod = 0x%04X, "
6351             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6352             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6353
6354         BCE_LOCK_ASSERT(sc);
6355
6356         /* Get the hardware's view of the TX consumer index. */
6357         hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6358         sw_tx_cons = sc->tx_cons;
6359
6360         /* Prevent speculative reads of the status block. */
6361         bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6362             BUS_SPACE_BARRIER_READ);
6363
6364         /* Cycle through any completed TX chain page entries. */
6365         while (sw_tx_cons != hw_tx_cons) {
6366 #ifdef BCE_DEBUG
6367                 struct tx_bd *txbd = NULL;
6368 #endif
6369                 sw_tx_chain_cons = TX_CHAIN_IDX(sw_tx_cons);
6370
6371                 DBPRINT(sc, BCE_INFO_SEND,
6372                     "%s(): hw_tx_cons = 0x%04X, sw_tx_cons = 0x%04X, "
6373                     "sw_tx_chain_cons = 0x%04X\n",
6374                     __FUNCTION__, hw_tx_cons, sw_tx_cons, sw_tx_chain_cons);
6375
6376                 DBRUNIF((sw_tx_chain_cons > MAX_TX_BD),
6377                     BCE_PRINTF("%s(%d): TX chain consumer out of range! "
6378                     " 0x%04X > 0x%04X\n", __FILE__, __LINE__, sw_tx_chain_cons,
6379                     (int) MAX_TX_BD);
6380                     bce_breakpoint(sc));
6381
6382                 DBRUN(txbd = &sc->tx_bd_chain[TX_PAGE(sw_tx_chain_cons)]
6383                     [TX_IDX(sw_tx_chain_cons)]);
6384
6385                 DBRUNIF((txbd == NULL),
6386                     BCE_PRINTF("%s(%d): Unexpected NULL tx_bd[0x%04X]!\n",
6387                     __FILE__, __LINE__, sw_tx_chain_cons);
6388                     bce_breakpoint(sc));
6389
6390                 DBRUNMSG(BCE_INFO_SEND, BCE_PRINTF("%s(): ", __FUNCTION__);
6391                     bce_dump_txbd(sc, sw_tx_chain_cons, txbd));
6392
6393                 /*
6394                  * Free the associated mbuf. Remember
6395                  * that only the last tx_bd of a packet
6396                  * has an mbuf pointer and DMA map.
6397                  */
6398                 if (sc->tx_mbuf_ptr[sw_tx_chain_cons] != NULL) {
6399
6400                         /* Validate that this is the last tx_bd. */
6401                         DBRUNIF((!(txbd->tx_bd_flags & TX_BD_FLAGS_END)),
6402                             BCE_PRINTF("%s(%d): tx_bd END flag not set but "
6403                             "txmbuf == NULL!\n", __FILE__, __LINE__);
6404                             bce_breakpoint(sc));
6405
6406                         DBRUNMSG(BCE_INFO_SEND,
6407                             BCE_PRINTF("%s(): Unloading map/freeing mbuf "
6408                             "from tx_bd[0x%04X]\n", __FUNCTION__,
6409                             sw_tx_chain_cons));
6410
6411                         /* Unmap the mbuf. */
6412                         bus_dmamap_unload(sc->tx_mbuf_tag,
6413                             sc->tx_mbuf_map[sw_tx_chain_cons]);
6414
6415                         /* Free the mbuf. */
6416                         m_freem(sc->tx_mbuf_ptr[sw_tx_chain_cons]);
6417                         sc->tx_mbuf_ptr[sw_tx_chain_cons] = NULL;
6418                         DBRUN(sc->debug_tx_mbuf_alloc--);
6419
6420                         ifp->if_opackets++;
6421                 }
6422
6423                 sc->used_tx_bd--;
6424                 sw_tx_cons = NEXT_TX_BD(sw_tx_cons);
6425
6426                 /* Refresh hw_cons to see if there's new work. */
6427                 hw_tx_cons = sc->hw_tx_cons = bce_get_hw_tx_cons(sc);
6428
6429                 /* Prevent speculative reads of the status block. */
6430                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
6431                     BUS_SPACE_BARRIER_READ);
6432         }
6433
6434         /* Clear the TX timeout timer. */
6435         sc->watchdog_timer = 0;
6436
6437         /* Clear the tx hardware queue full flag. */
6438         if (sc->used_tx_bd < sc->max_tx_bd) {
6439                 DBRUNIF((ifp->if_drv_flags & IFF_DRV_OACTIVE),
6440                     DBPRINT(sc, BCE_INFO_SEND,
6441                     "%s(): Open TX chain! %d/%d (used/total)\n",
6442                     __FUNCTION__, sc->used_tx_bd, sc->max_tx_bd));
6443                 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
6444         }
6445
6446         sc->tx_cons = sw_tx_cons;
6447
6448         DBPRINT(sc, BCE_EXTREME_SEND, "%s(exit): tx_prod = 0x%04X, "
6449             "tx_cons = 0x%04X, tx_prod_bseq = 0x%08X\n",
6450             __FUNCTION__, sc->tx_prod, sc->tx_cons, sc->tx_prod_bseq);
6451         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_INTR);
6452 }
6453
6454
6455 /****************************************************************************/
6456 /* Disables interrupt generation.                                           */
6457 /*                                                                          */
6458 /* Returns:                                                                 */
6459 /*   Nothing.                                                               */
6460 /****************************************************************************/
6461 static void
6462 bce_disable_intr(struct bce_softc *sc)
6463 {
6464         DBENTER(BCE_VERBOSE_INTR);
6465
6466         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD, BCE_PCICFG_INT_ACK_CMD_MASK_INT);
6467         REG_RD(sc, BCE_PCICFG_INT_ACK_CMD);
6468
6469         DBEXIT(BCE_VERBOSE_INTR);
6470 }
6471
6472
6473 /****************************************************************************/
6474 /* Enables interrupt generation.                                            */
6475 /*                                                                          */
6476 /* Returns:                                                                 */
6477 /*   Nothing.                                                               */
6478 /****************************************************************************/
6479 static void
6480 bce_enable_intr(struct bce_softc *sc, int coal_now)
6481 {
6482         DBENTER(BCE_VERBOSE_INTR);
6483
6484         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
6485             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID |
6486             BCE_PCICFG_INT_ACK_CMD_MASK_INT | sc->last_status_idx);
6487
6488         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
6489             BCE_PCICFG_INT_ACK_CMD_INDEX_VALID | sc->last_status_idx);
6490
6491         /* Force an immediate interrupt (whether there is new data or not). */
6492         if (coal_now)
6493                 REG_WR(sc, BCE_HC_COMMAND, sc->hc_command | BCE_HC_COMMAND_COAL_NOW);
6494
6495         DBEXIT(BCE_VERBOSE_INTR);
6496 }
6497
6498
6499 /****************************************************************************/
6500 /* Handles controller initialization.                                       */
6501 /*                                                                          */
6502 /* Returns:                                                                 */
6503 /*   Nothing.                                                               */
6504 /****************************************************************************/
6505 static void
6506 bce_init_locked(struct bce_softc *sc)
6507 {
6508         struct ifnet *ifp;
6509         u32 ether_mtu = 0;
6510
6511         DBENTER(BCE_VERBOSE_RESET);
6512
6513         BCE_LOCK_ASSERT(sc);
6514
6515         ifp = sc->bce_ifp;
6516
6517         /* Check if the driver is still running and bail out if it is. */
6518         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
6519                 goto bce_init_locked_exit;
6520
6521         bce_stop(sc);
6522
6523         if (bce_reset(sc, BCE_DRV_MSG_CODE_RESET)) {
6524                 BCE_PRINTF("%s(%d): Controller reset failed!\n",
6525                     __FILE__, __LINE__);
6526                 goto bce_init_locked_exit;
6527         }
6528
6529         if (bce_chipinit(sc)) {
6530                 BCE_PRINTF("%s(%d): Controller initialization failed!\n",
6531                     __FILE__, __LINE__);
6532                 goto bce_init_locked_exit;
6533         }
6534
6535         if (bce_blockinit(sc)) {
6536                 BCE_PRINTF("%s(%d): Block initialization failed!\n",
6537                     __FILE__, __LINE__);
6538                 goto bce_init_locked_exit;
6539         }
6540
6541         /* Load our MAC address. */
6542         bcopy(IF_LLADDR(sc->bce_ifp), sc->eaddr, ETHER_ADDR_LEN);
6543         bce_set_mac_addr(sc);
6544
6545         /*
6546          * Calculate and program the hardware Ethernet MTU
6547          * size. Be generous on the receive if we have room.
6548          */
6549 #ifdef BCE_JUMBO_HDRSPLIT
6550         if (ifp->if_mtu <= (sc->rx_bd_mbuf_data_len +
6551             sc->pg_bd_mbuf_alloc_size))
6552                 ether_mtu = sc->rx_bd_mbuf_data_len +
6553                     sc->pg_bd_mbuf_alloc_size;
6554 #else
6555         if (ifp->if_mtu <= sc->rx_bd_mbuf_data_len)
6556                 ether_mtu = sc->rx_bd_mbuf_data_len;
6557 #endif
6558         else
6559                 ether_mtu = ifp->if_mtu;
6560
6561         ether_mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN;
6562
6563         DBPRINT(sc, BCE_INFO_MISC, "%s(): setting h/w mtu = %d\n",
6564             __FUNCTION__, ether_mtu);
6565
6566         /* Program the mtu, enabling jumbo frame support if necessary. */
6567         if (ether_mtu > (ETHER_MAX_LEN + ETHER_VLAN_ENCAP_LEN))
6568                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE,
6569                     min(ether_mtu, BCE_MAX_JUMBO_ETHER_MTU) |
6570                     BCE_EMAC_RX_MTU_SIZE_JUMBO_ENA);
6571         else
6572                 REG_WR(sc, BCE_EMAC_RX_MTU_SIZE, ether_mtu);
6573
6574         DBPRINT(sc, BCE_INFO_LOAD,
6575             "%s(): rx_bd_mbuf_alloc_size = %d, rx_bce_mbuf_data_len = %d, "
6576             "rx_bd_mbuf_align_pad = %d\n", __FUNCTION__,
6577             sc->rx_bd_mbuf_alloc_size, sc->rx_bd_mbuf_data_len,
6578             sc->rx_bd_mbuf_align_pad);
6579
6580         /* Program appropriate promiscuous/multicast filtering. */
6581         bce_set_rx_mode(sc);
6582
6583 #ifdef BCE_JUMBO_HDRSPLIT
6584         DBPRINT(sc, BCE_INFO_LOAD, "%s(): pg_bd_mbuf_alloc_size = %d\n",
6585             __FUNCTION__, sc->pg_bd_mbuf_alloc_size);
6586
6587         /* Init page buffer descriptor chain. */
6588         bce_init_pg_chain(sc);
6589 #endif
6590
6591         /* Init RX buffer descriptor chain. */
6592         bce_init_rx_chain(sc);
6593
6594         /* Init TX buffer descriptor chain. */
6595         bce_init_tx_chain(sc);
6596
6597         /* Enable host interrupts. */
6598         bce_enable_intr(sc, 1);
6599
6600         bce_ifmedia_upd_locked(ifp);
6601
6602         /* Let the OS know the driver is up and running. */
6603         ifp->if_drv_flags |= IFF_DRV_RUNNING;
6604         ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
6605
6606         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
6607
6608 bce_init_locked_exit:
6609         DBEXIT(BCE_VERBOSE_RESET);
6610 }
6611
6612
6613 /****************************************************************************/
6614 /* Initialize the controller just enough so that any management firmware    */
6615 /* running on the device will continue to operate correctly.                */
6616 /*                                                                          */
6617 /* Returns:                                                                 */
6618 /*   Nothing.                                                               */
6619 /****************************************************************************/
6620 static void
6621 bce_mgmt_init_locked(struct bce_softc *sc)
6622 {
6623         struct ifnet *ifp;
6624
6625         DBENTER(BCE_VERBOSE_RESET);
6626
6627         BCE_LOCK_ASSERT(sc);
6628
6629         /* Bail out if management firmware is not running. */
6630         if (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)) {
6631                 DBPRINT(sc, BCE_VERBOSE_SPECIAL,
6632                     "No management firmware running...\n");
6633                 goto bce_mgmt_init_locked_exit;
6634         }
6635
6636         ifp = sc->bce_ifp;
6637
6638         /* Enable all critical blocks in the MAC. */
6639         REG_WR(sc, BCE_MISC_ENABLE_SET_BITS, BCE_MISC_ENABLE_DEFAULT);
6640         REG_RD(sc, BCE_MISC_ENABLE_SET_BITS);
6641         DELAY(20);
6642
6643         bce_ifmedia_upd_locked(ifp);
6644
6645 bce_mgmt_init_locked_exit:
6646         DBEXIT(BCE_VERBOSE_RESET);
6647 }
6648
6649
6650 /****************************************************************************/
6651 /* Handles controller initialization when called from an unlocked routine.  */
6652 /*                                                                          */
6653 /* Returns:                                                                 */
6654 /*   Nothing.                                                               */
6655 /****************************************************************************/
6656 static void
6657 bce_init(void *xsc)
6658 {
6659         struct bce_softc *sc = xsc;
6660
6661         DBENTER(BCE_VERBOSE_RESET);
6662
6663         BCE_LOCK(sc);
6664         bce_init_locked(sc);
6665         BCE_UNLOCK(sc);
6666
6667         DBEXIT(BCE_VERBOSE_RESET);
6668 }
6669
6670
6671 /****************************************************************************/
6672 /* Modifies an mbuf for TSO on the hardware.                                */
6673 /*                                                                          */
6674 /* Returns:                                                                 */
6675 /*   Pointer to a modified mbuf.                                            */
6676 /****************************************************************************/
6677 static struct mbuf *
6678 bce_tso_setup(struct bce_softc *sc, struct mbuf **m_head, u16 *flags)
6679 {
6680         struct mbuf *m;
6681         struct ether_header *eh;
6682         struct ip *ip;
6683         struct tcphdr *th;
6684         u16 etype;
6685         int hdr_len, ip_hlen = 0, tcp_hlen = 0, ip_len = 0;
6686
6687         DBRUN(sc->tso_frames_requested++);
6688
6689         /* Controller may modify mbuf chains. */
6690         if (M_WRITABLE(*m_head) == 0) {
6691                 m = m_dup(*m_head, M_DONTWAIT);
6692                 m_freem(*m_head);
6693                 if (m == NULL) {
6694                         sc->mbuf_alloc_failed_count++;
6695                         *m_head = NULL;
6696                         return (NULL);
6697                 }
6698                 *m_head = m;
6699         }
6700
6701         /*
6702          * For TSO the controller needs two pieces of info,
6703          * the MSS and the IP+TCP options length.
6704          */
6705         m = m_pullup(*m_head, sizeof(struct ether_header) + sizeof(struct ip));
6706         if (m == NULL) {
6707                 *m_head = NULL;
6708                 return (NULL);
6709         }
6710         eh = mtod(m, struct ether_header *);
6711         etype = ntohs(eh->ether_type);
6712
6713         /* Check for supported TSO Ethernet types (only IPv4 for now) */
6714         switch (etype) {
6715         case ETHERTYPE_IP:
6716                 ip = (struct ip *)(m->m_data + sizeof(struct ether_header));
6717                 /* TSO only supported for TCP protocol. */
6718                 if (ip->ip_p != IPPROTO_TCP) {
6719                         BCE_PRINTF("%s(%d): TSO enabled for non-TCP frame!.\n",
6720                             __FILE__, __LINE__);
6721                         m_freem(*m_head);
6722                         *m_head = NULL;
6723                         return (NULL);
6724                 }
6725
6726                 /* Get IP header length in bytes (min 20) */
6727                 ip_hlen = ip->ip_hl << 2;
6728                 m = m_pullup(*m_head, sizeof(struct ether_header) + ip_hlen +
6729                     sizeof(struct tcphdr));
6730                 if (m == NULL) {
6731                         *m_head = NULL;
6732                         return (NULL);
6733                 }
6734
6735                 /* Get the TCP header length in bytes (min 20) */
6736                 th = (struct tcphdr *)((caddr_t)ip + ip_hlen);
6737                 tcp_hlen = (th->th_off << 2);
6738
6739                 /* Make sure all IP/TCP options live in the same buffer. */
6740                 m = m_pullup(*m_head,  sizeof(struct ether_header)+ ip_hlen +
6741                     tcp_hlen);
6742                 if (m == NULL) {
6743                         *m_head = NULL;
6744                         return (NULL);
6745                 }
6746
6747                 /* IP header length and checksum will be calc'd by hardware */
6748                 ip_len = ip->ip_len;
6749                 ip->ip_len = 0;
6750                 ip->ip_sum = 0;
6751                 break;
6752         case ETHERTYPE_IPV6:
6753                 BCE_PRINTF("%s(%d): TSO over IPv6 not supported!.\n",
6754                     __FILE__, __LINE__);
6755                 m_freem(*m_head);
6756                 *m_head = NULL;
6757                 return (NULL);
6758                 /* NOT REACHED */
6759         default:
6760                 BCE_PRINTF("%s(%d): TSO enabled for unsupported protocol!.\n",
6761                     __FILE__, __LINE__);
6762                 m_freem(*m_head);
6763                 *m_head = NULL;
6764                 return (NULL);
6765         }
6766
6767         hdr_len = sizeof(struct ether_header) + ip_hlen + tcp_hlen;
6768
6769         DBPRINT(sc, BCE_EXTREME_SEND, "%s(): hdr_len = %d, e_hlen = %d, "
6770             "ip_hlen = %d, tcp_hlen = %d, ip_len = %d\n",
6771             __FUNCTION__, hdr_len, (int) sizeof(struct ether_header), ip_hlen,
6772             tcp_hlen, ip_len);
6773
6774         /* Set the LSO flag in the TX BD */
6775         *flags |= TX_BD_FLAGS_SW_LSO;
6776
6777         /* Set the length of IP + TCP options (in 32 bit words) */
6778         *flags |= (((ip_hlen + tcp_hlen - sizeof(struct ip) -
6779             sizeof(struct tcphdr)) >> 2) << 8);
6780
6781         DBRUN(sc->tso_frames_completed++);
6782         return (*m_head);
6783 }
6784
6785
6786 /****************************************************************************/
6787 /* Encapsultes an mbuf cluster into the tx_bd chain structure and makes the */
6788 /* memory visible to the controller.                                        */
6789 /*                                                                          */
6790 /* Returns:                                                                 */
6791 /*   0 for success, positive value for failure.                             */
6792 /* Modified:                                                                */
6793 /*   m_head: May be set to NULL if MBUF is excessively fragmented.          */
6794 /****************************************************************************/
6795 static int
6796 bce_tx_encap(struct bce_softc *sc, struct mbuf **m_head)
6797 {
6798         bus_dma_segment_t segs[BCE_MAX_SEGMENTS];
6799         bus_dmamap_t map;
6800         struct tx_bd *txbd = NULL;
6801         struct mbuf *m0;
6802         u16 prod, chain_prod, mss = 0, vlan_tag = 0, flags = 0;
6803         u32 prod_bseq;
6804
6805 #ifdef BCE_DEBUG
6806         u16 debug_prod;
6807 #endif
6808
6809         int i, error, nsegs, rc = 0;
6810
6811         DBENTER(BCE_VERBOSE_SEND);
6812
6813         /* Make sure we have room in the TX chain. */
6814         if (sc->used_tx_bd >= sc->max_tx_bd)
6815                 goto bce_tx_encap_exit;
6816
6817         /* Transfer any checksum offload flags to the bd. */
6818         m0 = *m_head;
6819         if (m0->m_pkthdr.csum_flags) {
6820                 if (m0->m_pkthdr.csum_flags & CSUM_TSO) {
6821                         m0 = bce_tso_setup(sc, m_head, &flags);
6822                         if (m0 == NULL) {
6823                                 DBRUN(sc->tso_frames_failed++);
6824                                 goto bce_tx_encap_exit;
6825                         }
6826                         mss = htole16(m0->m_pkthdr.tso_segsz);
6827                 } else {
6828                         if (m0->m_pkthdr.csum_flags & CSUM_IP)
6829                                 flags |= TX_BD_FLAGS_IP_CKSUM;
6830                         if (m0->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP))
6831                                 flags |= TX_BD_FLAGS_TCP_UDP_CKSUM;
6832                 }
6833         }
6834
6835         /* Transfer any VLAN tags to the bd. */
6836         if (m0->m_flags & M_VLANTAG) {
6837                 flags |= TX_BD_FLAGS_VLAN_TAG;
6838                 vlan_tag = m0->m_pkthdr.ether_vtag;
6839         }
6840
6841         /* Map the mbuf into DMAable memory. */
6842         prod = sc->tx_prod;
6843         chain_prod = TX_CHAIN_IDX(prod);
6844         map = sc->tx_mbuf_map[chain_prod];
6845
6846         /* Map the mbuf into our DMA address space. */
6847         error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag, map, m0,
6848             segs, &nsegs, BUS_DMA_NOWAIT);
6849
6850         /* Check if the DMA mapping was successful */
6851         if (error == EFBIG) {
6852                 sc->mbuf_frag_count++;
6853
6854                 /* Try to defrag the mbuf. */
6855                 m0 = m_collapse(*m_head, M_DONTWAIT, BCE_MAX_SEGMENTS);
6856                 if (m0 == NULL) {
6857                         /* Defrag was unsuccessful */
6858                         m_freem(*m_head);
6859                         *m_head = NULL;
6860                         sc->mbuf_alloc_failed_count++;
6861                         rc = ENOBUFS;
6862                         goto bce_tx_encap_exit;
6863                 }
6864
6865                 /* Defrag was successful, try mapping again */
6866                 *m_head = m0;
6867                 error = bus_dmamap_load_mbuf_sg(sc->tx_mbuf_tag,
6868                     map, m0, segs, &nsegs, BUS_DMA_NOWAIT);
6869
6870                 /* Still getting an error after a defrag. */
6871                 if (error == ENOMEM) {
6872                         /* Insufficient DMA buffers available. */
6873                         sc->dma_map_addr_tx_failed_count++;
6874                         rc = error;
6875                         goto bce_tx_encap_exit;
6876                 } else if (error != 0) {
6877                         /* Release it and return an error. */
6878                         BCE_PRINTF("%s(%d): Unknown error mapping mbuf into "
6879                             "TX chain!\n", __FILE__, __LINE__);
6880                         m_freem(m0);
6881                         *m_head = NULL;
6882                         sc->dma_map_addr_tx_failed_count++;
6883                         rc = ENOBUFS;
6884                         goto bce_tx_encap_exit;
6885                 }
6886         } else if (error == ENOMEM) {
6887                 /* Insufficient DMA buffers available. */
6888                 sc->dma_map_addr_tx_failed_count++;
6889                 rc = error;
6890                 goto bce_tx_encap_exit;
6891         } else if (error != 0) {
6892                 m_freem(m0);
6893                 *m_head = NULL;
6894                 sc->dma_map_addr_tx_failed_count++;
6895                 rc = error;
6896                 goto bce_tx_encap_exit;
6897         }
6898
6899         /* Make sure there's room in the chain */
6900         if (nsegs > (sc->max_tx_bd - sc->used_tx_bd)) {
6901                 bus_dmamap_unload(sc->tx_mbuf_tag, map);
6902                 rc = ENOBUFS;
6903                 goto bce_tx_encap_exit;
6904         }
6905
6906         /* prod points to an empty tx_bd at this point. */
6907         prod_bseq  = sc->tx_prod_bseq;
6908
6909 #ifdef BCE_DEBUG
6910         debug_prod = chain_prod;
6911 #endif
6912
6913         DBPRINT(sc, BCE_INFO_SEND,
6914             "%s(start): prod = 0x%04X, chain_prod = 0x%04X, "
6915             "prod_bseq = 0x%08X\n",
6916             __FUNCTION__, prod, chain_prod, prod_bseq);
6917
6918         /*
6919          * Cycle through each mbuf segment that makes up
6920          * the outgoing frame, gathering the mapping info
6921          * for that segment and creating a tx_bd for
6922          * the mbuf.
6923          */
6924         for (i = 0; i < nsegs ; i++) {
6925
6926                 chain_prod = TX_CHAIN_IDX(prod);
6927                 txbd= &sc->tx_bd_chain[TX_PAGE(chain_prod)]
6928                     [TX_IDX(chain_prod)];
6929
6930                 txbd->tx_bd_haddr_lo =
6931                     htole32(BCE_ADDR_LO(segs[i].ds_addr));
6932                 txbd->tx_bd_haddr_hi =
6933                     htole32(BCE_ADDR_HI(segs[i].ds_addr));
6934                 txbd->tx_bd_mss_nbytes = htole32(mss << 16) |
6935                     htole16(segs[i].ds_len);
6936                 txbd->tx_bd_vlan_tag = htole16(vlan_tag);
6937                 txbd->tx_bd_flags = htole16(flags);
6938                 prod_bseq += segs[i].ds_len;
6939                 if (i == 0)
6940                         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_START);
6941                 prod = NEXT_TX_BD(prod);
6942         }
6943
6944         /* Set the END flag on the last TX buffer descriptor. */
6945         txbd->tx_bd_flags |= htole16(TX_BD_FLAGS_END);
6946
6947         DBRUNMSG(BCE_EXTREME_SEND,
6948             bce_dump_tx_chain(sc, debug_prod, nsegs));
6949
6950         /*
6951          * Ensure that the mbuf pointer for this transmission
6952          * is placed at the array index of the last
6953          * descriptor in this chain.  This is done
6954          * because a single map is used for all
6955          * segments of the mbuf and we don't want to
6956          * unload the map before all of the segments
6957          * have been freed.
6958          */
6959         sc->tx_mbuf_ptr[chain_prod] = m0;
6960         sc->used_tx_bd += nsegs;
6961
6962         /* Update some debug statistic counters */
6963         DBRUNIF((sc->used_tx_bd > sc->tx_hi_watermark),
6964             sc->tx_hi_watermark = sc->used_tx_bd);
6965         DBRUNIF((sc->used_tx_bd == sc->max_tx_bd), sc->tx_full_count++);
6966         DBRUNIF(sc->debug_tx_mbuf_alloc++);
6967
6968         DBRUNMSG(BCE_EXTREME_SEND, bce_dump_tx_mbuf_chain(sc, chain_prod, 1));
6969
6970         /* prod points to the next free tx_bd at this point. */
6971         sc->tx_prod = prod;
6972         sc->tx_prod_bseq = prod_bseq;
6973
6974         /* Tell the chip about the waiting TX frames. */
6975         REG_WR16(sc, MB_GET_CID_ADDR(TX_CID) +
6976             BCE_L2MQ_TX_HOST_BIDX, sc->tx_prod);
6977         REG_WR(sc, MB_GET_CID_ADDR(TX_CID) +
6978             BCE_L2MQ_TX_HOST_BSEQ, sc->tx_prod_bseq);
6979
6980 bce_tx_encap_exit:
6981         DBEXIT(BCE_VERBOSE_SEND);
6982         return(rc);
6983 }
6984
6985
6986 /****************************************************************************/
6987 /* Main transmit routine when called from another routine with a lock.      */
6988 /*                                                                          */
6989 /* Returns:                                                                 */
6990 /*   Nothing.                                                               */
6991 /****************************************************************************/
6992 static void
6993 bce_start_locked(struct ifnet *ifp)
6994 {
6995         struct bce_softc *sc = ifp->if_softc;
6996         struct mbuf *m_head = NULL;
6997         int count = 0;
6998         u16 tx_prod, tx_chain_prod;
6999
7000         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7001
7002         BCE_LOCK_ASSERT(sc);
7003
7004         /* prod points to the next free tx_bd. */
7005         tx_prod = sc->tx_prod;
7006         tx_chain_prod = TX_CHAIN_IDX(tx_prod);
7007
7008         DBPRINT(sc, BCE_INFO_SEND,
7009             "%s(enter): tx_prod = 0x%04X, tx_chain_prod = 0x%04X, "
7010             "tx_prod_bseq = 0x%08X\n",
7011             __FUNCTION__, tx_prod, tx_chain_prod, sc->tx_prod_bseq);
7012
7013         /* If there's no link or the transmit queue is empty then just exit. */
7014         if (sc->bce_link_up == FALSE) {
7015                 DBPRINT(sc, BCE_INFO_SEND, "%s(): No link.\n",
7016                     __FUNCTION__);
7017                 goto bce_start_locked_exit;
7018         }
7019
7020         if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7021                 DBPRINT(sc, BCE_INFO_SEND, "%s(): Transmit queue empty.\n",
7022                     __FUNCTION__);
7023                 goto bce_start_locked_exit;
7024         }
7025
7026         /*
7027          * Keep adding entries while there is space in the ring.
7028          */
7029         while (sc->used_tx_bd < sc->max_tx_bd) {
7030
7031                 /* Check for any frames to send. */
7032                 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
7033
7034                 /* Stop when the transmit queue is empty. */
7035                 if (m_head == NULL)
7036                         break;
7037
7038                 /*
7039                  * Pack the data into the transmit ring. If we
7040                  * don't have room, place the mbuf back at the
7041                  * head of the queue and set the OACTIVE flag
7042                  * to wait for the NIC to drain the chain.
7043                  */
7044                 if (bce_tx_encap(sc, &m_head)) {
7045                         if (m_head != NULL)
7046                                 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
7047                         ifp->if_drv_flags |= IFF_DRV_OACTIVE;
7048                         DBPRINT(sc, BCE_INFO_SEND,
7049                             "TX chain is closed for business! Total "
7050                             "tx_bd used = %d\n", sc->used_tx_bd);
7051                         break;
7052                 }
7053
7054                 count++;
7055
7056                 /* Send a copy of the frame to any BPF listeners. */
7057                 ETHER_BPF_MTAP(ifp, m_head);
7058         }
7059
7060         /* Exit if no packets were dequeued. */
7061         if (count == 0) {
7062                 DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): No packets were "
7063                     "dequeued\n", __FUNCTION__);
7064                 goto bce_start_locked_exit;
7065         }
7066
7067         DBPRINT(sc, BCE_VERBOSE_SEND, "%s(): Inserted %d frames into "
7068             "send queue.\n", __FUNCTION__, count);
7069
7070         /* Set the tx timeout. */
7071         sc->watchdog_timer = BCE_TX_TIMEOUT;
7072
7073         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_ctx(sc, TX_CID));
7074         DBRUNMSG(BCE_VERBOSE_SEND, bce_dump_mq_regs(sc));
7075
7076 bce_start_locked_exit:
7077         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_CTX);
7078         return;
7079 }
7080
7081
7082 /****************************************************************************/
7083 /* Main transmit routine when called from another routine without a lock.   */
7084 /*                                                                          */
7085 /* Returns:                                                                 */
7086 /*   Nothing.                                                               */
7087 /****************************************************************************/
7088 static void
7089 bce_start(struct ifnet *ifp)
7090 {
7091         struct bce_softc *sc = ifp->if_softc;
7092
7093         DBENTER(BCE_VERBOSE_SEND);
7094
7095         BCE_LOCK(sc);
7096         bce_start_locked(ifp);
7097         BCE_UNLOCK(sc);
7098
7099         DBEXIT(BCE_VERBOSE_SEND);
7100 }
7101
7102
7103 /****************************************************************************/
7104 /* Handles any IOCTL calls from the operating system.                       */
7105 /*                                                                          */
7106 /* Returns:                                                                 */
7107 /*   0 for success, positive value for failure.                             */
7108 /****************************************************************************/
7109 static int
7110 bce_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
7111 {
7112         struct bce_softc *sc = ifp->if_softc;
7113         struct ifreq *ifr = (struct ifreq *) data;
7114         struct mii_data *mii;
7115         int mask, error = 0, reinit;
7116
7117         DBENTER(BCE_VERBOSE_MISC);
7118
7119         switch(command) {
7120
7121         /* Set the interface MTU. */
7122         case SIOCSIFMTU:
7123                 /* Check that the MTU setting is supported. */
7124                 if ((ifr->ifr_mtu < BCE_MIN_MTU) ||
7125                         (ifr->ifr_mtu > BCE_MAX_JUMBO_MTU)) {
7126                         error = EINVAL;
7127                         break;
7128                 }
7129
7130                 DBPRINT(sc, BCE_INFO_MISC,
7131                     "SIOCSIFMTU: Changing MTU from %d to %d\n",
7132                     (int) ifp->if_mtu, (int) ifr->ifr_mtu);
7133
7134                 BCE_LOCK(sc);
7135                 ifp->if_mtu = ifr->ifr_mtu;
7136                 reinit = 0;
7137                 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7138                         /*
7139                          * Because allocation size is used in RX
7140                          * buffer allocation, stop controller if
7141                          * it is already running.
7142                          */
7143                         bce_stop(sc);
7144                         reinit = 1;
7145                 }
7146 #ifdef BCE_JUMBO_HDRSPLIT
7147                 /* No buffer allocation size changes are necessary. */
7148 #else
7149                 /* Recalculate our buffer allocation sizes. */
7150                 if ((ifp->if_mtu + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
7151                      ETHER_CRC_LEN) > MCLBYTES) {
7152                         sc->rx_bd_mbuf_alloc_size = MJUM9BYTES;
7153                         sc->rx_bd_mbuf_align_pad  =
7154                             roundup2(MJUM9BYTES, 16) - MJUM9BYTES;
7155                         sc->rx_bd_mbuf_data_len =
7156                             sc->rx_bd_mbuf_alloc_size -
7157                             sc->rx_bd_mbuf_align_pad;
7158                 } else {
7159                         sc->rx_bd_mbuf_alloc_size = MCLBYTES;
7160                         sc->rx_bd_mbuf_align_pad  =
7161                             roundup2(MCLBYTES, 16) - MCLBYTES;
7162                         sc->rx_bd_mbuf_data_len =
7163                             sc->rx_bd_mbuf_alloc_size -
7164                             sc->rx_bd_mbuf_align_pad;
7165                 }
7166 #endif
7167
7168                 if (reinit != 0)
7169                         bce_init_locked(sc);
7170                 BCE_UNLOCK(sc);
7171                 break;
7172
7173         /* Set interface flags. */
7174         case SIOCSIFFLAGS:
7175                 DBPRINT(sc, BCE_VERBOSE_SPECIAL, "Received SIOCSIFFLAGS\n");
7176
7177                 BCE_LOCK(sc);
7178
7179                 /* Check if the interface is up. */
7180                 if (ifp->if_flags & IFF_UP) {
7181                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7182                                 /* Change promiscuous/multicast flags as necessary. */
7183                                 bce_set_rx_mode(sc);
7184                         } else {
7185                                 /* Start the HW */
7186                                 bce_init_locked(sc);
7187                         }
7188                 } else {
7189                         /* The interface is down, check if driver is running. */
7190                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
7191                                 bce_stop(sc);
7192
7193                                 /* If MFW is running, restart the controller a bit. */
7194                                 if (sc->bce_flags & BCE_MFW_ENABLE_FLAG) {
7195                                         bce_reset(sc, BCE_DRV_MSG_CODE_RESET);
7196                                         bce_chipinit(sc);
7197                                         bce_mgmt_init_locked(sc);
7198                                 }
7199                         }
7200                 }
7201
7202                 BCE_UNLOCK(sc);
7203                 break;
7204
7205         /* Add/Delete multicast address */
7206         case SIOCADDMULTI:
7207         case SIOCDELMULTI:
7208                 DBPRINT(sc, BCE_VERBOSE_MISC,
7209                     "Received SIOCADDMULTI/SIOCDELMULTI\n");
7210
7211                 BCE_LOCK(sc);
7212                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
7213                         bce_set_rx_mode(sc);
7214                 BCE_UNLOCK(sc);
7215
7216                 break;
7217
7218         /* Set/Get Interface media */
7219         case SIOCSIFMEDIA:
7220         case SIOCGIFMEDIA:
7221                 DBPRINT(sc, BCE_VERBOSE_MISC,
7222                     "Received SIOCSIFMEDIA/SIOCGIFMEDIA\n");
7223
7224                 mii = device_get_softc(sc->bce_miibus);
7225                 error = ifmedia_ioctl(ifp, ifr,
7226                     &mii->mii_media, command);
7227                 break;
7228
7229         /* Set interface capability */
7230         case SIOCSIFCAP:
7231                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
7232                 DBPRINT(sc, BCE_INFO_MISC,
7233                     "Received SIOCSIFCAP = 0x%08X\n", (u32) mask);
7234
7235                 /* Toggle the TX checksum capabilities enable flag. */
7236                 if (mask & IFCAP_TXCSUM &&
7237                     ifp->if_capabilities & IFCAP_TXCSUM) {
7238                         ifp->if_capenable ^= IFCAP_TXCSUM;
7239                         if (IFCAP_TXCSUM & ifp->if_capenable)
7240                                 ifp->if_hwassist |= BCE_IF_HWASSIST;
7241                         else
7242                                 ifp->if_hwassist &= ~BCE_IF_HWASSIST;
7243                 }
7244
7245                 /* Toggle the RX checksum capabilities enable flag. */
7246                 if (mask & IFCAP_RXCSUM &&
7247                     ifp->if_capabilities & IFCAP_RXCSUM)
7248                         ifp->if_capenable ^= IFCAP_RXCSUM;
7249
7250                 /* Toggle the TSO capabilities enable flag. */
7251                 if (bce_tso_enable && (mask & IFCAP_TSO4) &&
7252                     ifp->if_capabilities & IFCAP_TSO4) {
7253                         ifp->if_capenable ^= IFCAP_TSO4;
7254                         if (IFCAP_TSO4 & ifp->if_capenable)
7255                                 ifp->if_hwassist |= CSUM_TSO;
7256                         else
7257                                 ifp->if_hwassist &= ~CSUM_TSO;
7258                 }
7259
7260                 if (mask & IFCAP_VLAN_HWCSUM &&
7261                     ifp->if_capabilities & IFCAP_VLAN_HWCSUM)
7262                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
7263
7264                 if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
7265                     (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
7266                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
7267                 /*
7268                  * Don't actually disable VLAN tag stripping as
7269                  * management firmware (ASF/IPMI/UMP) requires the
7270                  * feature. If VLAN tag stripping is disabled driver
7271                  * will manually reconstruct the VLAN frame by
7272                  * appending stripped VLAN tag.
7273                  */
7274                 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
7275                     (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING)) {
7276                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
7277                         if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING)
7278                             == 0)
7279                                 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
7280                 }
7281                 VLAN_CAPABILITIES(ifp);
7282                 break;
7283         default:
7284                 /* We don't know how to handle the IOCTL, pass it on. */
7285                 error = ether_ioctl(ifp, command, data);
7286                 break;
7287         }
7288
7289         DBEXIT(BCE_VERBOSE_MISC);
7290         return(error);
7291 }
7292
7293
7294 /****************************************************************************/
7295 /* Transmit timeout handler.                                                */
7296 /*                                                                          */
7297 /* Returns:                                                                 */
7298 /*   Nothing.                                                               */
7299 /****************************************************************************/
7300 static void
7301 bce_watchdog(struct bce_softc *sc)
7302 {
7303         DBENTER(BCE_EXTREME_SEND);
7304
7305         BCE_LOCK_ASSERT(sc);
7306
7307         /* If the watchdog timer hasn't expired then just exit. */
7308         if (sc->watchdog_timer == 0 || --sc->watchdog_timer)
7309                 goto bce_watchdog_exit;
7310
7311         /* If pause frames are active then don't reset the hardware. */
7312         /* ToDo: Should we reset the timer here? */
7313         if (REG_RD(sc, BCE_EMAC_TX_STATUS) & BCE_EMAC_TX_STATUS_XOFFED)
7314                 goto bce_watchdog_exit;
7315
7316         BCE_PRINTF("%s(%d): Watchdog timeout occurred, resetting!\n",
7317             __FILE__, __LINE__);
7318
7319         DBRUNMSG(BCE_INFO,
7320             bce_dump_driver_state(sc);
7321             bce_dump_status_block(sc);
7322             bce_dump_stats_block(sc);
7323             bce_dump_ftqs(sc);
7324             bce_dump_txp_state(sc, 0);
7325             bce_dump_rxp_state(sc, 0);
7326             bce_dump_tpat_state(sc, 0);
7327             bce_dump_cp_state(sc, 0);
7328             bce_dump_com_state(sc, 0));
7329
7330         DBRUN(bce_breakpoint(sc));
7331
7332         sc->bce_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
7333
7334         bce_init_locked(sc);
7335         sc->bce_ifp->if_oerrors++;
7336
7337 bce_watchdog_exit:
7338         DBEXIT(BCE_EXTREME_SEND);
7339 }
7340
7341
7342 /*
7343  * Interrupt handler.
7344  */
7345 /****************************************************************************/
7346 /* Main interrupt entry point.  Verifies that the controller generated the  */
7347 /* interrupt and then calls a separate routine for handle the various       */
7348 /* interrupt causes (PHY, TX, RX).                                          */
7349 /*                                                                          */
7350 /* Returns:                                                                 */
7351 /*   0 for success, positive value for failure.                             */
7352 /****************************************************************************/
7353 static void
7354 bce_intr(void *xsc)
7355 {
7356         struct bce_softc *sc;
7357         struct ifnet *ifp;
7358         u32 status_attn_bits;
7359         u16 hw_rx_cons, hw_tx_cons;
7360
7361         sc = xsc;
7362         ifp = sc->bce_ifp;
7363
7364         DBENTER(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7365         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_status_block(sc));
7366         DBRUNMSG(BCE_VERBOSE_INTR, bce_dump_stats_block(sc));
7367
7368         BCE_LOCK(sc);
7369
7370         DBRUN(sc->interrupts_generated++);
7371
7372         /* Synchnorize before we read from interface's status block */
7373         bus_dmamap_sync(sc->status_tag, sc->status_map,
7374             BUS_DMASYNC_POSTREAD);
7375
7376         /*
7377          * If the hardware status block index
7378          * matches the last value read by the
7379          * driver and we haven't asserted our
7380          * interrupt then there's nothing to do.
7381          */
7382         if ((sc->status_block->status_idx == sc->last_status_idx) &&
7383             (REG_RD(sc, BCE_PCICFG_MISC_STATUS) &
7384              BCE_PCICFG_MISC_STATUS_INTA_VALUE)) {
7385                 DBPRINT(sc, BCE_VERBOSE_INTR, "%s(): Spurious interrupt.\n",
7386                     __FUNCTION__);
7387                 goto bce_intr_exit;
7388         }
7389
7390         /* Ack the interrupt and stop others from occuring. */
7391         REG_WR(sc, BCE_PCICFG_INT_ACK_CMD,
7392             BCE_PCICFG_INT_ACK_CMD_USE_INT_HC_PARAM |
7393             BCE_PCICFG_INT_ACK_CMD_MASK_INT);
7394
7395         /* Check if the hardware has finished any work. */
7396         hw_rx_cons = bce_get_hw_rx_cons(sc);
7397         hw_tx_cons = bce_get_hw_tx_cons(sc);
7398
7399         /* Keep processing data as long as there is work to do. */
7400         for (;;) {
7401
7402                 status_attn_bits = sc->status_block->status_attn_bits;
7403
7404                 DBRUNIF(DB_RANDOMTRUE(unexpected_attention_sim_control),
7405                     BCE_PRINTF("Simulating unexpected status attention "
7406                     "bit set.");
7407                     sc->unexpected_attention_sim_count++;
7408                     status_attn_bits = status_attn_bits |
7409                     STATUS_ATTN_BITS_PARITY_ERROR);
7410
7411                 /* Was it a link change interrupt? */
7412                 if ((status_attn_bits & STATUS_ATTN_BITS_LINK_STATE) !=
7413                     (sc->status_block->status_attn_bits_ack &
7414                      STATUS_ATTN_BITS_LINK_STATE)) {
7415                         bce_phy_intr(sc);
7416
7417                         /* Clear transient updates during link state change. */
7418                         REG_WR(sc, BCE_HC_COMMAND, sc->hc_command |
7419                             BCE_HC_COMMAND_COAL_NOW_WO_INT);
7420                         REG_RD(sc, BCE_HC_COMMAND);
7421                 }
7422
7423                 /* If any other attention is asserted, the chip is toast. */
7424                 if (((status_attn_bits & ~STATUS_ATTN_BITS_LINK_STATE) !=
7425                     (sc->status_block->status_attn_bits_ack &
7426                     ~STATUS_ATTN_BITS_LINK_STATE))) {
7427
7428                         sc->unexpected_attention_count++;
7429
7430                         BCE_PRINTF("%s(%d): Fatal attention detected: "
7431                             "0x%08X\n", __FILE__, __LINE__,
7432                             sc->status_block->status_attn_bits);
7433
7434                         DBRUNMSG(BCE_FATAL,
7435                             if (unexpected_attention_sim_control == 0)
7436                                 bce_breakpoint(sc));
7437
7438                         bce_init_locked(sc);
7439                         goto bce_intr_exit;
7440                 }
7441
7442                 /* Check for any completed RX frames. */
7443                 if (hw_rx_cons != sc->hw_rx_cons)
7444                         bce_rx_intr(sc);
7445
7446                 /* Check for any completed TX frames. */
7447                 if (hw_tx_cons != sc->hw_tx_cons)
7448                         bce_tx_intr(sc);
7449
7450                 /* Save status block index value for the next interrupt. */
7451                 sc->last_status_idx = sc->status_block->status_idx;
7452
7453                 /*
7454                  * Prevent speculative reads from getting
7455                  * ahead of the status block.
7456                  */
7457                 bus_space_barrier(sc->bce_btag, sc->bce_bhandle, 0, 0,
7458                     BUS_SPACE_BARRIER_READ);
7459
7460                 /*
7461                  * If there's no work left then exit the
7462                  * interrupt service routine.
7463                  */
7464                 hw_rx_cons = bce_get_hw_rx_cons(sc);
7465                 hw_tx_cons = bce_get_hw_tx_cons(sc);
7466
7467                 if ((hw_rx_cons == sc->hw_rx_cons) &&
7468                     (hw_tx_cons == sc->hw_tx_cons))
7469                         break;
7470
7471         }
7472
7473         bus_dmamap_sync(sc->status_tag, sc->status_map,
7474             BUS_DMASYNC_PREREAD);
7475
7476         /* Re-enable interrupts. */
7477         bce_enable_intr(sc, 0);
7478
7479         /* Handle any frames that arrived while handling the interrupt. */
7480         if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
7481             !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
7482                 bce_start_locked(ifp);
7483
7484 bce_intr_exit:
7485         BCE_UNLOCK(sc);
7486
7487         DBEXIT(BCE_VERBOSE_SEND | BCE_VERBOSE_RECV | BCE_VERBOSE_INTR);
7488 }
7489
7490
7491 /****************************************************************************/
7492 /* Programs the various packet receive modes (broadcast and multicast).     */
7493 /*                                                                          */
7494 /* Returns:                                                                 */
7495 /*   Nothing.                                                               */
7496 /****************************************************************************/
7497 static void
7498 bce_set_rx_mode(struct bce_softc *sc)
7499 {
7500         struct ifnet *ifp;
7501         struct ifmultiaddr *ifma;
7502         u32 hashes[NUM_MC_HASH_REGISTERS] = { 0, 0, 0, 0, 0, 0, 0, 0 };
7503         u32 rx_mode, sort_mode;
7504         int h, i;
7505
7506         DBENTER(BCE_VERBOSE_MISC);
7507
7508         BCE_LOCK_ASSERT(sc);
7509
7510         ifp = sc->bce_ifp;
7511
7512         /* Initialize receive mode default settings. */
7513         rx_mode   = sc->rx_mode & ~(BCE_EMAC_RX_MODE_PROMISCUOUS |
7514             BCE_EMAC_RX_MODE_KEEP_VLAN_TAG);
7515         sort_mode = 1 | BCE_RPM_SORT_USER0_BC_EN;
7516
7517         /*
7518          * ASF/IPMI/UMP firmware requires that VLAN tag stripping
7519          * be enbled.
7520          */
7521         if (!(BCE_IF_CAPABILITIES & IFCAP_VLAN_HWTAGGING) &&
7522             (!(sc->bce_flags & BCE_MFW_ENABLE_FLAG)))
7523                 rx_mode |= BCE_EMAC_RX_MODE_KEEP_VLAN_TAG;
7524
7525         /*
7526          * Check for promiscuous, all multicast, or selected
7527          * multicast address filtering.
7528          */
7529         if (ifp->if_flags & IFF_PROMISC) {
7530                 DBPRINT(sc, BCE_INFO_MISC, "Enabling promiscuous mode.\n");
7531
7532                 /* Enable promiscuous mode. */
7533                 rx_mode |= BCE_EMAC_RX_MODE_PROMISCUOUS;
7534                 sort_mode |= BCE_RPM_SORT_USER0_PROM_EN;
7535         } else if (ifp->if_flags & IFF_ALLMULTI) {
7536                 DBPRINT(sc, BCE_INFO_MISC, "Enabling all multicast mode.\n");
7537
7538                 /* Enable all multicast addresses. */
7539                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++) {
7540                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), 0xffffffff);
7541         }
7542                 sort_mode |= BCE_RPM_SORT_USER0_MC_EN;
7543         } else {
7544                 /* Accept one or more multicast(s). */
7545                 DBPRINT(sc, BCE_INFO_MISC, "Enabling selective multicast mode.\n");
7546
7547                 if_maddr_rlock(ifp);
7548                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
7549                         if (ifma->ifma_addr->sa_family != AF_LINK)
7550                                 continue;
7551                         h = ether_crc32_le(LLADDR((struct sockaddr_dl *)
7552                             ifma->ifma_addr), ETHER_ADDR_LEN) & 0xFF;
7553                             hashes[(h & 0xE0) >> 5] |= 1 << (h & 0x1F);
7554                 }
7555                 if_maddr_runlock(ifp);
7556
7557                 for (i = 0; i < NUM_MC_HASH_REGISTERS; i++)
7558                         REG_WR(sc, BCE_EMAC_MULTICAST_HASH0 + (i * 4), hashes[i]);
7559
7560                 sort_mode |= BCE_RPM_SORT_USER0_MC_HSH_EN;
7561         }
7562
7563         /* Only make changes if the recive mode has actually changed. */
7564         if (rx_mode != sc->rx_mode) {
7565                 DBPRINT(sc, BCE_VERBOSE_MISC, "Enabling new receive mode: "
7566                     "0x%08X\n", rx_mode);
7567
7568                 sc->rx_mode = rx_mode;
7569                 REG_WR(sc, BCE_EMAC_RX_MODE, rx_mode);
7570         }
7571
7572         /* Disable and clear the exisitng sort before enabling a new sort. */
7573         REG_WR(sc, BCE_RPM_SORT_USER0, 0x0);
7574         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode);
7575         REG_WR(sc, BCE_RPM_SORT_USER0, sort_mode | BCE_RPM_SORT_USER0_ENA);
7576
7577         DBEXIT(BCE_VERBOSE_MISC);
7578 }
7579
7580
7581 /****************************************************************************/
7582 /* Called periodically to updates statistics from the controllers           */
7583 /* statistics block.                                                        */
7584 /*                                                                          */
7585 /* Returns:                                                                 */
7586 /*   Nothing.                                                               */
7587 /****************************************************************************/
7588 static void
7589 bce_stats_update(struct bce_softc *sc)
7590 {
7591         struct ifnet *ifp;
7592         struct statistics_block *stats;
7593
7594         DBENTER(BCE_EXTREME_MISC);
7595
7596         ifp = sc->bce_ifp;
7597
7598         stats = (struct statistics_block *) sc->stats_block;
7599
7600         /*
7601          * Certain controllers don't report
7602          * carrier sense errors correctly.
7603          * See errata E11_5708CA0_1165.
7604          */
7605         if (!(BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5706) &&
7606             !(BCE_CHIP_ID(sc) == BCE_CHIP_ID_5708_A0))
7607                 ifp->if_oerrors +=
7608                     (u_long) stats->stat_Dot3StatsCarrierSenseErrors;
7609
7610         /*
7611          * Update the sysctl statistics from the
7612          * hardware statistics.
7613          */
7614         sc->stat_IfHCInOctets =
7615             ((u64) stats->stat_IfHCInOctets_hi << 32) +
7616              (u64) stats->stat_IfHCInOctets_lo;
7617
7618         sc->stat_IfHCInBadOctets =
7619             ((u64) stats->stat_IfHCInBadOctets_hi << 32) +
7620              (u64) stats->stat_IfHCInBadOctets_lo;
7621
7622         sc->stat_IfHCOutOctets =
7623             ((u64) stats->stat_IfHCOutOctets_hi << 32) +
7624              (u64) stats->stat_IfHCOutOctets_lo;
7625
7626         sc->stat_IfHCOutBadOctets =
7627             ((u64) stats->stat_IfHCOutBadOctets_hi << 32) +
7628              (u64) stats->stat_IfHCOutBadOctets_lo;
7629
7630         sc->stat_IfHCInUcastPkts =
7631             ((u64) stats->stat_IfHCInUcastPkts_hi << 32) +
7632              (u64) stats->stat_IfHCInUcastPkts_lo;
7633
7634         sc->stat_IfHCInMulticastPkts =
7635             ((u64) stats->stat_IfHCInMulticastPkts_hi << 32) +
7636              (u64) stats->stat_IfHCInMulticastPkts_lo;
7637
7638         sc->stat_IfHCInBroadcastPkts =
7639             ((u64) stats->stat_IfHCInBroadcastPkts_hi << 32) +
7640              (u64) stats->stat_IfHCInBroadcastPkts_lo;
7641
7642         sc->stat_IfHCOutUcastPkts =
7643             ((u64) stats->stat_IfHCOutUcastPkts_hi << 32) +
7644              (u64) stats->stat_IfHCOutUcastPkts_lo;
7645
7646         sc->stat_IfHCOutMulticastPkts =
7647             ((u64) stats->stat_IfHCOutMulticastPkts_hi << 32) +
7648              (u64) stats->stat_IfHCOutMulticastPkts_lo;
7649
7650         sc->stat_IfHCOutBroadcastPkts =
7651             ((u64) stats->stat_IfHCOutBroadcastPkts_hi << 32) +
7652              (u64) stats->stat_IfHCOutBroadcastPkts_lo;
7653
7654         /* ToDo: Preserve counters beyond 32 bits? */
7655         /* ToDo: Read the statistics from auto-clear regs? */
7656
7657         sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors =
7658             stats->stat_emac_tx_stat_dot3statsinternalmactransmiterrors;
7659
7660         sc->stat_Dot3StatsCarrierSenseErrors =
7661             stats->stat_Dot3StatsCarrierSenseErrors;
7662
7663         sc->stat_Dot3StatsFCSErrors =
7664             stats->stat_Dot3StatsFCSErrors;
7665
7666         sc->stat_Dot3StatsAlignmentErrors =
7667             stats->stat_Dot3StatsAlignmentErrors;
7668
7669         sc->stat_Dot3StatsSingleCollisionFrames =
7670             stats->stat_Dot3StatsSingleCollisionFrames;
7671
7672         sc->stat_Dot3StatsMultipleCollisionFrames =
7673             stats->stat_Dot3StatsMultipleCollisionFrames;
7674
7675         sc->stat_Dot3StatsDeferredTransmissions =
7676             stats->stat_Dot3StatsDeferredTransmissions;
7677
7678         sc->stat_Dot3StatsExcessiveCollisions =
7679             stats->stat_Dot3StatsExcessiveCollisions;
7680
7681         sc->stat_Dot3StatsLateCollisions =
7682             stats->stat_Dot3StatsLateCollisions;
7683
7684         sc->stat_EtherStatsCollisions =
7685             stats->stat_EtherStatsCollisions;
7686
7687         sc->stat_EtherStatsFragments =
7688             stats->stat_EtherStatsFragments;
7689
7690         sc->stat_EtherStatsJabbers =
7691             stats->stat_EtherStatsJabbers;
7692
7693         sc->stat_EtherStatsUndersizePkts =
7694             stats->stat_EtherStatsUndersizePkts;
7695
7696         sc->stat_EtherStatsOversizePkts =
7697              stats->stat_EtherStatsOversizePkts;
7698
7699         sc->stat_EtherStatsPktsRx64Octets =
7700             stats->stat_EtherStatsPktsRx64Octets;
7701
7702         sc->stat_EtherStatsPktsRx65Octetsto127Octets =
7703             stats->stat_EtherStatsPktsRx65Octetsto127Octets;
7704
7705         sc->stat_EtherStatsPktsRx128Octetsto255Octets =
7706             stats->stat_EtherStatsPktsRx128Octetsto255Octets;
7707
7708         sc->stat_EtherStatsPktsRx256Octetsto511Octets =
7709             stats->stat_EtherStatsPktsRx256Octetsto511Octets;
7710
7711         sc->stat_EtherStatsPktsRx512Octetsto1023Octets =
7712             stats->stat_EtherStatsPktsRx512Octetsto1023Octets;
7713
7714         sc->stat_EtherStatsPktsRx1024Octetsto1522Octets =
7715             stats->stat_EtherStatsPktsRx1024Octetsto1522Octets;
7716
7717         sc->stat_EtherStatsPktsRx1523Octetsto9022Octets =
7718             stats->stat_EtherStatsPktsRx1523Octetsto9022Octets;
7719
7720         sc->stat_EtherStatsPktsTx64Octets =
7721             stats->stat_EtherStatsPktsTx64Octets;
7722
7723         sc->stat_EtherStatsPktsTx65Octetsto127Octets =
7724             stats->stat_EtherStatsPktsTx65Octetsto127Octets;
7725
7726         sc->stat_EtherStatsPktsTx128Octetsto255Octets =
7727             stats->stat_EtherStatsPktsTx128Octetsto255Octets;
7728
7729         sc->stat_EtherStatsPktsTx256Octetsto511Octets =
7730             stats->stat_EtherStatsPktsTx256Octetsto511Octets;
7731
7732         sc->stat_EtherStatsPktsTx512Octetsto1023Octets =
7733             stats->stat_EtherStatsPktsTx512Octetsto1023Octets;
7734
7735         sc->stat_EtherStatsPktsTx1024Octetsto1522Octets =
7736             stats->stat_EtherStatsPktsTx1024Octetsto1522Octets;
7737
7738         sc->stat_EtherStatsPktsTx1523Octetsto9022Octets =
7739             stats->stat_EtherStatsPktsTx1523Octetsto9022Octets;
7740
7741         sc->stat_XonPauseFramesReceived =
7742             stats->stat_XonPauseFramesReceived;
7743
7744         sc->stat_XoffPauseFramesReceived =
7745             stats->stat_XoffPauseFramesReceived;
7746
7747         sc->stat_OutXonSent =
7748             stats->stat_OutXonSent;
7749
7750         sc->stat_OutXoffSent =
7751             stats->stat_OutXoffSent;
7752
7753         sc->stat_FlowControlDone =
7754             stats->stat_FlowControlDone;
7755
7756         sc->stat_MacControlFramesReceived =
7757             stats->stat_MacControlFramesReceived;
7758
7759         sc->stat_XoffStateEntered =
7760             stats->stat_XoffStateEntered;
7761
7762         sc->stat_IfInFramesL2FilterDiscards =
7763             stats->stat_IfInFramesL2FilterDiscards;
7764
7765         sc->stat_IfInRuleCheckerDiscards =
7766             stats->stat_IfInRuleCheckerDiscards;
7767
7768         sc->stat_IfInFTQDiscards =
7769             stats->stat_IfInFTQDiscards;
7770
7771         sc->stat_IfInMBUFDiscards =
7772             stats->stat_IfInMBUFDiscards;
7773
7774         sc->stat_IfInRuleCheckerP4Hit =
7775             stats->stat_IfInRuleCheckerP4Hit;
7776
7777         sc->stat_CatchupInRuleCheckerDiscards =
7778             stats->stat_CatchupInRuleCheckerDiscards;
7779
7780         sc->stat_CatchupInFTQDiscards =
7781             stats->stat_CatchupInFTQDiscards;
7782
7783         sc->stat_CatchupInMBUFDiscards =
7784             stats->stat_CatchupInMBUFDiscards;
7785
7786         sc->stat_CatchupInRuleCheckerP4Hit =
7787             stats->stat_CatchupInRuleCheckerP4Hit;
7788
7789         sc->com_no_buffers = REG_RD_IND(sc, 0x120084);
7790
7791         /*
7792          * Update the interface statistics from the
7793          * hardware statistics.
7794          */
7795         ifp->if_collisions =
7796             (u_long) sc->stat_EtherStatsCollisions;
7797
7798         /* ToDo: This method loses soft errors. */
7799         ifp->if_ierrors =
7800             (u_long) sc->stat_EtherStatsUndersizePkts +
7801             (u_long) sc->stat_EtherStatsOversizePkts +
7802             (u_long) sc->stat_IfInMBUFDiscards +
7803             (u_long) sc->stat_Dot3StatsAlignmentErrors +
7804             (u_long) sc->stat_Dot3StatsFCSErrors +
7805             (u_long) sc->stat_IfInRuleCheckerDiscards +
7806             (u_long) sc->stat_IfInFTQDiscards +
7807             (u_long) sc->com_no_buffers;
7808
7809         /* ToDo: This method loses soft errors. */
7810         ifp->if_oerrors =
7811             (u_long) sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors +
7812             (u_long) sc->stat_Dot3StatsExcessiveCollisions +
7813             (u_long) sc->stat_Dot3StatsLateCollisions;
7814
7815         /* ToDo: Add additional statistics? */
7816
7817         DBEXIT(BCE_EXTREME_MISC);
7818 }
7819
7820
7821 /****************************************************************************/
7822 /* Periodic function to notify the bootcode that the driver is still        */
7823 /* present.                                                                 */
7824 /*                                                                          */
7825 /* Returns:                                                                 */
7826 /*   Nothing.                                                               */
7827 /****************************************************************************/
7828 static void
7829 bce_pulse(void *xsc)
7830 {
7831         struct bce_softc *sc = xsc;
7832         u32 msg;
7833
7834         DBENTER(BCE_EXTREME_MISC);
7835
7836         BCE_LOCK_ASSERT(sc);
7837
7838         /* Tell the firmware that the driver is still running. */
7839         msg = (u32) ++sc->bce_fw_drv_pulse_wr_seq;
7840         bce_shmem_wr(sc, BCE_DRV_PULSE_MB, msg);
7841
7842         /* Update the bootcode condition. */
7843         sc->bc_state = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
7844
7845         /* Report whether the bootcode still knows the driver is running. */
7846         if (bootverbose) {
7847                 if (sc->bce_drv_cardiac_arrest == FALSE) {
7848                         if (!(sc->bc_state & BCE_CONDITION_DRV_PRESENT)) {
7849                                 sc->bce_drv_cardiac_arrest = TRUE;
7850                                 BCE_PRINTF("%s(): Warning: bootcode "
7851                                     "thinks driver is absent! "
7852                                     "(bc_state = 0x%08X)\n",
7853                                     __FUNCTION__, sc->bc_state);
7854                         }
7855                 } else {
7856                         /*
7857                          * Not supported by all bootcode versions.
7858                          * (v5.0.11+ and v5.2.1+)  Older bootcode
7859                          * will require the driver to reset the
7860                          * controller to clear this condition.
7861                          */
7862                         if (sc->bc_state & BCE_CONDITION_DRV_PRESENT) {
7863                                 sc->bce_drv_cardiac_arrest = FALSE;
7864                                 BCE_PRINTF("%s(): Bootcode found the "
7865                                     "driver pulse! (bc_state = 0x%08X)\n",
7866                                     __FUNCTION__, sc->bc_state);
7867                         }
7868                 }
7869         }
7870
7871
7872         /* Schedule the next pulse. */
7873         callout_reset(&sc->bce_pulse_callout, hz, bce_pulse, sc);
7874
7875         DBEXIT(BCE_EXTREME_MISC);
7876 }
7877
7878
7879 /****************************************************************************/
7880 /* Periodic function to perform maintenance tasks.                          */
7881 /*                                                                          */
7882 /* Returns:                                                                 */
7883 /*   Nothing.                                                               */
7884 /****************************************************************************/
7885 static void
7886 bce_tick(void *xsc)
7887 {
7888         struct bce_softc *sc = xsc;
7889         struct mii_data *mii;
7890         struct ifnet *ifp;
7891
7892         ifp = sc->bce_ifp;
7893
7894         DBENTER(BCE_EXTREME_MISC);
7895
7896         BCE_LOCK_ASSERT(sc);
7897
7898         /* Schedule the next tick. */
7899         callout_reset(&sc->bce_tick_callout, hz, bce_tick, sc);
7900
7901         /* Update the statistics from the hardware statistics block. */
7902         bce_stats_update(sc);
7903
7904         /* Top off the receive and page chains. */
7905 #ifdef BCE_JUMBO_HDRSPLIT
7906         bce_fill_pg_chain(sc);
7907 #endif
7908         bce_fill_rx_chain(sc);
7909
7910         /* Check that chip hasn't hung. */
7911         bce_watchdog(sc);
7912
7913         /* If link is up already up then we're done. */
7914         if (sc->bce_link_up == TRUE)
7915                 goto bce_tick_exit;
7916
7917         /* Link is down.  Check what the PHY's doing. */
7918         mii = device_get_softc(sc->bce_miibus);
7919         mii_tick(mii);
7920
7921         /* Check if the link has come up. */
7922         if ((mii->mii_media_status & IFM_ACTIVE) &&
7923             (IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE)) {
7924                 DBPRINT(sc, BCE_VERBOSE_MISC,
7925                     "%s(): Link up!\n", __FUNCTION__);
7926                 sc->bce_link_up = TRUE;
7927                 if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T ||
7928                     IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX ||
7929                     IFM_SUBTYPE(mii->mii_media_active) == IFM_2500_SX) &&
7930                     bootverbose)
7931                         BCE_PRINTF("Gigabit link up!\n");
7932
7933                 /* Now that link is up, handle any outstanding TX traffic. */
7934                 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
7935                         DBPRINT(sc, BCE_VERBOSE_MISC, "%s(): Found "
7936                             "pending TX traffic.\n", __FUNCTION__);
7937                         bce_start_locked(ifp);
7938                 }
7939         }
7940
7941 bce_tick_exit:
7942         DBEXIT(BCE_EXTREME_MISC);
7943         return;
7944 }
7945
7946
7947 #ifdef BCE_DEBUG
7948 /****************************************************************************/
7949 /* Allows the driver state to be dumped through the sysctl interface.       */
7950 /*                                                                          */
7951 /* Returns:                                                                 */
7952 /*   0 for success, positive value for failure.                             */
7953 /****************************************************************************/
7954 static int
7955 bce_sysctl_driver_state(SYSCTL_HANDLER_ARGS)
7956 {
7957         int error;
7958         int result;
7959         struct bce_softc *sc;
7960
7961         result = -1;
7962         error = sysctl_handle_int(oidp, &result, 0, req);
7963
7964         if (error || !req->newptr)
7965                 return (error);
7966
7967         if (result == 1) {
7968                 sc = (struct bce_softc *)arg1;
7969                 bce_dump_driver_state(sc);
7970         }
7971
7972         return error;
7973 }
7974
7975
7976 /****************************************************************************/
7977 /* Allows the hardware state to be dumped through the sysctl interface.     */
7978 /*                                                                          */
7979 /* Returns:                                                                 */
7980 /*   0 for success, positive value for failure.                             */
7981 /****************************************************************************/
7982 static int
7983 bce_sysctl_hw_state(SYSCTL_HANDLER_ARGS)
7984 {
7985         int error;
7986         int result;
7987         struct bce_softc *sc;
7988
7989         result = -1;
7990         error = sysctl_handle_int(oidp, &result, 0, req);
7991
7992         if (error || !req->newptr)
7993                 return (error);
7994
7995         if (result == 1) {
7996                 sc = (struct bce_softc *)arg1;
7997                 bce_dump_hw_state(sc);
7998         }
7999
8000         return error;
8001 }
8002
8003
8004 /****************************************************************************/
8005 /* Allows the status block to be dumped through the sysctl interface.       */
8006 /*                                                                          */
8007 /* Returns:                                                                 */
8008 /*   0 for success, positive value for failure.                             */
8009 /****************************************************************************/
8010 static int
8011 bce_sysctl_status_block(SYSCTL_HANDLER_ARGS)
8012 {
8013         int error;
8014         int result;
8015         struct bce_softc *sc;
8016
8017         result = -1;
8018         error = sysctl_handle_int(oidp, &result, 0, req);
8019
8020         if (error || !req->newptr)
8021                 return (error);
8022
8023         if (result == 1) {
8024                 sc = (struct bce_softc *)arg1;
8025                 bce_dump_status_block(sc);
8026         }
8027
8028         return error;
8029 }
8030
8031
8032 /****************************************************************************/
8033 /* Allows the stats block to be dumped through the sysctl interface.        */
8034 /*                                                                          */
8035 /* Returns:                                                                 */
8036 /*   0 for success, positive value for failure.                             */
8037 /****************************************************************************/
8038 static int
8039 bce_sysctl_stats_block(SYSCTL_HANDLER_ARGS)
8040 {
8041         int error;
8042         int result;
8043         struct bce_softc *sc;
8044
8045         result = -1;
8046         error = sysctl_handle_int(oidp, &result, 0, req);
8047
8048         if (error || !req->newptr)
8049                 return (error);
8050
8051         if (result == 1) {
8052                 sc = (struct bce_softc *)arg1;
8053                 bce_dump_stats_block(sc);
8054         }
8055
8056         return error;
8057 }
8058
8059
8060 /****************************************************************************/
8061 /* Allows the stat counters to be cleared without unloading/reloading the   */
8062 /* driver.                                                                  */
8063 /*                                                                          */
8064 /* Returns:                                                                 */
8065 /*   0 for success, positive value for failure.                             */
8066 /****************************************************************************/
8067 static int
8068 bce_sysctl_stats_clear(SYSCTL_HANDLER_ARGS)
8069 {
8070         int error;
8071         int result;
8072         struct bce_softc *sc;
8073
8074         result = -1;
8075         error = sysctl_handle_int(oidp, &result, 0, req);
8076
8077         if (error || !req->newptr)
8078                 return (error);
8079
8080         if (result == 1) {
8081                 sc = (struct bce_softc *)arg1;
8082
8083                 /* Clear the internal H/W statistics counters. */
8084                 REG_WR(sc, BCE_HC_COMMAND, BCE_HC_COMMAND_CLR_STAT_NOW);
8085
8086                 /* Reset the driver maintained statistics. */
8087                 sc->interrupts_rx =
8088                     sc->interrupts_tx = 0;
8089                 sc->tso_frames_requested =
8090                     sc->tso_frames_completed =
8091                     sc->tso_frames_failed = 0;
8092                 sc->rx_empty_count =
8093                     sc->tx_full_count = 0;
8094                 sc->rx_low_watermark = USABLE_RX_BD;
8095                 sc->tx_hi_watermark = 0;
8096                 sc->l2fhdr_error_count =
8097                     sc->l2fhdr_error_sim_count = 0;
8098                 sc->mbuf_alloc_failed_count =
8099                     sc->mbuf_alloc_failed_sim_count = 0;
8100                 sc->dma_map_addr_rx_failed_count =
8101                     sc->dma_map_addr_tx_failed_count = 0;
8102                 sc->mbuf_frag_count = 0;
8103                 sc->csum_offload_tcp_udp =
8104                    sc->csum_offload_ip = 0;
8105                 sc->vlan_tagged_frames_rcvd =
8106                    sc->vlan_tagged_frames_stripped = 0;
8107
8108                 /* Clear firmware maintained statistics. */
8109                 REG_WR_IND(sc, 0x120084, 0);
8110         }
8111
8112         return error;
8113 }
8114
8115
8116 /****************************************************************************/
8117 /* Allows the bootcode state to be dumped through the sysctl interface.     */
8118 /*                                                                          */
8119 /* Returns:                                                                 */
8120 /*   0 for success, positive value for failure.                             */
8121 /****************************************************************************/
8122 static int
8123 bce_sysctl_bc_state(SYSCTL_HANDLER_ARGS)
8124 {
8125         int error;
8126         int result;
8127         struct bce_softc *sc;
8128
8129         result = -1;
8130         error = sysctl_handle_int(oidp, &result, 0, req);
8131
8132         if (error || !req->newptr)
8133                 return (error);
8134
8135         if (result == 1) {
8136                 sc = (struct bce_softc *)arg1;
8137                 bce_dump_bc_state(sc);
8138         }
8139
8140         return error;
8141 }
8142
8143
8144 /****************************************************************************/
8145 /* Provides a sysctl interface to allow dumping the RX BD chain.            */
8146 /*                                                                          */
8147 /* Returns:                                                                 */
8148 /*   0 for success, positive value for failure.                             */
8149 /****************************************************************************/
8150 static int
8151 bce_sysctl_dump_rx_bd_chain(SYSCTL_HANDLER_ARGS)
8152 {
8153         int error;
8154         int result;
8155         struct bce_softc *sc;
8156
8157         result = -1;
8158         error = sysctl_handle_int(oidp, &result, 0, req);
8159
8160         if (error || !req->newptr)
8161                 return (error);
8162
8163         if (result == 1) {
8164                 sc = (struct bce_softc *)arg1;
8165                 bce_dump_rx_bd_chain(sc, 0, TOTAL_RX_BD);
8166         }
8167
8168         return error;
8169 }
8170
8171
8172 /****************************************************************************/
8173 /* Provides a sysctl interface to allow dumping the RX MBUF chain.          */
8174 /*                                                                          */
8175 /* Returns:                                                                 */
8176 /*   0 for success, positive value for failure.                             */
8177 /****************************************************************************/
8178 static int
8179 bce_sysctl_dump_rx_mbuf_chain(SYSCTL_HANDLER_ARGS)
8180 {
8181         int error;
8182         int result;
8183         struct bce_softc *sc;
8184
8185         result = -1;
8186         error = sysctl_handle_int(oidp, &result, 0, req);
8187
8188         if (error || !req->newptr)
8189                 return (error);
8190
8191         if (result == 1) {
8192                 sc = (struct bce_softc *)arg1;
8193                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD);
8194         }
8195
8196         return error;
8197 }
8198
8199
8200 /****************************************************************************/
8201 /* Provides a sysctl interface to allow dumping the TX chain.               */
8202 /*                                                                          */
8203 /* Returns:                                                                 */
8204 /*   0 for success, positive value for failure.                             */
8205 /****************************************************************************/
8206 static int
8207 bce_sysctl_dump_tx_chain(SYSCTL_HANDLER_ARGS)
8208 {
8209         int error;
8210         int result;
8211         struct bce_softc *sc;
8212
8213         result = -1;
8214         error = sysctl_handle_int(oidp, &result, 0, req);
8215
8216         if (error || !req->newptr)
8217                 return (error);
8218
8219         if (result == 1) {
8220                 sc = (struct bce_softc *)arg1;
8221                 bce_dump_tx_chain(sc, 0, TOTAL_TX_BD);
8222         }
8223
8224         return error;
8225 }
8226
8227
8228 #ifdef BCE_JUMBO_HDRSPLIT
8229 /****************************************************************************/
8230 /* Provides a sysctl interface to allow dumping the page chain.             */
8231 /*                                                                          */
8232 /* Returns:                                                                 */
8233 /*   0 for success, positive value for failure.                             */
8234 /****************************************************************************/
8235 static int
8236 bce_sysctl_dump_pg_chain(SYSCTL_HANDLER_ARGS)
8237 {
8238         int error;
8239         int result;
8240         struct bce_softc *sc;
8241
8242         result = -1;
8243         error = sysctl_handle_int(oidp, &result, 0, req);
8244
8245         if (error || !req->newptr)
8246                 return (error);
8247
8248         if (result == 1) {
8249                 sc = (struct bce_softc *)arg1;
8250                 bce_dump_pg_chain(sc, 0, TOTAL_PG_BD);
8251         }
8252
8253         return error;
8254 }
8255 #endif
8256
8257 /****************************************************************************/
8258 /* Provides a sysctl interface to allow reading arbitrary NVRAM offsets in  */
8259 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8260 /*                                                                          */
8261 /* Returns:                                                                 */
8262 /*   0 for success, positive value for failure.                             */
8263 /****************************************************************************/
8264 static int
8265 bce_sysctl_nvram_read(SYSCTL_HANDLER_ARGS)
8266 {
8267         struct bce_softc *sc = (struct bce_softc *)arg1;
8268         int error;
8269         u32 result;
8270         u32 val[1];
8271         u8 *data = (u8 *) val;
8272
8273         result = -1;
8274         error = sysctl_handle_int(oidp, &result, 0, req);
8275         if (error || (req->newptr == NULL))
8276                 return (error);
8277
8278         bce_nvram_read(sc, result, data, 4);
8279         BCE_PRINTF("offset 0x%08X = 0x%08X\n", result, bce_be32toh(val[0]));
8280
8281         return (error);
8282 }
8283
8284
8285 /****************************************************************************/
8286 /* Provides a sysctl interface to allow reading arbitrary registers in the  */
8287 /* device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                            */
8288 /*                                                                          */
8289 /* Returns:                                                                 */
8290 /*   0 for success, positive value for failure.                             */
8291 /****************************************************************************/
8292 static int
8293 bce_sysctl_reg_read(SYSCTL_HANDLER_ARGS)
8294 {
8295         struct bce_softc *sc = (struct bce_softc *)arg1;
8296         int error;
8297         u32 val, result;
8298
8299         result = -1;
8300         error = sysctl_handle_int(oidp, &result, 0, req);
8301         if (error || (req->newptr == NULL))
8302                 return (error);
8303
8304         /* Make sure the register is accessible. */
8305         if (result < 0x8000) {
8306                 val = REG_RD(sc, result);
8307                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8308         } else if (result < 0x0280000) {
8309                 val = REG_RD_IND(sc, result);
8310                 BCE_PRINTF("reg 0x%08X = 0x%08X\n", result, val);
8311         }
8312
8313         return (error);
8314 }
8315
8316
8317 /****************************************************************************/
8318 /* Provides a sysctl interface to allow reading arbitrary PHY registers in  */
8319 /* the device.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                        */
8320 /*                                                                          */
8321 /* Returns:                                                                 */
8322 /*   0 for success, positive value for failure.                             */
8323 /****************************************************************************/
8324 static int
8325 bce_sysctl_phy_read(SYSCTL_HANDLER_ARGS)
8326 {
8327         struct bce_softc *sc;
8328         device_t dev;
8329         int error, result;
8330         u16 val;
8331
8332         result = -1;
8333         error = sysctl_handle_int(oidp, &result, 0, req);
8334         if (error || (req->newptr == NULL))
8335                 return (error);
8336
8337         /* Make sure the register is accessible. */
8338         if (result < 0x20) {
8339                 sc = (struct bce_softc *)arg1;
8340                 dev = sc->bce_dev;
8341                 val = bce_miibus_read_reg(dev, sc->bce_phy_addr, result);
8342                 BCE_PRINTF("phy 0x%02X = 0x%04X\n", result, val);
8343         }
8344         return (error);
8345 }
8346
8347
8348 /****************************************************************************/
8349 /* Provides a sysctl interface to allow reading a CID.                      */
8350 /*                                                                          */
8351 /* Returns:                                                                 */
8352 /*   0 for success, positive value for failure.                             */
8353 /****************************************************************************/
8354 static int
8355 bce_sysctl_dump_ctx(SYSCTL_HANDLER_ARGS)
8356 {
8357         struct bce_softc *sc;
8358         int error, result;
8359
8360         result = -1;
8361         error = sysctl_handle_int(oidp, &result, 0, req);
8362         if (error || (req->newptr == NULL))
8363                 return (error);
8364
8365         /* Make sure the register is accessible. */
8366         if (result <= TX_CID) {
8367                 sc = (struct bce_softc *)arg1;
8368                 bce_dump_ctx(sc, result);
8369         }
8370
8371         return (error);
8372 }
8373
8374
8375  /****************************************************************************/
8376 /* Provides a sysctl interface to forcing the driver to dump state and      */
8377 /* enter the debugger.  DO NOT ENABLE ON PRODUCTION SYSTEMS!                */
8378 /*                                                                          */
8379 /* Returns:                                                                 */
8380 /*   0 for success, positive value for failure.                             */
8381 /****************************************************************************/
8382 static int
8383 bce_sysctl_breakpoint(SYSCTL_HANDLER_ARGS)
8384 {
8385         int error;
8386         int result;
8387         struct bce_softc *sc;
8388
8389         result = -1;
8390         error = sysctl_handle_int(oidp, &result, 0, req);
8391
8392         if (error || !req->newptr)
8393                 return (error);
8394
8395         if (result == 1) {
8396                 sc = (struct bce_softc *)arg1;
8397                 bce_breakpoint(sc);
8398         }
8399
8400         return error;
8401 }
8402 #endif
8403
8404
8405 /****************************************************************************/
8406 /* Adds any sysctl parameters for tuning or debugging purposes.             */
8407 /*                                                                          */
8408 /* Returns:                                                                 */
8409 /*   0 for success, positive value for failure.                             */
8410 /****************************************************************************/
8411 static void
8412 bce_add_sysctls(struct bce_softc *sc)
8413 {
8414         struct sysctl_ctx_list *ctx;
8415         struct sysctl_oid_list *children;
8416
8417         DBENTER(BCE_VERBOSE_MISC);
8418
8419         ctx = device_get_sysctl_ctx(sc->bce_dev);
8420         children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->bce_dev));
8421
8422 #ifdef BCE_DEBUG
8423         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8424             "l2fhdr_error_sim_control",
8425             CTLFLAG_RW, &l2fhdr_error_sim_control,
8426             0, "Debug control to force l2fhdr errors");
8427
8428         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8429             "l2fhdr_error_sim_count",
8430             CTLFLAG_RD, &sc->l2fhdr_error_sim_count,
8431             0, "Number of simulated l2_fhdr errors");
8432 #endif
8433
8434         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8435             "l2fhdr_error_count",
8436             CTLFLAG_RD, &sc->l2fhdr_error_count,
8437             0, "Number of l2_fhdr errors");
8438
8439 #ifdef BCE_DEBUG
8440         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8441             "mbuf_alloc_failed_sim_control",
8442             CTLFLAG_RW, &mbuf_alloc_failed_sim_control,
8443             0, "Debug control to force mbuf allocation failures");
8444
8445         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8446             "mbuf_alloc_failed_sim_count",
8447             CTLFLAG_RD, &sc->mbuf_alloc_failed_sim_count,
8448             0, "Number of simulated mbuf cluster allocation failures");
8449 #endif
8450
8451         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8452             "mbuf_alloc_failed_count",
8453             CTLFLAG_RD, &sc->mbuf_alloc_failed_count,
8454             0, "Number of mbuf allocation failures");
8455
8456         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8457             "mbuf_frag_count",
8458             CTLFLAG_RD, &sc->mbuf_frag_count,
8459             0, "Number of fragmented mbufs");
8460
8461 #ifdef BCE_DEBUG
8462         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8463             "dma_map_addr_failed_sim_control",
8464             CTLFLAG_RW, &dma_map_addr_failed_sim_control,
8465             0, "Debug control to force DMA mapping failures");
8466
8467         /* ToDo: Figure out how to update this value in bce_dma_map_addr(). */
8468         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8469             "dma_map_addr_failed_sim_count",
8470             CTLFLAG_RD, &sc->dma_map_addr_failed_sim_count,
8471             0, "Number of simulated DMA mapping failures");
8472
8473 #endif
8474
8475         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8476             "dma_map_addr_rx_failed_count",
8477             CTLFLAG_RD, &sc->dma_map_addr_rx_failed_count,
8478             0, "Number of RX DMA mapping failures");
8479
8480         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8481             "dma_map_addr_tx_failed_count",
8482             CTLFLAG_RD, &sc->dma_map_addr_tx_failed_count,
8483             0, "Number of TX DMA mapping failures");
8484
8485 #ifdef BCE_DEBUG
8486         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8487             "unexpected_attention_sim_control",
8488             CTLFLAG_RW, &unexpected_attention_sim_control,
8489             0, "Debug control to simulate unexpected attentions");
8490
8491         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8492             "unexpected_attention_sim_count",
8493             CTLFLAG_RW, &sc->unexpected_attention_sim_count,
8494             0, "Number of simulated unexpected attentions");
8495 #endif
8496
8497         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8498             "unexpected_attention_count",
8499             CTLFLAG_RW, &sc->unexpected_attention_count,
8500             0, "Number of unexpected attentions");
8501
8502 #ifdef BCE_DEBUG
8503         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8504             "debug_bootcode_running_failure",
8505             CTLFLAG_RW, &bootcode_running_failure_sim_control,
8506             0, "Debug control to force bootcode running failures");
8507
8508         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8509             "rx_low_watermark",
8510             CTLFLAG_RD, &sc->rx_low_watermark,
8511             0, "Lowest level of free rx_bd's");
8512
8513         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8514             "rx_empty_count",
8515             CTLFLAG_RD, &sc->rx_empty_count,
8516             0, "Number of times the RX chain was empty");
8517
8518         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8519             "tx_hi_watermark",
8520             CTLFLAG_RD, &sc->tx_hi_watermark,
8521             0, "Highest level of used tx_bd's");
8522
8523         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8524             "tx_full_count",
8525             CTLFLAG_RD, &sc->tx_full_count,
8526             0, "Number of times the TX chain was full");
8527
8528         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8529             "tso_frames_requested",
8530             CTLFLAG_RD, &sc->tso_frames_requested,
8531             0, "Number of TSO frames requested");
8532
8533         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8534             "tso_frames_completed",
8535             CTLFLAG_RD, &sc->tso_frames_completed,
8536             0, "Number of TSO frames completed");
8537
8538         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8539             "tso_frames_failed",
8540             CTLFLAG_RD, &sc->tso_frames_failed,
8541             0, "Number of TSO frames failed");
8542
8543         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8544             "csum_offload_ip",
8545             CTLFLAG_RD, &sc->csum_offload_ip,
8546             0, "Number of IP checksum offload frames");
8547
8548         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8549             "csum_offload_tcp_udp",
8550             CTLFLAG_RD, &sc->csum_offload_tcp_udp,
8551             0, "Number of TCP/UDP checksum offload frames");
8552
8553         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8554             "vlan_tagged_frames_rcvd",
8555             CTLFLAG_RD, &sc->vlan_tagged_frames_rcvd,
8556             0, "Number of VLAN tagged frames received");
8557
8558         SYSCTL_ADD_INT(ctx, children, OID_AUTO,
8559             "vlan_tagged_frames_stripped",
8560             CTLFLAG_RD, &sc->vlan_tagged_frames_stripped,
8561             0, "Number of VLAN tagged frames stripped");
8562
8563         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8564             "interrupts_rx",
8565             CTLFLAG_RD, &sc->interrupts_rx,
8566             0, "Number of RX interrupts");
8567
8568         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8569             "interrupts_tx",
8570             CTLFLAG_RD, &sc->interrupts_tx,
8571             0, "Number of TX interrupts");
8572 #endif
8573
8574         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8575             "stat_IfHcInOctets",
8576             CTLFLAG_RD, &sc->stat_IfHCInOctets,
8577             "Bytes received");
8578
8579         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8580             "stat_IfHCInBadOctets",
8581             CTLFLAG_RD, &sc->stat_IfHCInBadOctets,
8582             "Bad bytes received");
8583
8584         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8585             "stat_IfHCOutOctets",
8586             CTLFLAG_RD, &sc->stat_IfHCOutOctets,
8587             "Bytes sent");
8588
8589         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8590             "stat_IfHCOutBadOctets",
8591             CTLFLAG_RD, &sc->stat_IfHCOutBadOctets,
8592             "Bad bytes sent");
8593
8594         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8595             "stat_IfHCInUcastPkts",
8596             CTLFLAG_RD, &sc->stat_IfHCInUcastPkts,
8597             "Unicast packets received");
8598
8599         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8600             "stat_IfHCInMulticastPkts",
8601             CTLFLAG_RD, &sc->stat_IfHCInMulticastPkts,
8602             "Multicast packets received");
8603
8604         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8605             "stat_IfHCInBroadcastPkts",
8606             CTLFLAG_RD, &sc->stat_IfHCInBroadcastPkts,
8607             "Broadcast packets received");
8608
8609         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8610             "stat_IfHCOutUcastPkts",
8611             CTLFLAG_RD, &sc->stat_IfHCOutUcastPkts,
8612             "Unicast packets sent");
8613
8614         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8615             "stat_IfHCOutMulticastPkts",
8616             CTLFLAG_RD, &sc->stat_IfHCOutMulticastPkts,
8617             "Multicast packets sent");
8618
8619         SYSCTL_ADD_ULONG(ctx, children, OID_AUTO,
8620             "stat_IfHCOutBroadcastPkts",
8621             CTLFLAG_RD, &sc->stat_IfHCOutBroadcastPkts,
8622             "Broadcast packets sent");
8623
8624         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8625             "stat_emac_tx_stat_dot3statsinternalmactransmiterrors",
8626             CTLFLAG_RD, &sc->stat_emac_tx_stat_dot3statsinternalmactransmiterrors,
8627             0, "Internal MAC transmit errors");
8628
8629         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8630             "stat_Dot3StatsCarrierSenseErrors",
8631             CTLFLAG_RD, &sc->stat_Dot3StatsCarrierSenseErrors,
8632             0, "Carrier sense errors");
8633
8634         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8635             "stat_Dot3StatsFCSErrors",
8636             CTLFLAG_RD, &sc->stat_Dot3StatsFCSErrors,
8637             0, "Frame check sequence errors");
8638
8639         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8640             "stat_Dot3StatsAlignmentErrors",
8641             CTLFLAG_RD, &sc->stat_Dot3StatsAlignmentErrors,
8642             0, "Alignment errors");
8643
8644         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8645             "stat_Dot3StatsSingleCollisionFrames",
8646             CTLFLAG_RD, &sc->stat_Dot3StatsSingleCollisionFrames,
8647             0, "Single Collision Frames");
8648
8649         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8650             "stat_Dot3StatsMultipleCollisionFrames",
8651             CTLFLAG_RD, &sc->stat_Dot3StatsMultipleCollisionFrames,
8652             0, "Multiple Collision Frames");
8653
8654         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8655             "stat_Dot3StatsDeferredTransmissions",
8656             CTLFLAG_RD, &sc->stat_Dot3StatsDeferredTransmissions,
8657             0, "Deferred Transmissions");
8658
8659         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8660             "stat_Dot3StatsExcessiveCollisions",
8661             CTLFLAG_RD, &sc->stat_Dot3StatsExcessiveCollisions,
8662             0, "Excessive Collisions");
8663
8664         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8665             "stat_Dot3StatsLateCollisions",
8666             CTLFLAG_RD, &sc->stat_Dot3StatsLateCollisions,
8667             0, "Late Collisions");
8668
8669         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8670             "stat_EtherStatsCollisions",
8671             CTLFLAG_RD, &sc->stat_EtherStatsCollisions,
8672             0, "Collisions");
8673
8674         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8675             "stat_EtherStatsFragments",
8676             CTLFLAG_RD, &sc->stat_EtherStatsFragments,
8677             0, "Fragments");
8678
8679         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8680             "stat_EtherStatsJabbers",
8681             CTLFLAG_RD, &sc->stat_EtherStatsJabbers,
8682             0, "Jabbers");
8683
8684         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8685             "stat_EtherStatsUndersizePkts",
8686             CTLFLAG_RD, &sc->stat_EtherStatsUndersizePkts,
8687             0, "Undersize packets");
8688
8689         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8690             "stat_EtherStatsOversizePkts",
8691             CTLFLAG_RD, &sc->stat_EtherStatsOversizePkts,
8692             0, "stat_EtherStatsOversizePkts");
8693
8694         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8695             "stat_EtherStatsPktsRx64Octets",
8696             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx64Octets,
8697             0, "Bytes received in 64 byte packets");
8698
8699         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8700             "stat_EtherStatsPktsRx65Octetsto127Octets",
8701             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx65Octetsto127Octets,
8702             0, "Bytes received in 65 to 127 byte packets");
8703
8704         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8705             "stat_EtherStatsPktsRx128Octetsto255Octets",
8706             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx128Octetsto255Octets,
8707             0, "Bytes received in 128 to 255 byte packets");
8708
8709         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8710             "stat_EtherStatsPktsRx256Octetsto511Octets",
8711             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx256Octetsto511Octets,
8712             0, "Bytes received in 256 to 511 byte packets");
8713
8714         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8715             "stat_EtherStatsPktsRx512Octetsto1023Octets",
8716             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx512Octetsto1023Octets,
8717             0, "Bytes received in 512 to 1023 byte packets");
8718
8719         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8720             "stat_EtherStatsPktsRx1024Octetsto1522Octets",
8721             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1024Octetsto1522Octets,
8722             0, "Bytes received in 1024 t0 1522 byte packets");
8723
8724         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8725             "stat_EtherStatsPktsRx1523Octetsto9022Octets",
8726             CTLFLAG_RD, &sc->stat_EtherStatsPktsRx1523Octetsto9022Octets,
8727             0, "Bytes received in 1523 to 9022 byte packets");
8728
8729         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8730             "stat_EtherStatsPktsTx64Octets",
8731             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx64Octets,
8732             0, "Bytes sent in 64 byte packets");
8733
8734         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8735             "stat_EtherStatsPktsTx65Octetsto127Octets",
8736             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx65Octetsto127Octets,
8737             0, "Bytes sent in 65 to 127 byte packets");
8738
8739         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8740             "stat_EtherStatsPktsTx128Octetsto255Octets",
8741             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx128Octetsto255Octets,
8742             0, "Bytes sent in 128 to 255 byte packets");
8743
8744         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8745             "stat_EtherStatsPktsTx256Octetsto511Octets",
8746             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx256Octetsto511Octets,
8747             0, "Bytes sent in 256 to 511 byte packets");
8748
8749         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8750             "stat_EtherStatsPktsTx512Octetsto1023Octets",
8751             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx512Octetsto1023Octets,
8752             0, "Bytes sent in 512 to 1023 byte packets");
8753
8754         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8755             "stat_EtherStatsPktsTx1024Octetsto1522Octets",
8756             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1024Octetsto1522Octets,
8757             0, "Bytes sent in 1024 to 1522 byte packets");
8758
8759         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8760             "stat_EtherStatsPktsTx1523Octetsto9022Octets",
8761             CTLFLAG_RD, &sc->stat_EtherStatsPktsTx1523Octetsto9022Octets,
8762             0, "Bytes sent in 1523 to 9022 byte packets");
8763
8764         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8765             "stat_XonPauseFramesReceived",
8766             CTLFLAG_RD, &sc->stat_XonPauseFramesReceived,
8767             0, "XON pause frames receved");
8768
8769         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8770             "stat_XoffPauseFramesReceived",
8771             CTLFLAG_RD, &sc->stat_XoffPauseFramesReceived,
8772             0, "XOFF pause frames received");
8773
8774         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8775             "stat_OutXonSent",
8776             CTLFLAG_RD, &sc->stat_OutXonSent,
8777             0, "XON pause frames sent");
8778
8779         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8780             "stat_OutXoffSent",
8781             CTLFLAG_RD, &sc->stat_OutXoffSent,
8782             0, "XOFF pause frames sent");
8783
8784         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8785             "stat_FlowControlDone",
8786             CTLFLAG_RD, &sc->stat_FlowControlDone,
8787             0, "Flow control done");
8788
8789         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8790             "stat_MacControlFramesReceived",
8791             CTLFLAG_RD, &sc->stat_MacControlFramesReceived,
8792             0, "MAC control frames received");
8793
8794         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8795             "stat_XoffStateEntered",
8796             CTLFLAG_RD, &sc->stat_XoffStateEntered,
8797             0, "XOFF state entered");
8798
8799         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8800             "stat_IfInFramesL2FilterDiscards",
8801             CTLFLAG_RD, &sc->stat_IfInFramesL2FilterDiscards,
8802             0, "Received L2 packets discarded");
8803
8804         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8805             "stat_IfInRuleCheckerDiscards",
8806             CTLFLAG_RD, &sc->stat_IfInRuleCheckerDiscards,
8807             0, "Received packets discarded by rule");
8808
8809         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8810             "stat_IfInFTQDiscards",
8811             CTLFLAG_RD, &sc->stat_IfInFTQDiscards,
8812             0, "Received packet FTQ discards");
8813
8814         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8815             "stat_IfInMBUFDiscards",
8816             CTLFLAG_RD, &sc->stat_IfInMBUFDiscards,
8817             0, "Received packets discarded due to lack "
8818             "of controller buffer memory");
8819
8820         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8821             "stat_IfInRuleCheckerP4Hit",
8822             CTLFLAG_RD, &sc->stat_IfInRuleCheckerP4Hit,
8823             0, "Received packets rule checker hits");
8824
8825         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8826             "stat_CatchupInRuleCheckerDiscards",
8827             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerDiscards,
8828             0, "Received packets discarded in Catchup path");
8829
8830         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8831             "stat_CatchupInFTQDiscards",
8832             CTLFLAG_RD, &sc->stat_CatchupInFTQDiscards,
8833             0, "Received packets discarded in FTQ in Catchup path");
8834
8835         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8836             "stat_CatchupInMBUFDiscards",
8837             CTLFLAG_RD, &sc->stat_CatchupInMBUFDiscards,
8838             0, "Received packets discarded in controller "
8839             "buffer memory in Catchup path");
8840
8841         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8842             "stat_CatchupInRuleCheckerP4Hit",
8843             CTLFLAG_RD, &sc->stat_CatchupInRuleCheckerP4Hit,
8844             0, "Received packets rule checker hits in Catchup path");
8845
8846         SYSCTL_ADD_UINT(ctx, children, OID_AUTO,
8847             "com_no_buffers",
8848             CTLFLAG_RD, &sc->com_no_buffers,
8849             0, "Valid packets received but no RX buffers available");
8850
8851 #ifdef BCE_DEBUG
8852         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8853             "driver_state", CTLTYPE_INT | CTLFLAG_RW,
8854             (void *)sc, 0,
8855             bce_sysctl_driver_state, "I", "Drive state information");
8856
8857         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8858             "hw_state", CTLTYPE_INT | CTLFLAG_RW,
8859             (void *)sc, 0,
8860             bce_sysctl_hw_state, "I", "Hardware state information");
8861
8862         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8863             "status_block", CTLTYPE_INT | CTLFLAG_RW,
8864             (void *)sc, 0,
8865             bce_sysctl_status_block, "I", "Dump status block");
8866
8867         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8868             "stats_block", CTLTYPE_INT | CTLFLAG_RW,
8869             (void *)sc, 0,
8870             bce_sysctl_stats_block, "I", "Dump statistics block");
8871
8872         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8873             "stats_clear", CTLTYPE_INT | CTLFLAG_RW,
8874             (void *)sc, 0,
8875             bce_sysctl_stats_clear, "I", "Clear statistics block");
8876
8877         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8878             "bc_state", CTLTYPE_INT | CTLFLAG_RW,
8879             (void *)sc, 0,
8880             bce_sysctl_bc_state, "I", "Bootcode state information");
8881
8882         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8883             "dump_rx_bd_chain", CTLTYPE_INT | CTLFLAG_RW,
8884             (void *)sc, 0,
8885             bce_sysctl_dump_rx_bd_chain, "I", "Dump RX BD chain");
8886
8887         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8888             "dump_rx_mbuf_chain", CTLTYPE_INT | CTLFLAG_RW,
8889             (void *)sc, 0,
8890             bce_sysctl_dump_rx_mbuf_chain, "I", "Dump RX MBUF chain");
8891
8892         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8893             "dump_tx_chain", CTLTYPE_INT | CTLFLAG_RW,
8894             (void *)sc, 0,
8895             bce_sysctl_dump_tx_chain, "I", "Dump tx_bd chain");
8896
8897 #ifdef BCE_JUMBO_HDRSPLIT
8898         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8899             "dump_pg_chain", CTLTYPE_INT | CTLFLAG_RW,
8900             (void *)sc, 0,
8901             bce_sysctl_dump_pg_chain, "I", "Dump page chain");
8902 #endif
8903         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8904             "dump_ctx", CTLTYPE_INT | CTLFLAG_RW,
8905             (void *)sc, 0,
8906             bce_sysctl_dump_ctx, "I", "Dump context memory");
8907
8908         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8909             "breakpoint", CTLTYPE_INT | CTLFLAG_RW,
8910             (void *)sc, 0,
8911             bce_sysctl_breakpoint, "I", "Driver breakpoint");
8912
8913         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8914             "reg_read", CTLTYPE_INT | CTLFLAG_RW,
8915             (void *)sc, 0,
8916             bce_sysctl_reg_read, "I", "Register read");
8917
8918         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8919             "nvram_read", CTLTYPE_INT | CTLFLAG_RW,
8920             (void *)sc, 0,
8921             bce_sysctl_nvram_read, "I", "NVRAM read");
8922
8923         SYSCTL_ADD_PROC(ctx, children, OID_AUTO,
8924             "phy_read", CTLTYPE_INT | CTLFLAG_RW,
8925             (void *)sc, 0,
8926             bce_sysctl_phy_read, "I", "PHY register read");
8927
8928 #endif
8929
8930         DBEXIT(BCE_VERBOSE_MISC);
8931 }
8932
8933
8934 /****************************************************************************/
8935 /* BCE Debug Routines                                                       */
8936 /****************************************************************************/
8937 #ifdef BCE_DEBUG
8938
8939 /****************************************************************************/
8940 /* Freezes the controller to allow for a cohesive state dump.               */
8941 /*                                                                          */
8942 /* Returns:                                                                 */
8943 /*   Nothing.                                                               */
8944 /****************************************************************************/
8945 static __attribute__ ((noinline)) void
8946 bce_freeze_controller(struct bce_softc *sc)
8947 {
8948         u32 val;
8949         val = REG_RD(sc, BCE_MISC_COMMAND);
8950         val |= BCE_MISC_COMMAND_DISABLE_ALL;
8951         REG_WR(sc, BCE_MISC_COMMAND, val);
8952 }
8953
8954
8955 /****************************************************************************/
8956 /* Unfreezes the controller after a freeze operation.  This may not always  */
8957 /* work and the controller will require a reset!                            */
8958 /*                                                                          */
8959 /* Returns:                                                                 */
8960 /*   Nothing.                                                               */
8961 /****************************************************************************/
8962 static __attribute__ ((noinline)) void
8963 bce_unfreeze_controller(struct bce_softc *sc)
8964 {
8965         u32 val;
8966         val = REG_RD(sc, BCE_MISC_COMMAND);
8967         val |= BCE_MISC_COMMAND_ENABLE_ALL;
8968         REG_WR(sc, BCE_MISC_COMMAND, val);
8969 }
8970
8971
8972 /****************************************************************************/
8973 /* Prints out Ethernet frame information from an mbuf.                      */
8974 /*                                                                          */
8975 /* Partially decode an Ethernet frame to look at some important headers.    */
8976 /*                                                                          */
8977 /* Returns:                                                                 */
8978 /*   Nothing.                                                               */
8979 /****************************************************************************/
8980 static __attribute__ ((noinline)) void
8981 bce_dump_enet(struct bce_softc *sc, struct mbuf *m)
8982 {
8983         struct ether_vlan_header *eh;
8984         u16 etype;
8985         int ehlen;
8986         struct ip *ip;
8987         struct tcphdr *th;
8988         struct udphdr *uh;
8989         struct arphdr *ah;
8990
8991         BCE_PRINTF(
8992             "-----------------------------"
8993             " Frame Decode "
8994             "-----------------------------\n");
8995
8996         eh = mtod(m, struct ether_vlan_header *);
8997
8998         /* Handle VLAN encapsulation if present. */
8999         if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
9000                 etype = ntohs(eh->evl_proto);
9001                 ehlen = ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN;
9002         } else {
9003                 etype = ntohs(eh->evl_encap_proto);
9004                 ehlen = ETHER_HDR_LEN;
9005         }
9006
9007         /* ToDo: Add VLAN output. */
9008         BCE_PRINTF("enet: dest = %6D, src = %6D, type = 0x%04X, hlen = %d\n",
9009             eh->evl_dhost, ":", eh->evl_shost, ":", etype, ehlen);
9010
9011         switch (etype) {
9012         case ETHERTYPE_IP:
9013                 ip = (struct ip *)(m->m_data + ehlen);
9014                 BCE_PRINTF("--ip: dest = 0x%08X , src = 0x%08X, "
9015                     "len = %d bytes, protocol = 0x%02X, xsum = 0x%04X\n",
9016                     ntohl(ip->ip_dst.s_addr), ntohl(ip->ip_src.s_addr),
9017                     ntohs(ip->ip_len), ip->ip_p, ntohs(ip->ip_sum));
9018
9019                 switch (ip->ip_p) {
9020                 case IPPROTO_TCP:
9021                         th = (struct tcphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9022                         BCE_PRINTF("-tcp: dest = %d, src = %d, hlen = "
9023                             "%d bytes, flags = 0x%b, csum = 0x%04X\n",
9024                             ntohs(th->th_dport), ntohs(th->th_sport),
9025                             (th->th_off << 2), th->th_flags,
9026                             "\20\10CWR\07ECE\06URG\05ACK\04PSH\03RST"
9027                             "\02SYN\01FIN", ntohs(th->th_sum));
9028                         break;
9029                 case IPPROTO_UDP:
9030                         uh = (struct udphdr *)((caddr_t)ip + (ip->ip_hl << 2));
9031                         BCE_PRINTF("-udp: dest = %d, src = %d, len = %d "
9032                             "bytes, csum = 0x%04X\n", ntohs(uh->uh_dport),
9033                             ntohs(uh->uh_sport), ntohs(uh->uh_ulen),
9034                             ntohs(uh->uh_sum));
9035                         break;
9036                 case IPPROTO_ICMP:
9037                         BCE_PRINTF("icmp:\n");
9038                         break;
9039                 default:
9040                         BCE_PRINTF("----: Other IP protocol.\n");
9041                         }
9042                 break;
9043         case ETHERTYPE_IPV6:
9044                 BCE_PRINTF("ipv6: No decode supported.\n");
9045                 break;
9046         case ETHERTYPE_ARP:
9047                 BCE_PRINTF("-arp: ");
9048                 ah = (struct arphdr *) (m->m_data + ehlen);
9049                 switch (ntohs(ah->ar_op)) {
9050                 case ARPOP_REVREQUEST:
9051                         printf("reverse ARP request\n");
9052                         break;
9053                 case ARPOP_REVREPLY:
9054                         printf("reverse ARP reply\n");
9055                         break;
9056                 case ARPOP_REQUEST:
9057                         printf("ARP request\n");
9058                         break;
9059                 case ARPOP_REPLY:
9060                         printf("ARP reply\n");
9061                         break;
9062                 default:
9063                         printf("other ARP operation\n");
9064                 }
9065                 break;
9066         default:
9067                 BCE_PRINTF("----: Other protocol.\n");
9068         }
9069
9070         BCE_PRINTF(
9071                 "-----------------------------"
9072                 "--------------"
9073                 "-----------------------------\n");
9074 }
9075
9076
9077 /****************************************************************************/
9078 /* Prints out information about an mbuf.                                    */
9079 /*                                                                          */
9080 /* Returns:                                                                 */
9081 /*   Nothing.                                                               */
9082 /****************************************************************************/
9083 static __attribute__ ((noinline)) void
9084 bce_dump_mbuf(struct bce_softc *sc, struct mbuf *m)
9085 {
9086         struct mbuf *mp = m;
9087
9088         if (m == NULL) {
9089                 BCE_PRINTF("mbuf: null pointer\n");
9090                 return;
9091         }
9092
9093         while (mp) {
9094                 BCE_PRINTF("mbuf: %p, m_len = %d, m_flags = 0x%b, "
9095                     "m_data = %p\n", mp, mp->m_len, mp->m_flags,
9096                     "\20\1M_EXT\2M_PKTHDR\3M_EOR\4M_RDONLY", mp->m_data);
9097
9098                 if (mp->m_flags & M_PKTHDR) {
9099                         BCE_PRINTF("- m_pkthdr: len = %d, flags = 0x%b, "
9100                             "csum_flags = %b\n", mp->m_pkthdr.len,
9101                             mp->m_flags, "\20\12M_BCAST\13M_MCAST\14M_FRAG"
9102                             "\15M_FIRSTFRAG\16M_LASTFRAG\21M_VLANTAG"
9103                             "\22M_PROMISC\23M_NOFREE",
9104                             mp->m_pkthdr.csum_flags,
9105                             "\20\1CSUM_IP\2CSUM_TCP\3CSUM_UDP\4CSUM_IP_FRAGS"
9106                             "\5CSUM_FRAGMENT\6CSUM_TSO\11CSUM_IP_CHECKED"
9107                             "\12CSUM_IP_VALID\13CSUM_DATA_VALID"
9108                             "\14CSUM_PSEUDO_HDR");
9109                 }
9110
9111                 if (mp->m_flags & M_EXT) {
9112                         BCE_PRINTF("- m_ext: %p, ext_size = %d, type = ",
9113                             mp->m_ext.ext_buf, mp->m_ext.ext_size);
9114                         switch (mp->m_ext.ext_type) {
9115                         case EXT_CLUSTER:
9116                                 printf("EXT_CLUSTER\n"); break;
9117                         case EXT_SFBUF:
9118                                 printf("EXT_SFBUF\n"); break;
9119                         case EXT_JUMBO9:
9120                                 printf("EXT_JUMBO9\n"); break;
9121                         case EXT_JUMBO16:
9122                                 printf("EXT_JUMBO16\n"); break;
9123                         case EXT_PACKET:
9124                                 printf("EXT_PACKET\n"); break;
9125                         case EXT_MBUF:
9126                                 printf("EXT_MBUF\n"); break;
9127                         case EXT_NET_DRV:
9128                                 printf("EXT_NET_DRV\n"); break;
9129                         case EXT_MOD_TYPE:
9130                                 printf("EXT_MDD_TYPE\n"); break;
9131                         case EXT_DISPOSABLE:
9132                                 printf("EXT_DISPOSABLE\n"); break;
9133                         case EXT_EXTREF:
9134                                 printf("EXT_EXTREF\n"); break;
9135                         default:
9136                                 printf("UNKNOWN\n");
9137                         }
9138                 }
9139
9140                 mp = mp->m_next;
9141         }
9142 }
9143
9144
9145 /****************************************************************************/
9146 /* Prints out the mbufs in the TX mbuf chain.                               */
9147 /*                                                                          */
9148 /* Returns:                                                                 */
9149 /*   Nothing.                                                               */
9150 /****************************************************************************/
9151 static __attribute__ ((noinline)) void
9152 bce_dump_tx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9153 {
9154         struct mbuf *m;
9155
9156         BCE_PRINTF(
9157                 "----------------------------"
9158                 "  tx mbuf data  "
9159                 "----------------------------\n");
9160
9161         for (int i = 0; i < count; i++) {
9162                 m = sc->tx_mbuf_ptr[chain_prod];
9163                 BCE_PRINTF("txmbuf[0x%04X]\n", chain_prod);
9164                 bce_dump_mbuf(sc, m);
9165                 chain_prod = TX_CHAIN_IDX(NEXT_TX_BD(chain_prod));
9166         }
9167
9168         BCE_PRINTF(
9169                 "----------------------------"
9170                 "----------------"
9171                 "----------------------------\n");
9172 }
9173
9174
9175 /****************************************************************************/
9176 /* Prints out the mbufs in the RX mbuf chain.                               */
9177 /*                                                                          */
9178 /* Returns:                                                                 */
9179 /*   Nothing.                                                               */
9180 /****************************************************************************/
9181 static __attribute__ ((noinline)) void
9182 bce_dump_rx_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9183 {
9184         struct mbuf *m;
9185
9186         BCE_PRINTF(
9187                 "----------------------------"
9188                 "  rx mbuf data  "
9189                 "----------------------------\n");
9190
9191         for (int i = 0; i < count; i++) {
9192                 m = sc->rx_mbuf_ptr[chain_prod];
9193                 BCE_PRINTF("rxmbuf[0x%04X]\n", chain_prod);
9194                 bce_dump_mbuf(sc, m);
9195                 chain_prod = RX_CHAIN_IDX(NEXT_RX_BD(chain_prod));
9196         }
9197
9198
9199         BCE_PRINTF(
9200                 "----------------------------"
9201                 "----------------"
9202                 "----------------------------\n");
9203 }
9204
9205
9206 #ifdef BCE_JUMBO_HDRSPLIT
9207 /****************************************************************************/
9208 /* Prints out the mbufs in the mbuf page chain.                             */
9209 /*                                                                          */
9210 /* Returns:                                                                 */
9211 /*   Nothing.                                                               */
9212 /****************************************************************************/
9213 static __attribute__ ((noinline)) void
9214 bce_dump_pg_mbuf_chain(struct bce_softc *sc, u16 chain_prod, int count)
9215 {
9216         struct mbuf *m;
9217
9218         BCE_PRINTF(
9219                 "----------------------------"
9220                 "  pg mbuf data  "
9221                 "----------------------------\n");
9222
9223         for (int i = 0; i < count; i++) {
9224                 m = sc->pg_mbuf_ptr[chain_prod];
9225                 BCE_PRINTF("pgmbuf[0x%04X]\n", chain_prod);
9226                 bce_dump_mbuf(sc, m);
9227                 chain_prod = PG_CHAIN_IDX(NEXT_PG_BD(chain_prod));
9228         }
9229
9230
9231         BCE_PRINTF(
9232                 "----------------------------"
9233                 "----------------"
9234                 "----------------------------\n");
9235 }
9236 #endif
9237
9238
9239 /****************************************************************************/
9240 /* Prints out a tx_bd structure.                                            */
9241 /*                                                                          */
9242 /* Returns:                                                                 */
9243 /*   Nothing.                                                               */
9244 /****************************************************************************/
9245 static __attribute__ ((noinline)) void
9246 bce_dump_txbd(struct bce_softc *sc, int idx, struct tx_bd *txbd)
9247 {
9248         int i = 0;
9249
9250         if (idx > MAX_TX_BD)
9251                 /* Index out of range. */
9252                 BCE_PRINTF("tx_bd[0x%04X]: Invalid tx_bd index!\n", idx);
9253         else if ((idx & USABLE_TX_BD_PER_PAGE) == USABLE_TX_BD_PER_PAGE)
9254                 /* TX Chain page pointer. */
9255                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
9256                     "pointer\n", idx, txbd->tx_bd_haddr_hi,
9257                     txbd->tx_bd_haddr_lo);
9258         else {
9259                 /* Normal tx_bd entry. */
9260                 BCE_PRINTF("tx_bd[0x%04X]: haddr = 0x%08X:%08X, "
9261                     "mss_nbytes = 0x%08X, vlan tag = 0x%04X, flags = "
9262                     "0x%04X (", idx, txbd->tx_bd_haddr_hi,
9263                     txbd->tx_bd_haddr_lo, txbd->tx_bd_mss_nbytes,
9264                     txbd->tx_bd_vlan_tag, txbd->tx_bd_flags);
9265
9266                 if (txbd->tx_bd_flags & TX_BD_FLAGS_CONN_FAULT) {
9267                         if (i>0)
9268                                 printf("|");
9269                         printf("CONN_FAULT");
9270                         i++;
9271                 }
9272
9273                 if (txbd->tx_bd_flags & TX_BD_FLAGS_TCP_UDP_CKSUM) {
9274                         if (i>0)
9275                                 printf("|");
9276                         printf("TCP_UDP_CKSUM");
9277                         i++;
9278                 }
9279
9280                 if (txbd->tx_bd_flags & TX_BD_FLAGS_IP_CKSUM) {
9281                         if (i>0)
9282                                 printf("|");
9283                         printf("IP_CKSUM");
9284                         i++;
9285                 }
9286
9287                 if (txbd->tx_bd_flags & TX_BD_FLAGS_VLAN_TAG) {
9288                         if (i>0)
9289                                 printf("|");
9290                         printf("VLAN");
9291                         i++;
9292                 }
9293
9294                 if (txbd->tx_bd_flags & TX_BD_FLAGS_COAL_NOW) {
9295                         if (i>0)
9296                                 printf("|");
9297                         printf("COAL_NOW");
9298                         i++;
9299                 }
9300
9301                 if (txbd->tx_bd_flags & TX_BD_FLAGS_DONT_GEN_CRC) {
9302                         if (i>0)
9303                                 printf("|");
9304                         printf("DONT_GEN_CRC");
9305                         i++;
9306                 }
9307
9308                 if (txbd->tx_bd_flags & TX_BD_FLAGS_START) {
9309                         if (i>0)
9310                                 printf("|");
9311                         printf("START");
9312                         i++;
9313                 }
9314
9315                 if (txbd->tx_bd_flags & TX_BD_FLAGS_END) {
9316                         if (i>0)
9317                                 printf("|");
9318                         printf("END");
9319                         i++;
9320                 }
9321
9322                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_LSO) {
9323                         if (i>0)
9324                                 printf("|");
9325                         printf("LSO");
9326                         i++;
9327                 }
9328
9329                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_OPTION_WORD) {
9330                         if (i>0)
9331                                 printf("|");
9332                         printf("SW_OPTION=%d", ((txbd->tx_bd_flags &
9333                             TX_BD_FLAGS_SW_OPTION_WORD) >> 8)); i++;
9334                 }
9335
9336                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_FLAGS) {
9337                         if (i>0)
9338                                 printf("|");
9339                         printf("SW_FLAGS");
9340                         i++;
9341                 }
9342
9343                 if (txbd->tx_bd_flags & TX_BD_FLAGS_SW_SNAP) {
9344                         if (i>0)
9345                                 printf("|");
9346                         printf("SNAP)");
9347                 } else {
9348                         printf(")\n");
9349                 }
9350         }
9351 }
9352
9353
9354 /****************************************************************************/
9355 /* Prints out a rx_bd structure.                                            */
9356 /*                                                                          */
9357 /* Returns:                                                                 */
9358 /*   Nothing.                                                               */
9359 /****************************************************************************/
9360 static __attribute__ ((noinline)) void
9361 bce_dump_rxbd(struct bce_softc *sc, int idx, struct rx_bd *rxbd)
9362 {
9363         if (idx > MAX_RX_BD)
9364                 /* Index out of range. */
9365                 BCE_PRINTF("rx_bd[0x%04X]: Invalid rx_bd index!\n", idx);
9366         else if ((idx & USABLE_RX_BD_PER_PAGE) == USABLE_RX_BD_PER_PAGE)
9367                 /* RX Chain page pointer. */
9368                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, chain page "
9369                     "pointer\n", idx, rxbd->rx_bd_haddr_hi,
9370                     rxbd->rx_bd_haddr_lo);
9371         else
9372                 /* Normal rx_bd entry. */
9373                 BCE_PRINTF("rx_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = "
9374                     "0x%08X, flags = 0x%08X\n", idx, rxbd->rx_bd_haddr_hi,
9375                     rxbd->rx_bd_haddr_lo, rxbd->rx_bd_len,
9376                     rxbd->rx_bd_flags);
9377 }
9378
9379
9380 #ifdef BCE_JUMBO_HDRSPLIT
9381 /****************************************************************************/
9382 /* Prints out a rx_bd structure in the page chain.                          */
9383 /*                                                                          */
9384 /* Returns:                                                                 */
9385 /*   Nothing.                                                               */
9386 /****************************************************************************/
9387 static __attribute__ ((noinline)) void
9388 bce_dump_pgbd(struct bce_softc *sc, int idx, struct rx_bd *pgbd)
9389 {
9390         if (idx > MAX_PG_BD)
9391                 /* Index out of range. */
9392                 BCE_PRINTF("pg_bd[0x%04X]: Invalid pg_bd index!\n", idx);
9393         else if ((idx & USABLE_PG_BD_PER_PAGE) == USABLE_PG_BD_PER_PAGE)
9394                 /* Page Chain page pointer. */
9395                 BCE_PRINTF("px_bd[0x%04X]: haddr = 0x%08X:%08X, chain page pointer\n",
9396                         idx, pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo);
9397         else
9398                 /* Normal rx_bd entry. */
9399                 BCE_PRINTF("pg_bd[0x%04X]: haddr = 0x%08X:%08X, nbytes = 0x%08X, "
9400                         "flags = 0x%08X\n", idx,
9401                         pgbd->rx_bd_haddr_hi, pgbd->rx_bd_haddr_lo,
9402                         pgbd->rx_bd_len, pgbd->rx_bd_flags);
9403 }
9404 #endif
9405
9406
9407 /****************************************************************************/
9408 /* Prints out a l2_fhdr structure.                                          */
9409 /*                                                                          */
9410 /* Returns:                                                                 */
9411 /*   Nothing.                                                               */
9412 /****************************************************************************/
9413 static __attribute__ ((noinline)) void
9414 bce_dump_l2fhdr(struct bce_softc *sc, int idx, struct l2_fhdr *l2fhdr)
9415 {
9416         BCE_PRINTF("l2_fhdr[0x%04X]: status = 0x%b, "
9417                 "pkt_len = %d, vlan = 0x%04x, ip_xsum/hdr_len = 0x%04X, "
9418                 "tcp_udp_xsum = 0x%04X\n", idx,
9419                 l2fhdr->l2_fhdr_status, BCE_L2FHDR_PRINTFB,
9420                 l2fhdr->l2_fhdr_pkt_len, l2fhdr->l2_fhdr_vlan_tag,
9421                 l2fhdr->l2_fhdr_ip_xsum, l2fhdr->l2_fhdr_tcp_udp_xsum);
9422 }
9423
9424
9425 /****************************************************************************/
9426 /* Prints out context memory info.  (Only useful for CID 0 to 16.)          */
9427 /*                                                                          */
9428 /* Returns:                                                                 */
9429 /*   Nothing.                                                               */
9430 /****************************************************************************/
9431 static __attribute__ ((noinline)) void
9432 bce_dump_ctx(struct bce_softc *sc, u16 cid)
9433 {
9434         if (cid > TX_CID) {
9435                 BCE_PRINTF(" Unknown CID\n");
9436                 return;
9437         }
9438
9439         BCE_PRINTF(
9440             "----------------------------"
9441             "    CTX Data    "
9442             "----------------------------\n");
9443
9444         BCE_PRINTF("     0x%04X - (CID) Context ID\n", cid);
9445
9446         if (cid == RX_CID) {
9447                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BDIDX) host rx "
9448                    "producer index\n",
9449                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_HOST_BDIDX));
9450                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_BSEQ) host "
9451                     "byte sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
9452                     BCE_L2CTX_RX_HOST_BSEQ));
9453                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BSEQ) h/w byte sequence\n",
9454                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BSEQ));
9455                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_HI) h/w buffer "
9456                     "descriptor address\n",
9457                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_HI));
9458                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDHADDR_LO) h/w buffer "
9459                     "descriptor address\n",
9460                     CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_RX_NX_BDHADDR_LO));
9461                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_BDIDX) h/w rx consumer "
9462                     "index\n", CTX_RD(sc, GET_CID_ADDR(cid),
9463                     BCE_L2CTX_RX_NX_BDIDX));
9464                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_HOST_PG_BDIDX) host page "
9465                     "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
9466                     BCE_L2CTX_RX_HOST_PG_BDIDX));
9467                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_PG_BUF_SIZE) host rx_bd/page "
9468                     "buffer size\n", CTX_RD(sc, GET_CID_ADDR(cid),
9469                     BCE_L2CTX_RX_PG_BUF_SIZE));
9470                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_HI) h/w page "
9471                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
9472                     BCE_L2CTX_RX_NX_PG_BDHADDR_HI));
9473                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDHADDR_LO) h/w page "
9474                     "chain address\n", CTX_RD(sc, GET_CID_ADDR(cid),
9475                     BCE_L2CTX_RX_NX_PG_BDHADDR_LO));
9476                 BCE_PRINTF(" 0x%08X - (L2CTX_RX_NX_PG_BDIDX) h/w page "
9477                     "consumer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
9478                     BCE_L2CTX_RX_NX_PG_BDIDX));
9479         } else if (cid == TX_CID) {
9480                 if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
9481                     (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
9482                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE_XI) ctx type\n",
9483                             CTX_RD(sc, GET_CID_ADDR(cid),
9484                             BCE_L2CTX_TX_TYPE_XI));
9485                         BCE_PRINTF(" 0x%08X - (L2CTX_CMD_TX_TYPE_XI) ctx "
9486                             "cmd\n", CTX_RD(sc, GET_CID_ADDR(cid),
9487                             BCE_L2CTX_TX_CMD_TYPE_XI));
9488                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI_XI) "
9489                             "h/w buffer descriptor address\n",
9490                             CTX_RD(sc, GET_CID_ADDR(cid),
9491                             BCE_L2CTX_TX_TBDR_BHADDR_HI_XI));
9492                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO_XI) "
9493                             "h/w buffer descriptor address\n",
9494                             CTX_RD(sc, GET_CID_ADDR(cid),
9495                             BCE_L2CTX_TX_TBDR_BHADDR_LO_XI));
9496                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX_XI) "
9497                             "host producer index\n",
9498                             CTX_RD(sc, GET_CID_ADDR(cid),
9499                             BCE_L2CTX_TX_HOST_BIDX_XI));
9500                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ_XI) "
9501                             "host byte sequence\n",
9502                             CTX_RD(sc, GET_CID_ADDR(cid),
9503                             BCE_L2CTX_TX_HOST_BSEQ_XI));
9504                 } else {
9505                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TYPE) ctx type\n",
9506                             CTX_RD(sc, GET_CID_ADDR(cid), BCE_L2CTX_TX_TYPE));
9507                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_CMD_TYPE) ctx cmd\n",
9508                             CTX_RD(sc, GET_CID_ADDR(cid),
9509                             BCE_L2CTX_TX_CMD_TYPE));
9510                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BDHADDR_HI) "
9511                             "h/w buffer descriptor address\n",
9512                             CTX_RD(sc, GET_CID_ADDR(cid),
9513                             BCE_L2CTX_TX_TBDR_BHADDR_HI));
9514                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_TBDR_BHADDR_LO) "
9515                             "h/w buffer descriptor address\n",
9516                             CTX_RD(sc, GET_CID_ADDR(cid),
9517                             BCE_L2CTX_TX_TBDR_BHADDR_LO));
9518                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BIDX) host "
9519                             "producer index\n", CTX_RD(sc, GET_CID_ADDR(cid),
9520                             BCE_L2CTX_TX_HOST_BIDX));
9521                         BCE_PRINTF(" 0x%08X - (L2CTX_TX_HOST_BSEQ) host byte "
9522                             "sequence\n", CTX_RD(sc, GET_CID_ADDR(cid),
9523                             BCE_L2CTX_TX_HOST_BSEQ));
9524                 }
9525         }
9526
9527         BCE_PRINTF(
9528            "----------------------------"
9529            "    Raw CTX     "
9530            "----------------------------\n");
9531
9532         for (int i = 0x0; i < 0x300; i += 0x10) {
9533                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n", i,
9534                    CTX_RD(sc, GET_CID_ADDR(cid), i),
9535                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x4),
9536                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0x8),
9537                    CTX_RD(sc, GET_CID_ADDR(cid), i + 0xc));
9538         }
9539
9540
9541         BCE_PRINTF(
9542            "----------------------------"
9543            "----------------"
9544            "----------------------------\n");
9545 }
9546
9547
9548 /****************************************************************************/
9549 /* Prints out the FTQ data.                                                 */
9550 /*                                                                          */
9551 /* Returns:                                                                */
9552 /*   Nothing.                                                               */
9553 /****************************************************************************/
9554 static __attribute__ ((noinline)) void
9555 bce_dump_ftqs(struct bce_softc *sc)
9556 {
9557         u32 cmd, ctl, cur_depth, max_depth, valid_cnt, val;
9558
9559         BCE_PRINTF(
9560             "----------------------------"
9561             "    FTQ Data    "
9562             "----------------------------\n");
9563
9564         BCE_PRINTF("   FTQ    Command    Control   Depth_Now  "
9565             "Max_Depth  Valid_Cnt \n");
9566         BCE_PRINTF(" ------- ---------- ---------- ---------- "
9567             "---------- ----------\n");
9568
9569         /* Setup the generic statistic counters for the FTQ valid count. */
9570         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PPQ_VALID_CNT << 24) |
9571             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPCQ_VALID_CNT  << 16) |
9572             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RXPQ_VALID_CNT   <<  8) |
9573             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RLUPQ_VALID_CNT);
9574         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
9575
9576         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TSCHQ_VALID_CNT  << 24) |
9577             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RDMAQ_VALID_CNT  << 16) |
9578             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PTQ_VALID_CNT <<  8) |
9579             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PMQ_VALID_CNT);
9580         REG_WR(sc, BCE_HC_STAT_GEN_SEL_1, val);
9581
9582         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TPATQ_VALID_CNT  << 24) |
9583             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TDMAQ_VALID_CNT  << 16) |
9584             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TXPQ_VALID_CNT   <<  8) |
9585             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TBDRQ_VALID_CNT);
9586         REG_WR(sc, BCE_HC_STAT_GEN_SEL_2, val);
9587
9588         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMQ_VALID_CNT   << 24) |
9589             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMTQ_VALID_CNT  << 16) |
9590             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_COMXQ_VALID_CNT  <<  8) |
9591             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_TASQ_VALID_CNT);
9592         REG_WR(sc, BCE_HC_STAT_GEN_SEL_3, val);
9593
9594         /* Input queue to the Receive Lookup state machine */
9595         cmd = REG_RD(sc, BCE_RLUP_FTQ_CMD);
9596         ctl = REG_RD(sc, BCE_RLUP_FTQ_CTL);
9597         cur_depth = (ctl & BCE_RLUP_FTQ_CTL_CUR_DEPTH) >> 22;
9598         max_depth = (ctl & BCE_RLUP_FTQ_CTL_MAX_DEPTH) >> 12;
9599         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
9600         BCE_PRINTF(" RLUP    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9601             cmd, ctl, cur_depth, max_depth, valid_cnt);
9602
9603         /* Input queue to the Receive Processor */
9604         cmd = REG_RD_IND(sc, BCE_RXP_FTQ_CMD);
9605         ctl = REG_RD_IND(sc, BCE_RXP_FTQ_CTL);
9606         cur_depth = (ctl & BCE_RXP_FTQ_CTL_CUR_DEPTH) >> 22;
9607         max_depth = (ctl & BCE_RXP_FTQ_CTL_MAX_DEPTH) >> 12;
9608         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
9609         BCE_PRINTF(" RXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9610             cmd, ctl, cur_depth, max_depth, valid_cnt);
9611
9612         /* Input queue to the Recevie Processor */
9613         cmd = REG_RD_IND(sc, BCE_RXP_CFTQ_CMD);
9614         ctl = REG_RD_IND(sc, BCE_RXP_CFTQ_CTL);
9615         cur_depth = (ctl & BCE_RXP_CFTQ_CTL_CUR_DEPTH) >> 22;
9616         max_depth = (ctl & BCE_RXP_CFTQ_CTL_MAX_DEPTH) >> 12;
9617         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
9618         BCE_PRINTF(" RXPC    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9619             cmd, ctl, cur_depth, max_depth, valid_cnt);
9620
9621         /* Input queue to the Receive Virtual to Physical state machine */
9622         cmd = REG_RD(sc, BCE_RV2P_PFTQ_CMD);
9623         ctl = REG_RD(sc, BCE_RV2P_PFTQ_CTL);
9624         cur_depth = (ctl & BCE_RV2P_PFTQ_CTL_CUR_DEPTH) >> 22;
9625         max_depth = (ctl & BCE_RV2P_PFTQ_CTL_MAX_DEPTH) >> 12;
9626         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
9627         BCE_PRINTF(" RV2PP   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9628             cmd, ctl, cur_depth, max_depth, valid_cnt);
9629
9630         /* Input queue to the Recevie Virtual to Physical state machine */
9631         cmd = REG_RD(sc, BCE_RV2P_MFTQ_CMD);
9632         ctl = REG_RD(sc, BCE_RV2P_MFTQ_CTL);
9633         cur_depth = (ctl & BCE_RV2P_MFTQ_CTL_CUR_DEPTH) >> 22;
9634         max_depth = (ctl & BCE_RV2P_MFTQ_CTL_MAX_DEPTH) >> 12;
9635         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT4);
9636         BCE_PRINTF(" RV2PM   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9637             cmd, ctl, cur_depth, max_depth, valid_cnt);
9638
9639         /* Input queue to the Receive Virtual to Physical state machine */
9640         cmd = REG_RD(sc, BCE_RV2P_TFTQ_CMD);
9641         ctl = REG_RD(sc, BCE_RV2P_TFTQ_CTL);
9642         cur_depth = (ctl & BCE_RV2P_TFTQ_CTL_CUR_DEPTH) >> 22;
9643         max_depth = (ctl & BCE_RV2P_TFTQ_CTL_MAX_DEPTH) >> 12;
9644         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT5);
9645         BCE_PRINTF(" RV2PT   0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9646             cmd, ctl, cur_depth, max_depth, valid_cnt);
9647
9648         /* Input queue to the Receive DMA state machine */
9649         cmd = REG_RD(sc, BCE_RDMA_FTQ_CMD);
9650         ctl = REG_RD(sc, BCE_RDMA_FTQ_CTL);
9651         cur_depth = (ctl & BCE_RDMA_FTQ_CTL_CUR_DEPTH) >> 22;
9652         max_depth = (ctl & BCE_RDMA_FTQ_CTL_MAX_DEPTH) >> 12;
9653         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT6);
9654         BCE_PRINTF(" RDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9655             cmd, ctl, cur_depth, max_depth, valid_cnt);
9656
9657         /* Input queue to the Transmit Scheduler state machine */
9658         cmd = REG_RD(sc, BCE_TSCH_FTQ_CMD);
9659         ctl = REG_RD(sc, BCE_TSCH_FTQ_CTL);
9660         cur_depth = (ctl & BCE_TSCH_FTQ_CTL_CUR_DEPTH) >> 22;
9661         max_depth = (ctl & BCE_TSCH_FTQ_CTL_MAX_DEPTH) >> 12;
9662         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT7);
9663         BCE_PRINTF(" TSCH    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9664             cmd, ctl, cur_depth, max_depth, valid_cnt);
9665
9666         /* Input queue to the Transmit Buffer Descriptor state machine */
9667         cmd = REG_RD(sc, BCE_TBDR_FTQ_CMD);
9668         ctl = REG_RD(sc, BCE_TBDR_FTQ_CTL);
9669         cur_depth = (ctl & BCE_TBDR_FTQ_CTL_CUR_DEPTH) >> 22;
9670         max_depth = (ctl & BCE_TBDR_FTQ_CTL_MAX_DEPTH) >> 12;
9671         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT8);
9672         BCE_PRINTF(" TBDR    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9673             cmd, ctl, cur_depth, max_depth, valid_cnt);
9674
9675         /* Input queue to the Transmit Processor */
9676         cmd = REG_RD_IND(sc, BCE_TXP_FTQ_CMD);
9677         ctl = REG_RD_IND(sc, BCE_TXP_FTQ_CTL);
9678         cur_depth = (ctl & BCE_TXP_FTQ_CTL_CUR_DEPTH) >> 22;
9679         max_depth = (ctl & BCE_TXP_FTQ_CTL_MAX_DEPTH) >> 12;
9680         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT9);
9681         BCE_PRINTF(" TXP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9682             cmd, ctl, cur_depth, max_depth, valid_cnt);
9683
9684         /* Input queue to the Transmit DMA state machine */
9685         cmd = REG_RD(sc, BCE_TDMA_FTQ_CMD);
9686         ctl = REG_RD(sc, BCE_TDMA_FTQ_CTL);
9687         cur_depth = (ctl & BCE_TDMA_FTQ_CTL_CUR_DEPTH) >> 22;
9688         max_depth = (ctl & BCE_TDMA_FTQ_CTL_MAX_DEPTH) >> 12;
9689         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT10);
9690         BCE_PRINTF(" TDMA    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9691             cmd, ctl, cur_depth, max_depth, valid_cnt);
9692
9693         /* Input queue to the Transmit Patch-Up Processor */
9694         cmd = REG_RD_IND(sc, BCE_TPAT_FTQ_CMD);
9695         ctl = REG_RD_IND(sc, BCE_TPAT_FTQ_CTL);
9696         cur_depth = (ctl & BCE_TPAT_FTQ_CTL_CUR_DEPTH) >> 22;
9697         max_depth = (ctl & BCE_TPAT_FTQ_CTL_MAX_DEPTH) >> 12;
9698         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT11);
9699         BCE_PRINTF(" TPAT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9700             cmd, ctl, cur_depth, max_depth, valid_cnt);
9701
9702         /* Input queue to the Transmit Assembler state machine */
9703         cmd = REG_RD_IND(sc, BCE_TAS_FTQ_CMD);
9704         ctl = REG_RD_IND(sc, BCE_TAS_FTQ_CTL);
9705         cur_depth = (ctl & BCE_TAS_FTQ_CTL_CUR_DEPTH) >> 22;
9706         max_depth = (ctl & BCE_TAS_FTQ_CTL_MAX_DEPTH) >> 12;
9707         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT12);
9708         BCE_PRINTF(" TAS     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9709             cmd, ctl, cur_depth, max_depth, valid_cnt);
9710
9711         /* Input queue to the Completion Processor */
9712         cmd = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CMD);
9713         ctl = REG_RD_IND(sc, BCE_COM_COMXQ_FTQ_CTL);
9714         cur_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_CUR_DEPTH) >> 22;
9715         max_depth = (ctl & BCE_COM_COMXQ_FTQ_CTL_MAX_DEPTH) >> 12;
9716         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT13);
9717         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9718             cmd, ctl, cur_depth, max_depth, valid_cnt);
9719
9720         /* Input queue to the Completion Processor */
9721         cmd = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CMD);
9722         ctl = REG_RD_IND(sc, BCE_COM_COMTQ_FTQ_CTL);
9723         cur_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_CUR_DEPTH) >> 22;
9724         max_depth = (ctl & BCE_COM_COMTQ_FTQ_CTL_MAX_DEPTH) >> 12;
9725         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT14);
9726         BCE_PRINTF(" COMT    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9727             cmd, ctl, cur_depth, max_depth, valid_cnt);
9728
9729         /* Input queue to the Completion Processor */
9730         cmd = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CMD);
9731         ctl = REG_RD_IND(sc, BCE_COM_COMQ_FTQ_CTL);
9732         cur_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_CUR_DEPTH) >> 22;
9733         max_depth = (ctl & BCE_COM_COMQ_FTQ_CTL_MAX_DEPTH) >> 12;
9734         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT15);
9735         BCE_PRINTF(" COMX    0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9736             cmd, ctl, cur_depth, max_depth, valid_cnt);
9737
9738         /* Setup the generic statistic counters for the FTQ valid count. */
9739         val = (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CSQ_VALID_CNT  << 16) |
9740             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_CPQ_VALID_CNT  <<  8) |
9741             (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_MGMQ_VALID_CNT);
9742
9743         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
9744             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716))
9745                 val = val |
9746                     (BCE_HC_STAT_GEN_SEL_0_GEN_SEL_0_RV2PCSQ_VALID_CNT_XI <<
9747                      24);
9748         REG_WR(sc, BCE_HC_STAT_GEN_SEL_0, val);
9749
9750         /* Input queue to the Management Control Processor */
9751         cmd = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CMD);
9752         ctl = REG_RD_IND(sc, BCE_MCP_MCPQ_FTQ_CTL);
9753         cur_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_CUR_DEPTH) >> 22;
9754         max_depth = (ctl & BCE_MCP_MCPQ_FTQ_CTL_MAX_DEPTH) >> 12;
9755         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT0);
9756         BCE_PRINTF(" MCP     0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9757             cmd, ctl, cur_depth, max_depth, valid_cnt);
9758
9759         /* Input queue to the Command Processor */
9760         cmd = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CMD);
9761         ctl = REG_RD_IND(sc, BCE_CP_CPQ_FTQ_CTL);
9762         cur_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_CUR_DEPTH) >> 22;
9763         max_depth = (ctl & BCE_CP_CPQ_FTQ_CTL_MAX_DEPTH) >> 12;
9764         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT1);
9765         BCE_PRINTF(" CP      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9766             cmd, ctl, cur_depth, max_depth, valid_cnt);
9767
9768         /* Input queue to the Completion Scheduler state machine */
9769         cmd = REG_RD(sc, BCE_CSCH_CH_FTQ_CMD);
9770         ctl = REG_RD(sc, BCE_CSCH_CH_FTQ_CTL);
9771         cur_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_CUR_DEPTH) >> 22;
9772         max_depth = (ctl & BCE_CSCH_CH_FTQ_CTL_MAX_DEPTH) >> 12;
9773         valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT2);
9774         BCE_PRINTF(" CS      0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9775             cmd, ctl, cur_depth, max_depth, valid_cnt);
9776
9777         if ((BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5709) ||
9778             (BCE_CHIP_NUM(sc) == BCE_CHIP_NUM_5716)) {
9779                 /* Input queue to the RV2P Command Scheduler */
9780                 cmd = REG_RD(sc, BCE_RV2PCSR_FTQ_CMD);
9781                 ctl = REG_RD(sc, BCE_RV2PCSR_FTQ_CTL);
9782                 cur_depth = (ctl & 0xFFC00000) >> 22;
9783                 max_depth = (ctl & 0x003FF000) >> 12;
9784                 valid_cnt = REG_RD(sc, BCE_HC_STAT_GEN_STAT3);
9785                 BCE_PRINTF(" RV2PCSR 0x%08X 0x%08X 0x%08X 0x%08X 0x%08X\n",
9786                     cmd, ctl, cur_depth, max_depth, valid_cnt);
9787         }
9788
9789         BCE_PRINTF(
9790             "----------------------------"
9791             "----------------"
9792             "----------------------------\n");
9793 }
9794
9795
9796 /****************************************************************************/
9797 /* Prints out the TX chain.                                                 */
9798 /*                                                                          */
9799 /* Returns:                                                                 */
9800 /*   Nothing.                                                               */
9801 /****************************************************************************/
9802 static __attribute__ ((noinline)) void
9803 bce_dump_tx_chain(struct bce_softc *sc, u16 tx_prod, int count)
9804 {
9805         struct tx_bd *txbd;
9806
9807         /* First some info about the tx_bd chain structure. */
9808         BCE_PRINTF(
9809             "----------------------------"
9810             "  tx_bd  chain  "
9811             "----------------------------\n");
9812
9813         BCE_PRINTF("page size      = 0x%08X, tx chain pages        = 0x%08X\n",
9814             (u32) BCM_PAGE_SIZE, (u32) TX_PAGES);
9815         BCE_PRINTF("tx_bd per page = 0x%08X, usable tx_bd per page = 0x%08X\n",
9816             (u32) TOTAL_TX_BD_PER_PAGE, (u32) USABLE_TX_BD_PER_PAGE);
9817         BCE_PRINTF("total tx_bd    = 0x%08X\n", (u32) TOTAL_TX_BD);
9818
9819         BCE_PRINTF(
9820             "----------------------------"
9821             "   tx_bd data   "
9822             "----------------------------\n");
9823
9824         /* Now print out a decoded list of TX buffer descriptors. */
9825         for (int i = 0; i < count; i++) {
9826                 txbd = &sc->tx_bd_chain[TX_PAGE(tx_prod)][TX_IDX(tx_prod)];
9827                 bce_dump_txbd(sc, tx_prod, txbd);
9828                 tx_prod++;
9829         }
9830
9831         BCE_PRINTF(
9832             "----------------------------"
9833             "----------------"
9834             "----------------------------\n");
9835 }
9836
9837
9838 /****************************************************************************/
9839 /* Prints out the RX chain.                                                 */
9840 /*                                                                          */
9841 /* Returns:                                                                 */
9842 /*   Nothing.                                                               */
9843 /****************************************************************************/
9844 static __attribute__ ((noinline)) void
9845 bce_dump_rx_bd_chain(struct bce_softc *sc, u16 rx_prod, int count)
9846 {
9847         struct rx_bd *rxbd;
9848
9849         /* First some info about the rx_bd chain structure. */
9850         BCE_PRINTF(
9851             "----------------------------"
9852             "  rx_bd  chain  "
9853             "----------------------------\n");
9854
9855         BCE_PRINTF("page size      = 0x%08X, rx chain pages        = 0x%08X\n",
9856             (u32) BCM_PAGE_SIZE, (u32) RX_PAGES);
9857
9858         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
9859             (u32) TOTAL_RX_BD_PER_PAGE, (u32) USABLE_RX_BD_PER_PAGE);
9860
9861         BCE_PRINTF("total rx_bd    = 0x%08X\n", (u32) TOTAL_RX_BD);
9862
9863         BCE_PRINTF(
9864             "----------------------------"
9865             "   rx_bd data   "
9866             "----------------------------\n");
9867
9868         /* Now print out the rx_bd's themselves. */
9869         for (int i = 0; i < count; i++) {
9870                 rxbd = &sc->rx_bd_chain[RX_PAGE(rx_prod)][RX_IDX(rx_prod)];
9871                 bce_dump_rxbd(sc, rx_prod, rxbd);
9872                 rx_prod = RX_CHAIN_IDX(rx_prod + 1);
9873         }
9874
9875         BCE_PRINTF(
9876             "----------------------------"
9877             "----------------"
9878             "----------------------------\n");
9879 }
9880
9881
9882 #ifdef BCE_JUMBO_HDRSPLIT
9883 /****************************************************************************/
9884 /* Prints out the page chain.                                               */
9885 /*                                                                          */
9886 /* Returns:                                                                 */
9887 /*   Nothing.                                                               */
9888 /****************************************************************************/
9889 static __attribute__ ((noinline)) void
9890 bce_dump_pg_chain(struct bce_softc *sc, u16 pg_prod, int count)
9891 {
9892         struct rx_bd *pgbd;
9893
9894         /* First some info about the page chain structure. */
9895         BCE_PRINTF(
9896             "----------------------------"
9897             "   page chain   "
9898             "----------------------------\n");
9899
9900         BCE_PRINTF("page size      = 0x%08X, pg chain pages        = 0x%08X\n",
9901             (u32) BCM_PAGE_SIZE, (u32) PG_PAGES);
9902
9903         BCE_PRINTF("rx_bd per page = 0x%08X, usable rx_bd per page = 0x%08X\n",
9904             (u32) TOTAL_PG_BD_PER_PAGE, (u32) USABLE_PG_BD_PER_PAGE);
9905
9906         BCE_PRINTF("total rx_bd    = 0x%08X, max_pg_bd             = 0x%08X\n",
9907             (u32) TOTAL_PG_BD, (u32) MAX_PG_BD);
9908
9909         BCE_PRINTF(
9910             "----------------------------"
9911             "   page data    "
9912             "----------------------------\n");
9913
9914         /* Now print out the rx_bd's themselves. */
9915         for (int i = 0; i < count; i++) {
9916                 pgbd = &sc->pg_bd_chain[PG_PAGE(pg_prod)][PG_IDX(pg_prod)];
9917                 bce_dump_pgbd(sc, pg_prod, pgbd);
9918                 pg_prod = PG_CHAIN_IDX(pg_prod + 1);
9919         }
9920
9921         BCE_PRINTF(
9922             "----------------------------"
9923             "----------------"
9924             "----------------------------\n");
9925 }
9926 #endif
9927
9928
9929 #define BCE_PRINT_RX_CONS(arg)                                          \
9930 if (sblk->status_rx_quick_consumer_index##arg)                          \
9931         BCE_PRINTF("0x%04X(0x%04X) - rx_quick_consumer_index%d\n",      \
9932             sblk->status_rx_quick_consumer_index##arg, (u16)            \
9933             RX_CHAIN_IDX(sblk->status_rx_quick_consumer_index##arg),    \
9934             arg);
9935
9936
9937 #define BCE_PRINT_TX_CONS(arg)                                          \
9938 if (sblk->status_tx_quick_consumer_index##arg)                          \
9939         BCE_PRINTF("0x%04X(0x%04X) - tx_quick_consumer_index%d\n",      \
9940             sblk->status_tx_quick_consumer_index##arg, (u16)            \
9941             TX_CHAIN_IDX(sblk->status_tx_quick_consumer_index##arg),    \
9942             arg);
9943
9944 /****************************************************************************/
9945 /* Prints out the status block from host memory.                            */
9946 /*                                                                          */
9947 /* Returns:                                                                 */
9948 /*   Nothing.                                                               */
9949 /****************************************************************************/
9950 static __attribute__ ((noinline)) void
9951 bce_dump_status_block(struct bce_softc *sc)
9952 {
9953         struct status_block *sblk;
9954
9955         sblk = sc->status_block;
9956
9957         BCE_PRINTF(
9958             "----------------------------"
9959             "  Status Block  "
9960             "----------------------------\n");
9961
9962         /* Theses indices are used for normal L2 drivers. */
9963         BCE_PRINTF("    0x%08X - attn_bits\n",
9964             sblk->status_attn_bits);
9965
9966         BCE_PRINTF("    0x%08X - attn_bits_ack\n",
9967             sblk->status_attn_bits_ack);
9968
9969         BCE_PRINT_RX_CONS(0);
9970         BCE_PRINT_TX_CONS(0)
9971
9972         BCE_PRINTF("        0x%04X - status_idx\n", sblk->status_idx);
9973
9974         /* Theses indices are not used for normal L2 drivers. */
9975         BCE_PRINT_RX_CONS(1);   BCE_PRINT_RX_CONS(2);   BCE_PRINT_RX_CONS(3);
9976         BCE_PRINT_RX_CONS(4);   BCE_PRINT_RX_CONS(5);   BCE_PRINT_RX_CONS(6);
9977         BCE_PRINT_RX_CONS(7);   BCE_PRINT_RX_CONS(8);   BCE_PRINT_RX_CONS(9);
9978         BCE_PRINT_RX_CONS(10);  BCE_PRINT_RX_CONS(11);  BCE_PRINT_RX_CONS(12);
9979         BCE_PRINT_RX_CONS(13);  BCE_PRINT_RX_CONS(14);  BCE_PRINT_RX_CONS(15);
9980
9981         BCE_PRINT_TX_CONS(1);   BCE_PRINT_TX_CONS(2);   BCE_PRINT_TX_CONS(3);
9982
9983         if (sblk->status_completion_producer_index ||
9984             sblk->status_cmd_consumer_index)
9985                 BCE_PRINTF("com_prod  = 0x%08X, cmd_cons      = 0x%08X\n",
9986                     sblk->status_completion_producer_index,
9987                     sblk->status_cmd_consumer_index);
9988
9989         BCE_PRINTF(
9990             "----------------------------"
9991             "----------------"
9992             "----------------------------\n");
9993 }
9994
9995
9996 #define BCE_PRINT_64BIT_STAT(arg)                               \
9997 if (sblk->arg##_lo || sblk->arg##_hi)                           \
9998         BCE_PRINTF("0x%08X:%08X : %s\n", sblk->arg##_hi,        \
9999             sblk->arg##_lo, #arg);
10000
10001 #define BCE_PRINT_32BIT_STAT(arg)                               \
10002 if (sblk->arg)                                                  \
10003         BCE_PRINTF("         0x%08X : %s\n",                    \
10004             sblk->arg, #arg);
10005
10006 /****************************************************************************/
10007 /* Prints out the statistics block from host memory.                        */
10008 /*                                                                          */
10009 /* Returns:                                                                 */
10010 /*   Nothing.                                                               */
10011 /****************************************************************************/
10012 static __attribute__ ((noinline)) void
10013 bce_dump_stats_block(struct bce_softc *sc)
10014 {
10015         struct statistics_block *sblk;
10016
10017         sblk = sc->stats_block;
10018
10019         BCE_PRINTF(
10020             "---------------"
10021             " Stats Block  (All Stats Not Shown Are 0) "
10022             "---------------\n");
10023
10024         BCE_PRINT_64BIT_STAT(stat_IfHCInOctets);
10025         BCE_PRINT_64BIT_STAT(stat_IfHCInBadOctets);
10026         BCE_PRINT_64BIT_STAT(stat_IfHCOutOctets);
10027         BCE_PRINT_64BIT_STAT(stat_IfHCOutBadOctets);
10028         BCE_PRINT_64BIT_STAT(stat_IfHCInUcastPkts);
10029         BCE_PRINT_64BIT_STAT(stat_IfHCInBroadcastPkts);
10030         BCE_PRINT_64BIT_STAT(stat_IfHCInMulticastPkts);
10031         BCE_PRINT_64BIT_STAT(stat_IfHCOutUcastPkts);
10032         BCE_PRINT_64BIT_STAT(stat_IfHCOutBroadcastPkts);
10033         BCE_PRINT_64BIT_STAT(stat_IfHCOutMulticastPkts);
10034         BCE_PRINT_32BIT_STAT(
10035             stat_emac_tx_stat_dot3statsinternalmactransmiterrors);
10036         BCE_PRINT_32BIT_STAT(stat_Dot3StatsCarrierSenseErrors);
10037         BCE_PRINT_32BIT_STAT(stat_Dot3StatsFCSErrors);
10038         BCE_PRINT_32BIT_STAT(stat_Dot3StatsAlignmentErrors);
10039         BCE_PRINT_32BIT_STAT(stat_Dot3StatsSingleCollisionFrames);
10040         BCE_PRINT_32BIT_STAT(stat_Dot3StatsMultipleCollisionFrames);
10041         BCE_PRINT_32BIT_STAT(stat_Dot3StatsDeferredTransmissions);
10042         BCE_PRINT_32BIT_STAT(stat_Dot3StatsExcessiveCollisions);
10043         BCE_PRINT_32BIT_STAT(stat_Dot3StatsLateCollisions);
10044         BCE_PRINT_32BIT_STAT(stat_EtherStatsCollisions);
10045         BCE_PRINT_32BIT_STAT(stat_EtherStatsFragments);
10046         BCE_PRINT_32BIT_STAT(stat_EtherStatsJabbers);
10047         BCE_PRINT_32BIT_STAT(stat_EtherStatsUndersizePkts);
10048         BCE_PRINT_32BIT_STAT(stat_EtherStatsOversizePkts);
10049         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx64Octets);
10050         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx65Octetsto127Octets);
10051         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx128Octetsto255Octets);
10052         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx256Octetsto511Octets);
10053         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx512Octetsto1023Octets);
10054         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1024Octetsto1522Octets);
10055         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsRx1523Octetsto9022Octets);
10056         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx64Octets);
10057         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx65Octetsto127Octets);
10058         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx128Octetsto255Octets);
10059         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx256Octetsto511Octets);
10060         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx512Octetsto1023Octets);
10061         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1024Octetsto1522Octets);
10062         BCE_PRINT_32BIT_STAT(stat_EtherStatsPktsTx1523Octetsto9022Octets);
10063         BCE_PRINT_32BIT_STAT(stat_XonPauseFramesReceived);
10064         BCE_PRINT_32BIT_STAT(stat_XoffPauseFramesReceived);
10065         BCE_PRINT_32BIT_STAT(stat_OutXonSent);
10066         BCE_PRINT_32BIT_STAT(stat_OutXoffSent);
10067         BCE_PRINT_32BIT_STAT(stat_FlowControlDone);
10068         BCE_PRINT_32BIT_STAT(stat_MacControlFramesReceived);
10069         BCE_PRINT_32BIT_STAT(stat_XoffStateEntered);
10070         BCE_PRINT_32BIT_STAT(stat_IfInFramesL2FilterDiscards);
10071         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerDiscards);
10072         BCE_PRINT_32BIT_STAT(stat_IfInFTQDiscards);
10073         BCE_PRINT_32BIT_STAT(stat_IfInMBUFDiscards);
10074         BCE_PRINT_32BIT_STAT(stat_IfInRuleCheckerP4Hit);
10075         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerDiscards);
10076         BCE_PRINT_32BIT_STAT(stat_CatchupInFTQDiscards);
10077         BCE_PRINT_32BIT_STAT(stat_CatchupInMBUFDiscards);
10078         BCE_PRINT_32BIT_STAT(stat_CatchupInRuleCheckerP4Hit);
10079
10080         BCE_PRINTF(
10081             "----------------------------"
10082             "----------------"
10083             "----------------------------\n");
10084 }
10085
10086
10087 /****************************************************************************/
10088 /* Prints out a summary of the driver state.                                */
10089 /*                                                                          */
10090 /* Returns:                                                                 */
10091 /*   Nothing.                                                               */
10092 /****************************************************************************/
10093 static __attribute__ ((noinline)) void
10094 bce_dump_driver_state(struct bce_softc *sc)
10095 {
10096         u32 val_hi, val_lo;
10097
10098         BCE_PRINTF(
10099             "-----------------------------"
10100             " Driver State "
10101             "-----------------------------\n");
10102
10103         val_hi = BCE_ADDR_HI(sc);
10104         val_lo = BCE_ADDR_LO(sc);
10105         BCE_PRINTF("0x%08X:%08X - (sc) driver softc structure virtual "
10106             "address\n", val_hi, val_lo);
10107
10108         val_hi = BCE_ADDR_HI(sc->bce_vhandle);
10109         val_lo = BCE_ADDR_LO(sc->bce_vhandle);
10110         BCE_PRINTF("0x%08X:%08X - (sc->bce_vhandle) PCI BAR virtual "
10111             "address\n", val_hi, val_lo);
10112
10113         val_hi = BCE_ADDR_HI(sc->status_block);
10114         val_lo = BCE_ADDR_LO(sc->status_block);
10115         BCE_PRINTF("0x%08X:%08X - (sc->status_block) status block "
10116             "virtual address\n",        val_hi, val_lo);
10117
10118         val_hi = BCE_ADDR_HI(sc->stats_block);
10119         val_lo = BCE_ADDR_LO(sc->stats_block);
10120         BCE_PRINTF("0x%08X:%08X - (sc->stats_block) statistics block "
10121             "virtual address\n", val_hi, val_lo);
10122
10123         val_hi = BCE_ADDR_HI(sc->tx_bd_chain);
10124         val_lo = BCE_ADDR_LO(sc->tx_bd_chain);
10125         BCE_PRINTF("0x%08X:%08X - (sc->tx_bd_chain) tx_bd chain "
10126             "virtual adddress\n", val_hi, val_lo);
10127
10128         val_hi = BCE_ADDR_HI(sc->rx_bd_chain);
10129         val_lo = BCE_ADDR_LO(sc->rx_bd_chain);
10130         BCE_PRINTF("0x%08X:%08X - (sc->rx_bd_chain) rx_bd chain "
10131             "virtual address\n", val_hi, val_lo);
10132
10133 #ifdef BCE_JUMBO_HDRSPLIT
10134         val_hi = BCE_ADDR_HI(sc->pg_bd_chain);
10135         val_lo = BCE_ADDR_LO(sc->pg_bd_chain);
10136         BCE_PRINTF("0x%08X:%08X - (sc->pg_bd_chain) page chain "
10137             "virtual address\n", val_hi, val_lo);
10138 #endif
10139
10140         val_hi = BCE_ADDR_HI(sc->tx_mbuf_ptr);
10141         val_lo = BCE_ADDR_LO(sc->tx_mbuf_ptr);
10142         BCE_PRINTF("0x%08X:%08X - (sc->tx_mbuf_ptr) tx mbuf chain "
10143             "virtual address\n",        val_hi, val_lo);
10144
10145         val_hi = BCE_ADDR_HI(sc->rx_mbuf_ptr);
10146         val_lo = BCE_ADDR_LO(sc->rx_mbuf_ptr);
10147         BCE_PRINTF("0x%08X:%08X - (sc->rx_mbuf_ptr) rx mbuf chain "
10148             "virtual address\n", val_hi, val_lo);
10149
10150 #ifdef BCE_JUMBO_HDRSPLIT
10151         val_hi = BCE_ADDR_HI(sc->pg_mbuf_ptr);
10152         val_lo = BCE_ADDR_LO(sc->pg_mbuf_ptr);
10153         BCE_PRINTF("0x%08X:%08X - (sc->pg_mbuf_ptr) page mbuf chain "
10154             "virtual address\n", val_hi, val_lo);
10155 #endif
10156
10157         BCE_PRINTF("         0x%08X - (sc->interrupts_generated) "
10158             "h/w intrs\n", sc->interrupts_generated);
10159
10160         BCE_PRINTF("         0x%08X - (sc->interrupts_rx) "
10161             "rx interrupts handled\n", sc->interrupts_rx);
10162
10163         BCE_PRINTF("         0x%08X - (sc->interrupts_tx) "
10164             "tx interrupts handled\n", sc->interrupts_tx);
10165
10166         BCE_PRINTF("         0x%08X - (sc->phy_interrupts) "
10167             "phy interrupts handled\n", sc->phy_interrupts);
10168
10169         BCE_PRINTF("         0x%08X - (sc->last_status_idx) "
10170             "status block index\n", sc->last_status_idx);
10171
10172         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_prod) tx producer "
10173             "index\n", sc->tx_prod, (u16) TX_CHAIN_IDX(sc->tx_prod));
10174
10175         BCE_PRINTF("     0x%04X(0x%04X) - (sc->tx_cons) tx consumer "
10176             "index\n", sc->tx_cons, (u16) TX_CHAIN_IDX(sc->tx_cons));
10177
10178         BCE_PRINTF("         0x%08X - (sc->tx_prod_bseq) tx producer "
10179             "byte seq index\n", sc->tx_prod_bseq);
10180
10181         BCE_PRINTF("         0x%08X - (sc->debug_tx_mbuf_alloc) tx "
10182             "mbufs allocated\n", sc->debug_tx_mbuf_alloc);
10183
10184         BCE_PRINTF("         0x%08X - (sc->used_tx_bd) used "
10185             "tx_bd's\n", sc->used_tx_bd);
10186
10187         BCE_PRINTF("0x%08X/%08X - (sc->tx_hi_watermark) tx hi "
10188             "watermark\n", sc->tx_hi_watermark, sc->max_tx_bd);
10189
10190         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_prod) rx producer "
10191             "index\n", sc->rx_prod, (u16) RX_CHAIN_IDX(sc->rx_prod));
10192
10193         BCE_PRINTF("     0x%04X(0x%04X) - (sc->rx_cons) rx consumer "
10194             "index\n", sc->rx_cons, (u16) RX_CHAIN_IDX(sc->rx_cons));
10195
10196         BCE_PRINTF("         0x%08X - (sc->rx_prod_bseq) rx producer "
10197             "byte seq index\n", sc->rx_prod_bseq);
10198
10199         BCE_PRINTF("         0x%08X - (sc->debug_rx_mbuf_alloc) rx "
10200             "mbufs allocated\n", sc->debug_rx_mbuf_alloc);
10201
10202         BCE_PRINTF("         0x%08X - (sc->free_rx_bd) free "
10203             "rx_bd's\n", sc->free_rx_bd);
10204
10205 #ifdef BCE_JUMBO_HDRSPLIT
10206         BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_prod) page producer "
10207             "index\n", sc->pg_prod, (u16) PG_CHAIN_IDX(sc->pg_prod));
10208
10209         BCE_PRINTF("     0x%04X(0x%04X) - (sc->pg_cons) page consumer "
10210             "index\n", sc->pg_cons, (u16) PG_CHAIN_IDX(sc->pg_cons));
10211
10212         BCE_PRINTF("         0x%08X - (sc->debug_pg_mbuf_alloc) page "
10213             "mbufs allocated\n", sc->debug_pg_mbuf_alloc);
10214
10215         BCE_PRINTF("         0x%08X - (sc->free_pg_bd) free page "
10216             "rx_bd's\n", sc->free_pg_bd);
10217
10218         BCE_PRINTF("0x%08X/%08X - (sc->pg_low_watermark) page low "
10219             "watermark\n", sc->pg_low_watermark, sc->max_pg_bd);
10220 #endif
10221
10222         BCE_PRINTF("         0x%08X - (sc->mbuf_alloc_failed_count) "
10223             "mbuf alloc failures\n", sc->mbuf_alloc_failed_count);
10224
10225         BCE_PRINTF("         0x%08X - (sc->bce_flags) "
10226             "bce mac flags\n", sc->bce_flags);
10227
10228         BCE_PRINTF("         0x%08X - (sc->bce_phy_flags) "
10229             "bce phy flags\n", sc->bce_phy_flags);
10230
10231         BCE_PRINTF(
10232             "----------------------------"
10233             "----------------"
10234             "----------------------------\n");
10235 }
10236
10237
10238 /****************************************************************************/
10239 /* Prints out the hardware state through a summary of important register,   */
10240 /* followed by a complete register dump.                                    */
10241 /*                                                                          */
10242 /* Returns:                                                                 */
10243 /*   Nothing.                                                               */
10244 /****************************************************************************/
10245 static __attribute__ ((noinline)) void
10246 bce_dump_hw_state(struct bce_softc *sc)
10247 {
10248         u32 val;
10249
10250         BCE_PRINTF(
10251             "----------------------------"
10252             " Hardware State "
10253             "----------------------------\n");
10254
10255         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
10256
10257         val = REG_RD(sc, BCE_MISC_ENABLE_STATUS_BITS);
10258         BCE_PRINTF("0x%08X - (0x%06X) misc_enable_status_bits\n",
10259             val, BCE_MISC_ENABLE_STATUS_BITS);
10260
10261         val = REG_RD(sc, BCE_DMA_STATUS);
10262         BCE_PRINTF("0x%08X - (0x%06X) dma_status\n",
10263             val, BCE_DMA_STATUS);
10264
10265         val = REG_RD(sc, BCE_CTX_STATUS);
10266         BCE_PRINTF("0x%08X - (0x%06X) ctx_status\n",
10267             val, BCE_CTX_STATUS);
10268
10269         val = REG_RD(sc, BCE_EMAC_STATUS);
10270         BCE_PRINTF("0x%08X - (0x%06X) emac_status\n",
10271             val, BCE_EMAC_STATUS);
10272
10273         val = REG_RD(sc, BCE_RPM_STATUS);
10274         BCE_PRINTF("0x%08X - (0x%06X) rpm_status\n",
10275             val, BCE_RPM_STATUS);
10276
10277         /* ToDo: Create a #define for this constant. */
10278         val = REG_RD(sc, 0x2004);
10279         BCE_PRINTF("0x%08X - (0x%06X) rlup_status\n",
10280             val, 0x2004);
10281
10282         val = REG_RD(sc, BCE_RV2P_STATUS);
10283         BCE_PRINTF("0x%08X - (0x%06X) rv2p_status\n",
10284             val, BCE_RV2P_STATUS);
10285
10286         /* ToDo: Create a #define for this constant. */
10287         val = REG_RD(sc, 0x2c04);
10288         BCE_PRINTF("0x%08X - (0x%06X) rdma_status\n",
10289             val, 0x2c04);
10290
10291         val = REG_RD(sc, BCE_TBDR_STATUS);
10292         BCE_PRINTF("0x%08X - (0x%06X) tbdr_status\n",
10293             val, BCE_TBDR_STATUS);
10294
10295         val = REG_RD(sc, BCE_TDMA_STATUS);
10296         BCE_PRINTF("0x%08X - (0x%06X) tdma_status\n",
10297             val, BCE_TDMA_STATUS);
10298
10299         val = REG_RD(sc, BCE_HC_STATUS);
10300         BCE_PRINTF("0x%08X - (0x%06X) hc_status\n",
10301             val, BCE_HC_STATUS);
10302
10303         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
10304         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
10305             val, BCE_TXP_CPU_STATE);
10306
10307         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
10308         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
10309             val, BCE_TPAT_CPU_STATE);
10310
10311         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
10312         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
10313             val, BCE_RXP_CPU_STATE);
10314
10315         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
10316         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
10317             val, BCE_COM_CPU_STATE);
10318
10319         val = REG_RD_IND(sc, BCE_MCP_CPU_STATE);
10320         BCE_PRINTF("0x%08X - (0x%06X) mcp_cpu_state\n",
10321             val, BCE_MCP_CPU_STATE);
10322
10323         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
10324         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
10325             val, BCE_CP_CPU_STATE);
10326
10327         BCE_PRINTF(
10328             "----------------------------"
10329             "----------------"
10330             "----------------------------\n");
10331
10332         BCE_PRINTF(
10333             "----------------------------"
10334             " Register  Dump "
10335             "----------------------------\n");
10336
10337         for (int i = 0x400; i < 0x8000; i += 0x10) {
10338                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
10339                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
10340                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
10341         }
10342
10343         BCE_PRINTF(
10344             "----------------------------"
10345             "----------------"
10346             "----------------------------\n");
10347 }
10348
10349
10350 /****************************************************************************/
10351 /* Prints out the mailbox queue registers.                                  */
10352 /*                                                                          */
10353 /* Returns:                                                                 */
10354 /*   Nothing.                                                               */
10355 /****************************************************************************/
10356 static __attribute__ ((noinline)) void
10357 bce_dump_mq_regs(struct bce_softc *sc)
10358 {
10359         BCE_PRINTF(
10360             "----------------------------"
10361             "    MQ Regs     "
10362             "----------------------------\n");
10363
10364         BCE_PRINTF(
10365             "----------------------------"
10366             "----------------"
10367             "----------------------------\n");
10368
10369         for (int i = 0x3c00; i < 0x4000; i += 0x10) {
10370                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X 0x%08X 0x%08X\n",
10371                     i, REG_RD(sc, i), REG_RD(sc, i + 0x4),
10372                     REG_RD(sc, i + 0x8), REG_RD(sc, i + 0xC));
10373         }
10374
10375         BCE_PRINTF(
10376             "----------------------------"
10377             "----------------"
10378             "----------------------------\n");
10379 }
10380
10381
10382 /****************************************************************************/
10383 /* Prints out the bootcode state.                                           */
10384 /*                                                                          */
10385 /* Returns:                                                                 */
10386 /*   Nothing.                                                               */
10387 /****************************************************************************/
10388 static __attribute__ ((noinline)) void
10389 bce_dump_bc_state(struct bce_softc *sc)
10390 {
10391         u32 val;
10392
10393         BCE_PRINTF(
10394             "----------------------------"
10395             " Bootcode State "
10396             "----------------------------\n");
10397
10398         BCE_PRINTF("%s - bootcode version\n", sc->bce_bc_ver);
10399
10400         val = bce_shmem_rd(sc, BCE_BC_RESET_TYPE);
10401         BCE_PRINTF("0x%08X - (0x%06X) reset_type\n",
10402             val, BCE_BC_RESET_TYPE);
10403
10404         val = bce_shmem_rd(sc, BCE_BC_STATE);
10405         BCE_PRINTF("0x%08X - (0x%06X) state\n",
10406             val, BCE_BC_STATE);
10407
10408         val = bce_shmem_rd(sc, BCE_BC_STATE_CONDITION);
10409         BCE_PRINTF("0x%08X - (0x%06X) condition\n",
10410             val, BCE_BC_STATE_CONDITION);
10411
10412         val = bce_shmem_rd(sc, BCE_BC_STATE_DEBUG_CMD);
10413         BCE_PRINTF("0x%08X - (0x%06X) debug_cmd\n",
10414             val, BCE_BC_STATE_DEBUG_CMD);
10415
10416         BCE_PRINTF(
10417             "----------------------------"
10418             "----------------"
10419             "----------------------------\n");
10420 }
10421
10422
10423 /****************************************************************************/
10424 /* Prints out the TXP processor state.                                      */
10425 /*                                                                          */
10426 /* Returns:                                                                 */
10427 /*   Nothing.                                                               */
10428 /****************************************************************************/
10429 static __attribute__ ((noinline)) void
10430 bce_dump_txp_state(struct bce_softc *sc, int regs)
10431 {
10432         u32 val;
10433         u32 fw_version[3];
10434
10435         BCE_PRINTF(
10436             "----------------------------"
10437             "   TXP  State   "
10438             "----------------------------\n");
10439
10440         for (int i = 0; i < 3; i++)
10441                 fw_version[i] = htonl(REG_RD_IND(sc,
10442                     (BCE_TXP_SCRATCH + 0x10 + i * 4)));
10443         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
10444
10445         val = REG_RD_IND(sc, BCE_TXP_CPU_MODE);
10446         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_mode\n",
10447             val, BCE_TXP_CPU_MODE);
10448
10449         val = REG_RD_IND(sc, BCE_TXP_CPU_STATE);
10450         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_state\n",
10451             val, BCE_TXP_CPU_STATE);
10452
10453         val = REG_RD_IND(sc, BCE_TXP_CPU_EVENT_MASK);
10454         BCE_PRINTF("0x%08X - (0x%06X) txp_cpu_event_mask\n",
10455             val, BCE_TXP_CPU_EVENT_MASK);
10456
10457         if (regs) {
10458                 BCE_PRINTF(
10459                     "----------------------------"
10460                     " Register  Dump "
10461                     "----------------------------\n");
10462
10463                 for (int i = BCE_TXP_CPU_MODE; i < 0x68000; i += 0x10) {
10464                         /* Skip the big blank spaces */
10465                         if (i < 0x454000 && i > 0x5ffff)
10466                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
10467                                     "0x%08X 0x%08X\n", i,
10468                                     REG_RD_IND(sc, i),
10469                                     REG_RD_IND(sc, i + 0x4),
10470                                     REG_RD_IND(sc, i + 0x8),
10471                                     REG_RD_IND(sc, i + 0xC));
10472                 }
10473         }
10474
10475         BCE_PRINTF(
10476             "----------------------------"
10477             "----------------"
10478             "----------------------------\n");
10479 }
10480
10481
10482 /****************************************************************************/
10483 /* Prints out the RXP processor state.                                      */
10484 /*                                                                          */
10485 /* Returns:                                                                 */
10486 /*   Nothing.                                                               */
10487 /****************************************************************************/
10488 static __attribute__ ((noinline)) void
10489 bce_dump_rxp_state(struct bce_softc *sc, int regs)
10490 {
10491         u32 val;
10492         u32 fw_version[3];
10493
10494         BCE_PRINTF(
10495             "----------------------------"
10496             "   RXP  State   "
10497             "----------------------------\n");
10498
10499         for (int i = 0; i < 3; i++)
10500                 fw_version[i] = htonl(REG_RD_IND(sc,
10501                     (BCE_RXP_SCRATCH + 0x10 + i * 4)));
10502
10503         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
10504
10505         val = REG_RD_IND(sc, BCE_RXP_CPU_MODE);
10506         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_mode\n",
10507             val, BCE_RXP_CPU_MODE);
10508
10509         val = REG_RD_IND(sc, BCE_RXP_CPU_STATE);
10510         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_state\n",
10511             val, BCE_RXP_CPU_STATE);
10512
10513         val = REG_RD_IND(sc, BCE_RXP_CPU_EVENT_MASK);
10514         BCE_PRINTF("0x%08X - (0x%06X) rxp_cpu_event_mask\n",
10515             val, BCE_RXP_CPU_EVENT_MASK);
10516
10517         if (regs) {
10518                 BCE_PRINTF(
10519                     "----------------------------"
10520                     " Register  Dump "
10521                     "----------------------------\n");
10522
10523                 for (int i = BCE_RXP_CPU_MODE; i < 0xe8fff; i += 0x10) {
10524                         /* Skip the big blank sapces */
10525                         if (i < 0xc5400 && i > 0xdffff)
10526                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
10527                                     "0x%08X 0x%08X\n", i,
10528                                     REG_RD_IND(sc, i),
10529                                     REG_RD_IND(sc, i + 0x4),
10530                                     REG_RD_IND(sc, i + 0x8),
10531                                     REG_RD_IND(sc, i + 0xC));
10532                 }
10533         }
10534
10535         BCE_PRINTF(
10536             "----------------------------"
10537             "----------------"
10538             "----------------------------\n");
10539 }
10540
10541
10542 /****************************************************************************/
10543 /* Prints out the TPAT processor state.                                     */
10544 /*                                                                          */
10545 /* Returns:                                                                 */
10546 /*   Nothing.                                                               */
10547 /****************************************************************************/
10548 static __attribute__ ((noinline)) void
10549 bce_dump_tpat_state(struct bce_softc *sc, int regs)
10550 {
10551         u32 val;
10552         u32 fw_version[3];
10553
10554         BCE_PRINTF(
10555             "----------------------------"
10556             "   TPAT State   "
10557             "----------------------------\n");
10558
10559         for (int i = 0; i < 3; i++)
10560                 fw_version[i] = htonl(REG_RD_IND(sc,
10561                     (BCE_TPAT_SCRATCH + 0x410 + i * 4)));
10562
10563         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
10564
10565         val = REG_RD_IND(sc, BCE_TPAT_CPU_MODE);
10566         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_mode\n",
10567             val, BCE_TPAT_CPU_MODE);
10568
10569         val = REG_RD_IND(sc, BCE_TPAT_CPU_STATE);
10570         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_state\n",
10571             val, BCE_TPAT_CPU_STATE);
10572
10573         val = REG_RD_IND(sc, BCE_TPAT_CPU_EVENT_MASK);
10574         BCE_PRINTF("0x%08X - (0x%06X) tpat_cpu_event_mask\n",
10575             val, BCE_TPAT_CPU_EVENT_MASK);
10576
10577         if (regs) {
10578                 BCE_PRINTF(
10579                     "----------------------------"
10580                     " Register  Dump "
10581                     "----------------------------\n");
10582
10583                 for (int i = BCE_TPAT_CPU_MODE; i < 0xa3fff; i += 0x10) {
10584                         /* Skip the big blank spaces */
10585                         if (i < 0x854000 && i > 0x9ffff)
10586                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
10587                                     "0x%08X 0x%08X\n", i,
10588                                     REG_RD_IND(sc, i),
10589                                     REG_RD_IND(sc, i + 0x4),
10590                                     REG_RD_IND(sc, i + 0x8),
10591                                     REG_RD_IND(sc, i + 0xC));
10592                 }
10593         }
10594
10595         BCE_PRINTF(
10596                 "----------------------------"
10597                 "----------------"
10598                 "----------------------------\n");
10599 }
10600
10601
10602 /****************************************************************************/
10603 /* Prints out the Command Procesor (CP) state.                              */
10604 /*                                                                          */
10605 /* Returns:                                                                 */
10606 /*   Nothing.                                                               */
10607 /****************************************************************************/
10608 static __attribute__ ((noinline)) void
10609 bce_dump_cp_state(struct bce_softc *sc, int regs)
10610 {
10611         u32 val;
10612         u32 fw_version[3];
10613
10614         BCE_PRINTF(
10615             "----------------------------"
10616             "    CP State    "
10617             "----------------------------\n");
10618
10619         for (int i = 0; i < 3; i++)
10620                 fw_version[i] = htonl(REG_RD_IND(sc,
10621                     (BCE_CP_SCRATCH + 0x10 + i * 4)));
10622
10623         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
10624
10625         val = REG_RD_IND(sc, BCE_CP_CPU_MODE);
10626         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_mode\n",
10627             val, BCE_CP_CPU_MODE);
10628
10629         val = REG_RD_IND(sc, BCE_CP_CPU_STATE);
10630         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_state\n",
10631             val, BCE_CP_CPU_STATE);
10632
10633         val = REG_RD_IND(sc, BCE_CP_CPU_EVENT_MASK);
10634         BCE_PRINTF("0x%08X - (0x%06X) cp_cpu_event_mask\n", val,
10635             BCE_CP_CPU_EVENT_MASK);
10636
10637         if (regs) {
10638                 BCE_PRINTF(
10639                     "----------------------------"
10640                     " Register  Dump "
10641                     "----------------------------\n");
10642
10643                 for (int i = BCE_CP_CPU_MODE; i < 0x1aa000; i += 0x10) {
10644                         /* Skip the big blank spaces */
10645                         if (i < 0x185400 && i > 0x19ffff)
10646                                 BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
10647                                     "0x%08X 0x%08X\n", i,
10648                                     REG_RD_IND(sc, i),
10649                                     REG_RD_IND(sc, i + 0x4),
10650                                     REG_RD_IND(sc, i + 0x8),
10651                                     REG_RD_IND(sc, i + 0xC));
10652                 }
10653         }
10654
10655         BCE_PRINTF(
10656             "----------------------------"
10657             "----------------"
10658             "----------------------------\n");
10659 }
10660
10661
10662 /****************************************************************************/
10663 /* Prints out the Completion Procesor (COM) state.                          */
10664 /*                                                                          */
10665 /* Returns:                                                                 */
10666 /*   Nothing.                                                               */
10667 /****************************************************************************/
10668 static __attribute__ ((noinline)) void
10669 bce_dump_com_state(struct bce_softc *sc, int regs)
10670 {
10671         u32 val;
10672         u32 fw_version[4];
10673
10674         BCE_PRINTF(
10675             "----------------------------"
10676             "   COM State    "
10677             "----------------------------\n");
10678
10679         for (int i = 0; i < 3; i++)
10680                 fw_version[i] = htonl(REG_RD_IND(sc,
10681                     (BCE_COM_SCRATCH + 0x10 + i * 4)));
10682
10683         BCE_PRINTF("Firmware version - %s\n", (char *) fw_version);
10684
10685         val = REG_RD_IND(sc, BCE_COM_CPU_MODE);
10686         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_mode\n",
10687             val, BCE_COM_CPU_MODE);
10688
10689         val = REG_RD_IND(sc, BCE_COM_CPU_STATE);
10690         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_state\n",
10691             val, BCE_COM_CPU_STATE);
10692
10693         val = REG_RD_IND(sc, BCE_COM_CPU_EVENT_MASK);
10694         BCE_PRINTF("0x%08X - (0x%06X) com_cpu_event_mask\n", val,
10695             BCE_COM_CPU_EVENT_MASK);
10696
10697         if (regs) {
10698                 BCE_PRINTF(
10699                     "----------------------------"
10700                     " Register  Dump "
10701                     "----------------------------\n");
10702
10703                 for (int i = BCE_COM_CPU_MODE; i < 0x1053e8; i += 0x10) {
10704                         BCE_PRINTF("0x%04X: 0x%08X 0x%08X "
10705                             "0x%08X 0x%08X\n", i,
10706                             REG_RD_IND(sc, i),
10707                             REG_RD_IND(sc, i + 0x4),
10708                             REG_RD_IND(sc, i + 0x8),
10709                             REG_RD_IND(sc, i + 0xC));
10710                 }
10711         }
10712
10713         BCE_PRINTF(
10714                 "----------------------------"
10715                 "----------------"
10716                 "----------------------------\n");
10717 }
10718
10719
10720 /****************************************************************************/
10721 /* Prints out the Receive Virtual 2 Physical (RV2P) state.                  */
10722 /*                                                                          */
10723 /* Returns:                                                                 */
10724 /*   Nothing.                                                               */
10725 /****************************************************************************/
10726 static __attribute__ ((noinline)) void
10727 bce_dump_rv2p_state(struct bce_softc *sc)
10728 {
10729         u32 val, pc1, pc2, fw_ver_high, fw_ver_low;
10730
10731         BCE_PRINTF(
10732             "----------------------------"
10733             "   RV2P State   "
10734             "----------------------------\n");
10735
10736         /* Stall the RV2P processors. */
10737         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
10738         val |= BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2;
10739         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
10740
10741         /* Read the firmware version. */
10742         val = 0x00000001;
10743         REG_WR_IND(sc, BCE_RV2P_PROC1_ADDR_CMD, val);
10744         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
10745         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
10746             BCE_RV2P_INSTR_HIGH_HIGH;
10747         BCE_PRINTF("RV2P1 Firmware version - 0x%08X:0x%08X\n",
10748             fw_ver_high, fw_ver_low);
10749
10750         val = 0x00000001;
10751         REG_WR_IND(sc, BCE_RV2P_PROC2_ADDR_CMD, val);
10752         fw_ver_low = REG_RD_IND(sc, BCE_RV2P_INSTR_LOW);
10753         fw_ver_high = REG_RD_IND(sc, BCE_RV2P_INSTR_HIGH) &
10754             BCE_RV2P_INSTR_HIGH_HIGH;
10755         BCE_PRINTF("RV2P2 Firmware version - 0x%08X:0x%08X\n",
10756             fw_ver_high, fw_ver_low);
10757
10758         /* Resume the RV2P processors. */
10759         val = REG_RD_IND(sc, BCE_RV2P_CONFIG);
10760         val &= ~(BCE_RV2P_CONFIG_STALL_PROC1 | BCE_RV2P_CONFIG_STALL_PROC2);
10761         REG_WR_IND(sc, BCE_RV2P_CONFIG, val);
10762
10763         /* Fetch the program counter value. */
10764         val = 0x68007800;
10765         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
10766         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
10767         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
10768         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
10769         BCE_PRINTF("0x%08X - RV2P1 program counter (1st read)\n", pc1);
10770         BCE_PRINTF("0x%08X - RV2P2 program counter (1st read)\n", pc2);
10771
10772         /* Fetch the program counter value again to see if it is advancing. */
10773         val = 0x68007800;
10774         REG_WR_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK, val);
10775         val = REG_RD_IND(sc, BCE_RV2P_DEBUG_VECT_PEEK);
10776         pc1 = (val & BCE_RV2P_DEBUG_VECT_PEEK_1_VALUE);
10777         pc2 = (val & BCE_RV2P_DEBUG_VECT_PEEK_2_VALUE) >> 16;
10778         BCE_PRINTF("0x%08X - RV2P1 program counter (2nd read)\n", pc1);
10779         BCE_PRINTF("0x%08X - RV2P2 program counter (2nd read)\n", pc2);
10780
10781         BCE_PRINTF(
10782             "----------------------------"
10783             "----------------"
10784             "----------------------------\n");
10785 }
10786
10787
10788 /****************************************************************************/
10789 /* Prints out the driver state and then enters the debugger.                */
10790 /*                                                                          */
10791 /* Returns:                                                                 */
10792 /*   Nothing.                                                               */
10793 /****************************************************************************/
10794 static __attribute__ ((noinline)) void
10795 bce_breakpoint(struct bce_softc *sc)
10796 {
10797
10798         /*
10799          * Unreachable code to silence compiler warnings
10800          * about unused functions.
10801          */
10802         if (0) {
10803                 bce_freeze_controller(sc);
10804                 bce_unfreeze_controller(sc);
10805                 bce_dump_enet(sc, NULL);
10806                 bce_dump_txbd(sc, 0, NULL);
10807                 bce_dump_rxbd(sc, 0, NULL);
10808                 bce_dump_tx_mbuf_chain(sc, 0, USABLE_TX_BD);
10809                 bce_dump_rx_mbuf_chain(sc, 0, USABLE_RX_BD);
10810                 bce_dump_l2fhdr(sc, 0, NULL);
10811                 bce_dump_ctx(sc, RX_CID);
10812                 bce_dump_ftqs(sc);
10813                 bce_dump_tx_chain(sc, 0, USABLE_TX_BD);
10814                 bce_dump_rx_bd_chain(sc, 0, USABLE_RX_BD);
10815                 bce_dump_status_block(sc);
10816                 bce_dump_stats_block(sc);
10817                 bce_dump_driver_state(sc);
10818                 bce_dump_hw_state(sc);
10819                 bce_dump_bc_state(sc);
10820                 bce_dump_txp_state(sc, 0);
10821                 bce_dump_rxp_state(sc, 0);
10822                 bce_dump_tpat_state(sc, 0);
10823                 bce_dump_cp_state(sc, 0);
10824                 bce_dump_com_state(sc, 0);
10825                 bce_dump_rv2p_state(sc);
10826
10827 #ifdef BCE_JUMBO_HDRSPLIT
10828                 bce_dump_pgbd(sc, 0, NULL);
10829                 bce_dump_pg_mbuf_chain(sc, 0, USABLE_PG_BD);
10830                 bce_dump_pg_chain(sc, 0, USABLE_PG_BD);
10831 #endif
10832         }
10833
10834         bce_dump_status_block(sc);
10835         bce_dump_driver_state(sc);
10836
10837         /* Call the debugger. */
10838         breakpoint();
10839
10840         return;
10841 }
10842 #endif
10843