2 * Copyright (c) 2003 Stuart Walsh<stu@ipng.org.uk>
3 * and Duncan Barclay<dmlb@dmlb.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/systm.h>
34 #include <sys/endian.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
38 #include <sys/module.h>
40 #include <sys/socket.h>
41 #include <sys/sockio.h>
42 #include <sys/sysctl.h>
46 #include <net/ethernet.h>
47 #include <net/if_dl.h>
48 #include <net/if_media.h>
49 #include <net/if_types.h>
50 #include <net/if_vlan_var.h>
52 #include <dev/mii/mii.h>
53 #include <dev/mii/miivar.h>
55 #include <dev/pci/pcireg.h>
56 #include <dev/pci/pcivar.h>
58 #include <machine/bus.h>
60 #include <dev/bfe/if_bfereg.h>
62 MODULE_DEPEND(bfe, pci, 1, 1, 1);
63 MODULE_DEPEND(bfe, ether, 1, 1, 1);
64 MODULE_DEPEND(bfe, miibus, 1, 1, 1);
66 /* "device miibus" required. See GENERIC if you get errors here. */
67 #include "miibus_if.h"
69 #define BFE_DEVDESC_MAX 64 /* Maximum device description length */
71 static struct bfe_type bfe_devs[] = {
72 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401,
73 "Broadcom BCM4401 Fast Ethernet" },
74 { BCOM_VENDORID, BCOM_DEVICEID_BCM4401B0,
75 "Broadcom BCM4401-B0 Fast Ethernet" },
79 static int bfe_probe (device_t);
80 static int bfe_attach (device_t);
81 static int bfe_detach (device_t);
82 static int bfe_suspend (device_t);
83 static int bfe_resume (device_t);
84 static void bfe_release_resources (struct bfe_softc *);
85 static void bfe_intr (void *);
86 static int bfe_encap (struct bfe_softc *, struct mbuf **);
87 static void bfe_start (struct ifnet *);
88 static void bfe_start_locked (struct ifnet *);
89 static int bfe_ioctl (struct ifnet *, u_long, caddr_t);
90 static void bfe_init (void *);
91 static void bfe_init_locked (void *);
92 static void bfe_stop (struct bfe_softc *);
93 static void bfe_watchdog (struct bfe_softc *);
94 static int bfe_shutdown (device_t);
95 static void bfe_tick (void *);
96 static void bfe_txeof (struct bfe_softc *);
97 static void bfe_rxeof (struct bfe_softc *);
98 static void bfe_set_rx_mode (struct bfe_softc *);
99 static int bfe_list_rx_init (struct bfe_softc *);
100 static void bfe_list_tx_init (struct bfe_softc *);
101 static void bfe_discard_buf (struct bfe_softc *, int);
102 static int bfe_list_newbuf (struct bfe_softc *, int);
103 static void bfe_rx_ring_free (struct bfe_softc *);
105 static void bfe_pci_setup (struct bfe_softc *, u_int32_t);
106 static int bfe_ifmedia_upd (struct ifnet *);
107 static void bfe_ifmedia_sts (struct ifnet *, struct ifmediareq *);
108 static int bfe_miibus_readreg (device_t, int, int);
109 static int bfe_miibus_writereg (device_t, int, int, int);
110 static void bfe_miibus_statchg (device_t);
111 static int bfe_wait_bit (struct bfe_softc *, u_int32_t, u_int32_t,
113 static void bfe_get_config (struct bfe_softc *sc);
114 static void bfe_read_eeprom (struct bfe_softc *, u_int8_t *);
115 static void bfe_stats_update (struct bfe_softc *);
116 static void bfe_clear_stats (struct bfe_softc *);
117 static int bfe_readphy (struct bfe_softc *, u_int32_t, u_int32_t*);
118 static int bfe_writephy (struct bfe_softc *, u_int32_t, u_int32_t);
119 static int bfe_resetphy (struct bfe_softc *);
120 static int bfe_setupphy (struct bfe_softc *);
121 static void bfe_chip_reset (struct bfe_softc *);
122 static void bfe_chip_halt (struct bfe_softc *);
123 static void bfe_core_reset (struct bfe_softc *);
124 static void bfe_core_disable (struct bfe_softc *);
125 static int bfe_dma_alloc (struct bfe_softc *);
126 static void bfe_dma_free (struct bfe_softc *sc);
127 static void bfe_dma_map (void *, bus_dma_segment_t *, int, int);
128 static void bfe_cam_write (struct bfe_softc *, u_char *, int);
129 static int sysctl_bfe_stats (SYSCTL_HANDLER_ARGS);
131 static device_method_t bfe_methods[] = {
132 /* Device interface */
133 DEVMETHOD(device_probe, bfe_probe),
134 DEVMETHOD(device_attach, bfe_attach),
135 DEVMETHOD(device_detach, bfe_detach),
136 DEVMETHOD(device_shutdown, bfe_shutdown),
137 DEVMETHOD(device_suspend, bfe_suspend),
138 DEVMETHOD(device_resume, bfe_resume),
141 DEVMETHOD(bus_print_child, bus_generic_print_child),
142 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
145 DEVMETHOD(miibus_readreg, bfe_miibus_readreg),
146 DEVMETHOD(miibus_writereg, bfe_miibus_writereg),
147 DEVMETHOD(miibus_statchg, bfe_miibus_statchg),
152 static driver_t bfe_driver = {
155 sizeof(struct bfe_softc)
158 static devclass_t bfe_devclass;
160 DRIVER_MODULE(bfe, pci, bfe_driver, bfe_devclass, 0, 0);
161 DRIVER_MODULE(miibus, bfe, miibus_driver, miibus_devclass, 0, 0);
164 * Probe for a Broadcom 4401 chip.
167 bfe_probe(device_t dev)
173 while (t->bfe_name != NULL) {
174 if (pci_get_vendor(dev) == t->bfe_vid &&
175 pci_get_device(dev) == t->bfe_did) {
176 device_set_desc(dev, t->bfe_name);
177 return (BUS_PROBE_DEFAULT);
185 struct bfe_dmamap_arg {
186 bus_addr_t bfe_busaddr;
190 bfe_dma_alloc(struct bfe_softc *sc)
192 struct bfe_dmamap_arg ctx;
193 struct bfe_rx_data *rd;
194 struct bfe_tx_data *td;
198 * parent tag. Apparently the chip cannot handle any DMA address
201 error = bus_dma_tag_create(bus_get_dma_tag(sc->bfe_dev), /* parent */
202 1, 0, /* alignment, boundary */
203 BFE_DMA_MAXADDR, /* lowaddr */
204 BUS_SPACE_MAXADDR, /* highaddr */
205 NULL, NULL, /* filter, filterarg */
206 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */
208 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
210 NULL, NULL, /* lockfunc, lockarg */
211 &sc->bfe_parent_tag);
213 device_printf(sc->bfe_dev, "cannot create parent DMA tag.\n");
217 /* Create tag for Tx ring. */
218 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
219 BFE_TX_RING_ALIGN, 0, /* alignment, boundary */
220 BUS_SPACE_MAXADDR, /* lowaddr */
221 BUS_SPACE_MAXADDR, /* highaddr */
222 NULL, NULL, /* filter, filterarg */
223 BFE_TX_LIST_SIZE, /* maxsize */
225 BFE_TX_LIST_SIZE, /* maxsegsize */
227 NULL, NULL, /* lockfunc, lockarg */
230 device_printf(sc->bfe_dev, "cannot create Tx ring DMA tag.\n");
234 /* Create tag for Rx ring. */
235 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
236 BFE_RX_RING_ALIGN, 0, /* alignment, boundary */
237 BUS_SPACE_MAXADDR, /* lowaddr */
238 BUS_SPACE_MAXADDR, /* highaddr */
239 NULL, NULL, /* filter, filterarg */
240 BFE_RX_LIST_SIZE, /* maxsize */
242 BFE_RX_LIST_SIZE, /* maxsegsize */
244 NULL, NULL, /* lockfunc, lockarg */
247 device_printf(sc->bfe_dev, "cannot create Rx ring DMA tag.\n");
251 /* Create tag for Tx buffers. */
252 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
253 1, 0, /* alignment, boundary */
254 BUS_SPACE_MAXADDR, /* lowaddr */
255 BUS_SPACE_MAXADDR, /* highaddr */
256 NULL, NULL, /* filter, filterarg */
257 MCLBYTES * BFE_MAXTXSEGS, /* maxsize */
258 BFE_MAXTXSEGS, /* nsegments */
259 MCLBYTES, /* maxsegsize */
261 NULL, NULL, /* lockfunc, lockarg */
262 &sc->bfe_txmbuf_tag);
264 device_printf(sc->bfe_dev,
265 "cannot create Tx buffer DMA tag.\n");
269 /* Create tag for Rx buffers. */
270 error = bus_dma_tag_create(sc->bfe_parent_tag, /* parent */
271 1, 0, /* alignment, boundary */
272 BUS_SPACE_MAXADDR, /* lowaddr */
273 BUS_SPACE_MAXADDR, /* highaddr */
274 NULL, NULL, /* filter, filterarg */
275 MCLBYTES, /* maxsize */
277 MCLBYTES, /* maxsegsize */
279 NULL, NULL, /* lockfunc, lockarg */
280 &sc->bfe_rxmbuf_tag);
282 device_printf(sc->bfe_dev,
283 "cannot create Rx buffer DMA tag.\n");
287 /* Allocate DMA'able memory and load DMA map. */
288 error = bus_dmamem_alloc(sc->bfe_tx_tag, (void *)&sc->bfe_tx_list,
289 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_tx_map);
291 device_printf(sc->bfe_dev,
292 "cannot allocate DMA'able memory for Tx ring.\n");
296 error = bus_dmamap_load(sc->bfe_tx_tag, sc->bfe_tx_map,
297 sc->bfe_tx_list, BFE_TX_LIST_SIZE, bfe_dma_map, &ctx,
299 if (error != 0 || ctx.bfe_busaddr == 0) {
300 device_printf(sc->bfe_dev,
301 "cannot load DMA'able memory for Tx ring.\n");
304 sc->bfe_tx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
306 error = bus_dmamem_alloc(sc->bfe_rx_tag, (void *)&sc->bfe_rx_list,
307 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, &sc->bfe_rx_map);
309 device_printf(sc->bfe_dev,
310 "cannot allocate DMA'able memory for Rx ring.\n");
314 error = bus_dmamap_load(sc->bfe_rx_tag, sc->bfe_rx_map,
315 sc->bfe_rx_list, BFE_RX_LIST_SIZE, bfe_dma_map, &ctx,
317 if (error != 0 || ctx.bfe_busaddr == 0) {
318 device_printf(sc->bfe_dev,
319 "cannot load DMA'able memory for Rx ring.\n");
322 sc->bfe_rx_dma = BFE_ADDR_LO(ctx.bfe_busaddr);
324 /* Create DMA maps for Tx buffers. */
325 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
326 td = &sc->bfe_tx_ring[i];
329 error = bus_dmamap_create(sc->bfe_txmbuf_tag, 0, &td->bfe_map);
331 device_printf(sc->bfe_dev,
332 "cannot create DMA map for Tx.\n");
337 /* Create spare DMA map for Rx buffers. */
338 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &sc->bfe_rx_sparemap);
340 device_printf(sc->bfe_dev, "cannot create spare DMA map for Rx.\n");
343 /* Create DMA maps for Rx buffers. */
344 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
345 rd = &sc->bfe_rx_ring[i];
349 error = bus_dmamap_create(sc->bfe_rxmbuf_tag, 0, &rd->bfe_map);
351 device_printf(sc->bfe_dev,
352 "cannot create DMA map for Rx.\n");
362 bfe_dma_free(struct bfe_softc *sc)
364 struct bfe_tx_data *td;
365 struct bfe_rx_data *rd;
369 if (sc->bfe_tx_tag != NULL) {
370 if (sc->bfe_tx_map != NULL)
371 bus_dmamap_unload(sc->bfe_tx_tag, sc->bfe_tx_map);
372 if (sc->bfe_tx_map != NULL && sc->bfe_tx_list != NULL)
373 bus_dmamem_free(sc->bfe_tx_tag, sc->bfe_tx_list,
375 sc->bfe_tx_map = NULL;
376 sc->bfe_tx_list = NULL;
377 bus_dma_tag_destroy(sc->bfe_tx_tag);
378 sc->bfe_tx_tag = NULL;
382 if (sc->bfe_rx_tag != NULL) {
383 if (sc->bfe_rx_map != NULL)
384 bus_dmamap_unload(sc->bfe_rx_tag, sc->bfe_rx_map);
385 if (sc->bfe_rx_map != NULL && sc->bfe_rx_list != NULL)
386 bus_dmamem_free(sc->bfe_rx_tag, sc->bfe_rx_list,
388 sc->bfe_rx_map = NULL;
389 sc->bfe_rx_list = NULL;
390 bus_dma_tag_destroy(sc->bfe_rx_tag);
391 sc->bfe_rx_tag = NULL;
395 if (sc->bfe_txmbuf_tag != NULL) {
396 for (i = 0; i < BFE_TX_LIST_CNT; i++) {
397 td = &sc->bfe_tx_ring[i];
398 if (td->bfe_map != NULL) {
399 bus_dmamap_destroy(sc->bfe_txmbuf_tag,
404 bus_dma_tag_destroy(sc->bfe_txmbuf_tag);
405 sc->bfe_txmbuf_tag = NULL;
409 if (sc->bfe_rxmbuf_tag != NULL) {
410 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
411 rd = &sc->bfe_rx_ring[i];
412 if (rd->bfe_map != NULL) {
413 bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
418 if (sc->bfe_rx_sparemap != NULL) {
419 bus_dmamap_destroy(sc->bfe_rxmbuf_tag,
420 sc->bfe_rx_sparemap);
421 sc->bfe_rx_sparemap = NULL;
423 bus_dma_tag_destroy(sc->bfe_rxmbuf_tag);
424 sc->bfe_rxmbuf_tag = NULL;
427 if (sc->bfe_parent_tag != NULL) {
428 bus_dma_tag_destroy(sc->bfe_parent_tag);
429 sc->bfe_parent_tag = NULL;
434 bfe_attach(device_t dev)
436 struct ifnet *ifp = NULL;
437 struct bfe_softc *sc;
440 sc = device_get_softc(dev);
441 mtx_init(&sc->bfe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
443 callout_init_mtx(&sc->bfe_stat_co, &sc->bfe_mtx, 0);
448 * Map control/status registers.
450 pci_enable_busmaster(dev);
453 sc->bfe_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
455 if (sc->bfe_res == NULL) {
456 device_printf(dev, "couldn't map memory\n");
461 /* Allocate interrupt */
464 sc->bfe_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
465 RF_SHAREABLE | RF_ACTIVE);
466 if (sc->bfe_irq == NULL) {
467 device_printf(dev, "couldn't map interrupt\n");
472 if (bfe_dma_alloc(sc) != 0) {
473 device_printf(dev, "failed to allocate DMA resources\n");
478 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
479 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
480 "stats", CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_bfe_stats,
483 /* Set up ifnet structure */
484 ifp = sc->bfe_ifp = if_alloc(IFT_ETHER);
486 device_printf(dev, "failed to if_alloc()\n");
491 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
492 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
493 ifp->if_ioctl = bfe_ioctl;
494 ifp->if_start = bfe_start;
495 ifp->if_init = bfe_init;
496 ifp->if_mtu = ETHERMTU;
497 IFQ_SET_MAXLEN(&ifp->if_snd, BFE_TX_QLEN);
498 ifp->if_snd.ifq_drv_maxlen = BFE_TX_QLEN;
499 IFQ_SET_READY(&ifp->if_snd);
503 /* Reset the chip and turn on the PHY */
508 if (mii_phy_probe(dev, &sc->bfe_miibus,
509 bfe_ifmedia_upd, bfe_ifmedia_sts)) {
510 device_printf(dev, "MII without any PHY!\n");
515 ether_ifattach(ifp, sc->bfe_enaddr);
518 * Tell the upper layer(s) we support long frames.
520 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header);
521 ifp->if_capabilities |= IFCAP_VLAN_MTU;
522 ifp->if_capenable |= IFCAP_VLAN_MTU;
525 * Hook interrupt last to avoid having to lock softc
527 error = bus_setup_intr(dev, sc->bfe_irq, INTR_TYPE_NET | INTR_MPSAFE,
528 NULL, bfe_intr, sc, &sc->bfe_intrhand);
531 device_printf(dev, "couldn't set up irq\n");
541 bfe_detach(device_t dev)
543 struct bfe_softc *sc;
546 sc = device_get_softc(dev);
550 if (device_is_attached(dev)) {
552 sc->bfe_flags |= BFE_FLAG_DETACH;
555 callout_drain(&sc->bfe_stat_co);
564 bus_generic_detach(dev);
565 if (sc->bfe_miibus != NULL)
566 device_delete_child(dev, sc->bfe_miibus);
568 bfe_release_resources(sc);
570 mtx_destroy(&sc->bfe_mtx);
576 * Stop all chip I/O so that the kernel's probe routines don't
577 * get confused by errant DMAs when rebooting.
580 bfe_shutdown(device_t dev)
582 struct bfe_softc *sc;
584 sc = device_get_softc(dev);
594 bfe_suspend(device_t dev)
596 struct bfe_softc *sc;
598 sc = device_get_softc(dev);
607 bfe_resume(device_t dev)
609 struct bfe_softc *sc;
612 sc = device_get_softc(dev);
616 if (ifp->if_flags & IFF_UP) {
618 if (ifp->if_drv_flags & IFF_DRV_RUNNING &&
619 !IFQ_DRV_IS_EMPTY(&ifp->if_snd))
620 bfe_start_locked(ifp);
628 bfe_miibus_readreg(device_t dev, int phy, int reg)
630 struct bfe_softc *sc;
633 sc = device_get_softc(dev);
634 if (phy != sc->bfe_phyaddr)
636 bfe_readphy(sc, reg, &ret);
642 bfe_miibus_writereg(device_t dev, int phy, int reg, int val)
644 struct bfe_softc *sc;
646 sc = device_get_softc(dev);
647 if (phy != sc->bfe_phyaddr)
649 bfe_writephy(sc, reg, val);
655 bfe_miibus_statchg(device_t dev)
657 struct bfe_softc *sc;
658 struct mii_data *mii;
661 sc = device_get_softc(dev);
662 mii = device_get_softc(sc->bfe_miibus);
664 sc->bfe_flags &= ~BFE_FLAG_LINK;
665 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
666 (IFM_ACTIVE | IFM_AVALID)) {
667 switch (IFM_SUBTYPE(mii->mii_media_active)) {
670 sc->bfe_flags |= BFE_FLAG_LINK;
677 /* XXX Should stop Rx/Tx engine prior to touching MAC. */
678 val = CSR_READ_4(sc, BFE_TX_CTRL);
679 val &= ~BFE_TX_DUPLEX;
680 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
681 val |= BFE_TX_DUPLEX;
684 flow = CSR_READ_4(sc, BFE_RXCONF);
685 flow &= ~BFE_RXCONF_FLOW;
686 if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) &
687 IFM_ETH_RXPAUSE) != 0)
688 flow |= BFE_RXCONF_FLOW;
689 CSR_WRITE_4(sc, BFE_RXCONF, flow);
691 * It seems that the hardware has Tx pause issues
692 * so enable only Rx pause.
694 flow = CSR_READ_4(sc, BFE_MAC_FLOW);
695 flow &= ~BFE_FLOW_PAUSE_ENAB;
696 CSR_WRITE_4(sc, BFE_MAC_FLOW, flow);
699 CSR_WRITE_4(sc, BFE_TX_CTRL, val);
703 bfe_tx_ring_free(struct bfe_softc *sc)
707 for(i = 0; i < BFE_TX_LIST_CNT; i++) {
708 if (sc->bfe_tx_ring[i].bfe_mbuf != NULL) {
709 bus_dmamap_sync(sc->bfe_txmbuf_tag,
710 sc->bfe_tx_ring[i].bfe_map, BUS_DMASYNC_POSTWRITE);
711 bus_dmamap_unload(sc->bfe_txmbuf_tag,
712 sc->bfe_tx_ring[i].bfe_map);
713 m_freem(sc->bfe_tx_ring[i].bfe_mbuf);
714 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
717 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
718 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
719 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
723 bfe_rx_ring_free(struct bfe_softc *sc)
727 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
728 if (sc->bfe_rx_ring[i].bfe_mbuf != NULL) {
729 bus_dmamap_sync(sc->bfe_rxmbuf_tag,
730 sc->bfe_rx_ring[i].bfe_map, BUS_DMASYNC_POSTREAD);
731 bus_dmamap_unload(sc->bfe_rxmbuf_tag,
732 sc->bfe_rx_ring[i].bfe_map);
733 m_freem(sc->bfe_rx_ring[i].bfe_mbuf);
734 sc->bfe_rx_ring[i].bfe_mbuf = NULL;
737 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
738 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
739 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
743 bfe_list_rx_init(struct bfe_softc *sc)
745 struct bfe_rx_data *rd;
748 sc->bfe_rx_prod = sc->bfe_rx_cons = 0;
749 bzero(sc->bfe_rx_list, BFE_RX_LIST_SIZE);
750 for (i = 0; i < BFE_RX_LIST_CNT; i++) {
751 rd = &sc->bfe_rx_ring[i];
754 if (bfe_list_newbuf(sc, i) != 0)
758 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
759 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
760 CSR_WRITE_4(sc, BFE_DMARX_PTR, (i * sizeof(struct bfe_desc)));
766 bfe_list_tx_init(struct bfe_softc *sc)
770 sc->bfe_tx_cnt = sc->bfe_tx_prod = sc->bfe_tx_cons = 0;
771 bzero(sc->bfe_tx_list, BFE_TX_LIST_SIZE);
772 for (i = 0; i < BFE_TX_LIST_CNT; i++)
773 sc->bfe_tx_ring[i].bfe_mbuf = NULL;
775 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
776 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
780 bfe_discard_buf(struct bfe_softc *sc, int c)
782 struct bfe_rx_data *r;
785 r = &sc->bfe_rx_ring[c];
786 d = &sc->bfe_rx_list[c];
787 d->bfe_ctrl = htole32(r->bfe_ctrl);
791 bfe_list_newbuf(struct bfe_softc *sc, int c)
793 struct bfe_rxheader *rx_header;
795 struct bfe_rx_data *r;
797 bus_dma_segment_t segs[1];
802 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR);
803 m->m_len = m->m_pkthdr.len = MCLBYTES;
805 if (bus_dmamap_load_mbuf_sg(sc->bfe_rxmbuf_tag, sc->bfe_rx_sparemap,
806 m, segs, &nsegs, 0) != 0) {
811 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
812 r = &sc->bfe_rx_ring[c];
813 if (r->bfe_mbuf != NULL) {
814 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map,
815 BUS_DMASYNC_POSTREAD);
816 bus_dmamap_unload(sc->bfe_rxmbuf_tag, r->bfe_map);
819 r->bfe_map = sc->bfe_rx_sparemap;
820 sc->bfe_rx_sparemap = map;
823 rx_header = mtod(m, struct bfe_rxheader *);
825 rx_header->flags = 0;
826 bus_dmamap_sync(sc->bfe_rxmbuf_tag, r->bfe_map, BUS_DMASYNC_PREREAD);
828 ctrl = segs[0].ds_len & BFE_DESC_LEN;
829 KASSERT(ctrl > ETHER_MAX_LEN + 32, ("%s: buffer size too small(%d)!",
831 if (c == BFE_RX_LIST_CNT - 1)
832 ctrl |= BFE_DESC_EOT;
835 d = &sc->bfe_rx_list[c];
836 d->bfe_ctrl = htole32(ctrl);
837 /* The chip needs all addresses to be added to BFE_PCI_DMA. */
838 d->bfe_addr = htole32(BFE_ADDR_LO(segs[0].ds_addr) + BFE_PCI_DMA);
844 bfe_get_config(struct bfe_softc *sc)
846 u_int8_t eeprom[128];
848 bfe_read_eeprom(sc, eeprom);
850 sc->bfe_enaddr[0] = eeprom[79];
851 sc->bfe_enaddr[1] = eeprom[78];
852 sc->bfe_enaddr[2] = eeprom[81];
853 sc->bfe_enaddr[3] = eeprom[80];
854 sc->bfe_enaddr[4] = eeprom[83];
855 sc->bfe_enaddr[5] = eeprom[82];
857 sc->bfe_phyaddr = eeprom[90] & 0x1f;
858 sc->bfe_mdc_port = (eeprom[90] >> 14) & 0x1;
860 sc->bfe_core_unit = 0;
861 sc->bfe_dma_offset = BFE_PCI_DMA;
865 bfe_pci_setup(struct bfe_softc *sc, u_int32_t cores)
867 u_int32_t bar_orig, pci_rev, val;
869 bar_orig = pci_read_config(sc->bfe_dev, BFE_BAR0_WIN, 4);
870 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, BFE_REG_PCI, 4);
871 pci_rev = CSR_READ_4(sc, BFE_SBIDHIGH) & BFE_RC_MASK;
873 val = CSR_READ_4(sc, BFE_SBINTVEC);
875 CSR_WRITE_4(sc, BFE_SBINTVEC, val);
877 val = CSR_READ_4(sc, BFE_SSB_PCI_TRANS_2);
878 val |= BFE_SSB_PCI_PREF | BFE_SSB_PCI_BURST;
879 CSR_WRITE_4(sc, BFE_SSB_PCI_TRANS_2, val);
881 pci_write_config(sc->bfe_dev, BFE_BAR0_WIN, bar_orig, 4);
885 bfe_clear_stats(struct bfe_softc *sc)
891 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
892 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
894 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
899 bfe_resetphy(struct bfe_softc *sc)
903 bfe_writephy(sc, 0, BMCR_RESET);
905 bfe_readphy(sc, 0, &val);
906 if (val & BMCR_RESET) {
907 device_printf(sc->bfe_dev, "PHY Reset would not complete.\n");
914 bfe_chip_halt(struct bfe_softc *sc)
917 /* disable interrupts - not that it actually does..*/
918 CSR_WRITE_4(sc, BFE_IMASK, 0);
919 CSR_READ_4(sc, BFE_IMASK);
921 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
922 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 200, 1);
924 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
925 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
930 bfe_chip_reset(struct bfe_softc *sc)
936 /* Set the interrupt vector for the enet core */
937 bfe_pci_setup(sc, BFE_INTVEC_ENET0);
940 val = CSR_READ_4(sc, BFE_SBTMSLOW) &
941 (BFE_RESET | BFE_REJECT | BFE_CLOCK);
942 if (val == BFE_CLOCK) {
943 /* It is, so shut it down */
944 CSR_WRITE_4(sc, BFE_RCV_LAZY, 0);
945 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE);
946 bfe_wait_bit(sc, BFE_ENET_CTRL, BFE_ENET_DISABLE, 100, 1);
947 CSR_WRITE_4(sc, BFE_DMATX_CTRL, 0);
948 if (CSR_READ_4(sc, BFE_DMARX_STAT) & BFE_STAT_EMASK)
949 bfe_wait_bit(sc, BFE_DMARX_STAT, BFE_STAT_SIDLE,
951 CSR_WRITE_4(sc, BFE_DMARX_CTRL, 0);
958 * We want the phy registers to be accessible even when
959 * the driver is "downed" so initialize MDC preamble, frequency,
960 * and whether internal or external phy here.
963 /* 4402 has 62.5Mhz SB clock and internal phy */
964 CSR_WRITE_4(sc, BFE_MDIO_CTRL, 0x8d);
966 /* Internal or external PHY? */
967 val = CSR_READ_4(sc, BFE_DEVCTRL);
968 if (!(val & BFE_IPP))
969 CSR_WRITE_4(sc, BFE_ENET_CTRL, BFE_ENET_EPSEL);
970 else if (CSR_READ_4(sc, BFE_DEVCTRL) & BFE_EPR) {
971 BFE_AND(sc, BFE_DEVCTRL, ~BFE_EPR);
975 /* Enable CRC32 generation and set proper LED modes */
976 BFE_OR(sc, BFE_MAC_CTRL, BFE_CTRL_CRC32_ENAB | BFE_CTRL_LED);
978 /* Reset or clear powerdown control bit */
979 BFE_AND(sc, BFE_MAC_CTRL, ~BFE_CTRL_PDOWN);
981 CSR_WRITE_4(sc, BFE_RCV_LAZY, ((1 << BFE_LAZY_FC_SHIFT) &
985 * We don't want lazy interrupts, so just send them at
986 * the end of a frame, please
988 BFE_OR(sc, BFE_RCV_LAZY, 0);
990 /* Set max lengths, accounting for VLAN tags */
991 CSR_WRITE_4(sc, BFE_RXMAXLEN, ETHER_MAX_LEN+32);
992 CSR_WRITE_4(sc, BFE_TXMAXLEN, ETHER_MAX_LEN+32);
994 /* Set watermark XXX - magic */
995 CSR_WRITE_4(sc, BFE_TX_WMARK, 56);
998 * Initialise DMA channels
999 * - not forgetting dma addresses need to be added to BFE_PCI_DMA
1001 CSR_WRITE_4(sc, BFE_DMATX_CTRL, BFE_TX_CTRL_ENABLE);
1002 CSR_WRITE_4(sc, BFE_DMATX_ADDR, sc->bfe_tx_dma + BFE_PCI_DMA);
1004 CSR_WRITE_4(sc, BFE_DMARX_CTRL, (BFE_RX_OFFSET << BFE_RX_CTRL_ROSHIFT) |
1005 BFE_RX_CTRL_ENABLE);
1006 CSR_WRITE_4(sc, BFE_DMARX_ADDR, sc->bfe_rx_dma + BFE_PCI_DMA);
1013 bfe_core_disable(struct bfe_softc *sc)
1015 if ((CSR_READ_4(sc, BFE_SBTMSLOW)) & BFE_RESET)
1019 * Set reject, wait for it set, then wait for the core to stop
1020 * being busy, then set reset and reject and enable the clocks.
1022 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_CLOCK));
1023 bfe_wait_bit(sc, BFE_SBTMSLOW, BFE_REJECT, 1000, 0);
1024 bfe_wait_bit(sc, BFE_SBTMSHIGH, BFE_BUSY, 1000, 1);
1025 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_FGC | BFE_CLOCK | BFE_REJECT |
1027 CSR_READ_4(sc, BFE_SBTMSLOW);
1029 /* Leave reset and reject set */
1030 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_REJECT | BFE_RESET));
1035 bfe_core_reset(struct bfe_softc *sc)
1039 /* Disable the core */
1040 bfe_core_disable(sc);
1042 /* and bring it back up */
1043 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_RESET | BFE_CLOCK | BFE_FGC));
1044 CSR_READ_4(sc, BFE_SBTMSLOW);
1047 /* Chip bug, clear SERR, IB and TO if they are set. */
1048 if (CSR_READ_4(sc, BFE_SBTMSHIGH) & BFE_SERR)
1049 CSR_WRITE_4(sc, BFE_SBTMSHIGH, 0);
1050 val = CSR_READ_4(sc, BFE_SBIMSTATE);
1051 if (val & (BFE_IBE | BFE_TO))
1052 CSR_WRITE_4(sc, BFE_SBIMSTATE, val & ~(BFE_IBE | BFE_TO));
1054 /* Clear reset and allow it to move through the core */
1055 CSR_WRITE_4(sc, BFE_SBTMSLOW, (BFE_CLOCK | BFE_FGC));
1056 CSR_READ_4(sc, BFE_SBTMSLOW);
1059 /* Leave the clock set */
1060 CSR_WRITE_4(sc, BFE_SBTMSLOW, BFE_CLOCK);
1061 CSR_READ_4(sc, BFE_SBTMSLOW);
1066 bfe_cam_write(struct bfe_softc *sc, u_char *data, int index)
1070 val = ((u_int32_t) data[2]) << 24;
1071 val |= ((u_int32_t) data[3]) << 16;
1072 val |= ((u_int32_t) data[4]) << 8;
1073 val |= ((u_int32_t) data[5]);
1074 CSR_WRITE_4(sc, BFE_CAM_DATA_LO, val);
1075 val = (BFE_CAM_HI_VALID |
1076 (((u_int32_t) data[0]) << 8) |
1077 (((u_int32_t) data[1])));
1078 CSR_WRITE_4(sc, BFE_CAM_DATA_HI, val);
1079 CSR_WRITE_4(sc, BFE_CAM_CTRL, (BFE_CAM_WRITE |
1080 ((u_int32_t) index << BFE_CAM_INDEX_SHIFT)));
1081 bfe_wait_bit(sc, BFE_CAM_CTRL, BFE_CAM_BUSY, 10000, 1);
1085 bfe_set_rx_mode(struct bfe_softc *sc)
1087 struct ifnet *ifp = sc->bfe_ifp;
1088 struct ifmultiaddr *ifma;
1092 BFE_LOCK_ASSERT(sc);
1094 val = CSR_READ_4(sc, BFE_RXCONF);
1096 if (ifp->if_flags & IFF_PROMISC)
1097 val |= BFE_RXCONF_PROMISC;
1099 val &= ~BFE_RXCONF_PROMISC;
1101 if (ifp->if_flags & IFF_BROADCAST)
1102 val &= ~BFE_RXCONF_DBCAST;
1104 val |= BFE_RXCONF_DBCAST;
1107 CSR_WRITE_4(sc, BFE_CAM_CTRL, 0);
1108 bfe_cam_write(sc, IF_LLADDR(sc->bfe_ifp), i++);
1110 if (ifp->if_flags & IFF_ALLMULTI)
1111 val |= BFE_RXCONF_ALLMULTI;
1113 val &= ~BFE_RXCONF_ALLMULTI;
1114 if_maddr_rlock(ifp);
1115 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
1116 if (ifma->ifma_addr->sa_family != AF_LINK)
1119 LLADDR((struct sockaddr_dl *)ifma->ifma_addr), i++);
1121 if_maddr_runlock(ifp);
1124 CSR_WRITE_4(sc, BFE_RXCONF, val);
1125 BFE_OR(sc, BFE_CAM_CTRL, BFE_CAM_ENABLE);
1129 bfe_dma_map(void *arg, bus_dma_segment_t *segs, int nseg, int error)
1131 struct bfe_dmamap_arg *ctx;
1136 KASSERT(nseg == 1, ("%s : %d segments returned!", __func__, nseg));
1138 ctx = (struct bfe_dmamap_arg *)arg;
1139 ctx->bfe_busaddr = segs[0].ds_addr;
1143 bfe_release_resources(struct bfe_softc *sc)
1146 if (sc->bfe_intrhand != NULL)
1147 bus_teardown_intr(sc->bfe_dev, sc->bfe_irq, sc->bfe_intrhand);
1149 if (sc->bfe_irq != NULL)
1150 bus_release_resource(sc->bfe_dev, SYS_RES_IRQ, 0, sc->bfe_irq);
1152 if (sc->bfe_res != NULL)
1153 bus_release_resource(sc->bfe_dev, SYS_RES_MEMORY, PCIR_BAR(0),
1156 if (sc->bfe_ifp != NULL)
1157 if_free(sc->bfe_ifp);
1161 bfe_read_eeprom(struct bfe_softc *sc, u_int8_t *data)
1164 u_int16_t *ptr = (u_int16_t *)data;
1166 for(i = 0; i < 128; i += 2)
1167 ptr[i/2] = CSR_READ_4(sc, 4096 + i);
1171 bfe_wait_bit(struct bfe_softc *sc, u_int32_t reg, u_int32_t bit,
1172 u_long timeout, const int clear)
1176 for (i = 0; i < timeout; i++) {
1177 u_int32_t val = CSR_READ_4(sc, reg);
1179 if (clear && !(val & bit))
1181 if (!clear && (val & bit))
1186 device_printf(sc->bfe_dev,
1187 "BUG! Timeout waiting for bit %08x of register "
1188 "%x to %s.\n", bit, reg, (clear ? "clear" : "set"));
1195 bfe_readphy(struct bfe_softc *sc, u_int32_t reg, u_int32_t *val)
1200 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1201 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1202 (BFE_MDIO_OP_READ << BFE_MDIO_OP_SHIFT) |
1203 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1204 (reg << BFE_MDIO_RA_SHIFT) |
1205 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT)));
1206 err = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1207 *val = CSR_READ_4(sc, BFE_MDIO_DATA) & BFE_MDIO_DATA_DATA;
1213 bfe_writephy(struct bfe_softc *sc, u_int32_t reg, u_int32_t val)
1217 CSR_WRITE_4(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII);
1218 CSR_WRITE_4(sc, BFE_MDIO_DATA, (BFE_MDIO_SB_START |
1219 (BFE_MDIO_OP_WRITE << BFE_MDIO_OP_SHIFT) |
1220 (sc->bfe_phyaddr << BFE_MDIO_PMD_SHIFT) |
1221 (reg << BFE_MDIO_RA_SHIFT) |
1222 (BFE_MDIO_TA_VALID << BFE_MDIO_TA_SHIFT) |
1223 (val & BFE_MDIO_DATA_DATA)));
1224 status = bfe_wait_bit(sc, BFE_EMAC_ISTAT, BFE_EMAC_INT_MII, 100, 0);
1230 * XXX - I think this is handled by the PHY driver, but it can't hurt to do it
1234 bfe_setupphy(struct bfe_softc *sc)
1238 /* Enable activity LED */
1239 bfe_readphy(sc, 26, &val);
1240 bfe_writephy(sc, 26, val & 0x7fff);
1241 bfe_readphy(sc, 26, &val);
1243 /* Enable traffic meter LED mode */
1244 bfe_readphy(sc, 27, &val);
1245 bfe_writephy(sc, 27, val | (1 << 6));
1251 bfe_stats_update(struct bfe_softc *sc)
1253 struct bfe_hw_stats *stats;
1255 uint32_t mib[BFE_MIB_CNT];
1258 BFE_LOCK_ASSERT(sc);
1261 CSR_WRITE_4(sc, BFE_MIB_CTRL, BFE_MIB_CLR_ON_READ);
1262 for (reg = BFE_TX_GOOD_O; reg <= BFE_TX_PAUSE; reg += 4)
1263 *val++ = CSR_READ_4(sc, reg);
1264 for (reg = BFE_RX_GOOD_O; reg <= BFE_RX_NPAUSE; reg += 4)
1265 *val++ = CSR_READ_4(sc, reg);
1268 stats = &sc->bfe_stats;
1270 stats->tx_good_octets += mib[MIB_TX_GOOD_O];
1271 stats->tx_good_frames += mib[MIB_TX_GOOD_P];
1272 stats->tx_octets += mib[MIB_TX_O];
1273 stats->tx_frames += mib[MIB_TX_P];
1274 stats->tx_bcast_frames += mib[MIB_TX_BCAST];
1275 stats->tx_mcast_frames += mib[MIB_TX_MCAST];
1276 stats->tx_pkts_64 += mib[MIB_TX_64];
1277 stats->tx_pkts_65_127 += mib[MIB_TX_65_127];
1278 stats->tx_pkts_128_255 += mib[MIB_TX_128_255];
1279 stats->tx_pkts_256_511 += mib[MIB_TX_256_511];
1280 stats->tx_pkts_512_1023 += mib[MIB_TX_512_1023];
1281 stats->tx_pkts_1024_max += mib[MIB_TX_1024_MAX];
1282 stats->tx_jabbers += mib[MIB_TX_JABBER];
1283 stats->tx_oversize_frames += mib[MIB_TX_OSIZE];
1284 stats->tx_frag_frames += mib[MIB_TX_FRAG];
1285 stats->tx_underruns += mib[MIB_TX_URUNS];
1286 stats->tx_colls += mib[MIB_TX_TCOLS];
1287 stats->tx_single_colls += mib[MIB_TX_SCOLS];
1288 stats->tx_multi_colls += mib[MIB_TX_MCOLS];
1289 stats->tx_excess_colls += mib[MIB_TX_ECOLS];
1290 stats->tx_late_colls += mib[MIB_TX_LCOLS];
1291 stats->tx_deferrals += mib[MIB_TX_DEFERED];
1292 stats->tx_carrier_losts += mib[MIB_TX_CLOST];
1293 stats->tx_pause_frames += mib[MIB_TX_PAUSE];
1295 stats->rx_good_octets += mib[MIB_RX_GOOD_O];
1296 stats->rx_good_frames += mib[MIB_RX_GOOD_P];
1297 stats->rx_octets += mib[MIB_RX_O];
1298 stats->rx_frames += mib[MIB_RX_P];
1299 stats->rx_bcast_frames += mib[MIB_RX_BCAST];
1300 stats->rx_mcast_frames += mib[MIB_RX_MCAST];
1301 stats->rx_pkts_64 += mib[MIB_RX_64];
1302 stats->rx_pkts_65_127 += mib[MIB_RX_65_127];
1303 stats->rx_pkts_128_255 += mib[MIB_RX_128_255];
1304 stats->rx_pkts_256_511 += mib[MIB_RX_256_511];
1305 stats->rx_pkts_512_1023 += mib[MIB_RX_512_1023];
1306 stats->rx_pkts_1024_max += mib[MIB_RX_1024_MAX];
1307 stats->rx_jabbers += mib[MIB_RX_JABBER];
1308 stats->rx_oversize_frames += mib[MIB_RX_OSIZE];
1309 stats->rx_frag_frames += mib[MIB_RX_FRAG];
1310 stats->rx_missed_frames += mib[MIB_RX_MISS];
1311 stats->rx_crc_align_errs += mib[MIB_RX_CRCA];
1312 stats->rx_runts += mib[MIB_RX_USIZE];
1313 stats->rx_crc_errs += mib[MIB_RX_CRC];
1314 stats->rx_align_errs += mib[MIB_RX_ALIGN];
1315 stats->rx_symbol_errs += mib[MIB_RX_SYM];
1316 stats->rx_pause_frames += mib[MIB_RX_PAUSE];
1317 stats->rx_control_frames += mib[MIB_RX_NPAUSE];
1319 /* Update counters in ifnet. */
1320 ifp->if_opackets += (u_long)mib[MIB_TX_GOOD_P];
1321 ifp->if_collisions += (u_long)mib[MIB_TX_TCOLS];
1322 ifp->if_oerrors += (u_long)mib[MIB_TX_URUNS] +
1323 (u_long)mib[MIB_TX_ECOLS] +
1324 (u_long)mib[MIB_TX_DEFERED] +
1325 (u_long)mib[MIB_TX_CLOST];
1327 ifp->if_ipackets += (u_long)mib[MIB_RX_GOOD_P];
1329 ifp->if_ierrors += mib[MIB_RX_JABBER] +
1339 bfe_txeof(struct bfe_softc *sc)
1341 struct bfe_tx_data *r;
1345 BFE_LOCK_ASSERT(sc);
1349 chipidx = CSR_READ_4(sc, BFE_DMATX_STAT) & BFE_STAT_CDMASK;
1350 chipidx /= sizeof(struct bfe_desc);
1352 i = sc->bfe_tx_cons;
1355 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1356 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1357 /* Go through the mbufs and free those that have been transmitted */
1358 for (; i != chipidx; BFE_INC(i, BFE_TX_LIST_CNT)) {
1359 r = &sc->bfe_tx_ring[i];
1361 if (r->bfe_mbuf == NULL)
1363 bus_dmamap_sync(sc->bfe_txmbuf_tag, r->bfe_map,
1364 BUS_DMASYNC_POSTWRITE);
1365 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1367 m_freem(r->bfe_mbuf);
1371 if (i != sc->bfe_tx_cons) {
1372 /* we freed up some mbufs */
1373 sc->bfe_tx_cons = i;
1374 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1377 if (sc->bfe_tx_cnt == 0)
1378 sc->bfe_watchdog_timer = 0;
1381 /* Pass a received packet up the stack */
1383 bfe_rxeof(struct bfe_softc *sc)
1387 struct bfe_rxheader *rxheader;
1388 struct bfe_rx_data *r;
1390 u_int32_t status, current, len, flags;
1392 BFE_LOCK_ASSERT(sc);
1393 cons = sc->bfe_rx_cons;
1394 status = CSR_READ_4(sc, BFE_DMARX_STAT);
1395 current = (status & BFE_STAT_CDMASK) / sizeof(struct bfe_desc);
1399 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1400 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1402 for (prog = 0; current != cons; prog++,
1403 BFE_INC(cons, BFE_RX_LIST_CNT)) {
1404 r = &sc->bfe_rx_ring[cons];
1407 * Rx status should be read from mbuf such that we can't
1408 * delay bus_dmamap_sync(9). This hardware limiation
1409 * results in inefficent mbuf usage as bfe(4) couldn't
1410 * reuse mapped buffer from errored frame.
1412 if (bfe_list_newbuf(sc, cons) != 0) {
1414 bfe_discard_buf(sc, cons);
1417 rxheader = mtod(m, struct bfe_rxheader*);
1418 len = le16toh(rxheader->len);
1419 flags = le16toh(rxheader->flags);
1421 /* Remove CRC bytes. */
1422 len -= ETHER_CRC_LEN;
1424 /* flag an error and try again */
1425 if ((len > ETHER_MAX_LEN+32) || (flags & BFE_RX_FLAG_ERRORS)) {
1430 /* Make sure to skip header bytes written by hardware. */
1431 m_adj(m, BFE_RX_OFFSET);
1432 m->m_len = m->m_pkthdr.len = len;
1434 m->m_pkthdr.rcvif = ifp;
1436 (*ifp->if_input)(ifp, m);
1441 sc->bfe_rx_cons = cons;
1442 bus_dmamap_sync(sc->bfe_rx_tag, sc->bfe_rx_map,
1443 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1450 struct bfe_softc *sc = xsc;
1458 istat = CSR_READ_4(sc, BFE_ISTAT);
1461 * Defer unsolicited interrupts - This is necessary because setting the
1462 * chips interrupt mask register to 0 doesn't actually stop the
1465 istat &= BFE_IMASK_DEF;
1466 CSR_WRITE_4(sc, BFE_ISTAT, istat);
1467 CSR_READ_4(sc, BFE_ISTAT);
1469 /* not expecting this interrupt, disregard it */
1470 if (istat == 0 || (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1475 /* A packet was received */
1476 if (istat & BFE_ISTAT_RX)
1479 /* A packet was sent */
1480 if (istat & BFE_ISTAT_TX)
1483 if (istat & BFE_ISTAT_ERRORS) {
1485 if (istat & BFE_ISTAT_DSCE) {
1486 device_printf(sc->bfe_dev, "Descriptor Error\n");
1492 if (istat & BFE_ISTAT_DPE) {
1493 device_printf(sc->bfe_dev,
1494 "Descriptor Protocol Error\n");
1499 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1500 bfe_init_locked(sc);
1503 /* We have packets pending, fire them out */
1504 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1505 bfe_start_locked(ifp);
1511 bfe_encap(struct bfe_softc *sc, struct mbuf **m_head)
1514 struct bfe_tx_data *r, *r1;
1517 bus_dma_segment_t txsegs[BFE_MAXTXSEGS];
1519 int error, i, nsegs;
1521 BFE_LOCK_ASSERT(sc);
1523 M_ASSERTPKTHDR((*m_head));
1525 si = cur = sc->bfe_tx_prod;
1526 r = &sc->bfe_tx_ring[cur];
1527 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map, *m_head,
1529 if (error == EFBIG) {
1530 m = m_collapse(*m_head, M_DONTWAIT, BFE_MAXTXSEGS);
1537 error = bus_dmamap_load_mbuf_sg(sc->bfe_txmbuf_tag, r->bfe_map,
1538 *m_head, txsegs, &nsegs, 0);
1544 } else if (error != 0)
1552 if (sc->bfe_tx_cnt + nsegs > BFE_TX_LIST_CNT - 1) {
1553 bus_dmamap_unload(sc->bfe_txmbuf_tag, r->bfe_map);
1557 for (i = 0; i < nsegs; i++) {
1558 d = &sc->bfe_tx_list[cur];
1559 d->bfe_ctrl = htole32(txsegs[i].ds_len & BFE_DESC_LEN);
1560 d->bfe_ctrl |= htole32(BFE_DESC_IOC);
1561 if (cur == BFE_TX_LIST_CNT - 1)
1563 * Tell the chip to wrap to the start of
1564 * the descriptor list.
1566 d->bfe_ctrl |= htole32(BFE_DESC_EOT);
1567 /* The chip needs all addresses to be added to BFE_PCI_DMA. */
1568 d->bfe_addr = htole32(BFE_ADDR_LO(txsegs[i].ds_addr) +
1570 BFE_INC(cur, BFE_TX_LIST_CNT);
1573 /* Update producer index. */
1574 sc->bfe_tx_prod = cur;
1576 /* Set EOF on the last descriptor. */
1577 cur = (cur + BFE_TX_LIST_CNT - 1) % BFE_TX_LIST_CNT;
1578 d = &sc->bfe_tx_list[cur];
1579 d->bfe_ctrl |= htole32(BFE_DESC_EOF);
1581 /* Lastly set SOF on the first descriptor to avoid races. */
1582 d = &sc->bfe_tx_list[si];
1583 d->bfe_ctrl |= htole32(BFE_DESC_SOF);
1585 r1 = &sc->bfe_tx_ring[cur];
1587 r->bfe_map = r1->bfe_map;
1589 r1->bfe_mbuf = *m_head;
1590 sc->bfe_tx_cnt += nsegs;
1592 bus_dmamap_sync(sc->bfe_txmbuf_tag, map, BUS_DMASYNC_PREWRITE);
1598 * Set up to transmit a packet.
1601 bfe_start(struct ifnet *ifp)
1603 BFE_LOCK((struct bfe_softc *)ifp->if_softc);
1604 bfe_start_locked(ifp);
1605 BFE_UNLOCK((struct bfe_softc *)ifp->if_softc);
1609 * Set up to transmit a packet. The softc is already locked.
1612 bfe_start_locked(struct ifnet *ifp)
1614 struct bfe_softc *sc;
1615 struct mbuf *m_head;
1620 BFE_LOCK_ASSERT(sc);
1623 * Not much point trying to send if the link is down
1624 * or we have nothing to send.
1626 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1627 IFF_DRV_RUNNING || (sc->bfe_flags & BFE_FLAG_LINK) == 0)
1630 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) &&
1631 sc->bfe_tx_cnt < BFE_TX_LIST_CNT - 1;) {
1632 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1637 * Pack the data into the tx ring. If we dont have
1638 * enough room, let the chip drain the ring.
1640 if (bfe_encap(sc, &m_head)) {
1643 IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1644 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1651 * If there's a BPF listener, bounce a copy of this frame
1654 BPF_MTAP(ifp, m_head);
1658 bus_dmamap_sync(sc->bfe_tx_tag, sc->bfe_tx_map,
1659 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1660 /* Transmit - twice due to apparent hardware bug */
1661 CSR_WRITE_4(sc, BFE_DMATX_PTR,
1662 sc->bfe_tx_prod * sizeof(struct bfe_desc));
1664 * XXX It seems the following write is not necessary
1665 * to kick Tx command. What might be required would be
1666 * a way flushing PCI posted write. Reading the register
1667 * back ensures the flush operation. In addition,
1668 * hardware will execute PCI posted write in the long
1669 * run and watchdog timer for the kick command was set
1670 * to 5 seconds. Therefore I think the second write
1671 * access is not necessary or could be replaced with
1674 CSR_WRITE_4(sc, BFE_DMATX_PTR,
1675 sc->bfe_tx_prod * sizeof(struct bfe_desc));
1678 * Set a timeout in case the chip goes out to lunch.
1680 sc->bfe_watchdog_timer = 5;
1687 BFE_LOCK((struct bfe_softc *)xsc);
1688 bfe_init_locked(xsc);
1689 BFE_UNLOCK((struct bfe_softc *)xsc);
1693 bfe_init_locked(void *xsc)
1695 struct bfe_softc *sc = (struct bfe_softc*)xsc;
1696 struct ifnet *ifp = sc->bfe_ifp;
1697 struct mii_data *mii;
1699 BFE_LOCK_ASSERT(sc);
1701 mii = device_get_softc(sc->bfe_miibus);
1703 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1709 if (bfe_list_rx_init(sc) == ENOBUFS) {
1710 device_printf(sc->bfe_dev,
1711 "%s: Not enough memory for list buffers\n", __func__);
1715 bfe_list_tx_init(sc);
1717 bfe_set_rx_mode(sc);
1719 /* Enable the chip and core */
1720 BFE_OR(sc, BFE_ENET_CTRL, BFE_ENET_ENABLE);
1721 /* Enable interrupts */
1722 CSR_WRITE_4(sc, BFE_IMASK, BFE_IMASK_DEF);
1724 /* Clear link state and change media. */
1725 sc->bfe_flags &= ~BFE_FLAG_LINK;
1728 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1729 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1731 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1735 * Set media options.
1738 bfe_ifmedia_upd(struct ifnet *ifp)
1740 struct bfe_softc *sc;
1741 struct mii_data *mii;
1747 mii = device_get_softc(sc->bfe_miibus);
1748 if (mii->mii_instance) {
1749 struct mii_softc *miisc;
1750 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL;
1751 miisc = LIST_NEXT(miisc, mii_list))
1752 mii_phy_reset(miisc);
1754 error = mii_mediachg(mii);
1761 * Report current media status.
1764 bfe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
1766 struct bfe_softc *sc = ifp->if_softc;
1767 struct mii_data *mii;
1770 mii = device_get_softc(sc->bfe_miibus);
1772 ifmr->ifm_active = mii->mii_media_active;
1773 ifmr->ifm_status = mii->mii_media_status;
1778 bfe_ioctl(struct ifnet *ifp, u_long command, caddr_t data)
1780 struct bfe_softc *sc = ifp->if_softc;
1781 struct ifreq *ifr = (struct ifreq *) data;
1782 struct mii_data *mii;
1788 if (ifp->if_flags & IFF_UP) {
1789 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1790 bfe_set_rx_mode(sc);
1791 else if ((sc->bfe_flags & BFE_FLAG_DETACH) == 0)
1792 bfe_init_locked(sc);
1793 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1800 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1801 bfe_set_rx_mode(sc);
1806 mii = device_get_softc(sc->bfe_miibus);
1807 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command);
1810 error = ether_ioctl(ifp, command, data);
1818 bfe_watchdog(struct bfe_softc *sc)
1822 BFE_LOCK_ASSERT(sc);
1824 if (sc->bfe_watchdog_timer == 0 || --sc->bfe_watchdog_timer)
1829 device_printf(sc->bfe_dev, "watchdog timeout -- resetting\n");
1832 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1833 bfe_init_locked(sc);
1835 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1836 bfe_start_locked(ifp);
1842 struct bfe_softc *sc = xsc;
1843 struct mii_data *mii;
1845 BFE_LOCK_ASSERT(sc);
1847 mii = device_get_softc(sc->bfe_miibus);
1849 bfe_stats_update(sc);
1851 callout_reset(&sc->bfe_stat_co, hz, bfe_tick, sc);
1855 * Stop the adapter and free any mbufs allocated to the
1859 bfe_stop(struct bfe_softc *sc)
1863 BFE_LOCK_ASSERT(sc);
1866 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1867 sc->bfe_flags &= ~BFE_FLAG_LINK;
1868 callout_stop(&sc->bfe_stat_co);
1869 sc->bfe_watchdog_timer = 0;
1872 bfe_tx_ring_free(sc);
1873 bfe_rx_ring_free(sc);
1877 sysctl_bfe_stats(SYSCTL_HANDLER_ARGS)
1879 struct bfe_softc *sc;
1880 struct bfe_hw_stats *stats;
1884 error = sysctl_handle_int(oidp, &result, 0, req);
1886 if (error != 0 || req->newptr == NULL)
1892 sc = (struct bfe_softc *)arg1;
1893 stats = &sc->bfe_stats;
1895 printf("%s statistics:\n", device_get_nameunit(sc->bfe_dev));
1896 printf("Transmit good octets : %ju\n",
1897 (uintmax_t)stats->tx_good_octets);
1898 printf("Transmit good frames : %ju\n",
1899 (uintmax_t)stats->tx_good_frames);
1900 printf("Transmit octets : %ju\n",
1901 (uintmax_t)stats->tx_octets);
1902 printf("Transmit frames : %ju\n",
1903 (uintmax_t)stats->tx_frames);
1904 printf("Transmit broadcast frames : %ju\n",
1905 (uintmax_t)stats->tx_bcast_frames);
1906 printf("Transmit multicast frames : %ju\n",
1907 (uintmax_t)stats->tx_mcast_frames);
1908 printf("Transmit frames 64 bytes : %ju\n",
1909 (uint64_t)stats->tx_pkts_64);
1910 printf("Transmit frames 65 to 127 bytes : %ju\n",
1911 (uint64_t)stats->tx_pkts_65_127);
1912 printf("Transmit frames 128 to 255 bytes : %ju\n",
1913 (uint64_t)stats->tx_pkts_128_255);
1914 printf("Transmit frames 256 to 511 bytes : %ju\n",
1915 (uint64_t)stats->tx_pkts_256_511);
1916 printf("Transmit frames 512 to 1023 bytes : %ju\n",
1917 (uint64_t)stats->tx_pkts_512_1023);
1918 printf("Transmit frames 1024 to max bytes : %ju\n",
1919 (uint64_t)stats->tx_pkts_1024_max);
1920 printf("Transmit jabber errors : %u\n", stats->tx_jabbers);
1921 printf("Transmit oversized frames : %ju\n",
1922 (uint64_t)stats->tx_oversize_frames);
1923 printf("Transmit fragmented frames : %ju\n",
1924 (uint64_t)stats->tx_frag_frames);
1925 printf("Transmit underruns : %u\n", stats->tx_colls);
1926 printf("Transmit total collisions : %u\n", stats->tx_single_colls);
1927 printf("Transmit single collisions : %u\n", stats->tx_single_colls);
1928 printf("Transmit multiple collisions : %u\n", stats->tx_multi_colls);
1929 printf("Transmit excess collisions : %u\n", stats->tx_excess_colls);
1930 printf("Transmit late collisions : %u\n", stats->tx_late_colls);
1931 printf("Transmit deferrals : %u\n", stats->tx_deferrals);
1932 printf("Transmit carrier losts : %u\n", stats->tx_carrier_losts);
1933 printf("Transmit pause frames : %u\n", stats->tx_pause_frames);
1935 printf("Receive good octets : %ju\n",
1936 (uintmax_t)stats->rx_good_octets);
1937 printf("Receive good frames : %ju\n",
1938 (uintmax_t)stats->rx_good_frames);
1939 printf("Receive octets : %ju\n",
1940 (uintmax_t)stats->rx_octets);
1941 printf("Receive frames : %ju\n",
1942 (uintmax_t)stats->rx_frames);
1943 printf("Receive broadcast frames : %ju\n",
1944 (uintmax_t)stats->rx_bcast_frames);
1945 printf("Receive multicast frames : %ju\n",
1946 (uintmax_t)stats->rx_mcast_frames);
1947 printf("Receive frames 64 bytes : %ju\n",
1948 (uint64_t)stats->rx_pkts_64);
1949 printf("Receive frames 65 to 127 bytes : %ju\n",
1950 (uint64_t)stats->rx_pkts_65_127);
1951 printf("Receive frames 128 to 255 bytes : %ju\n",
1952 (uint64_t)stats->rx_pkts_128_255);
1953 printf("Receive frames 256 to 511 bytes : %ju\n",
1954 (uint64_t)stats->rx_pkts_256_511);
1955 printf("Receive frames 512 to 1023 bytes : %ju\n",
1956 (uint64_t)stats->rx_pkts_512_1023);
1957 printf("Receive frames 1024 to max bytes : %ju\n",
1958 (uint64_t)stats->rx_pkts_1024_max);
1959 printf("Receive jabber errors : %u\n", stats->rx_jabbers);
1960 printf("Receive oversized frames : %ju\n",
1961 (uint64_t)stats->rx_oversize_frames);
1962 printf("Receive fragmented frames : %ju\n",
1963 (uint64_t)stats->rx_frag_frames);
1964 printf("Receive missed frames : %u\n", stats->rx_missed_frames);
1965 printf("Receive CRC align errors : %u\n", stats->rx_crc_align_errs);
1966 printf("Receive undersized frames : %u\n", stats->rx_runts);
1967 printf("Receive CRC errors : %u\n", stats->rx_crc_errs);
1968 printf("Receive align errors : %u\n", stats->rx_align_errs);
1969 printf("Receive symbol errors : %u\n", stats->rx_symbol_errs);
1970 printf("Receive pause frames : %u\n", stats->rx_pause_frames);
1971 printf("Receive control frames : %u\n", stats->rx_control_frames);