2 * Copyright (c) 2007 The DragonFly Project. All rights reserved.
4 * This code is derived from software contributed to The DragonFly Project
5 * by Sepherosa Ziehau <sepherosa@gmail.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in
15 * the documentation and/or other materials provided with the
17 * 3. Neither the name of The DragonFly Project nor the names of its
18 * contributors may be used to endorse or promote products derived
19 * from this software without specific, prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
22 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
23 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
24 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
25 * COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
26 * INCIDENTAL, SPECIAL, EXEMPLARY OR CONSEQUENTIAL DAMAGES (INCLUDING,
27 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
28 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
29 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT
31 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 * $DragonFly: src/sys/dev/netif/bwi/if_bwi.c,v 1.19 2008/02/15 11:15:38 sephe Exp $
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
44 #include <sys/param.h>
45 #include <sys/endian.h>
46 #include <sys/kernel.h>
48 #include <sys/malloc.h>
51 #include <sys/socket.h>
52 #include <sys/sockio.h>
53 #include <sys/sysctl.h>
54 #include <sys/systm.h>
55 #include <sys/taskqueue.h>
58 #include <net/if_dl.h>
59 #include <net/if_media.h>
60 #include <net/if_types.h>
61 #include <net/if_arp.h>
62 #include <net/ethernet.h>
63 #include <net/if_llc.h>
65 #include <net80211/ieee80211_var.h>
66 #include <net80211/ieee80211_radiotap.h>
67 #include <net80211/ieee80211_regdomain.h>
68 #include <net80211/ieee80211_phy.h>
69 #include <net80211/ieee80211_ratectl.h>
74 #include <netinet/in.h>
75 #include <netinet/if_ether.h>
78 #include <machine/bus.h>
80 #include <dev/pci/pcivar.h>
81 #include <dev/pci/pcireg.h>
83 #include <dev/bwi/bitops.h>
84 #include <dev/bwi/if_bwireg.h>
85 #include <dev/bwi/if_bwivar.h>
86 #include <dev/bwi/bwimac.h>
87 #include <dev/bwi/bwirf.h>
89 struct bwi_clock_freq {
94 struct bwi_myaddr_bssid {
95 uint8_t myaddr[IEEE80211_ADDR_LEN];
96 uint8_t bssid[IEEE80211_ADDR_LEN];
99 static struct ieee80211vap *bwi_vap_create(struct ieee80211com *,
100 const char [IFNAMSIZ], int, enum ieee80211_opmode, int,
101 const uint8_t [IEEE80211_ADDR_LEN],
102 const uint8_t [IEEE80211_ADDR_LEN]);
103 static void bwi_vap_delete(struct ieee80211vap *);
104 static void bwi_init(void *);
105 static int bwi_ioctl(struct ifnet *, u_long, caddr_t);
106 static void bwi_start(struct ifnet *);
107 static void bwi_start_locked(struct ifnet *);
108 static int bwi_raw_xmit(struct ieee80211_node *, struct mbuf *,
109 const struct ieee80211_bpf_params *);
110 static void bwi_watchdog(void *);
111 static void bwi_scan_start(struct ieee80211com *);
112 static void bwi_set_channel(struct ieee80211com *);
113 static void bwi_scan_end(struct ieee80211com *);
114 static int bwi_newstate(struct ieee80211vap *, enum ieee80211_state, int);
115 static void bwi_updateslot(struct ifnet *);
116 static int bwi_media_change(struct ifnet *);
118 static void bwi_calibrate(void *);
120 static int bwi_calc_rssi(struct bwi_softc *, const struct bwi_rxbuf_hdr *);
121 static int bwi_calc_noise(struct bwi_softc *);
122 static __inline uint8_t bwi_plcp2rate(uint32_t, enum ieee80211_phytype);
123 static void bwi_rx_radiotap(struct bwi_softc *, struct mbuf *,
124 struct bwi_rxbuf_hdr *, const void *, int, int, int);
126 static void bwi_restart(void *, int);
127 static void bwi_init_statechg(struct bwi_softc *, int);
128 static void bwi_stop(struct bwi_softc *, int);
129 static void bwi_stop_locked(struct bwi_softc *, int);
130 static int bwi_newbuf(struct bwi_softc *, int, int);
131 static int bwi_encap(struct bwi_softc *, int, struct mbuf *,
132 struct ieee80211_node *);
133 static int bwi_encap_raw(struct bwi_softc *, int, struct mbuf *,
134 struct ieee80211_node *,
135 const struct ieee80211_bpf_params *);
137 static void bwi_init_rxdesc_ring32(struct bwi_softc *, uint32_t,
138 bus_addr_t, int, int);
139 static void bwi_reset_rx_ring32(struct bwi_softc *, uint32_t);
141 static int bwi_init_tx_ring32(struct bwi_softc *, int);
142 static int bwi_init_rx_ring32(struct bwi_softc *);
143 static int bwi_init_txstats32(struct bwi_softc *);
144 static void bwi_free_tx_ring32(struct bwi_softc *, int);
145 static void bwi_free_rx_ring32(struct bwi_softc *);
146 static void bwi_free_txstats32(struct bwi_softc *);
147 static void bwi_setup_rx_desc32(struct bwi_softc *, int, bus_addr_t, int);
148 static void bwi_setup_tx_desc32(struct bwi_softc *, struct bwi_ring_data *,
149 int, bus_addr_t, int);
150 static int bwi_rxeof32(struct bwi_softc *);
151 static void bwi_start_tx32(struct bwi_softc *, uint32_t, int);
152 static void bwi_txeof_status32(struct bwi_softc *);
154 static int bwi_init_tx_ring64(struct bwi_softc *, int);
155 static int bwi_init_rx_ring64(struct bwi_softc *);
156 static int bwi_init_txstats64(struct bwi_softc *);
157 static void bwi_free_tx_ring64(struct bwi_softc *, int);
158 static void bwi_free_rx_ring64(struct bwi_softc *);
159 static void bwi_free_txstats64(struct bwi_softc *);
160 static void bwi_setup_rx_desc64(struct bwi_softc *, int, bus_addr_t, int);
161 static void bwi_setup_tx_desc64(struct bwi_softc *, struct bwi_ring_data *,
162 int, bus_addr_t, int);
163 static int bwi_rxeof64(struct bwi_softc *);
164 static void bwi_start_tx64(struct bwi_softc *, uint32_t, int);
165 static void bwi_txeof_status64(struct bwi_softc *);
167 static int bwi_rxeof(struct bwi_softc *, int);
168 static void _bwi_txeof(struct bwi_softc *, uint16_t, int, int);
169 static void bwi_txeof(struct bwi_softc *);
170 static void bwi_txeof_status(struct bwi_softc *, int);
171 static void bwi_enable_intrs(struct bwi_softc *, uint32_t);
172 static void bwi_disable_intrs(struct bwi_softc *, uint32_t);
174 static int bwi_dma_alloc(struct bwi_softc *);
175 static void bwi_dma_free(struct bwi_softc *);
176 static int bwi_dma_ring_alloc(struct bwi_softc *, bus_dma_tag_t,
177 struct bwi_ring_data *, bus_size_t,
179 static int bwi_dma_mbuf_create(struct bwi_softc *);
180 static void bwi_dma_mbuf_destroy(struct bwi_softc *, int, int);
181 static int bwi_dma_txstats_alloc(struct bwi_softc *, uint32_t, bus_size_t);
182 static void bwi_dma_txstats_free(struct bwi_softc *);
183 static void bwi_dma_ring_addr(void *, bus_dma_segment_t *, int, int);
184 static void bwi_dma_buf_addr(void *, bus_dma_segment_t *, int,
187 static void bwi_power_on(struct bwi_softc *, int);
188 static int bwi_power_off(struct bwi_softc *, int);
189 static int bwi_set_clock_mode(struct bwi_softc *, enum bwi_clock_mode);
190 static int bwi_set_clock_delay(struct bwi_softc *);
191 static void bwi_get_clock_freq(struct bwi_softc *, struct bwi_clock_freq *);
192 static int bwi_get_pwron_delay(struct bwi_softc *sc);
193 static void bwi_set_addr_filter(struct bwi_softc *, uint16_t,
195 static void bwi_set_bssid(struct bwi_softc *, const uint8_t *);
197 static void bwi_get_card_flags(struct bwi_softc *);
198 static void bwi_get_eaddr(struct bwi_softc *, uint16_t, uint8_t *);
200 static int bwi_bus_attach(struct bwi_softc *);
201 static int bwi_bbp_attach(struct bwi_softc *);
202 static int bwi_bbp_power_on(struct bwi_softc *, enum bwi_clock_mode);
203 static void bwi_bbp_power_off(struct bwi_softc *);
205 static const char *bwi_regwin_name(const struct bwi_regwin *);
206 static uint32_t bwi_regwin_disable_bits(struct bwi_softc *);
207 static void bwi_regwin_info(struct bwi_softc *, uint16_t *, uint8_t *);
208 static int bwi_regwin_select(struct bwi_softc *, int);
210 static void bwi_led_attach(struct bwi_softc *);
211 static void bwi_led_newstate(struct bwi_softc *, enum ieee80211_state);
212 static void bwi_led_event(struct bwi_softc *, int);
213 static void bwi_led_blink_start(struct bwi_softc *, int, int);
214 static void bwi_led_blink_next(void *);
215 static void bwi_led_blink_end(void *);
217 static const struct {
221 } bwi_bbpid_map[] = {
222 { 0x4301, 0x4301, 0x4301 },
223 { 0x4305, 0x4307, 0x4307 },
224 { 0x4402, 0x4403, 0x4402 },
225 { 0x4610, 0x4615, 0x4610 },
226 { 0x4710, 0x4715, 0x4710 },
227 { 0x4720, 0x4725, 0x4309 }
230 static const struct {
233 } bwi_regwin_count[] = {
246 #define CLKSRC(src) \
247 [BWI_CLKSRC_ ## src] = { \
248 .freq_min = BWI_CLKSRC_ ##src## _FMIN, \
249 .freq_max = BWI_CLKSRC_ ##src## _FMAX \
252 static const struct {
255 } bwi_clkfreq[BWI_CLKSRC_MAX] = {
263 #define VENDOR_LED_ACT(vendor) \
265 .vid = PCI_VENDOR_##vendor, \
266 .led_act = { BWI_VENDOR_LED_ACT_##vendor } \
269 static const struct {
270 #define PCI_VENDOR_COMPAQ 0x0e11
271 #define PCI_VENDOR_LINKSYS 0x1737
273 uint8_t led_act[BWI_LED_MAX];
274 } bwi_vendor_led_act[] = {
275 VENDOR_LED_ACT(COMPAQ),
276 VENDOR_LED_ACT(LINKSYS)
277 #undef PCI_VENDOR_LINKSYS
278 #undef PCI_VENDOR_COMPAQ
281 static const uint8_t bwi_default_led_act[BWI_LED_MAX] =
282 { BWI_VENDOR_LED_ACT_DEFAULT };
284 #undef VENDOR_LED_ACT
286 static const struct {
289 } bwi_led_duration[109] = {
306 #ifdef BWI_DEBUG_VERBOSE
307 static uint32_t bwi_debug = BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_TXPOWER;
309 static uint32_t bwi_debug;
311 TUNABLE_INT("hw.bwi.debug", (int *)&bwi_debug);
312 #endif /* BWI_DEBUG */
314 static const uint8_t bwi_zero_addr[IEEE80211_ADDR_LEN];
317 bwi_read_sprom(struct bwi_softc *sc, uint16_t ofs)
319 return CSR_READ_2(sc, ofs + BWI_SPROM_START);
323 bwi_setup_desc32(struct bwi_softc *sc, struct bwi_desc32 *desc_array,
324 int ndesc, int desc_idx, bus_addr_t paddr, int buf_len,
327 struct bwi_desc32 *desc = &desc_array[desc_idx];
328 uint32_t ctrl, addr, addr_hi, addr_lo;
330 addr_lo = __SHIFTOUT(paddr, BWI_DESC32_A_ADDR_MASK);
331 addr_hi = __SHIFTOUT(paddr, BWI_DESC32_A_FUNC_MASK);
333 addr = __SHIFTIN(addr_lo, BWI_DESC32_A_ADDR_MASK) |
334 __SHIFTIN(BWI_DESC32_A_FUNC_TXRX, BWI_DESC32_A_FUNC_MASK);
336 ctrl = __SHIFTIN(buf_len, BWI_DESC32_C_BUFLEN_MASK) |
337 __SHIFTIN(addr_hi, BWI_DESC32_C_ADDRHI_MASK);
338 if (desc_idx == ndesc - 1)
339 ctrl |= BWI_DESC32_C_EOR;
342 ctrl |= BWI_DESC32_C_FRAME_START |
343 BWI_DESC32_C_FRAME_END |
347 desc->addr = htole32(addr);
348 desc->ctrl = htole32(ctrl);
352 bwi_attach(struct bwi_softc *sc)
354 struct ieee80211com *ic;
355 device_t dev = sc->sc_dev;
361 uint8_t macaddr[IEEE80211_ADDR_LEN];
366 * Initialize taskq and various tasks
368 sc->sc_tq = taskqueue_create("bwi_taskq", M_NOWAIT | M_ZERO,
369 taskqueue_thread_enqueue, &sc->sc_tq);
370 taskqueue_start_threads(&sc->sc_tq, 1, PI_NET, "%s taskq",
371 device_get_nameunit(dev));
372 TASK_INIT(&sc->sc_restart_task, 0, bwi_restart, sc);
374 callout_init_mtx(&sc->sc_calib_ch, &sc->sc_mtx, 0);
377 * Initialize sysctl variables
379 sc->sc_fw_version = BWI_FW_VERSION3;
380 sc->sc_led_idle = (2350 * hz) / 1000;
381 sc->sc_led_blink = 1;
382 sc->sc_txpwr_calib = 1;
384 sc->sc_debug = bwi_debug;
388 error = bwi_bbp_attach(sc);
392 error = bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
396 if (BWI_REGWIN_EXIST(&sc->sc_com_regwin)) {
397 error = bwi_set_clock_delay(sc);
401 error = bwi_set_clock_mode(sc, BWI_CLOCK_MODE_FAST);
405 error = bwi_get_pwron_delay(sc);
410 error = bwi_bus_attach(sc);
414 bwi_get_card_flags(sc);
418 for (i = 0; i < sc->sc_nmac; ++i) {
419 struct bwi_regwin *old;
421 mac = &sc->sc_mac[i];
422 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old);
426 error = bwi_mac_lateattach(mac);
430 error = bwi_regwin_switch(sc, old, NULL);
436 * XXX First MAC is known to exist
439 mac = &sc->sc_mac[0];
442 bwi_bbp_power_off(sc);
444 error = bwi_dma_alloc(sc);
448 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
450 device_printf(dev, "can not if_alloc()\n");
456 /* set these up early for if_printf use */
457 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
460 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
461 ifp->if_init = bwi_init;
462 ifp->if_ioctl = bwi_ioctl;
463 ifp->if_start = bwi_start;
464 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
465 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
466 IFQ_SET_READY(&ifp->if_snd);
467 callout_init_mtx(&sc->sc_watchdog_timer, &sc->sc_mtx, 0);
470 * Setup ratesets, phytype, channels and get MAC address
473 if (phy->phy_mode == IEEE80211_MODE_11B ||
474 phy->phy_mode == IEEE80211_MODE_11G) {
475 setbit(&bands, IEEE80211_MODE_11B);
476 if (phy->phy_mode == IEEE80211_MODE_11B) {
477 ic->ic_phytype = IEEE80211_T_DS;
479 ic->ic_phytype = IEEE80211_T_OFDM;
480 setbit(&bands, IEEE80211_MODE_11G);
483 bwi_get_eaddr(sc, BWI_SPROM_11BG_EADDR, macaddr);
484 if (IEEE80211_IS_MULTICAST(macaddr)) {
485 bwi_get_eaddr(sc, BWI_SPROM_11A_EADDR, macaddr);
486 if (IEEE80211_IS_MULTICAST(macaddr)) {
488 "invalid MAC address: %6D\n",
492 } else if (phy->phy_mode == IEEE80211_MODE_11A) {
494 setbit(&bands, IEEE80211_MODE_11A);
498 panic("unknown phymode %d\n", phy->phy_mode);
502 sc->sc_locale = __SHIFTOUT(bwi_read_sprom(sc, BWI_SPROM_CARD_INFO),
503 BWI_SPROM_CARD_INFO_LOCALE);
504 DPRINTF(sc, BWI_DBG_ATTACH, "locale: %d\n", sc->sc_locale);
506 ieee80211_init_channels(ic, NULL, &bands);
509 ic->ic_caps = IEEE80211_C_STA |
511 IEEE80211_C_SHPREAMBLE |
515 ic->ic_opmode = IEEE80211_M_STA;
516 ieee80211_ifattach(ic, macaddr);
518 ic->ic_headroom = sizeof(struct bwi_txbuf_hdr);
520 /* override default methods */
521 ic->ic_vap_create = bwi_vap_create;
522 ic->ic_vap_delete = bwi_vap_delete;
523 ic->ic_raw_xmit = bwi_raw_xmit;
524 ic->ic_updateslot = bwi_updateslot;
525 ic->ic_scan_start = bwi_scan_start;
526 ic->ic_scan_end = bwi_scan_end;
527 ic->ic_set_channel = bwi_set_channel;
529 sc->sc_rates = ieee80211_get_ratetable(ic->ic_curchan);
531 ieee80211_radiotap_attach(ic,
532 &sc->sc_tx_th.wt_ihdr, sizeof(sc->sc_tx_th),
533 BWI_TX_RADIOTAP_PRESENT,
534 &sc->sc_rx_th.wr_ihdr, sizeof(sc->sc_rx_th),
535 BWI_RX_RADIOTAP_PRESENT);
540 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
541 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
542 "fw_version", CTLFLAG_RD, &sc->sc_fw_version, 0,
544 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
545 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
546 "led_idle", CTLFLAG_RW, &sc->sc_led_idle, 0,
547 "# ticks before LED enters idle state");
548 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
549 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
550 "led_blink", CTLFLAG_RW, &sc->sc_led_blink, 0,
551 "Allow LED to blink");
552 SYSCTL_ADD_INT(device_get_sysctl_ctx(dev),
553 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
554 "txpwr_calib", CTLFLAG_RW, &sc->sc_txpwr_calib, 0,
555 "Enable software TX power calibration");
557 SYSCTL_ADD_UINT(device_get_sysctl_ctx(dev),
558 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
559 "debug", CTLFLAG_RW, &sc->sc_debug, 0, "Debug flags");
562 ieee80211_announce(ic);
566 BWI_LOCK_DESTROY(sc);
571 bwi_detach(struct bwi_softc *sc)
573 struct ifnet *ifp = sc->sc_ifp;
574 struct ieee80211com *ic = ifp->if_l2com;
578 callout_drain(&sc->sc_led_blink_ch);
579 callout_drain(&sc->sc_calib_ch);
580 callout_drain(&sc->sc_watchdog_timer);
581 ieee80211_ifdetach(ic);
583 for (i = 0; i < sc->sc_nmac; ++i)
584 bwi_mac_detach(&sc->sc_mac[i]);
587 taskqueue_free(sc->sc_tq);
589 BWI_LOCK_DESTROY(sc);
594 static struct ieee80211vap *
595 bwi_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
596 enum ieee80211_opmode opmode, int flags,
597 const uint8_t bssid[IEEE80211_ADDR_LEN],
598 const uint8_t mac[IEEE80211_ADDR_LEN])
601 struct ieee80211vap *vap;
603 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
605 bvp = (struct bwi_vap *) malloc(sizeof(struct bwi_vap),
606 M_80211_VAP, M_WAITOK | M_ZERO);
610 /* enable s/w bmiss handling for sta mode */
611 ieee80211_vap_setup(ic, vap, name, unit, opmode,
612 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac);
614 /* override default methods */
615 bvp->bv_newstate = vap->iv_newstate;
616 vap->iv_newstate = bwi_newstate;
618 vap->iv_update_beacon = bwi_beacon_update;
620 ieee80211_ratectl_init(vap);
623 ieee80211_vap_attach(vap, bwi_media_change, ieee80211_media_status);
624 ic->ic_opmode = opmode;
629 bwi_vap_delete(struct ieee80211vap *vap)
631 struct bwi_vap *bvp = BWI_VAP(vap);
633 ieee80211_ratectl_deinit(vap);
634 ieee80211_vap_detach(vap);
635 free(bvp, M_80211_VAP);
639 bwi_suspend(struct bwi_softc *sc)
645 bwi_resume(struct bwi_softc *sc)
647 struct ifnet *ifp = sc->sc_ifp;
649 if (ifp->if_flags & IFF_UP)
654 bwi_shutdown(struct bwi_softc *sc)
661 bwi_power_on(struct bwi_softc *sc, int with_pll)
663 uint32_t gpio_in, gpio_out, gpio_en;
666 gpio_in = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4);
667 if (gpio_in & BWI_PCIM_GPIO_PWR_ON)
670 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
671 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
673 gpio_out |= BWI_PCIM_GPIO_PWR_ON;
674 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
676 /* Turn off PLL first */
677 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
678 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
681 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
682 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
687 gpio_out &= ~BWI_PCIM_GPIO_PLL_PWR_OFF;
688 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
693 /* Clear "Signaled Target Abort" */
694 status = pci_read_config(sc->sc_dev, PCIR_STATUS, 2);
695 status &= ~PCIM_STATUS_STABORT;
696 pci_write_config(sc->sc_dev, PCIR_STATUS, status, 2);
700 bwi_power_off(struct bwi_softc *sc, int with_pll)
702 uint32_t gpio_out, gpio_en;
704 pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_IN, 4); /* dummy read */
705 gpio_out = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
706 gpio_en = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, 4);
708 gpio_out &= ~BWI_PCIM_GPIO_PWR_ON;
709 gpio_en |= BWI_PCIM_GPIO_PWR_ON;
711 gpio_out |= BWI_PCIM_GPIO_PLL_PWR_OFF;
712 gpio_en |= BWI_PCIM_GPIO_PLL_PWR_OFF;
715 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, gpio_out, 4);
716 pci_write_config(sc->sc_dev, BWI_PCIR_GPIO_ENABLE, gpio_en, 4);
721 bwi_regwin_switch(struct bwi_softc *sc, struct bwi_regwin *rw,
722 struct bwi_regwin **old_rw)
729 if (!BWI_REGWIN_EXIST(rw))
732 if (sc->sc_cur_regwin != rw) {
733 error = bwi_regwin_select(sc, rw->rw_id);
735 device_printf(sc->sc_dev, "can't select regwin %d\n",
742 *old_rw = sc->sc_cur_regwin;
743 sc->sc_cur_regwin = rw;
748 bwi_regwin_select(struct bwi_softc *sc, int id)
750 uint32_t win = BWI_PCIM_REGWIN(id);
754 for (i = 0; i < RETRY_MAX; ++i) {
755 pci_write_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, win, 4);
756 if (pci_read_config(sc->sc_dev, BWI_PCIR_SEL_REGWIN, 4) == win)
766 bwi_regwin_info(struct bwi_softc *sc, uint16_t *type, uint8_t *rev)
770 val = CSR_READ_4(sc, BWI_ID_HI);
771 *type = BWI_ID_HI_REGWIN_TYPE(val);
772 *rev = BWI_ID_HI_REGWIN_REV(val);
774 DPRINTF(sc, BWI_DBG_ATTACH, "regwin: type 0x%03x, rev %d, "
775 "vendor 0x%04x\n", *type, *rev,
776 __SHIFTOUT(val, BWI_ID_HI_REGWIN_VENDOR_MASK));
780 bwi_bbp_attach(struct bwi_softc *sc)
782 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
783 uint16_t bbp_id, rw_type;
786 int error, nregwin, i;
789 * Get 0th regwin information
790 * NOTE: 0th regwin should exist
792 error = bwi_regwin_select(sc, 0);
794 device_printf(sc->sc_dev, "can't select regwin 0\n");
797 bwi_regwin_info(sc, &rw_type, &rw_rev);
804 if (rw_type == BWI_REGWIN_T_COM) {
805 info = CSR_READ_4(sc, BWI_INFO);
806 bbp_id = __SHIFTOUT(info, BWI_INFO_BBPID_MASK);
808 BWI_CREATE_REGWIN(&sc->sc_com_regwin, 0, rw_type, rw_rev);
810 sc->sc_cap = CSR_READ_4(sc, BWI_CAPABILITY);
812 for (i = 0; i < N(bwi_bbpid_map); ++i) {
813 if (sc->sc_pci_did >= bwi_bbpid_map[i].did_min &&
814 sc->sc_pci_did <= bwi_bbpid_map[i].did_max) {
815 bbp_id = bwi_bbpid_map[i].bbp_id;
820 device_printf(sc->sc_dev, "no BBP id for device id "
821 "0x%04x\n", sc->sc_pci_did);
825 info = __SHIFTIN(sc->sc_pci_revid, BWI_INFO_BBPREV_MASK) |
826 __SHIFTIN(0, BWI_INFO_BBPPKG_MASK);
830 * Find out number of regwins
833 if (rw_type == BWI_REGWIN_T_COM && rw_rev >= 4) {
834 nregwin = __SHIFTOUT(info, BWI_INFO_NREGWIN_MASK);
836 for (i = 0; i < N(bwi_regwin_count); ++i) {
837 if (bwi_regwin_count[i].bbp_id == bbp_id) {
838 nregwin = bwi_regwin_count[i].nregwin;
843 device_printf(sc->sc_dev, "no number of win for "
844 "BBP id 0x%04x\n", bbp_id);
849 /* Record BBP id/rev for later using */
850 sc->sc_bbp_id = bbp_id;
851 sc->sc_bbp_rev = __SHIFTOUT(info, BWI_INFO_BBPREV_MASK);
852 sc->sc_bbp_pkg = __SHIFTOUT(info, BWI_INFO_BBPPKG_MASK);
853 device_printf(sc->sc_dev, "BBP: id 0x%04x, rev 0x%x, pkg %d\n",
854 sc->sc_bbp_id, sc->sc_bbp_rev, sc->sc_bbp_pkg);
856 DPRINTF(sc, BWI_DBG_ATTACH, "nregwin %d, cap 0x%08x\n",
857 nregwin, sc->sc_cap);
860 * Create rest of the regwins
863 /* Don't re-create common regwin, if it is already created */
864 i = BWI_REGWIN_EXIST(&sc->sc_com_regwin) ? 1 : 0;
866 for (; i < nregwin; ++i) {
868 * Get regwin information
870 error = bwi_regwin_select(sc, i);
872 device_printf(sc->sc_dev,
873 "can't select regwin %d\n", i);
876 bwi_regwin_info(sc, &rw_type, &rw_rev);
880 * 1) Bus (PCI/PCIE) regwin
882 * Ignore rest types of regwin
884 if (rw_type == BWI_REGWIN_T_BUSPCI ||
885 rw_type == BWI_REGWIN_T_BUSPCIE) {
886 if (BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
887 device_printf(sc->sc_dev,
888 "bus regwin already exists\n");
890 BWI_CREATE_REGWIN(&sc->sc_bus_regwin, i,
893 } else if (rw_type == BWI_REGWIN_T_MAC) {
894 /* XXX ignore return value */
895 bwi_mac_attach(sc, i, rw_rev);
899 /* At least one MAC shold exist */
900 if (!BWI_REGWIN_EXIST(&sc->sc_mac[0].mac_regwin)) {
901 device_printf(sc->sc_dev, "no MAC was found\n");
904 KASSERT(sc->sc_nmac > 0, ("no mac's"));
906 /* Bus regwin must exist */
907 if (!BWI_REGWIN_EXIST(&sc->sc_bus_regwin)) {
908 device_printf(sc->sc_dev, "no bus regwin was found\n");
912 /* Start with first MAC */
913 error = bwi_regwin_switch(sc, &sc->sc_mac[0].mac_regwin, NULL);
922 bwi_bus_init(struct bwi_softc *sc, struct bwi_mac *mac)
924 struct bwi_regwin *old, *bus;
928 bus = &sc->sc_bus_regwin;
929 KASSERT(sc->sc_cur_regwin == &mac->mac_regwin, ("not cur regwin"));
932 * Tell bus to generate requested interrupts
934 if (bus->rw_rev < 6 && bus->rw_type == BWI_REGWIN_T_BUSPCI) {
936 * NOTE: Read BWI_FLAGS from MAC regwin
938 val = CSR_READ_4(sc, BWI_FLAGS);
940 error = bwi_regwin_switch(sc, bus, &old);
944 CSR_SETBITS_4(sc, BWI_INTRVEC, (val & BWI_FLAGS_INTR_MASK));
948 mac_mask = 1 << mac->mac_id;
950 error = bwi_regwin_switch(sc, bus, &old);
954 val = pci_read_config(sc->sc_dev, BWI_PCIR_INTCTL, 4);
955 val |= mac_mask << 8;
956 pci_write_config(sc->sc_dev, BWI_PCIR_INTCTL, val, 4);
959 if (sc->sc_flags & BWI_F_BUS_INITED)
962 if (bus->rw_type == BWI_REGWIN_T_BUSPCI) {
964 * Enable prefetch and burst
966 CSR_SETBITS_4(sc, BWI_BUS_CONFIG,
967 BWI_BUS_CONFIG_PREFETCH | BWI_BUS_CONFIG_BURST);
969 if (bus->rw_rev < 5) {
970 struct bwi_regwin *com = &sc->sc_com_regwin;
973 * Configure timeouts for bus operation
977 * Set service timeout and request timeout
979 CSR_SETBITS_4(sc, BWI_CONF_LO,
980 __SHIFTIN(BWI_CONF_LO_SERVTO, BWI_CONF_LO_SERVTO_MASK) |
981 __SHIFTIN(BWI_CONF_LO_REQTO, BWI_CONF_LO_REQTO_MASK));
984 * If there is common regwin, we switch to that regwin
985 * and switch back to bus regwin once we have done.
987 if (BWI_REGWIN_EXIST(com)) {
988 error = bwi_regwin_switch(sc, com, NULL);
993 /* Let bus know what we have changed */
994 CSR_WRITE_4(sc, BWI_BUS_ADDR, BWI_BUS_ADDR_MAGIC);
995 CSR_READ_4(sc, BWI_BUS_ADDR); /* Flush */
996 CSR_WRITE_4(sc, BWI_BUS_DATA, 0);
997 CSR_READ_4(sc, BWI_BUS_DATA); /* Flush */
999 if (BWI_REGWIN_EXIST(com)) {
1000 error = bwi_regwin_switch(sc, bus, NULL);
1004 } else if (bus->rw_rev >= 11) {
1006 * Enable memory read multiple
1008 CSR_SETBITS_4(sc, BWI_BUS_CONFIG, BWI_BUS_CONFIG_MRM);
1014 sc->sc_flags |= BWI_F_BUS_INITED;
1016 return bwi_regwin_switch(sc, old, NULL);
1020 bwi_get_card_flags(struct bwi_softc *sc)
1022 #define PCI_VENDOR_APPLE 0x106b
1023 #define PCI_VENDOR_DELL 0x1028
1024 sc->sc_card_flags = bwi_read_sprom(sc, BWI_SPROM_CARD_FLAGS);
1025 if (sc->sc_card_flags == 0xffff)
1026 sc->sc_card_flags = 0;
1028 if (sc->sc_pci_subvid == PCI_VENDOR_DELL &&
1029 sc->sc_bbp_id == BWI_BBPID_BCM4301 &&
1030 sc->sc_pci_revid == 0x74)
1031 sc->sc_card_flags |= BWI_CARD_F_BT_COEXIST;
1033 if (sc->sc_pci_subvid == PCI_VENDOR_APPLE &&
1034 sc->sc_pci_subdid == 0x4e && /* XXX */
1035 sc->sc_pci_revid > 0x40)
1036 sc->sc_card_flags |= BWI_CARD_F_PA_GPIO9;
1038 DPRINTF(sc, BWI_DBG_ATTACH, "card flags 0x%04x\n", sc->sc_card_flags);
1039 #undef PCI_VENDOR_DELL
1040 #undef PCI_VENDOR_APPLE
1044 bwi_get_eaddr(struct bwi_softc *sc, uint16_t eaddr_ofs, uint8_t *eaddr)
1048 for (i = 0; i < 3; ++i) {
1049 *((uint16_t *)eaddr + i) =
1050 htobe16(bwi_read_sprom(sc, eaddr_ofs + 2 * i));
1055 bwi_get_clock_freq(struct bwi_softc *sc, struct bwi_clock_freq *freq)
1057 struct bwi_regwin *com;
1062 bzero(freq, sizeof(*freq));
1063 com = &sc->sc_com_regwin;
1065 KASSERT(BWI_REGWIN_EXIST(com), ("regwin does not exist"));
1066 KASSERT(sc->sc_cur_regwin == com, ("wrong regwin"));
1067 KASSERT(sc->sc_cap & BWI_CAP_CLKMODE, ("wrong clock mode"));
1070 * Calculate clock frequency
1074 if (com->rw_rev < 6) {
1075 val = pci_read_config(sc->sc_dev, BWI_PCIR_GPIO_OUT, 4);
1076 if (val & BWI_PCIM_GPIO_OUT_CLKSRC) {
1077 src = BWI_CLKSRC_PCI;
1080 src = BWI_CLKSRC_CS_OSC;
1083 } else if (com->rw_rev < 10) {
1084 val = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1086 src = __SHIFTOUT(val, BWI_CLOCK_CTRL_CLKSRC);
1087 if (src == BWI_CLKSRC_LP_OSC) {
1090 div = (__SHIFTOUT(val, BWI_CLOCK_CTRL_FDIV) + 1) << 2;
1092 /* Unknown source */
1093 if (src >= BWI_CLKSRC_MAX)
1094 src = BWI_CLKSRC_CS_OSC;
1097 val = CSR_READ_4(sc, BWI_CLOCK_INFO);
1099 src = BWI_CLKSRC_CS_OSC;
1100 div = (__SHIFTOUT(val, BWI_CLOCK_INFO_FDIV) + 1) << 2;
1103 KASSERT(src >= 0 && src < BWI_CLKSRC_MAX, ("bad src %d", src));
1104 KASSERT(div != 0, ("div zero"));
1106 DPRINTF(sc, BWI_DBG_ATTACH, "clksrc %s\n",
1107 src == BWI_CLKSRC_PCI ? "PCI" :
1108 (src == BWI_CLKSRC_LP_OSC ? "LP_OSC" : "CS_OSC"));
1110 freq->clkfreq_min = bwi_clkfreq[src].freq_min / div;
1111 freq->clkfreq_max = bwi_clkfreq[src].freq_max / div;
1113 DPRINTF(sc, BWI_DBG_ATTACH, "clkfreq min %u, max %u\n",
1114 freq->clkfreq_min, freq->clkfreq_max);
1118 bwi_set_clock_mode(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
1120 struct bwi_regwin *old, *com;
1121 uint32_t clk_ctrl, clk_src;
1122 int error, pwr_off = 0;
1124 com = &sc->sc_com_regwin;
1125 if (!BWI_REGWIN_EXIST(com))
1128 if (com->rw_rev >= 10 || com->rw_rev < 6)
1132 * For common regwin whose rev is [6, 10), the chip
1133 * must be capable to change clock mode.
1135 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
1138 error = bwi_regwin_switch(sc, com, &old);
1142 if (clk_mode == BWI_CLOCK_MODE_FAST)
1143 bwi_power_on(sc, 0); /* Don't turn on PLL */
1145 clk_ctrl = CSR_READ_4(sc, BWI_CLOCK_CTRL);
1146 clk_src = __SHIFTOUT(clk_ctrl, BWI_CLOCK_CTRL_CLKSRC);
1149 case BWI_CLOCK_MODE_FAST:
1150 clk_ctrl &= ~BWI_CLOCK_CTRL_SLOW;
1151 clk_ctrl |= BWI_CLOCK_CTRL_IGNPLL;
1153 case BWI_CLOCK_MODE_SLOW:
1154 clk_ctrl |= BWI_CLOCK_CTRL_SLOW;
1156 case BWI_CLOCK_MODE_DYN:
1157 clk_ctrl &= ~(BWI_CLOCK_CTRL_SLOW |
1158 BWI_CLOCK_CTRL_IGNPLL |
1159 BWI_CLOCK_CTRL_NODYN);
1160 if (clk_src != BWI_CLKSRC_CS_OSC) {
1161 clk_ctrl |= BWI_CLOCK_CTRL_NODYN;
1166 CSR_WRITE_4(sc, BWI_CLOCK_CTRL, clk_ctrl);
1169 bwi_power_off(sc, 0); /* Leave PLL as it is */
1171 return bwi_regwin_switch(sc, old, NULL);
1175 bwi_set_clock_delay(struct bwi_softc *sc)
1177 struct bwi_regwin *old, *com;
1180 com = &sc->sc_com_regwin;
1181 if (!BWI_REGWIN_EXIST(com))
1184 error = bwi_regwin_switch(sc, com, &old);
1188 if (sc->sc_bbp_id == BWI_BBPID_BCM4321) {
1189 if (sc->sc_bbp_rev == 0)
1190 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC0);
1191 else if (sc->sc_bbp_rev == 1)
1192 CSR_WRITE_4(sc, BWI_CONTROL, BWI_CONTROL_MAGIC1);
1195 if (sc->sc_cap & BWI_CAP_CLKMODE) {
1196 if (com->rw_rev >= 10) {
1197 CSR_FILT_SETBITS_4(sc, BWI_CLOCK_INFO, 0xffff, 0x40000);
1199 struct bwi_clock_freq freq;
1201 bwi_get_clock_freq(sc, &freq);
1202 CSR_WRITE_4(sc, BWI_PLL_ON_DELAY,
1203 howmany(freq.clkfreq_max * 150, 1000000));
1204 CSR_WRITE_4(sc, BWI_FREQ_SEL_DELAY,
1205 howmany(freq.clkfreq_max * 15, 1000000));
1209 return bwi_regwin_switch(sc, old, NULL);
1215 struct bwi_softc *sc = xsc;
1216 struct ifnet *ifp = sc->sc_ifp;
1217 struct ieee80211com *ic = ifp->if_l2com;
1220 bwi_init_statechg(sc, 1);
1223 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1224 ieee80211_start_all(ic); /* start all vap's */
1228 bwi_init_statechg(struct bwi_softc *sc, int statechg)
1230 struct ifnet *ifp = sc->sc_ifp;
1231 struct bwi_mac *mac;
1234 bwi_stop_locked(sc, statechg);
1236 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_FAST);
1240 mac = &sc->sc_mac[0];
1241 error = bwi_regwin_switch(sc, &mac->mac_regwin, NULL);
1243 if_printf(ifp, "%s: error %d on regwin switch\n",
1247 error = bwi_mac_init(mac);
1249 if_printf(ifp, "%s: error %d on MAC init\n", __func__, error);
1253 bwi_bbp_power_on(sc, BWI_CLOCK_MODE_DYN);
1255 bwi_set_bssid(sc, bwi_zero_addr); /* Clear BSSID */
1256 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_MYADDR, IF_LLADDR(ifp));
1258 bwi_mac_reset_hwkeys(mac);
1260 if ((mac->mac_flags & BWI_MAC_F_HAS_TXSTATS) == 0) {
1265 * Drain any possible pending TX status
1267 for (i = 0; i < NRETRY; ++i) {
1268 if ((CSR_READ_4(sc, BWI_TXSTATUS0) &
1269 BWI_TXSTATUS0_VALID) == 0)
1271 CSR_READ_4(sc, BWI_TXSTATUS1);
1274 if_printf(ifp, "%s: can't drain TX status\n", __func__);
1278 if (mac->mac_phy.phy_mode == IEEE80211_MODE_11G)
1279 bwi_mac_updateslot(mac, 1);
1282 error = bwi_mac_start(mac);
1284 if_printf(ifp, "%s: error %d starting MAC\n", __func__, error);
1288 /* Clear stop flag before enabling interrupt */
1289 sc->sc_flags &= ~BWI_F_STOP;
1291 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1292 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc);
1295 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1298 bwi_stop_locked(sc, 1);
1302 bwi_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1304 #define IS_RUNNING(ifp) \
1305 ((ifp->if_flags & IFF_UP) && (ifp->if_drv_flags & IFF_DRV_RUNNING))
1306 struct bwi_softc *sc = ifp->if_softc;
1307 struct ieee80211com *ic = ifp->if_l2com;
1308 struct ifreq *ifr = (struct ifreq *) data;
1309 int error = 0, startall = 0;
1314 if (IS_RUNNING(ifp)) {
1315 struct bwi_mac *mac;
1318 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1319 ("current regwin type %d",
1320 sc->sc_cur_regwin->rw_type));
1321 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1323 if ((ifp->if_flags & IFF_PROMISC) &&
1324 (sc->sc_flags & BWI_F_PROMISC) == 0) {
1326 sc->sc_flags |= BWI_F_PROMISC;
1327 } else if ((ifp->if_flags & IFF_PROMISC) == 0 &&
1328 (sc->sc_flags & BWI_F_PROMISC)) {
1330 sc->sc_flags &= ~BWI_F_PROMISC;
1334 bwi_mac_set_promisc(mac, promisc);
1337 if (ifp->if_flags & IFF_UP) {
1338 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1339 bwi_init_statechg(sc, 1);
1343 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1344 bwi_stop_locked(sc, 1);
1348 ieee80211_start_all(ic);
1351 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1354 error = ether_ioctl(ifp, cmd, data);
1365 bwi_start(struct ifnet *ifp)
1367 struct bwi_softc *sc = ifp->if_softc;
1370 bwi_start_locked(ifp);
1375 bwi_start_locked(struct ifnet *ifp)
1377 struct bwi_softc *sc = ifp->if_softc;
1378 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1379 struct ieee80211_frame *wh;
1380 struct ieee80211_node *ni;
1381 struct ieee80211_key *k;
1385 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1391 while (tbd->tbd_buf[idx].tb_mbuf == NULL) {
1392 IFQ_DRV_DEQUEUE(&ifp->if_snd, m); /* XXX: LOCK */
1396 ni = (struct ieee80211_node *) m->m_pkthdr.rcvif;
1397 wh = mtod(m, struct ieee80211_frame *);
1398 if (wh->i_fc[1] & IEEE80211_FC1_WEP) {
1399 k = ieee80211_crypto_encap(ni, m);
1401 ieee80211_free_node(ni);
1407 wh = NULL; /* Catch any invalid use */
1409 if (bwi_encap(sc, idx, m, ni) != 0) {
1410 /* 'm' is freed in bwi_encap() if we reach here */
1412 ieee80211_free_node(ni);
1419 idx = (idx + 1) % BWI_TX_NDESC;
1423 if (tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC) {
1424 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1431 sc->sc_tx_timer = 5;
1435 bwi_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1436 const struct ieee80211_bpf_params *params)
1438 struct ieee80211com *ic = ni->ni_ic;
1439 struct ifnet *ifp = ic->ic_ifp;
1440 struct bwi_softc *sc = ifp->if_softc;
1442 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
1445 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) {
1446 ieee80211_free_node(ni);
1453 KASSERT(tbd->tbd_buf[idx].tb_mbuf == NULL, ("slot %d not empty", idx));
1454 if (params == NULL) {
1456 * Legacy path; interpret frame contents to decide
1457 * precisely how to send the frame.
1459 error = bwi_encap(sc, idx, m, ni);
1462 * Caller supplied explicit parameters to use in
1463 * sending the frame.
1465 error = bwi_encap_raw(sc, idx, m, ni, params);
1469 if (++tbd->tbd_used + BWI_TX_NSPRDESC >= BWI_TX_NDESC)
1470 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1471 tbd->tbd_idx = (idx + 1) % BWI_TX_NDESC;
1472 sc->sc_tx_timer = 5;
1474 /* NB: m is reclaimed on encap failure */
1475 ieee80211_free_node(ni);
1483 bwi_watchdog(void *arg)
1485 struct bwi_softc *sc;
1490 BWI_ASSERT_LOCKED(sc);
1491 if (sc->sc_tx_timer != 0 && --sc->sc_tx_timer == 0) {
1492 if_printf(ifp, "watchdog timeout\n");
1494 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1496 callout_reset(&sc->sc_watchdog_timer, hz, bwi_watchdog, sc);
1500 bwi_stop(struct bwi_softc *sc, int statechg)
1503 bwi_stop_locked(sc, statechg);
1508 bwi_stop_locked(struct bwi_softc *sc, int statechg)
1510 struct ifnet *ifp = sc->sc_ifp;
1511 struct bwi_mac *mac;
1512 int i, error, pwr_off = 0;
1514 BWI_ASSERT_LOCKED(sc);
1516 callout_stop(&sc->sc_calib_ch);
1517 callout_stop(&sc->sc_led_blink_ch);
1518 sc->sc_led_blinking = 0;
1519 sc->sc_flags |= BWI_F_STOP;
1521 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1522 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1523 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1524 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1526 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1527 CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1531 for (i = 0; i < sc->sc_nmac; ++i) {
1532 struct bwi_regwin *old_rw;
1534 mac = &sc->sc_mac[i];
1535 if ((mac->mac_flags & BWI_MAC_F_INITED) == 0)
1538 error = bwi_regwin_switch(sc, &mac->mac_regwin, &old_rw);
1542 bwi_mac_shutdown(mac);
1545 bwi_regwin_switch(sc, old_rw, NULL);
1549 bwi_bbp_power_off(sc);
1551 sc->sc_tx_timer = 0;
1552 callout_stop(&sc->sc_watchdog_timer);
1553 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1559 struct bwi_softc *sc = xsc;
1560 struct ifnet *ifp = sc->sc_ifp;
1561 struct bwi_mac *mac;
1562 uint32_t intr_status;
1563 uint32_t txrx_intr_status[BWI_TXRX_NRING];
1564 int i, txrx_error, tx = 0, rx_data = -1;
1568 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0 ||
1569 (sc->sc_flags & BWI_F_STOP)) {
1574 * Get interrupt status
1576 intr_status = CSR_READ_4(sc, BWI_MAC_INTR_STATUS);
1577 if (intr_status == 0xffffffff) { /* Not for us */
1582 DPRINTF(sc, BWI_DBG_INTR, "intr status 0x%08x\n", intr_status);
1584 intr_status &= CSR_READ_4(sc, BWI_MAC_INTR_MASK);
1585 if (intr_status == 0) { /* Nothing is interesting */
1590 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1591 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1592 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1595 DPRINTF(sc, BWI_DBG_INTR, "%s\n", "TX/RX intr");
1596 for (i = 0; i < BWI_TXRX_NRING; ++i) {
1599 if (BWI_TXRX_IS_RX(i))
1600 mask = BWI_TXRX_RX_INTRS;
1602 mask = BWI_TXRX_TX_INTRS;
1604 txrx_intr_status[i] =
1605 CSR_READ_4(sc, BWI_TXRX_INTR_STATUS(i)) & mask;
1607 _DPRINTF(sc, BWI_DBG_INTR, ", %d 0x%08x",
1608 i, txrx_intr_status[i]);
1610 if (txrx_intr_status[i] & BWI_TXRX_INTR_ERROR) {
1612 "%s: intr fatal TX/RX (%d) error 0x%08x\n",
1613 __func__, i, txrx_intr_status[i]);
1617 _DPRINTF(sc, BWI_DBG_INTR, "%s\n", "");
1620 * Acknowledge interrupt
1622 CSR_WRITE_4(sc, BWI_MAC_INTR_STATUS, intr_status);
1624 for (i = 0; i < BWI_TXRX_NRING; ++i)
1625 CSR_WRITE_4(sc, BWI_TXRX_INTR_STATUS(i), txrx_intr_status[i]);
1627 /* Disable all interrupts */
1628 bwi_disable_intrs(sc, BWI_ALL_INTRS);
1631 * http://bcm-specs.sipsolutions.net/Interrupts
1632 * Says for this bit (0x800):
1635 * We got this one while testing things when by accident the
1636 * template ram wasn't set to big endian when it should have
1637 * been after writing the initial values. It keeps on being
1638 * triggered, the only way to stop it seems to shut down the
1641 * Suggesting that we should never get it and if we do we're not
1642 * feeding TX packets into the MAC correctly if we do... Apparently,
1643 * it is valid only on mac version 5 and higher, but I couldn't
1644 * find a reference for that... Since I see them from time to time
1645 * on my card, this suggests an error in the tx path still...
1647 if (intr_status & BWI_INTR_PHY_TXERR) {
1648 if (mac->mac_flags & BWI_MAC_F_PHYE_RESET) {
1649 if_printf(ifp, "%s: intr PHY TX error\n", __func__);
1650 taskqueue_enqueue(sc->sc_tq, &sc->sc_restart_task);
1657 /* TODO: reset device */
1660 if (intr_status & BWI_INTR_TBTT)
1661 bwi_mac_config_ps(mac);
1663 if (intr_status & BWI_INTR_EO_ATIM)
1664 if_printf(ifp, "EO_ATIM\n");
1666 if (intr_status & BWI_INTR_PMQ) {
1668 if ((CSR_READ_4(sc, BWI_MAC_PS_STATUS) & 0x8) == 0)
1671 CSR_WRITE_2(sc, BWI_MAC_PS_STATUS, 0x2);
1674 if (intr_status & BWI_INTR_NOISE)
1675 if_printf(ifp, "intr noise\n");
1677 if (txrx_intr_status[0] & BWI_TXRX_INTR_RX) {
1678 rx_data = sc->sc_rxeof(sc);
1679 if (sc->sc_flags & BWI_F_STOP) {
1685 if (txrx_intr_status[3] & BWI_TXRX_INTR_RX) {
1686 sc->sc_txeof_status(sc);
1690 if (intr_status & BWI_INTR_TX_DONE) {
1695 /* Re-enable interrupts */
1696 bwi_enable_intrs(sc, BWI_INIT_INTRS);
1698 if (sc->sc_blink_led != NULL && sc->sc_led_blink) {
1699 int evt = BWI_LED_EVENT_NONE;
1701 if (tx && rx_data > 0) {
1702 if (sc->sc_rx_rate > sc->sc_tx_rate)
1703 evt = BWI_LED_EVENT_RX;
1705 evt = BWI_LED_EVENT_TX;
1707 evt = BWI_LED_EVENT_TX;
1708 } else if (rx_data > 0) {
1709 evt = BWI_LED_EVENT_RX;
1710 } else if (rx_data == 0) {
1711 evt = BWI_LED_EVENT_POLL;
1714 if (evt != BWI_LED_EVENT_NONE)
1715 bwi_led_event(sc, evt);
1722 bwi_scan_start(struct ieee80211com *ic)
1724 struct bwi_softc *sc = ic->ic_ifp->if_softc;
1727 /* Enable MAC beacon promiscuity */
1728 CSR_SETBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1733 bwi_set_channel(struct ieee80211com *ic)
1735 struct bwi_softc *sc = ic->ic_ifp->if_softc;
1736 struct ieee80211_channel *c = ic->ic_curchan;
1737 struct bwi_mac *mac;
1740 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1741 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1742 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1743 bwi_rf_set_chan(mac, ieee80211_chan2ieee(ic, c), 0);
1745 sc->sc_rates = ieee80211_get_ratetable(c);
1748 * Setup radio tap channel freq and flags
1750 sc->sc_tx_th.wt_chan_freq = sc->sc_rx_th.wr_chan_freq =
1751 htole16(c->ic_freq);
1752 sc->sc_tx_th.wt_chan_flags = sc->sc_rx_th.wr_chan_flags =
1753 htole16(c->ic_flags & 0xffff);
1759 bwi_scan_end(struct ieee80211com *ic)
1761 struct bwi_softc *sc = ic->ic_ifp->if_softc;
1764 CSR_CLRBITS_4(sc, BWI_MAC_STATUS, BWI_MAC_STATUS_PASS_BCN);
1769 bwi_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1771 struct bwi_vap *bvp = BWI_VAP(vap);
1772 struct ieee80211com *ic= vap->iv_ic;
1773 struct ifnet *ifp = ic->ic_ifp;
1774 enum ieee80211_state ostate = vap->iv_state;
1775 struct bwi_softc *sc = ifp->if_softc;
1776 struct bwi_mac *mac;
1781 callout_stop(&sc->sc_calib_ch);
1783 if (nstate == IEEE80211_S_INIT)
1784 sc->sc_txpwrcb_type = BWI_TXPWR_INIT;
1786 bwi_led_newstate(sc, nstate);
1788 error = bvp->bv_newstate(vap, nstate, arg);
1793 * Clear the BSSID when we stop a STA
1795 if (vap->iv_opmode == IEEE80211_M_STA) {
1796 if (ostate == IEEE80211_S_RUN && nstate != IEEE80211_S_RUN) {
1798 * Clear out the BSSID. If we reassociate to
1799 * the same AP, this will reinialize things
1802 if (ic->ic_opmode == IEEE80211_M_STA &&
1803 !(sc->sc_flags & BWI_F_STOP))
1804 bwi_set_bssid(sc, bwi_zero_addr);
1808 if (vap->iv_opmode == IEEE80211_M_MONITOR) {
1810 } else if (nstate == IEEE80211_S_RUN) {
1811 bwi_set_bssid(sc, vap->iv_bss->ni_bssid);
1813 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
1814 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
1815 mac = (struct bwi_mac *)sc->sc_cur_regwin;
1817 /* Initial TX power calibration */
1818 bwi_mac_calibrate_txpower(mac, BWI_TXPWR_INIT);
1820 sc->sc_txpwrcb_type = BWI_TXPWR_FORCE;
1822 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
1825 callout_reset(&sc->sc_calib_ch, hz, bwi_calibrate, sc);
1834 bwi_media_change(struct ifnet *ifp)
1836 int error = ieee80211_media_change(ifp);
1837 /* NB: only the fixed rate can change and that doesn't need a reset */
1838 return (error == ENETRESET ? 0 : error);
1842 bwi_dma_alloc(struct bwi_softc *sc)
1844 int error, i, has_txstats;
1845 bus_addr_t lowaddr = 0;
1846 bus_size_t tx_ring_sz, rx_ring_sz, desc_sz = 0;
1847 uint32_t txrx_ctrl_step = 0;
1850 for (i = 0; i < sc->sc_nmac; ++i) {
1851 if (sc->sc_mac[i].mac_flags & BWI_MAC_F_HAS_TXSTATS) {
1857 switch (sc->sc_bus_space) {
1858 case BWI_BUS_SPACE_30BIT:
1859 case BWI_BUS_SPACE_32BIT:
1860 if (sc->sc_bus_space == BWI_BUS_SPACE_30BIT)
1861 lowaddr = BWI_BUS_SPACE_MAXADDR;
1863 lowaddr = BUS_SPACE_MAXADDR_32BIT;
1864 desc_sz = sizeof(struct bwi_desc32);
1865 txrx_ctrl_step = 0x20;
1867 sc->sc_init_tx_ring = bwi_init_tx_ring32;
1868 sc->sc_free_tx_ring = bwi_free_tx_ring32;
1869 sc->sc_init_rx_ring = bwi_init_rx_ring32;
1870 sc->sc_free_rx_ring = bwi_free_rx_ring32;
1871 sc->sc_setup_rxdesc = bwi_setup_rx_desc32;
1872 sc->sc_setup_txdesc = bwi_setup_tx_desc32;
1873 sc->sc_rxeof = bwi_rxeof32;
1874 sc->sc_start_tx = bwi_start_tx32;
1876 sc->sc_init_txstats = bwi_init_txstats32;
1877 sc->sc_free_txstats = bwi_free_txstats32;
1878 sc->sc_txeof_status = bwi_txeof_status32;
1882 case BWI_BUS_SPACE_64BIT:
1883 lowaddr = BUS_SPACE_MAXADDR; /* XXX */
1884 desc_sz = sizeof(struct bwi_desc64);
1885 txrx_ctrl_step = 0x40;
1887 sc->sc_init_tx_ring = bwi_init_tx_ring64;
1888 sc->sc_free_tx_ring = bwi_free_tx_ring64;
1889 sc->sc_init_rx_ring = bwi_init_rx_ring64;
1890 sc->sc_free_rx_ring = bwi_free_rx_ring64;
1891 sc->sc_setup_rxdesc = bwi_setup_rx_desc64;
1892 sc->sc_setup_txdesc = bwi_setup_tx_desc64;
1893 sc->sc_rxeof = bwi_rxeof64;
1894 sc->sc_start_tx = bwi_start_tx64;
1896 sc->sc_init_txstats = bwi_init_txstats64;
1897 sc->sc_free_txstats = bwi_free_txstats64;
1898 sc->sc_txeof_status = bwi_txeof_status64;
1903 KASSERT(lowaddr != 0, ("lowaddr zero"));
1904 KASSERT(desc_sz != 0, ("desc_sz zero"));
1905 KASSERT(txrx_ctrl_step != 0, ("txrx_ctrl_step zero"));
1907 tx_ring_sz = roundup(desc_sz * BWI_TX_NDESC, BWI_RING_ALIGN);
1908 rx_ring_sz = roundup(desc_sz * BWI_RX_NDESC, BWI_RING_ALIGN);
1911 * Create top level DMA tag
1913 error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), /* parent */
1914 BWI_ALIGN, 0, /* alignment, bounds */
1915 lowaddr, /* lowaddr */
1916 BUS_SPACE_MAXADDR, /* highaddr */
1917 NULL, NULL, /* filter, filterarg */
1918 MAXBSIZE, /* maxsize */
1919 BUS_SPACE_UNRESTRICTED, /* nsegments */
1920 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */
1921 BUS_DMA_ALLOCNOW, /* flags */
1922 NULL, NULL, /* lockfunc, lockarg */
1923 &sc->sc_parent_dtag);
1925 device_printf(sc->sc_dev, "can't create parent DMA tag\n");
1929 #define TXRX_CTRL(idx) (BWI_TXRX_CTRL_BASE + (idx) * txrx_ctrl_step)
1932 * Create TX ring DMA stuffs
1934 error = bus_dma_tag_create(sc->sc_parent_dtag,
1941 BUS_SPACE_MAXSIZE_32BIT,
1944 &sc->sc_txring_dtag);
1946 device_printf(sc->sc_dev, "can't create TX ring DMA tag\n");
1950 for (i = 0; i < BWI_TX_NRING; ++i) {
1951 error = bwi_dma_ring_alloc(sc, sc->sc_txring_dtag,
1952 &sc->sc_tx_rdata[i], tx_ring_sz,
1955 device_printf(sc->sc_dev, "%dth TX ring "
1956 "DMA alloc failed\n", i);
1962 * Create RX ring DMA stuffs
1964 error = bus_dma_tag_create(sc->sc_parent_dtag,
1971 BUS_SPACE_MAXSIZE_32BIT,
1974 &sc->sc_rxring_dtag);
1976 device_printf(sc->sc_dev, "can't create RX ring DMA tag\n");
1980 error = bwi_dma_ring_alloc(sc, sc->sc_rxring_dtag, &sc->sc_rx_rdata,
1981 rx_ring_sz, TXRX_CTRL(0));
1983 device_printf(sc->sc_dev, "RX ring DMA alloc failed\n");
1988 error = bwi_dma_txstats_alloc(sc, TXRX_CTRL(3), desc_sz);
1990 device_printf(sc->sc_dev,
1991 "TX stats DMA alloc failed\n");
1998 return bwi_dma_mbuf_create(sc);
2002 bwi_dma_free(struct bwi_softc *sc)
2004 if (sc->sc_txring_dtag != NULL) {
2007 for (i = 0; i < BWI_TX_NRING; ++i) {
2008 struct bwi_ring_data *rd = &sc->sc_tx_rdata[i];
2010 if (rd->rdata_desc != NULL) {
2011 bus_dmamap_unload(sc->sc_txring_dtag,
2013 bus_dmamem_free(sc->sc_txring_dtag,
2018 bus_dma_tag_destroy(sc->sc_txring_dtag);
2021 if (sc->sc_rxring_dtag != NULL) {
2022 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2024 if (rd->rdata_desc != NULL) {
2025 bus_dmamap_unload(sc->sc_rxring_dtag, rd->rdata_dmap);
2026 bus_dmamem_free(sc->sc_rxring_dtag, rd->rdata_desc,
2029 bus_dma_tag_destroy(sc->sc_rxring_dtag);
2032 bwi_dma_txstats_free(sc);
2033 bwi_dma_mbuf_destroy(sc, BWI_TX_NRING, 1);
2035 if (sc->sc_parent_dtag != NULL)
2036 bus_dma_tag_destroy(sc->sc_parent_dtag);
2040 bwi_dma_ring_alloc(struct bwi_softc *sc, bus_dma_tag_t dtag,
2041 struct bwi_ring_data *rd, bus_size_t size,
2046 error = bus_dmamem_alloc(dtag, &rd->rdata_desc,
2047 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2050 device_printf(sc->sc_dev, "can't allocate DMA mem\n");
2054 error = bus_dmamap_load(dtag, rd->rdata_dmap, rd->rdata_desc, size,
2055 bwi_dma_ring_addr, &rd->rdata_paddr,
2058 device_printf(sc->sc_dev, "can't load DMA mem\n");
2059 bus_dmamem_free(dtag, rd->rdata_desc, rd->rdata_dmap);
2060 rd->rdata_desc = NULL;
2064 rd->rdata_txrx_ctrl = txrx_ctrl;
2069 bwi_dma_txstats_alloc(struct bwi_softc *sc, uint32_t ctrl_base,
2072 struct bwi_txstats_data *st;
2073 bus_size_t dma_size;
2076 st = malloc(sizeof(*st), M_DEVBUF, M_NOWAIT | M_ZERO);
2078 device_printf(sc->sc_dev, "can't allocate txstats data\n");
2081 sc->sc_txstats = st;
2084 * Create TX stats descriptor DMA stuffs
2086 dma_size = roundup(desc_sz * BWI_TXSTATS_NDESC, BWI_RING_ALIGN);
2088 error = bus_dma_tag_create(sc->sc_parent_dtag,
2096 BUS_SPACE_MAXSIZE_32BIT,
2099 &st->stats_ring_dtag);
2101 device_printf(sc->sc_dev, "can't create txstats ring "
2106 error = bus_dmamem_alloc(st->stats_ring_dtag, &st->stats_ring,
2107 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2108 &st->stats_ring_dmap);
2110 device_printf(sc->sc_dev, "can't allocate txstats ring "
2112 bus_dma_tag_destroy(st->stats_ring_dtag);
2113 st->stats_ring_dtag = NULL;
2117 error = bus_dmamap_load(st->stats_ring_dtag, st->stats_ring_dmap,
2118 st->stats_ring, dma_size,
2119 bwi_dma_ring_addr, &st->stats_ring_paddr,
2122 device_printf(sc->sc_dev, "can't load txstats ring DMA mem\n");
2123 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2124 st->stats_ring_dmap);
2125 bus_dma_tag_destroy(st->stats_ring_dtag);
2126 st->stats_ring_dtag = NULL;
2131 * Create TX stats DMA stuffs
2133 dma_size = roundup(sizeof(struct bwi_txstats) * BWI_TXSTATS_NDESC,
2136 error = bus_dma_tag_create(sc->sc_parent_dtag,
2144 BUS_SPACE_MAXSIZE_32BIT,
2149 device_printf(sc->sc_dev, "can't create txstats DMA tag\n");
2153 error = bus_dmamem_alloc(st->stats_dtag, (void **)&st->stats,
2154 BUS_DMA_WAITOK | BUS_DMA_ZERO,
2157 device_printf(sc->sc_dev, "can't allocate txstats DMA mem\n");
2158 bus_dma_tag_destroy(st->stats_dtag);
2159 st->stats_dtag = NULL;
2163 error = bus_dmamap_load(st->stats_dtag, st->stats_dmap, st->stats,
2164 dma_size, bwi_dma_ring_addr, &st->stats_paddr,
2167 device_printf(sc->sc_dev, "can't load txstats DMA mem\n");
2168 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2169 bus_dma_tag_destroy(st->stats_dtag);
2170 st->stats_dtag = NULL;
2174 st->stats_ctrl_base = ctrl_base;
2179 bwi_dma_txstats_free(struct bwi_softc *sc)
2181 struct bwi_txstats_data *st;
2183 if (sc->sc_txstats == NULL)
2185 st = sc->sc_txstats;
2187 if (st->stats_ring_dtag != NULL) {
2188 bus_dmamap_unload(st->stats_ring_dtag, st->stats_ring_dmap);
2189 bus_dmamem_free(st->stats_ring_dtag, st->stats_ring,
2190 st->stats_ring_dmap);
2191 bus_dma_tag_destroy(st->stats_ring_dtag);
2194 if (st->stats_dtag != NULL) {
2195 bus_dmamap_unload(st->stats_dtag, st->stats_dmap);
2196 bus_dmamem_free(st->stats_dtag, st->stats, st->stats_dmap);
2197 bus_dma_tag_destroy(st->stats_dtag);
2204 bwi_dma_ring_addr(void *arg, bus_dma_segment_t *seg, int nseg, int error)
2206 KASSERT(nseg == 1, ("too many segments\n"));
2207 *((bus_addr_t *)arg) = seg->ds_addr;
2211 bwi_dma_mbuf_create(struct bwi_softc *sc)
2213 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2214 int i, j, k, ntx, error;
2217 * Create TX/RX mbuf DMA tag
2219 error = bus_dma_tag_create(sc->sc_parent_dtag,
2227 BUS_SPACE_MAXSIZE_32BIT,
2232 device_printf(sc->sc_dev, "can't create mbuf DMA tag\n");
2239 * Create TX mbuf DMA map
2241 for (i = 0; i < BWI_TX_NRING; ++i) {
2242 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2244 for (j = 0; j < BWI_TX_NDESC; ++j) {
2245 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2246 &tbd->tbd_buf[j].tb_dmap);
2248 device_printf(sc->sc_dev, "can't create "
2249 "%dth tbd, %dth DMA map\n", i, j);
2252 for (k = 0; k < j; ++k) {
2253 bus_dmamap_destroy(sc->sc_buf_dtag,
2254 tbd->tbd_buf[k].tb_dmap);
2263 * Create RX mbuf DMA map and a spare DMA map
2265 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2266 &rbd->rbd_tmp_dmap);
2268 device_printf(sc->sc_dev,
2269 "can't create spare RX buf DMA map\n");
2273 for (j = 0; j < BWI_RX_NDESC; ++j) {
2274 error = bus_dmamap_create(sc->sc_buf_dtag, 0,
2275 &rbd->rbd_buf[j].rb_dmap);
2277 device_printf(sc->sc_dev, "can't create %dth "
2278 "RX buf DMA map\n", j);
2280 for (k = 0; k < j; ++k) {
2281 bus_dmamap_destroy(sc->sc_buf_dtag,
2282 rbd->rbd_buf[j].rb_dmap);
2284 bus_dmamap_destroy(sc->sc_buf_dtag,
2292 bwi_dma_mbuf_destroy(sc, ntx, 0);
2297 bwi_dma_mbuf_destroy(struct bwi_softc *sc, int ntx, int nrx)
2301 if (sc->sc_buf_dtag == NULL)
2304 for (i = 0; i < ntx; ++i) {
2305 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[i];
2307 for (j = 0; j < BWI_TX_NDESC; ++j) {
2308 struct bwi_txbuf *tb = &tbd->tbd_buf[j];
2310 if (tb->tb_mbuf != NULL) {
2311 bus_dmamap_unload(sc->sc_buf_dtag,
2313 m_freem(tb->tb_mbuf);
2315 if (tb->tb_ni != NULL)
2316 ieee80211_free_node(tb->tb_ni);
2317 bus_dmamap_destroy(sc->sc_buf_dtag, tb->tb_dmap);
2322 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2324 bus_dmamap_destroy(sc->sc_buf_dtag, rbd->rbd_tmp_dmap);
2325 for (j = 0; j < BWI_RX_NDESC; ++j) {
2326 struct bwi_rxbuf *rb = &rbd->rbd_buf[j];
2328 if (rb->rb_mbuf != NULL) {
2329 bus_dmamap_unload(sc->sc_buf_dtag,
2331 m_freem(rb->rb_mbuf);
2333 bus_dmamap_destroy(sc->sc_buf_dtag, rb->rb_dmap);
2337 bus_dma_tag_destroy(sc->sc_buf_dtag);
2338 sc->sc_buf_dtag = NULL;
2342 bwi_enable_intrs(struct bwi_softc *sc, uint32_t enable_intrs)
2344 CSR_SETBITS_4(sc, BWI_MAC_INTR_MASK, enable_intrs);
2348 bwi_disable_intrs(struct bwi_softc *sc, uint32_t disable_intrs)
2350 CSR_CLRBITS_4(sc, BWI_MAC_INTR_MASK, disable_intrs);
2354 bwi_init_tx_ring32(struct bwi_softc *sc, int ring_idx)
2356 struct bwi_ring_data *rd;
2357 struct bwi_txbuf_data *tbd;
2358 uint32_t val, addr_hi, addr_lo;
2360 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2361 rd = &sc->sc_tx_rdata[ring_idx];
2362 tbd = &sc->sc_tx_bdata[ring_idx];
2367 bzero(rd->rdata_desc, sizeof(struct bwi_desc32) * BWI_TX_NDESC);
2368 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
2369 BUS_DMASYNC_PREWRITE);
2371 addr_lo = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2372 addr_hi = __SHIFTOUT(rd->rdata_paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2374 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2375 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2376 BWI_TXRX32_RINGINFO_FUNC_MASK);
2377 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, val);
2379 val = __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2380 BWI_TXRX32_CTRL_ENABLE;
2381 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, val);
2387 bwi_init_rxdesc_ring32(struct bwi_softc *sc, uint32_t ctrl_base,
2388 bus_addr_t paddr, int hdr_size, int ndesc)
2390 uint32_t val, addr_hi, addr_lo;
2392 addr_lo = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_ADDR_MASK);
2393 addr_hi = __SHIFTOUT(paddr, BWI_TXRX32_RINGINFO_FUNC_MASK);
2395 val = __SHIFTIN(addr_lo, BWI_TXRX32_RINGINFO_ADDR_MASK) |
2396 __SHIFTIN(BWI_TXRX32_RINGINFO_FUNC_TXRX,
2397 BWI_TXRX32_RINGINFO_FUNC_MASK);
2398 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_RINGINFO, val);
2400 val = __SHIFTIN(hdr_size, BWI_RX32_CTRL_HDRSZ_MASK) |
2401 __SHIFTIN(addr_hi, BWI_TXRX32_CTRL_ADDRHI_MASK) |
2402 BWI_TXRX32_CTRL_ENABLE;
2403 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_CTRL, val);
2405 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
2406 (ndesc - 1) * sizeof(struct bwi_desc32));
2410 bwi_init_rx_ring32(struct bwi_softc *sc)
2412 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2415 sc->sc_rx_bdata.rbd_idx = 0;
2417 for (i = 0; i < BWI_RX_NDESC; ++i) {
2418 error = bwi_newbuf(sc, i, 1);
2420 device_printf(sc->sc_dev,
2421 "can't allocate %dth RX buffer\n", i);
2425 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2426 BUS_DMASYNC_PREWRITE);
2428 bwi_init_rxdesc_ring32(sc, rd->rdata_txrx_ctrl, rd->rdata_paddr,
2429 sizeof(struct bwi_rxbuf_hdr), BWI_RX_NDESC);
2434 bwi_init_txstats32(struct bwi_softc *sc)
2436 struct bwi_txstats_data *st = sc->sc_txstats;
2437 bus_addr_t stats_paddr;
2440 bzero(st->stats, BWI_TXSTATS_NDESC * sizeof(struct bwi_txstats));
2441 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_PREWRITE);
2445 stats_paddr = st->stats_paddr;
2446 for (i = 0; i < BWI_TXSTATS_NDESC; ++i) {
2447 bwi_setup_desc32(sc, st->stats_ring, BWI_TXSTATS_NDESC, i,
2448 stats_paddr, sizeof(struct bwi_txstats), 0);
2449 stats_paddr += sizeof(struct bwi_txstats);
2451 bus_dmamap_sync(st->stats_ring_dtag, st->stats_ring_dmap,
2452 BUS_DMASYNC_PREWRITE);
2454 bwi_init_rxdesc_ring32(sc, st->stats_ctrl_base,
2455 st->stats_ring_paddr, 0, BWI_TXSTATS_NDESC);
2460 bwi_setup_rx_desc32(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2463 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2465 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2466 bwi_setup_desc32(sc, rd->rdata_desc, BWI_RX_NDESC, buf_idx,
2471 bwi_setup_tx_desc32(struct bwi_softc *sc, struct bwi_ring_data *rd,
2472 int buf_idx, bus_addr_t paddr, int buf_len)
2474 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
2475 bwi_setup_desc32(sc, rd->rdata_desc, BWI_TX_NDESC, buf_idx,
2480 bwi_init_tx_ring64(struct bwi_softc *sc, int ring_idx)
2487 bwi_init_rx_ring64(struct bwi_softc *sc)
2494 bwi_init_txstats64(struct bwi_softc *sc)
2501 bwi_setup_rx_desc64(struct bwi_softc *sc, int buf_idx, bus_addr_t paddr,
2508 bwi_setup_tx_desc64(struct bwi_softc *sc, struct bwi_ring_data *rd,
2509 int buf_idx, bus_addr_t paddr, int buf_len)
2515 bwi_dma_buf_addr(void *arg, bus_dma_segment_t *seg, int nseg,
2516 bus_size_t mapsz __unused, int error)
2519 KASSERT(nseg == 1, ("too many segments(%d)\n", nseg));
2520 *((bus_addr_t *)arg) = seg->ds_addr;
2525 bwi_newbuf(struct bwi_softc *sc, int buf_idx, int init)
2527 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2528 struct bwi_rxbuf *rxbuf = &rbd->rbd_buf[buf_idx];
2529 struct bwi_rxbuf_hdr *hdr;
2535 KASSERT(buf_idx < BWI_RX_NDESC, ("buf_idx %d", buf_idx));
2537 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
2542 * If the NIC is up and running, we need to:
2543 * - Clear RX buffer's header.
2544 * - Restore RX descriptor settings.
2551 m->m_len = m->m_pkthdr.len = MCLBYTES;
2554 * Try to load RX buf into temporary DMA map
2556 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, rbd->rbd_tmp_dmap, m,
2557 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
2562 * See the comment above
2571 bus_dmamap_unload(sc->sc_buf_dtag, rxbuf->rb_dmap);
2573 rxbuf->rb_paddr = paddr;
2576 * Swap RX buf's DMA map with the loaded temporary one
2578 map = rxbuf->rb_dmap;
2579 rxbuf->rb_dmap = rbd->rbd_tmp_dmap;
2580 rbd->rbd_tmp_dmap = map;
2584 * Clear RX buf header
2586 hdr = mtod(rxbuf->rb_mbuf, struct bwi_rxbuf_hdr *);
2587 bzero(hdr, sizeof(*hdr));
2588 bus_dmamap_sync(sc->sc_buf_dtag, rxbuf->rb_dmap, BUS_DMASYNC_PREWRITE);
2591 * Setup RX buf descriptor
2593 sc->sc_setup_rxdesc(sc, buf_idx, rxbuf->rb_paddr,
2594 rxbuf->rb_mbuf->m_len - sizeof(*hdr));
2599 bwi_set_addr_filter(struct bwi_softc *sc, uint16_t addr_ofs,
2600 const uint8_t *addr)
2604 CSR_WRITE_2(sc, BWI_ADDR_FILTER_CTRL,
2605 BWI_ADDR_FILTER_CTRL_SET | addr_ofs);
2607 for (i = 0; i < (IEEE80211_ADDR_LEN / 2); ++i) {
2610 addr_val = (uint16_t)addr[i * 2] |
2611 (((uint16_t)addr[(i * 2) + 1]) << 8);
2612 CSR_WRITE_2(sc, BWI_ADDR_FILTER_DATA, addr_val);
2617 bwi_rxeof(struct bwi_softc *sc, int end_idx)
2619 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2620 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2621 struct ifnet *ifp = sc->sc_ifp;
2622 struct ieee80211com *ic = ifp->if_l2com;
2623 int idx, rx_data = 0;
2626 while (idx != end_idx) {
2627 struct bwi_rxbuf *rb = &rbd->rbd_buf[idx];
2628 struct bwi_rxbuf_hdr *hdr;
2629 struct ieee80211_frame_min *wh;
2630 struct ieee80211_node *ni;
2634 int buflen, wh_ofs, hdr_extra, rssi, noise, type, rate;
2637 bus_dmamap_sync(sc->sc_buf_dtag, rb->rb_dmap,
2638 BUS_DMASYNC_POSTREAD);
2640 if (bwi_newbuf(sc, idx, 0)) {
2645 hdr = mtod(m, struct bwi_rxbuf_hdr *);
2646 flags2 = le16toh(hdr->rxh_flags2);
2649 if (flags2 & BWI_RXH_F2_TYPE2FRAME)
2651 wh_ofs = hdr_extra + 6; /* XXX magic number */
2653 buflen = le16toh(hdr->rxh_buflen);
2654 if (buflen < BWI_FRAME_MIN_LEN(wh_ofs)) {
2655 if_printf(ifp, "%s: zero length data, hdr_extra %d\n",
2656 __func__, hdr_extra);
2662 bcopy((uint8_t *)(hdr + 1) + hdr_extra, &plcp, sizeof(plcp));
2663 rssi = bwi_calc_rssi(sc, hdr);
2664 noise = bwi_calc_noise(sc);
2666 m->m_pkthdr.rcvif = ifp;
2667 m->m_len = m->m_pkthdr.len = buflen + sizeof(*hdr);
2668 m_adj(m, sizeof(*hdr) + wh_ofs);
2670 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_OFDM)
2671 rate = bwi_plcp2rate(plcp, IEEE80211_T_OFDM);
2673 rate = bwi_plcp2rate(plcp, IEEE80211_T_CCK);
2676 if (ieee80211_radiotap_active(ic))
2677 bwi_rx_radiotap(sc, m, hdr, &plcp, rate, rssi, noise);
2679 m_adj(m, -IEEE80211_CRC_LEN);
2683 wh = mtod(m, struct ieee80211_frame_min *);
2684 ni = ieee80211_find_rxnode(ic, wh);
2686 type = ieee80211_input(ni, m, rssi - noise, noise);
2687 ieee80211_free_node(ni);
2689 type = ieee80211_input_all(ic, m, rssi - noise, noise);
2690 if (type == IEEE80211_FC0_TYPE_DATA) {
2692 sc->sc_rx_rate = rate;
2697 idx = (idx + 1) % BWI_RX_NDESC;
2699 if (sc->sc_flags & BWI_F_STOP) {
2701 * Take the fast lane, don't do
2702 * any damage to softc
2709 bus_dmamap_sync(sc->sc_rxring_dtag, rd->rdata_dmap,
2710 BUS_DMASYNC_PREWRITE);
2716 bwi_rxeof32(struct bwi_softc *sc)
2718 uint32_t val, rx_ctrl;
2719 int end_idx, rx_data;
2721 rx_ctrl = sc->sc_rx_rdata.rdata_txrx_ctrl;
2723 val = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2724 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
2725 sizeof(struct bwi_desc32);
2727 rx_data = bwi_rxeof(sc, end_idx);
2729 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_INDEX,
2730 end_idx * sizeof(struct bwi_desc32));
2736 bwi_rxeof64(struct bwi_softc *sc)
2743 bwi_reset_rx_ring32(struct bwi_softc *sc, uint32_t rx_ctrl)
2747 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_CTRL, 0);
2751 for (i = 0; i < NRETRY; ++i) {
2754 status = CSR_READ_4(sc, rx_ctrl + BWI_RX32_STATUS);
2755 if (__SHIFTOUT(status, BWI_RX32_STATUS_STATE_MASK) ==
2756 BWI_RX32_STATUS_STATE_DISABLED)
2762 device_printf(sc->sc_dev, "reset rx ring timedout\n");
2766 CSR_WRITE_4(sc, rx_ctrl + BWI_RX32_RINGINFO, 0);
2770 bwi_free_txstats32(struct bwi_softc *sc)
2772 bwi_reset_rx_ring32(sc, sc->sc_txstats->stats_ctrl_base);
2776 bwi_free_rx_ring32(struct bwi_softc *sc)
2778 struct bwi_ring_data *rd = &sc->sc_rx_rdata;
2779 struct bwi_rxbuf_data *rbd = &sc->sc_rx_bdata;
2782 bwi_reset_rx_ring32(sc, rd->rdata_txrx_ctrl);
2784 for (i = 0; i < BWI_RX_NDESC; ++i) {
2785 struct bwi_rxbuf *rb = &rbd->rbd_buf[i];
2787 if (rb->rb_mbuf != NULL) {
2788 bus_dmamap_unload(sc->sc_buf_dtag, rb->rb_dmap);
2789 m_freem(rb->rb_mbuf);
2796 bwi_free_tx_ring32(struct bwi_softc *sc, int ring_idx)
2798 struct bwi_ring_data *rd;
2799 struct bwi_txbuf_data *tbd;
2800 struct ifnet *ifp = sc->sc_ifp;
2801 uint32_t state, val;
2804 KASSERT(ring_idx < BWI_TX_NRING, ("ring_idx %d", ring_idx));
2805 rd = &sc->sc_tx_rdata[ring_idx];
2806 tbd = &sc->sc_tx_bdata[ring_idx];
2810 for (i = 0; i < NRETRY; ++i) {
2811 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2812 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2813 if (state == BWI_TX32_STATUS_STATE_DISABLED ||
2814 state == BWI_TX32_STATUS_STATE_IDLE ||
2815 state == BWI_TX32_STATUS_STATE_STOPPED)
2821 if_printf(ifp, "%s: wait for TX ring(%d) stable timed out\n",
2822 __func__, ring_idx);
2825 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_CTRL, 0);
2826 for (i = 0; i < NRETRY; ++i) {
2827 val = CSR_READ_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_STATUS);
2828 state = __SHIFTOUT(val, BWI_TX32_STATUS_STATE_MASK);
2829 if (state == BWI_TX32_STATUS_STATE_DISABLED)
2835 if_printf(ifp, "%s: reset TX ring (%d) timed out\n",
2836 __func__, ring_idx);
2842 CSR_WRITE_4(sc, rd->rdata_txrx_ctrl + BWI_TX32_RINGINFO, 0);
2844 for (i = 0; i < BWI_TX_NDESC; ++i) {
2845 struct bwi_txbuf *tb = &tbd->tbd_buf[i];
2847 if (tb->tb_mbuf != NULL) {
2848 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
2849 m_freem(tb->tb_mbuf);
2852 if (tb->tb_ni != NULL) {
2853 ieee80211_free_node(tb->tb_ni);
2860 bwi_free_txstats64(struct bwi_softc *sc)
2866 bwi_free_rx_ring64(struct bwi_softc *sc)
2872 bwi_free_tx_ring64(struct bwi_softc *sc, int ring_idx)
2877 /* XXX does not belong here */
2878 #define IEEE80211_OFDM_PLCP_RATE_MASK __BITS(3, 0)
2879 #define IEEE80211_OFDM_PLCP_LEN_MASK __BITS(16, 5)
2881 static __inline void
2882 bwi_ofdm_plcp_header(uint32_t *plcp0, int pkt_len, uint8_t rate)
2886 plcp = __SHIFTIN(ieee80211_rate2plcp(rate, IEEE80211_T_OFDM),
2887 IEEE80211_OFDM_PLCP_RATE_MASK) |
2888 __SHIFTIN(pkt_len, IEEE80211_OFDM_PLCP_LEN_MASK);
2889 *plcp0 = htole32(plcp);
2892 static __inline void
2893 bwi_ds_plcp_header(struct ieee80211_ds_plcp_hdr *plcp, int pkt_len,
2896 int len, service, pkt_bitlen;
2898 pkt_bitlen = pkt_len * NBBY;
2899 len = howmany(pkt_bitlen * 2, rate);
2901 service = IEEE80211_PLCP_SERVICE_LOCKED;
2902 if (rate == (11 * 2)) {
2906 * PLCP service field needs to be adjusted,
2907 * if TX rate is 11Mbytes/s
2909 pkt_bitlen1 = len * 11;
2910 if (pkt_bitlen1 - pkt_bitlen >= NBBY)
2911 service |= IEEE80211_PLCP_SERVICE_LENEXT7;
2914 plcp->i_signal = ieee80211_rate2plcp(rate, IEEE80211_T_CCK);
2915 plcp->i_service = service;
2916 plcp->i_length = htole16(len);
2917 /* NOTE: do NOT touch i_crc */
2920 static __inline void
2921 bwi_plcp_header(const struct ieee80211_rate_table *rt,
2922 void *plcp, int pkt_len, uint8_t rate)
2924 enum ieee80211_phytype modtype;
2927 * Assume caller has zeroed 'plcp'
2929 modtype = ieee80211_rate2phytype(rt, rate);
2930 if (modtype == IEEE80211_T_OFDM)
2931 bwi_ofdm_plcp_header(plcp, pkt_len, rate);
2932 else if (modtype == IEEE80211_T_DS)
2933 bwi_ds_plcp_header(plcp, pkt_len, rate);
2935 panic("unsupport modulation type %u\n", modtype);
2939 bwi_encap(struct bwi_softc *sc, int idx, struct mbuf *m,
2940 struct ieee80211_node *ni)
2942 struct ieee80211vap *vap = ni->ni_vap;
2943 struct ifnet *ifp = sc->sc_ifp;
2944 struct ieee80211com *ic = ifp->if_l2com;
2945 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
2946 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
2947 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
2948 struct bwi_mac *mac;
2949 struct bwi_txbuf_hdr *hdr;
2950 struct ieee80211_frame *wh;
2951 const struct ieee80211_txparam *tp;
2952 uint8_t rate, rate_fb;
2956 int type, ismcast, pkt_len, error, rix;
2962 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
2963 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
2964 mac = (struct bwi_mac *)sc->sc_cur_regwin;
2966 wh = mtod(m, struct ieee80211_frame *);
2967 type = wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK;
2968 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
2970 /* Get 802.11 frame len before prepending TX header */
2971 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
2976 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)];
2977 if (type != IEEE80211_FC0_TYPE_DATA || (m->m_flags & M_EAPOL)) {
2978 rate = rate_fb = tp->mgmtrate;
2979 } else if (ismcast) {
2980 rate = rate_fb = tp->mcastrate;
2981 } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) {
2982 rate = rate_fb = tp->ucastrate;
2984 rix = ieee80211_ratectl_rate(ni, NULL, pkt_len);
2985 rate = ni->ni_txrate;
2988 rate_fb = ni->ni_rates.rs_rates[rix-1] &
2994 tb->tb_rate[0] = rate;
2995 tb->tb_rate[1] = rate_fb;
2996 sc->sc_tx_rate = rate;
3001 if (ieee80211_radiotap_active_vap(vap)) {
3002 sc->sc_tx_th.wt_flags = 0;
3003 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3004 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3005 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_DS &&
3006 (ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
3008 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3010 sc->sc_tx_th.wt_rate = rate;
3012 ieee80211_radiotap_tx(vap, m);
3016 * Setup the embedded TX header
3018 M_PREPEND(m, sizeof(*hdr), M_NOWAIT);
3020 if_printf(ifp, "%s: prepend TX header failed\n", __func__);
3023 hdr = mtod(m, struct bwi_txbuf_hdr *);
3025 bzero(hdr, sizeof(*hdr));
3027 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3028 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3033 dur = ieee80211_ack_duration(sc->sc_rates, rate,
3034 ic->ic_flags & ~IEEE80211_F_SHPREAMBLE);
3036 hdr->txh_fb_duration = htole16(dur);
3039 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3040 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3042 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3043 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3045 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3046 BWI_TXH_PHY_C_ANTMODE_MASK);
3047 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM)
3048 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3049 else if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) && rate != (2 * 1))
3050 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3052 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3054 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3055 if (ieee80211_rate2phytype(sc->sc_rates, rate_fb) == IEEE80211_T_OFDM)
3056 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3058 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3059 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3061 /* Catch any further usage */
3066 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3067 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3068 if (error && error != EFBIG) {
3069 if_printf(ifp, "%s: can't load TX buffer (1) %d\n",
3074 if (error) { /* error == EFBIG */
3077 m_new = m_defrag(m, M_NOWAIT);
3078 if (m_new == NULL) {
3079 if_printf(ifp, "%s: can't defrag TX buffer\n",
3087 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3088 bwi_dma_buf_addr, &paddr,
3091 if_printf(ifp, "%s: can't load TX buffer (2) %d\n",
3098 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3104 p = mtod(m, const uint8_t *);
3105 for (i = 0; i < m->m_pkthdr.len; ++i) {
3106 if (i != 0 && i % 8 == 0)
3108 printf("%02x ", p[i]);
3112 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3113 idx, pkt_len, m->m_pkthdr.len);
3115 /* Setup TX descriptor */
3116 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3117 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3118 BUS_DMASYNC_PREWRITE);
3121 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3130 bwi_encap_raw(struct bwi_softc *sc, int idx, struct mbuf *m,
3131 struct ieee80211_node *ni, const struct ieee80211_bpf_params *params)
3133 struct ifnet *ifp = sc->sc_ifp;
3134 struct ieee80211vap *vap = ni->ni_vap;
3135 struct ieee80211com *ic = ni->ni_ic;
3136 struct bwi_ring_data *rd = &sc->sc_tx_rdata[BWI_TX_DATA_RING];
3137 struct bwi_txbuf_data *tbd = &sc->sc_tx_bdata[BWI_TX_DATA_RING];
3138 struct bwi_txbuf *tb = &tbd->tbd_buf[idx];
3139 struct bwi_mac *mac;
3140 struct bwi_txbuf_hdr *hdr;
3141 struct ieee80211_frame *wh;
3142 uint8_t rate, rate_fb;
3146 int ismcast, pkt_len, error;
3148 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3149 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3150 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3152 wh = mtod(m, struct ieee80211_frame *);
3153 ismcast = IEEE80211_IS_MULTICAST(wh->i_addr1);
3155 /* Get 802.11 frame len before prepending TX header */
3156 pkt_len = m->m_pkthdr.len + IEEE80211_CRC_LEN;
3161 rate = params->ibp_rate0;
3162 if (!ieee80211_isratevalid(ic->ic_rt, rate)) {
3163 /* XXX fall back to mcast/mgmt rate? */
3167 if (params->ibp_try1 != 0) {
3168 rate_fb = params->ibp_rate1;
3169 if (!ieee80211_isratevalid(ic->ic_rt, rate_fb)) {
3170 /* XXX fall back to rate0? */
3176 tb->tb_rate[0] = rate;
3177 tb->tb_rate[1] = rate_fb;
3178 sc->sc_tx_rate = rate;
3183 if (ieee80211_radiotap_active_vap(vap)) {
3184 sc->sc_tx_th.wt_flags = 0;
3185 /* XXX IEEE80211_BPF_CRYPTO */
3186 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3187 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_WEP;
3188 if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3189 sc->sc_tx_th.wt_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3190 sc->sc_tx_th.wt_rate = rate;
3192 ieee80211_radiotap_tx(vap, m);
3196 * Setup the embedded TX header
3198 M_PREPEND(m, sizeof(*hdr), M_NOWAIT);
3200 if_printf(ifp, "%s: prepend TX header failed\n", __func__);
3203 hdr = mtod(m, struct bwi_txbuf_hdr *);
3205 bzero(hdr, sizeof(*hdr));
3207 bcopy(wh->i_fc, hdr->txh_fc, sizeof(hdr->txh_fc));
3208 bcopy(wh->i_addr1, hdr->txh_addr1, sizeof(hdr->txh_addr1));
3210 mac_ctrl = BWI_TXH_MAC_C_HWSEQ | BWI_TXH_MAC_C_FIRST_FRAG;
3211 if (!ismcast && (params->ibp_flags & IEEE80211_BPF_NOACK) == 0) {
3214 dur = ieee80211_ack_duration(sc->sc_rates, rate_fb, 0);
3216 hdr->txh_fb_duration = htole16(dur);
3217 mac_ctrl |= BWI_TXH_MAC_C_ACK;
3220 hdr->txh_id = __SHIFTIN(BWI_TX_DATA_RING, BWI_TXH_ID_RING_MASK) |
3221 __SHIFTIN(idx, BWI_TXH_ID_IDX_MASK);
3223 bwi_plcp_header(sc->sc_rates, hdr->txh_plcp, pkt_len, rate);
3224 bwi_plcp_header(sc->sc_rates, hdr->txh_fb_plcp, pkt_len, rate_fb);
3226 phy_ctrl = __SHIFTIN(mac->mac_rf.rf_ant_mode,
3227 BWI_TXH_PHY_C_ANTMODE_MASK);
3228 if (ieee80211_rate2phytype(sc->sc_rates, rate) == IEEE80211_T_OFDM) {
3229 phy_ctrl |= BWI_TXH_PHY_C_OFDM;
3230 mac_ctrl |= BWI_TXH_MAC_C_FB_OFDM;
3231 } else if (params->ibp_flags & IEEE80211_BPF_SHORTPRE)
3232 phy_ctrl |= BWI_TXH_PHY_C_SHPREAMBLE;
3234 hdr->txh_mac_ctrl = htole32(mac_ctrl);
3235 hdr->txh_phy_ctrl = htole16(phy_ctrl);
3237 /* Catch any further usage */
3242 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3243 bwi_dma_buf_addr, &paddr, BUS_DMA_NOWAIT);
3247 if (error != EFBIG) {
3248 if_printf(ifp, "%s: can't load TX buffer (1) %d\n",
3252 m_new = m_defrag(m, M_NOWAIT);
3253 if (m_new == NULL) {
3254 if_printf(ifp, "%s: can't defrag TX buffer\n",
3260 error = bus_dmamap_load_mbuf(sc->sc_buf_dtag, tb->tb_dmap, m,
3261 bwi_dma_buf_addr, &paddr,
3264 if_printf(ifp, "%s: can't load TX buffer (2) %d\n",
3270 bus_dmamap_sync(sc->sc_buf_dtag, tb->tb_dmap, BUS_DMASYNC_PREWRITE);
3275 DPRINTF(sc, BWI_DBG_TX, "idx %d, pkt_len %d, buflen %d\n",
3276 idx, pkt_len, m->m_pkthdr.len);
3278 /* Setup TX descriptor */
3279 sc->sc_setup_txdesc(sc, rd, idx, paddr, m->m_pkthdr.len);
3280 bus_dmamap_sync(sc->sc_txring_dtag, rd->rdata_dmap,
3281 BUS_DMASYNC_PREWRITE);
3284 sc->sc_start_tx(sc, rd->rdata_txrx_ctrl, idx);
3292 bwi_start_tx32(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3294 idx = (idx + 1) % BWI_TX_NDESC;
3295 CSR_WRITE_4(sc, tx_ctrl + BWI_TX32_INDEX,
3296 idx * sizeof(struct bwi_desc32));
3300 bwi_start_tx64(struct bwi_softc *sc, uint32_t tx_ctrl, int idx)
3306 bwi_txeof_status32(struct bwi_softc *sc)
3308 struct ifnet *ifp = sc->sc_ifp;
3309 uint32_t val, ctrl_base;
3312 ctrl_base = sc->sc_txstats->stats_ctrl_base;
3314 val = CSR_READ_4(sc, ctrl_base + BWI_RX32_STATUS);
3315 end_idx = __SHIFTOUT(val, BWI_RX32_STATUS_INDEX_MASK) /
3316 sizeof(struct bwi_desc32);
3318 bwi_txeof_status(sc, end_idx);
3320 CSR_WRITE_4(sc, ctrl_base + BWI_RX32_INDEX,
3321 end_idx * sizeof(struct bwi_desc32));
3323 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0)
3328 bwi_txeof_status64(struct bwi_softc *sc)
3334 _bwi_txeof(struct bwi_softc *sc, uint16_t tx_id, int acked, int data_txcnt)
3336 struct ifnet *ifp = sc->sc_ifp;
3337 struct bwi_txbuf_data *tbd;
3338 struct bwi_txbuf *tb;
3339 int ring_idx, buf_idx;
3340 struct ieee80211_node *ni;
3341 struct ieee80211vap *vap;
3344 if_printf(ifp, "%s: zero tx id\n", __func__);
3348 ring_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_RING_MASK);
3349 buf_idx = __SHIFTOUT(tx_id, BWI_TXH_ID_IDX_MASK);
3351 KASSERT(ring_idx == BWI_TX_DATA_RING, ("ring_idx %d", ring_idx));
3352 KASSERT(buf_idx < BWI_TX_NDESC, ("buf_idx %d", buf_idx));
3354 tbd = &sc->sc_tx_bdata[ring_idx];
3355 KASSERT(tbd->tbd_used > 0, ("tbd_used %d", tbd->tbd_used));
3358 tb = &tbd->tbd_buf[buf_idx];
3359 DPRINTF(sc, BWI_DBG_TXEOF, "txeof idx %d, "
3360 "acked %d, data_txcnt %d, ni %p\n",
3361 buf_idx, acked, data_txcnt, tb->tb_ni);
3363 bus_dmamap_unload(sc->sc_buf_dtag, tb->tb_dmap);
3366 if (tb->tb_ni != NULL) {
3367 const struct bwi_txbuf_hdr *hdr =
3368 mtod(tb->tb_mbuf, const struct bwi_txbuf_hdr *);
3371 /* NB: update rate control only for unicast frames */
3372 if (hdr->txh_mac_ctrl & htole32(BWI_TXH_MAC_C_ACK)) {
3374 * Feed back 'acked and data_txcnt'. Note that the
3375 * generic AMRR code only understands one tx rate
3376 * and the estimator doesn't handle real retry counts
3377 * well so to avoid over-aggressive downshifting we
3378 * treat any number of retries as "1".
3380 ieee80211_ratectl_tx_complete(vap, ni,
3381 (data_txcnt > 1) ? IEEE80211_RATECTL_TX_SUCCESS :
3382 IEEE80211_RATECTL_TX_FAILURE, &acked, NULL);
3386 * Do any tx complete callback. Note this must
3387 * be done before releasing the node reference.
3389 if (tb->tb_mbuf->m_flags & M_TXCB)
3390 ieee80211_process_callback(ni, tb->tb_mbuf, !acked);
3392 ieee80211_free_node(tb->tb_ni);
3395 m_freem(tb->tb_mbuf);
3398 if (tbd->tbd_used == 0)
3399 sc->sc_tx_timer = 0;
3401 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
3405 bwi_txeof_status(struct bwi_softc *sc, int end_idx)
3407 struct bwi_txstats_data *st = sc->sc_txstats;
3410 bus_dmamap_sync(st->stats_dtag, st->stats_dmap, BUS_DMASYNC_POSTREAD);
3412 idx = st->stats_idx;
3413 while (idx != end_idx) {
3414 const struct bwi_txstats *stats = &st->stats[idx];
3416 if ((stats->txs_flags & BWI_TXS_F_PENDING) == 0) {
3419 data_txcnt = __SHIFTOUT(stats->txs_txcnt,
3420 BWI_TXS_TXCNT_DATA);
3421 _bwi_txeof(sc, le16toh(stats->txs_id),
3422 stats->txs_flags & BWI_TXS_F_ACKED,
3425 idx = (idx + 1) % BWI_TXSTATS_NDESC;
3427 st->stats_idx = idx;
3431 bwi_txeof(struct bwi_softc *sc)
3433 struct ifnet *ifp = sc->sc_ifp;
3436 uint32_t tx_status0, tx_status1;
3440 tx_status0 = CSR_READ_4(sc, BWI_TXSTATUS0);
3441 if ((tx_status0 & BWI_TXSTATUS0_VALID) == 0)
3443 tx_status1 = CSR_READ_4(sc, BWI_TXSTATUS1);
3445 tx_id = __SHIFTOUT(tx_status0, BWI_TXSTATUS0_TXID_MASK);
3446 data_txcnt = __SHIFTOUT(tx_status0,
3447 BWI_TXSTATUS0_DATA_TXCNT_MASK);
3449 if (tx_status0 & (BWI_TXSTATUS0_AMPDU | BWI_TXSTATUS0_PENDING))
3452 _bwi_txeof(sc, le16toh(tx_id), tx_status0 & BWI_TXSTATUS0_ACKED,
3456 if ((ifp->if_drv_flags & IFF_DRV_OACTIVE) == 0)
3461 bwi_bbp_power_on(struct bwi_softc *sc, enum bwi_clock_mode clk_mode)
3463 bwi_power_on(sc, 1);
3464 return bwi_set_clock_mode(sc, clk_mode);
3468 bwi_bbp_power_off(struct bwi_softc *sc)
3470 bwi_set_clock_mode(sc, BWI_CLOCK_MODE_SLOW);
3471 bwi_power_off(sc, 1);
3475 bwi_get_pwron_delay(struct bwi_softc *sc)
3477 struct bwi_regwin *com, *old;
3478 struct bwi_clock_freq freq;
3482 com = &sc->sc_com_regwin;
3483 KASSERT(BWI_REGWIN_EXIST(com), ("no regwin"));
3485 if ((sc->sc_cap & BWI_CAP_CLKMODE) == 0)
3488 error = bwi_regwin_switch(sc, com, &old);
3492 bwi_get_clock_freq(sc, &freq);
3494 val = CSR_READ_4(sc, BWI_PLL_ON_DELAY);
3495 sc->sc_pwron_delay = howmany((val + 2) * 1000000, freq.clkfreq_min);
3496 DPRINTF(sc, BWI_DBG_ATTACH, "power on delay %u\n", sc->sc_pwron_delay);
3498 return bwi_regwin_switch(sc, old, NULL);
3502 bwi_bus_attach(struct bwi_softc *sc)
3504 struct bwi_regwin *bus, *old;
3507 bus = &sc->sc_bus_regwin;
3509 error = bwi_regwin_switch(sc, bus, &old);
3513 if (!bwi_regwin_is_enabled(sc, bus))
3514 bwi_regwin_enable(sc, bus, 0);
3516 /* Disable interripts */
3517 CSR_WRITE_4(sc, BWI_INTRVEC, 0);
3519 return bwi_regwin_switch(sc, old, NULL);
3523 bwi_regwin_name(const struct bwi_regwin *rw)
3525 switch (rw->rw_type) {
3526 case BWI_REGWIN_T_COM:
3528 case BWI_REGWIN_T_BUSPCI:
3530 case BWI_REGWIN_T_MAC:
3532 case BWI_REGWIN_T_BUSPCIE:
3535 panic("unknown regwin type 0x%04x\n", rw->rw_type);
3540 bwi_regwin_disable_bits(struct bwi_softc *sc)
3544 /* XXX cache this */
3545 busrev = __SHIFTOUT(CSR_READ_4(sc, BWI_ID_LO), BWI_ID_LO_BUSREV_MASK);
3546 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT | BWI_DBG_MISC,
3547 "bus rev %u\n", busrev);
3549 if (busrev == BWI_BUSREV_0)
3550 return BWI_STATE_LO_DISABLE1;
3551 else if (busrev == BWI_BUSREV_1)
3552 return BWI_STATE_LO_DISABLE2;
3554 return (BWI_STATE_LO_DISABLE1 | BWI_STATE_LO_DISABLE2);
3558 bwi_regwin_is_enabled(struct bwi_softc *sc, struct bwi_regwin *rw)
3560 uint32_t val, disable_bits;
3562 disable_bits = bwi_regwin_disable_bits(sc);
3563 val = CSR_READ_4(sc, BWI_STATE_LO);
3565 if ((val & (BWI_STATE_LO_CLOCK |
3566 BWI_STATE_LO_RESET |
3567 disable_bits)) == BWI_STATE_LO_CLOCK) {
3568 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is enabled\n",
3569 bwi_regwin_name(rw));
3572 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT, "%s is disabled\n",
3573 bwi_regwin_name(rw));
3579 bwi_regwin_disable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3581 uint32_t state_lo, disable_bits;
3584 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3587 * If current regwin is in 'reset' state, it was already disabled.
3589 if (state_lo & BWI_STATE_LO_RESET) {
3590 DPRINTF(sc, BWI_DBG_ATTACH | BWI_DBG_INIT,
3591 "%s was already disabled\n", bwi_regwin_name(rw));
3595 disable_bits = bwi_regwin_disable_bits(sc);
3598 * Disable normal clock
3600 state_lo = BWI_STATE_LO_CLOCK | disable_bits;
3601 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3604 * Wait until normal clock is disabled
3607 for (i = 0; i < NRETRY; ++i) {
3608 state_lo = CSR_READ_4(sc, BWI_STATE_LO);
3609 if (state_lo & disable_bits)
3614 device_printf(sc->sc_dev, "%s disable clock timeout\n",
3615 bwi_regwin_name(rw));
3618 for (i = 0; i < NRETRY; ++i) {
3621 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3622 if ((state_hi & BWI_STATE_HI_BUSY) == 0)
3627 device_printf(sc->sc_dev, "%s wait BUSY unset timeout\n",
3628 bwi_regwin_name(rw));
3633 * Reset and disable regwin with gated clock
3635 state_lo = BWI_STATE_LO_RESET | disable_bits |
3636 BWI_STATE_LO_CLOCK | BWI_STATE_LO_GATED_CLOCK |
3637 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3638 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3640 /* Flush pending bus write */
3641 CSR_READ_4(sc, BWI_STATE_LO);
3644 /* Reset and disable regwin */
3645 state_lo = BWI_STATE_LO_RESET | disable_bits |
3646 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3647 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3649 /* Flush pending bus write */
3650 CSR_READ_4(sc, BWI_STATE_LO);
3655 bwi_regwin_enable(struct bwi_softc *sc, struct bwi_regwin *rw, uint32_t flags)
3657 uint32_t state_lo, state_hi, imstate;
3659 bwi_regwin_disable(sc, rw, flags);
3661 /* Reset regwin with gated clock */
3662 state_lo = BWI_STATE_LO_RESET |
3663 BWI_STATE_LO_CLOCK |
3664 BWI_STATE_LO_GATED_CLOCK |
3665 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3666 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3668 /* Flush pending bus write */
3669 CSR_READ_4(sc, BWI_STATE_LO);
3672 state_hi = CSR_READ_4(sc, BWI_STATE_HI);
3673 if (state_hi & BWI_STATE_HI_SERROR)
3674 CSR_WRITE_4(sc, BWI_STATE_HI, 0);
3676 imstate = CSR_READ_4(sc, BWI_IMSTATE);
3677 if (imstate & (BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT)) {
3678 imstate &= ~(BWI_IMSTATE_INBAND_ERR | BWI_IMSTATE_TIMEOUT);
3679 CSR_WRITE_4(sc, BWI_IMSTATE, imstate);
3682 /* Enable regwin with gated clock */
3683 state_lo = BWI_STATE_LO_CLOCK |
3684 BWI_STATE_LO_GATED_CLOCK |
3685 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3686 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3688 /* Flush pending bus write */
3689 CSR_READ_4(sc, BWI_STATE_LO);
3692 /* Enable regwin with normal clock */
3693 state_lo = BWI_STATE_LO_CLOCK |
3694 __SHIFTIN(flags, BWI_STATE_LO_FLAGS_MASK);
3695 CSR_WRITE_4(sc, BWI_STATE_LO, state_lo);
3697 /* Flush pending bus write */
3698 CSR_READ_4(sc, BWI_STATE_LO);
3703 bwi_set_bssid(struct bwi_softc *sc, const uint8_t *bssid)
3705 struct ifnet *ifp = sc->sc_ifp;
3706 struct bwi_mac *mac;
3707 struct bwi_myaddr_bssid buf;
3712 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3713 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3714 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3716 bwi_set_addr_filter(sc, BWI_ADDR_FILTER_BSSID, bssid);
3718 bcopy(IF_LLADDR(ifp), buf.myaddr, sizeof(buf.myaddr));
3719 bcopy(bssid, buf.bssid, sizeof(buf.bssid));
3721 n = sizeof(buf) / sizeof(val);
3722 p = (const uint8_t *)&buf;
3723 for (i = 0; i < n; ++i) {
3727 for (j = 0; j < sizeof(val); ++j)
3728 val |= ((uint32_t)(*p++)) << (j * 8);
3730 TMPLT_WRITE_4(mac, 0x20 + (i * sizeof(val)), val);
3735 bwi_updateslot(struct ifnet *ifp)
3737 struct bwi_softc *sc = ifp->if_softc;
3738 struct ieee80211com *ic = ifp->if_l2com;
3739 struct bwi_mac *mac;
3742 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
3743 DPRINTF(sc, BWI_DBG_80211, "%s\n", __func__);
3745 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3746 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3747 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3749 bwi_mac_updateslot(mac, (ic->ic_flags & IEEE80211_F_SHSLOT));
3755 bwi_calibrate(void *xsc)
3757 struct bwi_softc *sc = xsc;
3759 struct ifnet *ifp = sc->sc_ifp;
3760 struct ieee80211com *ic = ifp->if_l2com;
3762 struct bwi_mac *mac;
3764 BWI_ASSERT_LOCKED(sc);
3766 KASSERT(ic->ic_opmode != IEEE80211_M_MONITOR,
3767 ("opmode %d", ic->ic_opmode));
3769 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3770 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3771 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3773 bwi_mac_calibrate_txpower(mac, sc->sc_txpwrcb_type);
3774 sc->sc_txpwrcb_type = BWI_TXPWR_CALIB;
3776 /* XXX 15 seconds */
3777 callout_reset(&sc->sc_calib_ch, hz * 15, bwi_calibrate, sc);
3781 bwi_calc_rssi(struct bwi_softc *sc, const struct bwi_rxbuf_hdr *hdr)
3783 struct bwi_mac *mac;
3785 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3786 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3787 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3789 return bwi_rf_calc_rssi(mac, hdr);
3793 bwi_calc_noise(struct bwi_softc *sc)
3795 struct bwi_mac *mac;
3797 KASSERT(sc->sc_cur_regwin->rw_type == BWI_REGWIN_T_MAC,
3798 ("current regwin type %d", sc->sc_cur_regwin->rw_type));
3799 mac = (struct bwi_mac *)sc->sc_cur_regwin;
3801 return bwi_rf_calc_noise(mac);
3804 static __inline uint8_t
3805 bwi_plcp2rate(const uint32_t plcp0, enum ieee80211_phytype type)
3807 uint32_t plcp = le32toh(plcp0) & IEEE80211_OFDM_PLCP_RATE_MASK;
3808 return (ieee80211_plcp2rate(plcp, type));
3812 bwi_rx_radiotap(struct bwi_softc *sc, struct mbuf *m,
3813 struct bwi_rxbuf_hdr *hdr, const void *plcp, int rate, int rssi, int noise)
3815 const struct ieee80211_frame_min *wh;
3817 sc->sc_rx_th.wr_flags = IEEE80211_RADIOTAP_F_FCS;
3818 if (htole16(hdr->rxh_flags1) & BWI_RXH_F1_SHPREAMBLE)
3819 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_SHORTPRE;
3821 wh = mtod(m, const struct ieee80211_frame_min *);
3822 if (wh->i_fc[1] & IEEE80211_FC1_WEP)
3823 sc->sc_rx_th.wr_flags |= IEEE80211_RADIOTAP_F_WEP;
3825 sc->sc_rx_th.wr_tsf = hdr->rxh_tsf; /* No endian convertion */
3826 sc->sc_rx_th.wr_rate = rate;
3827 sc->sc_rx_th.wr_antsignal = rssi;
3828 sc->sc_rx_th.wr_antnoise = noise;
3832 bwi_led_attach(struct bwi_softc *sc)
3834 const uint8_t *led_act = NULL;
3835 uint16_t gpio, val[BWI_LED_MAX];
3838 #define N(arr) (int)(sizeof(arr) / sizeof(arr[0]))
3840 for (i = 0; i < N(bwi_vendor_led_act); ++i) {
3841 if (sc->sc_pci_subvid == bwi_vendor_led_act[i].vid) {
3842 led_act = bwi_vendor_led_act[i].led_act;
3846 if (led_act == NULL)
3847 led_act = bwi_default_led_act;
3851 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO01);
3852 val[0] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_0);
3853 val[1] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_1);
3855 gpio = bwi_read_sprom(sc, BWI_SPROM_GPIO23);
3856 val[2] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_2);
3857 val[3] = __SHIFTOUT(gpio, BWI_SPROM_GPIO_3);
3859 for (i = 0; i < BWI_LED_MAX; ++i) {
3860 struct bwi_led *led = &sc->sc_leds[i];
3862 if (val[i] == 0xff) {
3863 led->l_act = led_act[i];
3865 if (val[i] & BWI_LED_ACT_LOW)
3866 led->l_flags |= BWI_LED_F_ACTLOW;
3867 led->l_act = __SHIFTOUT(val[i], BWI_LED_ACT_MASK);
3869 led->l_mask = (1 << i);
3871 if (led->l_act == BWI_LED_ACT_BLINK_SLOW ||
3872 led->l_act == BWI_LED_ACT_BLINK_POLL ||
3873 led->l_act == BWI_LED_ACT_BLINK) {
3874 led->l_flags |= BWI_LED_F_BLINK;
3875 if (led->l_act == BWI_LED_ACT_BLINK_POLL)
3876 led->l_flags |= BWI_LED_F_POLLABLE;
3877 else if (led->l_act == BWI_LED_ACT_BLINK_SLOW)
3878 led->l_flags |= BWI_LED_F_SLOW;
3880 if (sc->sc_blink_led == NULL) {
3881 sc->sc_blink_led = led;
3882 if (led->l_flags & BWI_LED_F_SLOW)
3883 BWI_LED_SLOWDOWN(sc->sc_led_idle);
3887 DPRINTF(sc, BWI_DBG_LED | BWI_DBG_ATTACH,
3888 "%dth led, act %d, lowact %d\n", i,
3889 led->l_act, led->l_flags & BWI_LED_F_ACTLOW);
3891 callout_init_mtx(&sc->sc_led_blink_ch, &sc->sc_mtx, 0);
3894 static __inline uint16_t
3895 bwi_led_onoff(const struct bwi_led *led, uint16_t val, int on)
3897 if (led->l_flags & BWI_LED_F_ACTLOW)
3902 val &= ~led->l_mask;
3907 bwi_led_newstate(struct bwi_softc *sc, enum ieee80211_state nstate)
3909 struct ifnet *ifp = sc->sc_ifp;
3910 struct ieee80211com *ic = ifp->if_l2com;
3914 if (nstate == IEEE80211_S_INIT) {
3915 callout_stop(&sc->sc_led_blink_ch);
3916 sc->sc_led_blinking = 0;
3919 if ((ic->ic_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
3922 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
3923 for (i = 0; i < BWI_LED_MAX; ++i) {
3924 struct bwi_led *led = &sc->sc_leds[i];
3927 if (led->l_act == BWI_LED_ACT_UNKN ||
3928 led->l_act == BWI_LED_ACT_NULL)
3931 if ((led->l_flags & BWI_LED_F_BLINK) &&
3932 nstate != IEEE80211_S_INIT)
3935 switch (led->l_act) {
3936 case BWI_LED_ACT_ON: /* Always on */
3939 case BWI_LED_ACT_OFF: /* Always off */
3940 case BWI_LED_ACT_5GHZ: /* TODO: 11A */
3946 case IEEE80211_S_INIT:
3949 case IEEE80211_S_RUN:
3950 if (led->l_act == BWI_LED_ACT_11G &&
3951 ic->ic_curmode != IEEE80211_MODE_11G)
3955 if (led->l_act == BWI_LED_ACT_ASSOC)
3962 val = bwi_led_onoff(led, val, on);
3964 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
3967 bwi_led_event(struct bwi_softc *sc, int event)
3969 struct bwi_led *led = sc->sc_blink_led;
3972 if (event == BWI_LED_EVENT_POLL) {
3973 if ((led->l_flags & BWI_LED_F_POLLABLE) == 0)
3975 if (ticks - sc->sc_led_ticks < sc->sc_led_idle)
3979 sc->sc_led_ticks = ticks;
3980 if (sc->sc_led_blinking)
3984 case BWI_LED_EVENT_RX:
3985 rate = sc->sc_rx_rate;
3987 case BWI_LED_EVENT_TX:
3988 rate = sc->sc_tx_rate;
3990 case BWI_LED_EVENT_POLL:
3994 panic("unknown LED event %d\n", event);
3997 bwi_led_blink_start(sc, bwi_led_duration[rate].on_dur,
3998 bwi_led_duration[rate].off_dur);
4002 bwi_led_blink_start(struct bwi_softc *sc, int on_dur, int off_dur)
4004 struct bwi_led *led = sc->sc_blink_led;
4007 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
4008 val = bwi_led_onoff(led, val, 1);
4009 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
4011 if (led->l_flags & BWI_LED_F_SLOW) {
4012 BWI_LED_SLOWDOWN(on_dur);
4013 BWI_LED_SLOWDOWN(off_dur);
4016 sc->sc_led_blinking = 1;
4017 sc->sc_led_blink_offdur = off_dur;
4019 callout_reset(&sc->sc_led_blink_ch, on_dur, bwi_led_blink_next, sc);
4023 bwi_led_blink_next(void *xsc)
4025 struct bwi_softc *sc = xsc;
4028 val = CSR_READ_2(sc, BWI_MAC_GPIO_CTRL);
4029 val = bwi_led_onoff(sc->sc_blink_led, val, 0);
4030 CSR_WRITE_2(sc, BWI_MAC_GPIO_CTRL, val);
4032 callout_reset(&sc->sc_led_blink_ch, sc->sc_led_blink_offdur,
4033 bwi_led_blink_end, sc);
4037 bwi_led_blink_end(void *xsc)
4039 struct bwi_softc *sc = xsc;
4040 sc->sc_led_blinking = 0;
4044 bwi_restart(void *xsc, int pending)
4046 struct bwi_softc *sc = xsc;
4047 struct ifnet *ifp = sc->sc_ifp;
4049 if_printf(ifp, "%s begin, help!\n", __func__);
4051 bwi_init_statechg(xsc, 0);
4053 bwi_start_locked(ifp);