2 * Copyright (c) 2007-2014 QLogic Corporation. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
24 * THE POSSIBILITY OF SUCH DAMAGE.
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/kernel.h>
35 #include <sys/systm.h>
37 #include <sys/mutex.h>
39 #include <sys/module.h>
40 #include <sys/endian.h>
41 #include <sys/types.h>
42 #include <sys/malloc.h>
46 #include <sys/socket.h>
47 #include <sys/sockio.h>
48 #include <sys/sysctl.h>
50 #include <sys/bitstring.h>
51 #include <sys/limits.h>
52 #include <sys/queue.h>
53 #include <sys/taskqueue.h>
56 #include <net/if_types.h>
57 #include <net/if_arp.h>
58 #include <net/ethernet.h>
59 #include <net/if_dl.h>
60 #include <net/if_media.h>
61 #include <net/if_var.h>
62 #include <net/if_vlan_var.h>
66 #include <netinet/in.h>
67 #include <netinet/ip.h>
68 #include <netinet/ip6.h>
69 #include <netinet/tcp.h>
70 #include <netinet/udp.h>
72 #include <dev/pci/pcireg.h>
73 #include <dev/pci/pcivar.h>
75 #include <machine/atomic.h>
76 #include <machine/resource.h>
77 #include <machine/endian.h>
78 #include <machine/bus.h>
79 #include <machine/in_cksum.h>
81 #include "device_if.h"
85 #if _BYTE_ORDER == _LITTLE_ENDIAN
89 #ifndef __LITTLE_ENDIAN
90 #define __LITTLE_ENDIAN
94 #else /* _BIG_ENDIAN */
102 #undef __LITTLE_ENDIAN
105 #include "ecore_mfw_req.h"
106 #include "ecore_fw_defs.h"
107 #include "ecore_hsi.h"
108 #include "ecore_reg.h"
110 #include "bxe_stats.h"
112 #include "bxe_elink.h"
114 #if __FreeBSD_version < 800054
115 #if defined(__i386__) || defined(__amd64__)
116 #define mb() __asm volatile("mfence;" : : : "memory")
117 #define wmb() __asm volatile("sfence;" : : : "memory")
118 #define rmb() __asm volatile("lfence;" : : : "memory")
119 static __inline void prefetch(void *x)
121 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
131 #if __FreeBSD_version >= 1000000
132 #define PCIR_EXPRESS_DEVICE_STA PCIER_DEVICE_STA
133 #define PCIM_EXP_STA_TRANSACTION_PND PCIEM_STA_TRANSACTION_PND
134 #define PCIR_EXPRESS_LINK_STA PCIER_LINK_STA
135 #define PCIM_LINK_STA_WIDTH PCIEM_LINK_STA_WIDTH
136 #define PCIM_LINK_STA_SPEED PCIEM_LINK_STA_SPEED
137 #define PCIR_EXPRESS_DEVICE_CTL PCIER_DEVICE_CTL
138 #define PCIM_EXP_CTL_MAX_PAYLOAD PCIEM_CTL_MAX_PAYLOAD
139 #define PCIM_EXP_CTL_MAX_READ_REQUEST PCIEM_CTL_MAX_READ_REQUEST
143 #define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
146 #define ARRSIZE(arr) (sizeof(arr) / sizeof((arr)[0]))
149 #define DIV_ROUND_UP(n, d) (((n) + (d) - 1) / (d))
152 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
159 while (x >>= 1) log++;
162 #define ilog2(x) bxe_ilog2(x)
165 #include "ecore_sp.h"
167 #define BRCM_VENDORID 0x14e4
168 #define PCI_ANY_ID (uint16_t)(~0U)
170 struct bxe_device_type
179 #define BCM_PAGE_SHIFT 12
180 #define BCM_PAGE_SIZE (1 << BCM_PAGE_SHIFT)
181 #define BCM_PAGE_MASK (~(BCM_PAGE_SIZE - 1))
182 #define BCM_PAGE_ALIGN(addr) ((addr + BCM_PAGE_SIZE - 1) & BCM_PAGE_MASK)
184 #if BCM_PAGE_SIZE != 4096
185 #error Page sizes other than 4KB are unsupported!
188 #if (BUS_SPACE_MAXADDR > 0xFFFFFFFF)
189 #define U64_LO(addr) ((uint32_t)(((uint64_t)(addr)) & 0xFFFFFFFF))
190 #define U64_HI(addr) ((uint32_t)(((uint64_t)(addr)) >> 32))
192 #define U64_LO(addr) ((uint32_t)(addr))
193 #define U64_HI(addr) (0)
195 #define HILO_U64(hi, lo) ((((uint64_t)(hi)) << 32) + (lo))
197 #define SET_FLAG(value, mask, flag) \
199 (value) &= ~(mask); \
200 (value) |= ((flag) << (mask##_SHIFT)); \
203 #define GET_FLAG(value, mask) \
204 (((value) & (mask)) >> (mask##_SHIFT))
206 #define GET_FIELD(value, fname) \
207 (((value) & (fname##_MASK)) >> (fname##_SHIFT))
209 #define BXE_MAX_SEGMENTS 12 /* 13-1 for parsing buffer */
210 #define BXE_TSO_MAX_SEGMENTS 32
211 #define BXE_TSO_MAX_SIZE (65535 + sizeof(struct ether_vlan_header))
212 #define BXE_TSO_MAX_SEG_SIZE 4096
214 /* dropless fc FW/HW related params */
215 #define BRB_SIZE(sc) (CHIP_IS_E3(sc) ? 1024 : 512)
216 #define MAX_AGG_QS(sc) (CHIP_IS_E1(sc) ? \
217 ETH_MAX_AGGREGATION_QUEUES_E1 : \
218 ETH_MAX_AGGREGATION_QUEUES_E1H_E2)
219 #define FW_DROP_LEVEL(sc) (3 + MAX_SPQ_PENDING + MAX_AGG_QS(sc))
220 #define FW_PREFETCH_CNT 16
221 #define DROPLESS_FC_HEADROOM 100
227 #define RX_SGE_NUM_PAGES 2 /* must be a power of 2 */
228 #define RX_SGE_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_sge))
229 #define RX_SGE_NEXT_PAGE_DESC_CNT 2
230 #define RX_SGE_USABLE_PER_PAGE (RX_SGE_TOTAL_PER_PAGE - RX_SGE_NEXT_PAGE_DESC_CNT)
231 #define RX_SGE_PER_PAGE_MASK (RX_SGE_TOTAL_PER_PAGE - 1)
232 #define RX_SGE_TOTAL (RX_SGE_TOTAL_PER_PAGE * RX_SGE_NUM_PAGES)
233 #define RX_SGE_USABLE (RX_SGE_USABLE_PER_PAGE * RX_SGE_NUM_PAGES)
234 #define RX_SGE_MAX (RX_SGE_TOTAL - 1)
235 #define RX_SGE(x) ((x) & RX_SGE_MAX)
237 #define RX_SGE_NEXT(x) \
238 ((((x) & RX_SGE_PER_PAGE_MASK) == (RX_SGE_USABLE_PER_PAGE - 1)) \
239 ? (x) + 1 + RX_SGE_NEXT_PAGE_DESC_CNT : (x) + 1)
241 #define RX_SGE_MASK_ELEM_SZ 64
242 #define RX_SGE_MASK_ELEM_SHIFT 6
243 #define RX_SGE_MASK_ELEM_MASK ((uint64_t)RX_SGE_MASK_ELEM_SZ - 1)
246 * Creates a bitmask of all ones in less significant bits.
247 * idx - index of the most significant bit in the created mask.
249 #define RX_SGE_ONES_MASK(idx) \
250 (((uint64_t)0x1 << (((idx) & RX_SGE_MASK_ELEM_MASK) + 1)) - 1)
251 #define RX_SGE_MASK_ELEM_ONE_MASK ((uint64_t)(~0))
253 /* Number of uint64_t elements in SGE mask array. */
254 #define RX_SGE_MASK_LEN \
255 ((RX_SGE_NUM_PAGES * RX_SGE_TOTAL_PER_PAGE) / RX_SGE_MASK_ELEM_SZ)
256 #define RX_SGE_MASK_LEN_MASK (RX_SGE_MASK_LEN - 1)
257 #define RX_SGE_NEXT_MASK_ELEM(el) (((el) + 1) & RX_SGE_MASK_LEN_MASK)
260 * dropless fc calculations for SGEs
261 * Number of required SGEs is the sum of two:
262 * 1. Number of possible opened aggregations (next packet for
263 * these aggregations will probably consume SGE immidiatelly)
264 * 2. Rest of BRB blocks divided by 2 (block will consume new SGE only
265 * after placement on BD for new TPA aggregation)
266 * Takes into account RX_SGE_NEXT_PAGE_DESC_CNT "next" elements on each page
268 #define NUM_SGE_REQ(sc) \
269 (MAX_AGG_QS(sc) + (BRB_SIZE(sc) - MAX_AGG_QS(sc)) / 2)
270 #define NUM_SGE_PG_REQ(sc) \
271 ((NUM_SGE_REQ(sc) + RX_SGE_USABLE_PER_PAGE - 1) / RX_SGE_USABLE_PER_PAGE)
272 #define SGE_TH_LO(sc) \
273 (NUM_SGE_REQ(sc) + NUM_SGE_PG_REQ(sc) * RX_SGE_NEXT_PAGE_DESC_CNT)
274 #define SGE_TH_HI(sc) \
275 (SGE_TH_LO(sc) + DROPLESS_FC_HEADROOM)
277 #define PAGES_PER_SGE_SHIFT 0
278 #define PAGES_PER_SGE (1 << PAGES_PER_SGE_SHIFT)
279 #define SGE_PAGE_SIZE BCM_PAGE_SIZE
280 #define SGE_PAGE_SHIFT BCM_PAGE_SHIFT
281 #define SGE_PAGE_ALIGN(addr) BCM_PAGE_ALIGN(addr)
282 #define SGE_PAGES (SGE_PAGE_SIZE * PAGES_PER_SGE)
283 #define TPA_AGG_SIZE min((8 * SGE_PAGES), 0xffff)
289 #define TX_BD_NUM_PAGES 16 /* must be a power of 2 */
290 #define TX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_tx_bd_types))
291 #define TX_BD_USABLE_PER_PAGE (TX_BD_TOTAL_PER_PAGE - 1)
292 #define TX_BD_TOTAL (TX_BD_TOTAL_PER_PAGE * TX_BD_NUM_PAGES)
293 #define TX_BD_USABLE (TX_BD_USABLE_PER_PAGE * TX_BD_NUM_PAGES)
294 #define TX_BD_MAX (TX_BD_TOTAL - 1)
296 #define TX_BD_NEXT(x) \
297 ((((x) & TX_BD_USABLE_PER_PAGE) == (TX_BD_USABLE_PER_PAGE - 1)) ? \
298 ((x) + 2) : ((x) + 1))
299 #define TX_BD(x) ((x) & TX_BD_MAX)
300 #define TX_BD_PAGE(x) (((x) & ~TX_BD_USABLE_PER_PAGE) >> 8)
301 #define TX_BD_IDX(x) ((x) & TX_BD_USABLE_PER_PAGE)
304 * Trigger pending transmits when the number of available BDs is greater
305 * than 1/8 of the total number of usable BDs.
307 #define BXE_TX_CLEANUP_THRESHOLD (TX_BD_USABLE / 8)
308 #define BXE_TX_TIMEOUT 5
314 #define RX_BD_NUM_PAGES 8 /* power of 2 */
315 #define RX_BD_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(struct eth_rx_bd))
316 #define RX_BD_NEXT_PAGE_DESC_CNT 2
317 #define RX_BD_USABLE_PER_PAGE (RX_BD_TOTAL_PER_PAGE - RX_BD_NEXT_PAGE_DESC_CNT)
318 #define RX_BD_PER_PAGE_MASK (RX_BD_TOTAL_PER_PAGE - 1)
319 #define RX_BD_TOTAL (RX_BD_TOTAL_PER_PAGE * RX_BD_NUM_PAGES)
320 #define RX_BD_USABLE (RX_BD_USABLE_PER_PAGE * RX_BD_NUM_PAGES)
321 #define RX_BD_MAX (RX_BD_TOTAL - 1)
324 #define NUM_RX_RINGS RX_BD_NUM_PAGES
325 #define NUM_RX_BD RX_BD_TOTAL
326 #define MAX_RX_BD RX_BD_MAX
327 #define MAX_RX_AVAIL RX_BD_USABLE
330 #define RX_BD_NEXT(x) \
331 ((((x) & RX_BD_PER_PAGE_MASK) == (RX_BD_USABLE_PER_PAGE - 1)) ? \
332 ((x) + 3) : ((x) + 1))
333 #define RX_BD(x) ((x) & RX_BD_MAX)
334 #define RX_BD_PAGE(x) (((x) & ~RX_BD_PER_PAGE_MASK) >> 9)
335 #define RX_BD_IDX(x) ((x) & RX_BD_PER_PAGE_MASK)
338 * dropless fc calculations for BDs
339 * Number of BDs should be as number of buffers in BRB:
340 * Low threshold takes into account RX_BD_NEXT_PAGE_DESC_CNT
341 * "next" elements on each page
343 #define NUM_BD_REQ(sc) \
345 #define NUM_BD_PG_REQ(sc) \
346 ((NUM_BD_REQ(sc) + RX_BD_USABLE_PER_PAGE - 1) / RX_BD_USABLE_PER_PAGE)
347 #define BD_TH_LO(sc) \
349 NUM_BD_PG_REQ(sc) * RX_BD_NEXT_PAGE_DESC_CNT + \
351 #define BD_TH_HI(sc) \
352 (BD_TH_LO(sc) + DROPLESS_FC_HEADROOM)
353 #define MIN_RX_AVAIL(sc) \
354 ((sc)->dropless_fc ? BD_TH_HI(sc) + 128 : 128)
355 #define MIN_RX_SIZE_TPA_HW(sc) \
356 (CHIP_IS_E1(sc) ? ETH_MIN_RX_CQES_WITH_TPA_E1 : \
357 ETH_MIN_RX_CQES_WITH_TPA_E1H_E2)
358 #define MIN_RX_SIZE_NONTPA_HW ETH_MIN_RX_CQES_WITHOUT_TPA
359 #define MIN_RX_SIZE_TPA(sc) \
360 (max(MIN_RX_SIZE_TPA_HW(sc), MIN_RX_AVAIL(sc)))
361 #define MIN_RX_SIZE_NONTPA(sc) \
362 (max(MIN_RX_SIZE_NONTPA_HW, MIN_RX_AVAIL(sc)))
369 * As long as CQE is X times bigger than BD entry we have to allocate X times
370 * more pages for CQ ring in order to keep it balanced with BD ring
372 #define CQE_BD_REL (sizeof(union eth_rx_cqe) / \
373 sizeof(struct eth_rx_bd))
374 #define RCQ_NUM_PAGES (RX_BD_NUM_PAGES * CQE_BD_REL) /* power of 2 */
375 #define RCQ_TOTAL_PER_PAGE (BCM_PAGE_SIZE / sizeof(union eth_rx_cqe))
376 #define RCQ_NEXT_PAGE_DESC_CNT 1
377 #define RCQ_USABLE_PER_PAGE (RCQ_TOTAL_PER_PAGE - RCQ_NEXT_PAGE_DESC_CNT)
378 #define RCQ_TOTAL (RCQ_TOTAL_PER_PAGE * RCQ_NUM_PAGES)
379 #define RCQ_USABLE (RCQ_USABLE_PER_PAGE * RCQ_NUM_PAGES)
380 #define RCQ_MAX (RCQ_TOTAL - 1)
382 #define RCQ_NEXT(x) \
383 ((((x) & RCQ_USABLE_PER_PAGE) == (RCQ_USABLE_PER_PAGE - 1)) ? \
384 ((x) + 1 + RCQ_NEXT_PAGE_DESC_CNT) : ((x) + 1))
385 #define RCQ(x) ((x) & RCQ_MAX)
386 #define RCQ_PAGE(x) (((x) & ~RCQ_USABLE_PER_PAGE) >> 7)
387 #define RCQ_IDX(x) ((x) & RCQ_USABLE_PER_PAGE)
390 #define NUM_RCQ_RINGS RCQ_NUM_PAGES
391 #define NUM_RCQ_BD RCQ_TOTAL
392 #define MAX_RCQ_BD RCQ_MAX
393 #define MAX_RCQ_AVAIL RCQ_USABLE
397 * dropless fc calculations for RCQs
398 * Number of RCQs should be as number of buffers in BRB:
399 * Low threshold takes into account RCQ_NEXT_PAGE_DESC_CNT
400 * "next" elements on each page
402 #define NUM_RCQ_REQ(sc) \
404 #define NUM_RCQ_PG_REQ(sc) \
405 ((NUM_RCQ_REQ(sc) + RCQ_USABLE_PER_PAGE - 1) / RCQ_USABLE_PER_PAGE)
406 #define RCQ_TH_LO(sc) \
408 NUM_RCQ_PG_REQ(sc) * RCQ_NEXT_PAGE_DESC_CNT + \
410 #define RCQ_TH_HI(sc) \
411 (RCQ_TH_LO(sc) + DROPLESS_FC_HEADROOM)
413 /* This is needed for determening of last_max */
414 #define SUB_S16(a, b) (int16_t)((int16_t)(a) - (int16_t)(b))
416 #define __SGE_MASK_SET_BIT(el, bit) \
418 (el) = ((el) | ((uint64_t)0x1 << (bit))); \
421 #define __SGE_MASK_CLEAR_BIT(el, bit) \
423 (el) = ((el) & (~((uint64_t)0x1 << (bit)))); \
426 #define SGE_MASK_SET_BIT(fp, idx) \
427 __SGE_MASK_SET_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
428 ((idx) & RX_SGE_MASK_ELEM_MASK))
430 #define SGE_MASK_CLEAR_BIT(fp, idx) \
431 __SGE_MASK_CLEAR_BIT((fp)->sge_mask[(idx) >> RX_SGE_MASK_ELEM_SHIFT], \
432 ((idx) & RX_SGE_MASK_ELEM_MASK))
434 /* Load / Unload modes */
435 #define LOAD_NORMAL 0
438 #define LOAD_LOOPBACK_EXT 3
439 #define UNLOAD_NORMAL 0
440 #define UNLOAD_CLOSE 1
441 #define UNLOAD_RECOVERY 2
443 /* Some constants... */
444 //#define MAX_PATH_NUM 2
445 //#define E2_MAX_NUM_OF_VFS 64
446 //#define E1H_FUNC_MAX 8
447 //#define E2_FUNC_MAX 4 /* per path */
448 #define MAX_VNIC_NUM 4
449 #define MAX_FUNC_NUM 8 /* common to all chips */
450 //#define MAX_NDSB HC_SB_MAX_SB_E2 /* max non-default status block */
451 #define MAX_RSS_CHAINS 16 /* a constant for HW limit */
452 #define MAX_MSI_VECTOR 8 /* a constant for HW limit */
454 #define ILT_NUM_PAGE_ENTRIES 3072
456 * 57710/11 we use whole table since we have 8 functions.
457 * 57712 we have only 4 functions, but use same size per func, so only half
458 * of the table is used.
460 #define ILT_PER_FUNC (ILT_NUM_PAGE_ENTRIES / 8)
461 #define FUNC_ILT_BASE(func) (func * ILT_PER_FUNC)
463 * the phys address is shifted right 12 bits and has an added
464 * 1=valid bit added to the 53rd bit
465 * then since this is a wide register(TM)
466 * we split it into two 32 bit writes
468 #define ONCHIP_ADDR1(x) ((uint32_t)(((uint64_t)x >> 12) & 0xFFFFFFFF))
469 #define ONCHIP_ADDR2(x) ((uint32_t)((1 << 20) | ((uint64_t)x >> 44)))
471 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
473 #define ETH_OVERHEAD (ETH_HLEN + 8 + 8)
474 #define ETH_MIN_PACKET_SIZE 60
475 #define ETH_MAX_PACKET_SIZE ETHERMTU /* 1500 */
476 #define ETH_MAX_JUMBO_PACKET_SIZE 9600
477 /* TCP with Timestamp Option (32) + IPv6 (40) */
478 #define ETH_MAX_TPA_HEADER_SIZE 72
480 /* max supported alignment is 256 (8 shift) */
481 //#define BXE_RX_ALIGN_SHIFT ((CACHE_LINE_SHIFT < 8) ? CACHE_LINE_SHIFT : 8)
482 #define BXE_RX_ALIGN_SHIFT 8
483 /* FW uses 2 cache lines alignment for start packet and size */
484 #define BXE_FW_RX_ALIGN_START (1 << BXE_RX_ALIGN_SHIFT)
485 #define BXE_FW_RX_ALIGN_END (1 << BXE_RX_ALIGN_SHIFT)
487 #define BXE_PXP_DRAM_ALIGN (BXE_RX_ALIGN_SHIFT - 5) /* XXX ??? */
490 struct resource *resource;
493 bus_space_handle_t handle;
498 struct resource *resource;
503 /* Used to manage DMA allocations. */
505 struct bxe_softc *sc;
510 bus_dma_segment_t seg;
516 /* attn group wiring */
517 #define MAX_DYNAMIC_ATTN_GRPS 8
531 union bxe_host_hc_status_block {
532 /* pointer to fp status block e2 */
533 struct host_hc_status_block_e2 *e2_sb;
534 /* pointer to fp status block e1x */
535 struct host_hc_status_block_e1x *e1x_sb;
539 struct doorbell_set_prod data;
543 struct bxe_sw_tx_bd {
548 /* set on the first BD descriptor when there is a split BD */
549 #define BXE_TSO_SPLIT_BD (1 << 0)
552 struct bxe_sw_rx_bd {
557 struct bxe_sw_tpa_info {
558 struct bxe_sw_rx_bd bd;
559 bus_dma_segment_t seg;
561 #define BXE_TPA_STATE_START 1
562 #define BXE_TPA_STATE_STOP 2
563 uint8_t placement_offset;
564 uint16_t parsing_flags;
570 * This is the HSI fastpath data structure. There can be up to MAX_RSS_CHAIN
571 * instances of the fastpath structure when using multiple queues.
573 struct bxe_fastpath {
574 /* pointer back to parent structure */
575 struct bxe_softc *sc;
578 char tx_mtx_name[32];
580 char rx_mtx_name[32];
582 #define BXE_FP_TX_LOCK(fp) mtx_lock(&fp->tx_mtx)
583 #define BXE_FP_TX_UNLOCK(fp) mtx_unlock(&fp->tx_mtx)
584 #define BXE_FP_TX_LOCK_ASSERT(fp) mtx_assert(&fp->tx_mtx, MA_OWNED)
586 #define BXE_FP_RX_LOCK(fp) mtx_lock(&fp->rx_mtx)
587 #define BXE_FP_RX_UNLOCK(fp) mtx_unlock(&fp->rx_mtx)
588 #define BXE_FP_RX_LOCK_ASSERT(fp) mtx_assert(&fp->rx_mtx, MA_OWNED)
591 struct bxe_dma sb_dma;
592 union bxe_host_hc_status_block status_block;
594 /* transmit chain (tx bds) */
595 struct bxe_dma tx_dma;
596 union eth_tx_bd_types *tx_chain;
598 /* receive chain (rx bds) */
599 struct bxe_dma rx_dma;
600 struct eth_rx_bd *rx_chain;
602 /* receive completion queue chain (rcq bds) */
603 struct bxe_dma rcq_dma;
604 union eth_rx_cqe *rcq_chain;
606 /* receive scatter/gather entry chain (for TPA) */
607 struct bxe_dma rx_sge_dma;
608 struct eth_rx_sge *rx_sge_chain;
611 bus_dma_tag_t tx_mbuf_tag;
612 struct bxe_sw_tx_bd tx_mbuf_chain[TX_BD_TOTAL];
615 bus_dma_tag_t rx_mbuf_tag;
616 struct bxe_sw_rx_bd rx_mbuf_chain[RX_BD_TOTAL];
617 bus_dmamap_t rx_mbuf_spare_map;
620 bus_dma_tag_t rx_sge_mbuf_tag;
621 struct bxe_sw_rx_bd rx_sge_mbuf_chain[RX_SGE_TOTAL];
622 bus_dmamap_t rx_sge_mbuf_spare_map;
624 /* rx tpa mbufs (use the larger size for TPA queue length) */
625 int tpa_enable; /* disabled per fastpath upon error */
626 struct bxe_sw_tpa_info rx_tpa_info[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
627 bus_dmamap_t rx_tpa_info_mbuf_spare_map;
628 uint64_t rx_tpa_queue_used;
630 bus_dmamap_t rx_tpa_mbuf_map[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
631 bus_dmamap_t rx_tpa_mbuf_spare_map;
632 struct mbuf *rx_tpa_mbuf_ptr[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
633 bus_dma_segment_t rx_tpa_mbuf_segs[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
635 uint8_t tpa_state[ETH_MAX_AGGREGATION_QUEUES_E1H_E2];
638 uint16_t *sb_index_values;
639 uint16_t *sb_running_index;
640 uint32_t ustorm_rx_prods_offset;
642 uint8_t igu_sb_id; /* status block number in HW */
643 uint8_t fw_sb_id; /* status block number in FW */
645 uint32_t rx_buf_size;
649 #define BXE_FP_STATE_CLOSED 0x01
650 #define BXE_FP_STATE_IRQ 0x02
651 #define BXE_FP_STATE_OPENING 0x04
652 #define BXE_FP_STATE_OPEN 0x08
653 #define BXE_FP_STATE_HALTING 0x10
654 #define BXE_FP_STATE_HALTED 0x20
656 /* reference back to this fastpath queue number */
657 uint8_t index; /* this is also the 'cid' */
658 #define FP_IDX(fp) (fp->index)
660 /* interrupt taskqueue (fast) */
662 struct taskqueue *tq;
665 /* ethernet client ID (each fastpath set of RX/TX/CQE is a client) */
667 #define FP_CL_ID(fp) (fp->cl_id)
672 /* driver copy of the receive buffer descriptor prod/cons indices */
676 /* driver copy of the receive completion queue prod/cons indices */
680 union bxe_db_prod tx_db;
682 /* Transmit packet producer index (used in eth_tx_bd). */
683 uint16_t tx_pkt_prod;
684 uint16_t tx_pkt_cons;
686 /* Transmit buffer descriptor producer index. */
691 /* status block number in hardware */
693 #define FP_SB_ID(fp) (fp->sb_id)
695 /* driver copy of the fastpath CSTORM/USTORM indices */
700 uint64_t sge_mask[RX_SGE_MASK_LEN];
701 uint16_t rx_sge_prod;
703 struct tstorm_per_queue_stats old_tclient;
704 struct ustorm_per_queue_stats old_uclient;
705 struct xstorm_per_queue_stats old_xclient;
706 struct bxe_eth_q_stats eth_q_stats;
707 struct bxe_eth_q_stats_old eth_q_stats_old;
709 /* Pointer to the receive consumer in the status block */
710 uint16_t *rx_cq_cons_sb;
712 /* Pointer to the transmit consumer in the status block */
713 uint16_t *tx_cons_sb;
715 /* transmit timeout until chip reset */
718 /* Free/used buffer descriptor counters. */
719 //uint16_t used_tx_bd;
721 /* Last maximal completed SGE */
722 uint16_t last_max_sge;
724 //uint16_t rx_sge_free_idx;
728 #if __FreeBSD_version >= 800000
729 #define BXE_BR_SIZE 4096
730 struct buf_ring *tx_br;
732 }; /* struct bxe_fastpath */
735 #define BXE_MAX_NUM_OF_VFS 64
736 #define BXE_VF_CID_WND 0
737 #define BXE_CIDS_PER_VF (1 << BXE_VF_CID_WND)
738 #define BXE_CLIENTS_PER_VF 1
739 #define BXE_FIRST_VF_CID 256
740 #define BXE_VF_CIDS (BXE_MAX_NUM_OF_VFS * BXE_CIDS_PER_VF)
741 #define BXE_VF_ID_INVALID 0xFF
742 #define IS_SRIOV(sc) 0
744 #define GET_NUM_VFS_PER_PATH(sc) 0
745 #define GET_NUM_VFS_PER_PF(sc) 0
747 /* maximum number of fast-path interrupt contexts */
748 #define FP_SB_MAX_E1x 16
749 #define FP_SB_MAX_E2 HC_SB_MAX_SB_E2
752 struct eth_context eth;
756 /* CDU host DB constants */
757 #define CDU_ILT_PAGE_SZ_HW 2
758 #define CDU_ILT_PAGE_SZ (8192 << CDU_ILT_PAGE_SZ_HW) /* 32K */
759 #define ILT_PAGE_CIDS (CDU_ILT_PAGE_SZ / sizeof(union cdu_context))
761 #define CNIC_ISCSI_CID_MAX 256
762 #define CNIC_FCOE_CID_MAX 2048
763 #define CNIC_CID_MAX (CNIC_ISCSI_CID_MAX + CNIC_FCOE_CID_MAX)
764 #define CNIC_ILT_LINES DIV_ROUND_UP(CNIC_CID_MAX, ILT_PAGE_CIDS)
766 #define QM_ILT_PAGE_SZ_HW 0
767 #define QM_ILT_PAGE_SZ (4096 << QM_ILT_PAGE_SZ_HW) /* 4K */
768 #define QM_CID_ROUND 1024
770 /* TM (timers) host DB constants */
771 #define TM_ILT_PAGE_SZ_HW 0
772 #define TM_ILT_PAGE_SZ (4096 << TM_ILT_PAGE_SZ_HW) /* 4K */
773 /*#define TM_CONN_NUM (CNIC_STARTING_CID+CNIC_ISCSI_CXT_MAX) */
774 #define TM_CONN_NUM 1024
775 #define TM_ILT_SZ (8 * TM_CONN_NUM)
776 #define TM_ILT_LINES DIV_ROUND_UP(TM_ILT_SZ, TM_ILT_PAGE_SZ)
778 /* SRC (Searcher) host DB constants */
779 #define SRC_ILT_PAGE_SZ_HW 0
780 #define SRC_ILT_PAGE_SZ (4096 << SRC_ILT_PAGE_SZ_HW) /* 4K */
781 #define SRC_HASH_BITS 10
782 #define SRC_CONN_NUM (1 << SRC_HASH_BITS) /* 1024 */
783 #define SRC_ILT_SZ (sizeof(struct src_ent) * SRC_CONN_NUM)
784 #define SRC_T2_SZ SRC_ILT_SZ
785 #define SRC_ILT_LINES DIV_ROUND_UP(SRC_ILT_SZ, SRC_ILT_PAGE_SZ)
788 struct bxe_dma vcxt_dma;
789 union cdu_context *vcxt;
790 //bus_addr_t cxt_mapping;
797 /* defines for multiple tx priority indices */
798 #define FIRST_TX_ONLY_COS_INDEX 1
799 #define FIRST_TX_COS_INDEX 0
801 #define CID_TO_FP(cid, sc) ((cid) % BXE_NUM_NON_CNIC_QUEUES(sc))
803 #define HC_INDEX_ETH_RX_CQ_CONS 1
804 #define HC_INDEX_OOO_TX_CQ_CONS 4
805 #define HC_INDEX_ETH_TX_CQ_CONS_COS0 5
806 #define HC_INDEX_ETH_TX_CQ_CONS_COS1 6
807 #define HC_INDEX_ETH_TX_CQ_CONS_COS2 7
808 #define HC_INDEX_ETH_FIRST_TX_CQ_CONS HC_INDEX_ETH_TX_CQ_CONS_COS0
810 /* congestion management fairness mode */
811 #define CMNG_FNS_NONE 0
812 #define CMNG_FNS_MINMAX 1
814 /* CMNG constants, as derived from system spec calculations */
815 /* default MIN rate in case VNIC min rate is configured to zero - 100Mbps */
816 #define DEF_MIN_RATE 100
817 /* resolution of the rate shaping timer - 400 usec */
818 #define RS_PERIODIC_TIMEOUT_USEC 400
819 /* number of bytes in single QM arbitration cycle -
820 * coefficient for calculating the fairness timer */
821 #define QM_ARB_BYTES 160000
822 /* resolution of Min algorithm 1:100 */
824 /* how many bytes above threshold for the minimal credit of Min algorithm*/
825 #define MIN_ABOVE_THRESH 32768
826 /* fairness algorithm integration time coefficient -
827 * for calculating the actual Tfair */
828 #define T_FAIR_COEF ((MIN_ABOVE_THRESH + QM_ARB_BYTES) * 8 * MIN_RES)
829 /* memory of fairness algorithm - 2 cycles */
832 #define HC_SEG_ACCESS_DEF 0 /* Driver decision 0-3 */
833 #define HC_SEG_ACCESS_ATTN 4
834 #define HC_SEG_ACCESS_NORM 0 /* Driver decision 0-1 */
837 * The total number of L2 queues, MSIX vectors and HW contexts (CIDs) is
838 * control by the number of fast-path status blocks supported by the
839 * device (HW/FW). Each fast-path status block (FP-SB) aka non-default
840 * status block represents an independent interrupts context that can
841 * serve a regular L2 networking queue. However special L2 queues such
842 * as the FCoE queue do not require a FP-SB and other components like
843 * the CNIC may consume FP-SB reducing the number of possible L2 queues
845 * If the maximum number of FP-SB available is X then:
846 * a. If CNIC is supported it consumes 1 FP-SB thus the max number of
847 * regular L2 queues is Y=X-1
848 * b. in MF mode the actual number of L2 queues is Y= (X-1/MF_factor)
849 * c. If the FCoE L2 queue is supported the actual number of L2 queues
851 * d. The number of irqs (MSIX vectors) is either Y+1 (one extra for
852 * slow-path interrupts) or Y+2 if CNIC is supported (one additional
853 * FP interrupt context for the CNIC).
854 * e. The number of HW context (CID count) is always X or X+1 if FCoE
855 * L2 queue is supported. the cid for the FCoE L2 queue is always X.
857 * So this is quite simple for now as no ULPs are supported yet. :-)
859 #define BXE_NUM_QUEUES(sc) ((sc)->num_queues)
860 #define BXE_NUM_ETH_QUEUES(sc) BXE_NUM_QUEUES(sc)
861 #define BXE_NUM_NON_CNIC_QUEUES(sc) BXE_NUM_QUEUES(sc)
862 #define BXE_NUM_RX_QUEUES(sc) BXE_NUM_QUEUES(sc)
864 #define FOR_EACH_QUEUE(sc, var) \
865 for ((var) = 0; (var) < BXE_NUM_QUEUES(sc); (var)++)
867 #define FOR_EACH_NONDEFAULT_QUEUE(sc, var) \
868 for ((var) = 1; (var) < BXE_NUM_QUEUES(sc); (var)++)
870 #define FOR_EACH_ETH_QUEUE(sc, var) \
871 for ((var) = 0; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++)
873 #define FOR_EACH_NONDEFAULT_ETH_QUEUE(sc, var) \
874 for ((var) = 1; (var) < BXE_NUM_ETH_QUEUES(sc); (var)++)
876 #define FOR_EACH_COS_IN_TX_QUEUE(sc, var) \
877 for ((var) = 0; (var) < (sc)->max_cos; (var)++)
879 #define FOR_EACH_CNIC_QUEUE(sc, var) \
880 for ((var) = BXE_NUM_ETH_QUEUES(sc); \
881 (var) < BXE_NUM_QUEUES(sc); \
890 #define FCOE_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FCOE_IDX_OFFSET)
891 #define bxe_fcoe_fp(sc) (&sc->fp[FCOE_IDX(sc)])
892 #define bxe_fcoe(sc, var) (bxe_fcoe_fp(sc)->var)
893 #define bxe_fcoe_inner_sp_obj(sc) (&sc->sp_objs[FCOE_IDX(sc)])
894 #define bxe_fcoe_sp_obj(sc, var) (bxe_fcoe_inner_sp_obj(sc)->var)
895 #define bxe_fcoe_tx(sc, var) (bxe_fcoe_fp(sc)->txdata_ptr[FIRST_TX_COS_INDEX]->var)
897 #define OOO_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + OOO_IDX_OFFSET)
898 #define bxe_ooo_fp(sc) (&sc->fp[OOO_IDX(sc)])
899 #define bxe_ooo(sc, var) (bxe_ooo_fp(sc)->var)
900 #define bxe_ooo_inner_sp_obj(sc) (&sc->sp_objs[OOO_IDX(sc)])
901 #define bxe_ooo_sp_obj(sc, var) (bxe_ooo_inner_sp_obj(sc)->var)
903 #define FWD_IDX(sc) (BXE_NUM_NON_CNIC_QUEUES(sc) + FWD_IDX_OFFSET)
904 #define bxe_fwd_fp(sc) (&sc->fp[FWD_IDX(sc)])
905 #define bxe_fwd(sc, var) (bxe_fwd_fp(sc)->var)
906 #define bxe_fwd_inner_sp_obj(sc) (&sc->sp_objs[FWD_IDX(sc)])
907 #define bxe_fwd_sp_obj(sc, var) (bxe_fwd_inner_sp_obj(sc)->var)
908 #define bxe_fwd_txdata(fp) (fp->txdata_ptr[FIRST_TX_COS_INDEX])
910 #define IS_ETH_FP(fp) ((fp)->index < BXE_NUM_ETH_QUEUES((fp)->sc))
911 #define IS_FCOE_FP(fp) ((fp)->index == FCOE_IDX((fp)->sc))
912 #define IS_FCOE_IDX(idx) ((idx) == FCOE_IDX(sc))
913 #define IS_FWD_FP(fp) ((fp)->index == FWD_IDX((fp)->sc))
914 #define IS_FWD_IDX(idx) ((idx) == FWD_IDX(sc))
915 #define IS_OOO_FP(fp) ((fp)->index == OOO_IDX((fp)->sc))
916 #define IS_OOO_IDX(idx) ((idx) == OOO_IDX(sc))
922 BXE_FIRST_QUEUE_QUERY_IDX,
925 struct bxe_fw_stats_req {
926 struct stats_query_header hdr;
927 struct stats_query_entry query[FP_SB_MAX_E1x +
928 BXE_FIRST_QUEUE_QUERY_IDX];
931 struct bxe_fw_stats_data {
932 struct stats_counter storm_counters;
933 struct per_port_stats port;
934 struct per_pf_stats pf;
935 //struct fcoe_statistics_params fcoe;
936 struct per_queue_stats queue_stats[1];
939 /* IGU MSIX STATISTICS on 57712: 64 for VFs; 4 for PFs; 4 for Attentions */
940 #define BXE_IGU_STAS_MSG_VF_CNT 64
941 #define BXE_IGU_STAS_MSG_PF_CNT 4
946 * For the main interface up/down code paths, a not-so-fine-grained CORE
947 * mutex lock is used. Inside this code are various calls to kernel routines
948 * that can cause a sleep to occur. Namely memory allocations and taskqueue
949 * handling. If using an MTX lock we are *not* allowed to sleep but we can
950 * with an SX lock. This define forces the CORE lock to use and SX lock.
951 * Undefine this and an MTX lock will be used instead. Note that the IOCTL
952 * path can cause problems since it's called by a non-sleepable thread. To
953 * alleviate a potential sleep, any IOCTL processing that results in the
954 * chip/interface being started/stopped/reinitialized, the actual work is
955 * offloaded to a taskqueue.
957 #define BXE_CORE_LOCK_SX
960 * This is the slowpath data structure. It is mapped into non-paged memory
961 * so that the hardware can access it's contents directly and must be page
964 struct bxe_slowpath {
968 * The cdu_context array MUST be the first element in this
969 * structure. It is used during the leading edge ramrod
972 union cdu_context context[MAX_CONTEXT];
974 /* Used as a DMA source for MAC configuration. */
975 struct mac_configuration_cmd mac_config;
976 struct mac_configuration_cmd mcast_config;
979 /* used by the DMAE command executer */
980 struct dmae_command dmae[MAX_DMAE_C];
982 /* statistics completion */
985 /* firmware defined statistics blocks */
986 union mac_stats mac_stats;
987 struct nig_stats nig_stats;
988 struct host_port_stats port_stats;
989 struct host_func_stats func_stats;
990 //struct host_func_stats func_stats_base;
992 /* DMAE completion value and data source/sink */
997 struct mac_configuration_cmd e1x;
998 struct eth_classify_rules_ramrod_data e2;
1002 struct tstorm_eth_mac_filter_config e1x;
1003 struct eth_filter_rules_ramrod_data e2;
1006 struct eth_rss_update_ramrod_data rss_rdata;
1009 struct mac_configuration_cmd e1;
1010 struct eth_multicast_rules_ramrod_data e2;
1014 struct function_start_data func_start;
1015 struct flow_control_configuration pfc_config; /* for DCBX ramrod */
1018 /* Queue State related ramrods */
1020 struct client_init_ramrod_data init_data;
1021 struct client_update_ramrod_data update_data;
1025 * AFEX ramrod can not be a part of func_rdata union because these
1026 * events might arrive in parallel to other events from func_rdata.
1027 * If they were defined in the same union the data can get corrupted.
1029 struct afex_vif_list_ramrod_data func_afex_rdata;
1031 union drv_info_to_mcp drv_info_to_mcp;
1032 }; /* struct bxe_slowpath */
1035 * Port specifc data structure.
1039 * Port Management Function (for 57711E only).
1040 * When this field is set the driver instance is
1041 * responsible for managing port specifc
1042 * configurations such as handling link attentions.
1046 /* Ethernet maximum transmission unit. */
1049 uint32_t link_config[ELINK_LINK_CONFIG_SIZE];
1051 uint32_t ext_phy_config;
1053 /* Port feature config.*/
1056 /* Defines the features supported by the PHY. */
1057 uint32_t supported[ELINK_LINK_CONFIG_SIZE];
1059 /* Defines the features advertised by the PHY. */
1060 uint32_t advertising[ELINK_LINK_CONFIG_SIZE];
1061 #define ADVERTISED_10baseT_Half (1 << 1)
1062 #define ADVERTISED_10baseT_Full (1 << 2)
1063 #define ADVERTISED_100baseT_Half (1 << 3)
1064 #define ADVERTISED_100baseT_Full (1 << 4)
1065 #define ADVERTISED_1000baseT_Half (1 << 5)
1066 #define ADVERTISED_1000baseT_Full (1 << 6)
1067 #define ADVERTISED_TP (1 << 7)
1068 #define ADVERTISED_FIBRE (1 << 8)
1069 #define ADVERTISED_Autoneg (1 << 9)
1070 #define ADVERTISED_Asym_Pause (1 << 10)
1071 #define ADVERTISED_Pause (1 << 11)
1072 #define ADVERTISED_2500baseX_Full (1 << 15)
1073 #define ADVERTISED_10000baseT_Full (1 << 16)
1077 /* Used to synchronize phy accesses. */
1079 char phy_mtx_name[32];
1081 #define BXE_PHY_LOCK(sc) mtx_lock(&sc->port.phy_mtx)
1082 #define BXE_PHY_UNLOCK(sc) mtx_unlock(&sc->port.phy_mtx)
1083 #define BXE_PHY_LOCK_ASSERT(sc) mtx_assert(&sc->port.phy_mtx, MA_OWNED)
1086 * MCP scratchpad address for port specific statistics.
1087 * The device is responsible for writing statistcss
1088 * back to the MCP for use with management firmware such
1093 struct nig_stats old_nig_stats;
1094 }; /* struct bxe_port */
1096 struct bxe_mf_info {
1097 uint32_t mf_config[E1HVN_MAX];
1099 uint32_t vnics_per_port; /* 1, 2 or 4 */
1100 uint32_t multi_vnics_mode; /* can be set even if vnics_per_port = 1 */
1101 uint32_t path_has_ovlan; /* MF mode in the path (can be different than the MF mode of the function */
1103 #define IS_MULTI_VNIC(sc) ((sc)->devinfo.mf_info.multi_vnics_mode)
1104 #define VNICS_PER_PORT(sc) ((sc)->devinfo.mf_info.vnics_per_port)
1105 #define VNICS_PER_PATH(sc) \
1106 ((sc)->devinfo.mf_info.vnics_per_port * \
1107 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 1 ))
1109 uint8_t min_bw[MAX_VNIC_NUM];
1110 uint8_t max_bw[MAX_VNIC_NUM];
1112 uint16_t ext_id; /* vnic outer vlan or VIF ID */
1113 #define VALID_OVLAN(ovlan) ((ovlan) <= 4096)
1114 #define INVALID_VIF_ID 0xFFFF
1115 #define OVLAN(sc) ((sc)->devinfo.mf_info.ext_id)
1116 #define VIF_ID(sc) ((sc)->devinfo.mf_info.ext_id)
1118 uint16_t default_vlan;
1119 #define NIV_DEFAULT_VLAN(sc) ((sc)->devinfo.mf_info.default_vlan)
1121 uint8_t niv_allowed_priorities;
1122 #define NIV_ALLOWED_PRIORITIES(sc) ((sc)->devinfo.mf_info.niv_allowed_priorities)
1124 uint8_t niv_default_cos;
1125 #define NIV_DEFAULT_COS(sc) ((sc)->devinfo.mf_info.niv_default_cos)
1127 uint8_t niv_mba_enabled;
1129 enum mf_cfg_afex_vlan_mode afex_vlan_mode;
1130 #define AFEX_VLAN_MODE(sc) ((sc)->devinfo.mf_info.afex_vlan_mode)
1131 int afex_def_vlan_tag;
1132 uint32_t pending_max;
1135 #define MF_INFO_VALID_MAC 0x0001
1137 uint8_t mf_mode; /* Switch-Dependent or Switch-Independent */
1139 (IS_MULTI_VNIC(sc) && \
1140 ((sc)->devinfo.mf_info.mf_mode != 0))
1141 #define IS_MF_SD(sc) \
1142 (IS_MULTI_VNIC(sc) && \
1143 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SD))
1144 #define IS_MF_SI(sc) \
1145 (IS_MULTI_VNIC(sc) && \
1146 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_SI))
1147 #define IS_MF_AFEX(sc) \
1148 (IS_MULTI_VNIC(sc) && \
1149 ((sc)->devinfo.mf_info.mf_mode == MULTI_FUNCTION_AFEX))
1150 #define IS_MF_SD_MODE(sc) IS_MF_SD(sc)
1151 #define IS_MF_SI_MODE(sc) IS_MF_SI(sc)
1152 #define IS_MF_AFEX_MODE(sc) IS_MF_AFEX(sc)
1154 uint32_t mf_protos_supported;
1155 #define MF_PROTO_SUPPORT_ETHERNET 0x1
1156 #define MF_PROTO_SUPPORT_ISCSI 0x2
1157 #define MF_PROTO_SUPPORT_FCOE 0x4
1158 }; /* struct bxe_mf_info */
1160 /* Device information data structure. */
1161 struct bxe_devinfo {
1165 uint16_t subvendor_id;
1166 uint16_t subdevice_id;
1169 * chip_id = 0b'CCCCCCCCCCCCCCCCRRRRMMMMMMMMBBBB'
1170 * C = Chip Number (bits 16-31)
1171 * R = Chip Revision (bits 12-15)
1172 * M = Chip Metal (bits 4-11)
1173 * B = Chip Bond ID (bits 0-3)
1176 #define CHIP_ID(sc) ((sc)->devinfo.chip_id & 0xffff0000)
1177 #define CHIP_NUM(sc) ((sc)->devinfo.chip_id >> 16)
1179 #define CHIP_NUM_57710 0x164e
1180 #define CHIP_NUM_57711 0x164f
1181 #define CHIP_NUM_57711E 0x1650
1182 #define CHIP_NUM_57712 0x1662
1183 #define CHIP_NUM_57712_MF 0x1663
1184 #define CHIP_NUM_57712_VF 0x166f
1185 #define CHIP_NUM_57800 0x168a
1186 #define CHIP_NUM_57800_MF 0x16a5
1187 #define CHIP_NUM_57800_VF 0x16a9
1188 #define CHIP_NUM_57810 0x168e
1189 #define CHIP_NUM_57810_MF 0x16ae
1190 #define CHIP_NUM_57810_VF 0x16af
1191 #define CHIP_NUM_57811 0x163d
1192 #define CHIP_NUM_57811_MF 0x163e
1193 #define CHIP_NUM_57811_VF 0x163f
1194 #define CHIP_NUM_57840_OBS 0x168d
1195 #define CHIP_NUM_57840_OBS_MF 0x16ab
1196 #define CHIP_NUM_57840_4_10 0x16a1
1197 #define CHIP_NUM_57840_2_20 0x16a2
1198 #define CHIP_NUM_57840_MF 0x16a4
1199 #define CHIP_NUM_57840_VF 0x16ad
1201 #define CHIP_REV_SHIFT 12
1202 #define CHIP_REV_MASK (0xF << CHIP_REV_SHIFT)
1203 #define CHIP_REV(sc) ((sc)->devinfo.chip_id & CHIP_REV_MASK)
1205 #define CHIP_REV_Ax (0x0 << CHIP_REV_SHIFT)
1206 #define CHIP_REV_Bx (0x1 << CHIP_REV_SHIFT)
1207 #define CHIP_REV_Cx (0x2 << CHIP_REV_SHIFT)
1209 #define CHIP_REV_IS_SLOW(sc) \
1210 (CHIP_REV(sc) > 0x00005000)
1211 #define CHIP_REV_IS_FPGA(sc) \
1212 (CHIP_REV_IS_SLOW(sc) && (CHIP_REV(sc) & 0x00001000))
1213 #define CHIP_REV_IS_EMUL(sc) \
1214 (CHIP_REV_IS_SLOW(sc) && !(CHIP_REV(sc) & 0x00001000))
1215 #define CHIP_REV_IS_ASIC(sc) \
1216 (!CHIP_REV_IS_SLOW(sc))
1218 #define CHIP_METAL(sc) ((sc->devinfo.chip_id) & 0x00000ff0)
1219 #define CHIP_BOND_ID(sc) ((sc->devinfo.chip_id) & 0x0000000f)
1221 #define CHIP_IS_E1(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
1222 #define CHIP_IS_57710(sc) (CHIP_NUM(sc) == CHIP_NUM_57710)
1223 #define CHIP_IS_57711(sc) (CHIP_NUM(sc) == CHIP_NUM_57711)
1224 #define CHIP_IS_57711E(sc) (CHIP_NUM(sc) == CHIP_NUM_57711E)
1225 #define CHIP_IS_E1H(sc) ((CHIP_IS_57711(sc)) || \
1226 (CHIP_IS_57711E(sc)))
1227 #define CHIP_IS_E1x(sc) (CHIP_IS_E1((sc)) || \
1230 #define CHIP_IS_57712(sc) (CHIP_NUM(sc) == CHIP_NUM_57712)
1231 #define CHIP_IS_57712_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_MF)
1232 #define CHIP_IS_57712_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57712_VF)
1233 #define CHIP_IS_E2(sc) (CHIP_IS_57712(sc) || \
1234 CHIP_IS_57712_MF(sc))
1236 #define CHIP_IS_57800(sc) (CHIP_NUM(sc) == CHIP_NUM_57800)
1237 #define CHIP_IS_57800_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_MF)
1238 #define CHIP_IS_57800_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57800_VF)
1239 #define CHIP_IS_57810(sc) (CHIP_NUM(sc) == CHIP_NUM_57810)
1240 #define CHIP_IS_57810_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_MF)
1241 #define CHIP_IS_57810_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57810_VF)
1242 #define CHIP_IS_57811(sc) (CHIP_NUM(sc) == CHIP_NUM_57811)
1243 #define CHIP_IS_57811_MF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_MF)
1244 #define CHIP_IS_57811_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57811_VF)
1245 #define CHIP_IS_57840(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS) || \
1246 (CHIP_NUM(sc) == CHIP_NUM_57840_4_10) || \
1247 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20))
1248 #define CHIP_IS_57840_MF(sc) ((CHIP_NUM(sc) == CHIP_NUM_57840_OBS_MF) || \
1249 (CHIP_NUM(sc) == CHIP_NUM_57840_MF))
1250 #define CHIP_IS_57840_VF(sc) (CHIP_NUM(sc) == CHIP_NUM_57840_VF)
1252 #define CHIP_IS_E3(sc) (CHIP_IS_57800(sc) || \
1253 CHIP_IS_57800_MF(sc) || \
1254 CHIP_IS_57800_VF(sc) || \
1255 CHIP_IS_57810(sc) || \
1256 CHIP_IS_57810_MF(sc) || \
1257 CHIP_IS_57810_VF(sc) || \
1258 CHIP_IS_57811(sc) || \
1259 CHIP_IS_57811_MF(sc) || \
1260 CHIP_IS_57811_VF(sc) || \
1261 CHIP_IS_57840(sc) || \
1262 CHIP_IS_57840_MF(sc) || \
1263 CHIP_IS_57840_VF(sc))
1264 #define CHIP_IS_E3A0(sc) (CHIP_IS_E3(sc) && \
1265 (CHIP_REV(sc) == CHIP_REV_Ax))
1266 #define CHIP_IS_E3B0(sc) (CHIP_IS_E3(sc) && \
1267 (CHIP_REV(sc) == CHIP_REV_Bx))
1269 #define USES_WARPCORE(sc) (CHIP_IS_E3(sc))
1270 #define CHIP_IS_E2E3(sc) (CHIP_IS_E2(sc) || \
1273 #define CHIP_IS_MF_CAP(sc) (CHIP_IS_57711E(sc) || \
1274 CHIP_IS_57712_MF(sc) || \
1277 #define IS_VF(sc) (CHIP_IS_57712_VF(sc) || \
1278 CHIP_IS_57800_VF(sc) || \
1279 CHIP_IS_57810_VF(sc) || \
1280 CHIP_IS_57840_VF(sc))
1281 #define IS_PF(sc) (!IS_VF(sc))
1284 * This define is used in two main places:
1285 * 1. In the early stages of nic_load, to know if to configure Parser/Searcher
1286 * to nic-only mode or to offload mode. Offload mode is configured if either
1287 * the chip is E1x (where NIC_MODE register is not applicable), or if cnic
1288 * already registered for this port (which means that the user wants storage
1290 * 2. During cnic-related load, to know if offload mode is already configured
1291 * in the HW or needs to be configrued. Since the transition from nic-mode to
1292 * offload-mode in HW causes traffic coruption, nic-mode is configured only
1293 * in ports on which storage services where never requested.
1295 #define CONFIGURE_NIC_MODE(sc) (!CHIP_IS_E1x(sc) && !CNIC_ENABLED(sc))
1297 uint8_t chip_port_mode;
1298 #define CHIP_4_PORT_MODE 0x0
1299 #define CHIP_2_PORT_MODE 0x1
1300 #define CHIP_PORT_MODE_NONE 0x2
1301 #define CHIP_PORT_MODE(sc) ((sc)->devinfo.chip_port_mode)
1302 #define CHIP_IS_MODE_4_PORT(sc) (CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE)
1305 #define INT_BLOCK_HC 0
1306 #define INT_BLOCK_IGU 1
1307 #define INT_BLOCK_MODE_NORMAL 0
1308 #define INT_BLOCK_MODE_BW_COMP 2
1309 #define CHIP_INT_MODE_IS_NBC(sc) \
1310 (!CHIP_IS_E1x(sc) && \
1311 !((sc)->devinfo.int_block & INT_BLOCK_MODE_BW_COMP))
1312 #define CHIP_INT_MODE_IS_BC(sc) (!CHIP_INT_MODE_IS_NBC(sc))
1314 uint32_t shmem_base;
1315 uint32_t shmem2_base;
1317 char bc_ver_str[32];
1318 uint32_t mf_cfg_base; /* bootcode shmem address in BAR memory */
1319 struct bxe_mf_info mf_info;
1322 #define NVRAM_1MB_SIZE 0x20000
1323 #define NVRAM_TIMEOUT_COUNT 30000
1324 #define NVRAM_PAGE_SIZE 256
1326 /* PCIe capability information */
1327 uint32_t pcie_cap_flags;
1328 #define BXE_PM_CAPABLE_FLAG 0x00000001
1329 #define BXE_PCIE_CAPABLE_FLAG 0x00000002
1330 #define BXE_MSI_CAPABLE_FLAG 0x00000004
1331 #define BXE_MSIX_CAPABLE_FLAG 0x00000008
1332 uint16_t pcie_pm_cap_reg;
1333 uint16_t pcie_pcie_cap_reg;
1334 //uint16_t pcie_devctl;
1335 uint16_t pcie_link_width;
1336 uint16_t pcie_link_speed;
1337 uint16_t pcie_msi_cap_reg;
1338 uint16_t pcie_msix_cap_reg;
1340 /* device configuration read from bootcode shared memory */
1342 uint32_t hw_config2;
1343 }; /* struct bxe_devinfo */
1345 struct bxe_sp_objs {
1346 struct ecore_vlan_mac_obj mac_obj; /* MACs object */
1347 struct ecore_queue_sp_obj q_obj; /* Queue State object */
1348 }; /* struct bxe_sp_objs */
1351 * Data that will be used to create a link report message. We will keep the
1352 * data used for the last link report in order to prevent reporting the same
1353 * link parameters twice.
1355 struct bxe_link_report_data {
1356 uint16_t line_speed; /* Effective line speed */
1357 unsigned long link_report_flags; /* BXE_LINK_REPORT_XXX flags */
1360 BXE_LINK_REPORT_FULL_DUPLEX,
1361 BXE_LINK_REPORT_LINK_DOWN,
1362 BXE_LINK_REPORT_RX_FC_ON,
1363 BXE_LINK_REPORT_TX_FC_ON
1366 /* Top level device private data structure. */
1369 * First entry must be a pointer to the BSD ifnet struct which
1370 * has a first element of 'void *if_softc' (which is us).
1372 struct ifnet *ifnet;
1373 struct ifmedia ifmedia; /* network interface media structure */
1376 int state; /* device state */
1377 #define BXE_STATE_CLOSED 0x0000
1378 #define BXE_STATE_OPENING_WAITING_LOAD 0x1000
1379 #define BXE_STATE_OPENING_WAITING_PORT 0x2000
1380 #define BXE_STATE_OPEN 0x3000
1381 #define BXE_STATE_CLOSING_WAITING_HALT 0x4000
1382 #define BXE_STATE_CLOSING_WAITING_DELETE 0x5000
1383 #define BXE_STATE_CLOSING_WAITING_UNLOAD 0x6000
1384 #define BXE_STATE_DISABLED 0xD000
1385 #define BXE_STATE_DIAG 0xE000
1386 #define BXE_STATE_ERROR 0xF000
1389 #define BXE_ONE_PORT_FLAG 0x00000001
1390 #define BXE_NO_ISCSI 0x00000002
1391 #define BXE_NO_FCOE 0x00000004
1392 #define BXE_ONE_PORT(sc) (sc->flags & BXE_ONE_PORT_FLAG)
1393 //#define BXE_NO_WOL_FLAG 0x00000008
1394 //#define BXE_USING_DAC_FLAG 0x00000010
1395 //#define BXE_USING_MSIX_FLAG 0x00000020
1396 //#define BXE_USING_MSI_FLAG 0x00000040
1397 //#define BXE_DISABLE_MSI_FLAG 0x00000080
1398 #define BXE_NO_MCP_FLAG 0x00000200
1399 #define BXE_NOMCP(sc) (sc->flags & BXE_NO_MCP_FLAG)
1400 //#define BXE_SAFC_TX_FLAG 0x00000400
1401 #define BXE_MF_FUNC_DIS 0x00000800
1402 #define BXE_TX_SWITCHING 0x00001000
1404 unsigned long debug; /* per-instance debug logging config */
1407 struct bxe_bar bar[MAX_BARS]; /* map BARs 0, 2, 4 */
1409 uint16_t doorbell_size;
1411 /* periodic timer callout */
1412 #define PERIODIC_STOP 0
1413 #define PERIODIC_GO 1
1414 volatile unsigned long periodic_flags;
1415 struct callout periodic_callout;
1417 /* chip start/stop/reset taskqueue */
1418 #define CHIP_TQ_NONE 0
1419 #define CHIP_TQ_START 1
1420 #define CHIP_TQ_STOP 2
1421 #define CHIP_TQ_REINIT 3
1422 volatile unsigned long chip_tq_flags;
1423 struct task chip_tq_task;
1424 struct taskqueue *chip_tq;
1425 char chip_tq_name[32];
1427 /* slowpath interrupt taskqueue */
1428 struct task sp_tq_task;
1429 struct taskqueue *sp_tq;
1430 char sp_tq_name[32];
1432 /* set rx_mode asynchronous taskqueue */
1433 struct task rx_mode_tq_task;
1434 struct taskqueue *rx_mode_tq;
1435 char rx_mode_tq_name[32];
1437 struct bxe_fastpath fp[MAX_RSS_CHAINS];
1438 struct bxe_sp_objs sp_objs[MAX_RSS_CHAINS];
1440 device_t dev; /* parent device handle */
1441 uint8_t unit; /* driver instance number */
1443 int pcie_bus; /* PCIe bus number */
1444 int pcie_device; /* PCIe device/slot number */
1445 int pcie_func; /* PCIe function number */
1447 uint8_t pfunc_rel; /* function relative */
1448 uint8_t pfunc_abs; /* function absolute */
1449 uint8_t path_id; /* function absolute */
1450 #define SC_PATH(sc) (sc->path_id)
1451 #define SC_PORT(sc) (sc->pfunc_rel & 1)
1452 #define SC_FUNC(sc) (sc->pfunc_rel)
1453 #define SC_ABS_FUNC(sc) (sc->pfunc_abs)
1454 #define SC_VN(sc) (sc->pfunc_rel >> 1)
1455 #define SC_L_ID(sc) (SC_VN(sc) << 2)
1456 #define PORT_ID(sc) SC_PORT(sc)
1457 #define PATH_ID(sc) SC_PATH(sc)
1458 #define VNIC_ID(sc) SC_VN(sc)
1459 #define FUNC_ID(sc) SC_FUNC(sc)
1460 #define ABS_FUNC_ID(sc) SC_ABS_FUNC(sc)
1461 #define SC_FW_MB_IDX_VN(sc, vn) \
1462 (SC_PORT(sc) + (vn) * \
1463 ((CHIP_IS_E1x(sc) || (CHIP_IS_MODE_4_PORT(sc))) ? 2 : 1))
1464 #define SC_FW_MB_IDX(sc) SC_FW_MB_IDX_VN(sc, SC_VN(sc))
1466 int if_capen; /* enabled interface capabilities */
1468 struct bxe_devinfo devinfo;
1469 char fw_ver_str[32];
1470 char mf_mode_str[32];
1471 char pci_link_str[32];
1473 const struct iro *iro_array;
1475 #ifdef BXE_CORE_LOCK_SX
1477 char core_sx_name[32];
1479 struct mtx core_mtx;
1480 char core_mtx_name[32];
1483 char sp_mtx_name[32];
1484 struct mtx dmae_mtx;
1485 char dmae_mtx_name[32];
1486 struct mtx fwmb_mtx;
1487 char fwmb_mtx_name[32];
1488 struct mtx print_mtx;
1489 char print_mtx_name[32];
1490 struct mtx stats_mtx;
1491 char stats_mtx_name[32];
1492 struct mtx mcast_mtx;
1493 char mcast_mtx_name[32];
1495 #ifdef BXE_CORE_LOCK_SX
1496 #define BXE_CORE_TRYLOCK(sc) sx_try_xlock(&sc->core_sx)
1497 #define BXE_CORE_LOCK(sc) sx_xlock(&sc->core_sx)
1498 #define BXE_CORE_UNLOCK(sc) sx_xunlock(&sc->core_sx)
1499 #define BXE_CORE_LOCK_ASSERT(sc) sx_assert(&sc->core_sx, SA_XLOCKED)
1501 #define BXE_CORE_TRYLOCK(sc) mtx_trylock(&sc->core_mtx)
1502 #define BXE_CORE_LOCK(sc) mtx_lock(&sc->core_mtx)
1503 #define BXE_CORE_UNLOCK(sc) mtx_unlock(&sc->core_mtx)
1504 #define BXE_CORE_LOCK_ASSERT(sc) mtx_assert(&sc->core_mtx, MA_OWNED)
1507 #define BXE_SP_LOCK(sc) mtx_lock(&sc->sp_mtx)
1508 #define BXE_SP_UNLOCK(sc) mtx_unlock(&sc->sp_mtx)
1509 #define BXE_SP_LOCK_ASSERT(sc) mtx_assert(&sc->sp_mtx, MA_OWNED)
1511 #define BXE_DMAE_LOCK(sc) mtx_lock(&sc->dmae_mtx)
1512 #define BXE_DMAE_UNLOCK(sc) mtx_unlock(&sc->dmae_mtx)
1513 #define BXE_DMAE_LOCK_ASSERT(sc) mtx_assert(&sc->dmae_mtx, MA_OWNED)
1515 #define BXE_FWMB_LOCK(sc) mtx_lock(&sc->fwmb_mtx)
1516 #define BXE_FWMB_UNLOCK(sc) mtx_unlock(&sc->fwmb_mtx)
1517 #define BXE_FWMB_LOCK_ASSERT(sc) mtx_assert(&sc->fwmb_mtx, MA_OWNED)
1519 #define BXE_PRINT_LOCK(sc) mtx_lock(&sc->print_mtx)
1520 #define BXE_PRINT_UNLOCK(sc) mtx_unlock(&sc->print_mtx)
1521 #define BXE_PRINT_LOCK_ASSERT(sc) mtx_assert(&sc->print_mtx, MA_OWNED)
1523 #define BXE_STATS_LOCK(sc) mtx_lock(&sc->stats_mtx)
1524 #define BXE_STATS_UNLOCK(sc) mtx_unlock(&sc->stats_mtx)
1525 #define BXE_STATS_LOCK_ASSERT(sc) mtx_assert(&sc->stats_mtx, MA_OWNED)
1527 #if __FreeBSD_version < 800000
1528 #define BXE_MCAST_LOCK(sc) \
1530 mtx_lock(&sc->mcast_mtx); \
1531 IF_ADDR_LOCK(sc->ifnet); \
1533 #define BXE_MCAST_UNLOCK(sc) \
1535 IF_ADDR_UNLOCK(sc->ifnet); \
1536 mtx_unlock(&sc->mcast_mtx); \
1539 #define BXE_MCAST_LOCK(sc) \
1541 mtx_lock(&sc->mcast_mtx); \
1542 if_maddr_rlock(sc->ifnet); \
1544 #define BXE_MCAST_UNLOCK(sc) \
1546 if_maddr_runlock(sc->ifnet); \
1547 mtx_unlock(&sc->mcast_mtx); \
1550 #define BXE_MCAST_LOCK_ASSERT(sc) mtx_assert(&sc->mcast_mtx, MA_OWNED)
1553 #define DMAE_READY(sc) (sc->dmae_ready)
1555 struct ecore_credit_pool_obj vlans_pool;
1556 struct ecore_credit_pool_obj macs_pool;
1557 struct ecore_rx_mode_obj rx_mode_obj;
1558 struct ecore_mcast_obj mcast_obj;
1559 struct ecore_rss_config_obj rss_conf_obj;
1560 struct ecore_func_sp_obj func_obj;
1563 uint16_t fw_drv_pulse_wr_seq;
1566 struct elink_params link_params;
1567 struct elink_vars link_vars;
1569 struct bxe_link_report_data last_reported_link;
1570 char mac_addr_str[32];
1572 int last_reported_link_state;
1580 #define BXE_RECOVERY_DONE 1
1581 #define BXE_RECOVERY_INIT 2
1582 #define BXE_RECOVERY_WAIT 3
1583 #define BXE_RECOVERY_FAILED 4
1584 #define BXE_RECOVERY_NIC_LOADING 5
1587 #define BXE_RX_MODE_NONE 0
1588 #define BXE_RX_MODE_NORMAL 1
1589 #define BXE_RX_MODE_ALLMULTI 2
1590 #define BXE_RX_MODE_PROMISC 3
1591 #define BXE_MAX_MULTICAST 64
1593 struct bxe_port port;
1595 struct cmng_init cmng;
1603 int max_aggregation_size;
1606 #define AUTO_GREEN_HW_DEFAULT 0
1607 #define AUTO_GREEN_FORCE_ON 1
1608 #define AUTO_GREEN_FORCE_OFF 2
1610 #define INTR_MODE_INTX 0
1611 #define INTR_MODE_MSI 1
1612 #define INTR_MODE_MSIX 2
1615 /* interrupt allocations */
1616 struct bxe_intr intr[MAX_RSS_CHAINS+1];
1619 uint8_t igu_base_sb;
1621 //uint8_t min_msix_vec_cnt;
1622 uint32_t igu_base_addr;
1623 //bus_addr_t def_status_blk_mapping;
1624 uint8_t base_fw_ndsb;
1625 #define DEF_SB_IGU_ID 16
1626 #define DEF_SB_ID HC_SP_SB_ID
1628 /* parent bus DMA tag */
1629 bus_dma_tag_t parent_dma_tag;
1631 /* default status block */
1632 struct bxe_dma def_sb_dma;
1633 struct host_sp_status_block *def_sb;
1635 uint16_t def_att_idx;
1636 uint32_t attn_state;
1637 struct attn_route attn_group[MAX_DYNAMIC_ATTN_GRPS];
1639 /* general SP events - stats query, cfc delete, etc */
1640 #define HC_SP_INDEX_ETH_DEF_CONS 3
1641 /* EQ completions */
1642 #define HC_SP_INDEX_EQ_CONS 7
1643 /* FCoE L2 connection completions */
1644 #define HC_SP_INDEX_ETH_FCOE_TX_CQ_CONS 6
1645 #define HC_SP_INDEX_ETH_FCOE_RX_CQ_CONS 4
1647 #define HC_SP_INDEX_ETH_ISCSI_CQ_CONS 5
1648 #define HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS 1
1651 struct bxe_dma eq_dma;
1652 union event_ring_elem *eq;
1655 uint16_t *eq_cons_sb;
1656 #define NUM_EQ_PAGES 1 /* must be a power of 2 */
1657 #define EQ_DESC_CNT_PAGE (BCM_PAGE_SIZE / sizeof(union event_ring_elem))
1658 #define EQ_DESC_MAX_PAGE (EQ_DESC_CNT_PAGE - 1)
1659 #define NUM_EQ_DESC (EQ_DESC_CNT_PAGE * NUM_EQ_PAGES)
1660 #define EQ_DESC_MASK (NUM_EQ_DESC - 1)
1661 #define MAX_EQ_AVAIL (EQ_DESC_MAX_PAGE * NUM_EQ_PAGES - 2)
1662 /* depends on EQ_DESC_CNT_PAGE being a power of 2 */
1663 #define NEXT_EQ_IDX(x) \
1664 ((((x) & EQ_DESC_MAX_PAGE) == (EQ_DESC_MAX_PAGE - 1)) ? \
1665 ((x) + 2) : ((x) + 1))
1666 /* depends on the above and on NUM_EQ_PAGES being a power of 2 */
1667 #define EQ_DESC(x) ((x) & EQ_DESC_MASK)
1670 struct bxe_dma sp_dma;
1671 struct bxe_slowpath *sp;
1672 unsigned long sp_state;
1674 /* slow path queue */
1675 struct bxe_dma spq_dma;
1676 struct eth_spe *spq;
1677 #define SP_DESC_CNT (BCM_PAGE_SIZE / sizeof(struct eth_spe))
1678 #define MAX_SP_DESC_CNT (SP_DESC_CNT - 1)
1679 #define MAX_SPQ_PENDING 8
1681 uint16_t spq_prod_idx;
1682 struct eth_spe *spq_prod_bd;
1683 struct eth_spe *spq_last_bd;
1684 uint16_t *dsb_sp_prod;
1685 //uint16_t *spq_hw_con;
1686 //uint16_t spq_left;
1688 volatile unsigned long eq_spq_left; /* COMMON_xxx ramrod credit */
1689 volatile unsigned long cq_spq_left; /* ETH_xxx ramrod credit */
1691 /* fw decompression buffer */
1692 struct bxe_dma gz_buf_dma;
1696 #define GUNZIP_BUF(sc) (sc->gz_buf)
1697 #define GUNZIP_OUTLEN(sc) (sc->gz_outlen)
1698 #define GUNZIP_PHYS(sc) (sc->gz_buf_dma.paddr)
1699 #define FW_BUF_SIZE 0x40000
1701 const struct raw_op *init_ops;
1702 const uint16_t *init_ops_offsets; /* init block offsets inside init_ops */
1703 const uint32_t *init_data; /* data blob, 32 bit granularity */
1704 uint32_t init_mode_flags;
1705 #define INIT_MODE_FLAGS(sc) (sc->init_mode_flags)
1706 /* PRAM blobs - raw data */
1707 const uint8_t *tsem_int_table_data;
1708 const uint8_t *tsem_pram_data;
1709 const uint8_t *usem_int_table_data;
1710 const uint8_t *usem_pram_data;
1711 const uint8_t *xsem_int_table_data;
1712 const uint8_t *xsem_pram_data;
1713 const uint8_t *csem_int_table_data;
1714 const uint8_t *csem_pram_data;
1715 #define INIT_OPS(sc) (sc->init_ops)
1716 #define INIT_OPS_OFFSETS(sc) (sc->init_ops_offsets)
1717 #define INIT_DATA(sc) (sc->init_data)
1718 #define INIT_TSEM_INT_TABLE_DATA(sc) (sc->tsem_int_table_data)
1719 #define INIT_TSEM_PRAM_DATA(sc) (sc->tsem_pram_data)
1720 #define INIT_USEM_INT_TABLE_DATA(sc) (sc->usem_int_table_data)
1721 #define INIT_USEM_PRAM_DATA(sc) (sc->usem_pram_data)
1722 #define INIT_XSEM_INT_TABLE_DATA(sc) (sc->xsem_int_table_data)
1723 #define INIT_XSEM_PRAM_DATA(sc) (sc->xsem_pram_data)
1724 #define INIT_CSEM_INT_TABLE_DATA(sc) (sc->csem_int_table_data)
1725 #define INIT_CSEM_PRAM_DATA(sc) (sc->csem_pram_data)
1728 * For max 196 cids (64*3 + non-eth), 32KB ILT page size and 1KB
1729 * context size we need 8 ILT entries.
1731 #define ILT_MAX_L2_LINES 8
1732 struct hw_context context[ILT_MAX_L2_LINES];
1733 struct ecore_ilt *ilt;
1734 #define ILT_MAX_LINES 256
1736 /* max supported number of RSS queues: IGU SBs minus one for CNIC */
1737 #define BXE_MAX_RSS_COUNT(sc) ((sc)->igu_sb_cnt - CNIC_SUPPORT(sc))
1738 /* max CID count: Max RSS * Max_Tx_Multi_Cos + FCoE + iSCSI */
1740 #define BXE_L2_MAX_CID(sc) \
1741 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1743 #define BXE_L2_MAX_CID(sc) /* OOO + FWD */ \
1744 (BXE_MAX_RSS_COUNT(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc))
1747 #define BXE_L2_CID_COUNT(sc) \
1748 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 2 * CNIC_SUPPORT(sc))
1750 #define BXE_L2_CID_COUNT(sc) /* OOO + FWD */ \
1751 (BXE_NUM_ETH_QUEUES(sc) * ECORE_MULTI_TX_COS + 4 * CNIC_SUPPORT(sc))
1753 #define L2_ILT_LINES(sc) \
1754 (DIV_ROUND_UP(BXE_L2_CID_COUNT(sc), ILT_PAGE_CIDS))
1758 uint8_t dropless_fc;
1764 /* total number of FW statistics requests */
1765 uint8_t fw_stats_num;
1767 * This is a memory buffer that will contain both statistics ramrod
1770 struct bxe_dma fw_stats_dma;
1772 * FW statistics request shortcut (points at the beginning of fw_stats
1775 int fw_stats_req_size;
1776 struct bxe_fw_stats_req *fw_stats_req;
1777 bus_addr_t fw_stats_req_mapping;
1779 * FW statistics data shortcut (points at the beginning of fw_stats
1780 * buffer + fw_stats_req_size).
1782 int fw_stats_data_size;
1783 struct bxe_fw_stats_data *fw_stats_data;
1784 bus_addr_t fw_stats_data_mapping;
1786 /* tracking a pending STAT_QUERY ramrod */
1787 uint16_t stats_pending;
1788 /* number of completed statistics ramrods */
1789 uint16_t stats_comp;
1790 uint16_t stats_counter;
1794 struct bxe_eth_stats eth_stats;
1795 struct host_func_stats func_stats;
1796 struct bxe_eth_stats_old eth_stats_old;
1797 struct bxe_net_stats_old net_stats_old;
1798 struct bxe_fw_port_stats_old fw_stats_old;
1800 struct dmae_command stats_dmae; /* used by dmae command loader */
1806 struct bxe_config_lldp_params lldp_config_params;
1807 /* DCB support on/off */
1809 #define BXE_DCB_STATE_OFF 0
1810 #define BXE_DCB_STATE_ON 1
1811 /* DCBX engine mode */
1813 #define BXE_DCBX_ENABLED_OFF 0
1814 #define BXE_DCBX_ENABLED_ON_NEG_OFF 1
1815 #define BXE_DCBX_ENABLED_ON_NEG_ON 2
1816 #define BXE_DCBX_ENABLED_INVALID -1
1817 uint8_t dcbx_mode_uset;
1818 struct bxe_config_dcbx_params dcbx_config_params;
1819 struct bxe_dcbx_port_params dcbx_port_params;
1822 uint8_t cnic_support;
1823 uint8_t cnic_enabled;
1824 uint8_t cnic_loaded;
1825 #define CNIC_SUPPORT(sc) 0 /* ((sc)->cnic_support) */
1826 #define CNIC_ENABLED(sc) 0 /* ((sc)->cnic_enabled) */
1827 #define CNIC_LOADED(sc) 0 /* ((sc)->cnic_loaded) */
1829 /* multiple tx classes of service */
1831 #define BXE_MAX_PRIORITY 8
1832 /* priority to cos mapping */
1833 uint8_t prio_to_cos[BXE_MAX_PRIORITY];
1836 }; /* struct bxe_softc */
1838 /* IOCTL sub-commands for edebug and firmware upgrade */
1839 #define BXE_IOC_RD_NVRAM 1
1840 #define BXE_IOC_WR_NVRAM 2
1841 #define BXE_IOC_STATS_SHOW_NUM 3
1842 #define BXE_IOC_STATS_SHOW_STR 4
1843 #define BXE_IOC_STATS_SHOW_CNT 5
1845 struct bxe_nvram_data {
1846 uint32_t op; /* ioctl sub-command */
1849 uint32_t value[1]; /* variable */
1852 union bxe_stats_show_data {
1853 uint32_t op; /* ioctl sub-command */
1856 uint32_t num; /* return number of stats */
1857 uint32_t len; /* length of each string item */
1860 /* variable length... */
1861 char str[1]; /* holds names of desc.num stats, each desc.len in length */
1863 /* variable length... */
1864 uint64_t stats[1]; /* holds all stats */
1867 /* function init flags */
1868 #define FUNC_FLG_RSS 0x0001
1869 #define FUNC_FLG_STATS 0x0002
1870 /* FUNC_FLG_UNMATCHED 0x0004 */
1871 #define FUNC_FLG_TPA 0x0008
1872 #define FUNC_FLG_SPQ 0x0010
1873 #define FUNC_FLG_LEADING 0x0020 /* PF only */
1875 struct bxe_func_init_params {
1876 bus_addr_t fw_stat_map; /* (dma) valid if FUNC_FLG_STATS */
1877 bus_addr_t spq_map; /* (dma) valid if FUNC_FLG_SPQ */
1879 uint16_t func_id; /* abs function id */
1881 uint16_t spq_prod; /* valid if FUNC_FLG_SPQ */
1884 /* memory resources reside at BARs 0, 2, 4 */
1885 /* Run `pciconf -lb` to see mappings */
1890 #ifdef BXE_REG_NO_INLINE
1892 uint8_t bxe_reg_read8(struct bxe_softc *sc, bus_size_t offset);
1893 uint16_t bxe_reg_read16(struct bxe_softc *sc, bus_size_t offset);
1894 uint32_t bxe_reg_read32(struct bxe_softc *sc, bus_size_t offset);
1896 void bxe_reg_write8(struct bxe_softc *sc, bus_size_t offset, uint8_t val);
1897 void bxe_reg_write16(struct bxe_softc *sc, bus_size_t offset, uint16_t val);
1898 void bxe_reg_write32(struct bxe_softc *sc, bus_size_t offset, uint32_t val);
1900 #define REG_RD8(sc, offset) bxe_reg_read8(sc, offset)
1901 #define REG_RD16(sc, offset) bxe_reg_read16(sc, offset)
1902 #define REG_RD32(sc, offset) bxe_reg_read32(sc, offset)
1904 #define REG_WR8(sc, offset, val) bxe_reg_write8(sc, offset, val)
1905 #define REG_WR16(sc, offset, val) bxe_reg_write16(sc, offset, val)
1906 #define REG_WR32(sc, offset, val) bxe_reg_write32(sc, offset, val)
1908 #else /* not BXE_REG_NO_INLINE */
1910 #define REG_WR8(sc, offset, val) \
1911 bus_space_write_1(sc->bar[BAR0].tag, \
1912 sc->bar[BAR0].handle, \
1915 #define REG_WR16(sc, offset, val) \
1916 bus_space_write_2(sc->bar[BAR0].tag, \
1917 sc->bar[BAR0].handle, \
1920 #define REG_WR32(sc, offset, val) \
1921 bus_space_write_4(sc->bar[BAR0].tag, \
1922 sc->bar[BAR0].handle, \
1925 #define REG_RD8(sc, offset) \
1926 bus_space_read_1(sc->bar[BAR0].tag, \
1927 sc->bar[BAR0].handle, \
1930 #define REG_RD16(sc, offset) \
1931 bus_space_read_2(sc->bar[BAR0].tag, \
1932 sc->bar[BAR0].handle, \
1935 #define REG_RD32(sc, offset) \
1936 bus_space_read_4(sc->bar[BAR0].tag, \
1937 sc->bar[BAR0].handle, \
1940 #endif /* BXE_REG_NO_INLINE */
1942 #define REG_RD(sc, offset) REG_RD32(sc, offset)
1943 #define REG_WR(sc, offset, val) REG_WR32(sc, offset, val)
1945 #define REG_RD_IND(sc, offset) bxe_reg_rd_ind(sc, offset)
1946 #define REG_WR_IND(sc, offset, val) bxe_reg_wr_ind(sc, offset, val)
1948 #define BXE_SP(sc, var) (&(sc)->sp->var)
1949 #define BXE_SP_MAPPING(sc, var) \
1950 (sc->sp_dma.paddr + offsetof(struct bxe_slowpath, var))
1952 #define BXE_FP(sc, nr, var) ((sc)->fp[(nr)].var)
1953 #define BXE_SP_OBJ(sc, fp) ((sc)->sp_objs[(fp)->index])
1956 #define bxe_fp(sc, nr, var) ((sc)->fp[nr].var)
1957 #define bxe_sp_obj(sc, fp) ((sc)->sp_objs[(fp)->index])
1958 #define bxe_fp_stats(sc, fp) (&(sc)->fp_stats[(fp)->index])
1959 #define bxe_fp_qstats(sc, fp) (&(sc)->fp_stats[(fp)->index].eth_q_stats)
1962 #define REG_RD_DMAE(sc, offset, valp, len32) \
1964 bxe_read_dmae(sc, offset, len32); \
1965 memcpy(valp, BXE_SP(sc, wb_data[0]), (len32) * 4); \
1968 #define REG_WR_DMAE(sc, offset, valp, len32) \
1970 memcpy(BXE_SP(sc, wb_data[0]), valp, (len32) * 4); \
1971 bxe_write_dmae(sc, BXE_SP_MAPPING(sc, wb_data), offset, len32); \
1974 #define REG_WR_DMAE_LEN(sc, offset, valp, len32) \
1975 REG_WR_DMAE(sc, offset, valp, len32)
1977 #define REG_RD_DMAE_LEN(sc, offset, valp, len32) \
1978 REG_RD_DMAE(sc, offset, valp, len32)
1980 #define VIRT_WR_DMAE_LEN(sc, data, addr, len32, le32_swap) \
1982 /* if (le32_swap) { */ \
1983 /* BLOGW(sc, "VIRT_WR_DMAE_LEN with le32_swap=1\n"); */ \
1985 memcpy(GUNZIP_BUF(sc), data, len32 * 4); \
1986 ecore_write_big_buf_wb(sc, addr, len32); \
1989 #define BXE_DB_MIN_SHIFT 3 /* 8 bytes */
1990 #define BXE_DB_SHIFT 7 /* 128 bytes */
1991 #if (BXE_DB_SHIFT < BXE_DB_MIN_SHIFT)
1992 #error "Minimum DB doorbell stride is 8"
1994 #define DPM_TRIGGER_TYPE 0x40
1995 #define DOORBELL(sc, cid, val) \
1997 bus_space_write_4(sc->bar[BAR1].tag, sc->bar[BAR1].handle, \
1998 ((sc->doorbell_size * (cid)) + DPM_TRIGGER_TYPE), \
2002 #define SHMEM_ADDR(sc, field) \
2003 (sc->devinfo.shmem_base + offsetof(struct shmem_region, field))
2004 #define SHMEM_RD(sc, field) REG_RD(sc, SHMEM_ADDR(sc, field))
2005 #define SHMEM_RD16(sc, field) REG_RD16(sc, SHMEM_ADDR(sc, field))
2006 #define SHMEM_WR(sc, field, val) REG_WR(sc, SHMEM_ADDR(sc, field), val)
2008 #define SHMEM2_ADDR(sc, field) \
2009 (sc->devinfo.shmem2_base + offsetof(struct shmem2_region, field))
2010 #define SHMEM2_HAS(sc, field) \
2011 (sc->devinfo.shmem2_base && (REG_RD(sc, SHMEM2_ADDR(sc, size)) > \
2012 offsetof(struct shmem2_region, field)))
2013 #define SHMEM2_RD(sc, field) REG_RD(sc, SHMEM2_ADDR(sc, field))
2014 #define SHMEM2_WR(sc, field, val) REG_WR(sc, SHMEM2_ADDR(sc, field), val)
2016 #define MFCFG_ADDR(sc, field) \
2017 (sc->devinfo.mf_cfg_base + offsetof(struct mf_cfg, field))
2018 #define MFCFG_RD(sc, field) REG_RD(sc, MFCFG_ADDR(sc, field))
2019 #define MFCFG_RD16(sc, field) REG_RD16(sc, MFCFG_ADDR(sc, field))
2020 #define MFCFG_WR(sc, field, val) REG_WR(sc, MFCFG_ADDR(sc, field), val)
2022 /* DMAE command defines */
2024 #define DMAE_TIMEOUT -1
2025 #define DMAE_PCI_ERROR -2 /* E2 and onward */
2026 #define DMAE_NOT_RDY -3
2027 #define DMAE_PCI_ERR_FLAG 0x80000000
2029 #define DMAE_SRC_PCI 0
2030 #define DMAE_SRC_GRC 1
2032 #define DMAE_DST_NONE 0
2033 #define DMAE_DST_PCI 1
2034 #define DMAE_DST_GRC 2
2036 #define DMAE_COMP_PCI 0
2037 #define DMAE_COMP_GRC 1
2039 #define DMAE_COMP_REGULAR 0
2040 #define DMAE_COM_SET_ERR 1
2042 #define DMAE_CMD_SRC_PCI (DMAE_SRC_PCI << DMAE_COMMAND_SRC_SHIFT)
2043 #define DMAE_CMD_SRC_GRC (DMAE_SRC_GRC << DMAE_COMMAND_SRC_SHIFT)
2044 #define DMAE_CMD_DST_PCI (DMAE_DST_PCI << DMAE_COMMAND_DST_SHIFT)
2045 #define DMAE_CMD_DST_GRC (DMAE_DST_GRC << DMAE_COMMAND_DST_SHIFT)
2047 #define DMAE_CMD_C_DST_PCI (DMAE_COMP_PCI << DMAE_COMMAND_C_DST_SHIFT)
2048 #define DMAE_CMD_C_DST_GRC (DMAE_COMP_GRC << DMAE_COMMAND_C_DST_SHIFT)
2050 #define DMAE_CMD_ENDIANITY_NO_SWAP (0 << DMAE_COMMAND_ENDIANITY_SHIFT)
2051 #define DMAE_CMD_ENDIANITY_B_SWAP (1 << DMAE_COMMAND_ENDIANITY_SHIFT)
2052 #define DMAE_CMD_ENDIANITY_DW_SWAP (2 << DMAE_COMMAND_ENDIANITY_SHIFT)
2053 #define DMAE_CMD_ENDIANITY_B_DW_SWAP (3 << DMAE_COMMAND_ENDIANITY_SHIFT)
2055 #define DMAE_CMD_PORT_0 0
2056 #define DMAE_CMD_PORT_1 DMAE_COMMAND_PORT
2058 #define DMAE_SRC_PF 0
2059 #define DMAE_SRC_VF 1
2061 #define DMAE_DST_PF 0
2062 #define DMAE_DST_VF 1
2064 #define DMAE_C_SRC 0
2065 #define DMAE_C_DST 1
2067 #define DMAE_LEN32_RD_MAX 0x80
2068 #define DMAE_LEN32_WR_MAX(sc) (CHIP_IS_E1(sc) ? 0x400 : 0x2000)
2070 #define DMAE_COMP_VAL 0x60d0d0ae /* E2 and beyond, upper bit indicates error */
2072 #define MAX_DMAE_C_PER_PORT 8
2073 #define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
2074 #define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
2076 static const uint32_t dmae_reg_go_c[] = {
2077 DMAE_REG_GO_C0, DMAE_REG_GO_C1, DMAE_REG_GO_C2, DMAE_REG_GO_C3,
2078 DMAE_REG_GO_C4, DMAE_REG_GO_C5, DMAE_REG_GO_C6, DMAE_REG_GO_C7,
2079 DMAE_REG_GO_C8, DMAE_REG_GO_C9, DMAE_REG_GO_C10, DMAE_REG_GO_C11,
2080 DMAE_REG_GO_C12, DMAE_REG_GO_C13, DMAE_REG_GO_C14, DMAE_REG_GO_C15
2083 #define ATTN_NIG_FOR_FUNC (1L << 8)
2084 #define ATTN_SW_TIMER_4_FUNC (1L << 9)
2085 #define GPIO_2_FUNC (1L << 10)
2086 #define GPIO_3_FUNC (1L << 11)
2087 #define GPIO_4_FUNC (1L << 12)
2088 #define ATTN_GENERAL_ATTN_1 (1L << 13)
2089 #define ATTN_GENERAL_ATTN_2 (1L << 14)
2090 #define ATTN_GENERAL_ATTN_3 (1L << 15)
2091 #define ATTN_GENERAL_ATTN_4 (1L << 13)
2092 #define ATTN_GENERAL_ATTN_5 (1L << 14)
2093 #define ATTN_GENERAL_ATTN_6 (1L << 15)
2094 #define ATTN_HARD_WIRED_MASK 0xff00
2095 #define ATTENTION_ID 4
2097 #define AEU_IN_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR \
2098 AEU_INPUTS_ATTN_BITS_PXPPCICLOCKCLIENT_PARITY_ERROR
2100 #define MAX_IGU_ATTN_ACK_TO 100
2102 #define STORM_ASSERT_ARRAY_SIZE 50
2104 #define BXE_PMF_LINK_ASSERT(sc) \
2105 GENERAL_ATTEN_OFFSET(LINK_SYNC_ATTENTION_BIT_FUNC_0 + SC_FUNC(sc))
2107 #define BXE_MC_ASSERT_BITS \
2108 (GENERAL_ATTEN_OFFSET(TSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2109 GENERAL_ATTEN_OFFSET(USTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2110 GENERAL_ATTEN_OFFSET(CSTORM_FATAL_ASSERT_ATTENTION_BIT) | \
2111 GENERAL_ATTEN_OFFSET(XSTORM_FATAL_ASSERT_ATTENTION_BIT))
2113 #define BXE_MCP_ASSERT \
2114 GENERAL_ATTEN_OFFSET(MCP_FATAL_ASSERT_ATTENTION_BIT)
2116 #define BXE_GRC_TIMEOUT GENERAL_ATTEN_OFFSET(LATCHED_ATTN_TIMEOUT_GRC)
2117 #define BXE_GRC_RSV (GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCR) | \
2118 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCT) | \
2119 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCN) | \
2120 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCU) | \
2121 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RBCP) | \
2122 GENERAL_ATTEN_OFFSET(LATCHED_ATTN_RSVD_GRC))
2124 #define MULTI_MASK 0x7f
2126 #define PFS_PER_PORT(sc) \
2127 ((CHIP_PORT_MODE(sc) == CHIP_4_PORT_MODE) ? 2 : 4)
2128 #define SC_MAX_VN_NUM(sc) PFS_PER_PORT(sc)
2130 #define FIRST_ABS_FUNC_IN_PORT(sc) \
2131 ((CHIP_PORT_MODE(sc) == CHIP_PORT_MODE_NONE) ? \
2132 PORT_ID(sc) : (PATH_ID(sc) + (2 * PORT_ID(sc))))
2134 #define FOREACH_ABS_FUNC_IN_PORT(sc, i) \
2135 for ((i) = FIRST_ABS_FUNC_IN_PORT(sc); \
2136 (i) < MAX_FUNC_NUM; \
2137 (i) += (MAX_FUNC_NUM / PFS_PER_PORT(sc)))
2139 #define BXE_SWCID_SHIFT 17
2140 #define BXE_SWCID_MASK ((0x1 << BXE_SWCID_SHIFT) - 1)
2142 #define SW_CID(x) (le32toh(x) & BXE_SWCID_MASK)
2143 #define CQE_CMD(x) (le32toh(x) >> COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT)
2145 #define CQE_TYPE(cqe_fp_flags) ((cqe_fp_flags) & ETH_FAST_PATH_RX_CQE_TYPE)
2146 #define CQE_TYPE_START(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_START_AGG)
2147 #define CQE_TYPE_STOP(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_STOP_AGG)
2148 #define CQE_TYPE_SLOW(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_RAMROD)
2149 #define CQE_TYPE_FAST(cqe_type) ((cqe_type) == RX_ETH_CQE_TYPE_ETH_FASTPATH)
2151 /* must be used on a CID before placing it on a HW ring */
2152 #define HW_CID(sc, x) \
2153 ((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x))
2156 #define SPEED_100 100
2157 #define SPEED_1000 1000
2158 #define SPEED_2500 2500
2159 #define SPEED_10000 10000
2162 #define PCI_PM_D3hot 2
2164 int bxe_test_bit(int nr, volatile unsigned long * addr);
2165 void bxe_set_bit(unsigned int nr, volatile unsigned long * addr);
2166 void bxe_clear_bit(int nr, volatile unsigned long * addr);
2167 int bxe_test_and_set_bit(int nr, volatile unsigned long * addr);
2168 int bxe_test_and_clear_bit(int nr, volatile unsigned long * addr);
2169 int bxe_cmpxchg(volatile int *addr, int old, int new);
2171 void bxe_reg_wr_ind(struct bxe_softc *sc, uint32_t addr,
2173 uint32_t bxe_reg_rd_ind(struct bxe_softc *sc, uint32_t addr);
2176 int bxe_dma_alloc(struct bxe_softc *sc, bus_size_t size,
2177 struct bxe_dma *dma, const char *msg);
2178 void bxe_dma_free(struct bxe_softc *sc, struct bxe_dma *dma);
2180 uint32_t bxe_dmae_opcode_add_comp(uint32_t opcode, uint8_t comp_type);
2181 uint32_t bxe_dmae_opcode_clr_src_reset(uint32_t opcode);
2182 uint32_t bxe_dmae_opcode(struct bxe_softc *sc, uint8_t src_type,
2183 uint8_t dst_type, uint8_t with_comp,
2185 void bxe_post_dmae(struct bxe_softc *sc, struct dmae_command *dmae, int idx);
2186 void bxe_read_dmae(struct bxe_softc *sc, uint32_t src_addr, uint32_t len32);
2187 void bxe_write_dmae(struct bxe_softc *sc, bus_addr_t dma_addr,
2188 uint32_t dst_addr, uint32_t len32);
2189 void bxe_write_dmae_phys_len(struct bxe_softc *sc, bus_addr_t phys_addr,
2190 uint32_t addr, uint32_t len);
2192 void bxe_set_ctx_validation(struct bxe_softc *sc, struct eth_context *cxt,
2194 void bxe_update_coalesce_sb_index(struct bxe_softc *sc, uint8_t fw_sb_id,
2195 uint8_t sb_index, uint8_t disable,
2198 int bxe_sp_post(struct bxe_softc *sc, int command, int cid,
2199 uint32_t data_hi, uint32_t data_lo, int cmd_type);
2201 void bxe_igu_ack_sb(struct bxe_softc *sc, uint8_t igu_sb_id,
2202 uint8_t segment, uint16_t index, uint8_t op,
2205 void ecore_init_e1_firmware(struct bxe_softc *sc);
2206 void ecore_init_e1h_firmware(struct bxe_softc *sc);
2207 void ecore_init_e2_firmware(struct bxe_softc *sc);
2209 void ecore_storm_memset_struct(struct bxe_softc *sc, uint32_t addr,
2210 size_t size, uint32_t *data);
2212 /*********************/
2213 /* LOGGING AND DEBUG */
2214 /*********************/
2216 /* debug logging codepaths */
2217 #define DBG_LOAD 0x00000001 /* load and unload */
2218 #define DBG_INTR 0x00000002 /* interrupt handling */
2219 #define DBG_SP 0x00000004 /* slowpath handling */
2220 #define DBG_STATS 0x00000008 /* stats updates */
2221 #define DBG_TX 0x00000010 /* packet transmit */
2222 #define DBG_RX 0x00000020 /* packet receive */
2223 #define DBG_PHY 0x00000040 /* phy/link handling */
2224 #define DBG_IOCTL 0x00000080 /* ioctl handling */
2225 #define DBG_MBUF 0x00000100 /* dumping mbuf info */
2226 #define DBG_REGS 0x00000200 /* register access */
2227 #define DBG_LRO 0x00000400 /* lro processing */
2228 #define DBG_ASSERT 0x80000000 /* debug assert */
2229 #define DBG_ALL 0xFFFFFFFF /* flying monkeys */
2231 #define DBASSERT(sc, exp, msg) \
2233 if (__predict_false(sc->debug & DBG_ASSERT)) { \
2234 if (__predict_false(!(exp))) { \
2240 /* log a debug message */
2241 #define BLOGD(sc, codepath, format, args...) \
2243 if (__predict_false(sc->debug & (codepath))) { \
2244 device_printf((sc)->dev, \
2245 "%s(%s:%d) " format, \
2253 /* log a info message */
2254 #define BLOGI(sc, format, args...) \
2256 if (__predict_false(sc->debug)) { \
2257 device_printf((sc)->dev, \
2258 "%s(%s:%d) " format, \
2264 device_printf((sc)->dev, \
2270 /* log a warning message */
2271 #define BLOGW(sc, format, args...) \
2273 if (__predict_false(sc->debug)) { \
2274 device_printf((sc)->dev, \
2275 "%s(%s:%d) WARNING: " format, \
2281 device_printf((sc)->dev, \
2282 "WARNING: " format, \
2287 /* log a error message */
2288 #define BLOGE(sc, format, args...) \
2290 if (__predict_false(sc->debug)) { \
2291 device_printf((sc)->dev, \
2292 "%s(%s:%d) ERROR: " format, \
2298 device_printf((sc)->dev, \
2304 #ifdef ECORE_STOP_ON_ERROR
2306 #define bxe_panic(sc, msg) \
2313 #define bxe_panic(sc, msg) \
2314 device_printf((sc)->dev, "%s (%s,%d)\n", __FUNCTION__, __FILE__, __LINE__);
2318 #define CATC_TRIGGER(sc, data) REG_WR((sc), 0x2000, (data));
2319 #define CATC_TRIGGER_START(sc) CATC_TRIGGER((sc), 0xcafecafe)
2321 void bxe_dump_mem(struct bxe_softc *sc, char *tag,
2322 uint8_t *mem, uint32_t len);
2323 void bxe_dump_mbuf_data(struct bxe_softc *sc, char *pTag,
2324 struct mbuf *m, uint8_t contents);
2330 static inline uint32_t
2331 reg_poll(struct bxe_softc *sc,
2340 val = REG_RD(sc, reg);
2341 if (val == expected) {
2352 bxe_update_fp_sb_idx(struct bxe_fastpath *fp)
2354 mb(); /* status block is written to by the chip */
2355 fp->fp_hc_idx = fp->sb_running_index[SM_RX_ID];
2359 bxe_igu_ack_sb_gen(struct bxe_softc *sc,
2367 struct igu_regular cmd_data = {0};
2369 cmd_data.sb_id_and_flags =
2370 ((index << IGU_REGULAR_SB_INDEX_SHIFT) |
2371 (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
2372 (update << IGU_REGULAR_BUPDATE_SHIFT) |
2373 (op << IGU_REGULAR_ENABLE_INT_SHIFT));
2375 BLOGD(sc, DBG_INTR, "write 0x%08x to IGU addr 0x%x\n",
2376 cmd_data.sb_id_and_flags, igu_addr);
2377 REG_WR(sc, igu_addr, cmd_data.sb_id_and_flags);
2379 /* Make sure that ACK is written */
2380 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0,
2381 BUS_SPACE_BARRIER_WRITE);
2386 bxe_hc_ack_sb(struct bxe_softc *sc,
2393 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 +
2394 COMMAND_REG_INT_ACK);
2395 struct igu_ack_register igu_ack;
2397 igu_ack.status_block_index = index;
2398 igu_ack.sb_id_and_flags =
2399 ((sb_id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
2400 (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
2401 (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
2402 (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
2404 REG_WR(sc, hc_addr, (*(uint32_t *)&igu_ack));
2406 /* Make sure that ACK is written */
2407 bus_space_barrier(sc->bar[0].tag, sc->bar[0].handle, 0, 0,
2408 BUS_SPACE_BARRIER_WRITE);
2413 bxe_ack_sb(struct bxe_softc *sc,
2420 if (sc->devinfo.int_block == INT_BLOCK_HC)
2421 bxe_hc_ack_sb(sc, igu_sb_id, storm, index, op, update);
2424 if (CHIP_INT_MODE_IS_BC(sc)) {
2426 } else if (igu_sb_id != sc->igu_dsb_id) {
2427 segment = IGU_SEG_ACCESS_DEF;
2428 } else if (storm == ATTENTION_ID) {
2429 segment = IGU_SEG_ACCESS_ATTN;
2431 segment = IGU_SEG_ACCESS_DEF;
2433 bxe_igu_ack_sb(sc, igu_sb_id, segment, index, op, update);
2437 static inline uint16_t
2438 bxe_hc_ack_int(struct bxe_softc *sc)
2440 uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 +
2441 COMMAND_REG_SIMD_MASK);
2442 uint32_t result = REG_RD(sc, hc_addr);
2448 static inline uint16_t
2449 bxe_igu_ack_int(struct bxe_softc *sc)
2451 uint32_t igu_addr = (BAR_IGU_INTMEM + IGU_REG_SISR_MDPC_WMASK_LSB_UPPER*8);
2452 uint32_t result = REG_RD(sc, igu_addr);
2454 BLOGD(sc, DBG_INTR, "read 0x%08x from IGU addr 0x%x\n",
2461 static inline uint16_t
2462 bxe_ack_int(struct bxe_softc *sc)
2465 if (sc->devinfo.int_block == INT_BLOCK_HC) {
2466 return (bxe_hc_ack_int(sc));
2468 return (bxe_igu_ack_int(sc));
2473 func_by_vn(struct bxe_softc *sc,
2476 return (2 * vn + SC_PORT(sc));
2480 * Statistics ID are global per chip/path, while Client IDs for E1x
2483 static inline uint8_t
2484 bxe_stats_id(struct bxe_fastpath *fp)
2486 struct bxe_softc *sc = fp->sc;
2488 if (!CHIP_IS_E1x(sc)) {
2490 /* there are special statistics counters for FCoE 136..140 */
2491 if (IS_FCOE_FP(fp)) {
2492 return (sc->cnic_base_cl_id + (sc->pf_num >> 1));
2498 return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x);
2501 #endif /* __BXE_H__ */