2 * Copyright (c) 2007-2017 QLogic Corporation. All rights reserved.
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
18 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
19 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
20 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
21 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
22 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
23 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
24 * THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include "bxe_elink.h"
32 #include "ecore_mfw_req.h"
33 #include "ecore_fw_defs.h"
34 #include "ecore_hsi.h"
35 #include "ecore_reg.h"
38 #define MDIO_REG_BANK_CL73_IEEEB0 0x0
39 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL 0x0
40 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN 0x0200
41 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN 0x1000
42 #define MDIO_CL73_IEEEB0_CL73_AN_CONTROL_MAIN_RST 0x8000
44 #define MDIO_REG_BANK_CL73_IEEEB1 0x10
45 #define MDIO_CL73_IEEEB1_AN_ADV1 0x00
46 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE 0x0400
47 #define MDIO_CL73_IEEEB1_AN_ADV1_ASYMMETRIC 0x0800
48 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH 0x0C00
49 #define MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK 0x0C00
50 #define MDIO_CL73_IEEEB1_AN_ADV2 0x01
51 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M 0x0000
52 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX 0x0020
53 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 0x0040
54 #define MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR 0x0080
55 #define MDIO_CL73_IEEEB1_AN_LP_ADV1 0x03
56 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE 0x0400
57 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_ASYMMETRIC 0x0800
58 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_BOTH 0x0C00
59 #define MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK 0x0C00
60 #define MDIO_CL73_IEEEB1_AN_LP_ADV2 0x04
62 #define MDIO_REG_BANK_RX0 0x80b0
63 #define MDIO_RX0_RX_STATUS 0x10
64 #define MDIO_RX0_RX_STATUS_SIGDET 0x8000
65 #define MDIO_RX0_RX_STATUS_RX_SEQ_DONE 0x1000
66 #define MDIO_RX0_RX_EQ_BOOST 0x1c
67 #define MDIO_RX0_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
68 #define MDIO_RX0_RX_EQ_BOOST_OFFSET_CTRL 0x10
70 #define MDIO_REG_BANK_RX1 0x80c0
71 #define MDIO_RX1_RX_EQ_BOOST 0x1c
72 #define MDIO_RX1_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
73 #define MDIO_RX1_RX_EQ_BOOST_OFFSET_CTRL 0x10
75 #define MDIO_REG_BANK_RX2 0x80d0
76 #define MDIO_RX2_RX_EQ_BOOST 0x1c
77 #define MDIO_RX2_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
78 #define MDIO_RX2_RX_EQ_BOOST_OFFSET_CTRL 0x10
80 #define MDIO_REG_BANK_RX3 0x80e0
81 #define MDIO_RX3_RX_EQ_BOOST 0x1c
82 #define MDIO_RX3_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
83 #define MDIO_RX3_RX_EQ_BOOST_OFFSET_CTRL 0x10
85 #define MDIO_REG_BANK_RX_ALL 0x80f0
86 #define MDIO_RX_ALL_RX_EQ_BOOST 0x1c
87 #define MDIO_RX_ALL_RX_EQ_BOOST_EQUALIZER_CTRL_MASK 0x7
88 #define MDIO_RX_ALL_RX_EQ_BOOST_OFFSET_CTRL 0x10
90 #define MDIO_REG_BANK_TX0 0x8060
91 #define MDIO_TX0_TX_DRIVER 0x17
92 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
93 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
94 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
95 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
96 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
97 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
98 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
99 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
100 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
102 #define MDIO_REG_BANK_TX1 0x8070
103 #define MDIO_TX1_TX_DRIVER 0x17
104 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
105 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
106 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
107 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
108 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
109 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
110 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
111 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
112 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
114 #define MDIO_REG_BANK_TX2 0x8080
115 #define MDIO_TX2_TX_DRIVER 0x17
116 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
117 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
118 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
119 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
120 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
121 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
122 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
123 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
124 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
126 #define MDIO_REG_BANK_TX3 0x8090
127 #define MDIO_TX3_TX_DRIVER 0x17
128 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK 0xf000
129 #define MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT 12
130 #define MDIO_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
131 #define MDIO_TX0_TX_DRIVER_IDRIVER_SHIFT 8
132 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_MASK 0x00f0
133 #define MDIO_TX0_TX_DRIVER_IPREDRIVER_SHIFT 4
134 #define MDIO_TX0_TX_DRIVER_IFULLSPD_MASK 0x000e
135 #define MDIO_TX0_TX_DRIVER_IFULLSPD_SHIFT 1
136 #define MDIO_TX0_TX_DRIVER_ICBUF1T 1
138 #define MDIO_REG_BANK_XGXS_BLOCK0 0x8000
139 #define MDIO_BLOCK0_XGXS_CONTROL 0x10
141 #define MDIO_REG_BANK_XGXS_BLOCK1 0x8010
142 #define MDIO_BLOCK1_LANE_CTRL0 0x15
143 #define MDIO_BLOCK1_LANE_CTRL1 0x16
144 #define MDIO_BLOCK1_LANE_CTRL2 0x17
145 #define MDIO_BLOCK1_LANE_PRBS 0x19
147 #define MDIO_REG_BANK_XGXS_BLOCK2 0x8100
148 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP 0x10
149 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE 0x8000
150 #define MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE 0x4000
151 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP 0x11
152 #define MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE 0x8000
153 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G 0x14
154 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS 0x0001
155 #define MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS 0x0010
156 #define MDIO_XGXS_BLOCK2_TEST_MODE_LANE 0x15
158 #define MDIO_REG_BANK_GP_STATUS 0x8120
159 #define MDIO_GP_STATUS_TOP_AN_STATUS1 0x1B
160 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE 0x0001
161 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE 0x0002
162 #define MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS 0x0004
163 #define MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS 0x0008
164 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE 0x0010
165 #define MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_LP_NP_BAM_ABLE 0x0020
166 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE 0x0040
167 #define MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE 0x0080
168 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK 0x3f00
169 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M 0x0000
170 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M 0x0100
171 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G 0x0200
172 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G 0x0300
173 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G 0x0400
174 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G 0x0500
175 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG 0x0600
176 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4 0x0700
177 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12G_HIG 0x0800
178 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_12_5G 0x0900
179 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_13G 0x0A00
180 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_15G 0x0B00
181 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_16G 0x0C00
182 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX 0x0D00
183 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4 0x0E00
184 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR 0x0F00
185 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI 0x1B00
186 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS 0x1E00
187 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI 0x1F00
188 #define MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2 0x3900
191 #define MDIO_REG_BANK_10G_PARALLEL_DETECT 0x8130
192 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS 0x10
193 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK 0x8000
194 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL 0x11
195 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN 0x1
196 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK 0x13
197 #define MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT (0xb71<<1)
199 #define MDIO_REG_BANK_SERDES_DIGITAL 0x8300
200 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1 0x10
201 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE 0x0001
202 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_TBI_IF 0x0002
203 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN 0x0004
204 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT 0x0008
205 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET 0x0010
206 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE 0x0020
207 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2 0x11
208 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN 0x0001
209 #define MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_AN_FST_TMR 0x0040
210 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1 0x14
211 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SGMII 0x0001
212 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_LINK 0x0002
213 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_DUPLEX 0x0004
214 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_MASK 0x0018
215 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_SHIFT 3
216 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_2_5G 0x0018
217 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_1G 0x0010
218 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_100M 0x0008
219 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS1_SPEED_10M 0x0000
220 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2 0x15
221 #define MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED 0x0002
222 #define MDIO_SERDES_DIGITAL_MISC1 0x18
223 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_MASK 0xE000
224 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_25M 0x0000
225 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_100M 0x2000
226 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_125M 0x4000
227 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M 0x6000
228 #define MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_187_5M 0x8000
229 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL 0x0010
230 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK 0x000f
231 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_2_5G 0x0000
232 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_5G 0x0001
233 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_6G 0x0002
234 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_HIG 0x0003
235 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4 0x0004
236 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12G 0x0005
237 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_12_5G 0x0006
238 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_13G 0x0007
239 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_15G 0x0008
240 #define MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_16G 0x0009
242 #define MDIO_REG_BANK_OVER_1G 0x8320
243 #define MDIO_OVER_1G_DIGCTL_3_4 0x14
244 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_MASK 0xffe0
245 #define MDIO_OVER_1G_DIGCTL_3_4_MP_ID_SHIFT 5
246 #define MDIO_OVER_1G_UP1 0x19
247 #define MDIO_OVER_1G_UP1_2_5G 0x0001
248 #define MDIO_OVER_1G_UP1_5G 0x0002
249 #define MDIO_OVER_1G_UP1_6G 0x0004
250 #define MDIO_OVER_1G_UP1_10G 0x0010
251 #define MDIO_OVER_1G_UP1_10GH 0x0008
252 #define MDIO_OVER_1G_UP1_12G 0x0020
253 #define MDIO_OVER_1G_UP1_12_5G 0x0040
254 #define MDIO_OVER_1G_UP1_13G 0x0080
255 #define MDIO_OVER_1G_UP1_15G 0x0100
256 #define MDIO_OVER_1G_UP1_16G 0x0200
257 #define MDIO_OVER_1G_UP2 0x1A
258 #define MDIO_OVER_1G_UP2_IPREDRIVER_MASK 0x0007
259 #define MDIO_OVER_1G_UP2_IDRIVER_MASK 0x0038
260 #define MDIO_OVER_1G_UP2_PREEMPHASIS_MASK 0x03C0
261 #define MDIO_OVER_1G_UP3 0x1B
262 #define MDIO_OVER_1G_UP3_HIGIG2 0x0001
263 #define MDIO_OVER_1G_LP_UP1 0x1C
264 #define MDIO_OVER_1G_LP_UP2 0x1D
265 #define MDIO_OVER_1G_LP_UP2_MR_ADV_OVER_1G_MASK 0x03ff
266 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK 0x0780
267 #define MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT 7
268 #define MDIO_OVER_1G_LP_UP3 0x1E
270 #define MDIO_REG_BANK_REMOTE_PHY 0x8330
271 #define MDIO_REMOTE_PHY_MISC_RX_STATUS 0x10
272 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG 0x0010
273 #define MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG 0x0600
275 #define MDIO_REG_BANK_BAM_NEXT_PAGE 0x8350
276 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL 0x10
277 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE 0x0001
278 #define MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN 0x0002
280 #define MDIO_REG_BANK_CL73_USERB0 0x8370
281 #define MDIO_CL73_USERB0_CL73_UCTRL 0x10
282 #define MDIO_CL73_USERB0_CL73_UCTRL_USTAT1_MUXSEL 0x0002
283 #define MDIO_CL73_USERB0_CL73_USTAT1 0x11
284 #define MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK 0x0100
285 #define MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37 0x0400
286 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1 0x12
287 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN 0x8000
288 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN 0x4000
289 #define MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN 0x2000
290 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3 0x14
291 #define MDIO_CL73_USERB0_CL73_BAM_CTRL3_USE_CL73_HCD_MR 0x0001
293 #define MDIO_REG_BANK_AER_BLOCK 0xFFD0
294 #define MDIO_AER_BLOCK_AER_REG 0x1E
296 #define MDIO_REG_BANK_COMBO_IEEE0 0xFFE0
297 #define MDIO_COMBO_IEEE0_MII_CONTROL 0x10
298 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK 0x2040
299 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_10 0x0000
300 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100 0x2000
301 #define MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000 0x0040
302 #define MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX 0x0100
303 #define MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN 0x0200
304 #define MDIO_COMBO_IEEO_MII_CONTROL_AN_EN 0x1000
305 #define MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK 0x4000
306 #define MDIO_COMBO_IEEO_MII_CONTROL_RESET 0x8000
307 #define MDIO_COMBO_IEEE0_MII_STATUS 0x11
308 #define MDIO_COMBO_IEEE0_MII_STATUS_LINK_PASS 0x0004
309 #define MDIO_COMBO_IEEE0_MII_STATUS_AUTONEG_COMPLETE 0x0020
310 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV 0x14
311 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX 0x0020
312 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_HALF_DUPLEX 0x0040
313 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK 0x0180
314 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE 0x0000
315 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC 0x0080
316 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC 0x0100
317 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH 0x0180
318 #define MDIO_COMBO_IEEE0_AUTO_NEG_ADV_NEXT_PAGE 0x8000
319 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1 0x15
320 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_NEXT_PAGE 0x8000
321 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_ACK 0x4000
322 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_MASK 0x0180
323 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_NONE 0x0000
324 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_PAUSE_BOTH 0x0180
325 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_HALF_DUP_CAP 0x0040
326 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_FULL_DUP_CAP 0x0020
327 /*WhenthelinkpartnerisinSGMIImode(bit0=1),then
328 bit15=link,bit12=duplex,bits11:10=speed,bit14=acknowledge.
329 Theotherbitsarereservedandshouldbezero*/
330 #define MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1_SGMII_MODE 0x0001
333 #define MDIO_PMA_DEVAD 0x1
335 #define MDIO_PMA_REG_CTRL 0x0
336 #define MDIO_PMA_REG_STATUS 0x1
337 #define MDIO_PMA_REG_10G_CTRL2 0x7
338 #define MDIO_PMA_REG_TX_DISABLE 0x0009
339 #define MDIO_PMA_REG_RX_SD 0xa
341 #define MDIO_PMA_REG_BCM_CTRL 0x0096
342 #define MDIO_PMA_REG_FEC_CTRL 0x00ab
343 #define MDIO_PMA_LASI_RXCTRL 0x9000
344 #define MDIO_PMA_LASI_TXCTRL 0x9001
345 #define MDIO_PMA_LASI_CTRL 0x9002
346 #define MDIO_PMA_LASI_RXSTAT 0x9003
347 #define MDIO_PMA_LASI_TXSTAT 0x9004
348 #define MDIO_PMA_LASI_STAT 0x9005
349 #define MDIO_PMA_REG_PHY_IDENTIFIER 0xc800
350 #define MDIO_PMA_REG_DIGITAL_CTRL 0xc808
351 #define MDIO_PMA_REG_DIGITAL_STATUS 0xc809
352 #define MDIO_PMA_REG_TX_POWER_DOWN 0xca02
353 #define MDIO_PMA_REG_CMU_PLL_BYPASS 0xca09
354 #define MDIO_PMA_REG_MISC_CTRL 0xca0a
355 #define MDIO_PMA_REG_GEN_CTRL 0xca10
356 #define MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP 0x0188
357 #define MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET 0x018a
358 #define MDIO_PMA_REG_M8051_MSGIN_REG 0xca12
359 #define MDIO_PMA_REG_M8051_MSGOUT_REG 0xca13
360 #define MDIO_PMA_REG_ROM_VER1 0xca19
361 #define MDIO_PMA_REG_ROM_VER2 0xca1a
362 #define MDIO_PMA_REG_EDC_FFE_MAIN 0xca1b
363 #define MDIO_PMA_REG_PLL_BANDWIDTH 0xca1d
364 #define MDIO_PMA_REG_PLL_CTRL 0xca1e
365 #define MDIO_PMA_REG_MISC_CTRL0 0xca23
366 #define MDIO_PMA_REG_LRM_MODE 0xca3f
367 #define MDIO_PMA_REG_CDR_BANDWIDTH 0xca46
368 #define MDIO_PMA_REG_MISC_CTRL1 0xca85
370 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL 0x8000
371 #define MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK 0x000c
372 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE 0x0000
373 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE 0x0004
374 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IN_PROGRESS 0x0008
375 #define MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_FAILED 0x000c
376 #define MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT 0x8002
377 #define MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR 0x8003
378 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF 0xc820
379 #define MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK 0xff
380 #define MDIO_PMA_REG_8726_TX_CTRL1 0xca01
381 #define MDIO_PMA_REG_8726_TX_CTRL2 0xca05
383 #define MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR 0x8005
384 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF 0x8007
385 #define MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK 0xff
386 #define MDIO_PMA_REG_8727_MISC_CTRL 0x8309
387 #define MDIO_PMA_REG_8727_TX_CTRL1 0xca02
388 #define MDIO_PMA_REG_8727_TX_CTRL2 0xca05
389 #define MDIO_PMA_REG_8727_PCS_OPT_CTRL 0xc808
390 #define MDIO_PMA_REG_8727_GPIO_CTRL 0xc80e
391 #define MDIO_PMA_REG_8727_PCS_GP 0xc842
392 #define MDIO_PMA_REG_8727_OPT_CFG_REG 0xc8e4
394 #define MDIO_AN_REG_8727_MISC_CTRL 0x8309
395 #define MDIO_PMA_REG_8073_CHIP_REV 0xc801
396 #define MDIO_PMA_REG_8073_SPEED_LINK_STATUS 0xc820
397 #define MDIO_PMA_REG_8073_XAUI_WA 0xc841
398 #define MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL 0xcd08
400 #define MDIO_PMA_REG_7101_RESET 0xc000
401 #define MDIO_PMA_REG_7107_LED_CNTL 0xc007
402 #define MDIO_PMA_REG_7107_LINK_LED_CNTL 0xc009
403 #define MDIO_PMA_REG_7101_VER1 0xc026
404 #define MDIO_PMA_REG_7101_VER2 0xc027
406 #define MDIO_PMA_REG_8481_PMD_SIGNAL 0xa811
407 #define MDIO_PMA_REG_8481_LED1_MASK 0xa82c
408 #define MDIO_PMA_REG_8481_LED2_MASK 0xa82f
409 #define MDIO_PMA_REG_8481_LED3_MASK 0xa832
410 #define MDIO_PMA_REG_8481_LED3_BLINK 0xa834
411 #define MDIO_PMA_REG_8481_LED5_MASK 0xa838
412 #define MDIO_PMA_REG_8481_SIGNAL_MASK 0xa835
413 #define MDIO_PMA_REG_8481_LINK_SIGNAL 0xa83b
414 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK 0x800
415 #define MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT 11
419 #define MDIO_WIS_DEVAD 0x2
421 #define MDIO_WIS_REG_LASI_CNTL 0x9002
422 #define MDIO_WIS_REG_LASI_STATUS 0x9005
424 #define MDIO_PCS_DEVAD 0x3
425 #define MDIO_PCS_REG_STATUS 0x0020
426 #define MDIO_PCS_REG_LASI_STATUS 0x9005
427 #define MDIO_PCS_REG_7101_DSP_ACCESS 0xD000
428 #define MDIO_PCS_REG_7101_SPI_MUX 0xD008
429 #define MDIO_PCS_REG_7101_SPI_CTRL_ADDR 0xE12A
430 #define MDIO_PCS_REG_7101_SPI_RESET_BIT (5)
431 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR 0xE02A
432 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_WRITE_ENABLE_CMD (6)
433 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_BULK_ERASE_CMD (0xC7)
434 #define MDIO_PCS_REG_7101_SPI_FIFO_ADDR_PAGE_PROGRAM_CMD (2)
435 #define MDIO_PCS_REG_7101_SPI_BYTES_TO_TRANSFER_ADDR 0xE028
439 #define MDIO_XS_DEVAD 0x4
440 #define MDIO_XS_REG_STATUS 0x0001
441 #define MDIO_XS_PLL_SEQUENCER 0x8000
442 #define MDIO_XS_SFX7101_XGXS_TEST1 0xc00a
444 #define MDIO_XS_8706_REG_BANK_RX0 0x80bc
445 #define MDIO_XS_8706_REG_BANK_RX1 0x80cc
446 #define MDIO_XS_8706_REG_BANK_RX2 0x80dc
447 #define MDIO_XS_8706_REG_BANK_RX3 0x80ec
448 #define MDIO_XS_8706_REG_BANK_RXA 0x80fc
450 #define MDIO_XS_REG_8073_RX_CTRL_PCIE 0x80FA
452 #define MDIO_AN_DEVAD 0x7
454 #define MDIO_AN_REG_CTRL 0x0000
455 #define MDIO_AN_REG_STATUS 0x0001
456 #define MDIO_AN_REG_STATUS_AN_COMPLETE 0x0020
457 #define MDIO_AN_REG_ADV_PAUSE 0x0010
458 #define MDIO_AN_REG_ADV_PAUSE_PAUSE 0x0400
459 #define MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC 0x0800
460 #define MDIO_AN_REG_ADV_PAUSE_BOTH 0x0C00
461 #define MDIO_AN_REG_ADV_PAUSE_MASK 0x0C00
462 #define MDIO_AN_REG_ADV 0x0011
463 #define MDIO_AN_REG_ADV2 0x0012
464 #define MDIO_AN_REG_LP_AUTO_NEG 0x0013
465 #define MDIO_AN_REG_LP_AUTO_NEG2 0x0014
466 #define MDIO_AN_REG_MASTER_STATUS 0x0021
467 #define MDIO_AN_REG_EEE_ADV 0x003c
468 #define MDIO_AN_REG_LP_EEE_ADV 0x003d
470 #define MDIO_AN_REG_LINK_STATUS 0x8304
471 #define MDIO_AN_REG_CL37_CL73 0x8370
472 #define MDIO_AN_REG_CL37_AN 0xffe0
473 #define MDIO_AN_REG_CL37_FC_LD 0xffe4
474 #define MDIO_AN_REG_CL37_FC_LP 0xffe5
475 #define MDIO_AN_REG_1000T_STATUS 0xffea
477 #define MDIO_AN_REG_8073_2_5G 0x8329
478 #define MDIO_AN_REG_8073_BAM 0x8350
480 #define MDIO_AN_REG_8481_10GBASE_T_AN_CTRL 0x0020
481 #define MDIO_AN_REG_8481_LEGACY_MII_CTRL 0xffe0
482 #define MDIO_AN_REG_8481_MII_CTRL_FORCE_1G 0x40
483 #define MDIO_AN_REG_8481_LEGACY_MII_STATUS 0xffe1
484 #define MDIO_AN_REG_848xx_ID_MSB 0xffe2
485 #define BCM84858_PHY_ID 0x600d
486 #define MDIO_AN_REG_848xx_ID_LSB 0xffe3
487 #define MDIO_AN_REG_8481_LEGACY_AN_ADV 0xffe4
488 #define MDIO_AN_REG_8481_LEGACY_AN_EXPANSION 0xffe6
489 #define MDIO_AN_REG_8481_1000T_CTRL 0xffe9
490 #define MDIO_AN_REG_8481_1G_100T_EXT_CTRL 0xfff0
491 #define MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF 0x0008
492 #define MDIO_AN_REG_8481_EXPANSION_REG_RD_RW 0xfff5
493 #define MDIO_AN_REG_8481_EXPANSION_REG_ACCESS 0xfff7
494 #define MDIO_AN_REG_8481_AUX_CTRL 0xfff8
495 #define MDIO_AN_REG_8481_LEGACY_SHADOW 0xfffc
498 #define MDIO_CTL_DEVAD 0x1e
499 #define MDIO_CTL_REG_84823_MEDIA 0x401a
500 #define MDIO_CTL_REG_84823_MEDIA_MAC_MASK 0x0018
501 /* These pins configure the BCM84823 interface to MAC after reset. */
502 #define MDIO_CTL_REG_84823_CTRL_MAC_XFI 0x0008
503 #define MDIO_CTL_REG_84823_MEDIA_MAC_XAUI_M 0x0010
504 /* These pins configure the BCM84823 interface to Line after reset. */
505 #define MDIO_CTL_REG_84823_MEDIA_LINE_MASK 0x0060
506 #define MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L 0x0020
507 #define MDIO_CTL_REG_84823_MEDIA_LINE_XFI 0x0040
508 /* When this pin is active high during reset, 10GBASE-T core is power
509 * down, When it is active low the 10GBASE-T is power up
511 #define MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN 0x0080
512 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK 0x0100
513 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER 0x0000
514 #define MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER 0x0100
515 #define MDIO_CTL_REG_84823_MEDIA_FIBER_1G 0x1000
516 #define MDIO_CTL_REG_84823_USER_CTRL_REG 0x4005
517 #define MDIO_CTL_REG_84823_USER_CTRL_CMS 0x0080
518 #define MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH 0xa82b
519 #define MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ 0x2f
520 #define MDIO_PMA_REG_84823_CTL_LED_CTL_1 0xa8e3
521 #define MDIO_PMA_REG_84833_CTL_LED_CTL_1 0xa8ec
522 #define MDIO_PMA_REG_84823_LED3_STRETCH_EN 0x0080
525 #define MDIO_84833_TOP_CFG_FW_REV 0x400f
526 #define MDIO_84833_TOP_CFG_FW_EEE 0x10b1
527 #define MDIO_84833_TOP_CFG_FW_NO_EEE 0x1f81
528 #define MDIO_84833_TOP_CFG_XGPHY_STRAP1 0x401a
529 #define MDIO_84833_SUPER_ISOLATE 0x8000
530 /* These are mailbox register set used by 84833/84858. */
531 #define MDIO_848xx_TOP_CFG_SCRATCH_REG0 0x4005
532 #define MDIO_848xx_TOP_CFG_SCRATCH_REG1 0x4006
533 #define MDIO_848xx_TOP_CFG_SCRATCH_REG2 0x4007
534 #define MDIO_848xx_TOP_CFG_SCRATCH_REG3 0x4008
535 #define MDIO_848xx_TOP_CFG_SCRATCH_REG4 0x4009
536 #define MDIO_848xx_TOP_CFG_SCRATCH_REG26 0x4037
537 #define MDIO_848xx_TOP_CFG_SCRATCH_REG27 0x4038
538 #define MDIO_848xx_TOP_CFG_SCRATCH_REG28 0x4039
539 #define MDIO_848xx_TOP_CFG_SCRATCH_REG29 0x403a
540 #define MDIO_848xx_TOP_CFG_SCRATCH_REG30 0x403b
541 #define MDIO_848xx_TOP_CFG_SCRATCH_REG31 0x403c
542 #define MDIO_848xx_CMD_HDLR_COMMAND (MDIO_848xx_TOP_CFG_SCRATCH_REG0)
543 #define MDIO_848xx_CMD_HDLR_STATUS (MDIO_848xx_TOP_CFG_SCRATCH_REG26)
544 #define MDIO_848xx_CMD_HDLR_DATA1 (MDIO_848xx_TOP_CFG_SCRATCH_REG27)
545 #define MDIO_848xx_CMD_HDLR_DATA2 (MDIO_848xx_TOP_CFG_SCRATCH_REG28)
546 #define MDIO_848xx_CMD_HDLR_DATA3 (MDIO_848xx_TOP_CFG_SCRATCH_REG29)
547 #define MDIO_848xx_CMD_HDLR_DATA4 (MDIO_848xx_TOP_CFG_SCRATCH_REG30)
548 #define MDIO_848xx_CMD_HDLR_DATA5 (MDIO_848xx_TOP_CFG_SCRATCH_REG31)
550 /* Mailbox command set used by 84833/84858 */
551 #define PHY848xx_CMD_SET_PAIR_SWAP 0x8001
552 #define PHY848xx_CMD_GET_EEE_MODE 0x8008
553 #define PHY848xx_CMD_SET_EEE_MODE 0x8009
554 #define PHY848xx_CMD_GET_CURRENT_TEMP 0x8031
555 /* Mailbox status set used by 84833 only */
556 #define PHY84833_STATUS_CMD_RECEIVED 0x0001
557 #define PHY84833_STATUS_CMD_IN_PROGRESS 0x0002
558 #define PHY84833_STATUS_CMD_COMPLETE_PASS 0x0004
559 #define PHY84833_STATUS_CMD_COMPLETE_ERROR 0x0008
560 #define PHY84833_STATUS_CMD_OPEN_FOR_CMDS 0x0010
561 #define PHY84833_STATUS_CMD_SYSTEM_BOOT 0x0020
562 #define PHY84833_STATUS_CMD_NOT_OPEN_FOR_CMDS 0x0040
563 #define PHY84833_STATUS_CMD_CLEAR_COMPLETE 0x0080
564 #define PHY84833_STATUS_CMD_OPEN_OVERRIDE 0xa5a5
565 /* Mailbox Process */
566 #define PHY84833_MB_PROCESS1 1
567 #define PHY84833_MB_PROCESS2 2
568 #define PHY84833_MB_PROCESS3 3
571 /* Mailbox status set used by 84858 only */
572 #define PHY84858_STATUS_CMD_RECEIVED 0x0001
573 #define PHY84858_STATUS_CMD_IN_PROGRESS 0x0002
574 #define PHY84858_STATUS_CMD_COMPLETE_PASS 0x0004
575 #define PHY84858_STATUS_CMD_COMPLETE_ERROR 0x0008
576 #define PHY84858_STATUS_CMD_SYSTEM_BUSY 0xbbbb
579 /* Warpcore clause 45 addressing */
580 #define MDIO_WC_DEVAD 0x3
581 #define MDIO_WC_REG_IEEE0BLK_MIICNTL 0x0
582 #define MDIO_WC_REG_IEEE0BLK_AUTONEGNP 0x7
583 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT0 0x10
584 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1 0x11
585 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2 0x12
586 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY 0x4000
587 #define MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ 0x8000
588 #define MDIO_WC_REG_PCS_STATUS2 0x0021
589 #define MDIO_WC_REG_PMD_KR_CONTROL 0x0096
590 #define MDIO_WC_REG_XGXSBLK0_XGXSCONTROL 0x8000
591 #define MDIO_WC_REG_XGXSBLK0_MISCCONTROL1 0x800e
592 #define MDIO_WC_REG_XGXSBLK1_DESKEW 0x8010
593 #define MDIO_WC_REG_XGXSBLK1_LANECTRL0 0x8015
594 #define MDIO_WC_REG_XGXSBLK1_LANECTRL1 0x8016
595 #define MDIO_WC_REG_XGXSBLK1_LANECTRL2 0x8017
596 #define MDIO_WC_REG_XGXSBLK1_LANECTRL3 0x8018
597 #define MDIO_WC_REG_XGXSBLK1_LANETEST0 0x801a
598 #define MDIO_WC_REG_TX0_ANA_CTRL0 0x8061
599 #define MDIO_WC_REG_TX1_ANA_CTRL0 0x8071
600 #define MDIO_WC_REG_TX2_ANA_CTRL0 0x8081
601 #define MDIO_WC_REG_TX3_ANA_CTRL0 0x8091
602 #define MDIO_WC_REG_TX0_TX_DRIVER 0x8067
603 #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET 0x01
604 #define MDIO_WC_REG_TX0_TX_DRIVER_IFIR_MASK 0x000e
605 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET 0x04
606 #define MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_MASK 0x00f0
607 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET 0x08
608 #define MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_MASK 0x0f00
609 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET 0x0c
610 #define MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_MASK 0x7000
611 #define MDIO_WC_REG_TX1_TX_DRIVER 0x8077
612 #define MDIO_WC_REG_TX2_TX_DRIVER 0x8087
613 #define MDIO_WC_REG_TX3_TX_DRIVER 0x8097
614 #define MDIO_WC_REG_RX0_ANARXCONTROL1G 0x80b9
615 #define MDIO_WC_REG_RX2_ANARXCONTROL1G 0x80d9
616 #define MDIO_WC_REG_RX0_PCI_CTRL 0x80ba
617 #define MDIO_WC_REG_RX1_PCI_CTRL 0x80ca
618 #define MDIO_WC_REG_RX2_PCI_CTRL 0x80da
619 #define MDIO_WC_REG_RX3_PCI_CTRL 0x80ea
620 #define MDIO_WC_REG_RXB_ANA_RX_CONTROL_PCI 0x80fa
621 #define MDIO_WC_REG_XGXSBLK2_UNICORE_MODE_10G 0x8104
622 #define MDIO_WC_REG_XGXSBLK2_LANE_RESET 0x810a
623 #define MDIO_WC_REG_XGXS_STATUS3 0x8129
624 #define MDIO_WC_REG_PAR_DET_10G_STATUS 0x8130
625 #define MDIO_WC_REG_PAR_DET_10G_CTRL 0x8131
626 #define MDIO_WC_REG_XGXS_STATUS4 0x813c
627 #define MDIO_WC_REG_XGXS_X2_CONTROL2 0x8141
628 #define MDIO_WC_REG_XGXS_X2_CONTROL3 0x8142
629 #define MDIO_WC_REG_XGXS_RX_LN_SWAP1 0x816B
630 #define MDIO_WC_REG_XGXS_TX_LN_SWAP1 0x8169
631 #define MDIO_WC_REG_GP2_STATUS_GP_2_0 0x81d0
632 #define MDIO_WC_REG_GP2_STATUS_GP_2_1 0x81d1
633 #define MDIO_WC_REG_GP2_STATUS_GP_2_2 0x81d2
634 #define MDIO_WC_REG_GP2_STATUS_GP_2_3 0x81d3
635 #define MDIO_WC_REG_GP2_STATUS_GP_2_4 0x81d4
636 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL 0x1000
637 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CMPL 0x0100
638 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP 0x0010
639 #define MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_AN_CAP 0x1
640 #define MDIO_WC_REG_UC_INFO_B0_DEAD_TRAP 0x81EE
641 #define MDIO_WC_REG_UC_INFO_B1_VERSION 0x81F0
642 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE 0x81F2
643 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE0_OFFSET 0x0
644 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT 0x0
645 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_OPT_LR 0x1
646 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC 0x2
647 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_XLAUI 0x3
648 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_LONG_CH_6G 0x4
649 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE1_OFFSET 0x4
650 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE2_OFFSET 0x8
651 #define MDIO_WC_REG_UC_INFO_B1_FIRMWARE_LANE3_OFFSET 0xc
652 #define MDIO_WC_REG_UC_INFO_B1_CRC 0x81FE
653 #define MDIO_WC_REG_DSC1B0_UC_CTRL 0x820e
654 #define MDIO_WC_REG_DSC1B0_UC_CTRL_RDY4CMD (1<<7)
655 #define MDIO_WC_REG_DSC_SMC 0x8213
656 #define MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0 0x821e
657 #define MDIO_WC_REG_TX_FIR_TAP 0x82e2
658 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET 0x00
659 #define MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_MASK 0x000f
660 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET 0x04
661 #define MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_MASK 0x03f0
662 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET 0x0a
663 #define MDIO_WC_REG_TX_FIR_TAP_POST_TAP_MASK 0x7c00
664 #define MDIO_WC_REG_TX_FIR_TAP_ENABLE 0x8000
665 #define MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP 0x82e2
666 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL 0x82e3
667 #define MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL 0x82e6
668 #define MDIO_WC_REG_CL72_USERB0_CL72_BR_DEF_CTRL 0x82e7
669 #define MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL 0x82e8
670 #define MDIO_WC_REG_CL72_USERB0_CL72_MISC4_CONTROL 0x82ec
671 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1 0x8300
672 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2 0x8301
673 #define MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3 0x8302
674 #define MDIO_WC_REG_SERDESDIGITAL_STATUS1000X1 0x8304
675 #define MDIO_WC_REG_SERDESDIGITAL_MISC1 0x8308
676 #define MDIO_WC_REG_SERDESDIGITAL_MISC2 0x8309
677 #define MDIO_WC_REG_DIGITAL3_UP1 0x8329
678 #define MDIO_WC_REG_DIGITAL3_LP_UP1 0x832c
679 #define MDIO_WC_REG_DIGITAL4_MISC3 0x833c
680 #define MDIO_WC_REG_DIGITAL4_MISC5 0x833e
681 #define MDIO_WC_REG_DIGITAL5_MISC6 0x8345
682 #define MDIO_WC_REG_DIGITAL5_MISC7 0x8349
683 #define MDIO_WC_REG_DIGITAL5_LINK_STATUS 0x834d
684 #define MDIO_WC_REG_DIGITAL5_ACTUAL_SPEED 0x834e
685 #define MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL 0x8350
686 #define MDIO_WC_REG_CL49_USERB0_CTRL 0x8368
687 #define MDIO_WC_REG_CL73_USERB0_CTRL 0x8370
688 #define MDIO_WC_REG_CL73_USERB0_USTAT 0x8371
689 #define MDIO_WC_REG_CL73_BAM_CTRL1 0x8372
690 #define MDIO_WC_REG_CL73_BAM_CTRL2 0x8373
691 #define MDIO_WC_REG_CL73_BAM_CTRL3 0x8374
692 #define MDIO_WC_REG_CL73_BAM_CODE_FIELD 0x837b
693 #define MDIO_WC_REG_EEE_COMBO_CONTROL0 0x8390
694 #define MDIO_WC_REG_TX66_CONTROL 0x83b0
695 #define MDIO_WC_REG_RX66_CONTROL 0x83c0
696 #define MDIO_WC_REG_RX66_SCW0 0x83c2
697 #define MDIO_WC_REG_RX66_SCW1 0x83c3
698 #define MDIO_WC_REG_RX66_SCW2 0x83c4
699 #define MDIO_WC_REG_RX66_SCW3 0x83c5
700 #define MDIO_WC_REG_RX66_SCW0_MASK 0x83c6
701 #define MDIO_WC_REG_RX66_SCW1_MASK 0x83c7
702 #define MDIO_WC_REG_RX66_SCW2_MASK 0x83c8
703 #define MDIO_WC_REG_RX66_SCW3_MASK 0x83c9
704 #define MDIO_WC_REG_FX100_CTRL1 0x8400
705 #define MDIO_WC_REG_FX100_CTRL3 0x8402
706 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL5 0x8436
707 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL6 0x8437
708 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL7 0x8438
709 #define MDIO_WC_REG_CL82_USERB1_TX_CTRL9 0x8439
710 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL10 0x843a
711 #define MDIO_WC_REG_CL82_USERB1_RX_CTRL11 0x843b
712 #define MDIO_WC_REG_ETA_CL73_OUI1 0x8453
713 #define MDIO_WC_REG_ETA_CL73_OUI2 0x8454
714 #define MDIO_WC_REG_ETA_CL73_OUI3 0x8455
715 #define MDIO_WC_REG_ETA_CL73_LD_BAM_CODE 0x8456
716 #define MDIO_WC_REG_ETA_CL73_LD_UD_CODE 0x8457
717 #define MDIO_WC_REG_MICROBLK_CMD 0xffc2
718 #define MDIO_WC_REG_MICROBLK_DL_STATUS 0xffc5
719 #define MDIO_WC_REG_MICROBLK_CMD3 0xffcc
721 #define MDIO_WC_REG_AERBLK_AER 0xffde
722 #define MDIO_WC_REG_COMBO_IEEE0_MIICTRL 0xffe0
723 #define MDIO_WC_REG_COMBO_IEEE0_MIIISTAT 0xffe1
725 #define MDIO_WC0_XGXS_BLK2_LANE_RESET 0x810A
726 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_RX_BITSHIFT 0
727 #define MDIO_WC0_XGXS_BLK2_LANE_RESET_TX_BITSHIFT 4
729 #define MDIO_WC0_XGXS_BLK6_XGXS_X2_CONTROL2 0x8141
731 #define DIGITAL5_ACTUAL_SPEED_TX_MASK 0x003f
734 #define MDIO_REG_GPHY_MII_STATUS 0x1
735 #define MDIO_REG_GPHY_PHYID_LSB 0x3
736 #define MDIO_REG_GPHY_CL45_ADDR_REG 0xd
737 #define MDIO_REG_GPHY_CL45_REG_WRITE 0x4000
738 #define MDIO_REG_GPHY_CL45_REG_READ 0xc000
739 #define MDIO_REG_GPHY_CL45_DATA_REG 0xe
740 #define MDIO_REG_GPHY_EEE_RESOLVED 0x803e
741 #define MDIO_REG_GPHY_EXP_ACCESS_GATE 0x15
742 #define MDIO_REG_GPHY_EXP_ACCESS 0x17
743 #define MDIO_REG_GPHY_EXP_ACCESS_TOP 0xd00
744 #define MDIO_REG_GPHY_EXP_TOP_2K_BUF 0x40
745 #define MDIO_REG_GPHY_AUX_STATUS 0x19
746 #define MDIO_REG_INTR_STATUS 0x1a
747 #define MDIO_REG_INTR_MASK 0x1b
748 #define MDIO_REG_INTR_MASK_LINK_STATUS (0x1 << 1)
749 #define MDIO_REG_GPHY_SHADOW 0x1c
750 #define MDIO_REG_GPHY_SHADOW_LED_SEL1 (0x0d << 10)
751 #define MDIO_REG_GPHY_SHADOW_LED_SEL2 (0x0e << 10)
752 #define MDIO_REG_GPHY_SHADOW_WR_ENA (0x1 << 15)
753 #define MDIO_REG_GPHY_SHADOW_AUTO_DET_MED (0x1e << 10)
754 #define MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD (0x1 << 8)
757 typedef elink_status_t (*read_sfp_module_eeprom_func_p)(struct elink_phy *phy,
758 struct elink_params *params,
759 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
760 uint8_t *o_buf, uint8_t);
761 /********************************************************/
762 #define ELINK_ETH_HLEN 14
763 /* L2 header size + 2*VLANs (8 bytes) + LLC SNAP (8 bytes) */
764 #define ELINK_ETH_OVREHEAD (ELINK_ETH_HLEN + 8 + 8)
765 #define ELINK_ETH_MIN_PACKET_SIZE 60
766 #define ELINK_ETH_MAX_PACKET_SIZE 1500
767 #define ELINK_ETH_MAX_JUMBO_PACKET_SIZE 9600
768 #define ELINK_MDIO_ACCESS_TIMEOUT 1000
769 #define WC_LANE_MAX 4
770 #define I2C_SWITCH_WIDTH 2
773 #define I2C_WA_RETRY_CNT 3
774 #define I2C_WA_PWR_ITER (I2C_WA_RETRY_CNT - 1)
775 #define MCPR_IMC_COMMAND_READ_OP 1
776 #define MCPR_IMC_COMMAND_WRITE_OP 2
778 /* LED Blink rate that will achieve ~15.9Hz */
779 #define LED_BLINK_RATE_VAL_E3 354
780 #define LED_BLINK_RATE_VAL_E1X_E2 480
781 /***********************************************************/
782 /* Shortcut definitions */
783 /***********************************************************/
785 #define ELINK_NIG_LATCH_BC_ENABLE_MI_INT 0
787 #define ELINK_NIG_STATUS_EMAC0_MI_INT \
788 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_EMAC0_MISC_MI_INT
789 #define ELINK_NIG_STATUS_XGXS0_LINK10G \
790 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK10G
791 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS \
792 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS
793 #define ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE \
794 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_XGXS0_LINK_STATUS_SIZE
795 #define ELINK_NIG_STATUS_SERDES0_LINK_STATUS \
796 NIG_STATUS_INTERRUPT_PORT0_REG_STATUS_SERDES0_LINK_STATUS
797 #define ELINK_NIG_MASK_MI_INT \
798 NIG_MASK_INTERRUPT_PORT0_REG_MASK_EMAC0_MISC_MI_INT
799 #define ELINK_NIG_MASK_XGXS0_LINK10G \
800 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK10G
801 #define ELINK_NIG_MASK_XGXS0_LINK_STATUS \
802 NIG_MASK_INTERRUPT_PORT0_REG_MASK_XGXS0_LINK_STATUS
803 #define ELINK_NIG_MASK_SERDES0_LINK_STATUS \
804 NIG_MASK_INTERRUPT_PORT0_REG_MASK_SERDES0_LINK_STATUS
806 #define ELINK_MDIO_AN_CL73_OR_37_COMPLETE \
807 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE | \
808 MDIO_GP_STATUS_TOP_AN_STATUS1_CL37_AUTONEG_COMPLETE)
810 #define ELINK_XGXS_RESET_BITS \
811 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_RSTB_HW | \
812 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_IDDQ | \
813 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN | \
814 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_PWRDWN_SD | \
815 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_XGXS0_TXD_FIFO_RSTB)
817 #define ELINK_SERDES_RESET_BITS \
818 (MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_RSTB_HW | \
819 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_IDDQ | \
820 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN | \
821 MISC_REGISTERS_RESET_REG_3_MISC_NIG_MUX_SERDES0_PWRDWN_SD)
823 #define ELINK_AUTONEG_CL37 SHARED_HW_CFG_AN_ENABLE_CL37
824 #define ELINK_AUTONEG_CL73 SHARED_HW_CFG_AN_ENABLE_CL73
825 #define ELINK_AUTONEG_BAM SHARED_HW_CFG_AN_ENABLE_BAM
826 #define ELINK_AUTONEG_PARALLEL \
827 SHARED_HW_CFG_AN_ENABLE_PARALLEL_DETECTION
828 #define ELINK_AUTONEG_SGMII_FIBER_AUTODET \
829 SHARED_HW_CFG_AN_EN_SGMII_FIBER_AUTO_DETECT
830 #define ELINK_AUTONEG_REMOTE_PHY SHARED_HW_CFG_AN_ENABLE_REMOTE_PHY
832 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_TXSIDE \
833 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_TXSIDE
834 #define ELINK_GP_STATUS_PAUSE_RSOLUTION_RXSIDE \
835 MDIO_GP_STATUS_TOP_AN_STATUS1_PAUSE_RSOLUTION_RXSIDE
836 #define ELINK_GP_STATUS_SPEED_MASK \
837 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_MASK
838 #define ELINK_GP_STATUS_10M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10M
839 #define ELINK_GP_STATUS_100M MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_100M
840 #define ELINK_GP_STATUS_1G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G
841 #define ELINK_GP_STATUS_2_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_2_5G
842 #define ELINK_GP_STATUS_5G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_5G
843 #define ELINK_GP_STATUS_6G MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_6G
844 #define ELINK_GP_STATUS_10G_HIG \
845 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_HIG
846 #define ELINK_GP_STATUS_10G_CX4 \
847 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_CX4
848 #define ELINK_GP_STATUS_1G_KX MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_1G_KX
849 #define ELINK_GP_STATUS_10G_KX4 \
850 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KX4
851 #define ELINK_GP_STATUS_10G_KR MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_KR
852 #define ELINK_GP_STATUS_10G_XFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_XFI
853 #define ELINK_GP_STATUS_20G_DXGXS MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_DXGXS
854 #define ELINK_GP_STATUS_10G_SFI MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_10G_SFI
855 #define ELINK_GP_STATUS_20G_KR2 MDIO_GP_STATUS_TOP_AN_STATUS1_ACTUAL_SPEED_20G_KR2
856 #define ELINK_LINK_10THD LINK_STATUS_SPEED_AND_DUPLEX_10THD
857 #define ELINK_LINK_10TFD LINK_STATUS_SPEED_AND_DUPLEX_10TFD
858 #define ELINK_LINK_100TXHD LINK_STATUS_SPEED_AND_DUPLEX_100TXHD
859 #define ELINK_LINK_100T4 LINK_STATUS_SPEED_AND_DUPLEX_100T4
860 #define ELINK_LINK_100TXFD LINK_STATUS_SPEED_AND_DUPLEX_100TXFD
861 #define ELINK_LINK_1000THD LINK_STATUS_SPEED_AND_DUPLEX_1000THD
862 #define ELINK_LINK_1000TFD LINK_STATUS_SPEED_AND_DUPLEX_1000TFD
863 #define ELINK_LINK_1000XFD LINK_STATUS_SPEED_AND_DUPLEX_1000XFD
864 #define ELINK_LINK_2500THD LINK_STATUS_SPEED_AND_DUPLEX_2500THD
865 #define ELINK_LINK_2500TFD LINK_STATUS_SPEED_AND_DUPLEX_2500TFD
866 #define ELINK_LINK_2500XFD LINK_STATUS_SPEED_AND_DUPLEX_2500XFD
867 #define ELINK_LINK_10GTFD LINK_STATUS_SPEED_AND_DUPLEX_10GTFD
868 #define ELINK_LINK_10GXFD LINK_STATUS_SPEED_AND_DUPLEX_10GXFD
869 #define ELINK_LINK_20GTFD LINK_STATUS_SPEED_AND_DUPLEX_20GTFD
870 #define ELINK_LINK_20GXFD LINK_STATUS_SPEED_AND_DUPLEX_20GXFD
872 #define ELINK_LINK_UPDATE_MASK \
873 (LINK_STATUS_SPEED_AND_DUPLEX_MASK | \
874 LINK_STATUS_LINK_UP | \
875 LINK_STATUS_PHYSICAL_LINK_FLAG | \
876 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE | \
877 LINK_STATUS_RX_FLOW_CONTROL_FLAG_MASK | \
878 LINK_STATUS_TX_FLOW_CONTROL_FLAG_MASK | \
879 LINK_STATUS_PARALLEL_DETECTION_FLAG_MASK | \
880 LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE | \
881 LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE)
883 #define ELINK_SFP_EEPROM_CON_TYPE_ADDR 0x2
884 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN 0x0
885 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_LC 0x7
886 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER 0x21
887 #define ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45 0x22
890 #define ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR 0x3
891 #define ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK (1<<4)
892 #define ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK (1<<5)
893 #define ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK (1<<6)
895 #define ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR 0x6
896 #define ELINK_SFP_EEPROM_1G_COMP_CODE_SX (1<<0)
897 #define ELINK_SFP_EEPROM_1G_COMP_CODE_LX (1<<1)
898 #define ELINK_SFP_EEPROM_1G_COMP_CODE_CX (1<<2)
899 #define ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T (1<<3)
901 #define ELINK_SFP_EEPROM_FC_TX_TECH_ADDR 0x8
902 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE 0x4
903 #define ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE 0x8
905 #define ELINK_SFP_EEPROM_OPTIONS_ADDR 0x40
906 #define ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK 0x1
907 #define ELINK_SFP_EEPROM_OPTIONS_SIZE 2
909 #define ELINK_EDC_MODE_LINEAR 0x0022
910 #define ELINK_EDC_MODE_LIMITING 0x0044
911 #define ELINK_EDC_MODE_PASSIVE_DAC 0x0055
912 #define ELINK_EDC_MODE_ACTIVE_DAC 0x0066
915 #define DCBX_INVALID_COS (0xFF)
917 #define ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND (0x5000)
918 #define ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT (0x5000)
919 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS (1360)
920 #define ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS (2720)
921 #define ELINK_ETS_E3B0_PBF_MIN_W_VAL (10000)
923 #define ELINK_MAX_PACKET_SIZE (9700)
924 #define MAX_KR_LINK_RETRY 4
925 #define DEFAULT_TX_DRV_BRDCT 2
926 #define DEFAULT_TX_DRV_IFIR 0
927 #define DEFAULT_TX_DRV_POST2 3
928 #define DEFAULT_TX_DRV_IPRE_DRIVER 6
930 /**********************************************************/
932 /**********************************************************/
934 #define CL22_WR_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
935 elink_cl45_write(_sc, _phy, \
936 (_phy)->def_md_devad, \
937 (_bank + (_addr & 0xf)), \
940 #define CL22_RD_OVER_CL45(_sc, _phy, _bank, _addr, _val) \
941 elink_cl45_read(_sc, _phy, \
942 (_phy)->def_md_devad, \
943 (_bank + (_addr & 0xf)), \
946 static elink_status_t elink_check_half_open_conn(struct elink_params *params,
947 struct elink_vars *vars, uint8_t notify);
948 static elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
949 struct elink_params *params);
951 static uint32_t elink_bits_en(struct bxe_softc *sc, uint32_t reg, uint32_t bits)
953 uint32_t val = REG_RD(sc, reg);
956 REG_WR(sc, reg, val);
960 static uint32_t elink_bits_dis(struct bxe_softc *sc, uint32_t reg, uint32_t bits)
962 uint32_t val = REG_RD(sc, reg);
965 REG_WR(sc, reg, val);
970 * elink_check_lfa - This function checks if link reinitialization is required,
971 * or link flap can be avoided.
973 * @params: link parameters
974 * Returns 0 if Link Flap Avoidance conditions are met otherwise, the failed
977 static int elink_check_lfa(struct elink_params *params)
979 uint32_t link_status, cfg_idx, lfa_mask, cfg_size;
980 uint32_t cur_speed_cap_mask, cur_req_fc_auto_adv, additional_config;
981 uint32_t saved_val, req_val, eee_status;
982 struct bxe_softc *sc = params->sc;
985 REG_RD(sc, params->lfa_base +
986 offsetof(struct shmem_lfa, additional_config));
988 /* NOTE: must be first condition checked -
989 * to verify DCC bit is cleared in any case!
991 if (additional_config & NO_LFA_DUE_TO_DCC_MASK) {
992 ELINK_DEBUG_P0(sc, "No LFA due to DCC flap after clp exit\n");
993 REG_WR(sc, params->lfa_base +
994 offsetof(struct shmem_lfa, additional_config),
995 additional_config & ~NO_LFA_DUE_TO_DCC_MASK);
996 return LFA_DCC_LFA_DISABLED;
999 /* Verify that link is up */
1000 link_status = REG_RD(sc, params->shmem_base +
1001 offsetof(struct shmem_region,
1002 port_mb[params->port].link_status));
1003 if (!(link_status & LINK_STATUS_LINK_UP))
1004 return LFA_LINK_DOWN;
1006 /* if loaded after BOOT from SAN, don't flap the link in any case and
1007 * rely on link set by preboot driver
1009 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BOOT_FROM_SAN)
1012 /* Verify that loopback mode is not set */
1013 if (params->loopback_mode)
1014 return LFA_LOOPBACK_ENABLED;
1016 /* Verify that MFW supports LFA */
1017 if (!params->lfa_base)
1018 return LFA_MFW_IS_TOO_OLD;
1020 if (params->num_phys == 3) {
1022 lfa_mask = 0xffffffff;
1028 /* Compare Duplex */
1029 saved_val = REG_RD(sc, params->lfa_base +
1030 offsetof(struct shmem_lfa, req_duplex));
1031 req_val = params->req_duplex[0] | (params->req_duplex[1] << 16);
1032 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1033 ELINK_DEBUG_P2(sc, "Duplex mismatch %x vs. %x\n",
1034 (saved_val & lfa_mask), (req_val & lfa_mask));
1035 return LFA_DUPLEX_MISMATCH;
1037 /* Compare Flow Control */
1038 saved_val = REG_RD(sc, params->lfa_base +
1039 offsetof(struct shmem_lfa, req_flow_ctrl));
1040 req_val = params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16);
1041 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1042 ELINK_DEBUG_P2(sc, "Flow control mismatch %x vs. %x\n",
1043 (saved_val & lfa_mask), (req_val & lfa_mask));
1044 return LFA_FLOW_CTRL_MISMATCH;
1046 /* Compare Link Speed */
1047 saved_val = REG_RD(sc, params->lfa_base +
1048 offsetof(struct shmem_lfa, req_line_speed));
1049 req_val = params->req_line_speed[0] | (params->req_line_speed[1] << 16);
1050 if ((saved_val & lfa_mask) != (req_val & lfa_mask)) {
1051 ELINK_DEBUG_P2(sc, "Link speed mismatch %x vs. %x\n",
1052 (saved_val & lfa_mask), (req_val & lfa_mask));
1053 return LFA_LINK_SPEED_MISMATCH;
1056 for (cfg_idx = 0; cfg_idx < cfg_size; cfg_idx++) {
1057 cur_speed_cap_mask = REG_RD(sc, params->lfa_base +
1058 offsetof(struct shmem_lfa,
1059 speed_cap_mask[cfg_idx]));
1061 if (cur_speed_cap_mask != params->speed_cap_mask[cfg_idx]) {
1062 ELINK_DEBUG_P2(sc, "Speed Cap mismatch %x vs. %x\n",
1064 params->speed_cap_mask[cfg_idx]);
1065 return LFA_SPEED_CAP_MISMATCH;
1069 cur_req_fc_auto_adv =
1070 REG_RD(sc, params->lfa_base +
1071 offsetof(struct shmem_lfa, additional_config)) &
1072 REQ_FC_AUTO_ADV_MASK;
1074 if ((uint16_t)cur_req_fc_auto_adv != params->req_fc_auto_adv) {
1075 ELINK_DEBUG_P2(sc, "Flow Ctrl AN mismatch %x vs. %x\n",
1076 cur_req_fc_auto_adv, params->req_fc_auto_adv);
1077 return LFA_FLOW_CTRL_MISMATCH;
1080 eee_status = REG_RD(sc, params->shmem2_base +
1081 offsetof(struct shmem2_region,
1082 eee_status[params->port]));
1084 if (((eee_status & SHMEM_EEE_LPI_REQUESTED_BIT) ^
1085 (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)) ||
1086 ((eee_status & SHMEM_EEE_REQUESTED_BIT) ^
1087 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI))) {
1088 ELINK_DEBUG_P2(sc, "EEE mismatch %x vs. %x\n", params->eee_mode,
1090 return LFA_EEE_MISMATCH;
1093 /* LFA conditions are met */
1096 /******************************************************************/
1097 /* EPIO/GPIO section */
1098 /******************************************************************/
1099 static void elink_get_epio(struct bxe_softc *sc, uint32_t epio_pin, uint32_t *en)
1101 uint32_t epio_mask, gp_oenable;
1104 if (epio_pin > 31) {
1105 ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to get\n", epio_pin);
1109 epio_mask = 1 << epio_pin;
1110 /* Set this EPIO to output */
1111 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1112 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable & ~epio_mask);
1114 *en = (REG_RD(sc, MCP_REG_MCPR_GP_INPUTS) & epio_mask) >> epio_pin;
1116 static void elink_set_epio(struct bxe_softc *sc, uint32_t epio_pin, uint32_t en)
1118 uint32_t epio_mask, gp_output, gp_oenable;
1121 if (epio_pin > 31) {
1122 ELINK_DEBUG_P1(sc, "Invalid EPIO pin %d to set\n", epio_pin);
1125 ELINK_DEBUG_P2(sc, "Setting EPIO pin %d to %d\n", epio_pin, en);
1126 epio_mask = 1 << epio_pin;
1127 /* Set this EPIO to output */
1128 gp_output = REG_RD(sc, MCP_REG_MCPR_GP_OUTPUTS);
1130 gp_output |= epio_mask;
1132 gp_output &= ~epio_mask;
1134 REG_WR(sc, MCP_REG_MCPR_GP_OUTPUTS, gp_output);
1136 /* Set the value for this EPIO */
1137 gp_oenable = REG_RD(sc, MCP_REG_MCPR_GP_OENABLE);
1138 REG_WR(sc, MCP_REG_MCPR_GP_OENABLE, gp_oenable | epio_mask);
1141 static void elink_set_cfg_pin(struct bxe_softc *sc, uint32_t pin_cfg, uint32_t val)
1143 if (pin_cfg == PIN_CFG_NA)
1145 if (pin_cfg >= PIN_CFG_EPIO0) {
1146 elink_set_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1148 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1149 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1150 elink_cb_gpio_write(sc, gpio_num, (uint8_t)val, gpio_port);
1154 static uint32_t elink_get_cfg_pin(struct bxe_softc *sc, uint32_t pin_cfg, uint32_t *val)
1156 if (pin_cfg == PIN_CFG_NA)
1157 return ELINK_STATUS_ERROR;
1158 if (pin_cfg >= PIN_CFG_EPIO0) {
1159 elink_get_epio(sc, pin_cfg - PIN_CFG_EPIO0, val);
1161 uint8_t gpio_num = (pin_cfg - PIN_CFG_GPIO0_P0) & 0x3;
1162 uint8_t gpio_port = (pin_cfg - PIN_CFG_GPIO0_P0) >> 2;
1163 *val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
1165 return ELINK_STATUS_OK;
1168 /******************************************************************/
1170 /******************************************************************/
1171 static void elink_ets_e2e3a0_disabled(struct elink_params *params)
1173 /* ETS disabled configuration*/
1174 struct bxe_softc *sc = params->sc;
1176 ELINK_DEBUG_P0(sc, "ETS E2E3 disabled configuration\n");
1178 /* mapping between entry priority to client number (0,1,2 -debug and
1179 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
1181 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1182 * cos1-100 cos0-011 dbg1-010 dbg0-001 MCP-000
1185 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, 0x4688);
1186 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1187 * as strict. Bits 0,1,2 - debug and management entries, 3 -
1188 * COS0 entry, 4 - COS1 entry.
1189 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
1190 * bit4 bit3 bit2 bit1 bit0
1191 * MCP and debug are strict
1194 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
1195 /* defines which entries (clients) are subjected to WFQ arbitration */
1196 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
1197 /* For strict priority entries defines the number of consecutive
1198 * slots for the highest priority.
1200 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1201 /* mapping between the CREDIT_WEIGHT registers and actual client
1204 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0);
1205 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0);
1206 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0);
1208 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, 0);
1209 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, 0);
1210 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, 0);
1211 /* ETS mode disable */
1212 REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
1213 /* If ETS mode is enabled (there is no strict priority) defines a WFQ
1214 * weight for COS0/COS1.
1216 REG_WR(sc, PBF_REG_COS0_WEIGHT, 0x2710);
1217 REG_WR(sc, PBF_REG_COS1_WEIGHT, 0x2710);
1218 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter */
1219 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND, 0x989680);
1220 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND, 0x989680);
1221 /* Defines the number of consecutive slots for the strict priority */
1222 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1224 /******************************************************************************
1226 * Getting min_w_val will be set according to line speed .
1228 ******************************************************************************/
1229 static uint32_t elink_ets_get_min_w_val_nig(const struct elink_vars *vars)
1231 uint32_t min_w_val = 0;
1232 /* Calculate min_w_val.*/
1233 if (vars->link_up) {
1234 if (vars->line_speed == ELINK_SPEED_20000)
1235 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
1237 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_UP_TO_10GBPS;
1239 min_w_val = ELINK_ETS_E3B0_NIG_MIN_W_VAL_20GBPS;
1240 /* If the link isn't up (static configuration for example ) The
1241 * link will be according to 20GBPS.
1245 /******************************************************************************
1247 * Getting credit upper bound form min_w_val.
1249 ******************************************************************************/
1250 static uint32_t elink_ets_get_credit_upper_bound(const uint32_t min_w_val)
1252 const uint32_t credit_upper_bound = (uint32_t)ELINK_MAXVAL((150 * min_w_val),
1253 ELINK_MAX_PACKET_SIZE);
1254 return credit_upper_bound;
1256 /******************************************************************************
1258 * Set credit upper bound for NIG.
1260 ******************************************************************************/
1261 static void elink_ets_e3b0_set_credit_upper_bound_nig(
1262 const struct elink_params *params,
1263 const uint32_t min_w_val)
1265 struct bxe_softc *sc = params->sc;
1266 const uint8_t port = params->port;
1267 const uint32_t credit_upper_bound =
1268 elink_ets_get_credit_upper_bound(min_w_val);
1270 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_0 :
1271 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0, credit_upper_bound);
1272 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_1 :
1273 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1, credit_upper_bound);
1274 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_2 :
1275 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_2, credit_upper_bound);
1276 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_3 :
1277 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_3, credit_upper_bound);
1278 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_4 :
1279 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_4, credit_upper_bound);
1280 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_UPPER_BOUND_5 :
1281 NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_5, credit_upper_bound);
1284 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_6,
1285 credit_upper_bound);
1286 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_7,
1287 credit_upper_bound);
1288 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_8,
1289 credit_upper_bound);
1292 /******************************************************************************
1294 * Will return the NIG ETS registers to init values.Except
1295 * credit_upper_bound.
1296 * That isn't used in this configuration (No WFQ is enabled) and will be
1297 * configured acording to spec
1299 ******************************************************************************/
1300 static void elink_ets_e3b0_nig_disabled(const struct elink_params *params,
1301 const struct elink_vars *vars)
1303 struct bxe_softc *sc = params->sc;
1304 const uint8_t port = params->port;
1305 const uint32_t min_w_val = elink_ets_get_min_w_val_nig(vars);
1306 /* Mapping between entry priority to client number (0,1,2 -debug and
1307 * management clients, 3 - COS0 client, 4 - COS1, ... 8 -
1308 * COS5)(HIGHEST) 4bits client num.TODO_ETS - Should be done by
1309 * reset value or init tool
1312 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB, 0x543210);
1313 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_MSB, 0x0);
1315 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB, 0x76543210);
1316 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB, 0x8);
1318 /* For strict priority entries defines the number of consecutive
1319 * slots for the highest priority.
1321 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS :
1322 NIG_REG_P1_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
1323 /* Mapping between the CREDIT_WEIGHT registers and actual client
1327 /*Port 1 has 6 COS*/
1328 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_LSB, 0x210543);
1329 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x0);
1331 /*Port 0 has 9 COS*/
1332 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_LSB,
1334 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP2_MSB, 0x5);
1337 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1338 * as strict. Bits 0,1,2 - debug and management entries, 3 -
1339 * COS0 entry, 4 - COS1 entry.
1340 * COS1 | COS0 | DEBUG1 | DEBUG0 | MGMT
1341 * bit4 bit3 bit2 bit1 bit0
1342 * MCP and debug are strict
1345 REG_WR(sc, NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT, 0x3f);
1347 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1ff);
1348 /* defines which entries (clients) are subjected to WFQ arbitration */
1349 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
1350 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0);
1352 /* Please notice the register address are note continuous and a
1353 * for here is note appropriate.In 2 port mode port0 only COS0-5
1354 * can be used. DEBUG1,DEBUG1,MGMT are never used for WFQ* In 4
1355 * port mode port1 only COS0-2 can be used. DEBUG1,DEBUG1,MGMT
1356 * are never used for WFQ
1358 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
1359 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, 0x0);
1360 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
1361 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, 0x0);
1362 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
1363 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2, 0x0);
1364 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_3 :
1365 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3, 0x0);
1366 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_4 :
1367 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4, 0x0);
1368 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_5 :
1369 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5, 0x0);
1371 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_6, 0x0);
1372 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_7, 0x0);
1373 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_8, 0x0);
1376 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val);
1378 /******************************************************************************
1380 * Set credit upper bound for PBF.
1382 ******************************************************************************/
1383 static void elink_ets_e3b0_set_credit_upper_bound_pbf(
1384 const struct elink_params *params,
1385 const uint32_t min_w_val)
1387 struct bxe_softc *sc = params->sc;
1388 const uint32_t credit_upper_bound =
1389 elink_ets_get_credit_upper_bound(min_w_val);
1390 const uint8_t port = params->port;
1391 uint32_t base_upper_bound = 0;
1392 uint8_t max_cos = 0;
1394 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.In 4
1395 * port mode port1 has COS0-2 that can be used for WFQ.
1398 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P0;
1399 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1401 base_upper_bound = PBF_REG_COS0_UPPER_BOUND_P1;
1402 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
1405 for (i = 0; i < max_cos; i++)
1406 REG_WR(sc, base_upper_bound + (i << 2), credit_upper_bound);
1409 /******************************************************************************
1411 * Will return the PBF ETS registers to init values.Except
1412 * credit_upper_bound.
1413 * That isn't used in this configuration (No WFQ is enabled) and will be
1414 * configured acording to spec
1416 ******************************************************************************/
1417 static void elink_ets_e3b0_pbf_disabled(const struct elink_params *params)
1419 struct bxe_softc *sc = params->sc;
1420 const uint8_t port = params->port;
1421 const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
1423 uint32_t base_weight = 0;
1424 uint8_t max_cos = 0;
1426 /* Mapping between entry priority to client number 0 - COS0
1427 * client, 2 - COS1, ... 5 - COS5)(HIGHEST) 4bits client num.
1428 * TODO_ETS - Should be done by reset value or init tool
1431 /* 0x688 (|011|0 10|00 1|000) */
1432 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , 0x688);
1434 /* (10 1|100 |011|0 10|00 1|000) */
1435 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , 0x2C688);
1437 /* TODO_ETS - Should be done by reset value or init tool */
1439 /* 0x688 (|011|0 10|00 1|000)*/
1440 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P1, 0x688);
1442 /* 0x2C688 (10 1|100 |011|0 10|00 1|000) */
1443 REG_WR(sc, PBF_REG_ETS_ARB_CLIENT_CREDIT_MAP_P0, 0x2C688);
1445 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P1 :
1446 PBF_REG_ETS_ARB_NUM_STRICT_ARB_SLOTS_P0 , 0x100);
1449 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
1450 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , 0);
1452 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
1453 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0 , 0);
1454 /* In 2 port mode port0 has COS0-5 that can be used for WFQ.
1455 * In 4 port mode port1 has COS0-2 that can be used for WFQ.
1458 base_weight = PBF_REG_COS0_WEIGHT_P0;
1459 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1461 base_weight = PBF_REG_COS0_WEIGHT_P1;
1462 max_cos = ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1;
1465 for (i = 0; i < max_cos; i++)
1466 REG_WR(sc, base_weight + (0x4 * i), 0);
1468 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1470 /******************************************************************************
1472 * E3B0 disable will return basicly the values to init values.
1474 ******************************************************************************/
1475 static elink_status_t elink_ets_e3b0_disabled(const struct elink_params *params,
1476 const struct elink_vars *vars)
1478 struct bxe_softc *sc = params->sc;
1480 if (!CHIP_IS_E3B0(sc)) {
1482 "elink_ets_e3b0_disabled the chip isn't E3B0\n");
1483 return ELINK_STATUS_ERROR;
1486 elink_ets_e3b0_nig_disabled(params, vars);
1488 elink_ets_e3b0_pbf_disabled(params);
1490 return ELINK_STATUS_OK;
1493 /******************************************************************************
1495 * Disable will return basicly the values to init values.
1497 ******************************************************************************/
1498 elink_status_t elink_ets_disabled(struct elink_params *params,
1499 struct elink_vars *vars)
1501 struct bxe_softc *sc = params->sc;
1502 elink_status_t elink_status = ELINK_STATUS_OK;
1504 if ((CHIP_IS_E2(sc)) || (CHIP_IS_E3A0(sc)))
1505 elink_ets_e2e3a0_disabled(params);
1506 else if (CHIP_IS_E3B0(sc))
1507 elink_status = elink_ets_e3b0_disabled(params, vars);
1509 ELINK_DEBUG_P0(sc, "elink_ets_disabled - chip not supported\n");
1510 return ELINK_STATUS_ERROR;
1513 return elink_status;
1516 /******************************************************************************
1518 * Set the COS mappimg to SP and BW until this point all the COS are not
1520 ******************************************************************************/
1521 static elink_status_t elink_ets_e3b0_cli_map(const struct elink_params *params,
1522 const struct elink_ets_params *ets_params,
1523 const uint8_t cos_sp_bitmap,
1524 const uint8_t cos_bw_bitmap)
1526 struct bxe_softc *sc = params->sc;
1527 const uint8_t port = params->port;
1528 const uint8_t nig_cli_sp_bitmap = 0x7 | (cos_sp_bitmap << 3);
1529 const uint8_t pbf_cli_sp_bitmap = cos_sp_bitmap;
1530 const uint8_t nig_cli_subject2wfq_bitmap = cos_bw_bitmap << 3;
1531 const uint8_t pbf_cli_subject2wfq_bitmap = cos_bw_bitmap;
1533 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_STRICT :
1534 NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, nig_cli_sp_bitmap);
1536 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P1 :
1537 PBF_REG_ETS_ARB_CLIENT_IS_STRICT_P0 , pbf_cli_sp_bitmap);
1539 REG_WR(sc, (port) ? NIG_REG_P1_TX_ARB_CLIENT_IS_SUBJECT2WFQ :
1540 NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ,
1541 nig_cli_subject2wfq_bitmap);
1543 REG_WR(sc, (port) ? PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P1 :
1544 PBF_REG_ETS_ARB_CLIENT_IS_SUBJECT2WFQ_P0,
1545 pbf_cli_subject2wfq_bitmap);
1547 return ELINK_STATUS_OK;
1550 /******************************************************************************
1552 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
1553 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
1554 ******************************************************************************/
1555 static elink_status_t elink_ets_e3b0_set_cos_bw(struct bxe_softc *sc,
1556 const uint8_t cos_entry,
1557 const uint32_t min_w_val_nig,
1558 const uint32_t min_w_val_pbf,
1559 const uint16_t total_bw,
1563 uint32_t nig_reg_adress_crd_weight = 0;
1564 uint32_t pbf_reg_adress_crd_weight = 0;
1565 /* Calculate and set BW for this COS - use 1 instead of 0 for BW */
1566 const uint32_t cos_bw_nig = ((bw ? bw : 1) * min_w_val_nig) / total_bw;
1567 const uint32_t cos_bw_pbf = ((bw ? bw : 1) * min_w_val_pbf) / total_bw;
1569 switch (cos_entry) {
1571 nig_reg_adress_crd_weight =
1572 (port) ? NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_0 :
1573 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0;
1574 pbf_reg_adress_crd_weight = (port) ?
1575 PBF_REG_COS0_WEIGHT_P1 : PBF_REG_COS0_WEIGHT_P0;
1578 nig_reg_adress_crd_weight = (port) ?
1579 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_1 :
1580 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1;
1581 pbf_reg_adress_crd_weight = (port) ?
1582 PBF_REG_COS1_WEIGHT_P1 : PBF_REG_COS1_WEIGHT_P0;
1585 nig_reg_adress_crd_weight = (port) ?
1586 NIG_REG_P1_TX_ARB_CREDIT_WEIGHT_2 :
1587 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_2;
1589 pbf_reg_adress_crd_weight = (port) ?
1590 PBF_REG_COS2_WEIGHT_P1 : PBF_REG_COS2_WEIGHT_P0;
1594 return ELINK_STATUS_ERROR;
1595 nig_reg_adress_crd_weight =
1596 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_3;
1597 pbf_reg_adress_crd_weight =
1598 PBF_REG_COS3_WEIGHT_P0;
1602 return ELINK_STATUS_ERROR;
1603 nig_reg_adress_crd_weight =
1604 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_4;
1605 pbf_reg_adress_crd_weight = PBF_REG_COS4_WEIGHT_P0;
1609 return ELINK_STATUS_ERROR;
1610 nig_reg_adress_crd_weight =
1611 NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_5;
1612 pbf_reg_adress_crd_weight = PBF_REG_COS5_WEIGHT_P0;
1616 REG_WR(sc, nig_reg_adress_crd_weight, cos_bw_nig);
1618 REG_WR(sc, pbf_reg_adress_crd_weight, cos_bw_pbf);
1620 return ELINK_STATUS_OK;
1622 /******************************************************************************
1624 * Calculate the total BW.A value of 0 isn't legal.
1626 ******************************************************************************/
1627 static elink_status_t elink_ets_e3b0_get_total_bw(
1628 const struct elink_params *params,
1629 struct elink_ets_params *ets_params,
1632 struct bxe_softc *sc = params->sc;
1633 uint8_t cos_idx = 0;
1634 uint8_t is_bw_cos_exist = 0;
1637 /* Calculate total BW requested */
1638 for (cos_idx = 0; cos_idx < ets_params->num_of_cos; cos_idx++) {
1639 if (ets_params->cos[cos_idx].state == elink_cos_state_bw) {
1640 is_bw_cos_exist = 1;
1641 if (!ets_params->cos[cos_idx].params.bw_params.bw) {
1642 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config BW"
1644 /* This is to prevent a state when ramrods
1647 ets_params->cos[cos_idx].params.bw_params.bw
1651 ets_params->cos[cos_idx].params.bw_params.bw;
1655 /* Check total BW is valid */
1656 if ((is_bw_cos_exist == 1) && (*total_bw != 100)) {
1657 if (*total_bw == 0) {
1659 "elink_ets_E3B0_config total BW shouldn't be 0\n");
1660 return ELINK_STATUS_ERROR;
1663 "elink_ets_E3B0_config total BW should be 100\n");
1664 /* We can handle a case whre the BW isn't 100 this can happen
1665 * if the TC are joined.
1668 return ELINK_STATUS_OK;
1671 /******************************************************************************
1673 * Invalidate all the sp_pri_to_cos.
1675 ******************************************************************************/
1676 static void elink_ets_e3b0_sp_pri_to_cos_init(uint8_t *sp_pri_to_cos)
1679 for (pri = 0; pri < ELINK_DCBX_MAX_NUM_COS; pri++)
1680 sp_pri_to_cos[pri] = DCBX_INVALID_COS;
1682 /******************************************************************************
1684 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1685 * according to sp_pri_to_cos.
1687 ******************************************************************************/
1688 static elink_status_t elink_ets_e3b0_sp_pri_to_cos_set(const struct elink_params *params,
1689 uint8_t *sp_pri_to_cos, const uint8_t pri,
1690 const uint8_t cos_entry)
1692 struct bxe_softc *sc = params->sc;
1693 const uint8_t port = params->port;
1694 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1695 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1697 if (pri >= max_num_of_cos) {
1698 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
1699 "parameter Illegal strict priority\n");
1700 return ELINK_STATUS_ERROR;
1703 if (sp_pri_to_cos[pri] != DCBX_INVALID_COS) {
1704 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_pri_to_cos_set invalid "
1705 "parameter There can't be two COS's with "
1706 "the same strict pri\n");
1707 return ELINK_STATUS_ERROR;
1710 sp_pri_to_cos[pri] = cos_entry;
1711 return ELINK_STATUS_OK;
1715 /******************************************************************************
1717 * Returns the correct value according to COS and priority in
1718 * the sp_pri_cli register.
1720 ******************************************************************************/
1721 static uint64_t elink_e3b0_sp_get_pri_cli_reg(const uint8_t cos, const uint8_t cos_offset,
1722 const uint8_t pri_set,
1723 const uint8_t pri_offset,
1724 const uint8_t entry_size)
1726 uint64_t pri_cli_nig = 0;
1727 pri_cli_nig = ((uint64_t)(cos + cos_offset)) << (entry_size *
1728 (pri_set + pri_offset));
1732 /******************************************************************************
1734 * Returns the correct value according to COS and priority in the
1735 * sp_pri_cli register for NIG.
1737 ******************************************************************************/
1738 static uint64_t elink_e3b0_sp_get_pri_cli_reg_nig(const uint8_t cos, const uint8_t pri_set)
1740 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1741 const uint8_t nig_cos_offset = 3;
1742 const uint8_t nig_pri_offset = 3;
1744 return elink_e3b0_sp_get_pri_cli_reg(cos, nig_cos_offset, pri_set,
1748 /******************************************************************************
1750 * Returns the correct value according to COS and priority in the
1751 * sp_pri_cli register for PBF.
1753 ******************************************************************************/
1754 static uint64_t elink_e3b0_sp_get_pri_cli_reg_pbf(const uint8_t cos, const uint8_t pri_set)
1756 const uint8_t pbf_cos_offset = 0;
1757 const uint8_t pbf_pri_offset = 0;
1759 return elink_e3b0_sp_get_pri_cli_reg(cos, pbf_cos_offset, pri_set,
1764 /******************************************************************************
1766 * Calculate and set the SP (ARB_PRIORITY_CLIENT) NIG and PBF registers
1767 * according to sp_pri_to_cos.(which COS has higher priority)
1769 ******************************************************************************/
1770 static elink_status_t elink_ets_e3b0_sp_set_pri_cli_reg(const struct elink_params *params,
1771 uint8_t *sp_pri_to_cos)
1773 struct bxe_softc *sc = params->sc;
1775 const uint8_t port = params->port;
1776 /* MCP Dbg0 and dbg1 are always with higher strict pri*/
1777 uint64_t pri_cli_nig = 0x210;
1778 uint32_t pri_cli_pbf = 0x0;
1779 uint8_t pri_set = 0;
1780 uint8_t pri_bitmask = 0;
1781 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1782 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1784 uint8_t cos_bit_to_set = (1 << max_num_of_cos) - 1;
1786 /* Set all the strict priority first */
1787 for (i = 0; i < max_num_of_cos; i++) {
1788 if (sp_pri_to_cos[i] != DCBX_INVALID_COS) {
1789 if (sp_pri_to_cos[i] >= ELINK_DCBX_MAX_NUM_COS) {
1791 "elink_ets_e3b0_sp_set_pri_cli_reg "
1792 "invalid cos entry\n");
1793 return ELINK_STATUS_ERROR;
1796 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
1797 sp_pri_to_cos[i], pri_set);
1799 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
1800 sp_pri_to_cos[i], pri_set);
1801 pri_bitmask = 1 << sp_pri_to_cos[i];
1802 /* COS is used remove it from bitmap.*/
1803 if (!(pri_bitmask & cos_bit_to_set)) {
1805 "elink_ets_e3b0_sp_set_pri_cli_reg "
1806 "invalid There can't be two COS's with"
1807 " the same strict pri\n");
1808 return ELINK_STATUS_ERROR;
1810 cos_bit_to_set &= ~pri_bitmask;
1815 /* Set all the Non strict priority i= COS*/
1816 for (i = 0; i < max_num_of_cos; i++) {
1817 pri_bitmask = 1 << i;
1818 /* Check if COS was already used for SP */
1819 if (pri_bitmask & cos_bit_to_set) {
1820 /* COS wasn't used for SP */
1821 pri_cli_nig |= elink_e3b0_sp_get_pri_cli_reg_nig(
1824 pri_cli_pbf |= elink_e3b0_sp_get_pri_cli_reg_pbf(
1826 /* COS is used remove it from bitmap.*/
1827 cos_bit_to_set &= ~pri_bitmask;
1832 if (pri_set != max_num_of_cos) {
1833 ELINK_DEBUG_P0(sc, "elink_ets_e3b0_sp_set_pri_cli_reg not all "
1834 "entries were set\n");
1835 return ELINK_STATUS_ERROR;
1839 /* Only 6 usable clients*/
1840 REG_WR(sc, NIG_REG_P1_TX_ARB_PRIORITY_CLIENT2_LSB,
1841 (uint32_t)pri_cli_nig);
1843 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P1 , pri_cli_pbf);
1845 /* Only 9 usable clients*/
1846 const uint32_t pri_cli_nig_lsb = (uint32_t) (pri_cli_nig);
1847 const uint32_t pri_cli_nig_msb = (uint32_t) ((pri_cli_nig >> 32) & 0xF);
1849 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_LSB,
1851 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT2_MSB,
1854 REG_WR(sc, PBF_REG_ETS_ARB_PRIORITY_CLIENT_P0 , pri_cli_pbf);
1856 return ELINK_STATUS_OK;
1859 /******************************************************************************
1861 * Configure the COS to ETS according to BW and SP settings.
1862 ******************************************************************************/
1863 elink_status_t elink_ets_e3b0_config(const struct elink_params *params,
1864 const struct elink_vars *vars,
1865 struct elink_ets_params *ets_params)
1867 struct bxe_softc *sc = params->sc;
1868 elink_status_t elink_status = ELINK_STATUS_OK;
1869 const uint8_t port = params->port;
1870 uint16_t total_bw = 0;
1871 const uint32_t min_w_val_nig = elink_ets_get_min_w_val_nig(vars);
1872 const uint32_t min_w_val_pbf = ELINK_ETS_E3B0_PBF_MIN_W_VAL;
1873 uint8_t cos_bw_bitmap = 0;
1874 uint8_t cos_sp_bitmap = 0;
1875 uint8_t sp_pri_to_cos[ELINK_DCBX_MAX_NUM_COS] = {0};
1876 const uint8_t max_num_of_cos = (port) ? ELINK_DCBX_E3B0_MAX_NUM_COS_PORT1 :
1877 ELINK_DCBX_E3B0_MAX_NUM_COS_PORT0;
1878 uint8_t cos_entry = 0;
1880 if (!CHIP_IS_E3B0(sc)) {
1882 "elink_ets_e3b0_disabled the chip isn't E3B0\n");
1883 return ELINK_STATUS_ERROR;
1886 if ((ets_params->num_of_cos > max_num_of_cos)) {
1887 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config the number of COS "
1888 "isn't supported\n");
1889 return ELINK_STATUS_ERROR;
1892 /* Prepare sp strict priority parameters*/
1893 elink_ets_e3b0_sp_pri_to_cos_init(sp_pri_to_cos);
1895 /* Prepare BW parameters*/
1896 elink_status = elink_ets_e3b0_get_total_bw(params, ets_params,
1898 if (elink_status != ELINK_STATUS_OK) {
1900 "elink_ets_E3B0_config get_total_bw failed\n");
1901 return ELINK_STATUS_ERROR;
1904 /* Upper bound is set according to current link speed (min_w_val
1905 * should be the same for upper bound and COS credit val).
1907 elink_ets_e3b0_set_credit_upper_bound_nig(params, min_w_val_nig);
1908 elink_ets_e3b0_set_credit_upper_bound_pbf(params, min_w_val_pbf);
1911 for (cos_entry = 0; cos_entry < ets_params->num_of_cos; cos_entry++) {
1912 if (elink_cos_state_bw == ets_params->cos[cos_entry].state) {
1913 cos_bw_bitmap |= (1 << cos_entry);
1914 /* The function also sets the BW in HW(not the mappin
1917 elink_status = elink_ets_e3b0_set_cos_bw(
1918 sc, cos_entry, min_w_val_nig, min_w_val_pbf,
1920 ets_params->cos[cos_entry].params.bw_params.bw,
1922 } else if (elink_cos_state_strict ==
1923 ets_params->cos[cos_entry].state){
1924 cos_sp_bitmap |= (1 << cos_entry);
1926 elink_status = elink_ets_e3b0_sp_pri_to_cos_set(
1929 ets_params->cos[cos_entry].params.sp_params.pri,
1934 "elink_ets_e3b0_config cos state not valid\n");
1935 return ELINK_STATUS_ERROR;
1937 if (elink_status != ELINK_STATUS_OK) {
1939 "elink_ets_e3b0_config set cos bw failed\n");
1940 return elink_status;
1944 /* Set SP register (which COS has higher priority) */
1945 elink_status = elink_ets_e3b0_sp_set_pri_cli_reg(params,
1948 if (elink_status != ELINK_STATUS_OK) {
1950 "elink_ets_E3B0_config set_pri_cli_reg failed\n");
1951 return elink_status;
1954 /* Set client mapping of BW and strict */
1955 elink_status = elink_ets_e3b0_cli_map(params, ets_params,
1959 if (elink_status != ELINK_STATUS_OK) {
1960 ELINK_DEBUG_P0(sc, "elink_ets_E3B0_config SP failed\n");
1961 return elink_status;
1963 return ELINK_STATUS_OK;
1965 static void elink_ets_bw_limit_common(const struct elink_params *params)
1967 /* ETS disabled configuration */
1968 struct bxe_softc *sc = params->sc;
1969 ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration\n");
1970 /* Defines which entries (clients) are subjected to WFQ arbitration
1974 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_SUBJECT2WFQ, 0x18);
1975 /* Mapping between the ARB_CREDIT_WEIGHT registers and actual
1976 * client numbers (WEIGHT_0 does not actually have to represent
1978 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
1979 * cos1-001 cos0-000 dbg1-100 dbg0-011 MCP-010
1981 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_CREDIT_MAP, 0x111A);
1983 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_0,
1984 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1985 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_UPPER_BOUND_1,
1986 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
1988 /* ETS mode enabled*/
1989 REG_WR(sc, PBF_REG_ETS_ENABLED, 1);
1991 /* Defines the number of consecutive slots for the strict priority */
1992 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0);
1993 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
1994 * as strict. Bits 0,1,2 - debug and management entries, 3 - COS0
1995 * entry, 4 - COS1 entry.
1996 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
1997 * bit4 bit3 bit2 bit1 bit0
1998 * MCP and debug are strict
2000 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x7);
2002 /* Upper bound that COS0_WEIGHT can reach in the WFQ arbiter.*/
2003 REG_WR(sc, PBF_REG_COS0_UPPER_BOUND,
2004 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
2005 REG_WR(sc, PBF_REG_COS1_UPPER_BOUND,
2006 ELINK_ETS_BW_LIMIT_CREDIT_UPPER_BOUND);
2009 void elink_ets_bw_limit(const struct elink_params *params, const uint32_t cos0_bw,
2010 const uint32_t cos1_bw)
2012 /* ETS disabled configuration*/
2013 struct bxe_softc *sc = params->sc;
2014 const uint32_t total_bw = cos0_bw + cos1_bw;
2015 uint32_t cos0_credit_weight = 0;
2016 uint32_t cos1_credit_weight = 0;
2018 ELINK_DEBUG_P0(sc, "ETS enabled BW limit configuration\n");
2023 ELINK_DEBUG_P0(sc, "Total BW can't be zero\n");
2027 cos0_credit_weight = (cos0_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/
2029 cos1_credit_weight = (cos1_bw * ELINK_ETS_BW_LIMIT_CREDIT_WEIGHT)/
2032 elink_ets_bw_limit_common(params);
2034 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_0, cos0_credit_weight);
2035 REG_WR(sc, NIG_REG_P0_TX_ARB_CREDIT_WEIGHT_1, cos1_credit_weight);
2037 REG_WR(sc, PBF_REG_COS0_WEIGHT, cos0_credit_weight);
2038 REG_WR(sc, PBF_REG_COS1_WEIGHT, cos1_credit_weight);
2041 elink_status_t elink_ets_strict(const struct elink_params *params, const uint8_t strict_cos)
2043 /* ETS disabled configuration*/
2044 struct bxe_softc *sc = params->sc;
2047 ELINK_DEBUG_P0(sc, "ETS enabled strict configuration\n");
2048 /* Bitmap of 5bits length. Each bit specifies whether the entry behaves
2049 * as strict. Bits 0,1,2 - debug and management entries,
2050 * 3 - COS0 entry, 4 - COS1 entry.
2051 * COS1 | COS0 | DEBUG21 | DEBUG0 | MGMT
2052 * bit4 bit3 bit2 bit1 bit0
2053 * MCP and debug are strict
2055 REG_WR(sc, NIG_REG_P0_TX_ARB_CLIENT_IS_STRICT, 0x1F);
2056 /* For strict priority entries defines the number of consecutive slots
2057 * for the highest priority.
2059 REG_WR(sc, NIG_REG_P0_TX_ARB_NUM_STRICT_ARB_SLOTS, 0x100);
2060 /* ETS mode disable */
2061 REG_WR(sc, PBF_REG_ETS_ENABLED, 0);
2062 /* Defines the number of consecutive slots for the strict priority */
2063 REG_WR(sc, PBF_REG_NUM_STRICT_ARB_SLOTS, 0x100);
2065 /* Defines the number of consecutive slots for the strict priority */
2066 REG_WR(sc, PBF_REG_HIGH_PRIORITY_COS_NUM, strict_cos);
2068 /* Mapping between entry priority to client number (0,1,2 -debug and
2069 * management clients, 3 - COS0 client, 4 - COS client)(HIGHEST)
2071 * PRI4 | PRI3 | PRI2 | PRI1 | PRI0
2072 * dbg0-010 dbg1-001 cos1-100 cos0-011 MCP-000
2073 * dbg0-010 dbg1-001 cos0-011 cos1-100 MCP-000
2075 val = (!strict_cos) ? 0x2318 : 0x22E0;
2076 REG_WR(sc, NIG_REG_P0_TX_ARB_PRIORITY_CLIENT, val);
2078 return ELINK_STATUS_OK;
2081 /******************************************************************/
2083 /******************************************************************/
2084 static void elink_update_pfc_xmac(struct elink_params *params,
2085 struct elink_vars *vars,
2088 struct bxe_softc *sc = params->sc;
2090 uint32_t pause_val, pfc0_val, pfc1_val;
2092 /* XMAC base adrr */
2093 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2095 /* Initialize pause and pfc registers */
2096 pause_val = 0x18000;
2097 pfc0_val = 0xFFFF8000;
2100 /* No PFC support */
2101 if (!(params->feature_config_flags &
2102 ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
2104 /* RX flow control - Process pause frame in receive direction
2106 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
2107 pause_val |= XMAC_PAUSE_CTRL_REG_RX_PAUSE_EN;
2109 /* TX flow control - Send pause packet when buffer is full */
2110 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
2111 pause_val |= XMAC_PAUSE_CTRL_REG_TX_PAUSE_EN;
2112 } else {/* PFC support */
2113 pfc1_val |= XMAC_PFC_CTRL_HI_REG_PFC_REFRESH_EN |
2114 XMAC_PFC_CTRL_HI_REG_PFC_STATS_EN |
2115 XMAC_PFC_CTRL_HI_REG_RX_PFC_EN |
2116 XMAC_PFC_CTRL_HI_REG_TX_PFC_EN |
2117 XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
2118 /* Write pause and PFC registers */
2119 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
2120 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
2121 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
2122 pfc1_val &= ~XMAC_PFC_CTRL_HI_REG_FORCE_PFC_XON;
2126 /* Write pause and PFC registers */
2127 REG_WR(sc, xmac_base + XMAC_REG_PAUSE_CTRL, pause_val);
2128 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL, pfc0_val);
2129 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI, pfc1_val);
2132 /* Set MAC address for source TX Pause/PFC frames */
2133 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_LO,
2134 ((params->mac_addr[2] << 24) |
2135 (params->mac_addr[3] << 16) |
2136 (params->mac_addr[4] << 8) |
2137 (params->mac_addr[5])));
2138 REG_WR(sc, xmac_base + XMAC_REG_CTRL_SA_HI,
2139 ((params->mac_addr[0] << 8) |
2140 (params->mac_addr[1])));
2145 static void elink_emac_get_pfc_stat(struct elink_params *params,
2146 uint32_t pfc_frames_sent[2],
2147 uint32_t pfc_frames_received[2])
2149 /* Read pfc statistic */
2150 struct bxe_softc *sc = params->sc;
2151 uint32_t emac_base = params->port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2152 uint32_t val_xon = 0;
2153 uint32_t val_xoff = 0;
2155 ELINK_DEBUG_P0(sc, "pfc statistic read from EMAC\n");
2157 /* PFC received frames */
2158 val_xoff = REG_RD(sc, emac_base +
2159 EMAC_REG_RX_PFC_STATS_XOFF_RCVD);
2160 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_RCVD_COUNT;
2161 val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_RCVD);
2162 val_xon &= EMAC_REG_RX_PFC_STATS_XON_RCVD_COUNT;
2164 pfc_frames_received[0] = val_xon + val_xoff;
2166 /* PFC received sent */
2167 val_xoff = REG_RD(sc, emac_base +
2168 EMAC_REG_RX_PFC_STATS_XOFF_SENT);
2169 val_xoff &= EMAC_REG_RX_PFC_STATS_XOFF_SENT_COUNT;
2170 val_xon = REG_RD(sc, emac_base + EMAC_REG_RX_PFC_STATS_XON_SENT);
2171 val_xon &= EMAC_REG_RX_PFC_STATS_XON_SENT_COUNT;
2173 pfc_frames_sent[0] = val_xon + val_xoff;
2176 /* Read pfc statistic*/
2177 void elink_pfc_statistic(struct elink_params *params, struct elink_vars *vars,
2178 uint32_t pfc_frames_sent[2],
2179 uint32_t pfc_frames_received[2])
2181 /* Read pfc statistic */
2182 struct bxe_softc *sc = params->sc;
2184 ELINK_DEBUG_P0(sc, "pfc statistic\n");
2189 if (vars->mac_type == ELINK_MAC_TYPE_EMAC) {
2190 ELINK_DEBUG_P0(sc, "About to read PFC stats from EMAC\n");
2191 elink_emac_get_pfc_stat(params, pfc_frames_sent,
2192 pfc_frames_received);
2195 /******************************************************************/
2196 /* MAC/PBF section */
2197 /******************************************************************/
2198 static void elink_set_mdio_clk(struct bxe_softc *sc, uint32_t chip_id,
2201 uint32_t new_mode, cur_mode;
2203 /* Set clause 45 mode, slow down the MDIO clock to 2.5MHz
2204 * (a value of 49==0x31) and make sure that the AUTO poll is off
2206 cur_mode = REG_RD(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE);
2208 if (USES_WARPCORE(sc))
2209 clc_cnt = 74L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
2211 clc_cnt = 49L << EMAC_MDIO_MODE_CLOCK_CNT_BITSHIFT;
2213 if (((cur_mode & EMAC_MDIO_MODE_CLOCK_CNT) == clc_cnt) &&
2214 (cur_mode & (EMAC_MDIO_MODE_CLAUSE_45)))
2217 new_mode = cur_mode &
2218 ~(EMAC_MDIO_MODE_AUTO_POLL | EMAC_MDIO_MODE_CLOCK_CNT);
2219 new_mode |= clc_cnt;
2220 new_mode |= (EMAC_MDIO_MODE_CLAUSE_45);
2222 ELINK_DEBUG_P2(sc, "Changing emac_mode from 0x%x to 0x%x\n",
2223 cur_mode, new_mode);
2224 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_MODE, new_mode);
2228 static uint8_t elink_is_4_port_mode(struct bxe_softc *sc)
2230 uint32_t port4mode_ovwr_val;
2231 /* Check 4-port override enabled */
2232 port4mode_ovwr_val = REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR);
2233 if (port4mode_ovwr_val & (1<<0)) {
2234 /* Return 4-port mode override value */
2235 return ((port4mode_ovwr_val & (1<<1)) == (1<<1));
2237 /* Return 4-port mode from input pin */
2238 return (uint8_t)REG_RD(sc, MISC_REG_PORT4MODE_EN);
2241 static void elink_set_mdio_emac_per_phy(struct bxe_softc *sc,
2242 struct elink_params *params)
2246 /* Set mdio clock per phy */
2247 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
2249 elink_set_mdio_clk(sc, params->chip_id,
2250 params->phy[phy_index].mdio_ctrl);
2253 static void elink_emac_init(struct elink_params *params,
2254 struct elink_vars *vars)
2256 /* reset and unreset the emac core */
2257 struct bxe_softc *sc = params->sc;
2258 uint8_t port = params->port;
2259 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2263 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2264 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2266 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2267 (MISC_REGISTERS_RESET_REG_2_RST_EMAC0_HARD_CORE << port));
2269 /* init emac - use read-modify-write */
2270 /* self clear reset */
2271 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2272 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, (val | EMAC_MODE_RESET));
2276 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2277 ELINK_DEBUG_P1(sc, "EMAC reset reg is %u\n", val);
2279 ELINK_DEBUG_P0(sc, "EMAC timeout!\n");
2283 } while (val & EMAC_MODE_RESET);
2285 elink_set_mdio_emac_per_phy(sc, params);
2286 /* Set mac address */
2287 val = ((params->mac_addr[0] << 8) |
2288 params->mac_addr[1]);
2289 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH, val);
2291 val = ((params->mac_addr[2] << 24) |
2292 (params->mac_addr[3] << 16) |
2293 (params->mac_addr[4] << 8) |
2294 params->mac_addr[5]);
2295 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MAC_MATCH + 4, val);
2298 static void elink_set_xumac_nig(struct elink_params *params,
2299 uint16_t tx_pause_en,
2302 struct bxe_softc *sc = params->sc;
2304 REG_WR(sc, params->port ? NIG_REG_P1_MAC_IN_EN : NIG_REG_P0_MAC_IN_EN,
2306 REG_WR(sc, params->port ? NIG_REG_P1_MAC_OUT_EN : NIG_REG_P0_MAC_OUT_EN,
2308 REG_WR(sc, params->port ? NIG_REG_P1_MAC_PAUSE_OUT_EN :
2309 NIG_REG_P0_MAC_PAUSE_OUT_EN, tx_pause_en);
2312 static void elink_set_umac_rxtx(struct elink_params *params, uint8_t en)
2314 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
2316 struct bxe_softc *sc = params->sc;
2317 if (!(REG_RD(sc, MISC_REG_RESET_REG_2) &
2318 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port)))
2320 val = REG_RD(sc, umac_base + UMAC_REG_COMMAND_CONFIG);
2322 val |= (UMAC_COMMAND_CONFIG_REG_TX_ENA |
2323 UMAC_COMMAND_CONFIG_REG_RX_ENA);
2325 val &= ~(UMAC_COMMAND_CONFIG_REG_TX_ENA |
2326 UMAC_COMMAND_CONFIG_REG_RX_ENA);
2327 /* Disable RX and TX */
2328 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2331 static void elink_umac_enable(struct elink_params *params,
2332 struct elink_vars *vars, uint8_t lb)
2335 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
2336 struct bxe_softc *sc = params->sc;
2338 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2339 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
2342 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2343 (MISC_REGISTERS_RESET_REG_2_UMAC0 << params->port));
2345 ELINK_DEBUG_P0(sc, "enabling UMAC\n");
2347 /* This register opens the gate for the UMAC despite its name */
2348 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
2350 val = UMAC_COMMAND_CONFIG_REG_PROMIS_EN |
2351 UMAC_COMMAND_CONFIG_REG_PAD_EN |
2352 UMAC_COMMAND_CONFIG_REG_SW_RESET |
2353 UMAC_COMMAND_CONFIG_REG_NO_LGTH_CHECK;
2354 switch (vars->line_speed) {
2355 case ELINK_SPEED_10:
2358 case ELINK_SPEED_100:
2361 case ELINK_SPEED_1000:
2364 case ELINK_SPEED_2500:
2368 ELINK_DEBUG_P1(sc, "Invalid speed for UMAC %d\n",
2372 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2373 val |= UMAC_COMMAND_CONFIG_REG_IGNORE_TX_PAUSE;
2375 if (!(vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2376 val |= UMAC_COMMAND_CONFIG_REG_PAUSE_IGNORE;
2378 if (vars->duplex == DUPLEX_HALF)
2379 val |= UMAC_COMMAND_CONFIG_REG_HD_ENA;
2381 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2384 /* Configure UMAC for EEE */
2385 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
2386 ELINK_DEBUG_P0(sc, "configured UMAC for EEE\n");
2387 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL,
2388 UMAC_UMAC_EEE_CTRL_REG_EEE_EN);
2389 REG_WR(sc, umac_base + UMAC_REG_EEE_WAKE_TIMER, 0x11);
2391 REG_WR(sc, umac_base + UMAC_REG_UMAC_EEE_CTRL, 0x0);
2394 /* Set MAC address for source TX Pause/PFC frames (under SW reset) */
2395 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR0,
2396 ((params->mac_addr[2] << 24) |
2397 (params->mac_addr[3] << 16) |
2398 (params->mac_addr[4] << 8) |
2399 (params->mac_addr[5])));
2400 REG_WR(sc, umac_base + UMAC_REG_MAC_ADDR1,
2401 ((params->mac_addr[0] << 8) |
2402 (params->mac_addr[1])));
2404 /* Enable RX and TX */
2405 val &= ~UMAC_COMMAND_CONFIG_REG_PAD_EN;
2406 val |= UMAC_COMMAND_CONFIG_REG_TX_ENA |
2407 UMAC_COMMAND_CONFIG_REG_RX_ENA;
2408 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2411 /* Remove SW Reset */
2412 val &= ~UMAC_COMMAND_CONFIG_REG_SW_RESET;
2414 /* Check loopback mode */
2416 val |= UMAC_COMMAND_CONFIG_REG_LOOP_ENA;
2417 REG_WR(sc, umac_base + UMAC_REG_COMMAND_CONFIG, val);
2419 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
2420 * length used by the MAC receive logic to check frames.
2422 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
2423 elink_set_xumac_nig(params,
2424 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
2425 vars->mac_type = ELINK_MAC_TYPE_UMAC;
2429 /* Define the XMAC mode */
2430 static void elink_xmac_init(struct elink_params *params, uint32_t max_speed)
2432 struct bxe_softc *sc = params->sc;
2433 uint32_t is_port4mode = elink_is_4_port_mode(sc);
2435 /* In 4-port mode, need to set the mode only once, so if XMAC is
2436 * already out of reset, it means the mode has already been set,
2437 * and it must not* reset the XMAC again, since it controls both
2441 if (((CHIP_NUM(sc) == CHIP_NUM_57840_4_10) ||
2442 (CHIP_NUM(sc) == CHIP_NUM_57840_2_20) ||
2443 (CHIP_NUM(sc) == CHIP_NUM_57840_OBS)) &&
2445 (REG_RD(sc, MISC_REG_RESET_REG_2) &
2446 MISC_REGISTERS_RESET_REG_2_XMAC)) {
2448 "XMAC already out of reset in 4-port mode\n");
2453 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2454 MISC_REGISTERS_RESET_REG_2_XMAC);
2457 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2458 MISC_REGISTERS_RESET_REG_2_XMAC);
2460 ELINK_DEBUG_P0(sc, "Init XMAC to 2 ports x 10G per path\n");
2462 /* Set the number of ports on the system side to up to 2 */
2463 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 1);
2465 /* Set the number of ports on the Warp Core to 10G */
2466 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
2468 /* Set the number of ports on the system side to 1 */
2469 REG_WR(sc, MISC_REG_XMAC_CORE_PORT_MODE, 0);
2470 if (max_speed == ELINK_SPEED_10000) {
2472 "Init XMAC to 10G x 1 port per path\n");
2473 /* Set the number of ports on the Warp Core to 10G */
2474 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 3);
2477 "Init XMAC to 20G x 2 ports per path\n");
2478 /* Set the number of ports on the Warp Core to 20G */
2479 REG_WR(sc, MISC_REG_XMAC_PHY_PORT_MODE, 1);
2483 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2484 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
2487 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2488 MISC_REGISTERS_RESET_REG_2_XMAC_SOFT);
2492 static void elink_set_xmac_rxtx(struct elink_params *params, uint8_t en)
2494 uint8_t port = params->port;
2495 struct bxe_softc *sc = params->sc;
2496 uint32_t pfc_ctrl, xmac_base = (port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2499 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
2500 MISC_REGISTERS_RESET_REG_2_XMAC) {
2501 /* Send an indication to change the state in the NIG back to XON
2502 * Clearing this bit enables the next set of this bit to get
2505 pfc_ctrl = REG_RD(sc, xmac_base + XMAC_REG_PFC_CTRL_HI);
2506 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
2507 (pfc_ctrl & ~(1<<1)));
2508 REG_WR(sc, xmac_base + XMAC_REG_PFC_CTRL_HI,
2509 (pfc_ctrl | (1<<1)));
2510 ELINK_DEBUG_P1(sc, "Disable XMAC on port %x\n", port);
2511 val = REG_RD(sc, xmac_base + XMAC_REG_CTRL);
2513 val |= (XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
2515 val &= ~(XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN);
2516 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
2520 static elink_status_t elink_xmac_enable(struct elink_params *params,
2521 struct elink_vars *vars, uint8_t lb)
2523 uint32_t val, xmac_base;
2524 struct bxe_softc *sc = params->sc;
2525 ELINK_DEBUG_P0(sc, "enabling XMAC\n");
2527 xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
2529 elink_xmac_init(params, vars->line_speed);
2531 /* This register determines on which events the MAC will assert
2532 * error on the i/f to the NIG along w/ EOP.
2535 /* This register tells the NIG whether to send traffic to UMAC
2538 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 0);
2540 /* When XMAC is in XLGMII mode, disable sending idles for fault
2543 if (!(params->phy[ELINK_INT_PHY].flags & ELINK_FLAGS_TX_ERROR_CHECK)) {
2544 REG_WR(sc, xmac_base + XMAC_REG_RX_LSS_CTRL,
2545 (XMAC_RX_LSS_CTRL_REG_LOCAL_FAULT_DISABLE |
2546 XMAC_RX_LSS_CTRL_REG_REMOTE_FAULT_DISABLE));
2547 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
2548 REG_WR(sc, xmac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
2549 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
2550 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
2552 /* Set Max packet size */
2553 REG_WR(sc, xmac_base + XMAC_REG_RX_MAX_SIZE, 0x2710);
2555 /* CRC append for Tx packets */
2556 REG_WR(sc, xmac_base + XMAC_REG_TX_CTRL, 0xC800);
2559 elink_update_pfc_xmac(params, vars, 0);
2561 if (vars->eee_status & SHMEM_EEE_ADV_STATUS_MASK) {
2562 ELINK_DEBUG_P0(sc, "Setting XMAC for EEE\n");
2563 REG_WR(sc, xmac_base + XMAC_REG_EEE_TIMERS_HI, 0x1380008);
2564 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x1);
2566 REG_WR(sc, xmac_base + XMAC_REG_EEE_CTRL, 0x0);
2569 /* Enable TX and RX */
2570 val = XMAC_CTRL_REG_TX_EN | XMAC_CTRL_REG_RX_EN;
2572 /* Set MAC in XLGMII mode for dual-mode */
2573 if ((vars->line_speed == ELINK_SPEED_20000) &&
2574 (params->phy[ELINK_INT_PHY].supported &
2575 ELINK_SUPPORTED_20000baseKR2_Full))
2576 val |= XMAC_CTRL_REG_XLGMII_ALIGN_ENB;
2578 /* Check loopback mode */
2580 val |= XMAC_CTRL_REG_LINE_LOCAL_LPBK;
2581 REG_WR(sc, xmac_base + XMAC_REG_CTRL, val);
2582 elink_set_xumac_nig(params,
2583 ((vars->flow_ctrl & ELINK_FLOW_CTRL_TX) != 0), 1);
2585 vars->mac_type = ELINK_MAC_TYPE_XMAC;
2587 return ELINK_STATUS_OK;
2590 static elink_status_t elink_emac_enable(struct elink_params *params,
2591 struct elink_vars *vars, uint8_t lb)
2593 struct bxe_softc *sc = params->sc;
2594 uint8_t port = params->port;
2595 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
2598 ELINK_DEBUG_P0(sc, "enabling EMAC\n");
2601 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
2602 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2604 /* enable emac and not bmac */
2605 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 1);
2607 #ifdef ELINK_INCLUDE_EMUL
2609 if (CHIP_REV_IS_EMUL(sc)) {
2610 /* Use lane 1 (of lanes 0-3) */
2611 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2612 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2617 #ifdef ELINK_INCLUDE_FPGA
2618 if (CHIP_REV_IS_FPGA(sc)) {
2619 /* Use lane 1 (of lanes 0-3) */
2620 ELINK_DEBUG_P0(sc, "elink_emac_enable: Setting FPGA\n");
2622 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 1);
2623 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2627 if (vars->phy_flags & PHY_XGXS_FLAG) {
2628 uint32_t ser_lane = ((params->lane_config &
2629 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
2630 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
2632 ELINK_DEBUG_P0(sc, "XGXS\n");
2633 /* select the master lanes (out of 0-3) */
2634 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, ser_lane);
2636 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 1);
2638 } else { /* SerDes */
2639 ELINK_DEBUG_P0(sc, "SerDes\n");
2641 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0);
2644 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
2645 EMAC_RX_MODE_RESET);
2646 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2647 EMAC_TX_MODE_RESET);
2649 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
2650 if (CHIP_REV_IS_SLOW(sc)) {
2651 /* config GMII mode */
2652 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2653 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, (val | EMAC_MODE_PORT_GMII));
2656 /* pause enable/disable */
2657 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_RX_MODE,
2658 EMAC_RX_MODE_FLOW_EN);
2660 elink_bits_dis(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2661 (EMAC_TX_MODE_EXT_PAUSE_EN |
2662 EMAC_TX_MODE_FLOW_EN));
2663 if (!(params->feature_config_flags &
2664 ELINK_FEATURE_CONFIG_PFC_ENABLED)) {
2665 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
2666 elink_bits_en(sc, emac_base +
2667 EMAC_REG_EMAC_RX_MODE,
2668 EMAC_RX_MODE_FLOW_EN);
2670 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
2671 elink_bits_en(sc, emac_base +
2672 EMAC_REG_EMAC_TX_MODE,
2673 (EMAC_TX_MODE_EXT_PAUSE_EN |
2674 EMAC_TX_MODE_FLOW_EN));
2676 elink_bits_en(sc, emac_base + EMAC_REG_EMAC_TX_MODE,
2677 EMAC_TX_MODE_FLOW_EN);
2678 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
2682 /* KEEP_VLAN_TAG, promiscuous */
2683 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_RX_MODE);
2684 val |= EMAC_RX_MODE_KEEP_VLAN_TAG | EMAC_RX_MODE_PROMISCUOUS;
2686 /* Setting this bit causes MAC control frames (except for pause
2687 * frames) to be passed on for processing. This setting has no
2688 * affect on the operation of the pause frames. This bit effects
2689 * all packets regardless of RX Parser packet sorting logic.
2690 * Turn the PFC off to make sure we are in Xon state before
2693 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE, 0);
2694 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
2695 ELINK_DEBUG_P0(sc, "PFC is enabled\n");
2696 /* Enable PFC again */
2697 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_MODE,
2698 EMAC_REG_RX_PFC_MODE_RX_EN |
2699 EMAC_REG_RX_PFC_MODE_TX_EN |
2700 EMAC_REG_RX_PFC_MODE_PRIORITIES);
2702 elink_cb_reg_write(sc, emac_base + EMAC_REG_RX_PFC_PARAM,
2704 EMAC_REG_RX_PFC_PARAM_OPCODE_BITSHIFT) |
2706 EMAC_REG_RX_PFC_PARAM_PRIORITY_EN_BITSHIFT)));
2707 val |= EMAC_RX_MODE_KEEP_MAC_CONTROL;
2709 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MODE, val);
2712 val = REG_RD(sc, emac_base + EMAC_REG_EMAC_MODE);
2717 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_MODE, val);
2720 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 1);
2722 /* Enable emac for jumbo packets */
2723 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_RX_MTU_SIZE,
2724 (EMAC_RX_MTU_SIZE_JUMBO_ENA |
2725 (ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD)));
2728 REG_WR(sc, NIG_REG_NIG_INGRESS_EMAC0_NO_CRC + port*4, 0x1);
2730 /* Disable the NIG in/out to the bmac */
2731 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x0);
2732 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, 0x0);
2733 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x0);
2735 /* Enable the NIG in/out to the emac */
2736 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x1);
2738 if ((params->feature_config_flags &
2739 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
2740 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2743 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, val);
2744 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x1);
2746 #ifdef ELINK_INCLUDE_EMUL
2747 if (CHIP_REV_IS_EMUL(sc)) {
2748 /* Take the BigMac out of reset */
2749 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
2750 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
2752 /* Enable access for bmac registers */
2753 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
2756 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x0);
2758 vars->mac_type = ELINK_MAC_TYPE_EMAC;
2759 return ELINK_STATUS_OK;
2762 static void elink_update_pfc_bmac1(struct elink_params *params,
2763 struct elink_vars *vars)
2765 uint32_t wb_data[2];
2766 struct bxe_softc *sc = params->sc;
2767 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2768 NIG_REG_INGRESS_BMAC0_MEM;
2770 uint32_t val = 0x14;
2771 if ((!(params->feature_config_flags &
2772 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
2773 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2774 /* Enable BigMAC to react on received Pause packets */
2778 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_CONTROL, wb_data, 2);
2782 if (!(params->feature_config_flags &
2783 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
2784 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2788 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_CONTROL, wb_data, 2);
2791 static void elink_update_pfc_bmac2(struct elink_params *params,
2792 struct elink_vars *vars,
2795 /* Set rx control: Strip CRC and enable BigMAC to relay
2796 * control packets to the system as well
2798 uint32_t wb_data[2];
2799 struct bxe_softc *sc = params->sc;
2800 uint32_t bmac_addr = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
2801 NIG_REG_INGRESS_BMAC0_MEM;
2802 uint32_t val = 0x14;
2804 if ((!(params->feature_config_flags &
2805 ELINK_FEATURE_CONFIG_PFC_ENABLED)) &&
2806 (vars->flow_ctrl & ELINK_FLOW_CTRL_RX))
2807 /* Enable BigMAC to react on received Pause packets */
2811 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_CONTROL, wb_data, 2);
2816 if (!(params->feature_config_flags &
2817 ELINK_FEATURE_CONFIG_PFC_ENABLED) &&
2818 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
2822 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_CONTROL, wb_data, 2);
2824 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED) {
2825 ELINK_DEBUG_P0(sc, "PFC is enabled\n");
2826 /* Enable PFC RX & TX & STATS and set 8 COS */
2828 wb_data[0] |= (1<<0); /* RX */
2829 wb_data[0] |= (1<<1); /* TX */
2830 wb_data[0] |= (1<<2); /* Force initial Xon */
2831 wb_data[0] |= (1<<3); /* 8 cos */
2832 wb_data[0] |= (1<<5); /* STATS */
2834 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL,
2836 /* Clear the force Xon */
2837 wb_data[0] &= ~(1<<2);
2839 ELINK_DEBUG_P0(sc, "PFC is disabled\n");
2840 /* Disable PFC RX & TX & STATS and set 8 COS */
2845 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_PFC_CONTROL, wb_data, 2);
2847 /* Set Time (based unit is 512 bit time) between automatic
2848 * re-sending of PP packets amd enable automatic re-send of
2849 * Per-Priroity Packet as long as pp_gen is asserted and
2850 * pp_disable is low.
2853 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2854 val |= (1<<16); /* enable automatic re-send */
2858 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_PAUSE_CONTROL,
2862 val = 0x3; /* Enable RX and TX */
2864 val |= 0x4; /* Local loopback */
2865 ELINK_DEBUG_P0(sc, "enable bmac loopback\n");
2867 /* When PFC enabled, Pass pause frames towards the NIG. */
2868 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
2869 val |= ((1<<6)|(1<<5));
2873 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
2876 /******************************************************************************
2878 * This function is needed because NIG ARB_CREDIT_WEIGHT_X are
2879 * not continues and ARB_CREDIT_WEIGHT_0 + offset is suitable.
2880 ******************************************************************************/
2881 static elink_status_t elink_pfc_nig_rx_priority_mask(struct bxe_softc *sc,
2883 uint32_t priority_mask, uint8_t port)
2885 uint32_t nig_reg_rx_priority_mask_add = 0;
2887 switch (cos_entry) {
2889 nig_reg_rx_priority_mask_add = (port) ?
2890 NIG_REG_P1_RX_COS0_PRIORITY_MASK :
2891 NIG_REG_P0_RX_COS0_PRIORITY_MASK;
2894 nig_reg_rx_priority_mask_add = (port) ?
2895 NIG_REG_P1_RX_COS1_PRIORITY_MASK :
2896 NIG_REG_P0_RX_COS1_PRIORITY_MASK;
2899 nig_reg_rx_priority_mask_add = (port) ?
2900 NIG_REG_P1_RX_COS2_PRIORITY_MASK :
2901 NIG_REG_P0_RX_COS2_PRIORITY_MASK;
2905 return ELINK_STATUS_ERROR;
2906 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS3_PRIORITY_MASK;
2910 return ELINK_STATUS_ERROR;
2911 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS4_PRIORITY_MASK;
2915 return ELINK_STATUS_ERROR;
2916 nig_reg_rx_priority_mask_add = NIG_REG_P0_RX_COS5_PRIORITY_MASK;
2920 REG_WR(sc, nig_reg_rx_priority_mask_add, priority_mask);
2922 return ELINK_STATUS_OK;
2924 static void elink_update_mng(struct elink_params *params, uint32_t link_status)
2926 struct bxe_softc *sc = params->sc;
2928 REG_WR(sc, params->shmem_base +
2929 offsetof(struct shmem_region,
2930 port_mb[params->port].link_status), link_status);
2933 static void elink_update_pfc_nig(struct elink_params *params,
2934 struct elink_vars *vars,
2935 struct elink_nig_brb_pfc_port_params *nig_params)
2937 uint32_t xcm_mask = 0, ppp_enable = 0, pause_enable = 0, llfc_out_en = 0;
2938 uint32_t llfc_enable = 0, xcm_out_en = 0, hwpfc_enable = 0;
2939 uint32_t pkt_priority_to_cos = 0;
2940 struct bxe_softc *sc = params->sc;
2941 uint8_t port = params->port;
2943 int set_pfc = params->feature_config_flags &
2944 ELINK_FEATURE_CONFIG_PFC_ENABLED;
2945 ELINK_DEBUG_P0(sc, "updating pfc nig parameters\n");
2947 /* When NIG_LLH0_XCM_MASK_REG_LLHX_XCM_MASK_BCN bit is set
2948 * MAC control frames (that are not pause packets)
2949 * will be forwarded to the XCM.
2951 xcm_mask = REG_RD(sc, port ? NIG_REG_LLH1_XCM_MASK :
2952 NIG_REG_LLH0_XCM_MASK);
2953 /* NIG params will override non PFC params, since it's possible to
2954 * do transition from PFC to SAFC
2964 xcm_mask &= ~(port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2965 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2970 llfc_out_en = nig_params->llfc_out_en;
2971 llfc_enable = nig_params->llfc_enable;
2972 pause_enable = nig_params->pause_enable;
2973 } else /* Default non PFC mode - PAUSE */
2976 xcm_mask |= (port ? NIG_LLH1_XCM_MASK_REG_LLH1_XCM_MASK_BCN :
2977 NIG_LLH0_XCM_MASK_REG_LLH0_XCM_MASK_BCN);
2982 REG_WR(sc, port ? NIG_REG_BRB1_PAUSE_IN_EN :
2983 NIG_REG_BRB0_PAUSE_IN_EN, pause_enable);
2984 REG_WR(sc, port ? NIG_REG_LLFC_OUT_EN_1 :
2985 NIG_REG_LLFC_OUT_EN_0, llfc_out_en);
2986 REG_WR(sc, port ? NIG_REG_LLFC_ENABLE_1 :
2987 NIG_REG_LLFC_ENABLE_0, llfc_enable);
2988 REG_WR(sc, port ? NIG_REG_PAUSE_ENABLE_1 :
2989 NIG_REG_PAUSE_ENABLE_0, pause_enable);
2991 REG_WR(sc, port ? NIG_REG_PPP_ENABLE_1 :
2992 NIG_REG_PPP_ENABLE_0, ppp_enable);
2994 REG_WR(sc, port ? NIG_REG_LLH1_XCM_MASK :
2995 NIG_REG_LLH0_XCM_MASK, xcm_mask);
2997 REG_WR(sc, port ? NIG_REG_LLFC_EGRESS_SRC_ENABLE_1 :
2998 NIG_REG_LLFC_EGRESS_SRC_ENABLE_0, 0x7);
3000 /* Output enable for RX_XCM # IF */
3001 REG_WR(sc, port ? NIG_REG_XCM1_OUT_EN :
3002 NIG_REG_XCM0_OUT_EN, xcm_out_en);
3004 /* HW PFC TX enable */
3005 REG_WR(sc, port ? NIG_REG_P1_HWPFC_ENABLE :
3006 NIG_REG_P0_HWPFC_ENABLE, hwpfc_enable);
3010 pkt_priority_to_cos = nig_params->pkt_priority_to_cos;
3012 for (i = 0; i < nig_params->num_of_rx_cos_priority_mask; i++)
3013 elink_pfc_nig_rx_priority_mask(sc, i,
3014 nig_params->rx_cos_priority_mask[i], port);
3016 REG_WR(sc, port ? NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_1 :
3017 NIG_REG_LLFC_HIGH_PRIORITY_CLASSES_0,
3018 nig_params->llfc_high_priority_classes);
3020 REG_WR(sc, port ? NIG_REG_LLFC_LOW_PRIORITY_CLASSES_1 :
3021 NIG_REG_LLFC_LOW_PRIORITY_CLASSES_0,
3022 nig_params->llfc_low_priority_classes);
3024 REG_WR(sc, port ? NIG_REG_P1_PKT_PRIORITY_TO_COS :
3025 NIG_REG_P0_PKT_PRIORITY_TO_COS,
3026 pkt_priority_to_cos);
3029 elink_status_t elink_update_pfc(struct elink_params *params,
3030 struct elink_vars *vars,
3031 struct elink_nig_brb_pfc_port_params *pfc_params)
3033 /* The PFC and pause are orthogonal to one another, meaning when
3034 * PFC is enabled, the pause are disabled, and when PFC is
3035 * disabled, pause are set according to the pause result.
3038 struct bxe_softc *sc = params->sc;
3039 uint8_t bmac_loopback = (params->loopback_mode == ELINK_LOOPBACK_BMAC);
3041 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
3042 vars->link_status |= LINK_STATUS_PFC_ENABLED;
3044 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
3046 elink_update_mng(params, vars->link_status);
3048 /* Update NIG params */
3049 elink_update_pfc_nig(params, vars, pfc_params);
3052 return ELINK_STATUS_OK;
3054 ELINK_DEBUG_P0(sc, "About to update PFC in BMAC\n");
3056 if (CHIP_IS_E3(sc)) {
3057 if (vars->mac_type == ELINK_MAC_TYPE_XMAC)
3058 elink_update_pfc_xmac(params, vars, 0);
3060 val = REG_RD(sc, MISC_REG_RESET_REG_2);
3062 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port))
3064 ELINK_DEBUG_P0(sc, "About to update PFC in EMAC\n");
3065 elink_emac_enable(params, vars, 0);
3066 return ELINK_STATUS_OK;
3069 elink_update_pfc_bmac2(params, vars, bmac_loopback);
3071 elink_update_pfc_bmac1(params, vars);
3074 if ((params->feature_config_flags &
3075 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
3076 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
3078 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + params->port*4, val);
3080 return ELINK_STATUS_OK;
3083 static elink_status_t elink_bmac1_enable(struct elink_params *params,
3084 struct elink_vars *vars,
3087 struct bxe_softc *sc = params->sc;
3088 uint8_t port = params->port;
3089 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3090 NIG_REG_INGRESS_BMAC0_MEM;
3091 uint32_t wb_data[2];
3094 ELINK_DEBUG_P0(sc, "Enabling BigMAC1\n");
3099 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_XGXS_CONTROL,
3103 wb_data[0] = ((params->mac_addr[2] << 24) |
3104 (params->mac_addr[3] << 16) |
3105 (params->mac_addr[4] << 8) |
3106 params->mac_addr[5]);
3107 wb_data[1] = ((params->mac_addr[0] << 8) |
3108 params->mac_addr[1]);
3109 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_SOURCE_ADDR, wb_data, 2);
3115 ELINK_DEBUG_P0(sc, "enable bmac loopback\n");
3119 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_BMAC_CONTROL, wb_data, 2);
3122 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3124 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_MAX_SIZE, wb_data, 2);
3126 elink_update_pfc_bmac1(params, vars);
3129 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3131 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_MAX_SIZE, wb_data, 2);
3133 /* Set cnt max size */
3134 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3136 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_CNT_MAX_SIZE, wb_data, 2);
3138 /* Configure SAFC */
3139 wb_data[0] = 0x1000200;
3141 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_RX_LLFC_MSG_FLDS,
3143 #ifdef ELINK_INCLUDE_EMUL
3144 /* Fix for emulation */
3145 if (CHIP_REV_IS_EMUL(sc)) {
3146 wb_data[0] = 0xf000;
3148 REG_WR_DMAE(sc, bmac_addr + BIGMAC_REGISTER_TX_PAUSE_THRESHOLD,
3153 return ELINK_STATUS_OK;
3156 static elink_status_t elink_bmac2_enable(struct elink_params *params,
3157 struct elink_vars *vars,
3160 struct bxe_softc *sc = params->sc;
3161 uint8_t port = params->port;
3162 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3163 NIG_REG_INGRESS_BMAC0_MEM;
3164 uint32_t wb_data[2];
3166 ELINK_DEBUG_P0(sc, "Enabling BigMAC2\n");
3170 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_CONTROL, wb_data, 2);
3173 /* XGXS control: Reset phy HW, MDIO registers, PHY PLL and BMAC */
3176 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_BMAC_XGXS_CONTROL,
3182 wb_data[0] = ((params->mac_addr[2] << 24) |
3183 (params->mac_addr[3] << 16) |
3184 (params->mac_addr[4] << 8) |
3185 params->mac_addr[5]);
3186 wb_data[1] = ((params->mac_addr[0] << 8) |
3187 params->mac_addr[1]);
3188 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_SOURCE_ADDR,
3193 /* Configure SAFC */
3194 wb_data[0] = 0x1000200;
3196 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_LLFC_MSG_FLDS,
3201 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3203 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_RX_MAX_SIZE, wb_data, 2);
3207 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD;
3209 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_TX_MAX_SIZE, wb_data, 2);
3211 /* Set cnt max size */
3212 wb_data[0] = ELINK_ETH_MAX_JUMBO_PACKET_SIZE + ELINK_ETH_OVREHEAD - 2;
3214 REG_WR_DMAE(sc, bmac_addr + BIGMAC2_REGISTER_CNT_MAX_SIZE, wb_data, 2);
3216 elink_update_pfc_bmac2(params, vars, is_lb);
3218 return ELINK_STATUS_OK;
3221 static elink_status_t elink_bmac_enable(struct elink_params *params,
3222 struct elink_vars *vars,
3223 uint8_t is_lb, uint8_t reset_bmac)
3225 elink_status_t rc = ELINK_STATUS_OK;
3226 uint8_t port = params->port;
3227 struct bxe_softc *sc = params->sc;
3229 /* Reset and unreset the BigMac */
3231 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
3232 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3236 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_SET,
3237 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
3239 /* Enable access for bmac registers */
3240 REG_WR(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4, 0x1);
3242 /* Enable BMAC according to BMAC type*/
3244 rc = elink_bmac2_enable(params, vars, is_lb);
3246 rc = elink_bmac1_enable(params, vars, is_lb);
3247 REG_WR(sc, NIG_REG_XGXS_SERDES0_MODE_SEL + port*4, 0x1);
3248 REG_WR(sc, NIG_REG_XGXS_LANE_SEL_P0 + port*4, 0x0);
3249 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + port*4, 0x0);
3251 if ((params->feature_config_flags &
3252 ELINK_FEATURE_CONFIG_PFC_ENABLED) ||
3253 (vars->flow_ctrl & ELINK_FLOW_CTRL_TX))
3255 REG_WR(sc, NIG_REG_BMAC0_PAUSE_OUT_EN + port*4, val);
3256 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0x0);
3257 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0x0);
3258 REG_WR(sc, NIG_REG_EMAC0_PAUSE_OUT_EN + port*4, 0x0);
3259 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0x1);
3260 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0x1);
3262 vars->mac_type = ELINK_MAC_TYPE_BMAC;
3266 static void elink_set_bmac_rx(struct bxe_softc *sc, uint32_t chip_id, uint8_t port, uint8_t en)
3268 uint32_t bmac_addr = port ? NIG_REG_INGRESS_BMAC1_MEM :
3269 NIG_REG_INGRESS_BMAC0_MEM;
3270 uint32_t wb_data[2];
3271 uint32_t nig_bmac_enable = REG_RD(sc, NIG_REG_BMAC0_REGS_OUT_EN + port*4);
3274 bmac_addr += BIGMAC2_REGISTER_BMAC_CONTROL;
3276 bmac_addr += BIGMAC_REGISTER_BMAC_CONTROL;
3277 /* Only if the bmac is out of reset */
3278 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
3279 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port) &&
3281 /* Clear Rx Enable bit in BMAC_CONTROL register */
3282 REG_RD_DMAE(sc, bmac_addr, wb_data, 2);
3284 wb_data[0] |= ELINK_BMAC_CONTROL_RX_ENABLE;
3286 wb_data[0] &= ~ELINK_BMAC_CONTROL_RX_ENABLE;
3287 REG_WR_DMAE(sc, bmac_addr, wb_data, 2);
3292 static elink_status_t elink_pbf_update(struct elink_params *params, uint32_t flow_ctrl,
3293 uint32_t line_speed)
3295 struct bxe_softc *sc = params->sc;
3296 uint8_t port = params->port;
3297 uint32_t init_crd, crd;
3298 uint32_t count = 1000;
3301 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x1);
3303 /* Wait for init credit */
3304 init_crd = REG_RD(sc, PBF_REG_P0_INIT_CRD + port*4);
3305 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3306 ELINK_DEBUG_P2(sc, "init_crd 0x%x crd 0x%x\n", init_crd, crd);
3308 while ((init_crd != crd) && count) {
3310 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3313 crd = REG_RD(sc, PBF_REG_P0_CREDIT + port*8);
3314 if (init_crd != crd) {
3315 ELINK_DEBUG_P2(sc, "BUG! init_crd 0x%x != crd 0x%x\n",
3317 return ELINK_STATUS_ERROR;
3320 if (flow_ctrl & ELINK_FLOW_CTRL_RX ||
3321 line_speed == ELINK_SPEED_10 ||
3322 line_speed == ELINK_SPEED_100 ||
3323 line_speed == ELINK_SPEED_1000 ||
3324 line_speed == ELINK_SPEED_2500) {
3325 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 1);
3326 /* Update threshold */
3327 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, 0);
3328 /* Update init credit */
3329 init_crd = 778; /* (800-18-4) */
3332 uint32_t thresh = (ELINK_ETH_MAX_JUMBO_PACKET_SIZE +
3333 ELINK_ETH_OVREHEAD)/16;
3334 REG_WR(sc, PBF_REG_P0_PAUSE_ENABLE + port*4, 0);
3335 /* Update threshold */
3336 REG_WR(sc, PBF_REG_P0_ARB_THRSH + port*4, thresh);
3337 /* Update init credit */
3338 switch (line_speed) {
3339 case ELINK_SPEED_10000:
3340 init_crd = thresh + 553 - 22;
3343 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
3345 return ELINK_STATUS_ERROR;
3348 REG_WR(sc, PBF_REG_P0_INIT_CRD + port*4, init_crd);
3349 ELINK_DEBUG_P2(sc, "PBF updated to speed %d credit %d\n",
3350 line_speed, init_crd);
3352 /* Probe the credit changes */
3353 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x1);
3355 REG_WR(sc, PBF_REG_INIT_P0 + port*4, 0x0);
3358 REG_WR(sc, PBF_REG_DISABLE_NEW_TASK_PROC_P0 + port*4, 0x0);
3359 return ELINK_STATUS_OK;
3363 * elink_get_emac_base - retrive emac base address
3365 * @bp: driver handle
3366 * @mdc_mdio_access: access type
3369 * This function selects the MDC/MDIO access (through emac0 or
3370 * emac1) depend on the mdc_mdio_access, port, port swapped. Each
3371 * phy has a default access mode, which could also be overridden
3372 * by nvram configuration. This parameter, whether this is the
3373 * default phy configuration, or the nvram overrun
3374 * configuration, is passed here as mdc_mdio_access and selects
3375 * the emac_base for the CL45 read/writes operations
3377 static uint32_t elink_get_emac_base(struct bxe_softc *sc,
3378 uint32_t mdc_mdio_access, uint8_t port)
3380 uint32_t emac_base = 0;
3381 switch (mdc_mdio_access) {
3382 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_PHY_TYPE:
3384 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC0:
3385 if (REG_RD(sc, NIG_REG_PORT_SWAP))
3386 emac_base = GRCBASE_EMAC1;
3388 emac_base = GRCBASE_EMAC0;
3390 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1:
3391 if (REG_RD(sc, NIG_REG_PORT_SWAP))
3392 emac_base = GRCBASE_EMAC0;
3394 emac_base = GRCBASE_EMAC1;
3396 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH:
3397 emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
3399 case SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED:
3400 emac_base = (port) ? GRCBASE_EMAC0 : GRCBASE_EMAC1;
3409 /******************************************************************/
3410 /* CL22 access functions */
3411 /******************************************************************/
3412 static elink_status_t elink_cl22_write(struct bxe_softc *sc,
3413 struct elink_phy *phy,
3414 uint16_t reg, uint16_t val)
3418 elink_status_t rc = ELINK_STATUS_OK;
3419 /* Switch to CL22 */
3420 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3421 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3422 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3425 tmp = ((phy->addr << 21) | (reg << 16) | val |
3426 EMAC_MDIO_COMM_COMMAND_WRITE_22 |
3427 EMAC_MDIO_COMM_START_BUSY);
3428 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3430 for (i = 0; i < 50; i++) {
3433 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3434 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3439 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3440 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3441 rc = ELINK_STATUS_TIMEOUT;
3443 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3447 static elink_status_t elink_cl22_read(struct bxe_softc *sc,
3448 struct elink_phy *phy,
3449 uint16_t reg, uint16_t *ret_val)
3453 elink_status_t rc = ELINK_STATUS_OK;
3455 /* Switch to CL22 */
3456 mode = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE);
3457 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE,
3458 mode & ~EMAC_MDIO_MODE_CLAUSE_45);
3461 val = ((phy->addr << 21) | (reg << 16) |
3462 EMAC_MDIO_COMM_COMMAND_READ_22 |
3463 EMAC_MDIO_COMM_START_BUSY);
3464 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3466 for (i = 0; i < 50; i++) {
3469 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3470 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3471 *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA);
3476 if (val & EMAC_MDIO_COMM_START_BUSY) {
3477 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3480 rc = ELINK_STATUS_TIMEOUT;
3482 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_MODE, mode);
3486 /******************************************************************/
3487 /* CL45 access functions */
3488 /******************************************************************/
3489 static elink_status_t elink_cl45_read(struct bxe_softc *sc, struct elink_phy *phy,
3490 uint8_t devad, uint16_t reg, uint16_t *ret_val)
3494 elink_status_t rc = ELINK_STATUS_OK;
3496 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
3497 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
3498 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
3499 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
3502 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3503 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3504 EMAC_MDIO_STATUS_10MB);
3506 val = ((phy->addr << 21) | (devad << 16) | reg |
3507 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3508 EMAC_MDIO_COMM_START_BUSY);
3509 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3511 for (i = 0; i < 50; i++) {
3514 val = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3515 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3520 if (val & EMAC_MDIO_COMM_START_BUSY) {
3521 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3522 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3525 rc = ELINK_STATUS_TIMEOUT;
3528 val = ((phy->addr << 21) | (devad << 16) |
3529 EMAC_MDIO_COMM_COMMAND_READ_45 |
3530 EMAC_MDIO_COMM_START_BUSY);
3531 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, val);
3533 for (i = 0; i < 50; i++) {
3536 val = REG_RD(sc, phy->mdio_ctrl +
3537 EMAC_REG_EMAC_MDIO_COMM);
3538 if (!(val & EMAC_MDIO_COMM_START_BUSY)) {
3539 *ret_val = (uint16_t)(val & EMAC_MDIO_COMM_DATA);
3543 if (val & EMAC_MDIO_COMM_START_BUSY) {
3544 ELINK_DEBUG_P0(sc, "read phy register failed\n");
3545 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3548 rc = ELINK_STATUS_TIMEOUT;
3551 /* Work around for E3 A0 */
3552 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
3553 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
3554 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
3556 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
3560 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3561 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3562 EMAC_MDIO_STATUS_10MB);
3566 static elink_status_t elink_cl45_write(struct bxe_softc *sc, struct elink_phy *phy,
3567 uint8_t devad, uint16_t reg, uint16_t val)
3571 elink_status_t rc = ELINK_STATUS_OK;
3573 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_G) {
3574 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
3575 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
3576 elink_set_mdio_clk(sc, chip_id, phy->mdio_ctrl);
3579 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3580 elink_bits_en(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3581 EMAC_MDIO_STATUS_10MB);
3584 tmp = ((phy->addr << 21) | (devad << 16) | reg |
3585 EMAC_MDIO_COMM_COMMAND_ADDRESS |
3586 EMAC_MDIO_COMM_START_BUSY);
3587 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3589 for (i = 0; i < 50; i++) {
3592 tmp = REG_RD(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM);
3593 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3598 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3599 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3600 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3602 rc = ELINK_STATUS_TIMEOUT;
3605 tmp = ((phy->addr << 21) | (devad << 16) | val |
3606 EMAC_MDIO_COMM_COMMAND_WRITE_45 |
3607 EMAC_MDIO_COMM_START_BUSY);
3608 REG_WR(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_COMM, tmp);
3610 for (i = 0; i < 50; i++) {
3613 tmp = REG_RD(sc, phy->mdio_ctrl +
3614 EMAC_REG_EMAC_MDIO_COMM);
3615 if (!(tmp & EMAC_MDIO_COMM_START_BUSY)) {
3620 if (tmp & EMAC_MDIO_COMM_START_BUSY) {
3621 ELINK_DEBUG_P0(sc, "write phy register failed\n");
3622 elink_cb_event_log(sc, ELINK_LOG_ID_MDIO_ACCESS_TIMEOUT); // "MDC/MDIO access timeout\n"
3624 rc = ELINK_STATUS_TIMEOUT;
3627 /* Work around for E3 A0 */
3628 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA) {
3629 phy->flags ^= ELINK_FLAGS_DUMMY_READ;
3630 if (phy->flags & ELINK_FLAGS_DUMMY_READ) {
3632 elink_cl45_read(sc, phy, devad, 0xf, &temp_val);
3635 if (phy->flags & ELINK_FLAGS_MDC_MDIO_WA_B0)
3636 elink_bits_dis(sc, phy->mdio_ctrl + EMAC_REG_EMAC_MDIO_STATUS,
3637 EMAC_MDIO_STATUS_10MB);
3641 /******************************************************************/
3643 /******************************************************************/
3644 static uint8_t elink_eee_has_cap(struct elink_params *params)
3646 struct bxe_softc *sc = params->sc;
3648 if (REG_RD(sc, params->shmem2_base) <=
3649 offsetof(struct shmem2_region, eee_status[params->port]))
3655 static elink_status_t elink_eee_nvram_to_time(uint32_t nvram_mode, uint32_t *idle_timer)
3657 switch (nvram_mode) {
3658 case PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED:
3659 *idle_timer = ELINK_EEE_MODE_NVRAM_BALANCED_TIME;
3661 case PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE:
3662 *idle_timer = ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME;
3664 case PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY:
3665 *idle_timer = ELINK_EEE_MODE_NVRAM_LATENCY_TIME;
3672 return ELINK_STATUS_OK;
3675 static elink_status_t elink_eee_time_to_nvram(uint32_t idle_timer, uint32_t *nvram_mode)
3677 switch (idle_timer) {
3678 case ELINK_EEE_MODE_NVRAM_BALANCED_TIME:
3679 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_BALANCED;
3681 case ELINK_EEE_MODE_NVRAM_AGGRESSIVE_TIME:
3682 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_AGGRESSIVE;
3684 case ELINK_EEE_MODE_NVRAM_LATENCY_TIME:
3685 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_LOW_LATENCY;
3688 *nvram_mode = PORT_FEAT_CFG_EEE_POWER_MODE_DISABLED;
3692 return ELINK_STATUS_OK;
3695 static uint32_t elink_eee_calc_timer(struct elink_params *params)
3697 uint32_t eee_mode, eee_idle;
3698 struct bxe_softc *sc = params->sc;
3700 if (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) {
3701 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
3702 /* time value in eee_mode --> used directly*/
3703 eee_idle = params->eee_mode & ELINK_EEE_MODE_TIMER_MASK;
3705 /* hsi value in eee_mode --> time */
3706 if (elink_eee_nvram_to_time(params->eee_mode &
3707 ELINK_EEE_MODE_NVRAM_MASK,
3712 /* hsi values in nvram --> time*/
3713 eee_mode = ((REG_RD(sc, params->shmem_base +
3714 offsetof(struct shmem_region, dev_info.
3715 port_feature_config[params->port].
3717 PORT_FEAT_CFG_EEE_POWER_MODE_MASK) >>
3718 PORT_FEAT_CFG_EEE_POWER_MODE_SHIFT);
3720 if (elink_eee_nvram_to_time(eee_mode, &eee_idle))
3727 static elink_status_t elink_eee_set_timers(struct elink_params *params,
3728 struct elink_vars *vars)
3730 uint32_t eee_idle = 0, eee_mode;
3731 struct bxe_softc *sc = params->sc;
3733 eee_idle = elink_eee_calc_timer(params);
3736 REG_WR(sc, MISC_REG_CPMU_LP_IDLE_THR_P0 + (params->port << 2),
3738 } else if ((params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI) &&
3739 (params->eee_mode & ELINK_EEE_MODE_OVERRIDE_NVRAM) &&
3740 (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME)) {
3741 ELINK_DEBUG_P0(sc, "Error: Tx LPI is enabled with timer 0\n");
3742 return ELINK_STATUS_ERROR;
3745 vars->eee_status &= ~(SHMEM_EEE_TIMER_MASK | SHMEM_EEE_TIME_OUTPUT_BIT);
3746 if (params->eee_mode & ELINK_EEE_MODE_OUTPUT_TIME) {
3747 /* eee_idle in 1u --> eee_status in 16u */
3749 vars->eee_status |= (eee_idle & SHMEM_EEE_TIMER_MASK) |
3750 SHMEM_EEE_TIME_OUTPUT_BIT;
3752 if (elink_eee_time_to_nvram(eee_idle, &eee_mode))
3753 return ELINK_STATUS_ERROR;
3754 vars->eee_status |= eee_mode;
3757 return ELINK_STATUS_OK;
3760 static elink_status_t elink_eee_initial_config(struct elink_params *params,
3761 struct elink_vars *vars, uint8_t mode)
3763 vars->eee_status |= ((uint32_t) mode) << SHMEM_EEE_SUPPORTED_SHIFT;
3765 /* Propogate params' bits --> vars (for migration exposure) */
3766 if (params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)
3767 vars->eee_status |= SHMEM_EEE_LPI_REQUESTED_BIT;
3769 vars->eee_status &= ~SHMEM_EEE_LPI_REQUESTED_BIT;
3771 if (params->eee_mode & ELINK_EEE_MODE_ADV_LPI)
3772 vars->eee_status |= SHMEM_EEE_REQUESTED_BIT;
3774 vars->eee_status &= ~SHMEM_EEE_REQUESTED_BIT;
3776 return elink_eee_set_timers(params, vars);
3779 static elink_status_t elink_eee_disable(struct elink_phy *phy,
3780 struct elink_params *params,
3781 struct elink_vars *vars)
3783 struct bxe_softc *sc = params->sc;
3785 /* Make Certain LPI is disabled */
3786 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2), 0);
3788 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, 0x0);
3790 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3792 return ELINK_STATUS_OK;
3795 static elink_status_t elink_eee_advertise(struct elink_phy *phy,
3796 struct elink_params *params,
3797 struct elink_vars *vars, uint8_t modes)
3799 struct bxe_softc *sc = params->sc;
3802 /* Mask events preventing LPI generation */
3803 REG_WR(sc, MISC_REG_CPMU_LP_MASK_EXT_P0 + (params->port << 2), 0xfc20);
3805 if (modes & SHMEM_EEE_10G_ADV) {
3806 ELINK_DEBUG_P0(sc, "Advertise 10GBase-T EEE\n");
3809 if (modes & SHMEM_EEE_1G_ADV) {
3810 ELINK_DEBUG_P0(sc, "Advertise 1GBase-T EEE\n");
3814 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, val);
3816 vars->eee_status &= ~SHMEM_EEE_ADV_STATUS_MASK;
3817 vars->eee_status |= (modes << SHMEM_EEE_ADV_STATUS_SHIFT);
3819 return ELINK_STATUS_OK;
3822 static void elink_update_mng_eee(struct elink_params *params, uint32_t eee_status)
3824 struct bxe_softc *sc = params->sc;
3826 if (elink_eee_has_cap(params))
3827 REG_WR(sc, params->shmem2_base +
3828 offsetof(struct shmem2_region,
3829 eee_status[params->port]), eee_status);
3832 static void elink_eee_an_resolve(struct elink_phy *phy,
3833 struct elink_params *params,
3834 struct elink_vars *vars)
3836 struct bxe_softc *sc = params->sc;
3837 uint16_t adv = 0, lp = 0;
3838 uint32_t lp_adv = 0;
3841 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_EEE_ADV, &adv);
3842 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_LP_EEE_ADV, &lp);
3845 lp_adv |= SHMEM_EEE_100M_ADV;
3847 if (vars->line_speed == ELINK_SPEED_100)
3849 ELINK_DEBUG_P0(sc, "EEE negotiated - 100M\n");
3853 lp_adv |= SHMEM_EEE_1G_ADV;
3855 if (vars->line_speed == ELINK_SPEED_1000)
3857 ELINK_DEBUG_P0(sc, "EEE negotiated - 1G\n");
3861 lp_adv |= SHMEM_EEE_10G_ADV;
3863 if (vars->line_speed == ELINK_SPEED_10000)
3865 ELINK_DEBUG_P0(sc, "EEE negotiated - 10G\n");
3869 vars->eee_status &= ~SHMEM_EEE_LP_ADV_STATUS_MASK;
3870 vars->eee_status |= (lp_adv << SHMEM_EEE_LP_ADV_STATUS_SHIFT);
3873 ELINK_DEBUG_P0(sc, "EEE is active\n");
3874 vars->eee_status |= SHMEM_EEE_ACTIVE_BIT;
3878 /******************************************************************/
3879 /* BSC access functions from E3 */
3880 /******************************************************************/
3881 static void elink_bsc_module_sel(struct elink_params *params)
3884 uint32_t board_cfg, sfp_ctrl;
3885 uint32_t i2c_pins[I2C_SWITCH_WIDTH], i2c_val[I2C_SWITCH_WIDTH];
3886 struct bxe_softc *sc = params->sc;
3887 uint8_t port = params->port;
3888 /* Read I2C output PINs */
3889 board_cfg = REG_RD(sc, params->shmem_base +
3890 offsetof(struct shmem_region,
3891 dev_info.shared_hw_config.board));
3892 i2c_pins[I2C_BSC0] = board_cfg & SHARED_HW_CFG_E3_I2C_MUX0_MASK;
3893 i2c_pins[I2C_BSC1] = (board_cfg & SHARED_HW_CFG_E3_I2C_MUX1_MASK) >>
3894 SHARED_HW_CFG_E3_I2C_MUX1_SHIFT;
3896 /* Read I2C output value */
3897 sfp_ctrl = REG_RD(sc, params->shmem_base +
3898 offsetof(struct shmem_region,
3899 dev_info.port_hw_config[port].e3_cmn_pin_cfg));
3900 i2c_val[I2C_BSC0] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX0_MASK) > 0;
3901 i2c_val[I2C_BSC1] = (sfp_ctrl & PORT_HW_CFG_E3_I2C_MUX1_MASK) > 0;
3902 ELINK_DEBUG_P0(sc, "Setting BSC switch\n");
3903 for (idx = 0; idx < I2C_SWITCH_WIDTH; idx++)
3904 elink_set_cfg_pin(sc, i2c_pins[idx], i2c_val[idx]);
3907 static elink_status_t elink_bsc_read(struct bxe_softc *sc,
3912 uint32_t *data_array)
3915 elink_status_t rc = ELINK_STATUS_OK;
3917 if (xfer_cnt > 16) {
3918 ELINK_DEBUG_P1(sc, "invalid xfer_cnt %d. Max is 16 bytes\n",
3920 return ELINK_STATUS_ERROR;
3923 xfer_cnt = 16 - lc_addr;
3925 /* Enable the engine */
3926 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3927 val |= MCPR_IMC_COMMAND_ENABLE;
3928 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3930 /* Program slave device ID */
3931 val = (sl_devid << 16) | sl_addr;
3932 REG_WR(sc, MCP_REG_MCPR_IMC_SLAVE_CONTROL, val);
3934 /* Start xfer with 0 byte to update the address pointer ???*/
3935 val = (MCPR_IMC_COMMAND_ENABLE) |
3936 (MCPR_IMC_COMMAND_WRITE_OP <<
3937 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3938 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) | (0);
3939 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3941 /* Poll for completion */
3943 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3944 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3946 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3948 ELINK_DEBUG_P1(sc, "wr 0 byte timed out after %d try\n",
3950 rc = ELINK_STATUS_TIMEOUT;
3954 if (rc == ELINK_STATUS_TIMEOUT)
3957 /* Start xfer with read op */
3958 val = (MCPR_IMC_COMMAND_ENABLE) |
3959 (MCPR_IMC_COMMAND_READ_OP <<
3960 MCPR_IMC_COMMAND_OPERATION_BITSHIFT) |
3961 (lc_addr << MCPR_IMC_COMMAND_TRANSFER_ADDRESS_BITSHIFT) |
3963 REG_WR(sc, MCP_REG_MCPR_IMC_COMMAND, val);
3965 /* Poll for completion */
3967 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3968 while (((val >> MCPR_IMC_COMMAND_IMC_STATUS_BITSHIFT) & 0x3) != 1) {
3970 val = REG_RD(sc, MCP_REG_MCPR_IMC_COMMAND);
3972 ELINK_DEBUG_P1(sc, "rd op timed out after %d try\n", i);
3973 rc = ELINK_STATUS_TIMEOUT;
3977 if (rc == ELINK_STATUS_TIMEOUT)
3980 for (i = (lc_addr >> 2); i < 4; i++) {
3981 data_array[i] = REG_RD(sc, (MCP_REG_MCPR_IMC_DATAREG0 + i*4));
3983 data_array[i] = ((data_array[i] & 0x000000ff) << 24) |
3984 ((data_array[i] & 0x0000ff00) << 8) |
3985 ((data_array[i] & 0x00ff0000) >> 8) |
3986 ((data_array[i] & 0xff000000) >> 24);
3992 static void elink_cl45_read_or_write(struct bxe_softc *sc, struct elink_phy *phy,
3993 uint8_t devad, uint16_t reg, uint16_t or_val)
3996 elink_cl45_read(sc, phy, devad, reg, &val);
3997 elink_cl45_write(sc, phy, devad, reg, val | or_val);
4000 static void elink_cl45_read_and_write(struct bxe_softc *sc,
4001 struct elink_phy *phy,
4002 uint8_t devad, uint16_t reg, uint16_t and_val)
4005 elink_cl45_read(sc, phy, devad, reg, &val);
4006 elink_cl45_write(sc, phy, devad, reg, val & and_val);
4009 elink_status_t elink_phy_read(struct elink_params *params, uint8_t phy_addr,
4010 uint8_t devad, uint16_t reg, uint16_t *ret_val)
4013 /* Probe for the phy according to the given phy_addr, and execute
4014 * the read request on it
4016 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
4017 if (params->phy[phy_index].addr == phy_addr) {
4018 return elink_cl45_read(params->sc,
4019 ¶ms->phy[phy_index], devad,
4023 return ELINK_STATUS_ERROR;
4026 elink_status_t elink_phy_write(struct elink_params *params, uint8_t phy_addr,
4027 uint8_t devad, uint16_t reg, uint16_t val)
4030 /* Probe for the phy according to the given phy_addr, and execute
4031 * the write request on it
4033 for (phy_index = 0; phy_index < params->num_phys; phy_index++) {
4034 if (params->phy[phy_index].addr == phy_addr) {
4035 return elink_cl45_write(params->sc,
4036 ¶ms->phy[phy_index], devad,
4040 return ELINK_STATUS_ERROR;
4043 static uint8_t elink_get_warpcore_lane(struct elink_phy *phy,
4044 struct elink_params *params)
4047 struct bxe_softc *sc = params->sc;
4048 uint32_t path_swap, path_swap_ovr;
4052 port = params->port;
4054 if (elink_is_4_port_mode(sc)) {
4055 uint32_t port_swap, port_swap_ovr;
4057 /* Figure out path swap value */
4058 path_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP_OVWR);
4059 if (path_swap_ovr & 0x1)
4060 path_swap = (path_swap_ovr & 0x2);
4062 path_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PATH_SWAP);
4067 /* Figure out port swap value */
4068 port_swap_ovr = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP_OVWR);
4069 if (port_swap_ovr & 0x1)
4070 port_swap = (port_swap_ovr & 0x2);
4072 port_swap = REG_RD(sc, MISC_REG_FOUR_PORT_PORT_SWAP);
4077 lane = (port<<1) + path;
4078 } else { /* Two port mode - no port swap */
4080 /* Figure out path swap value */
4082 REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP_OVWR);
4083 if (path_swap_ovr & 0x1) {
4084 path_swap = (path_swap_ovr & 0x2);
4087 REG_RD(sc, MISC_REG_TWO_PORT_PATH_SWAP);
4098 static void elink_set_aer_mmd(struct elink_params *params,
4099 struct elink_phy *phy)
4102 uint16_t offset, aer_val;
4103 struct bxe_softc *sc = params->sc;
4104 ser_lane = ((params->lane_config &
4105 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
4106 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
4108 offset = (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) ?
4109 (phy->addr + ser_lane) : 0;
4111 if (USES_WARPCORE(sc)) {
4112 aer_val = elink_get_warpcore_lane(phy, params);
4113 /* In Dual-lane mode, two lanes are joined together,
4114 * so in order to configure them, the AER broadcast method is
4116 * 0x200 is the broadcast address for lanes 0,1
4117 * 0x201 is the broadcast address for lanes 2,3
4119 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4120 aer_val = (aer_val >> 1) | 0x200;
4121 } else if (CHIP_IS_E2(sc))
4122 aer_val = 0x3800 + offset - 1;
4124 aer_val = 0x3800 + offset;
4126 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4127 MDIO_AER_BLOCK_AER_REG, aer_val);
4131 /******************************************************************/
4132 /* Internal phy section */
4133 /******************************************************************/
4135 static void elink_set_serdes_access(struct bxe_softc *sc, uint8_t port)
4137 uint32_t emac_base = (port) ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
4140 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 1);
4141 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245f8000);
4143 REG_WR(sc, emac_base + EMAC_REG_EMAC_MDIO_COMM, 0x245d000f);
4146 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_ST + port*0x10, 0);
4149 static void elink_serdes_deassert(struct bxe_softc *sc, uint8_t port)
4153 ELINK_DEBUG_P0(sc, "elink_serdes_deassert\n");
4155 val = ELINK_SERDES_RESET_BITS << (port*16);
4157 /* Reset and unreset the SerDes/XGXS */
4158 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
4160 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
4162 elink_set_serdes_access(sc, port);
4164 REG_WR(sc, NIG_REG_SERDES0_CTRL_MD_DEVAD + port*0x10,
4165 ELINK_DEFAULT_PHY_DEV_ADDR);
4168 static void elink_xgxs_specific_func(struct elink_phy *phy,
4169 struct elink_params *params,
4172 struct bxe_softc *sc = params->sc;
4174 case ELINK_PHY_INIT:
4175 /* Set correct devad */
4176 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_ST + params->port*0x18, 0);
4177 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + params->port*0x18,
4183 static void elink_xgxs_deassert(struct elink_params *params)
4185 struct bxe_softc *sc = params->sc;
4188 ELINK_DEBUG_P0(sc, "elink_xgxs_deassert\n");
4189 port = params->port;
4191 val = ELINK_XGXS_RESET_BITS << (port*16);
4193 /* Reset and unreset the SerDes/XGXS */
4194 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR, val);
4196 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_SET, val);
4197 elink_xgxs_specific_func(¶ms->phy[ELINK_INT_PHY], params,
4201 static void elink_calc_ieee_aneg_adv(struct elink_phy *phy,
4202 struct elink_params *params, uint16_t *ieee_fc)
4204 struct bxe_softc *sc = params->sc;
4205 *ieee_fc = MDIO_COMBO_IEEE0_AUTO_NEG_ADV_FULL_DUPLEX;
4206 /* Resolve pause mode and advertisement Please refer to Table
4207 * 28B-3 of the 802.3ab-1999 spec
4210 switch (phy->req_flow_ctrl) {
4211 case ELINK_FLOW_CTRL_AUTO:
4212 switch (params->req_fc_auto_adv) {
4213 case ELINK_FLOW_CTRL_BOTH:
4214 case ELINK_FLOW_CTRL_RX:
4215 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4217 case ELINK_FLOW_CTRL_TX:
4219 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4225 case ELINK_FLOW_CTRL_TX:
4226 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
4229 case ELINK_FLOW_CTRL_RX:
4230 case ELINK_FLOW_CTRL_BOTH:
4231 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
4234 case ELINK_FLOW_CTRL_NONE:
4236 *ieee_fc |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_NONE;
4239 ELINK_DEBUG_P1(sc, "ieee_fc = 0x%x\n", *ieee_fc);
4242 static void set_phy_vars(struct elink_params *params,
4243 struct elink_vars *vars)
4245 struct bxe_softc *sc = params->sc;
4246 uint8_t actual_phy_idx, phy_index, link_cfg_idx;
4247 uint8_t phy_config_swapped = params->multi_phy_config &
4248 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
4249 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
4251 link_cfg_idx = ELINK_LINK_CONFIG_IDX(phy_index);
4252 actual_phy_idx = phy_index;
4253 if (phy_config_swapped) {
4254 if (phy_index == ELINK_EXT_PHY1)
4255 actual_phy_idx = ELINK_EXT_PHY2;
4256 else if (phy_index == ELINK_EXT_PHY2)
4257 actual_phy_idx = ELINK_EXT_PHY1;
4259 params->phy[actual_phy_idx].req_flow_ctrl =
4260 params->req_flow_ctrl[link_cfg_idx];
4262 params->phy[actual_phy_idx].req_line_speed =
4263 params->req_line_speed[link_cfg_idx];
4265 params->phy[actual_phy_idx].speed_cap_mask =
4266 params->speed_cap_mask[link_cfg_idx];
4268 params->phy[actual_phy_idx].req_duplex =
4269 params->req_duplex[link_cfg_idx];
4271 if (params->req_line_speed[link_cfg_idx] ==
4272 ELINK_SPEED_AUTO_NEG)
4273 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
4275 ELINK_DEBUG_P3(sc, "req_flow_ctrl %x, req_line_speed %x,"
4276 " speed_cap_mask %x\n",
4277 params->phy[actual_phy_idx].req_flow_ctrl,
4278 params->phy[actual_phy_idx].req_line_speed,
4279 params->phy[actual_phy_idx].speed_cap_mask);
4283 static void elink_ext_phy_set_pause(struct elink_params *params,
4284 struct elink_phy *phy,
4285 struct elink_vars *vars)
4288 struct bxe_softc *sc = params->sc;
4289 /* Read modify write pause advertizing */
4290 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, &val);
4292 val &= ~MDIO_AN_REG_ADV_PAUSE_BOTH;
4294 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
4295 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
4296 if ((vars->ieee_fc &
4297 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
4298 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
4299 val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
4301 if ((vars->ieee_fc &
4302 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
4303 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
4304 val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
4306 ELINK_DEBUG_P1(sc, "Ext phy AN advertize 0x%x\n", val);
4307 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV_PAUSE, val);
4310 static void elink_pause_resolve(struct elink_phy *phy,
4311 struct elink_params *params,
4312 struct elink_vars *vars,
4313 uint32_t pause_result)
4315 struct bxe_softc *sc = params->sc;
4317 switch (pause_result) { /* ASYM P ASYM P */
4318 case 0xb: /* 1 0 1 1 */
4319 ELINK_DEBUG_P0(sc, "Flow Control: TX only\n");
4320 vars->flow_ctrl = ELINK_FLOW_CTRL_TX;
4323 case 0xe: /* 1 1 1 0 */
4324 ELINK_DEBUG_P0(sc, "Flow Control: RX only\n");
4325 vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
4328 case 0x5: /* 0 1 0 1 */
4329 case 0x7: /* 0 1 1 1 */
4330 case 0xd: /* 1 1 0 1 */
4331 case 0xf: /* 1 1 1 1 */
4332 /* If the user selected to advertise RX ONLY,
4333 * although we advertised both, need to enable
4336 if (params->req_fc_auto_adv == ELINK_FLOW_CTRL_BOTH) {
4337 ELINK_DEBUG_P0(sc, "Flow Control: RX & TX\n");
4338 vars->flow_ctrl = ELINK_FLOW_CTRL_BOTH;
4340 ELINK_DEBUG_P0(sc, "Flow Control: RX only\n");
4341 vars->flow_ctrl = ELINK_FLOW_CTRL_RX;
4345 ELINK_DEBUG_P0(sc, "Flow Control: None\n");
4346 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4349 if (pause_result & (1<<0))
4350 vars->link_status |= LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE;
4351 if (pause_result & (1<<1))
4352 vars->link_status |= LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE;
4356 static void elink_ext_phy_update_adv_fc(struct elink_phy *phy,
4357 struct elink_params *params,
4358 struct elink_vars *vars)
4360 uint16_t ld_pause; /* local */
4361 uint16_t lp_pause; /* link partner */
4362 uint16_t pause_result;
4363 struct bxe_softc *sc = params->sc;
4364 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) {
4365 elink_cl22_read(sc, phy, 0x4, &ld_pause);
4366 elink_cl22_read(sc, phy, 0x5, &lp_pause);
4367 } else if (CHIP_IS_E3(sc) &&
4368 ELINK_SINGLE_MEDIA_DIRECT(params)) {
4369 uint8_t lane = elink_get_warpcore_lane(phy, params);
4370 uint16_t gp_status, gp_mask;
4371 elink_cl45_read(sc, phy,
4372 MDIO_AN_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_4,
4374 gp_mask = (MDIO_WC_REG_GP2_STATUS_GP_2_4_CL73_AN_CMPL |
4375 MDIO_WC_REG_GP2_STATUS_GP_2_4_CL37_LP_AN_CAP) <<
4377 if ((gp_status & gp_mask) == gp_mask) {
4378 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4379 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
4380 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4381 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
4383 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4384 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
4385 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
4386 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
4387 ld_pause = ((ld_pause &
4388 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
4390 lp_pause = ((lp_pause &
4391 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
4395 elink_cl45_read(sc, phy,
4397 MDIO_AN_REG_ADV_PAUSE, &ld_pause);
4398 elink_cl45_read(sc, phy,
4400 MDIO_AN_REG_LP_AUTO_NEG, &lp_pause);
4402 pause_result = (ld_pause &
4403 MDIO_AN_REG_ADV_PAUSE_MASK) >> 8;
4404 pause_result |= (lp_pause &
4405 MDIO_AN_REG_ADV_PAUSE_MASK) >> 10;
4406 ELINK_DEBUG_P1(sc, "Ext PHY pause result 0x%x\n", pause_result);
4407 elink_pause_resolve(phy, params, vars, pause_result);
4411 static uint8_t elink_ext_phy_resolve_fc(struct elink_phy *phy,
4412 struct elink_params *params,
4413 struct elink_vars *vars)
4416 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
4417 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
4418 /* Update the advertised flow-controled of LD/LP in AN */
4419 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
4420 elink_ext_phy_update_adv_fc(phy, params, vars);
4421 /* But set the flow-control result as the requested one */
4422 vars->flow_ctrl = phy->req_flow_ctrl;
4423 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
4424 vars->flow_ctrl = params->req_fc_auto_adv;
4425 else if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
4427 elink_ext_phy_update_adv_fc(phy, params, vars);
4431 /******************************************************************/
4432 /* Warpcore section */
4433 /******************************************************************/
4434 /* The init_internal_warpcore should mirror the xgxs,
4435 * i.e. reset the lane (if needed), set aer for the
4436 * init configuration, and set/clear SGMII flag. Internal
4437 * phy init is done purely in phy_init stage.
4439 #define WC_TX_DRIVER(post2, idriver, ipre, ifir) \
4440 ((post2 << MDIO_WC_REG_TX0_TX_DRIVER_POST2_COEFF_OFFSET) | \
4441 (idriver << MDIO_WC_REG_TX0_TX_DRIVER_IDRIVER_OFFSET) | \
4442 (ipre << MDIO_WC_REG_TX0_TX_DRIVER_IPRE_DRIVER_OFFSET) | \
4443 (ifir << MDIO_WC_REG_TX0_TX_DRIVER_IFIR_OFFSET))
4445 #define WC_TX_FIR(post, main, pre) \
4446 ((post << MDIO_WC_REG_TX_FIR_TAP_POST_TAP_OFFSET) | \
4447 (main << MDIO_WC_REG_TX_FIR_TAP_MAIN_TAP_OFFSET) | \
4448 (pre << MDIO_WC_REG_TX_FIR_TAP_PRE_TAP_OFFSET))
4450 static void elink_update_link_attr(struct elink_params *params, uint32_t link_attr)
4452 struct bxe_softc *sc = params->sc;
4454 if (SHMEM2_HAS(sc, link_attr_sync))
4455 REG_WR(sc, params->shmem2_base +
4456 offsetof(struct shmem2_region,
4457 link_attr_sync[params->port]), link_attr);
4460 static void elink_warpcore_enable_AN_KR2(struct elink_phy *phy,
4461 struct elink_params *params,
4462 struct elink_vars *vars)
4464 struct bxe_softc *sc = params->sc;
4466 static struct elink_reg_set reg_set[] = {
4467 /* Step 1 - Program the TX/RX alignment markers */
4468 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0xa157},
4469 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xcbe2},
4470 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0x7537},
4471 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0xa157},
4472 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xcbe2},
4473 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0x7537},
4474 /* Step 2 - Configure the NP registers */
4475 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000a},
4476 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6400},
4477 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0620},
4478 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0157},
4479 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x6464},
4480 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x3150},
4481 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x3150},
4482 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0157},
4483 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0620}
4485 ELINK_DEBUG_P0(sc, "Enabling 20G-KR2\n");
4487 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4488 MDIO_WC_REG_CL49_USERB0_CTRL, (3<<6));
4490 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4491 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4494 /* Start KR2 work-around timer which handles BCM8073 link-parner */
4495 params->link_attr_sync |= LINK_ATTR_SYNC_KR2_ENABLE;
4496 elink_update_link_attr(params, params->link_attr_sync);
4499 static void elink_disable_kr2(struct elink_params *params,
4500 struct elink_vars *vars,
4501 struct elink_phy *phy)
4503 struct bxe_softc *sc = params->sc;
4505 static struct elink_reg_set reg_set[] = {
4506 /* Step 1 - Program the TX/RX alignment markers */
4507 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL5, 0x7690},
4508 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL7, 0xe647},
4509 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL6, 0xc4f0},
4510 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_TX_CTRL9, 0x7690},
4511 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL11, 0xe647},
4512 {MDIO_WC_DEVAD, MDIO_WC_REG_CL82_USERB1_RX_CTRL10, 0xc4f0},
4513 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_USERB0_CTRL, 0x000c},
4514 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL1, 0x6000},
4515 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CTRL3, 0x0000},
4516 {MDIO_WC_DEVAD, MDIO_WC_REG_CL73_BAM_CODE_FIELD, 0x0002},
4517 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI1, 0x0000},
4518 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI2, 0x0af7},
4519 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_OUI3, 0x0af7},
4520 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_BAM_CODE, 0x0002},
4521 {MDIO_WC_DEVAD, MDIO_WC_REG_ETA_CL73_LD_UD_CODE, 0x0000}
4523 ELINK_DEBUG_P0(sc, "Disabling 20G-KR2\n");
4525 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4526 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4528 params->link_attr_sync &= ~LINK_ATTR_SYNC_KR2_ENABLE;
4529 elink_update_link_attr(params, params->link_attr_sync);
4531 vars->check_kr2_recovery_cnt = ELINK_CHECK_KR2_RECOVERY_CNT;
4534 static void elink_warpcore_set_lpi_passthrough(struct elink_phy *phy,
4535 struct elink_params *params)
4537 struct bxe_softc *sc = params->sc;
4539 ELINK_DEBUG_P0(sc, "Configure WC for LPI pass through\n");
4540 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4541 MDIO_WC_REG_EEE_COMBO_CONTROL0, 0x7c);
4542 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4543 MDIO_WC_REG_DIGITAL4_MISC5, 0xc000);
4546 static void elink_warpcore_restart_AN_KR(struct elink_phy *phy,
4547 struct elink_params *params)
4549 /* Restart autoneg on the leading lane only */
4550 struct bxe_softc *sc = params->sc;
4551 uint16_t lane = elink_get_warpcore_lane(phy, params);
4552 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4553 MDIO_AER_BLOCK_AER_REG, lane);
4554 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4555 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
4558 elink_set_aer_mmd(params, phy);
4561 static void elink_warpcore_enable_AN_KR(struct elink_phy *phy,
4562 struct elink_params *params,
4563 struct elink_vars *vars) {
4564 uint16_t lane, i, cl72_ctrl, an_adv = 0, val;
4565 uint32_t wc_lane_config;
4566 struct bxe_softc *sc = params->sc;
4567 static struct elink_reg_set reg_set[] = {
4568 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
4569 {MDIO_PMA_DEVAD, MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0x0},
4570 {MDIO_WC_DEVAD, MDIO_WC_REG_RX66_CONTROL, 0x7415},
4571 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x6190},
4572 /* Disable Autoneg: re-enable it after adv is done. */
4573 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0},
4574 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2},
4575 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0},
4577 ELINK_DEBUG_P0(sc, "Enable Auto Negotiation for KR\n");
4578 /* Set to default registers that may be overriden by 10G force */
4579 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4580 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4583 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4584 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &cl72_ctrl);
4585 cl72_ctrl &= 0x08ff;
4586 cl72_ctrl |= 0x3800;
4587 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4588 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, cl72_ctrl);
4590 /* Check adding advertisement for 1G KX */
4591 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
4592 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
4593 (vars->line_speed == ELINK_SPEED_1000)) {
4594 uint16_t addr = MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2;
4597 /* Enable CL37 1G Parallel Detect */
4598 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD, addr, 0x1);
4599 ELINK_DEBUG_P0(sc, "Advertize 1G\n");
4601 if (((vars->line_speed == ELINK_SPEED_AUTO_NEG) &&
4602 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
4603 (vars->line_speed == ELINK_SPEED_10000)) {
4604 /* Check adding advertisement for 10G KR */
4606 /* Enable 10G Parallel Detect */
4607 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4608 MDIO_AER_BLOCK_AER_REG, 0);
4610 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4611 MDIO_WC_REG_PAR_DET_10G_CTRL, 1);
4612 elink_set_aer_mmd(params, phy);
4613 ELINK_DEBUG_P0(sc, "Advertize 10G\n");
4616 /* Set Transmit PMD settings */
4617 lane = elink_get_warpcore_lane(phy, params);
4618 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4619 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4620 WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
4621 /* Configure the next lane if dual mode */
4622 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
4623 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4624 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*(lane+1),
4625 WC_TX_DRIVER(0x02, 0x06, 0x09, 0));
4626 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4627 MDIO_WC_REG_CL72_USERB0_CL72_OS_DEF_CTRL,
4629 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4630 MDIO_WC_REG_CL72_USERB0_CL72_2P5_DEF_CTRL,
4633 /* Advertised speeds */
4634 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4635 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, an_adv);
4637 /* Advertised and set FEC (Forward Error Correction) */
4638 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4639 MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT2,
4640 (MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_ABILITY |
4641 MDIO_WC_REG_AN_IEEE1BLK_AN_ADV2_FEC_REQ));
4643 /* Enable CL37 BAM */
4644 if (REG_RD(sc, params->shmem_base +
4645 offsetof(struct shmem_region, dev_info.
4646 port_hw_config[params->port].default_cfg)) &
4647 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
4648 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4649 MDIO_WC_REG_DIGITAL6_MP5_NEXTPAGECTRL,
4651 ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR\n");
4654 /* Advertise pause */
4655 elink_ext_phy_set_pause(params, phy, vars);
4656 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
4657 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4658 MDIO_WC_REG_DIGITAL5_MISC7, 0x100);
4660 /* Over 1G - AN local device user page 1 */
4661 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4662 MDIO_WC_REG_DIGITAL3_UP1, 0x1f);
4664 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
4665 (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
4666 (phy->req_line_speed == ELINK_SPEED_20000)) {
4668 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4669 MDIO_AER_BLOCK_AER_REG, lane);
4671 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4672 MDIO_WC_REG_RX1_PCI_CTRL + (0x10*lane),
4675 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4676 MDIO_WC_REG_XGXS_X2_CONTROL3, 0x7);
4677 elink_set_aer_mmd(params, phy);
4679 elink_warpcore_enable_AN_KR2(phy, params, vars);
4681 /* Enable Auto-Detect to support 1G over CL37 as well */
4682 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4683 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0x10);
4684 wc_lane_config = REG_RD(sc, params->shmem_base +
4685 offsetof(struct shmem_region, dev_info.
4686 shared_hw_config.wc_lane_config));
4687 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4688 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4), &val);
4689 /* Force cl48 sync_status LOW to avoid getting stuck in CL73
4690 * parallel-detect loop when CL73 and CL37 are enabled.
4694 /* Restore Polarity settings in case it was run over by
4695 * previous link owner
4697 if (wc_lane_config &
4698 (SHARED_HW_CFG_RX_LANE0_POL_FLIP_ENABLED << lane))
4702 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4703 MDIO_WC_REG_RX0_PCI_CTRL + (lane << 4),
4706 elink_disable_kr2(params, vars, phy);
4709 /* Enable Autoneg: only on the main lane */
4710 elink_warpcore_restart_AN_KR(phy, params);
4713 static void elink_warpcore_set_10G_KR(struct elink_phy *phy,
4714 struct elink_params *params,
4715 struct elink_vars *vars)
4717 struct bxe_softc *sc = params->sc;
4718 uint16_t val16, i, lane;
4719 static struct elink_reg_set reg_set[] = {
4720 /* Disable Autoneg */
4721 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, 0x7},
4722 {MDIO_WC_DEVAD, MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL,
4724 {MDIO_AN_DEVAD, MDIO_WC_REG_AN_IEEE1BLK_AN_ADVERTISEMENT1, 0},
4725 {MDIO_AN_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0},
4726 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL3_UP1, 0x1},
4727 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL5_MISC7, 0xa},
4728 /* Leave cl72 training enable, needed for KR */
4729 {MDIO_PMA_DEVAD, MDIO_WC_REG_PMD_KR_CONTROL, 0x2}
4732 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
4733 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
4736 lane = elink_get_warpcore_lane(phy, params);
4737 /* Global registers */
4738 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4739 MDIO_AER_BLOCK_AER_REG, 0);
4740 /* Disable CL36 PCS Tx */
4741 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4742 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
4743 val16 &= ~(0x0011 << lane);
4744 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4745 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
4747 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4748 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
4749 val16 |= (0x0303 << (lane << 1));
4750 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4751 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
4753 elink_set_aer_mmd(params, phy);
4754 /* Set speed via PMA/PMD register */
4755 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
4756 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040);
4758 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD,
4759 MDIO_WC_REG_IEEE0BLK_AUTONEGNP, 0xB);
4761 /* Enable encoded forced speed */
4762 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4763 MDIO_WC_REG_SERDESDIGITAL_MISC2, 0x30);
4765 /* Turn TX scramble payload only the 64/66 scrambler */
4766 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4767 MDIO_WC_REG_TX66_CONTROL, 0x9);
4769 /* Turn RX scramble payload only the 64/66 scrambler */
4770 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4771 MDIO_WC_REG_RX66_CONTROL, 0xF9);
4773 /* Set and clear loopback to cause a reset to 64/66 decoder */
4774 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4775 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x4000);
4776 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4777 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x0);
4781 static void elink_warpcore_set_10G_XFI(struct elink_phy *phy,
4782 struct elink_params *params,
4785 struct bxe_softc *sc = params->sc;
4786 uint16_t misc1_val, tap_val, tx_driver_val, lane, val;
4787 uint32_t cfg_tap_val, tx_drv_brdct, tx_equal;
4788 uint32_t ifir_val, ipost2_val, ipre_driver_val;
4789 /* Hold rxSeqStart */
4790 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4791 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x8000);
4793 /* Hold tx_fifo_reset */
4794 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4795 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3, 0x1);
4797 /* Disable CL73 AN */
4798 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0);
4800 /* Disable 100FX Enable and Auto-Detect */
4801 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4802 MDIO_WC_REG_FX100_CTRL1, 0xFFFA);
4804 /* Disable 100FX Idle detect */
4805 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4806 MDIO_WC_REG_FX100_CTRL3, 0x0080);
4808 /* Set Block address to Remote PHY & Clear forced_speed[5] */
4809 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4810 MDIO_WC_REG_DIGITAL4_MISC3, 0xFF7F);
4812 /* Turn off auto-detect & fiber mode */
4813 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4814 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
4817 /* Set filter_force_link, disable_false_link and parallel_detect */
4818 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4819 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &val);
4820 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4821 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
4822 ((val | 0x0006) & 0xFFFE));
4825 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4826 MDIO_WC_REG_SERDESDIGITAL_MISC1, &misc1_val);
4828 misc1_val &= ~(0x1f);
4832 tap_val = WC_TX_FIR(0x08, 0x37, 0x00);
4833 tx_driver_val = WC_TX_DRIVER(0x00, 0x02, 0x03, 0);
4835 cfg_tap_val = REG_RD(sc, params->shmem_base +
4836 offsetof(struct shmem_region, dev_info.
4837 port_hw_config[params->port].
4840 tx_equal = cfg_tap_val & PORT_HW_CFG_TX_EQUALIZATION_MASK;
4844 /* TAP values are controlled by nvram, if value there isn't 0 */
4846 tap_val = (uint16_t)tx_equal;
4848 tap_val = WC_TX_FIR(0x0f, 0x2b, 0x02);
4850 ifir_val = DEFAULT_TX_DRV_IFIR;
4851 ipost2_val = DEFAULT_TX_DRV_POST2;
4852 ipre_driver_val = DEFAULT_TX_DRV_IPRE_DRIVER;
4853 tx_drv_brdct = DEFAULT_TX_DRV_BRDCT;
4855 /* If any of the IFIR/IPRE_DRIVER/POST@ is set, apply all
4858 if (cfg_tap_val & (PORT_HW_CFG_TX_DRV_IFIR_MASK |
4859 PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK |
4860 PORT_HW_CFG_TX_DRV_POST2_MASK)) {
4861 ifir_val = (cfg_tap_val &
4862 PORT_HW_CFG_TX_DRV_IFIR_MASK) >>
4863 PORT_HW_CFG_TX_DRV_IFIR_SHIFT;
4864 ipre_driver_val = (cfg_tap_val &
4865 PORT_HW_CFG_TX_DRV_IPREDRIVER_MASK)
4866 >> PORT_HW_CFG_TX_DRV_IPREDRIVER_SHIFT;
4867 ipost2_val = (cfg_tap_val &
4868 PORT_HW_CFG_TX_DRV_POST2_MASK) >>
4869 PORT_HW_CFG_TX_DRV_POST2_SHIFT;
4872 if (cfg_tap_val & PORT_HW_CFG_TX_DRV_BROADCAST_MASK) {
4873 tx_drv_brdct = (cfg_tap_val &
4874 PORT_HW_CFG_TX_DRV_BROADCAST_MASK) >>
4875 PORT_HW_CFG_TX_DRV_BROADCAST_SHIFT;
4878 tx_driver_val = WC_TX_DRIVER(ipost2_val, tx_drv_brdct,
4879 ipre_driver_val, ifir_val);
4881 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4882 MDIO_WC_REG_SERDESDIGITAL_MISC1, misc1_val);
4884 /* Set Transmit PMD settings */
4885 lane = elink_get_warpcore_lane(phy, params);
4886 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4887 MDIO_WC_REG_TX_FIR_TAP,
4888 tap_val | MDIO_WC_REG_TX_FIR_TAP_ENABLE);
4889 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4890 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
4893 /* Enable fiber mode, enable and invert sig_det */
4894 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4895 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, 0xd);
4897 /* Set Block address to Remote PHY & Set forced_speed[5], 40bit mode */
4898 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4899 MDIO_WC_REG_DIGITAL4_MISC3, 0x8080);
4901 elink_warpcore_set_lpi_passthrough(phy, params);
4903 /* 10G XFI Full Duplex */
4904 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4905 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x100);
4907 /* Release tx_fifo_reset */
4908 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4909 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
4911 /* Release rxSeqStart */
4912 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4913 MDIO_WC_REG_DSC2B0_DSC_MISC_CTRL0, 0x7FFF);
4916 static void elink_warpcore_set_20G_force_KR2(struct elink_phy *phy,
4917 struct elink_params *params)
4920 struct bxe_softc *sc = params->sc;
4921 /* Set global registers, so set AER lane to 0 */
4922 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4923 MDIO_AER_BLOCK_AER_REG, 0);
4925 /* Disable sequencer */
4926 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
4927 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, ~(1<<13));
4929 elink_set_aer_mmd(params, phy);
4931 elink_cl45_read_and_write(sc, phy, MDIO_PMA_DEVAD,
4932 MDIO_WC_REG_PMD_KR_CONTROL, ~(1<<1));
4933 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
4934 MDIO_AN_REG_CTRL, 0);
4936 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4937 MDIO_WC_REG_CL73_USERB0_CTRL, &val);
4940 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4941 MDIO_WC_REG_CL73_USERB0_CTRL, val);
4943 /* Set 20G KR2 force speed */
4944 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4945 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x1f);
4947 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4948 MDIO_WC_REG_DIGITAL4_MISC3, (1<<7));
4950 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
4951 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, &val);
4954 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4955 MDIO_WC_REG_CL72_USERB0_CL72_MISC1_CONTROL, val);
4956 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4957 MDIO_WC_REG_CL72_USERB0_CL72_TX_FIR_TAP, 0x835A);
4959 /* Enable sequencer (over lane 0) */
4960 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
4961 MDIO_AER_BLOCK_AER_REG, 0);
4963 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
4964 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL, (1<<13));
4966 elink_set_aer_mmd(params, phy);
4969 static void elink_warpcore_set_20G_DXGXS(struct bxe_softc *sc,
4970 struct elink_phy *phy,
4973 /* Rx0 anaRxControl1G */
4974 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4975 MDIO_WC_REG_RX0_ANARXCONTROL1G, 0x90);
4977 /* Rx2 anaRxControl1G */
4978 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4979 MDIO_WC_REG_RX2_ANARXCONTROL1G, 0x90);
4981 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4982 MDIO_WC_REG_RX66_SCW0, 0xE070);
4984 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4985 MDIO_WC_REG_RX66_SCW1, 0xC0D0);
4987 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4988 MDIO_WC_REG_RX66_SCW2, 0xA0B0);
4990 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4991 MDIO_WC_REG_RX66_SCW3, 0x8090);
4993 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4994 MDIO_WC_REG_RX66_SCW0_MASK, 0xF0F0);
4996 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
4997 MDIO_WC_REG_RX66_SCW1_MASK, 0xF0F0);
4999 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5000 MDIO_WC_REG_RX66_SCW2_MASK, 0xF0F0);
5002 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5003 MDIO_WC_REG_RX66_SCW3_MASK, 0xF0F0);
5005 /* Serdes Digital Misc1 */
5006 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5007 MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6008);
5009 /* Serdes Digital4 Misc3 */
5010 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5011 MDIO_WC_REG_DIGITAL4_MISC3, 0x8088);
5013 /* Set Transmit PMD settings */
5014 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5015 MDIO_WC_REG_TX_FIR_TAP,
5016 (WC_TX_FIR(0x12, 0x2d, 0x00) |
5017 MDIO_WC_REG_TX_FIR_TAP_ENABLE));
5018 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5019 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane,
5020 WC_TX_DRIVER(0x02, 0x02, 0x02, 0));
5023 static void elink_warpcore_set_sgmii_speed(struct elink_phy *phy,
5024 struct elink_params *params,
5026 uint8_t always_autoneg)
5028 struct bxe_softc *sc = params->sc;
5029 uint16_t val16, digctrl_kx1, digctrl_kx2;
5031 /* Clear XFI clock comp in non-10G single lane mode. */
5032 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5033 MDIO_WC_REG_RX66_CONTROL, ~(3<<13));
5035 elink_warpcore_set_lpi_passthrough(phy, params);
5037 if (always_autoneg || phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
5039 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5040 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
5042 ELINK_DEBUG_P0(sc, "set SGMII AUTONEG\n");
5044 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5045 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
5047 switch (phy->req_line_speed) {
5048 case ELINK_SPEED_10:
5050 case ELINK_SPEED_100:
5053 case ELINK_SPEED_1000:
5058 "Speed not supported: 0x%x\n", phy->req_line_speed);
5062 if (phy->req_duplex == DUPLEX_FULL)
5065 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5066 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, val16);
5068 ELINK_DEBUG_P1(sc, "set SGMII force speed %d\n",
5069 phy->req_line_speed);
5070 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5071 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, &val16);
5072 ELINK_DEBUG_P1(sc, " (readback) %x\n", val16);
5075 /* SGMII Slave mode and disable signal detect */
5076 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5077 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1, &digctrl_kx1);
5081 digctrl_kx1 &= 0xff4a;
5083 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5084 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
5087 /* Turn off parallel detect */
5088 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5089 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2, &digctrl_kx2);
5090 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5091 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5092 (digctrl_kx2 & ~(1<<2)));
5094 /* Re-enable parallel detect */
5095 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5096 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5097 (digctrl_kx2 | (1<<2)));
5099 /* Enable autodet */
5100 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5101 MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
5102 (digctrl_kx1 | 0x10));
5106 static void elink_warpcore_reset_lane(struct bxe_softc *sc,
5107 struct elink_phy *phy,
5111 /* Take lane out of reset after configuration is finished */
5112 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5113 MDIO_WC_REG_DIGITAL5_MISC6, &val);
5118 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5119 MDIO_WC_REG_DIGITAL5_MISC6, val);
5120 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5121 MDIO_WC_REG_DIGITAL5_MISC6, &val);
5124 /* Clear SFI/XFI link settings registers */
5125 static void elink_warpcore_clear_regs(struct elink_phy *phy,
5126 struct elink_params *params,
5129 struct bxe_softc *sc = params->sc;
5131 static struct elink_reg_set wc_regs[] = {
5132 {MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0},
5133 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL1, 0x014a},
5134 {MDIO_WC_DEVAD, MDIO_WC_REG_FX100_CTRL3, 0x0800},
5135 {MDIO_WC_DEVAD, MDIO_WC_REG_DIGITAL4_MISC3, 0x8008},
5136 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X1,
5138 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X2,
5140 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_CONTROL1000X3,
5142 {MDIO_WC_DEVAD, MDIO_WC_REG_SERDESDIGITAL_MISC1, 0x6000},
5143 {MDIO_WC_DEVAD, MDIO_WC_REG_TX_FIR_TAP, 0x0000},
5144 {MDIO_WC_DEVAD, MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x2040},
5145 {MDIO_WC_DEVAD, MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0x0140}
5147 /* Set XFI clock comp as default. */
5148 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5149 MDIO_WC_REG_RX66_CONTROL, (3<<13));
5151 for (i = 0; i < ARRAY_SIZE(wc_regs); i++)
5152 elink_cl45_write(sc, phy, wc_regs[i].devad, wc_regs[i].reg,
5155 lane = elink_get_warpcore_lane(phy, params);
5156 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5157 MDIO_WC_REG_TX0_TX_DRIVER + 0x10*lane, 0x0990);
5161 static elink_status_t elink_get_mod_abs_int_cfg(struct bxe_softc *sc,
5163 uint32_t shmem_base, uint8_t port,
5164 uint8_t *gpio_num, uint8_t *gpio_port)
5169 if (CHIP_IS_E3(sc)) {
5170 cfg_pin = (REG_RD(sc, shmem_base +
5171 offsetof(struct shmem_region,
5172 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
5173 PORT_HW_CFG_E3_MOD_ABS_MASK) >>
5174 PORT_HW_CFG_E3_MOD_ABS_SHIFT;
5176 /* Should not happen. This function called upon interrupt
5177 * triggered by GPIO ( since EPIO can only generate interrupts
5179 * So if this function was called and none of the GPIOs was set,
5180 * it means the shit hit the fan.
5182 if ((cfg_pin < PIN_CFG_GPIO0_P0) ||
5183 (cfg_pin > PIN_CFG_GPIO3_P1)) {
5185 "No cfg pin %x for module detect indication\n",
5187 return ELINK_STATUS_ERROR;
5190 *gpio_num = (cfg_pin - PIN_CFG_GPIO0_P0) & 0x3;
5191 *gpio_port = (cfg_pin - PIN_CFG_GPIO0_P0) >> 2;
5193 *gpio_num = MISC_REGISTERS_GPIO_3;
5197 return ELINK_STATUS_OK;
5200 static int elink_is_sfp_module_plugged(struct elink_phy *phy,
5201 struct elink_params *params)
5203 struct bxe_softc *sc = params->sc;
5204 uint8_t gpio_num, gpio_port;
5206 if (elink_get_mod_abs_int_cfg(sc, params->chip_id,
5207 params->shmem_base, params->port,
5208 &gpio_num, &gpio_port) != ELINK_STATUS_OK)
5210 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
5212 /* Call the handling function in case module is detected */
5218 static int elink_warpcore_get_sigdet(struct elink_phy *phy,
5219 struct elink_params *params)
5221 uint16_t gp2_status_reg0, lane;
5222 struct bxe_softc *sc = params->sc;
5224 lane = elink_get_warpcore_lane(phy, params);
5226 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, MDIO_WC_REG_GP2_STATUS_GP_2_0,
5229 return (gp2_status_reg0 >> (8+lane)) & 0x1;
5232 static void elink_warpcore_config_runtime(struct elink_phy *phy,
5233 struct elink_params *params,
5234 struct elink_vars *vars)
5236 struct bxe_softc *sc = params->sc;
5237 uint32_t serdes_net_if;
5238 uint16_t gp_status1 = 0, lnkup = 0, lnkup_kr = 0;
5240 vars->turn_to_run_wc_rt = vars->turn_to_run_wc_rt ? 0 : 1;
5242 if (!vars->turn_to_run_wc_rt)
5245 if (vars->rx_tx_asic_rst) {
5246 uint16_t lane = elink_get_warpcore_lane(phy, params);
5247 serdes_net_if = (REG_RD(sc, params->shmem_base +
5248 offsetof(struct shmem_region, dev_info.
5249 port_hw_config[params->port].default_cfg)) &
5250 PORT_HW_CFG_NET_SERDES_IF_MASK);
5252 switch (serdes_net_if) {
5253 case PORT_HW_CFG_NET_SERDES_IF_KR:
5254 /* Do we get link yet? */
5255 elink_cl45_read(sc, phy, MDIO_WC_DEVAD, 0x81d1,
5257 lnkup = (gp_status1 >> (8+lane)) & 0x1;/* 1G */
5259 lnkup_kr = (gp_status1 >> (12+lane)) & 0x1;
5261 if (lnkup_kr || lnkup) {
5262 vars->rx_tx_asic_rst = 0;
5264 /* Reset the lane to see if link comes up.*/
5265 elink_warpcore_reset_lane(sc, phy, 1);
5266 elink_warpcore_reset_lane(sc, phy, 0);
5268 /* Restart Autoneg */
5269 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
5270 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1200);
5272 vars->rx_tx_asic_rst--;
5273 ELINK_DEBUG_P1(sc, "0x%x retry left\n",
5274 vars->rx_tx_asic_rst);
5282 } /*params->rx_tx_asic_rst*/
5285 static void elink_warpcore_config_sfi(struct elink_phy *phy,
5286 struct elink_params *params)
5288 uint16_t lane = elink_get_warpcore_lane(phy, params);
5289 struct bxe_softc *sc = params->sc;
5290 elink_warpcore_clear_regs(phy, params, lane);
5291 if ((params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)] ==
5292 ELINK_SPEED_10000) &&
5293 (phy->media_type != ELINK_ETH_PHY_SFP_1G_FIBER)) {
5294 ELINK_DEBUG_P0(sc, "Setting 10G SFI\n");
5295 elink_warpcore_set_10G_XFI(phy, params, 0);
5297 ELINK_DEBUG_P0(sc, "Setting 1G Fiber\n");
5298 elink_warpcore_set_sgmii_speed(phy, params, 1, 0);
5302 static void elink_sfp_e3_set_transmitter(struct elink_params *params,
5303 struct elink_phy *phy,
5306 struct bxe_softc *sc = params->sc;
5308 uint8_t port = params->port;
5310 cfg_pin = REG_RD(sc, params->shmem_base +
5311 offsetof(struct shmem_region,
5312 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
5313 PORT_HW_CFG_E3_TX_LASER_MASK;
5314 /* Set the !tx_en since this pin is DISABLE_TX_LASER */
5315 ELINK_DEBUG_P1(sc, "Setting WC TX to %d\n", tx_en);
5317 /* For 20G, the expected pin to be used is 3 pins after the current */
5318 elink_set_cfg_pin(sc, cfg_pin, tx_en ^ 1);
5319 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)
5320 elink_set_cfg_pin(sc, cfg_pin + 3, tx_en ^ 1);
5323 static void elink_warpcore_config_init(struct elink_phy *phy,
5324 struct elink_params *params,
5325 struct elink_vars *vars)
5327 struct bxe_softc *sc = params->sc;
5328 uint32_t serdes_net_if;
5330 uint16_t lane = elink_get_warpcore_lane(phy, params);
5331 serdes_net_if = (REG_RD(sc, params->shmem_base +
5332 offsetof(struct shmem_region, dev_info.
5333 port_hw_config[params->port].default_cfg)) &
5334 PORT_HW_CFG_NET_SERDES_IF_MASK);
5335 ELINK_DEBUG_P2(sc, "Begin Warpcore init, link_speed %d, "
5336 "serdes_net_if = 0x%x\n",
5337 vars->line_speed, serdes_net_if);
5338 elink_set_aer_mmd(params, phy);
5339 elink_warpcore_reset_lane(sc, phy, 1);
5340 vars->phy_flags |= PHY_XGXS_FLAG;
5341 if ((serdes_net_if == PORT_HW_CFG_NET_SERDES_IF_SGMII) ||
5342 (phy->req_line_speed &&
5343 ((phy->req_line_speed == ELINK_SPEED_100) ||
5344 (phy->req_line_speed == ELINK_SPEED_10)))) {
5345 vars->phy_flags |= PHY_SGMII_FLAG;
5346 ELINK_DEBUG_P0(sc, "Setting SGMII mode\n");
5347 elink_warpcore_clear_regs(phy, params, lane);
5348 elink_warpcore_set_sgmii_speed(phy, params, 0, 1);
5350 switch (serdes_net_if) {
5351 case PORT_HW_CFG_NET_SERDES_IF_KR:
5352 /* Enable KR Auto Neg */
5353 if (params->loopback_mode != ELINK_LOOPBACK_EXT)
5354 elink_warpcore_enable_AN_KR(phy, params, vars);
5356 ELINK_DEBUG_P0(sc, "Setting KR 10G-Force\n");
5357 elink_warpcore_set_10G_KR(phy, params, vars);
5361 case PORT_HW_CFG_NET_SERDES_IF_XFI:
5362 elink_warpcore_clear_regs(phy, params, lane);
5363 if (vars->line_speed == ELINK_SPEED_10000) {
5364 ELINK_DEBUG_P0(sc, "Setting 10G XFI\n");
5365 elink_warpcore_set_10G_XFI(phy, params, 1);
5367 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
5368 ELINK_DEBUG_P0(sc, "1G Fiber\n");
5371 ELINK_DEBUG_P0(sc, "10/100/1G SGMII\n");
5374 elink_warpcore_set_sgmii_speed(phy,
5382 case PORT_HW_CFG_NET_SERDES_IF_SFI:
5383 /* Issue Module detection if module is plugged, or
5384 * enabled transmitter to avoid current leakage in case
5385 * no module is connected
5387 if ((params->loopback_mode == ELINK_LOOPBACK_NONE) ||
5388 (params->loopback_mode == ELINK_LOOPBACK_EXT)) {
5389 if (elink_is_sfp_module_plugged(phy, params))
5390 elink_sfp_module_detection(phy, params);
5392 elink_sfp_e3_set_transmitter(params,
5396 elink_warpcore_config_sfi(phy, params);
5399 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
5400 if (vars->line_speed != ELINK_SPEED_20000) {
5401 ELINK_DEBUG_P0(sc, "Speed not supported yet\n");
5404 ELINK_DEBUG_P0(sc, "Setting 20G DXGXS\n");
5405 elink_warpcore_set_20G_DXGXS(sc, phy, lane);
5406 /* Issue Module detection */
5408 elink_sfp_module_detection(phy, params);
5410 case PORT_HW_CFG_NET_SERDES_IF_KR2:
5411 if (!params->loopback_mode) {
5412 elink_warpcore_enable_AN_KR(phy, params, vars);
5414 ELINK_DEBUG_P0(sc, "Setting KR 20G-Force\n");
5415 elink_warpcore_set_20G_force_KR2(phy, params);
5420 "Unsupported Serdes Net Interface 0x%x\n",
5426 /* Take lane out of reset after configuration is finished */
5427 elink_warpcore_reset_lane(sc, phy, 0);
5428 ELINK_DEBUG_P0(sc, "Exit config init\n");
5431 static void elink_warpcore_link_reset(struct elink_phy *phy,
5432 struct elink_params *params)
5434 struct bxe_softc *sc = params->sc;
5435 uint16_t val16, lane;
5436 elink_sfp_e3_set_transmitter(params, phy, 0);
5437 elink_set_mdio_emac_per_phy(sc, params);
5438 elink_set_aer_mmd(params, phy);
5439 /* Global register */
5440 elink_warpcore_reset_lane(sc, phy, 1);
5442 /* Clear loopback settings (if any) */
5444 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5445 MDIO_WC_REG_COMBO_IEEE0_MIICTRL, 0xBFFF);
5447 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5448 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0xfffe);
5450 /* Update those 1-copy registers */
5451 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
5452 MDIO_AER_BLOCK_AER_REG, 0);
5453 /* Enable 1G MDIO (1-copy) */
5454 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5455 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
5458 elink_cl45_read_and_write(sc, phy, MDIO_WC_DEVAD,
5459 MDIO_WC_REG_XGXSBLK1_LANECTRL2, 0xff00);
5460 lane = elink_get_warpcore_lane(phy, params);
5461 /* Disable CL36 PCS Tx */
5462 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5463 MDIO_WC_REG_XGXSBLK1_LANECTRL0, &val16);
5464 val16 |= (0x11 << lane);
5465 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
5466 val16 |= (0x22 << lane);
5467 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5468 MDIO_WC_REG_XGXSBLK1_LANECTRL0, val16);
5470 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5471 MDIO_WC_REG_XGXSBLK1_LANECTRL1, &val16);
5472 val16 &= ~(0x0303 << (lane << 1));
5473 val16 |= (0x0101 << (lane << 1));
5474 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE) {
5475 val16 &= ~(0x0c0c << (lane << 1));
5476 val16 |= (0x0404 << (lane << 1));
5479 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5480 MDIO_WC_REG_XGXSBLK1_LANECTRL1, val16);
5482 elink_set_aer_mmd(params, phy);
5486 static void elink_set_warpcore_loopback(struct elink_phy *phy,
5487 struct elink_params *params)
5489 struct bxe_softc *sc = params->sc;
5492 ELINK_DEBUG_P2(sc, "Setting Warpcore loopback type %x, speed %d\n",
5493 params->loopback_mode, phy->req_line_speed);
5495 if (phy->req_line_speed < ELINK_SPEED_10000 ||
5496 phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
5497 /* 10/100/1000/20G-KR2 */
5499 /* Update those 1-copy registers */
5500 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
5501 MDIO_AER_BLOCK_AER_REG, 0);
5502 /* Enable 1G MDIO (1-copy) */
5503 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5504 MDIO_WC_REG_XGXSBLK0_XGXSCONTROL,
5506 /* Set 1G loopback based on lane (1-copy) */
5507 lane = elink_get_warpcore_lane(phy, params);
5508 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
5509 MDIO_WC_REG_XGXSBLK1_LANECTRL2, &val16);
5511 if (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)
5513 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
5514 MDIO_WC_REG_XGXSBLK1_LANECTRL2,
5517 /* Switch back to 4-copy registers */
5518 elink_set_aer_mmd(params, phy);
5520 /* 10G / 20G-DXGXS */
5521 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5522 MDIO_WC_REG_COMBO_IEEE0_MIICTRL,
5524 elink_cl45_read_or_write(sc, phy, MDIO_WC_DEVAD,
5525 MDIO_WC_REG_IEEE0BLK_MIICNTL, 0x1);
5531 static void elink_sync_link(struct elink_params *params,
5532 struct elink_vars *vars)
5534 struct bxe_softc *sc = params->sc;
5535 uint8_t link_10g_plus;
5536 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
5537 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
5538 vars->link_up = (vars->link_status & LINK_STATUS_LINK_UP);
5539 if (vars->link_up) {
5540 ELINK_DEBUG_P0(sc, "phy link up\n");
5542 vars->phy_link_up = 1;
5543 vars->duplex = DUPLEX_FULL;
5544 switch (vars->link_status &
5545 LINK_STATUS_SPEED_AND_DUPLEX_MASK) {
5546 case ELINK_LINK_10THD:
5547 vars->duplex = DUPLEX_HALF;
5549 case ELINK_LINK_10TFD:
5550 vars->line_speed = ELINK_SPEED_10;
5553 case ELINK_LINK_100TXHD:
5554 vars->duplex = DUPLEX_HALF;
5556 case ELINK_LINK_100T4:
5557 case ELINK_LINK_100TXFD:
5558 vars->line_speed = ELINK_SPEED_100;
5561 case ELINK_LINK_1000THD:
5562 vars->duplex = DUPLEX_HALF;
5564 case ELINK_LINK_1000TFD:
5565 vars->line_speed = ELINK_SPEED_1000;
5568 case ELINK_LINK_2500THD:
5569 vars->duplex = DUPLEX_HALF;
5571 case ELINK_LINK_2500TFD:
5572 vars->line_speed = ELINK_SPEED_2500;
5575 case ELINK_LINK_10GTFD:
5576 vars->line_speed = ELINK_SPEED_10000;
5578 case ELINK_LINK_20GTFD:
5579 vars->line_speed = ELINK_SPEED_20000;
5584 vars->flow_ctrl = 0;
5585 if (vars->link_status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED)
5586 vars->flow_ctrl |= ELINK_FLOW_CTRL_TX;
5588 if (vars->link_status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED)
5589 vars->flow_ctrl |= ELINK_FLOW_CTRL_RX;
5591 if (!vars->flow_ctrl)
5592 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5594 if (vars->line_speed &&
5595 ((vars->line_speed == ELINK_SPEED_10) ||
5596 (vars->line_speed == ELINK_SPEED_100))) {
5597 vars->phy_flags |= PHY_SGMII_FLAG;
5599 vars->phy_flags &= ~PHY_SGMII_FLAG;
5601 if (vars->line_speed &&
5602 USES_WARPCORE(sc) &&
5603 (vars->line_speed == ELINK_SPEED_1000))
5604 vars->phy_flags |= PHY_SGMII_FLAG;
5605 /* Anything 10 and over uses the bmac */
5606 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
5608 if (link_10g_plus) {
5609 if (USES_WARPCORE(sc))
5610 vars->mac_type = ELINK_MAC_TYPE_XMAC;
5612 vars->mac_type = ELINK_MAC_TYPE_BMAC;
5614 if (USES_WARPCORE(sc))
5615 vars->mac_type = ELINK_MAC_TYPE_UMAC;
5617 vars->mac_type = ELINK_MAC_TYPE_EMAC;
5619 } else { /* Link down */
5620 ELINK_DEBUG_P0(sc, "phy link down\n");
5622 vars->phy_link_up = 0;
5624 vars->line_speed = 0;
5625 vars->duplex = DUPLEX_FULL;
5626 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
5628 /* Indicate no mac active */
5629 vars->mac_type = ELINK_MAC_TYPE_NONE;
5630 if (vars->link_status & LINK_STATUS_PHYSICAL_LINK_FLAG)
5631 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
5632 if (vars->link_status & LINK_STATUS_SFP_TX_FAULT)
5633 vars->phy_flags |= PHY_SFP_TX_FAULT_FLAG;
5637 void elink_link_status_update(struct elink_params *params,
5638 struct elink_vars *vars)
5640 struct bxe_softc *sc = params->sc;
5641 uint8_t port = params->port;
5642 uint32_t sync_offset, media_types;
5643 /* Update PHY configuration */
5644 set_phy_vars(params, vars);
5646 vars->link_status = REG_RD(sc, params->shmem_base +
5647 offsetof(struct shmem_region,
5648 port_mb[port].link_status));
5650 /* Force link UP in non LOOPBACK_EXT loopback mode(s) */
5651 if (params->loopback_mode != ELINK_LOOPBACK_NONE &&
5652 params->loopback_mode != ELINK_LOOPBACK_EXT)
5653 vars->link_status |= LINK_STATUS_LINK_UP;
5655 if (elink_eee_has_cap(params))
5656 vars->eee_status = REG_RD(sc, params->shmem2_base +
5657 offsetof(struct shmem2_region,
5658 eee_status[params->port]));
5660 vars->phy_flags = PHY_XGXS_FLAG;
5661 elink_sync_link(params, vars);
5662 /* Sync media type */
5663 sync_offset = params->shmem_base +
5664 offsetof(struct shmem_region,
5665 dev_info.port_hw_config[port].media_type);
5666 media_types = REG_RD(sc, sync_offset);
5668 params->phy[ELINK_INT_PHY].media_type =
5669 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) >>
5670 PORT_HW_CFG_MEDIA_TYPE_PHY0_SHIFT;
5671 params->phy[ELINK_EXT_PHY1].media_type =
5672 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY1_MASK) >>
5673 PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT;
5674 params->phy[ELINK_EXT_PHY2].media_type =
5675 (media_types & PORT_HW_CFG_MEDIA_TYPE_PHY2_MASK) >>
5676 PORT_HW_CFG_MEDIA_TYPE_PHY2_SHIFT;
5677 ELINK_DEBUG_P1(sc, "media_types = 0x%x\n", media_types);
5679 /* Sync AEU offset */
5680 sync_offset = params->shmem_base +
5681 offsetof(struct shmem_region,
5682 dev_info.port_hw_config[port].aeu_int_mask);
5684 vars->aeu_int_mask = REG_RD(sc, sync_offset);
5686 /* Sync PFC status */
5687 if (vars->link_status & LINK_STATUS_PFC_ENABLED)
5688 params->feature_config_flags |=
5689 ELINK_FEATURE_CONFIG_PFC_ENABLED;
5691 params->feature_config_flags &=
5692 ~ELINK_FEATURE_CONFIG_PFC_ENABLED;
5694 if (SHMEM2_HAS(sc, link_attr_sync))
5695 params->link_attr_sync = SHMEM2_RD(sc,
5696 link_attr_sync[params->port]);
5698 ELINK_DEBUG_P3(sc, "link_status 0x%x phy_link_up %x int_mask 0x%x\n",
5699 vars->link_status, vars->phy_link_up, vars->aeu_int_mask);
5700 ELINK_DEBUG_P3(sc, "line_speed %x duplex %x flow_ctrl 0x%x\n",
5701 vars->line_speed, vars->duplex, vars->flow_ctrl);
5704 static void elink_set_master_ln(struct elink_params *params,
5705 struct elink_phy *phy)
5707 struct bxe_softc *sc = params->sc;
5708 uint16_t new_master_ln, ser_lane;
5709 ser_lane = ((params->lane_config &
5710 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
5711 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
5713 /* Set the master_ln for AN */
5714 CL22_RD_OVER_CL45(sc, phy,
5715 MDIO_REG_BANK_XGXS_BLOCK2,
5716 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
5719 CL22_WR_OVER_CL45(sc, phy,
5720 MDIO_REG_BANK_XGXS_BLOCK2 ,
5721 MDIO_XGXS_BLOCK2_TEST_MODE_LANE,
5722 (new_master_ln | ser_lane));
5725 static elink_status_t elink_reset_unicore(struct elink_params *params,
5726 struct elink_phy *phy,
5729 struct bxe_softc *sc = params->sc;
5730 uint16_t mii_control;
5732 CL22_RD_OVER_CL45(sc, phy,
5733 MDIO_REG_BANK_COMBO_IEEE0,
5734 MDIO_COMBO_IEEE0_MII_CONTROL, &mii_control);
5736 /* Reset the unicore */
5737 CL22_WR_OVER_CL45(sc, phy,
5738 MDIO_REG_BANK_COMBO_IEEE0,
5739 MDIO_COMBO_IEEE0_MII_CONTROL,
5741 MDIO_COMBO_IEEO_MII_CONTROL_RESET));
5743 elink_set_serdes_access(sc, params->port);
5745 /* Wait for the reset to self clear */
5746 for (i = 0; i < ELINK_MDIO_ACCESS_TIMEOUT; i++) {
5749 /* The reset erased the previous bank value */
5750 CL22_RD_OVER_CL45(sc, phy,
5751 MDIO_REG_BANK_COMBO_IEEE0,
5752 MDIO_COMBO_IEEE0_MII_CONTROL,
5755 if (!(mii_control & MDIO_COMBO_IEEO_MII_CONTROL_RESET)) {
5757 return ELINK_STATUS_OK;
5761 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
5764 ELINK_DEBUG_P0(sc, "BUG! XGXS is still in reset!\n");
5765 return ELINK_STATUS_ERROR;
5769 static void elink_set_swap_lanes(struct elink_params *params,
5770 struct elink_phy *phy)
5772 struct bxe_softc *sc = params->sc;
5773 /* Each two bits represents a lane number:
5774 * No swap is 0123 => 0x1b no need to enable the swap
5776 uint16_t rx_lane_swap, tx_lane_swap;
5778 rx_lane_swap = ((params->lane_config &
5779 PORT_HW_CFG_LANE_SWAP_CFG_RX_MASK) >>
5780 PORT_HW_CFG_LANE_SWAP_CFG_RX_SHIFT);
5781 tx_lane_swap = ((params->lane_config &
5782 PORT_HW_CFG_LANE_SWAP_CFG_TX_MASK) >>
5783 PORT_HW_CFG_LANE_SWAP_CFG_TX_SHIFT);
5785 if (rx_lane_swap != 0x1b) {
5786 CL22_WR_OVER_CL45(sc, phy,
5787 MDIO_REG_BANK_XGXS_BLOCK2,
5788 MDIO_XGXS_BLOCK2_RX_LN_SWAP,
5790 MDIO_XGXS_BLOCK2_RX_LN_SWAP_ENABLE |
5791 MDIO_XGXS_BLOCK2_RX_LN_SWAP_FORCE_ENABLE));
5793 CL22_WR_OVER_CL45(sc, phy,
5794 MDIO_REG_BANK_XGXS_BLOCK2,
5795 MDIO_XGXS_BLOCK2_RX_LN_SWAP, 0);
5798 if (tx_lane_swap != 0x1b) {
5799 CL22_WR_OVER_CL45(sc, phy,
5800 MDIO_REG_BANK_XGXS_BLOCK2,
5801 MDIO_XGXS_BLOCK2_TX_LN_SWAP,
5803 MDIO_XGXS_BLOCK2_TX_LN_SWAP_ENABLE));
5805 CL22_WR_OVER_CL45(sc, phy,
5806 MDIO_REG_BANK_XGXS_BLOCK2,
5807 MDIO_XGXS_BLOCK2_TX_LN_SWAP, 0);
5811 static void elink_set_parallel_detection(struct elink_phy *phy,
5812 struct elink_params *params)
5814 struct bxe_softc *sc = params->sc;
5816 CL22_RD_OVER_CL45(sc, phy,
5817 MDIO_REG_BANK_SERDES_DIGITAL,
5818 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
5820 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5821 control2 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
5823 control2 &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL2_PRL_DT_EN;
5824 ELINK_DEBUG_P2(sc, "phy->speed_cap_mask = 0x%x, control2 = 0x%x\n",
5825 phy->speed_cap_mask, control2);
5826 CL22_WR_OVER_CL45(sc, phy,
5827 MDIO_REG_BANK_SERDES_DIGITAL,
5828 MDIO_SERDES_DIGITAL_A_1000X_CONTROL2,
5831 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
5832 (phy->speed_cap_mask &
5833 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
5834 ELINK_DEBUG_P0(sc, "XGXS\n");
5836 CL22_WR_OVER_CL45(sc, phy,
5837 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5838 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK,
5839 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_LINK_CNT);
5841 CL22_RD_OVER_CL45(sc, phy,
5842 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5843 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5848 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL_PARDET10G_EN;
5850 CL22_WR_OVER_CL45(sc, phy,
5851 MDIO_REG_BANK_10G_PARALLEL_DETECT,
5852 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_CONTROL,
5855 /* Disable parallel detection of HiG */
5856 CL22_WR_OVER_CL45(sc, phy,
5857 MDIO_REG_BANK_XGXS_BLOCK2,
5858 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G,
5859 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_CX4_XGXS |
5860 MDIO_XGXS_BLOCK2_UNICORE_MODE_10G_HIGIG_XGXS);
5864 static void elink_set_autoneg(struct elink_phy *phy,
5865 struct elink_params *params,
5866 struct elink_vars *vars,
5867 uint8_t enable_cl73)
5869 struct bxe_softc *sc = params->sc;
5873 CL22_RD_OVER_CL45(sc, phy,
5874 MDIO_REG_BANK_COMBO_IEEE0,
5875 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5877 /* CL37 Autoneg Enabled */
5878 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
5879 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_AN_EN;
5880 else /* CL37 Autoneg Disabled */
5881 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5882 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN);
5884 CL22_WR_OVER_CL45(sc, phy,
5885 MDIO_REG_BANK_COMBO_IEEE0,
5886 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5888 /* Enable/Disable Autodetection */
5890 CL22_RD_OVER_CL45(sc, phy,
5891 MDIO_REG_BANK_SERDES_DIGITAL,
5892 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, ®_val);
5893 reg_val &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_SIGNAL_DETECT_EN |
5894 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT);
5895 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE;
5896 if (vars->line_speed == ELINK_SPEED_AUTO_NEG)
5897 reg_val |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5899 reg_val &= ~MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET;
5901 CL22_WR_OVER_CL45(sc, phy,
5902 MDIO_REG_BANK_SERDES_DIGITAL,
5903 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1, reg_val);
5905 /* Enable TetonII and BAM autoneg */
5906 CL22_RD_OVER_CL45(sc, phy,
5907 MDIO_REG_BANK_BAM_NEXT_PAGE,
5908 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5910 if (vars->line_speed == ELINK_SPEED_AUTO_NEG) {
5911 /* Enable BAM aneg Mode and TetonII aneg Mode */
5912 reg_val |= (MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5913 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5915 /* TetonII and BAM Autoneg Disabled */
5916 reg_val &= ~(MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_BAM_MODE |
5917 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL_TETON_AN);
5919 CL22_WR_OVER_CL45(sc, phy,
5920 MDIO_REG_BANK_BAM_NEXT_PAGE,
5921 MDIO_BAM_NEXT_PAGE_MP5_NEXT_PAGE_CTRL,
5925 /* Enable Cl73 FSM status bits */
5926 CL22_WR_OVER_CL45(sc, phy,
5927 MDIO_REG_BANK_CL73_USERB0,
5928 MDIO_CL73_USERB0_CL73_UCTRL,
5931 /* Enable BAM Station Manager*/
5932 CL22_WR_OVER_CL45(sc, phy,
5933 MDIO_REG_BANK_CL73_USERB0,
5934 MDIO_CL73_USERB0_CL73_BAM_CTRL1,
5935 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_EN |
5936 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_STATION_MNGR_EN |
5937 MDIO_CL73_USERB0_CL73_BAM_CTRL1_BAM_NP_AFTER_BP_EN);
5939 /* Advertise CL73 link speeds */
5940 CL22_RD_OVER_CL45(sc, phy,
5941 MDIO_REG_BANK_CL73_IEEEB1,
5942 MDIO_CL73_IEEEB1_AN_ADV2,
5944 if (phy->speed_cap_mask &
5945 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
5946 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4;
5947 if (phy->speed_cap_mask &
5948 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)
5949 reg_val |= MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX;
5951 CL22_WR_OVER_CL45(sc, phy,
5952 MDIO_REG_BANK_CL73_IEEEB1,
5953 MDIO_CL73_IEEEB1_AN_ADV2,
5956 /* CL73 Autoneg Enabled */
5957 reg_val = MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN;
5959 } else /* CL73 Autoneg Disabled */
5962 CL22_WR_OVER_CL45(sc, phy,
5963 MDIO_REG_BANK_CL73_IEEEB0,
5964 MDIO_CL73_IEEEB0_CL73_AN_CONTROL, reg_val);
5967 /* Program SerDes, forced speed */
5968 static void elink_program_serdes(struct elink_phy *phy,
5969 struct elink_params *params,
5970 struct elink_vars *vars)
5972 struct bxe_softc *sc = params->sc;
5975 /* Program duplex, disable autoneg and sgmii*/
5976 CL22_RD_OVER_CL45(sc, phy,
5977 MDIO_REG_BANK_COMBO_IEEE0,
5978 MDIO_COMBO_IEEE0_MII_CONTROL, ®_val);
5979 reg_val &= ~(MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX |
5980 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
5981 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK);
5982 if (phy->req_duplex == DUPLEX_FULL)
5983 reg_val |= MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
5984 CL22_WR_OVER_CL45(sc, phy,
5985 MDIO_REG_BANK_COMBO_IEEE0,
5986 MDIO_COMBO_IEEE0_MII_CONTROL, reg_val);
5989 * - needed only if the speed is greater than 1G (2.5G or 10G)
5991 CL22_RD_OVER_CL45(sc, phy,
5992 MDIO_REG_BANK_SERDES_DIGITAL,
5993 MDIO_SERDES_DIGITAL_MISC1, ®_val);
5994 /* Clearing the speed value before setting the right speed */
5995 ELINK_DEBUG_P1(sc, "MDIO_REG_BANK_SERDES_DIGITAL = 0x%x\n", reg_val);
5997 reg_val &= ~(MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_MASK |
5998 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
6000 if (!((vars->line_speed == ELINK_SPEED_1000) ||
6001 (vars->line_speed == ELINK_SPEED_100) ||
6002 (vars->line_speed == ELINK_SPEED_10))) {
6004 reg_val |= (MDIO_SERDES_DIGITAL_MISC1_REFCLK_SEL_156_25M |
6005 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_SEL);
6006 if (vars->line_speed == ELINK_SPEED_10000)
6008 MDIO_SERDES_DIGITAL_MISC1_FORCE_SPEED_10G_CX4;
6011 CL22_WR_OVER_CL45(sc, phy,
6012 MDIO_REG_BANK_SERDES_DIGITAL,
6013 MDIO_SERDES_DIGITAL_MISC1, reg_val);
6017 static void elink_set_brcm_cl37_advertisement(struct elink_phy *phy,
6018 struct elink_params *params)
6020 struct bxe_softc *sc = params->sc;
6023 /* Set extended capabilities */
6024 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G)
6025 val |= MDIO_OVER_1G_UP1_2_5G;
6026 if (phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
6027 val |= MDIO_OVER_1G_UP1_10G;
6028 CL22_WR_OVER_CL45(sc, phy,
6029 MDIO_REG_BANK_OVER_1G,
6030 MDIO_OVER_1G_UP1, val);
6032 CL22_WR_OVER_CL45(sc, phy,
6033 MDIO_REG_BANK_OVER_1G,
6034 MDIO_OVER_1G_UP3, 0x400);
6037 static void elink_set_ieee_aneg_advertisement(struct elink_phy *phy,
6038 struct elink_params *params,
6041 struct bxe_softc *sc = params->sc;
6043 /* For AN, we are always publishing full duplex */
6045 CL22_WR_OVER_CL45(sc, phy,
6046 MDIO_REG_BANK_COMBO_IEEE0,
6047 MDIO_COMBO_IEEE0_AUTO_NEG_ADV, ieee_fc);
6048 CL22_RD_OVER_CL45(sc, phy,
6049 MDIO_REG_BANK_CL73_IEEEB1,
6050 MDIO_CL73_IEEEB1_AN_ADV1, &val);
6051 val &= ~MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_BOTH;
6052 val |= ((ieee_fc<<3) & MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK);
6053 CL22_WR_OVER_CL45(sc, phy,
6054 MDIO_REG_BANK_CL73_IEEEB1,
6055 MDIO_CL73_IEEEB1_AN_ADV1, val);
6058 static void elink_restart_autoneg(struct elink_phy *phy,
6059 struct elink_params *params,
6060 uint8_t enable_cl73)
6062 struct bxe_softc *sc = params->sc;
6063 uint16_t mii_control;
6065 ELINK_DEBUG_P0(sc, "elink_restart_autoneg\n");
6066 /* Enable and restart BAM/CL37 aneg */
6069 CL22_RD_OVER_CL45(sc, phy,
6070 MDIO_REG_BANK_CL73_IEEEB0,
6071 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6074 CL22_WR_OVER_CL45(sc, phy,
6075 MDIO_REG_BANK_CL73_IEEEB0,
6076 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6078 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN |
6079 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_RESTART_AN));
6082 CL22_RD_OVER_CL45(sc, phy,
6083 MDIO_REG_BANK_COMBO_IEEE0,
6084 MDIO_COMBO_IEEE0_MII_CONTROL,
6087 "elink_restart_autoneg mii_control before = 0x%x\n",
6089 CL22_WR_OVER_CL45(sc, phy,
6090 MDIO_REG_BANK_COMBO_IEEE0,
6091 MDIO_COMBO_IEEE0_MII_CONTROL,
6093 MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
6094 MDIO_COMBO_IEEO_MII_CONTROL_RESTART_AN));
6098 static void elink_initialize_sgmii_process(struct elink_phy *phy,
6099 struct elink_params *params,
6100 struct elink_vars *vars)
6102 struct bxe_softc *sc = params->sc;
6105 /* In SGMII mode, the unicore is always slave */
6107 CL22_RD_OVER_CL45(sc, phy,
6108 MDIO_REG_BANK_SERDES_DIGITAL,
6109 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
6111 control1 |= MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_INVERT_SIGNAL_DETECT;
6112 /* Set sgmii mode (and not fiber) */
6113 control1 &= ~(MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_FIBER_MODE |
6114 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_AUTODET |
6115 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1_MSTR_MODE);
6116 CL22_WR_OVER_CL45(sc, phy,
6117 MDIO_REG_BANK_SERDES_DIGITAL,
6118 MDIO_SERDES_DIGITAL_A_1000X_CONTROL1,
6121 /* If forced speed */
6122 if (!(vars->line_speed == ELINK_SPEED_AUTO_NEG)) {
6123 /* Set speed, disable autoneg */
6124 uint16_t mii_control;
6126 CL22_RD_OVER_CL45(sc, phy,
6127 MDIO_REG_BANK_COMBO_IEEE0,
6128 MDIO_COMBO_IEEE0_MII_CONTROL,
6130 mii_control &= ~(MDIO_COMBO_IEEO_MII_CONTROL_AN_EN |
6131 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_MASK|
6132 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX);
6134 switch (vars->line_speed) {
6135 case ELINK_SPEED_100:
6137 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_100;
6139 case ELINK_SPEED_1000:
6141 MDIO_COMBO_IEEO_MII_CONTROL_MAN_SGMII_SP_1000;
6143 case ELINK_SPEED_10:
6144 /* There is nothing to set for 10M */
6147 /* Invalid speed for SGMII */
6148 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
6153 /* Setting the full duplex */
6154 if (phy->req_duplex == DUPLEX_FULL)
6156 MDIO_COMBO_IEEO_MII_CONTROL_FULL_DUPLEX;
6157 CL22_WR_OVER_CL45(sc, phy,
6158 MDIO_REG_BANK_COMBO_IEEE0,
6159 MDIO_COMBO_IEEE0_MII_CONTROL,
6162 } else { /* AN mode */
6163 /* Enable and restart AN */
6164 elink_restart_autoneg(phy, params, 0);
6170 static elink_status_t elink_direct_parallel_detect_used(struct elink_phy *phy,
6171 struct elink_params *params)
6173 struct bxe_softc *sc = params->sc;
6174 uint16_t pd_10g, status2_1000x;
6175 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
6176 return ELINK_STATUS_OK;
6177 CL22_RD_OVER_CL45(sc, phy,
6178 MDIO_REG_BANK_SERDES_DIGITAL,
6179 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
6181 CL22_RD_OVER_CL45(sc, phy,
6182 MDIO_REG_BANK_SERDES_DIGITAL,
6183 MDIO_SERDES_DIGITAL_A_1000X_STATUS2,
6185 if (status2_1000x & MDIO_SERDES_DIGITAL_A_1000X_STATUS2_AN_DISABLED) {
6186 ELINK_DEBUG_P1(sc, "1G parallel detect link on port %d\n",
6191 CL22_RD_OVER_CL45(sc, phy,
6192 MDIO_REG_BANK_10G_PARALLEL_DETECT,
6193 MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS,
6196 if (pd_10g & MDIO_10G_PARALLEL_DETECT_PAR_DET_10G_STATUS_PD_LINK) {
6197 ELINK_DEBUG_P1(sc, "10G parallel detect link on port %d\n",
6201 return ELINK_STATUS_OK;
6204 static void elink_update_adv_fc(struct elink_phy *phy,
6205 struct elink_params *params,
6206 struct elink_vars *vars,
6209 uint16_t ld_pause; /* local driver */
6210 uint16_t lp_pause; /* link partner */
6211 uint16_t pause_result;
6212 struct bxe_softc *sc = params->sc;
6214 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
6215 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) ==
6216 (MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_AUTONEG_COMPLETE |
6217 MDIO_GP_STATUS_TOP_AN_STATUS1_CL73_MR_LP_NP_AN_ABLE)) {
6219 CL22_RD_OVER_CL45(sc, phy,
6220 MDIO_REG_BANK_CL73_IEEEB1,
6221 MDIO_CL73_IEEEB1_AN_ADV1,
6223 CL22_RD_OVER_CL45(sc, phy,
6224 MDIO_REG_BANK_CL73_IEEEB1,
6225 MDIO_CL73_IEEEB1_AN_LP_ADV1,
6227 pause_result = (ld_pause &
6228 MDIO_CL73_IEEEB1_AN_ADV1_PAUSE_MASK) >> 8;
6229 pause_result |= (lp_pause &
6230 MDIO_CL73_IEEEB1_AN_LP_ADV1_PAUSE_MASK) >> 10;
6231 ELINK_DEBUG_P1(sc, "pause_result CL73 0x%x\n", pause_result);
6233 CL22_RD_OVER_CL45(sc, phy,
6234 MDIO_REG_BANK_COMBO_IEEE0,
6235 MDIO_COMBO_IEEE0_AUTO_NEG_ADV,
6237 CL22_RD_OVER_CL45(sc, phy,
6238 MDIO_REG_BANK_COMBO_IEEE0,
6239 MDIO_COMBO_IEEE0_AUTO_NEG_LINK_PARTNER_ABILITY1,
6241 pause_result = (ld_pause &
6242 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>5;
6243 pause_result |= (lp_pause &
6244 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_MASK)>>7;
6245 ELINK_DEBUG_P1(sc, "pause_result CL37 0x%x\n", pause_result);
6247 elink_pause_resolve(phy, params, vars, pause_result);
6251 static void elink_flow_ctrl_resolve(struct elink_phy *phy,
6252 struct elink_params *params,
6253 struct elink_vars *vars,
6256 struct bxe_softc *sc = params->sc;
6257 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
6259 /* Resolve from gp_status in case of AN complete and not sgmii */
6260 if (phy->req_flow_ctrl != ELINK_FLOW_CTRL_AUTO) {
6261 /* Update the advertised flow-controled of LD/LP in AN */
6262 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6263 elink_update_adv_fc(phy, params, vars, gp_status);
6264 /* But set the flow-control result as the requested one */
6265 vars->flow_ctrl = phy->req_flow_ctrl;
6266 } else if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG)
6267 vars->flow_ctrl = params->req_fc_auto_adv;
6268 else if ((gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE) &&
6269 (!(vars->phy_flags & PHY_SGMII_FLAG))) {
6270 if (elink_direct_parallel_detect_used(phy, params)) {
6271 vars->flow_ctrl = params->req_fc_auto_adv;
6274 elink_update_adv_fc(phy, params, vars, gp_status);
6276 ELINK_DEBUG_P1(sc, "flow_ctrl 0x%x\n", vars->flow_ctrl);
6279 static void elink_check_fallback_to_cl37(struct elink_phy *phy,
6280 struct elink_params *params)
6282 struct bxe_softc *sc = params->sc;
6283 uint16_t rx_status, ustat_val, cl37_fsm_received;
6284 ELINK_DEBUG_P0(sc, "elink_check_fallback_to_cl37\n");
6285 /* Step 1: Make sure signal is detected */
6286 CL22_RD_OVER_CL45(sc, phy,
6290 if ((rx_status & MDIO_RX0_RX_STATUS_SIGDET) !=
6291 (MDIO_RX0_RX_STATUS_SIGDET)) {
6292 ELINK_DEBUG_P1(sc, "Signal is not detected. Restoring CL73."
6293 "rx_status(0x80b0) = 0x%x\n", rx_status);
6294 CL22_WR_OVER_CL45(sc, phy,
6295 MDIO_REG_BANK_CL73_IEEEB0,
6296 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6297 MDIO_CL73_IEEEB0_CL73_AN_CONTROL_AN_EN);
6300 /* Step 2: Check CL73 state machine */
6301 CL22_RD_OVER_CL45(sc, phy,
6302 MDIO_REG_BANK_CL73_USERB0,
6303 MDIO_CL73_USERB0_CL73_USTAT1,
6306 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
6307 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) !=
6308 (MDIO_CL73_USERB0_CL73_USTAT1_LINK_STATUS_CHECK |
6309 MDIO_CL73_USERB0_CL73_USTAT1_AN_GOOD_CHECK_BAM37)) {
6310 ELINK_DEBUG_P1(sc, "CL73 state-machine is not stable. "
6311 "ustat_val(0x8371) = 0x%x\n", ustat_val);
6314 /* Step 3: Check CL37 Message Pages received to indicate LP
6315 * supports only CL37
6317 CL22_RD_OVER_CL45(sc, phy,
6318 MDIO_REG_BANK_REMOTE_PHY,
6319 MDIO_REMOTE_PHY_MISC_RX_STATUS,
6320 &cl37_fsm_received);
6321 if ((cl37_fsm_received &
6322 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
6323 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) !=
6324 (MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_OVER1G_MSG |
6325 MDIO_REMOTE_PHY_MISC_RX_STATUS_CL37_FSM_RECEIVED_BRCM_OUI_MSG)) {
6326 ELINK_DEBUG_P1(sc, "No CL37 FSM were received. "
6327 "misc_rx_status(0x8330) = 0x%x\n",
6331 /* The combined cl37/cl73 fsm state information indicating that
6332 * we are connected to a device which does not support cl73, but
6333 * does support cl37 BAM. In this case we disable cl73 and
6334 * restart cl37 auto-neg
6338 CL22_WR_OVER_CL45(sc, phy,
6339 MDIO_REG_BANK_CL73_IEEEB0,
6340 MDIO_CL73_IEEEB0_CL73_AN_CONTROL,
6342 /* Restart CL37 autoneg */
6343 elink_restart_autoneg(phy, params, 0);
6344 ELINK_DEBUG_P0(sc, "Disabling CL73, and restarting CL37 autoneg\n");
6347 static void elink_xgxs_an_resolve(struct elink_phy *phy,
6348 struct elink_params *params,
6349 struct elink_vars *vars,
6352 if (gp_status & ELINK_MDIO_AN_CL73_OR_37_COMPLETE)
6353 vars->link_status |=
6354 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6356 if (elink_direct_parallel_detect_used(phy, params))
6357 vars->link_status |=
6358 LINK_STATUS_PARALLEL_DETECTION_USED;
6360 static elink_status_t elink_get_link_speed_duplex(struct elink_phy *phy,
6361 struct elink_params *params,
6362 struct elink_vars *vars,
6363 uint16_t is_link_up,
6364 uint16_t speed_mask,
6367 struct bxe_softc *sc = params->sc;
6368 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6369 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_ENABLED;
6371 ELINK_DEBUG_P0(sc, "phy link up\n");
6373 vars->phy_link_up = 1;
6374 vars->link_status |= LINK_STATUS_LINK_UP;
6376 switch (speed_mask) {
6377 case ELINK_GP_STATUS_10M:
6378 vars->line_speed = ELINK_SPEED_10;
6379 if (is_duplex == DUPLEX_FULL)
6380 vars->link_status |= ELINK_LINK_10TFD;
6382 vars->link_status |= ELINK_LINK_10THD;
6385 case ELINK_GP_STATUS_100M:
6386 vars->line_speed = ELINK_SPEED_100;
6387 if (is_duplex == DUPLEX_FULL)
6388 vars->link_status |= ELINK_LINK_100TXFD;
6390 vars->link_status |= ELINK_LINK_100TXHD;
6393 case ELINK_GP_STATUS_1G:
6394 case ELINK_GP_STATUS_1G_KX:
6395 vars->line_speed = ELINK_SPEED_1000;
6396 if (is_duplex == DUPLEX_FULL)
6397 vars->link_status |= ELINK_LINK_1000TFD;
6399 vars->link_status |= ELINK_LINK_1000THD;
6402 case ELINK_GP_STATUS_2_5G:
6403 vars->line_speed = ELINK_SPEED_2500;
6404 if (is_duplex == DUPLEX_FULL)
6405 vars->link_status |= ELINK_LINK_2500TFD;
6407 vars->link_status |= ELINK_LINK_2500THD;
6410 case ELINK_GP_STATUS_5G:
6411 case ELINK_GP_STATUS_6G:
6413 "link speed unsupported gp_status 0x%x\n",
6415 return ELINK_STATUS_ERROR;
6417 case ELINK_GP_STATUS_10G_KX4:
6418 case ELINK_GP_STATUS_10G_HIG:
6419 case ELINK_GP_STATUS_10G_CX4:
6420 case ELINK_GP_STATUS_10G_KR:
6421 case ELINK_GP_STATUS_10G_SFI:
6422 case ELINK_GP_STATUS_10G_XFI:
6423 vars->line_speed = ELINK_SPEED_10000;
6424 vars->link_status |= ELINK_LINK_10GTFD;
6426 case ELINK_GP_STATUS_20G_DXGXS:
6427 case ELINK_GP_STATUS_20G_KR2:
6428 vars->line_speed = ELINK_SPEED_20000;
6429 vars->link_status |= ELINK_LINK_20GTFD;
6433 "link speed unsupported gp_status 0x%x\n",
6435 return ELINK_STATUS_ERROR;
6437 } else { /* link_down */
6438 ELINK_DEBUG_P0(sc, "phy link down\n");
6440 vars->phy_link_up = 0;
6442 vars->duplex = DUPLEX_FULL;
6443 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
6444 vars->mac_type = ELINK_MAC_TYPE_NONE;
6446 ELINK_DEBUG_P2(sc, " phy_link_up %x line_speed %d\n",
6447 vars->phy_link_up, vars->line_speed);
6448 return ELINK_STATUS_OK;
6451 static elink_status_t elink_link_settings_status(struct elink_phy *phy,
6452 struct elink_params *params,
6453 struct elink_vars *vars)
6455 struct bxe_softc *sc = params->sc;
6457 uint16_t gp_status, duplex = DUPLEX_HALF, link_up = 0, speed_mask;
6458 elink_status_t rc = ELINK_STATUS_OK;
6460 /* Read gp_status */
6461 CL22_RD_OVER_CL45(sc, phy,
6462 MDIO_REG_BANK_GP_STATUS,
6463 MDIO_GP_STATUS_TOP_AN_STATUS1,
6465 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_DUPLEX_STATUS)
6466 duplex = DUPLEX_FULL;
6467 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS)
6469 speed_mask = gp_status & ELINK_GP_STATUS_SPEED_MASK;
6470 ELINK_DEBUG_P3(sc, "gp_status 0x%x, is_link_up %d, speed_mask 0x%x\n",
6471 gp_status, link_up, speed_mask);
6472 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, speed_mask,
6474 if (rc == ELINK_STATUS_ERROR)
6477 if (gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS) {
6478 if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
6479 vars->duplex = duplex;
6480 elink_flow_ctrl_resolve(phy, params, vars, gp_status);
6481 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)
6482 elink_xgxs_an_resolve(phy, params, vars,
6485 } else { /* Link_down */
6486 if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
6487 ELINK_SINGLE_MEDIA_DIRECT(params)) {
6488 /* Check signal is detected */
6489 elink_check_fallback_to_cl37(phy, params);
6493 /* Read LP advertised speeds*/
6494 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6495 (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)) {
6498 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_CL73_IEEEB1,
6499 MDIO_CL73_IEEEB1_AN_LP_ADV2, &val);
6501 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
6502 vars->link_status |=
6503 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
6504 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
6505 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
6506 vars->link_status |=
6507 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6509 CL22_RD_OVER_CL45(sc, phy, MDIO_REG_BANK_OVER_1G,
6510 MDIO_OVER_1G_LP_UP1, &val);
6512 if (val & MDIO_OVER_1G_UP1_2_5G)
6513 vars->link_status |=
6514 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
6515 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
6516 vars->link_status |=
6517 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6520 ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
6521 vars->duplex, vars->flow_ctrl, vars->link_status);
6525 static elink_status_t elink_warpcore_read_status(struct elink_phy *phy,
6526 struct elink_params *params,
6527 struct elink_vars *vars)
6529 struct bxe_softc *sc = params->sc;
6531 uint16_t gp_status1, gp_speed, link_up, duplex = DUPLEX_FULL;
6532 elink_status_t rc = ELINK_STATUS_OK;
6533 lane = elink_get_warpcore_lane(phy, params);
6534 /* Read gp_status */
6535 if ((params->loopback_mode) &&
6536 (phy->flags & ELINK_FLAGS_WC_DUAL_MODE)) {
6537 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6538 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
6539 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6540 MDIO_WC_REG_DIGITAL5_LINK_STATUS, &link_up);
6542 } else if ((phy->req_line_speed > ELINK_SPEED_10000) &&
6543 (phy->supported & ELINK_SUPPORTED_20000baseMLD2_Full)) {
6544 uint16_t temp_link_up;
6545 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6547 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6549 ELINK_DEBUG_P2(sc, "PCS RX link status = 0x%x-->0x%x\n",
6550 temp_link_up, link_up);
6553 elink_ext_phy_resolve_fc(phy, params, vars);
6555 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6556 MDIO_WC_REG_GP2_STATUS_GP_2_1,
6558 ELINK_DEBUG_P1(sc, "0x81d1 = 0x%x\n", gp_status1);
6559 /* Check for either KR, 1G, or AN up. */
6560 link_up = ((gp_status1 >> 8) |
6561 (gp_status1 >> 12) |
6564 if (phy->supported & ELINK_SUPPORTED_20000baseKR2_Full) {
6566 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6567 MDIO_AN_REG_STATUS, &an_link);
6568 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6569 MDIO_AN_REG_STATUS, &an_link);
6570 link_up |= (an_link & (1<<2));
6572 if (link_up && ELINK_SINGLE_MEDIA_DIRECT(params)) {
6573 uint16_t pd, gp_status4;
6574 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
6575 /* Check Autoneg complete */
6576 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6577 MDIO_WC_REG_GP2_STATUS_GP_2_4,
6579 if (gp_status4 & ((1<<12)<<lane))
6580 vars->link_status |=
6581 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
6583 /* Check parallel detect used */
6584 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6585 MDIO_WC_REG_PAR_DET_10G_STATUS,
6588 vars->link_status |=
6589 LINK_STATUS_PARALLEL_DETECTION_USED;
6591 elink_ext_phy_resolve_fc(phy, params, vars);
6592 vars->duplex = duplex;
6596 if ((vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) &&
6597 ELINK_SINGLE_MEDIA_DIRECT(params)) {
6600 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
6601 MDIO_AN_REG_LP_AUTO_NEG2, &val);
6603 if (val & MDIO_CL73_IEEEB1_AN_ADV2_ADVR_1000M_KX)
6604 vars->link_status |=
6605 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
6606 if (val & (MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KX4 |
6607 MDIO_CL73_IEEEB1_AN_ADV2_ADVR_10G_KR))
6608 vars->link_status |=
6609 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6611 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6612 MDIO_WC_REG_DIGITAL3_LP_UP1, &val);
6614 if (val & MDIO_OVER_1G_UP1_2_5G)
6615 vars->link_status |=
6616 LINK_STATUS_LINK_PARTNER_2500XFD_CAPABLE;
6617 if (val & (MDIO_OVER_1G_UP1_10G | MDIO_OVER_1G_UP1_10GH))
6618 vars->link_status |=
6619 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
6625 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6626 MDIO_WC_REG_GP2_STATUS_GP_2_2, &gp_speed);
6628 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
6629 MDIO_WC_REG_GP2_STATUS_GP_2_3, &gp_speed);
6631 ELINK_DEBUG_P2(sc, "lane %d gp_speed 0x%x\n", lane, gp_speed);
6633 if ((lane & 1) == 0)
6636 link_up = !!link_up;
6638 /* Reset the TX FIFO to fix SGMII issue */
6639 rc = elink_get_link_speed_duplex(phy, params, vars, link_up, gp_speed,
6642 /* In case of KR link down, start up the recovering procedure */
6643 if ((!link_up) && (phy->media_type == ELINK_ETH_PHY_KR) &&
6644 (!(phy->flags & ELINK_FLAGS_WC_DUAL_MODE)))
6645 vars->rx_tx_asic_rst = MAX_KR_LINK_RETRY;
6647 ELINK_DEBUG_P3(sc, "duplex %x flow_ctrl 0x%x link_status 0x%x\n",
6648 vars->duplex, vars->flow_ctrl, vars->link_status);
6651 static void elink_set_gmii_tx_driver(struct elink_params *params)
6653 struct bxe_softc *sc = params->sc;
6654 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
6660 CL22_RD_OVER_CL45(sc, phy,
6661 MDIO_REG_BANK_OVER_1G,
6662 MDIO_OVER_1G_LP_UP2, &lp_up2);
6664 /* Bits [10:7] at lp_up2, positioned at [15:12] */
6665 lp_up2 = (((lp_up2 & MDIO_OVER_1G_LP_UP2_PREEMPHASIS_MASK) >>
6666 MDIO_OVER_1G_LP_UP2_PREEMPHASIS_SHIFT) <<
6667 MDIO_TX0_TX_DRIVER_PREEMPHASIS_SHIFT);
6672 for (bank = MDIO_REG_BANK_TX0; bank <= MDIO_REG_BANK_TX3;
6673 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0)) {
6674 CL22_RD_OVER_CL45(sc, phy,
6676 MDIO_TX0_TX_DRIVER, &tx_driver);
6678 /* Replace tx_driver bits [15:12] */
6680 (tx_driver & MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK)) {
6681 tx_driver &= ~MDIO_TX0_TX_DRIVER_PREEMPHASIS_MASK;
6682 tx_driver |= lp_up2;
6683 CL22_WR_OVER_CL45(sc, phy,
6685 MDIO_TX0_TX_DRIVER, tx_driver);
6690 static elink_status_t elink_emac_program(struct elink_params *params,
6691 struct elink_vars *vars)
6693 struct bxe_softc *sc = params->sc;
6694 uint8_t port = params->port;
6697 ELINK_DEBUG_P0(sc, "setting link speed & duplex\n");
6698 elink_bits_dis(sc, GRCBASE_EMAC0 + port*0x400 +
6700 (EMAC_MODE_25G_MODE |
6701 EMAC_MODE_PORT_MII_10M |
6702 EMAC_MODE_HALF_DUPLEX));
6703 switch (vars->line_speed) {
6704 case ELINK_SPEED_10:
6705 mode |= EMAC_MODE_PORT_MII_10M;
6708 case ELINK_SPEED_100:
6709 mode |= EMAC_MODE_PORT_MII;
6712 case ELINK_SPEED_1000:
6713 mode |= EMAC_MODE_PORT_GMII;
6716 case ELINK_SPEED_2500:
6717 mode |= (EMAC_MODE_25G_MODE | EMAC_MODE_PORT_GMII);
6721 /* 10G not valid for EMAC */
6722 ELINK_DEBUG_P1(sc, "Invalid line_speed 0x%x\n",
6724 return ELINK_STATUS_ERROR;
6727 if (vars->duplex == DUPLEX_HALF)
6728 mode |= EMAC_MODE_HALF_DUPLEX;
6730 GRCBASE_EMAC0 + port*0x400 + EMAC_REG_EMAC_MODE,
6733 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
6734 return ELINK_STATUS_OK;
6737 static void elink_set_preemphasis(struct elink_phy *phy,
6738 struct elink_params *params)
6741 uint16_t bank, i = 0;
6742 struct bxe_softc *sc = params->sc;
6744 for (bank = MDIO_REG_BANK_RX0, i = 0; bank <= MDIO_REG_BANK_RX3;
6745 bank += (MDIO_REG_BANK_RX1-MDIO_REG_BANK_RX0), i++) {
6746 CL22_WR_OVER_CL45(sc, phy,
6748 MDIO_RX0_RX_EQ_BOOST,
6749 phy->rx_preemphasis[i]);
6752 for (bank = MDIO_REG_BANK_TX0, i = 0; bank <= MDIO_REG_BANK_TX3;
6753 bank += (MDIO_REG_BANK_TX1 - MDIO_REG_BANK_TX0), i++) {
6754 CL22_WR_OVER_CL45(sc, phy,
6757 phy->tx_preemphasis[i]);
6761 static void elink_xgxs_config_init(struct elink_phy *phy,
6762 struct elink_params *params,
6763 struct elink_vars *vars)
6765 struct bxe_softc *sc = params->sc;
6766 uint8_t enable_cl73 = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
6767 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
6768 if (!(vars->phy_flags & PHY_SGMII_FLAG)) {
6769 if (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6770 (params->feature_config_flags &
6771 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED))
6772 elink_set_preemphasis(phy, params);
6774 /* Forced speed requested? */
6775 if (vars->line_speed != ELINK_SPEED_AUTO_NEG ||
6776 (ELINK_SINGLE_MEDIA_DIRECT(params) &&
6777 params->loopback_mode == ELINK_LOOPBACK_EXT)) {
6778 ELINK_DEBUG_P0(sc, "not SGMII, no AN\n");
6780 /* Disable autoneg */
6781 elink_set_autoneg(phy, params, vars, 0);
6783 /* Program speed and duplex */
6784 elink_program_serdes(phy, params, vars);
6786 } else { /* AN_mode */
6787 ELINK_DEBUG_P0(sc, "not SGMII, AN\n");
6790 elink_set_brcm_cl37_advertisement(phy, params);
6792 /* Program duplex & pause advertisement (for aneg) */
6793 elink_set_ieee_aneg_advertisement(phy, params,
6796 /* Enable autoneg */
6797 elink_set_autoneg(phy, params, vars, enable_cl73);
6799 /* Enable and restart AN */
6800 elink_restart_autoneg(phy, params, enable_cl73);
6803 } else { /* SGMII mode */
6804 ELINK_DEBUG_P0(sc, "SGMII\n");
6806 elink_initialize_sgmii_process(phy, params, vars);
6810 static elink_status_t elink_prepare_xgxs(struct elink_phy *phy,
6811 struct elink_params *params,
6812 struct elink_vars *vars)
6815 vars->phy_flags |= PHY_XGXS_FLAG;
6816 if ((phy->req_line_speed &&
6817 ((phy->req_line_speed == ELINK_SPEED_100) ||
6818 (phy->req_line_speed == ELINK_SPEED_10))) ||
6819 (!phy->req_line_speed &&
6820 (phy->speed_cap_mask >=
6821 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
6822 (phy->speed_cap_mask <
6823 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
6824 (phy->type == PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT_SD))
6825 vars->phy_flags |= PHY_SGMII_FLAG;
6827 vars->phy_flags &= ~PHY_SGMII_FLAG;
6829 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
6830 elink_set_aer_mmd(params, phy);
6831 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
6832 elink_set_master_ln(params, phy);
6834 rc = elink_reset_unicore(params, phy, 0);
6835 /* Reset the SerDes and wait for reset bit return low */
6836 if (rc != ELINK_STATUS_OK)
6839 elink_set_aer_mmd(params, phy);
6840 /* Setting the masterLn_def again after the reset */
6841 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) {
6842 elink_set_master_ln(params, phy);
6843 elink_set_swap_lanes(params, phy);
6849 static uint16_t elink_wait_reset_complete(struct bxe_softc *sc,
6850 struct elink_phy *phy,
6851 struct elink_params *params)
6854 /* Wait for soft reset to get cleared up to 1 sec */
6855 for (cnt = 0; cnt < 1000; cnt++) {
6856 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
6857 elink_cl22_read(sc, phy,
6858 MDIO_PMA_REG_CTRL, &ctrl);
6860 elink_cl45_read(sc, phy,
6862 MDIO_PMA_REG_CTRL, &ctrl);
6863 if (!(ctrl & (1<<15)))
6869 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, params->port); // "Warning: PHY was not initialized,"
6872 ELINK_DEBUG_P2(sc, "control reg 0x%x (after %d ms)\n", ctrl, cnt);
6876 static void elink_link_int_enable(struct elink_params *params)
6878 uint8_t port = params->port;
6880 struct bxe_softc *sc = params->sc;
6882 /* Setting the status to report on link up for either XGXS or SerDes */
6883 if (CHIP_IS_E3(sc)) {
6884 mask = ELINK_NIG_MASK_XGXS0_LINK_STATUS;
6885 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)))
6886 mask |= ELINK_NIG_MASK_MI_INT;
6887 } else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
6888 mask = (ELINK_NIG_MASK_XGXS0_LINK10G |
6889 ELINK_NIG_MASK_XGXS0_LINK_STATUS);
6890 ELINK_DEBUG_P0(sc, "enabled XGXS interrupt\n");
6891 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6892 params->phy[ELINK_INT_PHY].type !=
6893 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE) {
6894 mask |= ELINK_NIG_MASK_MI_INT;
6895 ELINK_DEBUG_P0(sc, "enabled external phy int\n");
6898 } else { /* SerDes */
6899 mask = ELINK_NIG_MASK_SERDES0_LINK_STATUS;
6900 ELINK_DEBUG_P0(sc, "enabled SerDes interrupt\n");
6901 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) &&
6902 params->phy[ELINK_INT_PHY].type !=
6903 PORT_HW_CFG_SERDES_EXT_PHY_TYPE_NOT_CONN) {
6904 mask |= ELINK_NIG_MASK_MI_INT;
6905 ELINK_DEBUG_P0(sc, "enabled external phy int\n");
6909 NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
6912 ELINK_DEBUG_P3(sc, "port %x, is_xgxs %x, int_status 0x%x\n", port,
6913 (params->switch_cfg == ELINK_SWITCH_CFG_10G),
6914 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
6915 ELINK_DEBUG_P3(sc, " int_mask 0x%x, MI_INT %x, SERDES_LINK %x\n",
6916 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
6917 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18),
6918 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS+port*0x3c));
6919 ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x\n",
6920 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
6921 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
6924 static void elink_rearm_latch_signal(struct bxe_softc *sc, uint8_t port,
6927 uint32_t latch_status = 0;
6929 /* Disable the MI INT ( external phy int ) by writing 1 to the
6930 * status register. Link down indication is high-active-signal,
6931 * so in this case we need to write the status to clear the XOR
6933 /* Read Latched signals */
6934 latch_status = REG_RD(sc,
6935 NIG_REG_LATCH_STATUS_0 + port*8);
6936 ELINK_DEBUG_P1(sc, "latch_status = 0x%x\n", latch_status);
6937 /* Handle only those with latched-signal=up.*/
6940 NIG_REG_STATUS_INTERRUPT_PORT0
6942 ELINK_NIG_STATUS_EMAC0_MI_INT);
6945 NIG_REG_STATUS_INTERRUPT_PORT0
6947 ELINK_NIG_STATUS_EMAC0_MI_INT);
6949 if (latch_status & 1) {
6951 /* For all latched-signal=up : Re-Arm Latch signals */
6952 REG_WR(sc, NIG_REG_LATCH_STATUS_0 + port*8,
6953 (latch_status & 0xfffe) | (latch_status & 1));
6955 /* For all latched-signal=up,Write original_signal to status */
6958 static void elink_link_int_ack(struct elink_params *params,
6959 struct elink_vars *vars, uint8_t is_10g_plus)
6961 struct bxe_softc *sc = params->sc;
6962 uint8_t port = params->port;
6964 /* First reset all status we assume only one line will be
6967 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6968 (ELINK_NIG_STATUS_XGXS0_LINK10G |
6969 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
6970 ELINK_NIG_STATUS_SERDES0_LINK_STATUS));
6971 if (vars->phy_link_up) {
6972 if (USES_WARPCORE(sc))
6973 mask = ELINK_NIG_STATUS_XGXS0_LINK_STATUS;
6976 mask = ELINK_NIG_STATUS_XGXS0_LINK10G;
6977 else if (params->switch_cfg == ELINK_SWITCH_CFG_10G) {
6978 /* Disable the link interrupt by writing 1 to
6979 * the relevant lane in the status register
6982 ((params->lane_config &
6983 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_MASK) >>
6984 PORT_HW_CFG_LANE_SWAP_CFG_MASTER_SHIFT);
6985 mask = ((1 << ser_lane) <<
6986 ELINK_NIG_STATUS_XGXS0_LINK_STATUS_SIZE);
6988 mask = ELINK_NIG_STATUS_SERDES0_LINK_STATUS;
6990 ELINK_DEBUG_P1(sc, "Ack link up interrupt with mask 0x%x\n",
6993 NIG_REG_STATUS_INTERRUPT_PORT0 + port*4,
6998 static elink_status_t elink_format_ver(uint32_t num, uint8_t *str, uint16_t *len)
7000 uint8_t *str_ptr = str;
7001 uint32_t mask = 0xf0000000;
7002 uint8_t shift = 8*4;
7004 uint8_t remove_leading_zeros = 1;
7006 /* Need more than 10chars for this format */
7009 return ELINK_STATUS_ERROR;
7014 digit = ((num & mask) >> shift);
7015 if (digit == 0 && remove_leading_zeros) {
7018 } else if (digit < 0xa)
7019 *str_ptr = digit + '0';
7021 *str_ptr = digit - 0xa + 'a';
7022 remove_leading_zeros = 0;
7030 remove_leading_zeros = 1;
7033 return ELINK_STATUS_OK;
7037 static elink_status_t elink_null_format_ver(uint32_t spirom_ver, uint8_t *str, uint16_t *len)
7041 return ELINK_STATUS_OK;
7044 elink_status_t elink_get_ext_phy_fw_version(struct elink_params *params, uint8_t *version,
7047 struct bxe_softc *sc;
7048 uint32_t spirom_ver = 0;
7049 elink_status_t status = ELINK_STATUS_OK;
7050 uint8_t *ver_p = version;
7051 uint16_t remain_len = len;
7052 if (version == NULL || params == NULL)
7053 return ELINK_STATUS_ERROR;
7056 /* Extract first external phy*/
7058 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY1].ver_addr);
7060 if (params->phy[ELINK_EXT_PHY1].format_fw_ver) {
7061 status |= params->phy[ELINK_EXT_PHY1].format_fw_ver(spirom_ver,
7064 ver_p += (len - remain_len);
7066 if ((params->num_phys == ELINK_MAX_PHYS) &&
7067 (params->phy[ELINK_EXT_PHY2].ver_addr != 0)) {
7068 spirom_ver = REG_RD(sc, params->phy[ELINK_EXT_PHY2].ver_addr);
7069 if (params->phy[ELINK_EXT_PHY2].format_fw_ver) {
7073 status |= params->phy[ELINK_EXT_PHY2].format_fw_ver(
7077 ver_p = version + (len - remain_len);
7084 static void elink_set_xgxs_loopback(struct elink_phy *phy,
7085 struct elink_params *params)
7087 uint8_t port = params->port;
7088 struct bxe_softc *sc = params->sc;
7090 if (phy->req_line_speed != ELINK_SPEED_1000) {
7091 uint32_t md_devad = 0;
7093 ELINK_DEBUG_P0(sc, "XGXS 10G loopback enable\n");
7095 if (!CHIP_IS_E3(sc)) {
7096 /* Change the uni_phy_addr in the nig */
7097 md_devad = REG_RD(sc, (NIG_REG_XGXS0_CTRL_MD_DEVAD +
7100 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
7104 elink_cl45_write(sc, phy,
7106 (MDIO_REG_BANK_AER_BLOCK +
7107 (MDIO_AER_BLOCK_AER_REG & 0xf)),
7110 elink_cl45_write(sc, phy,
7112 (MDIO_REG_BANK_CL73_IEEEB0 +
7113 (MDIO_CL73_IEEEB0_CL73_AN_CONTROL & 0xf)),
7116 /* Set aer mmd back */
7117 elink_set_aer_mmd(params, phy);
7119 if (!CHIP_IS_E3(sc)) {
7121 REG_WR(sc, NIG_REG_XGXS0_CTRL_MD_DEVAD + port*0x18,
7126 ELINK_DEBUG_P0(sc, "XGXS 1G loopback enable\n");
7127 elink_cl45_read(sc, phy, 5,
7128 (MDIO_REG_BANK_COMBO_IEEE0 +
7129 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
7131 elink_cl45_write(sc, phy, 5,
7132 (MDIO_REG_BANK_COMBO_IEEE0 +
7133 (MDIO_COMBO_IEEE0_MII_CONTROL & 0xf)),
7135 MDIO_COMBO_IEEO_MII_CONTROL_LOOPBACK);
7139 elink_status_t elink_set_led(struct elink_params *params,
7140 struct elink_vars *vars, uint8_t mode, uint32_t speed)
7142 uint8_t port = params->port;
7143 uint16_t hw_led_mode = params->hw_led_mode;
7144 elink_status_t rc = ELINK_STATUS_OK;
7147 uint32_t emac_base = port ? GRCBASE_EMAC1 : GRCBASE_EMAC0;
7148 struct bxe_softc *sc = params->sc;
7149 ELINK_DEBUG_P2(sc, "elink_set_led: port %x, mode %d\n", port, mode);
7150 ELINK_DEBUG_P2(sc, "speed 0x%x, hw_led_mode 0x%x\n",
7151 speed, hw_led_mode);
7153 for (phy_idx = ELINK_EXT_PHY1; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7154 if (params->phy[phy_idx].set_link_led) {
7155 params->phy[phy_idx].set_link_led(
7156 ¶ms->phy[phy_idx], params, mode);
7159 #ifdef ELINK_INCLUDE_EMUL
7160 if (params->feature_config_flags &
7161 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC)
7166 case ELINK_LED_MODE_FRONT_PANEL_OFF:
7167 case ELINK_LED_MODE_OFF:
7168 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 0);
7169 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7170 SHARED_HW_CFG_LED_MAC1);
7172 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7173 if (params->phy[ELINK_EXT_PHY1].type ==
7174 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
7175 tmp &= ~(EMAC_LED_1000MB_OVERRIDE |
7176 EMAC_LED_100MB_OVERRIDE |
7177 EMAC_LED_10MB_OVERRIDE);
7179 tmp |= EMAC_LED_OVERRIDE;
7181 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp);
7184 case ELINK_LED_MODE_OPER:
7185 /* For all other phys, OPER mode is same as ON, so in case
7186 * link is down, do nothing
7190 case ELINK_LED_MODE_ON:
7191 if (((params->phy[ELINK_EXT_PHY1].type ==
7192 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727) ||
7193 (params->phy[ELINK_EXT_PHY1].type ==
7194 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722)) &&
7195 CHIP_IS_E2(sc) && params->num_phys == 2) {
7196 /* This is a work-around for E2+8727 Configurations */
7197 if (mode == ELINK_LED_MODE_ON ||
7198 speed == ELINK_SPEED_10000){
7199 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7200 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1);
7202 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7203 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
7204 (tmp | EMAC_LED_OVERRIDE));
7205 /* Return here without enabling traffic
7206 * LED blink and setting rate in ON mode.
7207 * In oper mode, enabling LED blink
7208 * and setting rate is needed.
7210 if (mode == ELINK_LED_MODE_ON)
7213 } else if (ELINK_SINGLE_MEDIA_DIRECT(params)) {
7214 /* This is a work-around for HW issue found when link
7217 if ((!CHIP_IS_E3(sc)) ||
7219 mode == ELINK_LED_MODE_ON))
7220 REG_WR(sc, NIG_REG_LED_10G_P0 + port*4, 1);
7222 if (CHIP_IS_E1x(sc) ||
7224 (mode == ELINK_LED_MODE_ON))
7225 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7227 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7229 } else if ((params->phy[ELINK_EXT_PHY1].type ==
7230 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE) &&
7231 (mode == ELINK_LED_MODE_ON)) {
7232 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4, 0);
7233 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7234 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED, tmp |
7235 EMAC_LED_OVERRIDE | EMAC_LED_1000MB_OVERRIDE);
7236 /* Break here; otherwise, it'll disable the
7237 * intended override.
7241 uint32_t nig_led_mode = ((params->hw_led_mode <<
7242 SHARED_HW_CFG_LED_MODE_SHIFT) ==
7243 SHARED_HW_CFG_LED_EXTPHY2) ?
7244 (SHARED_HW_CFG_LED_PHY1 >>
7245 SHARED_HW_CFG_LED_MODE_SHIFT) : hw_led_mode;
7246 REG_WR(sc, NIG_REG_LED_MODE_P0 + port*4,
7250 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0 + port*4, 0);
7251 /* Set blinking rate to ~15.9Hz */
7253 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7254 LED_BLINK_RATE_VAL_E3);
7256 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_P0 + port*4,
7257 LED_BLINK_RATE_VAL_E1X_E2);
7258 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_RATE_ENA_P0 +
7260 tmp = elink_cb_reg_read(sc, emac_base + EMAC_REG_EMAC_LED);
7261 elink_cb_reg_write(sc, emac_base + EMAC_REG_EMAC_LED,
7262 (tmp & (~EMAC_LED_OVERRIDE)));
7264 if (CHIP_IS_E1(sc) &&
7265 ((speed == ELINK_SPEED_2500) ||
7266 (speed == ELINK_SPEED_1000) ||
7267 (speed == ELINK_SPEED_100) ||
7268 (speed == ELINK_SPEED_10))) {
7269 /* For speeds less than 10G LED scheme is different */
7270 REG_WR(sc, NIG_REG_LED_CONTROL_OVERRIDE_TRAFFIC_P0
7272 REG_WR(sc, NIG_REG_LED_CONTROL_TRAFFIC_P0 +
7274 REG_WR(sc, NIG_REG_LED_CONTROL_BLINK_TRAFFIC_P0 +
7280 rc = ELINK_STATUS_ERROR;
7281 ELINK_DEBUG_P1(sc, "elink_set_led: Invalid led mode %d\n",
7289 /* This function comes to reflect the actual link state read DIRECTLY from the
7292 elink_status_t elink_test_link(struct elink_params *params, struct elink_vars *vars,
7295 struct bxe_softc *sc = params->sc;
7296 uint16_t gp_status = 0, phy_index = 0;
7297 uint8_t ext_phy_link_up = 0, serdes_phy_type;
7298 struct elink_vars temp_vars;
7299 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
7300 #ifdef ELINK_INCLUDE_FPGA
7301 if (CHIP_REV_IS_FPGA(sc))
7302 return ELINK_STATUS_OK;
7304 #ifdef ELINK_INCLUDE_EMUL
7305 if (CHIP_REV_IS_EMUL(sc))
7306 return ELINK_STATUS_OK;
7309 if (CHIP_IS_E3(sc)) {
7311 if (params->req_line_speed[ELINK_LINK_CONFIG_IDX(ELINK_INT_PHY)]
7312 > ELINK_SPEED_10000) {
7313 /* Check 20G link */
7314 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7316 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7320 /* Check 10G link and below*/
7321 uint8_t lane = elink_get_warpcore_lane(int_phy, params);
7322 elink_cl45_read(sc, int_phy, MDIO_WC_DEVAD,
7323 MDIO_WC_REG_GP2_STATUS_GP_2_1,
7325 gp_status = ((gp_status >> 8) & 0xf) |
7326 ((gp_status >> 12) & 0xf);
7327 link_up = gp_status & (1 << lane);
7330 return ELINK_STATUS_NO_LINK;
7332 CL22_RD_OVER_CL45(sc, int_phy,
7333 MDIO_REG_BANK_GP_STATUS,
7334 MDIO_GP_STATUS_TOP_AN_STATUS1,
7336 /* Link is up only if both local phy and external phy are up */
7337 if (!(gp_status & MDIO_GP_STATUS_TOP_AN_STATUS1_LINK_STATUS))
7338 return ELINK_STATUS_NO_LINK;
7340 /* In XGXS loopback mode, do not check external PHY */
7341 if (params->loopback_mode == ELINK_LOOPBACK_XGXS)
7342 return ELINK_STATUS_OK;
7344 switch (params->num_phys) {
7346 /* No external PHY */
7347 return ELINK_STATUS_OK;
7349 ext_phy_link_up = params->phy[ELINK_EXT_PHY1].read_status(
7350 ¶ms->phy[ELINK_EXT_PHY1],
7351 params, &temp_vars);
7353 case 3: /* Dual Media */
7354 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7356 serdes_phy_type = ((params->phy[phy_index].media_type ==
7357 ELINK_ETH_PHY_SFPP_10G_FIBER) ||
7358 (params->phy[phy_index].media_type ==
7359 ELINK_ETH_PHY_SFP_1G_FIBER) ||
7360 (params->phy[phy_index].media_type ==
7361 ELINK_ETH_PHY_XFP_FIBER) ||
7362 (params->phy[phy_index].media_type ==
7363 ELINK_ETH_PHY_DA_TWINAX));
7365 if (is_serdes != serdes_phy_type)
7367 if (params->phy[phy_index].read_status) {
7369 params->phy[phy_index].read_status(
7370 ¶ms->phy[phy_index],
7371 params, &temp_vars);
7376 if (ext_phy_link_up)
7377 return ELINK_STATUS_OK;
7378 return ELINK_STATUS_NO_LINK;
7381 static elink_status_t elink_link_initialize(struct elink_params *params,
7382 struct elink_vars *vars)
7384 uint8_t phy_index, non_ext_phy;
7385 struct bxe_softc *sc = params->sc;
7386 /* In case of external phy existence, the line speed would be the
7387 * line speed linked up by the external phy. In case it is direct
7388 * only, then the line_speed during initialization will be
7389 * equal to the req_line_speed
7391 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
7393 /* Initialize the internal phy in case this is a direct board
7394 * (no external phys), or this board has external phy which requires
7397 if (!USES_WARPCORE(sc))
7398 elink_prepare_xgxs(¶ms->phy[ELINK_INT_PHY], params, vars);
7399 /* init ext phy and enable link state int */
7400 non_ext_phy = (ELINK_SINGLE_MEDIA_DIRECT(params) ||
7401 (params->loopback_mode == ELINK_LOOPBACK_XGXS));
7404 (params->phy[ELINK_EXT_PHY1].flags & ELINK_FLAGS_INIT_XGXS_FIRST) ||
7405 (params->loopback_mode == ELINK_LOOPBACK_EXT_PHY)) {
7406 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
7407 if (vars->line_speed == ELINK_SPEED_AUTO_NEG &&
7410 elink_set_parallel_detection(phy, params);
7411 if (params->phy[ELINK_INT_PHY].config_init)
7412 params->phy[ELINK_INT_PHY].config_init(phy, params, vars);
7415 /* Re-read this value in case it was changed inside config_init due to
7416 * limitations of optic module
7418 vars->line_speed = params->phy[ELINK_INT_PHY].req_line_speed;
7420 /* Init external phy*/
7422 if (params->phy[ELINK_INT_PHY].supported &
7423 ELINK_SUPPORTED_FIBRE)
7424 vars->link_status |= LINK_STATUS_SERDES_LINK;
7426 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7428 /* No need to initialize second phy in case of first
7429 * phy only selection. In case of second phy, we do
7430 * need to initialize the first phy, since they are
7433 if (params->phy[phy_index].supported &
7434 ELINK_SUPPORTED_FIBRE)
7435 vars->link_status |= LINK_STATUS_SERDES_LINK;
7437 if (phy_index == ELINK_EXT_PHY2 &&
7438 (elink_phy_selection(params) ==
7439 PORT_HW_CFG_PHY_SELECTION_FIRST_PHY)) {
7441 "Not initializing second phy\n");
7444 params->phy[phy_index].config_init(
7445 ¶ms->phy[phy_index],
7449 /* Reset the interrupt indication after phy was initialized */
7450 elink_bits_dis(sc, NIG_REG_STATUS_INTERRUPT_PORT0 +
7452 (ELINK_NIG_STATUS_XGXS0_LINK10G |
7453 ELINK_NIG_STATUS_XGXS0_LINK_STATUS |
7454 ELINK_NIG_STATUS_SERDES0_LINK_STATUS |
7455 ELINK_NIG_MASK_MI_INT));
7456 return ELINK_STATUS_OK;
7459 static void elink_int_link_reset(struct elink_phy *phy,
7460 struct elink_params *params)
7462 /* Reset the SerDes/XGXS */
7463 REG_WR(params->sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_3_CLEAR,
7464 (0x1ff << (params->port*16)));
7467 static void elink_common_ext_link_reset(struct elink_phy *phy,
7468 struct elink_params *params)
7470 struct bxe_softc *sc = params->sc;
7474 gpio_port = SC_PATH(sc);
7476 gpio_port = params->port;
7477 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7478 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7480 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
7481 MISC_REGISTERS_GPIO_OUTPUT_LOW,
7483 ELINK_DEBUG_P0(sc, "reset external PHY\n");
7486 static elink_status_t elink_update_link_down(struct elink_params *params,
7487 struct elink_vars *vars)
7489 struct bxe_softc *sc = params->sc;
7490 uint8_t port = params->port;
7492 ELINK_DEBUG_P1(sc, "Port %x: Link is down\n", port);
7493 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
7494 vars->phy_flags &= ~PHY_PHYSICAL_LINK_FLAG;
7495 /* Indicate no mac active */
7496 vars->mac_type = ELINK_MAC_TYPE_NONE;
7498 /* Update shared memory */
7499 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
7500 vars->line_speed = 0;
7501 elink_update_mng(params, vars->link_status);
7503 /* Activate nig drain */
7504 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
7507 if (!CHIP_IS_E3(sc))
7508 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7511 /* Reset BigMac/Xmac */
7512 if (CHIP_IS_E1x(sc) ||
7514 elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
7516 if (CHIP_IS_E3(sc)) {
7517 /* Prevent LPI Generation by chip */
7518 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 + (params->port << 2),
7520 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 + (params->port << 2),
7522 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
7523 SHMEM_EEE_ACTIVE_BIT);
7525 elink_update_mng_eee(params, vars->eee_status);
7526 elink_set_xmac_rxtx(params, 0);
7527 elink_set_umac_rxtx(params, 0);
7530 return ELINK_STATUS_OK;
7533 static elink_status_t elink_update_link_up(struct elink_params *params,
7534 struct elink_vars *vars,
7537 struct bxe_softc *sc = params->sc;
7538 uint8_t phy_idx, port = params->port;
7539 elink_status_t rc = ELINK_STATUS_OK;
7541 vars->link_status |= (LINK_STATUS_LINK_UP |
7542 LINK_STATUS_PHYSICAL_LINK_FLAG);
7543 vars->phy_flags |= PHY_PHYSICAL_LINK_FLAG;
7545 if (vars->flow_ctrl & ELINK_FLOW_CTRL_TX)
7546 vars->link_status |=
7547 LINK_STATUS_TX_FLOW_CONTROL_ENABLED;
7549 if (vars->flow_ctrl & ELINK_FLOW_CTRL_RX)
7550 vars->link_status |=
7551 LINK_STATUS_RX_FLOW_CONTROL_ENABLED;
7552 if (USES_WARPCORE(sc)) {
7554 if (elink_xmac_enable(params, vars, 0) ==
7555 ELINK_STATUS_NO_LINK) {
7556 ELINK_DEBUG_P0(sc, "Found errors on XMAC\n");
7558 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
7559 vars->link_status &= ~LINK_STATUS_LINK_UP;
7562 elink_umac_enable(params, vars, 0);
7563 elink_set_led(params, vars,
7564 ELINK_LED_MODE_OPER, vars->line_speed);
7566 if ((vars->eee_status & SHMEM_EEE_ACTIVE_BIT) &&
7567 (vars->eee_status & SHMEM_EEE_LPI_REQUESTED_BIT)) {
7568 ELINK_DEBUG_P0(sc, "Enabling LPI assertion\n");
7569 REG_WR(sc, MISC_REG_CPMU_LP_FW_ENABLE_P0 +
7570 (params->port << 2), 1);
7571 REG_WR(sc, MISC_REG_CPMU_LP_DR_ENABLE, 1);
7572 REG_WR(sc, MISC_REG_CPMU_LP_MASK_ENT_P0 +
7573 (params->port << 2), 0xfc20);
7576 if ((CHIP_IS_E1x(sc) ||
7579 if (elink_bmac_enable(params, vars, 0, 1) ==
7580 ELINK_STATUS_NO_LINK) {
7581 ELINK_DEBUG_P0(sc, "Found errors on BMAC\n");
7583 vars->phy_flags |= PHY_HALF_OPEN_CONN_FLAG;
7584 vars->link_status &= ~LINK_STATUS_LINK_UP;
7587 elink_set_led(params, vars,
7588 ELINK_LED_MODE_OPER, ELINK_SPEED_10000);
7590 rc = elink_emac_program(params, vars);
7591 elink_emac_enable(params, vars, 0);
7594 if ((vars->link_status &
7595 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE)
7596 && (!(vars->phy_flags & PHY_SGMII_FLAG)) &&
7597 ELINK_SINGLE_MEDIA_DIRECT(params))
7598 elink_set_gmii_tx_driver(params);
7603 if (CHIP_IS_E1x(sc))
7604 rc |= elink_pbf_update(params, vars->flow_ctrl,
7608 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 0);
7610 /* Update shared memory */
7611 elink_update_mng(params, vars->link_status);
7612 elink_update_mng_eee(params, vars->eee_status);
7613 /* Check remote fault */
7614 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
7615 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
7616 elink_check_half_open_conn(params, vars, 0);
7624 static void elink_chng_link_count(struct elink_params *params, uint8_t clear)
7626 struct bxe_softc *sc = params->sc;
7629 /* Verify the link_change_count is supported by the MFW */
7630 if (!(SHMEM2_HAS(sc, link_change_count)))
7633 addr = params->shmem2_base +
7634 offsetof(struct shmem2_region, link_change_count[params->port]);
7638 val = REG_RD(sc, addr) + 1;
7639 REG_WR(sc, addr, val);
7642 /* The elink_link_update function should be called upon link
7644 * Link is considered up as follows:
7645 * - DIRECT_SINGLE_MEDIA - Only XGXS link (internal link) needs
7647 * - SINGLE_MEDIA - The link between the 577xx and the external
7648 * phy (XGXS) need to up as well as the external link of the
7650 * - DUAL_MEDIA - The link between the 577xx and the first
7651 * external phy needs to be up, and at least one of the 2
7652 * external phy link must be up.
7654 elink_status_t elink_link_update(struct elink_params *params, struct elink_vars *vars)
7656 struct bxe_softc *sc = params->sc;
7657 struct elink_vars phy_vars[ELINK_MAX_PHYS];
7658 uint8_t port = params->port;
7659 uint8_t link_10g_plus, phy_index;
7660 uint32_t prev_link_status = vars->link_status;
7661 uint8_t ext_phy_link_up = 0, cur_link_up;
7662 elink_status_t rc = ELINK_STATUS_OK;
7663 uint16_t ext_phy_line_speed = 0, prev_line_speed = vars->line_speed;
7664 uint8_t active_external_phy = ELINK_INT_PHY;
7665 vars->phy_flags &= ~PHY_HALF_OPEN_CONN_FLAG;
7666 vars->link_status &= ~ELINK_LINK_UPDATE_MASK;
7667 for (phy_index = ELINK_INT_PHY; phy_index < params->num_phys;
7669 phy_vars[phy_index].flow_ctrl = 0;
7670 phy_vars[phy_index].link_status = 0;
7671 phy_vars[phy_index].line_speed = 0;
7672 phy_vars[phy_index].duplex = DUPLEX_FULL;
7673 phy_vars[phy_index].phy_link_up = 0;
7674 phy_vars[phy_index].link_up = 0;
7675 phy_vars[phy_index].fault_detected = 0;
7676 /* different consideration, since vars holds inner state */
7677 phy_vars[phy_index].eee_status = vars->eee_status;
7680 if (USES_WARPCORE(sc))
7681 elink_set_aer_mmd(params, ¶ms->phy[ELINK_INT_PHY]);
7683 ELINK_DEBUG_P3(sc, "port %x, XGXS?%x, int_status 0x%x\n",
7684 port, (vars->phy_flags & PHY_XGXS_FLAG),
7685 REG_RD(sc, NIG_REG_STATUS_INTERRUPT_PORT0 + port*4));
7687 ELINK_DEBUG_P3(sc, "int_mask 0x%x MI_INT %x, SERDES_LINK %x\n",
7688 REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4),
7689 REG_RD(sc, NIG_REG_EMAC0_STATUS_MISC_MI_INT + port*0x18) > 0,
7690 REG_RD(sc, NIG_REG_SERDES0_STATUS_LINK_STATUS + port*0x3c));
7692 ELINK_DEBUG_P2(sc, " 10G %x, XGXS_LINK %x\n",
7693 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK10G + port*0x68),
7694 REG_RD(sc, NIG_REG_XGXS0_STATUS_LINK_STATUS + port*0x68));
7697 if (!CHIP_IS_E3(sc))
7698 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
7701 * Check external link change only for external phys, and apply
7702 * priority selection between them in case the link on both phys
7703 * is up. Note that instead of the common vars, a temporary
7704 * vars argument is used since each phy may have different link/
7705 * speed/duplex result
7707 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7709 struct elink_phy *phy = ¶ms->phy[phy_index];
7710 if (!phy->read_status)
7712 /* Read link status and params of this ext phy */
7713 cur_link_up = phy->read_status(phy, params,
7714 &phy_vars[phy_index]);
7716 ELINK_DEBUG_P1(sc, "phy in index %d link is up\n",
7719 ELINK_DEBUG_P1(sc, "phy in index %d link is down\n",
7724 if (!ext_phy_link_up) {
7725 ext_phy_link_up = 1;
7726 active_external_phy = phy_index;
7728 switch (elink_phy_selection(params)) {
7729 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
7730 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
7731 /* In this option, the first PHY makes sure to pass the
7732 * traffic through itself only.
7733 * Its not clear how to reset the link on the second phy
7735 active_external_phy = ELINK_EXT_PHY1;
7737 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
7738 /* In this option, the first PHY makes sure to pass the
7739 * traffic through the second PHY.
7741 active_external_phy = ELINK_EXT_PHY2;
7744 /* Link indication on both PHYs with the following cases
7746 * - FIRST_PHY means that second phy wasn't initialized,
7747 * hence its link is expected to be down
7748 * - SECOND_PHY means that first phy should not be able
7749 * to link up by itself (using configuration)
7750 * - DEFAULT should be overriden during initialiazation
7752 ELINK_DEBUG_P1(sc, "Invalid link indication"
7753 "mpc=0x%x. DISABLING LINK !!!\n",
7754 params->multi_phy_config);
7755 ext_phy_link_up = 0;
7760 prev_line_speed = vars->line_speed;
7762 * Read the status of the internal phy. In case of
7763 * DIRECT_SINGLE_MEDIA board, this link is the external link,
7764 * otherwise this is the link between the 577xx and the first
7767 if (params->phy[ELINK_INT_PHY].read_status)
7768 params->phy[ELINK_INT_PHY].read_status(
7769 ¶ms->phy[ELINK_INT_PHY],
7771 /* The INT_PHY flow control reside in the vars. This include the
7772 * case where the speed or flow control are not set to AUTO.
7773 * Otherwise, the active external phy flow control result is set
7774 * to the vars. The ext_phy_line_speed is needed to check if the
7775 * speed is different between the internal phy and external phy.
7776 * This case may be result of intermediate link speed change.
7778 if (active_external_phy > ELINK_INT_PHY) {
7779 vars->flow_ctrl = phy_vars[active_external_phy].flow_ctrl;
7780 /* Link speed is taken from the XGXS. AN and FC result from
7783 vars->link_status |= phy_vars[active_external_phy].link_status;
7785 /* if active_external_phy is first PHY and link is up - disable
7786 * disable TX on second external PHY
7788 if (active_external_phy == ELINK_EXT_PHY1) {
7789 if (params->phy[ELINK_EXT_PHY2].phy_specific_func) {
7791 "Disabling TX on EXT_PHY2\n");
7792 params->phy[ELINK_EXT_PHY2].phy_specific_func(
7793 ¶ms->phy[ELINK_EXT_PHY2],
7794 params, ELINK_DISABLE_TX);
7798 ext_phy_line_speed = phy_vars[active_external_phy].line_speed;
7799 vars->duplex = phy_vars[active_external_phy].duplex;
7800 if (params->phy[active_external_phy].supported &
7801 ELINK_SUPPORTED_FIBRE)
7802 vars->link_status |= LINK_STATUS_SERDES_LINK;
7804 vars->link_status &= ~LINK_STATUS_SERDES_LINK;
7806 vars->eee_status = phy_vars[active_external_phy].eee_status;
7808 ELINK_DEBUG_P1(sc, "Active external phy selected: %x\n",
7809 active_external_phy);
7812 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
7814 if (params->phy[phy_index].flags &
7815 ELINK_FLAGS_REARM_LATCH_SIGNAL) {
7816 elink_rearm_latch_signal(sc, port,
7818 active_external_phy);
7822 ELINK_DEBUG_P3(sc, "vars->flow_ctrl = 0x%x, vars->link_status = 0x%x,"
7823 " ext_phy_line_speed = %d\n", vars->flow_ctrl,
7824 vars->link_status, ext_phy_line_speed);
7825 /* Upon link speed change set the NIG into drain mode. Comes to
7826 * deals with possible FIFO glitch due to clk change when speed
7827 * is decreased without link down indicator
7830 if (vars->phy_link_up) {
7831 if (!(ELINK_SINGLE_MEDIA_DIRECT(params)) && ext_phy_link_up &&
7832 (ext_phy_line_speed != vars->line_speed)) {
7833 ELINK_DEBUG_P2(sc, "Internal link speed %d is"
7834 " different than the external"
7835 " link speed %d\n", vars->line_speed,
7836 ext_phy_line_speed);
7837 vars->phy_link_up = 0;
7838 } else if (prev_line_speed != vars->line_speed) {
7839 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4,
7845 /* Anything 10 and over uses the bmac */
7846 link_10g_plus = (vars->line_speed >= ELINK_SPEED_10000);
7848 elink_link_int_ack(params, vars, link_10g_plus);
7850 /* In case external phy link is up, and internal link is down
7851 * (not initialized yet probably after link initialization, it
7852 * needs to be initialized.
7853 * Note that after link down-up as result of cable plug, the xgxs
7854 * link would probably become up again without the need
7857 if (!(ELINK_SINGLE_MEDIA_DIRECT(params))) {
7858 ELINK_DEBUG_P3(sc, "ext_phy_link_up = %d, int_link_up = %d,"
7859 " init_preceding = %d\n", ext_phy_link_up,
7861 params->phy[ELINK_EXT_PHY1].flags &
7862 ELINK_FLAGS_INIT_XGXS_FIRST);
7863 if (!(params->phy[ELINK_EXT_PHY1].flags &
7864 ELINK_FLAGS_INIT_XGXS_FIRST)
7865 && ext_phy_link_up && !vars->phy_link_up) {
7866 vars->line_speed = ext_phy_line_speed;
7867 if (vars->line_speed < ELINK_SPEED_1000)
7868 vars->phy_flags |= PHY_SGMII_FLAG;
7870 vars->phy_flags &= ~PHY_SGMII_FLAG;
7872 if (params->phy[ELINK_INT_PHY].config_init)
7873 params->phy[ELINK_INT_PHY].config_init(
7874 ¶ms->phy[ELINK_INT_PHY], params,
7878 /* Link is up only if both local phy and external phy (in case of
7879 * non-direct board) are up and no fault detected on active PHY.
7881 vars->link_up = (vars->phy_link_up &&
7883 ELINK_SINGLE_MEDIA_DIRECT(params)) &&
7884 (phy_vars[active_external_phy].fault_detected == 0));
7886 /* Update the PFC configuration in case it was changed */
7887 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
7888 vars->link_status |= LINK_STATUS_PFC_ENABLED;
7890 vars->link_status &= ~LINK_STATUS_PFC_ENABLED;
7893 rc = elink_update_link_up(params, vars, link_10g_plus);
7895 rc = elink_update_link_down(params, vars);
7897 if ((prev_link_status ^ vars->link_status) & LINK_STATUS_LINK_UP)
7898 elink_chng_link_count(params, 0);
7900 /* Update MCP link status was changed */
7901 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_BC_SUPPORTS_AFEX)
7902 elink_cb_fw_command(sc, DRV_MSG_CODE_LINK_STATUS_CHANGED, 0);
7907 /*****************************************************************************/
7908 /* External Phy section */
7909 /*****************************************************************************/
7910 void elink_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port)
7912 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7913 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
7915 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
7916 MISC_REGISTERS_GPIO_OUTPUT_HIGH, port);
7919 static void elink_save_spirom_version(struct bxe_softc *sc, uint8_t port,
7920 uint32_t spirom_ver, uint32_t ver_addr)
7922 ELINK_DEBUG_P3(sc, "FW version 0x%x:0x%x for port %d\n",
7923 (uint16_t)(spirom_ver>>16), (uint16_t)spirom_ver, port);
7926 REG_WR(sc, ver_addr, spirom_ver);
7929 static void elink_save_bcm_spirom_ver(struct bxe_softc *sc,
7930 struct elink_phy *phy,
7933 uint16_t fw_ver1, fw_ver2;
7935 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7936 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
7937 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
7938 MDIO_PMA_REG_ROM_VER2, &fw_ver2);
7939 elink_save_spirom_version(sc, port, (uint32_t)(fw_ver1<<16 | fw_ver2),
7943 static void elink_ext_phy_10G_an_resolve(struct bxe_softc *sc,
7944 struct elink_phy *phy,
7945 struct elink_vars *vars)
7948 elink_cl45_read(sc, phy,
7950 MDIO_AN_REG_STATUS, &val);
7951 elink_cl45_read(sc, phy,
7953 MDIO_AN_REG_STATUS, &val);
7955 vars->link_status |= LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
7956 if ((val & (1<<0)) == 0)
7957 vars->link_status |= LINK_STATUS_PARALLEL_DETECTION_USED;
7960 /******************************************************************/
7961 /* common BCM8073/BCM8727 PHY SECTION */
7962 /******************************************************************/
7963 static void elink_8073_resolve_fc(struct elink_phy *phy,
7964 struct elink_params *params,
7965 struct elink_vars *vars)
7967 struct bxe_softc *sc = params->sc;
7968 if (phy->req_line_speed == ELINK_SPEED_10 ||
7969 phy->req_line_speed == ELINK_SPEED_100) {
7970 vars->flow_ctrl = phy->req_flow_ctrl;
7974 if (elink_ext_phy_resolve_fc(phy, params, vars) &&
7975 (vars->flow_ctrl == ELINK_FLOW_CTRL_NONE)) {
7976 uint16_t pause_result;
7977 uint16_t ld_pause; /* local */
7978 uint16_t lp_pause; /* link partner */
7979 elink_cl45_read(sc, phy,
7981 MDIO_AN_REG_CL37_FC_LD, &ld_pause);
7983 elink_cl45_read(sc, phy,
7985 MDIO_AN_REG_CL37_FC_LP, &lp_pause);
7986 pause_result = (ld_pause &
7987 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 5;
7988 pause_result |= (lp_pause &
7989 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) >> 7;
7991 elink_pause_resolve(phy, params, vars, pause_result);
7992 ELINK_DEBUG_P1(sc, "Ext PHY CL37 pause result 0x%x\n",
7996 static elink_status_t elink_8073_8727_external_rom_boot(struct bxe_softc *sc,
7997 struct elink_phy *phy,
8001 uint16_t fw_ver1, fw_msgout;
8002 elink_status_t rc = ELINK_STATUS_OK;
8004 /* Boot port from external ROM */
8006 elink_cl45_write(sc, phy,
8008 MDIO_PMA_REG_GEN_CTRL,
8011 /* Ucode reboot and rst */
8012 elink_cl45_write(sc, phy,
8014 MDIO_PMA_REG_GEN_CTRL,
8017 elink_cl45_write(sc, phy,
8019 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
8021 /* Reset internal microprocessor */
8022 elink_cl45_write(sc, phy,
8024 MDIO_PMA_REG_GEN_CTRL,
8025 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
8027 /* Release srst bit */
8028 elink_cl45_write(sc, phy,
8030 MDIO_PMA_REG_GEN_CTRL,
8031 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
8033 /* Delay 100ms per the PHY specifications */
8036 /* 8073 sometimes taking longer to download */
8041 "elink_8073_8727_external_rom_boot port %x:"
8042 "Download failed. fw version = 0x%x\n",
8044 rc = ELINK_STATUS_ERROR;
8048 elink_cl45_read(sc, phy,
8050 MDIO_PMA_REG_ROM_VER1, &fw_ver1);
8051 elink_cl45_read(sc, phy,
8053 MDIO_PMA_REG_M8051_MSGOUT_REG, &fw_msgout);
8056 } while (fw_ver1 == 0 || fw_ver1 == 0x4321 ||
8057 ((fw_msgout & 0xff) != 0x03 && (phy->type ==
8058 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073)));
8060 /* Clear ser_boot_ctl bit */
8061 elink_cl45_write(sc, phy,
8063 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
8064 elink_save_bcm_spirom_ver(sc, phy, port);
8067 "elink_8073_8727_external_rom_boot port %x:"
8068 "Download complete. fw version = 0x%x\n",
8074 /******************************************************************/
8075 /* BCM8073 PHY SECTION */
8076 /******************************************************************/
8077 static elink_status_t elink_8073_is_snr_needed(struct bxe_softc *sc, struct elink_phy *phy)
8079 /* This is only required for 8073A1, version 102 only */
8082 /* Read 8073 HW revision*/
8083 elink_cl45_read(sc, phy,
8085 MDIO_PMA_REG_8073_CHIP_REV, &val);
8088 /* No need to workaround in 8073 A1 */
8089 return ELINK_STATUS_OK;
8092 elink_cl45_read(sc, phy,
8094 MDIO_PMA_REG_ROM_VER2, &val);
8096 /* SNR should be applied only for version 0x102 */
8098 return ELINK_STATUS_OK;
8103 static elink_status_t elink_8073_xaui_wa(struct bxe_softc *sc, struct elink_phy *phy)
8105 uint16_t val, cnt, cnt1 ;
8107 elink_cl45_read(sc, phy,
8109 MDIO_PMA_REG_8073_CHIP_REV, &val);
8112 /* No need to workaround in 8073 A1 */
8113 return ELINK_STATUS_OK;
8115 /* XAUI workaround in 8073 A0: */
8117 /* After loading the boot ROM and restarting Autoneg, poll
8121 for (cnt = 0; cnt < 1000; cnt++) {
8122 elink_cl45_read(sc, phy,
8124 MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
8126 /* If bit [14] = 0 or bit [13] = 0, continue on with
8127 * system initialization (XAUI work-around not required, as
8128 * these bits indicate 2.5G or 1G link up).
8130 if (!(val & (1<<14)) || !(val & (1<<13))) {
8131 ELINK_DEBUG_P0(sc, "XAUI work-around not required\n");
8132 return ELINK_STATUS_OK;
8133 } else if (!(val & (1<<15))) {
8134 ELINK_DEBUG_P0(sc, "bit 15 went off\n");
8135 /* If bit 15 is 0, then poll Dev1, Reg $C841 until it's
8136 * MSB (bit15) goes to 1 (indicating that the XAUI
8137 * workaround has completed), then continue on with
8138 * system initialization.
8140 for (cnt1 = 0; cnt1 < 1000; cnt1++) {
8141 elink_cl45_read(sc, phy,
8143 MDIO_PMA_REG_8073_XAUI_WA, &val);
8144 if (val & (1<<15)) {
8146 "XAUI workaround has completed\n");
8147 return ELINK_STATUS_OK;
8155 ELINK_DEBUG_P0(sc, "Warning: XAUI work-around timeout !!!\n");
8156 return ELINK_STATUS_ERROR;
8159 static void elink_807x_force_10G(struct bxe_softc *sc, struct elink_phy *phy)
8161 /* Force KR or KX */
8162 elink_cl45_write(sc, phy,
8163 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
8164 elink_cl45_write(sc, phy,
8165 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0x000b);
8166 elink_cl45_write(sc, phy,
8167 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0000);
8168 elink_cl45_write(sc, phy,
8169 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
8172 static void elink_8073_set_pause_cl37(struct elink_params *params,
8173 struct elink_phy *phy,
8174 struct elink_vars *vars)
8177 struct bxe_softc *sc = params->sc;
8178 elink_cl45_read(sc, phy,
8179 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &cl37_val);
8181 cl37_val &= ~MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
8182 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
8183 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
8184 if ((vars->ieee_fc &
8185 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) ==
8186 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC) {
8187 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_SYMMETRIC;
8189 if ((vars->ieee_fc &
8190 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
8191 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) {
8192 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC;
8194 if ((vars->ieee_fc &
8195 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
8196 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) {
8197 cl37_val |= MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH;
8200 "Ext phy AN advertize cl37 0x%x\n", cl37_val);
8202 elink_cl45_write(sc, phy,
8203 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, cl37_val);
8207 static void elink_8073_specific_func(struct elink_phy *phy,
8208 struct elink_params *params,
8211 struct bxe_softc *sc = params->sc;
8213 case ELINK_PHY_INIT:
8215 elink_cl45_write(sc, phy,
8216 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL, (1<<2));
8217 elink_cl45_write(sc, phy,
8218 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0004);
8223 static elink_status_t elink_8073_config_init(struct elink_phy *phy,
8224 struct elink_params *params,
8225 struct elink_vars *vars)
8227 struct bxe_softc *sc = params->sc;
8228 uint16_t val = 0, tmp1;
8230 ELINK_DEBUG_P0(sc, "Init 8073\n");
8233 gpio_port = SC_PATH(sc);
8235 gpio_port = params->port;
8236 /* Restore normal power mode*/
8237 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8238 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
8240 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
8241 MISC_REGISTERS_GPIO_OUTPUT_HIGH, gpio_port);
8243 elink_8073_specific_func(phy, params, ELINK_PHY_INIT);
8244 elink_8073_set_pause_cl37(params, phy, vars);
8246 elink_cl45_read(sc, phy,
8247 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
8249 elink_cl45_read(sc, phy,
8250 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
8252 ELINK_DEBUG_P1(sc, "Before rom RX_ALARM(port1): 0x%x\n", tmp1);
8254 /* Swap polarity if required - Must be done only in non-1G mode */
8255 if (params->lane_config & PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
8256 /* Configure the 8073 to swap _P and _N of the KR lines */
8257 ELINK_DEBUG_P0(sc, "Swapping polarity for the 8073\n");
8258 /* 10G Rx/Tx and 1G Tx signal polarity swap */
8259 elink_cl45_read(sc, phy,
8261 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL, &val);
8262 elink_cl45_write(sc, phy,
8264 MDIO_PMA_REG_8073_OPT_DIGITAL_CTRL,
8269 /* Enable CL37 BAM */
8270 if (REG_RD(sc, params->shmem_base +
8271 offsetof(struct shmem_region, dev_info.
8272 port_hw_config[params->port].default_cfg)) &
8273 PORT_HW_CFG_ENABLE_BAM_ON_KR_ENABLED) {
8275 elink_cl45_read(sc, phy,
8277 MDIO_AN_REG_8073_BAM, &val);
8278 elink_cl45_write(sc, phy,
8280 MDIO_AN_REG_8073_BAM, val | 1);
8281 ELINK_DEBUG_P0(sc, "Enable CL37 BAM on KR\n");
8283 if (params->loopback_mode == ELINK_LOOPBACK_EXT) {
8284 elink_807x_force_10G(sc, phy);
8285 ELINK_DEBUG_P0(sc, "Forced speed 10G on 807X\n");
8286 return ELINK_STATUS_OK;
8288 elink_cl45_write(sc, phy,
8289 MDIO_PMA_DEVAD, MDIO_PMA_REG_BCM_CTRL, 0x0002);
8291 if (phy->req_line_speed != ELINK_SPEED_AUTO_NEG) {
8292 if (phy->req_line_speed == ELINK_SPEED_10000) {
8294 } else if (phy->req_line_speed == ELINK_SPEED_2500) {
8296 /* Note that 2.5G works only when used with 1G
8303 if (phy->speed_cap_mask &
8304 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)
8307 /* Note that 2.5G works only when used with 1G advertisement */
8308 if (phy->speed_cap_mask &
8309 (PORT_HW_CFG_SPEED_CAPABILITY_D0_1G |
8310 PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G))
8312 ELINK_DEBUG_P1(sc, "807x autoneg val = 0x%x\n", val);
8315 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV, val);
8316 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, &tmp1);
8318 if (((phy->speed_cap_mask & PORT_HW_CFG_SPEED_CAPABILITY_D0_2_5G) &&
8319 (phy->req_line_speed == ELINK_SPEED_AUTO_NEG)) ||
8320 (phy->req_line_speed == ELINK_SPEED_2500)) {
8322 /* Allow 2.5G for A1 and above */
8323 elink_cl45_read(sc, phy,
8324 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_CHIP_REV,
8326 ELINK_DEBUG_P0(sc, "Add 2.5G\n");
8332 ELINK_DEBUG_P0(sc, "Disable 2.5G\n");
8336 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_8073_2_5G, tmp1);
8337 /* Add support for CL37 (passive mode) II */
8339 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, &tmp1);
8340 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD,
8341 (tmp1 | ((phy->req_duplex == DUPLEX_FULL) ?
8344 /* Add support for CL37 (passive mode) III */
8345 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
8347 /* The SNR will improve about 2db by changing BW and FEE main
8348 * tap. Rest commands are executed after link is up
8349 * Change FFE main cursor to 5 in EDC register
8351 if (elink_8073_is_snr_needed(sc, phy))
8352 elink_cl45_write(sc, phy,
8353 MDIO_PMA_DEVAD, MDIO_PMA_REG_EDC_FFE_MAIN,
8356 /* Enable FEC (Forware Error Correction) Request in the AN */
8357 elink_cl45_read(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, &tmp1);
8359 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_ADV2, tmp1);
8361 elink_ext_phy_set_pause(params, phy, vars);
8363 /* Restart autoneg */
8365 elink_cl45_write(sc, phy, MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
8366 ELINK_DEBUG_P2(sc, "807x Autoneg Restart: Advertise 1G=%x, 10G=%x\n",
8367 ((val & (1<<5)) > 0), ((val & (1<<7)) > 0));
8368 return ELINK_STATUS_OK;
8371 static uint8_t elink_8073_read_status(struct elink_phy *phy,
8372 struct elink_params *params,
8373 struct elink_vars *vars)
8375 struct bxe_softc *sc = params->sc;
8376 uint8_t link_up = 0;
8377 uint16_t val1, val2;
8378 uint16_t link_status = 0;
8379 uint16_t an1000_status = 0;
8381 elink_cl45_read(sc, phy,
8382 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
8384 ELINK_DEBUG_P1(sc, "8703 LASI status 0x%x\n", val1);
8386 /* Clear the interrupt LASI status register */
8387 elink_cl45_read(sc, phy,
8388 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
8389 elink_cl45_read(sc, phy,
8390 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val1);
8391 ELINK_DEBUG_P2(sc, "807x PCS status 0x%x->0x%x\n", val2, val1);
8393 elink_cl45_read(sc, phy,
8394 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
8396 /* Check the LASI */
8397 elink_cl45_read(sc, phy,
8398 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
8400 ELINK_DEBUG_P1(sc, "KR 0x9003 0x%x\n", val2);
8402 /* Check the link status */
8403 elink_cl45_read(sc, phy,
8404 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &val2);
8405 ELINK_DEBUG_P1(sc, "KR PCS status 0x%x\n", val2);
8407 elink_cl45_read(sc, phy,
8408 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
8409 elink_cl45_read(sc, phy,
8410 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
8411 link_up = ((val1 & 4) == 4);
8412 ELINK_DEBUG_P1(sc, "PMA_REG_STATUS=0x%x\n", val1);
8415 ((phy->req_line_speed != ELINK_SPEED_10000))) {
8416 if (elink_8073_xaui_wa(sc, phy) != 0)
8419 elink_cl45_read(sc, phy,
8420 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
8421 elink_cl45_read(sc, phy,
8422 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &an1000_status);
8424 /* Check the link status on 1.1.2 */
8425 elink_cl45_read(sc, phy,
8426 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
8427 elink_cl45_read(sc, phy,
8428 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
8429 ELINK_DEBUG_P3(sc, "KR PMA status 0x%x->0x%x,"
8430 "an_link_status=0x%x\n", val2, val1, an1000_status);
8432 link_up = (((val1 & 4) == 4) || (an1000_status & (1<<1)));
8433 if (link_up && elink_8073_is_snr_needed(sc, phy)) {
8434 /* The SNR will improve about 2dbby changing the BW and FEE main
8435 * tap. The 1st write to change FFE main tap is set before
8436 * restart AN. Change PLL Bandwidth in EDC register
8438 elink_cl45_write(sc, phy,
8439 MDIO_PMA_DEVAD, MDIO_PMA_REG_PLL_BANDWIDTH,
8442 /* Change CDR Bandwidth in EDC register */
8443 elink_cl45_write(sc, phy,
8444 MDIO_PMA_DEVAD, MDIO_PMA_REG_CDR_BANDWIDTH,
8447 elink_cl45_read(sc, phy,
8448 MDIO_PMA_DEVAD, MDIO_PMA_REG_8073_SPEED_LINK_STATUS,
8451 /* Bits 0..2 --> speed detected, bits 13..15--> link is down */
8452 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
8454 vars->line_speed = ELINK_SPEED_10000;
8455 ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n",
8457 } else if ((link_status & (1<<1)) && (!(link_status & (1<<14)))) {
8459 vars->line_speed = ELINK_SPEED_2500;
8460 ELINK_DEBUG_P1(sc, "port %x: External link up in 2.5G\n",
8462 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
8464 vars->line_speed = ELINK_SPEED_1000;
8465 ELINK_DEBUG_P1(sc, "port %x: External link up in 1G\n",
8469 ELINK_DEBUG_P1(sc, "port %x: External link is down\n",
8474 /* Swap polarity if required */
8475 if (params->lane_config &
8476 PORT_HW_CFG_SWAP_PHY_POLARITY_ENABLED) {
8477 /* Configure the 8073 to swap P and N of the KR lines */
8478 elink_cl45_read(sc, phy,
8480 MDIO_XS_REG_8073_RX_CTRL_PCIE, &val1);
8481 /* Set bit 3 to invert Rx in 1G mode and clear this bit
8482 * when it`s in 10G mode.
8484 if (vars->line_speed == ELINK_SPEED_1000) {
8485 ELINK_DEBUG_P0(sc, "Swapping 1G polarity for"
8491 elink_cl45_write(sc, phy,
8493 MDIO_XS_REG_8073_RX_CTRL_PCIE,
8496 elink_ext_phy_10G_an_resolve(sc, phy, vars);
8497 elink_8073_resolve_fc(phy, params, vars);
8498 vars->duplex = DUPLEX_FULL;
8501 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
8502 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
8503 MDIO_AN_REG_LP_AUTO_NEG2, &val1);
8506 vars->link_status |=
8507 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
8509 vars->link_status |=
8510 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
8516 static void elink_8073_link_reset(struct elink_phy *phy,
8517 struct elink_params *params)
8519 struct bxe_softc *sc = params->sc;
8522 gpio_port = SC_PATH(sc);
8524 gpio_port = params->port;
8525 ELINK_DEBUG_P1(sc, "Setting 8073 port %d into low power mode\n",
8527 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8528 MISC_REGISTERS_GPIO_OUTPUT_LOW,
8532 /******************************************************************/
8533 /* BCM8705 PHY SECTION */
8534 /******************************************************************/
8535 static elink_status_t elink_8705_config_init(struct elink_phy *phy,
8536 struct elink_params *params,
8537 struct elink_vars *vars)
8539 struct bxe_softc *sc = params->sc;
8540 ELINK_DEBUG_P0(sc, "init 8705\n");
8541 /* Restore normal power mode*/
8542 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
8543 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
8545 elink_ext_phy_hw_reset(sc, params->port);
8546 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
8547 elink_wait_reset_complete(sc, phy, params);
8549 elink_cl45_write(sc, phy,
8550 MDIO_PMA_DEVAD, MDIO_PMA_REG_MISC_CTRL, 0x8288);
8551 elink_cl45_write(sc, phy,
8552 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, 0x7fbf);
8553 elink_cl45_write(sc, phy,
8554 MDIO_PMA_DEVAD, MDIO_PMA_REG_CMU_PLL_BYPASS, 0x0100);
8555 elink_cl45_write(sc, phy,
8556 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_CNTL, 0x1);
8557 /* BCM8705 doesn't have microcode, hence the 0 */
8558 elink_save_spirom_version(sc, params->port, params->shmem_base, 0);
8559 return ELINK_STATUS_OK;
8562 static uint8_t elink_8705_read_status(struct elink_phy *phy,
8563 struct elink_params *params,
8564 struct elink_vars *vars)
8566 uint8_t link_up = 0;
8567 uint16_t val1, rx_sd;
8568 struct bxe_softc *sc = params->sc;
8569 ELINK_DEBUG_P0(sc, "read status 8705\n");
8570 elink_cl45_read(sc, phy,
8571 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
8572 ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x\n", val1);
8574 elink_cl45_read(sc, phy,
8575 MDIO_WIS_DEVAD, MDIO_WIS_REG_LASI_STATUS, &val1);
8576 ELINK_DEBUG_P1(sc, "8705 LASI status 0x%x\n", val1);
8578 elink_cl45_read(sc, phy,
8579 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
8581 elink_cl45_read(sc, phy,
8582 MDIO_PMA_DEVAD, 0xc809, &val1);
8583 elink_cl45_read(sc, phy,
8584 MDIO_PMA_DEVAD, 0xc809, &val1);
8586 ELINK_DEBUG_P1(sc, "8705 1.c809 val=0x%x\n", val1);
8587 link_up = ((rx_sd & 0x1) && (val1 & (1<<9)) && ((val1 & (1<<8)) == 0));
8589 vars->line_speed = ELINK_SPEED_10000;
8590 elink_ext_phy_resolve_fc(phy, params, vars);
8595 /******************************************************************/
8596 /* SFP+ module Section */
8597 /******************************************************************/
8598 static void elink_set_disable_pmd_transmit(struct elink_params *params,
8599 struct elink_phy *phy,
8602 struct bxe_softc *sc = params->sc;
8603 /* Disable transmitter only for bootcodes which can enable it afterwards
8607 if (params->feature_config_flags &
8608 ELINK_FEATURE_CONFIG_BC_SUPPORTS_SFP_TX_DISABLED) {
8609 ELINK_DEBUG_P0(sc, "Disabling PMD transmitter\n");
8611 ELINK_DEBUG_P0(sc, "NOT disabling PMD transmitter\n");
8615 ELINK_DEBUG_P0(sc, "Enabling PMD transmitter\n");
8616 elink_cl45_write(sc, phy,
8618 MDIO_PMA_REG_TX_DISABLE, pmd_dis);
8621 static uint8_t elink_get_gpio_port(struct elink_params *params)
8624 uint32_t swap_val, swap_override;
8625 struct bxe_softc *sc = params->sc;
8627 gpio_port = SC_PATH(sc);
8629 gpio_port = params->port;
8630 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
8631 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
8632 return gpio_port ^ (swap_val && swap_override);
8635 static void elink_sfp_e1e2_set_transmitter(struct elink_params *params,
8636 struct elink_phy *phy,
8640 uint8_t port = params->port;
8641 struct bxe_softc *sc = params->sc;
8642 uint32_t tx_en_mode;
8644 /* Disable/Enable transmitter ( TX laser of the SFP+ module.)*/
8645 tx_en_mode = REG_RD(sc, params->shmem_base +
8646 offsetof(struct shmem_region,
8647 dev_info.port_hw_config[port].sfp_ctrl)) &
8648 PORT_HW_CFG_TX_LASER_MASK;
8649 ELINK_DEBUG_P3(sc, "Setting transmitter tx_en=%x for port %x "
8650 "mode = %x\n", tx_en, port, tx_en_mode);
8651 switch (tx_en_mode) {
8652 case PORT_HW_CFG_TX_LASER_MDIO:
8654 elink_cl45_read(sc, phy,
8656 MDIO_PMA_REG_PHY_IDENTIFIER,
8664 elink_cl45_write(sc, phy,
8666 MDIO_PMA_REG_PHY_IDENTIFIER,
8669 case PORT_HW_CFG_TX_LASER_GPIO0:
8670 case PORT_HW_CFG_TX_LASER_GPIO1:
8671 case PORT_HW_CFG_TX_LASER_GPIO2:
8672 case PORT_HW_CFG_TX_LASER_GPIO3:
8675 uint8_t gpio_port, gpio_mode;
8677 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_HIGH;
8679 gpio_mode = MISC_REGISTERS_GPIO_OUTPUT_LOW;
8681 gpio_pin = tx_en_mode - PORT_HW_CFG_TX_LASER_GPIO0;
8682 gpio_port = elink_get_gpio_port(params);
8683 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
8687 ELINK_DEBUG_P1(sc, "Invalid TX_LASER_MDIO 0x%x\n", tx_en_mode);
8692 static void elink_sfp_set_transmitter(struct elink_params *params,
8693 struct elink_phy *phy,
8696 struct bxe_softc *sc = params->sc;
8697 ELINK_DEBUG_P1(sc, "Setting SFP+ transmitter to %d\n", tx_en);
8699 elink_sfp_e3_set_transmitter(params, phy, tx_en);
8701 elink_sfp_e1e2_set_transmitter(params, phy, tx_en);
8704 static elink_status_t elink_8726_read_sfp_module_eeprom(struct elink_phy *phy,
8705 struct elink_params *params,
8706 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
8707 uint8_t *o_buf, uint8_t is_init)
8709 struct bxe_softc *sc = params->sc;
8712 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8714 "Reading from eeprom is limited to 0xf\n");
8715 return ELINK_STATUS_ERROR;
8717 /* Set the read command byte count */
8718 elink_cl45_write(sc, phy,
8719 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8720 (byte_cnt | (dev_addr << 8)));
8722 /* Set the read command address */
8723 elink_cl45_write(sc, phy,
8724 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8727 /* Activate read command */
8728 elink_cl45_write(sc, phy,
8729 MDIO_PMA_DEVAD, MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8732 /* Wait up to 500us for command complete status */
8733 for (i = 0; i < 100; i++) {
8734 elink_cl45_read(sc, phy,
8736 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8737 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8738 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8743 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8744 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8746 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8747 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8748 return ELINK_STATUS_ERROR;
8751 /* Read the buffer */
8752 for (i = 0; i < byte_cnt; i++) {
8753 elink_cl45_read(sc, phy,
8755 MDIO_PMA_REG_8726_TWO_WIRE_DATA_BUF + i, &val);
8756 o_buf[i] = (uint8_t)(val & MDIO_PMA_REG_8726_TWO_WIRE_DATA_MASK);
8759 for (i = 0; i < 100; i++) {
8760 elink_cl45_read(sc, phy,
8762 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8763 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8764 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8765 return ELINK_STATUS_OK;
8768 return ELINK_STATUS_ERROR;
8771 static void elink_warpcore_power_module(struct elink_params *params,
8775 struct bxe_softc *sc = params->sc;
8777 pin_cfg = (REG_RD(sc, params->shmem_base +
8778 offsetof(struct shmem_region,
8779 dev_info.port_hw_config[params->port].e3_sfp_ctrl)) &
8780 PORT_HW_CFG_E3_PWR_DIS_MASK) >>
8781 PORT_HW_CFG_E3_PWR_DIS_SHIFT;
8783 if (pin_cfg == PIN_CFG_NA)
8785 ELINK_DEBUG_P2(sc, "Setting SFP+ module power to %d using pin cfg %d\n",
8787 /* Low ==> corresponding SFP+ module is powered
8788 * high ==> the SFP+ module is powered down
8790 elink_set_cfg_pin(sc, pin_cfg, power ^ 1);
8792 static elink_status_t elink_warpcore_read_sfp_module_eeprom(struct elink_phy *phy,
8793 struct elink_params *params,
8795 uint16_t addr, uint8_t byte_cnt,
8796 uint8_t *o_buf, uint8_t is_init)
8798 elink_status_t rc = ELINK_STATUS_OK;
8799 uint8_t i, j = 0, cnt = 0;
8800 uint32_t data_array[4];
8802 struct bxe_softc *sc = params->sc;
8804 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8806 "Reading from eeprom is limited to 16 bytes\n");
8807 return ELINK_STATUS_ERROR;
8810 /* 4 byte aligned address */
8811 addr32 = addr & (~0x3);
8813 if ((!is_init) && (cnt == I2C_WA_PWR_ITER)) {
8814 elink_warpcore_power_module(params, 0);
8815 /* Note that 100us are not enough here */
8817 elink_warpcore_power_module(params, 1);
8820 elink_bsc_module_sel(params);
8821 rc = elink_bsc_read(sc, dev_addr, addr32, 0, byte_cnt,
8823 } while ((rc != ELINK_STATUS_OK) && (++cnt < I2C_WA_RETRY_CNT));
8825 if (rc == ELINK_STATUS_OK) {
8826 for (i = (addr - addr32); i < byte_cnt + (addr - addr32); i++) {
8827 o_buf[j] = *((uint8_t *)data_array + i);
8835 static elink_status_t elink_8727_read_sfp_module_eeprom(struct elink_phy *phy,
8836 struct elink_params *params,
8837 uint8_t dev_addr, uint16_t addr, uint8_t byte_cnt,
8838 uint8_t *o_buf, uint8_t is_init)
8840 struct bxe_softc *sc = params->sc;
8843 if (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) {
8845 "Reading from eeprom is limited to 0xf\n");
8846 return ELINK_STATUS_ERROR;
8849 /* Set 2-wire transfer rate of SFP+ module EEPROM
8850 * to 100Khz since some DACs(direct attached cables) do
8851 * not work at 400Khz.
8853 elink_cl45_write(sc, phy,
8855 MDIO_PMA_REG_8727_TWO_WIRE_SLAVE_ADDR,
8856 ((dev_addr << 8) | 1));
8858 /* Need to read from 1.8000 to clear it */
8859 elink_cl45_read(sc, phy,
8861 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8864 /* Set the read command byte count */
8865 elink_cl45_write(sc, phy,
8867 MDIO_PMA_REG_SFP_TWO_WIRE_BYTE_CNT,
8868 ((byte_cnt < 2) ? 2 : byte_cnt));
8870 /* Set the read command address */
8871 elink_cl45_write(sc, phy,
8873 MDIO_PMA_REG_SFP_TWO_WIRE_MEM_ADDR,
8875 /* Set the destination address */
8876 elink_cl45_write(sc, phy,
8879 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF);
8881 /* Activate read command */
8882 elink_cl45_write(sc, phy,
8884 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL,
8886 /* Wait appropriate time for two-wire command to finish before
8887 * polling the status register
8891 /* Wait up to 500us for command complete status */
8892 for (i = 0; i < 100; i++) {
8893 elink_cl45_read(sc, phy,
8895 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8896 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8897 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE)
8902 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) !=
8903 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_COMPLETE) {
8905 "Got bad status 0x%x when reading from SFP+ EEPROM\n",
8906 (val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK));
8907 return ELINK_STATUS_TIMEOUT;
8910 /* Read the buffer */
8911 for (i = 0; i < byte_cnt; i++) {
8912 elink_cl45_read(sc, phy,
8914 MDIO_PMA_REG_8727_TWO_WIRE_DATA_BUF + i, &val);
8915 o_buf[i] = (uint8_t)(val & MDIO_PMA_REG_8727_TWO_WIRE_DATA_MASK);
8918 for (i = 0; i < 100; i++) {
8919 elink_cl45_read(sc, phy,
8921 MDIO_PMA_REG_SFP_TWO_WIRE_CTRL, &val);
8922 if ((val & MDIO_PMA_REG_SFP_TWO_WIRE_CTRL_STATUS_MASK) ==
8923 MDIO_PMA_REG_SFP_TWO_WIRE_STATUS_IDLE)
8924 return ELINK_STATUS_OK;
8928 return ELINK_STATUS_ERROR;
8930 elink_status_t elink_read_sfp_module_eeprom(struct elink_phy *phy,
8931 struct elink_params *params, uint8_t dev_addr,
8932 uint16_t addr, uint16_t byte_cnt, uint8_t *o_buf)
8934 elink_status_t rc = 0;
8935 struct bxe_softc *sc = params->sc;
8937 uint8_t *user_data = o_buf;
8938 read_sfp_module_eeprom_func_p read_func;
8939 if ((dev_addr != 0xa0) && (dev_addr != 0xa2)) {
8940 ELINK_DEBUG_P1(sc, "invalid dev_addr 0x%x\n", dev_addr);
8941 return ELINK_STATUS_ERROR;
8944 switch (phy->type) {
8945 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
8946 read_func = elink_8726_read_sfp_module_eeprom;
8948 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
8949 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
8950 read_func = elink_8727_read_sfp_module_eeprom;
8952 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
8953 read_func = elink_warpcore_read_sfp_module_eeprom;
8956 return ELINK_OP_NOT_SUPPORTED;
8959 while (!rc && (byte_cnt > 0)) {
8960 xfer_size = (byte_cnt > ELINK_SFP_EEPROM_PAGE_SIZE) ?
8961 ELINK_SFP_EEPROM_PAGE_SIZE : byte_cnt;
8962 rc = read_func(phy, params, dev_addr, addr, xfer_size,
8964 byte_cnt -= xfer_size;
8965 user_data += xfer_size;
8971 static elink_status_t elink_get_edc_mode(struct elink_phy *phy,
8972 struct elink_params *params,
8975 struct bxe_softc *sc = params->sc;
8976 uint32_t sync_offset = 0, phy_idx, media_types;
8977 uint8_t val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1], check_limiting_mode = 0;
8978 *edc_mode = ELINK_EDC_MODE_LIMITING;
8979 phy->media_type = ELINK_ETH_PHY_UNSPECIFIED;
8980 /* First check for copper cable */
8981 if (elink_read_sfp_module_eeprom(phy,
8983 ELINK_I2C_DEV_ADDR_A0,
8985 ELINK_SFP_EEPROM_FC_TX_TECH_ADDR + 1,
8986 (uint8_t *)val) != 0) {
8987 ELINK_DEBUG_P0(sc, "Failed to read from SFP+ module EEPROM\n");
8988 return ELINK_STATUS_ERROR;
8990 params->link_attr_sync &= ~LINK_SFP_EEPROM_COMP_CODE_MASK;
8991 params->link_attr_sync |= val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] <<
8992 LINK_SFP_EEPROM_COMP_CODE_SHIFT;
8993 elink_update_link_attr(params, params->link_attr_sync);
8994 switch (val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]) {
8995 case ELINK_SFP_EEPROM_CON_TYPE_VAL_COPPER:
8997 uint8_t copper_module_type;
8998 phy->media_type = ELINK_ETH_PHY_DA_TWINAX;
8999 /* Check if its active cable (includes SFP+ module)
9002 copper_module_type = val[ELINK_SFP_EEPROM_FC_TX_TECH_ADDR];
9003 if (copper_module_type &
9004 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_ACTIVE) {
9005 ELINK_DEBUG_P0(sc, "Active Copper cable detected\n");
9006 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9007 *edc_mode = ELINK_EDC_MODE_ACTIVE_DAC;
9009 check_limiting_mode = 1;
9011 *edc_mode = ELINK_EDC_MODE_PASSIVE_DAC;
9012 /* Even in case PASSIVE_DAC indication is not set,
9013 * treat it as a passive DAC cable, since some cables
9014 * don't have this indication.
9016 if (copper_module_type &
9017 ELINK_SFP_EEPROM_FC_TX_TECH_BITMASK_COPPER_PASSIVE) {
9019 "Passive Copper cable detected\n");
9022 "Unknown copper-cable-type\n");
9027 case ELINK_SFP_EEPROM_CON_TYPE_VAL_UNKNOWN:
9028 case ELINK_SFP_EEPROM_CON_TYPE_VAL_LC:
9029 case ELINK_SFP_EEPROM_CON_TYPE_VAL_RJ45:
9030 check_limiting_mode = 1;
9031 /* Module is considered as 1G in case it's NOT compliant with
9032 * any 10G ethernet protocol, but is 1G Ethernet compliant.
9034 if (((val[ELINK_SFP_EEPROM_10G_COMP_CODE_ADDR] &
9035 (ELINK_SFP_EEPROM_10G_COMP_CODE_SR_MASK |
9036 ELINK_SFP_EEPROM_10G_COMP_CODE_LR_MASK |
9037 ELINK_SFP_EEPROM_10G_COMP_CODE_LRM_MASK)) == 0) &&
9038 (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] != 0)) {
9039 ELINK_DEBUG_P0(sc, "1G SFP module detected\n");
9040 phy->media_type = ELINK_ETH_PHY_SFP_1G_FIBER;
9041 if (phy->req_line_speed != ELINK_SPEED_1000) {
9042 uint8_t gport = params->port;
9043 phy->req_line_speed = ELINK_SPEED_1000;
9044 if (!CHIP_IS_E1x(sc)) {
9045 gport = SC_PATH(sc) +
9046 (params->port << 1);
9048 elink_cb_event_log(sc, ELINK_LOG_ID_NON_10G_MODULE, gport); //"Warning: Link speed was forced to 1000Mbps."
9049 // " Current SFP module in port %d is not"
9050 // " compliant with 10G Ethernet\n",
9053 if (val[ELINK_SFP_EEPROM_1G_COMP_CODE_ADDR] &
9054 ELINK_SFP_EEPROM_1G_COMP_CODE_BASE_T) {
9055 /* Some 1G-baseT modules will not link up,
9056 * unless TX_EN is toggled with long delay in
9059 elink_sfp_set_transmitter(params, phy, 0);
9061 elink_sfp_set_transmitter(params, phy, 1);
9064 int idx, cfg_idx = 0;
9065 ELINK_DEBUG_P0(sc, "10G Optic module detected\n");
9066 for (idx = ELINK_INT_PHY; idx < ELINK_MAX_PHYS; idx++) {
9067 if (params->phy[idx].type == phy->type) {
9068 cfg_idx = ELINK_LINK_CONFIG_IDX(idx);
9072 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
9073 phy->req_line_speed = params->req_line_speed[cfg_idx];
9077 ELINK_DEBUG_P1(sc, "Unable to determine module type 0x%x !!!\n",
9078 val[ELINK_SFP_EEPROM_CON_TYPE_ADDR]);
9079 return ELINK_STATUS_ERROR;
9081 sync_offset = params->shmem_base +
9082 offsetof(struct shmem_region,
9083 dev_info.port_hw_config[params->port].media_type);
9084 media_types = REG_RD(sc, sync_offset);
9085 /* Update media type for non-PMF sync */
9086 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
9087 if (&(params->phy[phy_idx]) == phy) {
9088 media_types &= ~(PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
9089 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
9090 media_types |= ((phy->media_type &
9091 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
9092 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT * phy_idx));
9096 REG_WR(sc, sync_offset, media_types);
9097 if (check_limiting_mode) {
9098 uint8_t options[ELINK_SFP_EEPROM_OPTIONS_SIZE];
9099 if (elink_read_sfp_module_eeprom(phy,
9101 ELINK_I2C_DEV_ADDR_A0,
9102 ELINK_SFP_EEPROM_OPTIONS_ADDR,
9103 ELINK_SFP_EEPROM_OPTIONS_SIZE,
9106 "Failed to read Option field from module EEPROM\n");
9107 return ELINK_STATUS_ERROR;
9109 if ((options[0] & ELINK_SFP_EEPROM_OPTIONS_LINEAR_RX_OUT_MASK))
9110 *edc_mode = ELINK_EDC_MODE_LINEAR;
9112 *edc_mode = ELINK_EDC_MODE_LIMITING;
9114 ELINK_DEBUG_P1(sc, "EDC mode is set to 0x%x\n", *edc_mode);
9115 return ELINK_STATUS_OK;
9117 /* This function read the relevant field from the module (SFP+), and verify it
9118 * is compliant with this board
9120 static elink_status_t elink_verify_sfp_module(struct elink_phy *phy,
9121 struct elink_params *params)
9123 struct bxe_softc *sc = params->sc;
9125 uint32_t fw_resp, fw_cmd_param;
9126 char vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE+1];
9127 char vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE+1];
9128 phy->flags &= ~ELINK_FLAGS_SFP_NOT_APPROVED;
9129 val = REG_RD(sc, params->shmem_base +
9130 offsetof(struct shmem_region, dev_info.
9131 port_feature_config[params->port].config));
9132 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9133 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_NO_ENFORCEMENT) {
9134 ELINK_DEBUG_P0(sc, "NOT enforcing module verification\n");
9135 return ELINK_STATUS_OK;
9138 if (params->feature_config_flags &
9139 ELINK_FEATURE_CONFIG_BC_SUPPORTS_DUAL_PHY_OPT_MDL_VRFY) {
9140 /* Use specific phy request */
9141 cmd = DRV_MSG_CODE_VRFY_SPECIFIC_PHY_OPT_MDL;
9142 } else if (params->feature_config_flags &
9143 ELINK_FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY) {
9144 /* Use first phy request only in case of non-dual media*/
9145 if (ELINK_DUAL_MEDIA(params)) {
9147 "FW does not support OPT MDL verification\n");
9148 return ELINK_STATUS_ERROR;
9150 cmd = DRV_MSG_CODE_VRFY_FIRST_PHY_OPT_MDL;
9152 /* No support in OPT MDL detection */
9154 "FW does not support OPT MDL verification\n");
9155 return ELINK_STATUS_ERROR;
9158 fw_cmd_param = ELINK_FW_PARAM_SET(phy->addr, phy->type, phy->mdio_ctrl);
9159 fw_resp = elink_cb_fw_command(sc, cmd, fw_cmd_param);
9160 if (fw_resp == FW_MSG_CODE_VRFY_OPT_MDL_SUCCESS) {
9161 ELINK_DEBUG_P0(sc, "Approved module\n");
9162 return ELINK_STATUS_OK;
9165 /* Format the warning message */
9166 if (elink_read_sfp_module_eeprom(phy,
9168 ELINK_I2C_DEV_ADDR_A0,
9169 ELINK_SFP_EEPROM_VENDOR_NAME_ADDR,
9170 ELINK_SFP_EEPROM_VENDOR_NAME_SIZE,
9171 (uint8_t *)vendor_name))
9172 vendor_name[0] = '\0';
9174 vendor_name[ELINK_SFP_EEPROM_VENDOR_NAME_SIZE] = '\0';
9175 if (elink_read_sfp_module_eeprom(phy,
9177 ELINK_I2C_DEV_ADDR_A0,
9178 ELINK_SFP_EEPROM_PART_NO_ADDR,
9179 ELINK_SFP_EEPROM_PART_NO_SIZE,
9180 (uint8_t *)vendor_pn))
9181 vendor_pn[0] = '\0';
9183 vendor_pn[ELINK_SFP_EEPROM_PART_NO_SIZE] = '\0';
9185 elink_cb_event_log(sc, ELINK_LOG_ID_UNQUAL_IO_MODULE, params->port, vendor_name, vendor_pn); // "Warning: Unqualified SFP+ module detected,"
9186 // " Port %d from %s part number %s\n",
9188 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) !=
9189 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_WARNING_MSG)
9190 phy->flags |= ELINK_FLAGS_SFP_NOT_APPROVED;
9191 return ELINK_STATUS_ERROR;
9194 static elink_status_t elink_wait_for_sfp_module_initialized(struct elink_phy *phy,
9195 struct elink_params *params)
9200 struct bxe_softc *sc = params->sc;
9202 /* Initialization time after hot-plug may take up to 300ms for
9203 * some phys type ( e.g. JDSU )
9206 for (timeout = 0; timeout < 60; timeout++) {
9207 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT)
9208 rc = elink_warpcore_read_sfp_module_eeprom(
9209 phy, params, ELINK_I2C_DEV_ADDR_A0, 1, 1, &val,
9212 rc = elink_read_sfp_module_eeprom(phy, params,
9213 ELINK_I2C_DEV_ADDR_A0,
9217 "SFP+ module initialization took %d ms\n",
9219 return ELINK_STATUS_OK;
9223 rc = elink_read_sfp_module_eeprom(phy, params, ELINK_I2C_DEV_ADDR_A0,
9228 static void elink_8727_power_module(struct bxe_softc *sc,
9229 struct elink_phy *phy,
9230 uint8_t is_power_up) {
9231 /* Make sure GPIOs are not using for LED mode */
9233 /* In the GPIO register, bit 4 is use to determine if the GPIOs are
9234 * operating as INPUT or as OUTPUT. Bit 1 is for input, and 0 for
9236 * Bits 0-1 determine the GPIOs value for OUTPUT in case bit 4 val is 0
9237 * Bits 8-9 determine the GPIOs value for INPUT in case bit 4 val is 1
9238 * where the 1st bit is the over-current(only input), and 2nd bit is
9239 * for power( only output )
9241 * In case of NOC feature is disabled and power is up, set GPIO control
9242 * as input to enable listening of over-current indication
9244 if (phy->flags & ELINK_FLAGS_NOC)
9249 /* Set GPIO control to OUTPUT, and set the power bit
9250 * to according to the is_power_up
9254 elink_cl45_write(sc, phy,
9256 MDIO_PMA_REG_8727_GPIO_CTRL,
9260 static elink_status_t elink_8726_set_limiting_mode(struct bxe_softc *sc,
9261 struct elink_phy *phy,
9264 uint16_t cur_limiting_mode;
9266 elink_cl45_read(sc, phy,
9268 MDIO_PMA_REG_ROM_VER2,
9269 &cur_limiting_mode);
9270 ELINK_DEBUG_P1(sc, "Current Limiting mode is 0x%x\n",
9273 if (edc_mode == ELINK_EDC_MODE_LIMITING) {
9274 ELINK_DEBUG_P0(sc, "Setting LIMITING MODE\n");
9275 elink_cl45_write(sc, phy,
9277 MDIO_PMA_REG_ROM_VER2,
9278 ELINK_EDC_MODE_LIMITING);
9279 } else { /* LRM mode ( default )*/
9281 ELINK_DEBUG_P0(sc, "Setting LRM MODE\n");
9283 /* Changing to LRM mode takes quite few seconds. So do it only
9284 * if current mode is limiting (default is LRM)
9286 if (cur_limiting_mode != ELINK_EDC_MODE_LIMITING)
9287 return ELINK_STATUS_OK;
9289 elink_cl45_write(sc, phy,
9291 MDIO_PMA_REG_LRM_MODE,
9293 elink_cl45_write(sc, phy,
9295 MDIO_PMA_REG_ROM_VER2,
9297 elink_cl45_write(sc, phy,
9299 MDIO_PMA_REG_MISC_CTRL0,
9301 elink_cl45_write(sc, phy,
9303 MDIO_PMA_REG_LRM_MODE,
9306 return ELINK_STATUS_OK;
9309 static elink_status_t elink_8727_set_limiting_mode(struct bxe_softc *sc,
9310 struct elink_phy *phy,
9313 uint16_t phy_identifier;
9314 uint16_t rom_ver2_val;
9315 elink_cl45_read(sc, phy,
9317 MDIO_PMA_REG_PHY_IDENTIFIER,
9320 elink_cl45_write(sc, phy,
9322 MDIO_PMA_REG_PHY_IDENTIFIER,
9323 (phy_identifier & ~(1<<9)));
9325 elink_cl45_read(sc, phy,
9327 MDIO_PMA_REG_ROM_VER2,
9329 /* Keep the MSB 8-bits, and set the LSB 8-bits with the edc_mode */
9330 elink_cl45_write(sc, phy,
9332 MDIO_PMA_REG_ROM_VER2,
9333 (rom_ver2_val & 0xff00) | (edc_mode & 0x00ff));
9335 elink_cl45_write(sc, phy,
9337 MDIO_PMA_REG_PHY_IDENTIFIER,
9338 (phy_identifier | (1<<9)));
9340 return ELINK_STATUS_OK;
9343 static void elink_8727_specific_func(struct elink_phy *phy,
9344 struct elink_params *params,
9347 struct bxe_softc *sc = params->sc;
9350 case ELINK_DISABLE_TX:
9351 elink_sfp_set_transmitter(params, phy, 0);
9353 case ELINK_ENABLE_TX:
9354 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED))
9355 elink_sfp_set_transmitter(params, phy, 1);
9357 case ELINK_PHY_INIT:
9358 elink_cl45_write(sc, phy,
9359 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9361 elink_cl45_write(sc, phy,
9362 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9364 elink_cl45_write(sc, phy,
9365 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x0006);
9366 /* Make MOD_ABS give interrupt on change */
9367 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9368 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9371 if (phy->flags & ELINK_FLAGS_NOC)
9373 /* Set 8727 GPIOs to input to allow reading from the 8727 GPIO0
9374 * status which reflect SFP+ module over-current
9376 if (!(phy->flags & ELINK_FLAGS_NOC))
9377 val &= 0xff8f; /* Reset bits 4-6 */
9378 elink_cl45_write(sc, phy,
9379 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_PCS_OPT_CTRL,
9383 ELINK_DEBUG_P1(sc, "Function 0x%x not supported by 8727\n",
9389 static void elink_set_e1e2_module_fault_led(struct elink_params *params,
9392 struct bxe_softc *sc = params->sc;
9394 uint32_t fault_led_gpio = REG_RD(sc, params->shmem_base +
9395 offsetof(struct shmem_region,
9396 dev_info.port_hw_config[params->port].sfp_ctrl)) &
9397 PORT_HW_CFG_FAULT_MODULE_LED_MASK;
9398 switch (fault_led_gpio) {
9399 case PORT_HW_CFG_FAULT_MODULE_LED_DISABLED:
9401 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO0:
9402 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO1:
9403 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO2:
9404 case PORT_HW_CFG_FAULT_MODULE_LED_GPIO3:
9406 uint8_t gpio_port = elink_get_gpio_port(params);
9407 uint16_t gpio_pin = fault_led_gpio -
9408 PORT_HW_CFG_FAULT_MODULE_LED_GPIO0;
9409 ELINK_DEBUG_P3(sc, "Set fault module-detected led "
9410 "pin %x port %x mode %x\n",
9411 gpio_pin, gpio_port, gpio_mode);
9412 elink_cb_gpio_write(sc, gpio_pin, gpio_mode, gpio_port);
9416 ELINK_DEBUG_P1(sc, "Error: Invalid fault led mode 0x%x\n",
9421 static void elink_set_e3_module_fault_led(struct elink_params *params,
9425 uint8_t port = params->port;
9426 struct bxe_softc *sc = params->sc;
9427 pin_cfg = (REG_RD(sc, params->shmem_base +
9428 offsetof(struct shmem_region,
9429 dev_info.port_hw_config[port].e3_sfp_ctrl)) &
9430 PORT_HW_CFG_E3_FAULT_MDL_LED_MASK) >>
9431 PORT_HW_CFG_E3_FAULT_MDL_LED_SHIFT;
9432 ELINK_DEBUG_P2(sc, "Setting Fault LED to %d using pin cfg %d\n",
9433 gpio_mode, pin_cfg);
9434 elink_set_cfg_pin(sc, pin_cfg, gpio_mode);
9437 static void elink_set_sfp_module_fault_led(struct elink_params *params,
9440 struct bxe_softc *sc = params->sc;
9441 ELINK_DEBUG_P1(sc, "Setting SFP+ module fault LED to %d\n", gpio_mode);
9442 if (CHIP_IS_E3(sc)) {
9443 /* Low ==> if SFP+ module is supported otherwise
9444 * High ==> if SFP+ module is not on the approved vendor list
9446 elink_set_e3_module_fault_led(params, gpio_mode);
9448 elink_set_e1e2_module_fault_led(params, gpio_mode);
9451 static void elink_warpcore_hw_reset(struct elink_phy *phy,
9452 struct elink_params *params)
9454 struct bxe_softc *sc = params->sc;
9455 elink_warpcore_power_module(params, 0);
9456 /* Put Warpcore in low power mode */
9457 REG_WR(sc, MISC_REG_WC0_RESET, 0x0c0e);
9459 /* Put LCPLL in low power mode */
9460 REG_WR(sc, MISC_REG_LCPLL_E40_PWRDWN, 1);
9461 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_ANA, 0);
9462 REG_WR(sc, MISC_REG_LCPLL_E40_RESETB_DIG, 0);
9465 static void elink_power_sfp_module(struct elink_params *params,
9466 struct elink_phy *phy,
9469 struct bxe_softc *sc = params->sc;
9470 ELINK_DEBUG_P1(sc, "Setting SFP+ power to %x\n", power);
9472 switch (phy->type) {
9473 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
9474 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
9475 elink_8727_power_module(params->sc, phy, power);
9477 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
9478 elink_warpcore_power_module(params, power);
9484 static void elink_warpcore_set_limiting_mode(struct elink_params *params,
9485 struct elink_phy *phy,
9489 uint16_t mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
9490 struct bxe_softc *sc = params->sc;
9492 uint8_t lane = elink_get_warpcore_lane(phy, params);
9493 /* This is a global register which controls all lanes */
9494 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
9495 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
9496 val &= ~(0xf << (lane << 2));
9499 case ELINK_EDC_MODE_LINEAR:
9500 case ELINK_EDC_MODE_LIMITING:
9501 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_DEFAULT;
9503 case ELINK_EDC_MODE_PASSIVE_DAC:
9504 case ELINK_EDC_MODE_ACTIVE_DAC:
9505 mode = MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE_SFP_DAC;
9511 val |= (mode << (lane << 2));
9512 elink_cl45_write(sc, phy, MDIO_WC_DEVAD,
9513 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, val);
9515 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
9516 MDIO_WC_REG_UC_INFO_B1_FIRMWARE_MODE, &val);
9518 /* Restart microcode to re-read the new mode */
9519 elink_warpcore_reset_lane(sc, phy, 1);
9520 elink_warpcore_reset_lane(sc, phy, 0);
9524 static void elink_set_limiting_mode(struct elink_params *params,
9525 struct elink_phy *phy,
9528 switch (phy->type) {
9529 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
9530 elink_8726_set_limiting_mode(params->sc, phy, edc_mode);
9532 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
9533 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
9534 elink_8727_set_limiting_mode(params->sc, phy, edc_mode);
9536 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT:
9537 elink_warpcore_set_limiting_mode(params, phy, edc_mode);
9542 elink_status_t elink_sfp_module_detection(struct elink_phy *phy,
9543 struct elink_params *params)
9545 struct bxe_softc *sc = params->sc;
9547 elink_status_t rc = ELINK_STATUS_OK;
9549 uint32_t val = REG_RD(sc, params->shmem_base +
9550 offsetof(struct shmem_region, dev_info.
9551 port_feature_config[params->port].config));
9552 /* Enabled transmitter by default */
9553 elink_sfp_set_transmitter(params, phy, 1);
9554 ELINK_DEBUG_P1(sc, "SFP+ module plugged in/out detected on port %d\n",
9556 /* Power up module */
9557 elink_power_sfp_module(params, phy, 1);
9558 if (elink_get_edc_mode(phy, params, &edc_mode) != 0) {
9559 ELINK_DEBUG_P0(sc, "Failed to get valid module type\n");
9560 return ELINK_STATUS_ERROR;
9561 } else if (elink_verify_sfp_module(phy, params) != 0) {
9562 /* Check SFP+ module compatibility */
9563 ELINK_DEBUG_P0(sc, "Module verification failed!!\n");
9564 rc = ELINK_STATUS_ERROR;
9565 /* Turn on fault module-detected led */
9566 elink_set_sfp_module_fault_led(params,
9567 MISC_REGISTERS_GPIO_HIGH);
9569 /* Check if need to power down the SFP+ module */
9570 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9571 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_POWER_DOWN) {
9572 ELINK_DEBUG_P0(sc, "Shutdown SFP+ module!!\n");
9573 elink_power_sfp_module(params, phy, 0);
9577 /* Turn off fault module-detected led */
9578 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_LOW);
9581 /* Check and set limiting mode / LRM mode on 8726. On 8727 it
9582 * is done automatically
9584 elink_set_limiting_mode(params, phy, edc_mode);
9586 /* Disable transmit for this module if the module is not approved, and
9587 * laser needs to be disabled.
9590 ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
9591 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER))
9592 elink_sfp_set_transmitter(params, phy, 0);
9597 void elink_handle_module_detect_int(struct elink_params *params)
9599 struct bxe_softc *sc = params->sc;
9600 struct elink_phy *phy;
9602 uint8_t gpio_num, gpio_port;
9603 if (CHIP_IS_E3(sc)) {
9604 phy = ¶ms->phy[ELINK_INT_PHY];
9605 /* Always enable TX laser,will be disabled in case of fault */
9606 elink_sfp_set_transmitter(params, phy, 1);
9608 phy = ¶ms->phy[ELINK_EXT_PHY1];
9610 if (elink_get_mod_abs_int_cfg(sc, params->chip_id, params->shmem_base,
9611 params->port, &gpio_num, &gpio_port) ==
9612 ELINK_STATUS_ERROR) {
9613 ELINK_DEBUG_P0(sc, "Failed to get MOD_ABS interrupt config\n");
9617 /* Set valid module led off */
9618 elink_set_sfp_module_fault_led(params, MISC_REGISTERS_GPIO_HIGH);
9620 /* Get current gpio val reflecting module plugged in / out*/
9621 gpio_val = elink_cb_gpio_read(sc, gpio_num, gpio_port);
9623 /* Call the handling function in case module is detected */
9624 if (gpio_val == 0) {
9625 elink_set_mdio_emac_per_phy(sc, params);
9626 elink_set_aer_mmd(params, phy);
9628 elink_power_sfp_module(params, phy, 1);
9629 elink_cb_gpio_int_write(sc, gpio_num,
9630 MISC_REGISTERS_GPIO_INT_OUTPUT_CLR,
9632 if (elink_wait_for_sfp_module_initialized(phy, params) == 0) {
9633 elink_sfp_module_detection(phy, params);
9634 if (CHIP_IS_E3(sc)) {
9635 uint16_t rx_tx_in_reset;
9636 /* In case WC is out of reset, reconfigure the
9637 * link speed while taking into account 1G
9638 * module limitation.
9640 elink_cl45_read(sc, phy,
9642 MDIO_WC_REG_DIGITAL5_MISC6,
9644 if ((!rx_tx_in_reset) &&
9645 (params->link_flags &
9646 ELINK_PHY_INITIALIZED)) {
9647 elink_warpcore_reset_lane(sc, phy, 1);
9648 elink_warpcore_config_sfi(phy, params);
9649 elink_warpcore_reset_lane(sc, phy, 0);
9653 ELINK_DEBUG_P0(sc, "SFP+ module is not initialized\n");
9656 elink_cb_gpio_int_write(sc, gpio_num,
9657 MISC_REGISTERS_GPIO_INT_OUTPUT_SET,
9659 /* Module was plugged out.
9660 * Disable transmit for this module
9662 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
9666 /******************************************************************/
9667 /* Used by 8706 and 8727 */
9668 /******************************************************************/
9669 static void elink_sfp_mask_fault(struct bxe_softc *sc,
9670 struct elink_phy *phy,
9671 uint16_t alarm_status_offset,
9672 uint16_t alarm_ctrl_offset)
9674 uint16_t alarm_status, val;
9675 elink_cl45_read(sc, phy,
9676 MDIO_PMA_DEVAD, alarm_status_offset,
9678 elink_cl45_read(sc, phy,
9679 MDIO_PMA_DEVAD, alarm_status_offset,
9681 /* Mask or enable the fault event. */
9682 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, &val);
9683 if (alarm_status & (1<<0))
9687 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, alarm_ctrl_offset, val);
9689 /******************************************************************/
9690 /* common BCM8706/BCM8726 PHY SECTION */
9691 /******************************************************************/
9692 static uint8_t elink_8706_8726_read_status(struct elink_phy *phy,
9693 struct elink_params *params,
9694 struct elink_vars *vars)
9696 uint8_t link_up = 0;
9697 uint16_t val1, val2, rx_sd, pcs_status;
9698 struct bxe_softc *sc = params->sc;
9699 ELINK_DEBUG_P0(sc, "XGXS 8706/8726\n");
9701 elink_cl45_read(sc, phy,
9702 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &val2);
9704 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
9705 MDIO_PMA_LASI_TXCTRL);
9707 /* Clear LASI indication*/
9708 elink_cl45_read(sc, phy,
9709 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
9710 elink_cl45_read(sc, phy,
9711 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
9712 ELINK_DEBUG_P2(sc, "8706/8726 LASI status 0x%x--> 0x%x\n", val1, val2);
9714 elink_cl45_read(sc, phy,
9715 MDIO_PMA_DEVAD, MDIO_PMA_REG_RX_SD, &rx_sd);
9716 elink_cl45_read(sc, phy,
9717 MDIO_PCS_DEVAD, MDIO_PCS_REG_STATUS, &pcs_status);
9718 elink_cl45_read(sc, phy,
9719 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
9720 elink_cl45_read(sc, phy,
9721 MDIO_AN_DEVAD, MDIO_AN_REG_LINK_STATUS, &val2);
9723 ELINK_DEBUG_P3(sc, "8706/8726 rx_sd 0x%x pcs_status 0x%x 1Gbps"
9724 " link_status 0x%x\n", rx_sd, pcs_status, val2);
9725 /* Link is up if both bit 0 of pmd_rx_sd and bit 0 of pcs_status
9726 * are set, or if the autoneg bit 1 is set
9728 link_up = ((rx_sd & pcs_status & 0x1) || (val2 & (1<<1)));
9731 vars->line_speed = ELINK_SPEED_1000;
9733 vars->line_speed = ELINK_SPEED_10000;
9734 elink_ext_phy_resolve_fc(phy, params, vars);
9735 vars->duplex = DUPLEX_FULL;
9738 /* Capture 10G link fault. Read twice to clear stale value. */
9739 if (vars->line_speed == ELINK_SPEED_10000) {
9740 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9741 MDIO_PMA_LASI_TXSTAT, &val1);
9742 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
9743 MDIO_PMA_LASI_TXSTAT, &val1);
9745 vars->fault_detected = 1;
9751 /******************************************************************/
9752 /* BCM8706 PHY SECTION */
9753 /******************************************************************/
9754 static uint8_t elink_8706_config_init(struct elink_phy *phy,
9755 struct elink_params *params,
9756 struct elink_vars *vars)
9758 uint32_t tx_en_mode;
9759 uint16_t cnt, val, tmp1;
9760 struct bxe_softc *sc = params->sc;
9762 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
9763 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
9765 elink_ext_phy_hw_reset(sc, params->port);
9766 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0xa040);
9767 elink_wait_reset_complete(sc, phy, params);
9769 /* Wait until fw is loaded */
9770 for (cnt = 0; cnt < 100; cnt++) {
9771 elink_cl45_read(sc, phy,
9772 MDIO_PMA_DEVAD, MDIO_PMA_REG_ROM_VER1, &val);
9777 ELINK_DEBUG_P1(sc, "XGXS 8706 is initialized after %d ms\n", cnt);
9778 if ((params->feature_config_flags &
9779 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
9782 for (i = 0; i < 4; i++) {
9783 reg = MDIO_XS_8706_REG_BANK_RX0 +
9784 i*(MDIO_XS_8706_REG_BANK_RX1 -
9785 MDIO_XS_8706_REG_BANK_RX0);
9786 elink_cl45_read(sc, phy, MDIO_XS_DEVAD, reg, &val);
9787 /* Clear first 3 bits of the control */
9789 /* Set control bits according to configuration */
9790 val |= (phy->rx_preemphasis[i] & 0x7);
9791 ELINK_DEBUG_P2(sc, "Setting RX Equalizer to BCM8706"
9792 " reg 0x%x <-- val 0x%x\n", reg, val);
9793 elink_cl45_write(sc, phy, MDIO_XS_DEVAD, reg, val);
9797 if (phy->req_line_speed == ELINK_SPEED_10000) {
9798 ELINK_DEBUG_P0(sc, "XGXS 8706 force 10Gbps\n");
9800 elink_cl45_write(sc, phy,
9802 MDIO_PMA_REG_DIGITAL_CTRL, 0x400);
9803 elink_cl45_write(sc, phy,
9804 MDIO_PMA_DEVAD, MDIO_PMA_LASI_TXCTRL,
9806 /* Arm LASI for link and Tx fault. */
9807 elink_cl45_write(sc, phy,
9808 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 3);
9810 /* Force 1Gbps using autoneg with 1G advertisement */
9812 /* Allow CL37 through CL73 */
9813 ELINK_DEBUG_P0(sc, "XGXS 8706 AutoNeg\n");
9814 elink_cl45_write(sc, phy,
9815 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9817 /* Enable Full-Duplex advertisement on CL37 */
9818 elink_cl45_write(sc, phy,
9819 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LP, 0x0020);
9820 /* Enable CL37 AN */
9821 elink_cl45_write(sc, phy,
9822 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9824 elink_cl45_write(sc, phy,
9825 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, (1<<5));
9827 /* Enable clause 73 AN */
9828 elink_cl45_write(sc, phy,
9829 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9830 elink_cl45_write(sc, phy,
9831 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9833 elink_cl45_write(sc, phy,
9834 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
9837 elink_save_bcm_spirom_ver(sc, phy, params->port);
9839 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
9840 * power mode, if TX Laser is disabled
9843 tx_en_mode = REG_RD(sc, params->shmem_base +
9844 offsetof(struct shmem_region,
9845 dev_info.port_hw_config[params->port].sfp_ctrl))
9846 & PORT_HW_CFG_TX_LASER_MASK;
9848 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
9849 ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS\n");
9850 elink_cl45_read(sc, phy,
9851 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, &tmp1);
9853 elink_cl45_write(sc, phy,
9854 MDIO_PMA_DEVAD, MDIO_PMA_REG_DIGITAL_CTRL, tmp1);
9857 return ELINK_STATUS_OK;
9860 static elink_status_t elink_8706_read_status(struct elink_phy *phy,
9861 struct elink_params *params,
9862 struct elink_vars *vars)
9864 return elink_8706_8726_read_status(phy, params, vars);
9867 /******************************************************************/
9868 /* BCM8726 PHY SECTION */
9869 /******************************************************************/
9870 static void elink_8726_config_loopback(struct elink_phy *phy,
9871 struct elink_params *params)
9873 struct bxe_softc *sc = params->sc;
9874 ELINK_DEBUG_P0(sc, "PMA/PMD ext_phy_loopback: 8726\n");
9875 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0001);
9878 static void elink_8726_external_rom_boot(struct elink_phy *phy,
9879 struct elink_params *params)
9881 struct bxe_softc *sc = params->sc;
9882 /* Need to wait 100ms after reset */
9885 /* Micro controller re-boot */
9886 elink_cl45_write(sc, phy,
9887 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x018B);
9889 /* Set soft reset */
9890 elink_cl45_write(sc, phy,
9892 MDIO_PMA_REG_GEN_CTRL,
9893 MDIO_PMA_REG_GEN_CTRL_ROM_MICRO_RESET);
9895 elink_cl45_write(sc, phy,
9897 MDIO_PMA_REG_MISC_CTRL1, 0x0001);
9899 elink_cl45_write(sc, phy,
9901 MDIO_PMA_REG_GEN_CTRL,
9902 MDIO_PMA_REG_GEN_CTRL_ROM_RESET_INTERNAL_MP);
9904 /* Wait for 150ms for microcode load */
9907 /* Disable serial boot control, tristates pins SS_N, SCK, MOSI, MISO */
9908 elink_cl45_write(sc, phy,
9910 MDIO_PMA_REG_MISC_CTRL1, 0x0000);
9913 elink_save_bcm_spirom_ver(sc, phy, params->port);
9916 static uint8_t elink_8726_read_status(struct elink_phy *phy,
9917 struct elink_params *params,
9918 struct elink_vars *vars)
9920 struct bxe_softc *sc = params->sc;
9922 uint8_t link_up = elink_8706_8726_read_status(phy, params, vars);
9924 elink_cl45_read(sc, phy,
9925 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
9927 if (val1 & (1<<15)) {
9928 ELINK_DEBUG_P0(sc, "Tx is disabled\n");
9930 vars->line_speed = 0;
9937 static elink_status_t elink_8726_config_init(struct elink_phy *phy,
9938 struct elink_params *params,
9939 struct elink_vars *vars)
9941 struct bxe_softc *sc = params->sc;
9942 ELINK_DEBUG_P0(sc, "Initializing BCM8726\n");
9944 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
9945 elink_wait_reset_complete(sc, phy, params);
9947 elink_8726_external_rom_boot(phy, params);
9949 /* Need to call module detected on initialization since the module
9950 * detection triggered by actual module insertion might occur before
9951 * driver is loaded, and when driver is loaded, it reset all
9952 * registers, including the transmitter
9954 elink_sfp_module_detection(phy, params);
9956 if (phy->req_line_speed == ELINK_SPEED_1000) {
9957 ELINK_DEBUG_P0(sc, "Setting 1G force\n");
9958 elink_cl45_write(sc, phy,
9959 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
9960 elink_cl45_write(sc, phy,
9961 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
9962 elink_cl45_write(sc, phy,
9963 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x5);
9964 elink_cl45_write(sc, phy,
9965 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9967 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
9968 (phy->speed_cap_mask &
9969 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G) &&
9970 ((phy->speed_cap_mask &
9971 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
9972 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
9973 ELINK_DEBUG_P0(sc, "Setting 1G clause37\n");
9974 /* Set Flow control */
9975 elink_ext_phy_set_pause(params, phy, vars);
9976 elink_cl45_write(sc, phy,
9977 MDIO_AN_DEVAD, MDIO_AN_REG_ADV, 0x20);
9978 elink_cl45_write(sc, phy,
9979 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_CL73, 0x040c);
9980 elink_cl45_write(sc, phy,
9981 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_FC_LD, 0x0020);
9982 elink_cl45_write(sc, phy,
9983 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1000);
9984 elink_cl45_write(sc, phy,
9985 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x1200);
9986 /* Enable RX-ALARM control to receive interrupt for 1G speed
9989 elink_cl45_write(sc, phy,
9990 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x4);
9991 elink_cl45_write(sc, phy,
9992 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
9995 } else { /* Default 10G. Set only LASI control */
9996 elink_cl45_write(sc, phy,
9997 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 1);
10000 /* Set TX PreEmphasis if needed */
10001 if ((params->feature_config_flags &
10002 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
10004 "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
10005 phy->tx_preemphasis[0],
10006 phy->tx_preemphasis[1]);
10007 elink_cl45_write(sc, phy,
10009 MDIO_PMA_REG_8726_TX_CTRL1,
10010 phy->tx_preemphasis[0]);
10012 elink_cl45_write(sc, phy,
10014 MDIO_PMA_REG_8726_TX_CTRL2,
10015 phy->tx_preemphasis[1]);
10018 return ELINK_STATUS_OK;
10022 static void elink_8726_link_reset(struct elink_phy *phy,
10023 struct elink_params *params)
10025 struct bxe_softc *sc = params->sc;
10026 ELINK_DEBUG_P1(sc, "elink_8726_link_reset port %d\n", params->port);
10027 /* Set serial boot control for external load */
10028 elink_cl45_write(sc, phy,
10030 MDIO_PMA_REG_GEN_CTRL, 0x0001);
10033 /******************************************************************/
10034 /* BCM8727 PHY SECTION */
10035 /******************************************************************/
10037 static void elink_8727_set_link_led(struct elink_phy *phy,
10038 struct elink_params *params, uint8_t mode)
10040 struct bxe_softc *sc = params->sc;
10041 uint16_t led_mode_bitmask = 0;
10042 uint16_t gpio_pins_bitmask = 0;
10044 /* Only NOC flavor requires to set the LED specifically */
10045 if (!(phy->flags & ELINK_FLAGS_NOC))
10048 case ELINK_LED_MODE_FRONT_PANEL_OFF:
10049 case ELINK_LED_MODE_OFF:
10050 led_mode_bitmask = 0;
10051 gpio_pins_bitmask = 0x03;
10053 case ELINK_LED_MODE_ON:
10054 led_mode_bitmask = 0;
10055 gpio_pins_bitmask = 0x02;
10057 case ELINK_LED_MODE_OPER:
10058 led_mode_bitmask = 0x60;
10059 gpio_pins_bitmask = 0x11;
10062 elink_cl45_read(sc, phy,
10064 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
10067 val |= led_mode_bitmask;
10068 elink_cl45_write(sc, phy,
10070 MDIO_PMA_REG_8727_PCS_OPT_CTRL,
10072 elink_cl45_read(sc, phy,
10074 MDIO_PMA_REG_8727_GPIO_CTRL,
10077 val |= gpio_pins_bitmask;
10078 elink_cl45_write(sc, phy,
10080 MDIO_PMA_REG_8727_GPIO_CTRL,
10083 static void elink_8727_hw_reset(struct elink_phy *phy,
10084 struct elink_params *params) {
10085 uint32_t swap_val, swap_override;
10087 /* The PHY reset is controlled by GPIO 1. Fake the port number
10088 * to cancel the swap done in set_gpio()
10090 struct bxe_softc *sc = params->sc;
10091 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
10092 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
10093 port = (swap_val && swap_override) ^ 1;
10094 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_1,
10095 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
10098 static void elink_8727_config_speed(struct elink_phy *phy,
10099 struct elink_params *params)
10101 struct bxe_softc *sc = params->sc;
10102 uint16_t tmp1, val;
10103 /* Set option 1G speed */
10104 if ((phy->req_line_speed == ELINK_SPEED_1000) ||
10105 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER)) {
10106 ELINK_DEBUG_P0(sc, "Setting 1G force\n");
10107 elink_cl45_write(sc, phy,
10108 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x40);
10109 elink_cl45_write(sc, phy,
10110 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, 0xD);
10111 elink_cl45_read(sc, phy,
10112 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2, &tmp1);
10113 ELINK_DEBUG_P1(sc, "1.7 = 0x%x\n", tmp1);
10114 /* Power down the XAUI until link is up in case of dual-media
10117 if (ELINK_DUAL_MEDIA(params)) {
10118 elink_cl45_read(sc, phy,
10120 MDIO_PMA_REG_8727_PCS_GP, &val);
10122 elink_cl45_write(sc, phy,
10124 MDIO_PMA_REG_8727_PCS_GP, val);
10126 } else if ((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10127 ((phy->speed_cap_mask &
10128 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) &&
10129 ((phy->speed_cap_mask &
10130 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G) !=
10131 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) {
10133 ELINK_DEBUG_P0(sc, "Setting 1G clause37\n");
10134 elink_cl45_write(sc, phy,
10135 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL, 0);
10136 elink_cl45_write(sc, phy,
10137 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x1300);
10139 /* Since the 8727 has only single reset pin, need to set the 10G
10140 * registers although it is default
10142 elink_cl45_write(sc, phy,
10143 MDIO_AN_DEVAD, MDIO_AN_REG_8727_MISC_CTRL,
10145 elink_cl45_write(sc, phy,
10146 MDIO_AN_DEVAD, MDIO_AN_REG_CL37_AN, 0x0100);
10147 elink_cl45_write(sc, phy,
10148 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x2040);
10149 elink_cl45_write(sc, phy,
10150 MDIO_PMA_DEVAD, MDIO_PMA_REG_10G_CTRL2,
10155 static elink_status_t elink_8727_config_init(struct elink_phy *phy,
10156 struct elink_params *params,
10157 struct elink_vars *vars)
10159 uint32_t tx_en_mode;
10160 uint16_t tmp1, mod_abs, tmp2;
10161 struct bxe_softc *sc = params->sc;
10162 /* Enable PMD link, MOD_ABS_FLT, and 1G link alarm */
10164 elink_wait_reset_complete(sc, phy, params);
10166 ELINK_DEBUG_P0(sc, "Initializing BCM8727\n");
10168 elink_8727_specific_func(phy, params, ELINK_PHY_INIT);
10169 /* Initially configure MOD_ABS to interrupt when module is
10172 elink_cl45_read(sc, phy,
10173 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
10174 /* Set EDC off by setting OPTXLOS signal input to low (bit 9).
10175 * When the EDC is off it locks onto a reference clock and avoids
10178 mod_abs &= ~(1<<8);
10179 if (!(phy->flags & ELINK_FLAGS_NOC))
10180 mod_abs &= ~(1<<9);
10181 elink_cl45_write(sc, phy,
10182 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10184 /* Enable/Disable PHY transmitter output */
10185 elink_set_disable_pmd_transmit(params, phy, 0);
10187 elink_8727_power_module(sc, phy, 1);
10189 elink_cl45_read(sc, phy,
10190 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &tmp1);
10192 elink_cl45_read(sc, phy,
10193 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT, &tmp1);
10195 elink_8727_config_speed(phy, params);
10198 /* Set TX PreEmphasis if needed */
10199 if ((params->feature_config_flags &
10200 ELINK_FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED)) {
10201 ELINK_DEBUG_P2(sc, "Setting TX_CTRL1 0x%x, TX_CTRL2 0x%x\n",
10202 phy->tx_preemphasis[0],
10203 phy->tx_preemphasis[1]);
10204 elink_cl45_write(sc, phy,
10205 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL1,
10206 phy->tx_preemphasis[0]);
10208 elink_cl45_write(sc, phy,
10209 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_TX_CTRL2,
10210 phy->tx_preemphasis[1]);
10213 /* If TX Laser is controlled by GPIO_0, do not let PHY go into low
10214 * power mode, if TX Laser is disabled
10216 tx_en_mode = REG_RD(sc, params->shmem_base +
10217 offsetof(struct shmem_region,
10218 dev_info.port_hw_config[params->port].sfp_ctrl))
10219 & PORT_HW_CFG_TX_LASER_MASK;
10221 if (tx_en_mode == PORT_HW_CFG_TX_LASER_GPIO0) {
10223 ELINK_DEBUG_P0(sc, "Enabling TXONOFF_PWRDN_DIS\n");
10224 elink_cl45_read(sc, phy,
10225 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, &tmp2);
10228 elink_cl45_write(sc, phy,
10229 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_OPT_CFG_REG, tmp2);
10230 elink_cl45_read(sc, phy,
10231 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
10233 elink_cl45_write(sc, phy,
10234 MDIO_PMA_DEVAD, MDIO_PMA_REG_PHY_IDENTIFIER,
10238 return ELINK_STATUS_OK;
10241 static void elink_8727_handle_mod_abs(struct elink_phy *phy,
10242 struct elink_params *params)
10244 struct bxe_softc *sc = params->sc;
10245 uint16_t mod_abs, rx_alarm_status;
10246 uint32_t val = REG_RD(sc, params->shmem_base +
10247 offsetof(struct shmem_region, dev_info.
10248 port_feature_config[params->port].
10250 elink_cl45_read(sc, phy,
10252 MDIO_PMA_REG_PHY_IDENTIFIER, &mod_abs);
10253 if (mod_abs & (1<<8)) {
10255 /* Module is absent */
10257 "MOD_ABS indication show module is absent\n");
10258 phy->media_type = ELINK_ETH_PHY_NOT_PRESENT;
10259 /* 1. Set mod_abs to detect next module
10261 * 2. Set EDC off by setting OPTXLOS signal input to low
10263 * When the EDC is off it locks onto a reference clock and
10264 * avoids becoming 'lost'.
10266 mod_abs &= ~(1<<8);
10267 if (!(phy->flags & ELINK_FLAGS_NOC))
10268 mod_abs &= ~(1<<9);
10269 elink_cl45_write(sc, phy,
10271 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10273 /* Clear RX alarm since it stays up as long as
10274 * the mod_abs wasn't changed
10276 elink_cl45_read(sc, phy,
10278 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10281 /* Module is present */
10283 "MOD_ABS indication show module is present\n");
10284 /* First disable transmitter, and if the module is ok, the
10285 * module_detection will enable it
10286 * 1. Set mod_abs to detect next module absent event ( bit 8)
10287 * 2. Restore the default polarity of the OPRXLOS signal and
10288 * this signal will then correctly indicate the presence or
10289 * absence of the Rx signal. (bit 9)
10292 if (!(phy->flags & ELINK_FLAGS_NOC))
10294 elink_cl45_write(sc, phy,
10296 MDIO_PMA_REG_PHY_IDENTIFIER, mod_abs);
10298 /* Clear RX alarm since it stays up as long as the mod_abs
10299 * wasn't changed. This is need to be done before calling the
10300 * module detection, otherwise it will clear* the link update
10303 elink_cl45_read(sc, phy,
10305 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10308 if ((val & PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_MASK) ==
10309 PORT_FEAT_CFG_OPT_MDL_ENFRCMNT_DISABLE_TX_LASER)
10310 elink_sfp_set_transmitter(params, phy, 0);
10312 if (elink_wait_for_sfp_module_initialized(phy, params) == 0)
10313 elink_sfp_module_detection(phy, params);
10315 ELINK_DEBUG_P0(sc, "SFP+ module is not initialized\n");
10317 /* Reconfigure link speed based on module type limitations */
10318 elink_8727_config_speed(phy, params);
10321 ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x\n",
10323 /* No need to check link status in case of module plugged in/out */
10326 static uint8_t elink_8727_read_status(struct elink_phy *phy,
10327 struct elink_params *params,
10328 struct elink_vars *vars)
10331 struct bxe_softc *sc = params->sc;
10332 uint8_t link_up = 0;
10333 uint16_t link_status = 0;
10334 uint16_t rx_alarm_status, lasi_ctrl, val1;
10336 /* If PHY is not initialized, do not check link status */
10337 elink_cl45_read(sc, phy,
10338 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL,
10343 /* Check the LASI on Rx */
10344 elink_cl45_read(sc, phy,
10345 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXSTAT,
10347 vars->line_speed = 0;
10348 ELINK_DEBUG_P1(sc, "8727 RX_ALARM_STATUS 0x%x\n", rx_alarm_status);
10350 elink_sfp_mask_fault(sc, phy, MDIO_PMA_LASI_TXSTAT,
10351 MDIO_PMA_LASI_TXCTRL);
10353 elink_cl45_read(sc, phy,
10354 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
10356 ELINK_DEBUG_P1(sc, "8727 LASI status 0x%x\n", val1);
10358 /* Clear MSG-OUT */
10359 elink_cl45_read(sc, phy,
10360 MDIO_PMA_DEVAD, MDIO_PMA_REG_M8051_MSGOUT_REG, &val1);
10362 /* If a module is present and there is need to check
10365 if (!(phy->flags & ELINK_FLAGS_NOC) && !(rx_alarm_status & (1<<5))) {
10366 /* Check over-current using 8727 GPIO0 input*/
10367 elink_cl45_read(sc, phy,
10368 MDIO_PMA_DEVAD, MDIO_PMA_REG_8727_GPIO_CTRL,
10371 if ((val1 & (1<<8)) == 0) {
10372 uint8_t oc_port = params->port;
10373 if (!CHIP_IS_E1x(sc))
10374 oc_port = SC_PATH(sc) + (params->port << 1);
10376 "8727 Power fault has been detected on port %d\n",
10378 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, oc_port); //"Error: Power fault on Port %d has "
10379 // "been detected and the power to "
10380 // "that SFP+ module has been removed "
10381 // "to prevent failure of the card. "
10382 // "Please remove the SFP+ module and "
10383 // "restart the system to clear this "
10385 /* Disable all RX_ALARMs except for mod_abs */
10386 elink_cl45_write(sc, phy,
10388 MDIO_PMA_LASI_RXCTRL, (1<<5));
10390 elink_cl45_read(sc, phy,
10392 MDIO_PMA_REG_PHY_IDENTIFIER, &val1);
10393 /* Wait for module_absent_event */
10395 elink_cl45_write(sc, phy,
10397 MDIO_PMA_REG_PHY_IDENTIFIER, val1);
10398 /* Clear RX alarm */
10399 elink_cl45_read(sc, phy,
10401 MDIO_PMA_LASI_RXSTAT, &rx_alarm_status);
10402 elink_8727_power_module(params->sc, phy, 0);
10405 } /* Over current check */
10407 /* When module absent bit is set, check module */
10408 if (rx_alarm_status & (1<<5)) {
10409 elink_8727_handle_mod_abs(phy, params);
10410 /* Enable all mod_abs and link detection bits */
10411 elink_cl45_write(sc, phy,
10412 MDIO_PMA_DEVAD, MDIO_PMA_LASI_RXCTRL,
10413 ((1<<5) | (1<<2)));
10416 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
10417 ELINK_DEBUG_P0(sc, "Enabling 8727 TX laser\n");
10418 elink_sfp_set_transmitter(params, phy, 1);
10420 ELINK_DEBUG_P0(sc, "Tx is disabled\n");
10424 elink_cl45_read(sc, phy,
10426 MDIO_PMA_REG_8073_SPEED_LINK_STATUS, &link_status);
10428 /* Bits 0..2 --> speed detected,
10429 * Bits 13..15--> link is down
10431 if ((link_status & (1<<2)) && (!(link_status & (1<<15)))) {
10433 vars->line_speed = ELINK_SPEED_10000;
10434 ELINK_DEBUG_P1(sc, "port %x: External link up in 10G\n",
10436 } else if ((link_status & (1<<0)) && (!(link_status & (1<<13)))) {
10438 vars->line_speed = ELINK_SPEED_1000;
10439 ELINK_DEBUG_P1(sc, "port %x: External link up in 1G\n",
10443 ELINK_DEBUG_P1(sc, "port %x: External link is down\n",
10447 /* Capture 10G link fault. */
10448 if (vars->line_speed == ELINK_SPEED_10000) {
10449 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
10450 MDIO_PMA_LASI_TXSTAT, &val1);
10452 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD,
10453 MDIO_PMA_LASI_TXSTAT, &val1);
10455 if (val1 & (1<<0)) {
10456 vars->fault_detected = 1;
10461 elink_ext_phy_resolve_fc(phy, params, vars);
10462 vars->duplex = DUPLEX_FULL;
10463 ELINK_DEBUG_P1(sc, "duplex = 0x%x\n", vars->duplex);
10466 if ((ELINK_DUAL_MEDIA(params)) &&
10467 (phy->req_line_speed == ELINK_SPEED_1000)) {
10468 elink_cl45_read(sc, phy,
10470 MDIO_PMA_REG_8727_PCS_GP, &val1);
10471 /* In case of dual-media board and 1G, power up the XAUI side,
10472 * otherwise power it down. For 10G it is done automatically
10478 elink_cl45_write(sc, phy,
10480 MDIO_PMA_REG_8727_PCS_GP, val1);
10485 static void elink_8727_link_reset(struct elink_phy *phy,
10486 struct elink_params *params)
10488 struct bxe_softc *sc = params->sc;
10490 /* Enable/Disable PHY transmitter output */
10491 elink_set_disable_pmd_transmit(params, phy, 1);
10493 /* Disable Transmitter */
10494 elink_sfp_set_transmitter(params, phy, 0);
10496 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0);
10500 /******************************************************************/
10501 /* BCM8481/BCM84823/BCM84833 PHY SECTION */
10502 /******************************************************************/
10503 static int elink_is_8483x_8485x(struct elink_phy *phy)
10505 return ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833) ||
10506 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) ||
10507 (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858));
10510 static void elink_save_848xx_spirom_version(struct elink_phy *phy,
10511 struct bxe_softc *sc,
10514 uint16_t val, fw_ver2, cnt, i;
10515 static struct elink_reg_set reg_set[] = {
10516 {MDIO_PMA_DEVAD, 0xA819, 0x0014},
10517 {MDIO_PMA_DEVAD, 0xA81A, 0xc200},
10518 {MDIO_PMA_DEVAD, 0xA81B, 0x0000},
10519 {MDIO_PMA_DEVAD, 0xA81C, 0x0300},
10520 {MDIO_PMA_DEVAD, 0xA817, 0x0009}
10524 if (elink_is_8483x_8485x(phy)) {
10525 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD, 0x400f, &fw_ver1);
10526 elink_save_spirom_version(sc, port, fw_ver1 & 0xfff,
10529 /* For 32-bit registers in 848xx, access via MDIO2ARM i/f. */
10530 /* (1) set reg 0xc200_0014(SPI_BRIDGE_CTRL_2) to 0x03000000 */
10531 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
10532 elink_cl45_write(sc, phy, reg_set[i].devad,
10533 reg_set[i].reg, reg_set[i].val);
10535 for (cnt = 0; cnt < 100; cnt++) {
10536 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
10542 ELINK_DEBUG_P0(sc, "Unable to read 848xx "
10543 "phy fw version(1)\n");
10544 elink_save_spirom_version(sc, port, 0,
10550 /* 2) read register 0xc200_0000 (SPI_FW_STATUS) */
10551 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA819, 0x0000);
10552 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA81A, 0xc200);
10553 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, 0xA817, 0x000A);
10554 for (cnt = 0; cnt < 100; cnt++) {
10555 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA818, &val);
10561 ELINK_DEBUG_P0(sc, "Unable to read 848xx phy fw "
10563 elink_save_spirom_version(sc, port, 0,
10568 /* lower 16 bits of the register SPI_FW_STATUS */
10569 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81B, &fw_ver1);
10570 /* upper 16 bits of register SPI_FW_STATUS */
10571 elink_cl45_read(sc, phy, MDIO_PMA_DEVAD, 0xA81C, &fw_ver2);
10573 elink_save_spirom_version(sc, port, (fw_ver2<<16) | fw_ver1,
10578 static void elink_848xx_set_led(struct bxe_softc *sc,
10579 struct elink_phy *phy)
10581 uint16_t val, offset, i;
10582 static struct elink_reg_set reg_set[] = {
10583 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED1_MASK, 0x0080},
10584 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED2_MASK, 0x0018},
10585 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_MASK, 0x0006},
10586 {MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_LED3_BLINK, 0x0000},
10587 {MDIO_PMA_DEVAD, MDIO_PMA_REG_84823_CTL_SLOW_CLK_CNT_HIGH,
10588 MDIO_PMA_REG_84823_BLINK_RATE_VAL_15P9HZ},
10589 {MDIO_AN_DEVAD, 0xFFFB, 0xFFFD}
10591 /* PHYC_CTL_LED_CTL */
10592 elink_cl45_read(sc, phy,
10594 MDIO_PMA_REG_8481_LINK_SIGNAL, &val);
10598 elink_cl45_write(sc, phy,
10600 MDIO_PMA_REG_8481_LINK_SIGNAL, val);
10602 for (i = 0; i < ARRAY_SIZE(reg_set); i++)
10603 elink_cl45_write(sc, phy, reg_set[i].devad, reg_set[i].reg,
10606 if (elink_is_8483x_8485x(phy))
10607 offset = MDIO_PMA_REG_84833_CTL_LED_CTL_1;
10609 offset = MDIO_PMA_REG_84823_CTL_LED_CTL_1;
10611 /* stretch_en for LED3*/
10612 elink_cl45_read_or_write(sc, phy,
10613 MDIO_PMA_DEVAD, offset,
10614 MDIO_PMA_REG_84823_LED3_STRETCH_EN);
10617 static void elink_848xx_specific_func(struct elink_phy *phy,
10618 struct elink_params *params,
10621 struct bxe_softc *sc = params->sc;
10623 case ELINK_PHY_INIT:
10624 if (!elink_is_8483x_8485x(phy)) {
10625 /* Save spirom version */
10626 elink_save_848xx_spirom_version(phy, sc, params->port);
10628 /* This phy uses the NIG latch mechanism since link indication
10629 * arrives through its LED4 and not via its LASI signal, so we
10630 * get steady signal instead of clear on read
10632 elink_bits_en(sc, NIG_REG_LATCH_BC_0 + params->port*4,
10633 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
10635 elink_848xx_set_led(sc, phy);
10640 static elink_status_t elink_848xx_cmn_config_init(struct elink_phy *phy,
10641 struct elink_params *params,
10642 struct elink_vars *vars)
10644 struct bxe_softc *sc = params->sc;
10645 uint16_t autoneg_val, an_1000_val, an_10_100_val;
10647 elink_848xx_specific_func(phy, params, ELINK_PHY_INIT);
10648 elink_cl45_write(sc, phy,
10649 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 0x0000);
10651 /* set 1000 speed advertisement */
10652 elink_cl45_read(sc, phy,
10653 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
10656 elink_ext_phy_set_pause(params, phy, vars);
10657 elink_cl45_read(sc, phy,
10659 MDIO_AN_REG_8481_LEGACY_AN_ADV,
10661 elink_cl45_read(sc, phy,
10662 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_MII_CTRL,
10664 /* Disable forced speed */
10665 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
10666 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8));
10668 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10669 (phy->speed_cap_mask &
10670 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
10671 (phy->req_line_speed == ELINK_SPEED_1000)) {
10672 an_1000_val |= (1<<8);
10673 autoneg_val |= (1<<9 | 1<<12);
10674 if (phy->req_duplex == DUPLEX_FULL)
10675 an_1000_val |= (1<<9);
10676 ELINK_DEBUG_P0(sc, "Advertising 1G\n");
10678 an_1000_val &= ~((1<<8) | (1<<9));
10680 elink_cl45_write(sc, phy,
10681 MDIO_AN_DEVAD, MDIO_AN_REG_8481_1000T_CTRL,
10684 /* Set 10/100 speed advertisement */
10685 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
10686 if (phy->speed_cap_mask &
10687 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
10688 /* Enable autoneg and restart autoneg for legacy speeds
10690 autoneg_val |= (1<<9 | 1<<12);
10691 an_10_100_val |= (1<<8);
10692 ELINK_DEBUG_P0(sc, "Advertising 100M-FD\n");
10695 if (phy->speed_cap_mask &
10696 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
10697 /* Enable autoneg and restart autoneg for legacy speeds
10699 autoneg_val |= (1<<9 | 1<<12);
10700 an_10_100_val |= (1<<7);
10701 ELINK_DEBUG_P0(sc, "Advertising 100M-HD\n");
10704 if ((phy->speed_cap_mask &
10705 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) &&
10706 (phy->supported & ELINK_SUPPORTED_10baseT_Full)) {
10707 an_10_100_val |= (1<<6);
10708 autoneg_val |= (1<<9 | 1<<12);
10709 ELINK_DEBUG_P0(sc, "Advertising 10M-FD\n");
10712 if ((phy->speed_cap_mask &
10713 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) &&
10714 (phy->supported & ELINK_SUPPORTED_10baseT_Half)) {
10715 an_10_100_val |= (1<<5);
10716 autoneg_val |= (1<<9 | 1<<12);
10717 ELINK_DEBUG_P0(sc, "Advertising 10M-HD\n");
10721 /* Only 10/100 are allowed to work in FORCE mode */
10722 if ((phy->req_line_speed == ELINK_SPEED_100) &&
10724 (ELINK_SUPPORTED_100baseT_Half |
10725 ELINK_SUPPORTED_100baseT_Full))) {
10726 autoneg_val |= (1<<13);
10727 /* Enabled AUTO-MDIX when autoneg is disabled */
10728 elink_cl45_write(sc, phy,
10729 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
10730 (1<<15 | 1<<9 | 7<<0));
10731 /* The PHY needs this set even for forced link. */
10732 an_10_100_val |= (1<<8) | (1<<7);
10733 ELINK_DEBUG_P0(sc, "Setting 100M force\n");
10735 if ((phy->req_line_speed == ELINK_SPEED_10) &&
10737 (ELINK_SUPPORTED_10baseT_Half |
10738 ELINK_SUPPORTED_10baseT_Full))) {
10739 /* Enabled AUTO-MDIX when autoneg is disabled */
10740 elink_cl45_write(sc, phy,
10741 MDIO_AN_DEVAD, MDIO_AN_REG_8481_AUX_CTRL,
10742 (1<<15 | 1<<9 | 7<<0));
10743 ELINK_DEBUG_P0(sc, "Setting 10M force\n");
10746 elink_cl45_write(sc, phy,
10747 MDIO_AN_DEVAD, MDIO_AN_REG_8481_LEGACY_AN_ADV,
10750 if (phy->req_duplex == DUPLEX_FULL)
10751 autoneg_val |= (1<<8);
10753 /* Always write this if this is not 84833/4.
10754 * For 84833/4, write it only when it's a forced speed.
10756 if (!elink_is_8483x_8485x(phy) ||
10757 ((autoneg_val & (1<<12)) == 0))
10758 elink_cl45_write(sc, phy,
10760 MDIO_AN_REG_8481_LEGACY_MII_CTRL, autoneg_val);
10762 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
10763 (phy->speed_cap_mask &
10764 PORT_HW_CFG_SPEED_CAPABILITY_D0_10G)) ||
10765 (phy->req_line_speed == ELINK_SPEED_10000)) {
10766 ELINK_DEBUG_P0(sc, "Advertising 10G\n");
10767 /* Restart autoneg for 10G*/
10769 elink_cl45_read_or_write(
10772 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
10774 elink_cl45_write(sc, phy,
10775 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL,
10778 elink_cl45_write(sc, phy,
10780 MDIO_AN_REG_8481_10GBASE_T_AN_CTRL,
10783 return ELINK_STATUS_OK;
10786 static elink_status_t elink_8481_config_init(struct elink_phy *phy,
10787 struct elink_params *params,
10788 struct elink_vars *vars)
10790 struct bxe_softc *sc = params->sc;
10791 /* Restore normal power mode*/
10792 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
10793 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
10796 elink_ext_phy_hw_reset(sc, params->port);
10797 elink_wait_reset_complete(sc, phy, params);
10799 elink_cl45_write(sc, phy, MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
10800 return elink_848xx_cmn_config_init(phy, params, vars);
10803 #define PHY848xx_CMDHDLR_WAIT 300
10804 #define PHY848xx_CMDHDLR_MAX_ARGS 5
10806 static elink_status_t elink_84858_cmd_hdlr(struct elink_phy *phy,
10807 struct elink_params *params,
10809 uint16_t cmd_args[], int argc)
10813 struct bxe_softc *sc = params->sc;
10815 /* Step 1: Poll the STATUS register to see whether the previous command
10816 * is in progress or the system is busy (CMD_IN_PROGRESS or
10817 * SYSTEM_BUSY). If previous command is in progress or system is busy,
10818 * check again until the previous command finishes execution and the
10819 * system is available for taking command
10822 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10823 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10824 MDIO_848xx_CMD_HDLR_STATUS, &val);
10825 if ((val != PHY84858_STATUS_CMD_IN_PROGRESS) &&
10826 (val != PHY84858_STATUS_CMD_SYSTEM_BUSY))
10830 if (idx >= PHY848xx_CMDHDLR_WAIT) {
10831 ELINK_DEBUG_P0(sc, "FW cmd: FW not ready.\n");
10832 return ELINK_STATUS_ERROR;
10835 /* Step2: If any parameters are required for the function, write them
10836 * to the required DATA registers
10839 for (idx = 0; idx < argc; idx++) {
10840 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10841 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10845 /* Step3: When the firmware is ready for commands, write the 'Command
10846 * code' to the CMD register
10848 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10849 MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
10851 /* Step4: Once the command has been written, poll the STATUS register
10852 * to check whether the command has completed (CMD_COMPLETED_PASS/
10853 * CMD_FOR_CMDS or CMD_COMPLETED_ERROR).
10856 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10857 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10858 MDIO_848xx_CMD_HDLR_STATUS, &val);
10859 if ((val == PHY84858_STATUS_CMD_COMPLETE_PASS) ||
10860 (val == PHY84858_STATUS_CMD_COMPLETE_ERROR))
10864 if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
10865 (val == PHY84858_STATUS_CMD_COMPLETE_ERROR)) {
10866 ELINK_DEBUG_P0(sc, "FW cmd failed.\n");
10867 return ELINK_STATUS_ERROR;
10869 /* Step5: Once the command has completed, read the specficied DATA
10870 * registers for any saved results for the command, if applicable
10873 /* Gather returning data */
10874 for (idx = 0; idx < argc; idx++) {
10875 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10876 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10880 return ELINK_STATUS_OK;
10883 static elink_status_t elink_84833_cmd_hdlr(struct elink_phy *phy,
10884 struct elink_params *params, uint16_t fw_cmd,
10885 uint16_t cmd_args[], int argc, int process)
10889 struct bxe_softc *sc = params->sc;
10890 elink_status_t rc = ELINK_STATUS_OK;
10892 if (process == PHY84833_MB_PROCESS2) {
10893 /* Write CMD_OPEN_OVERRIDE to STATUS reg */
10894 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10895 MDIO_848xx_CMD_HDLR_STATUS,
10896 PHY84833_STATUS_CMD_OPEN_OVERRIDE);
10899 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10900 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10901 MDIO_848xx_CMD_HDLR_STATUS, &val);
10902 if (val == PHY84833_STATUS_CMD_OPEN_FOR_CMDS)
10906 if (idx >= PHY848xx_CMDHDLR_WAIT) {
10907 ELINK_DEBUG_P0(sc, "FW cmd: FW not ready.\n");
10908 /* if the status is CMD_COMPLETE_PASS or CMD_COMPLETE_ERROR
10909 * clear the status to CMD_CLEAR_COMPLETE
10911 if (val == PHY84833_STATUS_CMD_COMPLETE_PASS ||
10912 val == PHY84833_STATUS_CMD_COMPLETE_ERROR) {
10913 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10914 MDIO_848xx_CMD_HDLR_STATUS,
10915 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10917 return ELINK_STATUS_ERROR;
10919 if (process == PHY84833_MB_PROCESS1 ||
10920 process == PHY84833_MB_PROCESS2) {
10921 /* Prepare argument(s) */
10922 for (idx = 0; idx < argc; idx++) {
10923 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10924 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10929 /* Issue command */
10930 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10931 MDIO_848xx_CMD_HDLR_COMMAND, fw_cmd);
10932 for (idx = 0; idx < PHY848xx_CMDHDLR_WAIT; idx++) {
10933 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10934 MDIO_848xx_CMD_HDLR_STATUS, &val);
10935 if ((val == PHY84833_STATUS_CMD_COMPLETE_PASS) ||
10936 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR))
10940 if ((idx >= PHY848xx_CMDHDLR_WAIT) ||
10941 (val == PHY84833_STATUS_CMD_COMPLETE_ERROR)) {
10942 ELINK_DEBUG_P0(sc, "FW cmd failed.\n");
10943 rc = ELINK_STATUS_ERROR;
10945 if (process == PHY84833_MB_PROCESS3 && rc == ELINK_STATUS_OK) {
10946 /* Gather returning data */
10947 for (idx = 0; idx < argc; idx++) {
10948 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
10949 MDIO_848xx_CMD_HDLR_DATA1 + idx,
10953 if (val == PHY84833_STATUS_CMD_COMPLETE_ERROR ||
10954 val == PHY84833_STATUS_CMD_COMPLETE_PASS) {
10955 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
10956 MDIO_848xx_CMD_HDLR_STATUS,
10957 PHY84833_STATUS_CMD_CLEAR_COMPLETE);
10962 static elink_status_t elink_848xx_cmd_hdlr(struct elink_phy *phy,
10963 struct elink_params *params,
10965 uint16_t cmd_args[], int argc,
10968 struct bxe_softc *sc = params->sc;
10970 if ((phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) ||
10971 (REG_RD(sc, params->shmem2_base +
10972 offsetof(struct shmem2_region,
10973 link_attr_sync[params->port])) & LINK_ATTR_84858)) {
10974 return elink_84858_cmd_hdlr(phy, params, fw_cmd, cmd_args,
10977 return elink_84833_cmd_hdlr(phy, params, fw_cmd, cmd_args,
10982 static elink_status_t elink_848xx_pair_swap_cfg(struct elink_phy *phy,
10983 struct elink_params *params,
10984 struct elink_vars *vars)
10986 uint32_t pair_swap;
10987 uint16_t data[PHY848xx_CMDHDLR_MAX_ARGS];
10988 elink_status_t status;
10989 struct bxe_softc *sc = params->sc;
10991 /* Check for configuration. */
10992 pair_swap = REG_RD(sc, params->shmem_base +
10993 offsetof(struct shmem_region,
10994 dev_info.port_hw_config[params->port].xgbt_phy_cfg)) &
10995 PORT_HW_CFG_RJ45_PAIR_SWAP_MASK;
10997 if (pair_swap == 0)
10998 return ELINK_STATUS_OK;
11000 /* Only the second argument is used for this command */
11001 data[1] = (uint16_t)pair_swap;
11003 status = elink_848xx_cmd_hdlr(phy, params,
11004 PHY848xx_CMD_SET_PAIR_SWAP, data,
11005 2, PHY84833_MB_PROCESS2);
11006 if (status == ELINK_STATUS_OK)
11007 ELINK_DEBUG_P1(sc, "Pairswap OK, val=0x%x\n", data[1]);
11012 static uint8_t elink_84833_get_reset_gpios(struct bxe_softc *sc,
11013 uint32_t shmem_base_path[],
11016 uint32_t reset_pin[2];
11018 uint8_t reset_gpios;
11019 if (CHIP_IS_E3(sc)) {
11020 /* Assume that these will be GPIOs, not EPIOs. */
11021 for (idx = 0; idx < 2; idx++) {
11022 /* Map config param to register bit. */
11023 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
11024 offsetof(struct shmem_region,
11025 dev_info.port_hw_config[0].e3_cmn_pin_cfg));
11026 reset_pin[idx] = (reset_pin[idx] &
11027 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11028 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11029 reset_pin[idx] -= PIN_CFG_GPIO0_P0;
11030 reset_pin[idx] = (1 << reset_pin[idx]);
11032 reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);
11034 /* E2, look from diff place of shmem. */
11035 for (idx = 0; idx < 2; idx++) {
11036 reset_pin[idx] = REG_RD(sc, shmem_base_path[idx] +
11037 offsetof(struct shmem_region,
11038 dev_info.port_hw_config[0].default_cfg));
11039 reset_pin[idx] &= PORT_HW_CFG_EXT_PHY_GPIO_RST_MASK;
11040 reset_pin[idx] -= PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0;
11041 reset_pin[idx] >>= PORT_HW_CFG_EXT_PHY_GPIO_RST_SHIFT;
11042 reset_pin[idx] = (1 << reset_pin[idx]);
11044 reset_gpios = (uint8_t)(reset_pin[0] | reset_pin[1]);
11047 return reset_gpios;
11050 static elink_status_t elink_84833_hw_reset_phy(struct elink_phy *phy,
11051 struct elink_params *params)
11053 struct bxe_softc *sc = params->sc;
11054 uint8_t reset_gpios;
11055 uint32_t other_shmem_base_addr = REG_RD(sc, params->shmem2_base +
11056 offsetof(struct shmem2_region,
11057 other_shmem_base_addr));
11059 uint32_t shmem_base_path[2];
11061 /* Work around for 84833 LED failure inside RESET status */
11062 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
11063 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
11064 MDIO_AN_REG_8481_MII_CTRL_FORCE_1G);
11065 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
11066 MDIO_AN_REG_8481_1G_100T_EXT_CTRL,
11067 MIDO_AN_REG_8481_EXT_CTRL_FORCE_LEDS_OFF);
11069 shmem_base_path[0] = params->shmem_base;
11070 shmem_base_path[1] = other_shmem_base_addr;
11072 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path,
11075 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
11077 ELINK_DEBUG_P1(sc, "84833 hw reset on pin values 0x%x\n",
11080 return ELINK_STATUS_OK;
11083 static elink_status_t elink_8483x_disable_eee(struct elink_phy *phy,
11084 struct elink_params *params,
11085 struct elink_vars *vars)
11088 struct bxe_softc *sc = params->sc;
11089 uint16_t cmd_args = 0;
11091 ELINK_DEBUG_P0(sc, "Don't Advertise 10GBase-T EEE\n");
11093 /* Prevent Phy from working in EEE and advertising it */
11094 rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
11095 &cmd_args, 1, PHY84833_MB_PROCESS1);
11096 if (rc != ELINK_STATUS_OK) {
11097 ELINK_DEBUG_P0(sc, "EEE disable failed.\n");
11101 return elink_eee_disable(phy, params, vars);
11104 static elink_status_t elink_8483x_enable_eee(struct elink_phy *phy,
11105 struct elink_params *params,
11106 struct elink_vars *vars)
11109 struct bxe_softc *sc = params->sc;
11110 uint16_t cmd_args = 1;
11112 rc = elink_848xx_cmd_hdlr(phy, params, PHY848xx_CMD_SET_EEE_MODE,
11113 &cmd_args, 1, PHY84833_MB_PROCESS1);
11114 if (rc != ELINK_STATUS_OK) {
11115 ELINK_DEBUG_P0(sc, "EEE enable failed.\n");
11119 return elink_eee_advertise(phy, params, vars, SHMEM_EEE_10G_ADV);
11122 #define PHY84833_CONSTANT_LATENCY 1193
11123 static elink_status_t elink_848x3_config_init(struct elink_phy *phy,
11124 struct elink_params *params,
11125 struct elink_vars *vars)
11127 struct bxe_softc *sc = params->sc;
11128 uint8_t port, initialize = 1;
11130 uint32_t actual_phy_selection;
11131 uint16_t cmd_args[PHY848xx_CMDHDLR_MAX_ARGS];
11132 elink_status_t rc = ELINK_STATUS_OK;
11136 if (!(CHIP_IS_E1x(sc)))
11137 port = SC_PATH(sc);
11139 port = params->port;
11141 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
11142 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
11143 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
11147 elink_cl45_write(sc, phy,
11149 MDIO_PMA_REG_CTRL, 0x8000);
11152 elink_wait_reset_complete(sc, phy, params);
11154 /* Wait for GPHY to come out of reset */
11156 if (!elink_is_8483x_8485x(phy)) {
11157 /* BCM84823 requires that XGXS links up first @ 10G for normal
11161 temp = vars->line_speed;
11162 vars->line_speed = ELINK_SPEED_10000;
11163 elink_set_autoneg(¶ms->phy[ELINK_INT_PHY], params, vars, 0);
11164 elink_program_serdes(¶ms->phy[ELINK_INT_PHY], params, vars);
11165 vars->line_speed = temp;
11167 /* Check if this is actually BCM84858 */
11168 if (phy->type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858) {
11171 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11172 MDIO_AN_REG_848xx_ID_MSB, &hw_rev);
11173 if (hw_rev == BCM84858_PHY_ID) {
11174 params->link_attr_sync |= LINK_ATTR_84858;
11175 elink_update_link_attr(params, params->link_attr_sync);
11179 /* Set dual-media configuration according to configuration */
11180 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11181 MDIO_CTL_REG_84823_MEDIA, &val);
11182 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
11183 MDIO_CTL_REG_84823_MEDIA_LINE_MASK |
11184 MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN |
11185 MDIO_CTL_REG_84823_MEDIA_PRIORITY_MASK |
11186 MDIO_CTL_REG_84823_MEDIA_FIBER_1G);
11188 if (CHIP_IS_E3(sc)) {
11189 val &= ~(MDIO_CTL_REG_84823_MEDIA_MAC_MASK |
11190 MDIO_CTL_REG_84823_MEDIA_LINE_MASK);
11192 val |= (MDIO_CTL_REG_84823_CTRL_MAC_XFI |
11193 MDIO_CTL_REG_84823_MEDIA_LINE_XAUI_L);
11196 actual_phy_selection = elink_phy_selection(params);
11198 switch (actual_phy_selection) {
11199 case PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT:
11200 /* Do nothing. Essentially this is like the priority copper */
11202 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
11203 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_COPPER;
11205 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
11206 val |= MDIO_CTL_REG_84823_MEDIA_PRIORITY_FIBER;
11208 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
11209 /* Do nothing here. The first PHY won't be initialized at all */
11211 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
11212 val |= MDIO_CTL_REG_84823_MEDIA_COPPER_CORE_DOWN;
11216 if (params->phy[ELINK_EXT_PHY2].req_line_speed == ELINK_SPEED_1000)
11217 val |= MDIO_CTL_REG_84823_MEDIA_FIBER_1G;
11219 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
11220 MDIO_CTL_REG_84823_MEDIA, val);
11221 ELINK_DEBUG_P2(sc, "Multi_phy config = 0x%x, Media control = 0x%x\n",
11222 params->multi_phy_config, val);
11224 if (elink_is_8483x_8485x(phy)) {
11225 elink_848xx_pair_swap_cfg(phy, params, vars);
11227 /* Keep AutogrEEEn disabled. */
11230 cmd_args[2] = PHY84833_CONSTANT_LATENCY + 1;
11231 cmd_args[3] = PHY84833_CONSTANT_LATENCY;
11232 rc = elink_848xx_cmd_hdlr(phy, params,
11233 PHY848xx_CMD_SET_EEE_MODE, cmd_args,
11234 4, PHY84833_MB_PROCESS1);
11235 if (rc != ELINK_STATUS_OK)
11236 ELINK_DEBUG_P0(sc, "Cfg AutogrEEEn failed.\n");
11239 rc = elink_848xx_cmn_config_init(phy, params, vars);
11241 elink_save_848xx_spirom_version(phy, sc, params->port);
11242 /* 84833 PHY has a better feature and doesn't need to support this. */
11243 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
11244 uint32_t cms_enable = REG_RD(sc, params->shmem_base +
11245 offsetof(struct shmem_region,
11246 dev_info.port_hw_config[params->port].default_cfg)) &
11247 PORT_HW_CFG_ENABLE_CMS_MASK;
11249 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11250 MDIO_CTL_REG_84823_USER_CTRL_REG, &val);
11252 val |= MDIO_CTL_REG_84823_USER_CTRL_CMS;
11254 val &= ~MDIO_CTL_REG_84823_USER_CTRL_CMS;
11255 elink_cl45_write(sc, phy, MDIO_CTL_DEVAD,
11256 MDIO_CTL_REG_84823_USER_CTRL_REG, val);
11259 elink_cl45_read(sc, phy, MDIO_CTL_DEVAD,
11260 MDIO_84833_TOP_CFG_FW_REV, &val);
11262 /* Configure EEE support */
11263 if ((val >= MDIO_84833_TOP_CFG_FW_EEE) &&
11264 (val != MDIO_84833_TOP_CFG_FW_NO_EEE) &&
11265 elink_eee_has_cap(params)) {
11266 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_10G_ADV);
11267 if (rc != ELINK_STATUS_OK) {
11268 ELINK_DEBUG_P0(sc, "Failed to configure EEE timers\n");
11269 elink_8483x_disable_eee(phy, params, vars);
11273 if ((phy->req_duplex == DUPLEX_FULL) &&
11274 (params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
11275 (elink_eee_calc_timer(params) ||
11276 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI)))
11277 rc = elink_8483x_enable_eee(phy, params, vars);
11279 rc = elink_8483x_disable_eee(phy, params, vars);
11280 if (rc != ELINK_STATUS_OK) {
11281 ELINK_DEBUG_P0(sc, "Failed to set EEE advertisement\n");
11285 vars->eee_status &= ~SHMEM_EEE_SUPPORTED_MASK;
11288 if (elink_is_8483x_8485x(phy)) {
11289 /* Bring PHY out of super isolate mode as the final step. */
11290 elink_cl45_read_and_write(sc, phy,
11292 MDIO_84833_TOP_CFG_XGPHY_STRAP1,
11293 (uint16_t)~MDIO_84833_SUPER_ISOLATE);
11298 static uint8_t elink_848xx_read_status(struct elink_phy *phy,
11299 struct elink_params *params,
11300 struct elink_vars *vars)
11302 struct bxe_softc *sc = params->sc;
11303 uint16_t val, val1, val2;
11304 uint8_t link_up = 0;
11307 /* Check 10G-BaseT link status */
11308 /* Check PMD signal ok */
11309 elink_cl45_read(sc, phy,
11310 MDIO_AN_DEVAD, 0xFFFA, &val1);
11311 elink_cl45_read(sc, phy,
11312 MDIO_PMA_DEVAD, MDIO_PMA_REG_8481_PMD_SIGNAL,
11314 ELINK_DEBUG_P1(sc, "BCM848xx: PMD_SIGNAL 1.a811 = 0x%x\n", val2);
11316 /* Check link 10G */
11317 if (val2 & (1<<11)) {
11318 vars->line_speed = ELINK_SPEED_10000;
11319 vars->duplex = DUPLEX_FULL;
11321 elink_ext_phy_10G_an_resolve(sc, phy, vars);
11322 } else { /* Check Legacy speed link */
11323 uint16_t legacy_status, legacy_speed;
11325 /* Enable expansion register 0x42 (Operation mode status) */
11326 elink_cl45_write(sc, phy,
11328 MDIO_AN_REG_8481_EXPANSION_REG_ACCESS, 0xf42);
11330 /* Get legacy speed operation status */
11331 elink_cl45_read(sc, phy,
11333 MDIO_AN_REG_8481_EXPANSION_REG_RD_RW,
11336 ELINK_DEBUG_P1(sc, "Legacy speed status = 0x%x\n",
11338 link_up = ((legacy_status & (1<<11)) == (1<<11));
11339 legacy_speed = (legacy_status & (3<<9));
11340 if (legacy_speed == (0<<9))
11341 vars->line_speed = ELINK_SPEED_10;
11342 else if (legacy_speed == (1<<9))
11343 vars->line_speed = ELINK_SPEED_100;
11344 else if (legacy_speed == (2<<9))
11345 vars->line_speed = ELINK_SPEED_1000;
11346 else { /* Should not happen: Treat as link down */
11347 vars->line_speed = 0;
11351 if (params->feature_config_flags &
11352 ELINK_FEATURE_CONFIG_IEEE_PHY_TEST) {
11355 elink_cl45_read(sc, phy,
11357 MDIO_AN_REG_8481_LEGACY_MII_CTRL,
11359 /* For IEEE testing, check for a fake link. */
11360 link_up |= ((mii_ctrl & 0x3040) == 0x40);
11364 if (legacy_status & (1<<8))
11365 vars->duplex = DUPLEX_FULL;
11367 vars->duplex = DUPLEX_HALF;
11370 "Link is up in %dMbps, is_duplex_full= %d\n",
11372 (vars->duplex == DUPLEX_FULL));
11373 /* Check legacy speed AN resolution */
11374 elink_cl45_read(sc, phy,
11376 MDIO_AN_REG_8481_LEGACY_MII_STATUS,
11379 vars->link_status |=
11380 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
11381 elink_cl45_read(sc, phy,
11383 MDIO_AN_REG_8481_LEGACY_AN_EXPANSION,
11385 if ((val & (1<<0)) == 0)
11386 vars->link_status |=
11387 LINK_STATUS_PARALLEL_DETECTION_USED;
11391 ELINK_DEBUG_P1(sc, "BCM848x3: link speed is %d\n",
11393 elink_ext_phy_resolve_fc(phy, params, vars);
11395 /* Read LP advertised speeds */
11396 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11397 MDIO_AN_REG_CL37_FC_LP, &val);
11399 vars->link_status |=
11400 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
11402 vars->link_status |=
11403 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
11405 vars->link_status |=
11406 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
11408 vars->link_status |=
11409 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
11411 vars->link_status |=
11412 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
11414 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11415 MDIO_AN_REG_1000T_STATUS, &val);
11418 vars->link_status |=
11419 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
11421 vars->link_status |=
11422 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
11424 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
11425 MDIO_AN_REG_MASTER_STATUS, &val);
11428 vars->link_status |=
11429 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
11431 /* Determine if EEE was negotiated */
11432 if (elink_is_8483x_8485x(phy))
11433 elink_eee_an_resolve(phy, params, vars);
11439 static elink_status_t elink_848xx_format_ver(uint32_t raw_ver, uint8_t *str, uint16_t *len)
11441 elink_status_t status = ELINK_STATUS_OK;
11442 uint32_t spirom_ver;
11443 spirom_ver = ((raw_ver & 0xF80) >> 7) << 16 | (raw_ver & 0x7F);
11444 status = elink_format_ver(spirom_ver, str, len);
11448 static void elink_8481_hw_reset(struct elink_phy *phy,
11449 struct elink_params *params)
11451 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
11452 MISC_REGISTERS_GPIO_OUTPUT_LOW, 0);
11453 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
11454 MISC_REGISTERS_GPIO_OUTPUT_LOW, 1);
11457 static void elink_8481_link_reset(struct elink_phy *phy,
11458 struct elink_params *params)
11460 elink_cl45_write(params->sc, phy,
11461 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, 0x0000);
11462 elink_cl45_write(params->sc, phy,
11463 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1);
11466 static void elink_848x3_link_reset(struct elink_phy *phy,
11467 struct elink_params *params)
11469 struct bxe_softc *sc = params->sc;
11473 if (!(CHIP_IS_E1x(sc)))
11474 port = SC_PATH(sc);
11476 port = params->port;
11478 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823) {
11479 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_3,
11480 MISC_REGISTERS_GPIO_OUTPUT_LOW,
11483 elink_cl45_read(sc, phy,
11485 MDIO_84833_TOP_CFG_XGPHY_STRAP1, &val16);
11486 val16 |= MDIO_84833_SUPER_ISOLATE;
11487 elink_cl45_write(sc, phy,
11489 MDIO_84833_TOP_CFG_XGPHY_STRAP1, val16);
11493 static void elink_848xx_set_link_led(struct elink_phy *phy,
11494 struct elink_params *params, uint8_t mode)
11496 struct bxe_softc *sc = params->sc;
11500 if (!(CHIP_IS_E1x(sc)))
11501 port = SC_PATH(sc);
11503 port = params->port;
11505 case ELINK_LED_MODE_OFF:
11507 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OFF\n", port);
11509 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11510 SHARED_HW_CFG_LED_EXTPHY1) {
11512 /* Set LED masks */
11513 elink_cl45_write(sc, phy,
11515 MDIO_PMA_REG_8481_LED1_MASK,
11518 elink_cl45_write(sc, phy,
11520 MDIO_PMA_REG_8481_LED2_MASK,
11523 elink_cl45_write(sc, phy,
11525 MDIO_PMA_REG_8481_LED3_MASK,
11528 elink_cl45_write(sc, phy,
11530 MDIO_PMA_REG_8481_LED5_MASK,
11534 elink_cl45_write(sc, phy,
11536 MDIO_PMA_REG_8481_LED1_MASK,
11540 case ELINK_LED_MODE_FRONT_PANEL_OFF:
11542 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE FRONT PANEL OFF\n",
11545 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11546 SHARED_HW_CFG_LED_EXTPHY1) {
11548 /* Set LED masks */
11549 elink_cl45_write(sc, phy,
11551 MDIO_PMA_REG_8481_LED1_MASK,
11554 elink_cl45_write(sc, phy,
11556 MDIO_PMA_REG_8481_LED2_MASK,
11559 elink_cl45_write(sc, phy,
11561 MDIO_PMA_REG_8481_LED3_MASK,
11564 elink_cl45_write(sc, phy,
11566 MDIO_PMA_REG_8481_LED5_MASK,
11570 elink_cl45_write(sc, phy,
11572 MDIO_PMA_REG_8481_LED1_MASK,
11575 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11576 /* Disable MI_INT interrupt before setting LED4
11577 * source to constant off.
11579 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
11581 ELINK_NIG_MASK_MI_INT) {
11582 params->link_flags |=
11583 ELINK_LINK_FLAGS_INT_DISABLED;
11587 NIG_REG_MASK_INTERRUPT_PORT0 +
11589 ELINK_NIG_MASK_MI_INT);
11591 elink_cl45_write(sc, phy,
11593 MDIO_PMA_REG_8481_SIGNAL_MASK,
11598 case ELINK_LED_MODE_ON:
11600 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE ON\n", port);
11602 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11603 SHARED_HW_CFG_LED_EXTPHY1) {
11604 /* Set control reg */
11605 elink_cl45_read(sc, phy,
11607 MDIO_PMA_REG_8481_LINK_SIGNAL,
11612 elink_cl45_write(sc, phy,
11614 MDIO_PMA_REG_8481_LINK_SIGNAL,
11617 /* Set LED masks */
11618 elink_cl45_write(sc, phy,
11620 MDIO_PMA_REG_8481_LED1_MASK,
11623 elink_cl45_write(sc, phy,
11625 MDIO_PMA_REG_8481_LED2_MASK,
11628 elink_cl45_write(sc, phy,
11630 MDIO_PMA_REG_8481_LED3_MASK,
11633 elink_cl45_write(sc, phy,
11635 MDIO_PMA_REG_8481_LED5_MASK,
11638 elink_cl45_write(sc, phy,
11640 MDIO_PMA_REG_8481_LED1_MASK,
11643 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11644 /* Disable MI_INT interrupt before setting LED4
11645 * source to constant on.
11647 if (REG_RD(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
11649 ELINK_NIG_MASK_MI_INT) {
11650 params->link_flags |=
11651 ELINK_LINK_FLAGS_INT_DISABLED;
11655 NIG_REG_MASK_INTERRUPT_PORT0 +
11657 ELINK_NIG_MASK_MI_INT);
11659 elink_cl45_write(sc, phy,
11661 MDIO_PMA_REG_8481_SIGNAL_MASK,
11667 case ELINK_LED_MODE_OPER:
11669 ELINK_DEBUG_P1(sc, "Port 0x%x: LED MODE OPER\n", port);
11671 if ((params->hw_led_mode << SHARED_HW_CFG_LED_MODE_SHIFT) ==
11672 SHARED_HW_CFG_LED_EXTPHY1) {
11674 /* Set control reg */
11675 elink_cl45_read(sc, phy,
11677 MDIO_PMA_REG_8481_LINK_SIGNAL,
11681 MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_MASK)
11682 >> MDIO_PMA_REG_8481_LINK_SIGNAL_LED4_ENABLE_SHIFT)) {
11683 ELINK_DEBUG_P0(sc, "Setting LINK_SIGNAL\n");
11684 elink_cl45_write(sc, phy,
11686 MDIO_PMA_REG_8481_LINK_SIGNAL,
11690 /* Set LED masks */
11691 elink_cl45_write(sc, phy,
11693 MDIO_PMA_REG_8481_LED1_MASK,
11696 elink_cl45_write(sc, phy,
11698 MDIO_PMA_REG_8481_LED2_MASK,
11701 elink_cl45_write(sc, phy,
11703 MDIO_PMA_REG_8481_LED3_MASK,
11706 elink_cl45_write(sc, phy,
11708 MDIO_PMA_REG_8481_LED5_MASK,
11712 /* EXTPHY2 LED mode indicate that the 100M/1G/10G LED
11713 * sources are all wired through LED1, rather than only
11714 * 10G in other modes.
11716 val = ((params->hw_led_mode <<
11717 SHARED_HW_CFG_LED_MODE_SHIFT) ==
11718 SHARED_HW_CFG_LED_EXTPHY2) ? 0x98 : 0x80;
11720 elink_cl45_write(sc, phy,
11722 MDIO_PMA_REG_8481_LED1_MASK,
11725 /* Tell LED3 to blink on source */
11726 elink_cl45_read(sc, phy,
11728 MDIO_PMA_REG_8481_LINK_SIGNAL,
11731 val |= (1<<6); /* A83B[8:6]= 1 */
11732 elink_cl45_write(sc, phy,
11734 MDIO_PMA_REG_8481_LINK_SIGNAL,
11737 PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834) {
11738 /* Restore LED4 source to external link,
11739 * and re-enable interrupts.
11741 elink_cl45_write(sc, phy,
11743 MDIO_PMA_REG_8481_SIGNAL_MASK,
11745 if (params->link_flags &
11746 ELINK_LINK_FLAGS_INT_DISABLED) {
11747 elink_link_int_enable(params);
11748 params->link_flags &=
11749 ~ELINK_LINK_FLAGS_INT_DISABLED;
11756 /* This is a workaround for E3+84833 until autoneg
11757 * restart is fixed in f/w
11759 if (CHIP_IS_E3(sc)) {
11760 elink_cl45_read(sc, phy, MDIO_WC_DEVAD,
11761 MDIO_WC_REG_GP2_STATUS_GP_2_1, &val);
11765 /******************************************************************/
11766 /* 54618SE PHY SECTION */
11767 /******************************************************************/
11768 static void elink_54618se_specific_func(struct elink_phy *phy,
11769 struct elink_params *params,
11772 struct bxe_softc *sc = params->sc;
11775 case ELINK_PHY_INIT:
11776 /* Configure LED4: set to INTR (0x6). */
11777 /* Accessing shadow register 0xe. */
11778 elink_cl22_write(sc, phy,
11779 MDIO_REG_GPHY_SHADOW,
11780 MDIO_REG_GPHY_SHADOW_LED_SEL2);
11781 elink_cl22_read(sc, phy,
11782 MDIO_REG_GPHY_SHADOW,
11784 temp &= ~(0xf << 4);
11785 temp |= (0x6 << 4);
11786 elink_cl22_write(sc, phy,
11787 MDIO_REG_GPHY_SHADOW,
11788 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11789 /* Configure INTR based on link status change. */
11790 elink_cl22_write(sc, phy,
11791 MDIO_REG_INTR_MASK,
11792 ~MDIO_REG_INTR_MASK_LINK_STATUS);
11797 static elink_status_t elink_54618se_config_init(struct elink_phy *phy,
11798 struct elink_params *params,
11799 struct elink_vars *vars)
11801 struct bxe_softc *sc = params->sc;
11803 uint16_t autoneg_val, an_1000_val, an_10_100_val, fc_val, temp;
11806 ELINK_DEBUG_P0(sc, "54618SE cfg init\n");
11809 /* This works with E3 only, no need to check the chip
11810 * before determining the port.
11812 port = params->port;
11814 cfg_pin = (REG_RD(sc, params->shmem_base +
11815 offsetof(struct shmem_region,
11816 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
11817 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
11818 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
11820 /* Drive pin high to bring the GPHY out of reset. */
11821 elink_set_cfg_pin(sc, cfg_pin, 1);
11823 /* wait for GPHY to reset */
11827 elink_cl22_write(sc, phy,
11828 MDIO_PMA_REG_CTRL, 0x8000);
11829 elink_wait_reset_complete(sc, phy, params);
11831 /* Wait for GPHY to reset */
11835 elink_54618se_specific_func(phy, params, ELINK_PHY_INIT);
11836 /* Flip the signal detect polarity (set 0x1c.0x1e[8]). */
11837 elink_cl22_write(sc, phy,
11838 MDIO_REG_GPHY_SHADOW,
11839 MDIO_REG_GPHY_SHADOW_AUTO_DET_MED);
11840 elink_cl22_read(sc, phy,
11841 MDIO_REG_GPHY_SHADOW,
11843 temp |= MDIO_REG_GPHY_SHADOW_INVERT_FIB_SD;
11844 elink_cl22_write(sc, phy,
11845 MDIO_REG_GPHY_SHADOW,
11846 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
11849 /* Please refer to Table 28B-3 of 802.3ab-1999 spec. */
11850 elink_calc_ieee_aneg_adv(phy, params, &vars->ieee_fc);
11852 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC) ==
11853 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_ASYMMETRIC)
11854 fc_val |= MDIO_AN_REG_ADV_PAUSE_ASYMMETRIC;
11856 if ((vars->ieee_fc & MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH) ==
11857 MDIO_COMBO_IEEE0_AUTO_NEG_ADV_PAUSE_BOTH)
11858 fc_val |= MDIO_AN_REG_ADV_PAUSE_PAUSE;
11860 /* Read all advertisement */
11861 elink_cl22_read(sc, phy,
11865 elink_cl22_read(sc, phy,
11869 elink_cl22_read(sc, phy,
11873 /* Disable forced speed */
11874 autoneg_val &= ~((1<<6) | (1<<8) | (1<<9) | (1<<12) | (1<<13));
11875 an_10_100_val &= ~((1<<5) | (1<<6) | (1<<7) | (1<<8) | (1<<10) |
11878 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
11879 (phy->speed_cap_mask &
11880 PORT_HW_CFG_SPEED_CAPABILITY_D0_1G)) ||
11881 (phy->req_line_speed == ELINK_SPEED_1000)) {
11882 an_1000_val |= (1<<8);
11883 autoneg_val |= (1<<9 | 1<<12);
11884 if (phy->req_duplex == DUPLEX_FULL)
11885 an_1000_val |= (1<<9);
11886 ELINK_DEBUG_P0(sc, "Advertising 1G\n");
11888 an_1000_val &= ~((1<<8) | (1<<9));
11890 elink_cl22_write(sc, phy,
11893 elink_cl22_read(sc, phy,
11897 /* Advertise 10/100 link speed */
11898 if (phy->req_line_speed == ELINK_SPEED_AUTO_NEG) {
11899 if (phy->speed_cap_mask &
11900 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_HALF) {
11901 an_10_100_val |= (1<<5);
11902 autoneg_val |= (1<<9 | 1<<12);
11903 ELINK_DEBUG_P0(sc, "Advertising 10M-HD\n");
11905 if (phy->speed_cap_mask &
11906 PORT_HW_CFG_SPEED_CAPABILITY_D0_10M_FULL) {
11907 an_10_100_val |= (1<<6);
11908 autoneg_val |= (1<<9 | 1<<12);
11909 ELINK_DEBUG_P0(sc, "Advertising 10M-FD\n");
11911 if (phy->speed_cap_mask &
11912 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_HALF) {
11913 an_10_100_val |= (1<<7);
11914 autoneg_val |= (1<<9 | 1<<12);
11915 ELINK_DEBUG_P0(sc, "Advertising 100M-HD\n");
11917 if (phy->speed_cap_mask &
11918 PORT_HW_CFG_SPEED_CAPABILITY_D0_100M_FULL) {
11919 an_10_100_val |= (1<<8);
11920 autoneg_val |= (1<<9 | 1<<12);
11921 ELINK_DEBUG_P0(sc, "Advertising 100M-FD\n");
11925 /* Only 10/100 are allowed to work in FORCE mode */
11926 if (phy->req_line_speed == ELINK_SPEED_100) {
11927 autoneg_val |= (1<<13);
11928 /* Enabled AUTO-MDIX when autoneg is disabled */
11929 elink_cl22_write(sc, phy,
11931 (1<<15 | 1<<9 | 7<<0));
11932 ELINK_DEBUG_P0(sc, "Setting 100M force\n");
11934 if (phy->req_line_speed == ELINK_SPEED_10) {
11935 /* Enabled AUTO-MDIX when autoneg is disabled */
11936 elink_cl22_write(sc, phy,
11938 (1<<15 | 1<<9 | 7<<0));
11939 ELINK_DEBUG_P0(sc, "Setting 10M force\n");
11942 if ((phy->flags & ELINK_FLAGS_EEE) && elink_eee_has_cap(params)) {
11945 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS,
11946 MDIO_REG_GPHY_EXP_ACCESS_TOP |
11947 MDIO_REG_GPHY_EXP_TOP_2K_BUF);
11948 elink_cl22_read(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, &temp);
11950 elink_cl22_write(sc, phy, MDIO_REG_GPHY_EXP_ACCESS_GATE, temp);
11952 rc = elink_eee_initial_config(params, vars, SHMEM_EEE_1G_ADV);
11953 if (rc != ELINK_STATUS_OK) {
11954 ELINK_DEBUG_P0(sc, "Failed to configure EEE timers\n");
11955 elink_eee_disable(phy, params, vars);
11956 } else if ((params->eee_mode & ELINK_EEE_MODE_ADV_LPI) &&
11957 (phy->req_duplex == DUPLEX_FULL) &&
11958 (elink_eee_calc_timer(params) ||
11959 !(params->eee_mode & ELINK_EEE_MODE_ENABLE_LPI))) {
11960 /* Need to advertise EEE only when requested,
11961 * and either no LPI assertion was requested,
11962 * or it was requested and a valid timer was set.
11963 * Also notice full duplex is required for EEE.
11965 elink_eee_advertise(phy, params, vars,
11968 ELINK_DEBUG_P0(sc, "Don't Advertise 1GBase-T EEE\n");
11969 elink_eee_disable(phy, params, vars);
11972 vars->eee_status &= ((uint32_t)(~SHMEM_EEE_1G_ADV) <<
11973 SHMEM_EEE_SUPPORTED_SHIFT);
11975 if (phy->flags & ELINK_FLAGS_EEE) {
11976 /* Handle legacy auto-grEEEn */
11977 if (params->feature_config_flags &
11978 ELINK_FEATURE_CONFIG_AUTOGREEEN_ENABLED) {
11980 ELINK_DEBUG_P0(sc, "Enabling Auto-GrEEEn\n");
11983 ELINK_DEBUG_P0(sc, "Don't Adv. EEE\n");
11985 elink_cl45_write(sc, phy, MDIO_AN_DEVAD,
11986 MDIO_AN_REG_EEE_ADV, temp);
11990 elink_cl22_write(sc, phy,
11992 an_10_100_val | fc_val);
11994 if (phy->req_duplex == DUPLEX_FULL)
11995 autoneg_val |= (1<<8);
11997 elink_cl22_write(sc, phy,
11998 MDIO_PMA_REG_CTRL, autoneg_val);
12000 return ELINK_STATUS_OK;
12004 static void elink_5461x_set_link_led(struct elink_phy *phy,
12005 struct elink_params *params, uint8_t mode)
12007 struct bxe_softc *sc = params->sc;
12010 elink_cl22_write(sc, phy,
12011 MDIO_REG_GPHY_SHADOW,
12012 MDIO_REG_GPHY_SHADOW_LED_SEL1);
12013 elink_cl22_read(sc, phy,
12014 MDIO_REG_GPHY_SHADOW,
12018 ELINK_DEBUG_P1(sc, "54618x set link led (mode=%x)\n", mode);
12020 case ELINK_LED_MODE_FRONT_PANEL_OFF:
12021 case ELINK_LED_MODE_OFF:
12024 case ELINK_LED_MODE_OPER:
12027 case ELINK_LED_MODE_ON:
12033 elink_cl22_write(sc, phy,
12034 MDIO_REG_GPHY_SHADOW,
12035 MDIO_REG_GPHY_SHADOW_WR_ENA | temp);
12040 static void elink_54618se_link_reset(struct elink_phy *phy,
12041 struct elink_params *params)
12043 struct bxe_softc *sc = params->sc;
12047 /* In case of no EPIO routed to reset the GPHY, put it
12048 * in low power mode.
12050 elink_cl22_write(sc, phy, MDIO_PMA_REG_CTRL, 0x800);
12051 /* This works with E3 only, no need to check the chip
12052 * before determining the port.
12054 port = params->port;
12055 cfg_pin = (REG_RD(sc, params->shmem_base +
12056 offsetof(struct shmem_region,
12057 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
12058 PORT_HW_CFG_E3_PHY_RESET_MASK) >>
12059 PORT_HW_CFG_E3_PHY_RESET_SHIFT;
12061 /* Drive pin low to put GPHY in reset. */
12062 elink_set_cfg_pin(sc, cfg_pin, 0);
12065 static uint8_t elink_54618se_read_status(struct elink_phy *phy,
12066 struct elink_params *params,
12067 struct elink_vars *vars)
12069 struct bxe_softc *sc = params->sc;
12071 uint8_t link_up = 0;
12072 uint16_t legacy_status, legacy_speed;
12074 /* Get speed operation status */
12075 elink_cl22_read(sc, phy,
12076 MDIO_REG_GPHY_AUX_STATUS,
12078 ELINK_DEBUG_P1(sc, "54618SE read_status: 0x%x\n", legacy_status);
12080 /* Read status to clear the PHY interrupt. */
12081 elink_cl22_read(sc, phy,
12082 MDIO_REG_INTR_STATUS,
12085 link_up = ((legacy_status & (1<<2)) == (1<<2));
12088 legacy_speed = (legacy_status & (7<<8));
12089 if (legacy_speed == (7<<8)) {
12090 vars->line_speed = ELINK_SPEED_1000;
12091 vars->duplex = DUPLEX_FULL;
12092 } else if (legacy_speed == (6<<8)) {
12093 vars->line_speed = ELINK_SPEED_1000;
12094 vars->duplex = DUPLEX_HALF;
12095 } else if (legacy_speed == (5<<8)) {
12096 vars->line_speed = ELINK_SPEED_100;
12097 vars->duplex = DUPLEX_FULL;
12099 /* Omitting 100Base-T4 for now */
12100 else if (legacy_speed == (3<<8)) {
12101 vars->line_speed = ELINK_SPEED_100;
12102 vars->duplex = DUPLEX_HALF;
12103 } else if (legacy_speed == (2<<8)) {
12104 vars->line_speed = ELINK_SPEED_10;
12105 vars->duplex = DUPLEX_FULL;
12106 } else if (legacy_speed == (1<<8)) {
12107 vars->line_speed = ELINK_SPEED_10;
12108 vars->duplex = DUPLEX_HALF;
12109 } else /* Should not happen */
12110 vars->line_speed = 0;
12113 "Link is up in %dMbps, is_duplex_full= %d\n",
12115 (vars->duplex == DUPLEX_FULL));
12117 /* Check legacy speed AN resolution */
12118 elink_cl22_read(sc, phy,
12122 vars->link_status |=
12123 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE;
12124 elink_cl22_read(sc, phy,
12127 if ((val & (1<<0)) == 0)
12128 vars->link_status |=
12129 LINK_STATUS_PARALLEL_DETECTION_USED;
12131 ELINK_DEBUG_P1(sc, "BCM54618SE: link speed is %d\n",
12134 elink_ext_phy_resolve_fc(phy, params, vars);
12136 if (vars->link_status & LINK_STATUS_AUTO_NEGOTIATE_COMPLETE) {
12137 /* Report LP advertised speeds */
12138 elink_cl22_read(sc, phy, 0x5, &val);
12141 vars->link_status |=
12142 LINK_STATUS_LINK_PARTNER_10THD_CAPABLE;
12144 vars->link_status |=
12145 LINK_STATUS_LINK_PARTNER_10TFD_CAPABLE;
12147 vars->link_status |=
12148 LINK_STATUS_LINK_PARTNER_100TXHD_CAPABLE;
12150 vars->link_status |=
12151 LINK_STATUS_LINK_PARTNER_100TXFD_CAPABLE;
12153 vars->link_status |=
12154 LINK_STATUS_LINK_PARTNER_100T4_CAPABLE;
12156 elink_cl22_read(sc, phy, 0xa, &val);
12158 vars->link_status |=
12159 LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE;
12161 vars->link_status |=
12162 LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE;
12164 if ((phy->flags & ELINK_FLAGS_EEE) &&
12165 elink_eee_has_cap(params))
12166 elink_eee_an_resolve(phy, params, vars);
12172 static void elink_54618se_config_loopback(struct elink_phy *phy,
12173 struct elink_params *params)
12175 struct bxe_softc *sc = params->sc;
12177 uint32_t umac_base = params->port ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
12179 ELINK_DEBUG_P0(sc, "2PMA/PMD ext_phy_loopback: 54618se\n");
12181 /* Enable master/slave manual mmode and set to master */
12182 /* mii write 9 [bits set 11 12] */
12183 elink_cl22_write(sc, phy, 0x09, 3<<11);
12185 /* forced 1G and disable autoneg */
12186 /* set val [mii read 0] */
12187 /* set val [expr $val & [bits clear 6 12 13]] */
12188 /* set val [expr $val | [bits set 6 8]] */
12189 /* mii write 0 $val */
12190 elink_cl22_read(sc, phy, 0x00, &val);
12191 val &= ~((1<<6) | (1<<12) | (1<<13));
12192 val |= (1<<6) | (1<<8);
12193 elink_cl22_write(sc, phy, 0x00, val);
12195 /* Set external loopback and Tx using 6dB coding */
12196 /* mii write 0x18 7 */
12197 /* set val [mii read 0x18] */
12198 /* mii write 0x18 [expr $val | [bits set 10 15]] */
12199 elink_cl22_write(sc, phy, 0x18, 7);
12200 elink_cl22_read(sc, phy, 0x18, &val);
12201 elink_cl22_write(sc, phy, 0x18, val | (1<<10) | (1<<15));
12203 /* This register opens the gate for the UMAC despite its name */
12204 REG_WR(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4, 1);
12206 /* Maximum Frame Length (RW). Defines a 14-Bit maximum frame
12207 * length used by the MAC receive logic to check frames.
12209 REG_WR(sc, umac_base + UMAC_REG_MAXFR, 0x2710);
12212 /******************************************************************/
12213 /* SFX7101 PHY SECTION */
12214 /******************************************************************/
12215 static void elink_7101_config_loopback(struct elink_phy *phy,
12216 struct elink_params *params)
12218 struct bxe_softc *sc = params->sc;
12219 /* SFX7101_XGXS_TEST1 */
12220 elink_cl45_write(sc, phy,
12221 MDIO_XS_DEVAD, MDIO_XS_SFX7101_XGXS_TEST1, 0x100);
12224 static elink_status_t elink_7101_config_init(struct elink_phy *phy,
12225 struct elink_params *params,
12226 struct elink_vars *vars)
12228 uint16_t fw_ver1, fw_ver2, val;
12229 struct bxe_softc *sc = params->sc;
12230 ELINK_DEBUG_P0(sc, "Setting the SFX7101 LASI indication\n");
12232 /* Restore normal power mode*/
12233 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
12234 MISC_REGISTERS_GPIO_OUTPUT_HIGH, params->port);
12236 elink_ext_phy_hw_reset(sc, params->port);
12237 elink_wait_reset_complete(sc, phy, params);
12239 elink_cl45_write(sc, phy,
12240 MDIO_PMA_DEVAD, MDIO_PMA_LASI_CTRL, 0x1);
12241 ELINK_DEBUG_P0(sc, "Setting the SFX7101 LED to blink on traffic\n");
12242 elink_cl45_write(sc, phy,
12243 MDIO_PMA_DEVAD, MDIO_PMA_REG_7107_LED_CNTL, (1<<3));
12245 elink_ext_phy_set_pause(params, phy, vars);
12246 /* Restart autoneg */
12247 elink_cl45_read(sc, phy,
12248 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, &val);
12250 elink_cl45_write(sc, phy,
12251 MDIO_AN_DEVAD, MDIO_AN_REG_CTRL, val);
12253 /* Save spirom version */
12254 elink_cl45_read(sc, phy,
12255 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER1, &fw_ver1);
12257 elink_cl45_read(sc, phy,
12258 MDIO_PMA_DEVAD, MDIO_PMA_REG_7101_VER2, &fw_ver2);
12259 elink_save_spirom_version(sc, params->port,
12260 (uint32_t)(fw_ver1<<16 | fw_ver2), phy->ver_addr);
12261 return ELINK_STATUS_OK;
12264 static uint8_t elink_7101_read_status(struct elink_phy *phy,
12265 struct elink_params *params,
12266 struct elink_vars *vars)
12268 struct bxe_softc *sc = params->sc;
12270 uint16_t val1, val2;
12271 elink_cl45_read(sc, phy,
12272 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val2);
12273 elink_cl45_read(sc, phy,
12274 MDIO_PMA_DEVAD, MDIO_PMA_LASI_STAT, &val1);
12275 ELINK_DEBUG_P2(sc, "10G-base-T LASI status 0x%x->0x%x\n",
12277 elink_cl45_read(sc, phy,
12278 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val2);
12279 elink_cl45_read(sc, phy,
12280 MDIO_PMA_DEVAD, MDIO_PMA_REG_STATUS, &val1);
12281 ELINK_DEBUG_P2(sc, "10G-base-T PMA status 0x%x->0x%x\n",
12283 link_up = ((val1 & 4) == 4);
12284 /* If link is up print the AN outcome of the SFX7101 PHY */
12286 elink_cl45_read(sc, phy,
12287 MDIO_AN_DEVAD, MDIO_AN_REG_MASTER_STATUS,
12289 vars->line_speed = ELINK_SPEED_10000;
12290 vars->duplex = DUPLEX_FULL;
12291 ELINK_DEBUG_P2(sc, "SFX7101 AN status 0x%x->Master=%x\n",
12292 val2, (val2 & (1<<14)));
12293 elink_ext_phy_10G_an_resolve(sc, phy, vars);
12294 elink_ext_phy_resolve_fc(phy, params, vars);
12296 /* Read LP advertised speeds */
12297 if (val2 & (1<<11))
12298 vars->link_status |=
12299 LINK_STATUS_LINK_PARTNER_10GXFD_CAPABLE;
12304 static elink_status_t elink_7101_format_ver(uint32_t spirom_ver, uint8_t *str, uint16_t *len)
12307 return ELINK_STATUS_ERROR;
12308 str[0] = (spirom_ver & 0xFF);
12309 str[1] = (spirom_ver & 0xFF00) >> 8;
12310 str[2] = (spirom_ver & 0xFF0000) >> 16;
12311 str[3] = (spirom_ver & 0xFF000000) >> 24;
12314 return ELINK_STATUS_OK;
12317 void elink_sfx7101_sp_sw_reset(struct bxe_softc *sc, struct elink_phy *phy)
12321 elink_cl45_read(sc, phy,
12323 MDIO_PMA_REG_7101_RESET, &val);
12325 for (cnt = 0; cnt < 10; cnt++) {
12327 /* Writes a self-clearing reset */
12328 elink_cl45_write(sc, phy,
12330 MDIO_PMA_REG_7101_RESET,
12332 /* Wait for clear */
12333 elink_cl45_read(sc, phy,
12335 MDIO_PMA_REG_7101_RESET, &val);
12337 if ((val & (1<<15)) == 0)
12342 static void elink_7101_hw_reset(struct elink_phy *phy,
12343 struct elink_params *params) {
12344 /* Low power mode is controlled by GPIO 2 */
12345 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_2,
12346 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
12347 /* The PHY reset is controlled by GPIO 1 */
12348 elink_cb_gpio_write(params->sc, MISC_REGISTERS_GPIO_1,
12349 MISC_REGISTERS_GPIO_OUTPUT_LOW, params->port);
12352 static void elink_7101_set_link_led(struct elink_phy *phy,
12353 struct elink_params *params, uint8_t mode)
12356 struct bxe_softc *sc = params->sc;
12358 case ELINK_LED_MODE_FRONT_PANEL_OFF:
12359 case ELINK_LED_MODE_OFF:
12362 case ELINK_LED_MODE_ON:
12365 case ELINK_LED_MODE_OPER:
12369 elink_cl45_write(sc, phy,
12371 MDIO_PMA_REG_7107_LINK_LED_CNTL,
12375 /******************************************************************/
12376 /* STATIC PHY DECLARATION */
12377 /******************************************************************/
12379 static const struct elink_phy phy_null = {
12380 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN,
12383 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12384 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12385 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12388 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12390 .req_flow_ctrl = 0,
12391 .req_line_speed = 0,
12392 .speed_cap_mask = 0,
12395 .config_init = (config_init_t)NULL,
12396 .read_status = (read_status_t)NULL,
12397 .link_reset = (link_reset_t)NULL,
12398 .config_loopback = (config_loopback_t)NULL,
12399 .format_fw_ver = (format_fw_ver_t)NULL,
12400 .hw_reset = (hw_reset_t)NULL,
12401 .set_link_led = (set_link_led_t)NULL,
12402 .phy_specific_func = (phy_specific_func_t)NULL
12405 static const struct elink_phy phy_serdes = {
12406 .type = PORT_HW_CFG_SERDES_EXT_PHY_TYPE_DIRECT,
12410 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12411 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12413 .supported = (ELINK_SUPPORTED_10baseT_Half |
12414 ELINK_SUPPORTED_10baseT_Full |
12415 ELINK_SUPPORTED_100baseT_Half |
12416 ELINK_SUPPORTED_100baseT_Full |
12417 ELINK_SUPPORTED_1000baseT_Full |
12418 ELINK_SUPPORTED_2500baseX_Full |
12419 ELINK_SUPPORTED_TP |
12420 ELINK_SUPPORTED_Autoneg |
12421 ELINK_SUPPORTED_Pause |
12422 ELINK_SUPPORTED_Asym_Pause),
12423 .media_type = ELINK_ETH_PHY_BASE_T,
12425 .req_flow_ctrl = 0,
12426 .req_line_speed = 0,
12427 .speed_cap_mask = 0,
12430 .config_init = (config_init_t)elink_xgxs_config_init,
12431 .read_status = (read_status_t)elink_link_settings_status,
12432 .link_reset = (link_reset_t)elink_int_link_reset,
12433 .config_loopback = (config_loopback_t)NULL,
12434 .format_fw_ver = (format_fw_ver_t)NULL,
12435 .hw_reset = (hw_reset_t)NULL,
12436 .set_link_led = (set_link_led_t)NULL,
12437 .phy_specific_func = (phy_specific_func_t)NULL
12440 static const struct elink_phy phy_xgxs = {
12441 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
12445 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12446 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12448 .supported = (ELINK_SUPPORTED_10baseT_Half |
12449 ELINK_SUPPORTED_10baseT_Full |
12450 ELINK_SUPPORTED_100baseT_Half |
12451 ELINK_SUPPORTED_100baseT_Full |
12452 ELINK_SUPPORTED_1000baseT_Full |
12453 ELINK_SUPPORTED_2500baseX_Full |
12454 ELINK_SUPPORTED_10000baseT_Full |
12455 ELINK_SUPPORTED_FIBRE |
12456 ELINK_SUPPORTED_Autoneg |
12457 ELINK_SUPPORTED_Pause |
12458 ELINK_SUPPORTED_Asym_Pause),
12459 .media_type = ELINK_ETH_PHY_CX4,
12461 .req_flow_ctrl = 0,
12462 .req_line_speed = 0,
12463 .speed_cap_mask = 0,
12466 .config_init = (config_init_t)elink_xgxs_config_init,
12467 .read_status = (read_status_t)elink_link_settings_status,
12468 .link_reset = (link_reset_t)elink_int_link_reset,
12469 .config_loopback = (config_loopback_t)elink_set_xgxs_loopback,
12470 .format_fw_ver = (format_fw_ver_t)NULL,
12471 .hw_reset = (hw_reset_t)NULL,
12472 .set_link_led = (set_link_led_t)NULL,
12473 .phy_specific_func = (phy_specific_func_t)elink_xgxs_specific_func
12475 static const struct elink_phy phy_warpcore = {
12476 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT,
12479 .flags = ELINK_FLAGS_TX_ERROR_CHECK,
12480 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12481 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12483 .supported = (ELINK_SUPPORTED_10baseT_Half |
12484 ELINK_SUPPORTED_10baseT_Full |
12485 ELINK_SUPPORTED_100baseT_Half |
12486 ELINK_SUPPORTED_100baseT_Full |
12487 ELINK_SUPPORTED_1000baseT_Full |
12488 ELINK_SUPPORTED_1000baseKX_Full |
12489 ELINK_SUPPORTED_10000baseT_Full |
12490 ELINK_SUPPORTED_10000baseKR_Full |
12491 ELINK_SUPPORTED_20000baseKR2_Full |
12492 ELINK_SUPPORTED_20000baseMLD2_Full |
12493 ELINK_SUPPORTED_FIBRE |
12494 ELINK_SUPPORTED_Autoneg |
12495 ELINK_SUPPORTED_Pause |
12496 ELINK_SUPPORTED_Asym_Pause),
12497 .media_type = ELINK_ETH_PHY_UNSPECIFIED,
12499 .req_flow_ctrl = 0,
12500 .req_line_speed = 0,
12501 .speed_cap_mask = 0,
12502 /* req_duplex = */0,
12504 .config_init = (config_init_t)elink_warpcore_config_init,
12505 .read_status = (read_status_t)elink_warpcore_read_status,
12506 .link_reset = (link_reset_t)elink_warpcore_link_reset,
12507 .config_loopback = (config_loopback_t)elink_set_warpcore_loopback,
12508 .format_fw_ver = (format_fw_ver_t)NULL,
12509 .hw_reset = (hw_reset_t)elink_warpcore_hw_reset,
12510 .set_link_led = (set_link_led_t)NULL,
12511 .phy_specific_func = (phy_specific_func_t)NULL
12515 static const struct elink_phy phy_7101 = {
12516 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101,
12519 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ,
12520 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12521 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12523 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12524 ELINK_SUPPORTED_TP |
12525 ELINK_SUPPORTED_Autoneg |
12526 ELINK_SUPPORTED_Pause |
12527 ELINK_SUPPORTED_Asym_Pause),
12528 .media_type = ELINK_ETH_PHY_BASE_T,
12530 .req_flow_ctrl = 0,
12531 .req_line_speed = 0,
12532 .speed_cap_mask = 0,
12535 .config_init = (config_init_t)elink_7101_config_init,
12536 .read_status = (read_status_t)elink_7101_read_status,
12537 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12538 .config_loopback = (config_loopback_t)elink_7101_config_loopback,
12539 .format_fw_ver = (format_fw_ver_t)elink_7101_format_ver,
12540 .hw_reset = (hw_reset_t)elink_7101_hw_reset,
12541 .set_link_led = (set_link_led_t)elink_7101_set_link_led,
12542 .phy_specific_func = (phy_specific_func_t)NULL
12544 static const struct elink_phy phy_8073 = {
12545 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073,
12549 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12550 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12552 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12553 ELINK_SUPPORTED_2500baseX_Full |
12554 ELINK_SUPPORTED_1000baseT_Full |
12555 ELINK_SUPPORTED_FIBRE |
12556 ELINK_SUPPORTED_Autoneg |
12557 ELINK_SUPPORTED_Pause |
12558 ELINK_SUPPORTED_Asym_Pause),
12559 .media_type = ELINK_ETH_PHY_KR,
12561 .req_flow_ctrl = 0,
12562 .req_line_speed = 0,
12563 .speed_cap_mask = 0,
12566 .config_init = (config_init_t)elink_8073_config_init,
12567 .read_status = (read_status_t)elink_8073_read_status,
12568 .link_reset = (link_reset_t)elink_8073_link_reset,
12569 .config_loopback = (config_loopback_t)NULL,
12570 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12571 .hw_reset = (hw_reset_t)NULL,
12572 .set_link_led = (set_link_led_t)NULL,
12573 .phy_specific_func = (phy_specific_func_t)elink_8073_specific_func
12575 static const struct elink_phy phy_8705 = {
12576 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705,
12579 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12580 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12581 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12583 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12584 ELINK_SUPPORTED_FIBRE |
12585 ELINK_SUPPORTED_Pause |
12586 ELINK_SUPPORTED_Asym_Pause),
12587 .media_type = ELINK_ETH_PHY_XFP_FIBER,
12589 .req_flow_ctrl = 0,
12590 .req_line_speed = 0,
12591 .speed_cap_mask = 0,
12594 .config_init = (config_init_t)elink_8705_config_init,
12595 .read_status = (read_status_t)elink_8705_read_status,
12596 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12597 .config_loopback = (config_loopback_t)NULL,
12598 .format_fw_ver = (format_fw_ver_t)elink_null_format_ver,
12599 .hw_reset = (hw_reset_t)NULL,
12600 .set_link_led = (set_link_led_t)NULL,
12601 .phy_specific_func = (phy_specific_func_t)NULL
12603 static const struct elink_phy phy_8706 = {
12604 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706,
12607 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12608 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12609 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12611 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12612 ELINK_SUPPORTED_1000baseT_Full |
12613 ELINK_SUPPORTED_FIBRE |
12614 ELINK_SUPPORTED_Pause |
12615 ELINK_SUPPORTED_Asym_Pause),
12616 .media_type = ELINK_ETH_PHY_SFPP_10G_FIBER,
12618 .req_flow_ctrl = 0,
12619 .req_line_speed = 0,
12620 .speed_cap_mask = 0,
12623 .config_init = (config_init_t)elink_8706_config_init,
12624 .read_status = (read_status_t)elink_8706_read_status,
12625 .link_reset = (link_reset_t)elink_common_ext_link_reset,
12626 .config_loopback = (config_loopback_t)NULL,
12627 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12628 .hw_reset = (hw_reset_t)NULL,
12629 .set_link_led = (set_link_led_t)NULL,
12630 .phy_specific_func = (phy_specific_func_t)NULL
12633 static const struct elink_phy phy_8726 = {
12634 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726,
12637 .flags = (ELINK_FLAGS_INIT_XGXS_FIRST |
12638 ELINK_FLAGS_TX_ERROR_CHECK),
12639 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12640 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12642 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12643 ELINK_SUPPORTED_1000baseT_Full |
12644 ELINK_SUPPORTED_Autoneg |
12645 ELINK_SUPPORTED_FIBRE |
12646 ELINK_SUPPORTED_Pause |
12647 ELINK_SUPPORTED_Asym_Pause),
12648 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12650 .req_flow_ctrl = 0,
12651 .req_line_speed = 0,
12652 .speed_cap_mask = 0,
12655 .config_init = (config_init_t)elink_8726_config_init,
12656 .read_status = (read_status_t)elink_8726_read_status,
12657 .link_reset = (link_reset_t)elink_8726_link_reset,
12658 .config_loopback = (config_loopback_t)elink_8726_config_loopback,
12659 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12660 .hw_reset = (hw_reset_t)NULL,
12661 .set_link_led = (set_link_led_t)NULL,
12662 .phy_specific_func = (phy_specific_func_t)NULL
12665 static const struct elink_phy phy_8727 = {
12666 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727,
12669 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12670 ELINK_FLAGS_TX_ERROR_CHECK),
12671 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12672 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12674 .supported = (ELINK_SUPPORTED_10000baseT_Full |
12675 ELINK_SUPPORTED_1000baseT_Full |
12676 ELINK_SUPPORTED_FIBRE |
12677 ELINK_SUPPORTED_Pause |
12678 ELINK_SUPPORTED_Asym_Pause),
12679 .media_type = ELINK_ETH_PHY_NOT_PRESENT,
12681 .req_flow_ctrl = 0,
12682 .req_line_speed = 0,
12683 .speed_cap_mask = 0,
12686 .config_init = (config_init_t)elink_8727_config_init,
12687 .read_status = (read_status_t)elink_8727_read_status,
12688 .link_reset = (link_reset_t)elink_8727_link_reset,
12689 .config_loopback = (config_loopback_t)NULL,
12690 .format_fw_ver = (format_fw_ver_t)elink_format_ver,
12691 .hw_reset = (hw_reset_t)elink_8727_hw_reset,
12692 .set_link_led = (set_link_led_t)elink_8727_set_link_led,
12693 .phy_specific_func = (phy_specific_func_t)elink_8727_specific_func
12695 static const struct elink_phy phy_8481 = {
12696 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481,
12699 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12700 ELINK_FLAGS_REARM_LATCH_SIGNAL,
12701 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12702 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12704 .supported = (ELINK_SUPPORTED_10baseT_Half |
12705 ELINK_SUPPORTED_10baseT_Full |
12706 ELINK_SUPPORTED_100baseT_Half |
12707 ELINK_SUPPORTED_100baseT_Full |
12708 ELINK_SUPPORTED_1000baseT_Full |
12709 ELINK_SUPPORTED_10000baseT_Full |
12710 ELINK_SUPPORTED_TP |
12711 ELINK_SUPPORTED_Autoneg |
12712 ELINK_SUPPORTED_Pause |
12713 ELINK_SUPPORTED_Asym_Pause),
12714 .media_type = ELINK_ETH_PHY_BASE_T,
12716 .req_flow_ctrl = 0,
12717 .req_line_speed = 0,
12718 .speed_cap_mask = 0,
12721 .config_init = (config_init_t)elink_8481_config_init,
12722 .read_status = (read_status_t)elink_848xx_read_status,
12723 .link_reset = (link_reset_t)elink_8481_link_reset,
12724 .config_loopback = (config_loopback_t)NULL,
12725 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12726 .hw_reset = (hw_reset_t)elink_8481_hw_reset,
12727 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12728 .phy_specific_func = (phy_specific_func_t)NULL
12731 static const struct elink_phy phy_84823 = {
12732 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823,
12735 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12736 ELINK_FLAGS_REARM_LATCH_SIGNAL |
12737 ELINK_FLAGS_TX_ERROR_CHECK),
12738 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12739 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12741 .supported = (ELINK_SUPPORTED_10baseT_Half |
12742 ELINK_SUPPORTED_10baseT_Full |
12743 ELINK_SUPPORTED_100baseT_Half |
12744 ELINK_SUPPORTED_100baseT_Full |
12745 ELINK_SUPPORTED_1000baseT_Full |
12746 ELINK_SUPPORTED_10000baseT_Full |
12747 ELINK_SUPPORTED_TP |
12748 ELINK_SUPPORTED_Autoneg |
12749 ELINK_SUPPORTED_Pause |
12750 ELINK_SUPPORTED_Asym_Pause),
12751 .media_type = ELINK_ETH_PHY_BASE_T,
12753 .req_flow_ctrl = 0,
12754 .req_line_speed = 0,
12755 .speed_cap_mask = 0,
12758 .config_init = (config_init_t)elink_848x3_config_init,
12759 .read_status = (read_status_t)elink_848xx_read_status,
12760 .link_reset = (link_reset_t)elink_848x3_link_reset,
12761 .config_loopback = (config_loopback_t)NULL,
12762 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12763 .hw_reset = (hw_reset_t)NULL,
12764 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12765 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12768 static const struct elink_phy phy_84833 = {
12769 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833,
12772 .flags = (ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12773 ELINK_FLAGS_REARM_LATCH_SIGNAL |
12774 ELINK_FLAGS_TX_ERROR_CHECK |
12775 ELINK_FLAGS_TEMPERATURE),
12776 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12777 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12779 .supported = (ELINK_SUPPORTED_100baseT_Half |
12780 ELINK_SUPPORTED_100baseT_Full |
12781 ELINK_SUPPORTED_1000baseT_Full |
12782 ELINK_SUPPORTED_10000baseT_Full |
12783 ELINK_SUPPORTED_TP |
12784 ELINK_SUPPORTED_Autoneg |
12785 ELINK_SUPPORTED_Pause |
12786 ELINK_SUPPORTED_Asym_Pause),
12787 .media_type = ELINK_ETH_PHY_BASE_T,
12789 .req_flow_ctrl = 0,
12790 .req_line_speed = 0,
12791 .speed_cap_mask = 0,
12794 .config_init = (config_init_t)elink_848x3_config_init,
12795 .read_status = (read_status_t)elink_848xx_read_status,
12796 .link_reset = (link_reset_t)elink_848x3_link_reset,
12797 .config_loopback = (config_loopback_t)NULL,
12798 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12799 .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
12800 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12801 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12804 static const struct elink_phy phy_84834 = {
12805 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834,
12808 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12809 ELINK_FLAGS_REARM_LATCH_SIGNAL,
12810 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12811 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12813 .supported = (ELINK_SUPPORTED_100baseT_Half |
12814 ELINK_SUPPORTED_100baseT_Full |
12815 ELINK_SUPPORTED_1000baseT_Full |
12816 ELINK_SUPPORTED_10000baseT_Full |
12817 ELINK_SUPPORTED_TP |
12818 ELINK_SUPPORTED_Autoneg |
12819 ELINK_SUPPORTED_Pause |
12820 ELINK_SUPPORTED_Asym_Pause),
12821 .media_type = ELINK_ETH_PHY_BASE_T,
12823 .req_flow_ctrl = 0,
12824 .req_line_speed = 0,
12825 .speed_cap_mask = 0,
12828 .config_init = (config_init_t)elink_848x3_config_init,
12829 .read_status = (read_status_t)elink_848xx_read_status,
12830 .link_reset = (link_reset_t)elink_848x3_link_reset,
12831 .config_loopback = (config_loopback_t)NULL,
12832 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12833 .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
12834 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12835 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12838 static const struct elink_phy phy_84858 = {
12839 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858,
12842 .flags = ELINK_FLAGS_FAN_FAILURE_DET_REQ |
12843 ELINK_FLAGS_REARM_LATCH_SIGNAL,
12844 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12845 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12847 .supported = (ELINK_SUPPORTED_100baseT_Half |
12848 ELINK_SUPPORTED_100baseT_Full |
12849 ELINK_SUPPORTED_1000baseT_Full |
12850 ELINK_SUPPORTED_10000baseT_Full |
12851 ELINK_SUPPORTED_TP |
12852 ELINK_SUPPORTED_Autoneg |
12853 ELINK_SUPPORTED_Pause |
12854 ELINK_SUPPORTED_Asym_Pause),
12855 .media_type = ELINK_ETH_PHY_BASE_T,
12857 .req_flow_ctrl = 0,
12858 .req_line_speed = 0,
12859 .speed_cap_mask = 0,
12862 .config_init = (config_init_t)elink_848x3_config_init,
12863 .read_status = (read_status_t)elink_848xx_read_status,
12864 .link_reset = (link_reset_t)elink_848x3_link_reset,
12865 .config_loopback = (config_loopback_t)NULL,
12866 .format_fw_ver = (format_fw_ver_t)elink_848xx_format_ver,
12867 .hw_reset = (hw_reset_t)elink_84833_hw_reset_phy,
12868 .set_link_led = (set_link_led_t)elink_848xx_set_link_led,
12869 .phy_specific_func = (phy_specific_func_t)elink_848xx_specific_func
12873 static const struct elink_phy phy_54618se = {
12874 .type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE,
12877 .flags = ELINK_FLAGS_INIT_XGXS_FIRST,
12878 .rx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12879 .tx_preemphasis = {0xffff, 0xffff, 0xffff, 0xffff},
12881 .supported = (ELINK_SUPPORTED_10baseT_Half |
12882 ELINK_SUPPORTED_10baseT_Full |
12883 ELINK_SUPPORTED_100baseT_Half |
12884 ELINK_SUPPORTED_100baseT_Full |
12885 ELINK_SUPPORTED_1000baseT_Full |
12886 ELINK_SUPPORTED_TP |
12887 ELINK_SUPPORTED_Autoneg |
12888 ELINK_SUPPORTED_Pause |
12889 ELINK_SUPPORTED_Asym_Pause),
12890 .media_type = ELINK_ETH_PHY_BASE_T,
12892 .req_flow_ctrl = 0,
12893 .req_line_speed = 0,
12894 .speed_cap_mask = 0,
12895 /* req_duplex = */0,
12897 .config_init = (config_init_t)elink_54618se_config_init,
12898 .read_status = (read_status_t)elink_54618se_read_status,
12899 .link_reset = (link_reset_t)elink_54618se_link_reset,
12900 .config_loopback = (config_loopback_t)elink_54618se_config_loopback,
12901 .format_fw_ver = (format_fw_ver_t)NULL,
12902 .hw_reset = (hw_reset_t)NULL,
12903 .set_link_led = (set_link_led_t)elink_5461x_set_link_led,
12904 .phy_specific_func = (phy_specific_func_t)elink_54618se_specific_func
12906 /*****************************************************************/
12908 /* Populate the phy according. Main function: elink_populate_phy */
12910 /*****************************************************************/
12912 static void elink_populate_preemphasis(struct bxe_softc *sc, uint32_t shmem_base,
12913 struct elink_phy *phy, uint8_t port,
12916 /* Get the 4 lanes xgxs config rx and tx */
12917 uint32_t rx = 0, tx = 0, i;
12918 for (i = 0; i < 2; i++) {
12919 /* INT_PHY and ELINK_EXT_PHY1 share the same value location in
12920 * the shmem. When num_phys is greater than 1, than this value
12921 * applies only to ELINK_EXT_PHY1
12923 if (phy_index == ELINK_INT_PHY || phy_index == ELINK_EXT_PHY1) {
12924 rx = REG_RD(sc, shmem_base +
12925 offsetof(struct shmem_region,
12926 dev_info.port_hw_config[port].xgxs_config_rx[i<<1]));
12928 tx = REG_RD(sc, shmem_base +
12929 offsetof(struct shmem_region,
12930 dev_info.port_hw_config[port].xgxs_config_tx[i<<1]));
12932 rx = REG_RD(sc, shmem_base +
12933 offsetof(struct shmem_region,
12934 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12936 tx = REG_RD(sc, shmem_base +
12937 offsetof(struct shmem_region,
12938 dev_info.port_hw_config[port].xgxs_config2_rx[i<<1]));
12941 phy->rx_preemphasis[i << 1] = ((rx>>16) & 0xffff);
12942 phy->rx_preemphasis[(i << 1) + 1] = (rx & 0xffff);
12944 phy->tx_preemphasis[i << 1] = ((tx>>16) & 0xffff);
12945 phy->tx_preemphasis[(i << 1) + 1] = (tx & 0xffff);
12949 static uint32_t elink_get_ext_phy_config(struct bxe_softc *sc, uint32_t shmem_base,
12950 uint8_t phy_index, uint8_t port)
12952 uint32_t ext_phy_config = 0;
12953 switch (phy_index) {
12954 case ELINK_EXT_PHY1:
12955 ext_phy_config = REG_RD(sc, shmem_base +
12956 offsetof(struct shmem_region,
12957 dev_info.port_hw_config[port].external_phy_config));
12959 case ELINK_EXT_PHY2:
12960 ext_phy_config = REG_RD(sc, shmem_base +
12961 offsetof(struct shmem_region,
12962 dev_info.port_hw_config[port].external_phy_config2));
12965 ELINK_DEBUG_P1(sc, "Invalid phy_index %d\n", phy_index);
12966 return ELINK_STATUS_ERROR;
12969 return ext_phy_config;
12971 static elink_status_t elink_populate_int_phy(struct bxe_softc *sc, uint32_t shmem_base, uint8_t port,
12972 struct elink_phy *phy)
12976 uint32_t switch_cfg = (REG_RD(sc, shmem_base +
12977 offsetof(struct shmem_region,
12978 dev_info.port_feature_config[port].link_config)) &
12979 PORT_FEATURE_CONNECTED_SWITCH_MASK);
12980 chip_id = (REG_RD(sc, MISC_REG_CHIP_NUM) << 16) |
12981 ((REG_RD(sc, MISC_REG_CHIP_REV) & 0xf) << 12);
12983 ELINK_DEBUG_P1(sc, ":chip_id = 0x%x\n", chip_id);
12984 if (USES_WARPCORE(sc)) {
12985 uint32_t serdes_net_if;
12986 phy_addr = REG_RD(sc,
12987 MISC_REG_WC0_CTRL_PHY_ADDR);
12988 *phy = phy_warpcore;
12989 if (REG_RD(sc, MISC_REG_PORT4MODE_EN_OVWR) == 0x3)
12990 phy->flags |= ELINK_FLAGS_4_PORT_MODE;
12992 phy->flags &= ~ELINK_FLAGS_4_PORT_MODE;
12993 /* Check Dual mode */
12994 serdes_net_if = (REG_RD(sc, shmem_base +
12995 offsetof(struct shmem_region, dev_info.
12996 port_hw_config[port].default_cfg)) &
12997 PORT_HW_CFG_NET_SERDES_IF_MASK);
12998 /* Set the appropriate supported and flags indications per
12999 * interface type of the chip
13001 switch (serdes_net_if) {
13002 case PORT_HW_CFG_NET_SERDES_IF_SGMII:
13003 phy->supported &= (ELINK_SUPPORTED_10baseT_Half |
13004 ELINK_SUPPORTED_10baseT_Full |
13005 ELINK_SUPPORTED_100baseT_Half |
13006 ELINK_SUPPORTED_100baseT_Full |
13007 ELINK_SUPPORTED_1000baseT_Full |
13008 ELINK_SUPPORTED_FIBRE |
13009 ELINK_SUPPORTED_Autoneg |
13010 ELINK_SUPPORTED_Pause |
13011 ELINK_SUPPORTED_Asym_Pause);
13012 phy->media_type = ELINK_ETH_PHY_BASE_T;
13014 case PORT_HW_CFG_NET_SERDES_IF_XFI:
13015 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
13016 ELINK_SUPPORTED_10000baseT_Full |
13017 ELINK_SUPPORTED_FIBRE |
13018 ELINK_SUPPORTED_Pause |
13019 ELINK_SUPPORTED_Asym_Pause);
13020 phy->media_type = ELINK_ETH_PHY_XFP_FIBER;
13022 case PORT_HW_CFG_NET_SERDES_IF_SFI:
13023 phy->supported &= (ELINK_SUPPORTED_1000baseT_Full |
13024 ELINK_SUPPORTED_10000baseT_Full |
13025 ELINK_SUPPORTED_FIBRE |
13026 ELINK_SUPPORTED_Pause |
13027 ELINK_SUPPORTED_Asym_Pause);
13028 phy->media_type = ELINK_ETH_PHY_SFPP_10G_FIBER;
13030 case PORT_HW_CFG_NET_SERDES_IF_KR:
13031 phy->media_type = ELINK_ETH_PHY_KR;
13032 phy->supported &= (ELINK_SUPPORTED_1000baseKX_Full |
13033 ELINK_SUPPORTED_10000baseKR_Full |
13034 ELINK_SUPPORTED_FIBRE |
13035 ELINK_SUPPORTED_Autoneg |
13036 ELINK_SUPPORTED_Pause |
13037 ELINK_SUPPORTED_Asym_Pause);
13039 case PORT_HW_CFG_NET_SERDES_IF_DXGXS:
13040 phy->media_type = ELINK_ETH_PHY_KR;
13041 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
13042 phy->supported &= (ELINK_SUPPORTED_20000baseMLD2_Full |
13043 ELINK_SUPPORTED_FIBRE |
13044 ELINK_SUPPORTED_Pause |
13045 ELINK_SUPPORTED_Asym_Pause);
13047 case PORT_HW_CFG_NET_SERDES_IF_KR2:
13048 phy->media_type = ELINK_ETH_PHY_KR;
13049 phy->flags |= ELINK_FLAGS_WC_DUAL_MODE;
13050 phy->supported &= (ELINK_SUPPORTED_20000baseKR2_Full |
13051 ELINK_SUPPORTED_10000baseKR_Full |
13052 ELINK_SUPPORTED_1000baseKX_Full |
13053 ELINK_SUPPORTED_Autoneg |
13054 ELINK_SUPPORTED_FIBRE |
13055 ELINK_SUPPORTED_Pause |
13056 ELINK_SUPPORTED_Asym_Pause);
13057 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
13060 ELINK_DEBUG_P1(sc, "Unknown WC interface type 0x%x\n",
13065 /* Enable MDC/MDIO work-around for E3 A0 since free running MDC
13066 * was not set as expected. For B0, ECO will be enabled so there
13067 * won't be an issue there
13069 if (CHIP_REV(sc) == CHIP_REV_Ax)
13070 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA;
13072 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_B0;
13075 switch (switch_cfg) {
13076 case ELINK_SWITCH_CFG_1G:
13077 phy_addr = REG_RD(sc,
13078 NIG_REG_SERDES0_CTRL_PHY_ADDR +
13082 case ELINK_SWITCH_CFG_10G:
13083 phy_addr = REG_RD(sc,
13084 NIG_REG_XGXS0_CTRL_PHY_ADDR +
13089 ELINK_DEBUG_P0(sc, "Invalid switch_cfg\n");
13090 return ELINK_STATUS_ERROR;
13093 phy->addr = (uint8_t)phy_addr;
13094 phy->mdio_ctrl = elink_get_emac_base(sc,
13095 SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH,
13097 if (CHIP_IS_E2(sc))
13098 phy->def_md_devad = ELINK_E2_DEFAULT_PHY_DEV_ADDR;
13100 phy->def_md_devad = ELINK_DEFAULT_PHY_DEV_ADDR;
13102 ELINK_DEBUG_P3(sc, "Internal phy port=%d, addr=0x%x, mdio_ctl=0x%x\n",
13103 port, phy->addr, phy->mdio_ctrl);
13105 elink_populate_preemphasis(sc, shmem_base, phy, port, ELINK_INT_PHY);
13106 return ELINK_STATUS_OK;
13109 static elink_status_t elink_populate_ext_phy(struct bxe_softc *sc,
13111 uint32_t shmem_base,
13112 uint32_t shmem2_base,
13114 struct elink_phy *phy)
13116 uint32_t ext_phy_config, phy_type, config2;
13117 uint32_t mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_BOTH;
13118 ext_phy_config = elink_get_ext_phy_config(sc, shmem_base,
13120 phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
13121 /* Select the phy type */
13122 switch (phy_type) {
13123 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
13124 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_SWAPPED;
13127 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8705:
13130 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8706:
13133 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
13134 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
13137 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
13138 /* BCM8727_NOC => BCM8727 no over current */
13139 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
13141 phy->flags |= ELINK_FLAGS_NOC;
13143 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
13144 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
13145 mdc_mdio_access = SHARED_HW_CFG_MDC_MDIO_ACCESS1_EMAC1;
13148 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8481:
13151 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84823:
13154 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
13157 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
13160 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
13163 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54616:
13164 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE:
13165 *phy = phy_54618se;
13166 if (phy_type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM54618SE)
13167 phy->flags |= ELINK_FLAGS_EEE;
13169 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_SFX7101:
13172 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
13174 return ELINK_STATUS_ERROR;
13177 /* In case external PHY wasn't found */
13178 if ((phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_DIRECT) &&
13179 (phy_type != PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN))
13180 return ELINK_STATUS_ERROR;
13181 return ELINK_STATUS_OK;
13184 phy->addr = ELINK_XGXS_EXT_PHY_ADDR(ext_phy_config);
13185 elink_populate_preemphasis(sc, shmem_base, phy, port, phy_index);
13187 /* The shmem address of the phy version is located on different
13188 * structures. In case this structure is too old, do not set
13191 config2 = REG_RD(sc, shmem_base + offsetof(struct shmem_region,
13192 dev_info.shared_hw_config.config2));
13193 if (phy_index == ELINK_EXT_PHY1) {
13194 phy->ver_addr = shmem_base + offsetof(struct shmem_region,
13195 port_mb[port].ext_phy_fw_version);
13197 /* Check specific mdc mdio settings */
13198 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK)
13199 mdc_mdio_access = config2 &
13200 SHARED_HW_CFG_MDC_MDIO_ACCESS1_MASK;
13202 uint32_t size = REG_RD(sc, shmem2_base);
13205 offsetof(struct shmem2_region, ext_phy_fw_version2)) {
13206 phy->ver_addr = shmem2_base +
13207 offsetof(struct shmem2_region,
13208 ext_phy_fw_version2[port]);
13210 /* Check specific mdc mdio settings */
13211 if (config2 & SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK)
13212 mdc_mdio_access = (config2 &
13213 SHARED_HW_CFG_MDC_MDIO_ACCESS2_MASK) >>
13214 (SHARED_HW_CFG_MDC_MDIO_ACCESS2_SHIFT -
13215 SHARED_HW_CFG_MDC_MDIO_ACCESS1_SHIFT);
13217 phy->mdio_ctrl = elink_get_emac_base(sc, mdc_mdio_access, port);
13219 if (elink_is_8483x_8485x(phy) && (phy->ver_addr)) {
13220 /* Remove 100Mb link supported for BCM84833/4 when phy fw
13221 * version lower than or equal to 1.39
13223 uint32_t raw_ver = REG_RD(sc, phy->ver_addr);
13224 if (((raw_ver & 0x7F) <= 39) &&
13225 (((raw_ver & 0xF80) >> 7) <= 1))
13226 phy->supported &= ~(ELINK_SUPPORTED_100baseT_Half |
13227 ELINK_SUPPORTED_100baseT_Full);
13230 ELINK_DEBUG_P3(sc, "phy_type 0x%x port %d found in index %d\n",
13231 phy_type, port, phy_index);
13232 ELINK_DEBUG_P2(sc, " addr=0x%x, mdio_ctl=0x%x\n",
13233 phy->addr, phy->mdio_ctrl);
13234 return ELINK_STATUS_OK;
13237 static elink_status_t elink_populate_phy(struct bxe_softc *sc, uint8_t phy_index, uint32_t shmem_base,
13238 uint32_t shmem2_base, uint8_t port, struct elink_phy *phy)
13240 elink_status_t status = ELINK_STATUS_OK;
13241 phy->type = PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN;
13242 if (phy_index == ELINK_INT_PHY)
13243 return elink_populate_int_phy(sc, shmem_base, port, phy);
13244 status = elink_populate_ext_phy(sc, phy_index, shmem_base, shmem2_base,
13249 static void elink_phy_def_cfg(struct elink_params *params,
13250 struct elink_phy *phy,
13253 struct bxe_softc *sc = params->sc;
13254 uint32_t link_config;
13255 /* Populate the default phy configuration for MF mode */
13256 if (phy_index == ELINK_EXT_PHY2) {
13257 link_config = REG_RD(sc, params->shmem_base +
13258 offsetof(struct shmem_region, dev_info.
13259 port_feature_config[params->port].link_config2));
13260 phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
13261 offsetof(struct shmem_region,
13263 port_hw_config[params->port].speed_capability_mask2));
13265 link_config = REG_RD(sc, params->shmem_base +
13266 offsetof(struct shmem_region, dev_info.
13267 port_feature_config[params->port].link_config));
13268 phy->speed_cap_mask = REG_RD(sc, params->shmem_base +
13269 offsetof(struct shmem_region,
13271 port_hw_config[params->port].speed_capability_mask));
13274 "Default config phy idx %x cfg 0x%x speed_cap_mask 0x%x\n",
13275 phy_index, link_config, phy->speed_cap_mask);
13277 phy->req_duplex = DUPLEX_FULL;
13278 switch (link_config & PORT_FEATURE_LINK_SPEED_MASK) {
13279 case PORT_FEATURE_LINK_SPEED_10M_HALF:
13280 phy->req_duplex = DUPLEX_HALF;
13281 case PORT_FEATURE_LINK_SPEED_10M_FULL:
13282 phy->req_line_speed = ELINK_SPEED_10;
13284 case PORT_FEATURE_LINK_SPEED_100M_HALF:
13285 phy->req_duplex = DUPLEX_HALF;
13286 case PORT_FEATURE_LINK_SPEED_100M_FULL:
13287 phy->req_line_speed = ELINK_SPEED_100;
13289 case PORT_FEATURE_LINK_SPEED_1G:
13290 phy->req_line_speed = ELINK_SPEED_1000;
13292 case PORT_FEATURE_LINK_SPEED_2_5G:
13293 phy->req_line_speed = ELINK_SPEED_2500;
13295 case PORT_FEATURE_LINK_SPEED_10G_CX4:
13296 phy->req_line_speed = ELINK_SPEED_10000;
13299 phy->req_line_speed = ELINK_SPEED_AUTO_NEG;
13303 switch (link_config & PORT_FEATURE_FLOW_CONTROL_MASK) {
13304 case PORT_FEATURE_FLOW_CONTROL_AUTO:
13305 phy->req_flow_ctrl = ELINK_FLOW_CTRL_AUTO;
13307 case PORT_FEATURE_FLOW_CONTROL_TX:
13308 phy->req_flow_ctrl = ELINK_FLOW_CTRL_TX;
13310 case PORT_FEATURE_FLOW_CONTROL_RX:
13311 phy->req_flow_ctrl = ELINK_FLOW_CTRL_RX;
13313 case PORT_FEATURE_FLOW_CONTROL_BOTH:
13314 phy->req_flow_ctrl = ELINK_FLOW_CTRL_BOTH;
13317 phy->req_flow_ctrl = ELINK_FLOW_CTRL_NONE;
13322 uint32_t elink_phy_selection(struct elink_params *params)
13324 uint32_t phy_config_swapped, prio_cfg;
13325 uint32_t return_cfg = PORT_HW_CFG_PHY_SELECTION_HARDWARE_DEFAULT;
13327 phy_config_swapped = params->multi_phy_config &
13328 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
13330 prio_cfg = params->multi_phy_config &
13331 PORT_HW_CFG_PHY_SELECTION_MASK;
13333 if (phy_config_swapped) {
13334 switch (prio_cfg) {
13335 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY:
13336 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY;
13338 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY_PRIORITY:
13339 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY_PRIORITY;
13341 case PORT_HW_CFG_PHY_SELECTION_SECOND_PHY:
13342 return_cfg = PORT_HW_CFG_PHY_SELECTION_FIRST_PHY;
13344 case PORT_HW_CFG_PHY_SELECTION_FIRST_PHY:
13345 return_cfg = PORT_HW_CFG_PHY_SELECTION_SECOND_PHY;
13349 return_cfg = prio_cfg;
13354 elink_status_t elink_phy_probe(struct elink_params *params)
13356 uint8_t phy_index, actual_phy_idx;
13357 uint32_t phy_config_swapped, sync_offset, media_types;
13358 struct bxe_softc *sc = params->sc;
13359 struct elink_phy *phy;
13360 params->num_phys = 0;
13361 ELINK_DEBUG_P0(sc, "Begin phy probe\n");
13362 #ifdef ELINK_INCLUDE_EMUL
13363 if (CHIP_REV_IS_EMUL(sc))
13364 return ELINK_STATUS_OK;
13366 phy_config_swapped = params->multi_phy_config &
13367 PORT_HW_CFG_PHY_SWAPPED_ENABLED;
13369 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
13371 actual_phy_idx = phy_index;
13372 if (phy_config_swapped) {
13373 if (phy_index == ELINK_EXT_PHY1)
13374 actual_phy_idx = ELINK_EXT_PHY2;
13375 else if (phy_index == ELINK_EXT_PHY2)
13376 actual_phy_idx = ELINK_EXT_PHY1;
13378 ELINK_DEBUG_P3(sc, "phy_config_swapped %x, phy_index %x,"
13379 " actual_phy_idx %x\n", phy_config_swapped,
13380 phy_index, actual_phy_idx);
13381 phy = ¶ms->phy[actual_phy_idx];
13382 if (elink_populate_phy(sc, phy_index, params->shmem_base,
13383 params->shmem2_base, params->port,
13384 phy) != ELINK_STATUS_OK) {
13385 params->num_phys = 0;
13386 ELINK_DEBUG_P1(sc, "phy probe failed in phy index %d\n",
13388 for (phy_index = ELINK_INT_PHY;
13389 phy_index < ELINK_MAX_PHYS;
13392 return ELINK_STATUS_ERROR;
13394 if (phy->type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_NOT_CONN)
13397 if (params->feature_config_flags &
13398 ELINK_FEATURE_CONFIG_DISABLE_REMOTE_FAULT_DET)
13399 phy->flags &= ~ELINK_FLAGS_TX_ERROR_CHECK;
13401 if (!(params->feature_config_flags &
13402 ELINK_FEATURE_CONFIG_MT_SUPPORT))
13403 phy->flags |= ELINK_FLAGS_MDC_MDIO_WA_G;
13405 sync_offset = params->shmem_base +
13406 offsetof(struct shmem_region,
13407 dev_info.port_hw_config[params->port].media_type);
13408 media_types = REG_RD(sc, sync_offset);
13410 /* Update media type for non-PMF sync only for the first time
13411 * In case the media type changes afterwards, it will be updated
13412 * using the update_status function
13414 if ((media_types & (PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK <<
13415 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
13416 actual_phy_idx))) == 0) {
13417 media_types |= ((phy->media_type &
13418 PORT_HW_CFG_MEDIA_TYPE_PHY0_MASK) <<
13419 (PORT_HW_CFG_MEDIA_TYPE_PHY1_SHIFT *
13422 REG_WR(sc, sync_offset, media_types);
13424 elink_phy_def_cfg(params, phy, phy_index);
13425 params->num_phys++;
13428 ELINK_DEBUG_P1(sc, "End phy probe. #phys found %x\n", params->num_phys);
13429 return ELINK_STATUS_OK;
13432 #ifdef ELINK_INCLUDE_EMUL
13433 static elink_status_t elink_init_e3_emul_mac(struct elink_params *params,
13434 struct elink_vars *vars)
13436 struct bxe_softc *sc = params->sc;
13437 vars->line_speed = params->req_line_speed[0];
13438 /* In case link speed is auto, set speed the highest as possible */
13439 if (params->req_line_speed[0] == ELINK_SPEED_AUTO_NEG) {
13440 if (params->feature_config_flags &
13441 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC)
13442 vars->line_speed = ELINK_SPEED_2500;
13443 else if (elink_is_4_port_mode(sc))
13444 vars->line_speed = ELINK_SPEED_10000;
13446 vars->line_speed = ELINK_SPEED_20000;
13448 if (vars->line_speed < ELINK_SPEED_10000) {
13449 if ((params->feature_config_flags &
13450 ELINK_FEATURE_CONFIG_EMUL_DISABLE_UMAC)) {
13451 ELINK_DEBUG_P1(sc, "Invalid line speed %d while UMAC is"
13452 " disabled!\n", params->req_line_speed[0]);
13453 return ELINK_STATUS_ERROR;
13455 switch (vars->line_speed) {
13456 case ELINK_SPEED_10:
13457 vars->link_status = ELINK_LINK_10TFD;
13459 case ELINK_SPEED_100:
13460 vars->link_status = ELINK_LINK_100TXFD;
13462 case ELINK_SPEED_1000:
13463 vars->link_status = ELINK_LINK_1000TFD;
13465 case ELINK_SPEED_2500:
13466 vars->link_status = ELINK_LINK_2500TFD;
13469 ELINK_DEBUG_P1(sc, "Invalid line speed %d for UMAC\n",
13471 return ELINK_STATUS_ERROR;
13473 vars->link_status |= LINK_STATUS_LINK_UP;
13475 if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
13476 elink_umac_enable(params, vars, 1);
13478 elink_umac_enable(params, vars, 0);
13480 /* Link speed >= 10000 requires XMAC enabled */
13481 if (params->feature_config_flags &
13482 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC) {
13483 ELINK_DEBUG_P1(sc, "Invalid line speed %d while XMAC is"
13484 " disabled!\n", params->req_line_speed[0]);
13485 return ELINK_STATUS_ERROR;
13487 /* Check link speed */
13488 switch (vars->line_speed) {
13489 case ELINK_SPEED_10000:
13490 vars->link_status = ELINK_LINK_10GTFD;
13492 case ELINK_SPEED_20000:
13493 vars->link_status = ELINK_LINK_20GTFD;
13496 ELINK_DEBUG_P1(sc, "Invalid line speed %d for XMAC\n",
13498 return ELINK_STATUS_ERROR;
13500 vars->link_status |= LINK_STATUS_LINK_UP;
13501 if (params->loopback_mode == ELINK_LOOPBACK_XMAC)
13502 elink_xmac_enable(params, vars, 1);
13504 elink_xmac_enable(params, vars, 0);
13506 return ELINK_STATUS_OK;
13509 static elink_status_t elink_init_emul(struct elink_params *params,
13510 struct elink_vars *vars)
13512 struct bxe_softc *sc = params->sc;
13513 if (CHIP_IS_E3(sc)) {
13514 if (elink_init_e3_emul_mac(params, vars) !=
13516 return ELINK_STATUS_ERROR;
13518 if (params->feature_config_flags &
13519 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC) {
13520 vars->line_speed = ELINK_SPEED_1000;
13521 vars->link_status = (LINK_STATUS_LINK_UP |
13522 ELINK_LINK_1000XFD);
13523 if (params->loopback_mode ==
13524 ELINK_LOOPBACK_EMAC)
13525 elink_emac_enable(params, vars, 1);
13527 elink_emac_enable(params, vars, 0);
13529 vars->line_speed = ELINK_SPEED_10000;
13530 vars->link_status = (LINK_STATUS_LINK_UP |
13531 ELINK_LINK_10GTFD);
13532 if (params->loopback_mode ==
13533 ELINK_LOOPBACK_BMAC)
13534 elink_bmac_enable(params, vars, 1, 1);
13536 elink_bmac_enable(params, vars, 0, 1);
13540 vars->duplex = DUPLEX_FULL;
13541 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13543 if (CHIP_IS_E1x(sc))
13544 elink_pbf_update(params, vars->flow_ctrl,
13546 /* Disable drain */
13547 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13549 /* update shared memory */
13550 elink_update_mng(params, vars->link_status);
13551 return ELINK_STATUS_OK;
13554 #ifdef ELINK_INCLUDE_FPGA
13555 static elink_status_t elink_init_fpga(struct elink_params *params,
13556 struct elink_vars *vars)
13558 /* Enable on E1.5 FPGA */
13559 struct bxe_softc *sc = params->sc;
13560 vars->duplex = DUPLEX_FULL;
13561 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13562 if (!(CHIP_IS_E1(sc))) {
13563 vars->flow_ctrl = (ELINK_FLOW_CTRL_TX |
13564 ELINK_FLOW_CTRL_RX);
13565 vars->link_status |= (LINK_STATUS_TX_FLOW_CONTROL_ENABLED |
13566 LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
13568 if (CHIP_IS_E3(sc)) {
13569 vars->line_speed = params->req_line_speed[0];
13570 switch (vars->line_speed) {
13571 case ELINK_SPEED_AUTO_NEG:
13572 vars->line_speed = ELINK_SPEED_2500;
13573 case ELINK_SPEED_2500:
13574 vars->link_status = ELINK_LINK_2500TFD;
13576 case ELINK_SPEED_1000:
13577 vars->link_status = ELINK_LINK_1000XFD;
13579 case ELINK_SPEED_100:
13580 vars->link_status = ELINK_LINK_100TXFD;
13582 case ELINK_SPEED_10:
13583 vars->link_status = ELINK_LINK_10TFD;
13586 ELINK_DEBUG_P1(sc, "Invalid link speed %d\n",
13587 params->req_line_speed[0]);
13588 return ELINK_STATUS_ERROR;
13590 vars->link_status |= LINK_STATUS_LINK_UP;
13591 if (params->loopback_mode == ELINK_LOOPBACK_UMAC)
13592 elink_umac_enable(params, vars, 1);
13594 elink_umac_enable(params, vars, 0);
13596 vars->line_speed = ELINK_SPEED_10000;
13597 vars->link_status = (LINK_STATUS_LINK_UP | ELINK_LINK_10GTFD);
13598 if (params->loopback_mode == ELINK_LOOPBACK_EMAC)
13599 elink_emac_enable(params, vars, 1);
13601 elink_emac_enable(params, vars, 0);
13605 if (CHIP_IS_E1x(sc))
13606 elink_pbf_update(params, vars->flow_ctrl,
13608 /* Disable drain */
13609 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13611 /* Update shared memory */
13612 elink_update_mng(params, vars->link_status);
13613 return ELINK_STATUS_OK;
13616 static void elink_init_bmac_loopback(struct elink_params *params,
13617 struct elink_vars *vars)
13619 struct bxe_softc *sc = params->sc;
13621 vars->line_speed = ELINK_SPEED_10000;
13622 vars->duplex = DUPLEX_FULL;
13623 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13624 vars->mac_type = ELINK_MAC_TYPE_BMAC;
13626 vars->phy_flags = PHY_XGXS_FLAG;
13628 elink_xgxs_deassert(params);
13630 /* Set bmac loopback */
13631 elink_bmac_enable(params, vars, 1, 1);
13633 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13636 static void elink_init_emac_loopback(struct elink_params *params,
13637 struct elink_vars *vars)
13639 struct bxe_softc *sc = params->sc;
13641 vars->line_speed = ELINK_SPEED_1000;
13642 vars->duplex = DUPLEX_FULL;
13643 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13644 vars->mac_type = ELINK_MAC_TYPE_EMAC;
13646 vars->phy_flags = PHY_XGXS_FLAG;
13648 elink_xgxs_deassert(params);
13649 /* Set bmac loopback */
13650 elink_emac_enable(params, vars, 1);
13651 elink_emac_program(params, vars);
13652 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13655 static void elink_init_xmac_loopback(struct elink_params *params,
13656 struct elink_vars *vars)
13658 struct bxe_softc *sc = params->sc;
13660 if (!params->req_line_speed[0])
13661 vars->line_speed = ELINK_SPEED_10000;
13663 vars->line_speed = params->req_line_speed[0];
13664 vars->duplex = DUPLEX_FULL;
13665 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13666 vars->mac_type = ELINK_MAC_TYPE_XMAC;
13667 vars->phy_flags = PHY_XGXS_FLAG;
13668 /* Set WC to loopback mode since link is required to provide clock
13669 * to the XMAC in 20G mode
13671 elink_set_aer_mmd(params, ¶ms->phy[0]);
13672 elink_warpcore_reset_lane(sc, ¶ms->phy[0], 0);
13673 params->phy[ELINK_INT_PHY].config_loopback(
13674 ¶ms->phy[ELINK_INT_PHY],
13677 elink_xmac_enable(params, vars, 1);
13678 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13681 static void elink_init_umac_loopback(struct elink_params *params,
13682 struct elink_vars *vars)
13684 struct bxe_softc *sc = params->sc;
13686 vars->line_speed = ELINK_SPEED_1000;
13687 vars->duplex = DUPLEX_FULL;
13688 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13689 vars->mac_type = ELINK_MAC_TYPE_UMAC;
13690 vars->phy_flags = PHY_XGXS_FLAG;
13691 elink_umac_enable(params, vars, 1);
13693 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13696 static void elink_init_xgxs_loopback(struct elink_params *params,
13697 struct elink_vars *vars)
13699 struct bxe_softc *sc = params->sc;
13700 struct elink_phy *int_phy = ¶ms->phy[ELINK_INT_PHY];
13702 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13703 vars->duplex = DUPLEX_FULL;
13704 if (params->req_line_speed[0] == ELINK_SPEED_1000)
13705 vars->line_speed = ELINK_SPEED_1000;
13706 else if ((params->req_line_speed[0] == ELINK_SPEED_20000) ||
13707 (int_phy->flags & ELINK_FLAGS_WC_DUAL_MODE))
13708 vars->line_speed = ELINK_SPEED_20000;
13710 vars->line_speed = ELINK_SPEED_10000;
13712 if (!USES_WARPCORE(sc))
13713 elink_xgxs_deassert(params);
13714 elink_link_initialize(params, vars);
13716 if (params->req_line_speed[0] == ELINK_SPEED_1000) {
13717 if (USES_WARPCORE(sc))
13718 elink_umac_enable(params, vars, 0);
13720 elink_emac_program(params, vars);
13721 elink_emac_enable(params, vars, 0);
13724 if (USES_WARPCORE(sc))
13725 elink_xmac_enable(params, vars, 0);
13727 elink_bmac_enable(params, vars, 0, 1);
13730 if (params->loopback_mode == ELINK_LOOPBACK_XGXS) {
13731 /* Set 10G XGXS loopback */
13732 int_phy->config_loopback(int_phy, params);
13734 /* Set external phy loopback */
13736 for (phy_index = ELINK_EXT_PHY1;
13737 phy_index < params->num_phys; phy_index++)
13738 if (params->phy[phy_index].config_loopback)
13739 params->phy[phy_index].config_loopback(
13740 ¶ms->phy[phy_index],
13743 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13745 elink_set_led(params, vars, ELINK_LED_MODE_OPER, vars->line_speed);
13748 void elink_set_rx_filter(struct elink_params *params, uint8_t en)
13750 struct bxe_softc *sc = params->sc;
13751 uint8_t val = en * 0x1F;
13753 /* Open / close the gate between the NIG and the BRB */
13754 if (!CHIP_IS_E1x(sc))
13756 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK + params->port*4, val);
13758 if (!CHIP_IS_E1(sc)) {
13759 REG_WR(sc, NIG_REG_LLH0_BRB1_DRV_MASK_MF + params->port*4,
13763 REG_WR(sc, (params->port ? NIG_REG_LLH1_BRB1_NOT_MCP :
13764 NIG_REG_LLH0_BRB1_NOT_MCP), en);
13766 static elink_status_t elink_avoid_link_flap(struct elink_params *params,
13767 struct elink_vars *vars)
13770 uint32_t dont_clear_stat, lfa_sts;
13771 struct bxe_softc *sc = params->sc;
13773 elink_set_mdio_emac_per_phy(sc, params);
13774 /* Sync the link parameters */
13775 elink_link_status_update(params, vars);
13778 * The module verification was already done by previous link owner,
13779 * so this call is meant only to get warning message
13782 for (phy_idx = ELINK_INT_PHY; phy_idx < params->num_phys; phy_idx++) {
13783 struct elink_phy *phy = ¶ms->phy[phy_idx];
13784 if (phy->phy_specific_func) {
13785 ELINK_DEBUG_P0(sc, "Calling PHY specific func\n");
13786 phy->phy_specific_func(phy, params, ELINK_PHY_INIT);
13788 if ((phy->media_type == ELINK_ETH_PHY_SFPP_10G_FIBER) ||
13789 (phy->media_type == ELINK_ETH_PHY_SFP_1G_FIBER) ||
13790 (phy->media_type == ELINK_ETH_PHY_DA_TWINAX))
13791 elink_verify_sfp_module(phy, params);
13793 lfa_sts = REG_RD(sc, params->lfa_base +
13794 offsetof(struct shmem_lfa,
13797 dont_clear_stat = lfa_sts & SHMEM_LFA_DONT_CLEAR_STAT;
13799 /* Re-enable the NIG/MAC */
13800 if (CHIP_IS_E3(sc)) {
13801 if (!dont_clear_stat) {
13802 REG_WR(sc, GRCBASE_MISC +
13803 MISC_REGISTERS_RESET_REG_2_CLEAR,
13804 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
13806 REG_WR(sc, GRCBASE_MISC +
13807 MISC_REGISTERS_RESET_REG_2_SET,
13808 (MISC_REGISTERS_RESET_REG_2_MSTAT0 <<
13811 if (vars->line_speed < ELINK_SPEED_10000)
13812 elink_umac_enable(params, vars, 0);
13814 elink_xmac_enable(params, vars, 0);
13816 if (vars->line_speed < ELINK_SPEED_10000)
13817 elink_emac_enable(params, vars, 0);
13819 elink_bmac_enable(params, vars, 0, !dont_clear_stat);
13822 /* Increment LFA count */
13823 lfa_sts = ((lfa_sts & ~LINK_FLAP_AVOIDANCE_COUNT_MASK) |
13824 (((((lfa_sts & LINK_FLAP_AVOIDANCE_COUNT_MASK) >>
13825 LINK_FLAP_AVOIDANCE_COUNT_OFFSET) + 1) & 0xff)
13826 << LINK_FLAP_AVOIDANCE_COUNT_OFFSET));
13827 /* Clear link flap reason */
13828 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
13830 REG_WR(sc, params->lfa_base +
13831 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
13833 /* Disable NIG DRAIN */
13834 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
13836 /* Enable interrupts */
13837 elink_link_int_enable(params);
13838 return ELINK_STATUS_OK;
13841 static void elink_cannot_avoid_link_flap(struct elink_params *params,
13842 struct elink_vars *vars,
13845 uint32_t lfa_sts, cfg_idx, tmp_val;
13846 struct bxe_softc *sc = params->sc;
13848 elink_link_reset(params, vars, 1);
13850 if (!params->lfa_base)
13852 /* Store the new link parameters */
13853 REG_WR(sc, params->lfa_base +
13854 offsetof(struct shmem_lfa, req_duplex),
13855 params->req_duplex[0] | (params->req_duplex[1] << 16));
13857 REG_WR(sc, params->lfa_base +
13858 offsetof(struct shmem_lfa, req_flow_ctrl),
13859 params->req_flow_ctrl[0] | (params->req_flow_ctrl[1] << 16));
13861 REG_WR(sc, params->lfa_base +
13862 offsetof(struct shmem_lfa, req_line_speed),
13863 params->req_line_speed[0] | (params->req_line_speed[1] << 16));
13865 for (cfg_idx = 0; cfg_idx < SHMEM_LINK_CONFIG_SIZE; cfg_idx++) {
13866 REG_WR(sc, params->lfa_base +
13867 offsetof(struct shmem_lfa,
13868 speed_cap_mask[cfg_idx]),
13869 params->speed_cap_mask[cfg_idx]);
13872 tmp_val = REG_RD(sc, params->lfa_base +
13873 offsetof(struct shmem_lfa, additional_config));
13874 tmp_val &= ~REQ_FC_AUTO_ADV_MASK;
13875 tmp_val |= params->req_fc_auto_adv;
13877 REG_WR(sc, params->lfa_base +
13878 offsetof(struct shmem_lfa, additional_config), tmp_val);
13880 lfa_sts = REG_RD(sc, params->lfa_base +
13881 offsetof(struct shmem_lfa, lfa_sts));
13883 /* Clear the "Don't Clear Statistics" bit, and set reason */
13884 lfa_sts &= ~SHMEM_LFA_DONT_CLEAR_STAT;
13886 /* Set link flap reason */
13887 lfa_sts &= ~LFA_LINK_FLAP_REASON_MASK;
13888 lfa_sts |= ((lfa_status & LFA_LINK_FLAP_REASON_MASK) <<
13889 LFA_LINK_FLAP_REASON_OFFSET);
13891 /* Increment link flap counter */
13892 lfa_sts = ((lfa_sts & ~LINK_FLAP_COUNT_MASK) |
13893 (((((lfa_sts & LINK_FLAP_COUNT_MASK) >>
13894 LINK_FLAP_COUNT_OFFSET) + 1) & 0xff)
13895 << LINK_FLAP_COUNT_OFFSET));
13896 REG_WR(sc, params->lfa_base +
13897 offsetof(struct shmem_lfa, lfa_sts), lfa_sts);
13898 /* Proceed with regular link initialization */
13901 elink_status_t elink_phy_init(struct elink_params *params, struct elink_vars *vars)
13904 struct bxe_softc *sc = params->sc;
13905 ELINK_DEBUG_P0(sc, "Phy Initialization started\n");
13906 ELINK_DEBUG_P2(sc, "(1) req_speed %d, req_flowctrl %d\n",
13907 params->req_line_speed[0], params->req_flow_ctrl[0]);
13908 ELINK_DEBUG_P2(sc, "(2) req_speed %d, req_flowctrl %d\n",
13909 params->req_line_speed[1], params->req_flow_ctrl[1]);
13910 ELINK_DEBUG_P1(sc, "req_adv_flow_ctrl 0x%x\n", params->req_fc_auto_adv);
13911 vars->link_status = 0;
13912 vars->phy_link_up = 0;
13914 vars->line_speed = 0;
13915 vars->duplex = DUPLEX_FULL;
13916 vars->flow_ctrl = ELINK_FLOW_CTRL_NONE;
13917 vars->mac_type = ELINK_MAC_TYPE_NONE;
13918 vars->phy_flags = 0;
13919 vars->check_kr2_recovery_cnt = 0;
13920 params->link_flags = ELINK_PHY_INITIALIZED;
13921 /* Driver opens NIG-BRB filters */
13922 elink_set_rx_filter(params, 1);
13923 elink_chng_link_count(params, 1);
13924 /* Check if link flap can be avoided */
13925 lfa_status = elink_check_lfa(params);
13927 if (lfa_status == 0) {
13928 ELINK_DEBUG_P0(sc, "Link Flap Avoidance in progress\n");
13929 return elink_avoid_link_flap(params, vars);
13932 ELINK_DEBUG_P1(sc, "Cannot avoid link flap lfa_sta=0x%x\n",
13934 elink_cannot_avoid_link_flap(params, vars, lfa_status);
13936 /* Disable attentions */
13937 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
13938 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
13939 ELINK_NIG_MASK_XGXS0_LINK10G |
13940 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
13941 ELINK_NIG_MASK_MI_INT));
13942 #ifdef ELINK_INCLUDE_EMUL
13943 if (!(params->feature_config_flags &
13944 ELINK_FEATURE_CONFIG_EMUL_DISABLE_EMAC))
13947 elink_emac_init(params, vars);
13949 if (params->feature_config_flags & ELINK_FEATURE_CONFIG_PFC_ENABLED)
13950 vars->link_status |= LINK_STATUS_PFC_ENABLED;
13952 if ((params->num_phys == 0) &&
13953 !CHIP_REV_IS_SLOW(sc)) {
13954 ELINK_DEBUG_P0(sc, "No phy found for initialization !!\n");
13955 return ELINK_STATUS_ERROR;
13957 set_phy_vars(params, vars);
13959 ELINK_DEBUG_P1(sc, "Num of phys on board: %d\n", params->num_phys);
13960 #ifdef ELINK_INCLUDE_FPGA
13961 if (CHIP_REV_IS_FPGA(sc)) {
13962 return elink_init_fpga(params, vars);
13965 #ifdef ELINK_INCLUDE_EMUL
13966 if (CHIP_REV_IS_EMUL(sc)) {
13967 return elink_init_emul(params, vars);
13970 switch (params->loopback_mode) {
13971 case ELINK_LOOPBACK_BMAC:
13972 elink_init_bmac_loopback(params, vars);
13974 case ELINK_LOOPBACK_EMAC:
13975 elink_init_emac_loopback(params, vars);
13977 case ELINK_LOOPBACK_XMAC:
13978 elink_init_xmac_loopback(params, vars);
13980 case ELINK_LOOPBACK_UMAC:
13981 elink_init_umac_loopback(params, vars);
13983 case ELINK_LOOPBACK_XGXS:
13984 case ELINK_LOOPBACK_EXT_PHY:
13985 elink_init_xgxs_loopback(params, vars);
13988 if (!CHIP_IS_E3(sc)) {
13989 if (params->switch_cfg == ELINK_SWITCH_CFG_10G)
13990 elink_xgxs_deassert(params);
13992 elink_serdes_deassert(sc, params->port);
13994 elink_link_initialize(params, vars);
13996 elink_link_int_enable(params);
13999 elink_update_mng(params, vars->link_status);
14001 elink_update_mng_eee(params, vars->eee_status);
14002 return ELINK_STATUS_OK;
14005 elink_status_t elink_link_reset(struct elink_params *params, struct elink_vars *vars,
14006 uint8_t reset_ext_phy)
14008 struct bxe_softc *sc = params->sc;
14009 uint8_t phy_index, port = params->port, clear_latch_ind = 0;
14010 ELINK_DEBUG_P1(sc, "Resetting the link of port %d\n", port);
14011 /* Disable attentions */
14012 vars->link_status = 0;
14013 elink_chng_link_count(params, 1);
14014 elink_update_mng(params, vars->link_status);
14015 vars->eee_status &= ~(SHMEM_EEE_LP_ADV_STATUS_MASK |
14016 SHMEM_EEE_ACTIVE_BIT);
14017 elink_update_mng_eee(params, vars->eee_status);
14018 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + port*4,
14019 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
14020 ELINK_NIG_MASK_XGXS0_LINK10G |
14021 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
14022 ELINK_NIG_MASK_MI_INT));
14024 /* Activate nig drain */
14025 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + port*4, 1);
14027 /* Disable nig egress interface */
14028 if (!CHIP_IS_E3(sc)) {
14029 REG_WR(sc, NIG_REG_BMAC0_OUT_EN + port*4, 0);
14030 REG_WR(sc, NIG_REG_EGRESS_EMAC0_OUT_EN + port*4, 0);
14033 #ifdef ELINK_INCLUDE_EMUL
14034 /* Stop BigMac rx */
14035 if (!(params->feature_config_flags &
14036 ELINK_FEATURE_CONFIG_EMUL_DISABLE_BMAC))
14038 if (!CHIP_IS_E3(sc))
14039 elink_set_bmac_rx(sc, params->chip_id, port, 0);
14040 #ifdef ELINK_INCLUDE_EMUL
14041 /* Stop XMAC/UMAC rx */
14042 if (!(params->feature_config_flags &
14043 ELINK_FEATURE_CONFIG_EMUL_DISABLE_XMAC))
14045 if (CHIP_IS_E3(sc) &&
14046 !CHIP_REV_IS_FPGA(sc)) {
14047 elink_set_xmac_rxtx(params, 0);
14048 elink_set_umac_rxtx(params, 0);
14051 if (!CHIP_IS_E3(sc))
14052 REG_WR(sc, NIG_REG_NIG_EMAC0_EN + port*4, 0);
14055 /* The PHY reset is controlled by GPIO 1
14056 * Hold it as vars low
14058 /* Clear link led */
14059 elink_set_mdio_emac_per_phy(sc, params);
14060 elink_set_led(params, vars, ELINK_LED_MODE_OFF, 0);
14062 if (reset_ext_phy && (!CHIP_REV_IS_SLOW(sc))) {
14063 for (phy_index = ELINK_EXT_PHY1; phy_index < params->num_phys;
14065 if (params->phy[phy_index].link_reset) {
14066 elink_set_aer_mmd(params,
14067 ¶ms->phy[phy_index]);
14068 params->phy[phy_index].link_reset(
14069 ¶ms->phy[phy_index],
14072 if (params->phy[phy_index].flags &
14073 ELINK_FLAGS_REARM_LATCH_SIGNAL)
14074 clear_latch_ind = 1;
14078 if (clear_latch_ind) {
14079 /* Clear latching indication */
14080 elink_rearm_latch_signal(sc, port, 0);
14081 elink_bits_dis(sc, NIG_REG_LATCH_BC_0 + port*4,
14082 1 << ELINK_NIG_LATCH_BC_ENABLE_MI_INT);
14084 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
14085 if (!CHIP_REV_IS_SLOW(sc))
14087 if (params->phy[ELINK_INT_PHY].link_reset)
14088 params->phy[ELINK_INT_PHY].link_reset(
14089 ¶ms->phy[ELINK_INT_PHY], params);
14091 /* Disable nig ingress interface */
14092 if (!CHIP_IS_E3(sc)) {
14094 REG_WR(sc, GRCBASE_MISC + MISC_REGISTERS_RESET_REG_2_CLEAR,
14095 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << port));
14096 REG_WR(sc, NIG_REG_BMAC0_IN_EN + port*4, 0);
14097 REG_WR(sc, NIG_REG_EMAC0_IN_EN + port*4, 0);
14099 uint32_t xmac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
14100 elink_set_xumac_nig(params, 0, 0);
14101 if (REG_RD(sc, MISC_REG_RESET_REG_2) &
14102 MISC_REGISTERS_RESET_REG_2_XMAC)
14103 REG_WR(sc, xmac_base + XMAC_REG_CTRL,
14104 XMAC_CTRL_REG_SOFT_RESET);
14107 vars->phy_flags = 0;
14108 return ELINK_STATUS_OK;
14110 elink_status_t elink_lfa_reset(struct elink_params *params,
14111 struct elink_vars *vars)
14113 struct bxe_softc *sc = params->sc;
14115 vars->phy_flags = 0;
14116 params->link_flags &= ~ELINK_PHY_INITIALIZED;
14117 if (!params->lfa_base)
14118 return elink_link_reset(params, vars, 1);
14120 * Activate NIG drain so that during this time the device won't send
14121 * anything while it is unable to response.
14123 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
14126 * Close gracefully the gate from BMAC to NIG such that no half packets
14129 if (!CHIP_IS_E3(sc))
14130 elink_set_bmac_rx(sc, params->chip_id, params->port, 0);
14132 if (CHIP_IS_E3(sc)) {
14133 elink_set_xmac_rxtx(params, 0);
14134 elink_set_umac_rxtx(params, 0);
14136 /* Wait 10ms for the pipe to clean up*/
14139 /* Clean the NIG-BRB using the network filters in a way that will
14140 * not cut a packet in the middle.
14142 elink_set_rx_filter(params, 0);
14145 * Re-open the gate between the BMAC and the NIG, after verifying the
14146 * gate to the BRB is closed, otherwise packets may arrive to the
14147 * firmware before driver had initialized it. The target is to achieve
14148 * minimum management protocol down time.
14150 if (!CHIP_IS_E3(sc))
14151 elink_set_bmac_rx(sc, params->chip_id, params->port, 1);
14153 if (CHIP_IS_E3(sc)) {
14154 elink_set_xmac_rxtx(params, 1);
14155 elink_set_umac_rxtx(params, 1);
14157 /* Disable NIG drain */
14158 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
14159 return ELINK_STATUS_OK;
14162 /****************************************************************************/
14163 /* Common function */
14164 /****************************************************************************/
14165 static elink_status_t elink_8073_common_init_phy(struct bxe_softc *sc,
14166 uint32_t shmem_base_path[],
14167 uint32_t shmem2_base_path[], uint8_t phy_index,
14170 struct elink_phy phy[PORT_MAX];
14171 struct elink_phy *phy_blk[PORT_MAX];
14174 int8_t port_of_path = 0;
14175 uint32_t swap_val, swap_override;
14176 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
14177 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
14178 port ^= (swap_val && swap_override);
14179 elink_ext_phy_hw_reset(sc, port);
14180 /* PART1 - Reset both phys */
14181 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14182 uint32_t shmem_base, shmem2_base;
14183 /* In E2, same phy is using for port0 of the two paths */
14184 if (CHIP_IS_E1x(sc)) {
14185 shmem_base = shmem_base_path[0];
14186 shmem2_base = shmem2_base_path[0];
14187 port_of_path = port;
14189 shmem_base = shmem_base_path[port];
14190 shmem2_base = shmem2_base_path[port];
14194 /* Extract the ext phy address for the port */
14195 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14196 port_of_path, &phy[port]) !=
14198 ELINK_DEBUG_P0(sc, "populate_phy failed\n");
14199 return ELINK_STATUS_ERROR;
14201 /* Disable attentions */
14202 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
14204 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
14205 ELINK_NIG_MASK_XGXS0_LINK10G |
14206 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
14207 ELINK_NIG_MASK_MI_INT));
14209 /* Need to take the phy out of low power mode in order
14210 * to write to access its registers
14212 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
14213 MISC_REGISTERS_GPIO_OUTPUT_HIGH,
14216 /* Reset the phy */
14217 elink_cl45_write(sc, &phy[port],
14223 /* Add delay of 150ms after reset */
14226 if (phy[PORT_0].addr & 0x1) {
14227 phy_blk[PORT_0] = &(phy[PORT_1]);
14228 phy_blk[PORT_1] = &(phy[PORT_0]);
14230 phy_blk[PORT_0] = &(phy[PORT_0]);
14231 phy_blk[PORT_1] = &(phy[PORT_1]);
14234 /* PART2 - Download firmware to both phys */
14235 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14236 if (CHIP_IS_E1x(sc))
14237 port_of_path = port;
14241 ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n",
14242 phy_blk[port]->addr);
14243 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
14245 return ELINK_STATUS_ERROR;
14247 /* Only set bit 10 = 1 (Tx power down) */
14248 elink_cl45_read(sc, phy_blk[port],
14250 MDIO_PMA_REG_TX_POWER_DOWN, &val);
14252 /* Phase1 of TX_POWER_DOWN reset */
14253 elink_cl45_write(sc, phy_blk[port],
14255 MDIO_PMA_REG_TX_POWER_DOWN,
14259 /* Toggle Transmitter: Power down and then up with 600ms delay
14264 /* PART3 - complete TX_POWER_DOWN process, and set GPIO2 back to low */
14265 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14266 /* Phase2 of POWER_DOWN_RESET */
14267 /* Release bit 10 (Release Tx power down) */
14268 elink_cl45_read(sc, phy_blk[port],
14270 MDIO_PMA_REG_TX_POWER_DOWN, &val);
14272 elink_cl45_write(sc, phy_blk[port],
14274 MDIO_PMA_REG_TX_POWER_DOWN, (val & (~(1<<10))));
14277 /* Read modify write the SPI-ROM version select register */
14278 elink_cl45_read(sc, phy_blk[port],
14280 MDIO_PMA_REG_EDC_FFE_MAIN, &val);
14281 elink_cl45_write(sc, phy_blk[port],
14283 MDIO_PMA_REG_EDC_FFE_MAIN, (val | (1<<12)));
14285 /* set GPIO2 back to LOW */
14286 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_2,
14287 MISC_REGISTERS_GPIO_OUTPUT_LOW, port);
14289 return ELINK_STATUS_OK;
14291 static elink_status_t elink_8726_common_init_phy(struct bxe_softc *sc,
14292 uint32_t shmem_base_path[],
14293 uint32_t shmem2_base_path[], uint8_t phy_index,
14298 struct elink_phy phy;
14299 /* Use port1 because of the static port-swap */
14300 /* Enable the module detection interrupt */
14301 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
14302 val |= ((1<<MISC_REGISTERS_GPIO_3)|
14303 (1<<(MISC_REGISTERS_GPIO_3 + MISC_REGISTERS_GPIO_PORT_SHIFT)));
14304 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);
14306 elink_ext_phy_hw_reset(sc, 0);
14308 for (port = 0; port < PORT_MAX; port++) {
14309 uint32_t shmem_base, shmem2_base;
14311 /* In E2, same phy is using for port0 of the two paths */
14312 if (CHIP_IS_E1x(sc)) {
14313 shmem_base = shmem_base_path[0];
14314 shmem2_base = shmem2_base_path[0];
14316 shmem_base = shmem_base_path[port];
14317 shmem2_base = shmem2_base_path[port];
14319 /* Extract the ext phy address for the port */
14320 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14323 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14324 return ELINK_STATUS_ERROR;
14328 elink_cl45_write(sc, &phy,
14329 MDIO_PMA_DEVAD, MDIO_PMA_REG_GEN_CTRL, 0x0001);
14332 /* Set fault module detected LED on */
14333 elink_cb_gpio_write(sc, MISC_REGISTERS_GPIO_0,
14334 MISC_REGISTERS_GPIO_HIGH,
14338 return ELINK_STATUS_OK;
14340 static void elink_get_ext_phy_reset_gpio(struct bxe_softc *sc, uint32_t shmem_base,
14341 uint8_t *io_gpio, uint8_t *io_port)
14344 uint32_t phy_gpio_reset = REG_RD(sc, shmem_base +
14345 offsetof(struct shmem_region,
14346 dev_info.port_hw_config[PORT_0].default_cfg));
14347 switch (phy_gpio_reset) {
14348 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P0:
14352 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P0:
14356 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P0:
14360 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P0:
14364 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO0_P1:
14368 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO1_P1:
14372 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO2_P1:
14376 case PORT_HW_CFG_EXT_PHY_GPIO_RST_GPIO3_P1:
14381 /* Don't override the io_gpio and io_port */
14386 static elink_status_t elink_8727_common_init_phy(struct bxe_softc *sc,
14387 uint32_t shmem_base_path[],
14388 uint32_t shmem2_base_path[], uint8_t phy_index,
14391 int8_t port, reset_gpio;
14392 uint32_t swap_val, swap_override;
14393 struct elink_phy phy[PORT_MAX];
14394 struct elink_phy *phy_blk[PORT_MAX];
14395 int8_t port_of_path;
14396 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
14397 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
14399 reset_gpio = MISC_REGISTERS_GPIO_1;
14402 /* Retrieve the reset gpio/port which control the reset.
14403 * Default is GPIO1, PORT1
14405 elink_get_ext_phy_reset_gpio(sc, shmem_base_path[0],
14406 (uint8_t *)&reset_gpio, (uint8_t *)&port);
14408 /* Calculate the port based on port swap */
14409 port ^= (swap_val && swap_override);
14411 /* Initiate PHY reset*/
14412 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_LOW,
14415 elink_cb_gpio_write(sc, reset_gpio, MISC_REGISTERS_GPIO_OUTPUT_HIGH,
14420 /* PART1 - Reset both phys */
14421 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14422 uint32_t shmem_base, shmem2_base;
14424 /* In E2, same phy is using for port0 of the two paths */
14425 if (CHIP_IS_E1x(sc)) {
14426 shmem_base = shmem_base_path[0];
14427 shmem2_base = shmem2_base_path[0];
14428 port_of_path = port;
14430 shmem_base = shmem_base_path[port];
14431 shmem2_base = shmem2_base_path[port];
14435 /* Extract the ext phy address for the port */
14436 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14437 port_of_path, &phy[port]) !=
14439 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14440 return ELINK_STATUS_ERROR;
14442 /* disable attentions */
14443 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 +
14445 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
14446 ELINK_NIG_MASK_XGXS0_LINK10G |
14447 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
14448 ELINK_NIG_MASK_MI_INT));
14451 /* Reset the phy */
14452 elink_cl45_write(sc, &phy[port],
14453 MDIO_PMA_DEVAD, MDIO_PMA_REG_CTRL, 1<<15);
14456 /* Add delay of 150ms after reset */
14458 if (phy[PORT_0].addr & 0x1) {
14459 phy_blk[PORT_0] = &(phy[PORT_1]);
14460 phy_blk[PORT_1] = &(phy[PORT_0]);
14462 phy_blk[PORT_0] = &(phy[PORT_0]);
14463 phy_blk[PORT_1] = &(phy[PORT_1]);
14465 /* PART2 - Download firmware to both phys */
14466 for (port = PORT_MAX - 1; port >= PORT_0; port--) {
14467 if (CHIP_IS_E1x(sc))
14468 port_of_path = port;
14471 ELINK_DEBUG_P1(sc, "Loading spirom for phy address 0x%x\n",
14472 phy_blk[port]->addr);
14473 if (elink_8073_8727_external_rom_boot(sc, phy_blk[port],
14475 return ELINK_STATUS_ERROR;
14476 /* Disable PHY transmitter output */
14477 elink_cl45_write(sc, phy_blk[port],
14479 MDIO_PMA_REG_TX_DISABLE, 1);
14482 return ELINK_STATUS_OK;
14485 static elink_status_t elink_84833_common_init_phy(struct bxe_softc *sc,
14486 uint32_t shmem_base_path[],
14487 uint32_t shmem2_base_path[],
14491 uint8_t reset_gpios;
14492 reset_gpios = elink_84833_get_reset_gpios(sc, shmem_base_path, chip_id);
14493 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_LOW);
14495 elink_cb_gpio_mult_write(sc, reset_gpios, MISC_REGISTERS_GPIO_OUTPUT_HIGH);
14496 ELINK_DEBUG_P1(sc, "84833 reset pulse on pin values 0x%x\n",
14498 return ELINK_STATUS_OK;
14500 static elink_status_t elink_ext_phy_common_init(struct bxe_softc *sc, uint32_t shmem_base_path[],
14501 uint32_t shmem2_base_path[], uint8_t phy_index,
14502 uint32_t ext_phy_type, uint32_t chip_id)
14504 elink_status_t rc = ELINK_STATUS_OK;
14506 switch (ext_phy_type) {
14507 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8073:
14508 rc = elink_8073_common_init_phy(sc, shmem_base_path,
14510 phy_index, chip_id);
14512 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8722:
14513 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727:
14514 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8727_NOC:
14515 rc = elink_8727_common_init_phy(sc, shmem_base_path,
14517 phy_index, chip_id);
14520 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726:
14521 /* GPIO1 affects both ports, so there's need to pull
14522 * it for single port alone
14524 rc = elink_8726_common_init_phy(sc, shmem_base_path,
14526 phy_index, chip_id);
14528 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84833:
14529 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84834:
14530 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM84858:
14531 /* GPIO3's are linked, and so both need to be toggled
14532 * to obtain required 2us pulse.
14534 rc = elink_84833_common_init_phy(sc, shmem_base_path,
14536 phy_index, chip_id);
14538 case PORT_HW_CFG_XGXS_EXT_PHY_TYPE_FAILURE:
14539 rc = ELINK_STATUS_ERROR;
14543 "ext_phy 0x%x common init not required\n",
14548 if (rc != ELINK_STATUS_OK)
14549 elink_cb_event_log(sc, ELINK_LOG_ID_PHY_UNINITIALIZED, 0); // "Warning: PHY was not initialized,"
14555 elink_status_t elink_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base_path[],
14556 uint32_t shmem2_base_path[], uint32_t chip_id,
14557 uint8_t one_port_enabled)
14559 elink_status_t rc = ELINK_STATUS_OK;
14560 uint32_t phy_ver, val;
14561 uint8_t phy_index = 0;
14562 uint32_t ext_phy_type, ext_phy_config;
14563 #if defined(ELINK_INCLUDE_EMUL) || defined(ELINK_INCLUDE_FPGA)
14564 if (CHIP_REV_IS_EMUL(sc) || CHIP_REV_IS_FPGA(sc))
14565 return ELINK_STATUS_OK;
14568 elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC0);
14569 elink_set_mdio_clk(sc, chip_id, GRCBASE_EMAC1);
14570 ELINK_DEBUG_P0(sc, "Begin common phy init\n");
14571 if (CHIP_IS_E3(sc)) {
14573 val = REG_RD(sc, MISC_REG_GEN_PURP_HWG);
14574 REG_WR(sc, MISC_REG_GEN_PURP_HWG, val | 1);
14576 /* Check if common init was already done */
14577 phy_ver = REG_RD(sc, shmem_base_path[0] +
14578 offsetof(struct shmem_region,
14579 port_mb[PORT_0].ext_phy_fw_version));
14581 ELINK_DEBUG_P1(sc, "Not doing common init; phy ver is 0x%x\n",
14583 return ELINK_STATUS_OK;
14586 /* Read the ext_phy_type for arbitrary port(0) */
14587 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
14589 ext_phy_config = elink_get_ext_phy_config(sc,
14590 shmem_base_path[0],
14592 ext_phy_type = ELINK_XGXS_EXT_PHY_TYPE(ext_phy_config);
14593 rc |= elink_ext_phy_common_init(sc, shmem_base_path,
14595 phy_index, ext_phy_type,
14601 static void elink_check_over_curr(struct elink_params *params,
14602 struct elink_vars *vars)
14604 struct bxe_softc *sc = params->sc;
14606 uint8_t port = params->port;
14609 cfg_pin = (REG_RD(sc, params->shmem_base +
14610 offsetof(struct shmem_region,
14611 dev_info.port_hw_config[port].e3_cmn_pin_cfg1)) &
14612 PORT_HW_CFG_E3_OVER_CURRENT_MASK) >>
14613 PORT_HW_CFG_E3_OVER_CURRENT_SHIFT;
14615 /* Ignore check if no external input PIN available */
14616 if (elink_get_cfg_pin(sc, cfg_pin, &pin_val) != ELINK_STATUS_OK)
14620 if ((vars->phy_flags & PHY_OVER_CURRENT_FLAG) == 0) {
14621 elink_cb_event_log(sc, ELINK_LOG_ID_OVER_CURRENT, params->port); //"Error: Power fault on Port %d has"
14622 // " been detected and the power to "
14623 // "that SFP+ module has been removed"
14624 // " to prevent failure of the card."
14625 // " Please remove the SFP+ module and"
14626 // " restart the system to clear this"
14628 vars->phy_flags |= PHY_OVER_CURRENT_FLAG;
14629 elink_warpcore_power_module(params, 0);
14632 vars->phy_flags &= ~PHY_OVER_CURRENT_FLAG;
14635 /* Returns 0 if no change occured since last check; 1 otherwise. */
14636 static uint8_t elink_analyze_link_error(struct elink_params *params,
14637 struct elink_vars *vars, uint32_t status,
14638 uint32_t phy_flag, uint32_t link_flag, uint8_t notify)
14640 struct bxe_softc *sc = params->sc;
14641 /* Compare new value with previous value */
14643 uint32_t old_status = (vars->phy_flags & phy_flag) ? 1 : 0;
14645 if ((status ^ old_status) == 0)
14648 /* If values differ */
14649 switch (phy_flag) {
14650 case PHY_HALF_OPEN_CONN_FLAG:
14651 ELINK_DEBUG_P0(sc, "Analyze Remote Fault\n");
14653 case PHY_SFP_TX_FAULT_FLAG:
14654 ELINK_DEBUG_P0(sc, "Analyze TX Fault\n");
14657 ELINK_DEBUG_P0(sc, "Analyze UNKNOWN\n");
14659 ELINK_DEBUG_P3(sc, "Link changed:[%x %x]->%x\n", vars->link_up,
14660 old_status, status);
14662 /* Do not touch the link in case physical link down */
14663 if ((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0)
14666 /* a. Update shmem->link_status accordingly
14667 * b. Update elink_vars->link_up
14670 vars->link_status &= ~LINK_STATUS_LINK_UP;
14671 vars->link_status |= link_flag;
14673 vars->phy_flags |= phy_flag;
14675 /* activate nig drain */
14676 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 1);
14677 /* Set LED mode to off since the PHY doesn't know about these
14680 led_mode = ELINK_LED_MODE_OFF;
14682 vars->link_status |= LINK_STATUS_LINK_UP;
14683 vars->link_status &= ~link_flag;
14685 vars->phy_flags &= ~phy_flag;
14686 led_mode = ELINK_LED_MODE_OPER;
14688 /* Clear nig drain */
14689 REG_WR(sc, NIG_REG_EGRESS_DRAIN0_MODE + params->port*4, 0);
14691 elink_sync_link(params, vars);
14692 /* Update the LED according to the link state */
14693 elink_set_led(params, vars, led_mode, ELINK_SPEED_10000);
14695 /* Update link status in the shared memory */
14696 elink_update_mng(params, vars->link_status);
14698 /* C. Trigger General Attention */
14699 vars->periodic_flags |= ELINK_PERIODIC_FLAGS_LINK_EVENT;
14701 elink_cb_notify_link_changed(sc);
14706 /******************************************************************************
14708 * This function checks for half opened connection change indication.
14709 * When such change occurs, it calls the elink_analyze_link_error
14710 * to check if Remote Fault is set or cleared. Reception of remote fault
14711 * status message in the MAC indicates that the peer's MAC has detected
14712 * a fault, for example, due to break in the TX side of fiber.
14714 ******************************************************************************/
14716 elink_status_t elink_check_half_open_conn(struct elink_params *params,
14717 struct elink_vars *vars,
14720 struct bxe_softc *sc = params->sc;
14721 uint32_t lss_status = 0;
14723 /* In case link status is physically up @ 10G do */
14724 if (((vars->phy_flags & PHY_PHYSICAL_LINK_FLAG) == 0) ||
14725 (REG_RD(sc, NIG_REG_EGRESS_EMAC0_PORT + params->port*4)))
14726 return ELINK_STATUS_OK;
14728 if (CHIP_IS_E3(sc) &&
14729 (REG_RD(sc, MISC_REG_RESET_REG_2) &
14730 (MISC_REGISTERS_RESET_REG_2_XMAC))) {
14731 /* Check E3 XMAC */
14732 /* Note that link speed cannot be queried here, since it may be
14733 * zero while link is down. In case UMAC is active, LSS will
14734 * simply not be set
14736 mac_base = (params->port) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
14738 /* Clear stick bits (Requires rising edge) */
14739 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS, 0);
14740 REG_WR(sc, mac_base + XMAC_REG_CLEAR_RX_LSS_STATUS,
14741 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_LOCAL_FAULT_STATUS |
14742 XMAC_CLEAR_RX_LSS_STATUS_REG_CLEAR_REMOTE_FAULT_STATUS);
14743 if (REG_RD(sc, mac_base + XMAC_REG_RX_LSS_STATUS))
14746 elink_analyze_link_error(params, vars, lss_status,
14747 PHY_HALF_OPEN_CONN_FLAG,
14748 LINK_STATUS_NONE, notify);
14749 } else if (REG_RD(sc, MISC_REG_RESET_REG_2) &
14750 (MISC_REGISTERS_RESET_REG_2_RST_BMAC0 << params->port)) {
14751 /* Check E1X / E2 BMAC */
14752 uint32_t lss_status_reg;
14753 uint32_t wb_data[2];
14754 mac_base = params->port ? NIG_REG_INGRESS_BMAC1_MEM :
14755 NIG_REG_INGRESS_BMAC0_MEM;
14756 /* Read BIGMAC_REGISTER_RX_LSS_STATUS */
14757 if (CHIP_IS_E2(sc))
14758 lss_status_reg = BIGMAC2_REGISTER_RX_LSS_STAT;
14760 lss_status_reg = BIGMAC_REGISTER_RX_LSS_STATUS;
14762 REG_RD_DMAE(sc, mac_base + lss_status_reg, wb_data, 2);
14763 lss_status = (wb_data[0] > 0);
14765 elink_analyze_link_error(params, vars, lss_status,
14766 PHY_HALF_OPEN_CONN_FLAG,
14767 LINK_STATUS_NONE, notify);
14769 return ELINK_STATUS_OK;
14771 static void elink_sfp_tx_fault_detection(struct elink_phy *phy,
14772 struct elink_params *params,
14773 struct elink_vars *vars)
14775 struct bxe_softc *sc = params->sc;
14776 uint32_t cfg_pin, value = 0;
14777 uint8_t led_change, port = params->port;
14779 /* Get The SFP+ TX_Fault controlling pin ([eg]pio) */
14780 cfg_pin = (REG_RD(sc, params->shmem_base + offsetof(struct shmem_region,
14781 dev_info.port_hw_config[port].e3_cmn_pin_cfg)) &
14782 PORT_HW_CFG_E3_TX_FAULT_MASK) >>
14783 PORT_HW_CFG_E3_TX_FAULT_SHIFT;
14785 if (elink_get_cfg_pin(sc, cfg_pin, &value)) {
14786 ELINK_DEBUG_P1(sc, "Failed to read pin 0x%02x\n", cfg_pin);
14790 led_change = elink_analyze_link_error(params, vars, value,
14791 PHY_SFP_TX_FAULT_FLAG,
14792 LINK_STATUS_SFP_TX_FAULT, 1);
14795 /* Change TX_Fault led, set link status for further syncs */
14798 if (vars->phy_flags & PHY_SFP_TX_FAULT_FLAG) {
14799 led_mode = MISC_REGISTERS_GPIO_HIGH;
14800 vars->link_status |= LINK_STATUS_SFP_TX_FAULT;
14802 led_mode = MISC_REGISTERS_GPIO_LOW;
14803 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
14806 /* If module is unapproved, led should be on regardless */
14807 if (!(phy->flags & ELINK_FLAGS_SFP_NOT_APPROVED)) {
14808 ELINK_DEBUG_P1(sc, "Change TX_Fault LED: ->%x\n",
14810 elink_set_e3_module_fault_led(params, led_mode);
14814 static void elink_kr2_recovery(struct elink_params *params,
14815 struct elink_vars *vars,
14816 struct elink_phy *phy)
14818 struct bxe_softc *sc = params->sc;
14819 ELINK_DEBUG_P0(sc, "KR2 recovery\n");
14820 elink_warpcore_enable_AN_KR2(phy, params, vars);
14821 elink_warpcore_restart_AN_KR(phy, params);
14824 static void elink_check_kr2_wa(struct elink_params *params,
14825 struct elink_vars *vars,
14826 struct elink_phy *phy)
14828 struct bxe_softc *sc = params->sc;
14829 uint16_t base_page, next_page, not_kr2_device, lane;
14832 /* Once KR2 was disabled, wait 5 seconds before checking KR2 recovery
14833 * Since some switches tend to reinit the AN process and clear the
14834 * the advertised BP/NP after ~2 seconds causing the KR2 to be disabled
14835 * and recovered many times
14837 if (vars->check_kr2_recovery_cnt > 0) {
14838 vars->check_kr2_recovery_cnt--;
14842 sigdet = elink_warpcore_get_sigdet(phy, params);
14844 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14845 elink_kr2_recovery(params, vars, phy);
14846 ELINK_DEBUG_P0(sc, "No sigdet\n");
14851 lane = elink_get_warpcore_lane(phy, params);
14852 CL22_WR_OVER_CL45(sc, phy, MDIO_REG_BANK_AER_BLOCK,
14853 MDIO_AER_BLOCK_AER_REG, lane);
14854 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
14855 MDIO_AN_REG_LP_AUTO_NEG, &base_page);
14856 elink_cl45_read(sc, phy, MDIO_AN_DEVAD,
14857 MDIO_AN_REG_LP_AUTO_NEG2, &next_page);
14858 elink_set_aer_mmd(params, phy);
14860 /* CL73 has not begun yet */
14861 if (base_page == 0) {
14862 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14863 elink_kr2_recovery(params, vars, phy);
14864 ELINK_DEBUG_P0(sc, "No BP\n");
14869 /* In case NP bit is not set in the BasePage, or it is set,
14870 * but only KX is advertised, declare this link partner as non-KR2
14873 not_kr2_device = (((base_page & 0x8000) == 0) ||
14874 (((base_page & 0x8000) &&
14875 ((next_page & 0xe0) == 0x20))));
14877 /* In case KR2 is already disabled, check if we need to re-enable it */
14878 if (!(params->link_attr_sync & LINK_ATTR_SYNC_KR2_ENABLE)) {
14879 if (!not_kr2_device) {
14880 ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x\n", base_page,
14882 elink_kr2_recovery(params, vars, phy);
14886 /* KR2 is enabled, but not KR2 device */
14887 if (not_kr2_device) {
14888 /* Disable KR2 on both lanes */
14889 ELINK_DEBUG_P2(sc, "BP=0x%x, NP=0x%x\n", base_page, next_page);
14890 elink_disable_kr2(params, vars, phy);
14891 /* Restart AN on leading lane */
14892 elink_warpcore_restart_AN_KR(phy, params);
14897 void elink_period_func(struct elink_params *params, struct elink_vars *vars)
14900 struct bxe_softc *sc = params->sc;
14901 for (phy_idx = ELINK_INT_PHY; phy_idx < ELINK_MAX_PHYS; phy_idx++) {
14902 if (params->phy[phy_idx].flags & ELINK_FLAGS_TX_ERROR_CHECK) {
14903 elink_set_aer_mmd(params, ¶ms->phy[phy_idx]);
14904 if (elink_check_half_open_conn(params, vars, 1) !=
14906 ELINK_DEBUG_P0(sc, "Fault detection failed\n");
14911 if (CHIP_IS_E3(sc)) {
14912 struct elink_phy *phy = ¶ms->phy[ELINK_INT_PHY];
14913 elink_set_aer_mmd(params, phy);
14914 if (((phy->req_line_speed == ELINK_SPEED_AUTO_NEG) &&
14915 (phy->speed_cap_mask &
14916 PORT_HW_CFG_SPEED_CAPABILITY_D0_20G)) ||
14917 (phy->req_line_speed == ELINK_SPEED_20000))
14918 elink_check_kr2_wa(params, vars, phy);
14919 elink_check_over_curr(params, vars);
14920 if (vars->rx_tx_asic_rst)
14921 elink_warpcore_config_runtime(phy, params, vars);
14923 if ((REG_RD(sc, params->shmem_base +
14924 offsetof(struct shmem_region, dev_info.
14925 port_hw_config[params->port].default_cfg))
14926 & PORT_HW_CFG_NET_SERDES_IF_MASK) ==
14927 PORT_HW_CFG_NET_SERDES_IF_SFI) {
14928 if (elink_is_sfp_module_plugged(phy, params)) {
14929 elink_sfp_tx_fault_detection(phy, params, vars);
14930 } else if (vars->link_status &
14931 LINK_STATUS_SFP_TX_FAULT) {
14932 /* Clean trail, interrupt corrects the leds */
14933 vars->link_status &= ~LINK_STATUS_SFP_TX_FAULT;
14934 vars->phy_flags &= ~PHY_SFP_TX_FAULT_FLAG;
14935 /* Update link status in the shared memory */
14936 elink_update_mng(params, vars->link_status);
14942 uint8_t elink_fan_failure_det_req(struct bxe_softc *sc,
14943 uint32_t shmem_base,
14944 uint32_t shmem2_base,
14947 uint8_t phy_index, fan_failure_det_req = 0;
14948 struct elink_phy phy;
14949 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
14951 if (elink_populate_phy(sc, phy_index, shmem_base, shmem2_base,
14953 != ELINK_STATUS_OK) {
14954 ELINK_DEBUG_P0(sc, "populate phy failed\n");
14957 fan_failure_det_req |= (phy.flags &
14958 ELINK_FLAGS_FAN_FAILURE_DET_REQ);
14960 return fan_failure_det_req;
14963 void elink_hw_reset_phy(struct elink_params *params)
14966 struct bxe_softc *sc = params->sc;
14967 elink_update_mng(params, 0);
14968 elink_bits_dis(sc, NIG_REG_MASK_INTERRUPT_PORT0 + params->port*4,
14969 (ELINK_NIG_MASK_XGXS0_LINK_STATUS |
14970 ELINK_NIG_MASK_XGXS0_LINK10G |
14971 ELINK_NIG_MASK_SERDES0_LINK_STATUS |
14972 ELINK_NIG_MASK_MI_INT));
14974 for (phy_index = ELINK_INT_PHY; phy_index < ELINK_MAX_PHYS;
14976 if (params->phy[phy_index].hw_reset) {
14977 params->phy[phy_index].hw_reset(
14978 ¶ms->phy[phy_index],
14980 params->phy[phy_index] = phy_null;
14985 void elink_init_mod_abs_int(struct bxe_softc *sc, struct elink_vars *vars,
14986 uint32_t chip_id, uint32_t shmem_base, uint32_t shmem2_base,
14989 uint8_t gpio_num = 0xff, gpio_port = 0xff, phy_index;
14991 uint32_t offset, aeu_mask, swap_val, swap_override, sync_offset;
14992 if (CHIP_IS_E3(sc)) {
14993 if (elink_get_mod_abs_int_cfg(sc, chip_id,
14997 &gpio_port) != ELINK_STATUS_OK)
15000 struct elink_phy phy;
15001 for (phy_index = ELINK_EXT_PHY1; phy_index < ELINK_MAX_PHYS;
15003 if (elink_populate_phy(sc, phy_index, shmem_base,
15004 shmem2_base, port, &phy)
15005 != ELINK_STATUS_OK) {
15006 ELINK_DEBUG_P0(sc, "populate phy failed\n");
15009 if (phy.type == PORT_HW_CFG_XGXS_EXT_PHY_TYPE_BCM8726) {
15010 gpio_num = MISC_REGISTERS_GPIO_3;
15017 if (gpio_num == 0xff)
15020 /* Set GPIO3 to trigger SFP+ module insertion/removal */
15021 elink_cb_gpio_write(sc, gpio_num, MISC_REGISTERS_GPIO_INPUT_HI_Z, gpio_port);
15023 swap_val = REG_RD(sc, NIG_REG_PORT_SWAP);
15024 swap_override = REG_RD(sc, NIG_REG_STRAP_OVERRIDE);
15025 gpio_port ^= (swap_val && swap_override);
15027 vars->aeu_int_mask = AEU_INPUTS_ATTN_BITS_GPIO0_FUNCTION_0 <<
15028 (gpio_num + (gpio_port << 2));
15030 sync_offset = shmem_base +
15031 offsetof(struct shmem_region,
15032 dev_info.port_hw_config[port].aeu_int_mask);
15033 REG_WR(sc, sync_offset, vars->aeu_int_mask);
15035 ELINK_DEBUG_P3(sc, "Setting MOD_ABS (GPIO%d_P%d) AEU to 0x%x\n",
15036 gpio_num, gpio_port, vars->aeu_int_mask);
15039 offset = MISC_REG_AEU_ENABLE1_FUNC_0_OUT_0;
15041 offset = MISC_REG_AEU_ENABLE1_FUNC_1_OUT_0;
15043 /* Open appropriate AEU for interrupts */
15044 aeu_mask = REG_RD(sc, offset);
15045 aeu_mask |= vars->aeu_int_mask;
15046 REG_WR(sc, offset, aeu_mask);
15048 /* Enable the GPIO to trigger interrupt */
15049 val = REG_RD(sc, MISC_REG_GPIO_EVENT_EN);
15050 val |= 1 << (gpio_num + (gpio_port << 2));
15051 REG_WR(sc, MISC_REG_GPIO_EVENT_EN, val);