2 * Copyright (c) 2007-2010 Broadcom Corporation. All rights reserved.
4 * Gary Zambrano <zambrano@broadcom.com>
5 * David Christensen <davidch@broadcom.com>
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. Neither the name of Broadcom Corporation nor the name of its contributors
17 * may be used to endorse or promote products derived from this software
18 * without specific prior written consent.
20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS'
21 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS
24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
30 * THE POSSIBILITY OF SUCH DAMAGE.
41 #define DEFAULT_PHY_DEV_ADDR 3
45 #define FLOW_CTRL_AUTO PORT_FEATURE_FLOW_CONTROL_AUTO
46 #define FLOW_CTRL_TX PORT_FEATURE_FLOW_CONTROL_TX
47 #define FLOW_CTRL_RX PORT_FEATURE_FLOW_CONTROL_RX
48 #define FLOW_CTRL_BOTH PORT_FEATURE_FLOW_CONTROL_BOTH
49 #define FLOW_CTRL_NONE PORT_FEATURE_FLOW_CONTROL_NONE
51 #define SPEED_AUTO_NEG 0
52 #define SPEED_12000 12000
53 #define SPEED_12500 12500
54 #define SPEED_13000 13000
55 #define SPEED_15000 15000
56 #define SPEED_16000 16000
58 #define SFP_EEPROM_VENDOR_NAME_ADDR 0x14
59 #define SFP_EEPROM_VENDOR_NAME_SIZE 16
60 #define SFP_EEPROM_VENDOR_OUI_ADDR 0x25
61 #define SFP_EEPROM_VENDOR_OUI_SIZE 3
62 #define SFP_EEPROM_PART_NO_ADDR 0x28
63 #define SFP_EEPROM_PART_NO_SIZE 16
64 #define PWR_FLT_ERR_MSG_LEN 250
69 /* Inputs parameters to the CLC. */
72 /* Default / User Configuration */
73 uint8_t loopback_mode;
74 #define LOOPBACK_NONE 0
75 #define LOOPBACK_EMAC 1
76 #define LOOPBACK_BMAC 2
77 #define LOOPBACK_XGXS_10 3
78 #define LOOPBACK_EXT_PHY 4
79 #define LOOPBACK_EXT 5
82 uint16_t req_flow_ctrl;
83 /* Should be set to TX / BOTH when req_flow_ctrl is set to AUTO. */
84 uint16_t req_fc_auto_adv;
85 /* Also determine AutoNeg. */
86 uint16_t req_line_speed;
88 /* Device parameters */
91 /* shmem parameters */
93 uint32_t speed_cap_mask;
95 #define SWITCH_CFG_1G PORT_FEATURE_CON_SWITCH_1G_SWITCH
96 #define SWITCH_CFG_10G PORT_FEATURE_CON_SWITCH_10G_SWITCH
97 #define SWITCH_CFG_AUTO_DETECT PORT_FEATURE_CON_SWITCH_AUTO_DETECT
99 /* Part of the hw_config read from the shmem. */
100 uint16_t hw_led_mode;
102 /* phy_addr populated by the CLC. */
104 /* uint8_t reserved1; */
106 uint32_t lane_config;
107 uint32_t ext_phy_config;
108 #define XGXS_EXT_PHY_TYPE(ext_phy_config) \
109 ((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_TYPE_MASK)
110 #define XGXS_EXT_PHY_ADDR(ext_phy_config) \
111 (((ext_phy_config) & PORT_HW_CFG_XGXS_EXT_PHY_ADDR_MASK) >> \
112 PORT_HW_CFG_XGXS_EXT_PHY_ADDR_SHIFT)
113 #define SERDES_EXT_PHY_TYPE(ext_phy_config) \
114 ((ext_phy_config) & PORT_HW_CFG_SERDES_EXT_PHY_TYPE_MASK)
116 /* Phy register parameter */
119 uint16_t xgxs_config_rx[4]; /* preemphasis values for the rx side */
120 uint16_t xgxs_config_tx[4]; /* preemphasis values for the tx side */
122 uint32_t feature_config_flags;
123 #define FEATURE_CONFIG_OVERRIDE_PREEMPHASIS_ENABLED (1<<0)
124 #define FEATURE_CONFIG_PFC_ENABLED (1<<1)
125 #define FEATURE_CONFIG_BC_SUPPORTS_OPT_MDL_VRFY (1<<2)
126 #define FEATURE_CONFIG_BCM8727_NOC (1<<3)
128 /* Device pointer passed to all callback functions. */
129 struct bxe_softc *sc;
132 /* Output parameters */
137 #define MAC_TYPE_NONE 0
138 #define MAC_TYPE_EMAC 1
139 #define MAC_TYPE_BMAC 2
141 /* Internal phy link indication. */
152 #define AUTO_NEG_DISABLED 0x0
153 #define AUTO_NEG_ENABLED 0x1
154 #define AUTO_NEG_COMPLETE 0x2
155 #define AUTO_NEG_PARALLEL_DETECTION_USED 0x4
157 /* The same definitions as the shmem parameter. */
158 uint32_t link_status;
165 /* Initialize the phy. */
166 uint8_t bxe_phy_init(struct link_params *input, struct link_vars *output);
169 * Reset the link. Should be called when driver or interface goes down
170 * Before calling phy firmware upgrade, the reset_ext_phy should be set
173 uint8_t bxe_link_reset(struct link_params *params, struct link_vars *vars,
174 uint8_t reset_ext_phy);
176 /* bxe_link_update should be called upon link interrupt */
177 uint8_t bxe_link_update(struct link_params *input, struct link_vars *output);
180 * Use the following cl45 functions to read/write from external_phy
181 * In order to use it to read/write internal phy registers, use
182 * DEFAULT_PHY_DEV_ADDR as devad, and (_bank + (_addr & 0xf)) as
183 * Use ext_phy_type of 0 in case of cl22 over cl45
186 uint8_t bxe_cl45_read(struct bxe_softc *sc, uint8_t port, uint32_t ext_phy_type,
187 uint8_t phy_addr, uint8_t devad, uint16_t reg, uint16_t *ret_val);
189 uint8_t bxe_cl45_write(struct bxe_softc *sc, uint8_t port,
190 uint32_t ext_phy_type, uint8_t phy_addr, uint8_t devad, uint16_t reg,
194 * Reads the link_status from the shmem, and update the link vars accordingly.
196 void bxe_link_status_update(struct link_params *input,
197 struct link_vars *output);
198 /* Returns string representing the fw_version of the external phy. */
199 uint8_t bxe_get_ext_phy_fw_version(struct link_params *params,
200 uint8_t driver_loaded, uint8_t *version, uint16_t len);
204 * Basically, the CLC takes care of the led for the link, but in case one needs
205 * to set/unset the led unnaturally, set the "mode" to LED_MODE_OPER to blink
206 * the led, and LED_MODE_OFF to set the led off.
208 uint8_t bxe_set_led(struct link_params *params, uint8_t mode, uint32_t speed);
209 #define LED_MODE_OFF 0
210 #define LED_MODE_OPER 2
212 uint8_t bxe_override_led_value(struct bxe_softc *sc, uint8_t port,
213 uint32_t led_idx, uint32_t value);
216 * bxe_handle_module_detect_int should be called upon module detection
219 void bxe_handle_module_detect_int(struct link_params *params);
222 * Get the actual link status. In case it returns 0, link is up, otherwise
225 uint8_t bxe_test_link(struct link_params *input, struct link_vars *vars);
227 /* One-time initialization for external phy after power up. */
228 uint8_t bxe_common_init_phy(struct bxe_softc *sc, uint32_t shmem_base);
230 /* Reset the external PHY using GPIO. */
231 void bxe_ext_phy_hw_reset(struct bxe_softc *sc, uint8_t port);
233 void bxe_sfx7101_sp_sw_reset(struct bxe_softc *sc, uint8_t port,
236 uint8_t bxe_read_sfp_module_eeprom(struct link_params *params, uint16_t addr,
237 uint8_t byte_cnt, uint8_t *o_buf);
239 #endif /* BXE_LINK_H */