2 * Copyright (c) 2012-2013 Thomas Skibo
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 * Hardware and register defines for Cadence GEM Gigabit Ethernet
31 * controller such as the one used in Zynq-7000 SoC.
33 * Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
34 * (v1.4) November 16, 2012. Xilinx doc UG585. GEM is covered in Ch. 16
35 * and register definitions are in appendix B.18.
38 #ifndef _IF_CGEM_HW_H_
39 #define _IF_CGEM_HW_H_
41 /* Cadence GEM hardware register definitions. */
42 #define CGEM_NET_CTRL 0x000 /* Network Control */
43 #define CGEM_NET_CTRL_FLUSH_DPRAM_PKT (1<<18)
44 #define CGEM_NET_CTRL_TX_PFC_PRI_PAUSE_FRAME (1<<17)
45 #define CGEM_NET_CTRL_EN_PFC_PRI_PAUSE_RX (1<<16)
46 #define CGEM_NET_CTRL_STORE_RX_TSTAMP (1<<15)
47 #define CGEM_NET_CTRL_TX_ZEROQ_PAUSE_FRAME (1<<12)
48 #define CGEM_NET_CTRL_TX_PAUSE_FRAME (1<<11)
49 #define CGEM_NET_CTRL_TX_HALT (1<<10)
50 #define CGEM_NET_CTRL_START_TX (1<<9)
51 #define CGEM_NET_CTRL_BACK_PRESSURE (1<<8)
52 #define CGEM_NET_CTRL_WREN_STAT_REGS (1<<7)
53 #define CGEM_NET_CTRL_INCR_STAT_REGS (1<<6)
54 #define CGEM_NET_CTRL_CLR_STAT_REGS (1<<5)
55 #define CGEM_NET_CTRL_MGMT_PORT_EN (1<<4)
56 #define CGEM_NET_CTRL_TX_EN (1<<3)
57 #define CGEM_NET_CTRL_RX_EN (1<<2)
58 #define CGEM_NET_CTRL_LOOP_LOCAL (1<<1)
60 #define CGEM_NET_CFG 0x004 /* Netowrk Configuration */
61 #define CGEM_NET_CFG_UNIDIR_EN (1<<31)
62 #define CGEM_NET_CFG_IGNORE_IPG_RX_ER (1<<30)
63 #define CGEM_NET_CFG_RX_BAD_PREAMBLE (1<<29)
64 #define CGEM_NET_CFG_IPG_STRETCH_EN (1<<28)
65 #define CGEM_NET_CFG_SGMII_EN (1<<27)
66 #define CGEM_NET_CFG_IGNORE_RX_FCS (1<<26)
67 #define CGEM_NET_CFG_RX_HD_WHILE_TX (1<<25)
68 #define CGEM_NET_CFG_RX_CHKSUM_OFFLD_EN (1<<24)
69 #define CGEM_NET_CFG_DIS_CP_PAUSE_FRAME (1<<23)
70 #define CGEM_NET_CFG_DBUS_WIDTH_32 (0<<21)
71 #define CGEM_NET_CFG_DBUS_WIDTH_64 (1<<21)
72 #define CGEM_NET_CFG_DBUS_WIDTH_128 (2<<21)
73 #define CGEM_NET_CFG_DBUS_WIDTH_MASK (3<<21)
74 #define CGEM_NET_CFG_MDC_CLK_DIV_8 (0<<18)
75 #define CGEM_NET_CFG_MDC_CLK_DIV_16 (1<<18)
76 #define CGEM_NET_CFG_MDC_CLK_DIV_32 (2<<18)
77 #define CGEM_NET_CFG_MDC_CLK_DIV_48 (3<<18)
78 #define CGEM_NET_CFG_MDC_CLK_DIV_64 (4<<18)
79 #define CGEM_NET_CFG_MDC_CLK_DIV_96 (5<<18)
80 #define CGEM_NET_CFG_MDC_CLK_DIV_128 (6<<18)
81 #define CGEM_NET_CFG_MDC_CLK_DIV_224 (7<<18)
82 #define CGEM_NET_CFG_MDC_CLK_DIV_MASK (7<<18)
83 #define CGEM_NET_CFG_FCS_REMOVE (1<<17)
84 #define CGEM_NET_CFG_LEN_ERR_FRAME_DISC (1<<16)
85 #define CGEM_NET_CFG_RX_BUF_OFFSET_SHFT 14
86 #define CGEM_NET_CFG_RX_BUF_OFFSET_MASK (3<<14)
87 #define CGEM_NET_CFG_RX_BUF_OFFSET(n) ((n)<<14)
88 #define CGEM_NET_CFG_PAUSE_EN (1<<13)
89 #define CGEM_NET_CFG_RETRY_TEST (1<<12)
90 #define CGEM_NET_CFG_PCS_SEL (1<<11)
91 #define CGEM_NET_CFG_GIGE_EN (1<<10)
92 #define CGEM_NET_CFG_EXT_ADDR_MATCH_EN (1<<9)
93 #define CGEM_NET_CFG_1536RXEN (1<<8)
94 #define CGEM_NET_CFG_UNI_HASH_EN (1<<7)
95 #define CGEM_NET_CFG_MULTI_HASH_EN (1<<6)
96 #define CGEM_NET_CFG_NO_BCAST (1<<5)
97 #define CGEM_NET_CFG_COPY_ALL (1<<4)
98 #define CGEM_NET_CFG_DISC_NON_VLAN (1<<2)
99 #define CGEM_NET_CFG_FULL_DUPLEX (1<<1)
100 #define CGEM_NET_CFG_SPEED100 (1<<0)
102 #define CGEM_NET_STAT 0x008 /* Network Status */
103 #define CGEM_NET_STAT_PFC_PRI_PAUSE_NEG (1<<6)
104 #define CGEM_NET_STAT_PCS_AUTONEG_PAUSE_TX_RES (1<<5)
105 #define CGEM_NET_STAT_PCS_AUTONEG_PAUSE_RX_RES (1<<4)
106 #define CGEM_NET_STAT_PCS_AUTONEG_DUP_RES (1<<3)
107 #define CGEM_NET_STAT_PHY_MGMT_IDLE (1<<2)
108 #define CGEM_NET_STAT_MDIO_IN_PIN_STATUS (1<<1)
109 #define CGEM_NET_STAT_PCS_LINK_STATE (1<<0)
111 #define CGEM_USER_IO 0x00C /* User I/O */
113 #define CGEM_DMA_CFG 0x010 /* DMA Config */
114 #define CGEM_DMA_CFG_DISC_WHEN_NO_AHB (1<<24)
115 #define CGEM_DMA_CFG_RX_BUF_SIZE_SHIFT 16
116 #define CGEM_DMA_CFG_RX_BUF_SIZE_MASK (0xff<<16)
117 #define CGEM_DMA_CFG_RX_BUF_SIZE(sz) ((((sz) + 63) / 64) << 16)
118 #define CGEM_DMA_CFG_CHKSUM_GEN_OFFLOAD_EN (1<<11)
119 #define CGEM_DMA_CFG_TX_PKTBUF_MEMSZ_SEL (1<<10)
120 #define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_1K (0<<8)
121 #define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_2K (1<<8)
122 #define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_4K (2<<8)
123 #define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_8K (3<<8)
124 #define CGEM_DMA_CFG_RX_PKTBUF_MEMSZ_SEL_MASK (3<<8)
125 #define CGEM_DMA_CFG_AHB_ENDIAN_SWAP_PKT_EN (1<<7)
126 #define CGEM_DMA_CFG_AHB_ENDIAN_SWAP_MGMT_EN (1<<6)
127 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_1 (1<<0)
128 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_4 (4<<0)
129 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_8 (8<<0)
130 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_16 (16<<0)
131 #define CGEM_DMA_CFG_AHB_FIXED_BURST_LEN_MASK (0x1f<<0)
133 #define CGEM_TX_STAT 0x014 /* Transmit Status */
134 #define CGEM_TX_STAT_HRESP_NOT_OK (1<<8)
135 #define CGEM_TX_STAT_LATE_COLL (1<<7)
136 #define CGEM_TX_STAT_UNDERRUN (1<<6)
137 #define CGEM_TX_STAT_COMPLETE (1<<5)
138 #define CGEM_TX_STAT_CORRUPT_AHB_ERR (1<<4)
139 #define CGEM_TX_STAT_GO (1<<3)
140 #define CGEM_TX_STAT_RETRY_LIMIT_EXC (1<<2)
141 #define CGEM_TX_STAT_COLLISION (1<<1)
142 #define CGEM_TX_STAT_USED_BIT_READ (1<<0)
143 #define CGEM_TX_STAT_ALL 0x1ff
145 #define CGEM_RX_QBAR 0x018 /* Receive Buf Q Base Addr */
146 #define CGEM_TX_QBAR 0x01C /* Transmit Buf Q Base Addr */
148 #define CGEM_RX_STAT 0x020 /* Receive Status */
149 #define CGEM_RX_STAT_HRESP_NOT_OK (1<<3)
150 #define CGEM_RX_STAT_OVERRUN (1<<2)
151 #define CGEM_RX_STAT_FRAME_RECD (1<<1)
152 #define CGEM_RX_STAT_BUF_NOT_AVAIL (1<<0)
153 #define CGEM_RX_STAT_ALL 0xf
155 #define CGEM_INTR_STAT 0x024 /* Interrupt Status */
156 #define CGEM_INTR_EN 0x028 /* Interrupt Enable */
157 #define CGEM_INTR_DIS 0x02C /* Interrupt Disable */
158 #define CGEM_INTR_MASK 0x030 /* Interrupt Mask */
159 #define CGEM_INTR_TSU_SEC_INCR (1<<26)
160 #define CGEM_INTR_PDELAY_RESP_TX (1<<25)
161 #define CGEM_INTR_PDELAY_REQ_TX (1<<24)
162 #define CGEM_INTR_PDELAY_RESP_RX (1<<23)
163 #define CGEM_INTR_PDELAY_REQ_RX (1<<22)
164 #define CGEM_INTR_SYNX_TX (1<<21)
165 #define CGEM_INTR_DELAY_REQ_TX (1<<20)
166 #define CGEM_INTR_SYNC_RX (1<<19)
167 #define CGEM_INTR_DELAY_REQ_RX (1<<18)
168 #define CGEM_INTR_PARTNER_PG_RX (1<<17)
169 #define CGEM_INTR_AUTONEG_COMPL (1<<16)
170 #define CGEM_INTR_EXT_INTR (1<<15)
171 #define CGEM_INTR_PAUSE_TX (1<<14)
172 #define CGEM_INTR_PAUSE_ZERO (1<<13)
173 #define CGEM_INTR_PAUSE_NONZEROQ_RX (1<<12)
174 #define CGEM_INTR_HRESP_NOT_OK (1<<11)
175 #define CGEM_INTR_RX_OVERRUN (1<<10)
176 #define CGEM_INTR_LINK_CHNG (1<<9)
177 #define CGEM_INTR_TX_COMPLETE (1<<7)
178 #define CGEM_INTR_TX_CORRUPT_AHB_ERR (1<<6)
179 #define CGEM_INTR_RETRY_EX_LATE_COLLISION (1<<5)
180 #define CGEM_INTR_TX_USED_READ (1<<3)
181 #define CGEM_INTR_RX_USED_READ (1<<2)
182 #define CGEM_INTR_RX_COMPLETE (1<<1)
183 #define CGEM_INTR_MGMT_SENT (1<<0)
184 #define CGEM_INTR_ALL 0x7FFFEFF
186 #define CGEM_PHY_MAINT 0x034 /* PHY Maintenenace */
187 #define CGEM_PHY_MAINT_CLAUSE_22 (1<<30)
188 #define CGEM_PHY_MAINT_OP_SHIFT 28
189 #define CGEM_PHY_MAINT_OP_MASK (3<<28)
190 #define CGEM_PHY_MAINT_OP_READ (2<<28)
191 #define CGEM_PHY_MAINT_OP_WRITE (1<<28)
192 #define CGEM_PHY_MAINT_PHY_ADDR_SHIFT 23
193 #define CGEM_PHY_MAINT_PHY_ADDR_MASK (0x1f<<23)
194 #define CGEM_PHY_MAINT_REG_ADDR_SHIFT 18
195 #define CGEM_PHY_MAINT_REG_ADDR_MASK (0x1f<<18)
196 #define CGEM_PHY_MAINT_MUST_10 (2<<16)
197 #define CGEM_PHY_MAINT_DATA_MASK 0xffff
199 #define CGEM_RX_PAUSEQ 0x038 /* Received Pause Quantum */
200 #define CGEM_TX_PAUSEQ 0x03C /* Transmit Puase Quantum */
202 #define CGEM_HASH_BOT 0x080 /* Hash Reg Bottom [31:0] */
203 #define CGEM_HASH_TOP 0x084 /* Hash Reg Top [63:32] */
204 #define CGEM_SPEC_ADDR_LOW(n) (0x088+(n)*8) /* Specific Addr low */
205 #define CGEM_SPEC_ADDR_HI(n) (0x08C+(n)*8) /* Specific Addr hi */
207 #define CGEM_TYPE_ID_MATCH1 0x0A8 /* Type ID Match 1 */
208 #define CGEM_TYPE_ID_MATCH_COPY_EN (1<<31)
209 #define CGEM_TYPE_ID_MATCH2 0x0AC /* Type ID Match 2 */
210 #define CGEM_TYPE_ID_MATCH3 0x0B0 /* Type ID Match 3 */
211 #define CGEM_TYPE_ID_MATCH4 0x0B4 /* Type ID Match 4 */
213 #define CGEM_WAKE_ON_LAN 0x0B8 /* Wake on LAN Register */
214 #define CGEM_WOL_MULTI_HASH_EN (1<<19)
215 #define CGEM_WOL_SPEC_ADDR1_EN (1<<18)
216 #define CGEM_WOL_ARP_REQ_EN (1<<17)
217 #define CGEM_WOL_MAGIC_PKT_EN (1<<16)
218 #define CGEM_WOL_ARP_REQ_IP_ADDR_MASK 0xffff
220 #define CGEM_IPG_STRETCH /* IPG Stretch Register */
222 #define CGEM_STACKED_VLAN 0x0C0 /* Stacked VLAN Register */
223 #define CGEM_STACKED_VLAN_EN (1<<31)
225 #define CGEM_TX_PFC_PAUSE 0x0C4 /* Transmit PFC Pause Reg */
226 #define CGEM_TX_PFC_PAUSEQ_SEL_SHIFT 8
227 #define CGEM_TX_PFC_PAUSEQ_SEL_MASK (0xff<<8)
228 #define CGEM_TX_PFC_PAUSE_PRI_EN_VEC_VAL_MASK 0xff
230 #define CGEM_SPEC_ADDR1_MASK_BOT 0x0C8 /* Specific Addr Mask1 [31:0]*/
231 #define CGEM_SPEC_ADDR1_MASK_TOP 0x0CC /* Specific Addr Mask1[47:32]*/
232 #define CGEM_MODULE_ID 0x0FC /* Module ID */
233 #define CGEM_OCTETS_TX_BOT 0x100 /* Octets xmitted [31:0] */
234 #define CGEM_OCTETS_TX_TOP 0x104 /* Octets xmitted [47:32] */
235 #define CGEM_FRAMES_TX 0x108 /* Frames xmitted */
236 #define CGEM_BCAST_FRAMES_TX 0x10C /* Broadcast Frames xmitted */
237 #define CGEM_MULTI_FRAMES_TX 0x110 /* Multicast Frames xmitted */
238 #define CGEM_PAUSE_FRAMES_TX 0x114 /* Pause Frames xmitted */
239 #define CGEM_FRAMES_64B_TX 0x118 /* 64-Byte Frames xmitted */
240 #define CGEM_FRAMES_65_127B_TX 0x11C /* 65-127 Byte Frames xmitted*/
241 #define CGEM_FRAMES_128_255B_TX 0x120 /* 128-255 Byte Frames xmit */
242 #define CGEM_FRAMES_256_511B_TX 0x124 /* 256-511 Byte Frames xmit */
243 #define CGEM_FRAMES_512_1023B_TX 0x128 /* 512-1023 Byte frames xmit */
244 #define CGEM_FRAMES_1024_1518B_TX 0x12C /* 1024-1518 Byte frames xmit*/
245 #define CGEM_TX_UNDERRUNS 0x134 /* Transmit Under-runs */
246 #define CGEM_SINGLE_COLL_FRAMES 0x138 /* Single-Collision Frames */
247 #define CGEM_MULTI_COLL_FRAMES 0x13C /* Multi-Collision Frames */
248 #define CGEM_EXCESSIVE_COLL_FRAMES 0x140 /* Excessive Collision Frames*/
249 #define CGEM_LATE_COLL 0x144 /* Late Collisions */
250 #define CGEM_DEFERRED_TX_FRAMES 0x148 /* Deferred Transmit Frames */
251 #define CGEM_CARRIER_SENSE_ERRS 0x14C /* Carrier Sense Errors */
252 #define CGEM_OCTETS_RX_BOT 0x150 /* Octets Received [31:0] */
253 #define CGEM_OCTETS_RX_TOP 0x154 /* Octets Received [47:32] */
254 #define CGEM_FRAMES_RX 0x158 /* Frames Received */
255 #define CGEM_BCAST_FRAMES_RX 0x15C /* Broadcast Frames Received */
256 #define CGEM_MULTI_FRAMES_RX 0x160 /* Multicast Frames Received */
257 #define CGEM_PAUSE_FRAMES_RX 0x164 /* Pause Frames Reeived */
258 #define CGEM_FRAMES_64B_RX 0x168 /* 64-Byte Frames Received */
259 #define CGEM_FRAMES_65_127B_RX 0x16C /* 65-127 Byte Frames Rx'd */
260 #define CGEM_FRAMES_128_255B_RX 0x170 /* 128-255 Byte Frames Rx'd */
261 #define CGEM_FRAMES_256_511B_RX 0x174 /* 256-511 Byte Frames Rx'd */
262 #define CGEM_FRAMES_512_1023B_RX 0x178 /* 512-1023 Byte Frames Rx'd */
263 #define CGEM_FRAMES_1024_1518B_RX 0x17C /* 1024-1518 Byte Frames Rx'd*/
264 #define CGEM_UNDERSZ_RX 0x184 /* Undersize Frames Rx'd */
265 #define CGEM_OVERSZ_RX 0x188 /* Oversize Frames Rx'd */
266 #define CGEM_JABBERS_RX 0x18C /* Jabbers received */
267 #define CGEM_FCS_ERRS 0x190 /* Frame Check Sequence Errs */
268 #define CGEM_LENGTH_FIELD_ERRS 0x194 /* Length Firled Frame Errs */
269 #define CGEM_RX_SYMBOL_ERRS 0x198 /* Receive Symbol Errs */
270 #define CGEM_ALIGN_ERRS 0x19C /* Alignment Errors */
271 #define CGEM_RX_RESOURCE_ERRS 0x1A0 /* Receive Resoure Errors */
272 #define CGEM_RX_OVERRUN_ERRS 0x1A4 /* Receive Overrun Errors */
273 #define CGEM_IP_HDR_CKSUM_ERRS 0x1A8 /* IP Hdr Checksum Errors */
274 #define CGEM_TCP_CKSUM_ERRS 0x1AC /* TCP Checksum Errors */
275 #define CGEM_UDP_CKSUM_ERRS 0x1B0 /* UDP Checksum Errors */
276 #define CGEM_TIMER_STROBE_S 0x1C8 /* 1588 timer sync strobe s */
277 #define CGEM_TIMER_STROBE_NS 0x1CC /* timer sync strobe ns */
278 #define CGEM_TIMER_S 0x1D0 /* 1588 timer seconds */
279 #define CGEM_TIMER_NS 0x1D4 /* 1588 timer ns */
280 #define CGEM_ADJUST 0x1D8 /* 1588 timer adjust */
281 #define CGEM_INCR 0x1DC /* 1588 timer increment */
282 #define CGEM_PTP_TX_S 0x1E0 /* PTP Event Frame xmit secs */
283 #define CGEM_PTP_TX_NS 0x1E4 /* PTP Event Frame xmit ns */
284 #define CGEM_PTP_RX_S 0x1E8 /* PTP Event Frame rcv'd s */
285 #define CGEM_PTP_RX_NS 0x1EC /* PTP Event Frame rcv'd ns */
286 #define CGEM_PTP_PEER_TX_S 0x1F0 /* PTP Peer Event xmit s */
287 #define CGEM_PTP_PEER_TX_NS 0x1F4 /* PTP Peer Event xmit ns */
288 #define CGEM_PTP_PEER_RX_S 0x1F8 /* PTP Peer Event rcv'd s */
289 #define CGEM_PTP_PEER_RX_NS 0x1FC /* PTP Peer Event rcv'd ns */
291 #define CGEM_DESIGN_CFG2 0x284 /* Design Configuration 2 */
292 #define CGEM_DESIGN_CFG2_TX_PBUF_ADDR_SHIFT 26
293 #define CGEM_DESIGN_CFG2_TX_PBUF_ADDR_MASK (0xf<<26)
294 #define CGEM_DESIGN_CFG2_RX_PBUF_ADDR_SHIFT 22
295 #define CGEM_DESIGN_CFG2_RX_PBUF_ADDR_MASK (0xf<<22)
296 #define CGEM_DESIGN_CFG2_TX_PKT_BUF (1<<21)
297 #define CGEM_DESIGN_CFG2_RX_PKT_BUF (1<<20)
298 #define CGEM_DESIGN_CFG2_HPROT_VAL_SHIFT 16
299 #define CGEM_DESIGN_CFG2_HPROT_VAL_MASK (0xf<<16)
300 #define CGEM_DESIGN_CFG2_JUMBO_MAX_LEN_MASK 0xffff
302 #define CGEM_DESIGN_CFG3 0x288 /* Design Configuration 3 */
303 #define CGEM_DESIGN_CFG3_RX_BASE2_FIFO_SZ_MASK (0xffff<<16)
304 #define CGEM_DESIGN_CFG3_RX_BASE2_FIFO_SZ_SHIFT 16
305 #define CGEM_DESIGN_CFG3_RX_FIFO_SIZE_MASK 0xffff
307 #define CGEM_DESIGN_CFG4 0x28C /* Design Configuration 4 */
308 #define CGEM_DESIGN_CFG4_TX_BASE2_FIFO_SZ_SHIFT 16
309 #define CGEM_DESIGN_CFG4_TX_BASE2_FIFO_SZ_MASK (0xffff<<16)
310 #define CGEM_DESIGN_CFG4_TX_FIFO_SIZE_MASK 0xffff
312 #define CGEM_DESIGN_CFG5 0x290 /* Design Configuration 5 */
313 #define CGEM_DESIGN_CFG5_TSU_CLK (1<<28)
314 #define CGEM_DESIGN_CFG5_RX_BUF_LEN_DEF_SHIFT 20
315 #define CGEM_DESIGN_CFG5_RX_BUF_LEN_DEF_MASK (0xff<<20)
316 #define CGEM_DESIGN_CFG5_TX_PBUF_SIZE_DEF (1<<19)
317 #define CGEM_DESIGN_CFG5_RX_PBUF_SIZE_DEF_SHIFT 17
318 #define CGEM_DESIGN_CFG5_RX_PBUF_SIZE_DEF_MASK (3<<17)
319 #define CGEM_DESIGN_CFG5_ENDIAN_SWAP_DEF_SHIFT 15
320 #define CGEM_DESIGN_CFG5_ENDIAN_SWAP_DEF_MASK (3<<15)
321 #define CGEM_DESIGN_CFG5_MDC_CLOCK_DIV_SHIFT 12
322 #define CGEM_DESIGN_CFG5_MDC_CLOCK_DIV_MASK (7<<12)
323 #define CGEM_DESIGN_CFG5_DMA_BUS_WIDTH_SHIFT 10
324 #define CGEM_DESIGN_CFG5_DMA_BUS_WIDTH_MASK (3<<10)
325 #define CGEM_DESIGN_CFG5_PHY_IDENT (1<<9)
326 #define CGEM_DESIGN_CFG5_TSU (1<<8)
327 #define CGEM_DESIGN_CFG5_TX_FIFO_CNT_WIDTH_SHIFT 4
328 #define CGEM_DESIGN_CFG5_TX_FIFO_CNT_WIDTH_MASK (0xf<<4)
329 #define CGEM_DESIGN_CFG5_RX_FIFO_CNT_WIDTH_MASK 0xf
331 /* Transmit Descriptors */
332 struct cgem_tx_desc {
335 #define CGEM_TXDESC_USED (1<<31) /* done transmitting */
336 #define CGEM_TXDESC_WRAP (1<<30) /* end of descr ring */
337 #define CGEM_TXDESC_RETRY_ERR (1<<29)
338 #define CGEM_TXDESC_AHB_ERR (1<<27)
339 #define CGEM_TXDESC_LATE_COLL (1<<26)
340 #define CGEM_TXDESC_CKSUM_GEN_STAT_MASK (7<<20)
341 #define CGEM_TXDESC_CKSUM_GEN_STAT_VLAN_HDR_ERR (1<<20)
342 #define CGEM_TXDESC_CKSUM_GEN_STAT_SNAP_HDR_ERR (2<<20)
343 #define CGEM_TXDESC_CKSUM_GEN_STAT_IP_HDR_ERR (3<<20)
344 #define CGEM_TXDESC_CKSUM_GEN_STAT_UNKNOWN_TYPE (4<<20)
345 #define CGEM_TXDESC_CKSUM_GEN_STAT_UNSUPP_FRAG (5<<20)
346 #define CGEM_TXDESC_CKSUM_GEN_STAT_NOT_TCPUDP (6<<20)
347 #define CGEM_TXDESC_CKSUM_GEN_STAT_SHORT_PKT (7<<20)
348 #define CGEM_TXDESC_NO_CRC_APPENDED (1<<16)
349 #define CGEM_TXDESC_LAST_BUF (1<<15) /* last buf in frame */
350 #define CGEM_TXDESC_LENGTH_MASK 0x3fff
353 struct cgem_rx_desc {
355 #define CGEM_RXDESC_WRAP (1<<1) /* goes in addr! */
356 #define CGEM_RXDESC_OWN (1<<0) /* buf filled */
358 #define CGEM_RXDESC_BCAST (1<<31) /* all 1's broadcast */
359 #define CGEM_RXDESC_MULTI_MATCH (1<<30) /* mutlicast match */
360 #define CGEM_RXDESC_UNICAST_MATCH (1<<29)
361 #define CGEM_RXDESC_EXTERNAL_MATCH (1<<28) /* ext addr match */
362 #define CGEM_RXDESC_SPEC_MATCH_SHIFT 25
363 #define CGEM_RXDESC_SPEC_MATCH_MASK (3<<25)
364 #define CGEM_RXDESC_TYPE_ID_MATCH_SHIFT 22
365 #define CGEM_RXDESC_TYPE_ID_MATCH_MASK (3<<22)
366 #define CGEM_RXDESC_CKSUM_STAT_MASK (3<<22) /* same field above */
367 #define CGEM_RXDESC_CKSUM_STAT_NONE (0<<22)
368 #define CGEM_RXDESC_CKSUM_STAT_IP_GOOD (1<<22)
369 #define CGEM_RXDESC_CKSUM_STAT_TCP_GOOD (2<<22) /* and ip good */
370 #define CGEM_RXDESC_CKSUM_STAT_UDP_GOOD (3<<22) /* and ip good */
371 #define CGEM_RXDESC_VLAN_DETECTED (1<<21)
372 #define CGEM_RXDESC_PRIO_DETECTED (1<<20)
373 #define CGEM_RXDESC_VLAN_PRIO_SHIFT 17
374 #define CGEM_RXDESC_VLAN_PRIO_MASK (7<<17)
375 #define CGEM_RXDESC_CFI (1<<16)
376 #define CGEM_RXDESC_EOF (1<<15) /* end of frame */
377 #define CGEM_RXDESC_SOF (1<<14) /* start of frame */
378 #define CGEM_RXDESC_BAD_FCS (1<<13)
379 #define CGEM_RXDESC_LENGTH_MASK 0x1fff
382 #endif /* _IF_CGEM_HW_H_ */