1 /* $NecBSD: ct.c,v 1.13.12.5 2001/06/26 07:31:53 honda Exp $ */
8 #define CT_IO_CONTROL_FLAGS (CT_USE_CCSEQ | CT_FAST_INTR)
11 * [NetBSD for NEC PC-98 series]
12 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
13 * NetBSD/pc98 porting staff. All rights reserved.
15 * Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001
16 * Naofumi HONDA. All rights reserved.
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions
21 * 1. Redistributions of source code must retain the above copyright
22 * notice, this list of conditions and the following disclaimer.
23 * 2. Redistributions in binary form must reproduce the above copyright
24 * notice, this list of conditions and the following disclaimer in the
25 * documentation and/or other materials provided with the distribution.
26 * 3. The name of the author may not be used to endorse or promote products
27 * derived from this software without specific prior written permission.
29 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
30 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
31 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
32 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
33 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
34 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
35 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
36 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
37 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
38 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
39 * POSSIBILITY OF SUCH DAMAGE.
42 #include <sys/param.h>
43 #include <sys/systm.h>
44 #include <sys/kernel.h>
45 #if defined(__FreeBSD__) && __FreeBSD_version > 500001
47 #endif /* __ FreeBSD__ */
49 #include <sys/queue.h>
50 #include <sys/malloc.h>
51 #include <sys/errno.h>
54 #include <sys/device.h>
56 #include <machine/bus.h>
57 #include <machine/intr.h>
59 #include <dev/scsipi/scsi_all.h>
60 #include <dev/scsipi/scsipi_all.h>
61 #include <dev/scsipi/scsiconf.h>
62 #include <dev/scsipi/scsi_disk.h>
64 #include <machine/dvcfg.h>
65 #include <machine/physio_proc.h>
67 #include <i386/Cbus/dev/scsi_low.h>
69 #include <dev/ic/wd33c93reg.h>
70 #include <i386/Cbus/dev/ct/ctvar.h>
71 #include <i386/Cbus/dev/ct/ct_machdep.h>
72 #endif /* __NetBSD__ */
75 #include <machine/bus.h>
77 #include <compat/netbsd/dvcfg.h>
78 #include <compat/netbsd/physio_proc.h>
80 #include <cam/scsi/scsi_low.h>
82 #include <dev/ic/wd33c93reg.h>
83 #include <dev/ct/ctvar.h>
84 #include <dev/ct/ct_machdep.h>
85 #endif /* __FreeBSD__ */
89 #define CT_RESET_DEFAULT 2000
90 #define CT_DELAY_MAX (2 * 1000 * 1000)
91 #define CT_DELAY_INTERVAL (1)
93 /***************************************************
95 ***************************************************/
100 /***************************************************
102 ***************************************************/
103 #define CT_USE_CCSEQ 0x0100
104 #define CT_FAST_INTR 0x0200
106 u_int ct_io_control = CT_IO_CONTROL_FLAGS;
108 /***************************************************
110 ***************************************************/
111 u_int8_t cthw_cmdlevel[256] = {
112 /* 0 1 2 3 4 5 6 7 8 9 A B C E D F */
113 /*0*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 ,
114 /*1*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
115 /*2*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,1 ,0 ,1 ,0 ,0 ,0 ,0 ,0 ,
116 /*3*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
117 /*4*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
118 /*5*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
119 /*6*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
120 /*7*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
121 /*8*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
122 /*9*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
123 /*A*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
124 /*B*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
125 /*C*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
126 /*D*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
127 /*E*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
128 /*F*/0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,0 ,
132 /* default synch data table */
133 /* A 10 6.6 5.0 4.0 3.3 2.8 2.5 2.0 M/s */
134 /* X 100 150 200 250 300 350 400 500 ns */
135 static struct ct_synch_data ct_synch_data_FSCSI[] = {
136 {25, 0xa0}, {37, 0xb0}, {50, 0x20}, {62, 0xd0}, {75, 0x30},
137 {87, 0xf0}, {100, 0x40}, {125, 0x50}, {0, 0}
140 static struct ct_synch_data ct_synch_data_SCSI[] = {
141 {50, 0x20}, {75, 0x30}, {100, 0x40}, {125, 0x50}, {0, 0}
144 /***************************************************
146 ***************************************************/
147 extern struct cfdriver ct_cd;
149 /*****************************************************************
150 * Interface functions
151 *****************************************************************/
152 static int ct_xfer(struct ct_softc *, u_int8_t *, int, int, u_int *);
153 static void ct_io_xfer(struct ct_softc *);
154 static int ct_reselected(struct ct_softc *, u_int8_t);
155 static void ct_phase_error(struct ct_softc *, u_int8_t);
156 static int ct_start_selection(struct ct_softc *, struct slccb *);
157 static int ct_msg(struct ct_softc *, struct targ_info *, u_int);
158 static int ct_world_start(struct ct_softc *, int);
159 static __inline void cthw_phase_bypass(struct ct_softc *, u_int8_t);
160 static int cthw_chip_reset(struct ct_bus_access_handle *, int *, int, int);
161 static void cthw_bus_reset(struct ct_softc *);
162 static int ct_ccb_nexus_establish(struct ct_softc *);
163 static int ct_lun_nexus_establish(struct ct_softc *);
164 static int ct_target_nexus_establish(struct ct_softc *, int, int);
165 static void cthw_attention(struct ct_softc *);
166 static int ct_targ_init(struct ct_softc *, struct targ_info *, int);
167 static int ct_unbusy(struct ct_softc *);
168 static void ct_attention(struct ct_softc *);
169 static struct ct_synch_data *ct_make_synch_table(struct ct_softc *);
170 static int ct_catch_intr(struct ct_softc *);
172 struct scsi_low_funcs ct_funcs = {
173 SC_LOW_INIT_T ct_world_start,
174 SC_LOW_BUSRST_T cthw_bus_reset,
175 SC_LOW_TARG_INIT_T ct_targ_init,
176 SC_LOW_LUN_INIT_T NULL,
178 SC_LOW_SELECT_T ct_start_selection,
179 SC_LOW_NEXUS_T ct_lun_nexus_establish,
180 SC_LOW_NEXUS_T ct_ccb_nexus_establish,
182 SC_LOW_ATTEN_T cthw_attention,
185 SC_LOW_TIMEOUT_T NULL,
186 SC_LOW_POLL_T ctintr,
188 NULL, /* SC_LOW_POWER_T cthw_power, */
191 /**************************************************
193 **************************************************/
195 cthw_phase_bypass(struct ct_softc *ct, u_int8_t ph)
197 struct ct_bus_access_handle *chp = &ct->sc_ch;
199 ct_cr_write_1(chp, wd3s_cph, ph);
200 ct_cr_write_1(chp, wd3s_cmd, WD3S_SELECT_ATN_TFR);
204 cthw_bus_reset(struct ct_softc *ct)
208 * wd33c93 does not have bus reset function.
210 if (ct->ct_bus_reset != NULL)
211 ((*ct->ct_bus_reset) (ct));
215 cthw_chip_reset(struct ct_bus_access_handle *chp, int *chiprevp, int chipclk,
218 #define CT_SELTIMEOUT_20MHz_REGV (0x80)
223 /* issue abort cmd */
224 ct_cr_write_1(chp, wd3s_cmd, WD3S_ABORT);
225 SCSI_LOW_DELAY(1000); /* 1ms wait */
226 (void) ct_stat_read_1(chp);
227 (void) ct_cr_read_1(chp, wd3s_stat);
229 /* setup chip registers */
231 seltout = CT_SELTIMEOUT_20MHz_REGV;
236 seltout = (seltout * chipclk) / 20;
242 seltout = (seltout * chipclk) / 20;
248 seltout = (seltout * chipclk) / 20;
253 panic("ct: illegal chip clk rate");
257 regv |= IDR_EHP | hostid | IDR_RAF | IDR_EAF;
258 ct_cr_write_1(chp, wd3s_oid, regv);
260 ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
261 for (wc = CT_RESET_DEFAULT; wc > 0; wc --)
263 aux = ct_stat_read_1(chp);
264 if (aux != 0xff && (aux & STR_INT))
266 regv = ct_cr_read_1(chp, wd3s_stat);
267 if (regv == BSR_RESET || regv == BSR_AFM_RESET)
270 ct_cr_write_1(chp, wd3s_cmd, WD3S_RESET);
277 ct_cr_write_1(chp, wd3s_tout, seltout);
278 ct_cr_write_1(chp, wd3s_sid, SIDR_RESEL);
279 ct_cr_write_1(chp, wd3s_ctrl, CR_DEFAULT);
280 ct_cr_write_1(chp, wd3s_synch, 0);
281 if (chiprevp != NULL)
283 *chiprevp = CT_WD33C93;
284 if (regv == BSR_RESET)
287 *chiprevp = CT_WD33C93_A;
288 ct_cr_write_1(chp, wd3s_qtag, 0xaa);
289 if (ct_cr_read_1(chp, wd3s_qtag) != 0xaa)
291 ct_cr_write_1(chp, wd3s_qtag, 0x0);
294 ct_cr_write_1(chp, wd3s_qtag, 0x55);
295 if (ct_cr_read_1(chp, wd3s_qtag) != 0x55)
297 ct_cr_write_1(chp, wd3s_qtag, 0x0);
300 ct_cr_write_1(chp, wd3s_qtag, 0x0);
301 *chiprevp = CT_WD33C93_B;
305 (void) ct_stat_read_1(chp);
306 (void) ct_cr_read_1(chp, wd3s_stat);
310 static struct ct_synch_data *
311 ct_make_synch_table(struct ct_softc *ct)
313 struct ct_synch_data *sdtp, *sdp;
314 u_int base, i, period;
316 sdtp = sdp = &ct->sc_default_sdt[0];
318 if ((ct->sc_chipclk % 5) == 0)
319 base = 1000 / (5 * 2); /* 5 MHz type */
321 base = 1000 / (4 * 2); /* 4 MHz type */
323 if (ct->sc_chiprev >= CT_WD33C93_B)
326 for (i = 2; i < 8; i ++, sdp ++)
328 period = (base * i) / 2;
329 if (period >= 200) /* 5 MHz */
331 sdp->cs_period = period / 4;
332 sdp->cs_syncr = (i * 0x10) | 0x80;
336 for (i = 2; i < 8; i ++, sdp ++)
339 if (period > 500) /* 2 MHz */
341 sdp->cs_period = period / 4;
342 sdp->cs_syncr = (i * 0x10);
350 /**************************************************
352 **************************************************/
354 ctprobesubr(struct ct_bus_access_handle *chp, u_int dvcfg, int hsid,
355 u_int chipclk, int *chiprevp)
359 if ((ct_stat_read_1(chp) & STR_BSY) != 0)
362 if (cthw_chip_reset(chp, chiprevp, chipclk, hsid) != 0)
374 printf("%s: scsibus ", name);
379 ctattachsubr(struct ct_softc *ct)
381 struct scsi_low_softc *slp = &ct->sc_sclow;
383 ct->sc_tmaxcnt = SCSI_LOW_MIN_TOUT * 1000 * 1000; /* default */
384 slp->sl_funcs = &ct_funcs;
385 slp->sl_flags |= HW_READ_PADDING;
386 (void) scsi_low_attach(slp, 0, CT_NTARGETS, CT_NLUNS,
387 sizeof(struct ct_targ_info), 0);
390 /**************************************************
391 * SCSI LOW interface functions
392 **************************************************/
394 cthw_attention(struct ct_softc *ct)
396 struct ct_bus_access_handle *chp = &ct->sc_ch;
399 if ((ct_stat_read_1(chp) & (STR_BSY | STR_CIP)) != 0)
402 ct_cr_write_1(chp, wd3s_cmd, WD3S_ASSERT_ATN);
404 if ((ct_stat_read_1(chp) & STR_LCI) == 0)
411 ct_attention(struct ct_softc *ct)
413 struct scsi_low_softc *slp = &ct->sc_sclow;
415 if (slp->sl_atten == 0)
418 scsi_low_attention(slp);
420 else if (ct->sc_atten != 0)
428 ct_targ_init(struct ct_softc *ct, struct targ_info *ti, int action)
430 struct ct_targ_info *cti = (void *) ti;
432 if (action == SCSI_LOW_INFO_ALLOC || action == SCSI_LOW_INFO_REVOKE)
434 if (ct->sc_sdp == NULL)
436 ct->sc_sdp = ct_make_synch_table(ct);
439 switch (ct->sc_chiprev)
442 ti->ti_maxsynch.offset = 5;
447 ti->ti_maxsynch.offset = 12;
452 ti->ti_maxsynch.offset = 12;
456 ti->ti_maxsynch.period = ct->sc_sdp[0].cs_period;
457 ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
458 cti->cti_syncreg = 0;
465 ct_world_start(struct ct_softc *ct, int fdone)
467 struct scsi_low_softc *slp = &ct->sc_sclow;
468 struct ct_bus_access_handle *chp = &ct->sc_ch;
470 if (ct->sc_sdp == NULL)
472 ct->sc_sdp = ct_make_synch_table(ct);
475 if (slp->sl_cfgflags & CFG_NOPARITY)
476 ct->sc_creg = CR_DEFAULT;
478 ct->sc_creg = CR_DEFAULT_HP;
480 if (ct->sc_dma & CT_DMA_DMASTART)
481 (*ct->ct_dma_xfer_stop) (ct);
482 if (ct->sc_dma & CT_DMA_PIOSTART)
483 (*ct->ct_pio_xfer_stop) (ct);
487 cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
488 scsi_low_bus_reset(slp);
489 cthw_chip_reset(chp, NULL, ct->sc_chipclk, slp->sl_hostid);
491 SOFT_INTR_REQUIRED(slp);
496 ct_start_selection(struct ct_softc *ct, struct slccb *cb)
498 struct scsi_low_softc *slp = &ct->sc_sclow;
499 struct ct_bus_access_handle *chp = &ct->sc_ch;
501 struct targ_info *ti = slp->sl_Tnexus;
502 struct lun_info *li = slp->sl_Lnexus;
506 ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
510 if (scsi_low_is_disconnect_ok(cb) != 0)
512 if (ct->sc_chiprev >= CT_WD33C93_A)
514 else if (cthw_cmdlevel[slp->sl_scp.scp_cmd[0]] != 0)
519 scsi_low_is_msgout_continue(ti, SCSI_LOW_MSG_IDENTIFY) == 0)
521 cmd = WD3S_SELECT_ATN_TFR;
522 ct->sc_satgo = CT_SAT_GOING;
526 cmd = WD3S_SELECT_ATN;
530 if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) != 0)
531 return SCSI_LOW_START_FAIL;
533 if ((ct->sc_satgo & CT_SAT_GOING) != 0)
535 (void) scsi_low_msgout(slp, ti, SCSI_LOW_MSGOUT_INIT);
536 scsi_low_cmd(slp, ti);
537 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
538 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
542 /* anyway attention assert */
543 SCSI_LOW_ASSERT_ATN(slp);
546 ct_target_nexus_establish(ct, li->li_lun, slp->sl_scp.scp_direction);
549 if ((ct_stat_read_1(chp) & (STR_BSY | STR_INT | STR_CIP)) == 0)
552 * Reload a lun again here.
554 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
555 ct_cr_write_1(chp, wd3s_cmd, cmd);
556 if ((ct_stat_read_1(chp) & STR_LCI) == 0)
559 SCSI_LOW_SETUP_PHASE(ti, PH_SELSTART);
560 return SCSI_LOW_START_OK;
564 return SCSI_LOW_START_FAIL;
568 ct_msg(struct ct_softc *ct, struct targ_info *ti, u_int msg)
570 struct ct_bus_access_handle *chp = &ct->sc_ch;
571 struct ct_targ_info *cti = (void *) ti;
572 struct ct_synch_data *csp = ct->sc_sdp;
573 u_int offset, period;
576 if ((msg & SCSI_LOW_MSG_WIDE) != 0)
578 if (ti->ti_width != SCSI_LOW_BUS_WIDTH_8)
580 ti->ti_width = SCSI_LOW_BUS_WIDTH_8;
586 if ((msg & SCSI_LOW_MSG_SYNCH) == 0)
589 offset = ti->ti_maxsynch.offset;
590 period = ti->ti_maxsynch.period;
591 for ( ; csp->cs_period != 0; csp ++)
593 if (period == csp->cs_period)
597 if (ti->ti_maxsynch.period != 0 && csp->cs_period == 0)
599 ti->ti_maxsynch.period = 0;
600 ti->ti_maxsynch.offset = 0;
601 cti->cti_syncreg = 0;
606 cti->cti_syncreg = ((offset & 0x0f) | csp->cs_syncr);
610 if (ct->ct_synch_setup != 0)
611 (*ct->ct_synch_setup) (ct, ti);
612 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
616 /*************************************************
618 *************************************************/
620 ct_xfer(struct ct_softc *ct, u_int8_t *data, int len, int direction,
623 struct ct_bus_access_handle *chp = &ct->sc_ch;
625 register u_int8_t aux;
630 ct_cr_write_1(chp, wd3s_cmd, WD3S_SBT | WD3S_TFR_INFO);
634 cthw_set_count(chp, len);
635 ct_cr_write_1(chp, wd3s_cmd, WD3S_TFR_INFO);
638 aux = ct_stat_read_1(chp);
639 if ((aux & STR_LCI) != 0)
641 cthw_set_count(chp, 0);
645 for (wc = 0; wc < ct->sc_tmaxcnt; wc ++)
647 /* check data ready */
648 if ((aux & (STR_BSY | STR_DBR)) == (STR_BSY | STR_DBR))
650 if (direction == SCSI_LOW_READ)
652 *data = ct_cr_read_1(chp, wd3s_data);
653 if ((aux & STR_PE) != 0)
654 *statp |= SCSI_LOW_DATA_PE;
658 ct_cr_write_1(chp, wd3s_data, *data);
670 /* check phase miss */
671 aux = ct_stat_read_1(chp);
672 if ((aux & STR_INT) != 0)
678 #define CT_PADDING_BUF_SIZE 32
681 ct_io_xfer(struct ct_softc *ct)
683 struct scsi_low_softc *slp = &ct->sc_sclow;
684 struct ct_bus_access_handle *chp = &ct->sc_ch;
685 struct sc_p *sp = &slp->sl_scp;
688 u_int8_t pbuf[CT_PADDING_BUF_SIZE];
691 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg);
693 if (sp->scp_datalen <= 0)
695 slp->sl_error |= PDMAERR;
697 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
698 SCSI_LOW_BZERO(pbuf, CT_PADDING_BUF_SIZE);
699 ct_xfer(ct, pbuf, CT_PADDING_BUF_SIZE,
700 sp->scp_direction, &stat);
704 len = ct_xfer(ct, sp->scp_data, sp->scp_datalen,
705 sp->scp_direction, &stat);
706 sp->scp_data += (sp->scp_datalen - len);
707 sp->scp_datalen = len;
711 /**************************************************
713 **************************************************/
721 struct ct_err ct_cmderr[] = {
722 /*0*/ { "illegal cmd", FATALIO, SCSI_LOW_MSG_ABORT, 1},
723 /*1*/ { "unexpected bus free", FATALIO, 0, 1},
724 /*2*/ { NULL, SELTIMEOUTIO, 0, 1},
725 /*3*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
726 /*4*/ { "scsi bus parity error", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
727 /*5*/ { "unknown" , FATALIO, SCSI_LOW_MSG_ABORT, 1},
728 /*6*/ { "miss reselection (target mode)", FATALIO, SCSI_LOW_MSG_ABORT, 0},
729 /*7*/ { "wrong status byte", PARITYERR, SCSI_LOW_MSG_ERROR, 0},
733 ct_phase_error(struct ct_softc *ct, u_int8_t scsi_status)
735 struct scsi_low_softc *slp = &ct->sc_sclow;
736 struct targ_info *ti = slp->sl_Tnexus;
740 if ((scsi_status & BSR_CM) == BSR_CMDERR &&
741 (scsi_status & BSR_PHVALID) == 0)
743 pep = &ct_cmderr[scsi_status & BSR_PM];
744 slp->sl_error |= pep->pe_err;
745 if ((pep->pe_err & PARITYERR) != 0)
747 if (ti->ti_phase == PH_MSGIN)
748 msg = SCSI_LOW_MSG_PARITY;
750 msg = SCSI_LOW_MSG_ERROR;
753 msg = pep->pe_errmsg;
756 scsi_low_assert_msg(slp, slp->sl_Tnexus, msg, 1);
758 if (pep->pe_msg != NULL)
760 printf("%s: phase error: %s",
761 slp->sl_xname, pep->pe_msg);
762 scsi_low_print(slp, slp->sl_Tnexus);
765 if (pep->pe_done != 0)
766 scsi_low_disconnected(slp, ti);
770 slp->sl_error |= FATALIO;
771 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD, "phase error");
775 /**************************************************
776 * ### SCSI PHASE SEQUENCER ###
777 **************************************************/
779 ct_reselected(struct ct_softc *ct, u_int8_t scsi_status)
781 struct scsi_low_softc *slp = &ct->sc_sclow;
782 struct ct_bus_access_handle *chp = &ct->sc_ch;
783 struct targ_info *ti;
788 ct->sc_satgo &= ~CT_SAT_GOING;
789 regv = ct_cr_read_1(chp, wd3s_sid);
790 if ((regv & SIDR_VALID) == 0)
793 sid = regv & SIDR_IDM;
794 if ((ti = scsi_low_reselected(slp, sid)) == NULL)
797 ct_target_nexus_establish(ct, 0, SCSI_LOW_READ);
798 if (scsi_status != BSR_AFM_RESEL)
801 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
802 regv = ct_cr_read_1(chp, wd3s_data);
803 if (scsi_low_msgin(slp, ti, (u_int) regv) == 0)
805 if (scsi_low_is_msgout_continue(ti, 0) != 0)
807 /* XXX: scsi_low_attetion */
808 scsi_low_attention(slp);
812 if (ct->sc_atten != 0)
817 ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
822 ct_target_nexus_establish(struct ct_softc *ct, int lun, int dir)
824 struct scsi_low_softc *slp = &ct->sc_sclow;
825 struct ct_bus_access_handle *chp = &ct->sc_ch;
826 struct targ_info *ti = slp->sl_Tnexus;
827 struct ct_targ_info *cti = (void *) ti;
829 if (dir == SCSI_LOW_WRITE)
830 ct_cr_write_1(chp, wd3s_did, ti->ti_id);
832 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
833 ct_cr_write_1(chp, wd3s_lun, lun);
834 ct_cr_write_1(chp, wd3s_ctrl, ct->sc_creg | CR_DMA);
835 ct_cr_write_1(chp, wd3s_cph, 0);
836 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
837 cthw_set_count(chp, 0);
842 ct_lun_nexus_establish(struct ct_softc *ct)
844 struct scsi_low_softc *slp = &ct->sc_sclow;
845 struct ct_bus_access_handle *chp = &ct->sc_ch;
846 struct lun_info *li = slp->sl_Lnexus;
848 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
853 ct_ccb_nexus_establish(struct ct_softc *ct)
855 struct scsi_low_softc *slp = &ct->sc_sclow;
856 struct ct_bus_access_handle *chp = &ct->sc_ch;
857 struct lun_info *li = slp->sl_Lnexus;
858 struct targ_info *ti = slp->sl_Tnexus;
859 struct ct_targ_info *cti = (void *) ti;
860 struct slccb *cb = slp->sl_Qnexus;
862 ct->sc_tmaxcnt = cb->ccb_tcmax * 1000 * 1000;
864 if ((ct->sc_satgo & CT_SAT_GOING) != 0)
866 ct_cr_write_1(chp, wd3s_oid, slp->sl_scp.scp_cmdlen);
867 ct_write_cmds(chp, slp->sl_scp.scp_cmd, slp->sl_scp.scp_cmdlen);
869 if (slp->sl_scp.scp_direction == SCSI_LOW_WRITE)
870 ct_cr_write_1(chp, wd3s_did, ti->ti_id);
872 ct_cr_write_1(chp, wd3s_did, ti->ti_id | DIDR_DPD);
873 ct_cr_write_1(chp, wd3s_lun, li->li_lun);
874 ct_cr_write_1(chp, wd3s_synch, cti->cti_syncreg);
879 ct_unbusy(struct ct_softc *ct)
881 struct scsi_low_softc *slp = &ct->sc_sclow;
882 struct ct_bus_access_handle *chp = &ct->sc_ch;
884 register u_int8_t regv;
886 for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
888 regv = ct_stat_read_1(chp);
889 if ((regv & (STR_BSY | STR_CIP)) == 0)
891 if (regv == (u_int8_t) -1)
894 SCSI_LOW_DELAY(CT_DELAY_INTERVAL);
897 printf("%s: unbusy timeout\n", slp->sl_xname);
902 ct_catch_intr(struct ct_softc *ct)
904 struct ct_bus_access_handle *chp = &ct->sc_ch;
906 register u_int8_t regv;
908 for (wc = 0; wc < CT_DELAY_MAX / CT_DELAY_INTERVAL; wc ++)
910 regv = ct_stat_read_1(chp);
911 if ((regv & (STR_INT | STR_BSY | STR_CIP)) == STR_INT)
914 SCSI_LOW_DELAY(CT_DELAY_INTERVAL);
922 struct ct_softc *ct = arg;
923 struct scsi_low_softc *slp = &ct->sc_sclow;
924 struct ct_bus_access_handle *chp = &ct->sc_ch;
925 struct targ_info *ti;
926 struct physio_proc *pp;
929 int len, satgo, error;
930 u_int8_t scsi_status, regv;
933 if (slp->sl_flags & HW_INACTIVE)
936 /**************************************************
937 * Get status & bus phase
938 **************************************************/
939 if ((ct_stat_read_1(chp) & STR_INT) == 0)
942 scsi_status = ct_cr_read_1(chp, wd3s_stat);
943 if (scsi_status == ((u_int8_t) -1))
946 /**************************************************
947 * Check reselection, or nexus
948 **************************************************/
949 if (scsi_status == BSR_RESEL || scsi_status == BSR_AFM_RESEL)
951 if (ct_reselected(ct, scsi_status) == EJUSTRETURN)
955 if ((ti = slp->sl_Tnexus) == NULL)
958 /**************************************************
960 **************************************************/
964 scsi_low_print(slp, NULL);
965 printf("%s: scsi_status 0x%x\n\n", slp->sl_xname,
966 (u_int) scsi_status);
969 SCSI_LOW_DEBUGGER("ct");
972 #endif /* CT_DEBUG */
974 /**************************************************
975 * Internal scsi phase
976 **************************************************/
977 satgo = ct->sc_satgo;
978 ct->sc_satgo &= ~CT_SAT_GOING;
980 switch (ti->ti_phase)
983 if ((satgo & CT_SAT_GOING) == 0)
985 if (scsi_status != BSR_SELECTED)
987 ct_phase_error(ct, scsi_status);
990 scsi_low_arbit_win(slp);
991 SCSI_LOW_SETUP_PHASE(ti, PH_SELECTED);
996 scsi_low_arbit_win(slp);
997 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT); /* XXX */
1002 if ((scsi_status & BSR_PHVALID) == 0 ||
1003 (scsi_status & BSR_PM) != BSR_MSGIN)
1005 scsi_low_restart(slp, SCSI_LOW_RESTART_HARD,
1006 "phase miss after reselect");
1012 if (slp->sl_flags & HW_PDMASTART)
1014 slp->sl_flags &= ~HW_PDMASTART;
1015 if (ct->sc_dma & CT_DMA_DMASTART)
1017 (*ct->ct_dma_xfer_stop) (ct);
1018 ct->sc_dma &= ~CT_DMA_DMASTART;
1020 else if (ct->sc_dma & CT_DMA_PIOSTART)
1022 (*ct->ct_pio_xfer_stop) (ct);
1023 ct->sc_dma &= ~CT_DMA_PIOSTART;
1027 scsi_low_data_finish(slp);
1033 /**************************************************
1035 **************************************************/
1036 if (scsi_status & BSR_PHVALID)
1038 /**************************************************
1039 * Normal SCSI phase.
1040 **************************************************/
1041 if ((scsi_status & BSR_CM) == BSR_CMDABT)
1043 ct_phase_error(ct, scsi_status);
1047 switch (scsi_status & BSR_PM)
1050 SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
1051 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_WRITE) != 0)
1055 goto common_data_phase;
1058 SCSI_LOW_SETUP_PHASE(ti, PH_DATA);
1059 if (scsi_low_data(slp, ti, &bp, SCSI_LOW_READ) != 0)
1065 if (slp->sl_scp.scp_datalen > 0)
1067 slp->sl_flags |= HW_PDMASTART;
1068 if ((ct->sc_xmode & CT_XMODE_PIO) != 0)
1070 pp = physio_proc_enter(bp);
1071 error = (*ct->ct_pio_xfer_start) (ct);
1072 physio_proc_leave(pp);
1075 ct->sc_dma |= CT_DMA_PIOSTART;
1080 if ((ct->sc_xmode & CT_XMODE_DMA) != 0)
1082 error = (*ct->ct_dma_xfer_start) (ct);
1085 ct->sc_dma |= CT_DMA_DMASTART;
1092 if (slp->sl_scp.scp_direction == SCSI_LOW_READ)
1094 if (!(slp->sl_flags & HW_READ_PADDING))
1096 printf("%s: read padding required\n", slp->sl_xname);
1102 if (!(slp->sl_flags & HW_WRITE_PADDING))
1104 printf("%s: write padding required\n", slp->sl_xname);
1108 slp->sl_flags |= HW_PDMASTART;
1115 SCSI_LOW_SETUP_PHASE(ti, PH_CMD);
1116 if (scsi_low_cmd(slp, ti) != 0)
1121 if (ct_xfer(ct, slp->sl_scp.scp_cmd,
1122 slp->sl_scp.scp_cmdlen,
1123 SCSI_LOW_WRITE, &derror) != 0)
1125 printf("%s: scsi cmd xfer short\n",
1131 SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
1132 if ((ct_io_control & CT_USE_CCSEQ) != 0)
1134 if (scsi_low_is_msgout_continue(ti, 0) != 0 ||
1137 ct_xfer(ct, ®v, 1, SCSI_LOW_READ,
1139 scsi_low_statusin(slp, ti,
1144 ct->sc_satgo |= CT_SAT_GOING;
1145 cthw_set_count(chp, 0);
1146 cthw_phase_bypass(ct, 0x41);
1151 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror);
1152 scsi_low_statusin(slp, ti, regv | derror);
1158 printf("%s: illegal bus phase (0x%x)\n", slp->sl_xname,
1159 (u_int) scsi_status);
1160 scsi_low_print(slp, ti);
1164 SCSI_LOW_SETUP_PHASE(ti, PH_MSGOUT);
1165 flags = SCSI_LOW_MSGOUT_UNIFY;
1166 if (ti->ti_ophase != ti->ti_phase)
1167 flags |= SCSI_LOW_MSGOUT_INIT;
1168 len = scsi_low_msgout(slp, ti, flags);
1170 if (len > 1 && slp->sl_atten == 0)
1175 if (ct_xfer(ct, ti->ti_msgoutstr, len,
1176 SCSI_LOW_WRITE, &derror) != 0)
1178 printf("%s: scsi msgout xfer short\n",
1181 SCSI_LOW_DEASSERT_ATN(slp);
1185 case BSR_MSGIN:/* msg in */
1186 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1188 ct_xfer(ct, ®v, 1, SCSI_LOW_READ, &derror);
1189 if (scsi_low_msgin(slp, ti, regv | derror) == 0)
1191 if (scsi_low_is_msgout_continue(ti, 0) != 0)
1193 /* XXX: scsi_low_attetion */
1194 scsi_low_attention(slp);
1198 if ((ct_io_control & CT_FAST_INTR) != 0)
1200 if (ct_catch_intr(ct) == 0)
1208 /**************************************************
1209 * Special SCSI phase
1210 **************************************************/
1211 switch (scsi_status)
1213 case BSR_SATSDP: /* SAT with save data pointer */
1214 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1215 ct->sc_satgo |= CT_SAT_GOING;
1216 scsi_low_msgin(slp, ti, MSG_SAVESP);
1217 cthw_phase_bypass(ct, 0x41);
1220 case BSR_SATFIN: /* SAT COMPLETE */
1222 * emulate statusin => msgin
1224 SCSI_LOW_SETUP_PHASE(ti, PH_STAT);
1225 scsi_low_statusin(slp, ti, ct_cr_read_1(chp, wd3s_lun));
1227 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1228 scsi_low_msgin(slp, ti, MSG_COMP);
1230 scsi_low_disconnected(slp, ti);
1233 case BSR_ACKREQ: /* negate ACK */
1234 if (ct->sc_atten != 0)
1239 ct_cr_write_1(chp, wd3s_cmd, WD3S_NEGATE_ACK);
1240 if ((ct_io_control & CT_FAST_INTR) != 0)
1243 * Should clear a pending interrupt and
1244 * sync with a next interrupt!
1250 case BSR_DISC: /* disconnect */
1251 if (slp->sl_msgphase == MSGPH_NULL &&
1252 (satgo & CT_SAT_GOING) != 0)
1255 * emulate disconnect msg
1257 SCSI_LOW_SETUP_PHASE(ti, PH_MSGIN);
1258 scsi_low_msgin(slp, ti, MSG_DISCON);
1260 scsi_low_disconnected(slp, ti);
1268 ct_phase_error(ct, scsi_status);