1 /**************************************************************************
3 Copyright (c) 2007-2009, Chelsio Inc.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
28 ***************************************************************************/
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/pciio.h>
40 #include <machine/bus.h>
41 #include <machine/resource.h>
42 #include <sys/bus_dma.h>
45 #include <sys/ioccom.h>
47 #include <sys/linker.h>
48 #include <sys/firmware.h>
49 #include <sys/socket.h>
50 #include <sys/sockio.h>
52 #include <sys/sysctl.h>
53 #include <sys/syslog.h>
54 #include <sys/queue.h>
55 #include <sys/taskqueue.h>
59 #include <net/ethernet.h>
61 #include <net/if_arp.h>
62 #include <net/if_dl.h>
63 #include <net/if_media.h>
64 #include <net/if_types.h>
65 #include <net/if_vlan_var.h>
67 #include <netinet/in_systm.h>
68 #include <netinet/in.h>
69 #include <netinet/if_ether.h>
70 #include <netinet/ip.h>
71 #include <netinet/ip.h>
72 #include <netinet/tcp.h>
73 #include <netinet/udp.h>
75 #include <dev/pci/pcireg.h>
76 #include <dev/pci/pcivar.h>
77 #include <dev/pci/pci_private.h>
79 #include <cxgb_include.h>
85 static int cxgb_setup_interrupts(adapter_t *);
86 static void cxgb_teardown_interrupts(adapter_t *);
87 static int cxgb_begin_op(struct port_info *, const char *);
88 static int cxgb_begin_detach(struct port_info *);
89 static int cxgb_end_op(struct port_info *);
90 static void cxgb_init(void *);
91 static int cxgb_init_synchronized(struct port_info *);
92 static int cxgb_uninit_synchronized(struct port_info *);
93 static int cxgb_ioctl(struct ifnet *, unsigned long, caddr_t);
94 static int cxgb_media_change(struct ifnet *);
95 static int cxgb_ifm_type(int);
96 static void cxgb_build_medialist(struct port_info *);
97 static void cxgb_media_status(struct ifnet *, struct ifmediareq *);
98 static int setup_sge_qsets(adapter_t *);
99 static void cxgb_async_intr(void *);
100 static void cxgb_ext_intr_handler(void *, int);
101 static void cxgb_tick_handler(void *, int);
102 static void cxgb_tick(void *);
103 static void setup_rss(adapter_t *sc);
105 /* Attachment glue for the PCI controller end of the device. Each port of
106 * the device is attached separately, as defined later.
108 static int cxgb_controller_probe(device_t);
109 static int cxgb_controller_attach(device_t);
110 static int cxgb_controller_detach(device_t);
111 static void cxgb_free(struct adapter *);
112 static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start,
114 static void cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf);
115 static int cxgb_get_regs_len(void);
116 static int offload_open(struct port_info *pi);
117 static void touch_bars(device_t dev);
118 static int offload_close(struct t3cdev *tdev);
119 static void cxgb_update_mac_settings(struct port_info *p);
121 static device_method_t cxgb_controller_methods[] = {
122 DEVMETHOD(device_probe, cxgb_controller_probe),
123 DEVMETHOD(device_attach, cxgb_controller_attach),
124 DEVMETHOD(device_detach, cxgb_controller_detach),
127 DEVMETHOD(bus_print_child, bus_generic_print_child),
128 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
133 static driver_t cxgb_controller_driver = {
135 cxgb_controller_methods,
136 sizeof(struct adapter)
139 static devclass_t cxgb_controller_devclass;
140 DRIVER_MODULE(cxgbc, pci, cxgb_controller_driver, cxgb_controller_devclass, 0, 0);
143 * Attachment glue for the ports. Attachment is done directly to the
146 static int cxgb_port_probe(device_t);
147 static int cxgb_port_attach(device_t);
148 static int cxgb_port_detach(device_t);
150 static device_method_t cxgb_port_methods[] = {
151 DEVMETHOD(device_probe, cxgb_port_probe),
152 DEVMETHOD(device_attach, cxgb_port_attach),
153 DEVMETHOD(device_detach, cxgb_port_detach),
157 static driver_t cxgb_port_driver = {
163 static d_ioctl_t cxgb_extension_ioctl;
164 static d_open_t cxgb_extension_open;
165 static d_close_t cxgb_extension_close;
167 static struct cdevsw cxgb_cdevsw = {
168 .d_version = D_VERSION,
170 .d_open = cxgb_extension_open,
171 .d_close = cxgb_extension_close,
172 .d_ioctl = cxgb_extension_ioctl,
176 static devclass_t cxgb_port_devclass;
177 DRIVER_MODULE(cxgb, cxgbc, cxgb_port_driver, cxgb_port_devclass, 0, 0);
180 * The driver uses the best interrupt scheme available on a platform in the
181 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
182 * of these schemes the driver may consider as follows:
184 * msi = 2: choose from among all three options
185 * msi = 1 : only consider MSI and pin interrupts
186 * msi = 0: force pin interrupts
188 static int msi_allowed = 2;
190 TUNABLE_INT("hw.cxgb.msi_allowed", &msi_allowed);
191 SYSCTL_NODE(_hw, OID_AUTO, cxgb, CTLFLAG_RD, 0, "CXGB driver parameters");
192 SYSCTL_UINT(_hw_cxgb, OID_AUTO, msi_allowed, CTLFLAG_RDTUN, &msi_allowed, 0,
193 "MSI-X, MSI, INTx selector");
196 * The driver enables offload as a default.
197 * To disable it, use ofld_disable = 1.
199 static int ofld_disable = 0;
200 TUNABLE_INT("hw.cxgb.ofld_disable", &ofld_disable);
201 SYSCTL_UINT(_hw_cxgb, OID_AUTO, ofld_disable, CTLFLAG_RDTUN, &ofld_disable, 0,
202 "disable ULP offload");
205 * The driver uses an auto-queue algorithm by default.
206 * To disable it and force a single queue-set per port, use multiq = 0
208 static int multiq = 1;
209 TUNABLE_INT("hw.cxgb.multiq", &multiq);
210 SYSCTL_UINT(_hw_cxgb, OID_AUTO, multiq, CTLFLAG_RDTUN, &multiq, 0,
211 "use min(ncpus/ports, 8) queue-sets per port");
214 * By default the driver will not update the firmware unless
215 * it was compiled against a newer version
218 static int force_fw_update = 0;
219 TUNABLE_INT("hw.cxgb.force_fw_update", &force_fw_update);
220 SYSCTL_UINT(_hw_cxgb, OID_AUTO, force_fw_update, CTLFLAG_RDTUN, &force_fw_update, 0,
221 "update firmware even if up to date");
223 int cxgb_use_16k_clusters = 1;
224 TUNABLE_INT("hw.cxgb.use_16k_clusters", &cxgb_use_16k_clusters);
225 SYSCTL_UINT(_hw_cxgb, OID_AUTO, use_16k_clusters, CTLFLAG_RDTUN,
226 &cxgb_use_16k_clusters, 0, "use 16kB clusters for the jumbo queue ");
229 * Tune the size of the output queue.
231 int cxgb_snd_queue_len = IFQ_MAXLEN;
232 TUNABLE_INT("hw.cxgb.snd_queue_len", &cxgb_snd_queue_len);
233 SYSCTL_UINT(_hw_cxgb, OID_AUTO, snd_queue_len, CTLFLAG_RDTUN,
234 &cxgb_snd_queue_len, 0, "send queue size ");
238 MAX_TXQ_ENTRIES = 16384,
239 MAX_CTRL_TXQ_ENTRIES = 1024,
240 MAX_RSPQ_ENTRIES = 16384,
241 MAX_RX_BUFFERS = 16384,
242 MAX_RX_JUMBO_BUFFERS = 16384,
244 MIN_CTRL_TXQ_ENTRIES = 4,
245 MIN_RSPQ_ENTRIES = 32,
247 MIN_FL_JUMBO_ENTRIES = 32
262 u32 report_filter_id:1;
270 enum { FILTER_NO_VLAN_PRI = 7 };
272 #define EEPROM_MAGIC 0x38E2F10C
274 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
276 /* Table for probing the cards. The desc field isn't actually used */
282 } cxgb_identifiers[] = {
283 {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"},
284 {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"},
285 {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"},
286 {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"},
287 {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"},
288 {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"},
289 {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"},
290 {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"},
291 {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"},
292 {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"},
293 {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"},
294 {PCI_VENDOR_ID_CHELSIO, 0x0035, 6, "T3C10"},
295 {PCI_VENDOR_ID_CHELSIO, 0x0036, 3, "S320E-CR"},
296 {PCI_VENDOR_ID_CHELSIO, 0x0037, 7, "N320E-G2"},
300 static int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset);
304 t3rev2char(struct adapter *adapter)
308 switch(adapter->params.rev) {
323 static struct cxgb_ident *
324 cxgb_get_ident(device_t dev)
326 struct cxgb_ident *id;
328 for (id = cxgb_identifiers; id->desc != NULL; id++) {
329 if ((id->vendor == pci_get_vendor(dev)) &&
330 (id->device == pci_get_device(dev))) {
337 static const struct adapter_info *
338 cxgb_get_adapter_info(device_t dev)
340 struct cxgb_ident *id;
341 const struct adapter_info *ai;
343 id = cxgb_get_ident(dev);
347 ai = t3_get_adapter_info(id->index);
353 cxgb_controller_probe(device_t dev)
355 const struct adapter_info *ai;
356 char *ports, buf[80];
359 ai = cxgb_get_adapter_info(dev);
363 nports = ai->nports0 + ai->nports1;
369 snprintf(buf, sizeof(buf), "%s, %d %s", ai->desc, nports, ports);
370 device_set_desc_copy(dev, buf);
371 return (BUS_PROBE_DEFAULT);
374 #define FW_FNAME "cxgb_t3fw"
375 #define TPEEPROM_NAME "cxgb_t3%c_tp_eeprom"
376 #define TPSRAM_NAME "cxgb_t3%c_protocol_sram"
379 upgrade_fw(adapter_t *sc)
381 #ifdef FIRMWARE_LATEST
382 const struct firmware *fw;
388 if ((fw = firmware_get(FW_FNAME)) == NULL) {
389 device_printf(sc->dev, "Could not find firmware image %s\n", FW_FNAME);
392 device_printf(sc->dev, "updating firmware on card\n");
393 status = t3_load_fw(sc, (const uint8_t *)fw->data, fw->datasize);
395 device_printf(sc->dev, "firmware update returned %s %d\n", (status == 0) ? "success" : "fail", status);
397 firmware_put(fw, FIRMWARE_UNLOAD);
403 * The cxgb_controller_attach function is responsible for the initial
404 * bringup of the device. Its responsibilities include:
406 * 1. Determine if the device supports MSI or MSI-X.
407 * 2. Allocate bus resources so that we can access the Base Address Register
408 * 3. Create and initialize mutexes for the controller and its control
409 * logic such as SGE and MDIO.
410 * 4. Call hardware specific setup routine for the adapter as a whole.
411 * 5. Allocate the BAR for doing MSI-X.
412 * 6. Setup the line interrupt iff MSI-X is not supported.
413 * 7. Create the driver's taskq.
414 * 8. Start one task queue service thread.
415 * 9. Check if the firmware and SRAM are up-to-date. They will be
416 * auto-updated later (before FULL_INIT_DONE), if required.
417 * 10. Create a child device for each MAC (port)
418 * 11. Initialize T3 private state.
419 * 12. Trigger the LED
420 * 13. Setup offload iff supported.
421 * 14. Reset/restart the tick callout.
424 * NOTE: Any modification or deviation from this list MUST be reflected in
425 * the above comment. Failure to do so will result in problems on various
426 * error conditions including link flapping.
429 cxgb_controller_attach(device_t dev)
432 const struct adapter_info *ai;
442 sc = device_get_softc(dev);
445 ai = cxgb_get_adapter_info(dev);
448 * XXX not really related but a recent addition
451 /* find the PCIe link width and set max read request to 4KB*/
452 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
454 lnk = pci_read_config(dev, reg + 0x12, 2);
455 sc->link_width = (lnk >> 4) & 0x3f;
457 pectl = pci_read_config(dev, reg + 0x8, 2);
458 pectl = (pectl & ~0x7000) | (5 << 12);
459 pci_write_config(dev, reg + 0x8, pectl, 2);
462 if (sc->link_width != 0 && sc->link_width <= 4 &&
463 (ai->nports0 + ai->nports1) <= 2) {
464 device_printf(sc->dev,
465 "PCIe x%d Link, expect reduced performance\n",
470 pci_enable_busmaster(dev);
472 * Allocate the registers and make them available to the driver.
473 * The registers that we care about for NIC mode are in BAR 0
475 sc->regs_rid = PCIR_BAR(0);
476 if ((sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
477 &sc->regs_rid, RF_ACTIVE)) == NULL) {
478 device_printf(dev, "Cannot allocate BAR region 0\n");
481 sc->udbs_rid = PCIR_BAR(2);
483 if (is_offload(sc) &&
484 ((sc->udbs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
485 &sc->udbs_rid, RF_ACTIVE)) == NULL)) {
486 device_printf(dev, "Cannot allocate BAR region 1\n");
491 snprintf(sc->lockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb controller lock %d",
492 device_get_unit(dev));
493 ADAPTER_LOCK_INIT(sc, sc->lockbuf);
495 snprintf(sc->reglockbuf, ADAPTER_LOCK_NAME_LEN, "SGE reg lock %d",
496 device_get_unit(dev));
497 snprintf(sc->mdiolockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb mdio lock %d",
498 device_get_unit(dev));
499 snprintf(sc->elmerlockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb elmer lock %d",
500 device_get_unit(dev));
502 MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_SPIN);
503 MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF);
504 MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF);
506 sc->bt = rman_get_bustag(sc->regs_res);
507 sc->bh = rman_get_bushandle(sc->regs_res);
508 sc->mmio_len = rman_get_size(sc->regs_res);
510 for (i = 0; i < MAX_NPORTS; i++)
511 sc->port[i].adapter = sc;
513 if (t3_prep_adapter(sc, ai, 1) < 0) {
514 printf("prep adapter failed\n");
518 /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate
519 * enough messages for the queue sets. If that fails, try falling
520 * back to MSI. If that fails, then try falling back to the legacy
521 * interrupt pin model.
525 sc->msix_regs_rid = 0x20;
526 if ((msi_allowed >= 2) &&
527 (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
528 &sc->msix_regs_rid, RF_ACTIVE)) != NULL) {
531 port_qsets = min(SGE_QSETS/sc->params.nports, mp_ncpus);
532 msi_needed = sc->msi_count = sc->params.nports * port_qsets + 1;
534 if (pci_msix_count(dev) == 0 ||
535 (error = pci_alloc_msix(dev, &sc->msi_count)) != 0 ||
536 sc->msi_count != msi_needed) {
537 device_printf(dev, "alloc msix failed - "
538 "msi_count=%d, msi_needed=%d, err=%d; "
539 "will try MSI\n", sc->msi_count,
543 pci_release_msi(dev);
544 bus_release_resource(dev, SYS_RES_MEMORY,
545 sc->msix_regs_rid, sc->msix_regs_res);
546 sc->msix_regs_res = NULL;
548 sc->flags |= USING_MSIX;
549 sc->cxgb_intr = cxgb_async_intr;
551 "using MSI-X interrupts (%u vectors)\n",
556 if ((msi_allowed >= 1) && (sc->msi_count == 0)) {
558 if ((error = pci_alloc_msi(dev, &sc->msi_count)) != 0) {
559 device_printf(dev, "alloc msi failed - "
560 "err=%d; will try INTx\n", error);
563 pci_release_msi(dev);
565 sc->flags |= USING_MSI;
566 sc->cxgb_intr = t3_intr_msi;
567 device_printf(dev, "using MSI interrupts\n");
571 if (sc->msi_count == 0) {
572 device_printf(dev, "using line interrupts\n");
573 sc->cxgb_intr = t3b_intr;
576 /* Create a private taskqueue thread for handling driver events */
577 #ifdef TASKQUEUE_CURRENT
578 sc->tq = taskqueue_create("cxgb_taskq", M_NOWAIT,
579 taskqueue_thread_enqueue, &sc->tq);
581 sc->tq = taskqueue_create_fast("cxgb_taskq", M_NOWAIT,
582 taskqueue_thread_enqueue, &sc->tq);
584 if (sc->tq == NULL) {
585 device_printf(dev, "failed to allocate controller task queue\n");
589 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq",
590 device_get_nameunit(dev));
591 TASK_INIT(&sc->ext_intr_task, 0, cxgb_ext_intr_handler, sc);
592 TASK_INIT(&sc->tick_task, 0, cxgb_tick_handler, sc);
595 /* Create a periodic callout for checking adapter status */
596 callout_init(&sc->cxgb_tick_ch, TRUE);
598 if (t3_check_fw_version(sc) < 0 || force_fw_update) {
600 * Warn user that a firmware update will be attempted in init.
602 device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n",
603 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
604 sc->flags &= ~FW_UPTODATE;
606 sc->flags |= FW_UPTODATE;
609 if (t3_check_tpsram_version(sc) < 0) {
611 * Warn user that a firmware update will be attempted in init.
613 device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n",
614 t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
615 sc->flags &= ~TPS_UPTODATE;
617 sc->flags |= TPS_UPTODATE;
621 * Create a child device for each MAC. The ethernet attachment
622 * will be done in these children.
624 for (i = 0; i < (sc)->params.nports; i++) {
625 struct port_info *pi;
627 if ((child = device_add_child(dev, "cxgb", -1)) == NULL) {
628 device_printf(dev, "failed to add child port\n");
634 pi->nqsets = port_qsets;
635 pi->first_qset = i*port_qsets;
637 pi->tx_chan = i >= ai->nports0;
638 pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i;
639 sc->rxpkt_map[pi->txpkt_intf] = i;
640 sc->port[i].tx_chan = i >= ai->nports0;
641 sc->portdev[i] = child;
642 device_set_softc(child, pi);
644 if ((error = bus_generic_attach(dev)) != 0)
647 /* initialize sge private state */
648 t3_sge_init_adapter(sc);
653 if (is_offload(sc)) {
654 setbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT);
655 cxgb_adapter_ofld(sc);
657 error = t3_get_fw_version(sc, &vers);
661 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d",
662 G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers),
663 G_FW_VERSION_MICRO(vers));
665 snprintf(buf, sizeof(buf), "%s %sNIC\t E/C: %s S/N: %s",
666 ai->desc, is_offload(sc) ? "R" : "",
667 sc->params.vpd.ec, sc->params.vpd.sn);
668 device_set_desc_copy(dev, buf);
670 snprintf(&sc->port_types[0], sizeof(sc->port_types), "%x%x%x%x",
671 sc->params.vpd.port_type[0], sc->params.vpd.port_type[1],
672 sc->params.vpd.port_type[2], sc->params.vpd.port_type[3]);
674 device_printf(sc->dev, "Firmware Version %s\n", &sc->fw_version[0]);
675 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc);
676 t3_add_attach_sysctls(sc);
685 * The cxgb_controller_detach routine is called with the device is
686 * unloaded from the system.
690 cxgb_controller_detach(device_t dev)
694 sc = device_get_softc(dev);
702 * The cxgb_free() is called by the cxgb_controller_detach() routine
703 * to tear down the structures that were built up in
704 * cxgb_controller_attach(), and should be the final piece of work
705 * done when fully unloading the driver.
708 * 1. Shutting down the threads started by the cxgb_controller_attach()
710 * 2. Stopping the lower level device and all callouts (cxgb_down_locked()).
711 * 3. Detaching all of the port devices created during the
712 * cxgb_controller_attach() routine.
713 * 4. Removing the device children created via cxgb_controller_attach().
714 * 5. Releasing PCI resources associated with the device.
715 * 6. Turning off the offload support, iff it was turned on.
716 * 7. Destroying the mutexes created in cxgb_controller_attach().
720 cxgb_free(struct adapter *sc)
725 sc->flags |= CXGB_SHUTDOWN;
729 * Make sure all child devices are gone.
731 bus_generic_detach(sc->dev);
732 for (i = 0; i < (sc)->params.nports; i++) {
733 if (sc->portdev[i] &&
734 device_delete_child(sc->dev, sc->portdev[i]) != 0)
735 device_printf(sc->dev, "failed to delete child port\n");
739 * At this point, it is as if cxgb_port_detach has run on all ports, and
740 * cxgb_down has run on the adapter. All interrupts have been silenced,
741 * all open devices have been closed.
743 KASSERT(sc->open_device_map == 0, ("%s: device(s) still open (%x)",
744 __func__, sc->open_device_map));
745 for (i = 0; i < sc->params.nports; i++) {
746 KASSERT(sc->port[i].ifp == NULL, ("%s: port %i undead!",
751 * Finish off the adapter's callouts.
753 callout_drain(&sc->cxgb_tick_ch);
754 callout_drain(&sc->sge_timer_ch);
757 * Release resources grabbed under FULL_INIT_DONE by cxgb_up. The
758 * sysctls are cleaned up by the kernel linker.
760 if (sc->flags & FULL_INIT_DONE) {
761 t3_free_sge_resources(sc);
762 sc->flags &= ~FULL_INIT_DONE;
766 * Release all interrupt resources.
768 cxgb_teardown_interrupts(sc);
770 if (sc->flags & (USING_MSI | USING_MSIX)) {
771 device_printf(sc->dev, "releasing msi message(s)\n");
772 pci_release_msi(sc->dev);
774 device_printf(sc->dev, "no msi message to release\n");
777 if (sc->msix_regs_res != NULL) {
778 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid,
784 * Free the adapter's taskqueue.
786 if (sc->tq != NULL) {
787 taskqueue_free(sc->tq);
791 if (is_offload(sc)) {
792 clrbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT);
793 cxgb_adapter_unofld(sc);
797 if (sc->flags & CXGB_OFLD_INIT)
798 cxgb_offload_deactivate(sc);
800 free(sc->filters, M_DEVBUF);
805 if (sc->udbs_res != NULL)
806 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->udbs_rid,
809 if (sc->regs_res != NULL)
810 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->regs_rid,
813 MTX_DESTROY(&sc->mdio_lock);
814 MTX_DESTROY(&sc->sge.reg_lock);
815 MTX_DESTROY(&sc->elmer_lock);
816 ADAPTER_LOCK_DEINIT(sc);
820 * setup_sge_qsets - configure SGE Tx/Rx/response queues
821 * @sc: the controller softc
823 * Determines how many sets of SGE queues to use and initializes them.
824 * We support multiple queue sets per port if we have MSI-X, otherwise
825 * just one queue set per port.
828 setup_sge_qsets(adapter_t *sc)
830 int i, j, err, irq_idx = 0, qset_idx = 0;
831 u_int ntxq = SGE_TXQ_PER_SET;
833 if ((err = t3_sge_alloc(sc)) != 0) {
834 device_printf(sc->dev, "t3_sge_alloc returned %d\n", err);
838 if (sc->params.rev > 0 && !(sc->flags & USING_MSI))
841 for (i = 0; i < (sc)->params.nports; i++) {
842 struct port_info *pi = &sc->port[i];
844 for (j = 0; j < pi->nqsets; j++, qset_idx++) {
845 err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports,
846 (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx,
847 &sc->params.sge.qset[qset_idx], ntxq, pi);
849 t3_free_sge_resources(sc);
850 device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n",
861 cxgb_teardown_interrupts(adapter_t *sc)
865 for (i = 0; i < SGE_QSETS; i++) {
866 if (sc->msix_intr_tag[i] == NULL) {
868 /* Should have been setup fully or not at all */
869 KASSERT(sc->msix_irq_res[i] == NULL &&
870 sc->msix_irq_rid[i] == 0,
871 ("%s: half-done interrupt (%d).", __func__, i));
876 bus_teardown_intr(sc->dev, sc->msix_irq_res[i],
877 sc->msix_intr_tag[i]);
878 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->msix_irq_rid[i],
879 sc->msix_irq_res[i]);
881 sc->msix_irq_res[i] = sc->msix_intr_tag[i] = NULL;
882 sc->msix_irq_rid[i] = 0;
886 KASSERT(sc->irq_res != NULL,
887 ("%s: half-done interrupt.", __func__));
889 bus_teardown_intr(sc->dev, sc->irq_res, sc->intr_tag);
890 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid,
893 sc->irq_res = sc->intr_tag = NULL;
899 cxgb_setup_interrupts(adapter_t *sc)
901 struct resource *res;
903 int i, rid, err, intr_flag = sc->flags & (USING_MSI | USING_MSIX);
905 sc->irq_rid = intr_flag ? 1 : 0;
906 sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &sc->irq_rid,
907 RF_SHAREABLE | RF_ACTIVE);
908 if (sc->irq_res == NULL) {
909 device_printf(sc->dev, "Cannot allocate interrupt (%x, %u)\n",
910 intr_flag, sc->irq_rid);
914 err = bus_setup_intr(sc->dev, sc->irq_res,
915 INTR_MPSAFE | INTR_TYPE_NET,
919 sc->cxgb_intr, sc, &sc->intr_tag);
922 device_printf(sc->dev,
923 "Cannot set up interrupt (%x, %u, %d)\n",
924 intr_flag, sc->irq_rid, err);
925 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid,
927 sc->irq_res = sc->intr_tag = NULL;
932 /* That's all for INTx or MSI */
933 if (!(intr_flag & USING_MSIX) || err)
936 for (i = 0; i < sc->msi_count - 1; i++) {
938 res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid,
939 RF_SHAREABLE | RF_ACTIVE);
941 device_printf(sc->dev, "Cannot allocate interrupt "
942 "for message %d\n", rid);
947 err = bus_setup_intr(sc->dev, res, INTR_MPSAFE | INTR_TYPE_NET,
951 t3_intr_msix, &sc->sge.qs[i], &tag);
953 device_printf(sc->dev, "Cannot set up interrupt "
954 "for message %d (%d)\n", rid, err);
955 bus_release_resource(sc->dev, SYS_RES_IRQ, rid, res);
959 sc->msix_irq_rid[i] = rid;
960 sc->msix_irq_res[i] = res;
961 sc->msix_intr_tag[i] = tag;
965 cxgb_teardown_interrupts(sc);
972 cxgb_port_probe(device_t dev)
978 p = device_get_softc(dev);
980 snprintf(buf, sizeof(buf), "Port %d %s", p->port_id, desc);
981 device_set_desc_copy(dev, buf);
987 cxgb_makedev(struct port_info *pi)
990 pi->port_cdev = make_dev(&cxgb_cdevsw, pi->ifp->if_dunit,
991 UID_ROOT, GID_WHEEL, 0600, if_name(pi->ifp));
993 if (pi->port_cdev == NULL)
996 pi->port_cdev->si_drv1 = (void *)pi;
1001 #ifndef LRO_SUPPORTED
1005 #define IFCAP_LRO 0x0
1008 #ifdef TSO_SUPPORTED
1009 #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO)
1010 /* Don't enable TSO6 yet */
1011 #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4 | IFCAP_JUMBO_MTU | IFCAP_LRO)
1013 #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU)
1014 /* Don't enable TSO6 yet */
1015 #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU)
1016 #define IFCAP_TSO4 0x0
1017 #define IFCAP_TSO6 0x0
1018 #define CSUM_TSO 0x0
1023 cxgb_port_attach(device_t dev)
1025 struct port_info *p;
1031 p = device_get_softc(dev);
1033 snprintf(p->lockbuf, PORT_NAME_LEN, "cxgb port lock %d:%d",
1034 device_get_unit(device_get_parent(dev)), p->port_id);
1035 PORT_LOCK_INIT(p, p->lockbuf);
1037 /* Allocate an ifnet object and set it up */
1038 ifp = p->ifp = if_alloc(IFT_ETHER);
1040 device_printf(dev, "Cannot allocate ifnet\n");
1045 * Note that there is currently no watchdog timer.
1047 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1048 ifp->if_init = cxgb_init;
1050 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1051 ifp->if_ioctl = cxgb_ioctl;
1052 ifp->if_start = cxgb_start;
1055 ifp->if_timer = 0; /* Disable ifnet watchdog */
1056 ifp->if_watchdog = NULL;
1058 ifp->if_snd.ifq_drv_maxlen = cxgb_snd_queue_len;
1059 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1060 IFQ_SET_READY(&ifp->if_snd);
1062 ifp->if_hwassist = ifp->if_capabilities = ifp->if_capenable = 0;
1063 ifp->if_capabilities |= CXGB_CAP;
1064 ifp->if_capenable |= CXGB_CAP_ENABLE;
1065 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO);
1067 * disable TSO on 4-port - it isn't supported by the firmware yet
1069 if (p->adapter->params.nports > 2) {
1070 ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6);
1071 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6);
1072 ifp->if_hwassist &= ~CSUM_TSO;
1075 ether_ifattach(ifp, p->hw_addr);
1076 ifp->if_transmit = cxgb_transmit;
1077 ifp->if_qflush = cxgb_qflush;
1080 * Only default to jumbo frames on 10GigE
1082 if (p->adapter->params.nports <= 2)
1083 ifp->if_mtu = ETHERMTU_JUMBO;
1084 if ((err = cxgb_makedev(p)) != 0) {
1085 printf("makedev failed %d\n", err);
1089 /* Create a list of media supported by this port */
1090 ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change,
1092 cxgb_build_medialist(p);
1094 t3_sge_init_port(p);
1100 * cxgb_port_detach() is called via the device_detach methods when
1101 * cxgb_free() calls the bus_generic_detach. It is responsible for
1102 * removing the device from the view of the kernel, i.e. from all
1103 * interfaces lists etc. This routine is only called when the driver is
1104 * being unloaded, not when the link goes down.
1107 cxgb_port_detach(device_t dev)
1109 struct port_info *p;
1113 p = device_get_softc(dev);
1116 cxgb_begin_detach(p);
1118 if (p->port_cdev != NULL)
1119 destroy_dev(p->port_cdev);
1121 cxgb_uninit_synchronized(p);
1122 ether_ifdetach(p->ifp);
1124 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
1125 struct sge_qset *qs = &sc->sge.qs[i];
1126 struct sge_txq *txq = &qs->txq[TXQ_ETH];
1128 callout_drain(&txq->txq_watchdog);
1129 callout_drain(&txq->txq_timer);
1132 PORT_LOCK_DEINIT(p);
1141 t3_fatal_err(struct adapter *sc)
1145 if (sc->flags & FULL_INIT_DONE) {
1147 t3_write_reg(sc, A_XGM_TX_CTRL, 0);
1148 t3_write_reg(sc, A_XGM_RX_CTRL, 0);
1149 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0);
1150 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0);
1151 t3_intr_disable(sc);
1153 device_printf(sc->dev,"encountered fatal error, operation suspended\n");
1154 if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status))
1155 device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n",
1156 fw_status[0], fw_status[1], fw_status[2], fw_status[3]);
1160 t3_os_find_pci_capability(adapter_t *sc, int cap)
1163 struct pci_devinfo *dinfo;
1169 dinfo = device_get_ivars(dev);
1172 status = pci_read_config(dev, PCIR_STATUS, 2);
1173 if (!(status & PCIM_STATUS_CAPPRESENT))
1176 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1182 ptr = PCIR_CAP_PTR_2;
1188 ptr = pci_read_config(dev, ptr, 1);
1191 if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap)
1193 ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1);
1200 t3_os_pci_save_state(struct adapter *sc)
1203 struct pci_devinfo *dinfo;
1206 dinfo = device_get_ivars(dev);
1208 pci_cfg_save(dev, dinfo, 0);
1213 t3_os_pci_restore_state(struct adapter *sc)
1216 struct pci_devinfo *dinfo;
1219 dinfo = device_get_ivars(dev);
1221 pci_cfg_restore(dev, dinfo);
1226 * t3_os_link_changed - handle link status changes
1227 * @sc: the adapter associated with the link change
1228 * @port_id: the port index whose link status has changed
1229 * @link_status: the new status of the link
1230 * @speed: the new speed setting
1231 * @duplex: the new duplex setting
1232 * @fc: the new flow-control setting
1234 * This is the OS-dependent handler for link status changes. The OS
1235 * neutral handler takes care of most of the processing for these events,
1236 * then calls this handler for any OS-specific processing.
1239 t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed,
1240 int duplex, int fc, int mac_was_reset)
1242 struct port_info *pi = &adapter->port[port_id];
1243 struct ifnet *ifp = pi->ifp;
1245 /* no race with detach, so ifp should always be good */
1246 KASSERT(ifp, ("%s: if detached.", __func__));
1248 /* Reapply mac settings if they were lost due to a reset */
1249 if (mac_was_reset) {
1251 cxgb_update_mac_settings(pi);
1256 ifp->if_baudrate = IF_Mbps(speed);
1257 if_link_state_change(ifp, LINK_STATE_UP);
1259 if_link_state_change(ifp, LINK_STATE_DOWN);
1263 * t3_os_phymod_changed - handle PHY module changes
1264 * @phy: the PHY reporting the module change
1265 * @mod_type: new module type
1267 * This is the OS-dependent handler for PHY module changes. It is
1268 * invoked when a PHY module is removed or inserted for any OS-specific
1271 void t3_os_phymod_changed(struct adapter *adap, int port_id)
1273 static const char *mod_str[] = {
1274 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown"
1276 struct port_info *pi = &adap->port[port_id];
1277 int mod = pi->phy.modtype;
1279 if (mod != pi->media.ifm_cur->ifm_data)
1280 cxgb_build_medialist(pi);
1282 if (mod == phy_modtype_none)
1283 if_printf(pi->ifp, "PHY module unplugged\n");
1285 KASSERT(mod < ARRAY_SIZE(mod_str),
1286 ("invalid PHY module type %d", mod));
1287 if_printf(pi->ifp, "%s PHY module inserted\n", mod_str[mod]);
1292 * Interrupt-context handler for external (PHY) interrupts.
1295 t3_os_ext_intr_handler(adapter_t *sc)
1298 printf("t3_os_ext_intr_handler\n");
1300 * Schedule a task to handle external interrupts as they may be slow
1301 * and we use a mutex to protect MDIO registers. We disable PHY
1302 * interrupts in the meantime and let the task reenable them when
1305 if (sc->slow_intr_mask) {
1307 sc->slow_intr_mask &= ~F_T3DBG;
1308 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask);
1309 taskqueue_enqueue(sc->tq, &sc->ext_intr_task);
1315 t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[])
1319 * The ifnet might not be allocated before this gets called,
1320 * as this is called early on in attach by t3_prep_adapter
1321 * save the address off in the port structure
1324 printf("set_hw_addr on idx %d addr %6D\n", port_idx, hw_addr, ":");
1325 bcopy(hw_addr, adapter->port[port_idx].hw_addr, ETHER_ADDR_LEN);
1329 * Programs the XGMAC based on the settings in the ifnet. These settings
1330 * include MTU, MAC address, mcast addresses, etc.
1333 cxgb_update_mac_settings(struct port_info *p)
1335 struct ifnet *ifp = p->ifp;
1336 struct t3_rx_mode rm;
1337 struct cmac *mac = &p->mac;
1340 PORT_LOCK_ASSERT_OWNED(p);
1342 bcopy(IF_LLADDR(ifp), p->hw_addr, ETHER_ADDR_LEN);
1345 if (ifp->if_capenable & IFCAP_VLAN_MTU)
1346 mtu += ETHER_VLAN_ENCAP_LEN;
1348 hwtagging = (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0;
1350 t3_mac_set_mtu(mac, mtu);
1351 t3_set_vlan_accel(p->adapter, 1 << p->tx_chan, hwtagging);
1352 t3_mac_set_address(mac, 0, p->hw_addr);
1353 t3_init_rx_mode(&rm, p);
1354 t3_mac_set_rx_mode(mac, &rm);
1359 await_mgmt_replies(struct adapter *adap, unsigned long init_cnt,
1364 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) {
1373 init_tp_parity(struct adapter *adap)
1377 struct cpl_set_tcb_field *greq;
1378 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts;
1380 t3_tp_set_offload_mode(adap, 1);
1382 for (i = 0; i < 16; i++) {
1383 struct cpl_smt_write_req *req;
1385 m = m_gethdr(M_WAITOK, MT_DATA);
1386 req = mtod(m, struct cpl_smt_write_req *);
1387 m->m_len = m->m_pkthdr.len = sizeof(*req);
1388 memset(req, 0, sizeof(*req));
1389 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
1390 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i));
1392 t3_mgmt_tx(adap, m);
1395 for (i = 0; i < 2048; i++) {
1396 struct cpl_l2t_write_req *req;
1398 m = m_gethdr(M_WAITOK, MT_DATA);
1399 req = mtod(m, struct cpl_l2t_write_req *);
1400 m->m_len = m->m_pkthdr.len = sizeof(*req);
1401 memset(req, 0, sizeof(*req));
1402 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
1403 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i));
1404 req->params = htonl(V_L2T_W_IDX(i));
1405 t3_mgmt_tx(adap, m);
1408 for (i = 0; i < 2048; i++) {
1409 struct cpl_rte_write_req *req;
1411 m = m_gethdr(M_WAITOK, MT_DATA);
1412 req = mtod(m, struct cpl_rte_write_req *);
1413 m->m_len = m->m_pkthdr.len = sizeof(*req);
1414 memset(req, 0, sizeof(*req));
1415 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
1416 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i));
1417 req->l2t_idx = htonl(V_L2T_W_IDX(i));
1418 t3_mgmt_tx(adap, m);
1421 m = m_gethdr(M_WAITOK, MT_DATA);
1422 greq = mtod(m, struct cpl_set_tcb_field *);
1423 m->m_len = m->m_pkthdr.len = sizeof(*greq);
1424 memset(greq, 0, sizeof(*greq));
1425 greq->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
1426 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0));
1427 greq->mask = htobe64(1);
1428 t3_mgmt_tx(adap, m);
1430 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
1431 t3_tp_set_offload_mode(adap, 0);
1436 * setup_rss - configure Receive Side Steering (per-queue connection demux)
1437 * @adap: the adapter
1439 * Sets up RSS to distribute packets to multiple receive queues. We
1440 * configure the RSS CPU lookup table to distribute to the number of HW
1441 * receive queues, and the response queue lookup table to narrow that
1442 * down to the response queues actually configured for each port.
1443 * We always configure the RSS mapping for two ports since the mapping
1444 * table has plenty of entries.
1447 setup_rss(adapter_t *adap)
1451 uint8_t cpus[SGE_QSETS + 1];
1452 uint16_t rspq_map[RSS_TABLE_SIZE];
1454 for (i = 0; i < SGE_QSETS; ++i)
1456 cpus[SGE_QSETS] = 0xff;
1459 for_each_port(adap, i) {
1460 const struct port_info *pi = adap2pinfo(adap, i);
1462 nq[pi->tx_chan] += pi->nqsets;
1464 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
1465 rspq_map[i] = nq[0] ? i % nq[0] : 0;
1466 rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0;
1469 /* Calculate the reverse RSS map table */
1470 for (i = 0; i < SGE_QSETS; ++i)
1471 adap->rrss_map[i] = 0xff;
1472 for (i = 0; i < RSS_TABLE_SIZE; ++i)
1473 if (adap->rrss_map[rspq_map[i]] == 0xff)
1474 adap->rrss_map[rspq_map[i]] = i;
1476 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
1477 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN |
1478 F_RRCPLMAPEN | V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ,
1484 * Sends an mbuf to an offload queue driver
1485 * after dealing with any active network taps.
1488 offload_tx(struct t3cdev *tdev, struct mbuf *m)
1492 ret = t3_offload_tx(tdev, m);
1497 write_smt_entry(struct adapter *adapter, int idx)
1499 struct port_info *pi = &adapter->port[idx];
1500 struct cpl_smt_write_req *req;
1503 if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL)
1506 req = mtod(m, struct cpl_smt_write_req *);
1507 m->m_pkthdr.len = m->m_len = sizeof(struct cpl_smt_write_req);
1509 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
1510 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx));
1511 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */
1513 memset(req->src_mac1, 0, sizeof(req->src_mac1));
1514 memcpy(req->src_mac0, pi->hw_addr, ETHER_ADDR_LEN);
1516 m_set_priority(m, 1);
1518 offload_tx(&adapter->tdev, m);
1524 init_smt(struct adapter *adapter)
1528 for_each_port(adapter, i)
1529 write_smt_entry(adapter, i);
1534 init_port_mtus(adapter_t *adapter)
1536 unsigned int mtus = ETHERMTU | (ETHERMTU << 16);
1538 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus);
1542 send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo,
1546 struct mngt_pktsched_wr *req;
1548 m = m_gethdr(M_DONTWAIT, MT_DATA);
1550 req = mtod(m, struct mngt_pktsched_wr *);
1551 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT));
1552 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET;
1557 req->binding = port;
1558 m->m_len = m->m_pkthdr.len = sizeof(*req);
1559 t3_mgmt_tx(adap, m);
1564 bind_qsets(adapter_t *sc)
1568 for (i = 0; i < (sc)->params.nports; ++i) {
1569 const struct port_info *pi = adap2pinfo(sc, i);
1571 for (j = 0; j < pi->nqsets; ++j) {
1572 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1,
1580 update_tpeeprom(struct adapter *adap)
1582 #ifdef FIRMWARE_LATEST
1583 const struct firmware *tpeeprom;
1585 struct firmware *tpeeprom;
1589 unsigned int major, minor;
1593 t3_seeprom_read(adap, TP_SRAM_OFFSET, &version);
1595 major = G_TP_VERSION_MAJOR(version);
1596 minor = G_TP_VERSION_MINOR(version);
1597 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR)
1600 rev = t3rev2char(adap);
1601 snprintf(name, sizeof(name), TPEEPROM_NAME, rev);
1603 tpeeprom = firmware_get(name);
1604 if (tpeeprom == NULL) {
1605 device_printf(adap->dev,
1606 "could not load TP EEPROM: unable to load %s\n",
1611 len = tpeeprom->datasize - 4;
1613 ret = t3_check_tpsram(adap, tpeeprom->data, tpeeprom->datasize);
1615 goto release_tpeeprom;
1617 if (len != TP_SRAM_LEN) {
1618 device_printf(adap->dev,
1619 "%s length is wrong len=%d expected=%d\n", name,
1624 ret = set_eeprom(&adap->port[0], tpeeprom->data, tpeeprom->datasize,
1628 device_printf(adap->dev,
1629 "Protocol SRAM image updated in EEPROM to %d.%d.%d\n",
1630 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1632 device_printf(adap->dev,
1633 "Protocol SRAM image update in EEPROM failed\n");
1636 firmware_put(tpeeprom, FIRMWARE_UNLOAD);
1642 update_tpsram(struct adapter *adap)
1644 #ifdef FIRMWARE_LATEST
1645 const struct firmware *tpsram;
1647 struct firmware *tpsram;
1652 rev = t3rev2char(adap);
1653 snprintf(name, sizeof(name), TPSRAM_NAME, rev);
1655 update_tpeeprom(adap);
1657 tpsram = firmware_get(name);
1658 if (tpsram == NULL){
1659 device_printf(adap->dev, "could not load TP SRAM\n");
1662 device_printf(adap->dev, "updating TP SRAM\n");
1664 ret = t3_check_tpsram(adap, tpsram->data, tpsram->datasize);
1666 goto release_tpsram;
1668 ret = t3_set_proto_sram(adap, tpsram->data);
1670 device_printf(adap->dev, "loading protocol SRAM failed\n");
1673 firmware_put(tpsram, FIRMWARE_UNLOAD);
1679 * cxgb_up - enable the adapter
1680 * @adap: adapter being enabled
1682 * Called when the first port is enabled, this function performs the
1683 * actions necessary to make an adapter operational, such as completing
1684 * the initialization of HW modules, and enabling interrupts.
1687 cxgb_up(struct adapter *sc)
1691 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1692 KASSERT(sc->open_device_map == 0, ("%s: device(s) already open (%x)",
1693 __func__, sc->open_device_map));
1695 if ((sc->flags & FULL_INIT_DONE) == 0) {
1697 if ((sc->flags & FW_UPTODATE) == 0)
1698 if ((err = upgrade_fw(sc)))
1701 if ((sc->flags & TPS_UPTODATE) == 0)
1702 if ((err = update_tpsram(sc)))
1705 err = t3_init_hw(sc, 0);
1709 t3_set_reg_field(sc, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT);
1710 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
1712 err = setup_sge_qsets(sc);
1719 err = cxgb_setup_interrupts(sc);
1723 t3_add_configured_sysctls(sc);
1724 sc->flags |= FULL_INIT_DONE;
1731 if (sc->params.rev >= T3_REV_C && !(sc->flags & TP_PARITY_INIT) &&
1732 is_offload(sc) && init_tp_parity(sc) == 0)
1733 sc->flags |= TP_PARITY_INIT;
1735 if (sc->flags & TP_PARITY_INIT) {
1736 t3_write_reg(sc, A_TP_INT_CAUSE, F_CMCACHEPERR | F_ARPLUTPERR);
1737 t3_write_reg(sc, A_TP_INT_ENABLE, 0x7fbfffff);
1740 if (!(sc->flags & QUEUES_BOUND)) {
1742 sc->flags |= QUEUES_BOUND;
1745 t3_sge_reset_adapter(sc);
1751 * Called when the last open device is closed. Does NOT undo all of cxgb_up's
1752 * work. Specifically, the resources grabbed under FULL_INIT_DONE are released
1753 * during controller_detach, not here.
1756 cxgb_down(struct adapter *sc)
1758 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1761 t3_intr_disable(sc);
1765 offload_open(struct port_info *pi)
1767 struct adapter *sc = pi->adapter;
1768 struct t3cdev *tdev = &sc->tdev;
1770 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1772 setbit(&sc->open_device_map, OFFLOAD_DEVMAP_BIT);
1774 t3_tp_set_offload_mode(sc, 1);
1775 tdev->lldev = pi->ifp;
1777 t3_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd,
1778 sc->params.rev == 0 ? sc->port[0].ifp->if_mtu : 0xffff);
1780 cxgb_add_clients(tdev);
1786 offload_close(struct t3cdev *tdev)
1788 struct adapter *adapter = tdev2adap(tdev);
1790 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT))
1793 /* Call back all registered clients */
1794 cxgb_remove_clients(tdev);
1797 cxgb_set_dummy_ops(tdev);
1798 t3_tp_set_offload_mode(adapter, 0);
1800 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT);
1806 * Begin a synchronized operation. If this call succeeds, it is guaranteed that
1807 * no one will remove the port or its ifp from underneath the caller. Caller is
1808 * also granted exclusive access to open_device_map.
1810 * operation here means init, uninit, detach, and ioctl service.
1813 * EINTR (ctrl-c pressed during ifconfig for example).
1814 * ENXIO (port is about to detach - due to kldunload for example).
1817 cxgb_begin_op(struct port_info *p, const char *wmsg)
1820 struct adapter *sc = p->adapter;
1824 while (!IS_DOOMED(p) && IS_BUSY(sc)) {
1825 if (mtx_sleep(&sc->flags, &sc->lock, PCATCH, wmsg, 0)) {
1833 else if (!IS_BUSY(sc))
1836 KASSERT(0, ("%s: port %d, p->flags = %x , sc->flags = %x",
1837 __func__, p->port_id, p->flags, sc->flags));
1847 * End a synchronized operation. Read comment block above cxgb_begin_op.
1850 cxgb_end_op(struct port_info *p)
1852 struct adapter *sc = p->adapter;
1855 KASSERT(IS_BUSY(sc), ("%s: not busy.", __func__));
1857 wakeup_one(&sc->flags);
1864 * Prepare for port detachment. Detach is a special kind of synchronized
1865 * operation. Also read comment before cxgb_begin_op.
1868 cxgb_begin_detach(struct port_info *p)
1870 struct adapter *sc = p->adapter;
1873 * Inform those waiting for this port that it is going to be destroyed
1874 * and they should not continue further. (They'll return with ENXIO).
1882 * Wait for in-progress operations.
1885 while (IS_BUSY(sc)) {
1886 mtx_sleep(&sc->flags, &sc->lock, 0, "cxgbdtch", 0);
1895 * if_init for cxgb ports.
1898 cxgb_init(void *arg)
1900 struct port_info *p = arg;
1902 if (cxgb_begin_op(p, "cxgbinit"))
1905 cxgb_init_synchronized(p);
1910 cxgb_init_synchronized(struct port_info *p)
1912 struct adapter *sc = p->adapter;
1913 struct ifnet *ifp = p->ifp;
1914 struct cmac *mac = &p->mac;
1917 if (sc->open_device_map == 0) {
1918 if ((rc = cxgb_up(sc)) != 0)
1921 if (is_offload(sc) && !ofld_disable && offload_open(p))
1923 "Could not initialize offload capabilities\n");
1927 t3_port_intr_enable(sc, p->port_id);
1928 if (!mac->multiport)
1930 cxgb_update_mac_settings(p);
1931 t3_link_start(&p->phy, mac, &p->link_config);
1932 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
1933 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1934 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1937 t3_link_changed(sc, p->port_id);
1939 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
1940 struct sge_qset *qs = &sc->sge.qs[i];
1941 struct sge_txq *txq = &qs->txq[TXQ_ETH];
1943 callout_reset_on(&txq->txq_watchdog, hz, cxgb_tx_watchdog, qs,
1944 txq->txq_watchdog.c_cpu);
1948 setbit(&sc->open_device_map, p->port_id);
1954 * Called on "ifconfig down", and from port_detach
1957 cxgb_uninit_synchronized(struct port_info *pi)
1959 struct adapter *sc = pi->adapter;
1960 struct ifnet *ifp = pi->ifp;
1963 * Clear this port's bit from the open device map, and then drain all
1964 * the tasks that can access/manipulate this port's port_info or ifp.
1965 * We disable this port's interrupts here and so the the slow/ext
1966 * interrupt tasks won't be enqueued. The tick task will continue to
1967 * be enqueued every second but the runs after this drain will not see
1968 * this port in the open device map.
1970 * A well behaved task must take open_device_map into account and ignore
1971 * ports that are not open.
1973 clrbit(&sc->open_device_map, pi->port_id);
1974 t3_port_intr_disable(sc, pi->port_id);
1975 taskqueue_drain(sc->tq, &sc->slow_intr_task);
1976 taskqueue_drain(sc->tq, &sc->ext_intr_task);
1977 taskqueue_drain(sc->tq, &sc->tick_task);
1980 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1982 /* disable pause frames */
1983 t3_set_reg_field(sc, A_XGM_TX_CFG + pi->mac.offset, F_TXPAUSEEN, 0);
1985 /* Reset RX FIFO HWM */
1986 t3_set_reg_field(sc, A_XGM_RXFIFO_CFG + pi->mac.offset,
1987 V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM), 0);
1991 /* Wait for TXFIFO empty */
1992 t3_wait_op_done(sc, A_XGM_TXFIFO_CFG + pi->mac.offset,
1993 F_TXFIFO_EMPTY, 1, 20, 5);
1996 t3_mac_disable(&pi->mac, MAC_DIRECTION_RX);
1999 pi->phy.ops->power_down(&pi->phy, 1);
2003 pi->link_config.link_ok = 0;
2004 t3_os_link_changed(sc, pi->port_id, 0, 0, 0, 0, 0);
2006 if ((sc->open_device_map & PORT_MASK) == 0)
2007 offload_close(&sc->tdev);
2009 if (sc->open_device_map == 0)
2010 cxgb_down(pi->adapter);
2015 #ifdef LRO_SUPPORTED
2017 * Mark lro enabled or disabled in all qsets for this port
2020 cxgb_set_lro(struct port_info *p, int enabled)
2023 struct adapter *adp = p->adapter;
2026 PORT_LOCK_ASSERT_OWNED(p);
2027 for (i = 0; i < p->nqsets; i++) {
2028 q = &adp->sge.qs[p->first_qset + i];
2029 q->lro.enabled = (enabled != 0);
2036 cxgb_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data)
2038 struct port_info *p = ifp->if_softc;
2039 struct ifreq *ifr = (struct ifreq *)data;
2040 int flags, error = 0, mtu, handle_unsynchronized = 0;
2043 if ((error = cxgb_begin_op(p, "cxgbioct")) != 0)
2047 * Only commands that should be handled within begin-op/end-op are
2048 * serviced in this switch statement. See handle_unsynchronized.
2053 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) {
2058 cxgb_update_mac_settings(p);
2064 if (ifp->if_flags & IFF_UP) {
2065 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2066 flags = p->if_flags;
2067 if (((ifp->if_flags ^ flags) & IFF_PROMISC) ||
2068 ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) {
2070 cxgb_update_mac_settings(p);
2074 error = cxgb_init_synchronized(p);
2075 p->if_flags = ifp->if_flags;
2076 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2077 error = cxgb_uninit_synchronized(p);
2082 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2084 cxgb_update_mac_settings(p);
2090 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2091 if (mask & IFCAP_TXCSUM) {
2092 if (IFCAP_TXCSUM & ifp->if_capenable) {
2093 ifp->if_capenable &= ~(IFCAP_TXCSUM|IFCAP_TSO4);
2094 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP
2095 | CSUM_IP | CSUM_TSO);
2097 ifp->if_capenable |= IFCAP_TXCSUM;
2098 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP
2102 if (mask & IFCAP_RXCSUM) {
2103 ifp->if_capenable ^= IFCAP_RXCSUM;
2105 if (mask & IFCAP_TSO4) {
2106 if (IFCAP_TSO4 & ifp->if_capenable) {
2107 ifp->if_capenable &= ~IFCAP_TSO4;
2108 ifp->if_hwassist &= ~CSUM_TSO;
2109 } else if (IFCAP_TXCSUM & ifp->if_capenable) {
2110 ifp->if_capenable |= IFCAP_TSO4;
2111 ifp->if_hwassist |= CSUM_TSO;
2115 #ifdef LRO_SUPPORTED
2116 if (mask & IFCAP_LRO) {
2117 ifp->if_capenable ^= IFCAP_LRO;
2119 /* Safe to do this even if cxgb_up not called yet */
2120 cxgb_set_lro(p, ifp->if_capenable & IFCAP_LRO);
2123 if (mask & IFCAP_VLAN_HWTAGGING) {
2124 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2125 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2127 cxgb_update_mac_settings(p);
2131 if (mask & IFCAP_VLAN_MTU) {
2132 ifp->if_capenable ^= IFCAP_VLAN_MTU;
2133 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2135 cxgb_update_mac_settings(p);
2139 if (mask & IFCAP_VLAN_HWCSUM) {
2140 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2143 #ifdef VLAN_CAPABILITIES
2144 VLAN_CAPABILITIES(ifp);
2148 handle_unsynchronized = 1;
2153 * We don't want to call anything outside the driver while inside a
2154 * begin-op/end-op block. If it calls us back (eg. ether_ioctl may
2155 * call cxgb_init) we may deadlock if the state is already marked busy.
2157 * XXX: this probably opens a small race window with kldunload...
2161 /* The IS_DOOMED check is racy, we're clutching at straws here */
2162 if (handle_unsynchronized && !IS_DOOMED(p)) {
2163 if (command == SIOCSIFMEDIA || command == SIOCGIFMEDIA)
2164 error = ifmedia_ioctl(ifp, ifr, &p->media, command);
2166 error = ether_ioctl(ifp, command, data);
2173 cxgb_media_change(struct ifnet *ifp)
2175 return (EOPNOTSUPP);
2179 * Translates phy->modtype to the correct Ethernet media subtype.
2182 cxgb_ifm_type(int mod)
2185 case phy_modtype_sr:
2186 return (IFM_10G_SR);
2187 case phy_modtype_lr:
2188 return (IFM_10G_LR);
2189 case phy_modtype_lrm:
2190 return (IFM_10G_LRM);
2191 case phy_modtype_twinax:
2192 return (IFM_10G_TWINAX);
2193 case phy_modtype_twinax_long:
2194 return (IFM_10G_TWINAX_LONG);
2195 case phy_modtype_none:
2197 case phy_modtype_unknown:
2198 return (IFM_UNKNOWN);
2201 KASSERT(0, ("%s: modtype %d unknown", __func__, mod));
2202 return (IFM_UNKNOWN);
2206 * Rebuilds the ifmedia list for this port, and sets the current media.
2209 cxgb_build_medialist(struct port_info *p)
2211 struct cphy *phy = &p->phy;
2212 struct ifmedia *media = &p->media;
2213 int mod = phy->modtype;
2214 int m = IFM_ETHER | IFM_FDX;
2218 ifmedia_removeall(media);
2219 if (phy->caps & SUPPORTED_TP && phy->caps & SUPPORTED_Autoneg) {
2222 if (phy->caps & SUPPORTED_10000baseT_Full)
2223 ifmedia_add(media, m | IFM_10G_T, mod, NULL);
2225 if (phy->caps & SUPPORTED_1000baseT_Full)
2226 ifmedia_add(media, m | IFM_1000_T, mod, NULL);
2228 if (phy->caps & SUPPORTED_100baseT_Full)
2229 ifmedia_add(media, m | IFM_100_TX, mod, NULL);
2231 if (phy->caps & SUPPORTED_10baseT_Full)
2232 ifmedia_add(media, m | IFM_10_T, mod, NULL);
2234 ifmedia_add(media, IFM_ETHER | IFM_AUTO, mod, NULL);
2235 ifmedia_set(media, IFM_ETHER | IFM_AUTO);
2237 } else if (phy->caps & SUPPORTED_TP) {
2240 KASSERT(phy->caps & SUPPORTED_10000baseT_Full,
2241 ("%s: unexpected cap 0x%x", __func__, phy->caps));
2243 ifmedia_add(media, m | IFM_10G_CX4, mod, NULL);
2244 ifmedia_set(media, m | IFM_10G_CX4);
2246 } else if (phy->caps & SUPPORTED_FIBRE &&
2247 phy->caps & SUPPORTED_10000baseT_Full) {
2248 /* 10G optical (but includes SFP+ twinax) */
2250 m |= cxgb_ifm_type(mod);
2251 if (IFM_SUBTYPE(m) == IFM_NONE)
2254 ifmedia_add(media, m, mod, NULL);
2255 ifmedia_set(media, m);
2257 } else if (phy->caps & SUPPORTED_FIBRE &&
2258 phy->caps & SUPPORTED_1000baseT_Full) {
2261 /* XXX: Lie and claim to be SX, could actually be any 1G-X */
2262 ifmedia_add(media, m | IFM_1000_SX, mod, NULL);
2263 ifmedia_set(media, m | IFM_1000_SX);
2266 KASSERT(0, ("%s: don't know how to handle 0x%x.", __func__,
2274 cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2276 struct port_info *p = ifp->if_softc;
2277 struct ifmedia_entry *cur = p->media.ifm_cur;
2278 int speed = p->link_config.speed;
2280 if (cur->ifm_data != p->phy.modtype) {
2281 cxgb_build_medialist(p);
2282 cur = p->media.ifm_cur;
2285 ifmr->ifm_status = IFM_AVALID;
2286 if (!p->link_config.link_ok)
2289 ifmr->ifm_status |= IFM_ACTIVE;
2292 * active and current will differ iff current media is autoselect. That
2293 * can happen only for copper RJ45.
2295 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO)
2297 KASSERT(p->phy.caps & SUPPORTED_TP && p->phy.caps & SUPPORTED_Autoneg,
2298 ("%s: unexpected PHY caps 0x%x", __func__, p->phy.caps));
2300 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
2301 if (speed == SPEED_10000)
2302 ifmr->ifm_active |= IFM_10G_T;
2303 else if (speed == SPEED_1000)
2304 ifmr->ifm_active |= IFM_1000_T;
2305 else if (speed == SPEED_100)
2306 ifmr->ifm_active |= IFM_100_TX;
2307 else if (speed == SPEED_10)
2308 ifmr->ifm_active |= IFM_10_T;
2310 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__,
2315 cxgb_async_intr(void *data)
2317 adapter_t *sc = data;
2320 device_printf(sc->dev, "cxgb_async_intr\n");
2322 * May need to sleep - defer to taskqueue
2324 taskqueue_enqueue(sc->tq, &sc->slow_intr_task);
2328 cxgb_ext_intr_handler(void *arg, int count)
2330 adapter_t *sc = (adapter_t *)arg;
2333 printf("cxgb_ext_intr_handler\n");
2335 t3_phy_intr_handler(sc);
2337 /* Now reenable external interrupts */
2339 if (sc->slow_intr_mask) {
2340 sc->slow_intr_mask |= F_T3DBG;
2341 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG);
2342 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask);
2348 link_poll_needed(struct port_info *p)
2350 struct cphy *phy = &p->phy;
2352 if (phy->caps & POLL_LINK_1ST_TIME) {
2353 p->phy.caps &= ~POLL_LINK_1ST_TIME;
2357 return (p->link_fault || !(phy->caps & SUPPORTED_LINK_IRQ));
2361 check_link_status(adapter_t *sc)
2365 for (i = 0; i < (sc)->params.nports; ++i) {
2366 struct port_info *p = &sc->port[i];
2368 if (!isset(&sc->open_device_map, p->port_id))
2371 if (link_poll_needed(p))
2372 t3_link_changed(sc, i);
2377 check_t3b2_mac(struct adapter *sc)
2381 if (sc->flags & CXGB_SHUTDOWN)
2384 for_each_port(sc, i) {
2385 struct port_info *p = &sc->port[i];
2388 struct ifnet *ifp = p->ifp;
2391 if (!isset(&sc->open_device_map, p->port_id) || p->link_fault ||
2392 !p->link_config.link_ok)
2395 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING,
2396 ("%s: state mismatch (drv_flags %x, device_map %x)",
2397 __func__, ifp->if_drv_flags, sc->open_device_map));
2400 status = t3b2_mac_watchdog_task(&p->mac);
2402 p->mac.stats.num_toggled++;
2403 else if (status == 2) {
2404 struct cmac *mac = &p->mac;
2406 cxgb_update_mac_settings(p);
2407 t3_link_start(&p->phy, mac, &p->link_config);
2408 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
2409 t3_port_intr_enable(sc, p->port_id);
2410 p->mac.stats.num_resets++;
2417 cxgb_tick(void *arg)
2419 adapter_t *sc = (adapter_t *)arg;
2421 if (sc->flags & CXGB_SHUTDOWN)
2424 taskqueue_enqueue(sc->tq, &sc->tick_task);
2425 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc);
2429 cxgb_tick_handler(void *arg, int count)
2431 adapter_t *sc = (adapter_t *)arg;
2432 const struct adapter_params *p = &sc->params;
2434 uint32_t cause, reset;
2436 if (sc->flags & CXGB_SHUTDOWN || !(sc->flags & FULL_INIT_DONE))
2439 check_link_status(sc);
2441 if (p->rev == T3_REV_B2 && p->nports < 4 && sc->open_device_map)
2444 cause = t3_read_reg(sc, A_SG_INT_CAUSE);
2446 if (cause & F_FLEMPTY) {
2447 struct sge_qset *qs = &sc->sge.qs[0];
2452 cause = (t3_read_reg(sc, A_SG_RSPQ_FL_STATUS) >>
2453 S_FL0EMPTY) & 0xffff;
2455 qs->fl[i].empty += (cause & 1);
2462 t3_write_reg(sc, A_SG_INT_CAUSE, reset);
2464 for (i = 0; i < sc->params.nports; i++) {
2465 struct port_info *pi = &sc->port[i];
2466 struct ifnet *ifp = pi->ifp;
2467 struct cmac *mac = &pi->mac;
2468 struct mac_stats *mstats = &mac->stats;
2470 if (!isset(&sc->open_device_map, pi->port_id))
2474 t3_mac_update_stats(mac);
2478 mstats->tx_frames_64 +
2479 mstats->tx_frames_65_127 +
2480 mstats->tx_frames_128_255 +
2481 mstats->tx_frames_256_511 +
2482 mstats->tx_frames_512_1023 +
2483 mstats->tx_frames_1024_1518 +
2484 mstats->tx_frames_1519_max;
2487 mstats->rx_frames_64 +
2488 mstats->rx_frames_65_127 +
2489 mstats->rx_frames_128_255 +
2490 mstats->rx_frames_256_511 +
2491 mstats->rx_frames_512_1023 +
2492 mstats->rx_frames_1024_1518 +
2493 mstats->rx_frames_1519_max;
2495 ifp->if_obytes = mstats->tx_octets;
2496 ifp->if_ibytes = mstats->rx_octets;
2497 ifp->if_omcasts = mstats->tx_mcast_frames;
2498 ifp->if_imcasts = mstats->rx_mcast_frames;
2500 ifp->if_collisions =
2501 mstats->tx_total_collisions;
2503 ifp->if_iqdrops = mstats->rx_cong_drops;
2506 mstats->tx_excess_collisions +
2507 mstats->tx_underrun +
2508 mstats->tx_len_errs +
2509 mstats->tx_mac_internal_errs +
2510 mstats->tx_excess_deferral +
2511 mstats->tx_fcs_errs;
2514 mstats->rx_data_errs +
2515 mstats->rx_sequence_errs +
2517 mstats->rx_too_long +
2518 mstats->rx_mac_internal_errs +
2520 mstats->rx_fcs_errs;
2525 /* Count rx fifo overflows, once per second */
2526 cause = t3_read_reg(sc, A_XGM_INT_CAUSE + mac->offset);
2528 if (cause & F_RXFIFO_OVERFLOW) {
2529 mac->stats.rx_fifo_ovfl++;
2530 reset |= F_RXFIFO_OVERFLOW;
2532 t3_write_reg(sc, A_XGM_INT_CAUSE + mac->offset, reset);
2537 touch_bars(device_t dev)
2542 #if !defined(__LP64__) && 0
2545 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v);
2546 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v);
2547 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v);
2548 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v);
2549 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v);
2550 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v);
2555 set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset)
2559 u32 aligned_offset, aligned_len, *p;
2560 struct adapter *adapter = pi->adapter;
2563 aligned_offset = offset & ~3;
2564 aligned_len = (len + (offset & 3) + 3) & ~3;
2566 if (aligned_offset != offset || aligned_len != len) {
2567 buf = malloc(aligned_len, M_DEVBUF, M_WAITOK|M_ZERO);
2570 err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf);
2571 if (!err && aligned_len > 4)
2572 err = t3_seeprom_read(adapter,
2573 aligned_offset + aligned_len - 4,
2574 (u32 *)&buf[aligned_len - 4]);
2577 memcpy(buf + (offset & 3), data, len);
2579 buf = (uint8_t *)(uintptr_t)data;
2581 err = t3_seeprom_wp(adapter, 0);
2585 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2586 err = t3_seeprom_write(adapter, aligned_offset, *p);
2587 aligned_offset += 4;
2591 err = t3_seeprom_wp(adapter, 1);
2594 free(buf, M_DEVBUF);
2600 in_range(int val, int lo, int hi)
2602 return val < 0 || (val <= hi && val >= lo);
2606 cxgb_extension_open(struct cdev *dev, int flags, int fmp, struct thread *td)
2612 cxgb_extension_close(struct cdev *dev, int flags, int fmt, struct thread *td)
2618 cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data,
2619 int fflag, struct thread *td)
2622 struct port_info *pi = dev->si_drv1;
2623 adapter_t *sc = pi->adapter;
2625 #ifdef PRIV_SUPPORTED
2626 if (priv_check(td, PRIV_DRIVER)) {
2628 printf("user does not have access to privileged ioctls\n");
2634 printf("user does not have access to privileged ioctls\n");
2640 case CHELSIO_GET_MIIREG: {
2642 struct cphy *phy = &pi->phy;
2643 struct ch_mii_data *mid = (struct ch_mii_data *)data;
2645 if (!phy->mdio_read)
2646 return (EOPNOTSUPP);
2648 mmd = mid->phy_id >> 8;
2651 else if (mmd > MDIO_DEV_VEND2)
2654 error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd,
2655 mid->reg_num, &val);
2657 error = phy->mdio_read(sc, mid->phy_id & 0x1f, 0,
2658 mid->reg_num & 0x1f, &val);
2663 case CHELSIO_SET_MIIREG: {
2664 struct cphy *phy = &pi->phy;
2665 struct ch_mii_data *mid = (struct ch_mii_data *)data;
2667 if (!phy->mdio_write)
2668 return (EOPNOTSUPP);
2670 mmd = mid->phy_id >> 8;
2673 else if (mmd > MDIO_DEV_VEND2)
2676 error = phy->mdio_write(sc, mid->phy_id & 0x1f,
2677 mmd, mid->reg_num, mid->val_in);
2679 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 0,
2680 mid->reg_num & 0x1f,
2684 case CHELSIO_SETREG: {
2685 struct ch_reg *edata = (struct ch_reg *)data;
2686 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
2688 t3_write_reg(sc, edata->addr, edata->val);
2691 case CHELSIO_GETREG: {
2692 struct ch_reg *edata = (struct ch_reg *)data;
2693 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
2695 edata->val = t3_read_reg(sc, edata->addr);
2698 case CHELSIO_GET_SGE_CONTEXT: {
2699 struct ch_cntxt *ecntxt = (struct ch_cntxt *)data;
2700 mtx_lock_spin(&sc->sge.reg_lock);
2701 switch (ecntxt->cntxt_type) {
2702 case CNTXT_TYPE_EGRESS:
2703 error = -t3_sge_read_ecntxt(sc, ecntxt->cntxt_id,
2707 error = -t3_sge_read_fl(sc, ecntxt->cntxt_id,
2710 case CNTXT_TYPE_RSP:
2711 error = -t3_sge_read_rspq(sc, ecntxt->cntxt_id,
2715 error = -t3_sge_read_cq(sc, ecntxt->cntxt_id,
2722 mtx_unlock_spin(&sc->sge.reg_lock);
2725 case CHELSIO_GET_SGE_DESC: {
2726 struct ch_desc *edesc = (struct ch_desc *)data;
2728 if (edesc->queue_num >= SGE_QSETS * 6)
2730 ret = t3_get_desc(&sc->sge.qs[edesc->queue_num / 6],
2731 edesc->queue_num % 6, edesc->idx, edesc->data);
2737 case CHELSIO_GET_QSET_PARAMS: {
2738 struct qset_params *q;
2739 struct ch_qset_params *t = (struct ch_qset_params *)data;
2740 int q1 = pi->first_qset;
2741 int nqsets = pi->nqsets;
2744 if (t->qset_idx >= nqsets)
2747 i = q1 + t->qset_idx;
2748 q = &sc->params.sge.qset[i];
2749 t->rspq_size = q->rspq_size;
2750 t->txq_size[0] = q->txq_size[0];
2751 t->txq_size[1] = q->txq_size[1];
2752 t->txq_size[2] = q->txq_size[2];
2753 t->fl_size[0] = q->fl_size;
2754 t->fl_size[1] = q->jumbo_size;
2755 t->polling = q->polling;
2757 t->intr_lat = q->coalesce_usecs;
2758 t->cong_thres = q->cong_thres;
2761 if (sc->flags & USING_MSIX)
2762 t->vector = rman_get_start(sc->msix_irq_res[i]);
2764 t->vector = rman_get_start(sc->irq_res);
2768 case CHELSIO_GET_QSET_NUM: {
2769 struct ch_reg *edata = (struct ch_reg *)data;
2770 edata->val = pi->nqsets;
2773 case CHELSIO_LOAD_FW: {
2776 struct ch_mem_range *t = (struct ch_mem_range *)data;
2779 * You're allowed to load a firmware only before FULL_INIT_DONE
2781 * FW_UPTODATE is also set so the rest of the initialization
2782 * will not overwrite what was loaded here. This gives you the
2783 * flexibility to load any firmware (and maybe shoot yourself in
2788 if (sc->open_device_map || sc->flags & FULL_INIT_DONE) {
2793 fw_data = malloc(t->len, M_DEVBUF, M_NOWAIT);
2797 error = copyin(t->buf, fw_data, t->len);
2800 error = -t3_load_fw(sc, fw_data, t->len);
2802 if (t3_get_fw_version(sc, &vers) == 0) {
2803 snprintf(&sc->fw_version[0], sizeof(sc->fw_version),
2804 "%d.%d.%d", G_FW_VERSION_MAJOR(vers),
2805 G_FW_VERSION_MINOR(vers), G_FW_VERSION_MICRO(vers));
2809 sc->flags |= FW_UPTODATE;
2811 free(fw_data, M_DEVBUF);
2815 case CHELSIO_LOAD_BOOT: {
2817 struct ch_mem_range *t = (struct ch_mem_range *)data;
2819 boot_data = malloc(t->len, M_DEVBUF, M_NOWAIT);
2823 error = copyin(t->buf, boot_data, t->len);
2825 error = -t3_load_boot(sc, boot_data, t->len);
2827 free(boot_data, M_DEVBUF);
2830 case CHELSIO_GET_PM: {
2831 struct ch_pm *m = (struct ch_pm *)data;
2832 struct tp_params *p = &sc->params.tp;
2834 if (!is_offload(sc))
2835 return (EOPNOTSUPP);
2837 m->tx_pg_sz = p->tx_pg_size;
2838 m->tx_num_pg = p->tx_num_pgs;
2839 m->rx_pg_sz = p->rx_pg_size;
2840 m->rx_num_pg = p->rx_num_pgs;
2841 m->pm_total = p->pmtx_size + p->chan_rx_size * p->nchan;
2845 case CHELSIO_SET_PM: {
2846 struct ch_pm *m = (struct ch_pm *)data;
2847 struct tp_params *p = &sc->params.tp;
2849 if (!is_offload(sc))
2850 return (EOPNOTSUPP);
2851 if (sc->flags & FULL_INIT_DONE)
2854 if (!m->rx_pg_sz || (m->rx_pg_sz & (m->rx_pg_sz - 1)) ||
2855 !m->tx_pg_sz || (m->tx_pg_sz & (m->tx_pg_sz - 1)))
2856 return (EINVAL); /* not power of 2 */
2857 if (!(m->rx_pg_sz & 0x14000))
2858 return (EINVAL); /* not 16KB or 64KB */
2859 if (!(m->tx_pg_sz & 0x1554000))
2861 if (m->tx_num_pg == -1)
2862 m->tx_num_pg = p->tx_num_pgs;
2863 if (m->rx_num_pg == -1)
2864 m->rx_num_pg = p->rx_num_pgs;
2865 if (m->tx_num_pg % 24 || m->rx_num_pg % 24)
2867 if (m->rx_num_pg * m->rx_pg_sz > p->chan_rx_size ||
2868 m->tx_num_pg * m->tx_pg_sz > p->chan_tx_size)
2871 p->rx_pg_size = m->rx_pg_sz;
2872 p->tx_pg_size = m->tx_pg_sz;
2873 p->rx_num_pgs = m->rx_num_pg;
2874 p->tx_num_pgs = m->tx_num_pg;
2877 case CHELSIO_SETMTUTAB: {
2878 struct ch_mtus *m = (struct ch_mtus *)data;
2881 if (!is_offload(sc))
2882 return (EOPNOTSUPP);
2883 if (offload_running(sc))
2885 if (m->nmtus != NMTUS)
2887 if (m->mtus[0] < 81) /* accommodate SACK */
2891 * MTUs must be in ascending order
2893 for (i = 1; i < NMTUS; ++i)
2894 if (m->mtus[i] < m->mtus[i - 1])
2897 memcpy(sc->params.mtus, m->mtus, sizeof(sc->params.mtus));
2900 case CHELSIO_GETMTUTAB: {
2901 struct ch_mtus *m = (struct ch_mtus *)data;
2903 if (!is_offload(sc))
2904 return (EOPNOTSUPP);
2906 memcpy(m->mtus, sc->params.mtus, sizeof(m->mtus));
2910 case CHELSIO_GET_MEM: {
2911 struct ch_mem_range *t = (struct ch_mem_range *)data;
2917 * Use these to avoid modifying len/addr in the the return
2920 uint32_t len = t->len, addr = t->addr;
2922 if (!is_offload(sc))
2923 return (EOPNOTSUPP);
2924 if (!(sc->flags & FULL_INIT_DONE))
2925 return (EIO); /* need the memory controllers */
2926 if ((addr & 0x7) || (len & 0x7))
2928 if (t->mem_id == MEM_CM)
2930 else if (t->mem_id == MEM_PMRX)
2932 else if (t->mem_id == MEM_PMTX)
2939 * bits 0..9: chip version
2940 * bits 10..15: chip revision
2942 t->version = 3 | (sc->params.rev << 10);
2945 * Read 256 bytes at a time as len can be large and we don't
2946 * want to use huge intermediate buffers.
2948 useraddr = (uint8_t *)t->buf;
2950 unsigned int chunk = min(len, sizeof(buf));
2952 error = t3_mc7_bd_read(mem, addr / 8, chunk / 8, buf);
2955 if (copyout(buf, useraddr, chunk))
2963 case CHELSIO_READ_TCAM_WORD: {
2964 struct ch_tcam_word *t = (struct ch_tcam_word *)data;
2966 if (!is_offload(sc))
2967 return (EOPNOTSUPP);
2968 if (!(sc->flags & FULL_INIT_DONE))
2969 return (EIO); /* need MC5 */
2970 return -t3_read_mc5_range(&sc->mc5, t->addr, 1, t->buf);
2973 case CHELSIO_SET_TRACE_FILTER: {
2974 struct ch_trace *t = (struct ch_trace *)data;
2975 const struct trace_params *tp;
2977 tp = (const struct trace_params *)&t->sip;
2979 t3_config_trace_filter(sc, tp, 0, t->invert_match,
2982 t3_config_trace_filter(sc, tp, 1, t->invert_match,
2986 case CHELSIO_SET_PKTSCHED: {
2987 struct ch_pktsched_params *p = (struct ch_pktsched_params *)data;
2988 if (sc->open_device_map == 0)
2990 send_pktsched_cmd(sc, p->sched, p->idx, p->min, p->max,
2994 case CHELSIO_IFCONF_GETREGS: {
2995 struct ch_ifconf_regs *regs = (struct ch_ifconf_regs *)data;
2996 int reglen = cxgb_get_regs_len();
2997 uint8_t *buf = malloc(reglen, M_DEVBUF, M_NOWAIT);
3001 if (regs->len > reglen)
3003 else if (regs->len < reglen)
3007 cxgb_get_regs(sc, regs, buf);
3008 error = copyout(buf, regs->data, reglen);
3010 free(buf, M_DEVBUF);
3014 case CHELSIO_SET_HW_SCHED: {
3015 struct ch_hw_sched *t = (struct ch_hw_sched *)data;
3016 unsigned int ticks_per_usec = core_ticks_per_usec(sc);
3018 if ((sc->flags & FULL_INIT_DONE) == 0)
3019 return (EAGAIN); /* need TP to be initialized */
3020 if (t->sched >= NTX_SCHED || !in_range(t->mode, 0, 1) ||
3021 !in_range(t->channel, 0, 1) ||
3022 !in_range(t->kbps, 0, 10000000) ||
3023 !in_range(t->class_ipg, 0, 10000 * 65535 / ticks_per_usec) ||
3024 !in_range(t->flow_ipg, 0,
3025 dack_ticks_to_usec(sc, 0x7ff)))
3029 error = t3_config_sched(sc, t->kbps, t->sched);
3033 if (t->class_ipg >= 0)
3034 t3_set_sched_ipg(sc, t->sched, t->class_ipg);
3035 if (t->flow_ipg >= 0) {
3036 t->flow_ipg *= 1000; /* us -> ns */
3037 t3_set_pace_tbl(sc, &t->flow_ipg, t->sched, 1);
3040 int bit = 1 << (S_TX_MOD_TIMER_MODE + t->sched);
3042 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP,
3043 bit, t->mode ? bit : 0);
3045 if (t->channel >= 0)
3046 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP,
3047 1 << t->sched, t->channel << t->sched);
3050 case CHELSIO_GET_EEPROM: {
3052 struct ch_eeprom *e = (struct ch_eeprom *)data;
3053 uint8_t *buf = malloc(EEPROMSIZE, M_DEVBUF, M_NOWAIT);
3058 e->magic = EEPROM_MAGIC;
3059 for (i = e->offset & ~3; !error && i < e->offset + e->len; i += 4)
3060 error = -t3_seeprom_read(sc, i, (uint32_t *)&buf[i]);
3063 error = copyout(buf + e->offset, e->data, e->len);
3065 free(buf, M_DEVBUF);
3068 case CHELSIO_CLEAR_STATS: {
3069 if (!(sc->flags & FULL_INIT_DONE))
3073 t3_mac_update_stats(&pi->mac);
3074 memset(&pi->mac.stats, 0, sizeof(pi->mac.stats));
3078 case CHELSIO_GET_UP_LA: {
3079 struct ch_up_la *la = (struct ch_up_la *)data;
3080 uint8_t *buf = malloc(LA_BUFSIZE, M_DEVBUF, M_NOWAIT);
3084 if (la->bufsize < LA_BUFSIZE)
3088 error = -t3_get_up_la(sc, &la->stopped, &la->idx,
3091 error = copyout(buf, la->data, la->bufsize);
3093 free(buf, M_DEVBUF);
3096 case CHELSIO_GET_UP_IOQS: {
3097 struct ch_up_ioqs *ioqs = (struct ch_up_ioqs *)data;
3098 uint8_t *buf = malloc(IOQS_BUFSIZE, M_DEVBUF, M_NOWAIT);
3104 if (ioqs->bufsize < IOQS_BUFSIZE)
3108 error = -t3_get_up_ioqs(sc, &ioqs->bufsize, buf);
3111 v = (uint32_t *)buf;
3113 ioqs->bufsize -= 4 * sizeof(uint32_t);
3114 ioqs->ioq_rx_enable = *v++;
3115 ioqs->ioq_tx_enable = *v++;
3116 ioqs->ioq_rx_status = *v++;
3117 ioqs->ioq_tx_status = *v++;
3119 error = copyout(v, ioqs->data, ioqs->bufsize);
3122 free(buf, M_DEVBUF);
3126 return (EOPNOTSUPP);
3133 static __inline void
3134 reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start,
3137 uint32_t *p = (uint32_t *)(buf + start);
3139 for ( ; start <= end; start += sizeof(uint32_t))
3140 *p++ = t3_read_reg(ap, start);
3143 #define T3_REGMAP_SIZE (3 * 1024)
3145 cxgb_get_regs_len(void)
3147 return T3_REGMAP_SIZE;
3151 cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf)
3156 * bits 0..9: chip version
3157 * bits 10..15: chip revision
3158 * bit 31: set for PCIe cards
3160 regs->version = 3 | (sc->params.rev << 10) | (is_pcie(sc) << 31);
3163 * We skip the MAC statistics registers because they are clear-on-read.
3164 * Also reading multi-register stats would need to synchronize with the
3165 * periodic mac stats accumulation. Hard to justify the complexity.
3167 memset(buf, 0, cxgb_get_regs_len());
3168 reg_block_dump(sc, buf, 0, A_SG_RSPQ_CREDIT_RETURN);
3169 reg_block_dump(sc, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT);
3170 reg_block_dump(sc, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE);
3171 reg_block_dump(sc, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA);
3172 reg_block_dump(sc, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3);
3173 reg_block_dump(sc, buf, A_XGM_SERDES_STATUS0,
3174 XGM_REG(A_XGM_SERDES_STAT3, 1));
3175 reg_block_dump(sc, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1),
3176 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1));
3180 MODULE_DEPEND(if_cxgb, cxgb_t3fw, 1, 1, 1);