1 /**************************************************************************
3 Copyright (c) 2007-2009, Chelsio Inc.
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
9 1. Redistributions of source code must retain the above copyright notice,
10 this list of conditions and the following disclaimer.
12 2. Neither the name of the Chelsio Corporation nor the names of its
13 contributors may be used to endorse or promote products derived from
14 this software without specific prior written permission.
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
28 ***************************************************************************/
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/param.h>
34 #include <sys/systm.h>
35 #include <sys/kernel.h>
37 #include <sys/module.h>
38 #include <sys/pciio.h>
40 #include <machine/bus.h>
41 #include <machine/resource.h>
42 #include <sys/bus_dma.h>
45 #include <sys/ioccom.h>
47 #include <sys/linker.h>
48 #include <sys/firmware.h>
49 #include <sys/socket.h>
50 #include <sys/sockio.h>
52 #include <sys/sysctl.h>
53 #include <sys/syslog.h>
54 #include <sys/queue.h>
55 #include <sys/taskqueue.h>
59 #include <net/ethernet.h>
61 #include <net/if_arp.h>
62 #include <net/if_dl.h>
63 #include <net/if_media.h>
64 #include <net/if_types.h>
65 #include <net/if_vlan_var.h>
67 #include <netinet/in_systm.h>
68 #include <netinet/in.h>
69 #include <netinet/if_ether.h>
70 #include <netinet/ip.h>
71 #include <netinet/ip.h>
72 #include <netinet/tcp.h>
73 #include <netinet/udp.h>
75 #include <dev/pci/pcireg.h>
76 #include <dev/pci/pcivar.h>
77 #include <dev/pci/pci_private.h>
79 #include <cxgb_include.h>
85 static int cxgb_setup_interrupts(adapter_t *);
86 static void cxgb_teardown_interrupts(adapter_t *);
87 static int cxgb_begin_op(struct port_info *, const char *);
88 static int cxgb_begin_detach(struct port_info *);
89 static int cxgb_end_op(struct port_info *);
90 static void cxgb_init(void *);
91 static int cxgb_init_synchronized(struct port_info *);
92 static int cxgb_uninit_synchronized(struct port_info *);
93 static int cxgb_ioctl(struct ifnet *, unsigned long, caddr_t);
94 static int cxgb_media_change(struct ifnet *);
95 static int cxgb_ifm_type(int);
96 static void cxgb_build_medialist(struct port_info *);
97 static void cxgb_media_status(struct ifnet *, struct ifmediareq *);
98 static int setup_sge_qsets(adapter_t *);
99 static void cxgb_async_intr(void *);
100 static void cxgb_ext_intr_handler(void *, int);
101 static void cxgb_tick_handler(void *, int);
102 static void cxgb_tick(void *);
103 static void setup_rss(adapter_t *sc);
105 /* Attachment glue for the PCI controller end of the device. Each port of
106 * the device is attached separately, as defined later.
108 static int cxgb_controller_probe(device_t);
109 static int cxgb_controller_attach(device_t);
110 static int cxgb_controller_detach(device_t);
111 static void cxgb_free(struct adapter *);
112 static __inline void reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start,
114 static void cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf);
115 static int cxgb_get_regs_len(void);
116 static int offload_open(struct port_info *pi);
117 static void touch_bars(device_t dev);
118 static int offload_close(struct t3cdev *tdev);
119 static void cxgb_update_mac_settings(struct port_info *p);
121 static device_method_t cxgb_controller_methods[] = {
122 DEVMETHOD(device_probe, cxgb_controller_probe),
123 DEVMETHOD(device_attach, cxgb_controller_attach),
124 DEVMETHOD(device_detach, cxgb_controller_detach),
127 DEVMETHOD(bus_print_child, bus_generic_print_child),
128 DEVMETHOD(bus_driver_added, bus_generic_driver_added),
133 static driver_t cxgb_controller_driver = {
135 cxgb_controller_methods,
136 sizeof(struct adapter)
139 static devclass_t cxgb_controller_devclass;
140 DRIVER_MODULE(cxgbc, pci, cxgb_controller_driver, cxgb_controller_devclass, 0, 0);
143 * Attachment glue for the ports. Attachment is done directly to the
146 static int cxgb_port_probe(device_t);
147 static int cxgb_port_attach(device_t);
148 static int cxgb_port_detach(device_t);
150 static device_method_t cxgb_port_methods[] = {
151 DEVMETHOD(device_probe, cxgb_port_probe),
152 DEVMETHOD(device_attach, cxgb_port_attach),
153 DEVMETHOD(device_detach, cxgb_port_detach),
157 static driver_t cxgb_port_driver = {
163 static d_ioctl_t cxgb_extension_ioctl;
164 static d_open_t cxgb_extension_open;
165 static d_close_t cxgb_extension_close;
167 static struct cdevsw cxgb_cdevsw = {
168 .d_version = D_VERSION,
170 .d_open = cxgb_extension_open,
171 .d_close = cxgb_extension_close,
172 .d_ioctl = cxgb_extension_ioctl,
176 static devclass_t cxgb_port_devclass;
177 DRIVER_MODULE(cxgb, cxgbc, cxgb_port_driver, cxgb_port_devclass, 0, 0);
180 * The driver uses the best interrupt scheme available on a platform in the
181 * order MSI-X, MSI, legacy pin interrupts. This parameter determines which
182 * of these schemes the driver may consider as follows:
184 * msi = 2: choose from among all three options
185 * msi = 1 : only consider MSI and pin interrupts
186 * msi = 0: force pin interrupts
188 static int msi_allowed = 2;
190 TUNABLE_INT("hw.cxgb.msi_allowed", &msi_allowed);
191 SYSCTL_NODE(_hw, OID_AUTO, cxgb, CTLFLAG_RD, 0, "CXGB driver parameters");
192 SYSCTL_UINT(_hw_cxgb, OID_AUTO, msi_allowed, CTLFLAG_RDTUN, &msi_allowed, 0,
193 "MSI-X, MSI, INTx selector");
196 * The driver enables offload as a default.
197 * To disable it, use ofld_disable = 1.
199 static int ofld_disable = 0;
200 TUNABLE_INT("hw.cxgb.ofld_disable", &ofld_disable);
201 SYSCTL_UINT(_hw_cxgb, OID_AUTO, ofld_disable, CTLFLAG_RDTUN, &ofld_disable, 0,
202 "disable ULP offload");
205 * The driver uses an auto-queue algorithm by default.
206 * To disable it and force a single queue-set per port, use multiq = 0
208 static int multiq = 1;
209 TUNABLE_INT("hw.cxgb.multiq", &multiq);
210 SYSCTL_UINT(_hw_cxgb, OID_AUTO, multiq, CTLFLAG_RDTUN, &multiq, 0,
211 "use min(ncpus/ports, 8) queue-sets per port");
214 * By default the driver will not update the firmware unless
215 * it was compiled against a newer version
218 static int force_fw_update = 0;
219 TUNABLE_INT("hw.cxgb.force_fw_update", &force_fw_update);
220 SYSCTL_UINT(_hw_cxgb, OID_AUTO, force_fw_update, CTLFLAG_RDTUN, &force_fw_update, 0,
221 "update firmware even if up to date");
223 int cxgb_use_16k_clusters = 1;
224 TUNABLE_INT("hw.cxgb.use_16k_clusters", &cxgb_use_16k_clusters);
225 SYSCTL_UINT(_hw_cxgb, OID_AUTO, use_16k_clusters, CTLFLAG_RDTUN,
226 &cxgb_use_16k_clusters, 0, "use 16kB clusters for the jumbo queue ");
229 * Tune the size of the output queue.
231 int cxgb_snd_queue_len = IFQ_MAXLEN;
232 TUNABLE_INT("hw.cxgb.snd_queue_len", &cxgb_snd_queue_len);
233 SYSCTL_UINT(_hw_cxgb, OID_AUTO, snd_queue_len, CTLFLAG_RDTUN,
234 &cxgb_snd_queue_len, 0, "send queue size ");
238 MAX_TXQ_ENTRIES = 16384,
239 MAX_CTRL_TXQ_ENTRIES = 1024,
240 MAX_RSPQ_ENTRIES = 16384,
241 MAX_RX_BUFFERS = 16384,
242 MAX_RX_JUMBO_BUFFERS = 16384,
244 MIN_CTRL_TXQ_ENTRIES = 4,
245 MIN_RSPQ_ENTRIES = 32,
247 MIN_FL_JUMBO_ENTRIES = 32
262 u32 report_filter_id:1;
270 enum { FILTER_NO_VLAN_PRI = 7 };
272 #define EEPROM_MAGIC 0x38E2F10C
274 #define PORT_MASK ((1 << MAX_NPORTS) - 1)
276 /* Table for probing the cards. The desc field isn't actually used */
282 } cxgb_identifiers[] = {
283 {PCI_VENDOR_ID_CHELSIO, 0x0020, 0, "PE9000"},
284 {PCI_VENDOR_ID_CHELSIO, 0x0021, 1, "T302E"},
285 {PCI_VENDOR_ID_CHELSIO, 0x0022, 2, "T310E"},
286 {PCI_VENDOR_ID_CHELSIO, 0x0023, 3, "T320X"},
287 {PCI_VENDOR_ID_CHELSIO, 0x0024, 1, "T302X"},
288 {PCI_VENDOR_ID_CHELSIO, 0x0025, 3, "T320E"},
289 {PCI_VENDOR_ID_CHELSIO, 0x0026, 2, "T310X"},
290 {PCI_VENDOR_ID_CHELSIO, 0x0030, 2, "T3B10"},
291 {PCI_VENDOR_ID_CHELSIO, 0x0031, 3, "T3B20"},
292 {PCI_VENDOR_ID_CHELSIO, 0x0032, 1, "T3B02"},
293 {PCI_VENDOR_ID_CHELSIO, 0x0033, 4, "T3B04"},
294 {PCI_VENDOR_ID_CHELSIO, 0x0035, 6, "T3C10"},
295 {PCI_VENDOR_ID_CHELSIO, 0x0036, 3, "S320E-CR"},
296 {PCI_VENDOR_ID_CHELSIO, 0x0037, 7, "N320E-G2"},
300 static int set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset);
304 t3rev2char(struct adapter *adapter)
308 switch(adapter->params.rev) {
323 static struct cxgb_ident *
324 cxgb_get_ident(device_t dev)
326 struct cxgb_ident *id;
328 for (id = cxgb_identifiers; id->desc != NULL; id++) {
329 if ((id->vendor == pci_get_vendor(dev)) &&
330 (id->device == pci_get_device(dev))) {
337 static const struct adapter_info *
338 cxgb_get_adapter_info(device_t dev)
340 struct cxgb_ident *id;
341 const struct adapter_info *ai;
343 id = cxgb_get_ident(dev);
347 ai = t3_get_adapter_info(id->index);
353 cxgb_controller_probe(device_t dev)
355 const struct adapter_info *ai;
356 char *ports, buf[80];
358 struct adapter *sc = device_get_softc(dev);
360 ai = cxgb_get_adapter_info(dev);
364 nports = ai->nports0 + ai->nports1;
370 snprintf(buf, sizeof(buf), "%s %sNIC, rev: %d nports: %d %s",
371 ai->desc, is_offload(sc) ? "R" : "",
372 sc->params.rev, nports, ports);
373 device_set_desc_copy(dev, buf);
374 return (BUS_PROBE_DEFAULT);
377 #define FW_FNAME "cxgb_t3fw"
378 #define TPEEPROM_NAME "cxgb_t3%c_tp_eeprom"
379 #define TPSRAM_NAME "cxgb_t3%c_protocol_sram"
382 upgrade_fw(adapter_t *sc)
384 #ifdef FIRMWARE_LATEST
385 const struct firmware *fw;
391 if ((fw = firmware_get(FW_FNAME)) == NULL) {
392 device_printf(sc->dev, "Could not find firmware image %s\n", FW_FNAME);
395 device_printf(sc->dev, "updating firmware on card\n");
396 status = t3_load_fw(sc, (const uint8_t *)fw->data, fw->datasize);
398 device_printf(sc->dev, "firmware update returned %s %d\n", (status == 0) ? "success" : "fail", status);
400 firmware_put(fw, FIRMWARE_UNLOAD);
406 * The cxgb_controller_attach function is responsible for the initial
407 * bringup of the device. Its responsibilities include:
409 * 1. Determine if the device supports MSI or MSI-X.
410 * 2. Allocate bus resources so that we can access the Base Address Register
411 * 3. Create and initialize mutexes for the controller and its control
412 * logic such as SGE and MDIO.
413 * 4. Call hardware specific setup routine for the adapter as a whole.
414 * 5. Allocate the BAR for doing MSI-X.
415 * 6. Setup the line interrupt iff MSI-X is not supported.
416 * 7. Create the driver's taskq.
417 * 8. Start one task queue service thread.
418 * 9. Check if the firmware and SRAM are up-to-date. They will be
419 * auto-updated later (before FULL_INIT_DONE), if required.
420 * 10. Create a child device for each MAC (port)
421 * 11. Initialize T3 private state.
422 * 12. Trigger the LED
423 * 13. Setup offload iff supported.
424 * 14. Reset/restart the tick callout.
427 * NOTE: Any modification or deviation from this list MUST be reflected in
428 * the above comment. Failure to do so will result in problems on various
429 * error conditions including link flapping.
432 cxgb_controller_attach(device_t dev)
435 const struct adapter_info *ai;
445 sc = device_get_softc(dev);
448 ai = cxgb_get_adapter_info(dev);
451 * XXX not really related but a recent addition
454 /* find the PCIe link width and set max read request to 4KB*/
455 if (pci_find_extcap(dev, PCIY_EXPRESS, ®) == 0) {
457 lnk = pci_read_config(dev, reg + 0x12, 2);
458 sc->link_width = (lnk >> 4) & 0x3f;
460 pectl = pci_read_config(dev, reg + 0x8, 2);
461 pectl = (pectl & ~0x7000) | (5 << 12);
462 pci_write_config(dev, reg + 0x8, pectl, 2);
465 if (sc->link_width != 0 && sc->link_width <= 4 &&
466 (ai->nports0 + ai->nports1) <= 2) {
467 device_printf(sc->dev,
468 "PCIe x%d Link, expect reduced performance\n",
473 pci_enable_busmaster(dev);
475 * Allocate the registers and make them available to the driver.
476 * The registers that we care about for NIC mode are in BAR 0
478 sc->regs_rid = PCIR_BAR(0);
479 if ((sc->regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
480 &sc->regs_rid, RF_ACTIVE)) == NULL) {
481 device_printf(dev, "Cannot allocate BAR region 0\n");
484 sc->udbs_rid = PCIR_BAR(2);
486 if (is_offload(sc) &&
487 ((sc->udbs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
488 &sc->udbs_rid, RF_ACTIVE)) == NULL)) {
489 device_printf(dev, "Cannot allocate BAR region 1\n");
494 snprintf(sc->lockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb controller lock %d",
495 device_get_unit(dev));
496 ADAPTER_LOCK_INIT(sc, sc->lockbuf);
498 snprintf(sc->reglockbuf, ADAPTER_LOCK_NAME_LEN, "SGE reg lock %d",
499 device_get_unit(dev));
500 snprintf(sc->mdiolockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb mdio lock %d",
501 device_get_unit(dev));
502 snprintf(sc->elmerlockbuf, ADAPTER_LOCK_NAME_LEN, "cxgb elmer lock %d",
503 device_get_unit(dev));
505 MTX_INIT(&sc->sge.reg_lock, sc->reglockbuf, NULL, MTX_SPIN);
506 MTX_INIT(&sc->mdio_lock, sc->mdiolockbuf, NULL, MTX_DEF);
507 MTX_INIT(&sc->elmer_lock, sc->elmerlockbuf, NULL, MTX_DEF);
509 sc->bt = rman_get_bustag(sc->regs_res);
510 sc->bh = rman_get_bushandle(sc->regs_res);
511 sc->mmio_len = rman_get_size(sc->regs_res);
513 for (i = 0; i < MAX_NPORTS; i++)
514 sc->port[i].adapter = sc;
516 if (t3_prep_adapter(sc, ai, 1) < 0) {
517 printf("prep adapter failed\n");
521 /* Allocate the BAR for doing MSI-X. If it succeeds, try to allocate
522 * enough messages for the queue sets. If that fails, try falling
523 * back to MSI. If that fails, then try falling back to the legacy
524 * interrupt pin model.
528 sc->msix_regs_rid = 0x20;
529 if ((msi_allowed >= 2) &&
530 (sc->msix_regs_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
531 &sc->msix_regs_rid, RF_ACTIVE)) != NULL) {
534 port_qsets = min(SGE_QSETS/sc->params.nports, mp_ncpus);
535 msi_needed = sc->msi_count = sc->params.nports * port_qsets + 1;
537 if (pci_msix_count(dev) == 0 ||
538 (error = pci_alloc_msix(dev, &sc->msi_count)) != 0 ||
539 sc->msi_count != msi_needed) {
540 device_printf(dev, "alloc msix failed - "
541 "msi_count=%d, msi_needed=%d, err=%d; "
542 "will try MSI\n", sc->msi_count,
546 pci_release_msi(dev);
547 bus_release_resource(dev, SYS_RES_MEMORY,
548 sc->msix_regs_rid, sc->msix_regs_res);
549 sc->msix_regs_res = NULL;
551 sc->flags |= USING_MSIX;
552 sc->cxgb_intr = cxgb_async_intr;
554 "using MSI-X interrupts (%u vectors)\n",
559 if ((msi_allowed >= 1) && (sc->msi_count == 0)) {
561 if ((error = pci_alloc_msi(dev, &sc->msi_count)) != 0) {
562 device_printf(dev, "alloc msi failed - "
563 "err=%d; will try INTx\n", error);
566 pci_release_msi(dev);
568 sc->flags |= USING_MSI;
569 sc->cxgb_intr = t3_intr_msi;
570 device_printf(dev, "using MSI interrupts\n");
574 if (sc->msi_count == 0) {
575 device_printf(dev, "using line interrupts\n");
576 sc->cxgb_intr = t3b_intr;
579 /* Create a private taskqueue thread for handling driver events */
580 #ifdef TASKQUEUE_CURRENT
581 sc->tq = taskqueue_create("cxgb_taskq", M_NOWAIT,
582 taskqueue_thread_enqueue, &sc->tq);
584 sc->tq = taskqueue_create_fast("cxgb_taskq", M_NOWAIT,
585 taskqueue_thread_enqueue, &sc->tq);
587 if (sc->tq == NULL) {
588 device_printf(dev, "failed to allocate controller task queue\n");
592 taskqueue_start_threads(&sc->tq, 1, PI_NET, "%s taskq",
593 device_get_nameunit(dev));
594 TASK_INIT(&sc->ext_intr_task, 0, cxgb_ext_intr_handler, sc);
595 TASK_INIT(&sc->tick_task, 0, cxgb_tick_handler, sc);
598 /* Create a periodic callout for checking adapter status */
599 callout_init(&sc->cxgb_tick_ch, TRUE);
601 if (t3_check_fw_version(sc) < 0 || force_fw_update) {
603 * Warn user that a firmware update will be attempted in init.
605 device_printf(dev, "firmware needs to be updated to version %d.%d.%d\n",
606 FW_VERSION_MAJOR, FW_VERSION_MINOR, FW_VERSION_MICRO);
607 sc->flags &= ~FW_UPTODATE;
609 sc->flags |= FW_UPTODATE;
612 if (t3_check_tpsram_version(sc) < 0) {
614 * Warn user that a firmware update will be attempted in init.
616 device_printf(dev, "SRAM needs to be updated to version %c-%d.%d.%d\n",
617 t3rev2char(sc), TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
618 sc->flags &= ~TPS_UPTODATE;
620 sc->flags |= TPS_UPTODATE;
624 * Create a child device for each MAC. The ethernet attachment
625 * will be done in these children.
627 for (i = 0; i < (sc)->params.nports; i++) {
628 struct port_info *pi;
630 if ((child = device_add_child(dev, "cxgb", -1)) == NULL) {
631 device_printf(dev, "failed to add child port\n");
637 pi->nqsets = port_qsets;
638 pi->first_qset = i*port_qsets;
640 pi->tx_chan = i >= ai->nports0;
641 pi->txpkt_intf = pi->tx_chan ? 2 * (i - ai->nports0) + 1 : 2 * i;
642 sc->rxpkt_map[pi->txpkt_intf] = i;
643 sc->port[i].tx_chan = i >= ai->nports0;
644 sc->portdev[i] = child;
645 device_set_softc(child, pi);
647 if ((error = bus_generic_attach(dev)) != 0)
650 /* initialize sge private state */
651 t3_sge_init_adapter(sc);
656 if (is_offload(sc)) {
657 setbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT);
658 cxgb_adapter_ofld(sc);
660 error = t3_get_fw_version(sc, &vers);
664 snprintf(&sc->fw_version[0], sizeof(sc->fw_version), "%d.%d.%d",
665 G_FW_VERSION_MAJOR(vers), G_FW_VERSION_MINOR(vers),
666 G_FW_VERSION_MICRO(vers));
668 snprintf(buf, sizeof(buf), "%s\t E/C: %s S/N: %s",
670 sc->params.vpd.ec, sc->params.vpd.sn);
671 device_set_desc_copy(dev, buf);
673 snprintf(&sc->port_types[0], sizeof(sc->port_types), "%x%x%x%x",
674 sc->params.vpd.port_type[0], sc->params.vpd.port_type[1],
675 sc->params.vpd.port_type[2], sc->params.vpd.port_type[3]);
677 device_printf(sc->dev, "Firmware Version %s\n", &sc->fw_version[0]);
678 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc);
679 t3_add_attach_sysctls(sc);
688 * The cxgb_controller_detach routine is called with the device is
689 * unloaded from the system.
693 cxgb_controller_detach(device_t dev)
697 sc = device_get_softc(dev);
705 * The cxgb_free() is called by the cxgb_controller_detach() routine
706 * to tear down the structures that were built up in
707 * cxgb_controller_attach(), and should be the final piece of work
708 * done when fully unloading the driver.
711 * 1. Shutting down the threads started by the cxgb_controller_attach()
713 * 2. Stopping the lower level device and all callouts (cxgb_down_locked()).
714 * 3. Detaching all of the port devices created during the
715 * cxgb_controller_attach() routine.
716 * 4. Removing the device children created via cxgb_controller_attach().
717 * 5. Releasing PCI resources associated with the device.
718 * 6. Turning off the offload support, iff it was turned on.
719 * 7. Destroying the mutexes created in cxgb_controller_attach().
723 cxgb_free(struct adapter *sc)
728 sc->flags |= CXGB_SHUTDOWN;
732 * Make sure all child devices are gone.
734 bus_generic_detach(sc->dev);
735 for (i = 0; i < (sc)->params.nports; i++) {
736 if (sc->portdev[i] &&
737 device_delete_child(sc->dev, sc->portdev[i]) != 0)
738 device_printf(sc->dev, "failed to delete child port\n");
742 * At this point, it is as if cxgb_port_detach has run on all ports, and
743 * cxgb_down has run on the adapter. All interrupts have been silenced,
744 * all open devices have been closed.
746 KASSERT(sc->open_device_map == 0, ("%s: device(s) still open (%x)",
747 __func__, sc->open_device_map));
748 for (i = 0; i < sc->params.nports; i++) {
749 KASSERT(sc->port[i].ifp == NULL, ("%s: port %i undead!",
754 * Finish off the adapter's callouts.
756 callout_drain(&sc->cxgb_tick_ch);
757 callout_drain(&sc->sge_timer_ch);
760 * Release resources grabbed under FULL_INIT_DONE by cxgb_up. The
761 * sysctls are cleaned up by the kernel linker.
763 if (sc->flags & FULL_INIT_DONE) {
764 t3_free_sge_resources(sc);
765 sc->flags &= ~FULL_INIT_DONE;
769 * Release all interrupt resources.
771 cxgb_teardown_interrupts(sc);
773 if (sc->flags & (USING_MSI | USING_MSIX)) {
774 device_printf(sc->dev, "releasing msi message(s)\n");
775 pci_release_msi(sc->dev);
777 device_printf(sc->dev, "no msi message to release\n");
780 if (sc->msix_regs_res != NULL) {
781 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->msix_regs_rid,
787 * Free the adapter's taskqueue.
789 if (sc->tq != NULL) {
790 taskqueue_free(sc->tq);
794 if (is_offload(sc)) {
795 clrbit(&sc->registered_device_map, OFFLOAD_DEVMAP_BIT);
796 cxgb_adapter_unofld(sc);
800 if (sc->flags & CXGB_OFLD_INIT)
801 cxgb_offload_deactivate(sc);
803 free(sc->filters, M_DEVBUF);
808 if (sc->udbs_res != NULL)
809 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->udbs_rid,
812 if (sc->regs_res != NULL)
813 bus_release_resource(sc->dev, SYS_RES_MEMORY, sc->regs_rid,
816 MTX_DESTROY(&sc->mdio_lock);
817 MTX_DESTROY(&sc->sge.reg_lock);
818 MTX_DESTROY(&sc->elmer_lock);
819 ADAPTER_LOCK_DEINIT(sc);
823 * setup_sge_qsets - configure SGE Tx/Rx/response queues
824 * @sc: the controller softc
826 * Determines how many sets of SGE queues to use and initializes them.
827 * We support multiple queue sets per port if we have MSI-X, otherwise
828 * just one queue set per port.
831 setup_sge_qsets(adapter_t *sc)
833 int i, j, err, irq_idx = 0, qset_idx = 0;
834 u_int ntxq = SGE_TXQ_PER_SET;
836 if ((err = t3_sge_alloc(sc)) != 0) {
837 device_printf(sc->dev, "t3_sge_alloc returned %d\n", err);
841 if (sc->params.rev > 0 && !(sc->flags & USING_MSI))
844 for (i = 0; i < (sc)->params.nports; i++) {
845 struct port_info *pi = &sc->port[i];
847 for (j = 0; j < pi->nqsets; j++, qset_idx++) {
848 err = t3_sge_alloc_qset(sc, qset_idx, (sc)->params.nports,
849 (sc->flags & USING_MSIX) ? qset_idx + 1 : irq_idx,
850 &sc->params.sge.qset[qset_idx], ntxq, pi);
852 t3_free_sge_resources(sc);
853 device_printf(sc->dev, "t3_sge_alloc_qset failed with %d\n",
864 cxgb_teardown_interrupts(adapter_t *sc)
868 for (i = 0; i < SGE_QSETS; i++) {
869 if (sc->msix_intr_tag[i] == NULL) {
871 /* Should have been setup fully or not at all */
872 KASSERT(sc->msix_irq_res[i] == NULL &&
873 sc->msix_irq_rid[i] == 0,
874 ("%s: half-done interrupt (%d).", __func__, i));
879 bus_teardown_intr(sc->dev, sc->msix_irq_res[i],
880 sc->msix_intr_tag[i]);
881 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->msix_irq_rid[i],
882 sc->msix_irq_res[i]);
884 sc->msix_irq_res[i] = sc->msix_intr_tag[i] = NULL;
885 sc->msix_irq_rid[i] = 0;
889 KASSERT(sc->irq_res != NULL,
890 ("%s: half-done interrupt.", __func__));
892 bus_teardown_intr(sc->dev, sc->irq_res, sc->intr_tag);
893 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid,
896 sc->irq_res = sc->intr_tag = NULL;
902 cxgb_setup_interrupts(adapter_t *sc)
904 struct resource *res;
906 int i, rid, err, intr_flag = sc->flags & (USING_MSI | USING_MSIX);
908 sc->irq_rid = intr_flag ? 1 : 0;
909 sc->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &sc->irq_rid,
910 RF_SHAREABLE | RF_ACTIVE);
911 if (sc->irq_res == NULL) {
912 device_printf(sc->dev, "Cannot allocate interrupt (%x, %u)\n",
913 intr_flag, sc->irq_rid);
917 err = bus_setup_intr(sc->dev, sc->irq_res,
918 INTR_MPSAFE | INTR_TYPE_NET,
922 sc->cxgb_intr, sc, &sc->intr_tag);
925 device_printf(sc->dev,
926 "Cannot set up interrupt (%x, %u, %d)\n",
927 intr_flag, sc->irq_rid, err);
928 bus_release_resource(sc->dev, SYS_RES_IRQ, sc->irq_rid,
930 sc->irq_res = sc->intr_tag = NULL;
935 /* That's all for INTx or MSI */
936 if (!(intr_flag & USING_MSIX) || err)
939 for (i = 0; i < sc->msi_count - 1; i++) {
941 res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &rid,
942 RF_SHAREABLE | RF_ACTIVE);
944 device_printf(sc->dev, "Cannot allocate interrupt "
945 "for message %d\n", rid);
950 err = bus_setup_intr(sc->dev, res, INTR_MPSAFE | INTR_TYPE_NET,
954 t3_intr_msix, &sc->sge.qs[i], &tag);
956 device_printf(sc->dev, "Cannot set up interrupt "
957 "for message %d (%d)\n", rid, err);
958 bus_release_resource(sc->dev, SYS_RES_IRQ, rid, res);
962 sc->msix_irq_rid[i] = rid;
963 sc->msix_irq_res[i] = res;
964 sc->msix_intr_tag[i] = tag;
968 cxgb_teardown_interrupts(sc);
975 cxgb_port_probe(device_t dev)
981 p = device_get_softc(dev);
983 snprintf(buf, sizeof(buf), "Port %d %s", p->port_id, desc);
984 device_set_desc_copy(dev, buf);
990 cxgb_makedev(struct port_info *pi)
993 pi->port_cdev = make_dev(&cxgb_cdevsw, pi->ifp->if_dunit,
994 UID_ROOT, GID_WHEEL, 0600, if_name(pi->ifp));
996 if (pi->port_cdev == NULL)
999 pi->port_cdev->si_drv1 = (void *)pi;
1004 #ifndef LRO_SUPPORTED
1008 #define IFCAP_LRO 0x0
1011 #ifdef TSO_SUPPORTED
1012 #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO)
1013 /* Don't enable TSO6 yet */
1014 #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_VLAN_HWCSUM | IFCAP_TSO4 | IFCAP_JUMBO_MTU | IFCAP_LRO)
1016 #define CXGB_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU)
1017 /* Don't enable TSO6 yet */
1018 #define CXGB_CAP_ENABLE (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | IFCAP_JUMBO_MTU)
1019 #define IFCAP_TSO4 0x0
1020 #define IFCAP_TSO6 0x0
1021 #define CSUM_TSO 0x0
1026 cxgb_port_attach(device_t dev)
1028 struct port_info *p;
1034 p = device_get_softc(dev);
1036 snprintf(p->lockbuf, PORT_NAME_LEN, "cxgb port lock %d:%d",
1037 device_get_unit(device_get_parent(dev)), p->port_id);
1038 PORT_LOCK_INIT(p, p->lockbuf);
1040 /* Allocate an ifnet object and set it up */
1041 ifp = p->ifp = if_alloc(IFT_ETHER);
1043 device_printf(dev, "Cannot allocate ifnet\n");
1048 * Note that there is currently no watchdog timer.
1050 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1051 ifp->if_init = cxgb_init;
1053 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1054 ifp->if_ioctl = cxgb_ioctl;
1055 ifp->if_start = cxgb_start;
1058 ifp->if_timer = 0; /* Disable ifnet watchdog */
1059 ifp->if_watchdog = NULL;
1061 ifp->if_snd.ifq_drv_maxlen = cxgb_snd_queue_len;
1062 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
1063 IFQ_SET_READY(&ifp->if_snd);
1065 ifp->if_hwassist = ifp->if_capabilities = ifp->if_capenable = 0;
1066 ifp->if_capabilities |= CXGB_CAP;
1067 ifp->if_capenable |= CXGB_CAP_ENABLE;
1068 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO);
1070 * disable TSO on 4-port - it isn't supported by the firmware yet
1072 if (p->adapter->params.nports > 2) {
1073 ifp->if_capabilities &= ~(IFCAP_TSO4 | IFCAP_TSO6);
1074 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_TSO6);
1075 ifp->if_hwassist &= ~CSUM_TSO;
1078 ether_ifattach(ifp, p->hw_addr);
1079 ifp->if_transmit = cxgb_transmit;
1080 ifp->if_qflush = cxgb_qflush;
1083 * Only default to jumbo frames on 10GigE
1085 if (p->adapter->params.nports <= 2)
1086 ifp->if_mtu = ETHERMTU_JUMBO;
1087 if ((err = cxgb_makedev(p)) != 0) {
1088 printf("makedev failed %d\n", err);
1092 /* Create a list of media supported by this port */
1093 ifmedia_init(&p->media, IFM_IMASK, cxgb_media_change,
1095 cxgb_build_medialist(p);
1097 t3_sge_init_port(p);
1103 * cxgb_port_detach() is called via the device_detach methods when
1104 * cxgb_free() calls the bus_generic_detach. It is responsible for
1105 * removing the device from the view of the kernel, i.e. from all
1106 * interfaces lists etc. This routine is only called when the driver is
1107 * being unloaded, not when the link goes down.
1110 cxgb_port_detach(device_t dev)
1112 struct port_info *p;
1116 p = device_get_softc(dev);
1119 cxgb_begin_detach(p);
1121 if (p->port_cdev != NULL)
1122 destroy_dev(p->port_cdev);
1124 cxgb_uninit_synchronized(p);
1125 ether_ifdetach(p->ifp);
1127 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
1128 struct sge_qset *qs = &sc->sge.qs[i];
1129 struct sge_txq *txq = &qs->txq[TXQ_ETH];
1131 callout_drain(&txq->txq_watchdog);
1132 callout_drain(&txq->txq_timer);
1135 PORT_LOCK_DEINIT(p);
1144 t3_fatal_err(struct adapter *sc)
1148 if (sc->flags & FULL_INIT_DONE) {
1150 t3_write_reg(sc, A_XGM_TX_CTRL, 0);
1151 t3_write_reg(sc, A_XGM_RX_CTRL, 0);
1152 t3_write_reg(sc, XGM_REG(A_XGM_TX_CTRL, 1), 0);
1153 t3_write_reg(sc, XGM_REG(A_XGM_RX_CTRL, 1), 0);
1154 t3_intr_disable(sc);
1156 device_printf(sc->dev,"encountered fatal error, operation suspended\n");
1157 if (!t3_cim_ctl_blk_read(sc, 0xa0, 4, fw_status))
1158 device_printf(sc->dev, "FW_ status: 0x%x, 0x%x, 0x%x, 0x%x\n",
1159 fw_status[0], fw_status[1], fw_status[2], fw_status[3]);
1163 t3_os_find_pci_capability(adapter_t *sc, int cap)
1166 struct pci_devinfo *dinfo;
1172 dinfo = device_get_ivars(dev);
1175 status = pci_read_config(dev, PCIR_STATUS, 2);
1176 if (!(status & PCIM_STATUS_CAPPRESENT))
1179 switch (cfg->hdrtype & PCIM_HDRTYPE) {
1185 ptr = PCIR_CAP_PTR_2;
1191 ptr = pci_read_config(dev, ptr, 1);
1194 if (pci_read_config(dev, ptr + PCICAP_ID, 1) == cap)
1196 ptr = pci_read_config(dev, ptr + PCICAP_NEXTPTR, 1);
1203 t3_os_pci_save_state(struct adapter *sc)
1206 struct pci_devinfo *dinfo;
1209 dinfo = device_get_ivars(dev);
1211 pci_cfg_save(dev, dinfo, 0);
1216 t3_os_pci_restore_state(struct adapter *sc)
1219 struct pci_devinfo *dinfo;
1222 dinfo = device_get_ivars(dev);
1224 pci_cfg_restore(dev, dinfo);
1229 * t3_os_link_changed - handle link status changes
1230 * @sc: the adapter associated with the link change
1231 * @port_id: the port index whose link status has changed
1232 * @link_status: the new status of the link
1233 * @speed: the new speed setting
1234 * @duplex: the new duplex setting
1235 * @fc: the new flow-control setting
1237 * This is the OS-dependent handler for link status changes. The OS
1238 * neutral handler takes care of most of the processing for these events,
1239 * then calls this handler for any OS-specific processing.
1242 t3_os_link_changed(adapter_t *adapter, int port_id, int link_status, int speed,
1243 int duplex, int fc, int mac_was_reset)
1245 struct port_info *pi = &adapter->port[port_id];
1246 struct ifnet *ifp = pi->ifp;
1248 /* no race with detach, so ifp should always be good */
1249 KASSERT(ifp, ("%s: if detached.", __func__));
1251 /* Reapply mac settings if they were lost due to a reset */
1252 if (mac_was_reset) {
1254 cxgb_update_mac_settings(pi);
1259 ifp->if_baudrate = IF_Mbps(speed);
1260 if_link_state_change(ifp, LINK_STATE_UP);
1262 if_link_state_change(ifp, LINK_STATE_DOWN);
1266 * t3_os_phymod_changed - handle PHY module changes
1267 * @phy: the PHY reporting the module change
1268 * @mod_type: new module type
1270 * This is the OS-dependent handler for PHY module changes. It is
1271 * invoked when a PHY module is removed or inserted for any OS-specific
1274 void t3_os_phymod_changed(struct adapter *adap, int port_id)
1276 static const char *mod_str[] = {
1277 NULL, "SR", "LR", "LRM", "TWINAX", "TWINAX", "unknown"
1279 struct port_info *pi = &adap->port[port_id];
1280 int mod = pi->phy.modtype;
1282 if (mod != pi->media.ifm_cur->ifm_data)
1283 cxgb_build_medialist(pi);
1285 if (mod == phy_modtype_none)
1286 if_printf(pi->ifp, "PHY module unplugged\n");
1288 KASSERT(mod < ARRAY_SIZE(mod_str),
1289 ("invalid PHY module type %d", mod));
1290 if_printf(pi->ifp, "%s PHY module inserted\n", mod_str[mod]);
1295 * Interrupt-context handler for external (PHY) interrupts.
1298 t3_os_ext_intr_handler(adapter_t *sc)
1301 printf("t3_os_ext_intr_handler\n");
1303 * Schedule a task to handle external interrupts as they may be slow
1304 * and we use a mutex to protect MDIO registers. We disable PHY
1305 * interrupts in the meantime and let the task reenable them when
1308 if (sc->slow_intr_mask) {
1310 sc->slow_intr_mask &= ~F_T3DBG;
1311 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask);
1312 taskqueue_enqueue(sc->tq, &sc->ext_intr_task);
1318 t3_os_set_hw_addr(adapter_t *adapter, int port_idx, u8 hw_addr[])
1322 * The ifnet might not be allocated before this gets called,
1323 * as this is called early on in attach by t3_prep_adapter
1324 * save the address off in the port structure
1327 printf("set_hw_addr on idx %d addr %6D\n", port_idx, hw_addr, ":");
1328 bcopy(hw_addr, adapter->port[port_idx].hw_addr, ETHER_ADDR_LEN);
1332 * Programs the XGMAC based on the settings in the ifnet. These settings
1333 * include MTU, MAC address, mcast addresses, etc.
1336 cxgb_update_mac_settings(struct port_info *p)
1338 struct ifnet *ifp = p->ifp;
1339 struct t3_rx_mode rm;
1340 struct cmac *mac = &p->mac;
1343 PORT_LOCK_ASSERT_OWNED(p);
1345 bcopy(IF_LLADDR(ifp), p->hw_addr, ETHER_ADDR_LEN);
1348 if (ifp->if_capenable & IFCAP_VLAN_MTU)
1349 mtu += ETHER_VLAN_ENCAP_LEN;
1351 hwtagging = (ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0;
1353 t3_mac_set_mtu(mac, mtu);
1354 t3_set_vlan_accel(p->adapter, 1 << p->tx_chan, hwtagging);
1355 t3_mac_set_address(mac, 0, p->hw_addr);
1356 t3_init_rx_mode(&rm, p);
1357 t3_mac_set_rx_mode(mac, &rm);
1362 await_mgmt_replies(struct adapter *adap, unsigned long init_cnt,
1367 while (adap->sge.qs[0].rspq.offload_pkts < init_cnt + n) {
1376 init_tp_parity(struct adapter *adap)
1380 struct cpl_set_tcb_field *greq;
1381 unsigned long cnt = adap->sge.qs[0].rspq.offload_pkts;
1383 t3_tp_set_offload_mode(adap, 1);
1385 for (i = 0; i < 16; i++) {
1386 struct cpl_smt_write_req *req;
1388 m = m_gethdr(M_WAITOK, MT_DATA);
1389 req = mtod(m, struct cpl_smt_write_req *);
1390 m->m_len = m->m_pkthdr.len = sizeof(*req);
1391 memset(req, 0, sizeof(*req));
1392 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
1393 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, i));
1395 t3_mgmt_tx(adap, m);
1398 for (i = 0; i < 2048; i++) {
1399 struct cpl_l2t_write_req *req;
1401 m = m_gethdr(M_WAITOK, MT_DATA);
1402 req = mtod(m, struct cpl_l2t_write_req *);
1403 m->m_len = m->m_pkthdr.len = sizeof(*req);
1404 memset(req, 0, sizeof(*req));
1405 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
1406 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_L2T_WRITE_REQ, i));
1407 req->params = htonl(V_L2T_W_IDX(i));
1408 t3_mgmt_tx(adap, m);
1411 for (i = 0; i < 2048; i++) {
1412 struct cpl_rte_write_req *req;
1414 m = m_gethdr(M_WAITOK, MT_DATA);
1415 req = mtod(m, struct cpl_rte_write_req *);
1416 m->m_len = m->m_pkthdr.len = sizeof(*req);
1417 memset(req, 0, sizeof(*req));
1418 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
1419 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_RTE_WRITE_REQ, i));
1420 req->l2t_idx = htonl(V_L2T_W_IDX(i));
1421 t3_mgmt_tx(adap, m);
1424 m = m_gethdr(M_WAITOK, MT_DATA);
1425 greq = mtod(m, struct cpl_set_tcb_field *);
1426 m->m_len = m->m_pkthdr.len = sizeof(*greq);
1427 memset(greq, 0, sizeof(*greq));
1428 greq->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
1429 OPCODE_TID(greq) = htonl(MK_OPCODE_TID(CPL_SET_TCB_FIELD, 0));
1430 greq->mask = htobe64(1);
1431 t3_mgmt_tx(adap, m);
1433 i = await_mgmt_replies(adap, cnt, 16 + 2048 + 2048 + 1);
1434 t3_tp_set_offload_mode(adap, 0);
1439 * setup_rss - configure Receive Side Steering (per-queue connection demux)
1440 * @adap: the adapter
1442 * Sets up RSS to distribute packets to multiple receive queues. We
1443 * configure the RSS CPU lookup table to distribute to the number of HW
1444 * receive queues, and the response queue lookup table to narrow that
1445 * down to the response queues actually configured for each port.
1446 * We always configure the RSS mapping for two ports since the mapping
1447 * table has plenty of entries.
1450 setup_rss(adapter_t *adap)
1454 uint8_t cpus[SGE_QSETS + 1];
1455 uint16_t rspq_map[RSS_TABLE_SIZE];
1457 for (i = 0; i < SGE_QSETS; ++i)
1459 cpus[SGE_QSETS] = 0xff;
1462 for_each_port(adap, i) {
1463 const struct port_info *pi = adap2pinfo(adap, i);
1465 nq[pi->tx_chan] += pi->nqsets;
1467 for (i = 0; i < RSS_TABLE_SIZE / 2; ++i) {
1468 rspq_map[i] = nq[0] ? i % nq[0] : 0;
1469 rspq_map[i + RSS_TABLE_SIZE / 2] = nq[1] ? i % nq[1] + nq[0] : 0;
1472 /* Calculate the reverse RSS map table */
1473 for (i = 0; i < SGE_QSETS; ++i)
1474 adap->rrss_map[i] = 0xff;
1475 for (i = 0; i < RSS_TABLE_SIZE; ++i)
1476 if (adap->rrss_map[rspq_map[i]] == 0xff)
1477 adap->rrss_map[rspq_map[i]] = i;
1479 t3_config_rss(adap, F_RQFEEDBACKENABLE | F_TNLLKPEN | F_TNLMAPEN |
1480 F_TNLPRTEN | F_TNL2TUPEN | F_TNL4TUPEN | F_OFDMAPEN |
1481 F_RRCPLMAPEN | V_RRCPLCPUSIZE(6) | F_HASHTOEPLITZ,
1487 * Sends an mbuf to an offload queue driver
1488 * after dealing with any active network taps.
1491 offload_tx(struct t3cdev *tdev, struct mbuf *m)
1495 ret = t3_offload_tx(tdev, m);
1500 write_smt_entry(struct adapter *adapter, int idx)
1502 struct port_info *pi = &adapter->port[idx];
1503 struct cpl_smt_write_req *req;
1506 if ((m = m_gethdr(M_NOWAIT, MT_DATA)) == NULL)
1509 req = mtod(m, struct cpl_smt_write_req *);
1510 m->m_pkthdr.len = m->m_len = sizeof(struct cpl_smt_write_req);
1512 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_FORWARD));
1513 OPCODE_TID(req) = htonl(MK_OPCODE_TID(CPL_SMT_WRITE_REQ, idx));
1514 req->mtu_idx = NMTUS - 1; /* should be 0 but there's a T3 bug */
1516 memset(req->src_mac1, 0, sizeof(req->src_mac1));
1517 memcpy(req->src_mac0, pi->hw_addr, ETHER_ADDR_LEN);
1519 m_set_priority(m, 1);
1521 offload_tx(&adapter->tdev, m);
1527 init_smt(struct adapter *adapter)
1531 for_each_port(adapter, i)
1532 write_smt_entry(adapter, i);
1537 init_port_mtus(adapter_t *adapter)
1539 unsigned int mtus = ETHERMTU | (ETHERMTU << 16);
1541 t3_write_reg(adapter, A_TP_MTU_PORT_TABLE, mtus);
1545 send_pktsched_cmd(struct adapter *adap, int sched, int qidx, int lo,
1549 struct mngt_pktsched_wr *req;
1551 m = m_gethdr(M_DONTWAIT, MT_DATA);
1553 req = mtod(m, struct mngt_pktsched_wr *);
1554 req->wr.wrh_hi = htonl(V_WR_OP(FW_WROPCODE_MNGT));
1555 req->mngt_opcode = FW_MNGTOPCODE_PKTSCHED_SET;
1560 req->binding = port;
1561 m->m_len = m->m_pkthdr.len = sizeof(*req);
1562 t3_mgmt_tx(adap, m);
1567 bind_qsets(adapter_t *sc)
1571 for (i = 0; i < (sc)->params.nports; ++i) {
1572 const struct port_info *pi = adap2pinfo(sc, i);
1574 for (j = 0; j < pi->nqsets; ++j) {
1575 send_pktsched_cmd(sc, 1, pi->first_qset + j, -1,
1583 update_tpeeprom(struct adapter *adap)
1585 #ifdef FIRMWARE_LATEST
1586 const struct firmware *tpeeprom;
1588 struct firmware *tpeeprom;
1592 unsigned int major, minor;
1596 t3_seeprom_read(adap, TP_SRAM_OFFSET, &version);
1598 major = G_TP_VERSION_MAJOR(version);
1599 minor = G_TP_VERSION_MINOR(version);
1600 if (major == TP_VERSION_MAJOR && minor == TP_VERSION_MINOR)
1603 rev = t3rev2char(adap);
1604 snprintf(name, sizeof(name), TPEEPROM_NAME, rev);
1606 tpeeprom = firmware_get(name);
1607 if (tpeeprom == NULL) {
1608 device_printf(adap->dev,
1609 "could not load TP EEPROM: unable to load %s\n",
1614 len = tpeeprom->datasize - 4;
1616 ret = t3_check_tpsram(adap, tpeeprom->data, tpeeprom->datasize);
1618 goto release_tpeeprom;
1620 if (len != TP_SRAM_LEN) {
1621 device_printf(adap->dev,
1622 "%s length is wrong len=%d expected=%d\n", name,
1627 ret = set_eeprom(&adap->port[0], tpeeprom->data, tpeeprom->datasize,
1631 device_printf(adap->dev,
1632 "Protocol SRAM image updated in EEPROM to %d.%d.%d\n",
1633 TP_VERSION_MAJOR, TP_VERSION_MINOR, TP_VERSION_MICRO);
1635 device_printf(adap->dev,
1636 "Protocol SRAM image update in EEPROM failed\n");
1639 firmware_put(tpeeprom, FIRMWARE_UNLOAD);
1645 update_tpsram(struct adapter *adap)
1647 #ifdef FIRMWARE_LATEST
1648 const struct firmware *tpsram;
1650 struct firmware *tpsram;
1655 rev = t3rev2char(adap);
1656 snprintf(name, sizeof(name), TPSRAM_NAME, rev);
1658 update_tpeeprom(adap);
1660 tpsram = firmware_get(name);
1661 if (tpsram == NULL){
1662 device_printf(adap->dev, "could not load TP SRAM\n");
1665 device_printf(adap->dev, "updating TP SRAM\n");
1667 ret = t3_check_tpsram(adap, tpsram->data, tpsram->datasize);
1669 goto release_tpsram;
1671 ret = t3_set_proto_sram(adap, tpsram->data);
1673 device_printf(adap->dev, "loading protocol SRAM failed\n");
1676 firmware_put(tpsram, FIRMWARE_UNLOAD);
1682 * cxgb_up - enable the adapter
1683 * @adap: adapter being enabled
1685 * Called when the first port is enabled, this function performs the
1686 * actions necessary to make an adapter operational, such as completing
1687 * the initialization of HW modules, and enabling interrupts.
1690 cxgb_up(struct adapter *sc)
1694 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1695 KASSERT(sc->open_device_map == 0, ("%s: device(s) already open (%x)",
1696 __func__, sc->open_device_map));
1698 if ((sc->flags & FULL_INIT_DONE) == 0) {
1700 if ((sc->flags & FW_UPTODATE) == 0)
1701 if ((err = upgrade_fw(sc)))
1704 if ((sc->flags & TPS_UPTODATE) == 0)
1705 if ((err = update_tpsram(sc)))
1708 err = t3_init_hw(sc, 0);
1712 t3_set_reg_field(sc, A_TP_PARA_REG5, 0, F_RXDDPOFFINIT);
1713 t3_write_reg(sc, A_ULPRX_TDDP_PSZ, V_HPZ0(PAGE_SHIFT - 12));
1715 err = setup_sge_qsets(sc);
1722 err = cxgb_setup_interrupts(sc);
1726 t3_add_configured_sysctls(sc);
1727 sc->flags |= FULL_INIT_DONE;
1734 if (sc->params.rev >= T3_REV_C && !(sc->flags & TP_PARITY_INIT) &&
1735 is_offload(sc) && init_tp_parity(sc) == 0)
1736 sc->flags |= TP_PARITY_INIT;
1738 if (sc->flags & TP_PARITY_INIT) {
1739 t3_write_reg(sc, A_TP_INT_CAUSE, F_CMCACHEPERR | F_ARPLUTPERR);
1740 t3_write_reg(sc, A_TP_INT_ENABLE, 0x7fbfffff);
1743 if (!(sc->flags & QUEUES_BOUND)) {
1745 sc->flags |= QUEUES_BOUND;
1748 t3_sge_reset_adapter(sc);
1754 * Called when the last open device is closed. Does NOT undo all of cxgb_up's
1755 * work. Specifically, the resources grabbed under FULL_INIT_DONE are released
1756 * during controller_detach, not here.
1759 cxgb_down(struct adapter *sc)
1761 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1764 t3_intr_disable(sc);
1768 offload_open(struct port_info *pi)
1770 struct adapter *sc = pi->adapter;
1771 struct t3cdev *tdev = &sc->tdev;
1773 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
1775 setbit(&sc->open_device_map, OFFLOAD_DEVMAP_BIT);
1777 t3_tp_set_offload_mode(sc, 1);
1778 tdev->lldev = pi->ifp;
1780 t3_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd,
1781 sc->params.rev == 0 ? sc->port[0].ifp->if_mtu : 0xffff);
1783 cxgb_add_clients(tdev);
1789 offload_close(struct t3cdev *tdev)
1791 struct adapter *adapter = tdev2adap(tdev);
1793 if (!isset(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT))
1796 /* Call back all registered clients */
1797 cxgb_remove_clients(tdev);
1800 cxgb_set_dummy_ops(tdev);
1801 t3_tp_set_offload_mode(adapter, 0);
1803 clrbit(&adapter->open_device_map, OFFLOAD_DEVMAP_BIT);
1809 * Begin a synchronized operation. If this call succeeds, it is guaranteed that
1810 * no one will remove the port or its ifp from underneath the caller. Caller is
1811 * also granted exclusive access to open_device_map.
1813 * operation here means init, uninit, detach, and ioctl service.
1816 * EINTR (ctrl-c pressed during ifconfig for example).
1817 * ENXIO (port is about to detach - due to kldunload for example).
1820 cxgb_begin_op(struct port_info *p, const char *wmsg)
1823 struct adapter *sc = p->adapter;
1827 while (!IS_DOOMED(p) && IS_BUSY(sc)) {
1828 if (mtx_sleep(&sc->flags, &sc->lock, PCATCH, wmsg, 0)) {
1836 else if (!IS_BUSY(sc))
1839 KASSERT(0, ("%s: port %d, p->flags = %x , sc->flags = %x",
1840 __func__, p->port_id, p->flags, sc->flags));
1850 * End a synchronized operation. Read comment block above cxgb_begin_op.
1853 cxgb_end_op(struct port_info *p)
1855 struct adapter *sc = p->adapter;
1858 KASSERT(IS_BUSY(sc), ("%s: not busy.", __func__));
1860 wakeup_one(&sc->flags);
1867 * Prepare for port detachment. Detach is a special kind of synchronized
1868 * operation. Also read comment before cxgb_begin_op.
1871 cxgb_begin_detach(struct port_info *p)
1873 struct adapter *sc = p->adapter;
1876 * Inform those waiting for this port that it is going to be destroyed
1877 * and they should not continue further. (They'll return with ENXIO).
1885 * Wait for in-progress operations.
1888 while (IS_BUSY(sc)) {
1889 mtx_sleep(&sc->flags, &sc->lock, 0, "cxgbdtch", 0);
1898 * if_init for cxgb ports.
1901 cxgb_init(void *arg)
1903 struct port_info *p = arg;
1905 if (cxgb_begin_op(p, "cxgbinit"))
1908 cxgb_init_synchronized(p);
1913 cxgb_init_synchronized(struct port_info *p)
1915 struct adapter *sc = p->adapter;
1916 struct ifnet *ifp = p->ifp;
1917 struct cmac *mac = &p->mac;
1920 if (sc->open_device_map == 0) {
1921 if ((rc = cxgb_up(sc)) != 0)
1924 if (is_offload(sc) && !ofld_disable && offload_open(p))
1926 "Could not initialize offload capabilities\n");
1930 t3_port_intr_enable(sc, p->port_id);
1931 if (!mac->multiport)
1933 cxgb_update_mac_settings(p);
1934 t3_link_start(&p->phy, mac, &p->link_config);
1935 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
1936 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1937 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1940 t3_link_changed(sc, p->port_id);
1942 for (i = p->first_qset; i < p->first_qset + p->nqsets; i++) {
1943 struct sge_qset *qs = &sc->sge.qs[i];
1944 struct sge_txq *txq = &qs->txq[TXQ_ETH];
1946 callout_reset_on(&txq->txq_watchdog, hz, cxgb_tx_watchdog, qs,
1947 txq->txq_watchdog.c_cpu);
1951 setbit(&sc->open_device_map, p->port_id);
1957 * Called on "ifconfig down", and from port_detach
1960 cxgb_uninit_synchronized(struct port_info *pi)
1962 struct adapter *sc = pi->adapter;
1963 struct ifnet *ifp = pi->ifp;
1966 * Clear this port's bit from the open device map, and then drain all
1967 * the tasks that can access/manipulate this port's port_info or ifp.
1968 * We disable this port's interrupts here and so the the slow/ext
1969 * interrupt tasks won't be enqueued. The tick task will continue to
1970 * be enqueued every second but the runs after this drain will not see
1971 * this port in the open device map.
1973 * A well behaved task must take open_device_map into account and ignore
1974 * ports that are not open.
1976 clrbit(&sc->open_device_map, pi->port_id);
1977 t3_port_intr_disable(sc, pi->port_id);
1978 taskqueue_drain(sc->tq, &sc->slow_intr_task);
1979 taskqueue_drain(sc->tq, &sc->ext_intr_task);
1980 taskqueue_drain(sc->tq, &sc->tick_task);
1983 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1985 /* disable pause frames */
1986 t3_set_reg_field(sc, A_XGM_TX_CFG + pi->mac.offset, F_TXPAUSEEN, 0);
1988 /* Reset RX FIFO HWM */
1989 t3_set_reg_field(sc, A_XGM_RXFIFO_CFG + pi->mac.offset,
1990 V_RXFIFOPAUSEHWM(M_RXFIFOPAUSEHWM), 0);
1994 /* Wait for TXFIFO empty */
1995 t3_wait_op_done(sc, A_XGM_TXFIFO_CFG + pi->mac.offset,
1996 F_TXFIFO_EMPTY, 1, 20, 5);
1999 t3_mac_disable(&pi->mac, MAC_DIRECTION_RX);
2002 pi->phy.ops->power_down(&pi->phy, 1);
2006 pi->link_config.link_ok = 0;
2007 t3_os_link_changed(sc, pi->port_id, 0, 0, 0, 0, 0);
2009 if ((sc->open_device_map & PORT_MASK) == 0)
2010 offload_close(&sc->tdev);
2012 if (sc->open_device_map == 0)
2013 cxgb_down(pi->adapter);
2018 #ifdef LRO_SUPPORTED
2020 * Mark lro enabled or disabled in all qsets for this port
2023 cxgb_set_lro(struct port_info *p, int enabled)
2026 struct adapter *adp = p->adapter;
2029 PORT_LOCK_ASSERT_OWNED(p);
2030 for (i = 0; i < p->nqsets; i++) {
2031 q = &adp->sge.qs[p->first_qset + i];
2032 q->lro.enabled = (enabled != 0);
2039 cxgb_ioctl(struct ifnet *ifp, unsigned long command, caddr_t data)
2041 struct port_info *p = ifp->if_softc;
2042 struct ifreq *ifr = (struct ifreq *)data;
2043 int flags, error = 0, mtu, handle_unsynchronized = 0;
2046 if ((error = cxgb_begin_op(p, "cxgbioct")) != 0)
2050 * Only commands that should be handled within begin-op/end-op are
2051 * serviced in this switch statement. See handle_unsynchronized.
2056 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO)) {
2061 cxgb_update_mac_settings(p);
2067 if (ifp->if_flags & IFF_UP) {
2068 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2069 flags = p->if_flags;
2070 if (((ifp->if_flags ^ flags) & IFF_PROMISC) ||
2071 ((ifp->if_flags ^ flags) & IFF_ALLMULTI)) {
2073 cxgb_update_mac_settings(p);
2077 error = cxgb_init_synchronized(p);
2078 p->if_flags = ifp->if_flags;
2079 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING)
2080 error = cxgb_uninit_synchronized(p);
2085 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2087 cxgb_update_mac_settings(p);
2093 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2094 if (mask & IFCAP_TXCSUM) {
2095 if (IFCAP_TXCSUM & ifp->if_capenable) {
2096 ifp->if_capenable &= ~(IFCAP_TXCSUM|IFCAP_TSO4);
2097 ifp->if_hwassist &= ~(CSUM_TCP | CSUM_UDP
2098 | CSUM_IP | CSUM_TSO);
2100 ifp->if_capenable |= IFCAP_TXCSUM;
2101 ifp->if_hwassist |= (CSUM_TCP | CSUM_UDP
2105 if (mask & IFCAP_RXCSUM) {
2106 ifp->if_capenable ^= IFCAP_RXCSUM;
2108 if (mask & IFCAP_TSO4) {
2109 if (IFCAP_TSO4 & ifp->if_capenable) {
2110 ifp->if_capenable &= ~IFCAP_TSO4;
2111 ifp->if_hwassist &= ~CSUM_TSO;
2112 } else if (IFCAP_TXCSUM & ifp->if_capenable) {
2113 ifp->if_capenable |= IFCAP_TSO4;
2114 ifp->if_hwassist |= CSUM_TSO;
2118 #ifdef LRO_SUPPORTED
2119 if (mask & IFCAP_LRO) {
2120 ifp->if_capenable ^= IFCAP_LRO;
2122 /* Safe to do this even if cxgb_up not called yet */
2123 cxgb_set_lro(p, ifp->if_capenable & IFCAP_LRO);
2126 if (mask & IFCAP_VLAN_HWTAGGING) {
2127 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2128 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2130 cxgb_update_mac_settings(p);
2134 if (mask & IFCAP_VLAN_MTU) {
2135 ifp->if_capenable ^= IFCAP_VLAN_MTU;
2136 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
2138 cxgb_update_mac_settings(p);
2142 if (mask & IFCAP_VLAN_HWCSUM) {
2143 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2146 #ifdef VLAN_CAPABILITIES
2147 VLAN_CAPABILITIES(ifp);
2151 handle_unsynchronized = 1;
2156 * We don't want to call anything outside the driver while inside a
2157 * begin-op/end-op block. If it calls us back (eg. ether_ioctl may
2158 * call cxgb_init) we may deadlock if the state is already marked busy.
2160 * XXX: this probably opens a small race window with kldunload...
2164 /* The IS_DOOMED check is racy, we're clutching at straws here */
2165 if (handle_unsynchronized && !IS_DOOMED(p)) {
2166 if (command == SIOCSIFMEDIA || command == SIOCGIFMEDIA)
2167 error = ifmedia_ioctl(ifp, ifr, &p->media, command);
2169 error = ether_ioctl(ifp, command, data);
2176 cxgb_media_change(struct ifnet *ifp)
2178 return (EOPNOTSUPP);
2182 * Translates phy->modtype to the correct Ethernet media subtype.
2185 cxgb_ifm_type(int mod)
2188 case phy_modtype_sr:
2189 return (IFM_10G_SR);
2190 case phy_modtype_lr:
2191 return (IFM_10G_LR);
2192 case phy_modtype_lrm:
2193 return (IFM_10G_LRM);
2194 case phy_modtype_twinax:
2195 return (IFM_10G_TWINAX);
2196 case phy_modtype_twinax_long:
2197 return (IFM_10G_TWINAX_LONG);
2198 case phy_modtype_none:
2200 case phy_modtype_unknown:
2201 return (IFM_UNKNOWN);
2204 KASSERT(0, ("%s: modtype %d unknown", __func__, mod));
2205 return (IFM_UNKNOWN);
2209 * Rebuilds the ifmedia list for this port, and sets the current media.
2212 cxgb_build_medialist(struct port_info *p)
2214 struct cphy *phy = &p->phy;
2215 struct ifmedia *media = &p->media;
2216 int mod = phy->modtype;
2217 int m = IFM_ETHER | IFM_FDX;
2221 ifmedia_removeall(media);
2222 if (phy->caps & SUPPORTED_TP && phy->caps & SUPPORTED_Autoneg) {
2225 if (phy->caps & SUPPORTED_10000baseT_Full)
2226 ifmedia_add(media, m | IFM_10G_T, mod, NULL);
2228 if (phy->caps & SUPPORTED_1000baseT_Full)
2229 ifmedia_add(media, m | IFM_1000_T, mod, NULL);
2231 if (phy->caps & SUPPORTED_100baseT_Full)
2232 ifmedia_add(media, m | IFM_100_TX, mod, NULL);
2234 if (phy->caps & SUPPORTED_10baseT_Full)
2235 ifmedia_add(media, m | IFM_10_T, mod, NULL);
2237 ifmedia_add(media, IFM_ETHER | IFM_AUTO, mod, NULL);
2238 ifmedia_set(media, IFM_ETHER | IFM_AUTO);
2240 } else if (phy->caps & SUPPORTED_TP) {
2243 KASSERT(phy->caps & SUPPORTED_10000baseT_Full,
2244 ("%s: unexpected cap 0x%x", __func__, phy->caps));
2246 ifmedia_add(media, m | IFM_10G_CX4, mod, NULL);
2247 ifmedia_set(media, m | IFM_10G_CX4);
2249 } else if (phy->caps & SUPPORTED_FIBRE &&
2250 phy->caps & SUPPORTED_10000baseT_Full) {
2251 /* 10G optical (but includes SFP+ twinax) */
2253 m |= cxgb_ifm_type(mod);
2254 if (IFM_SUBTYPE(m) == IFM_NONE)
2257 ifmedia_add(media, m, mod, NULL);
2258 ifmedia_set(media, m);
2260 } else if (phy->caps & SUPPORTED_FIBRE &&
2261 phy->caps & SUPPORTED_1000baseT_Full) {
2264 /* XXX: Lie and claim to be SX, could actually be any 1G-X */
2265 ifmedia_add(media, m | IFM_1000_SX, mod, NULL);
2266 ifmedia_set(media, m | IFM_1000_SX);
2269 KASSERT(0, ("%s: don't know how to handle 0x%x.", __func__,
2277 cxgb_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2279 struct port_info *p = ifp->if_softc;
2280 struct ifmedia_entry *cur = p->media.ifm_cur;
2281 int speed = p->link_config.speed;
2283 if (cur->ifm_data != p->phy.modtype) {
2284 cxgb_build_medialist(p);
2285 cur = p->media.ifm_cur;
2288 ifmr->ifm_status = IFM_AVALID;
2289 if (!p->link_config.link_ok)
2292 ifmr->ifm_status |= IFM_ACTIVE;
2295 * active and current will differ iff current media is autoselect. That
2296 * can happen only for copper RJ45.
2298 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO)
2300 KASSERT(p->phy.caps & SUPPORTED_TP && p->phy.caps & SUPPORTED_Autoneg,
2301 ("%s: unexpected PHY caps 0x%x", __func__, p->phy.caps));
2303 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
2304 if (speed == SPEED_10000)
2305 ifmr->ifm_active |= IFM_10G_T;
2306 else if (speed == SPEED_1000)
2307 ifmr->ifm_active |= IFM_1000_T;
2308 else if (speed == SPEED_100)
2309 ifmr->ifm_active |= IFM_100_TX;
2310 else if (speed == SPEED_10)
2311 ifmr->ifm_active |= IFM_10_T;
2313 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__,
2318 cxgb_async_intr(void *data)
2320 adapter_t *sc = data;
2323 device_printf(sc->dev, "cxgb_async_intr\n");
2325 * May need to sleep - defer to taskqueue
2327 taskqueue_enqueue(sc->tq, &sc->slow_intr_task);
2331 cxgb_ext_intr_handler(void *arg, int count)
2333 adapter_t *sc = (adapter_t *)arg;
2336 printf("cxgb_ext_intr_handler\n");
2338 t3_phy_intr_handler(sc);
2340 /* Now reenable external interrupts */
2342 if (sc->slow_intr_mask) {
2343 sc->slow_intr_mask |= F_T3DBG;
2344 t3_write_reg(sc, A_PL_INT_CAUSE0, F_T3DBG);
2345 t3_write_reg(sc, A_PL_INT_ENABLE0, sc->slow_intr_mask);
2351 link_poll_needed(struct port_info *p)
2353 struct cphy *phy = &p->phy;
2355 if (phy->caps & POLL_LINK_1ST_TIME) {
2356 p->phy.caps &= ~POLL_LINK_1ST_TIME;
2360 return (p->link_fault || !(phy->caps & SUPPORTED_LINK_IRQ));
2364 check_link_status(adapter_t *sc)
2368 for (i = 0; i < (sc)->params.nports; ++i) {
2369 struct port_info *p = &sc->port[i];
2371 if (!isset(&sc->open_device_map, p->port_id))
2374 if (link_poll_needed(p))
2375 t3_link_changed(sc, i);
2380 check_t3b2_mac(struct adapter *sc)
2384 if (sc->flags & CXGB_SHUTDOWN)
2387 for_each_port(sc, i) {
2388 struct port_info *p = &sc->port[i];
2391 struct ifnet *ifp = p->ifp;
2394 if (!isset(&sc->open_device_map, p->port_id) || p->link_fault ||
2395 !p->link_config.link_ok)
2398 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING,
2399 ("%s: state mismatch (drv_flags %x, device_map %x)",
2400 __func__, ifp->if_drv_flags, sc->open_device_map));
2403 status = t3b2_mac_watchdog_task(&p->mac);
2405 p->mac.stats.num_toggled++;
2406 else if (status == 2) {
2407 struct cmac *mac = &p->mac;
2409 cxgb_update_mac_settings(p);
2410 t3_link_start(&p->phy, mac, &p->link_config);
2411 t3_mac_enable(mac, MAC_DIRECTION_RX | MAC_DIRECTION_TX);
2412 t3_port_intr_enable(sc, p->port_id);
2413 p->mac.stats.num_resets++;
2420 cxgb_tick(void *arg)
2422 adapter_t *sc = (adapter_t *)arg;
2424 if (sc->flags & CXGB_SHUTDOWN)
2427 taskqueue_enqueue(sc->tq, &sc->tick_task);
2428 callout_reset(&sc->cxgb_tick_ch, CXGB_TICKS(sc), cxgb_tick, sc);
2432 cxgb_tick_handler(void *arg, int count)
2434 adapter_t *sc = (adapter_t *)arg;
2435 const struct adapter_params *p = &sc->params;
2437 uint32_t cause, reset;
2439 if (sc->flags & CXGB_SHUTDOWN || !(sc->flags & FULL_INIT_DONE))
2442 check_link_status(sc);
2444 if (p->rev == T3_REV_B2 && p->nports < 4 && sc->open_device_map)
2447 cause = t3_read_reg(sc, A_SG_INT_CAUSE);
2449 if (cause & F_FLEMPTY) {
2450 struct sge_qset *qs = &sc->sge.qs[0];
2455 cause = (t3_read_reg(sc, A_SG_RSPQ_FL_STATUS) >>
2456 S_FL0EMPTY) & 0xffff;
2458 qs->fl[i].empty += (cause & 1);
2465 t3_write_reg(sc, A_SG_INT_CAUSE, reset);
2467 for (i = 0; i < sc->params.nports; i++) {
2468 struct port_info *pi = &sc->port[i];
2469 struct ifnet *ifp = pi->ifp;
2470 struct cmac *mac = &pi->mac;
2471 struct mac_stats *mstats = &mac->stats;
2473 if (!isset(&sc->open_device_map, pi->port_id))
2477 t3_mac_update_stats(mac);
2481 mstats->tx_frames_64 +
2482 mstats->tx_frames_65_127 +
2483 mstats->tx_frames_128_255 +
2484 mstats->tx_frames_256_511 +
2485 mstats->tx_frames_512_1023 +
2486 mstats->tx_frames_1024_1518 +
2487 mstats->tx_frames_1519_max;
2490 mstats->rx_frames_64 +
2491 mstats->rx_frames_65_127 +
2492 mstats->rx_frames_128_255 +
2493 mstats->rx_frames_256_511 +
2494 mstats->rx_frames_512_1023 +
2495 mstats->rx_frames_1024_1518 +
2496 mstats->rx_frames_1519_max;
2498 ifp->if_obytes = mstats->tx_octets;
2499 ifp->if_ibytes = mstats->rx_octets;
2500 ifp->if_omcasts = mstats->tx_mcast_frames;
2501 ifp->if_imcasts = mstats->rx_mcast_frames;
2503 ifp->if_collisions =
2504 mstats->tx_total_collisions;
2506 ifp->if_iqdrops = mstats->rx_cong_drops;
2509 mstats->tx_excess_collisions +
2510 mstats->tx_underrun +
2511 mstats->tx_len_errs +
2512 mstats->tx_mac_internal_errs +
2513 mstats->tx_excess_deferral +
2514 mstats->tx_fcs_errs;
2517 mstats->rx_data_errs +
2518 mstats->rx_sequence_errs +
2520 mstats->rx_too_long +
2521 mstats->rx_mac_internal_errs +
2523 mstats->rx_fcs_errs;
2528 /* Count rx fifo overflows, once per second */
2529 cause = t3_read_reg(sc, A_XGM_INT_CAUSE + mac->offset);
2531 if (cause & F_RXFIFO_OVERFLOW) {
2532 mac->stats.rx_fifo_ovfl++;
2533 reset |= F_RXFIFO_OVERFLOW;
2535 t3_write_reg(sc, A_XGM_INT_CAUSE + mac->offset, reset);
2540 touch_bars(device_t dev)
2545 #if !defined(__LP64__) && 0
2548 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_1, &v);
2549 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_1, v);
2550 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_3, &v);
2551 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_3, v);
2552 pci_read_config_dword(pdev, PCI_BASE_ADDRESS_5, &v);
2553 pci_write_config_dword(pdev, PCI_BASE_ADDRESS_5, v);
2558 set_eeprom(struct port_info *pi, const uint8_t *data, int len, int offset)
2562 u32 aligned_offset, aligned_len, *p;
2563 struct adapter *adapter = pi->adapter;
2566 aligned_offset = offset & ~3;
2567 aligned_len = (len + (offset & 3) + 3) & ~3;
2569 if (aligned_offset != offset || aligned_len != len) {
2570 buf = malloc(aligned_len, M_DEVBUF, M_WAITOK|M_ZERO);
2573 err = t3_seeprom_read(adapter, aligned_offset, (u32 *)buf);
2574 if (!err && aligned_len > 4)
2575 err = t3_seeprom_read(adapter,
2576 aligned_offset + aligned_len - 4,
2577 (u32 *)&buf[aligned_len - 4]);
2580 memcpy(buf + (offset & 3), data, len);
2582 buf = (uint8_t *)(uintptr_t)data;
2584 err = t3_seeprom_wp(adapter, 0);
2588 for (p = (u32 *)buf; !err && aligned_len; aligned_len -= 4, p++) {
2589 err = t3_seeprom_write(adapter, aligned_offset, *p);
2590 aligned_offset += 4;
2594 err = t3_seeprom_wp(adapter, 1);
2597 free(buf, M_DEVBUF);
2603 in_range(int val, int lo, int hi)
2605 return val < 0 || (val <= hi && val >= lo);
2609 cxgb_extension_open(struct cdev *dev, int flags, int fmp, struct thread *td)
2615 cxgb_extension_close(struct cdev *dev, int flags, int fmt, struct thread *td)
2621 cxgb_extension_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data,
2622 int fflag, struct thread *td)
2625 struct port_info *pi = dev->si_drv1;
2626 adapter_t *sc = pi->adapter;
2628 #ifdef PRIV_SUPPORTED
2629 if (priv_check(td, PRIV_DRIVER)) {
2631 printf("user does not have access to privileged ioctls\n");
2637 printf("user does not have access to privileged ioctls\n");
2643 case CHELSIO_GET_MIIREG: {
2645 struct cphy *phy = &pi->phy;
2646 struct ch_mii_data *mid = (struct ch_mii_data *)data;
2648 if (!phy->mdio_read)
2649 return (EOPNOTSUPP);
2651 mmd = mid->phy_id >> 8;
2654 else if (mmd > MDIO_DEV_VEND2)
2657 error = phy->mdio_read(sc, mid->phy_id & 0x1f, mmd,
2658 mid->reg_num, &val);
2660 error = phy->mdio_read(sc, mid->phy_id & 0x1f, 0,
2661 mid->reg_num & 0x1f, &val);
2666 case CHELSIO_SET_MIIREG: {
2667 struct cphy *phy = &pi->phy;
2668 struct ch_mii_data *mid = (struct ch_mii_data *)data;
2670 if (!phy->mdio_write)
2671 return (EOPNOTSUPP);
2673 mmd = mid->phy_id >> 8;
2676 else if (mmd > MDIO_DEV_VEND2)
2679 error = phy->mdio_write(sc, mid->phy_id & 0x1f,
2680 mmd, mid->reg_num, mid->val_in);
2682 error = phy->mdio_write(sc, mid->phy_id & 0x1f, 0,
2683 mid->reg_num & 0x1f,
2687 case CHELSIO_SETREG: {
2688 struct ch_reg *edata = (struct ch_reg *)data;
2689 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
2691 t3_write_reg(sc, edata->addr, edata->val);
2694 case CHELSIO_GETREG: {
2695 struct ch_reg *edata = (struct ch_reg *)data;
2696 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
2698 edata->val = t3_read_reg(sc, edata->addr);
2701 case CHELSIO_GET_SGE_CONTEXT: {
2702 struct ch_cntxt *ecntxt = (struct ch_cntxt *)data;
2703 mtx_lock_spin(&sc->sge.reg_lock);
2704 switch (ecntxt->cntxt_type) {
2705 case CNTXT_TYPE_EGRESS:
2706 error = -t3_sge_read_ecntxt(sc, ecntxt->cntxt_id,
2710 error = -t3_sge_read_fl(sc, ecntxt->cntxt_id,
2713 case CNTXT_TYPE_RSP:
2714 error = -t3_sge_read_rspq(sc, ecntxt->cntxt_id,
2718 error = -t3_sge_read_cq(sc, ecntxt->cntxt_id,
2725 mtx_unlock_spin(&sc->sge.reg_lock);
2728 case CHELSIO_GET_SGE_DESC: {
2729 struct ch_desc *edesc = (struct ch_desc *)data;
2731 if (edesc->queue_num >= SGE_QSETS * 6)
2733 ret = t3_get_desc(&sc->sge.qs[edesc->queue_num / 6],
2734 edesc->queue_num % 6, edesc->idx, edesc->data);
2740 case CHELSIO_GET_QSET_PARAMS: {
2741 struct qset_params *q;
2742 struct ch_qset_params *t = (struct ch_qset_params *)data;
2743 int q1 = pi->first_qset;
2744 int nqsets = pi->nqsets;
2747 if (t->qset_idx >= nqsets)
2750 i = q1 + t->qset_idx;
2751 q = &sc->params.sge.qset[i];
2752 t->rspq_size = q->rspq_size;
2753 t->txq_size[0] = q->txq_size[0];
2754 t->txq_size[1] = q->txq_size[1];
2755 t->txq_size[2] = q->txq_size[2];
2756 t->fl_size[0] = q->fl_size;
2757 t->fl_size[1] = q->jumbo_size;
2758 t->polling = q->polling;
2760 t->intr_lat = q->coalesce_usecs;
2761 t->cong_thres = q->cong_thres;
2764 if (sc->flags & USING_MSIX)
2765 t->vector = rman_get_start(sc->msix_irq_res[i]);
2767 t->vector = rman_get_start(sc->irq_res);
2771 case CHELSIO_GET_QSET_NUM: {
2772 struct ch_reg *edata = (struct ch_reg *)data;
2773 edata->val = pi->nqsets;
2776 case CHELSIO_LOAD_FW: {
2779 struct ch_mem_range *t = (struct ch_mem_range *)data;
2782 * You're allowed to load a firmware only before FULL_INIT_DONE
2784 * FW_UPTODATE is also set so the rest of the initialization
2785 * will not overwrite what was loaded here. This gives you the
2786 * flexibility to load any firmware (and maybe shoot yourself in
2791 if (sc->open_device_map || sc->flags & FULL_INIT_DONE) {
2796 fw_data = malloc(t->len, M_DEVBUF, M_NOWAIT);
2800 error = copyin(t->buf, fw_data, t->len);
2803 error = -t3_load_fw(sc, fw_data, t->len);
2805 if (t3_get_fw_version(sc, &vers) == 0) {
2806 snprintf(&sc->fw_version[0], sizeof(sc->fw_version),
2807 "%d.%d.%d", G_FW_VERSION_MAJOR(vers),
2808 G_FW_VERSION_MINOR(vers), G_FW_VERSION_MICRO(vers));
2812 sc->flags |= FW_UPTODATE;
2814 free(fw_data, M_DEVBUF);
2818 case CHELSIO_LOAD_BOOT: {
2820 struct ch_mem_range *t = (struct ch_mem_range *)data;
2822 boot_data = malloc(t->len, M_DEVBUF, M_NOWAIT);
2826 error = copyin(t->buf, boot_data, t->len);
2828 error = -t3_load_boot(sc, boot_data, t->len);
2830 free(boot_data, M_DEVBUF);
2833 case CHELSIO_GET_PM: {
2834 struct ch_pm *m = (struct ch_pm *)data;
2835 struct tp_params *p = &sc->params.tp;
2837 if (!is_offload(sc))
2838 return (EOPNOTSUPP);
2840 m->tx_pg_sz = p->tx_pg_size;
2841 m->tx_num_pg = p->tx_num_pgs;
2842 m->rx_pg_sz = p->rx_pg_size;
2843 m->rx_num_pg = p->rx_num_pgs;
2844 m->pm_total = p->pmtx_size + p->chan_rx_size * p->nchan;
2848 case CHELSIO_SET_PM: {
2849 struct ch_pm *m = (struct ch_pm *)data;
2850 struct tp_params *p = &sc->params.tp;
2852 if (!is_offload(sc))
2853 return (EOPNOTSUPP);
2854 if (sc->flags & FULL_INIT_DONE)
2857 if (!m->rx_pg_sz || (m->rx_pg_sz & (m->rx_pg_sz - 1)) ||
2858 !m->tx_pg_sz || (m->tx_pg_sz & (m->tx_pg_sz - 1)))
2859 return (EINVAL); /* not power of 2 */
2860 if (!(m->rx_pg_sz & 0x14000))
2861 return (EINVAL); /* not 16KB or 64KB */
2862 if (!(m->tx_pg_sz & 0x1554000))
2864 if (m->tx_num_pg == -1)
2865 m->tx_num_pg = p->tx_num_pgs;
2866 if (m->rx_num_pg == -1)
2867 m->rx_num_pg = p->rx_num_pgs;
2868 if (m->tx_num_pg % 24 || m->rx_num_pg % 24)
2870 if (m->rx_num_pg * m->rx_pg_sz > p->chan_rx_size ||
2871 m->tx_num_pg * m->tx_pg_sz > p->chan_tx_size)
2874 p->rx_pg_size = m->rx_pg_sz;
2875 p->tx_pg_size = m->tx_pg_sz;
2876 p->rx_num_pgs = m->rx_num_pg;
2877 p->tx_num_pgs = m->tx_num_pg;
2880 case CHELSIO_SETMTUTAB: {
2881 struct ch_mtus *m = (struct ch_mtus *)data;
2884 if (!is_offload(sc))
2885 return (EOPNOTSUPP);
2886 if (offload_running(sc))
2888 if (m->nmtus != NMTUS)
2890 if (m->mtus[0] < 81) /* accommodate SACK */
2894 * MTUs must be in ascending order
2896 for (i = 1; i < NMTUS; ++i)
2897 if (m->mtus[i] < m->mtus[i - 1])
2900 memcpy(sc->params.mtus, m->mtus, sizeof(sc->params.mtus));
2903 case CHELSIO_GETMTUTAB: {
2904 struct ch_mtus *m = (struct ch_mtus *)data;
2906 if (!is_offload(sc))
2907 return (EOPNOTSUPP);
2909 memcpy(m->mtus, sc->params.mtus, sizeof(m->mtus));
2913 case CHELSIO_GET_MEM: {
2914 struct ch_mem_range *t = (struct ch_mem_range *)data;
2920 * Use these to avoid modifying len/addr in the the return
2923 uint32_t len = t->len, addr = t->addr;
2925 if (!is_offload(sc))
2926 return (EOPNOTSUPP);
2927 if (!(sc->flags & FULL_INIT_DONE))
2928 return (EIO); /* need the memory controllers */
2929 if ((addr & 0x7) || (len & 0x7))
2931 if (t->mem_id == MEM_CM)
2933 else if (t->mem_id == MEM_PMRX)
2935 else if (t->mem_id == MEM_PMTX)
2942 * bits 0..9: chip version
2943 * bits 10..15: chip revision
2945 t->version = 3 | (sc->params.rev << 10);
2948 * Read 256 bytes at a time as len can be large and we don't
2949 * want to use huge intermediate buffers.
2951 useraddr = (uint8_t *)t->buf;
2953 unsigned int chunk = min(len, sizeof(buf));
2955 error = t3_mc7_bd_read(mem, addr / 8, chunk / 8, buf);
2958 if (copyout(buf, useraddr, chunk))
2966 case CHELSIO_READ_TCAM_WORD: {
2967 struct ch_tcam_word *t = (struct ch_tcam_word *)data;
2969 if (!is_offload(sc))
2970 return (EOPNOTSUPP);
2971 if (!(sc->flags & FULL_INIT_DONE))
2972 return (EIO); /* need MC5 */
2973 return -t3_read_mc5_range(&sc->mc5, t->addr, 1, t->buf);
2976 case CHELSIO_SET_TRACE_FILTER: {
2977 struct ch_trace *t = (struct ch_trace *)data;
2978 const struct trace_params *tp;
2980 tp = (const struct trace_params *)&t->sip;
2982 t3_config_trace_filter(sc, tp, 0, t->invert_match,
2985 t3_config_trace_filter(sc, tp, 1, t->invert_match,
2989 case CHELSIO_SET_PKTSCHED: {
2990 struct ch_pktsched_params *p = (struct ch_pktsched_params *)data;
2991 if (sc->open_device_map == 0)
2993 send_pktsched_cmd(sc, p->sched, p->idx, p->min, p->max,
2997 case CHELSIO_IFCONF_GETREGS: {
2998 struct ch_ifconf_regs *regs = (struct ch_ifconf_regs *)data;
2999 int reglen = cxgb_get_regs_len();
3000 uint8_t *buf = malloc(reglen, M_DEVBUF, M_NOWAIT);
3004 if (regs->len > reglen)
3006 else if (regs->len < reglen)
3010 cxgb_get_regs(sc, regs, buf);
3011 error = copyout(buf, regs->data, reglen);
3013 free(buf, M_DEVBUF);
3017 case CHELSIO_SET_HW_SCHED: {
3018 struct ch_hw_sched *t = (struct ch_hw_sched *)data;
3019 unsigned int ticks_per_usec = core_ticks_per_usec(sc);
3021 if ((sc->flags & FULL_INIT_DONE) == 0)
3022 return (EAGAIN); /* need TP to be initialized */
3023 if (t->sched >= NTX_SCHED || !in_range(t->mode, 0, 1) ||
3024 !in_range(t->channel, 0, 1) ||
3025 !in_range(t->kbps, 0, 10000000) ||
3026 !in_range(t->class_ipg, 0, 10000 * 65535 / ticks_per_usec) ||
3027 !in_range(t->flow_ipg, 0,
3028 dack_ticks_to_usec(sc, 0x7ff)))
3032 error = t3_config_sched(sc, t->kbps, t->sched);
3036 if (t->class_ipg >= 0)
3037 t3_set_sched_ipg(sc, t->sched, t->class_ipg);
3038 if (t->flow_ipg >= 0) {
3039 t->flow_ipg *= 1000; /* us -> ns */
3040 t3_set_pace_tbl(sc, &t->flow_ipg, t->sched, 1);
3043 int bit = 1 << (S_TX_MOD_TIMER_MODE + t->sched);
3045 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP,
3046 bit, t->mode ? bit : 0);
3048 if (t->channel >= 0)
3049 t3_set_reg_field(sc, A_TP_TX_MOD_QUEUE_REQ_MAP,
3050 1 << t->sched, t->channel << t->sched);
3053 case CHELSIO_GET_EEPROM: {
3055 struct ch_eeprom *e = (struct ch_eeprom *)data;
3056 uint8_t *buf = malloc(EEPROMSIZE, M_DEVBUF, M_NOWAIT);
3061 e->magic = EEPROM_MAGIC;
3062 for (i = e->offset & ~3; !error && i < e->offset + e->len; i += 4)
3063 error = -t3_seeprom_read(sc, i, (uint32_t *)&buf[i]);
3066 error = copyout(buf + e->offset, e->data, e->len);
3068 free(buf, M_DEVBUF);
3071 case CHELSIO_CLEAR_STATS: {
3072 if (!(sc->flags & FULL_INIT_DONE))
3076 t3_mac_update_stats(&pi->mac);
3077 memset(&pi->mac.stats, 0, sizeof(pi->mac.stats));
3081 case CHELSIO_GET_UP_LA: {
3082 struct ch_up_la *la = (struct ch_up_la *)data;
3083 uint8_t *buf = malloc(LA_BUFSIZE, M_DEVBUF, M_NOWAIT);
3087 if (la->bufsize < LA_BUFSIZE)
3091 error = -t3_get_up_la(sc, &la->stopped, &la->idx,
3094 error = copyout(buf, la->data, la->bufsize);
3096 free(buf, M_DEVBUF);
3099 case CHELSIO_GET_UP_IOQS: {
3100 struct ch_up_ioqs *ioqs = (struct ch_up_ioqs *)data;
3101 uint8_t *buf = malloc(IOQS_BUFSIZE, M_DEVBUF, M_NOWAIT);
3107 if (ioqs->bufsize < IOQS_BUFSIZE)
3111 error = -t3_get_up_ioqs(sc, &ioqs->bufsize, buf);
3114 v = (uint32_t *)buf;
3116 ioqs->bufsize -= 4 * sizeof(uint32_t);
3117 ioqs->ioq_rx_enable = *v++;
3118 ioqs->ioq_tx_enable = *v++;
3119 ioqs->ioq_rx_status = *v++;
3120 ioqs->ioq_tx_status = *v++;
3122 error = copyout(v, ioqs->data, ioqs->bufsize);
3125 free(buf, M_DEVBUF);
3129 return (EOPNOTSUPP);
3136 static __inline void
3137 reg_block_dump(struct adapter *ap, uint8_t *buf, unsigned int start,
3140 uint32_t *p = (uint32_t *)(buf + start);
3142 for ( ; start <= end; start += sizeof(uint32_t))
3143 *p++ = t3_read_reg(ap, start);
3146 #define T3_REGMAP_SIZE (3 * 1024)
3148 cxgb_get_regs_len(void)
3150 return T3_REGMAP_SIZE;
3154 cxgb_get_regs(adapter_t *sc, struct ch_ifconf_regs *regs, uint8_t *buf)
3159 * bits 0..9: chip version
3160 * bits 10..15: chip revision
3161 * bit 31: set for PCIe cards
3163 regs->version = 3 | (sc->params.rev << 10) | (is_pcie(sc) << 31);
3166 * We skip the MAC statistics registers because they are clear-on-read.
3167 * Also reading multi-register stats would need to synchronize with the
3168 * periodic mac stats accumulation. Hard to justify the complexity.
3170 memset(buf, 0, cxgb_get_regs_len());
3171 reg_block_dump(sc, buf, 0, A_SG_RSPQ_CREDIT_RETURN);
3172 reg_block_dump(sc, buf, A_SG_HI_DRB_HI_THRSH, A_ULPRX_PBL_ULIMIT);
3173 reg_block_dump(sc, buf, A_ULPTX_CONFIG, A_MPS_INT_CAUSE);
3174 reg_block_dump(sc, buf, A_CPL_SWITCH_CNTRL, A_CPL_MAP_TBL_DATA);
3175 reg_block_dump(sc, buf, A_SMB_GLOBAL_TIME_CFG, A_XGM_SERDES_STAT3);
3176 reg_block_dump(sc, buf, A_XGM_SERDES_STATUS0,
3177 XGM_REG(A_XGM_SERDES_STAT3, 1));
3178 reg_block_dump(sc, buf, XGM_REG(A_XGM_SERDES_STATUS0, 1),
3179 XGM_REG(A_XGM_RX_SPI4_SOP_EOP_CNT, 1));
3183 MODULE_DEPEND(if_cxgb, cxgb_t3fw, 1, 1, 1);