2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
34 #include <sys/kernel.h>
37 #include <sys/types.h>
38 #include <sys/malloc.h>
39 #include <dev/pci/pcivar.h>
40 #include <dev/pci/pcireg.h>
41 #include <machine/bus.h>
42 #include <sys/socket.h>
43 #include <sys/sysctl.h>
44 #include <net/ethernet.h>
46 #include <net/if_media.h>
47 #include <netinet/in.h>
48 #include <netinet/tcp_lro.h>
51 #include "common/t4_msg.h"
52 #include "firmware/t4fw_interface.h"
54 #define KTR_CXGBE KTR_SPARE3
55 MALLOC_DECLARE(M_CXGBE);
56 #define CXGBE_UNIMPLEMENTED(s) \
57 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
59 #if defined(__i386__) || defined(__amd64__)
63 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
69 #ifndef SYSCTL_ADD_UQUAD
70 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
71 #define sysctl_handle_64 sysctl_handle_quad
72 #define CTLTYPE_U64 CTLTYPE_QUAD
75 #if (__FreeBSD_version >= 900030) || \
76 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
81 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
82 static __inline uint64_t
83 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
86 KASSERT(tag == X86_BUS_SPACE_MEM,
87 ("%s: can only handle mem space", __func__));
89 return (*(volatile uint64_t *)(handle + offset));
93 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
94 bus_size_t offset, uint64_t value)
96 KASSERT(tag == X86_BUS_SPACE_MEM,
97 ("%s: can only handle mem space", __func__));
99 *(volatile uint64_t *)(bsh + offset) = value;
102 static __inline uint64_t
103 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
106 return (uint64_t)bus_space_read_4(tag, handle, offset) +
107 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
111 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
112 bus_size_t offset, uint64_t value)
114 bus_space_write_4(tag, bsh, offset, value);
115 bus_space_write_4(tag, bsh, offset + 4, value >> 32);
120 typedef struct adapter adapter_t;
124 * All ingress queues use this entry size. Note that the firmware event
125 * queue and any iq expecting CPL_RX_PKT in the descriptor needs this to
130 /* Default queue sizes for all kinds of ingress queues */
134 /* All egress queues use this entry size */
137 /* Default queue sizes for all kinds of egress queues */
141 #if MJUMPAGESIZE != MCLBYTES
142 SW_ZONE_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
144 SW_ZONE_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
146 CL_METADATA_SIZE = CACHE_LINE_SIZE,
148 SGE_MAX_WR_NDESC = SGE_MAX_WR_LEN / EQ_ESIZE, /* max WR size in desc */
150 TX_SGL_SEGS_TSO = 38,
151 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
155 /* adapter intr_type */
156 INTR_INTX = (1 << 0),
162 XGMAC_MTU = (1 << 0),
163 XGMAC_PROMISC = (1 << 1),
164 XGMAC_ALLMULTI = (1 << 2),
165 XGMAC_VLANEX = (1 << 3),
166 XGMAC_UCADDR = (1 << 4),
167 XGMAC_MCADDRS = (1 << 5),
173 /* flags understood by begin_synchronized_op */
174 HOLD_LOCK = (1 << 0),
178 /* flags understood by end_synchronized_op */
179 LOCK_HELD = HOLD_LOCK,
184 FULL_INIT_DONE = (1 << 0),
186 /* INTR_DIRECT = (1 << 2), No longer used. */
187 MASTER_PF = (1 << 3),
188 ADAP_SYSCTL_CTX = (1 << 4),
189 /* TOM_INIT_DONE= (1 << 5), No longer used */
190 BUF_PACKING_OK = (1 << 6),
192 CXGBE_BUSY = (1 << 9),
196 PORT_INIT_DONE = (1 << 1),
197 PORT_SYSCTL_CTX = (1 << 2),
198 HAS_TRACEQ = (1 << 3),
199 INTR_RXQ = (1 << 4), /* All NIC rxq's take interrupts */
200 INTR_OFLD_RXQ = (1 << 5), /* All TOE rxq's take interrupts */
201 INTR_NM_RXQ = (1 << 6), /* All netmap rxq's take interrupts */
202 INTR_ALL = (INTR_RXQ | INTR_OFLD_RXQ | INTR_NM_RXQ),
204 /* adapter debug_flags */
205 DF_DUMP_MBOX = (1 << 0),
208 #define IS_DOOMED(pi) ((pi)->flags & DOOMED)
209 #define SET_DOOMED(pi) do {(pi)->flags |= DOOMED;} while (0)
210 #define IS_BUSY(sc) ((sc)->flags & CXGBE_BUSY)
211 #define SET_BUSY(sc) do {(sc)->flags |= CXGBE_BUSY;} while (0)
212 #define CLR_BUSY(sc) do {(sc)->flags &= ~CXGBE_BUSY;} while (0)
216 struct adapter *adapter;
219 struct ifmedia media;
228 int16_t xact_addr_filt;/* index of exact MAC address filter */
229 uint16_t rss_size; /* size of VI's RSS table slice */
230 uint8_t lport; /* associated offload logical port */
236 uint8_t rx_chan_map; /* rx MPS channel bitmap */
238 /* These need to be int as they are used in sysctl */
239 int ntxq; /* # of tx queues */
240 int first_txq; /* index of first tx queue */
241 int rsrv_noflowq; /* Reserve queue 0 for non-flowid packets */
242 int nrxq; /* # of rx queues */
243 int first_rxq; /* index of first rx queue */
245 int nofldtxq; /* # of offload tx queues */
246 int first_ofld_txq; /* index of first offload tx queue */
247 int nofldrxq; /* # of offload rx queues */
248 int first_ofld_rxq; /* index of first offload rx queue */
251 int nnmtxq; /* # of netmap tx queues */
252 int first_nm_txq; /* index of first netmap tx queue */
253 int nnmrxq; /* # of netmap rx queues */
254 int first_nm_rxq; /* index of first netmap rx queue */
256 struct ifnet *nm_ifp;
257 struct ifmedia nm_media;
260 int16_t nm_xact_addr_filt;
261 uint16_t nm_rss_size; /* size of netmap VI's RSS table slice */
269 struct link_config link_cfg;
271 struct timeval last_refreshed;
272 struct port_stats stats;
273 u_int tx_parse_error;
275 eventhandler_tag vlan_c;
278 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
280 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
283 /* Where the cluster came from, how it has been carved up. */
284 struct cluster_layout {
287 uint16_t region1; /* mbufs laid out within this region */
288 /* region2 is the DMA region */
289 uint16_t region3; /* cluster_metadata within this region */
292 struct cluster_metadata {
295 struct fl_sdesc *sd; /* For debug only. Could easily be stale */
301 uint16_t nmbuf; /* # of driver originated mbufs with ref on cluster */
302 struct cluster_layout cll;
310 struct mbuf *m; /* m_nextpkt linked chain of frames */
311 uint8_t desc_used; /* # of hardware descriptors used by the WR */
315 #define IQ_PAD (IQ_ESIZE - sizeof(struct rsp_ctrl) - sizeof(struct rss_header))
317 struct rss_header rss;
322 CTASSERT(sizeof(struct iq_desc) == IQ_ESIZE);
326 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
327 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
328 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
329 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
338 * Ingress Queue: T4 is producer, driver is consumer.
343 struct adapter *adapter;
344 struct iq_desc *desc; /* KVA of descriptor ring */
345 int8_t intr_pktc_idx; /* packet count threshold index */
346 uint8_t gen; /* generation bit */
347 uint8_t intr_params; /* interrupt holdoff parameters */
348 uint8_t intr_next; /* XXX: holdoff for next interrupt */
349 uint16_t qsize; /* size (# of entries) of the queue */
350 uint16_t sidx; /* index of the entry with the status page */
351 uint16_t cidx; /* consumer index */
352 uint16_t cntxt_id; /* SGE context id for the iq */
353 uint16_t abs_id; /* absolute SGE id for the iq */
355 STAILQ_ENTRY(sge_iq) link;
357 bus_dma_tag_t desc_tag;
358 bus_dmamap_t desc_map;
359 bus_addr_t ba; /* bus address of descriptor ring */
368 EQ_TYPEMASK = 0x3, /* 2 lsbits hold the type (see above) */
369 EQ_ALLOCATED = (1 << 2), /* firmware resources allocated */
370 EQ_ENABLED = (1 << 3), /* open for business */
373 /* Listed in order of preference. Update t4_sysctls too if you change these */
374 enum {DOORBELL_UDB, DOORBELL_WCWR, DOORBELL_UDBWC, DOORBELL_KDB};
377 * Egress Queue: driver is producer, T4 is consumer.
379 * Note: A free list is an egress queue (driver produces the buffers and T4
380 * consumes them) but it's special enough to have its own struct (see sge_fl).
383 unsigned int flags; /* MUST be first */
384 unsigned int cntxt_id; /* SGE context id for the eq */
387 struct tx_desc *desc; /* KVA of descriptor ring */
389 volatile uint32_t *udb; /* KVA of doorbell (lies within BAR2) */
390 u_int udb_qid; /* relative qid within the doorbell page */
391 uint16_t sidx; /* index of the entry with the status page */
392 uint16_t cidx; /* consumer idx (desc idx) */
393 uint16_t pidx; /* producer idx (desc idx) */
394 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
395 uint16_t dbidx; /* pidx of the most recent doorbell */
396 uint16_t iqid; /* iq that gets egr_update for the eq */
397 uint8_t tx_chan; /* tx channel used by the eq */
398 volatile u_int equiq; /* EQUIQ outstanding */
400 bus_dma_tag_t desc_tag;
401 bus_dmamap_t desc_map;
402 bus_addr_t ba; /* bus address of descriptor ring */
406 struct sw_zone_info {
407 uma_zone_t zone; /* zone that this cluster comes from */
408 int size; /* size of cluster: 2K, 4K, 9K, 16K, etc. */
409 int type; /* EXT_xxx type of the cluster */
415 int8_t zidx; /* backpointer to zone; -ve means unused */
416 int8_t next; /* next hwidx for this zone; -1 means no more */
421 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
422 FL_DOOMED = (1 << 1), /* about to be destroyed */
423 FL_BUF_PACKING = (1 << 2), /* buffer packing enabled */
424 FL_BUF_RESUME = (1 << 3), /* resume from the middle of the frame */
427 #define FL_RUNNING_LOW(fl) \
428 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) <= fl->lowat)
429 #define FL_NOT_RUNNING_LOW(fl) \
430 (IDXDIFF(fl->dbidx * 8, fl->cidx, fl->sidx * 8) >= 2 * fl->lowat)
434 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
435 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
436 struct cluster_layout cll_def; /* default refill zone, layout */
437 uint16_t lowat; /* # of buffers <= this means fl needs help */
439 uint16_t buf_boundary;
441 /* The 16b idx all deal with hw descriptors */
442 uint16_t dbidx; /* hw pidx after last doorbell */
443 uint16_t sidx; /* index of status page */
444 volatile uint16_t hw_cidx;
446 /* The 32b idx are all buffer idx, not hardware descriptor idx */
447 uint32_t cidx; /* consumer index */
448 uint32_t pidx; /* producer index */
451 u_int rx_offset; /* offset in fl buf (when buffer packing) */
452 volatile uint32_t *udb;
454 uint64_t mbuf_allocated;/* # of mbuf allocated from zone_mbuf */
455 uint64_t mbuf_inlined; /* # of mbuf created within clusters */
456 uint64_t cl_allocated; /* # of clusters allocated */
457 uint64_t cl_recycled; /* # of clusters recycled */
458 uint64_t cl_fast_recycled; /* # of clusters recycled (fast) */
460 /* These 3 are valid when FL_BUF_RESUME is set, stale otherwise. */
465 uint16_t qsize; /* # of hw descriptors (status page included) */
466 uint16_t cntxt_id; /* SGE context id for the freelist */
467 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
468 bus_dma_tag_t desc_tag;
469 bus_dmamap_t desc_map;
471 bus_addr_t ba; /* bus address of descriptor ring */
472 struct cluster_layout cll_alt; /* alternate refill zone, layout */
477 /* txq: SGE egress queue + what's needed for Ethernet NIC */
479 struct sge_eq eq; /* MUST be first */
481 struct ifnet *ifp; /* the interface this txq belongs to */
482 struct mp_ring *r; /* tx software ring */
483 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
485 __be32 cpl_ctrl0; /* for convenience */
487 struct task tx_reclaim_task;
488 /* stats for common events first */
490 uint64_t txcsum; /* # of times hardware assisted with checksum */
491 uint64_t tso_wrs; /* # of TSO work requests */
492 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
493 uint64_t imm_wrs; /* # of work requests with immediate data */
494 uint64_t sgl_wrs; /* # of work requests with direct SGL */
495 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
496 uint64_t txpkts0_wrs; /* # of type0 coalesced tx work requests */
497 uint64_t txpkts1_wrs; /* # of type1 coalesced tx work requests */
498 uint64_t txpkts0_pkts; /* # of frames in type0 coalesced tx WRs */
499 uint64_t txpkts1_pkts; /* # of frames in type1 coalesced tx WRs */
501 /* stats for not-that-common events */
502 } __aligned(CACHE_LINE_SIZE);
504 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
506 struct sge_iq iq; /* MUST be first */
507 struct sge_fl fl; /* MUST follow iq */
509 struct ifnet *ifp; /* the interface this rxq belongs to */
510 #if defined(INET) || defined(INET6)
511 struct lro_ctrl lro; /* LRO state */
514 /* stats for common events first */
516 uint64_t rxcsum; /* # of times hardware assisted with checksum */
517 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
519 /* stats for not-that-common events */
521 } __aligned(CACHE_LINE_SIZE);
523 static inline struct sge_rxq *
524 iq_to_rxq(struct sge_iq *iq)
527 return (__containerof(iq, struct sge_rxq, iq));
532 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
533 struct sge_ofld_rxq {
534 struct sge_iq iq; /* MUST be first */
535 struct sge_fl fl; /* MUST follow iq */
536 } __aligned(CACHE_LINE_SIZE);
538 static inline struct sge_ofld_rxq *
539 iq_to_ofld_rxq(struct sge_iq *iq)
542 return (__containerof(iq, struct sge_ofld_rxq, iq));
547 STAILQ_ENTRY(wrqe) link;
550 char wr[] __aligned(16);
554 TAILQ_ENTRY(wrq_cookie) link;
560 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
561 * and offload tx queues are of this type.
564 struct sge_eq eq; /* MUST be first */
566 struct adapter *adapter;
567 struct task wrq_tx_task;
569 /* Tx desc reserved but WR not "committed" yet. */
570 TAILQ_HEAD(wrq_incomplete_wrs , wrq_cookie) incomplete_wrs;
572 /* List of WRs ready to go out as soon as descriptors are available. */
573 STAILQ_HEAD(, wrqe) wr_list;
577 /* stats for common events first */
579 uint64_t tx_wrs_direct; /* # of WRs written directly to desc ring. */
580 uint64_t tx_wrs_ss; /* # of WRs copied from scratch space. */
581 uint64_t tx_wrs_copied; /* # of WRs queued and copied to desc ring. */
583 /* stats for not-that-common events */
586 * Scratch space for work requests that wrap around after reaching the
587 * status page, and some infomation about the last WR that used it.
591 uint8_t ss[SGE_MAX_WR_LEN];
593 } __aligned(CACHE_LINE_SIZE);
598 struct port_info *pi;
600 struct iq_desc *iq_desc;
602 uint16_t iq_cntxt_id;
608 uint16_t fl_cntxt_id;
615 u_int nid; /* netmap ring # for this queue */
617 /* infrequently used items after this */
619 bus_dma_tag_t iq_desc_tag;
620 bus_dmamap_t iq_desc_map;
624 bus_dma_tag_t fl_desc_tag;
625 bus_dmamap_t fl_desc_map;
627 } __aligned(CACHE_LINE_SIZE);
630 struct tx_desc *desc;
634 uint16_t equiqidx; /* EQUIQ last requested at this pidx */
635 uint16_t equeqidx; /* EQUEQ last requested at this pidx */
636 uint16_t dbidx; /* pidx of the most recent doorbell */
638 volatile uint32_t *udb;
641 __be32 cpl_ctrl0; /* for convenience */
642 u_int nid; /* netmap ring # for this queue */
644 /* infrequently used items after this */
646 bus_dma_tag_t desc_tag;
647 bus_dmamap_t desc_map;
650 } __aligned(CACHE_LINE_SIZE);
654 int timer_val[SGE_NTIMERS];
655 int counter_val[SGE_NCOUNTERS];
656 int fl_starve_threshold;
657 int fl_starve_threshold2;
661 int nrxq; /* total # of Ethernet rx queues */
662 int ntxq; /* total # of Ethernet tx tx queues */
664 int nofldrxq; /* total # of TOE rx queues */
665 int nofldtxq; /* total # of TOE tx queues */
668 int nnmrxq; /* total # of netmap rx queues */
669 int nnmtxq; /* total # of netmap tx queues */
671 int niq; /* total # of ingress queues */
672 int neq; /* total # of egress queues */
674 struct sge_iq fwq; /* Firmware event queue */
675 struct sge_wrq mgmtq; /* Management queue (control queue) */
676 struct sge_wrq *ctrlq; /* Control queues */
677 struct sge_txq *txq; /* NIC tx queues */
678 struct sge_rxq *rxq; /* NIC rx queues */
680 struct sge_wrq *ofld_txq; /* TOE tx queues */
681 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
684 struct sge_nm_txq *nm_txq; /* netmap tx queues */
685 struct sge_nm_rxq *nm_rxq; /* netmap rx queues */
690 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
691 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
695 int8_t safe_hwidx1; /* may not have room for metadata */
696 int8_t safe_hwidx2; /* with room for metadata and maybe more */
697 struct sw_zone_info sw_zone_info[SW_ZONE_SIZES];
698 struct hw_buf_info hw_buf_info[SGE_FLBUF_SIZES];
702 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
704 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
705 typedef int (*fw_msg_handler_t)(struct adapter *, const __be64 *);
708 SLIST_ENTRY(adapter) link;
712 /* PCIe register resources */
714 struct resource *regs_res;
716 struct resource *msix_res;
717 bus_space_handle_t bh;
721 struct resource *udbs_res;
722 volatile uint8_t *udbs_base;
727 /* Interrupt information */
731 struct resource *res;
736 bus_dma_tag_t dmat; /* Parent DMA tag */
741 struct taskqueue *tq[NCHAN]; /* General purpose taskqueues */
742 struct port_info *port[MAX_NPORTS];
743 uint8_t chan_map[NCHAN];
746 void *tom_softc; /* (struct tom_data *) */
747 struct tom_tunables tt;
748 void *iwarp_softc; /* (struct c4iw_dev *) */
751 struct l2t_data *l2t; /* L2 table */
752 struct tid_info tids;
757 int offload_map; /* ports with IFCAP_TOE enabled */
758 int active_ulds; /* ULDs activated on this adapter */
763 char ifp_lockname[16];
765 struct ifnet *ifp; /* tracer ifp */
766 struct ifmedia media;
767 int traceq; /* iq used by all tracers, -1 if none */
768 int tracer_valid; /* bitmap of valid tracers */
769 int tracer_enabled; /* bitmap of enabled tracers */
774 struct adapter_params params;
775 struct t4_virt_res vres;
784 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
789 /* Starving free lists */
790 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
791 TAILQ_HEAD(, sge_fl) sfl;
792 struct callout sfl_callout;
794 struct mtx regwin_lock; /* for indirect reads and memory windows */
796 an_handler_t an_handler __aligned(CACHE_LINE_SIZE);
797 fw_msg_handler_t fw_msg_handler[5]; /* NUM_FW6_TYPES */
798 cpl_handler_t cpl_handler[0xef]; /* NUM_CPL_CMDS */
802 const void *last_op_thr;
808 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
809 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
810 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
811 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
813 #define ASSERT_SYNCHRONIZED_OP(sc) \
814 KASSERT(IS_BUSY(sc) && \
815 (mtx_owned(&(sc)->sc_lock) || sc->last_op_thr == curthread), \
816 ("%s: operation not synchronized.", __func__))
818 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
819 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
820 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
821 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
823 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
824 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
825 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
826 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
827 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
829 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
830 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
831 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
832 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
834 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
835 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
836 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
837 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
838 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
840 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
841 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
842 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
843 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
844 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
846 #define CH_DUMP_MBOX(sc, mbox, data_reg) \
848 if (sc->debug_flags & DF_DUMP_MBOX) { \
850 "%s mbox %u: %016llx %016llx %016llx %016llx " \
851 "%016llx %016llx %016llx %016llx\n", \
852 device_get_nameunit(sc->dev), mbox, \
853 (unsigned long long)t4_read_reg64(sc, data_reg), \
854 (unsigned long long)t4_read_reg64(sc, data_reg + 8), \
855 (unsigned long long)t4_read_reg64(sc, data_reg + 16), \
856 (unsigned long long)t4_read_reg64(sc, data_reg + 24), \
857 (unsigned long long)t4_read_reg64(sc, data_reg + 32), \
858 (unsigned long long)t4_read_reg64(sc, data_reg + 40), \
859 (unsigned long long)t4_read_reg64(sc, data_reg + 48), \
860 (unsigned long long)t4_read_reg64(sc, data_reg + 56)); \
864 #define for_each_txq(pi, iter, q) \
865 for (q = &pi->adapter->sge.txq[pi->first_txq], iter = 0; \
866 iter < pi->ntxq; ++iter, ++q)
867 #define for_each_rxq(pi, iter, q) \
868 for (q = &pi->adapter->sge.rxq[pi->first_rxq], iter = 0; \
869 iter < pi->nrxq; ++iter, ++q)
870 #define for_each_ofld_txq(pi, iter, q) \
871 for (q = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq], iter = 0; \
872 iter < pi->nofldtxq; ++iter, ++q)
873 #define for_each_ofld_rxq(pi, iter, q) \
874 for (q = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq], iter = 0; \
875 iter < pi->nofldrxq; ++iter, ++q)
876 #define for_each_nm_txq(pi, iter, q) \
877 for (q = &pi->adapter->sge.nm_txq[pi->first_nm_txq], iter = 0; \
878 iter < pi->nnmtxq; ++iter, ++q)
879 #define for_each_nm_rxq(pi, iter, q) \
880 for (q = &pi->adapter->sge.nm_rxq[pi->first_nm_rxq], iter = 0; \
881 iter < pi->nnmrxq; ++iter, ++q)
883 #define IDXINCR(idx, incr, wrap) do { \
884 idx = wrap - idx > incr ? idx + incr : incr - (wrap - idx); \
886 #define IDXDIFF(head, tail, wrap) \
887 ((head) >= (tail) ? (head) - (tail) : (wrap) - (tail) + (head))
889 /* One for errors, one for firmware events */
890 #define T4_EXTRA_INTR 2
892 static inline uint32_t
893 t4_read_reg(struct adapter *sc, uint32_t reg)
896 return bus_space_read_4(sc->bt, sc->bh, reg);
900 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
903 bus_space_write_4(sc->bt, sc->bh, reg, val);
906 static inline uint64_t
907 t4_read_reg64(struct adapter *sc, uint32_t reg)
910 return t4_bus_space_read_8(sc->bt, sc->bh, reg);
914 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
917 t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
921 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
924 *val = pci_read_config(sc->dev, reg, 1);
928 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
931 pci_write_config(sc->dev, reg, val, 1);
935 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
938 *val = pci_read_config(sc->dev, reg, 2);
942 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
945 pci_write_config(sc->dev, reg, val, 2);
949 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
952 *val = pci_read_config(sc->dev, reg, 4);
956 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
959 pci_write_config(sc->dev, reg, val, 4);
962 static inline struct port_info *
963 adap2pinfo(struct adapter *sc, int idx)
966 return (sc->port[idx]);
970 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
973 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN);
977 is_10G_port(const struct port_info *pi)
980 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
984 is_40G_port(const struct port_info *pi)
987 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_40G) != 0);
991 tx_resume_threshold(struct sge_eq *eq)
994 /* not quite the same as qsize / 4, but this will do. */
995 return (eq->sidx / 4);
999 int t4_os_find_pci_capability(struct adapter *, int);
1000 int t4_os_pci_save_state(struct adapter *);
1001 int t4_os_pci_restore_state(struct adapter *);
1002 void t4_os_portmod_changed(const struct adapter *, int);
1003 void t4_os_link_changed(struct adapter *, int, int, int);
1004 void t4_iterate(void (*)(struct adapter *, void *), void *);
1005 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
1006 int t4_register_an_handler(struct adapter *, an_handler_t);
1007 int t4_register_fw_msg_handler(struct adapter *, int, fw_msg_handler_t);
1008 int t4_filter_rpl(struct sge_iq *, const struct rss_header *, struct mbuf *);
1009 int begin_synchronized_op(struct adapter *, struct port_info *, int, char *);
1010 void end_synchronized_op(struct adapter *, int);
1011 int update_mac_settings(struct ifnet *, int);
1012 int adapter_full_init(struct adapter *);
1013 int adapter_full_uninit(struct adapter *);
1014 int port_full_init(struct port_info *);
1015 int port_full_uninit(struct port_info *);
1019 int create_netmap_ifnet(struct port_info *);
1020 int destroy_netmap_ifnet(struct port_info *);
1021 void t4_nm_intr(void *);
1025 void t4_sge_modload(void);
1026 void t4_sge_modunload(void);
1027 uint64_t t4_sge_extfree_refs(void);
1028 void t4_init_sge_cpl_handlers(struct adapter *);
1029 void t4_tweak_chip_settings(struct adapter *);
1030 int t4_read_chip_settings(struct adapter *);
1031 int t4_create_dma_tag(struct adapter *);
1032 void t4_sge_sysctls(struct adapter *, struct sysctl_ctx_list *,
1033 struct sysctl_oid_list *);
1034 int t4_destroy_dma_tag(struct adapter *);
1035 int t4_setup_adapter_queues(struct adapter *);
1036 int t4_teardown_adapter_queues(struct adapter *);
1037 int t4_setup_port_queues(struct port_info *);
1038 int t4_teardown_port_queues(struct port_info *);
1039 void t4_intr_all(void *);
1040 void t4_intr(void *);
1041 void t4_intr_err(void *);
1042 void t4_intr_evt(void *);
1043 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
1044 void t4_update_fl_bufsize(struct ifnet *);
1045 int parse_pkt(struct mbuf **);
1046 void *start_wrq_wr(struct sge_wrq *, int, struct wrq_cookie *);
1047 void commit_wrq_wr(struct sge_wrq *, void *, struct wrq_cookie *);
1048 int tnl_cong(struct port_info *);
1052 void t4_tracer_modload(void);
1053 void t4_tracer_modunload(void);
1054 void t4_tracer_port_detach(struct adapter *);
1055 int t4_get_tracer(struct adapter *, struct t4_tracer *);
1056 int t4_set_tracer(struct adapter *, struct t4_tracer *);
1057 int t4_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1058 int t5_trace_pkt(struct sge_iq *, const struct rss_header *, struct mbuf *);
1060 static inline struct wrqe *
1061 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
1063 int len = offsetof(struct wrqe, wr) + wr_len;
1066 wr = malloc(len, M_CXGBE, M_NOWAIT);
1067 if (__predict_false(wr == NULL))
1069 wr->wr_len = wr_len;
1074 static inline void *
1075 wrtod(struct wrqe *wr)
1077 return (&wr->wr[0]);
1081 free_wrqe(struct wrqe *wr)
1087 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
1089 struct sge_wrq *wrq = wr->wrq;
1092 t4_wrq_tx_locked(sc, wrq, wr);