2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
34 #include <sys/kernel.h>
37 #include <sys/types.h>
38 #include <sys/malloc.h>
39 #include <dev/pci/pcivar.h>
40 #include <dev/pci/pcireg.h>
41 #include <machine/bus.h>
42 #include <sys/socket.h>
43 #include <sys/sysctl.h>
44 #include <net/ethernet.h>
46 #include <net/if_media.h>
47 #include <netinet/in.h>
48 #include <netinet/tcp_lro.h>
51 #include "firmware/t4fw_interface.h"
53 #define T4_CFGNAME "t4fw_cfg"
54 #define T4_FWNAME "t4fw"
56 MALLOC_DECLARE(M_CXGBE);
57 #define CXGBE_UNIMPLEMENTED(s) \
58 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
60 #if defined(__i386__) || defined(__amd64__)
64 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
70 #ifndef SYSCTL_ADD_UQUAD
71 #define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD
72 #define sysctl_handle_64 sysctl_handle_quad
73 #define CTLTYPE_U64 CTLTYPE_QUAD
76 #if (__FreeBSD_version >= 900030) || \
77 ((__FreeBSD_version >= 802507) && (__FreeBSD_version < 900000))
82 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
83 static __inline uint64_t
84 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
87 KASSERT(tag == X86_BUS_SPACE_MEM,
88 ("%s: can only handle mem space", __func__));
90 return (*(volatile uint64_t *)(handle + offset));
94 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
95 bus_size_t offset, uint64_t value)
97 KASSERT(tag == X86_BUS_SPACE_MEM,
98 ("%s: can only handle mem space", __func__));
100 *(volatile uint64_t *)(bsh + offset) = value;
103 static __inline uint64_t
104 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
107 return (uint64_t)bus_space_read_4(tag, handle, offset) +
108 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
112 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
113 bus_size_t offset, uint64_t value)
115 bus_space_write_4(tag, bsh, offset, value);
116 bus_space_write_4(tag, bsh, offset + 4, value >> 32);
121 typedef struct adapter adapter_t;
125 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */
128 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */
130 EQ_ESIZE = 64, /* All egress queues use this entry size */
132 RX_FL_ESIZE = EQ_ESIZE, /* 8 64bit addresses */
133 #if MJUMPAGESIZE != MCLBYTES
134 FL_BUF_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
136 FL_BUF_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
143 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
147 /* adapter intr_type */
148 INTR_INTX = (1 << 0),
155 FULL_INIT_DONE = (1 << 0),
157 INTR_DIRECT = (1 << 2), /* direct interrupts for everything */
158 MASTER_PF = (1 << 3),
159 ADAP_SYSCTL_CTX = (1 << 4),
160 TOM_INIT_DONE = (1 << 5),
162 CXGBE_BUSY = (1 << 9),
166 PORT_INIT_DONE = (1 << 1),
167 PORT_SYSCTL_CTX = (1 << 2),
170 #define IS_DOOMED(pi) (pi->flags & DOOMED)
171 #define SET_DOOMED(pi) do {pi->flags |= DOOMED;} while (0)
172 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY)
173 #define SET_BUSY(sc) do {sc->flags |= CXGBE_BUSY;} while (0)
174 #define CLR_BUSY(sc) do {sc->flags &= ~CXGBE_BUSY;} while (0)
178 struct adapter *adapter;
181 struct ifmedia media;
189 int16_t xact_addr_filt;/* index of exact MAC address filter */
190 uint16_t rss_size; /* size of VI's RSS table slice */
191 uint8_t lport; /* associated offload logical port */
198 /* These need to be int as they are used in sysctl */
199 int ntxq; /* # of tx queues */
200 int first_txq; /* index of first tx queue */
201 int nrxq; /* # of rx queues */
202 int first_rxq; /* index of first rx queue */
204 int nofldtxq; /* # of offload tx queues */
205 int first_ofld_txq; /* index of first offload tx queue */
206 int nofldrxq; /* # of offload rx queues */
207 int first_ofld_rxq; /* index of first offload rx queue */
214 struct link_config link_cfg;
215 struct port_stats stats;
217 eventhandler_tag vlan_c;
220 struct sysctl_ctx_list ctx; /* from ifconfig up to driver detach */
222 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
229 uint8_t tag_idx; /* the sc->fl_tag this map comes from */
244 /* DMA maps used for tx */
247 uint32_t map_total; /* # of DMA maps */
248 uint32_t map_pidx; /* next map to be used */
249 uint32_t map_cidx; /* reclaimed up to this index */
250 uint32_t map_avail; /* # of available maps */
254 uint8_t desc_used; /* # of hardware descriptors used by the WR */
255 uint8_t credits; /* NIC txq: # of frames sent out in the WR */
260 IQ_ALLOCATED = (1 << 0), /* firmware resources allocated */
261 IQ_HAS_FL = (1 << 1), /* iq associated with a freelist */
262 IQ_INTR = (1 << 2), /* iq takes direct interrupt */
263 IQ_LRO_ENABLED = (1 << 3), /* iq is an eth rxq with LRO enabled */
272 * Ingress Queue: T4 is producer, driver is consumer.
275 bus_dma_tag_t desc_tag;
276 bus_dmamap_t desc_map;
277 bus_addr_t ba; /* bus address of descriptor ring */
280 uint16_t abs_id; /* absolute SGE id for the iq */
281 int8_t intr_pktc_idx; /* packet count threshold index */
283 __be64 *desc; /* KVA of descriptor ring */
286 struct adapter *adapter;
287 const __be64 *cdesc; /* current descriptor */
288 uint8_t gen; /* generation bit */
289 uint8_t intr_params; /* interrupt holdoff parameters */
290 uint8_t intr_next; /* XXX: holdoff for next interrupt */
291 uint8_t esize; /* size (bytes) of each entry in the queue */
292 uint16_t qsize; /* size (# of entries) of the queue */
293 uint16_t cidx; /* consumer index */
294 uint16_t cntxt_id; /* SGE context id for the iq */
296 STAILQ_ENTRY(sge_iq) link;
307 EQ_TYPEMASK = 7, /* 3 lsbits hold the type */
308 EQ_ALLOCATED = (1 << 3), /* firmware resources allocated */
309 EQ_DOOMED = (1 << 4), /* about to be destroyed */
310 EQ_CRFLUSHED = (1 << 5), /* expecting an update from SGE */
311 EQ_STALLED = (1 << 6), /* out of hw descriptors or dmamaps */
315 * Egress Queue: driver is producer, T4 is consumer.
317 * Note: A free list is an egress queue (driver produces the buffers and T4
318 * consumes them) but it's special enough to have its own struct (see sge_fl).
321 unsigned int flags; /* MUST be first */
322 unsigned int cntxt_id; /* SGE context id for the eq */
323 bus_dma_tag_t desc_tag;
324 bus_dmamap_t desc_map;
328 struct tx_desc *desc; /* KVA of descriptor ring */
329 bus_addr_t ba; /* bus address of descriptor ring */
330 struct sge_qstat *spg; /* status page, for convenience */
331 uint16_t cap; /* max # of desc, for convenience */
332 uint16_t avail; /* available descriptors, for convenience */
333 uint16_t qsize; /* size (# of entries) of the queue */
334 uint16_t cidx; /* consumer idx (desc idx) */
335 uint16_t pidx; /* producer idx (desc idx) */
336 uint16_t pending; /* # of descriptors used since last doorbell */
337 uint16_t iqid; /* iq that gets egr_update for the eq */
338 uint8_t tx_chan; /* tx channel used by the eq */
340 struct callout tx_callout;
344 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for eq */
345 uint32_t unstalled; /* recovered from stall */
349 FL_STARVING = (1 << 0), /* on the adapter's list of starving fl's */
350 FL_DOOMED = (1 << 1), /* about to be destroyed */
353 #define FL_RUNNING_LOW(fl) (fl->cap - fl->needed <= fl->lowat)
354 #define FL_NOT_RUNNING_LOW(fl) (fl->cap - fl->needed >= 2 * fl->lowat)
357 bus_dma_tag_t desc_tag;
358 bus_dmamap_t desc_map;
359 bus_dma_tag_t tag[FL_BUF_SIZES];
365 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
366 bus_addr_t ba; /* bus address of descriptor ring */
367 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
368 uint32_t cap; /* max # of buffers, for convenience */
369 uint16_t qsize; /* size (# of entries) of the queue */
370 uint16_t cntxt_id; /* SGE context id for the freelist */
371 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */
372 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */
373 uint32_t needed; /* # of buffers needed to fill up fl. */
374 uint32_t lowat; /* # of buffers <= this means fl needs help */
375 uint32_t pending; /* # of bufs allocated since last doorbell */
376 unsigned int dmamap_failed;
377 TAILQ_ENTRY(sge_fl) link; /* All starving freelists */
380 /* txq: SGE egress queue + what's needed for Ethernet NIC */
382 struct sge_eq eq; /* MUST be first */
384 struct ifnet *ifp; /* the interface this txq belongs to */
385 bus_dma_tag_t tx_tag; /* tag for transmit buffers */
386 struct buf_ring *br; /* tx buffer ring */
387 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
388 struct mbuf *m; /* held up due to temporary resource shortage */
390 struct tx_maps txmaps;
392 /* stats for common events first */
394 uint64_t txcsum; /* # of times hardware assisted with checksum */
395 uint64_t tso_wrs; /* # of TSO work requests */
396 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
397 uint64_t imm_wrs; /* # of work requests with immediate data */
398 uint64_t sgl_wrs; /* # of work requests with direct SGL */
399 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
400 uint64_t txpkts_wrs; /* # of coalesced tx work requests */
401 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */
403 /* stats for not-that-common events */
405 uint32_t no_dmamap; /* no DMA map to load the mbuf */
406 uint32_t no_desc; /* out of hardware descriptors */
407 } __aligned(CACHE_LINE_SIZE);
409 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
411 struct sge_iq iq; /* MUST be first */
412 struct sge_fl fl; /* MUST follow iq */
414 struct ifnet *ifp; /* the interface this rxq belongs to */
415 #if defined(INET) || defined(INET6)
416 struct lro_ctrl lro; /* LRO state */
419 /* stats for common events first */
421 uint64_t rxcsum; /* # of times hardware assisted with checksum */
422 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
424 /* stats for not-that-common events */
426 } __aligned(CACHE_LINE_SIZE);
428 static inline struct sge_rxq *
429 iq_to_rxq(struct sge_iq *iq)
432 return (member2struct(sge_rxq, iq, iq));
437 /* ofld_rxq: SGE ingress queue + SGE free list + miscellaneous items */
438 struct sge_ofld_rxq {
439 struct sge_iq iq; /* MUST be first */
440 struct sge_fl fl; /* MUST follow iq */
441 } __aligned(CACHE_LINE_SIZE);
443 static inline struct sge_ofld_rxq *
444 iq_to_ofld_rxq(struct sge_iq *iq)
447 return (member2struct(sge_ofld_rxq, iq, iq));
452 STAILQ_ENTRY(wrqe) link;
455 uint64_t wr[] __aligned(16);
459 * wrq: SGE egress queue that is given prebuilt work requests. Both the control
460 * and offload tx queues are of this type.
463 struct sge_eq eq; /* MUST be first */
465 struct adapter *adapter;
467 /* List of WRs held up due to lack of tx descriptors */
468 STAILQ_HEAD(, wrqe) wr_list;
470 /* stats for common events first */
472 uint64_t tx_wrs; /* # of tx work requests */
474 /* stats for not-that-common events */
476 uint32_t no_desc; /* out of hardware descriptors */
477 } __aligned(CACHE_LINE_SIZE);
480 int timer_val[SGE_NTIMERS];
481 int counter_val[SGE_NCOUNTERS];
482 int fl_starve_threshold;
484 int nrxq; /* total # of Ethernet rx queues */
485 int ntxq; /* total # of Ethernet tx tx queues */
487 int nofldrxq; /* total # of TOE rx queues */
488 int nofldtxq; /* total # of TOE tx queues */
490 int niq; /* total # of ingress queues */
491 int neq; /* total # of egress queues */
493 struct sge_iq fwq; /* Firmware event queue */
494 struct sge_wrq mgmtq; /* Management queue (control queue) */
495 struct sge_wrq *ctrlq; /* Control queues */
496 struct sge_txq *txq; /* NIC tx queues */
497 struct sge_rxq *rxq; /* NIC rx queues */
499 struct sge_wrq *ofld_txq; /* TOE tx queues */
500 struct sge_ofld_rxq *ofld_rxq; /* TOE rx queues */
505 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
506 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
510 typedef int (*cpl_handler_t)(struct sge_iq *, const struct rss_header *,
512 typedef int (*an_handler_t)(struct sge_iq *, const struct rsp_ctrl *);
515 SLIST_ENTRY(adapter) link;
519 /* PCIe register resources */
521 struct resource *regs_res;
523 struct resource *msix_res;
524 bus_space_handle_t bh;
531 /* Interrupt information */
535 struct resource *res;
540 bus_dma_tag_t dmat; /* Parent DMA tag */
544 struct taskqueue *tq[NCHAN]; /* taskqueues that flush data out */
545 struct port_info *port[MAX_NPORTS];
546 uint8_t chan_map[NCHAN];
547 uint32_t filter_mode;
550 void *tom_softc; /* (struct tom_data *) */
551 struct tom_tunables tt;
553 struct l2t_data *l2t; /* L2 table */
554 struct tid_info tids;
564 struct adapter_params params;
565 struct t4_virt_res vres;
574 struct sysctl_ctx_list ctx; /* from adapter_full_init to full_uninit */
579 /* Starving free lists */
580 struct mtx sfl_lock; /* same cache-line as sc_lock? but that's ok */
581 TAILQ_HEAD(, sge_fl) sfl;
582 struct callout sfl_callout;
584 an_handler_t an_handler __aligned(CACHE_LINE_SIZE);
585 cpl_handler_t cpl_handler[256];
588 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
589 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
590 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
591 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
593 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
594 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
595 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
596 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
598 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
599 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
600 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
601 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
602 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
604 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
605 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
606 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
607 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
609 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
610 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
611 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
612 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
613 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
615 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
616 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
617 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
618 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
619 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
621 #define for_each_txq(pi, iter, txq) \
622 txq = &pi->adapter->sge.txq[pi->first_txq]; \
623 for (iter = 0; iter < pi->ntxq; ++iter, ++txq)
624 #define for_each_rxq(pi, iter, rxq) \
625 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \
626 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq)
627 #define for_each_ofld_txq(pi, iter, ofld_txq) \
628 ofld_txq = &pi->adapter->sge.ofld_txq[pi->first_ofld_txq]; \
629 for (iter = 0; iter < pi->nofldtxq; ++iter, ++ofld_txq)
630 #define for_each_ofld_rxq(pi, iter, ofld_rxq) \
631 ofld_rxq = &pi->adapter->sge.ofld_rxq[pi->first_ofld_rxq]; \
632 for (iter = 0; iter < pi->nofldrxq; ++iter, ++ofld_rxq)
634 /* One for errors, one for firmware events */
635 #define T4_EXTRA_INTR 2
637 static inline uint32_t
638 t4_read_reg(struct adapter *sc, uint32_t reg)
641 return bus_space_read_4(sc->bt, sc->bh, reg);
645 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
648 bus_space_write_4(sc->bt, sc->bh, reg, val);
651 static inline uint64_t
652 t4_read_reg64(struct adapter *sc, uint32_t reg)
655 return t4_bus_space_read_8(sc->bt, sc->bh, reg);
659 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
662 t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
666 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
669 *val = pci_read_config(sc->dev, reg, 1);
673 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
676 pci_write_config(sc->dev, reg, val, 1);
680 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
683 *val = pci_read_config(sc->dev, reg, 2);
687 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
690 pci_write_config(sc->dev, reg, val, 2);
694 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
697 *val = pci_read_config(sc->dev, reg, 4);
701 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
704 pci_write_config(sc->dev, reg, val, 4);
707 static inline struct port_info *
708 adap2pinfo(struct adapter *sc, int idx)
711 return (sc->port[idx]);
715 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
718 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN);
721 static inline bool is_10G_port(const struct port_info *pi)
724 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
727 static inline int tx_resume_threshold(struct sge_eq *eq)
730 return (eq->qsize / 4);
734 void t4_tx_task(void *, int);
735 void t4_tx_callout(void *);
736 int t4_os_find_pci_capability(struct adapter *, int);
737 int t4_os_pci_save_state(struct adapter *);
738 int t4_os_pci_restore_state(struct adapter *);
739 void t4_os_portmod_changed(const struct adapter *, int);
740 void t4_os_link_changed(struct adapter *, int, int);
741 void t4_iterate(void (*)(struct adapter *, void *), void *);
742 int t4_register_cpl_handler(struct adapter *, int, cpl_handler_t);
743 int t4_register_an_handler(struct adapter *, an_handler_t);
746 void t4_sge_modload(void);
747 int t4_sge_init(struct adapter *);
748 int t4_create_dma_tag(struct adapter *);
749 int t4_destroy_dma_tag(struct adapter *);
750 int t4_setup_adapter_queues(struct adapter *);
751 int t4_teardown_adapter_queues(struct adapter *);
752 int t4_setup_port_queues(struct port_info *);
753 int t4_teardown_port_queues(struct port_info *);
754 int t4_alloc_tx_maps(struct tx_maps *, bus_dma_tag_t, int, int);
755 void t4_free_tx_maps(struct tx_maps *, bus_dma_tag_t);
756 void t4_intr_all(void *);
757 void t4_intr(void *);
758 void t4_intr_err(void *);
759 void t4_intr_evt(void *);
760 void t4_wrq_tx_locked(struct adapter *, struct sge_wrq *, struct wrqe *);
761 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *);
762 void t4_update_fl_bufsize(struct ifnet *);
763 int can_resume_tx(struct sge_eq *);
765 static inline struct wrqe *
766 alloc_wrqe(int wr_len, struct sge_wrq *wrq)
768 int len = offsetof(struct wrqe, wr) + wr_len;
771 wr = malloc(len, M_CXGBE, M_NOWAIT);
772 if (__predict_false(wr == NULL))
780 wrtod(struct wrqe *wr)
786 free_wrqe(struct wrqe *wr)
792 t4_wrq_tx(struct adapter *sc, struct wrqe *wr)
794 struct sge_wrq *wrq = wr->wrq;
797 t4_wrq_tx_locked(sc, wrq, wr);