2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 #ifndef __T4_ADAPTER_H__
32 #define __T4_ADAPTER_H__
36 #include <sys/types.h>
37 #include <sys/malloc.h>
38 #include <dev/pci/pcivar.h>
39 #include <dev/pci/pcireg.h>
40 #include <machine/bus.h>
41 #include <sys/socket.h>
42 #include <sys/sysctl.h>
43 #include <net/ethernet.h>
45 #include <net/if_media.h>
46 #include <netinet/tcp_lro.h>
49 #include "common/t4fw_interface.h"
51 #define T4_FWNAME "t4fw"
53 MALLOC_DECLARE(M_CXGBE);
54 #define CXGBE_UNIMPLEMENTED(s) \
55 panic("%s (%s, line %d) not implemented yet.", s, __FILE__, __LINE__)
57 #if defined(__i386__) || defined(__amd64__)
61 __asm volatile("prefetcht0 %0" :: "m" (*(unsigned long *)x));
68 /* XXX: need systemwide bus_space_read_8/bus_space_write_8 */
69 static __inline uint64_t
70 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
73 KASSERT(tag == AMD64_BUS_SPACE_MEM,
74 ("%s: can only handle mem space", __func__));
76 return (*(volatile uint64_t *)(handle + offset));
80 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
81 bus_size_t offset, uint64_t value)
83 KASSERT(tag == AMD64_BUS_SPACE_MEM,
84 ("%s: can only handle mem space", __func__));
86 *(volatile uint64_t *)(bsh + offset) = value;
89 static __inline uint64_t
90 t4_bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle,
93 return (uint64_t)bus_space_read_4(tag, handle, offset) +
94 ((uint64_t)bus_space_read_4(tag, handle, offset + 4) << 32);
98 t4_bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t bsh,
99 bus_size_t offset, uint64_t value)
101 bus_space_write_4(tag, bsh, offset, value);
102 bus_space_write_4(tag, bsh, offset + 4, value >> 32);
107 typedef struct adapter adapter_t;
111 FW_IQ_ESIZE = 64, /* At least 64 mandated by the firmware spec */
114 RX_IQ_ESIZE = 64, /* At least 64 so CPL_RX_PKT will fit */
116 RX_FL_ESIZE = 64, /* 8 64bit addresses */
118 #if MJUMPAGESIZE != MCLBYTES
119 FL_BUF_SIZES = 4, /* cluster, jumbop, jumbo9k, jumbo16k */
121 FL_BUF_SIZES = 3, /* cluster, jumbo9k, jumbo16k */
127 TX_WR_FLITS = SGE_MAX_WR_LEN / 8
131 /* adapter intr_type */
132 INTR_INTX = (1 << 0),
139 FULL_INIT_DONE = (1 << 0),
143 CXGBE_BUSY = (1 << 9),
147 VI_ENABLED = (1 << 1),
150 #define IS_DOOMED(pi) (pi->flags & DOOMED)
151 #define SET_DOOMED(pi) do {pi->flags |= DOOMED;} while (0)
152 #define IS_BUSY(sc) (sc->flags & CXGBE_BUSY)
153 #define SET_BUSY(sc) do {sc->flags |= CXGBE_BUSY;} while (0)
154 #define CLR_BUSY(sc) do {sc->flags &= ~CXGBE_BUSY;} while (0)
158 struct adapter *adapter;
161 struct ifmedia media;
169 int16_t xact_addr_filt;/* index of exact MAC address filter */
170 uint16_t rss_size; /* size of VI's RSS table slice */
171 uint8_t lport; /* associated offload logical port */
178 /* These need to be int as they are used in sysctl */
179 int ntxq; /* # of tx queues */
180 int first_txq; /* index of first tx queue */
181 int nrxq; /* # of rx queues */
182 int first_rxq; /* index of first rx queue */
188 struct link_config link_cfg;
189 struct port_stats stats;
191 struct taskqueue *tq;
193 struct sysctl_ctx_list ctx; /* lives from ifconfig up to down */
194 struct sysctl_oid *oid_rxq;
195 struct sysctl_oid *oid_txq;
197 uint8_t hw_addr[ETHER_ADDR_LEN]; /* factory MAC address, won't change */
204 uint8_t tag_idx; /* the sc->fl_tag this map comes from */
220 uint8_t desc_used; /* # of hardware descriptors used by the WR */
221 uint8_t map_used; /* # of frames sent out in the WR */
224 typedef void (iq_intr_handler_t)(void *);
228 IQ_ALLOCATED = (1 << 1), /* firmware resources allocated */
229 IQ_STARTED = (1 << 2), /* started */
233 * Ingress Queue: T4 is producer, driver is consumer.
236 bus_dma_tag_t desc_tag;
237 bus_dmamap_t desc_map;
238 bus_addr_t ba; /* bus address of descriptor ring */
241 uint16_t abs_id; /* absolute SGE id for the iq */
242 int8_t intr_pktc_idx; /* packet count threshold index */
244 iq_intr_handler_t *handler;
245 __be64 *desc; /* KVA of descriptor ring */
248 struct adapter *adapter;
249 const __be64 *cdesc; /* current descriptor */
250 uint8_t gen; /* generation bit */
251 uint8_t intr_params; /* interrupt holdoff parameters */
252 uint8_t intr_next; /* holdoff for next interrupt */
253 uint8_t esize; /* size (bytes) of each entry in the queue */
254 uint16_t qsize; /* size (# of entries) of the queue */
255 uint16_t cidx; /* consumer index */
256 uint16_t cntxt_id; /* SGE context id for the iq */
261 EQ_ALLOCATED = (1 << 1), /* firmware resources allocated */
262 EQ_STARTED = (1 << 2), /* started */
263 EQ_STALLED = (1 << 3), /* currently stalled */
267 * Egress Queue: driver is producer, T4 is consumer.
269 * Note: A free list is an egress queue (driver produces the buffers and T4
270 * consumes them) but it's special enough to have its own struct (see sge_fl).
273 bus_dma_tag_t tx_tag; /* tag for transmit buffers */
274 bus_dma_tag_t desc_tag;
275 bus_dmamap_t desc_map;
280 struct tx_desc *desc; /* KVA of descriptor ring */
281 bus_addr_t ba; /* bus address of descriptor ring */
282 struct tx_sdesc *sdesc; /* KVA of software descriptor ring */
283 struct buf_ring *br; /* tx buffer ring */
284 struct sge_qstat *spg; /* status page, for convenience */
285 uint16_t cap; /* max # of desc, for convenience */
286 uint16_t avail; /* available descriptors, for convenience */
287 uint16_t qsize; /* size (# of entries) of the queue */
288 uint16_t cidx; /* consumer idx (desc idx) */
289 uint16_t pidx; /* producer idx (desc idx) */
290 uint16_t pending; /* # of descriptors used since last doorbell */
291 uint16_t iqid; /* iq that gets egr_update for the eq */
292 uint32_t cntxt_id; /* SGE context id for the eq */
294 /* DMA maps used for tx */
296 uint32_t map_total; /* # of DMA maps */
297 uint32_t map_pidx; /* next map to be used */
298 uint32_t map_cidx; /* reclaimed up to this index */
299 uint32_t map_avail; /* # of available maps */
300 } __aligned(CACHE_LINE_SIZE);
303 bus_dma_tag_t desc_tag;
304 bus_dmamap_t desc_map;
305 bus_dma_tag_t tag[FL_BUF_SIZES];
310 __be64 *desc; /* KVA of descriptor ring, ptr to addresses */
311 bus_addr_t ba; /* bus address of descriptor ring */
312 struct fl_sdesc *sdesc; /* KVA of software descriptor ring */
313 uint32_t cap; /* max # of buffers, for convenience */
314 uint16_t qsize; /* size (# of entries) of the queue */
315 uint16_t cntxt_id; /* SGE context id for the freelist */
316 uint32_t cidx; /* consumer idx (buffer idx, NOT hw desc idx) */
317 uint32_t pidx; /* producer idx (buffer idx, NOT hw desc idx) */
318 uint32_t needed; /* # of buffers needed to fill up fl. */
319 uint32_t pending; /* # of bufs allocated since last doorbell */
320 unsigned int dmamap_failed;
323 /* txq: SGE egress queue + miscellaneous items */
325 struct sge_eq eq; /* MUST be first */
326 struct mbuf *m; /* held up due to temporary resource shortage */
327 struct task resume_tx;
329 struct ifnet *ifp; /* the interface this txq belongs to */
331 /* stats for common events first */
333 uint64_t txcsum; /* # of times hardware assisted with checksum */
334 uint64_t tso_wrs; /* # of IPv4 TSO work requests */
335 uint64_t vlan_insertion;/* # of times VLAN tag was inserted */
336 uint64_t imm_wrs; /* # of work requests with immediate data */
337 uint64_t sgl_wrs; /* # of work requests with direct SGL */
338 uint64_t txpkt_wrs; /* # of txpkt work requests (not coalesced) */
339 uint64_t txpkts_wrs; /* # of coalesced tx work requests */
340 uint64_t txpkts_pkts; /* # of frames in coalesced tx work requests */
342 /* stats for not-that-common events */
344 uint32_t no_dmamap; /* no DMA map to load the mbuf */
345 uint32_t no_desc; /* out of hardware descriptors */
346 uint32_t egr_update; /* # of SGE_EGR_UPDATE notifications for txq */
350 RXQ_LRO_ENABLED = (1 << 0)
352 /* rxq: SGE ingress queue + SGE free list + miscellaneous items */
354 struct sge_iq iq; /* MUST be first */
357 struct ifnet *ifp; /* the interface this rxq belongs to */
360 struct lro_ctrl lro; /* LRO state */
363 /* stats for common events first */
365 uint64_t rxcsum; /* # of times hardware assisted with checksum */
366 uint64_t vlan_extraction;/* # of times VLAN tag was extracted */
368 /* stats for not-that-common events */
370 } __aligned(CACHE_LINE_SIZE);
373 uint16_t timer_val[SGE_NTIMERS];
374 uint8_t counter_val[SGE_NCOUNTERS];
376 int nrxq; /* total rx queues (all ports and the rest) */
377 int ntxq; /* total tx queues (all ports and the rest) */
378 int niq; /* total ingress queues */
379 int neq; /* total egress queues */
381 struct sge_iq fwq; /* Firmware event queue */
382 struct sge_iq *fiq; /* Forwarded interrupt queues (INTR_FWD) */
383 struct sge_txq *txq; /* NIC tx queues */
384 struct sge_rxq *rxq; /* NIC rx queues */
388 struct sge_iq **iqmap; /* iq->cntxt_id to iq mapping */
389 struct sge_eq **eqmap; /* eq->cntxt_id to eq mapping */
396 /* PCIe register resources */
398 struct resource *regs_res;
400 struct resource *msix_res;
401 bus_space_handle_t bh;
408 /* Interrupt information */
412 struct resource *res;
417 bus_dma_tag_t dmat; /* Parent DMA tag */
421 struct port_info *port[MAX_NPORTS];
422 uint8_t chan_map[NCHAN];
424 struct tid_info tids;
426 int registered_device_map;
431 struct adapter_params params;
432 struct t4_virt_res vres;
438 #define ADAPTER_LOCK(sc) mtx_lock(&(sc)->sc_lock)
439 #define ADAPTER_UNLOCK(sc) mtx_unlock(&(sc)->sc_lock)
440 #define ADAPTER_LOCK_ASSERT_OWNED(sc) mtx_assert(&(sc)->sc_lock, MA_OWNED)
441 #define ADAPTER_LOCK_ASSERT_NOTOWNED(sc) mtx_assert(&(sc)->sc_lock, MA_NOTOWNED)
443 #define PORT_LOCK(pi) mtx_lock(&(pi)->pi_lock)
444 #define PORT_UNLOCK(pi) mtx_unlock(&(pi)->pi_lock)
445 #define PORT_LOCK_ASSERT_OWNED(pi) mtx_assert(&(pi)->pi_lock, MA_OWNED)
446 #define PORT_LOCK_ASSERT_NOTOWNED(pi) mtx_assert(&(pi)->pi_lock, MA_NOTOWNED)
448 #define IQ_LOCK(iq) mtx_lock(&(iq)->iq_lock)
449 #define IQ_UNLOCK(iq) mtx_unlock(&(iq)->iq_lock)
450 #define IQ_LOCK_ASSERT_OWNED(iq) mtx_assert(&(iq)->iq_lock, MA_OWNED)
451 #define IQ_LOCK_ASSERT_NOTOWNED(iq) mtx_assert(&(iq)->iq_lock, MA_NOTOWNED)
453 #define FL_LOCK(fl) mtx_lock(&(fl)->fl_lock)
454 #define FL_TRYLOCK(fl) mtx_trylock(&(fl)->fl_lock)
455 #define FL_UNLOCK(fl) mtx_unlock(&(fl)->fl_lock)
456 #define FL_LOCK_ASSERT_OWNED(fl) mtx_assert(&(fl)->fl_lock, MA_OWNED)
457 #define FL_LOCK_ASSERT_NOTOWNED(fl) mtx_assert(&(fl)->fl_lock, MA_NOTOWNED)
459 #define RXQ_LOCK(rxq) IQ_LOCK(&(rxq)->iq)
460 #define RXQ_UNLOCK(rxq) IQ_UNLOCK(&(rxq)->iq)
461 #define RXQ_LOCK_ASSERT_OWNED(rxq) IQ_LOCK_ASSERT_OWNED(&(rxq)->iq)
462 #define RXQ_LOCK_ASSERT_NOTOWNED(rxq) IQ_LOCK_ASSERT_NOTOWNED(&(rxq)->iq)
464 #define RXQ_FL_LOCK(rxq) FL_LOCK(&(rxq)->fl)
465 #define RXQ_FL_UNLOCK(rxq) FL_UNLOCK(&(rxq)->fl)
466 #define RXQ_FL_LOCK_ASSERT_OWNED(rxq) FL_LOCK_ASSERT_OWNED(&(rxq)->fl)
467 #define RXQ_FL_LOCK_ASSERT_NOTOWNED(rxq) FL_LOCK_ASSERT_NOTOWNED(&(rxq)->fl)
469 #define EQ_LOCK(eq) mtx_lock(&(eq)->eq_lock)
470 #define EQ_TRYLOCK(eq) mtx_trylock(&(eq)->eq_lock)
471 #define EQ_UNLOCK(eq) mtx_unlock(&(eq)->eq_lock)
472 #define EQ_LOCK_ASSERT_OWNED(eq) mtx_assert(&(eq)->eq_lock, MA_OWNED)
473 #define EQ_LOCK_ASSERT_NOTOWNED(eq) mtx_assert(&(eq)->eq_lock, MA_NOTOWNED)
475 #define TXQ_LOCK(txq) EQ_LOCK(&(txq)->eq)
476 #define TXQ_TRYLOCK(txq) EQ_TRYLOCK(&(txq)->eq)
477 #define TXQ_UNLOCK(txq) EQ_UNLOCK(&(txq)->eq)
478 #define TXQ_LOCK_ASSERT_OWNED(txq) EQ_LOCK_ASSERT_OWNED(&(txq)->eq)
479 #define TXQ_LOCK_ASSERT_NOTOWNED(txq) EQ_LOCK_ASSERT_NOTOWNED(&(txq)->eq)
481 #define for_each_txq(pi, iter, txq) \
482 txq = &pi->adapter->sge.txq[pi->first_txq]; \
483 for (iter = 0; iter < pi->ntxq; ++iter, ++txq)
484 #define for_each_rxq(pi, iter, rxq) \
485 rxq = &pi->adapter->sge.rxq[pi->first_rxq]; \
486 for (iter = 0; iter < pi->nrxq; ++iter, ++rxq)
488 #define NFIQ(sc) ((sc)->intr_count > 1 ? (sc)->intr_count - 1 : 1)
490 static inline uint32_t
491 t4_read_reg(struct adapter *sc, uint32_t reg)
493 return bus_space_read_4(sc->bt, sc->bh, reg);
497 t4_write_reg(struct adapter *sc, uint32_t reg, uint32_t val)
499 bus_space_write_4(sc->bt, sc->bh, reg, val);
502 static inline uint64_t
503 t4_read_reg64(struct adapter *sc, uint32_t reg)
505 return t4_bus_space_read_8(sc->bt, sc->bh, reg);
509 t4_write_reg64(struct adapter *sc, uint32_t reg, uint64_t val)
511 t4_bus_space_write_8(sc->bt, sc->bh, reg, val);
515 t4_os_pci_read_cfg1(struct adapter *sc, int reg, uint8_t *val)
517 *val = pci_read_config(sc->dev, reg, 1);
521 t4_os_pci_write_cfg1(struct adapter *sc, int reg, uint8_t val)
523 pci_write_config(sc->dev, reg, val, 1);
527 t4_os_pci_read_cfg2(struct adapter *sc, int reg, uint16_t *val)
529 *val = pci_read_config(sc->dev, reg, 2);
533 t4_os_pci_write_cfg2(struct adapter *sc, int reg, uint16_t val)
535 pci_write_config(sc->dev, reg, val, 2);
539 t4_os_pci_read_cfg4(struct adapter *sc, int reg, uint32_t *val)
541 *val = pci_read_config(sc->dev, reg, 4);
545 t4_os_pci_write_cfg4(struct adapter *sc, int reg, uint32_t val)
547 pci_write_config(sc->dev, reg, val, 4);
550 static inline struct port_info *
551 adap2pinfo(struct adapter *sc, int idx)
553 return (sc->port[idx]);
557 t4_os_set_hw_addr(struct adapter *sc, int idx, uint8_t hw_addr[])
559 bcopy(hw_addr, sc->port[idx]->hw_addr, ETHER_ADDR_LEN);
562 static inline bool is_10G_port(const struct port_info *pi)
564 return ((pi->link_cfg.supported & FW_PORT_CAP_SPEED_10G) != 0);
568 void cxgbe_txq_start(void *, int);
569 int t4_os_find_pci_capability(struct adapter *, int);
570 int t4_os_pci_save_state(struct adapter *);
571 int t4_os_pci_restore_state(struct adapter *);
572 void t4_os_portmod_changed(const struct adapter *, int);
573 void t4_os_link_changed(struct adapter *, int, int);
576 void t4_sge_modload(void);
577 void t4_sge_init(struct adapter *);
578 int t4_create_dma_tag(struct adapter *);
579 int t4_destroy_dma_tag(struct adapter *);
580 int t4_setup_adapter_iqs(struct adapter *);
581 int t4_teardown_adapter_iqs(struct adapter *);
582 int t4_setup_eth_queues(struct port_info *);
583 int t4_teardown_eth_queues(struct port_info *);
584 void t4_intr_all(void *);
585 void t4_intr_fwd(void *);
586 void t4_intr_err(void *);
587 void t4_intr_evt(void *);
588 void t4_intr_data(void *);
589 int t4_eth_tx(struct ifnet *, struct sge_txq *, struct mbuf *);
590 void t4_update_fl_bufsize(struct ifnet *);