2 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
36 NCHAN = 4, /* # of HW channels */
37 MAX_MTU = 9600, /* max MAC MTU, excluding header + FCS */
38 EEPROMSIZE = 17408, /* Serial EEPROM physical size */
39 EEPROMVSIZE = 32768, /* Serial EEPROM virtual address space size */
40 EEPROMPFSIZE = 1024, /* EEPROM writable area size for PFn, n>0 */
41 RSS_NENTRIES = 2048, /* # of entries in RSS mapping table */
42 TCB_SIZE = 128, /* TCB size */
43 NMTUS = 16, /* size of MTU table */
44 NCCTRL_WIN = 32, /* # of congestion control windows */
45 NTX_SCHED = 8, /* # of HW Tx scheduling queues */
46 PM_NSTATS = 5, /* # of PM stats */
47 MBOX_LEN = 64, /* mailbox size in bytes */
48 TRACE_LEN = 112, /* length of trace data and mask */
49 FILTER_OPT_LEN = 36, /* filter tuple width for optional components */
50 NWOL_PAT = 8, /* # of WoL patterns */
51 WOL_PAT_LEN = 128, /* length of WoL patterns */
55 CIM_NUM_IBQ = 6, /* # of CIM IBQs */
56 CIM_NUM_OBQ = 6, /* # of CIM OBQs */
57 CIMLA_SIZE = 2048, /* # of 32-bit words in CIM LA */
58 CIM_PIFLA_SIZE = 64, /* # of 192-bit words in CIM PIF LA */
59 CIM_MALA_SIZE = 64, /* # of 160-bit words in CIM MA LA */
60 CIM_IBQ_SIZE = 128, /* # of 128-bit words in a CIM IBQ */
61 CIM_OBQ_SIZE = 128, /* # of 128-bit words in a CIM OBQ */
62 TPLA_SIZE = 128, /* # of 64-bit words in TP LA */
63 ULPRX_LA_SIZE = 512, /* # of 256-bit words in ULP_RX LA */
67 SF_PAGE_SIZE = 256, /* serial flash page size */
68 SF_SEC_SIZE = 64 * 1024, /* serial flash sector size */
71 /* SGE context types */
72 enum ctxt_type { CTXT_EGRESS, CTXT_INGRESS, CTXT_FLM, CTXT_CNM };
74 enum { RSP_TYPE_FLBUF, RSP_TYPE_CPL, RSP_TYPE_INTR }; /* response entry types */
76 enum { MBOX_OWNER_NONE, MBOX_OWNER_FW, MBOX_OWNER_DRV }; /* mailbox owners */
79 SGE_MAX_WR_LEN = 512, /* max WR size in bytes */
80 SGE_CTXT_SIZE = 24, /* size of SGE context */
81 SGE_NTIMERS = 6, /* # of interrupt holdoff timer values */
82 SGE_NCOUNTERS = 4, /* # of interrupt packet counter values */
85 struct sge_qstat { /* data written to SGE queue status entries */
91 #define S_QSTAT_PIDX 0
92 #define M_QSTAT_PIDX 0xffff
93 #define G_QSTAT_PIDX(x) (((x) >> S_QSTAT_PIDX) & M_QSTAT_PIDX)
95 #define S_QSTAT_CIDX 16
96 #define M_QSTAT_CIDX 0xffff
97 #define G_QSTAT_CIDX(x) (((x) >> S_QSTAT_CIDX) & M_QSTAT_CIDX)
100 * Structure for last 128 bits of response descriptors
103 __be32 hdrbuflen_pidx;
104 __be32 pldbuflen_qid;
111 #define S_RSPD_NEWBUF 31
112 #define V_RSPD_NEWBUF(x) ((x) << S_RSPD_NEWBUF)
113 #define F_RSPD_NEWBUF V_RSPD_NEWBUF(1U)
116 #define M_RSPD_LEN 0x7fffffff
117 #define V_RSPD_LEN(x) ((x) << S_RSPD_LEN)
118 #define G_RSPD_LEN(x) (((x) >> S_RSPD_LEN) & M_RSPD_LEN)
120 #define S_RSPD_QID S_RSPD_LEN
121 #define M_RSPD_QID M_RSPD_LEN
122 #define V_RSPD_QID(x) V_RSPD_LEN(x)
123 #define G_RSPD_QID(x) G_RSPD_LEN(x)
126 #define V_RSPD_GEN(x) ((x) << S_RSPD_GEN)
127 #define F_RSPD_GEN V_RSPD_GEN(1U)
129 #define S_RSPD_QOVFL 6
130 #define V_RSPD_QOVFL(x) ((x) << S_RSPD_QOVFL)
131 #define F_RSPD_QOVFL V_RSPD_QOVFL(1U)
133 #define S_RSPD_TYPE 4
134 #define M_RSPD_TYPE 0x3
135 #define V_RSPD_TYPE(x) ((x) << S_RSPD_TYPE)
136 #define G_RSPD_TYPE(x) (((x) >> S_RSPD_TYPE) & M_RSPD_TYPE)
138 /* Rx queue interrupt deferral fields: counter enable and timer index */
139 #define S_QINTR_CNT_EN 0
140 #define V_QINTR_CNT_EN(x) ((x) << S_QINTR_CNT_EN)
141 #define F_QINTR_CNT_EN V_QINTR_CNT_EN(1U)
143 #define S_QINTR_TIMER_IDX 1
144 #define M_QINTR_TIMER_IDX 0x7
145 #define V_QINTR_TIMER_IDX(x) ((x) << S_QINTR_TIMER_IDX)
146 #define G_QINTR_TIMER_IDX(x) (((x) >> S_QINTR_TIMER_IDX) & M_QINTR_TIMER_IDX)
148 /* # of pages a pagepod can hold without needing another pagepod */
149 #define PPOD_PAGES 4U
152 __be64 vld_tid_pgsz_tag_color;
155 __be64 addr[PPOD_PAGES + 1];
158 #define S_PPOD_COLOR 0
159 #define M_PPOD_COLOR 0x3F
160 #define V_PPOD_COLOR(x) ((x) << S_PPOD_COLOR)
163 #define M_PPOD_TAG 0xFFFFFF
164 #define V_PPOD_TAG(x) ((x) << S_PPOD_TAG)
165 #define G_PPOD_TAG(x) (((x) >> S_PPOD_TAG) & M_PPOD_TAG)
167 #define S_PPOD_PGSZ 30
168 #define M_PPOD_PGSZ 0x3
169 #define V_PPOD_PGSZ(x) ((x) << S_PPOD_PGSZ)
170 #define G_PPOD_PGSZ(x) (((x) >> S_PPOD_PGSZ) & M_PPOD_PGSZ)
172 #define S_PPOD_TID 32
173 #define M_PPOD_TID 0xFFFFFF
174 #define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID)
176 #define S_PPOD_VALID 56
177 #define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID)
178 #define F_PPOD_VALID V_PPOD_VALID(1ULL)
180 #define S_PPOD_LEN 32
181 #define M_PPOD_LEN 0xFFFFFFFF
182 #define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN)
184 #define S_PPOD_OFST 0
185 #define M_PPOD_OFST 0xFFFFFFFF
186 #define V_PPOD_OFST(x) ((x) << S_PPOD_OFST)
191 #define FLASH_START(start) ((start) * SF_SEC_SIZE)
192 #define FLASH_MAX_SIZE(nsecs) ((nsecs) * SF_SEC_SIZE)
196 * Various Expansion-ROM boot images, etc.
198 FLASH_EXP_ROM_START_SEC = 0,
199 FLASH_EXP_ROM_NSECS = 6,
200 FLASH_EXP_ROM_START = FLASH_START(FLASH_EXP_ROM_START_SEC),
201 FLASH_EXP_ROM_MAX_SIZE = FLASH_MAX_SIZE(FLASH_EXP_ROM_NSECS),
204 * iSCSI Boot Firmware Table (iBFT) and other driver-related
207 FLASH_IBFT_START_SEC = 6,
208 FLASH_IBFT_NSECS = 1,
209 FLASH_IBFT_START = FLASH_START(FLASH_IBFT_START_SEC),
210 FLASH_IBFT_MAX_SIZE = FLASH_MAX_SIZE(FLASH_IBFT_NSECS),
213 * Boot configuration data.
215 FLASH_BOOTCFG_START_SEC = 7,
216 FLASH_BOOTCFG_NSECS = 1,
217 FLASH_BOOTCFG_START = FLASH_START(FLASH_BOOTCFG_START_SEC),
218 FLASH_BOOTCFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_BOOTCFG_NSECS),
221 * Location of firmware image in FLASH.
223 FLASH_FW_START_SEC = 8,
225 FLASH_FW_START = FLASH_START(FLASH_FW_START_SEC),
226 FLASH_FW_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FW_NSECS),
229 * iSCSI persistent/crash information.
231 FLASH_ISCSI_CRASH_START_SEC = 29,
232 FLASH_ISCSI_CRASH_NSECS = 1,
233 FLASH_ISCSI_CRASH_START = FLASH_START(FLASH_ISCSI_CRASH_START_SEC),
234 FLASH_ISCSI_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_ISCSI_CRASH_NSECS),
237 * FCoE persistent/crash information.
239 FLASH_FCOE_CRASH_START_SEC = 30,
240 FLASH_FCOE_CRASH_NSECS = 1,
241 FLASH_FCOE_CRASH_START = FLASH_START(FLASH_FCOE_CRASH_START_SEC),
242 FLASH_FCOE_CRASH_MAX_SIZE = FLASH_MAX_SIZE(FLASH_FCOE_CRASH_NSECS),
245 * Location of Firmware Configuration File in FLASH. Since the FPGA
246 * "FLASH" is smaller we need to store the Configuration File in a
247 * different location -- which will overlap the end of the firmware
248 * image if firmware ever gets that large ...
250 FLASH_CFG_START_SEC = 31,
252 FLASH_CFG_START = FLASH_START(FLASH_CFG_START_SEC),
253 FLASH_CFG_MAX_SIZE = FLASH_MAX_SIZE(FLASH_CFG_NSECS),
255 FLASH_FPGA_CFG_START_SEC = 15,
256 FLASH_FPGA_CFG_START = FLASH_START(FLASH_FPGA_CFG_START_SEC),
259 * Sectors 32-63 are reserved for FLASH failover.
264 #undef FLASH_MAX_SIZE
266 #endif /* __T4_HW_H */