2 * Copyright (c) 2011 Chelsio Communications, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
34 CPL_PASS_OPEN_REQ = 0x1,
35 CPL_PASS_ACCEPT_RPL = 0x2,
36 CPL_ACT_OPEN_REQ = 0x3,
38 CPL_SET_TCB_FIELD = 0x5,
40 CPL_CLOSE_CON_REQ = 0x8,
41 CPL_CLOSE_LISTSRV_REQ = 0x9,
45 CPL_RX_DATA_ACK = 0xD,
47 CPL_RTE_DELETE_REQ = 0xF,
48 CPL_RTE_WRITE_REQ = 0x10,
49 CPL_RTE_READ_REQ = 0x11,
50 CPL_L2T_WRITE_REQ = 0x12,
51 CPL_L2T_READ_REQ = 0x13,
52 CPL_SMT_WRITE_REQ = 0x14,
53 CPL_SMT_READ_REQ = 0x15,
54 CPL_TAG_WRITE_REQ = 0x16,
56 CPL_TID_RELEASE = 0x1A,
57 CPL_TAG_READ_REQ = 0x1B,
58 CPL_TX_PKT_FSO = 0x1E,
59 CPL_TX_PKT_ISO = 0x1F,
61 CPL_CLOSE_LISTSRV_RPL = 0x20,
63 CPL_GET_TCB_RPL = 0x22,
64 CPL_L2T_WRITE_RPL = 0x23,
65 CPL_PASS_OPEN_RPL = 0x24,
66 CPL_ACT_OPEN_RPL = 0x25,
67 CPL_PEER_CLOSE = 0x26,
68 CPL_RTE_DELETE_RPL = 0x27,
69 CPL_RTE_WRITE_RPL = 0x28,
70 CPL_RX_URG_PKT = 0x29,
71 CPL_TAG_WRITE_RPL = 0x2A,
72 CPL_ABORT_REQ_RSS = 0x2B,
73 CPL_RX_URG_NOTIFY = 0x2C,
74 CPL_ABORT_RPL_RSS = 0x2D,
75 CPL_SMT_WRITE_RPL = 0x2E,
76 CPL_TX_DATA_ACK = 0x2F,
78 CPL_RX_PHYS_ADDR = 0x30,
79 CPL_PCMD_READ_RPL = 0x31,
80 CPL_CLOSE_CON_RPL = 0x32,
82 CPL_L2T_READ_RPL = 0x34,
84 CPL_RDMA_CQE_READ_RSP = 0x36,
85 CPL_RDMA_CQE_ERR = 0x37,
86 CPL_RTE_READ_RPL = 0x38,
88 CPL_SET_TCB_RPL = 0x3A,
90 CPL_TAG_READ_RPL = 0x3C,
91 CPL_HIT_NOTIFY = 0x3D,
92 CPL_PKT_NOTIFY = 0x3E,
93 CPL_RX_DDP_COMPLETE = 0x3F,
95 CPL_ACT_ESTABLISH = 0x40,
96 CPL_PASS_ESTABLISH = 0x41,
97 CPL_RX_DATA_DDP = 0x42,
98 CPL_SMT_READ_RPL = 0x43,
99 CPL_PASS_ACCEPT_REQ = 0x44,
100 CPL_RX2TX_PKT = 0x45,
101 CPL_RX_FCOE_DDP = 0x46,
103 CPL_T5_TRACE_PKT = 0x48,
104 CPL_RX_ISCSI_DDP = 0x49,
105 CPL_RX_FCOE_DIF = 0x4A,
106 CPL_RX_DATA_DIF = 0x4B,
108 CPL_RDMA_READ_REQ = 0x60,
109 CPL_RX_ISCSI_DIF = 0x60,
111 CPL_SET_LE_REQ = 0x80,
112 CPL_PASS_OPEN_REQ6 = 0x81,
113 CPL_ACT_OPEN_REQ6 = 0x83,
115 CPL_RDMA_TERMINATE = 0xA2,
116 CPL_RDMA_WRITE = 0xA4,
117 CPL_SGE_EGR_UPDATE = 0xA5,
118 CPL_SET_LE_RPL = 0xA6,
121 CPL_T5_RDMA_READ_REQ = 0xA9,
122 CPL_RDMA_ATOMIC_REQ = 0xAA,
123 CPL_RDMA_ATOMIC_RPL = 0xAB,
124 CPL_RDMA_IMM_DATA = 0xAC,
125 CPL_RDMA_IMM_DATA_SE = 0xAD,
127 CPL_TRACE_PKT = 0xB0,
128 CPL_RX2TX_DATA = 0xB1,
129 CPL_ISCSI_DATA = 0xB2,
130 CPL_FCOE_DATA = 0xB3,
138 CPL_TX_PKT_LSO = 0xED,
139 CPL_TX_PKT_XT = 0xEE,
141 NUM_CPL_CMDS /* must be last and previous entries must be sorted */
146 CPL_ERR_TCAM_PARITY = 1,
147 CPL_ERR_TCAM_FULL = 3,
148 CPL_ERR_BAD_LENGTH = 15,
149 CPL_ERR_BAD_ROUTE = 18,
150 CPL_ERR_CONN_RESET = 20,
151 CPL_ERR_CONN_EXIST_SYNRECV = 21,
152 CPL_ERR_CONN_EXIST = 22,
153 CPL_ERR_ARP_MISS = 23,
154 CPL_ERR_BAD_SYN = 24,
155 CPL_ERR_CONN_TIMEDOUT = 30,
156 CPL_ERR_XMIT_TIMEDOUT = 31,
157 CPL_ERR_PERSIST_TIMEDOUT = 32,
158 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
159 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
160 CPL_ERR_RTX_NEG_ADVICE = 35,
161 CPL_ERR_PERSIST_NEG_ADVICE = 36,
162 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
163 CPL_ERR_WAIT_ARP_RPL = 41,
164 CPL_ERR_ABORT_FAILED = 42,
165 CPL_ERR_IWARP_FLM = 50,
169 CPL_CONN_POLICY_AUTO = 0,
170 CPL_CONN_POLICY_ASK = 1,
171 CPL_CONN_POLICY_FILTER = 2,
172 CPL_CONN_POLICY_DENY = 3
184 ULP_CRC_HEADER = 1 << 0,
185 ULP_CRC_DATA = 1 << 1
189 CPL_PASS_OPEN_ACCEPT,
190 CPL_PASS_OPEN_REJECT,
191 CPL_PASS_OPEN_ACCEPT_TNL
195 CPL_ABORT_SEND_RST = 0,
199 enum { /* TX_PKT_XT checksum types */
213 enum { /* packet type in CPL_RX_PKT */
214 PKTYPE_XACT_UCAST = 0,
215 PKTYPE_HASH_UCAST = 1,
216 PKTYPE_XACT_MCAST = 2,
217 PKTYPE_HASH_MCAST = 3,
223 enum { /* DMAC type in CPL_RX_PKT */
229 enum { /* TCP congestion control algorithms */
236 enum { /* RSS hash type */
237 RSS_HASH_NONE = 0, /* no hash computed */
238 RSS_HASH_IP = 1, /* IP or IPv6 2-tuple hash */
239 RSS_HASH_TCP = 2, /* TCP 4-tuple hash */
240 RSS_HASH_UDP = 3 /* UDP 4-tuple hash */
243 enum { /* LE commands */
248 enum { /* LE request size */
262 #define S_CPL_OPCODE 24
263 #define V_CPL_OPCODE(x) ((x) << S_CPL_OPCODE)
264 #define G_CPL_OPCODE(x) (((x) >> S_CPL_OPCODE) & 0xFF)
265 #define G_TID(x) ((x) & 0xFFFFFF)
267 /* tid is assumed to be 24-bits */
268 #define MK_OPCODE_TID(opcode, tid) (V_CPL_OPCODE(opcode) | (tid))
270 #define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
272 /* extract the TID from a CPL command */
273 #define GET_TID(cmd) (G_TID(ntohl(OPCODE_TID(cmd))))
275 /* partitioning of TID fields that also carry a queue id */
277 #define M_TID_TID 0x3fff
278 #define V_TID_TID(x) ((x) << S_TID_TID)
279 #define G_TID_TID(x) (((x) >> S_TID_TID) & M_TID_TID)
282 #define M_TID_QID 0x3ff
283 #define V_TID_QID(x) ((x) << S_TID_QID)
284 #define G_TID_QID(x) (((x) >> S_TID_QID) & M_TID_QID)
294 #if defined(__LITTLE_ENDIAN_BITFIELD)
311 #if defined(__LITTLE_ENDIAN_BITFIELD)
330 #define S_HASHTYPE 20
331 #define M_HASHTYPE 0x3
332 #define G_HASHTYPE(x) (((x) >> S_HASHTYPE) & M_HASHTYPE)
335 #define M_QNUM 0xFFFF
336 #define G_QNUM(x) (((x) >> S_QNUM) & M_QNUM)
339 struct work_request_hdr {
347 #define M_WR_LEN16 0xFF
348 #define V_WR_LEN16(x) ((x) << S_WR_LEN16)
349 #define G_WR_LEN16(x) (((x) >> S_WR_LEN16) & M_WR_LEN16)
354 #define V_WR_OP(x) ((__u64)(x) << S_WR_OP)
355 #define G_WR_OP(x) (((x) >> S_WR_OP) & M_WR_OP)
357 # define WR_HDR struct work_request_hdr wr
358 # define WR_HDR_SIZE sizeof(struct work_request_hdr)
362 # define WR_HDR_SIZE 0
363 # define RSS_HDR struct rss_header rss_hdr;
366 /* option 0 fields */
367 #define S_ACCEPT_MODE 0
368 #define M_ACCEPT_MODE 0x3
369 #define V_ACCEPT_MODE(x) ((x) << S_ACCEPT_MODE)
370 #define G_ACCEPT_MODE(x) (((x) >> S_ACCEPT_MODE) & M_ACCEPT_MODE)
373 #define M_TX_CHAN 0x3
374 #define V_TX_CHAN(x) ((x) << S_TX_CHAN)
375 #define G_TX_CHAN(x) (((x) >> S_TX_CHAN) & M_TX_CHAN)
378 #define V_NO_CONG(x) ((x) << S_NO_CONG)
379 #define F_NO_CONG V_NO_CONG(1U)
382 #define V_DELACK(x) ((x) << S_DELACK)
383 #define F_DELACK V_DELACK(1U)
385 #define S_INJECT_TIMER 6
386 #define V_INJECT_TIMER(x) ((x) << S_INJECT_TIMER)
387 #define F_INJECT_TIMER V_INJECT_TIMER(1U)
389 #define S_NON_OFFLOAD 7
390 #define V_NON_OFFLOAD(x) ((x) << S_NON_OFFLOAD)
391 #define F_NON_OFFLOAD V_NON_OFFLOAD(1U)
394 #define M_ULP_MODE 0xF
395 #define V_ULP_MODE(x) ((x) << S_ULP_MODE)
396 #define G_ULP_MODE(x) (((x) >> S_ULP_MODE) & M_ULP_MODE)
398 #define S_RCV_BUFSIZ 12
399 #define M_RCV_BUFSIZ 0x3FFU
400 #define V_RCV_BUFSIZ(x) ((x) << S_RCV_BUFSIZ)
401 #define G_RCV_BUFSIZ(x) (((x) >> S_RCV_BUFSIZ) & M_RCV_BUFSIZ)
405 #define V_DSCP(x) ((x) << S_DSCP)
406 #define G_DSCP(x) (((x) >> S_DSCP) & M_DSCP)
408 #define S_SMAC_SEL 28
409 #define M_SMAC_SEL 0xFF
410 #define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL)
411 #define G_SMAC_SEL(x) (((x) >> S_SMAC_SEL) & M_SMAC_SEL)
414 #define M_L2T_IDX 0xFFF
415 #define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX)
416 #define G_L2T_IDX(x) (((x) >> S_L2T_IDX) & M_L2T_IDX)
418 #define S_TCAM_BYPASS 48
419 #define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS)
420 #define F_TCAM_BYPASS V_TCAM_BYPASS(1ULL)
423 #define V_NAGLE(x) ((__u64)(x) << S_NAGLE)
424 #define F_NAGLE V_NAGLE(1ULL)
426 #define S_WND_SCALE 50
427 #define M_WND_SCALE 0xF
428 #define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE)
429 #define G_WND_SCALE(x) (((x) >> S_WND_SCALE) & M_WND_SCALE)
431 #define S_KEEP_ALIVE 54
432 #define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE)
433 #define F_KEEP_ALIVE V_KEEP_ALIVE(1ULL)
437 #define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT)
438 #define G_MAX_RT(x) (((x) >> S_MAX_RT) & M_MAX_RT)
440 #define S_MAX_RT_OVERRIDE 59
441 #define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE)
442 #define F_MAX_RT_OVERRIDE V_MAX_RT_OVERRIDE(1ULL)
445 #define M_MSS_IDX 0xF
446 #define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX)
447 #define G_MSS_IDX(x) (((x) >> S_MSS_IDX) & M_MSS_IDX)
449 /* option 1 fields */
450 #define S_SYN_RSS_ENABLE 0
451 #define V_SYN_RSS_ENABLE(x) ((x) << S_SYN_RSS_ENABLE)
452 #define F_SYN_RSS_ENABLE V_SYN_RSS_ENABLE(1U)
454 #define S_SYN_RSS_USE_HASH 1
455 #define V_SYN_RSS_USE_HASH(x) ((x) << S_SYN_RSS_USE_HASH)
456 #define F_SYN_RSS_USE_HASH V_SYN_RSS_USE_HASH(1U)
458 #define S_SYN_RSS_QUEUE 2
459 #define M_SYN_RSS_QUEUE 0x3FF
460 #define V_SYN_RSS_QUEUE(x) ((x) << S_SYN_RSS_QUEUE)
461 #define G_SYN_RSS_QUEUE(x) (((x) >> S_SYN_RSS_QUEUE) & M_SYN_RSS_QUEUE)
463 #define S_LISTEN_INTF 12
464 #define M_LISTEN_INTF 0xFF
465 #define V_LISTEN_INTF(x) ((x) << S_LISTEN_INTF)
466 #define G_LISTEN_INTF(x) (((x) >> S_LISTEN_INTF) & M_LISTEN_INTF)
468 #define S_LISTEN_FILTER 20
469 #define V_LISTEN_FILTER(x) ((x) << S_LISTEN_FILTER)
470 #define F_LISTEN_FILTER V_LISTEN_FILTER(1U)
472 #define S_SYN_DEFENSE 21
473 #define V_SYN_DEFENSE(x) ((x) << S_SYN_DEFENSE)
474 #define F_SYN_DEFENSE V_SYN_DEFENSE(1U)
476 #define S_CONN_POLICY 22
477 #define M_CONN_POLICY 0x3
478 #define V_CONN_POLICY(x) ((x) << S_CONN_POLICY)
479 #define G_CONN_POLICY(x) (((x) >> S_CONN_POLICY) & M_CONN_POLICY)
481 /* option 2 fields */
482 #define S_RSS_QUEUE 0
483 #define M_RSS_QUEUE 0x3FF
484 #define V_RSS_QUEUE(x) ((x) << S_RSS_QUEUE)
485 #define G_RSS_QUEUE(x) (((x) >> S_RSS_QUEUE) & M_RSS_QUEUE)
487 #define S_RSS_QUEUE_VALID 10
488 #define V_RSS_QUEUE_VALID(x) ((x) << S_RSS_QUEUE_VALID)
489 #define F_RSS_QUEUE_VALID V_RSS_QUEUE_VALID(1U)
491 #define S_RX_COALESCE_VALID 11
492 #define V_RX_COALESCE_VALID(x) ((x) << S_RX_COALESCE_VALID)
493 #define F_RX_COALESCE_VALID V_RX_COALESCE_VALID(1U)
495 #define S_RX_COALESCE 12
496 #define M_RX_COALESCE 0x3
497 #define V_RX_COALESCE(x) ((x) << S_RX_COALESCE)
498 #define G_RX_COALESCE(x) (((x) >> S_RX_COALESCE) & M_RX_COALESCE)
500 #define S_CONG_CNTRL 14
501 #define M_CONG_CNTRL 0x3
502 #define V_CONG_CNTRL(x) ((x) << S_CONG_CNTRL)
503 #define G_CONG_CNTRL(x) (((x) >> S_CONG_CNTRL) & M_CONG_CNTRL)
507 #define V_PACE(x) ((x) << S_PACE)
508 #define G_PACE(x) (((x) >> S_PACE) & M_PACE)
510 #define S_CONG_CNTRL_VALID 18
511 #define V_CONG_CNTRL_VALID(x) ((x) << S_CONG_CNTRL_VALID)
512 #define F_CONG_CNTRL_VALID V_CONG_CNTRL_VALID(1U)
514 #define S_PACE_VALID 19
515 #define V_PACE_VALID(x) ((x) << S_PACE_VALID)
516 #define F_PACE_VALID V_PACE_VALID(1U)
518 #define S_RX_FC_DISABLE 20
519 #define V_RX_FC_DISABLE(x) ((x) << S_RX_FC_DISABLE)
520 #define F_RX_FC_DISABLE V_RX_FC_DISABLE(1U)
522 #define S_RX_FC_DDP 21
523 #define V_RX_FC_DDP(x) ((x) << S_RX_FC_DDP)
524 #define F_RX_FC_DDP V_RX_FC_DDP(1U)
526 #define S_RX_FC_VALID 22
527 #define V_RX_FC_VALID(x) ((x) << S_RX_FC_VALID)
528 #define F_RX_FC_VALID V_RX_FC_VALID(1U)
530 #define S_TX_QUEUE 23
531 #define M_TX_QUEUE 0x7
532 #define V_TX_QUEUE(x) ((x) << S_TX_QUEUE)
533 #define G_TX_QUEUE(x) (((x) >> S_TX_QUEUE) & M_TX_QUEUE)
535 #define S_RX_CHANNEL 26
536 #define V_RX_CHANNEL(x) ((x) << S_RX_CHANNEL)
537 #define F_RX_CHANNEL V_RX_CHANNEL(1U)
539 #define S_CCTRL_ECN 27
540 #define V_CCTRL_ECN(x) ((x) << S_CCTRL_ECN)
541 #define F_CCTRL_ECN V_CCTRL_ECN(1U)
543 #define S_WND_SCALE_EN 28
544 #define V_WND_SCALE_EN(x) ((x) << S_WND_SCALE_EN)
545 #define F_WND_SCALE_EN V_WND_SCALE_EN(1U)
547 #define S_TSTAMPS_EN 29
548 #define V_TSTAMPS_EN(x) ((x) << S_TSTAMPS_EN)
549 #define F_TSTAMPS_EN V_TSTAMPS_EN(1U)
552 #define V_SACK_EN(x) ((x) << S_SACK_EN)
553 #define F_SACK_EN V_SACK_EN(1U)
555 struct cpl_pass_open_req {
566 struct cpl_pass_open_req6 {
579 struct cpl_pass_open_rpl {
586 struct cpl_pass_establish {
597 /* cpl_pass_establish.tos_stid fields */
598 #define S_PASS_OPEN_TID 0
599 #define M_PASS_OPEN_TID 0xFFFFFF
600 #define V_PASS_OPEN_TID(x) ((x) << S_PASS_OPEN_TID)
601 #define G_PASS_OPEN_TID(x) (((x) >> S_PASS_OPEN_TID) & M_PASS_OPEN_TID)
603 #define S_PASS_OPEN_TOS 24
604 #define M_PASS_OPEN_TOS 0xFF
605 #define V_PASS_OPEN_TOS(x) ((x) << S_PASS_OPEN_TOS)
606 #define G_PASS_OPEN_TOS(x) (((x) >> S_PASS_OPEN_TOS) & M_PASS_OPEN_TOS)
608 /* cpl_pass_establish.tcp_opt fields (also applies to act_open_establish) */
609 #define G_TCPOPT_WSCALE_OK(x) (((x) >> 5) & 1)
610 #define G_TCPOPT_SACK(x) (((x) >> 6) & 1)
611 #define G_TCPOPT_TSTAMP(x) (((x) >> 7) & 1)
612 #define G_TCPOPT_SND_WSCALE(x) (((x) >> 8) & 0xf)
613 #define G_TCPOPT_MSS(x) (((x) >> 12) & 0xf)
615 struct cpl_pass_accept_req {
624 struct tcp_options tcpopt;
627 /* cpl_pass_accept_req.hdr_len fields */
628 #define S_SYN_RX_CHAN 0
629 #define M_SYN_RX_CHAN 0xF
630 #define V_SYN_RX_CHAN(x) ((x) << S_SYN_RX_CHAN)
631 #define G_SYN_RX_CHAN(x) (((x) >> S_SYN_RX_CHAN) & M_SYN_RX_CHAN)
633 #define S_TCP_HDR_LEN 10
634 #define M_TCP_HDR_LEN 0x3F
635 #define V_TCP_HDR_LEN(x) ((x) << S_TCP_HDR_LEN)
636 #define G_TCP_HDR_LEN(x) (((x) >> S_TCP_HDR_LEN) & M_TCP_HDR_LEN)
638 #define S_IP_HDR_LEN 16
639 #define M_IP_HDR_LEN 0x3FF
640 #define V_IP_HDR_LEN(x) ((x) << S_IP_HDR_LEN)
641 #define G_IP_HDR_LEN(x) (((x) >> S_IP_HDR_LEN) & M_IP_HDR_LEN)
643 #define S_ETH_HDR_LEN 26
644 #define M_ETH_HDR_LEN 0x3F
645 #define V_ETH_HDR_LEN(x) ((x) << S_ETH_HDR_LEN)
646 #define G_ETH_HDR_LEN(x) (((x) >> S_ETH_HDR_LEN) & M_ETH_HDR_LEN)
648 /* cpl_pass_accept_req.l2info fields */
649 #define S_SYN_MAC_IDX 0
650 #define M_SYN_MAC_IDX 0x1FF
651 #define V_SYN_MAC_IDX(x) ((x) << S_SYN_MAC_IDX)
652 #define G_SYN_MAC_IDX(x) (((x) >> S_SYN_MAC_IDX) & M_SYN_MAC_IDX)
654 #define S_SYN_XACT_MATCH 9
655 #define V_SYN_XACT_MATCH(x) ((x) << S_SYN_XACT_MATCH)
656 #define F_SYN_XACT_MATCH V_SYN_XACT_MATCH(1U)
658 #define S_SYN_INTF 12
659 #define M_SYN_INTF 0xF
660 #define V_SYN_INTF(x) ((x) << S_SYN_INTF)
661 #define G_SYN_INTF(x) (((x) >> S_SYN_INTF) & M_SYN_INTF)
663 struct cpl_pass_accept_rpl {
670 struct cpl_act_open_req {
682 struct cpl_t5_act_open_req {
695 struct cpl_act_open_req6 {
709 struct cpl_t5_act_open_req6 {
724 struct cpl_act_open_rpl {
730 /* cpl_act_open_rpl.atid_status fields */
731 #define S_AOPEN_STATUS 0
732 #define M_AOPEN_STATUS 0xFF
733 #define V_AOPEN_STATUS(x) ((x) << S_AOPEN_STATUS)
734 #define G_AOPEN_STATUS(x) (((x) >> S_AOPEN_STATUS) & M_AOPEN_STATUS)
736 #define S_AOPEN_ATID 8
737 #define M_AOPEN_ATID 0xFFFFFF
738 #define V_AOPEN_ATID(x) ((x) << S_AOPEN_ATID)
739 #define G_AOPEN_ATID(x) (((x) >> S_AOPEN_ATID) & M_AOPEN_ATID)
741 struct cpl_act_establish {
759 /* cpl_get_tcb.reply_ctrl fields */
761 #define M_QUEUENO 0x3FF
762 #define V_QUEUENO(x) ((x) << S_QUEUENO)
763 #define G_QUEUENO(x) (((x) >> S_QUEUENO) & M_QUEUENO)
765 #define S_REPLY_CHAN 14
766 #define V_REPLY_CHAN(x) ((x) << S_REPLY_CHAN)
767 #define F_REPLY_CHAN V_REPLY_CHAN(1U)
769 #define S_NO_REPLY 15
770 #define V_NO_REPLY(x) ((x) << S_NO_REPLY)
771 #define F_NO_REPLY V_NO_REPLY(1U)
773 struct cpl_get_tcb_rpl {
788 struct cpl_set_tcb_field {
797 struct cpl_set_tcb_field_core {
805 /* cpl_set_tcb_field.word_cookie fields */
808 #define V_WORD(x) ((x) << S_WORD)
809 #define G_WORD(x) (((x) >> S_WORD) & M_WORD)
813 #define V_COOKIE(x) ((x) << S_COOKIE)
814 #define G_COOKIE(x) (((x) >> S_COOKIE) & M_COOKIE)
816 struct cpl_set_tcb_rpl {
825 struct cpl_close_con_req {
831 struct cpl_close_con_rpl {
840 struct cpl_close_listsvr_req {
847 /* additional cpl_close_listsvr_req.reply_ctrl field */
848 #define S_LISTSVR_IPV6 14
849 #define V_LISTSVR_IPV6(x) ((x) << S_LISTSVR_IPV6)
850 #define F_LISTSVR_IPV6 V_LISTSVR_IPV6(1U)
852 struct cpl_close_listsvr_rpl {
859 struct cpl_abort_req_rss {
866 struct cpl_abort_req {
875 struct cpl_abort_rpl_rss {
882 struct cpl_abort_rpl {
891 struct cpl_peer_close {
897 struct cpl_tid_release {
912 /* tx_data_wr.flags fields */
913 #define S_TX_ACK_PAGES 21
914 #define M_TX_ACK_PAGES 0x7
915 #define V_TX_ACK_PAGES(x) ((x) << S_TX_ACK_PAGES)
916 #define G_TX_ACK_PAGES(x) (((x) >> S_TX_ACK_PAGES) & M_TX_ACK_PAGES)
918 /* tx_data_wr.param fields */
920 #define M_TX_PORT 0x7
921 #define V_TX_PORT(x) ((x) << S_TX_PORT)
922 #define G_TX_PORT(x) (((x) >> S_TX_PORT) & M_TX_PORT)
926 #define V_TX_MSS(x) ((x) << S_TX_MSS)
927 #define G_TX_MSS(x) (((x) >> S_TX_MSS) & M_TX_MSS)
930 #define M_TX_QOS 0xFF
931 #define V_TX_QOS(x) ((x) << S_TX_QOS)
932 #define G_TX_QOS(x) (((x) >> S_TX_QOS) & M_TX_QOS)
934 #define S_TX_SNDBUF 16
935 #define M_TX_SNDBUF 0xFFFF
936 #define V_TX_SNDBUF(x) ((x) << S_TX_SNDBUF)
937 #define G_TX_SNDBUF(x) (((x) >> S_TX_SNDBUF) & M_TX_SNDBUF)
946 /* cpl_tx_data.flags fields */
948 #define V_TX_PROXY(x) ((x) << S_TX_PROXY)
949 #define F_TX_PROXY V_TX_PROXY(1U)
951 #define S_TX_ULP_SUBMODE 6
952 #define M_TX_ULP_SUBMODE 0xF
953 #define V_TX_ULP_SUBMODE(x) ((x) << S_TX_ULP_SUBMODE)
954 #define G_TX_ULP_SUBMODE(x) (((x) >> S_TX_ULP_SUBMODE) & M_TX_ULP_SUBMODE)
956 #define S_TX_ULP_MODE 10
957 #define M_TX_ULP_MODE 0xF
958 #define V_TX_ULP_MODE(x) ((x) << S_TX_ULP_MODE)
959 #define G_TX_ULP_MODE(x) (((x) >> S_TX_ULP_MODE) & M_TX_ULP_MODE)
961 #define S_TX_SHOVE 14
962 #define V_TX_SHOVE(x) ((x) << S_TX_SHOVE)
963 #define F_TX_SHOVE V_TX_SHOVE(1U)
966 #define V_TX_MORE(x) ((x) << S_TX_MORE)
967 #define F_TX_MORE V_TX_MORE(1U)
970 #define V_TX_URG(x) ((x) << S_TX_URG)
971 #define F_TX_URG V_TX_URG(1U)
973 #define S_TX_FLUSH 17
974 #define V_TX_FLUSH(x) ((x) << S_TX_FLUSH)
975 #define F_TX_FLUSH V_TX_FLUSH(1U)
978 #define V_TX_SAVE(x) ((x) << S_TX_SAVE)
979 #define F_TX_SAVE V_TX_SAVE(1U)
982 #define V_TX_TNL(x) ((x) << S_TX_TNL)
983 #define F_TX_TNL V_TX_TNL(1U)
985 /* additional tx_data_wr.flags fields */
986 #define S_TX_CPU_IDX 0
987 #define M_TX_CPU_IDX 0x3F
988 #define V_TX_CPU_IDX(x) ((x) << S_TX_CPU_IDX)
989 #define G_TX_CPU_IDX(x) (((x) >> S_TX_CPU_IDX) & M_TX_CPU_IDX)
991 #define S_TX_CLOSE 17
992 #define V_TX_CLOSE(x) ((x) << S_TX_CLOSE)
993 #define F_TX_CLOSE V_TX_CLOSE(1U)
996 #define V_TX_INIT(x) ((x) << S_TX_INIT)
997 #define F_TX_INIT V_TX_INIT(1U)
999 #define S_TX_IMM_ACK 19
1000 #define V_TX_IMM_ACK(x) ((x) << S_TX_IMM_ACK)
1001 #define F_TX_IMM_ACK V_TX_IMM_ACK(1U)
1003 #define S_TX_IMM_DMA 20
1004 #define V_TX_IMM_DMA(x) ((x) << S_TX_IMM_DMA)
1005 #define F_TX_IMM_DMA V_TX_IMM_DMA(1U)
1007 struct cpl_tx_data_ack {
1009 union opcode_tid ot;
1013 struct cpl_wr_ack { /* XXX */
1015 union opcode_tid ot;
1022 struct cpl_tx_pkt_core {
1031 struct cpl_tx_pkt_core c;
1034 #define cpl_tx_pkt_xt cpl_tx_pkt
1036 /* cpl_tx_pkt_core.ctrl0 fields */
1037 #define S_TXPKT_VF 0
1038 #define M_TXPKT_VF 0xFF
1039 #define V_TXPKT_VF(x) ((x) << S_TXPKT_VF)
1040 #define G_TXPKT_VF(x) (((x) >> S_TXPKT_VF) & M_TXPKT_VF)
1042 #define S_TXPKT_PF 8
1043 #define M_TXPKT_PF 0x7
1044 #define V_TXPKT_PF(x) ((x) << S_TXPKT_PF)
1045 #define G_TXPKT_PF(x) (((x) >> S_TXPKT_PF) & M_TXPKT_PF)
1047 #define S_TXPKT_VF_VLD 11
1048 #define V_TXPKT_VF_VLD(x) ((x) << S_TXPKT_VF_VLD)
1049 #define F_TXPKT_VF_VLD V_TXPKT_VF_VLD(1U)
1051 #define S_TXPKT_OVLAN_IDX 12
1052 #define M_TXPKT_OVLAN_IDX 0xF
1053 #define V_TXPKT_OVLAN_IDX(x) ((x) << S_TXPKT_OVLAN_IDX)
1054 #define G_TXPKT_OVLAN_IDX(x) (((x) >> S_TXPKT_OVLAN_IDX) & M_TXPKT_OVLAN_IDX)
1056 #define S_TXPKT_INTF 16
1057 #define M_TXPKT_INTF 0xF
1058 #define V_TXPKT_INTF(x) ((x) << S_TXPKT_INTF)
1059 #define G_TXPKT_INTF(x) (((x) >> S_TXPKT_INTF) & M_TXPKT_INTF)
1061 #define S_TXPKT_SPECIAL_STAT 20
1062 #define V_TXPKT_SPECIAL_STAT(x) ((x) << S_TXPKT_SPECIAL_STAT)
1063 #define F_TXPKT_SPECIAL_STAT V_TXPKT_SPECIAL_STAT(1U)
1065 #define S_TXPKT_INS_OVLAN 21
1066 #define V_TXPKT_INS_OVLAN(x) ((x) << S_TXPKT_INS_OVLAN)
1067 #define F_TXPKT_INS_OVLAN V_TXPKT_INS_OVLAN(1U)
1069 #define S_TXPKT_STAT_DIS 22
1070 #define V_TXPKT_STAT_DIS(x) ((x) << S_TXPKT_STAT_DIS)
1071 #define F_TXPKT_STAT_DIS V_TXPKT_STAT_DIS(1U)
1073 #define S_TXPKT_LOOPBACK 23
1074 #define V_TXPKT_LOOPBACK(x) ((x) << S_TXPKT_LOOPBACK)
1075 #define F_TXPKT_LOOPBACK V_TXPKT_LOOPBACK(1U)
1077 #define S_TXPKT_TSTAMP 23
1078 #define V_TXPKT_TSTAMP(x) ((x) << S_TXPKT_TSTAMP)
1079 #define F_TXPKT_TSTAMP V_TXPKT_TSTAMP(1U)
1081 #define S_TXPKT_OPCODE 24
1082 #define M_TXPKT_OPCODE 0xFF
1083 #define V_TXPKT_OPCODE(x) ((x) << S_TXPKT_OPCODE)
1084 #define G_TXPKT_OPCODE(x) (((x) >> S_TXPKT_OPCODE) & M_TXPKT_OPCODE)
1086 /* cpl_tx_pkt_core.ctrl1 fields */
1087 #define S_TXPKT_SA_IDX 0
1088 #define M_TXPKT_SA_IDX 0xFFF
1089 #define V_TXPKT_SA_IDX(x) ((x) << S_TXPKT_SA_IDX)
1090 #define G_TXPKT_SA_IDX(x) (((x) >> S_TXPKT_SA_IDX) & M_TXPKT_SA_IDX)
1092 #define S_TXPKT_CSUM_END 12
1093 #define M_TXPKT_CSUM_END 0xFF
1094 #define V_TXPKT_CSUM_END(x) ((x) << S_TXPKT_CSUM_END)
1095 #define G_TXPKT_CSUM_END(x) (((x) >> S_TXPKT_CSUM_END) & M_TXPKT_CSUM_END)
1097 #define S_TXPKT_CSUM_START 20
1098 #define M_TXPKT_CSUM_START 0x3FF
1099 #define V_TXPKT_CSUM_START(x) ((x) << S_TXPKT_CSUM_START)
1100 #define G_TXPKT_CSUM_START(x) (((x) >> S_TXPKT_CSUM_START) & M_TXPKT_CSUM_START)
1102 #define S_TXPKT_IPHDR_LEN 20
1103 #define M_TXPKT_IPHDR_LEN 0x3FFF
1104 #define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
1105 #define G_TXPKT_IPHDR_LEN(x) (((x) >> S_TXPKT_IPHDR_LEN) & M_TXPKT_IPHDR_LEN)
1107 #define S_TXPKT_CSUM_LOC 30
1108 #define M_TXPKT_CSUM_LOC 0x3FF
1109 #define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC)
1110 #define G_TXPKT_CSUM_LOC(x) (((x) >> S_TXPKT_CSUM_LOC) & M_TXPKT_CSUM_LOC)
1112 #define S_TXPKT_ETHHDR_LEN 34
1113 #define M_TXPKT_ETHHDR_LEN 0x3F
1114 #define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
1115 #define G_TXPKT_ETHHDR_LEN(x) (((x) >> S_TXPKT_ETHHDR_LEN) & M_TXPKT_ETHHDR_LEN)
1117 #define S_TXPKT_CSUM_TYPE 40
1118 #define M_TXPKT_CSUM_TYPE 0xF
1119 #define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
1120 #define G_TXPKT_CSUM_TYPE(x) (((x) >> S_TXPKT_CSUM_TYPE) & M_TXPKT_CSUM_TYPE)
1122 #define S_TXPKT_VLAN 44
1123 #define M_TXPKT_VLAN 0xFFFF
1124 #define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)
1125 #define G_TXPKT_VLAN(x) (((x) >> S_TXPKT_VLAN) & M_TXPKT_VLAN)
1127 #define S_TXPKT_VLAN_VLD 60
1128 #define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)
1129 #define F_TXPKT_VLAN_VLD V_TXPKT_VLAN_VLD(1ULL)
1131 #define S_TXPKT_IPSEC 61
1132 #define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC)
1133 #define F_TXPKT_IPSEC V_TXPKT_IPSEC(1ULL)
1135 #define S_TXPKT_IPCSUM_DIS 62
1136 #define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)
1137 #define F_TXPKT_IPCSUM_DIS V_TXPKT_IPCSUM_DIS(1ULL)
1139 #define S_TXPKT_L4CSUM_DIS 63
1140 #define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
1141 #define F_TXPKT_L4CSUM_DIS V_TXPKT_L4CSUM_DIS(1ULL)
1143 struct cpl_tx_pkt_lso_core {
1147 __be32 seqno_offset;
1149 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1152 struct cpl_tx_pkt_lso {
1154 struct cpl_tx_pkt_lso_core c;
1155 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1158 struct cpl_tx_pkt_ufo_core {
1165 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1168 struct cpl_tx_pkt_ufo {
1170 struct cpl_tx_pkt_ufo_core c;
1171 /* encapsulated CPL (TX_PKT, TX_PKT_XT or TX_DATA) follows here */
1174 /* cpl_tx_pkt_lso_core.lso_ctrl fields */
1175 #define S_LSO_TCPHDR_LEN 0
1176 #define M_LSO_TCPHDR_LEN 0xF
1177 #define V_LSO_TCPHDR_LEN(x) ((x) << S_LSO_TCPHDR_LEN)
1178 #define G_LSO_TCPHDR_LEN(x) (((x) >> S_LSO_TCPHDR_LEN) & M_LSO_TCPHDR_LEN)
1180 #define S_LSO_IPHDR_LEN 4
1181 #define M_LSO_IPHDR_LEN 0xFFF
1182 #define V_LSO_IPHDR_LEN(x) ((x) << S_LSO_IPHDR_LEN)
1183 #define G_LSO_IPHDR_LEN(x) (((x) >> S_LSO_IPHDR_LEN) & M_LSO_IPHDR_LEN)
1185 #define S_LSO_ETHHDR_LEN 16
1186 #define M_LSO_ETHHDR_LEN 0xF
1187 #define V_LSO_ETHHDR_LEN(x) ((x) << S_LSO_ETHHDR_LEN)
1188 #define G_LSO_ETHHDR_LEN(x) (((x) >> S_LSO_ETHHDR_LEN) & M_LSO_ETHHDR_LEN)
1190 #define S_LSO_IPV6 20
1191 #define V_LSO_IPV6(x) ((x) << S_LSO_IPV6)
1192 #define F_LSO_IPV6 V_LSO_IPV6(1U)
1194 #define S_LSO_OFLD_ENCAP 21
1195 #define V_LSO_OFLD_ENCAP(x) ((x) << S_LSO_OFLD_ENCAP)
1196 #define F_LSO_OFLD_ENCAP V_LSO_OFLD_ENCAP(1U)
1198 #define S_LSO_LAST_SLICE 22
1199 #define V_LSO_LAST_SLICE(x) ((x) << S_LSO_LAST_SLICE)
1200 #define F_LSO_LAST_SLICE V_LSO_LAST_SLICE(1U)
1202 #define S_LSO_FIRST_SLICE 23
1203 #define V_LSO_FIRST_SLICE(x) ((x) << S_LSO_FIRST_SLICE)
1204 #define F_LSO_FIRST_SLICE V_LSO_FIRST_SLICE(1U)
1206 #define S_LSO_OPCODE 24
1207 #define M_LSO_OPCODE 0xFF
1208 #define V_LSO_OPCODE(x) ((x) << S_LSO_OPCODE)
1209 #define G_LSO_OPCODE(x) (((x) >> S_LSO_OPCODE) & M_LSO_OPCODE)
1211 /* cpl_tx_pkt_lso_core.mss fields */
1213 #define M_LSO_MSS 0x3FFF
1214 #define V_LSO_MSS(x) ((x) << S_LSO_MSS)
1215 #define G_LSO_MSS(x) (((x) >> S_LSO_MSS) & M_LSO_MSS)
1217 #define S_LSO_IPID_SPLIT 15
1218 #define V_LSO_IPID_SPLIT(x) ((x) << S_LSO_IPID_SPLIT)
1219 #define F_LSO_IPID_SPLIT V_LSO_IPID_SPLIT(1U)
1221 struct cpl_tx_pkt_fso {
1226 __be32 param_offset;
1228 /* encapsulated CPL (TX_PKT or TX_PKT_XT) follows here */
1231 /* cpl_tx_pkt_fso.fso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */
1232 #define S_FSO_XCHG_CLASS 21
1233 #define V_FSO_XCHG_CLASS(x) ((x) << S_FSO_XCHG_CLASS)
1234 #define F_FSO_XCHG_CLASS V_FSO_XCHG_CLASS(1U)
1236 #define S_FSO_INITIATOR 20
1237 #define V_FSO_INITIATOR(x) ((x) << S_FSO_INITIATOR)
1238 #define F_FSO_INITIATOR V_FSO_INITIATOR(1U)
1240 #define S_FSO_FCHDR_LEN 12
1241 #define M_FSO_FCHDR_LEN 0xF
1242 #define V_FSO_FCHDR_LEN(x) ((x) << S_FSO_FCHDR_LEN)
1243 #define G_FSO_FCHDR_LEN(x) (((x) >> S_FSO_FCHDR_LEN) & M_FSO_FCHDR_LEN)
1245 struct cpl_iscsi_hdr_no_rss {
1246 union opcode_tid ot;
1255 struct cpl_tx_data_iso {
1263 /* encapsulated CPL_TX_DATA follows here */
1266 /* cpl_tx_data_iso.iso_ctrl fields different from cpl_tx_pkt_lso.lso_ctrl */
1267 #define S_ISO_CPLHDR_LEN 18
1268 #define M_ISO_CPLHDR_LEN 0xF
1269 #define V_ISO_CPLHDR_LEN(x) ((x) << S_ISO_CPLHDR_LEN)
1270 #define G_ISO_CPLHDR_LEN(x) (((x) >> S_ISO_CPLHDR_LEN) & M_ISO_CPLHDR_LEN)
1272 #define S_ISO_HDR_CRC 17
1273 #define V_ISO_HDR_CRC(x) ((x) << S_ISO_HDR_CRC)
1274 #define F_ISO_HDR_CRC V_ISO_HDR_CRC(1U)
1276 #define S_ISO_DATA_CRC 16
1277 #define V_ISO_DATA_CRC(x) ((x) << S_ISO_DATA_CRC)
1278 #define F_ISO_DATA_CRC V_ISO_DATA_CRC(1U)
1280 #define S_ISO_IMD_DATA_EN 15
1281 #define V_ISO_IMD_DATA_EN(x) ((x) << S_ISO_IMD_DATA_EN)
1282 #define F_ISO_IMD_DATA_EN V_ISO_IMD_DATA_EN(1U)
1284 #define S_ISO_PDU_TYPE 13
1285 #define M_ISO_PDU_TYPE 0x3
1286 #define V_ISO_PDU_TYPE(x) ((x) << S_ISO_PDU_TYPE)
1287 #define G_ISO_PDU_TYPE(x) (((x) >> S_ISO_PDU_TYPE) & M_ISO_PDU_TYPE)
1289 struct cpl_iscsi_hdr {
1291 union opcode_tid ot;
1300 /* cpl_iscsi_hdr.pdu_len_ddp fields */
1301 #define S_ISCSI_PDU_LEN 0
1302 #define M_ISCSI_PDU_LEN 0x7FFF
1303 #define V_ISCSI_PDU_LEN(x) ((x) << S_ISCSI_PDU_LEN)
1304 #define G_ISCSI_PDU_LEN(x) (((x) >> S_ISCSI_PDU_LEN) & M_ISCSI_PDU_LEN)
1306 #define S_ISCSI_DDP 15
1307 #define V_ISCSI_DDP(x) ((x) << S_ISCSI_DDP)
1308 #define F_ISCSI_DDP V_ISCSI_DDP(1U)
1310 struct cpl_iscsi_data {
1312 union opcode_tid ot;
1321 struct cpl_rx_data {
1323 union opcode_tid ot;
1328 #if defined(__LITTLE_ENDIAN_BITFIELD)
1344 struct cpl_fcoe_hdr {
1346 union opcode_tid ot;
1360 struct cpl_fcoe_data {
1362 union opcode_tid ot;
1370 struct cpl_rx_urg_notify {
1372 union opcode_tid ot;
1376 struct cpl_rx_urg_pkt {
1378 union opcode_tid ot;
1383 struct cpl_rx_data_ack {
1385 union opcode_tid ot;
1389 struct cpl_rx_data_ack_core {
1390 union opcode_tid ot;
1394 /* cpl_rx_data_ack.ack_seq fields */
1395 #define S_RX_CREDITS 0
1396 #define M_RX_CREDITS 0x3FFFFFF
1397 #define V_RX_CREDITS(x) ((x) << S_RX_CREDITS)
1398 #define G_RX_CREDITS(x) (((x) >> S_RX_CREDITS) & M_RX_CREDITS)
1400 #define S_RX_MODULATE_TX 26
1401 #define V_RX_MODULATE_TX(x) ((x) << S_RX_MODULATE_TX)
1402 #define F_RX_MODULATE_TX V_RX_MODULATE_TX(1U)
1404 #define S_RX_MODULATE_RX 27
1405 #define V_RX_MODULATE_RX(x) ((x) << S_RX_MODULATE_RX)
1406 #define F_RX_MODULATE_RX V_RX_MODULATE_RX(1U)
1408 #define S_RX_FORCE_ACK 28
1409 #define V_RX_FORCE_ACK(x) ((x) << S_RX_FORCE_ACK)
1410 #define F_RX_FORCE_ACK V_RX_FORCE_ACK(1U)
1412 #define S_RX_DACK_MODE 29
1413 #define M_RX_DACK_MODE 0x3
1414 #define V_RX_DACK_MODE(x) ((x) << S_RX_DACK_MODE)
1415 #define G_RX_DACK_MODE(x) (((x) >> S_RX_DACK_MODE) & M_RX_DACK_MODE)
1417 #define S_RX_DACK_CHANGE 31
1418 #define V_RX_DACK_CHANGE(x) ((x) << S_RX_DACK_CHANGE)
1419 #define F_RX_DACK_CHANGE V_RX_DACK_CHANGE(1U)
1421 struct cpl_rx_ddp_complete {
1423 union opcode_tid ot;
1429 struct cpl_rx_data_ddp {
1431 union opcode_tid ot;
1443 #define cpl_rx_iscsi_ddp cpl_rx_data_ddp
1445 struct cpl_rx_fcoe_ddp {
1447 union opcode_tid ot;
1456 struct cpl_rx_data_dif {
1458 union opcode_tid ot;
1470 struct cpl_rx_iscsi_dif {
1472 union opcode_tid ot;
1487 struct cpl_rx_fcoe_dif {
1489 union opcode_tid ot;
1498 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddpvld fields */
1499 #define S_DDP_VALID 15
1500 #define M_DDP_VALID 0x1FFFF
1501 #define V_DDP_VALID(x) ((x) << S_DDP_VALID)
1502 #define G_DDP_VALID(x) (((x) >> S_DDP_VALID) & M_DDP_VALID)
1504 #define S_DDP_PPOD_MISMATCH 15
1505 #define V_DDP_PPOD_MISMATCH(x) ((x) << S_DDP_PPOD_MISMATCH)
1506 #define F_DDP_PPOD_MISMATCH V_DDP_PPOD_MISMATCH(1U)
1508 #define S_DDP_PDU 16
1509 #define V_DDP_PDU(x) ((x) << S_DDP_PDU)
1510 #define F_DDP_PDU V_DDP_PDU(1U)
1512 #define S_DDP_LLIMIT_ERR 17
1513 #define V_DDP_LLIMIT_ERR(x) ((x) << S_DDP_LLIMIT_ERR)
1514 #define F_DDP_LLIMIT_ERR V_DDP_LLIMIT_ERR(1U)
1516 #define S_DDP_PPOD_PARITY_ERR 18
1517 #define V_DDP_PPOD_PARITY_ERR(x) ((x) << S_DDP_PPOD_PARITY_ERR)
1518 #define F_DDP_PPOD_PARITY_ERR V_DDP_PPOD_PARITY_ERR(1U)
1520 #define S_DDP_PADDING_ERR 19
1521 #define V_DDP_PADDING_ERR(x) ((x) << S_DDP_PADDING_ERR)
1522 #define F_DDP_PADDING_ERR V_DDP_PADDING_ERR(1U)
1524 #define S_DDP_HDRCRC_ERR 20
1525 #define V_DDP_HDRCRC_ERR(x) ((x) << S_DDP_HDRCRC_ERR)
1526 #define F_DDP_HDRCRC_ERR V_DDP_HDRCRC_ERR(1U)
1528 #define S_DDP_DATACRC_ERR 21
1529 #define V_DDP_DATACRC_ERR(x) ((x) << S_DDP_DATACRC_ERR)
1530 #define F_DDP_DATACRC_ERR V_DDP_DATACRC_ERR(1U)
1532 #define S_DDP_INVALID_TAG 22
1533 #define V_DDP_INVALID_TAG(x) ((x) << S_DDP_INVALID_TAG)
1534 #define F_DDP_INVALID_TAG V_DDP_INVALID_TAG(1U)
1536 #define S_DDP_ULIMIT_ERR 23
1537 #define V_DDP_ULIMIT_ERR(x) ((x) << S_DDP_ULIMIT_ERR)
1538 #define F_DDP_ULIMIT_ERR V_DDP_ULIMIT_ERR(1U)
1540 #define S_DDP_OFFSET_ERR 24
1541 #define V_DDP_OFFSET_ERR(x) ((x) << S_DDP_OFFSET_ERR)
1542 #define F_DDP_OFFSET_ERR V_DDP_OFFSET_ERR(1U)
1544 #define S_DDP_COLOR_ERR 25
1545 #define V_DDP_COLOR_ERR(x) ((x) << S_DDP_COLOR_ERR)
1546 #define F_DDP_COLOR_ERR V_DDP_COLOR_ERR(1U)
1548 #define S_DDP_TID_MISMATCH 26
1549 #define V_DDP_TID_MISMATCH(x) ((x) << S_DDP_TID_MISMATCH)
1550 #define F_DDP_TID_MISMATCH V_DDP_TID_MISMATCH(1U)
1552 #define S_DDP_INVALID_PPOD 27
1553 #define V_DDP_INVALID_PPOD(x) ((x) << S_DDP_INVALID_PPOD)
1554 #define F_DDP_INVALID_PPOD V_DDP_INVALID_PPOD(1U)
1556 #define S_DDP_ULP_MODE 28
1557 #define M_DDP_ULP_MODE 0xF
1558 #define V_DDP_ULP_MODE(x) ((x) << S_DDP_ULP_MODE)
1559 #define G_DDP_ULP_MODE(x) (((x) >> S_DDP_ULP_MODE) & M_DDP_ULP_MODE)
1561 /* cpl_rx_{data,iscsi,fcoe}_{ddp,dif}.ddp_report fields */
1562 #define S_DDP_OFFSET 0
1563 #define M_DDP_OFFSET 0xFFFFFF
1564 #define V_DDP_OFFSET(x) ((x) << S_DDP_OFFSET)
1565 #define G_DDP_OFFSET(x) (((x) >> S_DDP_OFFSET) & M_DDP_OFFSET)
1567 #define S_DDP_DACK_MODE 24
1568 #define M_DDP_DACK_MODE 0x3
1569 #define V_DDP_DACK_MODE(x) ((x) << S_DDP_DACK_MODE)
1570 #define G_DDP_DACK_MODE(x) (((x) >> S_DDP_DACK_MODE) & M_DDP_DACK_MODE)
1572 #define S_DDP_BUF_IDX 26
1573 #define V_DDP_BUF_IDX(x) ((x) << S_DDP_BUF_IDX)
1574 #define F_DDP_BUF_IDX V_DDP_BUF_IDX(1U)
1576 #define S_DDP_URG 27
1577 #define V_DDP_URG(x) ((x) << S_DDP_URG)
1578 #define F_DDP_URG V_DDP_URG(1U)
1580 #define S_DDP_PSH 28
1581 #define V_DDP_PSH(x) ((x) << S_DDP_PSH)
1582 #define F_DDP_PSH V_DDP_PSH(1U)
1584 #define S_DDP_BUF_COMPLETE 29
1585 #define V_DDP_BUF_COMPLETE(x) ((x) << S_DDP_BUF_COMPLETE)
1586 #define F_DDP_BUF_COMPLETE V_DDP_BUF_COMPLETE(1U)
1588 #define S_DDP_BUF_TIMED_OUT 30
1589 #define V_DDP_BUF_TIMED_OUT(x) ((x) << S_DDP_BUF_TIMED_OUT)
1590 #define F_DDP_BUF_TIMED_OUT V_DDP_BUF_TIMED_OUT(1U)
1592 #define S_DDP_INV 31
1593 #define V_DDP_INV(x) ((x) << S_DDP_INV)
1594 #define F_DDP_INV V_DDP_INV(1U)
1599 #if defined(__LITTLE_ENDIAN_BITFIELD)
1620 /* rx_pkt.l2info fields */
1621 #define S_RX_ETHHDR_LEN 0
1622 #define M_RX_ETHHDR_LEN 0x1F
1623 #define V_RX_ETHHDR_LEN(x) ((x) << S_RX_ETHHDR_LEN)
1624 #define G_RX_ETHHDR_LEN(x) (((x) >> S_RX_ETHHDR_LEN) & M_RX_ETHHDR_LEN)
1626 #define S_RX_T5_ETHHDR_LEN 0
1627 #define M_RX_T5_ETHHDR_LEN 0x3F
1628 #define V_RX_T5_ETHHDR_LEN(x) ((x) << S_RX_T5_ETHHDR_LEN)
1629 #define G_RX_T5_ETHHDR_LEN(x) (((x) >> S_RX_T5_ETHHDR_LEN) & M_RX_T5_ETHHDR_LEN)
1631 #define S_RX_PKTYPE 5
1632 #define M_RX_PKTYPE 0x7
1633 #define V_RX_PKTYPE(x) ((x) << S_RX_PKTYPE)
1634 #define G_RX_PKTYPE(x) (((x) >> S_RX_PKTYPE) & M_RX_PKTYPE)
1636 #define S_RX_T5_DATYPE 6
1637 #define M_RX_T5_DATYPE 0x3
1638 #define V_RX_T5_DATYPE(x) ((x) << S_RX_T5_DATYPE)
1639 #define G_RX_T5_DATYPE(x) (((x) >> S_RX_T5_DATYPE) & M_RX_T5_DATYPE)
1641 #define S_RX_MACIDX 8
1642 #define M_RX_MACIDX 0x1FF
1643 #define V_RX_MACIDX(x) ((x) << S_RX_MACIDX)
1644 #define G_RX_MACIDX(x) (((x) >> S_RX_MACIDX) & M_RX_MACIDX)
1646 #define S_RX_T5_PKTYPE 17
1647 #define M_RX_T5_PKTYPE 0x7
1648 #define V_RX_T5_PKTYPE(x) ((x) << S_RX_T5_PKTYPE)
1649 #define G_RX_T5_PKTYPE(x) (((x) >> S_RX_T5_PKTYPE) & M_RX_T5_PKTYPE)
1651 #define S_RX_DATYPE 18
1652 #define M_RX_DATYPE 0x3
1653 #define V_RX_DATYPE(x) ((x) << S_RX_DATYPE)
1654 #define G_RX_DATYPE(x) (((x) >> S_RX_DATYPE) & M_RX_DATYPE)
1656 #define S_RXF_PSH 20
1657 #define V_RXF_PSH(x) ((x) << S_RXF_PSH)
1658 #define F_RXF_PSH V_RXF_PSH(1U)
1660 #define S_RXF_SYN 21
1661 #define V_RXF_SYN(x) ((x) << S_RXF_SYN)
1662 #define F_RXF_SYN V_RXF_SYN(1U)
1664 #define S_RXF_UDP 22
1665 #define V_RXF_UDP(x) ((x) << S_RXF_UDP)
1666 #define F_RXF_UDP V_RXF_UDP(1U)
1668 #define S_RXF_TCP 23
1669 #define V_RXF_TCP(x) ((x) << S_RXF_TCP)
1670 #define F_RXF_TCP V_RXF_TCP(1U)
1673 #define V_RXF_IP(x) ((x) << S_RXF_IP)
1674 #define F_RXF_IP V_RXF_IP(1U)
1676 #define S_RXF_IP6 25
1677 #define V_RXF_IP6(x) ((x) << S_RXF_IP6)
1678 #define F_RXF_IP6 V_RXF_IP6(1U)
1680 #define S_RXF_SYN_COOKIE 26
1681 #define V_RXF_SYN_COOKIE(x) ((x) << S_RXF_SYN_COOKIE)
1682 #define F_RXF_SYN_COOKIE V_RXF_SYN_COOKIE(1U)
1684 #define S_RXF_FCOE 26
1685 #define V_RXF_FCOE(x) ((x) << S_RXF_FCOE)
1686 #define F_RXF_FCOE V_RXF_FCOE(1U)
1688 #define S_RXF_LRO 27
1689 #define V_RXF_LRO(x) ((x) << S_RXF_LRO)
1690 #define F_RXF_LRO V_RXF_LRO(1U)
1692 #define S_RX_CHAN 28
1693 #define M_RX_CHAN 0xF
1694 #define V_RX_CHAN(x) ((x) << S_RX_CHAN)
1695 #define G_RX_CHAN(x) (((x) >> S_RX_CHAN) & M_RX_CHAN)
1697 /* rx_pkt.hdr_len fields */
1698 #define S_RX_TCPHDR_LEN 0
1699 #define M_RX_TCPHDR_LEN 0x3F
1700 #define V_RX_TCPHDR_LEN(x) ((x) << S_RX_TCPHDR_LEN)
1701 #define G_RX_TCPHDR_LEN(x) (((x) >> S_RX_TCPHDR_LEN) & M_RX_TCPHDR_LEN)
1703 #define S_RX_IPHDR_LEN 6
1704 #define M_RX_IPHDR_LEN 0x3FF
1705 #define V_RX_IPHDR_LEN(x) ((x) << S_RX_IPHDR_LEN)
1706 #define G_RX_IPHDR_LEN(x) (((x) >> S_RX_IPHDR_LEN) & M_RX_IPHDR_LEN)
1708 /* rx_pkt.err_vec fields */
1709 #define S_RXERR_OR 0
1710 #define V_RXERR_OR(x) ((x) << S_RXERR_OR)
1711 #define F_RXERR_OR V_RXERR_OR(1U)
1713 #define S_RXERR_MAC 1
1714 #define V_RXERR_MAC(x) ((x) << S_RXERR_MAC)
1715 #define F_RXERR_MAC V_RXERR_MAC(1U)
1717 #define S_RXERR_IPVERS 2
1718 #define V_RXERR_IPVERS(x) ((x) << S_RXERR_IPVERS)
1719 #define F_RXERR_IPVERS V_RXERR_IPVERS(1U)
1721 #define S_RXERR_FRAG 3
1722 #define V_RXERR_FRAG(x) ((x) << S_RXERR_FRAG)
1723 #define F_RXERR_FRAG V_RXERR_FRAG(1U)
1725 #define S_RXERR_ATTACK 4
1726 #define V_RXERR_ATTACK(x) ((x) << S_RXERR_ATTACK)
1727 #define F_RXERR_ATTACK V_RXERR_ATTACK(1U)
1729 #define S_RXERR_ETHHDR_LEN 5
1730 #define V_RXERR_ETHHDR_LEN(x) ((x) << S_RXERR_ETHHDR_LEN)
1731 #define F_RXERR_ETHHDR_LEN V_RXERR_ETHHDR_LEN(1U)
1733 #define S_RXERR_IPHDR_LEN 6
1734 #define V_RXERR_IPHDR_LEN(x) ((x) << S_RXERR_IPHDR_LEN)
1735 #define F_RXERR_IPHDR_LEN V_RXERR_IPHDR_LEN(1U)
1737 #define S_RXERR_TCPHDR_LEN 7
1738 #define V_RXERR_TCPHDR_LEN(x) ((x) << S_RXERR_TCPHDR_LEN)
1739 #define F_RXERR_TCPHDR_LEN V_RXERR_TCPHDR_LEN(1U)
1741 #define S_RXERR_PKT_LEN 8
1742 #define V_RXERR_PKT_LEN(x) ((x) << S_RXERR_PKT_LEN)
1743 #define F_RXERR_PKT_LEN V_RXERR_PKT_LEN(1U)
1745 #define S_RXERR_TCP_OPT 9
1746 #define V_RXERR_TCP_OPT(x) ((x) << S_RXERR_TCP_OPT)
1747 #define F_RXERR_TCP_OPT V_RXERR_TCP_OPT(1U)
1749 #define S_RXERR_IPCSUM 12
1750 #define V_RXERR_IPCSUM(x) ((x) << S_RXERR_IPCSUM)
1751 #define F_RXERR_IPCSUM V_RXERR_IPCSUM(1U)
1753 #define S_RXERR_CSUM 13
1754 #define V_RXERR_CSUM(x) ((x) << S_RXERR_CSUM)
1755 #define F_RXERR_CSUM V_RXERR_CSUM(1U)
1757 #define S_RXERR_PING 14
1758 #define V_RXERR_PING(x) ((x) << S_RXERR_PING)
1759 #define F_RXERR_PING V_RXERR_PING(1U)
1761 struct cpl_trace_pkt {
1765 #if defined(__LITTLE_ENDIAN_BITFIELD)
1783 struct cpl_t5_trace_pkt {
1787 #if defined(__LITTLE_ENDIAN_BITFIELD)
1806 struct cpl_rte_delete_req {
1808 union opcode_tid ot;
1812 /* {cpl_rte_delete_req, cpl_rte_read_req}.params fields */
1813 #define S_RTE_REQ_LUT_IX 8
1814 #define M_RTE_REQ_LUT_IX 0x7FF
1815 #define V_RTE_REQ_LUT_IX(x) ((x) << S_RTE_REQ_LUT_IX)
1816 #define G_RTE_REQ_LUT_IX(x) (((x) >> S_RTE_REQ_LUT_IX) & M_RTE_REQ_LUT_IX)
1818 #define S_RTE_REQ_LUT_BASE 19
1819 #define M_RTE_REQ_LUT_BASE 0x7FF
1820 #define V_RTE_REQ_LUT_BASE(x) ((x) << S_RTE_REQ_LUT_BASE)
1821 #define G_RTE_REQ_LUT_BASE(x) (((x) >> S_RTE_REQ_LUT_BASE) & M_RTE_REQ_LUT_BASE)
1823 #define S_RTE_READ_REQ_SELECT 31
1824 #define V_RTE_READ_REQ_SELECT(x) ((x) << S_RTE_READ_REQ_SELECT)
1825 #define F_RTE_READ_REQ_SELECT V_RTE_READ_REQ_SELECT(1U)
1827 struct cpl_rte_delete_rpl {
1829 union opcode_tid ot;
1834 struct cpl_rte_write_req {
1836 union opcode_tid ot;
1844 /* cpl_rte_write_req.write_sel fields */
1845 #define S_RTE_WR_L2TIDX 31
1846 #define V_RTE_WR_L2TIDX(x) ((x) << S_RTE_WR_L2TIDX)
1847 #define F_RTE_WR_L2TIDX V_RTE_WR_L2TIDX(1U)
1849 #define S_RTE_WR_FADDR 30
1850 #define V_RTE_WR_FADDR(x) ((x) << S_RTE_WR_FADDR)
1851 #define F_RTE_WR_FADDR V_RTE_WR_FADDR(1U)
1853 /* cpl_rte_write_req.lut_params fields */
1854 #define S_RTE_WR_LUT_IX 10
1855 #define M_RTE_WR_LUT_IX 0x7FF
1856 #define V_RTE_WR_LUT_IX(x) ((x) << S_RTE_WR_LUT_IX)
1857 #define G_RTE_WR_LUT_IX(x) (((x) >> S_RTE_WR_LUT_IX) & M_RTE_WR_LUT_IX)
1859 #define S_RTE_WR_LUT_BASE 21
1860 #define M_RTE_WR_LUT_BASE 0x7FF
1861 #define V_RTE_WR_LUT_BASE(x) ((x) << S_RTE_WR_LUT_BASE)
1862 #define G_RTE_WR_LUT_BASE(x) (((x) >> S_RTE_WR_LUT_BASE) & M_RTE_WR_LUT_BASE)
1864 struct cpl_rte_write_rpl {
1866 union opcode_tid ot;
1871 struct cpl_rte_read_req {
1873 union opcode_tid ot;
1877 struct cpl_rte_read_rpl {
1879 union opcode_tid ot;
1883 #if defined(__LITTLE_ENDIAN_BITFIELD)
1893 struct cpl_l2t_write_req {
1895 union opcode_tid ot;
1902 /* cpl_l2t_write_req.params fields */
1903 #define S_L2T_W_INFO 2
1904 #define M_L2T_W_INFO 0x3F
1905 #define V_L2T_W_INFO(x) ((x) << S_L2T_W_INFO)
1906 #define G_L2T_W_INFO(x) (((x) >> S_L2T_W_INFO) & M_L2T_W_INFO)
1908 #define S_L2T_W_PORT 8
1909 #define M_L2T_W_PORT 0xF
1910 #define V_L2T_W_PORT(x) ((x) << S_L2T_W_PORT)
1911 #define G_L2T_W_PORT(x) (((x) >> S_L2T_W_PORT) & M_L2T_W_PORT)
1913 #define S_L2T_W_NOREPLY 15
1914 #define V_L2T_W_NOREPLY(x) ((x) << S_L2T_W_NOREPLY)
1915 #define F_L2T_W_NOREPLY V_L2T_W_NOREPLY(1U)
1917 struct cpl_l2t_write_rpl {
1919 union opcode_tid ot;
1924 struct cpl_l2t_read_req {
1926 union opcode_tid ot;
1930 struct cpl_l2t_read_rpl {
1932 union opcode_tid ot;
1934 #if defined(__LITTLE_ENDIAN_BITFIELD)
1946 struct cpl_smt_write_req {
1948 union opcode_tid ot;
1956 struct cpl_smt_write_rpl {
1958 union opcode_tid ot;
1963 struct cpl_smt_read_req {
1965 union opcode_tid ot;
1969 struct cpl_smt_read_rpl {
1971 union opcode_tid ot;
1981 /* cpl_smt_{read,write}_req.params fields */
1982 #define S_SMTW_OVLAN_IDX 16
1983 #define M_SMTW_OVLAN_IDX 0xF
1984 #define V_SMTW_OVLAN_IDX(x) ((x) << S_SMTW_OVLAN_IDX)
1985 #define G_SMTW_OVLAN_IDX(x) (((x) >> S_SMTW_OVLAN_IDX) & M_SMTW_OVLAN_IDX)
1987 #define S_SMTW_IDX 20
1988 #define M_SMTW_IDX 0x7F
1989 #define V_SMTW_IDX(x) ((x) << S_SMTW_IDX)
1990 #define G_SMTW_IDX(x) (((x) >> S_SMTW_IDX) & M_SMTW_IDX)
1992 #define S_SMTW_NORPL 31
1993 #define V_SMTW_NORPL(x) ((x) << S_SMTW_NORPL)
1994 #define F_SMTW_NORPL V_SMTW_NORPL(1U)
1996 /* cpl_smt_{read,write}_req.pfvf? fields */
1998 #define M_SMTW_VF 0xFF
1999 #define V_SMTW_VF(x) ((x) << S_SMTW_VF)
2000 #define G_SMTW_VF(x) (((x) >> S_SMTW_VF) & M_SMTW_VF)
2003 #define M_SMTW_PF 0x7
2004 #define V_SMTW_PF(x) ((x) << S_SMTW_PF)
2005 #define G_SMTW_PF(x) (((x) >> S_SMTW_PF) & M_SMTW_PF)
2007 #define S_SMTW_VF_VLD 11
2008 #define V_SMTW_VF_VLD(x) ((x) << S_SMTW_VF_VLD)
2009 #define F_SMTW_VF_VLD V_SMTW_VF_VLD(1U)
2011 struct cpl_tag_write_req {
2013 union opcode_tid ot;
2018 struct cpl_tag_write_rpl {
2020 union opcode_tid ot;
2026 struct cpl_tag_read_req {
2028 union opcode_tid ot;
2032 struct cpl_tag_read_rpl {
2034 union opcode_tid ot;
2036 #if defined(__LITTLE_ENDIAN_BITFIELD)
2052 /* cpl_tag{read,write}_req.params fields */
2053 #define S_TAGW_IDX 0
2054 #define M_TAGW_IDX 0x7F
2055 #define V_TAGW_IDX(x) ((x) << S_TAGW_IDX)
2056 #define G_TAGW_IDX(x) (((x) >> S_TAGW_IDX) & M_TAGW_IDX)
2058 #define S_TAGW_LEN 20
2059 #define V_TAGW_LEN(x) ((x) << S_TAGW_LEN)
2060 #define F_TAGW_LEN V_TAGW_LEN(1U)
2062 #define S_TAGW_INS_ENABLE 23
2063 #define V_TAGW_INS_ENABLE(x) ((x) << S_TAGW_INS_ENABLE)
2064 #define F_TAGW_INS_ENABLE V_TAGW_INS_ENABLE(1U)
2066 #define S_TAGW_NORPL 31
2067 #define V_TAGW_NORPL(x) ((x) << S_TAGW_NORPL)
2068 #define F_TAGW_NORPL V_TAGW_NORPL(1U)
2070 struct cpl_barrier {
2078 /* cpl_barrier.chan_map fields */
2079 #define S_CHAN_MAP 4
2080 #define M_CHAN_MAP 0xF
2081 #define V_CHAN_MAP(x) ((x) << S_CHAN_MAP)
2082 #define G_CHAN_MAP(x) (((x) >> S_CHAN_MAP) & M_CHAN_MAP)
2086 union opcode_tid ot;
2090 struct cpl_hit_notify {
2092 union opcode_tid ot;
2098 struct cpl_pkt_notify {
2100 union opcode_tid ot;
2107 /* cpl_{hit,pkt}_notify.info fields */
2108 #define S_NTFY_MAC_IDX 0
2109 #define M_NTFY_MAC_IDX 0x1FF
2110 #define V_NTFY_MAC_IDX(x) ((x) << S_NTFY_MAC_IDX)
2111 #define G_NTFY_MAC_IDX(x) (((x) >> S_NTFY_MAC_IDX) & M_NTFY_MAC_IDX)
2113 #define S_NTFY_INTF 10
2114 #define M_NTFY_INTF 0xF
2115 #define V_NTFY_INTF(x) ((x) << S_NTFY_INTF)
2116 #define G_NTFY_INTF(x) (((x) >> S_NTFY_INTF) & M_NTFY_INTF)
2118 #define S_NTFY_TCPHDR_LEN 14
2119 #define M_NTFY_TCPHDR_LEN 0xF
2120 #define V_NTFY_TCPHDR_LEN(x) ((x) << S_NTFY_TCPHDR_LEN)
2121 #define G_NTFY_TCPHDR_LEN(x) (((x) >> S_NTFY_TCPHDR_LEN) & M_NTFY_TCPHDR_LEN)
2123 #define S_NTFY_IPHDR_LEN 18
2124 #define M_NTFY_IPHDR_LEN 0x1FF
2125 #define V_NTFY_IPHDR_LEN(x) ((x) << S_NTFY_IPHDR_LEN)
2126 #define G_NTFY_IPHDR_LEN(x) (((x) >> S_NTFY_IPHDR_LEN) & M_NTFY_IPHDR_LEN)
2128 #define S_NTFY_ETHHDR_LEN 27
2129 #define M_NTFY_ETHHDR_LEN 0x1F
2130 #define V_NTFY_ETHHDR_LEN(x) ((x) << S_NTFY_ETHHDR_LEN)
2131 #define G_NTFY_ETHHDR_LEN(x) (((x) >> S_NTFY_ETHHDR_LEN) & M_NTFY_ETHHDR_LEN)
2133 #define S_NTFY_T5_IPHDR_LEN 18
2134 #define M_NTFY_T5_IPHDR_LEN 0xFF
2135 #define V_NTFY_T5_IPHDR_LEN(x) ((x) << S_NTFY_T5_IPHDR_LEN)
2136 #define G_NTFY_T5_IPHDR_LEN(x) (((x) >> S_NTFY_T5_IPHDR_LEN) & M_NTFY_T5_IPHDR_LEN)
2138 #define S_NTFY_T5_ETHHDR_LEN 26
2139 #define M_NTFY_T5_ETHHDR_LEN 0x3F
2140 #define V_NTFY_T5_ETHHDR_LEN(x) ((x) << S_NTFY_T5_ETHHDR_LEN)
2141 #define G_NTFY_T5_ETHHDR_LEN(x) (((x) >> S_NTFY_T5_ETHHDR_LEN) & M_NTFY_T5_ETHHDR_LEN)
2143 struct cpl_rdma_terminate {
2145 union opcode_tid ot;
2150 struct cpl_set_le_req {
2152 union opcode_tid ot;
2161 /* cpl_set_le_req.reply_ctrl additional fields */
2162 #define S_LE_REQ_IP6 13
2163 #define V_LE_REQ_IP6(x) ((x) << S_LE_REQ_IP6)
2164 #define F_LE_REQ_IP6 V_LE_REQ_IP6(1U)
2166 /* cpl_set_le_req.params fields */
2168 #define M_LE_CHAN 0x3
2169 #define V_LE_CHAN(x) ((x) << S_LE_CHAN)
2170 #define G_LE_CHAN(x) (((x) >> S_LE_CHAN) & M_LE_CHAN)
2172 #define S_LE_OFFSET 5
2173 #define M_LE_OFFSET 0x7
2174 #define V_LE_OFFSET(x) ((x) << S_LE_OFFSET)
2175 #define G_LE_OFFSET(x) (((x) >> S_LE_OFFSET) & M_LE_OFFSET)
2178 #define V_LE_MORE(x) ((x) << S_LE_MORE)
2179 #define F_LE_MORE V_LE_MORE(1U)
2181 #define S_LE_REQSIZE 9
2182 #define M_LE_REQSIZE 0x7
2183 #define V_LE_REQSIZE(x) ((x) << S_LE_REQSIZE)
2184 #define G_LE_REQSIZE(x) (((x) >> S_LE_REQSIZE) & M_LE_REQSIZE)
2186 #define S_LE_REQCMD 12
2187 #define M_LE_REQCMD 0xF
2188 #define V_LE_REQCMD(x) ((x) << S_LE_REQCMD)
2189 #define G_LE_REQCMD(x) (((x) >> S_LE_REQCMD) & M_LE_REQCMD)
2191 struct cpl_set_le_rpl {
2193 union opcode_tid ot;
2199 /* cpl_set_le_rpl.info fields */
2200 #define S_LE_RSPCMD 0
2201 #define M_LE_RSPCMD 0xF
2202 #define V_LE_RSPCMD(x) ((x) << S_LE_RSPCMD)
2203 #define G_LE_RSPCMD(x) (((x) >> S_LE_RSPCMD) & M_LE_RSPCMD)
2205 #define S_LE_RSPSIZE 4
2206 #define M_LE_RSPSIZE 0x7
2207 #define V_LE_RSPSIZE(x) ((x) << S_LE_RSPSIZE)
2208 #define G_LE_RSPSIZE(x) (((x) >> S_LE_RSPSIZE) & M_LE_RSPSIZE)
2210 #define S_LE_RSPTYPE 7
2211 #define V_LE_RSPTYPE(x) ((x) << S_LE_RSPTYPE)
2212 #define F_LE_RSPTYPE V_LE_RSPTYPE(1U)
2214 struct cpl_sge_egr_update {
2221 /* cpl_sge_egr_update.ot fields */
2223 #define M_EGR_QID 0x1FFFF
2224 #define V_EGR_QID(x) ((x) << S_EGR_QID)
2225 #define G_EGR_QID(x) (((x) >> S_EGR_QID) & M_EGR_QID)
2227 /* cpl_fw*.type values */
2229 FW_TYPE_CMD_RPL = 0,
2232 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
2236 struct cpl_fw2_pld {
2243 struct cpl_fw4_pld {
2254 struct cpl_fw6_pld {
2262 struct cpl_fw2_msg {
2264 union opcode_info oi;
2267 struct cpl_fw4_msg {
2276 struct cpl_fw4_ack {
2278 union opcode_tid ot;
2288 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1, /* seqn valid */
2289 CPL_FW4_ACK_FLAGS_CH = 0x2, /* channel change complete */
2290 CPL_FW4_ACK_FLAGS_FLOWC = 0x4, /* fw_flowc_wr complete */
2293 struct cpl_fw6_msg {
2302 /* cpl_fw6_msg.type values */
2304 FW6_TYPE_CMD_RPL = FW_TYPE_CMD_RPL,
2305 FW6_TYPE_WR_RPL = FW_TYPE_WR_RPL,
2306 FW6_TYPE_CQE = FW_TYPE_CQE,
2307 FW6_TYPE_OFLD_CONNECTION_WR_RPL = FW_TYPE_OFLD_CONNECTION_WR_RPL,
2308 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
2313 struct cpl_fw6_msg_ofld_connection_wr_rpl {
2315 __be32 tid; /* or atid in case of active failure */
2321 /* ULP_TX opcodes */
2323 ULP_TX_MEM_READ = 2,
2324 ULP_TX_MEM_WRITE = 3,
2329 ULP_TX_SC_NOOP = 0x80,
2330 ULP_TX_SC_IMM = 0x81,
2331 ULP_TX_SC_DSGL = 0x82,
2332 ULP_TX_SC_ISGL = 0x83
2335 #define S_ULPTX_CMD 24
2336 #define M_ULPTX_CMD 0xFF
2337 #define V_ULPTX_CMD(x) ((x) << S_ULPTX_CMD)
2339 #define S_ULPTX_LEN16 0
2340 #define M_ULPTX_LEN16 0xFF
2341 #define V_ULPTX_LEN16(x) ((x) << S_ULPTX_LEN16)
2343 #define S_ULP_TX_SC_MORE 23
2344 #define V_ULP_TX_SC_MORE(x) ((x) << S_ULP_TX_SC_MORE)
2345 #define F_ULP_TX_SC_MORE V_ULP_TX_SC_MORE(1U)
2347 struct ulptx_sge_pair {
2356 #if !(defined C99_NOT_SUPPORTED)
2357 struct ulptx_sge_pair sge[0];
2370 #if !(defined C99_NOT_SUPPORTED)
2371 struct ulptx_isge sge[0];
2375 struct ulptx_idata {
2380 #define S_ULPTX_NSGE 0
2381 #define M_ULPTX_NSGE 0xFFFF
2382 #define V_ULPTX_NSGE(x) ((x) << S_ULPTX_NSGE)
2387 __be32 len16; /* command length */
2388 __be32 dlen; /* data length in 32-byte units */
2392 /* additional ulp_mem_io.cmd fields */
2393 #define S_ULP_MEMIO_ORDER 23
2394 #define V_ULP_MEMIO_ORDER(x) ((x) << S_ULP_MEMIO_ORDER)
2395 #define F_ULP_MEMIO_ORDER V_ULP_MEMIO_ORDER(1U)
2397 /* ulp_mem_io.lock_addr fields */
2398 #define S_ULP_MEMIO_ADDR 0
2399 #define M_ULP_MEMIO_ADDR 0x7FFFFFF
2400 #define V_ULP_MEMIO_ADDR(x) ((x) << S_ULP_MEMIO_ADDR)
2402 #define S_ULP_MEMIO_LOCK 31
2403 #define V_ULP_MEMIO_LOCK(x) ((x) << S_ULP_MEMIO_LOCK)
2404 #define F_ULP_MEMIO_LOCK V_ULP_MEMIO_LOCK(1U)
2406 /* ulp_mem_io.dlen fields */
2407 #define S_ULP_MEMIO_DATA_LEN 0
2408 #define M_ULP_MEMIO_DATA_LEN 0x1F
2409 #define V_ULP_MEMIO_DATA_LEN(x) ((x) << S_ULP_MEMIO_DATA_LEN)
2416 /* ulp_txpkt.cmd_dest fields */
2417 #define S_ULP_TXPKT_DEST 16
2418 #define M_ULP_TXPKT_DEST 0x3
2419 #define V_ULP_TXPKT_DEST(x) ((x) << S_ULP_TXPKT_DEST)
2421 #define S_ULP_TXPKT_FID 4
2422 #define M_ULP_TXPKT_FID 0x7ff
2423 #define V_ULP_TXPKT_FID(x) ((x) << S_ULP_TXPKT_FID)
2425 #define S_ULP_TXPKT_RO 3
2426 #define V_ULP_TXPKT_RO(x) ((x) << S_ULP_TXPKT_RO)
2427 #define F_ULP_TXPKT_RO V_ULP_TXPKT_RO(1U)
2429 #endif /* T4_MSG_H */