2 * Copyright (c) 2013 Chelsio Communications, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 /* This file is automatically generated --- changes will be lost */
32 #define MYPF_BASE 0x1b000
33 #define MYPF_REG(reg_addr) (MYPF_BASE + (reg_addr))
35 #define PF0_BASE 0x1e000
36 #define PF0_REG(reg_addr) (PF0_BASE + (reg_addr))
38 #define PF1_BASE 0x1e400
39 #define PF1_REG(reg_addr) (PF1_BASE + (reg_addr))
41 #define PF2_BASE 0x1e800
42 #define PF2_REG(reg_addr) (PF2_BASE + (reg_addr))
44 #define PF3_BASE 0x1ec00
45 #define PF3_REG(reg_addr) (PF3_BASE + (reg_addr))
47 #define PF4_BASE 0x1f000
48 #define PF4_REG(reg_addr) (PF4_BASE + (reg_addr))
50 #define PF5_BASE 0x1f400
51 #define PF5_REG(reg_addr) (PF5_BASE + (reg_addr))
53 #define PF6_BASE 0x1f800
54 #define PF6_REG(reg_addr) (PF6_BASE + (reg_addr))
56 #define PF7_BASE 0x1fc00
57 #define PF7_REG(reg_addr) (PF7_BASE + (reg_addr))
59 #define PF_STRIDE 0x400
60 #define PF_BASE(idx) (PF0_BASE + (idx) * PF_STRIDE)
61 #define PF_REG(idx, reg) (PF_BASE(idx) + (reg))
63 #define VF_SGE_BASE 0x0
64 #define VF_SGE_REG(reg_addr) (VF_SGE_BASE + (reg_addr))
66 #define VF_MPS_BASE 0x100
67 #define VF_MPS_REG(reg_addr) (VF_MPS_BASE + (reg_addr))
69 #define VF_PL_BASE 0x200
70 #define VF_PL_REG(reg_addr) (VF_PL_BASE + (reg_addr))
72 #define VF_MBDATA_BASE 0x240
73 #define VF_MBDATA_REG(reg_addr) (VF_MBDATA_BASE + (reg_addr))
75 #define VF_CIM_BASE 0x300
76 #define VF_CIM_REG(reg_addr) (VF_CIM_BASE + (reg_addr))
78 #define MYPORT_BASE 0x1c000
79 #define MYPORT_REG(reg_addr) (MYPORT_BASE + (reg_addr))
81 #define PORT0_BASE 0x20000
82 #define PORT0_REG(reg_addr) (PORT0_BASE + (reg_addr))
84 #define PORT1_BASE 0x22000
85 #define PORT1_REG(reg_addr) (PORT1_BASE + (reg_addr))
87 #define PORT2_BASE 0x24000
88 #define PORT2_REG(reg_addr) (PORT2_BASE + (reg_addr))
90 #define PORT3_BASE 0x26000
91 #define PORT3_REG(reg_addr) (PORT3_BASE + (reg_addr))
93 #define PORT_STRIDE 0x2000
94 #define PORT_BASE(idx) (PORT0_BASE + (idx) * PORT_STRIDE)
95 #define PORT_REG(idx, reg) (PORT_BASE(idx) + (reg))
97 #define SGE_QUEUE_BASE_MAP_HIGH(idx) (A_SGE_QUEUE_BASE_MAP_HIGH + (idx) * 8)
98 #define NUM_SGE_QUEUE_BASE_MAP_HIGH_INSTANCES 136
100 #define SGE_QUEUE_BASE_MAP_LOW(idx) (A_SGE_QUEUE_BASE_MAP_LOW + (idx) * 8)
101 #define NUM_SGE_QUEUE_BASE_MAP_LOW_INSTANCES 136
103 #define PCIE_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
104 #define NUM_PCIE_DMA_INSTANCES 4
106 #define PCIE_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
107 #define NUM_PCIE_CMD_INSTANCES 2
109 #define PCIE_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
110 #define NUM_PCIE_HMA_INSTANCES 1
112 #define PCIE_MEM_ACCESS_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
113 #define NUM_PCIE_MEM_ACCESS_INSTANCES 8
115 #define PCIE_MAILBOX_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
116 #define NUM_PCIE_MAILBOX_INSTANCES 1
118 #define PCIE_FW_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
119 #define NUM_PCIE_FW_INSTANCES 8
121 #define PCIE_FUNC_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
122 #define NUM_PCIE_FUNC_INSTANCES 256
124 #define PCIE_FID(idx) (A_PCIE_FID + (idx) * 4)
125 #define NUM_PCIE_FID_INSTANCES 2048
127 #define PCIE_DMA_BUF_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
128 #define NUM_PCIE_DMA_BUF_INSTANCES 4
130 #define MC_DDR3PHYDATX8_REG(reg_addr, idx) ((reg_addr) + (idx) * 256)
131 #define NUM_MC_DDR3PHYDATX8_INSTANCES 9
133 #define MC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
134 #define NUM_MC_BIST_STATUS_INSTANCES 18
136 #define EDC_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
137 #define NUM_EDC_BIST_STATUS_INSTANCES 18
139 #define CIM_PF_MAILBOX_DATA(idx) (A_CIM_PF_MAILBOX_DATA + (idx) * 4)
140 #define NUM_CIM_PF_MAILBOX_DATA_INSTANCES 16
142 #define MPS_TRC_FILTER_MATCH_CTL_A(idx) (A_MPS_TRC_FILTER_MATCH_CTL_A + (idx) * 4)
143 #define NUM_MPS_TRC_FILTER_MATCH_CTL_A_INSTANCES 4
145 #define MPS_TRC_FILTER_MATCH_CTL_B(idx) (A_MPS_TRC_FILTER_MATCH_CTL_B + (idx) * 4)
146 #define NUM_MPS_TRC_FILTER_MATCH_CTL_B_INSTANCES 4
148 #define MPS_TRC_FILTER_RUNT_CTL(idx) (A_MPS_TRC_FILTER_RUNT_CTL + (idx) * 4)
149 #define NUM_MPS_TRC_FILTER_RUNT_CTL_INSTANCES 4
151 #define MPS_TRC_FILTER_DROP(idx) (A_MPS_TRC_FILTER_DROP + (idx) * 4)
152 #define NUM_MPS_TRC_FILTER_DROP_INSTANCES 4
154 #define MPS_TRC_FILTER0_MATCH(idx) (A_MPS_TRC_FILTER0_MATCH + (idx) * 4)
155 #define NUM_MPS_TRC_FILTER0_MATCH_INSTANCES 28
157 #define MPS_TRC_FILTER0_DONT_CARE(idx) (A_MPS_TRC_FILTER0_DONT_CARE + (idx) * 4)
158 #define NUM_MPS_TRC_FILTER0_DONT_CARE_INSTANCES 28
160 #define MPS_TRC_FILTER1_MATCH(idx) (A_MPS_TRC_FILTER1_MATCH + (idx) * 4)
161 #define NUM_MPS_TRC_FILTER1_MATCH_INSTANCES 28
163 #define MPS_TRC_FILTER1_DONT_CARE(idx) (A_MPS_TRC_FILTER1_DONT_CARE + (idx) * 4)
164 #define NUM_MPS_TRC_FILTER1_DONT_CARE_INSTANCES 28
166 #define MPS_TRC_FILTER2_MATCH(idx) (A_MPS_TRC_FILTER2_MATCH + (idx) * 4)
167 #define NUM_MPS_TRC_FILTER2_MATCH_INSTANCES 28
169 #define MPS_TRC_FILTER2_DONT_CARE(idx) (A_MPS_TRC_FILTER2_DONT_CARE + (idx) * 4)
170 #define NUM_MPS_TRC_FILTER2_DONT_CARE_INSTANCES 28
172 #define MPS_TRC_FILTER3_MATCH(idx) (A_MPS_TRC_FILTER3_MATCH + (idx) * 4)
173 #define NUM_MPS_TRC_FILTER3_MATCH_INSTANCES 28
175 #define MPS_TRC_FILTER3_DONT_CARE(idx) (A_MPS_TRC_FILTER3_DONT_CARE + (idx) * 4)
176 #define NUM_MPS_TRC_FILTER3_DONT_CARE_INSTANCES 28
178 #define MPS_PORT_CLS_HASH_SRAM(idx) (A_MPS_PORT_CLS_HASH_SRAM + (idx) * 4)
179 #define NUM_MPS_PORT_CLS_HASH_SRAM_INSTANCES 65
181 #define MPS_CLS_VLAN_TABLE(idx) (A_MPS_CLS_VLAN_TABLE + (idx) * 4)
182 #define NUM_MPS_CLS_VLAN_TABLE_INSTANCES 9
184 #define MPS_CLS_SRAM_L(idx) (A_MPS_CLS_SRAM_L + (idx) * 8)
185 #define NUM_MPS_CLS_SRAM_L_INSTANCES 336
187 #define MPS_CLS_SRAM_H(idx) (A_MPS_CLS_SRAM_H + (idx) * 8)
188 #define NUM_MPS_CLS_SRAM_H_INSTANCES 336
190 #define MPS_CLS_TCAM_Y_L(idx) (A_MPS_CLS_TCAM_Y_L + (idx) * 16)
191 #define NUM_MPS_CLS_TCAM_Y_L_INSTANCES 512
193 #define MPS_CLS_TCAM_Y_H(idx) (A_MPS_CLS_TCAM_Y_H + (idx) * 16)
194 #define NUM_MPS_CLS_TCAM_Y_H_INSTANCES 512
196 #define MPS_CLS_TCAM_X_L(idx) (A_MPS_CLS_TCAM_X_L + (idx) * 16)
197 #define NUM_MPS_CLS_TCAM_X_L_INSTANCES 512
199 #define MPS_CLS_TCAM_X_H(idx) (A_MPS_CLS_TCAM_X_H + (idx) * 16)
200 #define NUM_MPS_CLS_TCAM_X_H_INSTANCES 512
202 #define PL_SEMAPHORE_LOCK(idx) (A_PL_SEMAPHORE_LOCK + (idx) * 4)
203 #define NUM_PL_SEMAPHORE_LOCK_INSTANCES 8
205 #define PL_VF_SLICE_L(idx) (A_PL_VF_SLICE_L + (idx) * 8)
206 #define NUM_PL_VF_SLICE_L_INSTANCES 8
208 #define PL_VF_SLICE_H(idx) (A_PL_VF_SLICE_H + (idx) * 8)
209 #define NUM_PL_VF_SLICE_H_INSTANCES 8
211 #define PL_FLR_VF_STATUS(idx) (A_PL_FLR_VF_STATUS + (idx) * 4)
212 #define NUM_PL_FLR_VF_STATUS_INSTANCES 4
214 #define PL_VFID_MAP(idx) (A_PL_VFID_MAP + (idx) * 4)
215 #define NUM_PL_VFID_MAP_INSTANCES 256
217 #define LE_DB_MASK_IPV4(idx) (A_LE_DB_MASK_IPV4 + (idx) * 4)
218 #define NUM_LE_DB_MASK_IPV4_INSTANCES 17
220 #define LE_DB_MASK_IPV6(idx) (A_LE_DB_MASK_IPV6 + (idx) * 4)
221 #define NUM_LE_DB_MASK_IPV6_INSTANCES 17
223 #define LE_DB_DBGI_REQ_DATA(idx) (A_LE_DB_DBGI_REQ_DATA + (idx) * 4)
224 #define NUM_LE_DB_DBGI_REQ_DATA_INSTANCES 17
226 #define LE_DB_DBGI_REQ_MASK(idx) (A_LE_DB_DBGI_REQ_MASK + (idx) * 4)
227 #define NUM_LE_DB_DBGI_REQ_MASK_INSTANCES 17
229 #define LE_DB_DBGI_RSP_DATA(idx) (A_LE_DB_DBGI_RSP_DATA + (idx) * 4)
230 #define NUM_LE_DB_DBGI_RSP_DATA_INSTANCES 17
232 #define LE_DB_ACTIVE_MASK_IPV4(idx) (A_LE_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
233 #define NUM_LE_DB_ACTIVE_MASK_IPV4_INSTANCES 17
235 #define LE_DB_ACTIVE_MASK_IPV6(idx) (A_LE_DB_ACTIVE_MASK_IPV6 + (idx) * 4)
236 #define NUM_LE_DB_ACTIVE_MASK_IPV6_INSTANCES 17
238 #define LE_HASH_MASK_GEN_IPV4(idx) (A_LE_HASH_MASK_GEN_IPV4 + (idx) * 4)
239 #define NUM_LE_HASH_MASK_GEN_IPV4_INSTANCES 4
241 #define LE_HASH_MASK_GEN_IPV6(idx) (A_LE_HASH_MASK_GEN_IPV6 + (idx) * 4)
242 #define NUM_LE_HASH_MASK_GEN_IPV6_INSTANCES 12
244 #define LE_HASH_MASK_CMP_IPV4(idx) (A_LE_HASH_MASK_CMP_IPV4 + (idx) * 4)
245 #define NUM_LE_HASH_MASK_CMP_IPV4_INSTANCES 4
247 #define LE_HASH_MASK_CMP_IPV6(idx) (A_LE_HASH_MASK_CMP_IPV6 + (idx) * 4)
248 #define NUM_LE_HASH_MASK_CMP_IPV6_INSTANCES 12
250 #define UP_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
251 #define NUM_UP_TSCH_CHANNEL_INSTANCES 4
253 #define CIM_CTL_MAILBOX_VF_STATUS(idx) (A_CIM_CTL_MAILBOX_VF_STATUS + (idx) * 4)
254 #define NUM_CIM_CTL_MAILBOX_VF_STATUS_INSTANCES 4
256 #define CIM_CTL_MAILBOX_VFN_CTL(idx) (A_CIM_CTL_MAILBOX_VFN_CTL + (idx) * 16)
257 #define NUM_CIM_CTL_MAILBOX_VFN_CTL_INSTANCES 128
259 #define CIM_CTL_TSCH_CHANNEL_REG(reg_addr, idx) ((reg_addr) + (idx) * 288)
260 #define NUM_CIM_CTL_TSCH_CHANNEL_INSTANCES 4
262 #define CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
263 #define NUM_CIM_CTL_TSCH_CHANNEL_TSCH_CLASS_INSTANCES 16
265 #define T5_MYPORT_BASE 0x2c000
266 #define T5_MYPORT_REG(reg_addr) (T5_MYPORT_BASE + (reg_addr))
268 #define T5_PORT0_BASE 0x30000
269 #define T5_PORT0_REG(reg_addr) (T5_PORT0_BASE + (reg_addr))
271 #define T5_PORT1_BASE 0x34000
272 #define T5_PORT1_REG(reg_addr) (T5_PORT1_BASE + (reg_addr))
274 #define T5_PORT2_BASE 0x38000
275 #define T5_PORT2_REG(reg_addr) (T5_PORT2_BASE + (reg_addr))
277 #define T5_PORT3_BASE 0x3c000
278 #define T5_PORT3_REG(reg_addr) (T5_PORT3_BASE + (reg_addr))
280 #define T5_PORT_STRIDE 0x4000
281 #define T5_PORT_BASE(idx) (T5_PORT0_BASE + (idx) * T5_PORT_STRIDE)
282 #define T5_PORT_REG(idx, reg) (T5_PORT_BASE(idx) + (reg))
284 #define MC_STRIDE (MC_1_BASE_ADDR - MC_0_BASE_ADDR)
285 #define MC_REG(reg, idx) (reg + MC_STRIDE * idx)
287 #define PCIE_PF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
288 #define NUM_PCIE_PF_INT_INSTANCES 8
290 #define PCIE_VF_INT_REG(reg_addr, idx) ((reg_addr) + (idx) * 8)
291 #define NUM_PCIE_VF_INT_INSTANCES 128
293 #define PCIE_FID_VFID(idx) (A_PCIE_FID_VFID + (idx) * 4)
294 #define NUM_PCIE_FID_VFID_INSTANCES 2048
296 #define PCIE_COOKIE_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
297 #define NUM_PCIE_COOKIE_INSTANCES 8
299 #define PCIE_T5_DMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
300 #define NUM_PCIE_T5_DMA_INSTANCES 4
302 #define PCIE_T5_CMD_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
303 #define NUM_PCIE_T5_CMD_INSTANCES 3
305 #define PCIE_T5_HMA_REG(reg_addr, idx) ((reg_addr) + (idx) * 16)
306 #define NUM_PCIE_T5_HMA_INSTANCES 1
308 #define PCIE_PHY_PRESET_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
309 #define NUM_PCIE_PHY_PRESET_INSTANCES 11
311 #define MPS_T5_CLS_SRAM_L(idx) (A_MPS_T5_CLS_SRAM_L + (idx) * 8)
312 #define NUM_MPS_T5_CLS_SRAM_L_INSTANCES 512
314 #define MPS_T5_CLS_SRAM_H(idx) (A_MPS_T5_CLS_SRAM_H + (idx) * 8)
315 #define NUM_MPS_T5_CLS_SRAM_H_INSTANCES 512
317 #define LE_T5_DB_MASK_IPV4(idx) (A_LE_T5_DB_MASK_IPV4 + (idx) * 4)
318 #define NUM_LE_T5_DB_MASK_IPV4_INSTANCES 5
320 #define LE_T5_DB_ACTIVE_MASK_IPV4(idx) (A_LE_T5_DB_ACTIVE_MASK_IPV4 + (idx) * 4)
321 #define NUM_LE_T5_DB_ACTIVE_MASK_IPV4_INSTANCES 5
323 #define LE_HASH_MASK_GEN_IPV4T5(idx) (A_LE_HASH_MASK_GEN_IPV4T5 + (idx) * 4)
324 #define NUM_LE_HASH_MASK_GEN_IPV4T5_INSTANCES 5
326 #define LE_HASH_MASK_GEN_IPV6T5(idx) (A_LE_HASH_MASK_GEN_IPV6T5 + (idx) * 4)
327 #define NUM_LE_HASH_MASK_GEN_IPV6T5_INSTANCES 12
329 #define LE_HASH_MASK_CMP_IPV4T5(idx) (A_LE_HASH_MASK_CMP_IPV4T5 + (idx) * 4)
330 #define NUM_LE_HASH_MASK_CMP_IPV4T5_INSTANCES 5
332 #define LE_HASH_MASK_CMP_IPV6T5(idx) (A_LE_HASH_MASK_CMP_IPV6T5 + (idx) * 4)
333 #define NUM_LE_HASH_MASK_CMP_IPV6T5_INSTANCES 12
335 #define LE_DB_SECOND_ACTIVE_MASK_IPV4(idx) (A_LE_DB_SECOND_ACTIVE_MASK_IPV4 + (idx) * 4)
336 #define NUM_LE_DB_SECOND_ACTIVE_MASK_IPV4_INSTANCES 5
338 #define LE_DB_SECOND_GEN_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 + (idx) * 4)
339 #define NUM_LE_DB_SECOND_GEN_HASH_MASK_IPV4_INSTANCES 5
341 #define LE_DB_SECOND_CMP_HASH_MASK_IPV4(idx) (A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 + (idx) * 4)
342 #define NUM_LE_DB_SECOND_CMP_HASH_MASK_IPV4_INSTANCES 5
344 #define MC_ADR_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
345 #define NUM_MC_ADR_INSTANCES 2
347 #define MC_DDRPHY_DP18_REG(reg_addr, idx) ((reg_addr) + (idx) * 512)
348 #define NUM_MC_DDRPHY_DP18_INSTANCES 5
350 #define MC_CE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
351 #define NUM_MC_CE_ERR_DATA_INSTANCES 8
353 #define MC_CE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
354 #define NUM_MC_CE_COR_DATA_INSTANCES 8
356 #define MC_UE_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
357 #define NUM_MC_UE_ERR_DATA_INSTANCES 8
359 #define MC_UE_COR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
360 #define NUM_MC_UE_COR_DATA_INSTANCES 8
362 #define MC_P_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
363 #define NUM_MC_P_BIST_STATUS_INSTANCES 18
365 #define EDC_H_BIST_STATUS_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
366 #define NUM_EDC_H_BIST_STATUS_INSTANCES 18
368 #define EDC_H_ECC_ERR_DATA_REG(reg_addr, idx) ((reg_addr) + (idx) * 4)
369 #define NUM_EDC_H_ECC_ERR_DATA_INSTANCES 16
371 #define EDC_STRIDE (EDC_1_BASE_ADDR - EDC_0_BASE_ADDR)
372 #define EDC_REG(reg, idx) (reg + EDC_STRIDE * idx)
374 /* registers for module SGE */
375 #define SGE_BASE_ADDR 0x1000
377 #define A_SGE_PF_KDOORBELL 0x0
380 #define M_QID 0x1ffffU
381 #define V_QID(x) ((x) << S_QID)
382 #define G_QID(x) (((x) >> S_QID) & M_QID)
385 #define V_DBPRIO(x) ((x) << S_DBPRIO)
386 #define F_DBPRIO V_DBPRIO(1U)
389 #define M_PIDX 0x3fffU
390 #define V_PIDX(x) ((x) << S_PIDX)
391 #define G_PIDX(x) (((x) >> S_PIDX) & M_PIDX)
393 #define A_SGE_VF_KDOORBELL 0x0
396 #define V_DBTYPE(x) ((x) << S_DBTYPE)
397 #define F_DBTYPE V_DBTYPE(1U)
400 #define M_PIDX_T5 0x1fffU
401 #define V_PIDX_T5(x) ((x) << S_PIDX_T5)
402 #define G_PIDX_T5(x) (((x) >> S_PIDX_T5) & M_PIDX_T5)
404 #define A_SGE_PF_GTS 0x4
406 #define S_INGRESSQID 16
407 #define M_INGRESSQID 0xffffU
408 #define V_INGRESSQID(x) ((x) << S_INGRESSQID)
409 #define G_INGRESSQID(x) (((x) >> S_INGRESSQID) & M_INGRESSQID)
411 #define S_TIMERREG 13
412 #define M_TIMERREG 0x7U
413 #define V_TIMERREG(x) ((x) << S_TIMERREG)
414 #define G_TIMERREG(x) (((x) >> S_TIMERREG) & M_TIMERREG)
416 #define S_SEINTARM 12
417 #define V_SEINTARM(x) ((x) << S_SEINTARM)
418 #define F_SEINTARM V_SEINTARM(1U)
421 #define M_CIDXINC 0xfffU
422 #define V_CIDXINC(x) ((x) << S_CIDXINC)
423 #define G_CIDXINC(x) (((x) >> S_CIDXINC) & M_CIDXINC)
425 #define A_SGE_VF_GTS 0x4
426 #define A_SGE_PF_KTIMESTAMP_LO 0x8
427 #define A_SGE_VF_KTIMESTAMP_LO 0x8
428 #define A_SGE_PF_KTIMESTAMP_HI 0xc
430 #define S_TSTAMPVAL 0
431 #define M_TSTAMPVAL 0xfffffffU
432 #define V_TSTAMPVAL(x) ((x) << S_TSTAMPVAL)
433 #define G_TSTAMPVAL(x) (((x) >> S_TSTAMPVAL) & M_TSTAMPVAL)
435 #define A_SGE_VF_KTIMESTAMP_HI 0xc
436 #define A_SGE_CONTROL 0x1008
438 #define S_IGRALLCPLTOFL 31
439 #define V_IGRALLCPLTOFL(x) ((x) << S_IGRALLCPLTOFL)
440 #define F_IGRALLCPLTOFL V_IGRALLCPLTOFL(1U)
442 #define S_FLSPLITMIN 22
443 #define M_FLSPLITMIN 0x1ffU
444 #define V_FLSPLITMIN(x) ((x) << S_FLSPLITMIN)
445 #define G_FLSPLITMIN(x) (((x) >> S_FLSPLITMIN) & M_FLSPLITMIN)
447 #define S_FLSPLITMODE 20
448 #define M_FLSPLITMODE 0x3U
449 #define V_FLSPLITMODE(x) ((x) << S_FLSPLITMODE)
450 #define G_FLSPLITMODE(x) (((x) >> S_FLSPLITMODE) & M_FLSPLITMODE)
452 #define S_DCASYSTYPE 19
453 #define V_DCASYSTYPE(x) ((x) << S_DCASYSTYPE)
454 #define F_DCASYSTYPE V_DCASYSTYPE(1U)
456 #define S_RXPKTCPLMODE 18
457 #define V_RXPKTCPLMODE(x) ((x) << S_RXPKTCPLMODE)
458 #define F_RXPKTCPLMODE V_RXPKTCPLMODE(1U)
460 #define S_EGRSTATUSPAGESIZE 17
461 #define V_EGRSTATUSPAGESIZE(x) ((x) << S_EGRSTATUSPAGESIZE)
462 #define F_EGRSTATUSPAGESIZE V_EGRSTATUSPAGESIZE(1U)
464 #define S_INGHINTENABLE1 15
465 #define V_INGHINTENABLE1(x) ((x) << S_INGHINTENABLE1)
466 #define F_INGHINTENABLE1 V_INGHINTENABLE1(1U)
468 #define S_INGHINTENABLE0 14
469 #define V_INGHINTENABLE0(x) ((x) << S_INGHINTENABLE0)
470 #define F_INGHINTENABLE0 V_INGHINTENABLE0(1U)
472 #define S_INGINTCOMPAREIDX 13
473 #define V_INGINTCOMPAREIDX(x) ((x) << S_INGINTCOMPAREIDX)
474 #define F_INGINTCOMPAREIDX V_INGINTCOMPAREIDX(1U)
476 #define S_PKTSHIFT 10
477 #define M_PKTSHIFT 0x7U
478 #define V_PKTSHIFT(x) ((x) << S_PKTSHIFT)
479 #define G_PKTSHIFT(x) (((x) >> S_PKTSHIFT) & M_PKTSHIFT)
481 #define S_INGPCIEBOUNDARY 7
482 #define M_INGPCIEBOUNDARY 0x7U
483 #define V_INGPCIEBOUNDARY(x) ((x) << S_INGPCIEBOUNDARY)
484 #define G_INGPCIEBOUNDARY(x) (((x) >> S_INGPCIEBOUNDARY) & M_INGPCIEBOUNDARY)
486 #define S_INGPADBOUNDARY 4
487 #define M_INGPADBOUNDARY 0x7U
488 #define V_INGPADBOUNDARY(x) ((x) << S_INGPADBOUNDARY)
489 #define G_INGPADBOUNDARY(x) (((x) >> S_INGPADBOUNDARY) & M_INGPADBOUNDARY)
491 #define S_EGRPCIEBOUNDARY 1
492 #define M_EGRPCIEBOUNDARY 0x7U
493 #define V_EGRPCIEBOUNDARY(x) ((x) << S_EGRPCIEBOUNDARY)
494 #define G_EGRPCIEBOUNDARY(x) (((x) >> S_EGRPCIEBOUNDARY) & M_EGRPCIEBOUNDARY)
496 #define S_GLOBALENABLE 0
497 #define V_GLOBALENABLE(x) ((x) << S_GLOBALENABLE)
498 #define F_GLOBALENABLE V_GLOBALENABLE(1U)
500 #define A_SGE_HOST_PAGE_SIZE 0x100c
502 #define S_HOSTPAGESIZEPF7 28
503 #define M_HOSTPAGESIZEPF7 0xfU
504 #define V_HOSTPAGESIZEPF7(x) ((x) << S_HOSTPAGESIZEPF7)
505 #define G_HOSTPAGESIZEPF7(x) (((x) >> S_HOSTPAGESIZEPF7) & M_HOSTPAGESIZEPF7)
507 #define S_HOSTPAGESIZEPF6 24
508 #define M_HOSTPAGESIZEPF6 0xfU
509 #define V_HOSTPAGESIZEPF6(x) ((x) << S_HOSTPAGESIZEPF6)
510 #define G_HOSTPAGESIZEPF6(x) (((x) >> S_HOSTPAGESIZEPF6) & M_HOSTPAGESIZEPF6)
512 #define S_HOSTPAGESIZEPF5 20
513 #define M_HOSTPAGESIZEPF5 0xfU
514 #define V_HOSTPAGESIZEPF5(x) ((x) << S_HOSTPAGESIZEPF5)
515 #define G_HOSTPAGESIZEPF5(x) (((x) >> S_HOSTPAGESIZEPF5) & M_HOSTPAGESIZEPF5)
517 #define S_HOSTPAGESIZEPF4 16
518 #define M_HOSTPAGESIZEPF4 0xfU
519 #define V_HOSTPAGESIZEPF4(x) ((x) << S_HOSTPAGESIZEPF4)
520 #define G_HOSTPAGESIZEPF4(x) (((x) >> S_HOSTPAGESIZEPF4) & M_HOSTPAGESIZEPF4)
522 #define S_HOSTPAGESIZEPF3 12
523 #define M_HOSTPAGESIZEPF3 0xfU
524 #define V_HOSTPAGESIZEPF3(x) ((x) << S_HOSTPAGESIZEPF3)
525 #define G_HOSTPAGESIZEPF3(x) (((x) >> S_HOSTPAGESIZEPF3) & M_HOSTPAGESIZEPF3)
527 #define S_HOSTPAGESIZEPF2 8
528 #define M_HOSTPAGESIZEPF2 0xfU
529 #define V_HOSTPAGESIZEPF2(x) ((x) << S_HOSTPAGESIZEPF2)
530 #define G_HOSTPAGESIZEPF2(x) (((x) >> S_HOSTPAGESIZEPF2) & M_HOSTPAGESIZEPF2)
532 #define S_HOSTPAGESIZEPF1 4
533 #define M_HOSTPAGESIZEPF1 0xfU
534 #define V_HOSTPAGESIZEPF1(x) ((x) << S_HOSTPAGESIZEPF1)
535 #define G_HOSTPAGESIZEPF1(x) (((x) >> S_HOSTPAGESIZEPF1) & M_HOSTPAGESIZEPF1)
537 #define S_HOSTPAGESIZEPF0 0
538 #define M_HOSTPAGESIZEPF0 0xfU
539 #define V_HOSTPAGESIZEPF0(x) ((x) << S_HOSTPAGESIZEPF0)
540 #define G_HOSTPAGESIZEPF0(x) (((x) >> S_HOSTPAGESIZEPF0) & M_HOSTPAGESIZEPF0)
542 #define A_SGE_EGRESS_QUEUES_PER_PAGE_PF 0x1010
544 #define S_QUEUESPERPAGEPF7 28
545 #define M_QUEUESPERPAGEPF7 0xfU
546 #define V_QUEUESPERPAGEPF7(x) ((x) << S_QUEUESPERPAGEPF7)
547 #define G_QUEUESPERPAGEPF7(x) (((x) >> S_QUEUESPERPAGEPF7) & M_QUEUESPERPAGEPF7)
549 #define S_QUEUESPERPAGEPF6 24
550 #define M_QUEUESPERPAGEPF6 0xfU
551 #define V_QUEUESPERPAGEPF6(x) ((x) << S_QUEUESPERPAGEPF6)
552 #define G_QUEUESPERPAGEPF6(x) (((x) >> S_QUEUESPERPAGEPF6) & M_QUEUESPERPAGEPF6)
554 #define S_QUEUESPERPAGEPF5 20
555 #define M_QUEUESPERPAGEPF5 0xfU
556 #define V_QUEUESPERPAGEPF5(x) ((x) << S_QUEUESPERPAGEPF5)
557 #define G_QUEUESPERPAGEPF5(x) (((x) >> S_QUEUESPERPAGEPF5) & M_QUEUESPERPAGEPF5)
559 #define S_QUEUESPERPAGEPF4 16
560 #define M_QUEUESPERPAGEPF4 0xfU
561 #define V_QUEUESPERPAGEPF4(x) ((x) << S_QUEUESPERPAGEPF4)
562 #define G_QUEUESPERPAGEPF4(x) (((x) >> S_QUEUESPERPAGEPF4) & M_QUEUESPERPAGEPF4)
564 #define S_QUEUESPERPAGEPF3 12
565 #define M_QUEUESPERPAGEPF3 0xfU
566 #define V_QUEUESPERPAGEPF3(x) ((x) << S_QUEUESPERPAGEPF3)
567 #define G_QUEUESPERPAGEPF3(x) (((x) >> S_QUEUESPERPAGEPF3) & M_QUEUESPERPAGEPF3)
569 #define S_QUEUESPERPAGEPF2 8
570 #define M_QUEUESPERPAGEPF2 0xfU
571 #define V_QUEUESPERPAGEPF2(x) ((x) << S_QUEUESPERPAGEPF2)
572 #define G_QUEUESPERPAGEPF2(x) (((x) >> S_QUEUESPERPAGEPF2) & M_QUEUESPERPAGEPF2)
574 #define S_QUEUESPERPAGEPF1 4
575 #define M_QUEUESPERPAGEPF1 0xfU
576 #define V_QUEUESPERPAGEPF1(x) ((x) << S_QUEUESPERPAGEPF1)
577 #define G_QUEUESPERPAGEPF1(x) (((x) >> S_QUEUESPERPAGEPF1) & M_QUEUESPERPAGEPF1)
579 #define S_QUEUESPERPAGEPF0 0
580 #define M_QUEUESPERPAGEPF0 0xfU
581 #define V_QUEUESPERPAGEPF0(x) ((x) << S_QUEUESPERPAGEPF0)
582 #define G_QUEUESPERPAGEPF0(x) (((x) >> S_QUEUESPERPAGEPF0) & M_QUEUESPERPAGEPF0)
584 #define A_SGE_EGRESS_QUEUES_PER_PAGE_VF 0x1014
586 #define S_QUEUESPERPAGEVFPF7 28
587 #define M_QUEUESPERPAGEVFPF7 0xfU
588 #define V_QUEUESPERPAGEVFPF7(x) ((x) << S_QUEUESPERPAGEVFPF7)
589 #define G_QUEUESPERPAGEVFPF7(x) (((x) >> S_QUEUESPERPAGEVFPF7) & M_QUEUESPERPAGEVFPF7)
591 #define S_QUEUESPERPAGEVFPF6 24
592 #define M_QUEUESPERPAGEVFPF6 0xfU
593 #define V_QUEUESPERPAGEVFPF6(x) ((x) << S_QUEUESPERPAGEVFPF6)
594 #define G_QUEUESPERPAGEVFPF6(x) (((x) >> S_QUEUESPERPAGEVFPF6) & M_QUEUESPERPAGEVFPF6)
596 #define S_QUEUESPERPAGEVFPF5 20
597 #define M_QUEUESPERPAGEVFPF5 0xfU
598 #define V_QUEUESPERPAGEVFPF5(x) ((x) << S_QUEUESPERPAGEVFPF5)
599 #define G_QUEUESPERPAGEVFPF5(x) (((x) >> S_QUEUESPERPAGEVFPF5) & M_QUEUESPERPAGEVFPF5)
601 #define S_QUEUESPERPAGEVFPF4 16
602 #define M_QUEUESPERPAGEVFPF4 0xfU
603 #define V_QUEUESPERPAGEVFPF4(x) ((x) << S_QUEUESPERPAGEVFPF4)
604 #define G_QUEUESPERPAGEVFPF4(x) (((x) >> S_QUEUESPERPAGEVFPF4) & M_QUEUESPERPAGEVFPF4)
606 #define S_QUEUESPERPAGEVFPF3 12
607 #define M_QUEUESPERPAGEVFPF3 0xfU
608 #define V_QUEUESPERPAGEVFPF3(x) ((x) << S_QUEUESPERPAGEVFPF3)
609 #define G_QUEUESPERPAGEVFPF3(x) (((x) >> S_QUEUESPERPAGEVFPF3) & M_QUEUESPERPAGEVFPF3)
611 #define S_QUEUESPERPAGEVFPF2 8
612 #define M_QUEUESPERPAGEVFPF2 0xfU
613 #define V_QUEUESPERPAGEVFPF2(x) ((x) << S_QUEUESPERPAGEVFPF2)
614 #define G_QUEUESPERPAGEVFPF2(x) (((x) >> S_QUEUESPERPAGEVFPF2) & M_QUEUESPERPAGEVFPF2)
616 #define S_QUEUESPERPAGEVFPF1 4
617 #define M_QUEUESPERPAGEVFPF1 0xfU
618 #define V_QUEUESPERPAGEVFPF1(x) ((x) << S_QUEUESPERPAGEVFPF1)
619 #define G_QUEUESPERPAGEVFPF1(x) (((x) >> S_QUEUESPERPAGEVFPF1) & M_QUEUESPERPAGEVFPF1)
621 #define S_QUEUESPERPAGEVFPF0 0
622 #define M_QUEUESPERPAGEVFPF0 0xfU
623 #define V_QUEUESPERPAGEVFPF0(x) ((x) << S_QUEUESPERPAGEVFPF0)
624 #define G_QUEUESPERPAGEVFPF0(x) (((x) >> S_QUEUESPERPAGEVFPF0) & M_QUEUESPERPAGEVFPF0)
626 #define A_SGE_USER_MODE_LIMITS 0x1018
628 #define S_OPCODE_MIN 24
629 #define M_OPCODE_MIN 0xffU
630 #define V_OPCODE_MIN(x) ((x) << S_OPCODE_MIN)
631 #define G_OPCODE_MIN(x) (((x) >> S_OPCODE_MIN) & M_OPCODE_MIN)
633 #define S_OPCODE_MAX 16
634 #define M_OPCODE_MAX 0xffU
635 #define V_OPCODE_MAX(x) ((x) << S_OPCODE_MAX)
636 #define G_OPCODE_MAX(x) (((x) >> S_OPCODE_MAX) & M_OPCODE_MAX)
638 #define S_LENGTH_MIN 8
639 #define M_LENGTH_MIN 0xffU
640 #define V_LENGTH_MIN(x) ((x) << S_LENGTH_MIN)
641 #define G_LENGTH_MIN(x) (((x) >> S_LENGTH_MIN) & M_LENGTH_MIN)
643 #define S_LENGTH_MAX 0
644 #define M_LENGTH_MAX 0xffU
645 #define V_LENGTH_MAX(x) ((x) << S_LENGTH_MAX)
646 #define G_LENGTH_MAX(x) (((x) >> S_LENGTH_MAX) & M_LENGTH_MAX)
648 #define A_SGE_WR_ERROR 0x101c
650 #define S_WR_ERROR_OPCODE 0
651 #define M_WR_ERROR_OPCODE 0xffU
652 #define V_WR_ERROR_OPCODE(x) ((x) << S_WR_ERROR_OPCODE)
653 #define G_WR_ERROR_OPCODE(x) (((x) >> S_WR_ERROR_OPCODE) & M_WR_ERROR_OPCODE)
655 #define A_SGE_PERR_INJECT 0x1020
658 #define M_MEMSEL 0x1fU
659 #define V_MEMSEL(x) ((x) << S_MEMSEL)
660 #define G_MEMSEL(x) (((x) >> S_MEMSEL) & M_MEMSEL)
662 #define S_INJECTDATAERR 0
663 #define V_INJECTDATAERR(x) ((x) << S_INJECTDATAERR)
664 #define F_INJECTDATAERR V_INJECTDATAERR(1U)
666 #define A_SGE_INT_CAUSE1 0x1024
668 #define S_PERR_FLM_CREDITFIFO 30
669 #define V_PERR_FLM_CREDITFIFO(x) ((x) << S_PERR_FLM_CREDITFIFO)
670 #define F_PERR_FLM_CREDITFIFO V_PERR_FLM_CREDITFIFO(1U)
672 #define S_PERR_IMSG_HINT_FIFO 29
673 #define V_PERR_IMSG_HINT_FIFO(x) ((x) << S_PERR_IMSG_HINT_FIFO)
674 #define F_PERR_IMSG_HINT_FIFO V_PERR_IMSG_HINT_FIFO(1U)
676 #define S_PERR_MC_PC 28
677 #define V_PERR_MC_PC(x) ((x) << S_PERR_MC_PC)
678 #define F_PERR_MC_PC V_PERR_MC_PC(1U)
680 #define S_PERR_MC_IGR_CTXT 27
681 #define V_PERR_MC_IGR_CTXT(x) ((x) << S_PERR_MC_IGR_CTXT)
682 #define F_PERR_MC_IGR_CTXT V_PERR_MC_IGR_CTXT(1U)
684 #define S_PERR_MC_EGR_CTXT 26
685 #define V_PERR_MC_EGR_CTXT(x) ((x) << S_PERR_MC_EGR_CTXT)
686 #define F_PERR_MC_EGR_CTXT V_PERR_MC_EGR_CTXT(1U)
688 #define S_PERR_MC_FLM 25
689 #define V_PERR_MC_FLM(x) ((x) << S_PERR_MC_FLM)
690 #define F_PERR_MC_FLM V_PERR_MC_FLM(1U)
692 #define S_PERR_PC_MCTAG 24
693 #define V_PERR_PC_MCTAG(x) ((x) << S_PERR_PC_MCTAG)
694 #define F_PERR_PC_MCTAG V_PERR_PC_MCTAG(1U)
696 #define S_PERR_PC_CHPI_RSP1 23
697 #define V_PERR_PC_CHPI_RSP1(x) ((x) << S_PERR_PC_CHPI_RSP1)
698 #define F_PERR_PC_CHPI_RSP1 V_PERR_PC_CHPI_RSP1(1U)
700 #define S_PERR_PC_CHPI_RSP0 22
701 #define V_PERR_PC_CHPI_RSP0(x) ((x) << S_PERR_PC_CHPI_RSP0)
702 #define F_PERR_PC_CHPI_RSP0 V_PERR_PC_CHPI_RSP0(1U)
704 #define S_PERR_DBP_PC_RSP_FIFO3 21
705 #define V_PERR_DBP_PC_RSP_FIFO3(x) ((x) << S_PERR_DBP_PC_RSP_FIFO3)
706 #define F_PERR_DBP_PC_RSP_FIFO3 V_PERR_DBP_PC_RSP_FIFO3(1U)
708 #define S_PERR_DBP_PC_RSP_FIFO2 20
709 #define V_PERR_DBP_PC_RSP_FIFO2(x) ((x) << S_PERR_DBP_PC_RSP_FIFO2)
710 #define F_PERR_DBP_PC_RSP_FIFO2 V_PERR_DBP_PC_RSP_FIFO2(1U)
712 #define S_PERR_DBP_PC_RSP_FIFO1 19
713 #define V_PERR_DBP_PC_RSP_FIFO1(x) ((x) << S_PERR_DBP_PC_RSP_FIFO1)
714 #define F_PERR_DBP_PC_RSP_FIFO1 V_PERR_DBP_PC_RSP_FIFO1(1U)
716 #define S_PERR_DBP_PC_RSP_FIFO0 18
717 #define V_PERR_DBP_PC_RSP_FIFO0(x) ((x) << S_PERR_DBP_PC_RSP_FIFO0)
718 #define F_PERR_DBP_PC_RSP_FIFO0 V_PERR_DBP_PC_RSP_FIFO0(1U)
720 #define S_PERR_DMARBT 17
721 #define V_PERR_DMARBT(x) ((x) << S_PERR_DMARBT)
722 #define F_PERR_DMARBT V_PERR_DMARBT(1U)
724 #define S_PERR_FLM_DBPFIFO 16
725 #define V_PERR_FLM_DBPFIFO(x) ((x) << S_PERR_FLM_DBPFIFO)
726 #define F_PERR_FLM_DBPFIFO V_PERR_FLM_DBPFIFO(1U)
728 #define S_PERR_FLM_MCREQ_FIFO 15
729 #define V_PERR_FLM_MCREQ_FIFO(x) ((x) << S_PERR_FLM_MCREQ_FIFO)
730 #define F_PERR_FLM_MCREQ_FIFO V_PERR_FLM_MCREQ_FIFO(1U)
732 #define S_PERR_FLM_HINTFIFO 14
733 #define V_PERR_FLM_HINTFIFO(x) ((x) << S_PERR_FLM_HINTFIFO)
734 #define F_PERR_FLM_HINTFIFO V_PERR_FLM_HINTFIFO(1U)
736 #define S_PERR_ALIGN_CTL_FIFO3 13
737 #define V_PERR_ALIGN_CTL_FIFO3(x) ((x) << S_PERR_ALIGN_CTL_FIFO3)
738 #define F_PERR_ALIGN_CTL_FIFO3 V_PERR_ALIGN_CTL_FIFO3(1U)
740 #define S_PERR_ALIGN_CTL_FIFO2 12
741 #define V_PERR_ALIGN_CTL_FIFO2(x) ((x) << S_PERR_ALIGN_CTL_FIFO2)
742 #define F_PERR_ALIGN_CTL_FIFO2 V_PERR_ALIGN_CTL_FIFO2(1U)
744 #define S_PERR_ALIGN_CTL_FIFO1 11
745 #define V_PERR_ALIGN_CTL_FIFO1(x) ((x) << S_PERR_ALIGN_CTL_FIFO1)
746 #define F_PERR_ALIGN_CTL_FIFO1 V_PERR_ALIGN_CTL_FIFO1(1U)
748 #define S_PERR_ALIGN_CTL_FIFO0 10
749 #define V_PERR_ALIGN_CTL_FIFO0(x) ((x) << S_PERR_ALIGN_CTL_FIFO0)
750 #define F_PERR_ALIGN_CTL_FIFO0 V_PERR_ALIGN_CTL_FIFO0(1U)
752 #define S_PERR_EDMA_FIFO3 9
753 #define V_PERR_EDMA_FIFO3(x) ((x) << S_PERR_EDMA_FIFO3)
754 #define F_PERR_EDMA_FIFO3 V_PERR_EDMA_FIFO3(1U)
756 #define S_PERR_EDMA_FIFO2 8
757 #define V_PERR_EDMA_FIFO2(x) ((x) << S_PERR_EDMA_FIFO2)
758 #define F_PERR_EDMA_FIFO2 V_PERR_EDMA_FIFO2(1U)
760 #define S_PERR_EDMA_FIFO1 7
761 #define V_PERR_EDMA_FIFO1(x) ((x) << S_PERR_EDMA_FIFO1)
762 #define F_PERR_EDMA_FIFO1 V_PERR_EDMA_FIFO1(1U)
764 #define S_PERR_EDMA_FIFO0 6
765 #define V_PERR_EDMA_FIFO0(x) ((x) << S_PERR_EDMA_FIFO0)
766 #define F_PERR_EDMA_FIFO0 V_PERR_EDMA_FIFO0(1U)
768 #define S_PERR_PD_FIFO3 5
769 #define V_PERR_PD_FIFO3(x) ((x) << S_PERR_PD_FIFO3)
770 #define F_PERR_PD_FIFO3 V_PERR_PD_FIFO3(1U)
772 #define S_PERR_PD_FIFO2 4
773 #define V_PERR_PD_FIFO2(x) ((x) << S_PERR_PD_FIFO2)
774 #define F_PERR_PD_FIFO2 V_PERR_PD_FIFO2(1U)
776 #define S_PERR_PD_FIFO1 3
777 #define V_PERR_PD_FIFO1(x) ((x) << S_PERR_PD_FIFO1)
778 #define F_PERR_PD_FIFO1 V_PERR_PD_FIFO1(1U)
780 #define S_PERR_PD_FIFO0 2
781 #define V_PERR_PD_FIFO0(x) ((x) << S_PERR_PD_FIFO0)
782 #define F_PERR_PD_FIFO0 V_PERR_PD_FIFO0(1U)
784 #define S_PERR_ING_CTXT_MIFRSP 1
785 #define V_PERR_ING_CTXT_MIFRSP(x) ((x) << S_PERR_ING_CTXT_MIFRSP)
786 #define F_PERR_ING_CTXT_MIFRSP V_PERR_ING_CTXT_MIFRSP(1U)
788 #define S_PERR_EGR_CTXT_MIFRSP 0
789 #define V_PERR_EGR_CTXT_MIFRSP(x) ((x) << S_PERR_EGR_CTXT_MIFRSP)
790 #define F_PERR_EGR_CTXT_MIFRSP V_PERR_EGR_CTXT_MIFRSP(1U)
792 #define S_PERR_PC_CHPI_RSP2 31
793 #define V_PERR_PC_CHPI_RSP2(x) ((x) << S_PERR_PC_CHPI_RSP2)
794 #define F_PERR_PC_CHPI_RSP2 V_PERR_PC_CHPI_RSP2(1U)
796 #define A_SGE_INT_ENABLE1 0x1028
797 #define A_SGE_PERR_ENABLE1 0x102c
798 #define A_SGE_INT_CAUSE2 0x1030
800 #define S_PERR_HINT_DELAY_FIFO1 30
801 #define V_PERR_HINT_DELAY_FIFO1(x) ((x) << S_PERR_HINT_DELAY_FIFO1)
802 #define F_PERR_HINT_DELAY_FIFO1 V_PERR_HINT_DELAY_FIFO1(1U)
804 #define S_PERR_HINT_DELAY_FIFO0 29
805 #define V_PERR_HINT_DELAY_FIFO0(x) ((x) << S_PERR_HINT_DELAY_FIFO0)
806 #define F_PERR_HINT_DELAY_FIFO0 V_PERR_HINT_DELAY_FIFO0(1U)
808 #define S_PERR_IMSG_PD_FIFO 28
809 #define V_PERR_IMSG_PD_FIFO(x) ((x) << S_PERR_IMSG_PD_FIFO)
810 #define F_PERR_IMSG_PD_FIFO V_PERR_IMSG_PD_FIFO(1U)
812 #define S_PERR_ULPTX_FIFO1 27
813 #define V_PERR_ULPTX_FIFO1(x) ((x) << S_PERR_ULPTX_FIFO1)
814 #define F_PERR_ULPTX_FIFO1 V_PERR_ULPTX_FIFO1(1U)
816 #define S_PERR_ULPTX_FIFO0 26
817 #define V_PERR_ULPTX_FIFO0(x) ((x) << S_PERR_ULPTX_FIFO0)
818 #define F_PERR_ULPTX_FIFO0 V_PERR_ULPTX_FIFO0(1U)
820 #define S_PERR_IDMA2IMSG_FIFO1 25
821 #define V_PERR_IDMA2IMSG_FIFO1(x) ((x) << S_PERR_IDMA2IMSG_FIFO1)
822 #define F_PERR_IDMA2IMSG_FIFO1 V_PERR_IDMA2IMSG_FIFO1(1U)
824 #define S_PERR_IDMA2IMSG_FIFO0 24
825 #define V_PERR_IDMA2IMSG_FIFO0(x) ((x) << S_PERR_IDMA2IMSG_FIFO0)
826 #define F_PERR_IDMA2IMSG_FIFO0 V_PERR_IDMA2IMSG_FIFO0(1U)
828 #define S_PERR_HEADERSPLIT_FIFO1 23
829 #define V_PERR_HEADERSPLIT_FIFO1(x) ((x) << S_PERR_HEADERSPLIT_FIFO1)
830 #define F_PERR_HEADERSPLIT_FIFO1 V_PERR_HEADERSPLIT_FIFO1(1U)
832 #define S_PERR_HEADERSPLIT_FIFO0 22
833 #define V_PERR_HEADERSPLIT_FIFO0(x) ((x) << S_PERR_HEADERSPLIT_FIFO0)
834 #define F_PERR_HEADERSPLIT_FIFO0 V_PERR_HEADERSPLIT_FIFO0(1U)
836 #define S_PERR_ESWITCH_FIFO3 21
837 #define V_PERR_ESWITCH_FIFO3(x) ((x) << S_PERR_ESWITCH_FIFO3)
838 #define F_PERR_ESWITCH_FIFO3 V_PERR_ESWITCH_FIFO3(1U)
840 #define S_PERR_ESWITCH_FIFO2 20
841 #define V_PERR_ESWITCH_FIFO2(x) ((x) << S_PERR_ESWITCH_FIFO2)
842 #define F_PERR_ESWITCH_FIFO2 V_PERR_ESWITCH_FIFO2(1U)
844 #define S_PERR_ESWITCH_FIFO1 19
845 #define V_PERR_ESWITCH_FIFO1(x) ((x) << S_PERR_ESWITCH_FIFO1)
846 #define F_PERR_ESWITCH_FIFO1 V_PERR_ESWITCH_FIFO1(1U)
848 #define S_PERR_ESWITCH_FIFO0 18
849 #define V_PERR_ESWITCH_FIFO0(x) ((x) << S_PERR_ESWITCH_FIFO0)
850 #define F_PERR_ESWITCH_FIFO0 V_PERR_ESWITCH_FIFO0(1U)
852 #define S_PERR_PC_DBP1 17
853 #define V_PERR_PC_DBP1(x) ((x) << S_PERR_PC_DBP1)
854 #define F_PERR_PC_DBP1 V_PERR_PC_DBP1(1U)
856 #define S_PERR_PC_DBP0 16
857 #define V_PERR_PC_DBP0(x) ((x) << S_PERR_PC_DBP0)
858 #define F_PERR_PC_DBP0 V_PERR_PC_DBP0(1U)
860 #define S_PERR_IMSG_OB_FIFO 15
861 #define V_PERR_IMSG_OB_FIFO(x) ((x) << S_PERR_IMSG_OB_FIFO)
862 #define F_PERR_IMSG_OB_FIFO V_PERR_IMSG_OB_FIFO(1U)
864 #define S_PERR_CONM_SRAM 14
865 #define V_PERR_CONM_SRAM(x) ((x) << S_PERR_CONM_SRAM)
866 #define F_PERR_CONM_SRAM V_PERR_CONM_SRAM(1U)
868 #define S_PERR_PC_MC_RSP 13
869 #define V_PERR_PC_MC_RSP(x) ((x) << S_PERR_PC_MC_RSP)
870 #define F_PERR_PC_MC_RSP V_PERR_PC_MC_RSP(1U)
872 #define S_PERR_ISW_IDMA0_FIFO 12
873 #define V_PERR_ISW_IDMA0_FIFO(x) ((x) << S_PERR_ISW_IDMA0_FIFO)
874 #define F_PERR_ISW_IDMA0_FIFO V_PERR_ISW_IDMA0_FIFO(1U)
876 #define S_PERR_ISW_IDMA1_FIFO 11
877 #define V_PERR_ISW_IDMA1_FIFO(x) ((x) << S_PERR_ISW_IDMA1_FIFO)
878 #define F_PERR_ISW_IDMA1_FIFO V_PERR_ISW_IDMA1_FIFO(1U)
880 #define S_PERR_ISW_DBP_FIFO 10
881 #define V_PERR_ISW_DBP_FIFO(x) ((x) << S_PERR_ISW_DBP_FIFO)
882 #define F_PERR_ISW_DBP_FIFO V_PERR_ISW_DBP_FIFO(1U)
884 #define S_PERR_ISW_GTS_FIFO 9
885 #define V_PERR_ISW_GTS_FIFO(x) ((x) << S_PERR_ISW_GTS_FIFO)
886 #define F_PERR_ISW_GTS_FIFO V_PERR_ISW_GTS_FIFO(1U)
888 #define S_PERR_ITP_EVR 8
889 #define V_PERR_ITP_EVR(x) ((x) << S_PERR_ITP_EVR)
890 #define F_PERR_ITP_EVR V_PERR_ITP_EVR(1U)
892 #define S_PERR_FLM_CNTXMEM 7
893 #define V_PERR_FLM_CNTXMEM(x) ((x) << S_PERR_FLM_CNTXMEM)
894 #define F_PERR_FLM_CNTXMEM V_PERR_FLM_CNTXMEM(1U)
896 #define S_PERR_FLM_L1CACHE 6
897 #define V_PERR_FLM_L1CACHE(x) ((x) << S_PERR_FLM_L1CACHE)
898 #define F_PERR_FLM_L1CACHE V_PERR_FLM_L1CACHE(1U)
900 #define S_PERR_DBP_HINT_FIFO 5
901 #define V_PERR_DBP_HINT_FIFO(x) ((x) << S_PERR_DBP_HINT_FIFO)
902 #define F_PERR_DBP_HINT_FIFO V_PERR_DBP_HINT_FIFO(1U)
904 #define S_PERR_DBP_HP_FIFO 4
905 #define V_PERR_DBP_HP_FIFO(x) ((x) << S_PERR_DBP_HP_FIFO)
906 #define F_PERR_DBP_HP_FIFO V_PERR_DBP_HP_FIFO(1U)
908 #define S_PERR_DBP_LP_FIFO 3
909 #define V_PERR_DBP_LP_FIFO(x) ((x) << S_PERR_DBP_LP_FIFO)
910 #define F_PERR_DBP_LP_FIFO V_PERR_DBP_LP_FIFO(1U)
912 #define S_PERR_ING_CTXT_CACHE 2
913 #define V_PERR_ING_CTXT_CACHE(x) ((x) << S_PERR_ING_CTXT_CACHE)
914 #define F_PERR_ING_CTXT_CACHE V_PERR_ING_CTXT_CACHE(1U)
916 #define S_PERR_EGR_CTXT_CACHE 1
917 #define V_PERR_EGR_CTXT_CACHE(x) ((x) << S_PERR_EGR_CTXT_CACHE)
918 #define F_PERR_EGR_CTXT_CACHE V_PERR_EGR_CTXT_CACHE(1U)
920 #define S_PERR_BASE_SIZE 0
921 #define V_PERR_BASE_SIZE(x) ((x) << S_PERR_BASE_SIZE)
922 #define F_PERR_BASE_SIZE V_PERR_BASE_SIZE(1U)
924 #define S_PERR_DBP_HINT_FL_FIFO 24
925 #define V_PERR_DBP_HINT_FL_FIFO(x) ((x) << S_PERR_DBP_HINT_FL_FIFO)
926 #define F_PERR_DBP_HINT_FL_FIFO V_PERR_DBP_HINT_FL_FIFO(1U)
928 #define S_PERR_EGR_DBP_TX_COAL 23
929 #define V_PERR_EGR_DBP_TX_COAL(x) ((x) << S_PERR_EGR_DBP_TX_COAL)
930 #define F_PERR_EGR_DBP_TX_COAL V_PERR_EGR_DBP_TX_COAL(1U)
932 #define S_PERR_DBP_FL_FIFO 22
933 #define V_PERR_DBP_FL_FIFO(x) ((x) << S_PERR_DBP_FL_FIFO)
934 #define F_PERR_DBP_FL_FIFO V_PERR_DBP_FL_FIFO(1U)
936 #define S_PERR_PC_DBP2 15
937 #define V_PERR_PC_DBP2(x) ((x) << S_PERR_PC_DBP2)
938 #define F_PERR_PC_DBP2 V_PERR_PC_DBP2(1U)
940 #define A_SGE_INT_ENABLE2 0x1034
941 #define A_SGE_PERR_ENABLE2 0x1038
942 #define A_SGE_INT_CAUSE3 0x103c
944 #define S_ERR_FLM_DBP 31
945 #define V_ERR_FLM_DBP(x) ((x) << S_ERR_FLM_DBP)
946 #define F_ERR_FLM_DBP V_ERR_FLM_DBP(1U)
948 #define S_ERR_FLM_IDMA1 30
949 #define V_ERR_FLM_IDMA1(x) ((x) << S_ERR_FLM_IDMA1)
950 #define F_ERR_FLM_IDMA1 V_ERR_FLM_IDMA1(1U)
952 #define S_ERR_FLM_IDMA0 29
953 #define V_ERR_FLM_IDMA0(x) ((x) << S_ERR_FLM_IDMA0)
954 #define F_ERR_FLM_IDMA0 V_ERR_FLM_IDMA0(1U)
956 #define S_ERR_FLM_HINT 28
957 #define V_ERR_FLM_HINT(x) ((x) << S_ERR_FLM_HINT)
958 #define F_ERR_FLM_HINT V_ERR_FLM_HINT(1U)
960 #define S_ERR_PCIE_ERROR3 27
961 #define V_ERR_PCIE_ERROR3(x) ((x) << S_ERR_PCIE_ERROR3)
962 #define F_ERR_PCIE_ERROR3 V_ERR_PCIE_ERROR3(1U)
964 #define S_ERR_PCIE_ERROR2 26
965 #define V_ERR_PCIE_ERROR2(x) ((x) << S_ERR_PCIE_ERROR2)
966 #define F_ERR_PCIE_ERROR2 V_ERR_PCIE_ERROR2(1U)
968 #define S_ERR_PCIE_ERROR1 25
969 #define V_ERR_PCIE_ERROR1(x) ((x) << S_ERR_PCIE_ERROR1)
970 #define F_ERR_PCIE_ERROR1 V_ERR_PCIE_ERROR1(1U)
972 #define S_ERR_PCIE_ERROR0 24
973 #define V_ERR_PCIE_ERROR0(x) ((x) << S_ERR_PCIE_ERROR0)
974 #define F_ERR_PCIE_ERROR0 V_ERR_PCIE_ERROR0(1U)
976 #define S_ERR_TIMER_ABOVE_MAX_QID 23
977 #define V_ERR_TIMER_ABOVE_MAX_QID(x) ((x) << S_ERR_TIMER_ABOVE_MAX_QID)
978 #define F_ERR_TIMER_ABOVE_MAX_QID V_ERR_TIMER_ABOVE_MAX_QID(1U)
980 #define S_ERR_CPL_EXCEED_IQE_SIZE 22
981 #define V_ERR_CPL_EXCEED_IQE_SIZE(x) ((x) << S_ERR_CPL_EXCEED_IQE_SIZE)
982 #define F_ERR_CPL_EXCEED_IQE_SIZE V_ERR_CPL_EXCEED_IQE_SIZE(1U)
984 #define S_ERR_INVALID_CIDX_INC 21
985 #define V_ERR_INVALID_CIDX_INC(x) ((x) << S_ERR_INVALID_CIDX_INC)
986 #define F_ERR_INVALID_CIDX_INC V_ERR_INVALID_CIDX_INC(1U)
988 #define S_ERR_ITP_TIME_PAUSED 20
989 #define V_ERR_ITP_TIME_PAUSED(x) ((x) << S_ERR_ITP_TIME_PAUSED)
990 #define F_ERR_ITP_TIME_PAUSED V_ERR_ITP_TIME_PAUSED(1U)
992 #define S_ERR_CPL_OPCODE_0 19
993 #define V_ERR_CPL_OPCODE_0(x) ((x) << S_ERR_CPL_OPCODE_0)
994 #define F_ERR_CPL_OPCODE_0 V_ERR_CPL_OPCODE_0(1U)
996 #define S_ERR_DROPPED_DB 18
997 #define V_ERR_DROPPED_DB(x) ((x) << S_ERR_DROPPED_DB)
998 #define F_ERR_DROPPED_DB V_ERR_DROPPED_DB(1U)
1000 #define S_ERR_DATA_CPL_ON_HIGH_QID1 17
1001 #define V_ERR_DATA_CPL_ON_HIGH_QID1(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID1)
1002 #define F_ERR_DATA_CPL_ON_HIGH_QID1 V_ERR_DATA_CPL_ON_HIGH_QID1(1U)
1004 #define S_ERR_DATA_CPL_ON_HIGH_QID0 16
1005 #define V_ERR_DATA_CPL_ON_HIGH_QID0(x) ((x) << S_ERR_DATA_CPL_ON_HIGH_QID0)
1006 #define F_ERR_DATA_CPL_ON_HIGH_QID0 V_ERR_DATA_CPL_ON_HIGH_QID0(1U)
1008 #define S_ERR_BAD_DB_PIDX3 15
1009 #define V_ERR_BAD_DB_PIDX3(x) ((x) << S_ERR_BAD_DB_PIDX3)
1010 #define F_ERR_BAD_DB_PIDX3 V_ERR_BAD_DB_PIDX3(1U)
1012 #define S_ERR_BAD_DB_PIDX2 14
1013 #define V_ERR_BAD_DB_PIDX2(x) ((x) << S_ERR_BAD_DB_PIDX2)
1014 #define F_ERR_BAD_DB_PIDX2 V_ERR_BAD_DB_PIDX2(1U)
1016 #define S_ERR_BAD_DB_PIDX1 13
1017 #define V_ERR_BAD_DB_PIDX1(x) ((x) << S_ERR_BAD_DB_PIDX1)
1018 #define F_ERR_BAD_DB_PIDX1 V_ERR_BAD_DB_PIDX1(1U)
1020 #define S_ERR_BAD_DB_PIDX0 12
1021 #define V_ERR_BAD_DB_PIDX0(x) ((x) << S_ERR_BAD_DB_PIDX0)
1022 #define F_ERR_BAD_DB_PIDX0 V_ERR_BAD_DB_PIDX0(1U)
1024 #define S_ERR_ING_PCIE_CHAN 11
1025 #define V_ERR_ING_PCIE_CHAN(x) ((x) << S_ERR_ING_PCIE_CHAN)
1026 #define F_ERR_ING_PCIE_CHAN V_ERR_ING_PCIE_CHAN(1U)
1028 #define S_ERR_ING_CTXT_PRIO 10
1029 #define V_ERR_ING_CTXT_PRIO(x) ((x) << S_ERR_ING_CTXT_PRIO)
1030 #define F_ERR_ING_CTXT_PRIO V_ERR_ING_CTXT_PRIO(1U)
1032 #define S_ERR_EGR_CTXT_PRIO 9
1033 #define V_ERR_EGR_CTXT_PRIO(x) ((x) << S_ERR_EGR_CTXT_PRIO)
1034 #define F_ERR_EGR_CTXT_PRIO V_ERR_EGR_CTXT_PRIO(1U)
1036 #define S_DBFIFO_HP_INT 8
1037 #define V_DBFIFO_HP_INT(x) ((x) << S_DBFIFO_HP_INT)
1038 #define F_DBFIFO_HP_INT V_DBFIFO_HP_INT(1U)
1040 #define S_DBFIFO_LP_INT 7
1041 #define V_DBFIFO_LP_INT(x) ((x) << S_DBFIFO_LP_INT)
1042 #define F_DBFIFO_LP_INT V_DBFIFO_LP_INT(1U)
1044 #define S_REG_ADDRESS_ERR 6
1045 #define V_REG_ADDRESS_ERR(x) ((x) << S_REG_ADDRESS_ERR)
1046 #define F_REG_ADDRESS_ERR V_REG_ADDRESS_ERR(1U)
1048 #define S_INGRESS_SIZE_ERR 5
1049 #define V_INGRESS_SIZE_ERR(x) ((x) << S_INGRESS_SIZE_ERR)
1050 #define F_INGRESS_SIZE_ERR V_INGRESS_SIZE_ERR(1U)
1052 #define S_EGRESS_SIZE_ERR 4
1053 #define V_EGRESS_SIZE_ERR(x) ((x) << S_EGRESS_SIZE_ERR)
1054 #define F_EGRESS_SIZE_ERR V_EGRESS_SIZE_ERR(1U)
1056 #define S_ERR_INV_CTXT3 3
1057 #define V_ERR_INV_CTXT3(x) ((x) << S_ERR_INV_CTXT3)
1058 #define F_ERR_INV_CTXT3 V_ERR_INV_CTXT3(1U)
1060 #define S_ERR_INV_CTXT2 2
1061 #define V_ERR_INV_CTXT2(x) ((x) << S_ERR_INV_CTXT2)
1062 #define F_ERR_INV_CTXT2 V_ERR_INV_CTXT2(1U)
1064 #define S_ERR_INV_CTXT1 1
1065 #define V_ERR_INV_CTXT1(x) ((x) << S_ERR_INV_CTXT1)
1066 #define F_ERR_INV_CTXT1 V_ERR_INV_CTXT1(1U)
1068 #define S_ERR_INV_CTXT0 0
1069 #define V_ERR_INV_CTXT0(x) ((x) << S_ERR_INV_CTXT0)
1070 #define F_ERR_INV_CTXT0 V_ERR_INV_CTXT0(1U)
1072 #define A_SGE_INT_ENABLE3 0x1040
1073 #define A_SGE_FL_BUFFER_SIZE0 0x1044
1076 #define M_SIZE 0xfffffffU
1077 #define V_SIZE(x) ((x) << S_SIZE)
1078 #define G_SIZE(x) (((x) >> S_SIZE) & M_SIZE)
1080 #define A_SGE_FL_BUFFER_SIZE1 0x1048
1081 #define A_SGE_FL_BUFFER_SIZE2 0x104c
1082 #define A_SGE_FL_BUFFER_SIZE3 0x1050
1083 #define A_SGE_FL_BUFFER_SIZE4 0x1054
1084 #define A_SGE_FL_BUFFER_SIZE5 0x1058
1085 #define A_SGE_FL_BUFFER_SIZE6 0x105c
1086 #define A_SGE_FL_BUFFER_SIZE7 0x1060
1087 #define A_SGE_FL_BUFFER_SIZE8 0x1064
1088 #define A_SGE_FL_BUFFER_SIZE9 0x1068
1089 #define A_SGE_FL_BUFFER_SIZE10 0x106c
1090 #define A_SGE_FL_BUFFER_SIZE11 0x1070
1091 #define A_SGE_FL_BUFFER_SIZE12 0x1074
1092 #define A_SGE_FL_BUFFER_SIZE13 0x1078
1093 #define A_SGE_FL_BUFFER_SIZE14 0x107c
1094 #define A_SGE_FL_BUFFER_SIZE15 0x1080
1095 #define A_SGE_DBQ_CTXT_BADDR 0x1084
1097 #define S_BASEADDR 3
1098 #define M_BASEADDR 0x1fffffffU
1099 #define V_BASEADDR(x) ((x) << S_BASEADDR)
1100 #define G_BASEADDR(x) (((x) >> S_BASEADDR) & M_BASEADDR)
1102 #define A_SGE_IMSG_CTXT_BADDR 0x1088
1103 #define A_SGE_FLM_CACHE_BADDR 0x108c
1104 #define A_SGE_FLM_CFG 0x1090
1107 #define M_OPMODE 0x3fU
1108 #define V_OPMODE(x) ((x) << S_OPMODE)
1109 #define G_OPMODE(x) (((x) >> S_OPMODE) & M_OPMODE)
1112 #define V_NOHDR(x) ((x) << S_NOHDR)
1113 #define F_NOHDR V_NOHDR(1U)
1115 #define S_CACHEPTRCNT 16
1116 #define M_CACHEPTRCNT 0x3U
1117 #define V_CACHEPTRCNT(x) ((x) << S_CACHEPTRCNT)
1118 #define G_CACHEPTRCNT(x) (((x) >> S_CACHEPTRCNT) & M_CACHEPTRCNT)
1120 #define S_EDRAMPTRCNT 14
1121 #define M_EDRAMPTRCNT 0x3U
1122 #define V_EDRAMPTRCNT(x) ((x) << S_EDRAMPTRCNT)
1123 #define G_EDRAMPTRCNT(x) (((x) >> S_EDRAMPTRCNT) & M_EDRAMPTRCNT)
1125 #define S_HDRSTARTFLQ 11
1126 #define M_HDRSTARTFLQ 0x7U
1127 #define V_HDRSTARTFLQ(x) ((x) << S_HDRSTARTFLQ)
1128 #define G_HDRSTARTFLQ(x) (((x) >> S_HDRSTARTFLQ) & M_HDRSTARTFLQ)
1130 #define S_FETCHTHRESH 6
1131 #define M_FETCHTHRESH 0x1fU
1132 #define V_FETCHTHRESH(x) ((x) << S_FETCHTHRESH)
1133 #define G_FETCHTHRESH(x) (((x) >> S_FETCHTHRESH) & M_FETCHTHRESH)
1135 #define S_CREDITCNT 4
1136 #define M_CREDITCNT 0x3U
1137 #define V_CREDITCNT(x) ((x) << S_CREDITCNT)
1138 #define G_CREDITCNT(x) (((x) >> S_CREDITCNT) & M_CREDITCNT)
1141 #define V_NOEDRAM(x) ((x) << S_NOEDRAM)
1142 #define F_NOEDRAM V_NOEDRAM(1U)
1144 #define S_CREDITCNTPACKING 2
1145 #define M_CREDITCNTPACKING 0x3U
1146 #define V_CREDITCNTPACKING(x) ((x) << S_CREDITCNTPACKING)
1147 #define G_CREDITCNTPACKING(x) (((x) >> S_CREDITCNTPACKING) & M_CREDITCNTPACKING)
1149 #define A_SGE_CONM_CTRL 0x1094
1151 #define S_EGRTHRESHOLD 8
1152 #define M_EGRTHRESHOLD 0x3fU
1153 #define V_EGRTHRESHOLD(x) ((x) << S_EGRTHRESHOLD)
1154 #define G_EGRTHRESHOLD(x) (((x) >> S_EGRTHRESHOLD) & M_EGRTHRESHOLD)
1156 #define S_INGTHRESHOLD 2
1157 #define M_INGTHRESHOLD 0x3fU
1158 #define V_INGTHRESHOLD(x) ((x) << S_INGTHRESHOLD)
1159 #define G_INGTHRESHOLD(x) (((x) >> S_INGTHRESHOLD) & M_INGTHRESHOLD)
1161 #define S_MPS_ENABLE 1
1162 #define V_MPS_ENABLE(x) ((x) << S_MPS_ENABLE)
1163 #define F_MPS_ENABLE V_MPS_ENABLE(1U)
1165 #define S_TP_ENABLE 0
1166 #define V_TP_ENABLE(x) ((x) << S_TP_ENABLE)
1167 #define F_TP_ENABLE V_TP_ENABLE(1U)
1169 #define S_EGRTHRESHOLDPACKING 14
1170 #define M_EGRTHRESHOLDPACKING 0x3fU
1171 #define V_EGRTHRESHOLDPACKING(x) ((x) << S_EGRTHRESHOLDPACKING)
1172 #define G_EGRTHRESHOLDPACKING(x) (((x) >> S_EGRTHRESHOLDPACKING) & M_EGRTHRESHOLDPACKING)
1174 #define A_SGE_TIMESTAMP_LO 0x1098
1175 #define A_SGE_TIMESTAMP_HI 0x109c
1179 #define V_TSOP(x) ((x) << S_TSOP)
1180 #define G_TSOP(x) (((x) >> S_TSOP) & M_TSOP)
1183 #define M_TSVAL 0xfffffffU
1184 #define V_TSVAL(x) ((x) << S_TSVAL)
1185 #define G_TSVAL(x) (((x) >> S_TSVAL) & M_TSVAL)
1187 #define A_SGE_INGRESS_RX_THRESHOLD 0x10a0
1189 #define S_THRESHOLD_0 24
1190 #define M_THRESHOLD_0 0x3fU
1191 #define V_THRESHOLD_0(x) ((x) << S_THRESHOLD_0)
1192 #define G_THRESHOLD_0(x) (((x) >> S_THRESHOLD_0) & M_THRESHOLD_0)
1194 #define S_THRESHOLD_1 16
1195 #define M_THRESHOLD_1 0x3fU
1196 #define V_THRESHOLD_1(x) ((x) << S_THRESHOLD_1)
1197 #define G_THRESHOLD_1(x) (((x) >> S_THRESHOLD_1) & M_THRESHOLD_1)
1199 #define S_THRESHOLD_2 8
1200 #define M_THRESHOLD_2 0x3fU
1201 #define V_THRESHOLD_2(x) ((x) << S_THRESHOLD_2)
1202 #define G_THRESHOLD_2(x) (((x) >> S_THRESHOLD_2) & M_THRESHOLD_2)
1204 #define S_THRESHOLD_3 0
1205 #define M_THRESHOLD_3 0x3fU
1206 #define V_THRESHOLD_3(x) ((x) << S_THRESHOLD_3)
1207 #define G_THRESHOLD_3(x) (((x) >> S_THRESHOLD_3) & M_THRESHOLD_3)
1209 #define A_SGE_DBFIFO_STATUS 0x10a4
1211 #define S_HP_INT_THRESH 28
1212 #define M_HP_INT_THRESH 0xfU
1213 #define V_HP_INT_THRESH(x) ((x) << S_HP_INT_THRESH)
1214 #define G_HP_INT_THRESH(x) (((x) >> S_HP_INT_THRESH) & M_HP_INT_THRESH)
1216 #define S_HP_COUNT 16
1217 #define M_HP_COUNT 0x7ffU
1218 #define V_HP_COUNT(x) ((x) << S_HP_COUNT)
1219 #define G_HP_COUNT(x) (((x) >> S_HP_COUNT) & M_HP_COUNT)
1221 #define S_LP_INT_THRESH 12
1222 #define M_LP_INT_THRESH 0xfU
1223 #define V_LP_INT_THRESH(x) ((x) << S_LP_INT_THRESH)
1224 #define G_LP_INT_THRESH(x) (((x) >> S_LP_INT_THRESH) & M_LP_INT_THRESH)
1226 #define S_LP_COUNT 0
1227 #define M_LP_COUNT 0x7ffU
1228 #define V_LP_COUNT(x) ((x) << S_LP_COUNT)
1229 #define G_LP_COUNT(x) (((x) >> S_LP_COUNT) & M_LP_COUNT)
1231 #define S_BAR2VALID 31
1232 #define V_BAR2VALID(x) ((x) << S_BAR2VALID)
1233 #define F_BAR2VALID V_BAR2VALID(1U)
1235 #define S_BAR2FULL 30
1236 #define V_BAR2FULL(x) ((x) << S_BAR2FULL)
1237 #define F_BAR2FULL V_BAR2FULL(1U)
1239 #define S_LP_INT_THRESH_T5 18
1240 #define M_LP_INT_THRESH_T5 0xfffU
1241 #define V_LP_INT_THRESH_T5(x) ((x) << S_LP_INT_THRESH_T5)
1242 #define G_LP_INT_THRESH_T5(x) (((x) >> S_LP_INT_THRESH_T5) & M_LP_INT_THRESH_T5)
1244 #define S_LP_COUNT_T5 0
1245 #define M_LP_COUNT_T5 0x3ffffU
1246 #define V_LP_COUNT_T5(x) ((x) << S_LP_COUNT_T5)
1247 #define G_LP_COUNT_T5(x) (((x) >> S_LP_COUNT_T5) & M_LP_COUNT_T5)
1249 #define A_SGE_DOORBELL_CONTROL 0x10a8
1251 #define S_HINTDEPTHCTL 27
1252 #define M_HINTDEPTHCTL 0x1fU
1253 #define V_HINTDEPTHCTL(x) ((x) << S_HINTDEPTHCTL)
1254 #define G_HINTDEPTHCTL(x) (((x) >> S_HINTDEPTHCTL) & M_HINTDEPTHCTL)
1256 #define S_NOCOALESCE 26
1257 #define V_NOCOALESCE(x) ((x) << S_NOCOALESCE)
1258 #define F_NOCOALESCE V_NOCOALESCE(1U)
1260 #define S_HP_WEIGHT 24
1261 #define M_HP_WEIGHT 0x3U
1262 #define V_HP_WEIGHT(x) ((x) << S_HP_WEIGHT)
1263 #define G_HP_WEIGHT(x) (((x) >> S_HP_WEIGHT) & M_HP_WEIGHT)
1265 #define S_HP_DISABLE 23
1266 #define V_HP_DISABLE(x) ((x) << S_HP_DISABLE)
1267 #define F_HP_DISABLE V_HP_DISABLE(1U)
1269 #define S_FORCEUSERDBTOLP 22
1270 #define V_FORCEUSERDBTOLP(x) ((x) << S_FORCEUSERDBTOLP)
1271 #define F_FORCEUSERDBTOLP V_FORCEUSERDBTOLP(1U)
1273 #define S_FORCEVFPF0DBTOLP 21
1274 #define V_FORCEVFPF0DBTOLP(x) ((x) << S_FORCEVFPF0DBTOLP)
1275 #define F_FORCEVFPF0DBTOLP V_FORCEVFPF0DBTOLP(1U)
1277 #define S_FORCEVFPF1DBTOLP 20
1278 #define V_FORCEVFPF1DBTOLP(x) ((x) << S_FORCEVFPF1DBTOLP)
1279 #define F_FORCEVFPF1DBTOLP V_FORCEVFPF1DBTOLP(1U)
1281 #define S_FORCEVFPF2DBTOLP 19
1282 #define V_FORCEVFPF2DBTOLP(x) ((x) << S_FORCEVFPF2DBTOLP)
1283 #define F_FORCEVFPF2DBTOLP V_FORCEVFPF2DBTOLP(1U)
1285 #define S_FORCEVFPF3DBTOLP 18
1286 #define V_FORCEVFPF3DBTOLP(x) ((x) << S_FORCEVFPF3DBTOLP)
1287 #define F_FORCEVFPF3DBTOLP V_FORCEVFPF3DBTOLP(1U)
1289 #define S_FORCEVFPF4DBTOLP 17
1290 #define V_FORCEVFPF4DBTOLP(x) ((x) << S_FORCEVFPF4DBTOLP)
1291 #define F_FORCEVFPF4DBTOLP V_FORCEVFPF4DBTOLP(1U)
1293 #define S_FORCEVFPF5DBTOLP 16
1294 #define V_FORCEVFPF5DBTOLP(x) ((x) << S_FORCEVFPF5DBTOLP)
1295 #define F_FORCEVFPF5DBTOLP V_FORCEVFPF5DBTOLP(1U)
1297 #define S_FORCEVFPF6DBTOLP 15
1298 #define V_FORCEVFPF6DBTOLP(x) ((x) << S_FORCEVFPF6DBTOLP)
1299 #define F_FORCEVFPF6DBTOLP V_FORCEVFPF6DBTOLP(1U)
1301 #define S_FORCEVFPF7DBTOLP 14
1302 #define V_FORCEVFPF7DBTOLP(x) ((x) << S_FORCEVFPF7DBTOLP)
1303 #define F_FORCEVFPF7DBTOLP V_FORCEVFPF7DBTOLP(1U)
1305 #define S_ENABLE_DROP 13
1306 #define V_ENABLE_DROP(x) ((x) << S_ENABLE_DROP)
1307 #define F_ENABLE_DROP V_ENABLE_DROP(1U)
1309 #define S_DROP_TIMEOUT 1
1310 #define M_DROP_TIMEOUT 0xfffU
1311 #define V_DROP_TIMEOUT(x) ((x) << S_DROP_TIMEOUT)
1312 #define G_DROP_TIMEOUT(x) (((x) >> S_DROP_TIMEOUT) & M_DROP_TIMEOUT)
1314 #define S_DROPPED_DB 0
1315 #define V_DROPPED_DB(x) ((x) << S_DROPPED_DB)
1316 #define F_DROPPED_DB V_DROPPED_DB(1U)
1318 #define A_SGE_DROPPED_DOORBELL 0x10ac
1319 #define A_SGE_DOORBELL_THROTTLE_CONTROL 0x10b0
1321 #define S_THROTTLE_COUNT 1
1322 #define M_THROTTLE_COUNT 0xfffU
1323 #define V_THROTTLE_COUNT(x) ((x) << S_THROTTLE_COUNT)
1324 #define G_THROTTLE_COUNT(x) (((x) >> S_THROTTLE_COUNT) & M_THROTTLE_COUNT)
1326 #define S_THROTTLE_ENABLE 0
1327 #define V_THROTTLE_ENABLE(x) ((x) << S_THROTTLE_ENABLE)
1328 #define F_THROTTLE_ENABLE V_THROTTLE_ENABLE(1U)
1330 #define S_BAR2THROTTLECOUNT 16
1331 #define M_BAR2THROTTLECOUNT 0xffU
1332 #define V_BAR2THROTTLECOUNT(x) ((x) << S_BAR2THROTTLECOUNT)
1333 #define G_BAR2THROTTLECOUNT(x) (((x) >> S_BAR2THROTTLECOUNT) & M_BAR2THROTTLECOUNT)
1335 #define S_CLRCOALESCEDISABLE 15
1336 #define V_CLRCOALESCEDISABLE(x) ((x) << S_CLRCOALESCEDISABLE)
1337 #define F_CLRCOALESCEDISABLE V_CLRCOALESCEDISABLE(1U)
1339 #define S_OPENBAR2GATEONCE 14
1340 #define V_OPENBAR2GATEONCE(x) ((x) << S_OPENBAR2GATEONCE)
1341 #define F_OPENBAR2GATEONCE V_OPENBAR2GATEONCE(1U)
1343 #define S_FORCEOPENBAR2GATE 13
1344 #define V_FORCEOPENBAR2GATE(x) ((x) << S_FORCEOPENBAR2GATE)
1345 #define F_FORCEOPENBAR2GATE V_FORCEOPENBAR2GATE(1U)
1347 #define A_SGE_ITP_CONTROL 0x10b4
1349 #define S_CRITICAL_TIME 10
1350 #define M_CRITICAL_TIME 0x7fffU
1351 #define V_CRITICAL_TIME(x) ((x) << S_CRITICAL_TIME)
1352 #define G_CRITICAL_TIME(x) (((x) >> S_CRITICAL_TIME) & M_CRITICAL_TIME)
1354 #define S_LL_EMPTY 4
1355 #define M_LL_EMPTY 0x3fU
1356 #define V_LL_EMPTY(x) ((x) << S_LL_EMPTY)
1357 #define G_LL_EMPTY(x) (((x) >> S_LL_EMPTY) & M_LL_EMPTY)
1359 #define S_LL_READ_WAIT_DISABLE 0
1360 #define V_LL_READ_WAIT_DISABLE(x) ((x) << S_LL_READ_WAIT_DISABLE)
1361 #define F_LL_READ_WAIT_DISABLE V_LL_READ_WAIT_DISABLE(1U)
1363 #define A_SGE_TIMER_VALUE_0_AND_1 0x10b8
1365 #define S_TIMERVALUE0 16
1366 #define M_TIMERVALUE0 0xffffU
1367 #define V_TIMERVALUE0(x) ((x) << S_TIMERVALUE0)
1368 #define G_TIMERVALUE0(x) (((x) >> S_TIMERVALUE0) & M_TIMERVALUE0)
1370 #define S_TIMERVALUE1 0
1371 #define M_TIMERVALUE1 0xffffU
1372 #define V_TIMERVALUE1(x) ((x) << S_TIMERVALUE1)
1373 #define G_TIMERVALUE1(x) (((x) >> S_TIMERVALUE1) & M_TIMERVALUE1)
1375 #define A_SGE_TIMER_VALUE_2_AND_3 0x10bc
1377 #define S_TIMERVALUE2 16
1378 #define M_TIMERVALUE2 0xffffU
1379 #define V_TIMERVALUE2(x) ((x) << S_TIMERVALUE2)
1380 #define G_TIMERVALUE2(x) (((x) >> S_TIMERVALUE2) & M_TIMERVALUE2)
1382 #define S_TIMERVALUE3 0
1383 #define M_TIMERVALUE3 0xffffU
1384 #define V_TIMERVALUE3(x) ((x) << S_TIMERVALUE3)
1385 #define G_TIMERVALUE3(x) (((x) >> S_TIMERVALUE3) & M_TIMERVALUE3)
1387 #define A_SGE_TIMER_VALUE_4_AND_5 0x10c0
1389 #define S_TIMERVALUE4 16
1390 #define M_TIMERVALUE4 0xffffU
1391 #define V_TIMERVALUE4(x) ((x) << S_TIMERVALUE4)
1392 #define G_TIMERVALUE4(x) (((x) >> S_TIMERVALUE4) & M_TIMERVALUE4)
1394 #define S_TIMERVALUE5 0
1395 #define M_TIMERVALUE5 0xffffU
1396 #define V_TIMERVALUE5(x) ((x) << S_TIMERVALUE5)
1397 #define G_TIMERVALUE5(x) (((x) >> S_TIMERVALUE5) & M_TIMERVALUE5)
1399 #define A_SGE_PD_RSP_CREDIT01 0x10c4
1401 #define S_RSPCREDITEN0 31
1402 #define V_RSPCREDITEN0(x) ((x) << S_RSPCREDITEN0)
1403 #define F_RSPCREDITEN0 V_RSPCREDITEN0(1U)
1405 #define S_MAXTAG0 24
1406 #define M_MAXTAG0 0x7fU
1407 #define V_MAXTAG0(x) ((x) << S_MAXTAG0)
1408 #define G_MAXTAG0(x) (((x) >> S_MAXTAG0) & M_MAXTAG0)
1410 #define S_MAXRSPCNT0 16
1411 #define M_MAXRSPCNT0 0xffU
1412 #define V_MAXRSPCNT0(x) ((x) << S_MAXRSPCNT0)
1413 #define G_MAXRSPCNT0(x) (((x) >> S_MAXRSPCNT0) & M_MAXRSPCNT0)
1415 #define S_RSPCREDITEN1 15
1416 #define V_RSPCREDITEN1(x) ((x) << S_RSPCREDITEN1)
1417 #define F_RSPCREDITEN1 V_RSPCREDITEN1(1U)
1420 #define M_MAXTAG1 0x7fU
1421 #define V_MAXTAG1(x) ((x) << S_MAXTAG1)
1422 #define G_MAXTAG1(x) (((x) >> S_MAXTAG1) & M_MAXTAG1)
1424 #define S_MAXRSPCNT1 0
1425 #define M_MAXRSPCNT1 0xffU
1426 #define V_MAXRSPCNT1(x) ((x) << S_MAXRSPCNT1)
1427 #define G_MAXRSPCNT1(x) (((x) >> S_MAXRSPCNT1) & M_MAXRSPCNT1)
1429 #define A_SGE_PD_RSP_CREDIT23 0x10c8
1431 #define S_RSPCREDITEN2 31
1432 #define V_RSPCREDITEN2(x) ((x) << S_RSPCREDITEN2)
1433 #define F_RSPCREDITEN2 V_RSPCREDITEN2(1U)
1435 #define S_MAXTAG2 24
1436 #define M_MAXTAG2 0x7fU
1437 #define V_MAXTAG2(x) ((x) << S_MAXTAG2)
1438 #define G_MAXTAG2(x) (((x) >> S_MAXTAG2) & M_MAXTAG2)
1440 #define S_MAXRSPCNT2 16
1441 #define M_MAXRSPCNT2 0xffU
1442 #define V_MAXRSPCNT2(x) ((x) << S_MAXRSPCNT2)
1443 #define G_MAXRSPCNT2(x) (((x) >> S_MAXRSPCNT2) & M_MAXRSPCNT2)
1445 #define S_RSPCREDITEN3 15
1446 #define V_RSPCREDITEN3(x) ((x) << S_RSPCREDITEN3)
1447 #define F_RSPCREDITEN3 V_RSPCREDITEN3(1U)
1450 #define M_MAXTAG3 0x7fU
1451 #define V_MAXTAG3(x) ((x) << S_MAXTAG3)
1452 #define G_MAXTAG3(x) (((x) >> S_MAXTAG3) & M_MAXTAG3)
1454 #define S_MAXRSPCNT3 0
1455 #define M_MAXRSPCNT3 0xffU
1456 #define V_MAXRSPCNT3(x) ((x) << S_MAXRSPCNT3)
1457 #define G_MAXRSPCNT3(x) (((x) >> S_MAXRSPCNT3) & M_MAXRSPCNT3)
1459 #define A_SGE_DEBUG_INDEX 0x10cc
1460 #define A_SGE_DEBUG_DATA_HIGH 0x10d0
1461 #define A_SGE_DEBUG_DATA_LOW 0x10d4
1462 #define A_SGE_REVISION 0x10d8
1463 #define A_SGE_INT_CAUSE4 0x10dc
1465 #define S_ERR_BAD_UPFL_INC_CREDIT3 8
1466 #define V_ERR_BAD_UPFL_INC_CREDIT3(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT3)
1467 #define F_ERR_BAD_UPFL_INC_CREDIT3 V_ERR_BAD_UPFL_INC_CREDIT3(1U)
1469 #define S_ERR_BAD_UPFL_INC_CREDIT2 7
1470 #define V_ERR_BAD_UPFL_INC_CREDIT2(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT2)
1471 #define F_ERR_BAD_UPFL_INC_CREDIT2 V_ERR_BAD_UPFL_INC_CREDIT2(1U)
1473 #define S_ERR_BAD_UPFL_INC_CREDIT1 6
1474 #define V_ERR_BAD_UPFL_INC_CREDIT1(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT1)
1475 #define F_ERR_BAD_UPFL_INC_CREDIT1 V_ERR_BAD_UPFL_INC_CREDIT1(1U)
1477 #define S_ERR_BAD_UPFL_INC_CREDIT0 5
1478 #define V_ERR_BAD_UPFL_INC_CREDIT0(x) ((x) << S_ERR_BAD_UPFL_INC_CREDIT0)
1479 #define F_ERR_BAD_UPFL_INC_CREDIT0 V_ERR_BAD_UPFL_INC_CREDIT0(1U)
1481 #define S_ERR_PHYSADDR_LEN0_IDMA1 4
1482 #define V_ERR_PHYSADDR_LEN0_IDMA1(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA1)
1483 #define F_ERR_PHYSADDR_LEN0_IDMA1 V_ERR_PHYSADDR_LEN0_IDMA1(1U)
1485 #define S_ERR_PHYSADDR_LEN0_IDMA0 3
1486 #define V_ERR_PHYSADDR_LEN0_IDMA0(x) ((x) << S_ERR_PHYSADDR_LEN0_IDMA0)
1487 #define F_ERR_PHYSADDR_LEN0_IDMA0 V_ERR_PHYSADDR_LEN0_IDMA0(1U)
1489 #define S_ERR_FLM_INVALID_PKT_DROP1 2
1490 #define V_ERR_FLM_INVALID_PKT_DROP1(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP1)
1491 #define F_ERR_FLM_INVALID_PKT_DROP1 V_ERR_FLM_INVALID_PKT_DROP1(1U)
1493 #define S_ERR_FLM_INVALID_PKT_DROP0 1
1494 #define V_ERR_FLM_INVALID_PKT_DROP0(x) ((x) << S_ERR_FLM_INVALID_PKT_DROP0)
1495 #define F_ERR_FLM_INVALID_PKT_DROP0 V_ERR_FLM_INVALID_PKT_DROP0(1U)
1497 #define S_ERR_UNEXPECTED_TIMER 0
1498 #define V_ERR_UNEXPECTED_TIMER(x) ((x) << S_ERR_UNEXPECTED_TIMER)
1499 #define F_ERR_UNEXPECTED_TIMER V_ERR_UNEXPECTED_TIMER(1U)
1501 #define S_BAR2_EGRESS_LEN_OR_ADDR_ERR 29
1502 #define V_BAR2_EGRESS_LEN_OR_ADDR_ERR(x) ((x) << S_BAR2_EGRESS_LEN_OR_ADDR_ERR)
1503 #define F_BAR2_EGRESS_LEN_OR_ADDR_ERR V_BAR2_EGRESS_LEN_OR_ADDR_ERR(1U)
1505 #define S_ERR_CPL_EXCEED_MAX_IQE_SIZE1 28
1506 #define V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE1)
1507 #define F_ERR_CPL_EXCEED_MAX_IQE_SIZE1 V_ERR_CPL_EXCEED_MAX_IQE_SIZE1(1U)
1509 #define S_ERR_CPL_EXCEED_MAX_IQE_SIZE0 27
1510 #define V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(x) ((x) << S_ERR_CPL_EXCEED_MAX_IQE_SIZE0)
1511 #define F_ERR_CPL_EXCEED_MAX_IQE_SIZE0 V_ERR_CPL_EXCEED_MAX_IQE_SIZE0(1U)
1513 #define S_ERR_WR_LEN_TOO_LARGE3 26
1514 #define V_ERR_WR_LEN_TOO_LARGE3(x) ((x) << S_ERR_WR_LEN_TOO_LARGE3)
1515 #define F_ERR_WR_LEN_TOO_LARGE3 V_ERR_WR_LEN_TOO_LARGE3(1U)
1517 #define S_ERR_WR_LEN_TOO_LARGE2 25
1518 #define V_ERR_WR_LEN_TOO_LARGE2(x) ((x) << S_ERR_WR_LEN_TOO_LARGE2)
1519 #define F_ERR_WR_LEN_TOO_LARGE2 V_ERR_WR_LEN_TOO_LARGE2(1U)
1521 #define S_ERR_WR_LEN_TOO_LARGE1 24
1522 #define V_ERR_WR_LEN_TOO_LARGE1(x) ((x) << S_ERR_WR_LEN_TOO_LARGE1)
1523 #define F_ERR_WR_LEN_TOO_LARGE1 V_ERR_WR_LEN_TOO_LARGE1(1U)
1525 #define S_ERR_WR_LEN_TOO_LARGE0 23
1526 #define V_ERR_WR_LEN_TOO_LARGE0(x) ((x) << S_ERR_WR_LEN_TOO_LARGE0)
1527 #define F_ERR_WR_LEN_TOO_LARGE0 V_ERR_WR_LEN_TOO_LARGE0(1U)
1529 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL3 22
1530 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL3)
1531 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL3 V_ERR_LARGE_MINFETCH_WITH_TXCOAL3(1U)
1533 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL2 21
1534 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL2)
1535 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL2 V_ERR_LARGE_MINFETCH_WITH_TXCOAL2(1U)
1537 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL1 20
1538 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL1)
1539 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL1 V_ERR_LARGE_MINFETCH_WITH_TXCOAL1(1U)
1541 #define S_ERR_LARGE_MINFETCH_WITH_TXCOAL0 19
1542 #define V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(x) ((x) << S_ERR_LARGE_MINFETCH_WITH_TXCOAL0)
1543 #define F_ERR_LARGE_MINFETCH_WITH_TXCOAL0 V_ERR_LARGE_MINFETCH_WITH_TXCOAL0(1U)
1545 #define S_COAL_WITH_HP_DISABLE_ERR 18
1546 #define V_COAL_WITH_HP_DISABLE_ERR(x) ((x) << S_COAL_WITH_HP_DISABLE_ERR)
1547 #define F_COAL_WITH_HP_DISABLE_ERR V_COAL_WITH_HP_DISABLE_ERR(1U)
1549 #define S_BAR2_EGRESS_COAL0_ERR 17
1550 #define V_BAR2_EGRESS_COAL0_ERR(x) ((x) << S_BAR2_EGRESS_COAL0_ERR)
1551 #define F_BAR2_EGRESS_COAL0_ERR V_BAR2_EGRESS_COAL0_ERR(1U)
1553 #define S_BAR2_EGRESS_SIZE_ERR 16
1554 #define V_BAR2_EGRESS_SIZE_ERR(x) ((x) << S_BAR2_EGRESS_SIZE_ERR)
1555 #define F_BAR2_EGRESS_SIZE_ERR V_BAR2_EGRESS_SIZE_ERR(1U)
1557 #define S_FLM_PC_RSP_ERR 15
1558 #define V_FLM_PC_RSP_ERR(x) ((x) << S_FLM_PC_RSP_ERR)
1559 #define F_FLM_PC_RSP_ERR V_FLM_PC_RSP_ERR(1U)
1561 #define S_DBFIFO_HP_INT_LOW 14
1562 #define V_DBFIFO_HP_INT_LOW(x) ((x) << S_DBFIFO_HP_INT_LOW)
1563 #define F_DBFIFO_HP_INT_LOW V_DBFIFO_HP_INT_LOW(1U)
1565 #define S_DBFIFO_LP_INT_LOW 13
1566 #define V_DBFIFO_LP_INT_LOW(x) ((x) << S_DBFIFO_LP_INT_LOW)
1567 #define F_DBFIFO_LP_INT_LOW V_DBFIFO_LP_INT_LOW(1U)
1569 #define S_DBFIFO_FL_INT_LOW 12
1570 #define V_DBFIFO_FL_INT_LOW(x) ((x) << S_DBFIFO_FL_INT_LOW)
1571 #define F_DBFIFO_FL_INT_LOW V_DBFIFO_FL_INT_LOW(1U)
1573 #define S_DBFIFO_FL_INT 11
1574 #define V_DBFIFO_FL_INT(x) ((x) << S_DBFIFO_FL_INT)
1575 #define F_DBFIFO_FL_INT V_DBFIFO_FL_INT(1U)
1577 #define S_ERR_RX_CPL_PACKET_SIZE1 10
1578 #define V_ERR_RX_CPL_PACKET_SIZE1(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE1)
1579 #define F_ERR_RX_CPL_PACKET_SIZE1 V_ERR_RX_CPL_PACKET_SIZE1(1U)
1581 #define S_ERR_RX_CPL_PACKET_SIZE0 9
1582 #define V_ERR_RX_CPL_PACKET_SIZE0(x) ((x) << S_ERR_RX_CPL_PACKET_SIZE0)
1583 #define F_ERR_RX_CPL_PACKET_SIZE0 V_ERR_RX_CPL_PACKET_SIZE0(1U)
1585 #define A_SGE_INT_ENABLE4 0x10e0
1586 #define A_SGE_STAT_TOTAL 0x10e4
1587 #define A_SGE_STAT_MATCH 0x10e8
1588 #define A_SGE_STAT_CFG 0x10ec
1590 #define S_ITPOPMODE 8
1591 #define V_ITPOPMODE(x) ((x) << S_ITPOPMODE)
1592 #define F_ITPOPMODE V_ITPOPMODE(1U)
1594 #define S_EGRCTXTOPMODE 6
1595 #define M_EGRCTXTOPMODE 0x3U
1596 #define V_EGRCTXTOPMODE(x) ((x) << S_EGRCTXTOPMODE)
1597 #define G_EGRCTXTOPMODE(x) (((x) >> S_EGRCTXTOPMODE) & M_EGRCTXTOPMODE)
1599 #define S_INGCTXTOPMODE 4
1600 #define M_INGCTXTOPMODE 0x3U
1601 #define V_INGCTXTOPMODE(x) ((x) << S_INGCTXTOPMODE)
1602 #define G_INGCTXTOPMODE(x) (((x) >> S_INGCTXTOPMODE) & M_INGCTXTOPMODE)
1604 #define S_STATMODE 2
1605 #define M_STATMODE 0x3U
1606 #define V_STATMODE(x) ((x) << S_STATMODE)
1607 #define G_STATMODE(x) (((x) >> S_STATMODE) & M_STATMODE)
1609 #define S_STATSOURCE 0
1610 #define M_STATSOURCE 0x3U
1611 #define V_STATSOURCE(x) ((x) << S_STATSOURCE)
1612 #define G_STATSOURCE(x) (((x) >> S_STATSOURCE) & M_STATSOURCE)
1614 #define S_STATSOURCE_T5 9
1615 #define M_STATSOURCE_T5 0xfU
1616 #define V_STATSOURCE_T5(x) ((x) << S_STATSOURCE_T5)
1617 #define G_STATSOURCE_T5(x) (((x) >> S_STATSOURCE_T5) & M_STATSOURCE_T5)
1619 #define A_SGE_HINT_CFG 0x10f0
1621 #define S_HINTSALLOWEDNOHDR 6
1622 #define M_HINTSALLOWEDNOHDR 0x3fU
1623 #define V_HINTSALLOWEDNOHDR(x) ((x) << S_HINTSALLOWEDNOHDR)
1624 #define G_HINTSALLOWEDNOHDR(x) (((x) >> S_HINTSALLOWEDNOHDR) & M_HINTSALLOWEDNOHDR)
1626 #define S_HINTSALLOWEDHDR 0
1627 #define M_HINTSALLOWEDHDR 0x3fU
1628 #define V_HINTSALLOWEDHDR(x) ((x) << S_HINTSALLOWEDHDR)
1629 #define G_HINTSALLOWEDHDR(x) (((x) >> S_HINTSALLOWEDHDR) & M_HINTSALLOWEDHDR)
1631 #define S_UPCUTOFFTHRESHLP 12
1632 #define M_UPCUTOFFTHRESHLP 0x7ffU
1633 #define V_UPCUTOFFTHRESHLP(x) ((x) << S_UPCUTOFFTHRESHLP)
1634 #define G_UPCUTOFFTHRESHLP(x) (((x) >> S_UPCUTOFFTHRESHLP) & M_UPCUTOFFTHRESHLP)
1636 #define A_SGE_INGRESS_QUEUES_PER_PAGE_PF 0x10f4
1637 #define A_SGE_INGRESS_QUEUES_PER_PAGE_VF 0x10f8
1638 #define A_SGE_PD_WRR_CONFIG 0x10fc
1640 #define S_EDMA_WEIGHT 0
1641 #define M_EDMA_WEIGHT 0x3fU
1642 #define V_EDMA_WEIGHT(x) ((x) << S_EDMA_WEIGHT)
1643 #define G_EDMA_WEIGHT(x) (((x) >> S_EDMA_WEIGHT) & M_EDMA_WEIGHT)
1645 #define A_SGE_ERROR_STATS 0x1100
1647 #define S_UNCAPTURED_ERROR 18
1648 #define V_UNCAPTURED_ERROR(x) ((x) << S_UNCAPTURED_ERROR)
1649 #define F_UNCAPTURED_ERROR V_UNCAPTURED_ERROR(1U)
1651 #define S_ERROR_QID_VALID 17
1652 #define V_ERROR_QID_VALID(x) ((x) << S_ERROR_QID_VALID)
1653 #define F_ERROR_QID_VALID V_ERROR_QID_VALID(1U)
1655 #define S_ERROR_QID 0
1656 #define M_ERROR_QID 0x1ffffU
1657 #define V_ERROR_QID(x) ((x) << S_ERROR_QID)
1658 #define G_ERROR_QID(x) (((x) >> S_ERROR_QID) & M_ERROR_QID)
1660 #define S_CAUSE_REGISTER 24
1661 #define M_CAUSE_REGISTER 0x7U
1662 #define V_CAUSE_REGISTER(x) ((x) << S_CAUSE_REGISTER)
1663 #define G_CAUSE_REGISTER(x) (((x) >> S_CAUSE_REGISTER) & M_CAUSE_REGISTER)
1665 #define S_CAUSE_BIT 19
1666 #define M_CAUSE_BIT 0x1fU
1667 #define V_CAUSE_BIT(x) ((x) << S_CAUSE_BIT)
1668 #define G_CAUSE_BIT(x) (((x) >> S_CAUSE_BIT) & M_CAUSE_BIT)
1670 #define A_SGE_SHARED_TAG_CHAN_CFG 0x1104
1672 #define S_MINTAG3 24
1673 #define M_MINTAG3 0xffU
1674 #define V_MINTAG3(x) ((x) << S_MINTAG3)
1675 #define G_MINTAG3(x) (((x) >> S_MINTAG3) & M_MINTAG3)
1677 #define S_MINTAG2 16
1678 #define M_MINTAG2 0xffU
1679 #define V_MINTAG2(x) ((x) << S_MINTAG2)
1680 #define G_MINTAG2(x) (((x) >> S_MINTAG2) & M_MINTAG2)
1683 #define M_MINTAG1 0xffU
1684 #define V_MINTAG1(x) ((x) << S_MINTAG1)
1685 #define G_MINTAG1(x) (((x) >> S_MINTAG1) & M_MINTAG1)
1688 #define M_MINTAG0 0xffU
1689 #define V_MINTAG0(x) ((x) << S_MINTAG0)
1690 #define G_MINTAG0(x) (((x) >> S_MINTAG0) & M_MINTAG0)
1692 #define A_SGE_SHARED_TAG_POOL_CFG 0x1108
1694 #define S_TAGPOOLTOTAL 0
1695 #define M_TAGPOOLTOTAL 0xffU
1696 #define V_TAGPOOLTOTAL(x) ((x) << S_TAGPOOLTOTAL)
1697 #define G_TAGPOOLTOTAL(x) (((x) >> S_TAGPOOLTOTAL) & M_TAGPOOLTOTAL)
1699 #define A_SGE_INT_CAUSE5 0x110c
1701 #define S_ERR_T_RXCRC 31
1702 #define V_ERR_T_RXCRC(x) ((x) << S_ERR_T_RXCRC)
1703 #define F_ERR_T_RXCRC V_ERR_T_RXCRC(1U)
1705 #define S_PERR_MC_RSPDATA 30
1706 #define V_PERR_MC_RSPDATA(x) ((x) << S_PERR_MC_RSPDATA)
1707 #define F_PERR_MC_RSPDATA V_PERR_MC_RSPDATA(1U)
1709 #define S_PERR_PC_RSPDATA 29
1710 #define V_PERR_PC_RSPDATA(x) ((x) << S_PERR_PC_RSPDATA)
1711 #define F_PERR_PC_RSPDATA V_PERR_PC_RSPDATA(1U)
1713 #define S_PERR_PD_RDRSPDATA 28
1714 #define V_PERR_PD_RDRSPDATA(x) ((x) << S_PERR_PD_RDRSPDATA)
1715 #define F_PERR_PD_RDRSPDATA V_PERR_PD_RDRSPDATA(1U)
1717 #define S_PERR_U_RXDATA 27
1718 #define V_PERR_U_RXDATA(x) ((x) << S_PERR_U_RXDATA)
1719 #define F_PERR_U_RXDATA V_PERR_U_RXDATA(1U)
1721 #define S_PERR_UD_RXDATA 26
1722 #define V_PERR_UD_RXDATA(x) ((x) << S_PERR_UD_RXDATA)
1723 #define F_PERR_UD_RXDATA V_PERR_UD_RXDATA(1U)
1725 #define S_PERR_UP_DATA 25
1726 #define V_PERR_UP_DATA(x) ((x) << S_PERR_UP_DATA)
1727 #define F_PERR_UP_DATA V_PERR_UP_DATA(1U)
1729 #define S_PERR_CIM2SGE_RXDATA 24
1730 #define V_PERR_CIM2SGE_RXDATA(x) ((x) << S_PERR_CIM2SGE_RXDATA)
1731 #define F_PERR_CIM2SGE_RXDATA V_PERR_CIM2SGE_RXDATA(1U)
1733 #define S_PERR_HINT_DELAY_FIFO1_T5 23
1734 #define V_PERR_HINT_DELAY_FIFO1_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO1_T5)
1735 #define F_PERR_HINT_DELAY_FIFO1_T5 V_PERR_HINT_DELAY_FIFO1_T5(1U)
1737 #define S_PERR_HINT_DELAY_FIFO0_T5 22
1738 #define V_PERR_HINT_DELAY_FIFO0_T5(x) ((x) << S_PERR_HINT_DELAY_FIFO0_T5)
1739 #define F_PERR_HINT_DELAY_FIFO0_T5 V_PERR_HINT_DELAY_FIFO0_T5(1U)
1741 #define S_PERR_IMSG_PD_FIFO_T5 21
1742 #define V_PERR_IMSG_PD_FIFO_T5(x) ((x) << S_PERR_IMSG_PD_FIFO_T5)
1743 #define F_PERR_IMSG_PD_FIFO_T5 V_PERR_IMSG_PD_FIFO_T5(1U)
1745 #define S_PERR_ULPTX_FIFO1_T5 20
1746 #define V_PERR_ULPTX_FIFO1_T5(x) ((x) << S_PERR_ULPTX_FIFO1_T5)
1747 #define F_PERR_ULPTX_FIFO1_T5 V_PERR_ULPTX_FIFO1_T5(1U)
1749 #define S_PERR_ULPTX_FIFO0_T5 19
1750 #define V_PERR_ULPTX_FIFO0_T5(x) ((x) << S_PERR_ULPTX_FIFO0_T5)
1751 #define F_PERR_ULPTX_FIFO0_T5 V_PERR_ULPTX_FIFO0_T5(1U)
1753 #define S_PERR_IDMA2IMSG_FIFO1_T5 18
1754 #define V_PERR_IDMA2IMSG_FIFO1_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO1_T5)
1755 #define F_PERR_IDMA2IMSG_FIFO1_T5 V_PERR_IDMA2IMSG_FIFO1_T5(1U)
1757 #define S_PERR_IDMA2IMSG_FIFO0_T5 17
1758 #define V_PERR_IDMA2IMSG_FIFO0_T5(x) ((x) << S_PERR_IDMA2IMSG_FIFO0_T5)
1759 #define F_PERR_IDMA2IMSG_FIFO0_T5 V_PERR_IDMA2IMSG_FIFO0_T5(1U)
1761 #define S_PERR_POINTER_DATA_FIFO0 16
1762 #define V_PERR_POINTER_DATA_FIFO0(x) ((x) << S_PERR_POINTER_DATA_FIFO0)
1763 #define F_PERR_POINTER_DATA_FIFO0 V_PERR_POINTER_DATA_FIFO0(1U)
1765 #define S_PERR_POINTER_DATA_FIFO1 15
1766 #define V_PERR_POINTER_DATA_FIFO1(x) ((x) << S_PERR_POINTER_DATA_FIFO1)
1767 #define F_PERR_POINTER_DATA_FIFO1 V_PERR_POINTER_DATA_FIFO1(1U)
1769 #define S_PERR_POINTER_HDR_FIFO0 14
1770 #define V_PERR_POINTER_HDR_FIFO0(x) ((x) << S_PERR_POINTER_HDR_FIFO0)
1771 #define F_PERR_POINTER_HDR_FIFO0 V_PERR_POINTER_HDR_FIFO0(1U)
1773 #define S_PERR_POINTER_HDR_FIFO1 13
1774 #define V_PERR_POINTER_HDR_FIFO1(x) ((x) << S_PERR_POINTER_HDR_FIFO1)
1775 #define F_PERR_POINTER_HDR_FIFO1 V_PERR_POINTER_HDR_FIFO1(1U)
1777 #define S_PERR_PAYLOAD_FIFO0 12
1778 #define V_PERR_PAYLOAD_FIFO0(x) ((x) << S_PERR_PAYLOAD_FIFO0)
1779 #define F_PERR_PAYLOAD_FIFO0 V_PERR_PAYLOAD_FIFO0(1U)
1781 #define S_PERR_PAYLOAD_FIFO1 11
1782 #define V_PERR_PAYLOAD_FIFO1(x) ((x) << S_PERR_PAYLOAD_FIFO1)
1783 #define F_PERR_PAYLOAD_FIFO1 V_PERR_PAYLOAD_FIFO1(1U)
1785 #define S_PERR_EDMA_INPUT_FIFO3 10
1786 #define V_PERR_EDMA_INPUT_FIFO3(x) ((x) << S_PERR_EDMA_INPUT_FIFO3)
1787 #define F_PERR_EDMA_INPUT_FIFO3 V_PERR_EDMA_INPUT_FIFO3(1U)
1789 #define S_PERR_EDMA_INPUT_FIFO2 9
1790 #define V_PERR_EDMA_INPUT_FIFO2(x) ((x) << S_PERR_EDMA_INPUT_FIFO2)
1791 #define F_PERR_EDMA_INPUT_FIFO2 V_PERR_EDMA_INPUT_FIFO2(1U)
1793 #define S_PERR_EDMA_INPUT_FIFO1 8
1794 #define V_PERR_EDMA_INPUT_FIFO1(x) ((x) << S_PERR_EDMA_INPUT_FIFO1)
1795 #define F_PERR_EDMA_INPUT_FIFO1 V_PERR_EDMA_INPUT_FIFO1(1U)
1797 #define S_PERR_EDMA_INPUT_FIFO0 7
1798 #define V_PERR_EDMA_INPUT_FIFO0(x) ((x) << S_PERR_EDMA_INPUT_FIFO0)
1799 #define F_PERR_EDMA_INPUT_FIFO0 V_PERR_EDMA_INPUT_FIFO0(1U)
1801 #define S_PERR_MGT_BAR2_FIFO 6
1802 #define V_PERR_MGT_BAR2_FIFO(x) ((x) << S_PERR_MGT_BAR2_FIFO)
1803 #define F_PERR_MGT_BAR2_FIFO V_PERR_MGT_BAR2_FIFO(1U)
1805 #define S_PERR_HEADERSPLIT_FIFO1_T5 5
1806 #define V_PERR_HEADERSPLIT_FIFO1_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO1_T5)
1807 #define F_PERR_HEADERSPLIT_FIFO1_T5 V_PERR_HEADERSPLIT_FIFO1_T5(1U)
1809 #define S_PERR_HEADERSPLIT_FIFO0_T5 4
1810 #define V_PERR_HEADERSPLIT_FIFO0_T5(x) ((x) << S_PERR_HEADERSPLIT_FIFO0_T5)
1811 #define F_PERR_HEADERSPLIT_FIFO0_T5 V_PERR_HEADERSPLIT_FIFO0_T5(1U)
1813 #define S_PERR_CIM_FIFO1 3
1814 #define V_PERR_CIM_FIFO1(x) ((x) << S_PERR_CIM_FIFO1)
1815 #define F_PERR_CIM_FIFO1 V_PERR_CIM_FIFO1(1U)
1817 #define S_PERR_CIM_FIFO0 2
1818 #define V_PERR_CIM_FIFO0(x) ((x) << S_PERR_CIM_FIFO0)
1819 #define F_PERR_CIM_FIFO0 V_PERR_CIM_FIFO0(1U)
1821 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO1 1
1822 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO1)
1823 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO1 V_PERR_IDMA_SWITCH_OUTPUT_FIFO1(1U)
1825 #define S_PERR_IDMA_SWITCH_OUTPUT_FIFO0 0
1826 #define V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(x) ((x) << S_PERR_IDMA_SWITCH_OUTPUT_FIFO0)
1827 #define F_PERR_IDMA_SWITCH_OUTPUT_FIFO0 V_PERR_IDMA_SWITCH_OUTPUT_FIFO0(1U)
1829 #define A_SGE_INT_ENABLE5 0x1110
1830 #define A_SGE_PERR_ENABLE5 0x1114
1831 #define A_SGE_DBFIFO_STATUS2 0x1118
1833 #define S_FL_INT_THRESH 24
1834 #define M_FL_INT_THRESH 0xfU
1835 #define V_FL_INT_THRESH(x) ((x) << S_FL_INT_THRESH)
1836 #define G_FL_INT_THRESH(x) (((x) >> S_FL_INT_THRESH) & M_FL_INT_THRESH)
1838 #define S_FL_COUNT 14
1839 #define M_FL_COUNT 0x3ffU
1840 #define V_FL_COUNT(x) ((x) << S_FL_COUNT)
1841 #define G_FL_COUNT(x) (((x) >> S_FL_COUNT) & M_FL_COUNT)
1843 #define S_HP_INT_THRESH_T5 10
1844 #define M_HP_INT_THRESH_T5 0xfU
1845 #define V_HP_INT_THRESH_T5(x) ((x) << S_HP_INT_THRESH_T5)
1846 #define G_HP_INT_THRESH_T5(x) (((x) >> S_HP_INT_THRESH_T5) & M_HP_INT_THRESH_T5)
1848 #define S_HP_COUNT_T5 0
1849 #define M_HP_COUNT_T5 0x3ffU
1850 #define V_HP_COUNT_T5(x) ((x) << S_HP_COUNT_T5)
1851 #define G_HP_COUNT_T5(x) (((x) >> S_HP_COUNT_T5) & M_HP_COUNT_T5)
1853 #define A_SGE_FETCH_BURST_MAX_0_AND_1 0x111c
1855 #define S_FETCHBURSTMAX0 16
1856 #define M_FETCHBURSTMAX0 0x3ffU
1857 #define V_FETCHBURSTMAX0(x) ((x) << S_FETCHBURSTMAX0)
1858 #define G_FETCHBURSTMAX0(x) (((x) >> S_FETCHBURSTMAX0) & M_FETCHBURSTMAX0)
1860 #define S_FETCHBURSTMAX1 0
1861 #define M_FETCHBURSTMAX1 0x3ffU
1862 #define V_FETCHBURSTMAX1(x) ((x) << S_FETCHBURSTMAX1)
1863 #define G_FETCHBURSTMAX1(x) (((x) >> S_FETCHBURSTMAX1) & M_FETCHBURSTMAX1)
1865 #define A_SGE_FETCH_BURST_MAX_2_AND_3 0x1120
1867 #define S_FETCHBURSTMAX2 16
1868 #define M_FETCHBURSTMAX2 0x3ffU
1869 #define V_FETCHBURSTMAX2(x) ((x) << S_FETCHBURSTMAX2)
1870 #define G_FETCHBURSTMAX2(x) (((x) >> S_FETCHBURSTMAX2) & M_FETCHBURSTMAX2)
1872 #define S_FETCHBURSTMAX3 0
1873 #define M_FETCHBURSTMAX3 0x3ffU
1874 #define V_FETCHBURSTMAX3(x) ((x) << S_FETCHBURSTMAX3)
1875 #define G_FETCHBURSTMAX3(x) (((x) >> S_FETCHBURSTMAX3) & M_FETCHBURSTMAX3)
1877 #define A_SGE_CONTROL2 0x1124
1879 #define S_UPFLCUTOFFDIS 21
1880 #define V_UPFLCUTOFFDIS(x) ((x) << S_UPFLCUTOFFDIS)
1881 #define F_UPFLCUTOFFDIS V_UPFLCUTOFFDIS(1U)
1883 #define S_RXCPLSIZEAUTOCORRECT 20
1884 #define V_RXCPLSIZEAUTOCORRECT(x) ((x) << S_RXCPLSIZEAUTOCORRECT)
1885 #define F_RXCPLSIZEAUTOCORRECT V_RXCPLSIZEAUTOCORRECT(1U)
1887 #define S_IDMAARBROUNDROBIN 19
1888 #define V_IDMAARBROUNDROBIN(x) ((x) << S_IDMAARBROUNDROBIN)
1889 #define F_IDMAARBROUNDROBIN V_IDMAARBROUNDROBIN(1U)
1891 #define S_INGPACKBOUNDARY 16
1892 #define M_INGPACKBOUNDARY 0x7U
1893 #define V_INGPACKBOUNDARY(x) ((x) << S_INGPACKBOUNDARY)
1894 #define G_INGPACKBOUNDARY(x) (((x) >> S_INGPACKBOUNDARY) & M_INGPACKBOUNDARY)
1896 #define S_CGEN_EGRESS_CONTEXT 15
1897 #define V_CGEN_EGRESS_CONTEXT(x) ((x) << S_CGEN_EGRESS_CONTEXT)
1898 #define F_CGEN_EGRESS_CONTEXT V_CGEN_EGRESS_CONTEXT(1U)
1900 #define S_CGEN_INGRESS_CONTEXT 14
1901 #define V_CGEN_INGRESS_CONTEXT(x) ((x) << S_CGEN_INGRESS_CONTEXT)
1902 #define F_CGEN_INGRESS_CONTEXT V_CGEN_INGRESS_CONTEXT(1U)
1904 #define S_CGEN_IDMA 13
1905 #define V_CGEN_IDMA(x) ((x) << S_CGEN_IDMA)
1906 #define F_CGEN_IDMA V_CGEN_IDMA(1U)
1908 #define S_CGEN_DBP 12
1909 #define V_CGEN_DBP(x) ((x) << S_CGEN_DBP)
1910 #define F_CGEN_DBP V_CGEN_DBP(1U)
1912 #define S_CGEN_EDMA 11
1913 #define V_CGEN_EDMA(x) ((x) << S_CGEN_EDMA)
1914 #define F_CGEN_EDMA V_CGEN_EDMA(1U)
1916 #define S_VFIFO_ENABLE 10
1917 #define V_VFIFO_ENABLE(x) ((x) << S_VFIFO_ENABLE)
1918 #define F_VFIFO_ENABLE V_VFIFO_ENABLE(1U)
1920 #define S_FLM_RESCHEDULE_MODE 9
1921 #define V_FLM_RESCHEDULE_MODE(x) ((x) << S_FLM_RESCHEDULE_MODE)
1922 #define F_FLM_RESCHEDULE_MODE V_FLM_RESCHEDULE_MODE(1U)
1924 #define S_HINTDEPTHCTLFL 4
1925 #define M_HINTDEPTHCTLFL 0x1fU
1926 #define V_HINTDEPTHCTLFL(x) ((x) << S_HINTDEPTHCTLFL)
1927 #define G_HINTDEPTHCTLFL(x) (((x) >> S_HINTDEPTHCTLFL) & M_HINTDEPTHCTLFL)
1929 #define S_FORCE_ORDERING 3
1930 #define V_FORCE_ORDERING(x) ((x) << S_FORCE_ORDERING)
1931 #define F_FORCE_ORDERING V_FORCE_ORDERING(1U)
1933 #define S_TX_COALESCE_SIZE 2
1934 #define V_TX_COALESCE_SIZE(x) ((x) << S_TX_COALESCE_SIZE)
1935 #define F_TX_COALESCE_SIZE V_TX_COALESCE_SIZE(1U)
1937 #define S_COAL_STRICT_CIM_PRI 1
1938 #define V_COAL_STRICT_CIM_PRI(x) ((x) << S_COAL_STRICT_CIM_PRI)
1939 #define F_COAL_STRICT_CIM_PRI V_COAL_STRICT_CIM_PRI(1U)
1941 #define S_TX_COALESCE_PRI 0
1942 #define V_TX_COALESCE_PRI(x) ((x) << S_TX_COALESCE_PRI)
1943 #define F_TX_COALESCE_PRI V_TX_COALESCE_PRI(1U)
1945 #define A_SGE_DEEP_SLEEP 0x1128
1947 #define S_IDMA1_SLEEP_STATUS 11
1948 #define V_IDMA1_SLEEP_STATUS(x) ((x) << S_IDMA1_SLEEP_STATUS)
1949 #define F_IDMA1_SLEEP_STATUS V_IDMA1_SLEEP_STATUS(1U)
1951 #define S_IDMA0_SLEEP_STATUS 10
1952 #define V_IDMA0_SLEEP_STATUS(x) ((x) << S_IDMA0_SLEEP_STATUS)
1953 #define F_IDMA0_SLEEP_STATUS V_IDMA0_SLEEP_STATUS(1U)
1955 #define S_IDMA1_SLEEP_REQ 9
1956 #define V_IDMA1_SLEEP_REQ(x) ((x) << S_IDMA1_SLEEP_REQ)
1957 #define F_IDMA1_SLEEP_REQ V_IDMA1_SLEEP_REQ(1U)
1959 #define S_IDMA0_SLEEP_REQ 8
1960 #define V_IDMA0_SLEEP_REQ(x) ((x) << S_IDMA0_SLEEP_REQ)
1961 #define F_IDMA0_SLEEP_REQ V_IDMA0_SLEEP_REQ(1U)
1963 #define S_EDMA3_SLEEP_STATUS 7
1964 #define V_EDMA3_SLEEP_STATUS(x) ((x) << S_EDMA3_SLEEP_STATUS)
1965 #define F_EDMA3_SLEEP_STATUS V_EDMA3_SLEEP_STATUS(1U)
1967 #define S_EDMA2_SLEEP_STATUS 6
1968 #define V_EDMA2_SLEEP_STATUS(x) ((x) << S_EDMA2_SLEEP_STATUS)
1969 #define F_EDMA2_SLEEP_STATUS V_EDMA2_SLEEP_STATUS(1U)
1971 #define S_EDMA1_SLEEP_STATUS 5
1972 #define V_EDMA1_SLEEP_STATUS(x) ((x) << S_EDMA1_SLEEP_STATUS)
1973 #define F_EDMA1_SLEEP_STATUS V_EDMA1_SLEEP_STATUS(1U)
1975 #define S_EDMA0_SLEEP_STATUS 4
1976 #define V_EDMA0_SLEEP_STATUS(x) ((x) << S_EDMA0_SLEEP_STATUS)
1977 #define F_EDMA0_SLEEP_STATUS V_EDMA0_SLEEP_STATUS(1U)
1979 #define S_EDMA3_SLEEP_REQ 3
1980 #define V_EDMA3_SLEEP_REQ(x) ((x) << S_EDMA3_SLEEP_REQ)
1981 #define F_EDMA3_SLEEP_REQ V_EDMA3_SLEEP_REQ(1U)
1983 #define S_EDMA2_SLEEP_REQ 2
1984 #define V_EDMA2_SLEEP_REQ(x) ((x) << S_EDMA2_SLEEP_REQ)
1985 #define F_EDMA2_SLEEP_REQ V_EDMA2_SLEEP_REQ(1U)
1987 #define S_EDMA1_SLEEP_REQ 1
1988 #define V_EDMA1_SLEEP_REQ(x) ((x) << S_EDMA1_SLEEP_REQ)
1989 #define F_EDMA1_SLEEP_REQ V_EDMA1_SLEEP_REQ(1U)
1991 #define S_EDMA0_SLEEP_REQ 0
1992 #define V_EDMA0_SLEEP_REQ(x) ((x) << S_EDMA0_SLEEP_REQ)
1993 #define F_EDMA0_SLEEP_REQ V_EDMA0_SLEEP_REQ(1U)
1995 #define A_SGE_DOORBELL_THROTTLE_THRESHOLD 0x112c
1997 #define S_THROTTLE_THRESHOLD_FL 16
1998 #define M_THROTTLE_THRESHOLD_FL 0xfU
1999 #define V_THROTTLE_THRESHOLD_FL(x) ((x) << S_THROTTLE_THRESHOLD_FL)
2000 #define G_THROTTLE_THRESHOLD_FL(x) (((x) >> S_THROTTLE_THRESHOLD_FL) & M_THROTTLE_THRESHOLD_FL)
2002 #define S_THROTTLE_THRESHOLD_HP 12
2003 #define M_THROTTLE_THRESHOLD_HP 0xfU
2004 #define V_THROTTLE_THRESHOLD_HP(x) ((x) << S_THROTTLE_THRESHOLD_HP)
2005 #define G_THROTTLE_THRESHOLD_HP(x) (((x) >> S_THROTTLE_THRESHOLD_HP) & M_THROTTLE_THRESHOLD_HP)
2007 #define S_THROTTLE_THRESHOLD_LP 0
2008 #define M_THROTTLE_THRESHOLD_LP 0xfffU
2009 #define V_THROTTLE_THRESHOLD_LP(x) ((x) << S_THROTTLE_THRESHOLD_LP)
2010 #define G_THROTTLE_THRESHOLD_LP(x) (((x) >> S_THROTTLE_THRESHOLD_LP) & M_THROTTLE_THRESHOLD_LP)
2012 #define A_SGE_DBP_FETCH_THRESHOLD 0x1130
2014 #define S_DBP_FETCH_THRESHOLD_FL 21
2015 #define M_DBP_FETCH_THRESHOLD_FL 0xfU
2016 #define V_DBP_FETCH_THRESHOLD_FL(x) ((x) << S_DBP_FETCH_THRESHOLD_FL)
2017 #define G_DBP_FETCH_THRESHOLD_FL(x) (((x) >> S_DBP_FETCH_THRESHOLD_FL) & M_DBP_FETCH_THRESHOLD_FL)
2019 #define S_DBP_FETCH_THRESHOLD_HP 17
2020 #define M_DBP_FETCH_THRESHOLD_HP 0xfU
2021 #define V_DBP_FETCH_THRESHOLD_HP(x) ((x) << S_DBP_FETCH_THRESHOLD_HP)
2022 #define G_DBP_FETCH_THRESHOLD_HP(x) (((x) >> S_DBP_FETCH_THRESHOLD_HP) & M_DBP_FETCH_THRESHOLD_HP)
2024 #define S_DBP_FETCH_THRESHOLD_LP 5
2025 #define M_DBP_FETCH_THRESHOLD_LP 0xfffU
2026 #define V_DBP_FETCH_THRESHOLD_LP(x) ((x) << S_DBP_FETCH_THRESHOLD_LP)
2027 #define G_DBP_FETCH_THRESHOLD_LP(x) (((x) >> S_DBP_FETCH_THRESHOLD_LP) & M_DBP_FETCH_THRESHOLD_LP)
2029 #define S_DBP_FETCH_THRESHOLD_MODE 4
2030 #define V_DBP_FETCH_THRESHOLD_MODE(x) ((x) << S_DBP_FETCH_THRESHOLD_MODE)
2031 #define F_DBP_FETCH_THRESHOLD_MODE V_DBP_FETCH_THRESHOLD_MODE(1U)
2033 #define S_DBP_FETCH_THRESHOLD_EN3 3
2034 #define V_DBP_FETCH_THRESHOLD_EN3(x) ((x) << S_DBP_FETCH_THRESHOLD_EN3)
2035 #define F_DBP_FETCH_THRESHOLD_EN3 V_DBP_FETCH_THRESHOLD_EN3(1U)
2037 #define S_DBP_FETCH_THRESHOLD_EN2 2
2038 #define V_DBP_FETCH_THRESHOLD_EN2(x) ((x) << S_DBP_FETCH_THRESHOLD_EN2)
2039 #define F_DBP_FETCH_THRESHOLD_EN2 V_DBP_FETCH_THRESHOLD_EN2(1U)
2041 #define S_DBP_FETCH_THRESHOLD_EN1 1
2042 #define V_DBP_FETCH_THRESHOLD_EN1(x) ((x) << S_DBP_FETCH_THRESHOLD_EN1)
2043 #define F_DBP_FETCH_THRESHOLD_EN1 V_DBP_FETCH_THRESHOLD_EN1(1U)
2045 #define S_DBP_FETCH_THRESHOLD_EN0 0
2046 #define V_DBP_FETCH_THRESHOLD_EN0(x) ((x) << S_DBP_FETCH_THRESHOLD_EN0)
2047 #define F_DBP_FETCH_THRESHOLD_EN0 V_DBP_FETCH_THRESHOLD_EN0(1U)
2049 #define A_SGE_DBP_FETCH_THRESHOLD_QUEUE 0x1134
2051 #define S_DBP_FETCH_THRESHOLD_IQ1 16
2052 #define M_DBP_FETCH_THRESHOLD_IQ1 0xffffU
2053 #define V_DBP_FETCH_THRESHOLD_IQ1(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ1)
2054 #define G_DBP_FETCH_THRESHOLD_IQ1(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ1) & M_DBP_FETCH_THRESHOLD_IQ1)
2056 #define S_DBP_FETCH_THRESHOLD_IQ0 0
2057 #define M_DBP_FETCH_THRESHOLD_IQ0 0xffffU
2058 #define V_DBP_FETCH_THRESHOLD_IQ0(x) ((x) << S_DBP_FETCH_THRESHOLD_IQ0)
2059 #define G_DBP_FETCH_THRESHOLD_IQ0(x) (((x) >> S_DBP_FETCH_THRESHOLD_IQ0) & M_DBP_FETCH_THRESHOLD_IQ0)
2061 #define A_SGE_DBVFIFO_BADDR 0x1138
2062 #define A_SGE_DBVFIFO_SIZE 0x113c
2064 #define S_DBVFIFO_SIZE 6
2065 #define M_DBVFIFO_SIZE 0xfffU
2066 #define V_DBVFIFO_SIZE(x) ((x) << S_DBVFIFO_SIZE)
2067 #define G_DBVFIFO_SIZE(x) (((x) >> S_DBVFIFO_SIZE) & M_DBVFIFO_SIZE)
2069 #define A_SGE_DBFIFO_STATUS3 0x1140
2071 #define S_LP_PTRS_EQUAL 21
2072 #define V_LP_PTRS_EQUAL(x) ((x) << S_LP_PTRS_EQUAL)
2073 #define F_LP_PTRS_EQUAL V_LP_PTRS_EQUAL(1U)
2075 #define S_LP_SNAPHOT 20
2076 #define V_LP_SNAPHOT(x) ((x) << S_LP_SNAPHOT)
2077 #define F_LP_SNAPHOT V_LP_SNAPHOT(1U)
2079 #define S_FL_INT_THRESH_LOW 16
2080 #define M_FL_INT_THRESH_LOW 0xfU
2081 #define V_FL_INT_THRESH_LOW(x) ((x) << S_FL_INT_THRESH_LOW)
2082 #define G_FL_INT_THRESH_LOW(x) (((x) >> S_FL_INT_THRESH_LOW) & M_FL_INT_THRESH_LOW)
2084 #define S_HP_INT_THRESH_LOW 12
2085 #define M_HP_INT_THRESH_LOW 0xfU
2086 #define V_HP_INT_THRESH_LOW(x) ((x) << S_HP_INT_THRESH_LOW)
2087 #define G_HP_INT_THRESH_LOW(x) (((x) >> S_HP_INT_THRESH_LOW) & M_HP_INT_THRESH_LOW)
2089 #define S_LP_INT_THRESH_LOW 0
2090 #define M_LP_INT_THRESH_LOW 0xfffU
2091 #define V_LP_INT_THRESH_LOW(x) ((x) << S_LP_INT_THRESH_LOW)
2092 #define G_LP_INT_THRESH_LOW(x) (((x) >> S_LP_INT_THRESH_LOW) & M_LP_INT_THRESH_LOW)
2094 #define A_SGE_CHANGESET 0x1144
2095 #define A_SGE_PC_RSP_ERROR 0x1148
2096 #define A_SGE_PC0_REQ_BIST_CMD 0x1180
2097 #define A_SGE_PC0_REQ_BIST_ERROR_CNT 0x1184
2098 #define A_SGE_PC1_REQ_BIST_CMD 0x1190
2099 #define A_SGE_PC1_REQ_BIST_ERROR_CNT 0x1194
2100 #define A_SGE_PC0_RSP_BIST_CMD 0x11a0
2101 #define A_SGE_PC0_RSP_BIST_ERROR_CNT 0x11a4
2102 #define A_SGE_PC1_RSP_BIST_CMD 0x11b0
2103 #define A_SGE_PC1_RSP_BIST_ERROR_CNT 0x11b4
2104 #define A_SGE_CTXT_CMD 0x11fc
2107 #define V_BUSY(x) ((x) << S_BUSY)
2108 #define F_BUSY V_BUSY(1U)
2111 #define M_CTXTOP 0x3U
2112 #define V_CTXTOP(x) ((x) << S_CTXTOP)
2113 #define G_CTXTOP(x) (((x) >> S_CTXTOP) & M_CTXTOP)
2115 #define S_CTXTTYPE 24
2116 #define M_CTXTTYPE 0x3U
2117 #define V_CTXTTYPE(x) ((x) << S_CTXTTYPE)
2118 #define G_CTXTTYPE(x) (((x) >> S_CTXTTYPE) & M_CTXTTYPE)
2121 #define M_CTXTQID 0x1ffffU
2122 #define V_CTXTQID(x) ((x) << S_CTXTQID)
2123 #define G_CTXTQID(x) (((x) >> S_CTXTQID) & M_CTXTQID)
2125 #define A_SGE_CTXT_DATA0 0x1200
2126 #define A_SGE_CTXT_DATA1 0x1204
2127 #define A_SGE_CTXT_DATA2 0x1208
2128 #define A_SGE_CTXT_DATA3 0x120c
2129 #define A_SGE_CTXT_DATA4 0x1210
2130 #define A_SGE_CTXT_DATA5 0x1214
2131 #define A_SGE_CTXT_DATA6 0x1218
2132 #define A_SGE_CTXT_DATA7 0x121c
2133 #define A_SGE_CTXT_MASK0 0x1220
2134 #define A_SGE_CTXT_MASK1 0x1224
2135 #define A_SGE_CTXT_MASK2 0x1228
2136 #define A_SGE_CTXT_MASK3 0x122c
2137 #define A_SGE_CTXT_MASK4 0x1230
2138 #define A_SGE_CTXT_MASK5 0x1234
2139 #define A_SGE_CTXT_MASK6 0x1238
2140 #define A_SGE_CTXT_MASK7 0x123c
2141 #define A_SGE_DEBUG_DATA_HIGH_INDEX_0 0x1280
2144 #define M_CIM_WM 0x3U
2145 #define V_CIM_WM(x) ((x) << S_CIM_WM)
2146 #define G_CIM_WM(x) (((x) >> S_CIM_WM) & M_CIM_WM)
2148 #define S_DEBUG_UP_SOP_CNT 20
2149 #define M_DEBUG_UP_SOP_CNT 0xfU
2150 #define V_DEBUG_UP_SOP_CNT(x) ((x) << S_DEBUG_UP_SOP_CNT)
2151 #define G_DEBUG_UP_SOP_CNT(x) (((x) >> S_DEBUG_UP_SOP_CNT) & M_DEBUG_UP_SOP_CNT)
2153 #define S_DEBUG_UP_EOP_CNT 16
2154 #define M_DEBUG_UP_EOP_CNT 0xfU
2155 #define V_DEBUG_UP_EOP_CNT(x) ((x) << S_DEBUG_UP_EOP_CNT)
2156 #define G_DEBUG_UP_EOP_CNT(x) (((x) >> S_DEBUG_UP_EOP_CNT) & M_DEBUG_UP_EOP_CNT)
2158 #define S_DEBUG_CIM_SOP1_CNT 12
2159 #define M_DEBUG_CIM_SOP1_CNT 0xfU
2160 #define V_DEBUG_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CIM_SOP1_CNT)
2161 #define G_DEBUG_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CIM_SOP1_CNT) & M_DEBUG_CIM_SOP1_CNT)
2163 #define S_DEBUG_CIM_EOP1_CNT 8
2164 #define M_DEBUG_CIM_EOP1_CNT 0xfU
2165 #define V_DEBUG_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CIM_EOP1_CNT)
2166 #define G_DEBUG_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CIM_EOP1_CNT) & M_DEBUG_CIM_EOP1_CNT)
2168 #define S_DEBUG_CIM_SOP0_CNT 4
2169 #define M_DEBUG_CIM_SOP0_CNT 0xfU
2170 #define V_DEBUG_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CIM_SOP0_CNT)
2171 #define G_DEBUG_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CIM_SOP0_CNT) & M_DEBUG_CIM_SOP0_CNT)
2173 #define S_DEBUG_CIM_EOP0_CNT 0
2174 #define M_DEBUG_CIM_EOP0_CNT 0xfU
2175 #define V_DEBUG_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CIM_EOP0_CNT)
2176 #define G_DEBUG_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CIM_EOP0_CNT) & M_DEBUG_CIM_EOP0_CNT)
2178 #define A_SGE_DEBUG_DATA_HIGH_INDEX_1 0x1284
2180 #define S_DEBUG_T_RX_SOP1_CNT 28
2181 #define M_DEBUG_T_RX_SOP1_CNT 0xfU
2182 #define V_DEBUG_T_RX_SOP1_CNT(x) ((x) << S_DEBUG_T_RX_SOP1_CNT)
2183 #define G_DEBUG_T_RX_SOP1_CNT(x) (((x) >> S_DEBUG_T_RX_SOP1_CNT) & M_DEBUG_T_RX_SOP1_CNT)
2185 #define S_DEBUG_T_RX_EOP1_CNT 24
2186 #define M_DEBUG_T_RX_EOP1_CNT 0xfU
2187 #define V_DEBUG_T_RX_EOP1_CNT(x) ((x) << S_DEBUG_T_RX_EOP1_CNT)
2188 #define G_DEBUG_T_RX_EOP1_CNT(x) (((x) >> S_DEBUG_T_RX_EOP1_CNT) & M_DEBUG_T_RX_EOP1_CNT)
2190 #define S_DEBUG_T_RX_SOP0_CNT 20
2191 #define M_DEBUG_T_RX_SOP0_CNT 0xfU
2192 #define V_DEBUG_T_RX_SOP0_CNT(x) ((x) << S_DEBUG_T_RX_SOP0_CNT)
2193 #define G_DEBUG_T_RX_SOP0_CNT(x) (((x) >> S_DEBUG_T_RX_SOP0_CNT) & M_DEBUG_T_RX_SOP0_CNT)
2195 #define S_DEBUG_T_RX_EOP0_CNT 16
2196 #define M_DEBUG_T_RX_EOP0_CNT 0xfU
2197 #define V_DEBUG_T_RX_EOP0_CNT(x) ((x) << S_DEBUG_T_RX_EOP0_CNT)
2198 #define G_DEBUG_T_RX_EOP0_CNT(x) (((x) >> S_DEBUG_T_RX_EOP0_CNT) & M_DEBUG_T_RX_EOP0_CNT)
2200 #define S_DEBUG_U_RX_SOP1_CNT 12
2201 #define M_DEBUG_U_RX_SOP1_CNT 0xfU
2202 #define V_DEBUG_U_RX_SOP1_CNT(x) ((x) << S_DEBUG_U_RX_SOP1_CNT)
2203 #define G_DEBUG_U_RX_SOP1_CNT(x) (((x) >> S_DEBUG_U_RX_SOP1_CNT) & M_DEBUG_U_RX_SOP1_CNT)
2205 #define S_DEBUG_U_RX_EOP1_CNT 8
2206 #define M_DEBUG_U_RX_EOP1_CNT 0xfU
2207 #define V_DEBUG_U_RX_EOP1_CNT(x) ((x) << S_DEBUG_U_RX_EOP1_CNT)
2208 #define G_DEBUG_U_RX_EOP1_CNT(x) (((x) >> S_DEBUG_U_RX_EOP1_CNT) & M_DEBUG_U_RX_EOP1_CNT)
2210 #define S_DEBUG_U_RX_SOP0_CNT 4
2211 #define M_DEBUG_U_RX_SOP0_CNT 0xfU
2212 #define V_DEBUG_U_RX_SOP0_CNT(x) ((x) << S_DEBUG_U_RX_SOP0_CNT)
2213 #define G_DEBUG_U_RX_SOP0_CNT(x) (((x) >> S_DEBUG_U_RX_SOP0_CNT) & M_DEBUG_U_RX_SOP0_CNT)
2215 #define S_DEBUG_U_RX_EOP0_CNT 0
2216 #define M_DEBUG_U_RX_EOP0_CNT 0xfU
2217 #define V_DEBUG_U_RX_EOP0_CNT(x) ((x) << S_DEBUG_U_RX_EOP0_CNT)
2218 #define G_DEBUG_U_RX_EOP0_CNT(x) (((x) >> S_DEBUG_U_RX_EOP0_CNT) & M_DEBUG_U_RX_EOP0_CNT)
2220 #define A_SGE_DEBUG_DATA_HIGH_INDEX_2 0x1288
2222 #define S_DEBUG_UD_RX_SOP3_CNT 28
2223 #define M_DEBUG_UD_RX_SOP3_CNT 0xfU
2224 #define V_DEBUG_UD_RX_SOP3_CNT(x) ((x) << S_DEBUG_UD_RX_SOP3_CNT)
2225 #define G_DEBUG_UD_RX_SOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP3_CNT) & M_DEBUG_UD_RX_SOP3_CNT)
2227 #define S_DEBUG_UD_RX_EOP3_CNT 24
2228 #define M_DEBUG_UD_RX_EOP3_CNT 0xfU
2229 #define V_DEBUG_UD_RX_EOP3_CNT(x) ((x) << S_DEBUG_UD_RX_EOP3_CNT)
2230 #define G_DEBUG_UD_RX_EOP3_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP3_CNT) & M_DEBUG_UD_RX_EOP3_CNT)
2232 #define S_DEBUG_UD_RX_SOP2_CNT 20
2233 #define M_DEBUG_UD_RX_SOP2_CNT 0xfU
2234 #define V_DEBUG_UD_RX_SOP2_CNT(x) ((x) << S_DEBUG_UD_RX_SOP2_CNT)
2235 #define G_DEBUG_UD_RX_SOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP2_CNT) & M_DEBUG_UD_RX_SOP2_CNT)
2237 #define S_DEBUG_UD_RX_EOP2_CNT 16
2238 #define M_DEBUG_UD_RX_EOP2_CNT 0xfU
2239 #define V_DEBUG_UD_RX_EOP2_CNT(x) ((x) << S_DEBUG_UD_RX_EOP2_CNT)
2240 #define G_DEBUG_UD_RX_EOP2_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP2_CNT) & M_DEBUG_UD_RX_EOP2_CNT)
2242 #define S_DEBUG_UD_RX_SOP1_CNT 12
2243 #define M_DEBUG_UD_RX_SOP1_CNT 0xfU
2244 #define V_DEBUG_UD_RX_SOP1_CNT(x) ((x) << S_DEBUG_UD_RX_SOP1_CNT)
2245 #define G_DEBUG_UD_RX_SOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP1_CNT) & M_DEBUG_UD_RX_SOP1_CNT)
2247 #define S_DEBUG_UD_RX_EOP1_CNT 8
2248 #define M_DEBUG_UD_RX_EOP1_CNT 0xfU
2249 #define V_DEBUG_UD_RX_EOP1_CNT(x) ((x) << S_DEBUG_UD_RX_EOP1_CNT)
2250 #define G_DEBUG_UD_RX_EOP1_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP1_CNT) & M_DEBUG_UD_RX_EOP1_CNT)
2252 #define S_DEBUG_UD_RX_SOP0_CNT 4
2253 #define M_DEBUG_UD_RX_SOP0_CNT 0xfU
2254 #define V_DEBUG_UD_RX_SOP0_CNT(x) ((x) << S_DEBUG_UD_RX_SOP0_CNT)
2255 #define G_DEBUG_UD_RX_SOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_SOP0_CNT) & M_DEBUG_UD_RX_SOP0_CNT)
2257 #define S_DEBUG_UD_RX_EOP0_CNT 0
2258 #define M_DEBUG_UD_RX_EOP0_CNT 0xfU
2259 #define V_DEBUG_UD_RX_EOP0_CNT(x) ((x) << S_DEBUG_UD_RX_EOP0_CNT)
2260 #define G_DEBUG_UD_RX_EOP0_CNT(x) (((x) >> S_DEBUG_UD_RX_EOP0_CNT) & M_DEBUG_UD_RX_EOP0_CNT)
2262 #define A_SGE_DEBUG_DATA_HIGH_INDEX_3 0x128c
2264 #define S_DEBUG_U_TX_SOP3_CNT 28
2265 #define M_DEBUG_U_TX_SOP3_CNT 0xfU
2266 #define V_DEBUG_U_TX_SOP3_CNT(x) ((x) << S_DEBUG_U_TX_SOP3_CNT)
2267 #define G_DEBUG_U_TX_SOP3_CNT(x) (((x) >> S_DEBUG_U_TX_SOP3_CNT) & M_DEBUG_U_TX_SOP3_CNT)
2269 #define S_DEBUG_U_TX_EOP3_CNT 24
2270 #define M_DEBUG_U_TX_EOP3_CNT 0xfU
2271 #define V_DEBUG_U_TX_EOP3_CNT(x) ((x) << S_DEBUG_U_TX_EOP3_CNT)
2272 #define G_DEBUG_U_TX_EOP3_CNT(x) (((x) >> S_DEBUG_U_TX_EOP3_CNT) & M_DEBUG_U_TX_EOP3_CNT)
2274 #define S_DEBUG_U_TX_SOP2_CNT 20
2275 #define M_DEBUG_U_TX_SOP2_CNT 0xfU
2276 #define V_DEBUG_U_TX_SOP2_CNT(x) ((x) << S_DEBUG_U_TX_SOP2_CNT)
2277 #define G_DEBUG_U_TX_SOP2_CNT(x) (((x) >> S_DEBUG_U_TX_SOP2_CNT) & M_DEBUG_U_TX_SOP2_CNT)
2279 #define S_DEBUG_U_TX_EOP2_CNT 16
2280 #define M_DEBUG_U_TX_EOP2_CNT 0xfU
2281 #define V_DEBUG_U_TX_EOP2_CNT(x) ((x) << S_DEBUG_U_TX_EOP2_CNT)
2282 #define G_DEBUG_U_TX_EOP2_CNT(x) (((x) >> S_DEBUG_U_TX_EOP2_CNT) & M_DEBUG_U_TX_EOP2_CNT)
2284 #define S_DEBUG_U_TX_SOP1_CNT 12
2285 #define M_DEBUG_U_TX_SOP1_CNT 0xfU
2286 #define V_DEBUG_U_TX_SOP1_CNT(x) ((x) << S_DEBUG_U_TX_SOP1_CNT)
2287 #define G_DEBUG_U_TX_SOP1_CNT(x) (((x) >> S_DEBUG_U_TX_SOP1_CNT) & M_DEBUG_U_TX_SOP1_CNT)
2289 #define S_DEBUG_U_TX_EOP1_CNT 8
2290 #define M_DEBUG_U_TX_EOP1_CNT 0xfU
2291 #define V_DEBUG_U_TX_EOP1_CNT(x) ((x) << S_DEBUG_U_TX_EOP1_CNT)
2292 #define G_DEBUG_U_TX_EOP1_CNT(x) (((x) >> S_DEBUG_U_TX_EOP1_CNT) & M_DEBUG_U_TX_EOP1_CNT)
2294 #define S_DEBUG_U_TX_SOP0_CNT 4
2295 #define M_DEBUG_U_TX_SOP0_CNT 0xfU
2296 #define V_DEBUG_U_TX_SOP0_CNT(x) ((x) << S_DEBUG_U_TX_SOP0_CNT)
2297 #define G_DEBUG_U_TX_SOP0_CNT(x) (((x) >> S_DEBUG_U_TX_SOP0_CNT) & M_DEBUG_U_TX_SOP0_CNT)
2299 #define S_DEBUG_U_TX_EOP0_CNT 0
2300 #define M_DEBUG_U_TX_EOP0_CNT 0xfU
2301 #define V_DEBUG_U_TX_EOP0_CNT(x) ((x) << S_DEBUG_U_TX_EOP0_CNT)
2302 #define G_DEBUG_U_TX_EOP0_CNT(x) (((x) >> S_DEBUG_U_TX_EOP0_CNT) & M_DEBUG_U_TX_EOP0_CNT)
2304 #define A_SGE_DEBUG_DATA_HIGH_INDEX_4 0x1290
2306 #define S_DEBUG_PC_RSP_SOP1_CNT 28
2307 #define M_DEBUG_PC_RSP_SOP1_CNT 0xfU
2308 #define V_DEBUG_PC_RSP_SOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP1_CNT)
2309 #define G_DEBUG_PC_RSP_SOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP1_CNT) & M_DEBUG_PC_RSP_SOP1_CNT)
2311 #define S_DEBUG_PC_RSP_EOP1_CNT 24
2312 #define M_DEBUG_PC_RSP_EOP1_CNT 0xfU
2313 #define V_DEBUG_PC_RSP_EOP1_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP1_CNT)
2314 #define G_DEBUG_PC_RSP_EOP1_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP1_CNT) & M_DEBUG_PC_RSP_EOP1_CNT)
2316 #define S_DEBUG_PC_RSP_SOP0_CNT 20
2317 #define M_DEBUG_PC_RSP_SOP0_CNT 0xfU
2318 #define V_DEBUG_PC_RSP_SOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP0_CNT)
2319 #define G_DEBUG_PC_RSP_SOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP0_CNT) & M_DEBUG_PC_RSP_SOP0_CNT)
2321 #define S_DEBUG_PC_RSP_EOP0_CNT 16
2322 #define M_DEBUG_PC_RSP_EOP0_CNT 0xfU
2323 #define V_DEBUG_PC_RSP_EOP0_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP0_CNT)
2324 #define G_DEBUG_PC_RSP_EOP0_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP0_CNT) & M_DEBUG_PC_RSP_EOP0_CNT)
2326 #define S_DEBUG_PC_REQ_SOP1_CNT 12
2327 #define M_DEBUG_PC_REQ_SOP1_CNT 0xfU
2328 #define V_DEBUG_PC_REQ_SOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP1_CNT)
2329 #define G_DEBUG_PC_REQ_SOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP1_CNT) & M_DEBUG_PC_REQ_SOP1_CNT)
2331 #define S_DEBUG_PC_REQ_EOP1_CNT 8
2332 #define M_DEBUG_PC_REQ_EOP1_CNT 0xfU
2333 #define V_DEBUG_PC_REQ_EOP1_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP1_CNT)
2334 #define G_DEBUG_PC_REQ_EOP1_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP1_CNT) & M_DEBUG_PC_REQ_EOP1_CNT)
2336 #define S_DEBUG_PC_REQ_SOP0_CNT 4
2337 #define M_DEBUG_PC_REQ_SOP0_CNT 0xfU
2338 #define V_DEBUG_PC_REQ_SOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP0_CNT)
2339 #define G_DEBUG_PC_REQ_SOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP0_CNT) & M_DEBUG_PC_REQ_SOP0_CNT)
2341 #define S_DEBUG_PC_REQ_EOP0_CNT 0
2342 #define M_DEBUG_PC_REQ_EOP0_CNT 0xfU
2343 #define V_DEBUG_PC_REQ_EOP0_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP0_CNT)
2344 #define G_DEBUG_PC_REQ_EOP0_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP0_CNT) & M_DEBUG_PC_REQ_EOP0_CNT)
2346 #define A_SGE_DEBUG_DATA_HIGH_INDEX_5 0x1294
2348 #define S_DEBUG_PD_RDREQ_SOP3_CNT 28
2349 #define M_DEBUG_PD_RDREQ_SOP3_CNT 0xfU
2350 #define V_DEBUG_PD_RDREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP3_CNT)
2351 #define G_DEBUG_PD_RDREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP3_CNT) & M_DEBUG_PD_RDREQ_SOP3_CNT)
2353 #define S_DEBUG_PD_RDREQ_EOP3_CNT 24
2354 #define M_DEBUG_PD_RDREQ_EOP3_CNT 0xfU
2355 #define V_DEBUG_PD_RDREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP3_CNT)
2356 #define G_DEBUG_PD_RDREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP3_CNT) & M_DEBUG_PD_RDREQ_EOP3_CNT)
2358 #define S_DEBUG_PD_RDREQ_SOP2_CNT 20
2359 #define M_DEBUG_PD_RDREQ_SOP2_CNT 0xfU
2360 #define V_DEBUG_PD_RDREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP2_CNT)
2361 #define G_DEBUG_PD_RDREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP2_CNT) & M_DEBUG_PD_RDREQ_SOP2_CNT)
2363 #define S_DEBUG_PD_RDREQ_EOP2_CNT 16
2364 #define M_DEBUG_PD_RDREQ_EOP2_CNT 0xfU
2365 #define V_DEBUG_PD_RDREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP2_CNT)
2366 #define G_DEBUG_PD_RDREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP2_CNT) & M_DEBUG_PD_RDREQ_EOP2_CNT)
2368 #define S_DEBUG_PD_RDREQ_SOP1_CNT 12
2369 #define M_DEBUG_PD_RDREQ_SOP1_CNT 0xfU
2370 #define V_DEBUG_PD_RDREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP1_CNT)
2371 #define G_DEBUG_PD_RDREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP1_CNT) & M_DEBUG_PD_RDREQ_SOP1_CNT)
2373 #define S_DEBUG_PD_RDREQ_EOP1_CNT 8
2374 #define M_DEBUG_PD_RDREQ_EOP1_CNT 0xfU
2375 #define V_DEBUG_PD_RDREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP1_CNT)
2376 #define G_DEBUG_PD_RDREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP1_CNT) & M_DEBUG_PD_RDREQ_EOP1_CNT)
2378 #define S_DEBUG_PD_RDREQ_SOP0_CNT 4
2379 #define M_DEBUG_PD_RDREQ_SOP0_CNT 0xfU
2380 #define V_DEBUG_PD_RDREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_SOP0_CNT)
2381 #define G_DEBUG_PD_RDREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_SOP0_CNT) & M_DEBUG_PD_RDREQ_SOP0_CNT)
2383 #define S_DEBUG_PD_RDREQ_EOP0_CNT 0
2384 #define M_DEBUG_PD_RDREQ_EOP0_CNT 0xfU
2385 #define V_DEBUG_PD_RDREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDREQ_EOP0_CNT)
2386 #define G_DEBUG_PD_RDREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDREQ_EOP0_CNT) & M_DEBUG_PD_RDREQ_EOP0_CNT)
2388 #define A_SGE_DEBUG_DATA_HIGH_INDEX_6 0x1298
2390 #define S_DEBUG_PD_RDRSP_SOP3_CNT 28
2391 #define M_DEBUG_PD_RDRSP_SOP3_CNT 0xfU
2392 #define V_DEBUG_PD_RDRSP_SOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP3_CNT)
2393 #define G_DEBUG_PD_RDRSP_SOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP3_CNT) & M_DEBUG_PD_RDRSP_SOP3_CNT)
2395 #define S_DEBUG_PD_RDRSP_EOP3_CNT 24
2396 #define M_DEBUG_PD_RDRSP_EOP3_CNT 0xfU
2397 #define V_DEBUG_PD_RDRSP_EOP3_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP3_CNT)
2398 #define G_DEBUG_PD_RDRSP_EOP3_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP3_CNT) & M_DEBUG_PD_RDRSP_EOP3_CNT)
2400 #define S_DEBUG_PD_RDRSP_SOP2_CNT 20
2401 #define M_DEBUG_PD_RDRSP_SOP2_CNT 0xfU
2402 #define V_DEBUG_PD_RDRSP_SOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP2_CNT)
2403 #define G_DEBUG_PD_RDRSP_SOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP2_CNT) & M_DEBUG_PD_RDRSP_SOP2_CNT)
2405 #define S_DEBUG_PD_RDRSP_EOP2_CNT 16
2406 #define M_DEBUG_PD_RDRSP_EOP2_CNT 0xfU
2407 #define V_DEBUG_PD_RDRSP_EOP2_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP2_CNT)
2408 #define G_DEBUG_PD_RDRSP_EOP2_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP2_CNT) & M_DEBUG_PD_RDRSP_EOP2_CNT)
2410 #define S_DEBUG_PD_RDRSP_SOP1_CNT 12
2411 #define M_DEBUG_PD_RDRSP_SOP1_CNT 0xfU
2412 #define V_DEBUG_PD_RDRSP_SOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP1_CNT)
2413 #define G_DEBUG_PD_RDRSP_SOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP1_CNT) & M_DEBUG_PD_RDRSP_SOP1_CNT)
2415 #define S_DEBUG_PD_RDRSP_EOP1_CNT 8
2416 #define M_DEBUG_PD_RDRSP_EOP1_CNT 0xfU
2417 #define V_DEBUG_PD_RDRSP_EOP1_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP1_CNT)
2418 #define G_DEBUG_PD_RDRSP_EOP1_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP1_CNT) & M_DEBUG_PD_RDRSP_EOP1_CNT)
2420 #define S_DEBUG_PD_RDRSP_SOP0_CNT 4
2421 #define M_DEBUG_PD_RDRSP_SOP0_CNT 0xfU
2422 #define V_DEBUG_PD_RDRSP_SOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_SOP0_CNT)
2423 #define G_DEBUG_PD_RDRSP_SOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_SOP0_CNT) & M_DEBUG_PD_RDRSP_SOP0_CNT)
2425 #define S_DEBUG_PD_RDRSP_EOP0_CNT 0
2426 #define M_DEBUG_PD_RDRSP_EOP0_CNT 0xfU
2427 #define V_DEBUG_PD_RDRSP_EOP0_CNT(x) ((x) << S_DEBUG_PD_RDRSP_EOP0_CNT)
2428 #define G_DEBUG_PD_RDRSP_EOP0_CNT(x) (((x) >> S_DEBUG_PD_RDRSP_EOP0_CNT) & M_DEBUG_PD_RDRSP_EOP0_CNT)
2430 #define A_SGE_DEBUG_DATA_HIGH_INDEX_7 0x129c
2432 #define S_DEBUG_PD_WRREQ_SOP3_CNT 28
2433 #define M_DEBUG_PD_WRREQ_SOP3_CNT 0xfU
2434 #define V_DEBUG_PD_WRREQ_SOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP3_CNT)
2435 #define G_DEBUG_PD_WRREQ_SOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP3_CNT) & M_DEBUG_PD_WRREQ_SOP3_CNT)
2437 #define S_DEBUG_PD_WRREQ_EOP3_CNT 24
2438 #define M_DEBUG_PD_WRREQ_EOP3_CNT 0xfU
2439 #define V_DEBUG_PD_WRREQ_EOP3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP3_CNT)
2440 #define G_DEBUG_PD_WRREQ_EOP3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP3_CNT) & M_DEBUG_PD_WRREQ_EOP3_CNT)
2442 #define S_DEBUG_PD_WRREQ_SOP2_CNT 20
2443 #define M_DEBUG_PD_WRREQ_SOP2_CNT 0xfU
2444 #define V_DEBUG_PD_WRREQ_SOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP2_CNT)
2445 #define G_DEBUG_PD_WRREQ_SOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP2_CNT) & M_DEBUG_PD_WRREQ_SOP2_CNT)
2447 #define S_DEBUG_PD_WRREQ_EOP2_CNT 16
2448 #define M_DEBUG_PD_WRREQ_EOP2_CNT 0xfU
2449 #define V_DEBUG_PD_WRREQ_EOP2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP2_CNT)
2450 #define G_DEBUG_PD_WRREQ_EOP2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP2_CNT) & M_DEBUG_PD_WRREQ_EOP2_CNT)
2452 #define S_DEBUG_PD_WRREQ_SOP1_CNT 12
2453 #define M_DEBUG_PD_WRREQ_SOP1_CNT 0xfU
2454 #define V_DEBUG_PD_WRREQ_SOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP1_CNT)
2455 #define G_DEBUG_PD_WRREQ_SOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP1_CNT) & M_DEBUG_PD_WRREQ_SOP1_CNT)
2457 #define S_DEBUG_PD_WRREQ_EOP1_CNT 8
2458 #define M_DEBUG_PD_WRREQ_EOP1_CNT 0xfU
2459 #define V_DEBUG_PD_WRREQ_EOP1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP1_CNT)
2460 #define G_DEBUG_PD_WRREQ_EOP1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP1_CNT) & M_DEBUG_PD_WRREQ_EOP1_CNT)
2462 #define S_DEBUG_PD_WRREQ_SOP0_CNT 4
2463 #define M_DEBUG_PD_WRREQ_SOP0_CNT 0xfU
2464 #define V_DEBUG_PD_WRREQ_SOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_SOP0_CNT)
2465 #define G_DEBUG_PD_WRREQ_SOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_SOP0_CNT) & M_DEBUG_PD_WRREQ_SOP0_CNT)
2467 #define S_DEBUG_PD_WRREQ_EOP0_CNT 0
2468 #define M_DEBUG_PD_WRREQ_EOP0_CNT 0xfU
2469 #define V_DEBUG_PD_WRREQ_EOP0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_EOP0_CNT)
2470 #define G_DEBUG_PD_WRREQ_EOP0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_EOP0_CNT) & M_DEBUG_PD_WRREQ_EOP0_CNT)
2472 #define A_SGE_DEBUG_DATA_HIGH_INDEX_8 0x12a0
2474 #define S_GLOBALENABLE_OFF 29
2475 #define V_GLOBALENABLE_OFF(x) ((x) << S_GLOBALENABLE_OFF)
2476 #define F_GLOBALENABLE_OFF V_GLOBALENABLE_OFF(1U)
2478 #define S_DEBUG_CIM2SGE_RXAFULL_D 27
2479 #define M_DEBUG_CIM2SGE_RXAFULL_D 0x3U
2480 #define V_DEBUG_CIM2SGE_RXAFULL_D(x) ((x) << S_DEBUG_CIM2SGE_RXAFULL_D)
2481 #define G_DEBUG_CIM2SGE_RXAFULL_D(x) (((x) >> S_DEBUG_CIM2SGE_RXAFULL_D) & M_DEBUG_CIM2SGE_RXAFULL_D)
2483 #define S_DEBUG_CPLSW_CIM_TXAFULL_D 25
2484 #define M_DEBUG_CPLSW_CIM_TXAFULL_D 0x3U
2485 #define V_DEBUG_CPLSW_CIM_TXAFULL_D(x) ((x) << S_DEBUG_CPLSW_CIM_TXAFULL_D)
2486 #define G_DEBUG_CPLSW_CIM_TXAFULL_D(x) (((x) >> S_DEBUG_CPLSW_CIM_TXAFULL_D) & M_DEBUG_CPLSW_CIM_TXAFULL_D)
2488 #define S_DEBUG_UP_FULL 24
2489 #define V_DEBUG_UP_FULL(x) ((x) << S_DEBUG_UP_FULL)
2490 #define F_DEBUG_UP_FULL V_DEBUG_UP_FULL(1U)
2492 #define S_DEBUG_M_RD_REQ_OUTSTANDING_PC 23
2493 #define V_DEBUG_M_RD_REQ_OUTSTANDING_PC(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_PC)
2494 #define F_DEBUG_M_RD_REQ_OUTSTANDING_PC V_DEBUG_M_RD_REQ_OUTSTANDING_PC(1U)
2496 #define S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO 22
2497 #define V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO)
2498 #define F_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO V_DEBUG_M_RD_REQ_OUTSTANDING_VFIFO(1U)
2500 #define S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG 21
2501 #define V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_IMSG)
2502 #define F_DEBUG_M_RD_REQ_OUTSTANDING_IMSG V_DEBUG_M_RD_REQ_OUTSTANDING_IMSG(1U)
2504 #define S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB 20
2505 #define V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_CMARB)
2506 #define F_DEBUG_M_RD_REQ_OUTSTANDING_CMARB V_DEBUG_M_RD_REQ_OUTSTANDING_CMARB(1U)
2508 #define S_DEBUG_M_RD_REQ_OUTSTANDING_FLM 19
2509 #define V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(x) ((x) << S_DEBUG_M_RD_REQ_OUTSTANDING_FLM)
2510 #define F_DEBUG_M_RD_REQ_OUTSTANDING_FLM V_DEBUG_M_RD_REQ_OUTSTANDING_FLM(1U)
2512 #define S_DEBUG_M_REQVLD 18
2513 #define V_DEBUG_M_REQVLD(x) ((x) << S_DEBUG_M_REQVLD)
2514 #define F_DEBUG_M_REQVLD V_DEBUG_M_REQVLD(1U)
2516 #define S_DEBUG_M_REQRDY 17
2517 #define V_DEBUG_M_REQRDY(x) ((x) << S_DEBUG_M_REQRDY)
2518 #define F_DEBUG_M_REQRDY V_DEBUG_M_REQRDY(1U)
2520 #define S_DEBUG_M_RSPVLD 16
2521 #define V_DEBUG_M_RSPVLD(x) ((x) << S_DEBUG_M_RSPVLD)
2522 #define F_DEBUG_M_RSPVLD V_DEBUG_M_RSPVLD(1U)
2524 #define S_DEBUG_PD_WRREQ_INT3_CNT 12
2525 #define M_DEBUG_PD_WRREQ_INT3_CNT 0xfU
2526 #define V_DEBUG_PD_WRREQ_INT3_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT3_CNT)
2527 #define G_DEBUG_PD_WRREQ_INT3_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT3_CNT) & M_DEBUG_PD_WRREQ_INT3_CNT)
2529 #define S_DEBUG_PD_WRREQ_INT2_CNT 8
2530 #define M_DEBUG_PD_WRREQ_INT2_CNT 0xfU
2531 #define V_DEBUG_PD_WRREQ_INT2_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT2_CNT)
2532 #define G_DEBUG_PD_WRREQ_INT2_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT2_CNT) & M_DEBUG_PD_WRREQ_INT2_CNT)
2534 #define S_DEBUG_PD_WRREQ_INT1_CNT 4
2535 #define M_DEBUG_PD_WRREQ_INT1_CNT 0xfU
2536 #define V_DEBUG_PD_WRREQ_INT1_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT1_CNT)
2537 #define G_DEBUG_PD_WRREQ_INT1_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT1_CNT) & M_DEBUG_PD_WRREQ_INT1_CNT)
2539 #define S_DEBUG_PD_WRREQ_INT0_CNT 0
2540 #define M_DEBUG_PD_WRREQ_INT0_CNT 0xfU
2541 #define V_DEBUG_PD_WRREQ_INT0_CNT(x) ((x) << S_DEBUG_PD_WRREQ_INT0_CNT)
2542 #define G_DEBUG_PD_WRREQ_INT0_CNT(x) (((x) >> S_DEBUG_PD_WRREQ_INT0_CNT) & M_DEBUG_PD_WRREQ_INT0_CNT)
2544 #define A_SGE_DEBUG_DATA_HIGH_INDEX_9 0x12a4
2546 #define S_DEBUG_CPLSW_TP_RX_SOP1_CNT 28
2547 #define M_DEBUG_CPLSW_TP_RX_SOP1_CNT 0xfU
2548 #define V_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP1_CNT)
2549 #define G_DEBUG_CPLSW_TP_RX_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP1_CNT) & M_DEBUG_CPLSW_TP_RX_SOP1_CNT)
2551 #define S_DEBUG_CPLSW_TP_RX_EOP1_CNT 24
2552 #define M_DEBUG_CPLSW_TP_RX_EOP1_CNT 0xfU
2553 #define V_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP1_CNT)
2554 #define G_DEBUG_CPLSW_TP_RX_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP1_CNT) & M_DEBUG_CPLSW_TP_RX_EOP1_CNT)
2556 #define S_DEBUG_CPLSW_TP_RX_SOP0_CNT 20
2557 #define M_DEBUG_CPLSW_TP_RX_SOP0_CNT 0xfU
2558 #define V_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_SOP0_CNT)
2559 #define G_DEBUG_CPLSW_TP_RX_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_SOP0_CNT) & M_DEBUG_CPLSW_TP_RX_SOP0_CNT)
2561 #define S_DEBUG_CPLSW_TP_RX_EOP0_CNT 16
2562 #define M_DEBUG_CPLSW_TP_RX_EOP0_CNT 0xfU
2563 #define V_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_TP_RX_EOP0_CNT)
2564 #define G_DEBUG_CPLSW_TP_RX_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_TP_RX_EOP0_CNT) & M_DEBUG_CPLSW_TP_RX_EOP0_CNT)
2566 #define S_DEBUG_CPLSW_CIM_SOP1_CNT 12
2567 #define M_DEBUG_CPLSW_CIM_SOP1_CNT 0xfU
2568 #define V_DEBUG_CPLSW_CIM_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP1_CNT)
2569 #define G_DEBUG_CPLSW_CIM_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP1_CNT) & M_DEBUG_CPLSW_CIM_SOP1_CNT)
2571 #define S_DEBUG_CPLSW_CIM_EOP1_CNT 8
2572 #define M_DEBUG_CPLSW_CIM_EOP1_CNT 0xfU
2573 #define V_DEBUG_CPLSW_CIM_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP1_CNT)
2574 #define G_DEBUG_CPLSW_CIM_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP1_CNT) & M_DEBUG_CPLSW_CIM_EOP1_CNT)
2576 #define S_DEBUG_CPLSW_CIM_SOP0_CNT 4
2577 #define M_DEBUG_CPLSW_CIM_SOP0_CNT 0xfU
2578 #define V_DEBUG_CPLSW_CIM_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_SOP0_CNT)
2579 #define G_DEBUG_CPLSW_CIM_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_SOP0_CNT) & M_DEBUG_CPLSW_CIM_SOP0_CNT)
2581 #define S_DEBUG_CPLSW_CIM_EOP0_CNT 0
2582 #define M_DEBUG_CPLSW_CIM_EOP0_CNT 0xfU
2583 #define V_DEBUG_CPLSW_CIM_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_CIM_EOP0_CNT)
2584 #define G_DEBUG_CPLSW_CIM_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_CIM_EOP0_CNT) & M_DEBUG_CPLSW_CIM_EOP0_CNT)
2586 #define A_SGE_DEBUG_DATA_HIGH_INDEX_10 0x12a8
2588 #define S_DEBUG_T_RXAFULL_D 30
2589 #define M_DEBUG_T_RXAFULL_D 0x3U
2590 #define V_DEBUG_T_RXAFULL_D(x) ((x) << S_DEBUG_T_RXAFULL_D)
2591 #define G_DEBUG_T_RXAFULL_D(x) (((x) >> S_DEBUG_T_RXAFULL_D) & M_DEBUG_T_RXAFULL_D)
2593 #define S_DEBUG_PD_RDRSPAFULL_D 26
2594 #define M_DEBUG_PD_RDRSPAFULL_D 0xfU
2595 #define V_DEBUG_PD_RDRSPAFULL_D(x) ((x) << S_DEBUG_PD_RDRSPAFULL_D)
2596 #define G_DEBUG_PD_RDRSPAFULL_D(x) (((x) >> S_DEBUG_PD_RDRSPAFULL_D) & M_DEBUG_PD_RDRSPAFULL_D)
2598 #define S_DEBUG_PD_RDREQAFULL_D 22
2599 #define M_DEBUG_PD_RDREQAFULL_D 0xfU
2600 #define V_DEBUG_PD_RDREQAFULL_D(x) ((x) << S_DEBUG_PD_RDREQAFULL_D)
2601 #define G_DEBUG_PD_RDREQAFULL_D(x) (((x) >> S_DEBUG_PD_RDREQAFULL_D) & M_DEBUG_PD_RDREQAFULL_D)
2603 #define S_DEBUG_PD_WRREQAFULL_D 18
2604 #define M_DEBUG_PD_WRREQAFULL_D 0xfU
2605 #define V_DEBUG_PD_WRREQAFULL_D(x) ((x) << S_DEBUG_PD_WRREQAFULL_D)
2606 #define G_DEBUG_PD_WRREQAFULL_D(x) (((x) >> S_DEBUG_PD_WRREQAFULL_D) & M_DEBUG_PD_WRREQAFULL_D)
2608 #define S_DEBUG_PC_RSPAFULL_D 15
2609 #define M_DEBUG_PC_RSPAFULL_D 0x7U
2610 #define V_DEBUG_PC_RSPAFULL_D(x) ((x) << S_DEBUG_PC_RSPAFULL_D)
2611 #define G_DEBUG_PC_RSPAFULL_D(x) (((x) >> S_DEBUG_PC_RSPAFULL_D) & M_DEBUG_PC_RSPAFULL_D)
2613 #define S_DEBUG_PC_REQAFULL_D 12
2614 #define M_DEBUG_PC_REQAFULL_D 0x7U
2615 #define V_DEBUG_PC_REQAFULL_D(x) ((x) << S_DEBUG_PC_REQAFULL_D)
2616 #define G_DEBUG_PC_REQAFULL_D(x) (((x) >> S_DEBUG_PC_REQAFULL_D) & M_DEBUG_PC_REQAFULL_D)
2618 #define S_DEBUG_U_TXAFULL_D 8
2619 #define M_DEBUG_U_TXAFULL_D 0xfU
2620 #define V_DEBUG_U_TXAFULL_D(x) ((x) << S_DEBUG_U_TXAFULL_D)
2621 #define G_DEBUG_U_TXAFULL_D(x) (((x) >> S_DEBUG_U_TXAFULL_D) & M_DEBUG_U_TXAFULL_D)
2623 #define S_DEBUG_UD_RXAFULL_D 4
2624 #define M_DEBUG_UD_RXAFULL_D 0xfU
2625 #define V_DEBUG_UD_RXAFULL_D(x) ((x) << S_DEBUG_UD_RXAFULL_D)
2626 #define G_DEBUG_UD_RXAFULL_D(x) (((x) >> S_DEBUG_UD_RXAFULL_D) & M_DEBUG_UD_RXAFULL_D)
2628 #define S_DEBUG_U_RXAFULL_D 2
2629 #define M_DEBUG_U_RXAFULL_D 0x3U
2630 #define V_DEBUG_U_RXAFULL_D(x) ((x) << S_DEBUG_U_RXAFULL_D)
2631 #define G_DEBUG_U_RXAFULL_D(x) (((x) >> S_DEBUG_U_RXAFULL_D) & M_DEBUG_U_RXAFULL_D)
2633 #define S_DEBUG_CIM_AFULL_D 0
2634 #define M_DEBUG_CIM_AFULL_D 0x3U
2635 #define V_DEBUG_CIM_AFULL_D(x) ((x) << S_DEBUG_CIM_AFULL_D)
2636 #define G_DEBUG_CIM_AFULL_D(x) (((x) >> S_DEBUG_CIM_AFULL_D) & M_DEBUG_CIM_AFULL_D)
2638 #define A_SGE_DEBUG_DATA_HIGH_INDEX_11 0x12ac
2640 #define S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE 24
2641 #define V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE)
2642 #define F_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE V_DEBUG_FLM_IDMA1_CACHE_DATA_ACTIVE(1U)
2644 #define S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE 23
2645 #define V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE)
2646 #define F_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE V_DEBUG_FLM_IDMA1_CACHE_HDR_ACTIVE(1U)
2648 #define S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE 22
2649 #define V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE)
2650 #define F_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE V_DEBUG_FLM_IDMA1_CTXT_DATA_ACTIVE(1U)
2652 #define S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE 21
2653 #define V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE)
2654 #define F_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE V_DEBUG_FLM_IDMA1_CTXT_HDR_ACTIVE(1U)
2656 #define S_DEBUG_ST_FLM_IDMA1_CACHE 19
2657 #define M_DEBUG_ST_FLM_IDMA1_CACHE 0x3U
2658 #define V_DEBUG_ST_FLM_IDMA1_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CACHE)
2659 #define G_DEBUG_ST_FLM_IDMA1_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CACHE) & M_DEBUG_ST_FLM_IDMA1_CACHE)
2661 #define S_DEBUG_ST_FLM_IDMA1_CTXT 16
2662 #define M_DEBUG_ST_FLM_IDMA1_CTXT 0x7U
2663 #define V_DEBUG_ST_FLM_IDMA1_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA1_CTXT)
2664 #define G_DEBUG_ST_FLM_IDMA1_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA1_CTXT) & M_DEBUG_ST_FLM_IDMA1_CTXT)
2666 #define S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE 8
2667 #define V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE)
2668 #define F_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE V_DEBUG_FLM_IDMA0_CACHE_DATA_ACTIVE(1U)
2670 #define S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE 7
2671 #define V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE)
2672 #define F_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE V_DEBUG_FLM_IDMA0_CACHE_HDR_ACTIVE(1U)
2674 #define S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE 6
2675 #define V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE)
2676 #define F_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE V_DEBUG_FLM_IDMA0_CTXT_DATA_ACTIVE(1U)
2678 #define S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE 5
2679 #define V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(x) ((x) << S_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE)
2680 #define F_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE V_DEBUG_FLM_IDMA0_CTXT_HDR_ACTIVE(1U)
2682 #define S_DEBUG_ST_FLM_IDMA0_CACHE 3
2683 #define M_DEBUG_ST_FLM_IDMA0_CACHE 0x3U
2684 #define V_DEBUG_ST_FLM_IDMA0_CACHE(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CACHE)
2685 #define G_DEBUG_ST_FLM_IDMA0_CACHE(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CACHE) & M_DEBUG_ST_FLM_IDMA0_CACHE)
2687 #define S_DEBUG_ST_FLM_IDMA0_CTXT 0
2688 #define M_DEBUG_ST_FLM_IDMA0_CTXT 0x7U
2689 #define V_DEBUG_ST_FLM_IDMA0_CTXT(x) ((x) << S_DEBUG_ST_FLM_IDMA0_CTXT)
2690 #define G_DEBUG_ST_FLM_IDMA0_CTXT(x) (((x) >> S_DEBUG_ST_FLM_IDMA0_CTXT) & M_DEBUG_ST_FLM_IDMA0_CTXT)
2692 #define A_SGE_DEBUG_DATA_HIGH_INDEX_12 0x12b0
2694 #define S_DEBUG_CPLSW_SOP1_CNT 28
2695 #define M_DEBUG_CPLSW_SOP1_CNT 0xfU
2696 #define V_DEBUG_CPLSW_SOP1_CNT(x) ((x) << S_DEBUG_CPLSW_SOP1_CNT)
2697 #define G_DEBUG_CPLSW_SOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP1_CNT) & M_DEBUG_CPLSW_SOP1_CNT)
2699 #define S_DEBUG_CPLSW_EOP1_CNT 24
2700 #define M_DEBUG_CPLSW_EOP1_CNT 0xfU
2701 #define V_DEBUG_CPLSW_EOP1_CNT(x) ((x) << S_DEBUG_CPLSW_EOP1_CNT)
2702 #define G_DEBUG_CPLSW_EOP1_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP1_CNT) & M_DEBUG_CPLSW_EOP1_CNT)
2704 #define S_DEBUG_CPLSW_SOP0_CNT 20
2705 #define M_DEBUG_CPLSW_SOP0_CNT 0xfU
2706 #define V_DEBUG_CPLSW_SOP0_CNT(x) ((x) << S_DEBUG_CPLSW_SOP0_CNT)
2707 #define G_DEBUG_CPLSW_SOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_SOP0_CNT) & M_DEBUG_CPLSW_SOP0_CNT)
2709 #define S_DEBUG_CPLSW_EOP0_CNT 16
2710 #define M_DEBUG_CPLSW_EOP0_CNT 0xfU
2711 #define V_DEBUG_CPLSW_EOP0_CNT(x) ((x) << S_DEBUG_CPLSW_EOP0_CNT)
2712 #define G_DEBUG_CPLSW_EOP0_CNT(x) (((x) >> S_DEBUG_CPLSW_EOP0_CNT) & M_DEBUG_CPLSW_EOP0_CNT)
2714 #define S_DEBUG_PC_RSP_SOP2_CNT 12
2715 #define M_DEBUG_PC_RSP_SOP2_CNT 0xfU
2716 #define V_DEBUG_PC_RSP_SOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_SOP2_CNT)
2717 #define G_DEBUG_PC_RSP_SOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_SOP2_CNT) & M_DEBUG_PC_RSP_SOP2_CNT)
2719 #define S_DEBUG_PC_RSP_EOP2_CNT 8
2720 #define M_DEBUG_PC_RSP_EOP2_CNT 0xfU
2721 #define V_DEBUG_PC_RSP_EOP2_CNT(x) ((x) << S_DEBUG_PC_RSP_EOP2_CNT)
2722 #define G_DEBUG_PC_RSP_EOP2_CNT(x) (((x) >> S_DEBUG_PC_RSP_EOP2_CNT) & M_DEBUG_PC_RSP_EOP2_CNT)
2724 #define S_DEBUG_PC_REQ_SOP2_CNT 4
2725 #define M_DEBUG_PC_REQ_SOP2_CNT 0xfU
2726 #define V_DEBUG_PC_REQ_SOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_SOP2_CNT)
2727 #define G_DEBUG_PC_REQ_SOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_SOP2_CNT) & M_DEBUG_PC_REQ_SOP2_CNT)
2729 #define S_DEBUG_PC_REQ_EOP2_CNT 0
2730 #define M_DEBUG_PC_REQ_EOP2_CNT 0xfU
2731 #define V_DEBUG_PC_REQ_EOP2_CNT(x) ((x) << S_DEBUG_PC_REQ_EOP2_CNT)
2732 #define G_DEBUG_PC_REQ_EOP2_CNT(x) (((x) >> S_DEBUG_PC_REQ_EOP2_CNT) & M_DEBUG_PC_REQ_EOP2_CNT)
2734 #define A_SGE_DEBUG_DATA_HIGH_INDEX_13 0x12b4
2735 #define A_SGE_DEBUG_DATA_HIGH_INDEX_14 0x12b8
2736 #define A_SGE_DEBUG_DATA_HIGH_INDEX_15 0x12bc
2737 #define A_SGE_DEBUG_DATA_LOW_INDEX_0 0x12c0
2739 #define S_DEBUG_ST_IDMA1_FLM_REQ 29
2740 #define M_DEBUG_ST_IDMA1_FLM_REQ 0x7U
2741 #define V_DEBUG_ST_IDMA1_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA1_FLM_REQ)
2742 #define G_DEBUG_ST_IDMA1_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA1_FLM_REQ) & M_DEBUG_ST_IDMA1_FLM_REQ)
2744 #define S_DEBUG_ST_IDMA0_FLM_REQ 26
2745 #define M_DEBUG_ST_IDMA0_FLM_REQ 0x7U
2746 #define V_DEBUG_ST_IDMA0_FLM_REQ(x) ((x) << S_DEBUG_ST_IDMA0_FLM_REQ)
2747 #define G_DEBUG_ST_IDMA0_FLM_REQ(x) (((x) >> S_DEBUG_ST_IDMA0_FLM_REQ) & M_DEBUG_ST_IDMA0_FLM_REQ)
2749 #define S_DEBUG_ST_IMSG_CTXT 23
2750 #define M_DEBUG_ST_IMSG_CTXT 0x7U
2751 #define V_DEBUG_ST_IMSG_CTXT(x) ((x) << S_DEBUG_ST_IMSG_CTXT)
2752 #define G_DEBUG_ST_IMSG_CTXT(x) (((x) >> S_DEBUG_ST_IMSG_CTXT) & M_DEBUG_ST_IMSG_CTXT)
2754 #define S_DEBUG_ST_IMSG 18
2755 #define M_DEBUG_ST_IMSG 0x1fU
2756 #define V_DEBUG_ST_IMSG(x) ((x) << S_DEBUG_ST_IMSG)
2757 #define G_DEBUG_ST_IMSG(x) (((x) >> S_DEBUG_ST_IMSG) & M_DEBUG_ST_IMSG)
2759 #define S_DEBUG_ST_IDMA1_IALN 16
2760 #define M_DEBUG_ST_IDMA1_IALN 0x3U
2761 #define V_DEBUG_ST_IDMA1_IALN(x) ((x) << S_DEBUG_ST_IDMA1_IALN)
2762 #define G_DEBUG_ST_IDMA1_IALN(x) (((x) >> S_DEBUG_ST_IDMA1_IALN) & M_DEBUG_ST_IDMA1_IALN)
2764 #define S_DEBUG_ST_IDMA1_IDMA_SM 9
2765 #define M_DEBUG_ST_IDMA1_IDMA_SM 0x3fU
2766 #define V_DEBUG_ST_IDMA1_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA1_IDMA_SM)
2767 #define G_DEBUG_ST_IDMA1_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA1_IDMA_SM) & M_DEBUG_ST_IDMA1_IDMA_SM)
2769 #define S_DEBUG_ST_IDMA0_IALN 7
2770 #define M_DEBUG_ST_IDMA0_IALN 0x3U
2771 #define V_DEBUG_ST_IDMA0_IALN(x) ((x) << S_DEBUG_ST_IDMA0_IALN)
2772 #define G_DEBUG_ST_IDMA0_IALN(x) (((x) >> S_DEBUG_ST_IDMA0_IALN) & M_DEBUG_ST_IDMA0_IALN)
2774 #define S_DEBUG_ST_IDMA0_IDMA_SM 0
2775 #define M_DEBUG_ST_IDMA0_IDMA_SM 0x3fU
2776 #define V_DEBUG_ST_IDMA0_IDMA_SM(x) ((x) << S_DEBUG_ST_IDMA0_IDMA_SM)
2777 #define G_DEBUG_ST_IDMA0_IDMA_SM(x) (((x) >> S_DEBUG_ST_IDMA0_IDMA_SM) & M_DEBUG_ST_IDMA0_IDMA_SM)
2779 #define A_SGE_DEBUG_DATA_LOW_INDEX_1 0x12c4
2781 #define S_DEBUG_ITP_EMPTY 12
2782 #define M_DEBUG_ITP_EMPTY 0x3fU
2783 #define V_DEBUG_ITP_EMPTY(x) ((x) << S_DEBUG_ITP_EMPTY)
2784 #define G_DEBUG_ITP_EMPTY(x) (((x) >> S_DEBUG_ITP_EMPTY) & M_DEBUG_ITP_EMPTY)
2786 #define S_DEBUG_ITP_EXPIRED 6
2787 #define M_DEBUG_ITP_EXPIRED 0x3fU
2788 #define V_DEBUG_ITP_EXPIRED(x) ((x) << S_DEBUG_ITP_EXPIRED)
2789 #define G_DEBUG_ITP_EXPIRED(x) (((x) >> S_DEBUG_ITP_EXPIRED) & M_DEBUG_ITP_EXPIRED)
2791 #define S_DEBUG_ITP_PAUSE 5
2792 #define V_DEBUG_ITP_PAUSE(x) ((x) << S_DEBUG_ITP_PAUSE)
2793 #define F_DEBUG_ITP_PAUSE V_DEBUG_ITP_PAUSE(1U)
2795 #define S_DEBUG_ITP_DEL_DONE 4
2796 #define V_DEBUG_ITP_DEL_DONE(x) ((x) << S_DEBUG_ITP_DEL_DONE)
2797 #define F_DEBUG_ITP_DEL_DONE V_DEBUG_ITP_DEL_DONE(1U)
2799 #define S_DEBUG_ITP_ADD_DONE 3
2800 #define V_DEBUG_ITP_ADD_DONE(x) ((x) << S_DEBUG_ITP_ADD_DONE)
2801 #define F_DEBUG_ITP_ADD_DONE V_DEBUG_ITP_ADD_DONE(1U)
2803 #define S_DEBUG_ITP_EVR_STATE 0
2804 #define M_DEBUG_ITP_EVR_STATE 0x7U
2805 #define V_DEBUG_ITP_EVR_STATE(x) ((x) << S_DEBUG_ITP_EVR_STATE)
2806 #define G_DEBUG_ITP_EVR_STATE(x) (((x) >> S_DEBUG_ITP_EVR_STATE) & M_DEBUG_ITP_EVR_STATE)
2808 #define A_SGE_DEBUG_DATA_LOW_INDEX_2 0x12c8
2810 #define S_DEBUG_ST_DBP_THREAD2_CIMFL 25
2811 #define M_DEBUG_ST_DBP_THREAD2_CIMFL 0x1fU
2812 #define V_DEBUG_ST_DBP_THREAD2_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD2_CIMFL)
2813 #define G_DEBUG_ST_DBP_THREAD2_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_CIMFL) & M_DEBUG_ST_DBP_THREAD2_CIMFL)
2815 #define S_DEBUG_ST_DBP_THREAD2_MAIN 20
2816 #define M_DEBUG_ST_DBP_THREAD2_MAIN 0x1fU
2817 #define V_DEBUG_ST_DBP_THREAD2_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD2_MAIN)
2818 #define G_DEBUG_ST_DBP_THREAD2_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD2_MAIN) & M_DEBUG_ST_DBP_THREAD2_MAIN)
2820 #define S_DEBUG_ST_DBP_THREAD1_CIMFL 15
2821 #define M_DEBUG_ST_DBP_THREAD1_CIMFL 0x1fU
2822 #define V_DEBUG_ST_DBP_THREAD1_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD1_CIMFL)
2823 #define G_DEBUG_ST_DBP_THREAD1_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_CIMFL) & M_DEBUG_ST_DBP_THREAD1_CIMFL)
2825 #define S_DEBUG_ST_DBP_THREAD1_MAIN 10
2826 #define M_DEBUG_ST_DBP_THREAD1_MAIN 0x1fU
2827 #define V_DEBUG_ST_DBP_THREAD1_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD1_MAIN)
2828 #define G_DEBUG_ST_DBP_THREAD1_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD1_MAIN) & M_DEBUG_ST_DBP_THREAD1_MAIN)
2830 #define S_DEBUG_ST_DBP_THREAD0_CIMFL 5
2831 #define M_DEBUG_ST_DBP_THREAD0_CIMFL 0x1fU
2832 #define V_DEBUG_ST_DBP_THREAD0_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD0_CIMFL)
2833 #define G_DEBUG_ST_DBP_THREAD0_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_CIMFL) & M_DEBUG_ST_DBP_THREAD0_CIMFL)
2835 #define S_DEBUG_ST_DBP_THREAD0_MAIN 0
2836 #define M_DEBUG_ST_DBP_THREAD0_MAIN 0x1fU
2837 #define V_DEBUG_ST_DBP_THREAD0_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD0_MAIN)
2838 #define G_DEBUG_ST_DBP_THREAD0_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD0_MAIN) & M_DEBUG_ST_DBP_THREAD0_MAIN)
2840 #define A_SGE_DEBUG_DATA_LOW_INDEX_3 0x12cc
2842 #define S_DEBUG_ST_DBP_UPCP_MAIN 14
2843 #define M_DEBUG_ST_DBP_UPCP_MAIN 0x1fU
2844 #define V_DEBUG_ST_DBP_UPCP_MAIN(x) ((x) << S_DEBUG_ST_DBP_UPCP_MAIN)
2845 #define G_DEBUG_ST_DBP_UPCP_MAIN(x) (((x) >> S_DEBUG_ST_DBP_UPCP_MAIN) & M_DEBUG_ST_DBP_UPCP_MAIN)
2847 #define S_DEBUG_ST_DBP_DBFIFO_MAIN 13
2848 #define V_DEBUG_ST_DBP_DBFIFO_MAIN(x) ((x) << S_DEBUG_ST_DBP_DBFIFO_MAIN)
2849 #define F_DEBUG_ST_DBP_DBFIFO_MAIN V_DEBUG_ST_DBP_DBFIFO_MAIN(1U)
2851 #define S_DEBUG_ST_DBP_CTXT 10
2852 #define M_DEBUG_ST_DBP_CTXT 0x7U
2853 #define V_DEBUG_ST_DBP_CTXT(x) ((x) << S_DEBUG_ST_DBP_CTXT)
2854 #define G_DEBUG_ST_DBP_CTXT(x) (((x) >> S_DEBUG_ST_DBP_CTXT) & M_DEBUG_ST_DBP_CTXT)
2856 #define S_DEBUG_ST_DBP_THREAD3_CIMFL 5
2857 #define M_DEBUG_ST_DBP_THREAD3_CIMFL 0x1fU
2858 #define V_DEBUG_ST_DBP_THREAD3_CIMFL(x) ((x) << S_DEBUG_ST_DBP_THREAD3_CIMFL)
2859 #define G_DEBUG_ST_DBP_THREAD3_CIMFL(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_CIMFL) & M_DEBUG_ST_DBP_THREAD3_CIMFL)
2861 #define S_DEBUG_ST_DBP_THREAD3_MAIN 0
2862 #define M_DEBUG_ST_DBP_THREAD3_MAIN 0x1fU
2863 #define V_DEBUG_ST_DBP_THREAD3_MAIN(x) ((x) << S_DEBUG_ST_DBP_THREAD3_MAIN)
2864 #define G_DEBUG_ST_DBP_THREAD3_MAIN(x) (((x) >> S_DEBUG_ST_DBP_THREAD3_MAIN) & M_DEBUG_ST_DBP_THREAD3_MAIN)
2866 #define A_SGE_DEBUG_DATA_LOW_INDEX_4 0x12d0
2868 #define S_DEBUG_ST_EDMA3_ALIGN_SUB 29
2869 #define M_DEBUG_ST_EDMA3_ALIGN_SUB 0x7U
2870 #define V_DEBUG_ST_EDMA3_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN_SUB)
2871 #define G_DEBUG_ST_EDMA3_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN_SUB) & M_DEBUG_ST_EDMA3_ALIGN_SUB)
2873 #define S_DEBUG_ST_EDMA3_ALIGN 27
2874 #define M_DEBUG_ST_EDMA3_ALIGN 0x3U
2875 #define V_DEBUG_ST_EDMA3_ALIGN(x) ((x) << S_DEBUG_ST_EDMA3_ALIGN)
2876 #define G_DEBUG_ST_EDMA3_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA3_ALIGN) & M_DEBUG_ST_EDMA3_ALIGN)
2878 #define S_DEBUG_ST_EDMA3_REQ 24
2879 #define M_DEBUG_ST_EDMA3_REQ 0x7U
2880 #define V_DEBUG_ST_EDMA3_REQ(x) ((x) << S_DEBUG_ST_EDMA3_REQ)
2881 #define G_DEBUG_ST_EDMA3_REQ(x) (((x) >> S_DEBUG_ST_EDMA3_REQ) & M_DEBUG_ST_EDMA3_REQ)
2883 #define S_DEBUG_ST_EDMA2_ALIGN_SUB 21
2884 #define M_DEBUG_ST_EDMA2_ALIGN_SUB 0x7U
2885 #define V_DEBUG_ST_EDMA2_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN_SUB)
2886 #define G_DEBUG_ST_EDMA2_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN_SUB) & M_DEBUG_ST_EDMA2_ALIGN_SUB)
2888 #define S_DEBUG_ST_EDMA2_ALIGN 19
2889 #define M_DEBUG_ST_EDMA2_ALIGN 0x3U
2890 #define V_DEBUG_ST_EDMA2_ALIGN(x) ((x) << S_DEBUG_ST_EDMA2_ALIGN)
2891 #define G_DEBUG_ST_EDMA2_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA2_ALIGN) & M_DEBUG_ST_EDMA2_ALIGN)
2893 #define S_DEBUG_ST_EDMA2_REQ 16
2894 #define M_DEBUG_ST_EDMA2_REQ 0x7U
2895 #define V_DEBUG_ST_EDMA2_REQ(x) ((x) << S_DEBUG_ST_EDMA2_REQ)
2896 #define G_DEBUG_ST_EDMA2_REQ(x) (((x) >> S_DEBUG_ST_EDMA2_REQ) & M_DEBUG_ST_EDMA2_REQ)
2898 #define S_DEBUG_ST_EDMA1_ALIGN_SUB 13
2899 #define M_DEBUG_ST_EDMA1_ALIGN_SUB 0x7U
2900 #define V_DEBUG_ST_EDMA1_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN_SUB)
2901 #define G_DEBUG_ST_EDMA1_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN_SUB) & M_DEBUG_ST_EDMA1_ALIGN_SUB)
2903 #define S_DEBUG_ST_EDMA1_ALIGN 11
2904 #define M_DEBUG_ST_EDMA1_ALIGN 0x3U
2905 #define V_DEBUG_ST_EDMA1_ALIGN(x) ((x) << S_DEBUG_ST_EDMA1_ALIGN)
2906 #define G_DEBUG_ST_EDMA1_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA1_ALIGN) & M_DEBUG_ST_EDMA1_ALIGN)
2908 #define S_DEBUG_ST_EDMA1_REQ 8
2909 #define M_DEBUG_ST_EDMA1_REQ 0x7U
2910 #define V_DEBUG_ST_EDMA1_REQ(x) ((x) << S_DEBUG_ST_EDMA1_REQ)
2911 #define G_DEBUG_ST_EDMA1_REQ(x) (((x) >> S_DEBUG_ST_EDMA1_REQ) & M_DEBUG_ST_EDMA1_REQ)
2913 #define S_DEBUG_ST_EDMA0_ALIGN_SUB 5
2914 #define M_DEBUG_ST_EDMA0_ALIGN_SUB 0x7U
2915 #define V_DEBUG_ST_EDMA0_ALIGN_SUB(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN_SUB)
2916 #define G_DEBUG_ST_EDMA0_ALIGN_SUB(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN_SUB) & M_DEBUG_ST_EDMA0_ALIGN_SUB)
2918 #define S_DEBUG_ST_EDMA0_ALIGN 3
2919 #define M_DEBUG_ST_EDMA0_ALIGN 0x3U
2920 #define V_DEBUG_ST_EDMA0_ALIGN(x) ((x) << S_DEBUG_ST_EDMA0_ALIGN)
2921 #define G_DEBUG_ST_EDMA0_ALIGN(x) (((x) >> S_DEBUG_ST_EDMA0_ALIGN) & M_DEBUG_ST_EDMA0_ALIGN)
2923 #define S_DEBUG_ST_EDMA0_REQ 0
2924 #define M_DEBUG_ST_EDMA0_REQ 0x7U
2925 #define V_DEBUG_ST_EDMA0_REQ(x) ((x) << S_DEBUG_ST_EDMA0_REQ)
2926 #define G_DEBUG_ST_EDMA0_REQ(x) (((x) >> S_DEBUG_ST_EDMA0_REQ) & M_DEBUG_ST_EDMA0_REQ)
2928 #define A_SGE_DEBUG_DATA_LOW_INDEX_5 0x12d4
2930 #define S_DEBUG_ST_FLM_DBPTR 30
2931 #define M_DEBUG_ST_FLM_DBPTR 0x3U
2932 #define V_DEBUG_ST_FLM_DBPTR(x) ((x) << S_DEBUG_ST_FLM_DBPTR)
2933 #define G_DEBUG_ST_FLM_DBPTR(x) (((x) >> S_DEBUG_ST_FLM_DBPTR) & M_DEBUG_ST_FLM_DBPTR)
2935 #define S_DEBUG_FLM_CACHE_LOCKED_COUNT 23
2936 #define M_DEBUG_FLM_CACHE_LOCKED_COUNT 0x7fU
2937 #define V_DEBUG_FLM_CACHE_LOCKED_COUNT(x) ((x) << S_DEBUG_FLM_CACHE_LOCKED_COUNT)
2938 #define G_DEBUG_FLM_CACHE_LOCKED_COUNT(x) (((x) >> S_DEBUG_FLM_CACHE_LOCKED_COUNT) & M_DEBUG_FLM_CACHE_LOCKED_COUNT)
2940 #define S_DEBUG_FLM_CACHE_AGENT 20
2941 #define M_DEBUG_FLM_CACHE_AGENT 0x7U
2942 #define V_DEBUG_FLM_CACHE_AGENT(x) ((x) << S_DEBUG_FLM_CACHE_AGENT)
2943 #define G_DEBUG_FLM_CACHE_AGENT(x) (((x) >> S_DEBUG_FLM_CACHE_AGENT) & M_DEBUG_FLM_CACHE_AGENT)
2945 #define S_DEBUG_ST_FLM_CACHE 16
2946 #define M_DEBUG_ST_FLM_CACHE 0xfU
2947 #define V_DEBUG_ST_FLM_CACHE(x) ((x) << S_DEBUG_ST_FLM_CACHE)
2948 #define G_DEBUG_ST_FLM_CACHE(x) (((x) >> S_DEBUG_ST_FLM_CACHE) & M_DEBUG_ST_FLM_CACHE)
2950 #define S_DEBUG_FLM_DBPTR_CIDX_STALL 12
2951 #define V_DEBUG_FLM_DBPTR_CIDX_STALL(x) ((x) << S_DEBUG_FLM_DBPTR_CIDX_STALL)
2952 #define F_DEBUG_FLM_DBPTR_CIDX_STALL V_DEBUG_FLM_DBPTR_CIDX_STALL(1U)
2954 #define S_DEBUG_FLM_DBPTR_QID 0
2955 #define M_DEBUG_FLM_DBPTR_QID 0xfffU
2956 #define V_DEBUG_FLM_DBPTR_QID(x) ((x) << S_DEBUG_FLM_DBPTR_QID)
2957 #define G_DEBUG_FLM_DBPTR_QID(x) (((x) >> S_DEBUG_FLM_DBPTR_QID) & M_DEBUG_FLM_DBPTR_QID)
2959 #define A_SGE_DEBUG_DATA_LOW_INDEX_6 0x12d8
2961 #define S_DEBUG_DBP_THREAD0_QID 0
2962 #define M_DEBUG_DBP_THREAD0_QID 0x1ffffU
2963 #define V_DEBUG_DBP_THREAD0_QID(x) ((x) << S_DEBUG_DBP_THREAD0_QID)
2964 #define G_DEBUG_DBP_THREAD0_QID(x) (((x) >> S_DEBUG_DBP_THREAD0_QID) & M_DEBUG_DBP_THREAD0_QID)
2966 #define A_SGE_DEBUG_DATA_LOW_INDEX_7 0x12dc
2968 #define S_DEBUG_DBP_THREAD1_QID 0
2969 #define M_DEBUG_DBP_THREAD1_QID 0x1ffffU
2970 #define V_DEBUG_DBP_THREAD1_QID(x) ((x) << S_DEBUG_DBP_THREAD1_QID)
2971 #define G_DEBUG_DBP_THREAD1_QID(x) (((x) >> S_DEBUG_DBP_THREAD1_QID) & M_DEBUG_DBP_THREAD1_QID)
2973 #define A_SGE_DEBUG_DATA_LOW_INDEX_8 0x12e0
2975 #define S_DEBUG_DBP_THREAD2_QID 0
2976 #define M_DEBUG_DBP_THREAD2_QID 0x1ffffU
2977 #define V_DEBUG_DBP_THREAD2_QID(x) ((x) << S_DEBUG_DBP_THREAD2_QID)
2978 #define G_DEBUG_DBP_THREAD2_QID(x) (((x) >> S_DEBUG_DBP_THREAD2_QID) & M_DEBUG_DBP_THREAD2_QID)
2980 #define A_SGE_DEBUG_DATA_LOW_INDEX_9 0x12e4
2982 #define S_DEBUG_DBP_THREAD3_QID 0
2983 #define M_DEBUG_DBP_THREAD3_QID 0x1ffffU
2984 #define V_DEBUG_DBP_THREAD3_QID(x) ((x) << S_DEBUG_DBP_THREAD3_QID)
2985 #define G_DEBUG_DBP_THREAD3_QID(x) (((x) >> S_DEBUG_DBP_THREAD3_QID) & M_DEBUG_DBP_THREAD3_QID)
2987 #define A_SGE_DEBUG_DATA_LOW_INDEX_10 0x12e8
2989 #define S_DEBUG_IMSG_CPL 16
2990 #define M_DEBUG_IMSG_CPL 0xffU
2991 #define V_DEBUG_IMSG_CPL(x) ((x) << S_DEBUG_IMSG_CPL)
2992 #define G_DEBUG_IMSG_CPL(x) (((x) >> S_DEBUG_IMSG_CPL) & M_DEBUG_IMSG_CPL)
2994 #define S_DEBUG_IMSG_QID 0
2995 #define M_DEBUG_IMSG_QID 0xffffU
2996 #define V_DEBUG_IMSG_QID(x) ((x) << S_DEBUG_IMSG_QID)
2997 #define G_DEBUG_IMSG_QID(x) (((x) >> S_DEBUG_IMSG_QID) & M_DEBUG_IMSG_QID)
2999 #define A_SGE_DEBUG_DATA_LOW_INDEX_11 0x12ec
3001 #define S_DEBUG_IDMA1_QID 16
3002 #define M_DEBUG_IDMA1_QID 0xffffU
3003 #define V_DEBUG_IDMA1_QID(x) ((x) << S_DEBUG_IDMA1_QID)
3004 #define G_DEBUG_IDMA1_QID(x) (((x) >> S_DEBUG_IDMA1_QID) & M_DEBUG_IDMA1_QID)
3006 #define S_DEBUG_IDMA0_QID 0
3007 #define M_DEBUG_IDMA0_QID 0xffffU
3008 #define V_DEBUG_IDMA0_QID(x) ((x) << S_DEBUG_IDMA0_QID)
3009 #define G_DEBUG_IDMA0_QID(x) (((x) >> S_DEBUG_IDMA0_QID) & M_DEBUG_IDMA0_QID)
3011 #define A_SGE_DEBUG_DATA_LOW_INDEX_12 0x12f0
3013 #define S_DEBUG_IDMA1_FLM_REQ_QID 16
3014 #define M_DEBUG_IDMA1_FLM_REQ_QID 0xffffU
3015 #define V_DEBUG_IDMA1_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA1_FLM_REQ_QID)
3016 #define G_DEBUG_IDMA1_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA1_FLM_REQ_QID) & M_DEBUG_IDMA1_FLM_REQ_QID)
3018 #define S_DEBUG_IDMA0_FLM_REQ_QID 0
3019 #define M_DEBUG_IDMA0_FLM_REQ_QID 0xffffU
3020 #define V_DEBUG_IDMA0_FLM_REQ_QID(x) ((x) << S_DEBUG_IDMA0_FLM_REQ_QID)
3021 #define G_DEBUG_IDMA0_FLM_REQ_QID(x) (((x) >> S_DEBUG_IDMA0_FLM_REQ_QID) & M_DEBUG_IDMA0_FLM_REQ_QID)
3023 #define A_SGE_DEBUG_DATA_LOW_INDEX_13 0x12f4
3024 #define A_SGE_DEBUG_DATA_LOW_INDEX_14 0x12f8
3025 #define A_SGE_DEBUG_DATA_LOW_INDEX_15 0x12fc
3026 #define A_SGE_QUEUE_BASE_MAP_HIGH 0x1300
3028 #define S_EGRESS_LOG2SIZE 27
3029 #define M_EGRESS_LOG2SIZE 0x1fU
3030 #define V_EGRESS_LOG2SIZE(x) ((x) << S_EGRESS_LOG2SIZE)
3031 #define G_EGRESS_LOG2SIZE(x) (((x) >> S_EGRESS_LOG2SIZE) & M_EGRESS_LOG2SIZE)
3033 #define S_EGRESS_BASE 10
3034 #define M_EGRESS_BASE 0x1ffffU
3035 #define V_EGRESS_BASE(x) ((x) << S_EGRESS_BASE)
3036 #define G_EGRESS_BASE(x) (((x) >> S_EGRESS_BASE) & M_EGRESS_BASE)
3038 #define S_INGRESS2_LOG2SIZE 5
3039 #define M_INGRESS2_LOG2SIZE 0x1fU
3040 #define V_INGRESS2_LOG2SIZE(x) ((x) << S_INGRESS2_LOG2SIZE)
3041 #define G_INGRESS2_LOG2SIZE(x) (((x) >> S_INGRESS2_LOG2SIZE) & M_INGRESS2_LOG2SIZE)
3043 #define S_INGRESS1_LOG2SIZE 0
3044 #define M_INGRESS1_LOG2SIZE 0x1fU
3045 #define V_INGRESS1_LOG2SIZE(x) ((x) << S_INGRESS1_LOG2SIZE)
3046 #define G_INGRESS1_LOG2SIZE(x) (((x) >> S_INGRESS1_LOG2SIZE) & M_INGRESS1_LOG2SIZE)
3048 #define S_EGRESS_SIZE 27
3049 #define M_EGRESS_SIZE 0x1fU
3050 #define V_EGRESS_SIZE(x) ((x) << S_EGRESS_SIZE)
3051 #define G_EGRESS_SIZE(x) (((x) >> S_EGRESS_SIZE) & M_EGRESS_SIZE)
3053 #define S_INGRESS2_SIZE 5
3054 #define M_INGRESS2_SIZE 0x1fU
3055 #define V_INGRESS2_SIZE(x) ((x) << S_INGRESS2_SIZE)
3056 #define G_INGRESS2_SIZE(x) (((x) >> S_INGRESS2_SIZE) & M_INGRESS2_SIZE)
3058 #define S_INGRESS1_SIZE 0
3059 #define M_INGRESS1_SIZE 0x1fU
3060 #define V_INGRESS1_SIZE(x) ((x) << S_INGRESS1_SIZE)
3061 #define G_INGRESS1_SIZE(x) (((x) >> S_INGRESS1_SIZE) & M_INGRESS1_SIZE)
3063 #define A_SGE_QUEUE_BASE_MAP_LOW 0x1304
3065 #define S_INGRESS2_BASE 16
3066 #define M_INGRESS2_BASE 0xffffU
3067 #define V_INGRESS2_BASE(x) ((x) << S_INGRESS2_BASE)
3068 #define G_INGRESS2_BASE(x) (((x) >> S_INGRESS2_BASE) & M_INGRESS2_BASE)
3070 #define S_INGRESS1_BASE 0
3071 #define M_INGRESS1_BASE 0xffffU
3072 #define V_INGRESS1_BASE(x) ((x) << S_INGRESS1_BASE)
3073 #define G_INGRESS1_BASE(x) (((x) >> S_INGRESS1_BASE) & M_INGRESS1_BASE)
3075 #define A_SGE_LA_RDPTR_0 0x1800
3076 #define A_SGE_LA_RDDATA_0 0x1804
3077 #define A_SGE_LA_WRPTR_0 0x1808
3078 #define A_SGE_LA_RESERVED_0 0x180c
3079 #define A_SGE_LA_RDPTR_1 0x1810
3080 #define A_SGE_LA_RDDATA_1 0x1814
3081 #define A_SGE_LA_WRPTR_1 0x1818
3082 #define A_SGE_LA_RESERVED_1 0x181c
3083 #define A_SGE_LA_RDPTR_2 0x1820
3084 #define A_SGE_LA_RDDATA_2 0x1824
3085 #define A_SGE_LA_WRPTR_2 0x1828
3086 #define A_SGE_LA_RESERVED_2 0x182c
3087 #define A_SGE_LA_RDPTR_3 0x1830
3088 #define A_SGE_LA_RDDATA_3 0x1834
3089 #define A_SGE_LA_WRPTR_3 0x1838
3090 #define A_SGE_LA_RESERVED_3 0x183c
3091 #define A_SGE_LA_RDPTR_4 0x1840
3092 #define A_SGE_LA_RDDATA_4 0x1844
3093 #define A_SGE_LA_WRPTR_4 0x1848
3094 #define A_SGE_LA_RESERVED_4 0x184c
3095 #define A_SGE_LA_RDPTR_5 0x1850
3096 #define A_SGE_LA_RDDATA_5 0x1854
3097 #define A_SGE_LA_WRPTR_5 0x1858
3098 #define A_SGE_LA_RESERVED_5 0x185c
3099 #define A_SGE_LA_RDPTR_6 0x1860
3100 #define A_SGE_LA_RDDATA_6 0x1864
3101 #define A_SGE_LA_WRPTR_6 0x1868
3102 #define A_SGE_LA_RESERVED_6 0x186c
3103 #define A_SGE_LA_RDPTR_7 0x1870
3104 #define A_SGE_LA_RDDATA_7 0x1874
3105 #define A_SGE_LA_WRPTR_7 0x1878
3106 #define A_SGE_LA_RESERVED_7 0x187c
3107 #define A_SGE_LA_RDPTR_8 0x1880
3108 #define A_SGE_LA_RDDATA_8 0x1884
3109 #define A_SGE_LA_WRPTR_8 0x1888
3110 #define A_SGE_LA_RESERVED_8 0x188c
3111 #define A_SGE_LA_RDPTR_9 0x1890
3112 #define A_SGE_LA_RDDATA_9 0x1894
3113 #define A_SGE_LA_WRPTR_9 0x1898
3114 #define A_SGE_LA_RESERVED_9 0x189c
3115 #define A_SGE_LA_RDPTR_10 0x18a0
3116 #define A_SGE_LA_RDDATA_10 0x18a4
3117 #define A_SGE_LA_WRPTR_10 0x18a8
3118 #define A_SGE_LA_RESERVED_10 0x18ac
3119 #define A_SGE_LA_RDPTR_11 0x18b0
3120 #define A_SGE_LA_RDDATA_11 0x18b4
3121 #define A_SGE_LA_WRPTR_11 0x18b8
3122 #define A_SGE_LA_RESERVED_11 0x18bc
3123 #define A_SGE_LA_RDPTR_12 0x18c0
3124 #define A_SGE_LA_RDDATA_12 0x18c4
3125 #define A_SGE_LA_WRPTR_12 0x18c8
3126 #define A_SGE_LA_RESERVED_12 0x18cc
3127 #define A_SGE_LA_RDPTR_13 0x18d0
3128 #define A_SGE_LA_RDDATA_13 0x18d4
3129 #define A_SGE_LA_WRPTR_13 0x18d8
3130 #define A_SGE_LA_RESERVED_13 0x18dc
3131 #define A_SGE_LA_RDPTR_14 0x18e0
3132 #define A_SGE_LA_RDDATA_14 0x18e4
3133 #define A_SGE_LA_WRPTR_14 0x18e8
3134 #define A_SGE_LA_RESERVED_14 0x18ec
3135 #define A_SGE_LA_RDPTR_15 0x18f0
3136 #define A_SGE_LA_RDDATA_15 0x18f4
3137 #define A_SGE_LA_WRPTR_15 0x18f8
3138 #define A_SGE_LA_RESERVED_15 0x18fc
3140 /* registers for module PCIE */
3141 #define PCIE_BASE_ADDR 0x3000
3143 #define A_PCIE_PF_CFG 0x40
3145 #define S_INTXSTAT 16
3146 #define V_INTXSTAT(x) ((x) << S_INTXSTAT)
3147 #define F_INTXSTAT V_INTXSTAT(1U)
3149 #define S_AUXPWRPMEN 15
3150 #define V_AUXPWRPMEN(x) ((x) << S_AUXPWRPMEN)
3151 #define F_AUXPWRPMEN V_AUXPWRPMEN(1U)
3153 #define S_NOSOFTRESET 14
3154 #define V_NOSOFTRESET(x) ((x) << S_NOSOFTRESET)
3155 #define F_NOSOFTRESET V_NOSOFTRESET(1U)
3158 #define M_AIVEC 0x3ffU
3159 #define V_AIVEC(x) ((x) << S_AIVEC)
3160 #define G_AIVEC(x) (((x) >> S_AIVEC) & M_AIVEC)
3162 #define S_INTXTYPE 2
3163 #define M_INTXTYPE 0x3U
3164 #define V_INTXTYPE(x) ((x) << S_INTXTYPE)
3165 #define G_INTXTYPE(x) (((x) >> S_INTXTYPE) & M_INTXTYPE)
3168 #define V_D3HOTEN(x) ((x) << S_D3HOTEN)
3169 #define F_D3HOTEN V_D3HOTEN(1U)
3171 #define S_CLIDECEN 0
3172 #define V_CLIDECEN(x) ((x) << S_CLIDECEN)
3173 #define F_CLIDECEN V_CLIDECEN(1U)
3175 #define A_PCIE_PF_CLI 0x44
3176 #define A_PCIE_PF_GEN_MSG 0x48
3179 #define M_MSGTYPE 0xffU
3180 #define V_MSGTYPE(x) ((x) << S_MSGTYPE)
3181 #define G_MSGTYPE(x) (((x) >> S_MSGTYPE) & M_MSGTYPE)
3183 #define A_PCIE_PF_EXPROM_OFST 0x4c
3186 #define M_OFFSET 0x3fffU
3187 #define V_OFFSET(x) ((x) << S_OFFSET)
3188 #define G_OFFSET(x) (((x) >> S_OFFSET) & M_OFFSET)
3190 #define A_PCIE_INT_ENABLE 0x3000
3192 #define S_NONFATALERR 30
3193 #define V_NONFATALERR(x) ((x) << S_NONFATALERR)
3194 #define F_NONFATALERR V_NONFATALERR(1U)
3196 #define S_UNXSPLCPLERR 29
3197 #define V_UNXSPLCPLERR(x) ((x) << S_UNXSPLCPLERR)
3198 #define F_UNXSPLCPLERR V_UNXSPLCPLERR(1U)
3200 #define S_PCIEPINT 28
3201 #define V_PCIEPINT(x) ((x) << S_PCIEPINT)
3202 #define F_PCIEPINT V_PCIEPINT(1U)
3204 #define S_PCIESINT 27
3205 #define V_PCIESINT(x) ((x) << S_PCIESINT)
3206 #define F_PCIESINT V_PCIESINT(1U)
3208 #define S_RPLPERR 26
3209 #define V_RPLPERR(x) ((x) << S_RPLPERR)
3210 #define F_RPLPERR V_RPLPERR(1U)
3212 #define S_RXWRPERR 25
3213 #define V_RXWRPERR(x) ((x) << S_RXWRPERR)
3214 #define F_RXWRPERR V_RXWRPERR(1U)
3216 #define S_RXCPLPERR 24
3217 #define V_RXCPLPERR(x) ((x) << S_RXCPLPERR)
3218 #define F_RXCPLPERR V_RXCPLPERR(1U)
3220 #define S_PIOTAGPERR 23
3221 #define V_PIOTAGPERR(x) ((x) << S_PIOTAGPERR)
3222 #define F_PIOTAGPERR V_PIOTAGPERR(1U)
3224 #define S_MATAGPERR 22
3225 #define V_MATAGPERR(x) ((x) << S_MATAGPERR)
3226 #define F_MATAGPERR V_MATAGPERR(1U)
3228 #define S_INTXCLRPERR 21
3229 #define V_INTXCLRPERR(x) ((x) << S_INTXCLRPERR)
3230 #define F_INTXCLRPERR V_INTXCLRPERR(1U)
3232 #define S_FIDPERR 20
3233 #define V_FIDPERR(x) ((x) << S_FIDPERR)
3234 #define F_FIDPERR V_FIDPERR(1U)
3236 #define S_CFGSNPPERR 19
3237 #define V_CFGSNPPERR(x) ((x) << S_CFGSNPPERR)
3238 #define F_CFGSNPPERR V_CFGSNPPERR(1U)
3240 #define S_HRSPPERR 18
3241 #define V_HRSPPERR(x) ((x) << S_HRSPPERR)
3242 #define F_HRSPPERR V_HRSPPERR(1U)
3244 #define S_HREQPERR 17
3245 #define V_HREQPERR(x) ((x) << S_HREQPERR)
3246 #define F_HREQPERR V_HREQPERR(1U)
3248 #define S_HCNTPERR 16
3249 #define V_HCNTPERR(x) ((x) << S_HCNTPERR)
3250 #define F_HCNTPERR V_HCNTPERR(1U)
3252 #define S_DRSPPERR 15
3253 #define V_DRSPPERR(x) ((x) << S_DRSPPERR)
3254 #define F_DRSPPERR V_DRSPPERR(1U)
3256 #define S_DREQPERR 14
3257 #define V_DREQPERR(x) ((x) << S_DREQPERR)
3258 #define F_DREQPERR V_DREQPERR(1U)
3260 #define S_DCNTPERR 13
3261 #define V_DCNTPERR(x) ((x) << S_DCNTPERR)
3262 #define F_DCNTPERR V_DCNTPERR(1U)
3264 #define S_CRSPPERR 12
3265 #define V_CRSPPERR(x) ((x) << S_CRSPPERR)
3266 #define F_CRSPPERR V_CRSPPERR(1U)
3268 #define S_CREQPERR 11
3269 #define V_CREQPERR(x) ((x) << S_CREQPERR)
3270 #define F_CREQPERR V_CREQPERR(1U)
3272 #define S_CCNTPERR 10
3273 #define V_CCNTPERR(x) ((x) << S_CCNTPERR)
3274 #define F_CCNTPERR V_CCNTPERR(1U)
3276 #define S_TARTAGPERR 9
3277 #define V_TARTAGPERR(x) ((x) << S_TARTAGPERR)
3278 #define F_TARTAGPERR V_TARTAGPERR(1U)
3280 #define S_PIOREQPERR 8
3281 #define V_PIOREQPERR(x) ((x) << S_PIOREQPERR)
3282 #define F_PIOREQPERR V_PIOREQPERR(1U)
3284 #define S_PIOCPLPERR 7
3285 #define V_PIOCPLPERR(x) ((x) << S_PIOCPLPERR)
3286 #define F_PIOCPLPERR V_PIOCPLPERR(1U)
3288 #define S_MSIXDIPERR 6
3289 #define V_MSIXDIPERR(x) ((x) << S_MSIXDIPERR)
3290 #define F_MSIXDIPERR V_MSIXDIPERR(1U)
3292 #define S_MSIXDATAPERR 5
3293 #define V_MSIXDATAPERR(x) ((x) << S_MSIXDATAPERR)
3294 #define F_MSIXDATAPERR V_MSIXDATAPERR(1U)
3296 #define S_MSIXADDRHPERR 4
3297 #define V_MSIXADDRHPERR(x) ((x) << S_MSIXADDRHPERR)
3298 #define F_MSIXADDRHPERR V_MSIXADDRHPERR(1U)
3300 #define S_MSIXADDRLPERR 3
3301 #define V_MSIXADDRLPERR(x) ((x) << S_MSIXADDRLPERR)
3302 #define F_MSIXADDRLPERR V_MSIXADDRLPERR(1U)
3304 #define S_MSIDATAPERR 2
3305 #define V_MSIDATAPERR(x) ((x) << S_MSIDATAPERR)
3306 #define F_MSIDATAPERR V_MSIDATAPERR(1U)
3308 #define S_MSIADDRHPERR 1
3309 #define V_MSIADDRHPERR(x) ((x) << S_MSIADDRHPERR)
3310 #define F_MSIADDRHPERR V_MSIADDRHPERR(1U)
3312 #define S_MSIADDRLPERR 0
3313 #define V_MSIADDRLPERR(x) ((x) << S_MSIADDRLPERR)
3314 #define F_MSIADDRLPERR V_MSIADDRLPERR(1U)
3316 #define S_IPGRPPERR 31
3317 #define V_IPGRPPERR(x) ((x) << S_IPGRPPERR)
3318 #define F_IPGRPPERR V_IPGRPPERR(1U)
3320 #define S_READRSPERR 29
3321 #define V_READRSPERR(x) ((x) << S_READRSPERR)
3322 #define F_READRSPERR V_READRSPERR(1U)
3324 #define S_TRGT1GRPPERR 28
3325 #define V_TRGT1GRPPERR(x) ((x) << S_TRGT1GRPPERR)
3326 #define F_TRGT1GRPPERR V_TRGT1GRPPERR(1U)
3328 #define S_IPSOTPERR 27
3329 #define V_IPSOTPERR(x) ((x) << S_IPSOTPERR)
3330 #define F_IPSOTPERR V_IPSOTPERR(1U)
3332 #define S_IPRETRYPERR 26
3333 #define V_IPRETRYPERR(x) ((x) << S_IPRETRYPERR)
3334 #define F_IPRETRYPERR V_IPRETRYPERR(1U)
3336 #define S_IPRXDATAGRPPERR 25
3337 #define V_IPRXDATAGRPPERR(x) ((x) << S_IPRXDATAGRPPERR)
3338 #define F_IPRXDATAGRPPERR V_IPRXDATAGRPPERR(1U)
3340 #define S_IPRXHDRGRPPERR 24
3341 #define V_IPRXHDRGRPPERR(x) ((x) << S_IPRXHDRGRPPERR)
3342 #define F_IPRXHDRGRPPERR V_IPRXHDRGRPPERR(1U)
3344 #define S_PIOTAGQPERR 23
3345 #define V_PIOTAGQPERR(x) ((x) << S_PIOTAGQPERR)
3346 #define F_PIOTAGQPERR V_PIOTAGQPERR(1U)
3348 #define S_MAGRPPERR 22
3349 #define V_MAGRPPERR(x) ((x) << S_MAGRPPERR)
3350 #define F_MAGRPPERR V_MAGRPPERR(1U)
3352 #define S_VFIDPERR 21
3353 #define V_VFIDPERR(x) ((x) << S_VFIDPERR)
3354 #define F_VFIDPERR V_VFIDPERR(1U)
3356 #define S_HREQRDPERR 17
3357 #define V_HREQRDPERR(x) ((x) << S_HREQRDPERR)
3358 #define F_HREQRDPERR V_HREQRDPERR(1U)
3360 #define S_HREQWRPERR 16
3361 #define V_HREQWRPERR(x) ((x) << S_HREQWRPERR)
3362 #define F_HREQWRPERR V_HREQWRPERR(1U)
3364 #define S_DREQRDPERR 14
3365 #define V_DREQRDPERR(x) ((x) << S_DREQRDPERR)
3366 #define F_DREQRDPERR V_DREQRDPERR(1U)
3368 #define S_DREQWRPERR 13
3369 #define V_DREQWRPERR(x) ((x) << S_DREQWRPERR)
3370 #define F_DREQWRPERR V_DREQWRPERR(1U)
3372 #define S_CREQRDPERR 11
3373 #define V_CREQRDPERR(x) ((x) << S_CREQRDPERR)
3374 #define F_CREQRDPERR V_CREQRDPERR(1U)
3376 #define S_MSTTAGQPERR 10
3377 #define V_MSTTAGQPERR(x) ((x) << S_MSTTAGQPERR)
3378 #define F_MSTTAGQPERR V_MSTTAGQPERR(1U)
3380 #define S_TGTTAGQPERR 9
3381 #define V_TGTTAGQPERR(x) ((x) << S_TGTTAGQPERR)
3382 #define F_TGTTAGQPERR V_TGTTAGQPERR(1U)
3384 #define S_PIOREQGRPPERR 8
3385 #define V_PIOREQGRPPERR(x) ((x) << S_PIOREQGRPPERR)
3386 #define F_PIOREQGRPPERR V_PIOREQGRPPERR(1U)
3388 #define S_PIOCPLGRPPERR 7
3389 #define V_PIOCPLGRPPERR(x) ((x) << S_PIOCPLGRPPERR)
3390 #define F_PIOCPLGRPPERR V_PIOCPLGRPPERR(1U)
3392 #define S_MSIXSTIPERR 2
3393 #define V_MSIXSTIPERR(x) ((x) << S_MSIXSTIPERR)
3394 #define F_MSIXSTIPERR V_MSIXSTIPERR(1U)
3396 #define S_MSTTIMEOUTPERR 1
3397 #define V_MSTTIMEOUTPERR(x) ((x) << S_MSTTIMEOUTPERR)
3398 #define F_MSTTIMEOUTPERR V_MSTTIMEOUTPERR(1U)
3400 #define S_MSTGRPPERR 0
3401 #define V_MSTGRPPERR(x) ((x) << S_MSTGRPPERR)
3402 #define F_MSTGRPPERR V_MSTGRPPERR(1U)
3404 #define A_PCIE_INT_CAUSE 0x3004
3405 #define A_PCIE_PERR_ENABLE 0x3008
3406 #define A_PCIE_PERR_INJECT 0x300c
3409 #define V_IDE(x) ((x) << S_IDE)
3410 #define F_IDE V_IDE(1U)
3412 #define A_PCIE_NONFAT_ERR 0x3010
3414 #define S_RDRSPERR 9
3415 #define V_RDRSPERR(x) ((x) << S_RDRSPERR)
3416 #define F_RDRSPERR V_RDRSPERR(1U)
3418 #define S_VPDRSPERR 8
3419 #define V_VPDRSPERR(x) ((x) << S_VPDRSPERR)
3420 #define F_VPDRSPERR V_VPDRSPERR(1U)
3423 #define V_POPD(x) ((x) << S_POPD)
3424 #define F_POPD V_POPD(1U)
3427 #define V_POPH(x) ((x) << S_POPH)
3428 #define F_POPH V_POPH(1U)
3431 #define V_POPC(x) ((x) << S_POPC)
3432 #define F_POPC V_POPC(1U)
3435 #define V_MEMREQ(x) ((x) << S_MEMREQ)
3436 #define F_MEMREQ V_MEMREQ(1U)
3439 #define V_PIOREQ(x) ((x) << S_PIOREQ)
3440 #define F_PIOREQ V_PIOREQ(1U)
3443 #define V_TAGDROP(x) ((x) << S_TAGDROP)
3444 #define F_TAGDROP V_TAGDROP(1U)
3447 #define V_TAGCPL(x) ((x) << S_TAGCPL)
3448 #define F_TAGCPL V_TAGCPL(1U)
3451 #define V_CFGSNP(x) ((x) << S_CFGSNP)
3452 #define F_CFGSNP V_CFGSNP(1U)
3454 #define S_MAREQTIMEOUT 29
3455 #define V_MAREQTIMEOUT(x) ((x) << S_MAREQTIMEOUT)
3456 #define F_MAREQTIMEOUT V_MAREQTIMEOUT(1U)
3458 #define S_TRGT1BARTYPEERR 28
3459 #define V_TRGT1BARTYPEERR(x) ((x) << S_TRGT1BARTYPEERR)
3460 #define F_TRGT1BARTYPEERR V_TRGT1BARTYPEERR(1U)
3462 #define S_MAEXTRARSPERR 27
3463 #define V_MAEXTRARSPERR(x) ((x) << S_MAEXTRARSPERR)
3464 #define F_MAEXTRARSPERR V_MAEXTRARSPERR(1U)
3466 #define S_MARSPTIMEOUT 26
3467 #define V_MARSPTIMEOUT(x) ((x) << S_MARSPTIMEOUT)
3468 #define F_MARSPTIMEOUT V_MARSPTIMEOUT(1U)
3470 #define S_INTVFALLMSIDISERR 25
3471 #define V_INTVFALLMSIDISERR(x) ((x) << S_INTVFALLMSIDISERR)
3472 #define F_INTVFALLMSIDISERR V_INTVFALLMSIDISERR(1U)
3474 #define S_INTVFRANGEERR 24
3475 #define V_INTVFRANGEERR(x) ((x) << S_INTVFRANGEERR)
3476 #define F_INTVFRANGEERR V_INTVFRANGEERR(1U)
3478 #define S_INTPLIRSPERR 23
3479 #define V_INTPLIRSPERR(x) ((x) << S_INTPLIRSPERR)
3480 #define F_INTPLIRSPERR V_INTPLIRSPERR(1U)
3482 #define S_MEMREQRDTAGERR 22
3483 #define V_MEMREQRDTAGERR(x) ((x) << S_MEMREQRDTAGERR)
3484 #define F_MEMREQRDTAGERR V_MEMREQRDTAGERR(1U)
3486 #define S_CFGINITDONEERR 21
3487 #define V_CFGINITDONEERR(x) ((x) << S_CFGINITDONEERR)
3488 #define F_CFGINITDONEERR V_CFGINITDONEERR(1U)
3490 #define S_BAR2TIMEOUT 20
3491 #define V_BAR2TIMEOUT(x) ((x) << S_BAR2TIMEOUT)
3492 #define F_BAR2TIMEOUT V_BAR2TIMEOUT(1U)
3494 #define S_VPDTIMEOUT 19
3495 #define V_VPDTIMEOUT(x) ((x) << S_VPDTIMEOUT)
3496 #define F_VPDTIMEOUT V_VPDTIMEOUT(1U)
3498 #define S_MEMRSPRDTAGERR 18
3499 #define V_MEMRSPRDTAGERR(x) ((x) << S_MEMRSPRDTAGERR)
3500 #define F_MEMRSPRDTAGERR V_MEMRSPRDTAGERR(1U)
3502 #define S_MEMRSPWRTAGERR 17
3503 #define V_MEMRSPWRTAGERR(x) ((x) << S_MEMRSPWRTAGERR)
3504 #define F_MEMRSPWRTAGERR V_MEMRSPWRTAGERR(1U)
3506 #define S_PIORSPRDTAGERR 16
3507 #define V_PIORSPRDTAGERR(x) ((x) << S_PIORSPRDTAGERR)
3508 #define F_PIORSPRDTAGERR V_PIORSPRDTAGERR(1U)
3510 #define S_PIORSPWRTAGERR 15
3511 #define V_PIORSPWRTAGERR(x) ((x) << S_PIORSPWRTAGERR)
3512 #define F_PIORSPWRTAGERR V_PIORSPWRTAGERR(1U)
3514 #define S_DBITIMEOUT 14
3515 #define V_DBITIMEOUT(x) ((x) << S_DBITIMEOUT)
3516 #define F_DBITIMEOUT V_DBITIMEOUT(1U)
3518 #define S_PIOUNALINDWR 13
3519 #define V_PIOUNALINDWR(x) ((x) << S_PIOUNALINDWR)
3520 #define F_PIOUNALINDWR V_PIOUNALINDWR(1U)
3522 #define S_BAR2RDERR 12
3523 #define V_BAR2RDERR(x) ((x) << S_BAR2RDERR)
3524 #define F_BAR2RDERR V_BAR2RDERR(1U)
3526 #define S_MAWREOPERR 11
3527 #define V_MAWREOPERR(x) ((x) << S_MAWREOPERR)
3528 #define F_MAWREOPERR V_MAWREOPERR(1U)
3530 #define S_MARDEOPERR 10
3531 #define V_MARDEOPERR(x) ((x) << S_MARDEOPERR)
3532 #define F_MARDEOPERR V_MARDEOPERR(1U)
3535 #define V_BAR2REQ(x) ((x) << S_BAR2REQ)
3536 #define F_BAR2REQ V_BAR2REQ(1U)
3538 #define A_PCIE_CFG 0x3014
3540 #define S_CFGDMAXPYLDSZRX 26
3541 #define M_CFGDMAXPYLDSZRX 0x7U
3542 #define V_CFGDMAXPYLDSZRX(x) ((x) << S_CFGDMAXPYLDSZRX)
3543 #define G_CFGDMAXPYLDSZRX(x) (((x) >> S_CFGDMAXPYLDSZRX) & M_CFGDMAXPYLDSZRX)
3545 #define S_CFGDMAXPYLDSZTX 23
3546 #define M_CFGDMAXPYLDSZTX 0x7U
3547 #define V_CFGDMAXPYLDSZTX(x) ((x) << S_CFGDMAXPYLDSZTX)
3548 #define G_CFGDMAXPYLDSZTX(x) (((x) >> S_CFGDMAXPYLDSZTX) & M_CFGDMAXPYLDSZTX)
3550 #define S_CFGDMAXRDREQSZ 20
3551 #define M_CFGDMAXRDREQSZ 0x7U
3552 #define V_CFGDMAXRDREQSZ(x) ((x) << S_CFGDMAXRDREQSZ)
3553 #define G_CFGDMAXRDREQSZ(x) (((x) >> S_CFGDMAXRDREQSZ) & M_CFGDMAXRDREQSZ)
3555 #define S_MASYNCEN 19
3556 #define V_MASYNCEN(x) ((x) << S_MASYNCEN)
3557 #define F_MASYNCEN V_MASYNCEN(1U)
3559 #define S_DCAENDMA 18
3560 #define V_DCAENDMA(x) ((x) << S_DCAENDMA)
3561 #define F_DCAENDMA V_DCAENDMA(1U)
3563 #define S_DCAENCMD 17
3564 #define V_DCAENCMD(x) ((x) << S_DCAENCMD)
3565 #define F_DCAENCMD V_DCAENCMD(1U)
3567 #define S_VFMSIPNDEN 16
3568 #define V_VFMSIPNDEN(x) ((x) << S_VFMSIPNDEN)
3569 #define F_VFMSIPNDEN V_VFMSIPNDEN(1U)
3571 #define S_FORCETXERROR 15
3572 #define V_FORCETXERROR(x) ((x) << S_FORCETXERROR)
3573 #define F_FORCETXERROR V_FORCETXERROR(1U)
3575 #define S_VPDREQPROTECT 14
3576 #define V_VPDREQPROTECT(x) ((x) << S_VPDREQPROTECT)
3577 #define F_VPDREQPROTECT V_VPDREQPROTECT(1U)
3579 #define S_FIDTABLEINVALID 13
3580 #define V_FIDTABLEINVALID(x) ((x) << S_FIDTABLEINVALID)
3581 #define F_FIDTABLEINVALID V_FIDTABLEINVALID(1U)
3583 #define S_BYPASSMSIXCACHE 12
3584 #define V_BYPASSMSIXCACHE(x) ((x) << S_BYPASSMSIXCACHE)
3585 #define F_BYPASSMSIXCACHE V_BYPASSMSIXCACHE(1U)
3587 #define S_BYPASSMSICACHE 11
3588 #define V_BYPASSMSICACHE(x) ((x) << S_BYPASSMSICACHE)
3589 #define F_BYPASSMSICACHE V_BYPASSMSICACHE(1U)
3591 #define S_SIMSPEED 10
3592 #define V_SIMSPEED(x) ((x) << S_SIMSPEED)
3593 #define F_SIMSPEED V_SIMSPEED(1U)
3595 #define S_TC0_STAMP 9
3596 #define V_TC0_STAMP(x) ((x) << S_TC0_STAMP)
3597 #define F_TC0_STAMP V_TC0_STAMP(1U)
3599 #define S_AI_TCVAL 6
3600 #define M_AI_TCVAL 0x7U
3601 #define V_AI_TCVAL(x) ((x) << S_AI_TCVAL)
3602 #define G_AI_TCVAL(x) (((x) >> S_AI_TCVAL) & M_AI_TCVAL)
3604 #define S_DMASTOPEN 5
3605 #define V_DMASTOPEN(x) ((x) << S_DMASTOPEN)
3606 #define F_DMASTOPEN V_DMASTOPEN(1U)
3608 #define S_DEVSTATERSTMODE 4
3609 #define V_DEVSTATERSTMODE(x) ((x) << S_DEVSTATERSTMODE)
3610 #define F_DEVSTATERSTMODE V_DEVSTATERSTMODE(1U)
3612 #define S_HOTRSTPCIECRSTMODE 3
3613 #define V_HOTRSTPCIECRSTMODE(x) ((x) << S_HOTRSTPCIECRSTMODE)
3614 #define F_HOTRSTPCIECRSTMODE V_HOTRSTPCIECRSTMODE(1U)
3616 #define S_DLDNPCIECRSTMODE 2
3617 #define V_DLDNPCIECRSTMODE(x) ((x) << S_DLDNPCIECRSTMODE)
3618 #define F_DLDNPCIECRSTMODE V_DLDNPCIECRSTMODE(1U)
3620 #define S_DLDNPCIEPRECRSTMODE 1
3621 #define V_DLDNPCIEPRECRSTMODE(x) ((x) << S_DLDNPCIEPRECRSTMODE)
3622 #define F_DLDNPCIEPRECRSTMODE V_DLDNPCIEPRECRSTMODE(1U)
3624 #define S_LINKDNRSTEN 0
3625 #define V_LINKDNRSTEN(x) ((x) << S_LINKDNRSTEN)
3626 #define F_LINKDNRSTEN V_LINKDNRSTEN(1U)
3628 #define S_DIAGCTRLBUS 28
3629 #define M_DIAGCTRLBUS 0x7U
3630 #define V_DIAGCTRLBUS(x) ((x) << S_DIAGCTRLBUS)
3631 #define G_DIAGCTRLBUS(x) (((x) >> S_DIAGCTRLBUS) & M_DIAGCTRLBUS)
3633 #define S_IPPERREN 27
3634 #define V_IPPERREN(x) ((x) << S_IPPERREN)
3635 #define F_IPPERREN V_IPPERREN(1U)
3637 #define S_CFGDEXTTAGEN 26
3638 #define V_CFGDEXTTAGEN(x) ((x) << S_CFGDEXTTAGEN)
3639 #define F_CFGDEXTTAGEN V_CFGDEXTTAGEN(1U)
3641 #define S_CFGDMAXPYLDSZ 23
3642 #define M_CFGDMAXPYLDSZ 0x7U
3643 #define V_CFGDMAXPYLDSZ(x) ((x) << S_CFGDMAXPYLDSZ)
3644 #define G_CFGDMAXPYLDSZ(x) (((x) >> S_CFGDMAXPYLDSZ) & M_CFGDMAXPYLDSZ)
3647 #define V_DCAEN(x) ((x) << S_DCAEN)
3648 #define F_DCAEN V_DCAEN(1U)
3650 #define S_T5CMDREQPRIORITY 16
3651 #define V_T5CMDREQPRIORITY(x) ((x) << S_T5CMDREQPRIORITY)
3652 #define F_T5CMDREQPRIORITY V_T5CMDREQPRIORITY(1U)
3654 #define S_T5VPDREQPROTECT 14
3655 #define M_T5VPDREQPROTECT 0x3U
3656 #define V_T5VPDREQPROTECT(x) ((x) << S_T5VPDREQPROTECT)
3657 #define G_T5VPDREQPROTECT(x) (((x) >> S_T5VPDREQPROTECT) & M_T5VPDREQPROTECT)
3659 #define S_DROPPEDRDRSPDATA 12
3660 #define V_DROPPEDRDRSPDATA(x) ((x) << S_DROPPEDRDRSPDATA)
3661 #define F_DROPPEDRDRSPDATA V_DROPPEDRDRSPDATA(1U)
3663 #define S_AI_INTX_REASSERTEN 11
3664 #define V_AI_INTX_REASSERTEN(x) ((x) << S_AI_INTX_REASSERTEN)
3665 #define F_AI_INTX_REASSERTEN V_AI_INTX_REASSERTEN(1U)
3667 #define S_AUTOTXNDISABLE 10
3668 #define V_AUTOTXNDISABLE(x) ((x) << S_AUTOTXNDISABLE)
3669 #define F_AUTOTXNDISABLE V_AUTOTXNDISABLE(1U)
3671 #define S_LINKREQRSTPCIECRSTMODE 3
3672 #define V_LINKREQRSTPCIECRSTMODE(x) ((x) << S_LINKREQRSTPCIECRSTMODE)
3673 #define F_LINKREQRSTPCIECRSTMODE V_LINKREQRSTPCIECRSTMODE(1U)
3675 #define A_PCIE_DMA_CTRL 0x3018
3677 #define S_LITTLEENDIAN 7
3678 #define V_LITTLEENDIAN(x) ((x) << S_LITTLEENDIAN)
3679 #define F_LITTLEENDIAN V_LITTLEENDIAN(1U)
3681 #define A_PCIE_CFG2 0x3018
3683 #define S_VPDTIMER 16
3684 #define M_VPDTIMER 0xffffU
3685 #define V_VPDTIMER(x) ((x) << S_VPDTIMER)
3686 #define G_VPDTIMER(x) (((x) >> S_VPDTIMER) & M_VPDTIMER)
3688 #define S_BAR2TIMER 4
3689 #define M_BAR2TIMER 0xfffU
3690 #define V_BAR2TIMER(x) ((x) << S_BAR2TIMER)
3691 #define G_BAR2TIMER(x) (((x) >> S_BAR2TIMER) & M_BAR2TIMER)
3693 #define S_MSTREQRDRRASIMPLE 3
3694 #define V_MSTREQRDRRASIMPLE(x) ((x) << S_MSTREQRDRRASIMPLE)
3695 #define F_MSTREQRDRRASIMPLE V_MSTREQRDRRASIMPLE(1U)
3697 #define S_TOTMAXTAG 0
3698 #define M_TOTMAXTAG 0x3U
3699 #define V_TOTMAXTAG(x) ((x) << S_TOTMAXTAG)
3700 #define G_TOTMAXTAG(x) (((x) >> S_TOTMAXTAG) & M_TOTMAXTAG)
3702 #define A_PCIE_DMA_CFG 0x301c
3704 #define S_MAXPYLDSIZE 28
3705 #define M_MAXPYLDSIZE 0x7U
3706 #define V_MAXPYLDSIZE(x) ((x) << S_MAXPYLDSIZE)
3707 #define G_MAXPYLDSIZE(x) (((x) >> S_MAXPYLDSIZE) & M_MAXPYLDSIZE)
3709 #define S_MAXRDREQSIZE 25
3710 #define M_MAXRDREQSIZE 0x7U
3711 #define V_MAXRDREQSIZE(x) ((x) << S_MAXRDREQSIZE)
3712 #define G_MAXRDREQSIZE(x) (((x) >> S_MAXRDREQSIZE) & M_MAXRDREQSIZE)
3714 #define S_DMA_MAXRSPCNT 16
3715 #define M_DMA_MAXRSPCNT 0x1ffU
3716 #define V_DMA_MAXRSPCNT(x) ((x) << S_DMA_MAXRSPCNT)
3717 #define G_DMA_MAXRSPCNT(x) (((x) >> S_DMA_MAXRSPCNT) & M_DMA_MAXRSPCNT)
3719 #define S_DMA_MAXREQCNT 8
3720 #define M_DMA_MAXREQCNT 0xffU
3721 #define V_DMA_MAXREQCNT(x) ((x) << S_DMA_MAXREQCNT)
3722 #define G_DMA_MAXREQCNT(x) (((x) >> S_DMA_MAXREQCNT) & M_DMA_MAXREQCNT)
3725 #define M_MAXTAG 0x7fU
3726 #define V_MAXTAG(x) ((x) << S_MAXTAG)
3727 #define G_MAXTAG(x) (((x) >> S_MAXTAG) & M_MAXTAG)
3729 #define A_PCIE_CFG3 0x301c
3731 #define S_AUTOPIOCOOKIEMATCH 6
3732 #define V_AUTOPIOCOOKIEMATCH(x) ((x) << S_AUTOPIOCOOKIEMATCH)
3733 #define F_AUTOPIOCOOKIEMATCH V_AUTOPIOCOOKIEMATCH(1U)
3735 #define S_FLRPNDCPLMODE 4
3736 #define M_FLRPNDCPLMODE 0x3U
3737 #define V_FLRPNDCPLMODE(x) ((x) << S_FLRPNDCPLMODE)
3738 #define G_FLRPNDCPLMODE(x) (((x) >> S_FLRPNDCPLMODE) & M_FLRPNDCPLMODE)
3740 #define S_HMADCASTFIRSTONLY 2
3741 #define V_HMADCASTFIRSTONLY(x) ((x) << S_HMADCASTFIRSTONLY)
3742 #define F_HMADCASTFIRSTONLY V_HMADCASTFIRSTONLY(1U)
3744 #define S_CMDDCASTFIRSTONLY 1
3745 #define V_CMDDCASTFIRSTONLY(x) ((x) << S_CMDDCASTFIRSTONLY)
3746 #define F_CMDDCASTFIRSTONLY V_CMDDCASTFIRSTONLY(1U)
3748 #define S_DMADCASTFIRSTONLY 0
3749 #define V_DMADCASTFIRSTONLY(x) ((x) << S_DMADCASTFIRSTONLY)
3750 #define F_DMADCASTFIRSTONLY V_DMADCASTFIRSTONLY(1U)
3752 #define A_PCIE_DMA_STAT 0x3020
3754 #define S_STATEREQ 28
3755 #define M_STATEREQ 0xfU
3756 #define V_STATEREQ(x) ((x) << S_STATEREQ)
3757 #define G_STATEREQ(x) (((x) >> S_STATEREQ) & M_STATEREQ)
3759 #define S_DMA_RSPCNT 16
3760 #define M_DMA_RSPCNT 0xfffU
3761 #define V_DMA_RSPCNT(x) ((x) << S_DMA_RSPCNT)
3762 #define G_DMA_RSPCNT(x) (((x) >> S_DMA_RSPCNT) & M_DMA_RSPCNT)
3764 #define S_STATEAREQ 13
3765 #define M_STATEAREQ 0x7U
3766 #define V_STATEAREQ(x) ((x) << S_STATEAREQ)
3767 #define G_STATEAREQ(x) (((x) >> S_STATEAREQ) & M_STATEAREQ)
3769 #define S_TAGFREE 12
3770 #define V_TAGFREE(x) ((x) << S_TAGFREE)
3771 #define F_TAGFREE V_TAGFREE(1U)
3773 #define S_DMA_REQCNT 0
3774 #define M_DMA_REQCNT 0x7ffU
3775 #define V_DMA_REQCNT(x) ((x) << S_DMA_REQCNT)
3776 #define G_DMA_REQCNT(x) (((x) >> S_DMA_REQCNT) & M_DMA_REQCNT)
3778 #define A_PCIE_CFG4 0x3020
3780 #define S_L1CLKREMOVALEN 17
3781 #define V_L1CLKREMOVALEN(x) ((x) << S_L1CLKREMOVALEN)
3782 #define F_L1CLKREMOVALEN V_L1CLKREMOVALEN(1U)
3784 #define S_READYENTERL23 16
3785 #define V_READYENTERL23(x) ((x) << S_READYENTERL23)
3786 #define F_READYENTERL23 V_READYENTERL23(1U)
3789 #define V_EXITL1(x) ((x) << S_EXITL1)
3790 #define F_EXITL1 V_EXITL1(1U)
3793 #define V_ENTERL1(x) ((x) << S_ENTERL1)
3794 #define F_ENTERL1 V_ENTERL1(1U)
3797 #define M_GENPME 0xffU
3798 #define V_GENPME(x) ((x) << S_GENPME)
3799 #define G_GENPME(x) (((x) >> S_GENPME) & M_GENPME)
3801 #define A_PCIE_CFG5 0x3024
3803 #define S_ENABLESKPPARITYFIX 2
3804 #define V_ENABLESKPPARITYFIX(x) ((x) << S_ENABLESKPPARITYFIX)
3805 #define F_ENABLESKPPARITYFIX V_ENABLESKPPARITYFIX(1U)
3807 #define S_ENABLEL2ENTRYINL1 1
3808 #define V_ENABLEL2ENTRYINL1(x) ((x) << S_ENABLEL2ENTRYINL1)
3809 #define F_ENABLEL2ENTRYINL1 V_ENABLEL2ENTRYINL1(1U)
3811 #define S_HOLDCPLENTERINGL1 0
3812 #define V_HOLDCPLENTERINGL1(x) ((x) << S_HOLDCPLENTERINGL1)
3813 #define F_HOLDCPLENTERINGL1 V_HOLDCPLENTERINGL1(1U)
3815 #define A_PCIE_CFG6 0x3028
3817 #define S_PERSTTIMERCOUNT 12
3818 #define M_PERSTTIMERCOUNT 0x3fffU
3819 #define V_PERSTTIMERCOUNT(x) ((x) << S_PERSTTIMERCOUNT)
3820 #define G_PERSTTIMERCOUNT(x) (((x) >> S_PERSTTIMERCOUNT) & M_PERSTTIMERCOUNT)
3822 #define S_PERSTTIMEOUT 8
3823 #define V_PERSTTIMEOUT(x) ((x) << S_PERSTTIMEOUT)
3824 #define F_PERSTTIMEOUT V_PERSTTIMEOUT(1U)
3826 #define S_PERSTTIMER 0
3827 #define M_PERSTTIMER 0xfU
3828 #define V_PERSTTIMER(x) ((x) << S_PERSTTIMER)
3829 #define G_PERSTTIMER(x) (((x) >> S_PERSTTIMER) & M_PERSTTIMER)
3831 #define A_PCIE_CMD_CTRL 0x303c
3832 #define A_PCIE_CMD_CFG 0x3040
3834 #define S_MAXRSPCNT 16
3835 #define M_MAXRSPCNT 0xfU
3836 #define V_MAXRSPCNT(x) ((x) << S_MAXRSPCNT)
3837 #define G_MAXRSPCNT(x) (((x) >> S_MAXRSPCNT) & M_MAXRSPCNT)
3839 #define S_MAXREQCNT 8
3840 #define M_MAXREQCNT 0x1fU
3841 #define V_MAXREQCNT(x) ((x) << S_MAXREQCNT)
3842 #define G_MAXREQCNT(x) (((x) >> S_MAXREQCNT) & M_MAXREQCNT)
3844 #define A_PCIE_CMD_STAT 0x3044
3847 #define M_RSPCNT 0x7fU
3848 #define V_RSPCNT(x) ((x) << S_RSPCNT)
3849 #define G_RSPCNT(x) (((x) >> S_RSPCNT) & M_RSPCNT)
3852 #define M_REQCNT 0xffU
3853 #define V_REQCNT(x) ((x) << S_REQCNT)
3854 #define G_REQCNT(x) (((x) >> S_REQCNT) & M_REQCNT)
3856 #define A_PCIE_HMA_CTRL 0x3050
3858 #define S_IPLTSSM 12
3859 #define M_IPLTSSM 0xfU
3860 #define V_IPLTSSM(x) ((x) << S_IPLTSSM)
3861 #define G_IPLTSSM(x) (((x) >> S_IPLTSSM) & M_IPLTSSM)
3863 #define S_IPCONFIGDOWN 8
3864 #define M_IPCONFIGDOWN 0x7U
3865 #define V_IPCONFIGDOWN(x) ((x) << S_IPCONFIGDOWN)
3866 #define G_IPCONFIGDOWN(x) (((x) >> S_IPCONFIGDOWN) & M_IPCONFIGDOWN)
3868 #define A_PCIE_HMA_CFG 0x3054
3870 #define S_HMA_MAXRSPCNT 16
3871 #define M_HMA_MAXRSPCNT 0x1fU
3872 #define V_HMA_MAXRSPCNT(x) ((x) << S_HMA_MAXRSPCNT)
3873 #define G_HMA_MAXRSPCNT(x) (((x) >> S_HMA_MAXRSPCNT) & M_HMA_MAXRSPCNT)
3875 #define A_PCIE_HMA_STAT 0x3058
3877 #define S_HMA_RSPCNT 16
3878 #define M_HMA_RSPCNT 0xffU
3879 #define V_HMA_RSPCNT(x) ((x) << S_HMA_RSPCNT)
3880 #define G_HMA_RSPCNT(x) (((x) >> S_HMA_RSPCNT) & M_HMA_RSPCNT)
3882 #define A_PCIE_PIO_FIFO_CFG 0x305c
3884 #define S_CPLCONFIG 16
3885 #define M_CPLCONFIG 0xffffU
3886 #define V_CPLCONFIG(x) ((x) << S_CPLCONFIG)
3887 #define G_CPLCONFIG(x) (((x) >> S_CPLCONFIG) & M_CPLCONFIG)
3889 #define S_PIOSTOPEN 12
3890 #define V_PIOSTOPEN(x) ((x) << S_PIOSTOPEN)
3891 #define F_PIOSTOPEN V_PIOSTOPEN(1U)
3893 #define S_IPLANESWAP 11
3894 #define V_IPLANESWAP(x) ((x) << S_IPLANESWAP)
3895 #define F_IPLANESWAP V_IPLANESWAP(1U)
3897 #define S_FORCESTRICTTS1 10
3898 #define V_FORCESTRICTTS1(x) ((x) << S_FORCESTRICTTS1)
3899 #define F_FORCESTRICTTS1 V_FORCESTRICTTS1(1U)
3901 #define S_FORCEPROGRESSCNT 0
3902 #define M_FORCEPROGRESSCNT 0x3ffU
3903 #define V_FORCEPROGRESSCNT(x) ((x) << S_FORCEPROGRESSCNT)
3904 #define G_FORCEPROGRESSCNT(x) (((x) >> S_FORCEPROGRESSCNT) & M_FORCEPROGRESSCNT)
3906 #define A_PCIE_CFG_SPACE_REQ 0x3060
3909 #define V_ENABLE(x) ((x) << S_ENABLE)
3910 #define F_ENABLE V_ENABLE(1U)
3913 #define V_AI(x) ((x) << S_AI)
3914 #define F_AI V_AI(1U)
3916 #define S_LOCALCFG 28
3917 #define V_LOCALCFG(x) ((x) << S_LOCALCFG)
3918 #define F_LOCALCFG V_LOCALCFG(1U)
3922 #define V_BUS(x) ((x) << S_BUS)
3923 #define G_BUS(x) (((x) >> S_BUS) & M_BUS)
3926 #define M_DEVICE 0x1fU
3927 #define V_DEVICE(x) ((x) << S_DEVICE)
3928 #define G_DEVICE(x) (((x) >> S_DEVICE) & M_DEVICE)
3930 #define S_FUNCTION 12
3931 #define M_FUNCTION 0x7U
3932 #define V_FUNCTION(x) ((x) << S_FUNCTION)
3933 #define G_FUNCTION(x) (((x) >> S_FUNCTION) & M_FUNCTION)
3935 #define S_EXTREGISTER 8
3936 #define M_EXTREGISTER 0xfU
3937 #define V_EXTREGISTER(x) ((x) << S_EXTREGISTER)
3938 #define G_EXTREGISTER(x) (((x) >> S_EXTREGISTER) & M_EXTREGISTER)
3940 #define S_REGISTER 0
3941 #define M_REGISTER 0xffU
3942 #define V_REGISTER(x) ((x) << S_REGISTER)
3943 #define G_REGISTER(x) (((x) >> S_REGISTER) & M_REGISTER)
3946 #define V_CS2(x) ((x) << S_CS2)
3947 #define F_CS2 V_CS2(1U)
3951 #define V_WRBE(x) ((x) << S_WRBE)
3952 #define G_WRBE(x) (((x) >> S_WRBE) & M_WRBE)
3954 #define S_CFG_SPACE_VFVLD 23
3955 #define V_CFG_SPACE_VFVLD(x) ((x) << S_CFG_SPACE_VFVLD)
3956 #define F_CFG_SPACE_VFVLD V_CFG_SPACE_VFVLD(1U)
3958 #define S_CFG_SPACE_RVF 16
3959 #define M_CFG_SPACE_RVF 0x7fU
3960 #define V_CFG_SPACE_RVF(x) ((x) << S_CFG_SPACE_RVF)
3961 #define G_CFG_SPACE_RVF(x) (((x) >> S_CFG_SPACE_RVF) & M_CFG_SPACE_RVF)
3963 #define S_CFG_SPACE_PF 12
3964 #define M_CFG_SPACE_PF 0x7U
3965 #define V_CFG_SPACE_PF(x) ((x) << S_CFG_SPACE_PF)
3966 #define G_CFG_SPACE_PF(x) (((x) >> S_CFG_SPACE_PF) & M_CFG_SPACE_PF)
3968 #define A_PCIE_CFG_SPACE_DATA 0x3064
3969 #define A_PCIE_MEM_ACCESS_BASE_WIN 0x3068
3971 #define S_PCIEOFST 10
3972 #define M_PCIEOFST 0x3fffffU
3973 #define V_PCIEOFST(x) ((x) << S_PCIEOFST)
3974 #define G_PCIEOFST(x) (((x) >> S_PCIEOFST) & M_PCIEOFST)
3978 #define V_BIR(x) ((x) << S_BIR)
3979 #define G_BIR(x) (((x) >> S_BIR) & M_BIR)
3982 #define M_WINDOW 0xffU
3983 #define V_WINDOW(x) ((x) << S_WINDOW)
3984 #define G_WINDOW(x) (((x) >> S_WINDOW) & M_WINDOW)
3986 #define A_PCIE_MEM_ACCESS_OFFSET 0x306c
3989 #define M_MEMOFST 0x1ffffffU
3990 #define V_MEMOFST(x) ((x) << S_MEMOFST)
3991 #define G_MEMOFST(x) (((x) >> S_MEMOFST) & M_MEMOFST)
3993 #define A_PCIE_MAILBOX_BASE_WIN 0x30a8
3995 #define S_MBOXPCIEOFST 6
3996 #define M_MBOXPCIEOFST 0x3ffffffU
3997 #define V_MBOXPCIEOFST(x) ((x) << S_MBOXPCIEOFST)
3998 #define G_MBOXPCIEOFST(x) (((x) >> S_MBOXPCIEOFST) & M_MBOXPCIEOFST)
4001 #define M_MBOXBIR 0x3U
4002 #define V_MBOXBIR(x) ((x) << S_MBOXBIR)
4003 #define G_MBOXBIR(x) (((x) >> S_MBOXBIR) & M_MBOXBIR)
4006 #define M_MBOXWIN 0x3U
4007 #define V_MBOXWIN(x) ((x) << S_MBOXWIN)
4008 #define G_MBOXWIN(x) (((x) >> S_MBOXWIN) & M_MBOXWIN)
4010 #define A_PCIE_MAILBOX_OFFSET 0x30ac
4011 #define A_PCIE_MA_CTRL 0x30b0
4013 #define S_MA_TAGFREE 29
4014 #define V_MA_TAGFREE(x) ((x) << S_MA_TAGFREE)
4015 #define F_MA_TAGFREE V_MA_TAGFREE(1U)
4017 #define S_MA_MAXRSPCNT 24
4018 #define M_MA_MAXRSPCNT 0x1fU
4019 #define V_MA_MAXRSPCNT(x) ((x) << S_MA_MAXRSPCNT)
4020 #define G_MA_MAXRSPCNT(x) (((x) >> S_MA_MAXRSPCNT) & M_MA_MAXRSPCNT)
4022 #define S_MA_MAXREQCNT 16
4023 #define M_MA_MAXREQCNT 0x1fU
4024 #define V_MA_MAXREQCNT(x) ((x) << S_MA_MAXREQCNT)
4025 #define G_MA_MAXREQCNT(x) (((x) >> S_MA_MAXREQCNT) & M_MA_MAXREQCNT)
4028 #define V_MA_LE(x) ((x) << S_MA_LE)
4029 #define F_MA_LE V_MA_LE(1U)
4031 #define S_MA_MAXPYLDSIZE 12
4032 #define M_MA_MAXPYLDSIZE 0x7U
4033 #define V_MA_MAXPYLDSIZE(x) ((x) << S_MA_MAXPYLDSIZE)
4034 #define G_MA_MAXPYLDSIZE(x) (((x) >> S_MA_MAXPYLDSIZE) & M_MA_MAXPYLDSIZE)
4036 #define S_MA_MAXRDREQSIZE 8
4037 #define M_MA_MAXRDREQSIZE 0x7U
4038 #define V_MA_MAXRDREQSIZE(x) ((x) << S_MA_MAXRDREQSIZE)
4039 #define G_MA_MAXRDREQSIZE(x) (((x) >> S_MA_MAXRDREQSIZE) & M_MA_MAXRDREQSIZE)
4041 #define S_MA_MAXTAG 0
4042 #define M_MA_MAXTAG 0x1fU
4043 #define V_MA_MAXTAG(x) ((x) << S_MA_MAXTAG)
4044 #define G_MA_MAXTAG(x) (((x) >> S_MA_MAXTAG) & M_MA_MAXTAG)
4046 #define S_T5_MA_MAXREQCNT 16
4047 #define M_T5_MA_MAXREQCNT 0x7fU
4048 #define V_T5_MA_MAXREQCNT(x) ((x) << S_T5_MA_MAXREQCNT)
4049 #define G_T5_MA_MAXREQCNT(x) (((x) >> S_T5_MA_MAXREQCNT) & M_T5_MA_MAXREQCNT)
4051 #define S_MA_MAXREQSIZE 8
4052 #define M_MA_MAXREQSIZE 0x7U
4053 #define V_MA_MAXREQSIZE(x) ((x) << S_MA_MAXREQSIZE)
4054 #define G_MA_MAXREQSIZE(x) (((x) >> S_MA_MAXREQSIZE) & M_MA_MAXREQSIZE)
4056 #define A_PCIE_MA_SYNC 0x30b4
4057 #define A_PCIE_FW 0x30b8
4058 #define A_PCIE_FW_PF 0x30bc
4059 #define A_PCIE_PIO_PAUSE 0x30dc
4061 #define S_PIOPAUSEDONE 31
4062 #define V_PIOPAUSEDONE(x) ((x) << S_PIOPAUSEDONE)
4063 #define F_PIOPAUSEDONE V_PIOPAUSEDONE(1U)
4065 #define S_PIOPAUSETIME 4
4066 #define M_PIOPAUSETIME 0xffffffU
4067 #define V_PIOPAUSETIME(x) ((x) << S_PIOPAUSETIME)
4068 #define G_PIOPAUSETIME(x) (((x) >> S_PIOPAUSETIME) & M_PIOPAUSETIME)
4070 #define S_PIOPAUSE 0
4071 #define V_PIOPAUSE(x) ((x) << S_PIOPAUSE)
4072 #define F_PIOPAUSE V_PIOPAUSE(1U)
4074 #define S_MSTPAUSEDONE 30
4075 #define V_MSTPAUSEDONE(x) ((x) << S_MSTPAUSEDONE)
4076 #define F_MSTPAUSEDONE V_MSTPAUSEDONE(1U)
4078 #define S_MSTPAUSE 1
4079 #define V_MSTPAUSE(x) ((x) << S_MSTPAUSE)
4080 #define F_MSTPAUSE V_MSTPAUSE(1U)
4082 #define A_PCIE_SYS_CFG_READY 0x30e0
4083 #define A_PCIE_MA_STAT 0x30e0
4084 #define A_PCIE_STATIC_CFG1 0x30e4
4086 #define S_LINKDOWN_RESET_EN 26
4087 #define V_LINKDOWN_RESET_EN(x) ((x) << S_LINKDOWN_RESET_EN)
4088 #define F_LINKDOWN_RESET_EN V_LINKDOWN_RESET_EN(1U)
4090 #define S_IN_WR_DISCONTIG 25
4091 #define V_IN_WR_DISCONTIG(x) ((x) << S_IN_WR_DISCONTIG)
4092 #define F_IN_WR_DISCONTIG V_IN_WR_DISCONTIG(1U)
4094 #define S_IN_RD_CPLSIZE 22
4095 #define M_IN_RD_CPLSIZE 0x7U
4096 #define V_IN_RD_CPLSIZE(x) ((x) << S_IN_RD_CPLSIZE)
4097 #define G_IN_RD_CPLSIZE(x) (((x) >> S_IN_RD_CPLSIZE) & M_IN_RD_CPLSIZE)
4099 #define S_IN_RD_BUFMODE 20
4100 #define M_IN_RD_BUFMODE 0x3U
4101 #define V_IN_RD_BUFMODE(x) ((x) << S_IN_RD_BUFMODE)
4102 #define G_IN_RD_BUFMODE(x) (((x) >> S_IN_RD_BUFMODE) & M_IN_RD_BUFMODE)
4104 #define S_GBIF_NPTRANS_TOT 18
4105 #define M_GBIF_NPTRANS_TOT 0x3U
4106 #define V_GBIF_NPTRANS_TOT(x) ((x) << S_GBIF_NPTRANS_TOT)
4107 #define G_GBIF_NPTRANS_TOT(x) (((x) >> S_GBIF_NPTRANS_TOT) & M_GBIF_NPTRANS_TOT)
4109 #define S_IN_PDAT_TOT 15
4110 #define M_IN_PDAT_TOT 0x7U
4111 #define V_IN_PDAT_TOT(x) ((x) << S_IN_PDAT_TOT)
4112 #define G_IN_PDAT_TOT(x) (((x) >> S_IN_PDAT_TOT) & M_IN_PDAT_TOT)
4114 #define S_PCIE_NPTRANS_TOT 12
4115 #define M_PCIE_NPTRANS_TOT 0x7U
4116 #define V_PCIE_NPTRANS_TOT(x) ((x) << S_PCIE_NPTRANS_TOT)
4117 #define G_PCIE_NPTRANS_TOT(x) (((x) >> S_PCIE_NPTRANS_TOT) & M_PCIE_NPTRANS_TOT)
4119 #define S_OUT_PDAT_TOT 9
4120 #define M_OUT_PDAT_TOT 0x7U
4121 #define V_OUT_PDAT_TOT(x) ((x) << S_OUT_PDAT_TOT)
4122 #define G_OUT_PDAT_TOT(x) (((x) >> S_OUT_PDAT_TOT) & M_OUT_PDAT_TOT)
4124 #define S_GBIF_MAX_WRSIZE 6
4125 #define M_GBIF_MAX_WRSIZE 0x7U
4126 #define V_GBIF_MAX_WRSIZE(x) ((x) << S_GBIF_MAX_WRSIZE)
4127 #define G_GBIF_MAX_WRSIZE(x) (((x) >> S_GBIF_MAX_WRSIZE) & M_GBIF_MAX_WRSIZE)
4129 #define S_GBIF_MAX_RDSIZE 3
4130 #define M_GBIF_MAX_RDSIZE 0x7U
4131 #define V_GBIF_MAX_RDSIZE(x) ((x) << S_GBIF_MAX_RDSIZE)
4132 #define G_GBIF_MAX_RDSIZE(x) (((x) >> S_GBIF_MAX_RDSIZE) & M_GBIF_MAX_RDSIZE)
4134 #define S_PCIE_MAX_RDSIZE 0
4135 #define M_PCIE_MAX_RDSIZE 0x7U
4136 #define V_PCIE_MAX_RDSIZE(x) ((x) << S_PCIE_MAX_RDSIZE)
4137 #define G_PCIE_MAX_RDSIZE(x) (((x) >> S_PCIE_MAX_RDSIZE) & M_PCIE_MAX_RDSIZE)
4139 #define S_AUXPOWER_DETECTED 27
4140 #define V_AUXPOWER_DETECTED(x) ((x) << S_AUXPOWER_DETECTED)
4141 #define F_AUXPOWER_DETECTED V_AUXPOWER_DETECTED(1U)
4143 #define A_PCIE_STATIC_CFG2 0x30e8
4145 #define S_PL_CONTROL 16
4146 #define M_PL_CONTROL 0xffffU
4147 #define V_PL_CONTROL(x) ((x) << S_PL_CONTROL)
4148 #define G_PL_CONTROL(x) (((x) >> S_PL_CONTROL) & M_PL_CONTROL)
4150 #define S_STATIC_SPARE3 0
4151 #define M_STATIC_SPARE3 0x3fffU
4152 #define V_STATIC_SPARE3(x) ((x) << S_STATIC_SPARE3)
4153 #define G_STATIC_SPARE3(x) (((x) >> S_STATIC_SPARE3) & M_STATIC_SPARE3)
4155 #define A_PCIE_DBG_INDIR_REQ 0x30ec
4157 #define S_DBGENABLE 31
4158 #define V_DBGENABLE(x) ((x) << S_DBGENABLE)
4159 #define F_DBGENABLE V_DBGENABLE(1U)
4161 #define S_DBGAUTOINC 30
4162 #define V_DBGAUTOINC(x) ((x) << S_DBGAUTOINC)
4163 #define F_DBGAUTOINC V_DBGAUTOINC(1U)
4166 #define M_POINTER 0xffffU
4167 #define V_POINTER(x) ((x) << S_POINTER)
4168 #define G_POINTER(x) (((x) >> S_POINTER) & M_POINTER)
4171 #define M_SELECT 0xfU
4172 #define V_SELECT(x) ((x) << S_SELECT)
4173 #define G_SELECT(x) (((x) >> S_SELECT) & M_SELECT)
4175 #define A_PCIE_DBG_INDIR_DATA_0 0x30f0
4176 #define A_PCIE_DBG_INDIR_DATA_1 0x30f4
4177 #define A_PCIE_DBG_INDIR_DATA_2 0x30f8
4178 #define A_PCIE_DBG_INDIR_DATA_3 0x30fc
4179 #define A_PCIE_FUNC_INT_CFG 0x3100
4181 #define S_PBAOFST 28
4182 #define M_PBAOFST 0xfU
4183 #define V_PBAOFST(x) ((x) << S_PBAOFST)
4184 #define G_PBAOFST(x) (((x) >> S_PBAOFST) & M_PBAOFST)
4186 #define S_TABOFST 24
4187 #define M_TABOFST 0xfU
4188 #define V_TABOFST(x) ((x) << S_TABOFST)
4189 #define G_TABOFST(x) (((x) >> S_TABOFST) & M_TABOFST)
4192 #define M_VECNUM 0x3ffU
4193 #define V_VECNUM(x) ((x) << S_VECNUM)
4194 #define G_VECNUM(x) (((x) >> S_VECNUM) & M_VECNUM)
4197 #define M_VECBASE 0x7ffU
4198 #define V_VECBASE(x) ((x) << S_VECBASE)
4199 #define G_VECBASE(x) (((x) >> S_VECBASE) & M_VECBASE)
4201 #define A_PCIE_FUNC_CTL_STAT 0x3104
4203 #define S_SENDFLRRSP 31
4204 #define V_SENDFLRRSP(x) ((x) << S_SENDFLRRSP)
4205 #define F_SENDFLRRSP V_SENDFLRRSP(1U)
4207 #define S_IMMFLRRSP 24
4208 #define V_IMMFLRRSP(x) ((x) << S_IMMFLRRSP)
4209 #define F_IMMFLRRSP V_IMMFLRRSP(1U)
4211 #define S_TXNDISABLE 20
4212 #define V_TXNDISABLE(x) ((x) << S_TXNDISABLE)
4213 #define F_TXNDISABLE V_TXNDISABLE(1U)
4216 #define M_PNDTXNS 0x3ffU
4217 #define V_PNDTXNS(x) ((x) << S_PNDTXNS)
4218 #define G_PNDTXNS(x) (((x) >> S_PNDTXNS) & M_PNDTXNS)
4221 #define V_VFVLD(x) ((x) << S_VFVLD)
4222 #define F_VFVLD V_VFVLD(1U)
4225 #define M_PFNUM 0x7U
4226 #define V_PFNUM(x) ((x) << S_PFNUM)
4227 #define G_PFNUM(x) (((x) >> S_PFNUM) & M_PFNUM)
4229 #define A_PCIE_PF_INT_CFG 0x3140
4230 #define A_PCIE_PF_INT_CFG2 0x3144
4231 #define A_PCIE_VF_INT_CFG 0x3180
4232 #define A_PCIE_VF_INT_CFG2 0x3184
4233 #define A_PCIE_PF_MSI_EN 0x35a8
4235 #define S_PFMSIEN_7_0 0
4236 #define M_PFMSIEN_7_0 0xffU
4237 #define V_PFMSIEN_7_0(x) ((x) << S_PFMSIEN_7_0)
4238 #define G_PFMSIEN_7_0(x) (((x) >> S_PFMSIEN_7_0) & M_PFMSIEN_7_0)
4240 #define A_PCIE_VF_MSI_EN_0 0x35ac
4241 #define A_PCIE_VF_MSI_EN_1 0x35b0
4242 #define A_PCIE_VF_MSI_EN_2 0x35b4
4243 #define A_PCIE_VF_MSI_EN_3 0x35b8
4244 #define A_PCIE_PF_MSIX_EN 0x35bc
4246 #define S_PFMSIXEN_7_0 0
4247 #define M_PFMSIXEN_7_0 0xffU
4248 #define V_PFMSIXEN_7_0(x) ((x) << S_PFMSIXEN_7_0)
4249 #define G_PFMSIXEN_7_0(x) (((x) >> S_PFMSIXEN_7_0) & M_PFMSIXEN_7_0)
4251 #define A_PCIE_VF_MSIX_EN_0 0x35c0
4252 #define A_PCIE_VF_MSIX_EN_1 0x35c4
4253 #define A_PCIE_VF_MSIX_EN_2 0x35c8
4254 #define A_PCIE_VF_MSIX_EN_3 0x35cc
4255 #define A_PCIE_FID_VFID_SEL 0x35ec
4257 #define S_FID_VFID_SEL_SELECT 0
4258 #define M_FID_VFID_SEL_SELECT 0x3U
4259 #define V_FID_VFID_SEL_SELECT(x) ((x) << S_FID_VFID_SEL_SELECT)
4260 #define G_FID_VFID_SEL_SELECT(x) (((x) >> S_FID_VFID_SEL_SELECT) & M_FID_VFID_SEL_SELECT)
4262 #define A_PCIE_FID_VFID 0x3600
4264 #define S_FID_VFID_SELECT 30
4265 #define M_FID_VFID_SELECT 0x3U
4266 #define V_FID_VFID_SELECT(x) ((x) << S_FID_VFID_SELECT)
4267 #define G_FID_VFID_SELECT(x) (((x) >> S_FID_VFID_SELECT) & M_FID_VFID_SELECT)
4270 #define V_IDO(x) ((x) << S_IDO)
4271 #define F_IDO V_IDO(1U)
4273 #define S_FID_VFID_VFID 16
4274 #define M_FID_VFID_VFID 0xffU
4275 #define V_FID_VFID_VFID(x) ((x) << S_FID_VFID_VFID)
4276 #define G_FID_VFID_VFID(x) (((x) >> S_FID_VFID_VFID) & M_FID_VFID_VFID)
4278 #define S_FID_VFID_TC 11
4279 #define M_FID_VFID_TC 0x7U
4280 #define V_FID_VFID_TC(x) ((x) << S_FID_VFID_TC)
4281 #define G_FID_VFID_TC(x) (((x) >> S_FID_VFID_TC) & M_FID_VFID_TC)
4283 #define S_FID_VFID_VFVLD 10
4284 #define V_FID_VFID_VFVLD(x) ((x) << S_FID_VFID_VFVLD)
4285 #define F_FID_VFID_VFVLD V_FID_VFID_VFVLD(1U)
4287 #define S_FID_VFID_PF 7
4288 #define M_FID_VFID_PF 0x7U
4289 #define V_FID_VFID_PF(x) ((x) << S_FID_VFID_PF)
4290 #define G_FID_VFID_PF(x) (((x) >> S_FID_VFID_PF) & M_FID_VFID_PF)
4292 #define S_FID_VFID_RVF 0
4293 #define M_FID_VFID_RVF 0x7fU
4294 #define V_FID_VFID_RVF(x) ((x) << S_FID_VFID_RVF)
4295 #define G_FID_VFID_RVF(x) (((x) >> S_FID_VFID_RVF) & M_FID_VFID_RVF)
4297 #define A_PCIE_FID 0x3900
4300 #define V_PAD(x) ((x) << S_PAD)
4301 #define F_PAD V_PAD(1U)
4305 #define V_TC(x) ((x) << S_TC)
4306 #define G_TC(x) (((x) >> S_TC) & M_TC)
4309 #define M_FUNC 0xffU
4310 #define V_FUNC(x) ((x) << S_FUNC)
4311 #define G_FUNC(x) (((x) >> S_FUNC) & M_FUNC)
4313 #define A_PCIE_COOKIE_STAT 0x5600
4315 #define S_COOKIEB 16
4316 #define M_COOKIEB 0x3ffU
4317 #define V_COOKIEB(x) ((x) << S_COOKIEB)
4318 #define G_COOKIEB(x) (((x) >> S_COOKIEB) & M_COOKIEB)
4321 #define M_COOKIEA 0x3ffU
4322 #define V_COOKIEA(x) ((x) << S_COOKIEA)
4323 #define G_COOKIEA(x) (((x) >> S_COOKIEA) & M_COOKIEA)
4325 #define A_PCIE_FLR_PIO 0x5620
4327 #define S_RCVDBAR2COOKIE 24
4328 #define M_RCVDBAR2COOKIE 0xffU
4329 #define V_RCVDBAR2COOKIE(x) ((x) << S_RCVDBAR2COOKIE)
4330 #define G_RCVDBAR2COOKIE(x) (((x) >> S_RCVDBAR2COOKIE) & M_RCVDBAR2COOKIE)
4332 #define S_RCVDMARSPCOOKIE 16
4333 #define M_RCVDMARSPCOOKIE 0xffU
4334 #define V_RCVDMARSPCOOKIE(x) ((x) << S_RCVDMARSPCOOKIE)
4335 #define G_RCVDMARSPCOOKIE(x) (((x) >> S_RCVDMARSPCOOKIE) & M_RCVDMARSPCOOKIE)
4337 #define S_RCVDPIORSPCOOKIE 8
4338 #define M_RCVDPIORSPCOOKIE 0xffU
4339 #define V_RCVDPIORSPCOOKIE(x) ((x) << S_RCVDPIORSPCOOKIE)
4340 #define G_RCVDPIORSPCOOKIE(x) (((x) >> S_RCVDPIORSPCOOKIE) & M_RCVDPIORSPCOOKIE)
4342 #define S_EXPDCOOKIE 0
4343 #define M_EXPDCOOKIE 0xffU
4344 #define V_EXPDCOOKIE(x) ((x) << S_EXPDCOOKIE)
4345 #define G_EXPDCOOKIE(x) (((x) >> S_EXPDCOOKIE) & M_EXPDCOOKIE)
4347 #define A_PCIE_FLR_PIO2 0x5624
4349 #define S_RCVDMAREQCOOKIE 16
4350 #define M_RCVDMAREQCOOKIE 0xffU
4351 #define V_RCVDMAREQCOOKIE(x) ((x) << S_RCVDMAREQCOOKIE)
4352 #define G_RCVDMAREQCOOKIE(x) (((x) >> S_RCVDMAREQCOOKIE) & M_RCVDMAREQCOOKIE)
4354 #define S_RCVDPIOREQCOOKIE 8
4355 #define M_RCVDPIOREQCOOKIE 0xffU
4356 #define V_RCVDPIOREQCOOKIE(x) ((x) << S_RCVDPIOREQCOOKIE)
4357 #define G_RCVDPIOREQCOOKIE(x) (((x) >> S_RCVDPIOREQCOOKIE) & M_RCVDPIOREQCOOKIE)
4359 #define A_PCIE_VC0_CDTS0 0x56cc
4362 #define M_CPLD0 0xfffU
4363 #define V_CPLD0(x) ((x) << S_CPLD0)
4364 #define G_CPLD0(x) (((x) >> S_CPLD0) & M_CPLD0)
4368 #define V_PH0(x) ((x) << S_PH0)
4369 #define G_PH0(x) (((x) >> S_PH0) & M_PH0)
4372 #define M_PD0 0xfffU
4373 #define V_PD0(x) ((x) << S_PD0)
4374 #define G_PD0(x) (((x) >> S_PD0) & M_PD0)
4376 #define A_PCIE_VC0_CDTS1 0x56d0
4379 #define M_CPLH0 0xffU
4380 #define V_CPLH0(x) ((x) << S_CPLH0)
4381 #define G_CPLH0(x) (((x) >> S_CPLH0) & M_CPLH0)
4384 #define M_NPH0 0xffU
4385 #define V_NPH0(x) ((x) << S_NPH0)
4386 #define G_NPH0(x) (((x) >> S_NPH0) & M_NPH0)
4389 #define M_NPD0 0xfffU
4390 #define V_NPD0(x) ((x) << S_NPD0)
4391 #define G_NPD0(x) (((x) >> S_NPD0) & M_NPD0)
4393 #define A_PCIE_VC1_CDTS0 0x56d4
4396 #define M_CPLD1 0xfffU
4397 #define V_CPLD1(x) ((x) << S_CPLD1)
4398 #define G_CPLD1(x) (((x) >> S_CPLD1) & M_CPLD1)
4402 #define V_PH1(x) ((x) << S_PH1)
4403 #define G_PH1(x) (((x) >> S_PH1) & M_PH1)
4406 #define M_PD1 0xfffU
4407 #define V_PD1(x) ((x) << S_PD1)
4408 #define G_PD1(x) (((x) >> S_PD1) & M_PD1)
4410 #define A_PCIE_VC1_CDTS1 0x56d8
4413 #define M_CPLH1 0xffU
4414 #define V_CPLH1(x) ((x) << S_CPLH1)
4415 #define G_CPLH1(x) (((x) >> S_CPLH1) & M_CPLH1)
4418 #define M_NPH1 0xffU
4419 #define V_NPH1(x) ((x) << S_NPH1)
4420 #define G_NPH1(x) (((x) >> S_NPH1) & M_NPH1)
4423 #define M_NPD1 0xfffU
4424 #define V_NPD1(x) ((x) << S_NPD1)
4425 #define G_NPD1(x) (((x) >> S_NPD1) & M_NPD1)
4427 #define A_PCIE_FLR_PF_STATUS 0x56dc
4428 #define A_PCIE_FLR_VF0_STATUS 0x56e0
4429 #define A_PCIE_FLR_VF1_STATUS 0x56e4
4430 #define A_PCIE_FLR_VF2_STATUS 0x56e8
4431 #define A_PCIE_FLR_VF3_STATUS 0x56ec
4432 #define A_PCIE_STAT 0x56f4
4434 #define S_PM_STATUS 24
4435 #define M_PM_STATUS 0xffU
4436 #define V_PM_STATUS(x) ((x) << S_PM_STATUS)
4437 #define G_PM_STATUS(x) (((x) >> S_PM_STATUS) & M_PM_STATUS)
4439 #define S_PM_CURRENTSTATE 20
4440 #define M_PM_CURRENTSTATE 0x7U
4441 #define V_PM_CURRENTSTATE(x) ((x) << S_PM_CURRENTSTATE)
4442 #define G_PM_CURRENTSTATE(x) (((x) >> S_PM_CURRENTSTATE) & M_PM_CURRENTSTATE)
4444 #define S_LTSSMENABLE 12
4445 #define V_LTSSMENABLE(x) ((x) << S_LTSSMENABLE)
4446 #define F_LTSSMENABLE V_LTSSMENABLE(1U)
4448 #define S_STATECFGINITF 4
4449 #define M_STATECFGINITF 0x7fU
4450 #define V_STATECFGINITF(x) ((x) << S_STATECFGINITF)
4451 #define G_STATECFGINITF(x) (((x) >> S_STATECFGINITF) & M_STATECFGINITF)
4453 #define S_STATECFGINIT 0
4454 #define M_STATECFGINIT 0xfU
4455 #define V_STATECFGINIT(x) ((x) << S_STATECFGINIT)
4456 #define G_STATECFGINIT(x) (((x) >> S_STATECFGINIT) & M_STATECFGINIT)
4458 #define A_PCIE_CRS 0x56f8
4460 #define S_CRS_ENABLE 0
4461 #define V_CRS_ENABLE(x) ((x) << S_CRS_ENABLE)
4462 #define F_CRS_ENABLE V_CRS_ENABLE(1U)
4464 #define A_PCIE_LTSSM 0x56fc
4466 #define S_LTSSM_ENABLE 0
4467 #define V_LTSSM_ENABLE(x) ((x) << S_LTSSM_ENABLE)
4468 #define F_LTSSM_ENABLE V_LTSSM_ENABLE(1U)
4470 #define A_PCIE_CORE_ACK_LATENCY_TIMER_REPLAY_TIMER 0x5700
4472 #define S_REPLAY_TIME_LIMIT 16
4473 #define M_REPLAY_TIME_LIMIT 0xffffU
4474 #define V_REPLAY_TIME_LIMIT(x) ((x) << S_REPLAY_TIME_LIMIT)
4475 #define G_REPLAY_TIME_LIMIT(x) (((x) >> S_REPLAY_TIME_LIMIT) & M_REPLAY_TIME_LIMIT)
4477 #define S_ACK_LATENCY_TIMER_LIMIT 0
4478 #define M_ACK_LATENCY_TIMER_LIMIT 0xffffU
4479 #define V_ACK_LATENCY_TIMER_LIMIT(x) ((x) << S_ACK_LATENCY_TIMER_LIMIT)
4480 #define G_ACK_LATENCY_TIMER_LIMIT(x) (((x) >> S_ACK_LATENCY_TIMER_LIMIT) & M_ACK_LATENCY_TIMER_LIMIT)
4482 #define A_PCIE_CORE_VENDOR_SPECIFIC_DLLP 0x5704
4483 #define A_PCIE_CORE_PORT_FORCE_LINK 0x5708
4485 #define S_LOW_POWER_ENTRANCE_COUNT 24
4486 #define M_LOW_POWER_ENTRANCE_COUNT 0xffU
4487 #define V_LOW_POWER_ENTRANCE_COUNT(x) ((x) << S_LOW_POWER_ENTRANCE_COUNT)
4488 #define G_LOW_POWER_ENTRANCE_COUNT(x) (((x) >> S_LOW_POWER_ENTRANCE_COUNT) & M_LOW_POWER_ENTRANCE_COUNT)
4490 #define S_LINK_STATE 16
4491 #define M_LINK_STATE 0x3fU
4492 #define V_LINK_STATE(x) ((x) << S_LINK_STATE)
4493 #define G_LINK_STATE(x) (((x) >> S_LINK_STATE) & M_LINK_STATE)
4495 #define S_FORCE_LINK 15
4496 #define V_FORCE_LINK(x) ((x) << S_FORCE_LINK)
4497 #define F_FORCE_LINK V_FORCE_LINK(1U)
4499 #define S_LINK_NUMBER 0
4500 #define M_LINK_NUMBER 0xffU
4501 #define V_LINK_NUMBER(x) ((x) << S_LINK_NUMBER)
4502 #define G_LINK_NUMBER(x) (((x) >> S_LINK_NUMBER) & M_LINK_NUMBER)
4504 #define A_PCIE_CORE_ACK_FREQUENCY_L0L1_ASPM_CONTROL 0x570c
4506 #define S_ENTER_ASPM_L1_WO_L0S 30
4507 #define V_ENTER_ASPM_L1_WO_L0S(x) ((x) << S_ENTER_ASPM_L1_WO_L0S)
4508 #define F_ENTER_ASPM_L1_WO_L0S V_ENTER_ASPM_L1_WO_L0S(1U)
4510 #define S_L1_ENTRANCE_LATENCY 27
4511 #define M_L1_ENTRANCE_LATENCY 0x7U
4512 #define V_L1_ENTRANCE_LATENCY(x) ((x) << S_L1_ENTRANCE_LATENCY)
4513 #define G_L1_ENTRANCE_LATENCY(x) (((x) >> S_L1_ENTRANCE_LATENCY) & M_L1_ENTRANCE_LATENCY)
4515 #define S_L0S_ENTRANCE_LATENCY 24
4516 #define M_L0S_ENTRANCE_LATENCY 0x7U
4517 #define V_L0S_ENTRANCE_LATENCY(x) ((x) << S_L0S_ENTRANCE_LATENCY)
4518 #define G_L0S_ENTRANCE_LATENCY(x) (((x) >> S_L0S_ENTRANCE_LATENCY) & M_L0S_ENTRANCE_LATENCY)
4520 #define S_COMMON_CLOCK_N_FTS 16
4521 #define M_COMMON_CLOCK_N_FTS 0xffU
4522 #define V_COMMON_CLOCK_N_FTS(x) ((x) << S_COMMON_CLOCK_N_FTS)
4523 #define G_COMMON_CLOCK_N_FTS(x) (((x) >> S_COMMON_CLOCK_N_FTS) & M_COMMON_CLOCK_N_FTS)
4526 #define M_N_FTS 0xffU
4527 #define V_N_FTS(x) ((x) << S_N_FTS)
4528 #define G_N_FTS(x) (((x) >> S_N_FTS) & M_N_FTS)
4530 #define S_ACK_FREQUENCY 0
4531 #define M_ACK_FREQUENCY 0xffU
4532 #define V_ACK_FREQUENCY(x) ((x) << S_ACK_FREQUENCY)
4533 #define G_ACK_FREQUENCY(x) (((x) >> S_ACK_FREQUENCY) & M_ACK_FREQUENCY)
4535 #define A_PCIE_CORE_PORT_LINK_CONTROL 0x5710
4537 #define S_CROSSLINK_ACTIVE 23
4538 #define V_CROSSLINK_ACTIVE(x) ((x) << S_CROSSLINK_ACTIVE)
4539 #define F_CROSSLINK_ACTIVE V_CROSSLINK_ACTIVE(1U)
4541 #define S_CROSSLINK_ENABLE 22
4542 #define V_CROSSLINK_ENABLE(x) ((x) << S_CROSSLINK_ENABLE)
4543 #define F_CROSSLINK_ENABLE V_CROSSLINK_ENABLE(1U)
4545 #define S_LINK_MODE_ENABLE 16
4546 #define M_LINK_MODE_ENABLE 0x3fU
4547 #define V_LINK_MODE_ENABLE(x) ((x) << S_LINK_MODE_ENABLE)
4548 #define G_LINK_MODE_ENABLE(x) (((x) >> S_LINK_MODE_ENABLE) & M_LINK_MODE_ENABLE)
4550 #define S_FAST_LINK_MODE 7
4551 #define V_FAST_LINK_MODE(x) ((x) << S_FAST_LINK_MODE)
4552 #define F_FAST_LINK_MODE V_FAST_LINK_MODE(1U)
4554 #define S_DLL_LINK_ENABLE 5
4555 #define V_DLL_LINK_ENABLE(x) ((x) << S_DLL_LINK_ENABLE)
4556 #define F_DLL_LINK_ENABLE V_DLL_LINK_ENABLE(1U)
4558 #define S_RESET_ASSERT 3
4559 #define V_RESET_ASSERT(x) ((x) << S_RESET_ASSERT)
4560 #define F_RESET_ASSERT V_RESET_ASSERT(1U)
4562 #define S_LOOPBACK_ENABLE 2
4563 #define V_LOOPBACK_ENABLE(x) ((x) << S_LOOPBACK_ENABLE)
4564 #define F_LOOPBACK_ENABLE V_LOOPBACK_ENABLE(1U)
4566 #define S_SCRAMBLE_DISABLE 1
4567 #define V_SCRAMBLE_DISABLE(x) ((x) << S_SCRAMBLE_DISABLE)
4568 #define F_SCRAMBLE_DISABLE V_SCRAMBLE_DISABLE(1U)
4570 #define S_VENDOR_SPECIFIC_DLLP_REQUEST 0
4571 #define V_VENDOR_SPECIFIC_DLLP_REQUEST(x) ((x) << S_VENDOR_SPECIFIC_DLLP_REQUEST)
4572 #define F_VENDOR_SPECIFIC_DLLP_REQUEST V_VENDOR_SPECIFIC_DLLP_REQUEST(1U)
4574 #define A_PCIE_CORE_LANE_SKEW 0x5714
4576 #define S_DISABLE_DESKEW 31
4577 #define V_DISABLE_DESKEW(x) ((x) << S_DISABLE_DESKEW)
4578 #define F_DISABLE_DESKEW V_DISABLE_DESKEW(1U)
4580 #define S_ACK_NAK_DISABLE 25
4581 #define V_ACK_NAK_DISABLE(x) ((x) << S_ACK_NAK_DISABLE)
4582 #define F_ACK_NAK_DISABLE V_ACK_NAK_DISABLE(1U)
4584 #define S_FLOW_CONTROL_DISABLE 24
4585 #define V_FLOW_CONTROL_DISABLE(x) ((x) << S_FLOW_CONTROL_DISABLE)
4586 #define F_FLOW_CONTROL_DISABLE V_FLOW_CONTROL_DISABLE(1U)
4588 #define S_INSERT_TXSKEW 0
4589 #define M_INSERT_TXSKEW 0xffffffU
4590 #define V_INSERT_TXSKEW(x) ((x) << S_INSERT_TXSKEW)
4591 #define G_INSERT_TXSKEW(x) (((x) >> S_INSERT_TXSKEW) & M_INSERT_TXSKEW)
4593 #define A_PCIE_CORE_SYMBOL_NUMBER 0x5718
4595 #define S_FLOW_CONTROL_TIMER_MODIFIER 24
4596 #define M_FLOW_CONTROL_TIMER_MODIFIER 0x1fU
4597 #define V_FLOW_CONTROL_TIMER_MODIFIER(x) ((x) << S_FLOW_CONTROL_TIMER_MODIFIER)
4598 #define G_FLOW_CONTROL_TIMER_MODIFIER(x) (((x) >> S_FLOW_CONTROL_TIMER_MODIFIER) & M_FLOW_CONTROL_TIMER_MODIFIER)
4600 #define S_ACK_NAK_TIMER_MODIFIER 19
4601 #define M_ACK_NAK_TIMER_MODIFIER 0x1fU
4602 #define V_ACK_NAK_TIMER_MODIFIER(x) ((x) << S_ACK_NAK_TIMER_MODIFIER)
4603 #define G_ACK_NAK_TIMER_MODIFIER(x) (((x) >> S_ACK_NAK_TIMER_MODIFIER) & M_ACK_NAK_TIMER_MODIFIER)
4605 #define S_REPLAY_TIMER_MODIFIER 14
4606 #define M_REPLAY_TIMER_MODIFIER 0x1fU
4607 #define V_REPLAY_TIMER_MODIFIER(x) ((x) << S_REPLAY_TIMER_MODIFIER)
4608 #define G_REPLAY_TIMER_MODIFIER(x) (((x) >> S_REPLAY_TIMER_MODIFIER) & M_REPLAY_TIMER_MODIFIER)
4611 #define M_MAXFUNC 0x7U
4612 #define V_MAXFUNC(x) ((x) << S_MAXFUNC)
4613 #define G_MAXFUNC(x) (((x) >> S_MAXFUNC) & M_MAXFUNC)
4615 #define A_PCIE_CORE_SYMBOL_TIMER_FILTER_MASK1 0x571c
4617 #define S_MASK_RADM_FILTER 16
4618 #define M_MASK_RADM_FILTER 0xffffU
4619 #define V_MASK_RADM_FILTER(x) ((x) << S_MASK_RADM_FILTER)
4620 #define G_MASK_RADM_FILTER(x) (((x) >> S_MASK_RADM_FILTER) & M_MASK_RADM_FILTER)
4622 #define S_DISABLE_FC_WATCHDOG 15
4623 #define V_DISABLE_FC_WATCHDOG(x) ((x) << S_DISABLE_FC_WATCHDOG)
4624 #define F_DISABLE_FC_WATCHDOG V_DISABLE_FC_WATCHDOG(1U)
4626 #define S_SKP_INTERVAL 0
4627 #define M_SKP_INTERVAL 0x7ffU
4628 #define V_SKP_INTERVAL(x) ((x) << S_SKP_INTERVAL)
4629 #define G_SKP_INTERVAL(x) (((x) >> S_SKP_INTERVAL) & M_SKP_INTERVAL)
4631 #define A_PCIE_CORE_FILTER_MASK2 0x5720
4632 #define A_PCIE_CORE_DEBUG_0 0x5728
4633 #define A_PCIE_CORE_DEBUG_1 0x572c
4634 #define A_PCIE_CORE_TRANSMIT_POSTED_FC_CREDIT_STATUS 0x5730
4636 #define S_TXPH_FC 12
4637 #define M_TXPH_FC 0xffU
4638 #define V_TXPH_FC(x) ((x) << S_TXPH_FC)
4639 #define G_TXPH_FC(x) (((x) >> S_TXPH_FC) & M_TXPH_FC)
4642 #define M_TXPD_FC 0xfffU
4643 #define V_TXPD_FC(x) ((x) << S_TXPD_FC)
4644 #define G_TXPD_FC(x) (((x) >> S_TXPD_FC) & M_TXPD_FC)
4646 #define A_PCIE_CORE_TRANSMIT_NONPOSTED_FC_CREDIT_STATUS 0x5734
4648 #define S_TXNPH_FC 12
4649 #define M_TXNPH_FC 0xffU
4650 #define V_TXNPH_FC(x) ((x) << S_TXNPH_FC)
4651 #define G_TXNPH_FC(x) (((x) >> S_TXNPH_FC) & M_TXNPH_FC)
4653 #define S_TXNPD_FC 0
4654 #define M_TXNPD_FC 0xfffU
4655 #define V_TXNPD_FC(x) ((x) << S_TXNPD_FC)
4656 #define G_TXNPD_FC(x) (((x) >> S_TXNPD_FC) & M_TXNPD_FC)
4658 #define A_PCIE_CORE_TRANSMIT_COMPLETION_FC_CREDIT_STATUS 0x5738
4660 #define S_TXCPLH_FC 12
4661 #define M_TXCPLH_FC 0xffU
4662 #define V_TXCPLH_FC(x) ((x) << S_TXCPLH_FC)
4663 #define G_TXCPLH_FC(x) (((x) >> S_TXCPLH_FC) & M_TXCPLH_FC)
4665 #define S_TXCPLD_FC 0
4666 #define M_TXCPLD_FC 0xfffU
4667 #define V_TXCPLD_FC(x) ((x) << S_TXCPLD_FC)
4668 #define G_TXCPLD_FC(x) (((x) >> S_TXCPLD_FC) & M_TXCPLD_FC)
4670 #define A_PCIE_CORE_QUEUE_STATUS 0x573c
4672 #define S_RXQUEUE_NOT_EMPTY 2
4673 #define V_RXQUEUE_NOT_EMPTY(x) ((x) << S_RXQUEUE_NOT_EMPTY)
4674 #define F_RXQUEUE_NOT_EMPTY V_RXQUEUE_NOT_EMPTY(1U)
4676 #define S_TXRETRYBUF_NOT_EMPTY 1
4677 #define V_TXRETRYBUF_NOT_EMPTY(x) ((x) << S_TXRETRYBUF_NOT_EMPTY)
4678 #define F_TXRETRYBUF_NOT_EMPTY V_TXRETRYBUF_NOT_EMPTY(1U)
4680 #define S_RXTLP_FC_NOT_RETURNED 0
4681 #define V_RXTLP_FC_NOT_RETURNED(x) ((x) << S_RXTLP_FC_NOT_RETURNED)
4682 #define F_RXTLP_FC_NOT_RETURNED V_RXTLP_FC_NOT_RETURNED(1U)
4684 #define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_1 0x5740
4686 #define S_VC3_WRR 24
4687 #define M_VC3_WRR 0xffU
4688 #define V_VC3_WRR(x) ((x) << S_VC3_WRR)
4689 #define G_VC3_WRR(x) (((x) >> S_VC3_WRR) & M_VC3_WRR)
4691 #define S_VC2_WRR 16
4692 #define M_VC2_WRR 0xffU
4693 #define V_VC2_WRR(x) ((x) << S_VC2_WRR)
4694 #define G_VC2_WRR(x) (((x) >> S_VC2_WRR) & M_VC2_WRR)
4697 #define M_VC1_WRR 0xffU
4698 #define V_VC1_WRR(x) ((x) << S_VC1_WRR)
4699 #define G_VC1_WRR(x) (((x) >> S_VC1_WRR) & M_VC1_WRR)
4702 #define M_VC0_WRR 0xffU
4703 #define V_VC0_WRR(x) ((x) << S_VC0_WRR)
4704 #define G_VC0_WRR(x) (((x) >> S_VC0_WRR) & M_VC0_WRR)
4706 #define A_PCIE_CORE_VC_TRANSMIT_ARBITRATION_2 0x5744
4708 #define S_VC7_WRR 24
4709 #define M_VC7_WRR 0xffU
4710 #define V_VC7_WRR(x) ((x) << S_VC7_WRR)
4711 #define G_VC7_WRR(x) (((x) >> S_VC7_WRR) & M_VC7_WRR)
4713 #define S_VC6_WRR 16
4714 #define M_VC6_WRR 0xffU
4715 #define V_VC6_WRR(x) ((x) << S_VC6_WRR)
4716 #define G_VC6_WRR(x) (((x) >> S_VC6_WRR) & M_VC6_WRR)
4719 #define M_VC5_WRR 0xffU
4720 #define V_VC5_WRR(x) ((x) << S_VC5_WRR)
4721 #define G_VC5_WRR(x) (((x) >> S_VC5_WRR) & M_VC5_WRR)
4724 #define M_VC4_WRR 0xffU
4725 #define V_VC4_WRR(x) ((x) << S_VC4_WRR)
4726 #define G_VC4_WRR(x) (((x) >> S_VC4_WRR) & M_VC4_WRR)
4728 #define A_PCIE_CORE_VC0_POSTED_RECEIVE_QUEUE_CONTROL 0x5748
4730 #define S_VC0_RX_ORDERING 31
4731 #define V_VC0_RX_ORDERING(x) ((x) << S_VC0_RX_ORDERING)
4732 #define F_VC0_RX_ORDERING V_VC0_RX_ORDERING(1U)
4734 #define S_VC0_TLP_ORDERING 30
4735 #define V_VC0_TLP_ORDERING(x) ((x) << S_VC0_TLP_ORDERING)
4736 #define F_VC0_TLP_ORDERING V_VC0_TLP_ORDERING(1U)
4738 #define S_VC0_PTLP_QUEUE_MODE 21
4739 #define M_VC0_PTLP_QUEUE_MODE 0x7U
4740 #define V_VC0_PTLP_QUEUE_MODE(x) ((x) << S_VC0_PTLP_QUEUE_MODE)
4741 #define G_VC0_PTLP_QUEUE_MODE(x) (((x) >> S_VC0_PTLP_QUEUE_MODE) & M_VC0_PTLP_QUEUE_MODE)
4743 #define S_VC0_PH_CREDITS 12
4744 #define M_VC0_PH_CREDITS 0xffU
4745 #define V_VC0_PH_CREDITS(x) ((x) << S_VC0_PH_CREDITS)
4746 #define G_VC0_PH_CREDITS(x) (((x) >> S_VC0_PH_CREDITS) & M_VC0_PH_CREDITS)
4748 #define S_VC0_PD_CREDITS 0
4749 #define M_VC0_PD_CREDITS 0xfffU
4750 #define V_VC0_PD_CREDITS(x) ((x) << S_VC0_PD_CREDITS)
4751 #define G_VC0_PD_CREDITS(x) (((x) >> S_VC0_PD_CREDITS) & M_VC0_PD_CREDITS)
4753 #define A_PCIE_CORE_VC0_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x574c
4755 #define S_VC0_NPTLP_QUEUE_MODE 21
4756 #define M_VC0_NPTLP_QUEUE_MODE 0x7U
4757 #define V_VC0_NPTLP_QUEUE_MODE(x) ((x) << S_VC0_NPTLP_QUEUE_MODE)
4758 #define G_VC0_NPTLP_QUEUE_MODE(x) (((x) >> S_VC0_NPTLP_QUEUE_MODE) & M_VC0_NPTLP_QUEUE_MODE)
4760 #define S_VC0_NPH_CREDITS 12
4761 #define M_VC0_NPH_CREDITS 0xffU
4762 #define V_VC0_NPH_CREDITS(x) ((x) << S_VC0_NPH_CREDITS)
4763 #define G_VC0_NPH_CREDITS(x) (((x) >> S_VC0_NPH_CREDITS) & M_VC0_NPH_CREDITS)
4765 #define S_VC0_NPD_CREDITS 0
4766 #define M_VC0_NPD_CREDITS 0xfffU
4767 #define V_VC0_NPD_CREDITS(x) ((x) << S_VC0_NPD_CREDITS)
4768 #define G_VC0_NPD_CREDITS(x) (((x) >> S_VC0_NPD_CREDITS) & M_VC0_NPD_CREDITS)
4770 #define A_PCIE_CORE_VC0_COMPLETION_RECEIVE_QUEUE_CONTROL 0x5750
4772 #define S_VC0_CPLTLP_QUEUE_MODE 21
4773 #define M_VC0_CPLTLP_QUEUE_MODE 0x7U
4774 #define V_VC0_CPLTLP_QUEUE_MODE(x) ((x) << S_VC0_CPLTLP_QUEUE_MODE)
4775 #define G_VC0_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC0_CPLTLP_QUEUE_MODE) & M_VC0_CPLTLP_QUEUE_MODE)
4777 #define S_VC0_CPLH_CREDITS 12
4778 #define M_VC0_CPLH_CREDITS 0xffU
4779 #define V_VC0_CPLH_CREDITS(x) ((x) << S_VC0_CPLH_CREDITS)
4780 #define G_VC0_CPLH_CREDITS(x) (((x) >> S_VC0_CPLH_CREDITS) & M_VC0_CPLH_CREDITS)
4782 #define S_VC0_CPLD_CREDITS 0
4783 #define M_VC0_CPLD_CREDITS 0xfffU
4784 #define V_VC0_CPLD_CREDITS(x) ((x) << S_VC0_CPLD_CREDITS)
4785 #define G_VC0_CPLD_CREDITS(x) (((x) >> S_VC0_CPLD_CREDITS) & M_VC0_CPLD_CREDITS)
4787 #define A_PCIE_CORE_VC1_POSTED_RECEIVE_QUEUE_CONTROL 0x5754
4789 #define S_VC1_TLP_ORDERING 30
4790 #define V_VC1_TLP_ORDERING(x) ((x) << S_VC1_TLP_ORDERING)
4791 #define F_VC1_TLP_ORDERING V_VC1_TLP_ORDERING(1U)
4793 #define S_VC1_PTLP_QUEUE_MODE 21
4794 #define M_VC1_PTLP_QUEUE_MODE 0x7U
4795 #define V_VC1_PTLP_QUEUE_MODE(x) ((x) << S_VC1_PTLP_QUEUE_MODE)
4796 #define G_VC1_PTLP_QUEUE_MODE(x) (((x) >> S_VC1_PTLP_QUEUE_MODE) & M_VC1_PTLP_QUEUE_MODE)
4798 #define S_VC1_PH_CREDITS 12
4799 #define M_VC1_PH_CREDITS 0xffU
4800 #define V_VC1_PH_CREDITS(x) ((x) << S_VC1_PH_CREDITS)
4801 #define G_VC1_PH_CREDITS(x) (((x) >> S_VC1_PH_CREDITS) & M_VC1_PH_CREDITS)
4803 #define S_VC1_PD_CREDITS 0
4804 #define M_VC1_PD_CREDITS 0xfffU
4805 #define V_VC1_PD_CREDITS(x) ((x) << S_VC1_PD_CREDITS)
4806 #define G_VC1_PD_CREDITS(x) (((x) >> S_VC1_PD_CREDITS) & M_VC1_PD_CREDITS)
4808 #define A_PCIE_CORE_VC1_NONPOSTED_RECEIVE_QUEUE_CONTROL 0x5758
4810 #define S_VC1_NPTLP_QUEUE_MODE 21
4811 #define M_VC1_NPTLP_QUEUE_MODE 0x7U
4812 #define V_VC1_NPTLP_QUEUE_MODE(x) ((x) << S_VC1_NPTLP_QUEUE_MODE)
4813 #define G_VC1_NPTLP_QUEUE_MODE(x) (((x) >> S_VC1_NPTLP_QUEUE_MODE) & M_VC1_NPTLP_QUEUE_MODE)
4815 #define S_VC1_NPH_CREDITS 12
4816 #define M_VC1_NPH_CREDITS 0xffU
4817 #define V_VC1_NPH_CREDITS(x) ((x) << S_VC1_NPH_CREDITS)
4818 #define G_VC1_NPH_CREDITS(x) (((x) >> S_VC1_NPH_CREDITS) & M_VC1_NPH_CREDITS)
4820 #define S_VC1_NPD_CREDITS 0
4821 #define M_VC1_NPD_CREDITS 0xfffU
4822 #define V_VC1_NPD_CREDITS(x) ((x) << S_VC1_NPD_CREDITS)
4823 #define G_VC1_NPD_CREDITS(x) (((x) >> S_VC1_NPD_CREDITS) & M_VC1_NPD_CREDITS)
4825 #define A_PCIE_CORE_VC1_COMPLETION_RECEIVE_QUEUE_CONTROL 0x575c
4827 #define S_VC1_CPLTLP_QUEUE_MODE 21
4828 #define M_VC1_CPLTLP_QUEUE_MODE 0x7U
4829 #define V_VC1_CPLTLP_QUEUE_MODE(x) ((x) << S_VC1_CPLTLP_QUEUE_MODE)
4830 #define G_VC1_CPLTLP_QUEUE_MODE(x) (((x) >> S_VC1_CPLTLP_QUEUE_MODE) & M_VC1_CPLTLP_QUEUE_MODE)
4832 #define S_VC1_CPLH_CREDITS 12
4833 #define M_VC1_CPLH_CREDITS 0xffU
4834 #define V_VC1_CPLH_CREDITS(x) ((x) << S_VC1_CPLH_CREDITS)
4835 #define G_VC1_CPLH_CREDITS(x) (((x) >> S_VC1_CPLH_CREDITS) & M_VC1_CPLH_CREDITS)
4837 #define S_VC1_CPLD_CREDITS 0
4838 #define M_VC1_CPLD_CREDITS 0xfffU
4839 #define V_VC1_CPLD_CREDITS(x) ((x) << S_VC1_CPLD_CREDITS)
4840 #define G_VC1_CPLD_CREDITS(x) (((x) >> S_VC1_CPLD_CREDITS) & M_VC1_CPLD_CREDITS)
4842 #define A_PCIE_CORE_LINK_WIDTH_SPEED_CHANGE 0x580c
4844 #define S_SEL_DEEMPHASIS 20
4845 #define V_SEL_DEEMPHASIS(x) ((x) << S_SEL_DEEMPHASIS)
4846 #define F_SEL_DEEMPHASIS V_SEL_DEEMPHASIS(1U)
4848 #define S_TXCMPLRCV 19
4849 #define V_TXCMPLRCV(x) ((x) << S_TXCMPLRCV)
4850 #define F_TXCMPLRCV V_TXCMPLRCV(1U)
4852 #define S_PHYTXSWING 18
4853 #define V_PHYTXSWING(x) ((x) << S_PHYTXSWING)
4854 #define F_PHYTXSWING V_PHYTXSWING(1U)
4856 #define S_DIRSPDCHANGE 17
4857 #define V_DIRSPDCHANGE(x) ((x) << S_DIRSPDCHANGE)
4858 #define F_DIRSPDCHANGE V_DIRSPDCHANGE(1U)
4860 #define S_NUM_LANES 8
4861 #define M_NUM_LANES 0x1ffU
4862 #define V_NUM_LANES(x) ((x) << S_NUM_LANES)
4863 #define G_NUM_LANES(x) (((x) >> S_NUM_LANES) & M_NUM_LANES)
4865 #define S_NFTS_GEN2_3 0
4866 #define M_NFTS_GEN2_3 0xffU
4867 #define V_NFTS_GEN2_3(x) ((x) << S_NFTS_GEN2_3)
4868 #define G_NFTS_GEN2_3(x) (((x) >> S_NFTS_GEN2_3) & M_NFTS_GEN2_3)
4870 #define A_PCIE_CORE_PHY_STATUS 0x5810
4871 #define A_PCIE_CORE_PHY_CONTROL 0x5814
4872 #define A_PCIE_CORE_GEN3_CONTROL 0x5890
4874 #define S_DC_BALANCE_DISABLE 18
4875 #define V_DC_BALANCE_DISABLE(x) ((x) << S_DC_BALANCE_DISABLE)
4876 #define F_DC_BALANCE_DISABLE V_DC_BALANCE_DISABLE(1U)
4878 #define S_DLLP_DELAY_DISABLE 17
4879 #define V_DLLP_DELAY_DISABLE(x) ((x) << S_DLLP_DELAY_DISABLE)
4880 #define F_DLLP_DELAY_DISABLE V_DLLP_DELAY_DISABLE(1U)
4882 #define S_EQL_DISABLE 16
4883 #define V_EQL_DISABLE(x) ((x) << S_EQL_DISABLE)
4884 #define F_EQL_DISABLE V_EQL_DISABLE(1U)
4886 #define S_EQL_REDO_DISABLE 11
4887 #define V_EQL_REDO_DISABLE(x) ((x) << S_EQL_REDO_DISABLE)
4888 #define F_EQL_REDO_DISABLE V_EQL_REDO_DISABLE(1U)
4890 #define S_EQL_EIEOS_CNTRST_DISABLE 10
4891 #define V_EQL_EIEOS_CNTRST_DISABLE(x) ((x) << S_EQL_EIEOS_CNTRST_DISABLE)
4892 #define F_EQL_EIEOS_CNTRST_DISABLE V_EQL_EIEOS_CNTRST_DISABLE(1U)
4894 #define S_EQL_PH2_PH3_DISABLE 9
4895 #define V_EQL_PH2_PH3_DISABLE(x) ((x) << S_EQL_PH2_PH3_DISABLE)
4896 #define F_EQL_PH2_PH3_DISABLE V_EQL_PH2_PH3_DISABLE(1U)
4898 #define S_DISABLE_SCRAMBLER 8
4899 #define V_DISABLE_SCRAMBLER(x) ((x) << S_DISABLE_SCRAMBLER)
4900 #define F_DISABLE_SCRAMBLER V_DISABLE_SCRAMBLER(1U)
4902 #define A_PCIE_CORE_GEN3_EQ_FS_LF 0x5894
4904 #define S_FULL_SWING 6
4905 #define M_FULL_SWING 0x3fU
4906 #define V_FULL_SWING(x) ((x) << S_FULL_SWING)
4907 #define G_FULL_SWING(x) (((x) >> S_FULL_SWING) & M_FULL_SWING)
4909 #define S_LOW_FREQUENCY 0
4910 #define M_LOW_FREQUENCY 0x3fU
4911 #define V_LOW_FREQUENCY(x) ((x) << S_LOW_FREQUENCY)
4912 #define G_LOW_FREQUENCY(x) (((x) >> S_LOW_FREQUENCY) & M_LOW_FREQUENCY)
4914 #define A_PCIE_CORE_GEN3_EQ_PRESET_COEFF 0x5898
4916 #define S_POSTCURSOR 12
4917 #define M_POSTCURSOR 0x3fU
4918 #define V_POSTCURSOR(x) ((x) << S_POSTCURSOR)
4919 #define G_POSTCURSOR(x) (((x) >> S_POSTCURSOR) & M_POSTCURSOR)
4922 #define M_CURSOR 0x3fU
4923 #define V_CURSOR(x) ((x) << S_CURSOR)
4924 #define G_CURSOR(x) (((x) >> S_CURSOR) & M_CURSOR)
4926 #define S_PRECURSOR 0
4927 #define M_PRECURSOR 0x3fU
4928 #define V_PRECURSOR(x) ((x) << S_PRECURSOR)
4929 #define G_PRECURSOR(x) (((x) >> S_PRECURSOR) & M_PRECURSOR)
4931 #define A_PCIE_CORE_GEN3_EQ_PRESET_INDEX 0x589c
4934 #define M_INDEX 0xfU
4935 #define V_INDEX(x) ((x) << S_INDEX)
4936 #define G_INDEX(x) (((x) >> S_INDEX) & M_INDEX)
4938 #define A_PCIE_CORE_GEN3_EQ_STATUS 0x58a4
4940 #define S_LEGALITY_STATUS 0
4941 #define V_LEGALITY_STATUS(x) ((x) << S_LEGALITY_STATUS)
4942 #define F_LEGALITY_STATUS V_LEGALITY_STATUS(1U)
4944 #define A_PCIE_CORE_GEN3_EQ_CONTROL 0x58a8
4946 #define S_INCLUDE_INITIAL_FOM 24
4947 #define V_INCLUDE_INITIAL_FOM(x) ((x) << S_INCLUDE_INITIAL_FOM)
4948 #define F_INCLUDE_INITIAL_FOM V_INCLUDE_INITIAL_FOM(1U)
4950 #define S_PRESET_REQUEST_VECTOR 8
4951 #define M_PRESET_REQUEST_VECTOR 0xffffU
4952 #define V_PRESET_REQUEST_VECTOR(x) ((x) << S_PRESET_REQUEST_VECTOR)
4953 #define G_PRESET_REQUEST_VECTOR(x) (((x) >> S_PRESET_REQUEST_VECTOR) & M_PRESET_REQUEST_VECTOR)
4955 #define S_PHASE23_2MS_TIMEOUT_DISABLE 5
4956 #define V_PHASE23_2MS_TIMEOUT_DISABLE(x) ((x) << S_PHASE23_2MS_TIMEOUT_DISABLE)
4957 #define F_PHASE23_2MS_TIMEOUT_DISABLE V_PHASE23_2MS_TIMEOUT_DISABLE(1U)
4959 #define S_AFTER24MS 4
4960 #define V_AFTER24MS(x) ((x) << S_AFTER24MS)
4961 #define F_AFTER24MS V_AFTER24MS(1U)
4963 #define S_FEEDBACK_MODE 0
4964 #define M_FEEDBACK_MODE 0xfU
4965 #define V_FEEDBACK_MODE(x) ((x) << S_FEEDBACK_MODE)
4966 #define G_FEEDBACK_MODE(x) (((x) >> S_FEEDBACK_MODE) & M_FEEDBACK_MODE)
4968 #define A_PCIE_CORE_GEN3_EQ_DIRCHANGE_FEEDBACK 0x58ac
4970 #define S_WINAPERTURE_CPLUS1 14
4971 #define M_WINAPERTURE_CPLUS1 0xfU
4972 #define V_WINAPERTURE_CPLUS1(x) ((x) << S_WINAPERTURE_CPLUS1)
4973 #define G_WINAPERTURE_CPLUS1(x) (((x) >> S_WINAPERTURE_CPLUS1) & M_WINAPERTURE_CPLUS1)
4975 #define S_WINAPERTURE_CMINS1 10
4976 #define M_WINAPERTURE_CMINS1 0xfU
4977 #define V_WINAPERTURE_CMINS1(x) ((x) << S_WINAPERTURE_CMINS1)
4978 #define G_WINAPERTURE_CMINS1(x) (((x) >> S_WINAPERTURE_CMINS1) & M_WINAPERTURE_CMINS1)
4980 #define S_CONVERGENCE_WINDEPTH 5
4981 #define M_CONVERGENCE_WINDEPTH 0x1fU
4982 #define V_CONVERGENCE_WINDEPTH(x) ((x) << S_CONVERGENCE_WINDEPTH)
4983 #define G_CONVERGENCE_WINDEPTH(x) (((x) >> S_CONVERGENCE_WINDEPTH) & M_CONVERGENCE_WINDEPTH)
4985 #define S_EQMASTERPHASE_MINTIME 0
4986 #define M_EQMASTERPHASE_MINTIME 0x1fU
4987 #define V_EQMASTERPHASE_MINTIME(x) ((x) << S_EQMASTERPHASE_MINTIME)
4988 #define G_EQMASTERPHASE_MINTIME(x) (((x) >> S_EQMASTERPHASE_MINTIME) & M_EQMASTERPHASE_MINTIME)
4990 #define A_PCIE_CORE_PIPE_CONTROL 0x58b8
4992 #define S_PIPE_LOOPBACK_EN 0
4993 #define V_PIPE_LOOPBACK_EN(x) ((x) << S_PIPE_LOOPBACK_EN)
4994 #define F_PIPE_LOOPBACK_EN V_PIPE_LOOPBACK_EN(1U)
4996 #define A_PCIE_CORE_DBI_RO_WE 0x58bc
4998 #define S_READONLY_WRITEEN 0
4999 #define V_READONLY_WRITEEN(x) ((x) << S_READONLY_WRITEEN)
5000 #define F_READONLY_WRITEEN V_READONLY_WRITEEN(1U)
5002 #define A_PCIE_CORE_UTL_SYSTEM_BUS_CONTROL 0x5900
5005 #define V_SMTD(x) ((x) << S_SMTD)
5006 #define F_SMTD V_SMTD(1U)
5009 #define V_SSTD(x) ((x) << S_SSTD)
5010 #define F_SSTD V_SSTD(1U)
5013 #define V_SWD0(x) ((x) << S_SWD0)
5014 #define F_SWD0 V_SWD0(1U)
5017 #define V_SWD1(x) ((x) << S_SWD1)
5018 #define F_SWD1 V_SWD1(1U)
5021 #define V_SWD2(x) ((x) << S_SWD2)
5022 #define F_SWD2 V_SWD2(1U)
5025 #define V_SWD3(x) ((x) << S_SWD3)
5026 #define F_SWD3 V_SWD3(1U)
5029 #define V_SWD4(x) ((x) << S_SWD4)
5030 #define F_SWD4 V_SWD4(1U)
5033 #define V_SWD5(x) ((x) << S_SWD5)
5034 #define F_SWD5 V_SWD5(1U)
5037 #define V_SWD6(x) ((x) << S_SWD6)
5038 #define F_SWD6 V_SWD6(1U)
5041 #define V_SWD7(x) ((x) << S_SWD7)
5042 #define F_SWD7 V_SWD7(1U)
5045 #define V_SWD8(x) ((x) << S_SWD8)
5046 #define F_SWD8 V_SWD8(1U)
5049 #define V_SRD0(x) ((x) << S_SRD0)
5050 #define F_SRD0 V_SRD0(1U)
5053 #define V_SRD1(x) ((x) << S_SRD1)
5054 #define F_SRD1 V_SRD1(1U)
5057 #define V_SRD2(x) ((x) << S_SRD2)
5058 #define F_SRD2 V_SRD2(1U)
5061 #define V_SRD3(x) ((x) << S_SRD3)
5062 #define F_SRD3 V_SRD3(1U)
5065 #define V_SRD4(x) ((x) << S_SRD4)
5066 #define F_SRD4 V_SRD4(1U)
5069 #define V_SRD5(x) ((x) << S_SRD5)
5070 #define F_SRD5 V_SRD5(1U)
5073 #define V_SRD6(x) ((x) << S_SRD6)
5074 #define F_SRD6 V_SRD6(1U)
5077 #define V_SRD7(x) ((x) << S_SRD7)
5078 #define F_SRD7 V_SRD7(1U)
5081 #define V_SRD8(x) ((x) << S_SRD8)
5082 #define F_SRD8 V_SRD8(1U)
5085 #define V_CRRE(x) ((x) << S_CRRE)
5086 #define F_CRRE V_CRRE(1U)
5090 #define V_CRMC(x) ((x) << S_CRMC)
5091 #define G_CRMC(x) (((x) >> S_CRMC) & M_CRMC)
5093 #define A_PCIE_CORE_UTL_STATUS 0x5904
5096 #define V_USBP(x) ((x) << S_USBP)
5097 #define F_USBP V_USBP(1U)
5100 #define V_UPEP(x) ((x) << S_UPEP)
5101 #define F_UPEP V_UPEP(1U)
5104 #define V_RCEP(x) ((x) << S_RCEP)
5105 #define F_RCEP V_RCEP(1U)
5108 #define V_EPEP(x) ((x) << S_EPEP)
5109 #define F_EPEP V_EPEP(1U)
5112 #define V_USBS(x) ((x) << S_USBS)
5113 #define F_USBS V_USBS(1U)
5116 #define V_UPES(x) ((x) << S_UPES)
5117 #define F_UPES V_UPES(1U)
5120 #define V_RCES(x) ((x) << S_RCES)
5121 #define F_RCES V_RCES(1U)
5124 #define V_EPES(x) ((x) << S_EPES)
5125 #define F_EPES V_EPES(1U)
5127 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_STATUS 0x5908
5130 #define V_RNPP(x) ((x) << S_RNPP)
5131 #define F_RNPP V_RNPP(1U)
5134 #define V_RPCP(x) ((x) << S_RPCP)
5135 #define F_RPCP V_RPCP(1U)
5138 #define V_RCIP(x) ((x) << S_RCIP)
5139 #define F_RCIP V_RCIP(1U)
5142 #define V_RCCP(x) ((x) << S_RCCP)
5143 #define F_RCCP V_RCCP(1U)
5146 #define V_RFTP(x) ((x) << S_RFTP)
5147 #define F_RFTP V_RFTP(1U)
5150 #define V_PTRP(x) ((x) << S_PTRP)
5151 #define F_PTRP V_PTRP(1U)
5153 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_ERROR_SEVERITY 0x590c
5156 #define V_RNPS(x) ((x) << S_RNPS)
5157 #define F_RNPS V_RNPS(1U)
5160 #define V_RPCS(x) ((x) << S_RPCS)
5161 #define F_RPCS V_RPCS(1U)
5164 #define V_RCIS(x) ((x) << S_RCIS)
5165 #define F_RCIS V_RCIS(1U)
5168 #define V_RCCS(x) ((x) << S_RCCS)
5169 #define F_RCCS V_RCCS(1U)
5172 #define V_RFTS(x) ((x) << S_RFTS)
5173 #define F_RFTS V_RFTS(1U)
5175 #define A_PCIE_CORE_UTL_SYSTEM_BUS_AGENT_INTERRUPT_ENABLE 0x5910
5178 #define V_RNPI(x) ((x) << S_RNPI)
5179 #define F_RNPI V_RNPI(1U)
5182 #define V_RPCI(x) ((x) << S_RPCI)
5183 #define F_RPCI V_RPCI(1U)
5186 #define V_RCII(x) ((x) << S_RCII)
5187 #define F_RCII V_RCII(1U)
5190 #define V_RCCI(x) ((x) << S_RCCI)
5191 #define F_RCCI V_RCCI(1U)
5194 #define V_RFTI(x) ((x) << S_RFTI)
5195 #define F_RFTI V_RFTI(1U)
5197 #define A_PCIE_CORE_SYSTEM_BUS_BURST_SIZE_CONFIGURATION 0x5920
5201 #define V_SBRS(x) ((x) << S_SBRS)
5202 #define G_SBRS(x) (((x) >> S_SBRS) & M_SBRS)
5206 #define V_OTWS(x) ((x) << S_OTWS)
5207 #define G_OTWS(x) (((x) >> S_OTWS) & M_OTWS)
5209 #define A_PCIE_CORE_REVISION_ID 0x5924
5212 #define M_RVID 0xfffU
5213 #define V_RVID(x) ((x) << S_RVID)
5214 #define G_RVID(x) (((x) >> S_RVID) & M_RVID)
5217 #define M_BRVN 0xffU
5218 #define V_BRVN(x) ((x) << S_BRVN)
5219 #define G_BRVN(x) (((x) >> S_BRVN) & M_BRVN)
5221 #define A_PCIE_T5_DMA_CFG 0x5940
5223 #define S_T5_DMA_MAXREQCNT 20
5224 #define M_T5_DMA_MAXREQCNT 0xffU
5225 #define V_T5_DMA_MAXREQCNT(x) ((x) << S_T5_DMA_MAXREQCNT)
5226 #define G_T5_DMA_MAXREQCNT(x) (((x) >> S_T5_DMA_MAXREQCNT) & M_T5_DMA_MAXREQCNT)
5228 #define S_T5_DMA_MAXRDREQSIZE 17
5229 #define M_T5_DMA_MAXRDREQSIZE 0x7U
5230 #define V_T5_DMA_MAXRDREQSIZE(x) ((x) << S_T5_DMA_MAXRDREQSIZE)
5231 #define G_T5_DMA_MAXRDREQSIZE(x) (((x) >> S_T5_DMA_MAXRDREQSIZE) & M_T5_DMA_MAXRDREQSIZE)
5233 #define S_T5_DMA_MAXRSPCNT 8
5234 #define M_T5_DMA_MAXRSPCNT 0x1ffU
5235 #define V_T5_DMA_MAXRSPCNT(x) ((x) << S_T5_DMA_MAXRSPCNT)
5236 #define G_T5_DMA_MAXRSPCNT(x) (((x) >> S_T5_DMA_MAXRSPCNT) & M_T5_DMA_MAXRSPCNT)
5238 #define S_SEQCHKDIS 7
5239 #define V_SEQCHKDIS(x) ((x) << S_SEQCHKDIS)
5240 #define F_SEQCHKDIS V_SEQCHKDIS(1U)
5243 #define M_MINTAG 0x7fU
5244 #define V_MINTAG(x) ((x) << S_MINTAG)
5245 #define G_MINTAG(x) (((x) >> S_MINTAG) & M_MINTAG)
5247 #define A_PCIE_T5_DMA_STAT 0x5944
5249 #define S_DMA_RESPCNT 20
5250 #define M_DMA_RESPCNT 0xfffU
5251 #define V_DMA_RESPCNT(x) ((x) << S_DMA_RESPCNT)
5252 #define G_DMA_RESPCNT(x) (((x) >> S_DMA_RESPCNT) & M_DMA_RESPCNT)
5254 #define S_DMA_RDREQCNT 12
5255 #define M_DMA_RDREQCNT 0xffU
5256 #define V_DMA_RDREQCNT(x) ((x) << S_DMA_RDREQCNT)
5257 #define G_DMA_RDREQCNT(x) (((x) >> S_DMA_RDREQCNT) & M_DMA_RDREQCNT)
5259 #define S_DMA_WRREQCNT 0
5260 #define M_DMA_WRREQCNT 0x7ffU
5261 #define V_DMA_WRREQCNT(x) ((x) << S_DMA_WRREQCNT)
5262 #define G_DMA_WRREQCNT(x) (((x) >> S_DMA_WRREQCNT) & M_DMA_WRREQCNT)
5264 #define A_PCIE_T5_DMA_STAT2 0x5948
5266 #define S_COOKIECNT 24
5267 #define M_COOKIECNT 0xfU
5268 #define V_COOKIECNT(x) ((x) << S_COOKIECNT)
5269 #define G_COOKIECNT(x) (((x) >> S_COOKIECNT) & M_COOKIECNT)
5271 #define S_RDSEQNUMUPDCNT 20
5272 #define M_RDSEQNUMUPDCNT 0xfU
5273 #define V_RDSEQNUMUPDCNT(x) ((x) << S_RDSEQNUMUPDCNT)
5274 #define G_RDSEQNUMUPDCNT(x) (((x) >> S_RDSEQNUMUPDCNT) & M_RDSEQNUMUPDCNT)
5276 #define S_SIREQCNT 16
5277 #define M_SIREQCNT 0xfU
5278 #define V_SIREQCNT(x) ((x) << S_SIREQCNT)
5279 #define G_SIREQCNT(x) (((x) >> S_SIREQCNT) & M_SIREQCNT)
5281 #define S_WREOPMATCHSOP 12
5282 #define V_WREOPMATCHSOP(x) ((x) << S_WREOPMATCHSOP)
5283 #define F_WREOPMATCHSOP V_WREOPMATCHSOP(1U)
5285 #define S_WRSOPCNT 8
5286 #define M_WRSOPCNT 0xfU
5287 #define V_WRSOPCNT(x) ((x) << S_WRSOPCNT)
5288 #define G_WRSOPCNT(x) (((x) >> S_WRSOPCNT) & M_WRSOPCNT)
5290 #define S_RDSOPCNT 0
5291 #define M_RDSOPCNT 0xffU
5292 #define V_RDSOPCNT(x) ((x) << S_RDSOPCNT)
5293 #define G_RDSOPCNT(x) (((x) >> S_RDSOPCNT) & M_RDSOPCNT)
5295 #define A_PCIE_T5_DMA_STAT3 0x594c
5297 #define S_ATMREQSOPCNT 24
5298 #define M_ATMREQSOPCNT 0xffU
5299 #define V_ATMREQSOPCNT(x) ((x) << S_ATMREQSOPCNT)
5300 #define G_ATMREQSOPCNT(x) (((x) >> S_ATMREQSOPCNT) & M_ATMREQSOPCNT)
5302 #define S_ATMEOPMATCHSOP 17
5303 #define V_ATMEOPMATCHSOP(x) ((x) << S_ATMEOPMATCHSOP)
5304 #define F_ATMEOPMATCHSOP V_ATMEOPMATCHSOP(1U)
5306 #define S_RSPEOPMATCHSOP 16
5307 #define V_RSPEOPMATCHSOP(x) ((x) << S_RSPEOPMATCHSOP)
5308 #define F_RSPEOPMATCHSOP V_RSPEOPMATCHSOP(1U)
5310 #define S_RSPERRCNT 8
5311 #define M_RSPERRCNT 0xffU
5312 #define V_RSPERRCNT(x) ((x) << S_RSPERRCNT)
5313 #define G_RSPERRCNT(x) (((x) >> S_RSPERRCNT) & M_RSPERRCNT)
5315 #define S_RSPSOPCNT 0
5316 #define M_RSPSOPCNT 0xffU
5317 #define V_RSPSOPCNT(x) ((x) << S_RSPSOPCNT)
5318 #define G_RSPSOPCNT(x) (((x) >> S_RSPSOPCNT) & M_RSPSOPCNT)
5320 #define A_PCIE_CORE_OUTBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5960
5324 #define V_OP0H(x) ((x) << S_OP0H)
5325 #define G_OP0H(x) (((x) >> S_OP0H) & M_OP0H)
5329 #define V_OP1H(x) ((x) << S_OP1H)
5330 #define G_OP1H(x) (((x) >> S_OP1H) & M_OP1H)
5334 #define V_OP2H(x) ((x) << S_OP2H)
5335 #define G_OP2H(x) (((x) >> S_OP2H) & M_OP2H)
5339 #define V_OP3H(x) ((x) << S_OP3H)
5340 #define G_OP3H(x) (((x) >> S_OP3H) & M_OP3H)
5342 #define A_PCIE_CORE_OUTBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5968
5345 #define M_OP0D 0x7fU
5346 #define V_OP0D(x) ((x) << S_OP0D)
5347 #define G_OP0D(x) (((x) >> S_OP0D) & M_OP0D)
5350 #define M_OP1D 0x7fU
5351 #define V_OP1D(x) ((x) << S_OP1D)
5352 #define G_OP1D(x) (((x) >> S_OP1D) & M_OP1D)
5355 #define M_OP2D 0x7fU
5356 #define V_OP2D(x) ((x) << S_OP2D)
5357 #define G_OP2D(x) (((x) >> S_OP2D) & M_OP2D)
5360 #define M_OP3D 0x7fU
5361 #define V_OP3D(x) ((x) << S_OP3D)
5362 #define G_OP3D(x) (((x) >> S_OP3D) & M_OP3D)
5364 #define A_PCIE_CORE_INBOUND_POSTED_HEADER_BUFFER_ALLOCATION 0x5970
5367 #define M_IP0H 0x3fU
5368 #define V_IP0H(x) ((x) << S_IP0H)
5369 #define G_IP0H(x) (((x) >> S_IP0H) & M_IP0H)
5372 #define M_IP1H 0x3fU
5373 #define V_IP1H(x) ((x) << S_IP1H)
5374 #define G_IP1H(x) (((x) >> S_IP1H) & M_IP1H)
5377 #define M_IP2H 0x3fU
5378 #define V_IP2H(x) ((x) << S_IP2H)
5379 #define G_IP2H(x) (((x) >> S_IP2H) & M_IP2H)
5382 #define M_IP3H 0x3fU
5383 #define V_IP3H(x) ((x) << S_IP3H)
5384 #define G_IP3H(x) (((x) >> S_IP3H) & M_IP3H)
5386 #define A_PCIE_CORE_INBOUND_POSTED_DATA_BUFFER_ALLOCATION 0x5978
5389 #define M_IP0D 0xffU
5390 #define V_IP0D(x) ((x) << S_IP0D)
5391 #define G_IP0D(x) (((x) >> S_IP0D) & M_IP0D)
5394 #define M_IP1D 0xffU
5395 #define V_IP1D(x) ((x) << S_IP1D)
5396 #define G_IP1D(x) (((x) >> S_IP1D) & M_IP1D)
5399 #define M_IP2D 0xffU
5400 #define V_IP2D(x) ((x) << S_IP2D)
5401 #define G_IP2D(x) (((x) >> S_IP2D) & M_IP2D)
5404 #define M_IP3D 0xffU
5405 #define V_IP3D(x) ((x) << S_IP3D)
5406 #define G_IP3D(x) (((x) >> S_IP3D) & M_IP3D)
5408 #define A_PCIE_CORE_OUTBOUND_NON_POSTED_BUFFER_ALLOCATION 0x5980
5412 #define V_ON0H(x) ((x) << S_ON0H)
5413 #define G_ON0H(x) (((x) >> S_ON0H) & M_ON0H)
5417 #define V_ON1H(x) ((x) << S_ON1H)
5418 #define G_ON1H(x) (((x) >> S_ON1H) & M_ON1H)
5422 #define V_ON2H(x) ((x) << S_ON2H)
5423 #define G_ON2H(x) (((x) >> S_ON2H) & M_ON2H)
5427 #define V_ON3H(x) ((x) << S_ON3H)
5428 #define G_ON3H(x) (((x) >> S_ON3H) & M_ON3H)
5430 #define A_PCIE_T5_CMD_CFG 0x5980
5432 #define S_T5_CMD_MAXRDREQSIZE 17
5433 #define M_T5_CMD_MAXRDREQSIZE 0x7U
5434 #define V_T5_CMD_MAXRDREQSIZE(x) ((x) << S_T5_CMD_MAXRDREQSIZE)
5435 #define G_T5_CMD_MAXRDREQSIZE(x) (((x) >> S_T5_CMD_MAXRDREQSIZE) & M_T5_CMD_MAXRDREQSIZE)
5437 #define S_T5_CMD_MAXRSPCNT 8
5438 #define M_T5_CMD_MAXRSPCNT 0xffU
5439 #define V_T5_CMD_MAXRSPCNT(x) ((x) << S_T5_CMD_MAXRSPCNT)
5440 #define G_T5_CMD_MAXRSPCNT(x) (((x) >> S_T5_CMD_MAXRSPCNT) & M_T5_CMD_MAXRSPCNT)
5442 #define S_USECMDPOOL 7
5443 #define V_USECMDPOOL(x) ((x) << S_USECMDPOOL)
5444 #define F_USECMDPOOL V_USECMDPOOL(1U)
5446 #define A_PCIE_T5_CMD_STAT 0x5984
5448 #define S_T5_STAT_RSPCNT 20
5449 #define M_T5_STAT_RSPCNT 0x7ffU
5450 #define V_T5_STAT_RSPCNT(x) ((x) << S_T5_STAT_RSPCNT)
5451 #define G_T5_STAT_RSPCNT(x) (((x) >> S_T5_STAT_RSPCNT) & M_T5_STAT_RSPCNT)
5453 #define S_RDREQCNT 12
5454 #define M_RDREQCNT 0x1fU
5455 #define V_RDREQCNT(x) ((x) << S_RDREQCNT)
5456 #define G_RDREQCNT(x) (((x) >> S_RDREQCNT) & M_RDREQCNT)
5458 #define A_PCIE_CORE_INBOUND_NON_POSTED_REQUESTS_BUFFER_ALLOCATION 0x5988
5461 #define M_IN0H 0x3fU
5462 #define V_IN0H(x) ((x) << S_IN0H)
5463 #define G_IN0H(x) (((x) >> S_IN0H) & M_IN0H)
5466 #define M_IN1H 0x3fU
5467 #define V_IN1H(x) ((x) << S_IN1H)
5468 #define G_IN1H(x) (((x) >> S_IN1H) & M_IN1H)
5471 #define M_IN2H 0x3fU
5472 #define V_IN2H(x) ((x) << S_IN2H)
5473 #define G_IN2H(x) (((x) >> S_IN2H) & M_IN2H)
5476 #define M_IN3H 0x3fU
5477 #define V_IN3H(x) ((x) << S_IN3H)
5478 #define G_IN3H(x) (((x) >> S_IN3H) & M_IN3H)
5480 #define A_PCIE_T5_CMD_STAT2 0x5988
5481 #define A_PCIE_T5_CMD_STAT3 0x598c
5482 #define A_PCIE_CORE_PCI_EXPRESS_TAGS_ALLOCATION 0x5990
5485 #define M_OC0T 0xffU
5486 #define V_OC0T(x) ((x) << S_OC0T)
5487 #define G_OC0T(x) (((x) >> S_OC0T) & M_OC0T)
5490 #define M_OC1T 0xffU
5491 #define V_OC1T(x) ((x) << S_OC1T)
5492 #define G_OC1T(x) (((x) >> S_OC1T) & M_OC1T)
5495 #define M_OC2T 0xffU
5496 #define V_OC2T(x) ((x) << S_OC2T)
5497 #define G_OC2T(x) (((x) >> S_OC2T) & M_OC2T)
5500 #define M_OC3T 0xffU
5501 #define V_OC3T(x) ((x) << S_OC3T)
5502 #define G_OC3T(x) (((x) >> S_OC3T) & M_OC3T)
5504 #define A_PCIE_CORE_GBIF_READ_TAGS_ALLOCATION 0x5998
5507 #define M_IC0T 0x3fU
5508 #define V_IC0T(x) ((x) << S_IC0T)
5509 #define G_IC0T(x) (((x) >> S_IC0T) & M_IC0T)
5512 #define M_IC1T 0x3fU
5513 #define V_IC1T(x) ((x) << S_IC1T)
5514 #define G_IC1T(x) (((x) >> S_IC1T) & M_IC1T)
5517 #define M_IC2T 0x3fU
5518 #define V_IC2T(x) ((x) << S_IC2T)
5519 #define G_IC2T(x) (((x) >> S_IC2T) & M_IC2T)
5522 #define M_IC3T 0x3fU
5523 #define V_IC3T(x) ((x) << S_IC3T)
5524 #define G_IC3T(x) (((x) >> S_IC3T) & M_IC3T)
5526 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_CONTROL 0x59a0
5529 #define V_VRB0(x) ((x) << S_VRB0)
5530 #define F_VRB0 V_VRB0(1U)
5533 #define V_VRB1(x) ((x) << S_VRB1)
5534 #define F_VRB1 V_VRB1(1U)
5537 #define V_VRB2(x) ((x) << S_VRB2)
5538 #define F_VRB2 V_VRB2(1U)
5541 #define V_VRB3(x) ((x) << S_VRB3)
5542 #define F_VRB3 V_VRB3(1U)
5545 #define V_PSFE(x) ((x) << S_PSFE)
5546 #define F_PSFE V_PSFE(1U)
5549 #define V_RVDE(x) ((x) << S_RVDE)
5550 #define F_RVDE V_RVDE(1U)
5553 #define V_TXE0(x) ((x) << S_TXE0)
5554 #define F_TXE0 V_TXE0(1U)
5557 #define V_TXE1(x) ((x) << S_TXE1)
5558 #define F_TXE1 V_TXE1(1U)
5561 #define V_TXE2(x) ((x) << S_TXE2)
5562 #define F_TXE2 V_TXE2(1U)
5565 #define V_TXE3(x) ((x) << S_TXE3)
5566 #define F_TXE3 V_TXE3(1U)
5569 #define V_RPAM(x) ((x) << S_RPAM)
5570 #define F_RPAM V_RPAM(1U)
5574 #define V_RTOS(x) ((x) << S_RTOS)
5575 #define G_RTOS(x) (((x) >> S_RTOS) & M_RTOS)
5577 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_STATUS 0x59a4
5580 #define V_TPCP(x) ((x) << S_TPCP)
5581 #define F_TPCP V_TPCP(1U)
5584 #define V_TNPP(x) ((x) << S_TNPP)
5585 #define F_TNPP V_TNPP(1U)
5588 #define V_TFTP(x) ((x) << S_TFTP)
5589 #define F_TFTP V_TFTP(1U)
5592 #define V_TCAP(x) ((x) << S_TCAP)
5593 #define F_TCAP V_TCAP(1U)
5596 #define V_TCIP(x) ((x) << S_TCIP)
5597 #define F_TCIP V_TCIP(1U)
5600 #define V_RCAP(x) ((x) << S_RCAP)
5601 #define F_RCAP V_RCAP(1U)
5604 #define V_PLUP(x) ((x) << S_PLUP)
5605 #define F_PLUP V_PLUP(1U)
5608 #define V_PLDN(x) ((x) << S_PLDN)
5609 #define F_PLDN V_PLDN(1U)
5612 #define V_OTDD(x) ((x) << S_OTDD)
5613 #define F_OTDD V_OTDD(1U)
5616 #define V_GTRP(x) ((x) << S_GTRP)
5617 #define F_GTRP V_GTRP(1U)
5620 #define V_RDPE(x) ((x) << S_RDPE)
5621 #define F_RDPE V_RDPE(1U)
5624 #define V_TDCE(x) ((x) << S_TDCE)
5625 #define F_TDCE V_TDCE(1U)
5628 #define V_TDUE(x) ((x) << S_TDUE)
5629 #define F_TDUE V_TDUE(1U)
5631 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_ERROR_SEVERITY 0x59a8
5634 #define V_TPCS(x) ((x) << S_TPCS)
5635 #define F_TPCS V_TPCS(1U)
5638 #define V_TNPS(x) ((x) << S_TNPS)
5639 #define F_TNPS V_TNPS(1U)
5642 #define V_TFTS(x) ((x) << S_TFTS)
5643 #define F_TFTS V_TFTS(1U)
5646 #define V_TCAS(x) ((x) << S_TCAS)
5647 #define F_TCAS V_TCAS(1U)
5650 #define V_TCIS(x) ((x) << S_TCIS)
5651 #define F_TCIS V_TCIS(1U)
5654 #define V_RCAS(x) ((x) << S_RCAS)
5655 #define F_RCAS V_RCAS(1U)
5658 #define V_PLUS(x) ((x) << S_PLUS)
5659 #define F_PLUS V_PLUS(1U)
5662 #define V_PLDS(x) ((x) << S_PLDS)
5663 #define F_PLDS V_PLDS(1U)
5666 #define V_OTDS(x) ((x) << S_OTDS)
5667 #define F_OTDS V_OTDS(1U)
5670 #define V_RDPS(x) ((x) << S_RDPS)
5671 #define F_RDPS V_RDPS(1U)
5674 #define V_TDCS(x) ((x) << S_TDCS)
5675 #define F_TDCS V_TDCS(1U)
5678 #define V_TDUS(x) ((x) << S_TDUS)
5679 #define F_TDUS V_TDUS(1U)
5681 #define A_PCIE_CORE_UTL_PCI_EXPRESS_PORT_INTERRUPT_ENABLE 0x59ac
5684 #define V_TPCI(x) ((x) << S_TPCI)
5685 #define F_TPCI V_TPCI(1U)
5688 #define V_TNPI(x) ((x) << S_TNPI)
5689 #define F_TNPI V_TNPI(1U)
5692 #define V_TFTI(x) ((x) << S_TFTI)
5693 #define F_TFTI V_TFTI(1U)
5696 #define V_TCAI(x) ((x) << S_TCAI)
5697 #define F_TCAI V_TCAI(1U)
5700 #define V_TCII(x) ((x) << S_TCII)
5701 #define F_TCII V_TCII(1U)
5704 #define V_RCAI(x) ((x) << S_RCAI)
5705 #define F_RCAI V_RCAI(1U)
5708 #define V_PLUI(x) ((x) << S_PLUI)
5709 #define F_PLUI V_PLUI(1U)
5712 #define V_PLDI(x) ((x) << S_PLDI)
5713 #define F_PLDI V_PLDI(1U)
5716 #define V_OTDI(x) ((x) << S_OTDI)
5717 #define F_OTDI V_OTDI(1U)
5719 #define A_PCIE_CORE_ROOT_COMPLEX_STATUS 0x59b0
5722 #define V_RLCE(x) ((x) << S_RLCE)
5723 #define F_RLCE V_RLCE(1U)
5726 #define V_RLNE(x) ((x) << S_RLNE)
5727 #define F_RLNE V_RLNE(1U)
5730 #define V_RLFE(x) ((x) << S_RLFE)
5731 #define F_RLFE V_RLFE(1U)
5734 #define V_RCPE(x) ((x) << S_RCPE)
5735 #define F_RCPE V_RCPE(1U)
5738 #define V_RCTO(x) ((x) << S_RCTO)
5739 #define F_RCTO V_RCTO(1U)
5742 #define V_PINA(x) ((x) << S_PINA)
5743 #define F_PINA V_PINA(1U)
5746 #define V_PINB(x) ((x) << S_PINB)
5747 #define F_PINB V_PINB(1U)
5750 #define V_PINC(x) ((x) << S_PINC)
5751 #define F_PINC V_PINC(1U)
5754 #define V_PIND(x) ((x) << S_PIND)
5755 #define F_PIND V_PIND(1U)
5758 #define V_ALER(x) ((x) << S_ALER)
5759 #define F_ALER V_ALER(1U)
5762 #define V_CRSE(x) ((x) << S_CRSE)
5763 #define F_CRSE V_CRSE(1U)
5765 #define A_PCIE_T5_HMA_CFG 0x59b0
5767 #define S_HMA_MAXREQCNT 20
5768 #define M_HMA_MAXREQCNT 0x1fU
5769 #define V_HMA_MAXREQCNT(x) ((x) << S_HMA_MAXREQCNT)
5770 #define G_HMA_MAXREQCNT(x) (((x) >> S_HMA_MAXREQCNT) & M_HMA_MAXREQCNT)
5772 #define S_T5_HMA_MAXRDREQSIZE 17
5773 #define M_T5_HMA_MAXRDREQSIZE 0x7U
5774 #define V_T5_HMA_MAXRDREQSIZE(x) ((x) << S_T5_HMA_MAXRDREQSIZE)
5775 #define G_T5_HMA_MAXRDREQSIZE(x) (((x) >> S_T5_HMA_MAXRDREQSIZE) & M_T5_HMA_MAXRDREQSIZE)
5777 #define S_T5_HMA_MAXRSPCNT 8
5778 #define M_T5_HMA_MAXRSPCNT 0x1fU
5779 #define V_T5_HMA_MAXRSPCNT(x) ((x) << S_T5_HMA_MAXRSPCNT)
5780 #define G_T5_HMA_MAXRSPCNT(x) (((x) >> S_T5_HMA_MAXRSPCNT) & M_T5_HMA_MAXRSPCNT)
5782 #define A_PCIE_CORE_ROOT_COMPLEX_ERROR_SEVERITY 0x59b4
5785 #define V_RLCS(x) ((x) << S_RLCS)
5786 #define F_RLCS V_RLCS(1U)
5789 #define V_RLNS(x) ((x) << S_RLNS)
5790 #define F_RLNS V_RLNS(1U)
5793 #define V_RLFS(x) ((x) << S_RLFS)
5794 #define F_RLFS V_RLFS(1U)
5797 #define V_RCPS(x) ((x) << S_RCPS)
5798 #define F_RCPS V_RCPS(1U)
5801 #define V_RCTS(x) ((x) << S_RCTS)
5802 #define F_RCTS V_RCTS(1U)
5805 #define V_PAAS(x) ((x) << S_PAAS)
5806 #define F_PAAS V_PAAS(1U)
5809 #define V_PABS(x) ((x) << S_PABS)
5810 #define F_PABS V_PABS(1U)
5813 #define V_PACS(x) ((x) << S_PACS)
5814 #define F_PACS V_PACS(1U)
5817 #define V_PADS(x) ((x) << S_PADS)
5818 #define F_PADS V_PADS(1U)
5821 #define V_ALES(x) ((x) << S_ALES)
5822 #define F_ALES V_ALES(1U)
5825 #define V_CRSS(x) ((x) << S_CRSS)
5826 #define F_CRSS V_CRSS(1U)
5828 #define A_PCIE_T5_HMA_STAT 0x59b4
5830 #define S_HMA_RESPCNT 20
5831 #define M_HMA_RESPCNT 0x1ffU
5832 #define V_HMA_RESPCNT(x) ((x) << S_HMA_RESPCNT)
5833 #define G_HMA_RESPCNT(x) (((x) >> S_HMA_RESPCNT) & M_HMA_RESPCNT)
5835 #define S_HMA_RDREQCNT 12
5836 #define M_HMA_RDREQCNT 0x3fU
5837 #define V_HMA_RDREQCNT(x) ((x) << S_HMA_RDREQCNT)
5838 #define G_HMA_RDREQCNT(x) (((x) >> S_HMA_RDREQCNT) & M_HMA_RDREQCNT)
5840 #define S_HMA_WRREQCNT 0
5841 #define M_HMA_WRREQCNT 0x1ffU
5842 #define V_HMA_WRREQCNT(x) ((x) << S_HMA_WRREQCNT)
5843 #define G_HMA_WRREQCNT(x) (((x) >> S_HMA_WRREQCNT) & M_HMA_WRREQCNT)
5845 #define A_PCIE_CORE_ROOT_COMPLEX_INTERRUPT_ENABLE 0x59b8
5848 #define V_RLCI(x) ((x) << S_RLCI)
5849 #define F_RLCI V_RLCI(1U)
5852 #define V_RLNI(x) ((x) << S_RLNI)
5853 #define F_RLNI V_RLNI(1U)
5856 #define V_RLFI(x) ((x) << S_RLFI)
5857 #define F_RLFI V_RLFI(1U)
5860 #define V_RCPI(x) ((x) << S_RCPI)
5861 #define F_RCPI V_RCPI(1U)
5864 #define V_RCTI(x) ((x) << S_RCTI)
5865 #define F_RCTI V_RCTI(1U)
5868 #define V_PAAI(x) ((x) << S_PAAI)
5869 #define F_PAAI V_PAAI(1U)
5872 #define V_PABI(x) ((x) << S_PABI)
5873 #define F_PABI V_PABI(1U)
5876 #define V_PACI(x) ((x) << S_PACI)
5877 #define F_PACI V_PACI(1U)
5880 #define V_PADI(x) ((x) << S_PADI)
5881 #define F_PADI V_PADI(1U)
5884 #define V_ALEI(x) ((x) << S_ALEI)
5885 #define F_ALEI V_ALEI(1U)
5888 #define V_CRSI(x) ((x) << S_CRSI)
5889 #define F_CRSI V_CRSI(1U)
5891 #define A_PCIE_T5_HMA_STAT2 0x59b8
5892 #define A_PCIE_CORE_ENDPOINT_STATUS 0x59bc
5895 #define V_PTOM(x) ((x) << S_PTOM)
5896 #define F_PTOM V_PTOM(1U)
5899 #define V_ALEA(x) ((x) << S_ALEA)
5900 #define F_ALEA V_ALEA(1U)
5903 #define V_PMC0(x) ((x) << S_PMC0)
5904 #define F_PMC0 V_PMC0(1U)
5907 #define V_PMC1(x) ((x) << S_PMC1)
5908 #define F_PMC1 V_PMC1(1U)
5911 #define V_PMC2(x) ((x) << S_PMC2)
5912 #define F_PMC2 V_PMC2(1U)
5915 #define V_PMC3(x) ((x) << S_PMC3)
5916 #define F_PMC3 V_PMC3(1U)
5919 #define V_PMC4(x) ((x) << S_PMC4)
5920 #define F_PMC4 V_PMC4(1U)
5923 #define V_PMC5(x) ((x) << S_PMC5)
5924 #define F_PMC5 V_PMC5(1U)
5927 #define V_PMC6(x) ((x) << S_PMC6)
5928 #define F_PMC6 V_PMC6(1U)
5931 #define V_PMC7(x) ((x) << S_PMC7)
5932 #define F_PMC7 V_PMC7(1U)
5934 #define A_PCIE_T5_HMA_STAT3 0x59bc
5935 #define A_PCIE_CORE_ENDPOINT_ERROR_SEVERITY 0x59c0
5938 #define V_PTOS(x) ((x) << S_PTOS)
5939 #define F_PTOS V_PTOS(1U)
5942 #define V_AENS(x) ((x) << S_AENS)
5943 #define F_AENS V_AENS(1U)
5946 #define V_PC0S(x) ((x) << S_PC0S)
5947 #define F_PC0S V_PC0S(1U)
5950 #define V_PC1S(x) ((x) << S_PC1S)
5951 #define F_PC1S V_PC1S(1U)
5954 #define V_PC2S(x) ((x) << S_PC2S)
5955 #define F_PC2S V_PC2S(1U)
5958 #define V_PC3S(x) ((x) << S_PC3S)
5959 #define F_PC3S V_PC3S(1U)
5962 #define V_PC4S(x) ((x) << S_PC4S)
5963 #define F_PC4S V_PC4S(1U)
5966 #define V_PC5S(x) ((x) << S_PC5S)
5967 #define F_PC5S V_PC5S(1U)
5970 #define V_PC6S(x) ((x) << S_PC6S)
5971 #define F_PC6S V_PC6S(1U)
5974 #define V_PC7S(x) ((x) << S_PC7S)
5975 #define F_PC7S V_PC7S(1U)
5978 #define V_PME0(x) ((x) << S_PME0)
5979 #define F_PME0 V_PME0(1U)
5982 #define V_PME1(x) ((x) << S_PME1)
5983 #define F_PME1 V_PME1(1U)
5986 #define V_PME2(x) ((x) << S_PME2)
5987 #define F_PME2 V_PME2(1U)
5990 #define V_PME3(x) ((x) << S_PME3)
5991 #define F_PME3 V_PME3(1U)
5994 #define V_PME4(x) ((x) << S_PME4)
5995 #define F_PME4 V_PME4(1U)
5998 #define V_PME5(x) ((x) << S_PME5)
5999 #define F_PME5 V_PME5(1U)
6002 #define V_PME6(x) ((x) << S_PME6)
6003 #define F_PME6 V_PME6(1U)
6006 #define V_PME7(x) ((x) << S_PME7)
6007 #define F_PME7 V_PME7(1U)
6009 #define A_PCIE_CGEN 0x59c0
6011 #define S_VPD_DYNAMIC_CGEN 26
6012 #define V_VPD_DYNAMIC_CGEN(x) ((x) << S_VPD_DYNAMIC_CGEN)
6013 #define F_VPD_DYNAMIC_CGEN V_VPD_DYNAMIC_CGEN(1U)
6015 #define S_MA_DYNAMIC_CGEN 25
6016 #define V_MA_DYNAMIC_CGEN(x) ((x) << S_MA_DYNAMIC_CGEN)
6017 #define F_MA_DYNAMIC_CGEN V_MA_DYNAMIC_CGEN(1U)
6019 #define S_TAGQ_DYNAMIC_CGEN 24
6020 #define V_TAGQ_DYNAMIC_CGEN(x) ((x) << S_TAGQ_DYNAMIC_CGEN)
6021 #define F_TAGQ_DYNAMIC_CGEN V_TAGQ_DYNAMIC_CGEN(1U)
6023 #define S_REQCTL_DYNAMIC_CGEN 23
6024 #define V_REQCTL_DYNAMIC_CGEN(x) ((x) << S_REQCTL_DYNAMIC_CGEN)
6025 #define F_REQCTL_DYNAMIC_CGEN V_REQCTL_DYNAMIC_CGEN(1U)
6027 #define S_RSPDATAPROC_DYNAMIC_CGEN 22
6028 #define V_RSPDATAPROC_DYNAMIC_CGEN(x) ((x) << S_RSPDATAPROC_DYNAMIC_CGEN)
6029 #define F_RSPDATAPROC_DYNAMIC_CGEN V_RSPDATAPROC_DYNAMIC_CGEN(1U)
6031 #define S_RSPRDQ_DYNAMIC_CGEN 21
6032 #define V_RSPRDQ_DYNAMIC_CGEN(x) ((x) << S_RSPRDQ_DYNAMIC_CGEN)
6033 #define F_RSPRDQ_DYNAMIC_CGEN V_RSPRDQ_DYNAMIC_CGEN(1U)
6035 #define S_RSPIPIF_DYNAMIC_CGEN 20
6036 #define V_RSPIPIF_DYNAMIC_CGEN(x) ((x) << S_RSPIPIF_DYNAMIC_CGEN)
6037 #define F_RSPIPIF_DYNAMIC_CGEN V_RSPIPIF_DYNAMIC_CGEN(1U)
6039 #define S_HMA_STATIC_CGEN 19
6040 #define V_HMA_STATIC_CGEN(x) ((x) << S_HMA_STATIC_CGEN)
6041 #define F_HMA_STATIC_CGEN V_HMA_STATIC_CGEN(1U)
6043 #define S_HMA_DYNAMIC_CGEN 18
6044 #define V_HMA_DYNAMIC_CGEN(x) ((x) << S_HMA_DYNAMIC_CGEN)
6045 #define F_HMA_DYNAMIC_CGEN V_HMA_DYNAMIC_CGEN(1U)
6047 #define S_CMD_STATIC_CGEN 16
6048 #define V_CMD_STATIC_CGEN(x) ((x) << S_CMD_STATIC_CGEN)
6049 #define F_CMD_STATIC_CGEN V_CMD_STATIC_CGEN(1U)
6051 #define S_CMD_DYNAMIC_CGEN 15
6052 #define V_CMD_DYNAMIC_CGEN(x) ((x) << S_CMD_DYNAMIC_CGEN)
6053 #define F_CMD_DYNAMIC_CGEN V_CMD_DYNAMIC_CGEN(1U)
6055 #define S_DMA_STATIC_CGEN 13
6056 #define V_DMA_STATIC_CGEN(x) ((x) << S_DMA_STATIC_CGEN)
6057 #define F_DMA_STATIC_CGEN V_DMA_STATIC_CGEN(1U)
6059 #define S_DMA_DYNAMIC_CGEN 12
6060 #define V_DMA_DYNAMIC_CGEN(x) ((x) << S_DMA_DYNAMIC_CGEN)
6061 #define F_DMA_DYNAMIC_CGEN V_DMA_DYNAMIC_CGEN(1U)
6063 #define S_VFID_SLEEPSTATUS 10
6064 #define V_VFID_SLEEPSTATUS(x) ((x) << S_VFID_SLEEPSTATUS)
6065 #define F_VFID_SLEEPSTATUS V_VFID_SLEEPSTATUS(1U)
6067 #define S_VC1_SLEEPSTATUS 9
6068 #define V_VC1_SLEEPSTATUS(x) ((x) << S_VC1_SLEEPSTATUS)
6069 #define F_VC1_SLEEPSTATUS V_VC1_SLEEPSTATUS(1U)
6071 #define S_STI_SLEEPSTATUS 8
6072 #define V_STI_SLEEPSTATUS(x) ((x) << S_STI_SLEEPSTATUS)
6073 #define F_STI_SLEEPSTATUS V_STI_SLEEPSTATUS(1U)
6075 #define S_VFID_SLEEPREQ 2
6076 #define V_VFID_SLEEPREQ(x) ((x) << S_VFID_SLEEPREQ)
6077 #define F_VFID_SLEEPREQ V_VFID_SLEEPREQ(1U)
6079 #define S_VC1_SLEEPREQ 1
6080 #define V_VC1_SLEEPREQ(x) ((x) << S_VC1_SLEEPREQ)
6081 #define F_VC1_SLEEPREQ V_VC1_SLEEPREQ(1U)
6083 #define S_STI_SLEEPREQ 0
6084 #define V_STI_SLEEPREQ(x) ((x) << S_STI_SLEEPREQ)
6085 #define F_STI_SLEEPREQ V_STI_SLEEPREQ(1U)
6087 #define A_PCIE_CORE_ENDPOINT_INTERRUPT_ENABLE 0x59c4
6090 #define V_PTOI(x) ((x) << S_PTOI)
6091 #define F_PTOI V_PTOI(1U)
6094 #define V_AENI(x) ((x) << S_AENI)
6095 #define F_AENI V_AENI(1U)
6098 #define V_PC0I(x) ((x) << S_PC0I)
6099 #define F_PC0I V_PC0I(1U)
6102 #define V_PC1I(x) ((x) << S_PC1I)
6103 #define F_PC1I V_PC1I(1U)
6106 #define V_PC2I(x) ((x) << S_PC2I)
6107 #define F_PC2I V_PC2I(1U)
6110 #define V_PC3I(x) ((x) << S_PC3I)
6111 #define F_PC3I V_PC3I(1U)
6114 #define V_PC4I(x) ((x) << S_PC4I)
6115 #define F_PC4I V_PC4I(1U)
6118 #define V_PC5I(x) ((x) << S_PC5I)
6119 #define F_PC5I V_PC5I(1U)
6122 #define V_PC6I(x) ((x) << S_PC6I)
6123 #define F_PC6I V_PC6I(1U)
6126 #define V_PC7I(x) ((x) << S_PC7I)
6127 #define F_PC7I V_PC7I(1U)
6129 #define A_PCIE_MA_RSP 0x59c4
6131 #define S_TIMERVALUE 8
6132 #define M_TIMERVALUE 0xffffffU
6133 #define V_TIMERVALUE(x) ((x) << S_TIMERVALUE)
6134 #define G_TIMERVALUE(x) (((x) >> S_TIMERVALUE) & M_TIMERVALUE)
6136 #define S_MAREQTIMEREN 1
6137 #define V_MAREQTIMEREN(x) ((x) << S_MAREQTIMEREN)
6138 #define F_MAREQTIMEREN V_MAREQTIMEREN(1U)
6140 #define S_MARSPTIMEREN 0
6141 #define V_MARSPTIMEREN(x) ((x) << S_MARSPTIMEREN)
6142 #define F_MARSPTIMEREN V_MARSPTIMEREN(1U)
6144 #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_1 0x59c8
6147 #define V_TOAK(x) ((x) << S_TOAK)
6148 #define F_TOAK V_TOAK(1U)
6151 #define V_L1RS(x) ((x) << S_L1RS)
6152 #define F_L1RS V_L1RS(1U)
6155 #define V_L23S(x) ((x) << S_L23S)
6156 #define F_L23S V_L23S(1U)
6159 #define V_AL1S(x) ((x) << S_AL1S)
6160 #define F_AL1S V_AL1S(1U)
6163 #define V_ALET(x) ((x) << S_ALET)
6164 #define F_ALET V_ALET(1U)
6166 #define A_PCIE_HPRD 0x59c8
6168 #define S_NPH_CREDITSAVAILVC0 19
6169 #define M_NPH_CREDITSAVAILVC0 0x3U
6170 #define V_NPH_CREDITSAVAILVC0(x) ((x) << S_NPH_CREDITSAVAILVC0)
6171 #define G_NPH_CREDITSAVAILVC0(x) (((x) >> S_NPH_CREDITSAVAILVC0) & M_NPH_CREDITSAVAILVC0)
6173 #define S_NPD_CREDITSAVAILVC0 17
6174 #define M_NPD_CREDITSAVAILVC0 0x3U
6175 #define V_NPD_CREDITSAVAILVC0(x) ((x) << S_NPD_CREDITSAVAILVC0)
6176 #define G_NPD_CREDITSAVAILVC0(x) (((x) >> S_NPD_CREDITSAVAILVC0) & M_NPD_CREDITSAVAILVC0)
6178 #define S_NPH_CREDITSAVAILVC1 15
6179 #define M_NPH_CREDITSAVAILVC1 0x3U
6180 #define V_NPH_CREDITSAVAILVC1(x) ((x) << S_NPH_CREDITSAVAILVC1)
6181 #define G_NPH_CREDITSAVAILVC1(x) (((x) >> S_NPH_CREDITSAVAILVC1) & M_NPH_CREDITSAVAILVC1)
6183 #define S_NPD_CREDITSAVAILVC1 13
6184 #define M_NPD_CREDITSAVAILVC1 0x3U
6185 #define V_NPD_CREDITSAVAILVC1(x) ((x) << S_NPD_CREDITSAVAILVC1)
6186 #define G_NPD_CREDITSAVAILVC1(x) (((x) >> S_NPD_CREDITSAVAILVC1) & M_NPD_CREDITSAVAILVC1)
6188 #define S_NPH_CREDITSREQUIRED 11
6189 #define M_NPH_CREDITSREQUIRED 0x3U
6190 #define V_NPH_CREDITSREQUIRED(x) ((x) << S_NPH_CREDITSREQUIRED)
6191 #define G_NPH_CREDITSREQUIRED(x) (((x) >> S_NPH_CREDITSREQUIRED) & M_NPH_CREDITSREQUIRED)
6193 #define S_NPD_CREDITSREQUIRED 9
6194 #define M_NPD_CREDITSREQUIRED 0x3U
6195 #define V_NPD_CREDITSREQUIRED(x) ((x) << S_NPD_CREDITSREQUIRED)
6196 #define G_NPD_CREDITSREQUIRED(x) (((x) >> S_NPD_CREDITSREQUIRED) & M_NPD_CREDITSREQUIRED)
6198 #define S_REQBURSTCOUNT 5
6199 #define M_REQBURSTCOUNT 0xfU
6200 #define V_REQBURSTCOUNT(x) ((x) << S_REQBURSTCOUNT)
6201 #define G_REQBURSTCOUNT(x) (((x) >> S_REQBURSTCOUNT) & M_REQBURSTCOUNT)
6203 #define S_REQBURSTFREQUENCY 1
6204 #define M_REQBURSTFREQUENCY 0xfU
6205 #define V_REQBURSTFREQUENCY(x) ((x) << S_REQBURSTFREQUENCY)
6206 #define G_REQBURSTFREQUENCY(x) (((x) >> S_REQBURSTFREQUENCY) & M_REQBURSTFREQUENCY)
6208 #define S_ENABLEVC1 0
6209 #define V_ENABLEVC1(x) ((x) << S_ENABLEVC1)
6210 #define F_ENABLEVC1 V_ENABLEVC1(1U)
6212 #define A_PCIE_CORE_PCI_POWER_MANAGEMENT_CONTROL_2 0x59cc
6216 #define V_CPM0(x) ((x) << S_CPM0)
6217 #define G_CPM0(x) (((x) >> S_CPM0) & M_CPM0)
6221 #define V_CPM1(x) ((x) << S_CPM1)
6222 #define G_CPM1(x) (((x) >> S_CPM1) & M_CPM1)
6226 #define V_CPM2(x) ((x) << S_CPM2)
6227 #define G_CPM2(x) (((x) >> S_CPM2) & M_CPM2)
6231 #define V_CPM3(x) ((x) << S_CPM3)
6232 #define G_CPM3(x) (((x) >> S_CPM3) & M_CPM3)
6236 #define V_CPM4(x) ((x) << S_CPM4)
6237 #define G_CPM4(x) (((x) >> S_CPM4) & M_CPM4)
6241 #define V_CPM5(x) ((x) << S_CPM5)
6242 #define G_CPM5(x) (((x) >> S_CPM5) & M_CPM5)
6246 #define V_CPM6(x) ((x) << S_CPM6)
6247 #define G_CPM6(x) (((x) >> S_CPM6) & M_CPM6)
6251 #define V_CPM7(x) ((x) << S_CPM7)
6252 #define G_CPM7(x) (((x) >> S_CPM7) & M_CPM7)
6256 #define V_OPM0(x) ((x) << S_OPM0)
6257 #define G_OPM0(x) (((x) >> S_OPM0) & M_OPM0)
6261 #define V_OPM1(x) ((x) << S_OPM1)
6262 #define G_OPM1(x) (((x) >> S_OPM1) & M_OPM1)
6266 #define V_OPM2(x) ((x) << S_OPM2)
6267 #define G_OPM2(x) (((x) >> S_OPM2) & M_OPM2)
6271 #define V_OPM3(x) ((x) << S_OPM3)
6272 #define G_OPM3(x) (((x) >> S_OPM3) & M_OPM3)
6276 #define V_OPM4(x) ((x) << S_OPM4)
6277 #define G_OPM4(x) (((x) >> S_OPM4) & M_OPM4)
6281 #define V_OPM5(x) ((x) << S_OPM5)
6282 #define G_OPM5(x) (((x) >> S_OPM5) & M_OPM5)
6286 #define V_OPM6(x) ((x) << S_OPM6)
6287 #define G_OPM6(x) (((x) >> S_OPM6) & M_OPM6)
6291 #define V_OPM7(x) ((x) << S_OPM7)
6292 #define G_OPM7(x) (((x) >> S_OPM7) & M_OPM7)
6294 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_1 0x59d0
6295 #define A_PCIE_PERR_GROUP 0x59d0
6297 #define S_MST_DATAPATHPERR 25
6298 #define V_MST_DATAPATHPERR(x) ((x) << S_MST_DATAPATHPERR)
6299 #define F_MST_DATAPATHPERR V_MST_DATAPATHPERR(1U)
6301 #define S_MST_RSPRDQPERR 24
6302 #define V_MST_RSPRDQPERR(x) ((x) << S_MST_RSPRDQPERR)
6303 #define F_MST_RSPRDQPERR V_MST_RSPRDQPERR(1U)
6305 #define S_IP_RXPERR 23
6306 #define V_IP_RXPERR(x) ((x) << S_IP_RXPERR)
6307 #define F_IP_RXPERR V_IP_RXPERR(1U)
6309 #define S_IP_BACKTXPERR 22
6310 #define V_IP_BACKTXPERR(x) ((x) << S_IP_BACKTXPERR)
6311 #define F_IP_BACKTXPERR V_IP_BACKTXPERR(1U)
6313 #define S_IP_FRONTTXPERR 21
6314 #define V_IP_FRONTTXPERR(x) ((x) << S_IP_FRONTTXPERR)
6315 #define F_IP_FRONTTXPERR V_IP_FRONTTXPERR(1U)
6317 #define S_TRGT1_FIDLKUPHDRPERR 20
6318 #define V_TRGT1_FIDLKUPHDRPERR(x) ((x) << S_TRGT1_FIDLKUPHDRPERR)
6319 #define F_TRGT1_FIDLKUPHDRPERR V_TRGT1_FIDLKUPHDRPERR(1U)
6321 #define S_TRGT1_ALINDDATAPERR 19
6322 #define V_TRGT1_ALINDDATAPERR(x) ((x) << S_TRGT1_ALINDDATAPERR)
6323 #define F_TRGT1_ALINDDATAPERR V_TRGT1_ALINDDATAPERR(1U)
6325 #define S_TRGT1_UNALINDATAPERR 18
6326 #define V_TRGT1_UNALINDATAPERR(x) ((x) << S_TRGT1_UNALINDATAPERR)
6327 #define F_TRGT1_UNALINDATAPERR V_TRGT1_UNALINDATAPERR(1U)
6329 #define S_TRGT1_REQDATAPERR 17
6330 #define V_TRGT1_REQDATAPERR(x) ((x) << S_TRGT1_REQDATAPERR)
6331 #define F_TRGT1_REQDATAPERR V_TRGT1_REQDATAPERR(1U)
6333 #define S_TRGT1_REQHDRPERR 16
6334 #define V_TRGT1_REQHDRPERR(x) ((x) << S_TRGT1_REQHDRPERR)
6335 #define F_TRGT1_REQHDRPERR V_TRGT1_REQHDRPERR(1U)
6337 #define S_IPRXDATA_VC1PERR 15
6338 #define V_IPRXDATA_VC1PERR(x) ((x) << S_IPRXDATA_VC1PERR)
6339 #define F_IPRXDATA_VC1PERR V_IPRXDATA_VC1PERR(1U)
6341 #define S_IPRXDATA_VC0PERR 14
6342 #define V_IPRXDATA_VC0PERR(x) ((x) << S_IPRXDATA_VC0PERR)
6343 #define F_IPRXDATA_VC0PERR V_IPRXDATA_VC0PERR(1U)
6345 #define S_IPRXHDR_VC1PERR 13
6346 #define V_IPRXHDR_VC1PERR(x) ((x) << S_IPRXHDR_VC1PERR)
6347 #define F_IPRXHDR_VC1PERR V_IPRXHDR_VC1PERR(1U)
6349 #define S_IPRXHDR_VC0PERR 12
6350 #define V_IPRXHDR_VC0PERR(x) ((x) << S_IPRXHDR_VC0PERR)
6351 #define F_IPRXHDR_VC0PERR V_IPRXHDR_VC0PERR(1U)
6353 #define S_MA_RSPDATAPERR 11
6354 #define V_MA_RSPDATAPERR(x) ((x) << S_MA_RSPDATAPERR)
6355 #define F_MA_RSPDATAPERR V_MA_RSPDATAPERR(1U)
6357 #define S_MA_CPLTAGQPERR 10
6358 #define V_MA_CPLTAGQPERR(x) ((x) << S_MA_CPLTAGQPERR)
6359 #define F_MA_CPLTAGQPERR V_MA_CPLTAGQPERR(1U)
6361 #define S_MA_REQTAGQPERR 9
6362 #define V_MA_REQTAGQPERR(x) ((x) << S_MA_REQTAGQPERR)
6363 #define F_MA_REQTAGQPERR V_MA_REQTAGQPERR(1U)
6365 #define S_PIOREQ_BAR2CTLPERR 8
6366 #define V_PIOREQ_BAR2CTLPERR(x) ((x) << S_PIOREQ_BAR2CTLPERR)
6367 #define F_PIOREQ_BAR2CTLPERR V_PIOREQ_BAR2CTLPERR(1U)
6369 #define S_PIOREQ_MEMCTLPERR 7
6370 #define V_PIOREQ_MEMCTLPERR(x) ((x) << S_PIOREQ_MEMCTLPERR)
6371 #define F_PIOREQ_MEMCTLPERR V_PIOREQ_MEMCTLPERR(1U)
6373 #define S_PIOREQ_PLMCTLPERR 6
6374 #define V_PIOREQ_PLMCTLPERR(x) ((x) << S_PIOREQ_PLMCTLPERR)
6375 #define F_PIOREQ_PLMCTLPERR V_PIOREQ_PLMCTLPERR(1U)
6377 #define S_PIOREQ_BAR2DATAPERR 5
6378 #define V_PIOREQ_BAR2DATAPERR(x) ((x) << S_PIOREQ_BAR2DATAPERR)
6379 #define F_PIOREQ_BAR2DATAPERR V_PIOREQ_BAR2DATAPERR(1U)
6381 #define S_PIOREQ_MEMDATAPERR 4
6382 #define V_PIOREQ_MEMDATAPERR(x) ((x) << S_PIOREQ_MEMDATAPERR)
6383 #define F_PIOREQ_MEMDATAPERR V_PIOREQ_MEMDATAPERR(1U)
6385 #define S_PIOREQ_PLMDATAPERR 3
6386 #define V_PIOREQ_PLMDATAPERR(x) ((x) << S_PIOREQ_PLMDATAPERR)
6387 #define F_PIOREQ_PLMDATAPERR V_PIOREQ_PLMDATAPERR(1U)
6389 #define S_PIOCPL_CTLPERR 2
6390 #define V_PIOCPL_CTLPERR(x) ((x) << S_PIOCPL_CTLPERR)
6391 #define F_PIOCPL_CTLPERR V_PIOCPL_CTLPERR(1U)
6393 #define S_PIOCPL_DATAPERR 1
6394 #define V_PIOCPL_DATAPERR(x) ((x) << S_PIOCPL_DATAPERR)
6395 #define F_PIOCPL_DATAPERR V_PIOCPL_DATAPERR(1U)
6397 #define S_PIOCPL_PLMRSPPERR 0
6398 #define V_PIOCPL_PLMRSPPERR(x) ((x) << S_PIOCPL_PLMRSPPERR)
6399 #define F_PIOCPL_PLMRSPPERR V_PIOCPL_PLMRSPPERR(1U)
6401 #define A_PCIE_CORE_GENERAL_PURPOSE_CONTROL_2 0x59d4
6402 #define A_PCIE_RSP_ERR_INT_LOG_EN 0x59d4
6404 #define S_CPLSTATUSINTEN 12
6405 #define V_CPLSTATUSINTEN(x) ((x) << S_CPLSTATUSINTEN)
6406 #define F_CPLSTATUSINTEN V_CPLSTATUSINTEN(1U)
6408 #define S_REQTIMEOUTINTEN 11
6409 #define V_REQTIMEOUTINTEN(x) ((x) << S_REQTIMEOUTINTEN)
6410 #define F_REQTIMEOUTINTEN V_REQTIMEOUTINTEN(1U)
6412 #define S_DISABLEDINTEN 10
6413 #define V_DISABLEDINTEN(x) ((x) << S_DISABLEDINTEN)
6414 #define F_DISABLEDINTEN V_DISABLEDINTEN(1U)
6416 #define S_RSPDROPFLRINTEN 9
6417 #define V_RSPDROPFLRINTEN(x) ((x) << S_RSPDROPFLRINTEN)
6418 #define F_RSPDROPFLRINTEN V_RSPDROPFLRINTEN(1U)
6420 #define S_REQUNDERFLRINTEN 8
6421 #define V_REQUNDERFLRINTEN(x) ((x) << S_REQUNDERFLRINTEN)
6422 #define F_REQUNDERFLRINTEN V_REQUNDERFLRINTEN(1U)
6424 #define S_CPLSTATUSLOGEN 4
6425 #define V_CPLSTATUSLOGEN(x) ((x) << S_CPLSTATUSLOGEN)
6426 #define F_CPLSTATUSLOGEN V_CPLSTATUSLOGEN(1U)
6428 #define S_TIMEOUTLOGEN 3
6429 #define V_TIMEOUTLOGEN(x) ((x) << S_TIMEOUTLOGEN)
6430 #define F_TIMEOUTLOGEN V_TIMEOUTLOGEN(1U)
6432 #define S_DISABLEDLOGEN 2
6433 #define V_DISABLEDLOGEN(x) ((x) << S_DISABLEDLOGEN)
6434 #define F_DISABLEDLOGEN V_DISABLEDLOGEN(1U)
6436 #define S_RSPDROPFLRLOGEN 1
6437 #define V_RSPDROPFLRLOGEN(x) ((x) << S_RSPDROPFLRLOGEN)
6438 #define F_RSPDROPFLRLOGEN V_RSPDROPFLRLOGEN(1U)
6440 #define S_REQUNDERFLRLOGEN 0
6441 #define V_REQUNDERFLRLOGEN(x) ((x) << S_REQUNDERFLRLOGEN)
6442 #define F_REQUNDERFLRLOGEN V_REQUNDERFLRLOGEN(1U)
6444 #define A_PCIE_RSP_ERR_LOG1 0x59d8
6447 #define M_REQTAG 0x7fU
6448 #define V_REQTAG(x) ((x) << S_REQTAG)
6449 #define G_REQTAG(x) (((x) >> S_REQTAG) & M_REQTAG)
6453 #define V_CID(x) ((x) << S_CID)
6454 #define G_CID(x) (((x) >> S_CID) & M_CID)
6457 #define M_CHNUM 0x7U
6458 #define V_CHNUM(x) ((x) << S_CHNUM)
6459 #define G_CHNUM(x) (((x) >> S_CHNUM) & M_CHNUM)
6462 #define M_BYTELEN 0x1fffU
6463 #define V_BYTELEN(x) ((x) << S_BYTELEN)
6464 #define G_BYTELEN(x) (((x) >> S_BYTELEN) & M_BYTELEN)
6467 #define M_REASON 0x7U
6468 #define V_REASON(x) ((x) << S_REASON)
6469 #define G_REASON(x) (((x) >> S_REASON) & M_REASON)
6471 #define S_CPLSTATUS 0
6472 #define M_CPLSTATUS 0x7U
6473 #define V_CPLSTATUS(x) ((x) << S_CPLSTATUS)
6474 #define G_CPLSTATUS(x) (((x) >> S_CPLSTATUS) & M_CPLSTATUS)
6476 #define A_PCIE_RSP_ERR_LOG2 0x59dc
6478 #define S_LOGVALID 31
6479 #define V_LOGVALID(x) ((x) << S_LOGVALID)
6480 #define F_LOGVALID V_LOGVALID(1U)
6483 #define M_ADDR10B 0x3ffU
6484 #define V_ADDR10B(x) ((x) << S_ADDR10B)
6485 #define G_ADDR10B(x) (((x) >> S_ADDR10B) & M_ADDR10B)
6488 #define M_REQVFID 0xffU
6489 #define V_REQVFID(x) ((x) << S_REQVFID)
6490 #define G_REQVFID(x) (((x) >> S_REQVFID) & M_REQVFID)
6492 #define A_PCIE_CHANGESET 0x59fc
6493 #define A_PCIE_REVISION 0x5a00
6494 #define A_PCIE_PDEBUG_INDEX 0x5a04
6496 #define S_PDEBUGSELH 16
6497 #define M_PDEBUGSELH 0x3fU
6498 #define V_PDEBUGSELH(x) ((x) << S_PDEBUGSELH)
6499 #define G_PDEBUGSELH(x) (((x) >> S_PDEBUGSELH) & M_PDEBUGSELH)
6501 #define S_PDEBUGSELL 0
6502 #define M_PDEBUGSELL 0x3fU
6503 #define V_PDEBUGSELL(x) ((x) << S_PDEBUGSELL)
6504 #define G_PDEBUGSELL(x) (((x) >> S_PDEBUGSELL) & M_PDEBUGSELL)
6506 #define A_PCIE_PDEBUG_DATA_HIGH 0x5a08
6507 #define A_PCIE_PDEBUG_DATA_LOW 0x5a0c
6508 #define A_PCIE_CDEBUG_INDEX 0x5a10
6510 #define S_CDEBUGSELH 16
6511 #define M_CDEBUGSELH 0xffU
6512 #define V_CDEBUGSELH(x) ((x) << S_CDEBUGSELH)
6513 #define G_CDEBUGSELH(x) (((x) >> S_CDEBUGSELH) & M_CDEBUGSELH)
6515 #define S_CDEBUGSELL 0
6516 #define M_CDEBUGSELL 0xffU
6517 #define V_CDEBUGSELL(x) ((x) << S_CDEBUGSELL)
6518 #define G_CDEBUGSELL(x) (((x) >> S_CDEBUGSELL) & M_CDEBUGSELL)
6520 #define A_PCIE_CDEBUG_DATA_HIGH 0x5a14
6521 #define A_PCIE_CDEBUG_DATA_LOW 0x5a18
6522 #define A_PCIE_DMAW_SOP_CNT 0x5a1c
6526 #define V_CH3(x) ((x) << S_CH3)
6527 #define G_CH3(x) (((x) >> S_CH3) & M_CH3)
6531 #define V_CH2(x) ((x) << S_CH2)
6532 #define G_CH2(x) (((x) >> S_CH2) & M_CH2)
6536 #define V_CH1(x) ((x) << S_CH1)
6537 #define G_CH1(x) (((x) >> S_CH1) & M_CH1)
6541 #define V_CH0(x) ((x) << S_CH0)
6542 #define G_CH0(x) (((x) >> S_CH0) & M_CH0)
6544 #define A_PCIE_DMAW_EOP_CNT 0x5a20
6545 #define A_PCIE_DMAR_REQ_CNT 0x5a24
6546 #define A_PCIE_DMAR_RSP_SOP_CNT 0x5a28
6547 #define A_PCIE_DMAR_RSP_EOP_CNT 0x5a2c
6548 #define A_PCIE_DMAR_RSP_ERR_CNT 0x5a30
6549 #define A_PCIE_DMAI_CNT 0x5a34
6550 #define A_PCIE_CMDW_CNT 0x5a38
6552 #define S_CH1_EOP 24
6553 #define M_CH1_EOP 0xffU
6554 #define V_CH1_EOP(x) ((x) << S_CH1_EOP)
6555 #define G_CH1_EOP(x) (((x) >> S_CH1_EOP) & M_CH1_EOP)
6557 #define S_CH1_SOP 16
6558 #define M_CH1_SOP 0xffU
6559 #define V_CH1_SOP(x) ((x) << S_CH1_SOP)
6560 #define G_CH1_SOP(x) (((x) >> S_CH1_SOP) & M_CH1_SOP)
6563 #define M_CH0_EOP 0xffU
6564 #define V_CH0_EOP(x) ((x) << S_CH0_EOP)
6565 #define G_CH0_EOP(x) (((x) >> S_CH0_EOP) & M_CH0_EOP)
6568 #define M_CH0_SOP 0xffU
6569 #define V_CH0_SOP(x) ((x) << S_CH0_SOP)
6570 #define G_CH0_SOP(x) (((x) >> S_CH0_SOP) & M_CH0_SOP)
6572 #define A_PCIE_CMDR_REQ_CNT 0x5a3c
6573 #define A_PCIE_CMDR_RSP_CNT 0x5a40
6574 #define A_PCIE_CMDR_RSP_ERR_CNT 0x5a44
6575 #define A_PCIE_HMA_REQ_CNT 0x5a48
6577 #define S_CH0_READ 16
6578 #define M_CH0_READ 0xffU
6579 #define V_CH0_READ(x) ((x) << S_CH0_READ)
6580 #define G_CH0_READ(x) (((x) >> S_CH0_READ) & M_CH0_READ)
6582 #define S_CH0_WEOP 8
6583 #define M_CH0_WEOP 0xffU
6584 #define V_CH0_WEOP(x) ((x) << S_CH0_WEOP)
6585 #define G_CH0_WEOP(x) (((x) >> S_CH0_WEOP) & M_CH0_WEOP)
6587 #define S_CH0_WSOP 0
6588 #define M_CH0_WSOP 0xffU
6589 #define V_CH0_WSOP(x) ((x) << S_CH0_WSOP)
6590 #define G_CH0_WSOP(x) (((x) >> S_CH0_WSOP) & M_CH0_WSOP)
6592 #define A_PCIE_HMA_RSP_CNT 0x5a4c
6593 #define A_PCIE_DMA10_RSP_FREE 0x5a50
6595 #define S_CH1_RSP_FREE 16
6596 #define M_CH1_RSP_FREE 0xfffU
6597 #define V_CH1_RSP_FREE(x) ((x) << S_CH1_RSP_FREE)
6598 #define G_CH1_RSP_FREE(x) (((x) >> S_CH1_RSP_FREE) & M_CH1_RSP_FREE)
6600 #define S_CH0_RSP_FREE 0
6601 #define M_CH0_RSP_FREE 0xfffU
6602 #define V_CH0_RSP_FREE(x) ((x) << S_CH0_RSP_FREE)
6603 #define G_CH0_RSP_FREE(x) (((x) >> S_CH0_RSP_FREE) & M_CH0_RSP_FREE)
6605 #define A_PCIE_DMA32_RSP_FREE 0x5a54
6607 #define S_CH3_RSP_FREE 16
6608 #define M_CH3_RSP_FREE 0xfffU
6609 #define V_CH3_RSP_FREE(x) ((x) << S_CH3_RSP_FREE)
6610 #define G_CH3_RSP_FREE(x) (((x) >> S_CH3_RSP_FREE) & M_CH3_RSP_FREE)
6612 #define S_CH2_RSP_FREE 0
6613 #define M_CH2_RSP_FREE 0xfffU
6614 #define V_CH2_RSP_FREE(x) ((x) << S_CH2_RSP_FREE)
6615 #define G_CH2_RSP_FREE(x) (((x) >> S_CH2_RSP_FREE) & M_CH2_RSP_FREE)
6617 #define A_PCIE_CMD_RSP_FREE 0x5a58
6619 #define S_CMD_CH1_RSP_FREE 16
6620 #define M_CMD_CH1_RSP_FREE 0x7fU
6621 #define V_CMD_CH1_RSP_FREE(x) ((x) << S_CMD_CH1_RSP_FREE)
6622 #define G_CMD_CH1_RSP_FREE(x) (((x) >> S_CMD_CH1_RSP_FREE) & M_CMD_CH1_RSP_FREE)
6624 #define S_CMD_CH0_RSP_FREE 0
6625 #define M_CMD_CH0_RSP_FREE 0x7fU
6626 #define V_CMD_CH0_RSP_FREE(x) ((x) << S_CMD_CH0_RSP_FREE)
6627 #define G_CMD_CH0_RSP_FREE(x) (((x) >> S_CMD_CH0_RSP_FREE) & M_CMD_CH0_RSP_FREE)
6629 #define A_PCIE_HMA_RSP_FREE 0x5a5c
6630 #define A_PCIE_BUS_MST_STAT_0 0x5a60
6631 #define A_PCIE_BUS_MST_STAT_1 0x5a64
6632 #define A_PCIE_BUS_MST_STAT_2 0x5a68
6633 #define A_PCIE_BUS_MST_STAT_3 0x5a6c
6634 #define A_PCIE_BUS_MST_STAT_4 0x5a70
6636 #define S_BUSMST_135_128 0
6637 #define M_BUSMST_135_128 0xffU
6638 #define V_BUSMST_135_128(x) ((x) << S_BUSMST_135_128)
6639 #define G_BUSMST_135_128(x) (((x) >> S_BUSMST_135_128) & M_BUSMST_135_128)
6641 #define A_PCIE_BUS_MST_STAT_5 0x5a74
6642 #define A_PCIE_BUS_MST_STAT_6 0x5a78
6643 #define A_PCIE_BUS_MST_STAT_7 0x5a7c
6644 #define A_PCIE_RSP_ERR_STAT_0 0x5a80
6645 #define A_PCIE_RSP_ERR_STAT_1 0x5a84
6646 #define A_PCIE_RSP_ERR_STAT_2 0x5a88
6647 #define A_PCIE_RSP_ERR_STAT_3 0x5a8c
6648 #define A_PCIE_RSP_ERR_STAT_4 0x5a90
6650 #define S_RSPERR_135_128 0
6651 #define M_RSPERR_135_128 0xffU
6652 #define V_RSPERR_135_128(x) ((x) << S_RSPERR_135_128)
6653 #define G_RSPERR_135_128(x) (((x) >> S_RSPERR_135_128) & M_RSPERR_135_128)
6655 #define A_PCIE_RSP_ERR_STAT_5 0x5a94
6656 #define A_PCIE_DBI_TIMEOUT_CTL 0x5a94
6658 #define S_DBI_TIMER 0
6659 #define M_DBI_TIMER 0xffffU
6660 #define V_DBI_TIMER(x) ((x) << S_DBI_TIMER)
6661 #define G_DBI_TIMER(x) (((x) >> S_DBI_TIMER) & M_DBI_TIMER)
6663 #define A_PCIE_RSP_ERR_STAT_6 0x5a98
6664 #define A_PCIE_DBI_TIMEOUT_STATUS0 0x5a98
6665 #define A_PCIE_RSP_ERR_STAT_7 0x5a9c
6666 #define A_PCIE_DBI_TIMEOUT_STATUS1 0x5a9c
6669 #define M_SOURCE 0x3U
6670 #define V_SOURCE(x) ((x) << S_SOURCE)
6671 #define G_SOURCE(x) (((x) >> S_SOURCE) & M_SOURCE)
6673 #define S_DBI_WRITE 12
6674 #define M_DBI_WRITE 0xfU
6675 #define V_DBI_WRITE(x) ((x) << S_DBI_WRITE)
6676 #define G_DBI_WRITE(x) (((x) >> S_DBI_WRITE) & M_DBI_WRITE)
6678 #define S_DBI_CS2 11
6679 #define V_DBI_CS2(x) ((x) << S_DBI_CS2)
6680 #define F_DBI_CS2 V_DBI_CS2(1U)
6683 #define M_DBI_PF 0x7U
6684 #define V_DBI_PF(x) ((x) << S_DBI_PF)
6685 #define G_DBI_PF(x) (((x) >> S_DBI_PF) & M_DBI_PF)
6687 #define S_PL_TOVFVLD 7
6688 #define V_PL_TOVFVLD(x) ((x) << S_PL_TOVFVLD)
6689 #define F_PL_TOVFVLD V_PL_TOVFVLD(1U)
6692 #define M_PL_TOVF 0x7fU
6693 #define V_PL_TOVF(x) ((x) << S_PL_TOVF)
6694 #define G_PL_TOVF(x) (((x) >> S_PL_TOVF) & M_PL_TOVF)
6696 #define A_PCIE_MSI_EN_0 0x5aa0
6697 #define A_PCIE_MSI_EN_1 0x5aa4
6698 #define A_PCIE_MSI_EN_2 0x5aa8
6699 #define A_PCIE_MSI_EN_3 0x5aac
6700 #define A_PCIE_MSI_EN_4 0x5ab0
6701 #define A_PCIE_MSI_EN_5 0x5ab4
6702 #define A_PCIE_MSI_EN_6 0x5ab8
6703 #define A_PCIE_MSI_EN_7 0x5abc
6704 #define A_PCIE_MSIX_EN_0 0x5ac0
6705 #define A_PCIE_MSIX_EN_1 0x5ac4
6706 #define A_PCIE_MSIX_EN_2 0x5ac8
6707 #define A_PCIE_MSIX_EN_3 0x5acc
6708 #define A_PCIE_MSIX_EN_4 0x5ad0
6709 #define A_PCIE_MSIX_EN_5 0x5ad4
6710 #define A_PCIE_MSIX_EN_6 0x5ad8
6711 #define A_PCIE_MSIX_EN_7 0x5adc
6712 #define A_PCIE_DMA_BUF_CTL 0x5ae0
6714 #define S_BUFRDCNT 18
6715 #define M_BUFRDCNT 0x3fffU
6716 #define V_BUFRDCNT(x) ((x) << S_BUFRDCNT)
6717 #define G_BUFRDCNT(x) (((x) >> S_BUFRDCNT) & M_BUFRDCNT)
6719 #define S_BUFWRCNT 9
6720 #define M_BUFWRCNT 0x1ffU
6721 #define V_BUFWRCNT(x) ((x) << S_BUFWRCNT)
6722 #define G_BUFWRCNT(x) (((x) >> S_BUFWRCNT) & M_BUFWRCNT)
6724 #define S_MAXBUFWRREQ 0
6725 #define M_MAXBUFWRREQ 0x1ffU
6726 #define V_MAXBUFWRREQ(x) ((x) << S_MAXBUFWRREQ)
6727 #define G_MAXBUFWRREQ(x) (((x) >> S_MAXBUFWRREQ) & M_MAXBUFWRREQ)
6729 #define A_PCIE_PB_CTL 0x5b94
6732 #define M_PB_SEL 0xffU
6733 #define V_PB_SEL(x) ((x) << S_PB_SEL)
6734 #define G_PB_SEL(x) (((x) >> S_PB_SEL) & M_PB_SEL)
6736 #define S_PB_SELREG 8
6737 #define M_PB_SELREG 0xffU
6738 #define V_PB_SELREG(x) ((x) << S_PB_SELREG)
6739 #define G_PB_SELREG(x) (((x) >> S_PB_SELREG) & M_PB_SELREG)
6742 #define M_PB_FUNC 0x7U
6743 #define V_PB_FUNC(x) ((x) << S_PB_FUNC)
6744 #define G_PB_FUNC(x) (((x) >> S_PB_FUNC) & M_PB_FUNC)
6746 #define A_PCIE_PB_DATA 0x5b98
6747 #define A_PCIE_CUR_LINK 0x5b9c
6749 #define S_CFGINITCOEFFDONESEEN 22
6750 #define V_CFGINITCOEFFDONESEEN(x) ((x) << S_CFGINITCOEFFDONESEEN)
6751 #define F_CFGINITCOEFFDONESEEN V_CFGINITCOEFFDONESEEN(1U)
6753 #define S_CFGINITCOEFFDONE 21
6754 #define V_CFGINITCOEFFDONE(x) ((x) << S_CFGINITCOEFFDONE)
6755 #define F_CFGINITCOEFFDONE V_CFGINITCOEFFDONE(1U)
6757 #define S_XMLH_LINK_UP 20
6758 #define V_XMLH_LINK_UP(x) ((x) << S_XMLH_LINK_UP)
6759 #define F_XMLH_LINK_UP V_XMLH_LINK_UP(1U)
6761 #define S_PM_LINKST_IN_L0S 19
6762 #define V_PM_LINKST_IN_L0S(x) ((x) << S_PM_LINKST_IN_L0S)
6763 #define F_PM_LINKST_IN_L0S V_PM_LINKST_IN_L0S(1U)
6765 #define S_PM_LINKST_IN_L1 18
6766 #define V_PM_LINKST_IN_L1(x) ((x) << S_PM_LINKST_IN_L1)
6767 #define F_PM_LINKST_IN_L1 V_PM_LINKST_IN_L1(1U)
6769 #define S_PM_LINKST_IN_L2 17
6770 #define V_PM_LINKST_IN_L2(x) ((x) << S_PM_LINKST_IN_L2)
6771 #define F_PM_LINKST_IN_L2 V_PM_LINKST_IN_L2(1U)
6773 #define S_PM_LINKST_L2_EXIT 16
6774 #define V_PM_LINKST_L2_EXIT(x) ((x) << S_PM_LINKST_L2_EXIT)
6775 #define F_PM_LINKST_L2_EXIT V_PM_LINKST_L2_EXIT(1U)
6777 #define S_XMLH_IN_RL0S 15
6778 #define V_XMLH_IN_RL0S(x) ((x) << S_XMLH_IN_RL0S)
6779 #define F_XMLH_IN_RL0S V_XMLH_IN_RL0S(1U)
6781 #define S_XMLH_LTSSM_STATE_RCVRY_EQ 14
6782 #define V_XMLH_LTSSM_STATE_RCVRY_EQ(x) ((x) << S_XMLH_LTSSM_STATE_RCVRY_EQ)
6783 #define F_XMLH_LTSSM_STATE_RCVRY_EQ V_XMLH_LTSSM_STATE_RCVRY_EQ(1U)
6785 #define S_NEGOTIATEDWIDTH 8
6786 #define M_NEGOTIATEDWIDTH 0x3fU
6787 #define V_NEGOTIATEDWIDTH(x) ((x) << S_NEGOTIATEDWIDTH)
6788 #define G_NEGOTIATEDWIDTH(x) (((x) >> S_NEGOTIATEDWIDTH) & M_NEGOTIATEDWIDTH)
6790 #define S_ACTIVELANES 0
6791 #define M_ACTIVELANES 0xffU
6792 #define V_ACTIVELANES(x) ((x) << S_ACTIVELANES)
6793 #define G_ACTIVELANES(x) (((x) >> S_ACTIVELANES) & M_ACTIVELANES)
6795 #define A_PCIE_PHY_REQRXPWR 0x5ba0
6797 #define S_LNH_RXSTATEDONE 31
6798 #define V_LNH_RXSTATEDONE(x) ((x) << S_LNH_RXSTATEDONE)
6799 #define F_LNH_RXSTATEDONE V_LNH_RXSTATEDONE(1U)
6801 #define S_LNH_RXSTATEREQ 30
6802 #define V_LNH_RXSTATEREQ(x) ((x) << S_LNH_RXSTATEREQ)
6803 #define F_LNH_RXSTATEREQ V_LNH_RXSTATEREQ(1U)
6805 #define S_LNH_RXPWRSTATE 28
6806 #define M_LNH_RXPWRSTATE 0x3U
6807 #define V_LNH_RXPWRSTATE(x) ((x) << S_LNH_RXPWRSTATE)
6808 #define G_LNH_RXPWRSTATE(x) (((x) >> S_LNH_RXPWRSTATE) & M_LNH_RXPWRSTATE)
6810 #define S_LNG_RXSTATEDONE 27
6811 #define V_LNG_RXSTATEDONE(x) ((x) << S_LNG_RXSTATEDONE)
6812 #define F_LNG_RXSTATEDONE V_LNG_RXSTATEDONE(1U)
6814 #define S_LNG_RXSTATEREQ 26
6815 #define V_LNG_RXSTATEREQ(x) ((x) << S_LNG_RXSTATEREQ)
6816 #define F_LNG_RXSTATEREQ V_LNG_RXSTATEREQ(1U)
6818 #define S_LNG_RXPWRSTATE 24
6819 #define M_LNG_RXPWRSTATE 0x3U
6820 #define V_LNG_RXPWRSTATE(x) ((x) << S_LNG_RXPWRSTATE)
6821 #define G_LNG_RXPWRSTATE(x) (((x) >> S_LNG_RXPWRSTATE) & M_LNG_RXPWRSTATE)
6823 #define S_LNF_RXSTATEDONE 23
6824 #define V_LNF_RXSTATEDONE(x) ((x) << S_LNF_RXSTATEDONE)
6825 #define F_LNF_RXSTATEDONE V_LNF_RXSTATEDONE(1U)
6827 #define S_LNF_RXSTATEREQ 22
6828 #define V_LNF_RXSTATEREQ(x) ((x) << S_LNF_RXSTATEREQ)
6829 #define F_LNF_RXSTATEREQ V_LNF_RXSTATEREQ(1U)
6831 #define S_LNF_RXPWRSTATE 20
6832 #define M_LNF_RXPWRSTATE 0x3U
6833 #define V_LNF_RXPWRSTATE(x) ((x) << S_LNF_RXPWRSTATE)
6834 #define G_LNF_RXPWRSTATE(x) (((x) >> S_LNF_RXPWRSTATE) & M_LNF_RXPWRSTATE)
6836 #define S_LNE_RXSTATEDONE 19
6837 #define V_LNE_RXSTATEDONE(x) ((x) << S_LNE_RXSTATEDONE)
6838 #define F_LNE_RXSTATEDONE V_LNE_RXSTATEDONE(1U)
6840 #define S_LNE_RXSTATEREQ 18
6841 #define V_LNE_RXSTATEREQ(x) ((x) << S_LNE_RXSTATEREQ)
6842 #define F_LNE_RXSTATEREQ V_LNE_RXSTATEREQ(1U)
6844 #define S_LNE_RXPWRSTATE 16
6845 #define M_LNE_RXPWRSTATE 0x3U
6846 #define V_LNE_RXPWRSTATE(x) ((x) << S_LNE_RXPWRSTATE)
6847 #define G_LNE_RXPWRSTATE(x) (((x) >> S_LNE_RXPWRSTATE) & M_LNE_RXPWRSTATE)
6849 #define S_LND_RXSTATEDONE 15
6850 #define V_LND_RXSTATEDONE(x) ((x) << S_LND_RXSTATEDONE)
6851 #define F_LND_RXSTATEDONE V_LND_RXSTATEDONE(1U)
6853 #define S_LND_RXSTATEREQ 14
6854 #define V_LND_RXSTATEREQ(x) ((x) << S_LND_RXSTATEREQ)
6855 #define F_LND_RXSTATEREQ V_LND_RXSTATEREQ(1U)
6857 #define S_LND_RXPWRSTATE 12
6858 #define M_LND_RXPWRSTATE 0x3U
6859 #define V_LND_RXPWRSTATE(x) ((x) << S_LND_RXPWRSTATE)
6860 #define G_LND_RXPWRSTATE(x) (((x) >> S_LND_RXPWRSTATE) & M_LND_RXPWRSTATE)
6862 #define S_LNC_RXSTATEDONE 11
6863 #define V_LNC_RXSTATEDONE(x) ((x) << S_LNC_RXSTATEDONE)
6864 #define F_LNC_RXSTATEDONE V_LNC_RXSTATEDONE(1U)
6866 #define S_LNC_RXSTATEREQ 10
6867 #define V_LNC_RXSTATEREQ(x) ((x) << S_LNC_RXSTATEREQ)
6868 #define F_LNC_RXSTATEREQ V_LNC_RXSTATEREQ(1U)
6870 #define S_LNC_RXPWRSTATE 8
6871 #define M_LNC_RXPWRSTATE 0x3U
6872 #define V_LNC_RXPWRSTATE(x) ((x) << S_LNC_RXPWRSTATE)
6873 #define G_LNC_RXPWRSTATE(x) (((x) >> S_LNC_RXPWRSTATE) & M_LNC_RXPWRSTATE)
6875 #define S_LNB_RXSTATEDONE 7
6876 #define V_LNB_RXSTATEDONE(x) ((x) << S_LNB_RXSTATEDONE)
6877 #define F_LNB_RXSTATEDONE V_LNB_RXSTATEDONE(1U)
6879 #define S_LNB_RXSTATEREQ 6
6880 #define V_LNB_RXSTATEREQ(x) ((x) << S_LNB_RXSTATEREQ)
6881 #define F_LNB_RXSTATEREQ V_LNB_RXSTATEREQ(1U)
6883 #define S_LNB_RXPWRSTATE 4
6884 #define M_LNB_RXPWRSTATE 0x3U
6885 #define V_LNB_RXPWRSTATE(x) ((x) << S_LNB_RXPWRSTATE)
6886 #define G_LNB_RXPWRSTATE(x) (((x) >> S_LNB_RXPWRSTATE) & M_LNB_RXPWRSTATE)
6888 #define S_LNA_RXSTATEDONE 3
6889 #define V_LNA_RXSTATEDONE(x) ((x) << S_LNA_RXSTATEDONE)
6890 #define F_LNA_RXSTATEDONE V_LNA_RXSTATEDONE(1U)
6892 #define S_LNA_RXSTATEREQ 2
6893 #define V_LNA_RXSTATEREQ(x) ((x) << S_LNA_RXSTATEREQ)
6894 #define F_LNA_RXSTATEREQ V_LNA_RXSTATEREQ(1U)
6896 #define S_LNA_RXPWRSTATE 0
6897 #define M_LNA_RXPWRSTATE 0x3U
6898 #define V_LNA_RXPWRSTATE(x) ((x) << S_LNA_RXPWRSTATE)
6899 #define G_LNA_RXPWRSTATE(x) (((x) >> S_LNA_RXPWRSTATE) & M_LNA_RXPWRSTATE)
6901 #define A_PCIE_PHY_CURRXPWR 0x5ba4
6902 #define A_PCIE_PHY_GEN3_AE0 0x5ba8
6904 #define S_LND_STAT 28
6905 #define M_LND_STAT 0x7U
6906 #define V_LND_STAT(x) ((x) << S_LND_STAT)
6907 #define G_LND_STAT(x) (((x) >> S_LND_STAT) & M_LND_STAT)
6909 #define S_LND_CMD 24
6910 #define M_LND_CMD 0x7U
6911 #define V_LND_CMD(x) ((x) << S_LND_CMD)
6912 #define G_LND_CMD(x) (((x) >> S_LND_CMD) & M_LND_CMD)
6914 #define S_LNC_STAT 20
6915 #define M_LNC_STAT 0x7U
6916 #define V_LNC_STAT(x) ((x) << S_LNC_STAT)
6917 #define G_LNC_STAT(x) (((x) >> S_LNC_STAT) & M_LNC_STAT)
6919 #define S_LNC_CMD 16
6920 #define M_LNC_CMD 0x7U
6921 #define V_LNC_CMD(x) ((x) << S_LNC_CMD)
6922 #define G_LNC_CMD(x) (((x) >> S_LNC_CMD) & M_LNC_CMD)
6924 #define S_LNB_STAT 12
6925 #define M_LNB_STAT 0x7U
6926 #define V_LNB_STAT(x) ((x) << S_LNB_STAT)
6927 #define G_LNB_STAT(x) (((x) >> S_LNB_STAT) & M_LNB_STAT)
6930 #define M_LNB_CMD 0x7U
6931 #define V_LNB_CMD(x) ((x) << S_LNB_CMD)
6932 #define G_LNB_CMD(x) (((x) >> S_LNB_CMD) & M_LNB_CMD)
6934 #define S_LNA_STAT 4
6935 #define M_LNA_STAT 0x7U
6936 #define V_LNA_STAT(x) ((x) << S_LNA_STAT)
6937 #define G_LNA_STAT(x) (((x) >> S_LNA_STAT) & M_LNA_STAT)
6940 #define M_LNA_CMD 0x7U
6941 #define V_LNA_CMD(x) ((x) << S_LNA_CMD)
6942 #define G_LNA_CMD(x) (((x) >> S_LNA_CMD) & M_LNA_CMD)
6944 #define A_PCIE_PHY_GEN3_AE1 0x5bac
6946 #define S_LNH_STAT 28
6947 #define M_LNH_STAT 0x7U
6948 #define V_LNH_STAT(x) ((x) << S_LNH_STAT)
6949 #define G_LNH_STAT(x) (((x) >> S_LNH_STAT) & M_LNH_STAT)
6951 #define S_LNH_CMD 24
6952 #define M_LNH_CMD 0x7U
6953 #define V_LNH_CMD(x) ((x) << S_LNH_CMD)
6954 #define G_LNH_CMD(x) (((x) >> S_LNH_CMD) & M_LNH_CMD)
6956 #define S_LNG_STAT 20
6957 #define M_LNG_STAT 0x7U
6958 #define V_LNG_STAT(x) ((x) << S_LNG_STAT)
6959 #define G_LNG_STAT(x) (((x) >> S_LNG_STAT) & M_LNG_STAT)
6961 #define S_LNG_CMD 16
6962 #define M_LNG_CMD 0x7U
6963 #define V_LNG_CMD(x) ((x) << S_LNG_CMD)
6964 #define G_LNG_CMD(x) (((x) >> S_LNG_CMD) & M_LNG_CMD)
6966 #define S_LNF_STAT 12
6967 #define M_LNF_STAT 0x7U
6968 #define V_LNF_STAT(x) ((x) << S_LNF_STAT)
6969 #define G_LNF_STAT(x) (((x) >> S_LNF_STAT) & M_LNF_STAT)
6972 #define M_LNF_CMD 0x7U
6973 #define V_LNF_CMD(x) ((x) << S_LNF_CMD)
6974 #define G_LNF_CMD(x) (((x) >> S_LNF_CMD) & M_LNF_CMD)
6976 #define S_LNE_STAT 4
6977 #define M_LNE_STAT 0x7U
6978 #define V_LNE_STAT(x) ((x) << S_LNE_STAT)
6979 #define G_LNE_STAT(x) (((x) >> S_LNE_STAT) & M_LNE_STAT)
6982 #define M_LNE_CMD 0x7U
6983 #define V_LNE_CMD(x) ((x) << S_LNE_CMD)
6984 #define G_LNE_CMD(x) (((x) >> S_LNE_CMD) & M_LNE_CMD)
6986 #define A_PCIE_PHY_FS_LF0 0x5bb0
6988 #define S_LANE1LF 24
6989 #define M_LANE1LF 0x3fU
6990 #define V_LANE1LF(x) ((x) << S_LANE1LF)
6991 #define G_LANE1LF(x) (((x) >> S_LANE1LF) & M_LANE1LF)
6993 #define S_LANE1FS 16
6994 #define M_LANE1FS 0x3fU
6995 #define V_LANE1FS(x) ((x) << S_LANE1FS)
6996 #define G_LANE1FS(x) (((x) >> S_LANE1FS) & M_LANE1FS)
6999 #define M_LANE0LF 0x3fU
7000 #define V_LANE0LF(x) ((x) << S_LANE0LF)
7001 #define G_LANE0LF(x) (((x) >> S_LANE0LF) & M_LANE0LF)
7004 #define M_LANE0FS 0x3fU
7005 #define V_LANE0FS(x) ((x) << S_LANE0FS)
7006 #define G_LANE0FS(x) (((x) >> S_LANE0FS) & M_LANE0FS)
7008 #define A_PCIE_PHY_FS_LF1 0x5bb4
7010 #define S_LANE3LF 24
7011 #define M_LANE3LF 0x3fU
7012 #define V_LANE3LF(x) ((x) << S_LANE3LF)
7013 #define G_LANE3LF(x) (((x) >> S_LANE3LF) & M_LANE3LF)
7015 #define S_LANE3FS 16
7016 #define M_LANE3FS 0x3fU
7017 #define V_LANE3FS(x) ((x) << S_LANE3FS)
7018 #define G_LANE3FS(x) (((x) >> S_LANE3FS) & M_LANE3FS)
7021 #define M_LANE2LF 0x3fU
7022 #define V_LANE2LF(x) ((x) << S_LANE2LF)
7023 #define G_LANE2LF(x) (((x) >> S_LANE2LF) & M_LANE2LF)
7026 #define M_LANE2FS 0x3fU
7027 #define V_LANE2FS(x) ((x) << S_LANE2FS)
7028 #define G_LANE2FS(x) (((x) >> S_LANE2FS) & M_LANE2FS)
7030 #define A_PCIE_PHY_FS_LF2 0x5bb8
7032 #define S_LANE5LF 24
7033 #define M_LANE5LF 0x3fU
7034 #define V_LANE5LF(x) ((x) << S_LANE5LF)
7035 #define G_LANE5LF(x) (((x) >> S_LANE5LF) & M_LANE5LF)
7037 #define S_LANE5FS 16
7038 #define M_LANE5FS 0x3fU
7039 #define V_LANE5FS(x) ((x) << S_LANE5FS)
7040 #define G_LANE5FS(x) (((x) >> S_LANE5FS) & M_LANE5FS)
7043 #define M_LANE4LF 0x3fU
7044 #define V_LANE4LF(x) ((x) << S_LANE4LF)
7045 #define G_LANE4LF(x) (((x) >> S_LANE4LF) & M_LANE4LF)
7048 #define M_LANE4FS 0x3fU
7049 #define V_LANE4FS(x) ((x) << S_LANE4FS)
7050 #define G_LANE4FS(x) (((x) >> S_LANE4FS) & M_LANE4FS)
7052 #define A_PCIE_PHY_FS_LF3 0x5bbc
7054 #define S_LANE7LF 24
7055 #define M_LANE7LF 0x3fU
7056 #define V_LANE7LF(x) ((x) << S_LANE7LF)
7057 #define G_LANE7LF(x) (((x) >> S_LANE7LF) & M_LANE7LF)
7059 #define S_LANE7FS 16
7060 #define M_LANE7FS 0x3fU
7061 #define V_LANE7FS(x) ((x) << S_LANE7FS)
7062 #define G_LANE7FS(x) (((x) >> S_LANE7FS) & M_LANE7FS)
7065 #define M_LANE6LF 0x3fU
7066 #define V_LANE6LF(x) ((x) << S_LANE6LF)
7067 #define G_LANE6LF(x) (((x) >> S_LANE6LF) & M_LANE6LF)
7070 #define M_LANE6FS 0x3fU
7071 #define V_LANE6FS(x) ((x) << S_LANE6FS)
7072 #define G_LANE6FS(x) (((x) >> S_LANE6FS) & M_LANE6FS)
7074 #define A_PCIE_PHY_PRESET_REQ 0x5bc0
7076 #define S_COEFFDONE 16
7077 #define V_COEFFDONE(x) ((x) << S_COEFFDONE)
7078 #define F_COEFFDONE V_COEFFDONE(1U)
7080 #define S_COEFFLANE 8
7081 #define M_COEFFLANE 0x7U
7082 #define V_COEFFLANE(x) ((x) << S_COEFFLANE)
7083 #define G_COEFFLANE(x) (((x) >> S_COEFFLANE) & M_COEFFLANE)
7085 #define S_COEFFSTART 0
7086 #define V_COEFFSTART(x) ((x) << S_COEFFSTART)
7087 #define F_COEFFSTART V_COEFFSTART(1U)
7089 #define A_PCIE_PHY_PRESET_COEFF 0x5bc4
7092 #define M_COEFF 0x3ffffU
7093 #define V_COEFF(x) ((x) << S_COEFF)
7094 #define G_COEFF(x) (((x) >> S_COEFF) & M_COEFF)
7096 #define A_PCIE_PHY_INDIR_REQ 0x5bf0
7098 #define S_PHYENABLE 31
7099 #define V_PHYENABLE(x) ((x) << S_PHYENABLE)
7100 #define F_PHYENABLE V_PHYENABLE(1U)
7102 #define S_PCIE_PHY_REGADDR 0
7103 #define M_PCIE_PHY_REGADDR 0xffffU
7104 #define V_PCIE_PHY_REGADDR(x) ((x) << S_PCIE_PHY_REGADDR)
7105 #define G_PCIE_PHY_REGADDR(x) (((x) >> S_PCIE_PHY_REGADDR) & M_PCIE_PHY_REGADDR)
7107 #define A_PCIE_PHY_INDIR_DATA 0x5bf4
7108 #define A_PCIE_STATIC_SPARE1 0x5bf8
7109 #define A_PCIE_STATIC_SPARE2 0x5bfc
7111 /* registers for module DBG */
7112 #define DBG_BASE_ADDR 0x6000
7114 #define A_DBG_DBG0_CFG 0x6000
7116 #define S_MODULESELECT 12
7117 #define M_MODULESELECT 0xffU
7118 #define V_MODULESELECT(x) ((x) << S_MODULESELECT)
7119 #define G_MODULESELECT(x) (((x) >> S_MODULESELECT) & M_MODULESELECT)
7121 #define S_REGSELECT 4
7122 #define M_REGSELECT 0xffU
7123 #define V_REGSELECT(x) ((x) << S_REGSELECT)
7124 #define G_REGSELECT(x) (((x) >> S_REGSELECT) & M_REGSELECT)
7126 #define S_CLKSELECT 0
7127 #define M_CLKSELECT 0xfU
7128 #define V_CLKSELECT(x) ((x) << S_CLKSELECT)
7129 #define G_CLKSELECT(x) (((x) >> S_CLKSELECT) & M_CLKSELECT)
7131 #define A_DBG_DBG0_EN 0x6004
7133 #define S_PORTEN_PONR 16
7134 #define V_PORTEN_PONR(x) ((x) << S_PORTEN_PONR)
7135 #define F_PORTEN_PONR V_PORTEN_PONR(1U)
7137 #define S_PORTEN_POND 12
7138 #define V_PORTEN_POND(x) ((x) << S_PORTEN_POND)
7139 #define F_PORTEN_POND V_PORTEN_POND(1U)
7141 #define S_SDRHALFWORD0 8
7142 #define V_SDRHALFWORD0(x) ((x) << S_SDRHALFWORD0)
7143 #define F_SDRHALFWORD0 V_SDRHALFWORD0(1U)
7146 #define V_DDREN(x) ((x) << S_DDREN)
7147 #define F_DDREN V_DDREN(1U)
7149 #define S_DBG_PORTEN 0
7150 #define V_DBG_PORTEN(x) ((x) << S_DBG_PORTEN)
7151 #define F_DBG_PORTEN V_DBG_PORTEN(1U)
7153 #define A_DBG_DBG1_CFG 0x6008
7154 #define A_DBG_DBG1_EN 0x600c
7156 #define S_CLK_EN_ON_DBG1 20
7157 #define V_CLK_EN_ON_DBG1(x) ((x) << S_CLK_EN_ON_DBG1)
7158 #define F_CLK_EN_ON_DBG1 V_CLK_EN_ON_DBG1(1U)
7160 #define A_DBG_GPIO_EN 0x6010
7162 #define S_GPIO15_OEN 31
7163 #define V_GPIO15_OEN(x) ((x) << S_GPIO15_OEN)
7164 #define F_GPIO15_OEN V_GPIO15_OEN(1U)
7166 #define S_GPIO14_OEN 30
7167 #define V_GPIO14_OEN(x) ((x) << S_GPIO14_OEN)
7168 #define F_GPIO14_OEN V_GPIO14_OEN(1U)
7170 #define S_GPIO13_OEN 29
7171 #define V_GPIO13_OEN(x) ((x) << S_GPIO13_OEN)
7172 #define F_GPIO13_OEN V_GPIO13_OEN(1U)
7174 #define S_GPIO12_OEN 28
7175 #define V_GPIO12_OEN(x) ((x) << S_GPIO12_OEN)
7176 #define F_GPIO12_OEN V_GPIO12_OEN(1U)
7178 #define S_GPIO11_OEN 27
7179 #define V_GPIO11_OEN(x) ((x) << S_GPIO11_OEN)
7180 #define F_GPIO11_OEN V_GPIO11_OEN(1U)
7182 #define S_GPIO10_OEN 26
7183 #define V_GPIO10_OEN(x) ((x) << S_GPIO10_OEN)
7184 #define F_GPIO10_OEN V_GPIO10_OEN(1U)
7186 #define S_GPIO9_OEN 25
7187 #define V_GPIO9_OEN(x) ((x) << S_GPIO9_OEN)
7188 #define F_GPIO9_OEN V_GPIO9_OEN(1U)
7190 #define S_GPIO8_OEN 24
7191 #define V_GPIO8_OEN(x) ((x) << S_GPIO8_OEN)
7192 #define F_GPIO8_OEN V_GPIO8_OEN(1U)
7194 #define S_GPIO7_OEN 23
7195 #define V_GPIO7_OEN(x) ((x) << S_GPIO7_OEN)
7196 #define F_GPIO7_OEN V_GPIO7_OEN(1U)
7198 #define S_GPIO6_OEN 22
7199 #define V_GPIO6_OEN(x) ((x) << S_GPIO6_OEN)
7200 #define F_GPIO6_OEN V_GPIO6_OEN(1U)
7202 #define S_GPIO5_OEN 21
7203 #define V_GPIO5_OEN(x) ((x) << S_GPIO5_OEN)
7204 #define F_GPIO5_OEN V_GPIO5_OEN(1U)
7206 #define S_GPIO4_OEN 20
7207 #define V_GPIO4_OEN(x) ((x) << S_GPIO4_OEN)
7208 #define F_GPIO4_OEN V_GPIO4_OEN(1U)
7210 #define S_GPIO3_OEN 19
7211 #define V_GPIO3_OEN(x) ((x) << S_GPIO3_OEN)
7212 #define F_GPIO3_OEN V_GPIO3_OEN(1U)
7214 #define S_GPIO2_OEN 18
7215 #define V_GPIO2_OEN(x) ((x) << S_GPIO2_OEN)
7216 #define F_GPIO2_OEN V_GPIO2_OEN(1U)
7218 #define S_GPIO1_OEN 17
7219 #define V_GPIO1_OEN(x) ((x) << S_GPIO1_OEN)
7220 #define F_GPIO1_OEN V_GPIO1_OEN(1U)
7222 #define S_GPIO0_OEN 16
7223 #define V_GPIO0_OEN(x) ((x) << S_GPIO0_OEN)
7224 #define F_GPIO0_OEN V_GPIO0_OEN(1U)
7226 #define S_GPIO15_OUT_VAL 15
7227 #define V_GPIO15_OUT_VAL(x) ((x) << S_GPIO15_OUT_VAL)
7228 #define F_GPIO15_OUT_VAL V_GPIO15_OUT_VAL(1U)
7230 #define S_GPIO14_OUT_VAL 14
7231 #define V_GPIO14_OUT_VAL(x) ((x) << S_GPIO14_OUT_VAL)
7232 #define F_GPIO14_OUT_VAL V_GPIO14_OUT_VAL(1U)
7234 #define S_GPIO13_OUT_VAL 13
7235 #define V_GPIO13_OUT_VAL(x) ((x) << S_GPIO13_OUT_VAL)
7236 #define F_GPIO13_OUT_VAL V_GPIO13_OUT_VAL(1U)
7238 #define S_GPIO12_OUT_VAL 12
7239 #define V_GPIO12_OUT_VAL(x) ((x) << S_GPIO12_OUT_VAL)
7240 #define F_GPIO12_OUT_VAL V_GPIO12_OUT_VAL(1U)
7242 #define S_GPIO11_OUT_VAL 11
7243 #define V_GPIO11_OUT_VAL(x) ((x) << S_GPIO11_OUT_VAL)
7244 #define F_GPIO11_OUT_VAL V_GPIO11_OUT_VAL(1U)
7246 #define S_GPIO10_OUT_VAL 10
7247 #define V_GPIO10_OUT_VAL(x) ((x) << S_GPIO10_OUT_VAL)
7248 #define F_GPIO10_OUT_VAL V_GPIO10_OUT_VAL(1U)
7250 #define S_GPIO9_OUT_VAL 9
7251 #define V_GPIO9_OUT_VAL(x) ((x) << S_GPIO9_OUT_VAL)
7252 #define F_GPIO9_OUT_VAL V_GPIO9_OUT_VAL(1U)
7254 #define S_GPIO8_OUT_VAL 8
7255 #define V_GPIO8_OUT_VAL(x) ((x) << S_GPIO8_OUT_VAL)
7256 #define F_GPIO8_OUT_VAL V_GPIO8_OUT_VAL(1U)
7258 #define S_GPIO7_OUT_VAL 7
7259 #define V_GPIO7_OUT_VAL(x) ((x) << S_GPIO7_OUT_VAL)
7260 #define F_GPIO7_OUT_VAL V_GPIO7_OUT_VAL(1U)
7262 #define S_GPIO6_OUT_VAL 6
7263 #define V_GPIO6_OUT_VAL(x) ((x) << S_GPIO6_OUT_VAL)
7264 #define F_GPIO6_OUT_VAL V_GPIO6_OUT_VAL(1U)
7266 #define S_GPIO5_OUT_VAL 5
7267 #define V_GPIO5_OUT_VAL(x) ((x) << S_GPIO5_OUT_VAL)
7268 #define F_GPIO5_OUT_VAL V_GPIO5_OUT_VAL(1U)
7270 #define S_GPIO4_OUT_VAL 4
7271 #define V_GPIO4_OUT_VAL(x) ((x) << S_GPIO4_OUT_VAL)
7272 #define F_GPIO4_OUT_VAL V_GPIO4_OUT_VAL(1U)
7274 #define S_GPIO3_OUT_VAL 3
7275 #define V_GPIO3_OUT_VAL(x) ((x) << S_GPIO3_OUT_VAL)
7276 #define F_GPIO3_OUT_VAL V_GPIO3_OUT_VAL(1U)
7278 #define S_GPIO2_OUT_VAL 2
7279 #define V_GPIO2_OUT_VAL(x) ((x) << S_GPIO2_OUT_VAL)
7280 #define F_GPIO2_OUT_VAL V_GPIO2_OUT_VAL(1U)
7282 #define S_GPIO1_OUT_VAL 1
7283 #define V_GPIO1_OUT_VAL(x) ((x) << S_GPIO1_OUT_VAL)
7284 #define F_GPIO1_OUT_VAL V_GPIO1_OUT_VAL(1U)
7286 #define S_GPIO0_OUT_VAL 0
7287 #define V_GPIO0_OUT_VAL(x) ((x) << S_GPIO0_OUT_VAL)
7288 #define F_GPIO0_OUT_VAL V_GPIO0_OUT_VAL(1U)
7290 #define A_DBG_GPIO_IN 0x6014
7292 #define S_GPIO15_CHG_DET 31
7293 #define V_GPIO15_CHG_DET(x) ((x) << S_GPIO15_CHG_DET)
7294 #define F_GPIO15_CHG_DET V_GPIO15_CHG_DET(1U)
7296 #define S_GPIO14_CHG_DET 30
7297 #define V_GPIO14_CHG_DET(x) ((x) << S_GPIO14_CHG_DET)
7298 #define F_GPIO14_CHG_DET V_GPIO14_CHG_DET(1U)
7300 #define S_GPIO13_CHG_DET 29
7301 #define V_GPIO13_CHG_DET(x) ((x) << S_GPIO13_CHG_DET)
7302 #define F_GPIO13_CHG_DET V_GPIO13_CHG_DET(1U)
7304 #define S_GPIO12_CHG_DET 28
7305 #define V_GPIO12_CHG_DET(x) ((x) << S_GPIO12_CHG_DET)
7306 #define F_GPIO12_CHG_DET V_GPIO12_CHG_DET(1U)
7308 #define S_GPIO11_CHG_DET 27
7309 #define V_GPIO11_CHG_DET(x) ((x) << S_GPIO11_CHG_DET)
7310 #define F_GPIO11_CHG_DET V_GPIO11_CHG_DET(1U)
7312 #define S_GPIO10_CHG_DET 26
7313 #define V_GPIO10_CHG_DET(x) ((x) << S_GPIO10_CHG_DET)
7314 #define F_GPIO10_CHG_DET V_GPIO10_CHG_DET(1U)
7316 #define S_GPIO9_CHG_DET 25
7317 #define V_GPIO9_CHG_DET(x) ((x) << S_GPIO9_CHG_DET)
7318 #define F_GPIO9_CHG_DET V_GPIO9_CHG_DET(1U)
7320 #define S_GPIO8_CHG_DET 24
7321 #define V_GPIO8_CHG_DET(x) ((x) << S_GPIO8_CHG_DET)
7322 #define F_GPIO8_CHG_DET V_GPIO8_CHG_DET(1U)
7324 #define S_GPIO7_CHG_DET 23
7325 #define V_GPIO7_CHG_DET(x) ((x) << S_GPIO7_CHG_DET)
7326 #define F_GPIO7_CHG_DET V_GPIO7_CHG_DET(1U)
7328 #define S_GPIO6_CHG_DET 22
7329 #define V_GPIO6_CHG_DET(x) ((x) << S_GPIO6_CHG_DET)
7330 #define F_GPIO6_CHG_DET V_GPIO6_CHG_DET(1U)
7332 #define S_GPIO5_CHG_DET 21
7333 #define V_GPIO5_CHG_DET(x) ((x) << S_GPIO5_CHG_DET)
7334 #define F_GPIO5_CHG_DET V_GPIO5_CHG_DET(1U)
7336 #define S_GPIO4_CHG_DET 20
7337 #define V_GPIO4_CHG_DET(x) ((x) << S_GPIO4_CHG_DET)
7338 #define F_GPIO4_CHG_DET V_GPIO4_CHG_DET(1U)
7340 #define S_GPIO3_CHG_DET 19
7341 #define V_GPIO3_CHG_DET(x) ((x) << S_GPIO3_CHG_DET)
7342 #define F_GPIO3_CHG_DET V_GPIO3_CHG_DET(1U)
7344 #define S_GPIO2_CHG_DET 18
7345 #define V_GPIO2_CHG_DET(x) ((x) << S_GPIO2_CHG_DET)
7346 #define F_GPIO2_CHG_DET V_GPIO2_CHG_DET(1U)
7348 #define S_GPIO1_CHG_DET 17
7349 #define V_GPIO1_CHG_DET(x) ((x) << S_GPIO1_CHG_DET)
7350 #define F_GPIO1_CHG_DET V_GPIO1_CHG_DET(1U)
7352 #define S_GPIO0_CHG_DET 16
7353 #define V_GPIO0_CHG_DET(x) ((x) << S_GPIO0_CHG_DET)
7354 #define F_GPIO0_CHG_DET V_GPIO0_CHG_DET(1U)
7356 #define S_GPIO15_IN 15
7357 #define V_GPIO15_IN(x) ((x) << S_GPIO15_IN)
7358 #define F_GPIO15_IN V_GPIO15_IN(1U)
7360 #define S_GPIO14_IN 14
7361 #define V_GPIO14_IN(x) ((x) << S_GPIO14_IN)
7362 #define F_GPIO14_IN V_GPIO14_IN(1U)
7364 #define S_GPIO13_IN 13
7365 #define V_GPIO13_IN(x) ((x) << S_GPIO13_IN)
7366 #define F_GPIO13_IN V_GPIO13_IN(1U)
7368 #define S_GPIO12_IN 12
7369 #define V_GPIO12_IN(x) ((x) << S_GPIO12_IN)
7370 #define F_GPIO12_IN V_GPIO12_IN(1U)
7372 #define S_GPIO11_IN 11
7373 #define V_GPIO11_IN(x) ((x) << S_GPIO11_IN)
7374 #define F_GPIO11_IN V_GPIO11_IN(1U)
7376 #define S_GPIO10_IN 10
7377 #define V_GPIO10_IN(x) ((x) << S_GPIO10_IN)
7378 #define F_GPIO10_IN V_GPIO10_IN(1U)
7380 #define S_GPIO9_IN 9
7381 #define V_GPIO9_IN(x) ((x) << S_GPIO9_IN)
7382 #define F_GPIO9_IN V_GPIO9_IN(1U)
7384 #define S_GPIO8_IN 8
7385 #define V_GPIO8_IN(x) ((x) << S_GPIO8_IN)
7386 #define F_GPIO8_IN V_GPIO8_IN(1U)
7388 #define S_GPIO7_IN 7
7389 #define V_GPIO7_IN(x) ((x) << S_GPIO7_IN)
7390 #define F_GPIO7_IN V_GPIO7_IN(1U)
7392 #define S_GPIO6_IN 6
7393 #define V_GPIO6_IN(x) ((x) << S_GPIO6_IN)
7394 #define F_GPIO6_IN V_GPIO6_IN(1U)
7396 #define S_GPIO5_IN 5
7397 #define V_GPIO5_IN(x) ((x) << S_GPIO5_IN)
7398 #define F_GPIO5_IN V_GPIO5_IN(1U)
7400 #define S_GPIO4_IN 4
7401 #define V_GPIO4_IN(x) ((x) << S_GPIO4_IN)
7402 #define F_GPIO4_IN V_GPIO4_IN(1U)
7404 #define S_GPIO3_IN 3
7405 #define V_GPIO3_IN(x) ((x) << S_GPIO3_IN)
7406 #define F_GPIO3_IN V_GPIO3_IN(1U)
7408 #define S_GPIO2_IN 2
7409 #define V_GPIO2_IN(x) ((x) << S_GPIO2_IN)
7410 #define F_GPIO2_IN V_GPIO2_IN(1U)
7412 #define S_GPIO1_IN 1
7413 #define V_GPIO1_IN(x) ((x) << S_GPIO1_IN)
7414 #define F_GPIO1_IN V_GPIO1_IN(1U)
7416 #define S_GPIO0_IN 0
7417 #define V_GPIO0_IN(x) ((x) << S_GPIO0_IN)
7418 #define F_GPIO0_IN V_GPIO0_IN(1U)
7420 #define A_DBG_INT_ENABLE 0x6018
7422 #define S_IBM_FDL_FAIL_INT_ENBL 25
7423 #define V_IBM_FDL_FAIL_INT_ENBL(x) ((x) << S_IBM_FDL_FAIL_INT_ENBL)
7424 #define F_IBM_FDL_FAIL_INT_ENBL V_IBM_FDL_FAIL_INT_ENBL(1U)
7426 #define S_ARM_FAIL_INT_ENBL 24
7427 #define V_ARM_FAIL_INT_ENBL(x) ((x) << S_ARM_FAIL_INT_ENBL)
7428 #define F_ARM_FAIL_INT_ENBL V_ARM_FAIL_INT_ENBL(1U)
7430 #define S_ARM_ERROR_OUT_INT_ENBL 23
7431 #define V_ARM_ERROR_OUT_INT_ENBL(x) ((x) << S_ARM_ERROR_OUT_INT_ENBL)
7432 #define F_ARM_ERROR_OUT_INT_ENBL V_ARM_ERROR_OUT_INT_ENBL(1U)
7434 #define S_PLL_LOCK_LOST_INT_ENBL 22
7435 #define V_PLL_LOCK_LOST_INT_ENBL(x) ((x) << S_PLL_LOCK_LOST_INT_ENBL)
7436 #define F_PLL_LOCK_LOST_INT_ENBL V_PLL_LOCK_LOST_INT_ENBL(1U)
7439 #define V_C_LOCK(x) ((x) << S_C_LOCK)
7440 #define F_C_LOCK V_C_LOCK(1U)
7443 #define V_M_LOCK(x) ((x) << S_M_LOCK)
7444 #define F_M_LOCK V_M_LOCK(1U)
7447 #define V_U_LOCK(x) ((x) << S_U_LOCK)
7448 #define F_U_LOCK V_U_LOCK(1U)
7450 #define S_PCIE_LOCK 18
7451 #define V_PCIE_LOCK(x) ((x) << S_PCIE_LOCK)
7452 #define F_PCIE_LOCK V_PCIE_LOCK(1U)
7454 #define S_KX_LOCK 17
7455 #define V_KX_LOCK(x) ((x) << S_KX_LOCK)
7456 #define F_KX_LOCK V_KX_LOCK(1U)
7458 #define S_KR_LOCK 16
7459 #define V_KR_LOCK(x) ((x) << S_KR_LOCK)
7460 #define F_KR_LOCK V_KR_LOCK(1U)
7463 #define V_GPIO15(x) ((x) << S_GPIO15)
7464 #define F_GPIO15 V_GPIO15(1U)
7467 #define V_GPIO14(x) ((x) << S_GPIO14)
7468 #define F_GPIO14 V_GPIO14(1U)
7471 #define V_GPIO13(x) ((x) << S_GPIO13)
7472 #define F_GPIO13 V_GPIO13(1U)
7475 #define V_GPIO12(x) ((x) << S_GPIO12)
7476 #define F_GPIO12 V_GPIO12(1U)
7479 #define V_GPIO11(x) ((x) << S_GPIO11)
7480 #define F_GPIO11 V_GPIO11(1U)
7483 #define V_GPIO10(x) ((x) << S_GPIO10)
7484 #define F_GPIO10 V_GPIO10(1U)
7487 #define V_GPIO9(x) ((x) << S_GPIO9)
7488 #define F_GPIO9 V_GPIO9(1U)
7491 #define V_GPIO8(x) ((x) << S_GPIO8)
7492 #define F_GPIO8 V_GPIO8(1U)
7495 #define V_GPIO7(x) ((x) << S_GPIO7)
7496 #define F_GPIO7 V_GPIO7(1U)
7499 #define V_GPIO6(x) ((x) << S_GPIO6)
7500 #define F_GPIO6 V_GPIO6(1U)
7503 #define V_GPIO5(x) ((x) << S_GPIO5)
7504 #define F_GPIO5 V_GPIO5(1U)
7507 #define V_GPIO4(x) ((x) << S_GPIO4)
7508 #define F_GPIO4 V_GPIO4(1U)
7511 #define V_GPIO3(x) ((x) << S_GPIO3)
7512 #define F_GPIO3 V_GPIO3(1U)
7515 #define V_GPIO2(x) ((x) << S_GPIO2)
7516 #define F_GPIO2 V_GPIO2(1U)
7519 #define V_GPIO1(x) ((x) << S_GPIO1)
7520 #define F_GPIO1 V_GPIO1(1U)
7523 #define V_GPIO0(x) ((x) << S_GPIO0)
7524 #define F_GPIO0 V_GPIO0(1U)
7527 #define V_GPIO19(x) ((x) << S_GPIO19)
7528 #define F_GPIO19 V_GPIO19(1U)
7531 #define V_GPIO18(x) ((x) << S_GPIO18)
7532 #define F_GPIO18 V_GPIO18(1U)
7535 #define V_GPIO17(x) ((x) << S_GPIO17)
7536 #define F_GPIO17 V_GPIO17(1U)
7539 #define V_GPIO16(x) ((x) << S_GPIO16)
7540 #define F_GPIO16 V_GPIO16(1U)
7542 #define A_DBG_INT_CAUSE 0x601c
7544 #define S_IBM_FDL_FAIL_INT_CAUSE 25
7545 #define V_IBM_FDL_FAIL_INT_CAUSE(x) ((x) << S_IBM_FDL_FAIL_INT_CAUSE)
7546 #define F_IBM_FDL_FAIL_INT_CAUSE V_IBM_FDL_FAIL_INT_CAUSE(1U)
7548 #define S_ARM_FAIL_INT_CAUSE 24
7549 #define V_ARM_FAIL_INT_CAUSE(x) ((x) << S_ARM_FAIL_INT_CAUSE)
7550 #define F_ARM_FAIL_INT_CAUSE V_ARM_FAIL_INT_CAUSE(1U)
7552 #define S_ARM_ERROR_OUT_INT_CAUSE 23
7553 #define V_ARM_ERROR_OUT_INT_CAUSE(x) ((x) << S_ARM_ERROR_OUT_INT_CAUSE)
7554 #define F_ARM_ERROR_OUT_INT_CAUSE V_ARM_ERROR_OUT_INT_CAUSE(1U)
7556 #define S_PLL_LOCK_LOST_INT_CAUSE 22
7557 #define V_PLL_LOCK_LOST_INT_CAUSE(x) ((x) << S_PLL_LOCK_LOST_INT_CAUSE)
7558 #define F_PLL_LOCK_LOST_INT_CAUSE V_PLL_LOCK_LOST_INT_CAUSE(1U)
7560 #define A_DBG_DBG0_RST_VALUE 0x6020
7562 #define S_DEBUGDATA 0
7563 #define M_DEBUGDATA 0xffffU
7564 #define V_DEBUGDATA(x) ((x) << S_DEBUGDATA)
7565 #define G_DEBUGDATA(x) (((x) >> S_DEBUGDATA) & M_DEBUGDATA)
7567 #define A_DBG_OVERWRSERCFG_EN 0x6024
7569 #define S_OVERWRSERCFG_EN 0
7570 #define V_OVERWRSERCFG_EN(x) ((x) << S_OVERWRSERCFG_EN)
7571 #define F_OVERWRSERCFG_EN V_OVERWRSERCFG_EN(1U)
7573 #define A_DBG_PLL_OCLK_PAD_EN 0x6028
7575 #define S_PCIE_OCLK_EN 20
7576 #define V_PCIE_OCLK_EN(x) ((x) << S_PCIE_OCLK_EN)
7577 #define F_PCIE_OCLK_EN V_PCIE_OCLK_EN(1U)
7579 #define S_KX_OCLK_EN 16
7580 #define V_KX_OCLK_EN(x) ((x) << S_KX_OCLK_EN)
7581 #define F_KX_OCLK_EN V_KX_OCLK_EN(1U)
7583 #define S_U_OCLK_EN 12
7584 #define V_U_OCLK_EN(x) ((x) << S_U_OCLK_EN)
7585 #define F_U_OCLK_EN V_U_OCLK_EN(1U)
7587 #define S_KR_OCLK_EN 8
7588 #define V_KR_OCLK_EN(x) ((x) << S_KR_OCLK_EN)
7589 #define F_KR_OCLK_EN V_KR_OCLK_EN(1U)
7591 #define S_M_OCLK_EN 4
7592 #define V_M_OCLK_EN(x) ((x) << S_M_OCLK_EN)
7593 #define F_M_OCLK_EN V_M_OCLK_EN(1U)
7595 #define S_C_OCLK_EN 0
7596 #define V_C_OCLK_EN(x) ((x) << S_C_OCLK_EN)
7597 #define F_C_OCLK_EN V_C_OCLK_EN(1U)
7599 #define A_DBG_PLL_LOCK 0x602c
7601 #define S_PLL_P_LOCK 20
7602 #define V_PLL_P_LOCK(x) ((x) << S_PLL_P_LOCK)
7603 #define F_PLL_P_LOCK V_PLL_P_LOCK(1U)
7605 #define S_PLL_KX_LOCK 16
7606 #define V_PLL_KX_LOCK(x) ((x) << S_PLL_KX_LOCK)
7607 #define F_PLL_KX_LOCK V_PLL_KX_LOCK(1U)
7609 #define S_PLL_U_LOCK 12
7610 #define V_PLL_U_LOCK(x) ((x) << S_PLL_U_LOCK)
7611 #define F_PLL_U_LOCK V_PLL_U_LOCK(1U)
7613 #define S_PLL_KR_LOCK 8
7614 #define V_PLL_KR_LOCK(x) ((x) << S_PLL_KR_LOCK)
7615 #define F_PLL_KR_LOCK V_PLL_KR_LOCK(1U)
7617 #define S_PLL_M_LOCK 4
7618 #define V_PLL_M_LOCK(x) ((x) << S_PLL_M_LOCK)
7619 #define F_PLL_M_LOCK V_PLL_M_LOCK(1U)
7621 #define S_PLL_C_LOCK 0
7622 #define V_PLL_C_LOCK(x) ((x) << S_PLL_C_LOCK)
7623 #define F_PLL_C_LOCK V_PLL_C_LOCK(1U)
7625 #define A_DBG_GPIO_ACT_LOW 0x6030
7627 #define S_P_LOCK_ACT_LOW 21
7628 #define V_P_LOCK_ACT_LOW(x) ((x) << S_P_LOCK_ACT_LOW)
7629 #define F_P_LOCK_ACT_LOW V_P_LOCK_ACT_LOW(1U)
7631 #define S_C_LOCK_ACT_LOW 20
7632 #define V_C_LOCK_ACT_LOW(x) ((x) << S_C_LOCK_ACT_LOW)
7633 #define F_C_LOCK_ACT_LOW V_C_LOCK_ACT_LOW(1U)
7635 #define S_M_LOCK_ACT_LOW 19
7636 #define V_M_LOCK_ACT_LOW(x) ((x) << S_M_LOCK_ACT_LOW)
7637 #define F_M_LOCK_ACT_LOW V_M_LOCK_ACT_LOW(1U)
7639 #define S_U_LOCK_ACT_LOW 18
7640 #define V_U_LOCK_ACT_LOW(x) ((x) << S_U_LOCK_ACT_LOW)
7641 #define F_U_LOCK_ACT_LOW V_U_LOCK_ACT_LOW(1U)
7643 #define S_KR_LOCK_ACT_LOW 17
7644 #define V_KR_LOCK_ACT_LOW(x) ((x) << S_KR_LOCK_ACT_LOW)
7645 #define F_KR_LOCK_ACT_LOW V_KR_LOCK_ACT_LOW(1U)
7647 #define S_KX_LOCK_ACT_LOW 16
7648 #define V_KX_LOCK_ACT_LOW(x) ((x) << S_KX_LOCK_ACT_LOW)
7649 #define F_KX_LOCK_ACT_LOW V_KX_LOCK_ACT_LOW(1U)
7651 #define S_GPIO15_ACT_LOW 15
7652 #define V_GPIO15_ACT_LOW(x) ((x) << S_GPIO15_ACT_LOW)
7653 #define F_GPIO15_ACT_LOW V_GPIO15_ACT_LOW(1U)
7655 #define S_GPIO14_ACT_LOW 14
7656 #define V_GPIO14_ACT_LOW(x) ((x) << S_GPIO14_ACT_LOW)
7657 #define F_GPIO14_ACT_LOW V_GPIO14_ACT_LOW(1U)
7659 #define S_GPIO13_ACT_LOW 13
7660 #define V_GPIO13_ACT_LOW(x) ((x) << S_GPIO13_ACT_LOW)
7661 #define F_GPIO13_ACT_LOW V_GPIO13_ACT_LOW(1U)
7663 #define S_GPIO12_ACT_LOW 12
7664 #define V_GPIO12_ACT_LOW(x) ((x) << S_GPIO12_ACT_LOW)
7665 #define F_GPIO12_ACT_LOW V_GPIO12_ACT_LOW(1U)
7667 #define S_GPIO11_ACT_LOW 11
7668 #define V_GPIO11_ACT_LOW(x) ((x) << S_GPIO11_ACT_LOW)
7669 #define F_GPIO11_ACT_LOW V_GPIO11_ACT_LOW(1U)
7671 #define S_GPIO10_ACT_LOW 10
7672 #define V_GPIO10_ACT_LOW(x) ((x) << S_GPIO10_ACT_LOW)
7673 #define F_GPIO10_ACT_LOW V_GPIO10_ACT_LOW(1U)
7675 #define S_GPIO9_ACT_LOW 9
7676 #define V_GPIO9_ACT_LOW(x) ((x) << S_GPIO9_ACT_LOW)
7677 #define F_GPIO9_ACT_LOW V_GPIO9_ACT_LOW(1U)
7679 #define S_GPIO8_ACT_LOW 8
7680 #define V_GPIO8_ACT_LOW(x) ((x) << S_GPIO8_ACT_LOW)
7681 #define F_GPIO8_ACT_LOW V_GPIO8_ACT_LOW(1U)
7683 #define S_GPIO7_ACT_LOW 7
7684 #define V_GPIO7_ACT_LOW(x) ((x) << S_GPIO7_ACT_LOW)
7685 #define F_GPIO7_ACT_LOW V_GPIO7_ACT_LOW(1U)
7687 #define S_GPIO6_ACT_LOW 6
7688 #define V_GPIO6_ACT_LOW(x) ((x) << S_GPIO6_ACT_LOW)
7689 #define F_GPIO6_ACT_LOW V_GPIO6_ACT_LOW(1U)
7691 #define S_GPIO5_ACT_LOW 5
7692 #define V_GPIO5_ACT_LOW(x) ((x) << S_GPIO5_ACT_LOW)
7693 #define F_GPIO5_ACT_LOW V_GPIO5_ACT_LOW(1U)
7695 #define S_GPIO4_ACT_LOW 4
7696 #define V_GPIO4_ACT_LOW(x) ((x) << S_GPIO4_ACT_LOW)
7697 #define F_GPIO4_ACT_LOW V_GPIO4_ACT_LOW(1U)
7699 #define S_GPIO3_ACT_LOW 3
7700 #define V_GPIO3_ACT_LOW(x) ((x) << S_GPIO3_ACT_LOW)
7701 #define F_GPIO3_ACT_LOW V_GPIO3_ACT_LOW(1U)
7703 #define S_GPIO2_ACT_LOW 2
7704 #define V_GPIO2_ACT_LOW(x) ((x) << S_GPIO2_ACT_LOW)
7705 #define F_GPIO2_ACT_LOW V_GPIO2_ACT_LOW(1U)
7707 #define S_GPIO1_ACT_LOW 1
7708 #define V_GPIO1_ACT_LOW(x) ((x) << S_GPIO1_ACT_LOW)
7709 #define F_GPIO1_ACT_LOW V_GPIO1_ACT_LOW(1U)
7711 #define S_GPIO0_ACT_LOW 0
7712 #define V_GPIO0_ACT_LOW(x) ((x) << S_GPIO0_ACT_LOW)
7713 #define F_GPIO0_ACT_LOW V_GPIO0_ACT_LOW(1U)
7715 #define S_GPIO19_ACT_LOW 25
7716 #define V_GPIO19_ACT_LOW(x) ((x) << S_GPIO19_ACT_LOW)
7717 #define F_GPIO19_ACT_LOW V_GPIO19_ACT_LOW(1U)
7719 #define S_GPIO18_ACT_LOW 24
7720 #define V_GPIO18_ACT_LOW(x) ((x) << S_GPIO18_ACT_LOW)
7721 #define F_GPIO18_ACT_LOW V_GPIO18_ACT_LOW(1U)
7723 #define S_GPIO17_ACT_LOW 23
7724 #define V_GPIO17_ACT_LOW(x) ((x) << S_GPIO17_ACT_LOW)
7725 #define F_GPIO17_ACT_LOW V_GPIO17_ACT_LOW(1U)
7727 #define S_GPIO16_ACT_LOW 22
7728 #define V_GPIO16_ACT_LOW(x) ((x) << S_GPIO16_ACT_LOW)
7729 #define F_GPIO16_ACT_LOW V_GPIO16_ACT_LOW(1U)
7731 #define A_DBG_EFUSE_BYTE0_3 0x6034
7732 #define A_DBG_EFUSE_BYTE4_7 0x6038
7733 #define A_DBG_EFUSE_BYTE8_11 0x603c
7734 #define A_DBG_EFUSE_BYTE12_15 0x6040
7735 #define A_DBG_STATIC_U_PLL_CONF 0x6044
7737 #define S_STATIC_U_PLL_MULT 23
7738 #define M_STATIC_U_PLL_MULT 0x1ffU
7739 #define V_STATIC_U_PLL_MULT(x) ((x) << S_STATIC_U_PLL_MULT)
7740 #define G_STATIC_U_PLL_MULT(x) (((x) >> S_STATIC_U_PLL_MULT) & M_STATIC_U_PLL_MULT)
7742 #define S_STATIC_U_PLL_PREDIV 18
7743 #define M_STATIC_U_PLL_PREDIV 0x1fU
7744 #define V_STATIC_U_PLL_PREDIV(x) ((x) << S_STATIC_U_PLL_PREDIV)
7745 #define G_STATIC_U_PLL_PREDIV(x) (((x) >> S_STATIC_U_PLL_PREDIV) & M_STATIC_U_PLL_PREDIV)
7747 #define S_STATIC_U_PLL_RANGEA 14
7748 #define M_STATIC_U_PLL_RANGEA 0xfU
7749 #define V_STATIC_U_PLL_RANGEA(x) ((x) << S_STATIC_U_PLL_RANGEA)
7750 #define G_STATIC_U_PLL_RANGEA(x) (((x) >> S_STATIC_U_PLL_RANGEA) & M_STATIC_U_PLL_RANGEA)
7752 #define S_STATIC_U_PLL_RANGEB 10
7753 #define M_STATIC_U_PLL_RANGEB 0xfU
7754 #define V_STATIC_U_PLL_RANGEB(x) ((x) << S_STATIC_U_PLL_RANGEB)
7755 #define G_STATIC_U_PLL_RANGEB(x) (((x) >> S_STATIC_U_PLL_RANGEB) & M_STATIC_U_PLL_RANGEB)
7757 #define S_STATIC_U_PLL_TUNE 0
7758 #define M_STATIC_U_PLL_TUNE 0x3ffU
7759 #define V_STATIC_U_PLL_TUNE(x) ((x) << S_STATIC_U_PLL_TUNE)
7760 #define G_STATIC_U_PLL_TUNE(x) (((x) >> S_STATIC_U_PLL_TUNE) & M_STATIC_U_PLL_TUNE)
7762 #define A_DBG_STATIC_C_PLL_CONF 0x6048
7764 #define S_STATIC_C_PLL_MULT 23
7765 #define M_STATIC_C_PLL_MULT 0x1ffU
7766 #define V_STATIC_C_PLL_MULT(x) ((x) << S_STATIC_C_PLL_MULT)
7767 #define G_STATIC_C_PLL_MULT(x) (((x) >> S_STATIC_C_PLL_MULT) & M_STATIC_C_PLL_MULT)
7769 #define S_STATIC_C_PLL_PREDIV 18
7770 #define M_STATIC_C_PLL_PREDIV 0x1fU
7771 #define V_STATIC_C_PLL_PREDIV(x) ((x) << S_STATIC_C_PLL_PREDIV)
7772 #define G_STATIC_C_PLL_PREDIV(x) (((x) >> S_STATIC_C_PLL_PREDIV) & M_STATIC_C_PLL_PREDIV)
7774 #define S_STATIC_C_PLL_RANGEA 14
7775 #define M_STATIC_C_PLL_RANGEA 0xfU
7776 #define V_STATIC_C_PLL_RANGEA(x) ((x) << S_STATIC_C_PLL_RANGEA)
7777 #define G_STATIC_C_PLL_RANGEA(x) (((x) >> S_STATIC_C_PLL_RANGEA) & M_STATIC_C_PLL_RANGEA)
7779 #define S_STATIC_C_PLL_RANGEB 10
7780 #define M_STATIC_C_PLL_RANGEB 0xfU
7781 #define V_STATIC_C_PLL_RANGEB(x) ((x) << S_STATIC_C_PLL_RANGEB)
7782 #define G_STATIC_C_PLL_RANGEB(x) (((x) >> S_STATIC_C_PLL_RANGEB) & M_STATIC_C_PLL_RANGEB)
7784 #define S_STATIC_C_PLL_TUNE 0
7785 #define M_STATIC_C_PLL_TUNE 0x3ffU
7786 #define V_STATIC_C_PLL_TUNE(x) ((x) << S_STATIC_C_PLL_TUNE)
7787 #define G_STATIC_C_PLL_TUNE(x) (((x) >> S_STATIC_C_PLL_TUNE) & M_STATIC_C_PLL_TUNE)
7789 #define A_DBG_STATIC_M_PLL_CONF 0x604c
7791 #define S_STATIC_M_PLL_MULT 23
7792 #define M_STATIC_M_PLL_MULT 0x1ffU
7793 #define V_STATIC_M_PLL_MULT(x) ((x) << S_STATIC_M_PLL_MULT)
7794 #define G_STATIC_M_PLL_MULT(x) (((x) >> S_STATIC_M_PLL_MULT) & M_STATIC_M_PLL_MULT)
7796 #define S_STATIC_M_PLL_PREDIV 18
7797 #define M_STATIC_M_PLL_PREDIV 0x1fU
7798 #define V_STATIC_M_PLL_PREDIV(x) ((x) << S_STATIC_M_PLL_PREDIV)
7799 #define G_STATIC_M_PLL_PREDIV(x) (((x) >> S_STATIC_M_PLL_PREDIV) & M_STATIC_M_PLL_PREDIV)
7801 #define S_STATIC_M_PLL_RANGEA 14
7802 #define M_STATIC_M_PLL_RANGEA 0xfU
7803 #define V_STATIC_M_PLL_RANGEA(x) ((x) << S_STATIC_M_PLL_RANGEA)
7804 #define G_STATIC_M_PLL_RANGEA(x) (((x) >> S_STATIC_M_PLL_RANGEA) & M_STATIC_M_PLL_RANGEA)
7806 #define S_STATIC_M_PLL_RANGEB 10
7807 #define M_STATIC_M_PLL_RANGEB 0xfU
7808 #define V_STATIC_M_PLL_RANGEB(x) ((x) << S_STATIC_M_PLL_RANGEB)
7809 #define G_STATIC_M_PLL_RANGEB(x) (((x) >> S_STATIC_M_PLL_RANGEB) & M_STATIC_M_PLL_RANGEB)
7811 #define S_STATIC_M_PLL_TUNE 0
7812 #define M_STATIC_M_PLL_TUNE 0x3ffU
7813 #define V_STATIC_M_PLL_TUNE(x) ((x) << S_STATIC_M_PLL_TUNE)
7814 #define G_STATIC_M_PLL_TUNE(x) (((x) >> S_STATIC_M_PLL_TUNE) & M_STATIC_M_PLL_TUNE)
7816 #define A_DBG_STATIC_KX_PLL_CONF 0x6050
7818 #define S_STATIC_KX_PLL_C 21
7819 #define M_STATIC_KX_PLL_C 0xffU
7820 #define V_STATIC_KX_PLL_C(x) ((x) << S_STATIC_KX_PLL_C)
7821 #define G_STATIC_KX_PLL_C(x) (((x) >> S_STATIC_KX_PLL_C) & M_STATIC_KX_PLL_C)
7823 #define S_STATIC_KX_PLL_M 15
7824 #define M_STATIC_KX_PLL_M 0x3fU
7825 #define V_STATIC_KX_PLL_M(x) ((x) << S_STATIC_KX_PLL_M)
7826 #define G_STATIC_KX_PLL_M(x) (((x) >> S_STATIC_KX_PLL_M) & M_STATIC_KX_PLL_M)
7828 #define S_STATIC_KX_PLL_N1 11
7829 #define M_STATIC_KX_PLL_N1 0xfU
7830 #define V_STATIC_KX_PLL_N1(x) ((x) << S_STATIC_KX_PLL_N1)
7831 #define G_STATIC_KX_PLL_N1(x) (((x) >> S_STATIC_KX_PLL_N1) & M_STATIC_KX_PLL_N1)
7833 #define S_STATIC_KX_PLL_N2 7
7834 #define M_STATIC_KX_PLL_N2 0xfU
7835 #define V_STATIC_KX_PLL_N2(x) ((x) << S_STATIC_KX_PLL_N2)
7836 #define G_STATIC_KX_PLL_N2(x) (((x) >> S_STATIC_KX_PLL_N2) & M_STATIC_KX_PLL_N2)
7838 #define S_STATIC_KX_PLL_N3 3
7839 #define M_STATIC_KX_PLL_N3 0xfU
7840 #define V_STATIC_KX_PLL_N3(x) ((x) << S_STATIC_KX_PLL_N3)
7841 #define G_STATIC_KX_PLL_N3(x) (((x) >> S_STATIC_KX_PLL_N3) & M_STATIC_KX_PLL_N3)
7843 #define S_STATIC_KX_PLL_P 0
7844 #define M_STATIC_KX_PLL_P 0x7U
7845 #define V_STATIC_KX_PLL_P(x) ((x) << S_STATIC_KX_PLL_P)
7846 #define G_STATIC_KX_PLL_P(x) (((x) >> S_STATIC_KX_PLL_P) & M_STATIC_KX_PLL_P)
7848 #define A_DBG_STATIC_KR_PLL_CONF 0x6054
7850 #define S_STATIC_KR_PLL_C 21
7851 #define M_STATIC_KR_PLL_C 0xffU
7852 #define V_STATIC_KR_PLL_C(x) ((x) << S_STATIC_KR_PLL_C)
7853 #define G_STATIC_KR_PLL_C(x) (((x) >> S_STATIC_KR_PLL_C) & M_STATIC_KR_PLL_C)
7855 #define S_STATIC_KR_PLL_M 15
7856 #define M_STATIC_KR_PLL_M 0x3fU
7857 #define V_STATIC_KR_PLL_M(x) ((x) << S_STATIC_KR_PLL_M)
7858 #define G_STATIC_KR_PLL_M(x) (((x) >> S_STATIC_KR_PLL_M) & M_STATIC_KR_PLL_M)
7860 #define S_STATIC_KR_PLL_N1 11
7861 #define M_STATIC_KR_PLL_N1 0xfU
7862 #define V_STATIC_KR_PLL_N1(x) ((x) << S_STATIC_KR_PLL_N1)
7863 #define G_STATIC_KR_PLL_N1(x) (((x) >> S_STATIC_KR_PLL_N1) & M_STATIC_KR_PLL_N1)
7865 #define S_STATIC_KR_PLL_N2 7
7866 #define M_STATIC_KR_PLL_N2 0xfU
7867 #define V_STATIC_KR_PLL_N2(x) ((x) << S_STATIC_KR_PLL_N2)
7868 #define G_STATIC_KR_PLL_N2(x) (((x) >> S_STATIC_KR_PLL_N2) & M_STATIC_KR_PLL_N2)
7870 #define S_STATIC_KR_PLL_N3 3
7871 #define M_STATIC_KR_PLL_N3 0xfU
7872 #define V_STATIC_KR_PLL_N3(x) ((x) << S_STATIC_KR_PLL_N3)
7873 #define G_STATIC_KR_PLL_N3(x) (((x) >> S_STATIC_KR_PLL_N3) & M_STATIC_KR_PLL_N3)
7875 #define S_STATIC_KR_PLL_P 0
7876 #define M_STATIC_KR_PLL_P 0x7U
7877 #define V_STATIC_KR_PLL_P(x) ((x) << S_STATIC_KR_PLL_P)
7878 #define G_STATIC_KR_PLL_P(x) (((x) >> S_STATIC_KR_PLL_P) & M_STATIC_KR_PLL_P)
7880 #define A_DBG_EXTRA_STATIC_BITS_CONF 0x6058
7882 #define S_STATIC_M_PLL_RESET 30
7883 #define V_STATIC_M_PLL_RESET(x) ((x) << S_STATIC_M_PLL_RESET)
7884 #define F_STATIC_M_PLL_RESET V_STATIC_M_PLL_RESET(1U)
7886 #define S_STATIC_M_PLL_SLEEP 29
7887 #define V_STATIC_M_PLL_SLEEP(x) ((x) << S_STATIC_M_PLL_SLEEP)
7888 #define F_STATIC_M_PLL_SLEEP V_STATIC_M_PLL_SLEEP(1U)
7890 #define S_STATIC_M_PLL_BYPASS 28
7891 #define V_STATIC_M_PLL_BYPASS(x) ((x) << S_STATIC_M_PLL_BYPASS)
7892 #define F_STATIC_M_PLL_BYPASS V_STATIC_M_PLL_BYPASS(1U)
7894 #define S_STATIC_MPLL_CLK_SEL 27
7895 #define V_STATIC_MPLL_CLK_SEL(x) ((x) << S_STATIC_MPLL_CLK_SEL)
7896 #define F_STATIC_MPLL_CLK_SEL V_STATIC_MPLL_CLK_SEL(1U)
7898 #define S_STATIC_U_PLL_SLEEP 26
7899 #define V_STATIC_U_PLL_SLEEP(x) ((x) << S_STATIC_U_PLL_SLEEP)
7900 #define F_STATIC_U_PLL_SLEEP V_STATIC_U_PLL_SLEEP(1U)
7902 #define S_STATIC_C_PLL_SLEEP 25
7903 #define V_STATIC_C_PLL_SLEEP(x) ((x) << S_STATIC_C_PLL_SLEEP)
7904 #define F_STATIC_C_PLL_SLEEP V_STATIC_C_PLL_SLEEP(1U)
7906 #define S_STATIC_LVDS_CLKOUT_SEL 23
7907 #define M_STATIC_LVDS_CLKOUT_SEL 0x3U
7908 #define V_STATIC_LVDS_CLKOUT_SEL(x) ((x) << S_STATIC_LVDS_CLKOUT_SEL)
7909 #define G_STATIC_LVDS_CLKOUT_SEL(x) (((x) >> S_STATIC_LVDS_CLKOUT_SEL) & M_STATIC_LVDS_CLKOUT_SEL)
7911 #define S_STATIC_LVDS_CLKOUT_EN 22
7912 #define V_STATIC_LVDS_CLKOUT_EN(x) ((x) << S_STATIC_LVDS_CLKOUT_EN)
7913 #define F_STATIC_LVDS_CLKOUT_EN V_STATIC_LVDS_CLKOUT_EN(1U)
7915 #define S_STATIC_CCLK_FREQ_SEL 20
7916 #define M_STATIC_CCLK_FREQ_SEL 0x3U
7917 #define V_STATIC_CCLK_FREQ_SEL(x) ((x) << S_STATIC_CCLK_FREQ_SEL)
7918 #define G_STATIC_CCLK_FREQ_SEL(x) (((x) >> S_STATIC_CCLK_FREQ_SEL) & M_STATIC_CCLK_FREQ_SEL)
7920 #define S_STATIC_UCLK_FREQ_SEL 18
7921 #define M_STATIC_UCLK_FREQ_SEL 0x3U
7922 #define V_STATIC_UCLK_FREQ_SEL(x) ((x) << S_STATIC_UCLK_FREQ_SEL)
7923 #define G_STATIC_UCLK_FREQ_SEL(x) (((x) >> S_STATIC_UCLK_FREQ_SEL) & M_STATIC_UCLK_FREQ_SEL)
7925 #define S_EXPHYCLK_SEL_EN 17
7926 #define V_EXPHYCLK_SEL_EN(x) ((x) << S_EXPHYCLK_SEL_EN)
7927 #define F_EXPHYCLK_SEL_EN V_EXPHYCLK_SEL_EN(1U)
7929 #define S_EXPHYCLK_SEL 15
7930 #define M_EXPHYCLK_SEL 0x3U
7931 #define V_EXPHYCLK_SEL(x) ((x) << S_EXPHYCLK_SEL)
7932 #define G_EXPHYCLK_SEL(x) (((x) >> S_EXPHYCLK_SEL) & M_EXPHYCLK_SEL)
7934 #define S_STATIC_U_PLL_BYPASS 14
7935 #define V_STATIC_U_PLL_BYPASS(x) ((x) << S_STATIC_U_PLL_BYPASS)
7936 #define F_STATIC_U_PLL_BYPASS V_STATIC_U_PLL_BYPASS(1U)
7938 #define S_STATIC_C_PLL_BYPASS 13
7939 #define V_STATIC_C_PLL_BYPASS(x) ((x) << S_STATIC_C_PLL_BYPASS)
7940 #define F_STATIC_C_PLL_BYPASS V_STATIC_C_PLL_BYPASS(1U)
7942 #define S_STATIC_KR_PLL_BYPASS 12
7943 #define V_STATIC_KR_PLL_BYPASS(x) ((x) << S_STATIC_KR_PLL_BYPASS)
7944 #define F_STATIC_KR_PLL_BYPASS V_STATIC_KR_PLL_BYPASS(1U)
7946 #define S_STATIC_KX_PLL_BYPASS 11
7947 #define V_STATIC_KX_PLL_BYPASS(x) ((x) << S_STATIC_KX_PLL_BYPASS)
7948 #define F_STATIC_KX_PLL_BYPASS V_STATIC_KX_PLL_BYPASS(1U)
7950 #define S_STATIC_KX_PLL_V 7
7951 #define M_STATIC_KX_PLL_V 0xfU
7952 #define V_STATIC_KX_PLL_V(x) ((x) << S_STATIC_KX_PLL_V)
7953 #define G_STATIC_KX_PLL_V(x) (((x) >> S_STATIC_KX_PLL_V) & M_STATIC_KX_PLL_V)
7955 #define S_STATIC_KR_PLL_V 3
7956 #define M_STATIC_KR_PLL_V 0xfU
7957 #define V_STATIC_KR_PLL_V(x) ((x) << S_STATIC_KR_PLL_V)
7958 #define G_STATIC_KR_PLL_V(x) (((x) >> S_STATIC_KR_PLL_V) & M_STATIC_KR_PLL_V)
7960 #define S_PSRO_SEL 0
7961 #define M_PSRO_SEL 0x7U
7962 #define V_PSRO_SEL(x) ((x) << S_PSRO_SEL)
7963 #define G_PSRO_SEL(x) (((x) >> S_PSRO_SEL) & M_PSRO_SEL)
7965 #define A_DBG_STATIC_OCLK_MUXSEL_CONF 0x605c
7967 #define S_M_OCLK_MUXSEL 12
7968 #define V_M_OCLK_MUXSEL(x) ((x) << S_M_OCLK_MUXSEL)
7969 #define F_M_OCLK_MUXSEL V_M_OCLK_MUXSEL(1U)
7971 #define S_C_OCLK_MUXSEL 10
7972 #define M_C_OCLK_MUXSEL 0x3U
7973 #define V_C_OCLK_MUXSEL(x) ((x) << S_C_OCLK_MUXSEL)
7974 #define G_C_OCLK_MUXSEL(x) (((x) >> S_C_OCLK_MUXSEL) & M_C_OCLK_MUXSEL)
7976 #define S_U_OCLK_MUXSEL 8
7977 #define M_U_OCLK_MUXSEL 0x3U
7978 #define V_U_OCLK_MUXSEL(x) ((x) << S_U_OCLK_MUXSEL)
7979 #define G_U_OCLK_MUXSEL(x) (((x) >> S_U_OCLK_MUXSEL) & M_U_OCLK_MUXSEL)
7981 #define S_P_OCLK_MUXSEL 6
7982 #define M_P_OCLK_MUXSEL 0x3U
7983 #define V_P_OCLK_MUXSEL(x) ((x) << S_P_OCLK_MUXSEL)
7984 #define G_P_OCLK_MUXSEL(x) (((x) >> S_P_OCLK_MUXSEL) & M_P_OCLK_MUXSEL)
7986 #define S_KX_OCLK_MUXSEL 3
7987 #define M_KX_OCLK_MUXSEL 0x7U
7988 #define V_KX_OCLK_MUXSEL(x) ((x) << S_KX_OCLK_MUXSEL)
7989 #define G_KX_OCLK_MUXSEL(x) (((x) >> S_KX_OCLK_MUXSEL) & M_KX_OCLK_MUXSEL)
7991 #define S_KR_OCLK_MUXSEL 0
7992 #define M_KR_OCLK_MUXSEL 0x7U
7993 #define V_KR_OCLK_MUXSEL(x) ((x) << S_KR_OCLK_MUXSEL)
7994 #define G_KR_OCLK_MUXSEL(x) (((x) >> S_KR_OCLK_MUXSEL) & M_KR_OCLK_MUXSEL)
7996 #define S_T5_P_OCLK_MUXSEL 13
7997 #define M_T5_P_OCLK_MUXSEL 0xfU
7998 #define V_T5_P_OCLK_MUXSEL(x) ((x) << S_T5_P_OCLK_MUXSEL)
7999 #define G_T5_P_OCLK_MUXSEL(x) (((x) >> S_T5_P_OCLK_MUXSEL) & M_T5_P_OCLK_MUXSEL)
8001 #define A_DBG_TRACE0_CONF_COMPREG0 0x6060
8002 #define A_DBG_TRACE0_CONF_COMPREG1 0x6064
8003 #define A_DBG_TRACE1_CONF_COMPREG0 0x6068
8004 #define A_DBG_TRACE1_CONF_COMPREG1 0x606c
8005 #define A_DBG_TRACE0_CONF_MASKREG0 0x6070
8006 #define A_DBG_TRACE0_CONF_MASKREG1 0x6074
8007 #define A_DBG_TRACE1_CONF_MASKREG0 0x6078
8008 #define A_DBG_TRACE1_CONF_MASKREG1 0x607c
8009 #define A_DBG_TRACE_COUNTER 0x6080
8011 #define S_COUNTER1 16
8012 #define M_COUNTER1 0xffffU
8013 #define V_COUNTER1(x) ((x) << S_COUNTER1)
8014 #define G_COUNTER1(x) (((x) >> S_COUNTER1) & M_COUNTER1)
8016 #define S_COUNTER0 0
8017 #define M_COUNTER0 0xffffU
8018 #define V_COUNTER0(x) ((x) << S_COUNTER0)
8019 #define G_COUNTER0(x) (((x) >> S_COUNTER0) & M_COUNTER0)
8021 #define A_DBG_STATIC_REFCLK_PERIOD 0x6084
8023 #define S_STATIC_REFCLK_PERIOD 0
8024 #define M_STATIC_REFCLK_PERIOD 0xffffU
8025 #define V_STATIC_REFCLK_PERIOD(x) ((x) << S_STATIC_REFCLK_PERIOD)
8026 #define G_STATIC_REFCLK_PERIOD(x) (((x) >> S_STATIC_REFCLK_PERIOD) & M_STATIC_REFCLK_PERIOD)
8028 #define A_DBG_TRACE_CONF 0x6088
8030 #define S_DBG_TRACE_OPERATE_WITH_TRG 5
8031 #define V_DBG_TRACE_OPERATE_WITH_TRG(x) ((x) << S_DBG_TRACE_OPERATE_WITH_TRG)
8032 #define F_DBG_TRACE_OPERATE_WITH_TRG V_DBG_TRACE_OPERATE_WITH_TRG(1U)
8034 #define S_DBG_TRACE_OPERATE_EN 4
8035 #define V_DBG_TRACE_OPERATE_EN(x) ((x) << S_DBG_TRACE_OPERATE_EN)
8036 #define F_DBG_TRACE_OPERATE_EN V_DBG_TRACE_OPERATE_EN(1U)
8038 #define S_DBG_OPERATE_INDV_COMBINED 3
8039 #define V_DBG_OPERATE_INDV_COMBINED(x) ((x) << S_DBG_OPERATE_INDV_COMBINED)
8040 #define F_DBG_OPERATE_INDV_COMBINED V_DBG_OPERATE_INDV_COMBINED(1U)
8042 #define S_DBG_OPERATE_ORDER_OF_TRIGGER 2
8043 #define V_DBG_OPERATE_ORDER_OF_TRIGGER(x) ((x) << S_DBG_OPERATE_ORDER_OF_TRIGGER)
8044 #define F_DBG_OPERATE_ORDER_OF_TRIGGER V_DBG_OPERATE_ORDER_OF_TRIGGER(1U)
8046 #define S_DBG_OPERATE_SGL_DBL_TRIGGER 1
8047 #define V_DBG_OPERATE_SGL_DBL_TRIGGER(x) ((x) << S_DBG_OPERATE_SGL_DBL_TRIGGER)
8048 #define F_DBG_OPERATE_SGL_DBL_TRIGGER V_DBG_OPERATE_SGL_DBL_TRIGGER(1U)
8050 #define S_DBG_OPERATE0_OR_1 0
8051 #define V_DBG_OPERATE0_OR_1(x) ((x) << S_DBG_OPERATE0_OR_1)
8052 #define F_DBG_OPERATE0_OR_1 V_DBG_OPERATE0_OR_1(1U)
8054 #define A_DBG_TRACE_RDEN 0x608c
8056 #define S_RD_ADDR1 10
8057 #define M_RD_ADDR1 0xffU
8058 #define V_RD_ADDR1(x) ((x) << S_RD_ADDR1)
8059 #define G_RD_ADDR1(x) (((x) >> S_RD_ADDR1) & M_RD_ADDR1)
8061 #define S_RD_ADDR0 2
8062 #define M_RD_ADDR0 0xffU
8063 #define V_RD_ADDR0(x) ((x) << S_RD_ADDR0)
8064 #define G_RD_ADDR0(x) (((x) >> S_RD_ADDR0) & M_RD_ADDR0)
8067 #define V_RD_EN1(x) ((x) << S_RD_EN1)
8068 #define F_RD_EN1 V_RD_EN1(1U)
8071 #define V_RD_EN0(x) ((x) << S_RD_EN0)
8072 #define F_RD_EN0 V_RD_EN0(1U)
8074 #define A_DBG_TRACE_WRADDR 0x6090
8076 #define S_WR_POINTER_ADDR1 16
8077 #define M_WR_POINTER_ADDR1 0xffU
8078 #define V_WR_POINTER_ADDR1(x) ((x) << S_WR_POINTER_ADDR1)
8079 #define G_WR_POINTER_ADDR1(x) (((x) >> S_WR_POINTER_ADDR1) & M_WR_POINTER_ADDR1)
8081 #define S_WR_POINTER_ADDR0 0
8082 #define M_WR_POINTER_ADDR0 0xffU
8083 #define V_WR_POINTER_ADDR0(x) ((x) << S_WR_POINTER_ADDR0)
8084 #define G_WR_POINTER_ADDR0(x) (((x) >> S_WR_POINTER_ADDR0) & M_WR_POINTER_ADDR0)
8086 #define A_DBG_TRACE0_DATA_OUT 0x6094
8087 #define A_DBG_TRACE1_DATA_OUT 0x6098
8088 #define A_DBG_FUSE_SENSE_DONE 0x609c
8090 #define S_STATIC_JTAG_VERSIONNR 5
8091 #define M_STATIC_JTAG_VERSIONNR 0xfU
8092 #define V_STATIC_JTAG_VERSIONNR(x) ((x) << S_STATIC_JTAG_VERSIONNR)
8093 #define G_STATIC_JTAG_VERSIONNR(x) (((x) >> S_STATIC_JTAG_VERSIONNR) & M_STATIC_JTAG_VERSIONNR)
8097 #define V_UNQ0(x) ((x) << S_UNQ0)
8098 #define G_UNQ0(x) (((x) >> S_UNQ0) & M_UNQ0)
8100 #define S_FUSE_DONE_SENSE 0
8101 #define V_FUSE_DONE_SENSE(x) ((x) << S_FUSE_DONE_SENSE)
8102 #define F_FUSE_DONE_SENSE V_FUSE_DONE_SENSE(1U)
8104 #define A_DBG_TVSENSE_EN 0x60a8
8106 #define S_MCIMPED1_OUT 29
8107 #define V_MCIMPED1_OUT(x) ((x) << S_MCIMPED1_OUT)
8108 #define F_MCIMPED1_OUT V_MCIMPED1_OUT(1U)
8110 #define S_MCIMPED2_OUT 28
8111 #define V_MCIMPED2_OUT(x) ((x) << S_MCIMPED2_OUT)
8112 #define F_MCIMPED2_OUT V_MCIMPED2_OUT(1U)
8114 #define S_TVSENSE_SNSOUT 17
8115 #define M_TVSENSE_SNSOUT 0x1ffU
8116 #define V_TVSENSE_SNSOUT(x) ((x) << S_TVSENSE_SNSOUT)
8117 #define G_TVSENSE_SNSOUT(x) (((x) >> S_TVSENSE_SNSOUT) & M_TVSENSE_SNSOUT)
8119 #define S_TVSENSE_OUTPUTVALID 16
8120 #define V_TVSENSE_OUTPUTVALID(x) ((x) << S_TVSENSE_OUTPUTVALID)
8121 #define F_TVSENSE_OUTPUTVALID V_TVSENSE_OUTPUTVALID(1U)
8123 #define S_TVSENSE_SLEEP 10
8124 #define V_TVSENSE_SLEEP(x) ((x) << S_TVSENSE_SLEEP)
8125 #define F_TVSENSE_SLEEP V_TVSENSE_SLEEP(1U)
8127 #define S_TVSENSE_SENSV 9
8128 #define V_TVSENSE_SENSV(x) ((x) << S_TVSENSE_SENSV)
8129 #define F_TVSENSE_SENSV V_TVSENSE_SENSV(1U)
8131 #define S_TVSENSE_RST 8
8132 #define V_TVSENSE_RST(x) ((x) << S_TVSENSE_RST)
8133 #define F_TVSENSE_RST V_TVSENSE_RST(1U)
8135 #define S_TVSENSE_RATIO 0
8136 #define M_TVSENSE_RATIO 0xffU
8137 #define V_TVSENSE_RATIO(x) ((x) << S_TVSENSE_RATIO)
8138 #define G_TVSENSE_RATIO(x) (((x) >> S_TVSENSE_RATIO) & M_TVSENSE_RATIO)
8140 #define A_DBG_CUST_EFUSE_OUT_EN 0x60ac
8141 #define A_DBG_CUST_EFUSE_SEL1_EN 0x60b0
8142 #define A_DBG_CUST_EFUSE_SEL2_EN 0x60b4
8144 #define S_DBG_FEENABLE 29
8145 #define V_DBG_FEENABLE(x) ((x) << S_DBG_FEENABLE)
8146 #define F_DBG_FEENABLE V_DBG_FEENABLE(1U)
8148 #define S_DBG_FEF 23
8149 #define M_DBG_FEF 0x3fU
8150 #define V_DBG_FEF(x) ((x) << S_DBG_FEF)
8151 #define G_DBG_FEF(x) (((x) >> S_DBG_FEF) & M_DBG_FEF)
8153 #define S_DBG_FEMIMICN 22
8154 #define V_DBG_FEMIMICN(x) ((x) << S_DBG_FEMIMICN)
8155 #define F_DBG_FEMIMICN V_DBG_FEMIMICN(1U)
8157 #define S_DBG_FEGATEC 21
8158 #define V_DBG_FEGATEC(x) ((x) << S_DBG_FEGATEC)
8159 #define F_DBG_FEGATEC V_DBG_FEGATEC(1U)
8161 #define S_DBG_FEPROGP 20
8162 #define V_DBG_FEPROGP(x) ((x) << S_DBG_FEPROGP)
8163 #define F_DBG_FEPROGP V_DBG_FEPROGP(1U)
8165 #define S_DBG_FEREADCLK 19
8166 #define V_DBG_FEREADCLK(x) ((x) << S_DBG_FEREADCLK)
8167 #define F_DBG_FEREADCLK V_DBG_FEREADCLK(1U)
8169 #define S_DBG_FERSEL 3
8170 #define M_DBG_FERSEL 0xffffU
8171 #define V_DBG_FERSEL(x) ((x) << S_DBG_FERSEL)
8172 #define G_DBG_FERSEL(x) (((x) >> S_DBG_FERSEL) & M_DBG_FERSEL)
8174 #define S_DBG_FETIME 0
8175 #define M_DBG_FETIME 0x7U
8176 #define V_DBG_FETIME(x) ((x) << S_DBG_FETIME)
8177 #define G_DBG_FETIME(x) (((x) >> S_DBG_FETIME) & M_DBG_FETIME)
8179 #define A_DBG_T5_STATIC_M_PLL_CONF1 0x60b8
8181 #define S_T5_STATIC_M_PLL_MULTFRAC 8
8182 #define M_T5_STATIC_M_PLL_MULTFRAC 0xffffffU
8183 #define V_T5_STATIC_M_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_M_PLL_MULTFRAC)
8184 #define G_T5_STATIC_M_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_M_PLL_MULTFRAC) & M_T5_STATIC_M_PLL_MULTFRAC)
8186 #define S_T5_STATIC_M_PLL_FFSLEWRATE 0
8187 #define M_T5_STATIC_M_PLL_FFSLEWRATE 0xffU
8188 #define V_T5_STATIC_M_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_M_PLL_FFSLEWRATE)
8189 #define G_T5_STATIC_M_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_M_PLL_FFSLEWRATE) & M_T5_STATIC_M_PLL_FFSLEWRATE)
8191 #define A_DBG_T5_STATIC_M_PLL_CONF2 0x60bc
8193 #define S_T5_STATIC_M_PLL_DCO_BYPASS 23
8194 #define V_T5_STATIC_M_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_DCO_BYPASS)
8195 #define F_T5_STATIC_M_PLL_DCO_BYPASS V_T5_STATIC_M_PLL_DCO_BYPASS(1U)
8197 #define S_T5_STATIC_M_PLL_SDORDER 21
8198 #define M_T5_STATIC_M_PLL_SDORDER 0x3U
8199 #define V_T5_STATIC_M_PLL_SDORDER(x) ((x) << S_T5_STATIC_M_PLL_SDORDER)
8200 #define G_T5_STATIC_M_PLL_SDORDER(x) (((x) >> S_T5_STATIC_M_PLL_SDORDER) & M_T5_STATIC_M_PLL_SDORDER)
8202 #define S_T5_STATIC_M_PLL_FFENABLE 20
8203 #define V_T5_STATIC_M_PLL_FFENABLE(x) ((x) << S_T5_STATIC_M_PLL_FFENABLE)
8204 #define F_T5_STATIC_M_PLL_FFENABLE V_T5_STATIC_M_PLL_FFENABLE(1U)
8206 #define S_T5_STATIC_M_PLL_STOPCLKB 19
8207 #define V_T5_STATIC_M_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKB)
8208 #define F_T5_STATIC_M_PLL_STOPCLKB V_T5_STATIC_M_PLL_STOPCLKB(1U)
8210 #define S_T5_STATIC_M_PLL_STOPCLKA 18
8211 #define V_T5_STATIC_M_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_M_PLL_STOPCLKA)
8212 #define F_T5_STATIC_M_PLL_STOPCLKA V_T5_STATIC_M_PLL_STOPCLKA(1U)
8214 #define S_T5_STATIC_M_PLL_SLEEP 17
8215 #define V_T5_STATIC_M_PLL_SLEEP(x) ((x) << S_T5_STATIC_M_PLL_SLEEP)
8216 #define F_T5_STATIC_M_PLL_SLEEP V_T5_STATIC_M_PLL_SLEEP(1U)
8218 #define S_T5_STATIC_M_PLL_BYPASS 16
8219 #define V_T5_STATIC_M_PLL_BYPASS(x) ((x) << S_T5_STATIC_M_PLL_BYPASS)
8220 #define F_T5_STATIC_M_PLL_BYPASS V_T5_STATIC_M_PLL_BYPASS(1U)
8222 #define S_T5_STATIC_M_PLL_LOCKTUNE 0
8223 #define M_T5_STATIC_M_PLL_LOCKTUNE 0xffffU
8224 #define V_T5_STATIC_M_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_M_PLL_LOCKTUNE)
8225 #define G_T5_STATIC_M_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_M_PLL_LOCKTUNE) & M_T5_STATIC_M_PLL_LOCKTUNE)
8227 #define A_DBG_T5_STATIC_M_PLL_CONF3 0x60c0
8229 #define S_T5_STATIC_M_PLL_MULTPRE 30
8230 #define M_T5_STATIC_M_PLL_MULTPRE 0x3U
8231 #define V_T5_STATIC_M_PLL_MULTPRE(x) ((x) << S_T5_STATIC_M_PLL_MULTPRE)
8232 #define G_T5_STATIC_M_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_M_PLL_MULTPRE) & M_T5_STATIC_M_PLL_MULTPRE)
8234 #define S_T5_STATIC_M_PLL_LOCKSEL 28
8235 #define M_T5_STATIC_M_PLL_LOCKSEL 0x3U
8236 #define V_T5_STATIC_M_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_M_PLL_LOCKSEL)
8237 #define G_T5_STATIC_M_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_M_PLL_LOCKSEL) & M_T5_STATIC_M_PLL_LOCKSEL)
8239 #define S_T5_STATIC_M_PLL_FFTUNE 12
8240 #define M_T5_STATIC_M_PLL_FFTUNE 0xffffU
8241 #define V_T5_STATIC_M_PLL_FFTUNE(x) ((x) << S_T5_STATIC_M_PLL_FFTUNE)
8242 #define G_T5_STATIC_M_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_M_PLL_FFTUNE) & M_T5_STATIC_M_PLL_FFTUNE)
8244 #define S_T5_STATIC_M_PLL_RANGEPRE 10
8245 #define M_T5_STATIC_M_PLL_RANGEPRE 0x3U
8246 #define V_T5_STATIC_M_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_M_PLL_RANGEPRE)
8247 #define G_T5_STATIC_M_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_M_PLL_RANGEPRE) & M_T5_STATIC_M_PLL_RANGEPRE)
8249 #define S_T5_STATIC_M_PLL_RANGEB 5
8250 #define M_T5_STATIC_M_PLL_RANGEB 0x1fU
8251 #define V_T5_STATIC_M_PLL_RANGEB(x) ((x) << S_T5_STATIC_M_PLL_RANGEB)
8252 #define G_T5_STATIC_M_PLL_RANGEB(x) (((x) >> S_T5_STATIC_M_PLL_RANGEB) & M_T5_STATIC_M_PLL_RANGEB)
8254 #define S_T5_STATIC_M_PLL_RANGEA 0
8255 #define M_T5_STATIC_M_PLL_RANGEA 0x1fU
8256 #define V_T5_STATIC_M_PLL_RANGEA(x) ((x) << S_T5_STATIC_M_PLL_RANGEA)
8257 #define G_T5_STATIC_M_PLL_RANGEA(x) (((x) >> S_T5_STATIC_M_PLL_RANGEA) & M_T5_STATIC_M_PLL_RANGEA)
8259 #define A_DBG_T5_STATIC_M_PLL_CONF4 0x60c4
8260 #define A_DBG_T5_STATIC_M_PLL_CONF5 0x60c8
8262 #define S_T5_STATIC_M_PLL_VCVTUNE 24
8263 #define M_T5_STATIC_M_PLL_VCVTUNE 0x7U
8264 #define V_T5_STATIC_M_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_M_PLL_VCVTUNE)
8265 #define G_T5_STATIC_M_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_M_PLL_VCVTUNE) & M_T5_STATIC_M_PLL_VCVTUNE)
8267 #define S_T5_STATIC_M_PLL_RESET 23
8268 #define V_T5_STATIC_M_PLL_RESET(x) ((x) << S_T5_STATIC_M_PLL_RESET)
8269 #define F_T5_STATIC_M_PLL_RESET V_T5_STATIC_M_PLL_RESET(1U)
8271 #define S_T5_STATIC_MPLL_REFCLK_SEL 22
8272 #define V_T5_STATIC_MPLL_REFCLK_SEL(x) ((x) << S_T5_STATIC_MPLL_REFCLK_SEL)
8273 #define F_T5_STATIC_MPLL_REFCLK_SEL V_T5_STATIC_MPLL_REFCLK_SEL(1U)
8275 #define S_T5_STATIC_M_PLL_LFTUNE_32_40 13
8276 #define M_T5_STATIC_M_PLL_LFTUNE_32_40 0x1ffU
8277 #define V_T5_STATIC_M_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_M_PLL_LFTUNE_32_40)
8278 #define G_T5_STATIC_M_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_M_PLL_LFTUNE_32_40) & M_T5_STATIC_M_PLL_LFTUNE_32_40)
8280 #define S_T5_STATIC_M_PLL_PREDIV 8
8281 #define M_T5_STATIC_M_PLL_PREDIV 0x1fU
8282 #define V_T5_STATIC_M_PLL_PREDIV(x) ((x) << S_T5_STATIC_M_PLL_PREDIV)
8283 #define G_T5_STATIC_M_PLL_PREDIV(x) (((x) >> S_T5_STATIC_M_PLL_PREDIV) & M_T5_STATIC_M_PLL_PREDIV)
8285 #define S_T5_STATIC_M_PLL_MULT 0
8286 #define M_T5_STATIC_M_PLL_MULT 0xffU
8287 #define V_T5_STATIC_M_PLL_MULT(x) ((x) << S_T5_STATIC_M_PLL_MULT)
8288 #define G_T5_STATIC_M_PLL_MULT(x) (((x) >> S_T5_STATIC_M_PLL_MULT) & M_T5_STATIC_M_PLL_MULT)
8290 #define A_DBG_T5_STATIC_M_PLL_CONF6 0x60cc
8292 #define S_T5_STATIC_PHY0RECRST_ 5
8293 #define V_T5_STATIC_PHY0RECRST_(x) ((x) << S_T5_STATIC_PHY0RECRST_)
8294 #define F_T5_STATIC_PHY0RECRST_ V_T5_STATIC_PHY0RECRST_(1U)
8296 #define S_T5_STATIC_PHY1RECRST_ 4
8297 #define V_T5_STATIC_PHY1RECRST_(x) ((x) << S_T5_STATIC_PHY1RECRST_)
8298 #define F_T5_STATIC_PHY1RECRST_ V_T5_STATIC_PHY1RECRST_(1U)
8300 #define S_T5_STATIC_SWMC0RST_ 3
8301 #define V_T5_STATIC_SWMC0RST_(x) ((x) << S_T5_STATIC_SWMC0RST_)
8302 #define F_T5_STATIC_SWMC0RST_ V_T5_STATIC_SWMC0RST_(1U)
8304 #define S_T5_STATIC_SWMC0CFGRST_ 2
8305 #define V_T5_STATIC_SWMC0CFGRST_(x) ((x) << S_T5_STATIC_SWMC0CFGRST_)
8306 #define F_T5_STATIC_SWMC0CFGRST_ V_T5_STATIC_SWMC0CFGRST_(1U)
8308 #define S_T5_STATIC_SWMC1RST_ 1
8309 #define V_T5_STATIC_SWMC1RST_(x) ((x) << S_T5_STATIC_SWMC1RST_)
8310 #define F_T5_STATIC_SWMC1RST_ V_T5_STATIC_SWMC1RST_(1U)
8312 #define S_T5_STATIC_SWMC1CFGRST_ 0
8313 #define V_T5_STATIC_SWMC1CFGRST_(x) ((x) << S_T5_STATIC_SWMC1CFGRST_)
8314 #define F_T5_STATIC_SWMC1CFGRST_ V_T5_STATIC_SWMC1CFGRST_(1U)
8316 #define A_DBG_T5_STATIC_C_PLL_CONF1 0x60d0
8318 #define S_T5_STATIC_C_PLL_MULTFRAC 8
8319 #define M_T5_STATIC_C_PLL_MULTFRAC 0xffffffU
8320 #define V_T5_STATIC_C_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_C_PLL_MULTFRAC)
8321 #define G_T5_STATIC_C_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_C_PLL_MULTFRAC) & M_T5_STATIC_C_PLL_MULTFRAC)
8323 #define S_T5_STATIC_C_PLL_FFSLEWRATE 0
8324 #define M_T5_STATIC_C_PLL_FFSLEWRATE 0xffU
8325 #define V_T5_STATIC_C_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_C_PLL_FFSLEWRATE)
8326 #define G_T5_STATIC_C_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_C_PLL_FFSLEWRATE) & M_T5_STATIC_C_PLL_FFSLEWRATE)
8328 #define A_DBG_T5_STATIC_C_PLL_CONF2 0x60d4
8330 #define S_T5_STATIC_C_PLL_DCO_BYPASS 23
8331 #define V_T5_STATIC_C_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_DCO_BYPASS)
8332 #define F_T5_STATIC_C_PLL_DCO_BYPASS V_T5_STATIC_C_PLL_DCO_BYPASS(1U)
8334 #define S_T5_STATIC_C_PLL_SDORDER 21
8335 #define M_T5_STATIC_C_PLL_SDORDER 0x3U
8336 #define V_T5_STATIC_C_PLL_SDORDER(x) ((x) << S_T5_STATIC_C_PLL_SDORDER)
8337 #define G_T5_STATIC_C_PLL_SDORDER(x) (((x) >> S_T5_STATIC_C_PLL_SDORDER) & M_T5_STATIC_C_PLL_SDORDER)
8339 #define S_T5_STATIC_C_PLL_FFENABLE 20
8340 #define V_T5_STATIC_C_PLL_FFENABLE(x) ((x) << S_T5_STATIC_C_PLL_FFENABLE)
8341 #define F_T5_STATIC_C_PLL_FFENABLE V_T5_STATIC_C_PLL_FFENABLE(1U)
8343 #define S_T5_STATIC_C_PLL_STOPCLKB 19
8344 #define V_T5_STATIC_C_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKB)
8345 #define F_T5_STATIC_C_PLL_STOPCLKB V_T5_STATIC_C_PLL_STOPCLKB(1U)
8347 #define S_T5_STATIC_C_PLL_STOPCLKA 18
8348 #define V_T5_STATIC_C_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_C_PLL_STOPCLKA)
8349 #define F_T5_STATIC_C_PLL_STOPCLKA V_T5_STATIC_C_PLL_STOPCLKA(1U)
8351 #define S_T5_STATIC_C_PLL_SLEEP 17
8352 #define V_T5_STATIC_C_PLL_SLEEP(x) ((x) << S_T5_STATIC_C_PLL_SLEEP)
8353 #define F_T5_STATIC_C_PLL_SLEEP V_T5_STATIC_C_PLL_SLEEP(1U)
8355 #define S_T5_STATIC_C_PLL_BYPASS 16
8356 #define V_T5_STATIC_C_PLL_BYPASS(x) ((x) << S_T5_STATIC_C_PLL_BYPASS)
8357 #define F_T5_STATIC_C_PLL_BYPASS V_T5_STATIC_C_PLL_BYPASS(1U)
8359 #define S_T5_STATIC_C_PLL_LOCKTUNE 0
8360 #define M_T5_STATIC_C_PLL_LOCKTUNE 0xffffU
8361 #define V_T5_STATIC_C_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_C_PLL_LOCKTUNE)
8362 #define G_T5_STATIC_C_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_C_PLL_LOCKTUNE) & M_T5_STATIC_C_PLL_LOCKTUNE)
8364 #define A_DBG_T5_STATIC_C_PLL_CONF3 0x60d8
8366 #define S_T5_STATIC_C_PLL_MULTPRE 30
8367 #define M_T5_STATIC_C_PLL_MULTPRE 0x3U
8368 #define V_T5_STATIC_C_PLL_MULTPRE(x) ((x) << S_T5_STATIC_C_PLL_MULTPRE)
8369 #define G_T5_STATIC_C_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_C_PLL_MULTPRE) & M_T5_STATIC_C_PLL_MULTPRE)
8371 #define S_T5_STATIC_C_PLL_LOCKSEL 28
8372 #define M_T5_STATIC_C_PLL_LOCKSEL 0x3U
8373 #define V_T5_STATIC_C_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_C_PLL_LOCKSEL)
8374 #define G_T5_STATIC_C_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_C_PLL_LOCKSEL) & M_T5_STATIC_C_PLL_LOCKSEL)
8376 #define S_T5_STATIC_C_PLL_FFTUNE 12
8377 #define M_T5_STATIC_C_PLL_FFTUNE 0xffffU
8378 #define V_T5_STATIC_C_PLL_FFTUNE(x) ((x) << S_T5_STATIC_C_PLL_FFTUNE)
8379 #define G_T5_STATIC_C_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_C_PLL_FFTUNE) & M_T5_STATIC_C_PLL_FFTUNE)
8381 #define S_T5_STATIC_C_PLL_RANGEPRE 10
8382 #define M_T5_STATIC_C_PLL_RANGEPRE 0x3U
8383 #define V_T5_STATIC_C_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_C_PLL_RANGEPRE)
8384 #define G_T5_STATIC_C_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_C_PLL_RANGEPRE) & M_T5_STATIC_C_PLL_RANGEPRE)
8386 #define S_T5_STATIC_C_PLL_RANGEB 5
8387 #define M_T5_STATIC_C_PLL_RANGEB 0x1fU
8388 #define V_T5_STATIC_C_PLL_RANGEB(x) ((x) << S_T5_STATIC_C_PLL_RANGEB)
8389 #define G_T5_STATIC_C_PLL_RANGEB(x) (((x) >> S_T5_STATIC_C_PLL_RANGEB) & M_T5_STATIC_C_PLL_RANGEB)
8391 #define S_T5_STATIC_C_PLL_RANGEA 0
8392 #define M_T5_STATIC_C_PLL_RANGEA 0x1fU
8393 #define V_T5_STATIC_C_PLL_RANGEA(x) ((x) << S_T5_STATIC_C_PLL_RANGEA)
8394 #define G_T5_STATIC_C_PLL_RANGEA(x) (((x) >> S_T5_STATIC_C_PLL_RANGEA) & M_T5_STATIC_C_PLL_RANGEA)
8396 #define A_DBG_T5_STATIC_C_PLL_CONF4 0x60dc
8397 #define A_DBG_T5_STATIC_C_PLL_CONF5 0x60e0
8399 #define S_T5_STATIC_C_PLL_VCVTUNE 22
8400 #define M_T5_STATIC_C_PLL_VCVTUNE 0x7U
8401 #define V_T5_STATIC_C_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_C_PLL_VCVTUNE)
8402 #define G_T5_STATIC_C_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_C_PLL_VCVTUNE) & M_T5_STATIC_C_PLL_VCVTUNE)
8404 #define S_T5_STATIC_C_PLL_LFTUNE_32_40 13
8405 #define M_T5_STATIC_C_PLL_LFTUNE_32_40 0x1ffU
8406 #define V_T5_STATIC_C_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_C_PLL_LFTUNE_32_40)
8407 #define G_T5_STATIC_C_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_C_PLL_LFTUNE_32_40) & M_T5_STATIC_C_PLL_LFTUNE_32_40)
8409 #define S_T5_STATIC_C_PLL_PREDIV 8
8410 #define M_T5_STATIC_C_PLL_PREDIV 0x1fU
8411 #define V_T5_STATIC_C_PLL_PREDIV(x) ((x) << S_T5_STATIC_C_PLL_PREDIV)
8412 #define G_T5_STATIC_C_PLL_PREDIV(x) (((x) >> S_T5_STATIC_C_PLL_PREDIV) & M_T5_STATIC_C_PLL_PREDIV)
8414 #define S_T5_STATIC_C_PLL_MULT 0
8415 #define M_T5_STATIC_C_PLL_MULT 0xffU
8416 #define V_T5_STATIC_C_PLL_MULT(x) ((x) << S_T5_STATIC_C_PLL_MULT)
8417 #define G_T5_STATIC_C_PLL_MULT(x) (((x) >> S_T5_STATIC_C_PLL_MULT) & M_T5_STATIC_C_PLL_MULT)
8419 #define A_DBG_T5_STATIC_U_PLL_CONF1 0x60e4
8421 #define S_T5_STATIC_U_PLL_MULTFRAC 8
8422 #define M_T5_STATIC_U_PLL_MULTFRAC 0xffffffU
8423 #define V_T5_STATIC_U_PLL_MULTFRAC(x) ((x) << S_T5_STATIC_U_PLL_MULTFRAC)
8424 #define G_T5_STATIC_U_PLL_MULTFRAC(x) (((x) >> S_T5_STATIC_U_PLL_MULTFRAC) & M_T5_STATIC_U_PLL_MULTFRAC)
8426 #define S_T5_STATIC_U_PLL_FFSLEWRATE 0
8427 #define M_T5_STATIC_U_PLL_FFSLEWRATE 0xffU
8428 #define V_T5_STATIC_U_PLL_FFSLEWRATE(x) ((x) << S_T5_STATIC_U_PLL_FFSLEWRATE)
8429 #define G_T5_STATIC_U_PLL_FFSLEWRATE(x) (((x) >> S_T5_STATIC_U_PLL_FFSLEWRATE) & M_T5_STATIC_U_PLL_FFSLEWRATE)
8431 #define A_DBG_T5_STATIC_U_PLL_CONF2 0x60e8
8433 #define S_T5_STATIC_U_PLL_DCO_BYPASS 23
8434 #define V_T5_STATIC_U_PLL_DCO_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_DCO_BYPASS)
8435 #define F_T5_STATIC_U_PLL_DCO_BYPASS V_T5_STATIC_U_PLL_DCO_BYPASS(1U)
8437 #define S_T5_STATIC_U_PLL_SDORDER 21
8438 #define M_T5_STATIC_U_PLL_SDORDER 0x3U
8439 #define V_T5_STATIC_U_PLL_SDORDER(x) ((x) << S_T5_STATIC_U_PLL_SDORDER)
8440 #define G_T5_STATIC_U_PLL_SDORDER(x) (((x) >> S_T5_STATIC_U_PLL_SDORDER) & M_T5_STATIC_U_PLL_SDORDER)
8442 #define S_T5_STATIC_U_PLL_FFENABLE 20
8443 #define V_T5_STATIC_U_PLL_FFENABLE(x) ((x) << S_T5_STATIC_U_PLL_FFENABLE)
8444 #define F_T5_STATIC_U_PLL_FFENABLE V_T5_STATIC_U_PLL_FFENABLE(1U)
8446 #define S_T5_STATIC_U_PLL_STOPCLKB 19
8447 #define V_T5_STATIC_U_PLL_STOPCLKB(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKB)
8448 #define F_T5_STATIC_U_PLL_STOPCLKB V_T5_STATIC_U_PLL_STOPCLKB(1U)
8450 #define S_T5_STATIC_U_PLL_STOPCLKA 18
8451 #define V_T5_STATIC_U_PLL_STOPCLKA(x) ((x) << S_T5_STATIC_U_PLL_STOPCLKA)
8452 #define F_T5_STATIC_U_PLL_STOPCLKA V_T5_STATIC_U_PLL_STOPCLKA(1U)
8454 #define S_T5_STATIC_U_PLL_SLEEP 17
8455 #define V_T5_STATIC_U_PLL_SLEEP(x) ((x) << S_T5_STATIC_U_PLL_SLEEP)
8456 #define F_T5_STATIC_U_PLL_SLEEP V_T5_STATIC_U_PLL_SLEEP(1U)
8458 #define S_T5_STATIC_U_PLL_BYPASS 16
8459 #define V_T5_STATIC_U_PLL_BYPASS(x) ((x) << S_T5_STATIC_U_PLL_BYPASS)
8460 #define F_T5_STATIC_U_PLL_BYPASS V_T5_STATIC_U_PLL_BYPASS(1U)
8462 #define S_T5_STATIC_U_PLL_LOCKTUNE 0
8463 #define M_T5_STATIC_U_PLL_LOCKTUNE 0xffffU
8464 #define V_T5_STATIC_U_PLL_LOCKTUNE(x) ((x) << S_T5_STATIC_U_PLL_LOCKTUNE)
8465 #define G_T5_STATIC_U_PLL_LOCKTUNE(x) (((x) >> S_T5_STATIC_U_PLL_LOCKTUNE) & M_T5_STATIC_U_PLL_LOCKTUNE)
8467 #define A_DBG_T5_STATIC_U_PLL_CONF3 0x60ec
8469 #define S_T5_STATIC_U_PLL_MULTPRE 30
8470 #define M_T5_STATIC_U_PLL_MULTPRE 0x3U
8471 #define V_T5_STATIC_U_PLL_MULTPRE(x) ((x) << S_T5_STATIC_U_PLL_MULTPRE)
8472 #define G_T5_STATIC_U_PLL_MULTPRE(x) (((x) >> S_T5_STATIC_U_PLL_MULTPRE) & M_T5_STATIC_U_PLL_MULTPRE)
8474 #define S_T5_STATIC_U_PLL_LOCKSEL 28
8475 #define M_T5_STATIC_U_PLL_LOCKSEL 0x3U
8476 #define V_T5_STATIC_U_PLL_LOCKSEL(x) ((x) << S_T5_STATIC_U_PLL_LOCKSEL)
8477 #define G_T5_STATIC_U_PLL_LOCKSEL(x) (((x) >> S_T5_STATIC_U_PLL_LOCKSEL) & M_T5_STATIC_U_PLL_LOCKSEL)
8479 #define S_T5_STATIC_U_PLL_FFTUNE 12
8480 #define M_T5_STATIC_U_PLL_FFTUNE 0xffffU
8481 #define V_T5_STATIC_U_PLL_FFTUNE(x) ((x) << S_T5_STATIC_U_PLL_FFTUNE)
8482 #define G_T5_STATIC_U_PLL_FFTUNE(x) (((x) >> S_T5_STATIC_U_PLL_FFTUNE) & M_T5_STATIC_U_PLL_FFTUNE)
8484 #define S_T5_STATIC_U_PLL_RANGEPRE 10
8485 #define M_T5_STATIC_U_PLL_RANGEPRE 0x3U
8486 #define V_T5_STATIC_U_PLL_RANGEPRE(x) ((x) << S_T5_STATIC_U_PLL_RANGEPRE)
8487 #define G_T5_STATIC_U_PLL_RANGEPRE(x) (((x) >> S_T5_STATIC_U_PLL_RANGEPRE) & M_T5_STATIC_U_PLL_RANGEPRE)
8489 #define S_T5_STATIC_U_PLL_RANGEB 5
8490 #define M_T5_STATIC_U_PLL_RANGEB 0x1fU
8491 #define V_T5_STATIC_U_PLL_RANGEB(x) ((x) << S_T5_STATIC_U_PLL_RANGEB)
8492 #define G_T5_STATIC_U_PLL_RANGEB(x) (((x) >> S_T5_STATIC_U_PLL_RANGEB) & M_T5_STATIC_U_PLL_RANGEB)
8494 #define S_T5_STATIC_U_PLL_RANGEA 0
8495 #define M_T5_STATIC_U_PLL_RANGEA 0x1fU
8496 #define V_T5_STATIC_U_PLL_RANGEA(x) ((x) << S_T5_STATIC_U_PLL_RANGEA)
8497 #define G_T5_STATIC_U_PLL_RANGEA(x) (((x) >> S_T5_STATIC_U_PLL_RANGEA) & M_T5_STATIC_U_PLL_RANGEA)
8499 #define A_DBG_T5_STATIC_U_PLL_CONF4 0x60f0
8500 #define A_DBG_T5_STATIC_U_PLL_CONF5 0x60f4
8502 #define S_T5_STATIC_U_PLL_VCVTUNE 22
8503 #define M_T5_STATIC_U_PLL_VCVTUNE 0x7U
8504 #define V_T5_STATIC_U_PLL_VCVTUNE(x) ((x) << S_T5_STATIC_U_PLL_VCVTUNE)
8505 #define G_T5_STATIC_U_PLL_VCVTUNE(x) (((x) >> S_T5_STATIC_U_PLL_VCVTUNE) & M_T5_STATIC_U_PLL_VCVTUNE)
8507 #define S_T5_STATIC_U_PLL_LFTUNE_32_40 13
8508 #define M_T5_STATIC_U_PLL_LFTUNE_32_40 0x1ffU
8509 #define V_T5_STATIC_U_PLL_LFTUNE_32_40(x) ((x) << S_T5_STATIC_U_PLL_LFTUNE_32_40)
8510 #define G_T5_STATIC_U_PLL_LFTUNE_32_40(x) (((x) >> S_T5_STATIC_U_PLL_LFTUNE_32_40) & M_T5_STATIC_U_PLL_LFTUNE_32_40)
8512 #define S_T5_STATIC_U_PLL_PREDIV 8
8513 #define M_T5_STATIC_U_PLL_PREDIV 0x1fU
8514 #define V_T5_STATIC_U_PLL_PREDIV(x) ((x) << S_T5_STATIC_U_PLL_PREDIV)
8515 #define G_T5_STATIC_U_PLL_PREDIV(x) (((x) >> S_T5_STATIC_U_PLL_PREDIV) & M_T5_STATIC_U_PLL_PREDIV)
8517 #define S_T5_STATIC_U_PLL_MULT 0
8518 #define M_T5_STATIC_U_PLL_MULT 0xffU
8519 #define V_T5_STATIC_U_PLL_MULT(x) ((x) << S_T5_STATIC_U_PLL_MULT)
8520 #define G_T5_STATIC_U_PLL_MULT(x) (((x) >> S_T5_STATIC_U_PLL_MULT) & M_T5_STATIC_U_PLL_MULT)
8522 #define A_DBG_T5_STATIC_KR_PLL_CONF1 0x60f8
8524 #define S_T5_STATIC_KR_PLL_BYPASS 30
8525 #define V_T5_STATIC_KR_PLL_BYPASS(x) ((x) << S_T5_STATIC_KR_PLL_BYPASS)
8526 #define F_T5_STATIC_KR_PLL_BYPASS V_T5_STATIC_KR_PLL_BYPASS(1U)
8528 #define S_T5_STATIC_KR_PLL_VBOOSTDIV 27
8529 #define M_T5_STATIC_KR_PLL_VBOOSTDIV 0x7U
8530 #define V_T5_STATIC_KR_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KR_PLL_VBOOSTDIV)
8531 #define G_T5_STATIC_KR_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KR_PLL_VBOOSTDIV) & M_T5_STATIC_KR_PLL_VBOOSTDIV)
8533 #define S_T5_STATIC_KR_PLL_CPISEL 24
8534 #define M_T5_STATIC_KR_PLL_CPISEL 0x7U
8535 #define V_T5_STATIC_KR_PLL_CPISEL(x) ((x) << S_T5_STATIC_KR_PLL_CPISEL)
8536 #define G_T5_STATIC_KR_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KR_PLL_CPISEL) & M_T5_STATIC_KR_PLL_CPISEL)
8538 #define S_T5_STATIC_KR_PLL_CCALMETHOD 23
8539 #define V_T5_STATIC_KR_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KR_PLL_CCALMETHOD)
8540 #define F_T5_STATIC_KR_PLL_CCALMETHOD V_T5_STATIC_KR_PLL_CCALMETHOD(1U)
8542 #define S_T5_STATIC_KR_PLL_CCALLOAD 22
8543 #define V_T5_STATIC_KR_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KR_PLL_CCALLOAD)
8544 #define F_T5_STATIC_KR_PLL_CCALLOAD V_T5_STATIC_KR_PLL_CCALLOAD(1U)
8546 #define S_T5_STATIC_KR_PLL_CCALFMIN 21
8547 #define V_T5_STATIC_KR_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMIN)
8548 #define F_T5_STATIC_KR_PLL_CCALFMIN V_T5_STATIC_KR_PLL_CCALFMIN(1U)
8550 #define S_T5_STATIC_KR_PLL_CCALFMAX 20
8551 #define V_T5_STATIC_KR_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KR_PLL_CCALFMAX)
8552 #define F_T5_STATIC_KR_PLL_CCALFMAX V_T5_STATIC_KR_PLL_CCALFMAX(1U)
8554 #define S_T5_STATIC_KR_PLL_CCALCVHOLD 19
8555 #define V_T5_STATIC_KR_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KR_PLL_CCALCVHOLD)
8556 #define F_T5_STATIC_KR_PLL_CCALCVHOLD V_T5_STATIC_KR_PLL_CCALCVHOLD(1U)
8558 #define S_T5_STATIC_KR_PLL_CCALBANDSEL 15
8559 #define M_T5_STATIC_KR_PLL_CCALBANDSEL 0xfU
8560 #define V_T5_STATIC_KR_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KR_PLL_CCALBANDSEL)
8561 #define G_T5_STATIC_KR_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KR_PLL_CCALBANDSEL) & M_T5_STATIC_KR_PLL_CCALBANDSEL)
8563 #define S_T5_STATIC_KR_PLL_BGOFFSET 11
8564 #define M_T5_STATIC_KR_PLL_BGOFFSET 0xfU
8565 #define V_T5_STATIC_KR_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KR_PLL_BGOFFSET)
8566 #define G_T5_STATIC_KR_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KR_PLL_BGOFFSET) & M_T5_STATIC_KR_PLL_BGOFFSET)
8568 #define S_T5_STATIC_KR_PLL_P 8
8569 #define M_T5_STATIC_KR_PLL_P 0x7U
8570 #define V_T5_STATIC_KR_PLL_P(x) ((x) << S_T5_STATIC_KR_PLL_P)
8571 #define G_T5_STATIC_KR_PLL_P(x) (((x) >> S_T5_STATIC_KR_PLL_P) & M_T5_STATIC_KR_PLL_P)
8573 #define S_T5_STATIC_KR_PLL_N2 4
8574 #define M_T5_STATIC_KR_PLL_N2 0xfU
8575 #define V_T5_STATIC_KR_PLL_N2(x) ((x) << S_T5_STATIC_KR_PLL_N2)
8576 #define G_T5_STATIC_KR_PLL_N2(x) (((x) >> S_T5_STATIC_KR_PLL_N2) & M_T5_STATIC_KR_PLL_N2)
8578 #define S_T5_STATIC_KR_PLL_N1 0
8579 #define M_T5_STATIC_KR_PLL_N1 0xfU
8580 #define V_T5_STATIC_KR_PLL_N1(x) ((x) << S_T5_STATIC_KR_PLL_N1)
8581 #define G_T5_STATIC_KR_PLL_N1(x) (((x) >> S_T5_STATIC_KR_PLL_N1) & M_T5_STATIC_KR_PLL_N1)
8583 #define A_DBG_T5_STATIC_KR_PLL_CONF2 0x60fc
8585 #define S_T5_STATIC_KR_PLL_M 11
8586 #define M_T5_STATIC_KR_PLL_M 0x1ffU
8587 #define V_T5_STATIC_KR_PLL_M(x) ((x) << S_T5_STATIC_KR_PLL_M)
8588 #define G_T5_STATIC_KR_PLL_M(x) (((x) >> S_T5_STATIC_KR_PLL_M) & M_T5_STATIC_KR_PLL_M)
8590 #define S_T5_STATIC_KR_PLL_ANALOGTUNE 0
8591 #define M_T5_STATIC_KR_PLL_ANALOGTUNE 0x7ffU
8592 #define V_T5_STATIC_KR_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KR_PLL_ANALOGTUNE)
8593 #define G_T5_STATIC_KR_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KR_PLL_ANALOGTUNE) & M_T5_STATIC_KR_PLL_ANALOGTUNE)
8595 #define A_DBG_PVT_REG_CALIBRATE_CTL 0x6100
8597 #define S_HALT_CALIBRATE 1
8598 #define V_HALT_CALIBRATE(x) ((x) << S_HALT_CALIBRATE)
8599 #define F_HALT_CALIBRATE V_HALT_CALIBRATE(1U)
8601 #define S_RESET_CALIBRATE 0
8602 #define V_RESET_CALIBRATE(x) ((x) << S_RESET_CALIBRATE)
8603 #define F_RESET_CALIBRATE V_RESET_CALIBRATE(1U)
8605 #define A_DBG_GPIO_EN_NEW 0x6100
8607 #define S_GPIO16_OEN 7
8608 #define V_GPIO16_OEN(x) ((x) << S_GPIO16_OEN)
8609 #define F_GPIO16_OEN V_GPIO16_OEN(1U)
8611 #define S_GPIO17_OEN 6
8612 #define V_GPIO17_OEN(x) ((x) << S_GPIO17_OEN)
8613 #define F_GPIO17_OEN V_GPIO17_OEN(1U)
8615 #define S_GPIO18_OEN 5
8616 #define V_GPIO18_OEN(x) ((x) << S_GPIO18_OEN)
8617 #define F_GPIO18_OEN V_GPIO18_OEN(1U)
8619 #define S_GPIO19_OEN 4
8620 #define V_GPIO19_OEN(x) ((x) << S_GPIO19_OEN)
8621 #define F_GPIO19_OEN V_GPIO19_OEN(1U)
8623 #define S_GPIO16_OUT_VAL 3
8624 #define V_GPIO16_OUT_VAL(x) ((x) << S_GPIO16_OUT_VAL)
8625 #define F_GPIO16_OUT_VAL V_GPIO16_OUT_VAL(1U)
8627 #define S_GPIO17_OUT_VAL 2
8628 #define V_GPIO17_OUT_VAL(x) ((x) << S_GPIO17_OUT_VAL)
8629 #define F_GPIO17_OUT_VAL V_GPIO17_OUT_VAL(1U)
8631 #define S_GPIO18_OUT_VAL 1
8632 #define V_GPIO18_OUT_VAL(x) ((x) << S_GPIO18_OUT_VAL)
8633 #define F_GPIO18_OUT_VAL V_GPIO18_OUT_VAL(1U)
8635 #define S_GPIO19_OUT_VAL 0
8636 #define V_GPIO19_OUT_VAL(x) ((x) << S_GPIO19_OUT_VAL)
8637 #define F_GPIO19_OUT_VAL V_GPIO19_OUT_VAL(1U)
8639 #define A_DBG_PVT_REG_UPDATE_CTL 0x6104
8641 #define S_FAST_UPDATE 8
8642 #define V_FAST_UPDATE(x) ((x) << S_FAST_UPDATE)
8643 #define F_FAST_UPDATE V_FAST_UPDATE(1U)
8645 #define S_FORCE_REG_IN_VALUE 2
8646 #define V_FORCE_REG_IN_VALUE(x) ((x) << S_FORCE_REG_IN_VALUE)
8647 #define F_FORCE_REG_IN_VALUE V_FORCE_REG_IN_VALUE(1U)
8649 #define S_HALT_UPDATE 1
8650 #define V_HALT_UPDATE(x) ((x) << S_HALT_UPDATE)
8651 #define F_HALT_UPDATE V_HALT_UPDATE(1U)
8653 #define A_DBG_GPIO_IN_NEW 0x6104
8655 #define S_GPIO16_CHG_DET 7
8656 #define V_GPIO16_CHG_DET(x) ((x) << S_GPIO16_CHG_DET)
8657 #define F_GPIO16_CHG_DET V_GPIO16_CHG_DET(1U)
8659 #define S_GPIO17_CHG_DET 6
8660 #define V_GPIO17_CHG_DET(x) ((x) << S_GPIO17_CHG_DET)
8661 #define F_GPIO17_CHG_DET V_GPIO17_CHG_DET(1U)
8663 #define S_GPIO18_CHG_DET 5
8664 #define V_GPIO18_CHG_DET(x) ((x) << S_GPIO18_CHG_DET)
8665 #define F_GPIO18_CHG_DET V_GPIO18_CHG_DET(1U)
8667 #define S_GPIO19_CHG_DET 4
8668 #define V_GPIO19_CHG_DET(x) ((x) << S_GPIO19_CHG_DET)
8669 #define F_GPIO19_CHG_DET V_GPIO19_CHG_DET(1U)
8671 #define S_GPIO16_IN 3
8672 #define V_GPIO16_IN(x) ((x) << S_GPIO16_IN)
8673 #define F_GPIO16_IN V_GPIO16_IN(1U)
8675 #define S_GPIO17_IN 2
8676 #define V_GPIO17_IN(x) ((x) << S_GPIO17_IN)
8677 #define F_GPIO17_IN V_GPIO17_IN(1U)
8679 #define S_GPIO18_IN 1
8680 #define V_GPIO18_IN(x) ((x) << S_GPIO18_IN)
8681 #define F_GPIO18_IN V_GPIO18_IN(1U)
8683 #define S_GPIO19_IN 0
8684 #define V_GPIO19_IN(x) ((x) << S_GPIO19_IN)
8685 #define F_GPIO19_IN V_GPIO19_IN(1U)
8687 #define A_DBG_PVT_REG_LAST_MEASUREMENT 0x6108
8689 #define S_LAST_MEASUREMENT_SELECT 8
8690 #define M_LAST_MEASUREMENT_SELECT 0x3U
8691 #define V_LAST_MEASUREMENT_SELECT(x) ((x) << S_LAST_MEASUREMENT_SELECT)
8692 #define G_LAST_MEASUREMENT_SELECT(x) (((x) >> S_LAST_MEASUREMENT_SELECT) & M_LAST_MEASUREMENT_SELECT)
8694 #define S_LAST_MEASUREMENT_RESULT_BANK_B 4
8695 #define M_LAST_MEASUREMENT_RESULT_BANK_B 0xfU
8696 #define V_LAST_MEASUREMENT_RESULT_BANK_B(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_B)
8697 #define G_LAST_MEASUREMENT_RESULT_BANK_B(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_B) & M_LAST_MEASUREMENT_RESULT_BANK_B)
8699 #define S_LAST_MEASUREMENT_RESULT_BANK_A 0
8700 #define M_LAST_MEASUREMENT_RESULT_BANK_A 0xfU
8701 #define V_LAST_MEASUREMENT_RESULT_BANK_A(x) ((x) << S_LAST_MEASUREMENT_RESULT_BANK_A)
8702 #define G_LAST_MEASUREMENT_RESULT_BANK_A(x) (((x) >> S_LAST_MEASUREMENT_RESULT_BANK_A) & M_LAST_MEASUREMENT_RESULT_BANK_A)
8704 #define A_DBG_T5_STATIC_KX_PLL_CONF1 0x6108
8706 #define S_T5_STATIC_KX_PLL_BYPASS 30
8707 #define V_T5_STATIC_KX_PLL_BYPASS(x) ((x) << S_T5_STATIC_KX_PLL_BYPASS)
8708 #define F_T5_STATIC_KX_PLL_BYPASS V_T5_STATIC_KX_PLL_BYPASS(1U)
8710 #define S_T5_STATIC_KX_PLL_VBOOSTDIV 27
8711 #define M_T5_STATIC_KX_PLL_VBOOSTDIV 0x7U
8712 #define V_T5_STATIC_KX_PLL_VBOOSTDIV(x) ((x) << S_T5_STATIC_KX_PLL_VBOOSTDIV)
8713 #define G_T5_STATIC_KX_PLL_VBOOSTDIV(x) (((x) >> S_T5_STATIC_KX_PLL_VBOOSTDIV) & M_T5_STATIC_KX_PLL_VBOOSTDIV)
8715 #define S_T5_STATIC_KX_PLL_CPISEL 24
8716 #define M_T5_STATIC_KX_PLL_CPISEL 0x7U
8717 #define V_T5_STATIC_KX_PLL_CPISEL(x) ((x) << S_T5_STATIC_KX_PLL_CPISEL)
8718 #define G_T5_STATIC_KX_PLL_CPISEL(x) (((x) >> S_T5_STATIC_KX_PLL_CPISEL) & M_T5_STATIC_KX_PLL_CPISEL)
8720 #define S_T5_STATIC_KX_PLL_CCALMETHOD 23
8721 #define V_T5_STATIC_KX_PLL_CCALMETHOD(x) ((x) << S_T5_STATIC_KX_PLL_CCALMETHOD)
8722 #define F_T5_STATIC_KX_PLL_CCALMETHOD V_T5_STATIC_KX_PLL_CCALMETHOD(1U)
8724 #define S_T5_STATIC_KX_PLL_CCALLOAD 22
8725 #define V_T5_STATIC_KX_PLL_CCALLOAD(x) ((x) << S_T5_STATIC_KX_PLL_CCALLOAD)
8726 #define F_T5_STATIC_KX_PLL_CCALLOAD V_T5_STATIC_KX_PLL_CCALLOAD(1U)
8728 #define S_T5_STATIC_KX_PLL_CCALFMIN 21
8729 #define V_T5_STATIC_KX_PLL_CCALFMIN(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMIN)
8730 #define F_T5_STATIC_KX_PLL_CCALFMIN V_T5_STATIC_KX_PLL_CCALFMIN(1U)
8732 #define S_T5_STATIC_KX_PLL_CCALFMAX 20
8733 #define V_T5_STATIC_KX_PLL_CCALFMAX(x) ((x) << S_T5_STATIC_KX_PLL_CCALFMAX)
8734 #define F_T5_STATIC_KX_PLL_CCALFMAX V_T5_STATIC_KX_PLL_CCALFMAX(1U)
8736 #define S_T5_STATIC_KX_PLL_CCALCVHOLD 19
8737 #define V_T5_STATIC_KX_PLL_CCALCVHOLD(x) ((x) << S_T5_STATIC_KX_PLL_CCALCVHOLD)
8738 #define F_T5_STATIC_KX_PLL_CCALCVHOLD V_T5_STATIC_KX_PLL_CCALCVHOLD(1U)
8740 #define S_T5_STATIC_KX_PLL_CCALBANDSEL 15
8741 #define M_T5_STATIC_KX_PLL_CCALBANDSEL 0xfU
8742 #define V_T5_STATIC_KX_PLL_CCALBANDSEL(x) ((x) << S_T5_STATIC_KX_PLL_CCALBANDSEL)
8743 #define G_T5_STATIC_KX_PLL_CCALBANDSEL(x) (((x) >> S_T5_STATIC_KX_PLL_CCALBANDSEL) & M_T5_STATIC_KX_PLL_CCALBANDSEL)
8745 #define S_T5_STATIC_KX_PLL_BGOFFSET 11
8746 #define M_T5_STATIC_KX_PLL_BGOFFSET 0xfU
8747 #define V_T5_STATIC_KX_PLL_BGOFFSET(x) ((x) << S_T5_STATIC_KX_PLL_BGOFFSET)
8748 #define G_T5_STATIC_KX_PLL_BGOFFSET(x) (((x) >> S_T5_STATIC_KX_PLL_BGOFFSET) & M_T5_STATIC_KX_PLL_BGOFFSET)
8750 #define S_T5_STATIC_KX_PLL_P 8
8751 #define M_T5_STATIC_KX_PLL_P 0x7U
8752 #define V_T5_STATIC_KX_PLL_P(x) ((x) << S_T5_STATIC_KX_PLL_P)
8753 #define G_T5_STATIC_KX_PLL_P(x) (((x) >> S_T5_STATIC_KX_PLL_P) & M_T5_STATIC_KX_PLL_P)
8755 #define S_T5_STATIC_KX_PLL_N2 4
8756 #define M_T5_STATIC_KX_PLL_N2 0xfU
8757 #define V_T5_STATIC_KX_PLL_N2(x) ((x) << S_T5_STATIC_KX_PLL_N2)
8758 #define G_T5_STATIC_KX_PLL_N2(x) (((x) >> S_T5_STATIC_KX_PLL_N2) & M_T5_STATIC_KX_PLL_N2)
8760 #define S_T5_STATIC_KX_PLL_N1 0
8761 #define M_T5_STATIC_KX_PLL_N1 0xfU
8762 #define V_T5_STATIC_KX_PLL_N1(x) ((x) << S_T5_STATIC_KX_PLL_N1)
8763 #define G_T5_STATIC_KX_PLL_N1(x) (((x) >> S_T5_STATIC_KX_PLL_N1) & M_T5_STATIC_KX_PLL_N1)
8765 #define A_DBG_PVT_REG_DRVN 0x610c
8767 #define S_PVT_REG_DRVN_EN 8
8768 #define V_PVT_REG_DRVN_EN(x) ((x) << S_PVT_REG_DRVN_EN)
8769 #define F_PVT_REG_DRVN_EN V_PVT_REG_DRVN_EN(1U)
8771 #define S_PVT_REG_DRVN_B 4
8772 #define M_PVT_REG_DRVN_B 0xfU
8773 #define V_PVT_REG_DRVN_B(x) ((x) << S_PVT_REG_DRVN_B)
8774 #define G_PVT_REG_DRVN_B(x) (((x) >> S_PVT_REG_DRVN_B) & M_PVT_REG_DRVN_B)
8776 #define S_PVT_REG_DRVN_A 0
8777 #define M_PVT_REG_DRVN_A 0xfU
8778 #define V_PVT_REG_DRVN_A(x) ((x) << S_PVT_REG_DRVN_A)
8779 #define G_PVT_REG_DRVN_A(x) (((x) >> S_PVT_REG_DRVN_A) & M_PVT_REG_DRVN_A)
8781 #define A_DBG_T5_STATIC_KX_PLL_CONF2 0x610c
8783 #define S_T5_STATIC_KX_PLL_M 11
8784 #define M_T5_STATIC_KX_PLL_M 0x1ffU
8785 #define V_T5_STATIC_KX_PLL_M(x) ((x) << S_T5_STATIC_KX_PLL_M)
8786 #define G_T5_STATIC_KX_PLL_M(x) (((x) >> S_T5_STATIC_KX_PLL_M) & M_T5_STATIC_KX_PLL_M)
8788 #define S_T5_STATIC_KX_PLL_ANALOGTUNE 0
8789 #define M_T5_STATIC_KX_PLL_ANALOGTUNE 0x7ffU
8790 #define V_T5_STATIC_KX_PLL_ANALOGTUNE(x) ((x) << S_T5_STATIC_KX_PLL_ANALOGTUNE)
8791 #define G_T5_STATIC_KX_PLL_ANALOGTUNE(x) (((x) >> S_T5_STATIC_KX_PLL_ANALOGTUNE) & M_T5_STATIC_KX_PLL_ANALOGTUNE)
8793 #define A_DBG_PVT_REG_DRVP 0x6110
8795 #define S_PVT_REG_DRVP_EN 8
8796 #define V_PVT_REG_DRVP_EN(x) ((x) << S_PVT_REG_DRVP_EN)
8797 #define F_PVT_REG_DRVP_EN V_PVT_REG_DRVP_EN(1U)
8799 #define S_PVT_REG_DRVP_B 4
8800 #define M_PVT_REG_DRVP_B 0xfU
8801 #define V_PVT_REG_DRVP_B(x) ((x) << S_PVT_REG_DRVP_B)
8802 #define G_PVT_REG_DRVP_B(x) (((x) >> S_PVT_REG_DRVP_B) & M_PVT_REG_DRVP_B)
8804 #define S_PVT_REG_DRVP_A 0
8805 #define M_PVT_REG_DRVP_A 0xfU
8806 #define V_PVT_REG_DRVP_A(x) ((x) << S_PVT_REG_DRVP_A)
8807 #define G_PVT_REG_DRVP_A(x) (((x) >> S_PVT_REG_DRVP_A) & M_PVT_REG_DRVP_A)
8809 #define A_DBG_T5_STATIC_C_DFS_CONF 0x6110
8811 #define S_STATIC_C_DFS_RANGEA 8
8812 #define M_STATIC_C_DFS_RANGEA 0x1fU
8813 #define V_STATIC_C_DFS_RANGEA(x) ((x) << S_STATIC_C_DFS_RANGEA)
8814 #define G_STATIC_C_DFS_RANGEA(x) (((x) >> S_STATIC_C_DFS_RANGEA) & M_STATIC_C_DFS_RANGEA)
8816 #define S_STATIC_C_DFS_RANGEB 3
8817 #define M_STATIC_C_DFS_RANGEB 0x1fU
8818 #define V_STATIC_C_DFS_RANGEB(x) ((x) << S_STATIC_C_DFS_RANGEB)
8819 #define G_STATIC_C_DFS_RANGEB(x) (((x) >> S_STATIC_C_DFS_RANGEB) & M_STATIC_C_DFS_RANGEB)
8821 #define S_STATIC_C_DFS_FFTUNE4 2
8822 #define V_STATIC_C_DFS_FFTUNE4(x) ((x) << S_STATIC_C_DFS_FFTUNE4)
8823 #define F_STATIC_C_DFS_FFTUNE4 V_STATIC_C_DFS_FFTUNE4(1U)
8825 #define S_STATIC_C_DFS_FFTUNE5 1
8826 #define V_STATIC_C_DFS_FFTUNE5(x) ((x) << S_STATIC_C_DFS_FFTUNE5)
8827 #define F_STATIC_C_DFS_FFTUNE5 V_STATIC_C_DFS_FFTUNE5(1U)
8829 #define S_STATIC_C_DFS_ENABLE 0
8830 #define V_STATIC_C_DFS_ENABLE(x) ((x) << S_STATIC_C_DFS_ENABLE)
8831 #define F_STATIC_C_DFS_ENABLE V_STATIC_C_DFS_ENABLE(1U)
8833 #define A_DBG_PVT_REG_TERMN 0x6114
8835 #define S_PVT_REG_TERMN_EN 8
8836 #define V_PVT_REG_TERMN_EN(x) ((x) << S_PVT_REG_TERMN_EN)
8837 #define F_PVT_REG_TERMN_EN V_PVT_REG_TERMN_EN(1U)
8839 #define S_PVT_REG_TERMN_B 4
8840 #define M_PVT_REG_TERMN_B 0xfU
8841 #define V_PVT_REG_TERMN_B(x) ((x) << S_PVT_REG_TERMN_B)
8842 #define G_PVT_REG_TERMN_B(x) (((x) >> S_PVT_REG_TERMN_B) & M_PVT_REG_TERMN_B)
8844 #define S_PVT_REG_TERMN_A 0
8845 #define M_PVT_REG_TERMN_A 0xfU
8846 #define V_PVT_REG_TERMN_A(x) ((x) << S_PVT_REG_TERMN_A)
8847 #define G_PVT_REG_TERMN_A(x) (((x) >> S_PVT_REG_TERMN_A) & M_PVT_REG_TERMN_A)
8849 #define A_DBG_T5_STATIC_U_DFS_CONF 0x6114
8851 #define S_STATIC_U_DFS_RANGEA 8
8852 #define M_STATIC_U_DFS_RANGEA 0x1fU
8853 #define V_STATIC_U_DFS_RANGEA(x) ((x) << S_STATIC_U_DFS_RANGEA)
8854 #define G_STATIC_U_DFS_RANGEA(x) (((x) >> S_STATIC_U_DFS_RANGEA) & M_STATIC_U_DFS_RANGEA)
8856 #define S_STATIC_U_DFS_RANGEB 3
8857 #define M_STATIC_U_DFS_RANGEB 0x1fU
8858 #define V_STATIC_U_DFS_RANGEB(x) ((x) << S_STATIC_U_DFS_RANGEB)
8859 #define G_STATIC_U_DFS_RANGEB(x) (((x) >> S_STATIC_U_DFS_RANGEB) & M_STATIC_U_DFS_RANGEB)
8861 #define S_STATIC_U_DFS_FFTUNE4 2
8862 #define V_STATIC_U_DFS_FFTUNE4(x) ((x) << S_STATIC_U_DFS_FFTUNE4)
8863 #define F_STATIC_U_DFS_FFTUNE4 V_STATIC_U_DFS_FFTUNE4(1U)
8865 #define S_STATIC_U_DFS_FFTUNE5 1
8866 #define V_STATIC_U_DFS_FFTUNE5(x) ((x) << S_STATIC_U_DFS_FFTUNE5)
8867 #define F_STATIC_U_DFS_FFTUNE5 V_STATIC_U_DFS_FFTUNE5(1U)
8869 #define S_STATIC_U_DFS_ENABLE 0
8870 #define V_STATIC_U_DFS_ENABLE(x) ((x) << S_STATIC_U_DFS_ENABLE)
8871 #define F_STATIC_U_DFS_ENABLE V_STATIC_U_DFS_ENABLE(1U)
8873 #define A_DBG_PVT_REG_TERMP 0x6118
8875 #define S_PVT_REG_TERMP_EN 8
8876 #define V_PVT_REG_TERMP_EN(x) ((x) << S_PVT_REG_TERMP_EN)
8877 #define F_PVT_REG_TERMP_EN V_PVT_REG_TERMP_EN(1U)
8879 #define S_PVT_REG_TERMP_B 4
8880 #define M_PVT_REG_TERMP_B 0xfU
8881 #define V_PVT_REG_TERMP_B(x) ((x) << S_PVT_REG_TERMP_B)
8882 #define G_PVT_REG_TERMP_B(x) (((x) >> S_PVT_REG_TERMP_B) & M_PVT_REG_TERMP_B)
8884 #define S_PVT_REG_TERMP_A 0
8885 #define M_PVT_REG_TERMP_A 0xfU
8886 #define V_PVT_REG_TERMP_A(x) ((x) << S_PVT_REG_TERMP_A)
8887 #define G_PVT_REG_TERMP_A(x) (((x) >> S_PVT_REG_TERMP_A) & M_PVT_REG_TERMP_A)
8889 #define A_DBG_GPIO_PE_EN 0x6118
8891 #define S_GPIO19_PE_EN 19
8892 #define V_GPIO19_PE_EN(x) ((x) << S_GPIO19_PE_EN)
8893 #define F_GPIO19_PE_EN V_GPIO19_PE_EN(1U)
8895 #define S_GPIO18_PE_EN 18
8896 #define V_GPIO18_PE_EN(x) ((x) << S_GPIO18_PE_EN)
8897 #define F_GPIO18_PE_EN V_GPIO18_PE_EN(1U)
8899 #define S_GPIO17_PE_EN 17
8900 #define V_GPIO17_PE_EN(x) ((x) << S_GPIO17_PE_EN)
8901 #define F_GPIO17_PE_EN V_GPIO17_PE_EN(1U)
8903 #define S_GPIO16_PE_EN 16
8904 #define V_GPIO16_PE_EN(x) ((x) << S_GPIO16_PE_EN)
8905 #define F_GPIO16_PE_EN V_GPIO16_PE_EN(1U)
8907 #define S_GPIO15_PE_EN 15
8908 #define V_GPIO15_PE_EN(x) ((x) << S_GPIO15_PE_EN)
8909 #define F_GPIO15_PE_EN V_GPIO15_PE_EN(1U)
8911 #define S_GPIO14_PE_EN 14
8912 #define V_GPIO14_PE_EN(x) ((x) << S_GPIO14_PE_EN)
8913 #define F_GPIO14_PE_EN V_GPIO14_PE_EN(1U)
8915 #define S_GPIO13_PE_EN 13
8916 #define V_GPIO13_PE_EN(x) ((x) << S_GPIO13_PE_EN)
8917 #define F_GPIO13_PE_EN V_GPIO13_PE_EN(1U)
8919 #define S_GPIO12_PE_EN 12
8920 #define V_GPIO12_PE_EN(x) ((x) << S_GPIO12_PE_EN)
8921 #define F_GPIO12_PE_EN V_GPIO12_PE_EN(1U)
8923 #define S_GPIO11_PE_EN 11
8924 #define V_GPIO11_PE_EN(x) ((x) << S_GPIO11_PE_EN)
8925 #define F_GPIO11_PE_EN V_GPIO11_PE_EN(1U)
8927 #define S_GPIO10_PE_EN 10
8928 #define V_GPIO10_PE_EN(x) ((x) << S_GPIO10_PE_EN)
8929 #define F_GPIO10_PE_EN V_GPIO10_PE_EN(1U)
8931 #define S_GPIO9_PE_EN 9
8932 #define V_GPIO9_PE_EN(x) ((x) << S_GPIO9_PE_EN)
8933 #define F_GPIO9_PE_EN V_GPIO9_PE_EN(1U)
8935 #define S_GPIO8_PE_EN 8
8936 #define V_GPIO8_PE_EN(x) ((x) << S_GPIO8_PE_EN)
8937 #define F_GPIO8_PE_EN V_GPIO8_PE_EN(1U)
8939 #define S_GPIO7_PE_EN 7
8940 #define V_GPIO7_PE_EN(x) ((x) << S_GPIO7_PE_EN)
8941 #define F_GPIO7_PE_EN V_GPIO7_PE_EN(1U)
8943 #define S_GPIO6_PE_EN 6
8944 #define V_GPIO6_PE_EN(x) ((x) << S_GPIO6_PE_EN)
8945 #define F_GPIO6_PE_EN V_GPIO6_PE_EN(1U)
8947 #define S_GPIO5_PE_EN 5
8948 #define V_GPIO5_PE_EN(x) ((x) << S_GPIO5_PE_EN)
8949 #define F_GPIO5_PE_EN V_GPIO5_PE_EN(1U)
8951 #define S_GPIO4_PE_EN 4
8952 #define V_GPIO4_PE_EN(x) ((x) << S_GPIO4_PE_EN)
8953 #define F_GPIO4_PE_EN V_GPIO4_PE_EN(1U)
8955 #define S_GPIO3_PE_EN 3
8956 #define V_GPIO3_PE_EN(x) ((x) << S_GPIO3_PE_EN)
8957 #define F_GPIO3_PE_EN V_GPIO3_PE_EN(1U)
8959 #define S_GPIO2_PE_EN 2
8960 #define V_GPIO2_PE_EN(x) ((x) << S_GPIO2_PE_EN)
8961 #define F_GPIO2_PE_EN V_GPIO2_PE_EN(1U)
8963 #define S_GPIO1_PE_EN 1
8964 #define V_GPIO1_PE_EN(x) ((x) << S_GPIO1_PE_EN)
8965 #define F_GPIO1_PE_EN V_GPIO1_PE_EN(1U)
8967 #define S_GPIO0_PE_EN 0
8968 #define V_GPIO0_PE_EN(x) ((x) << S_GPIO0_PE_EN)
8969 #define F_GPIO0_PE_EN V_GPIO0_PE_EN(1U)
8971 #define A_DBG_PVT_REG_THRESHOLD 0x611c
8973 #define S_PVT_CALIBRATION_DONE 8
8974 #define V_PVT_CALIBRATION_DONE(x) ((x) << S_PVT_CALIBRATION_DONE)
8975 #define F_PVT_CALIBRATION_DONE V_PVT_CALIBRATION_DONE(1U)
8977 #define S_THRESHOLD_TERMP_MAX_SYNC 7
8978 #define V_THRESHOLD_TERMP_MAX_SYNC(x) ((x) << S_THRESHOLD_TERMP_MAX_SYNC)
8979 #define F_THRESHOLD_TERMP_MAX_SYNC V_THRESHOLD_TERMP_MAX_SYNC(1U)
8981 #define S_THRESHOLD_TERMP_MIN_SYNC 6
8982 #define V_THRESHOLD_TERMP_MIN_SYNC(x) ((x) << S_THRESHOLD_TERMP_MIN_SYNC)
8983 #define F_THRESHOLD_TERMP_MIN_SYNC V_THRESHOLD_TERMP_MIN_SYNC(1U)
8985 #define S_THRESHOLD_TERMN_MAX_SYNC 5
8986 #define V_THRESHOLD_TERMN_MAX_SYNC(x) ((x) << S_THRESHOLD_TERMN_MAX_SYNC)
8987 #define F_THRESHOLD_TERMN_MAX_SYNC V_THRESHOLD_TERMN_MAX_SYNC(1U)
8989 #define S_THRESHOLD_TERMN_MIN_SYNC 4
8990 #define V_THRESHOLD_TERMN_MIN_SYNC(x) ((x) << S_THRESHOLD_TERMN_MIN_SYNC)
8991 #define F_THRESHOLD_TERMN_MIN_SYNC V_THRESHOLD_TERMN_MIN_SYNC(1U)
8993 #define S_THRESHOLD_DRVP_MAX_SYNC 3
8994 #define V_THRESHOLD_DRVP_MAX_SYNC(x) ((x) << S_THRESHOLD_DRVP_MAX_SYNC)
8995 #define F_THRESHOLD_DRVP_MAX_SYNC V_THRESHOLD_DRVP_MAX_SYNC(1U)
8997 #define S_THRESHOLD_DRVP_MIN_SYNC 2
8998 #define V_THRESHOLD_DRVP_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVP_MIN_SYNC)
8999 #define F_THRESHOLD_DRVP_MIN_SYNC V_THRESHOLD_DRVP_MIN_SYNC(1U)
9001 #define S_THRESHOLD_DRVN_MAX_SYNC 1
9002 #define V_THRESHOLD_DRVN_MAX_SYNC(x) ((x) << S_THRESHOLD_DRVN_MAX_SYNC)
9003 #define F_THRESHOLD_DRVN_MAX_SYNC V_THRESHOLD_DRVN_MAX_SYNC(1U)
9005 #define S_THRESHOLD_DRVN_MIN_SYNC 0
9006 #define V_THRESHOLD_DRVN_MIN_SYNC(x) ((x) << S_THRESHOLD_DRVN_MIN_SYNC)
9007 #define F_THRESHOLD_DRVN_MIN_SYNC V_THRESHOLD_DRVN_MIN_SYNC(1U)
9009 #define A_DBG_GPIO_PS_EN 0x611c
9011 #define S_GPIO19_PS_EN 19
9012 #define V_GPIO19_PS_EN(x) ((x) << S_GPIO19_PS_EN)
9013 #define F_GPIO19_PS_EN V_GPIO19_PS_EN(1U)
9015 #define S_GPIO18_PS_EN 18
9016 #define V_GPIO18_PS_EN(x) ((x) << S_GPIO18_PS_EN)
9017 #define F_GPIO18_PS_EN V_GPIO18_PS_EN(1U)
9019 #define S_GPIO17_PS_EN 17
9020 #define V_GPIO17_PS_EN(x) ((x) << S_GPIO17_PS_EN)
9021 #define F_GPIO17_PS_EN V_GPIO17_PS_EN(1U)
9023 #define S_GPIO16_PS_EN 16
9024 #define V_GPIO16_PS_EN(x) ((x) << S_GPIO16_PS_EN)
9025 #define F_GPIO16_PS_EN V_GPIO16_PS_EN(1U)
9027 #define S_GPIO15_PS_EN 15
9028 #define V_GPIO15_PS_EN(x) ((x) << S_GPIO15_PS_EN)
9029 #define F_GPIO15_PS_EN V_GPIO15_PS_EN(1U)
9031 #define S_GPIO14_PS_EN 14
9032 #define V_GPIO14_PS_EN(x) ((x) << S_GPIO14_PS_EN)
9033 #define F_GPIO14_PS_EN V_GPIO14_PS_EN(1U)
9035 #define S_GPIO13_PS_EN 13
9036 #define V_GPIO13_PS_EN(x) ((x) << S_GPIO13_PS_EN)
9037 #define F_GPIO13_PS_EN V_GPIO13_PS_EN(1U)
9039 #define S_GPIO12_PS_EN 12
9040 #define V_GPIO12_PS_EN(x) ((x) << S_GPIO12_PS_EN)
9041 #define F_GPIO12_PS_EN V_GPIO12_PS_EN(1U)
9043 #define S_GPIO11_PS_EN 11
9044 #define V_GPIO11_PS_EN(x) ((x) << S_GPIO11_PS_EN)
9045 #define F_GPIO11_PS_EN V_GPIO11_PS_EN(1U)
9047 #define S_GPIO10_PS_EN 10
9048 #define V_GPIO10_PS_EN(x) ((x) << S_GPIO10_PS_EN)
9049 #define F_GPIO10_PS_EN V_GPIO10_PS_EN(1U)
9051 #define S_GPIO9_PS_EN 9
9052 #define V_GPIO9_PS_EN(x) ((x) << S_GPIO9_PS_EN)
9053 #define F_GPIO9_PS_EN V_GPIO9_PS_EN(1U)
9055 #define S_GPIO8_PS_EN 8
9056 #define V_GPIO8_PS_EN(x) ((x) << S_GPIO8_PS_EN)
9057 #define F_GPIO8_PS_EN V_GPIO8_PS_EN(1U)
9059 #define S_GPIO7_PS_EN 7
9060 #define V_GPIO7_PS_EN(x) ((x) << S_GPIO7_PS_EN)
9061 #define F_GPIO7_PS_EN V_GPIO7_PS_EN(1U)
9063 #define S_GPIO6_PS_EN 6
9064 #define V_GPIO6_PS_EN(x) ((x) << S_GPIO6_PS_EN)
9065 #define F_GPIO6_PS_EN V_GPIO6_PS_EN(1U)
9067 #define S_GPIO5_PS_EN 5
9068 #define V_GPIO5_PS_EN(x) ((x) << S_GPIO5_PS_EN)
9069 #define F_GPIO5_PS_EN V_GPIO5_PS_EN(1U)
9071 #define S_GPIO4_PS_EN 4
9072 #define V_GPIO4_PS_EN(x) ((x) << S_GPIO4_PS_EN)
9073 #define F_GPIO4_PS_EN V_GPIO4_PS_EN(1U)
9075 #define S_GPIO3_PS_EN 3
9076 #define V_GPIO3_PS_EN(x) ((x) << S_GPIO3_PS_EN)
9077 #define F_GPIO3_PS_EN V_GPIO3_PS_EN(1U)
9079 #define S_GPIO2_PS_EN 2
9080 #define V_GPIO2_PS_EN(x) ((x) << S_GPIO2_PS_EN)
9081 #define F_GPIO2_PS_EN V_GPIO2_PS_EN(1U)
9083 #define S_GPIO1_PS_EN 1
9084 #define V_GPIO1_PS_EN(x) ((x) << S_GPIO1_PS_EN)
9085 #define F_GPIO1_PS_EN V_GPIO1_PS_EN(1U)
9087 #define S_GPIO0_PS_EN 0
9088 #define V_GPIO0_PS_EN(x) ((x) << S_GPIO0_PS_EN)
9089 #define F_GPIO0_PS_EN V_GPIO0_PS_EN(1U)
9091 #define A_DBG_PVT_REG_IN_TERMP 0x6120
9093 #define S_REG_IN_TERMP_B 4
9094 #define M_REG_IN_TERMP_B 0xfU
9095 #define V_REG_IN_TERMP_B(x) ((x) << S_REG_IN_TERMP_B)
9096 #define G_REG_IN_TERMP_B(x) (((x) >> S_REG_IN_TERMP_B) & M_REG_IN_TERMP_B)
9098 #define S_REG_IN_TERMP_A 0
9099 #define M_REG_IN_TERMP_A 0xfU
9100 #define V_REG_IN_TERMP_A(x) ((x) << S_REG_IN_TERMP_A)
9101 #define G_REG_IN_TERMP_A(x) (((x) >> S_REG_IN_TERMP_A) & M_REG_IN_TERMP_A)
9103 #define A_DBG_EFUSE_BYTE16_19 0x6120
9104 #define A_DBG_PVT_REG_IN_TERMN 0x6124
9106 #define S_REG_IN_TERMN_B 4
9107 #define M_REG_IN_TERMN_B 0xfU
9108 #define V_REG_IN_TERMN_B(x) ((x) << S_REG_IN_TERMN_B)
9109 #define G_REG_IN_TERMN_B(x) (((x) >> S_REG_IN_TERMN_B) & M_REG_IN_TERMN_B)
9111 #define S_REG_IN_TERMN_A 0
9112 #define M_REG_IN_TERMN_A 0xfU
9113 #define V_REG_IN_TERMN_A(x) ((x) << S_REG_IN_TERMN_A)
9114 #define G_REG_IN_TERMN_A(x) (((x) >> S_REG_IN_TERMN_A) & M_REG_IN_TERMN_A)
9116 #define A_DBG_EFUSE_BYTE20_23 0x6124
9117 #define A_DBG_PVT_REG_IN_DRVP 0x6128
9119 #define S_REG_IN_DRVP_B 4
9120 #define M_REG_IN_DRVP_B 0xfU
9121 #define V_REG_IN_DRVP_B(x) ((x) << S_REG_IN_DRVP_B)
9122 #define G_REG_IN_DRVP_B(x) (((x) >> S_REG_IN_DRVP_B) & M_REG_IN_DRVP_B)
9124 #define S_REG_IN_DRVP_A 0
9125 #define M_REG_IN_DRVP_A 0xfU
9126 #define V_REG_IN_DRVP_A(x) ((x) << S_REG_IN_DRVP_A)
9127 #define G_REG_IN_DRVP_A(x) (((x) >> S_REG_IN_DRVP_A) & M_REG_IN_DRVP_A)
9129 #define A_DBG_EFUSE_BYTE24_27 0x6128
9130 #define A_DBG_PVT_REG_IN_DRVN 0x612c
9132 #define S_REG_IN_DRVN_B 4
9133 #define M_REG_IN_DRVN_B 0xfU
9134 #define V_REG_IN_DRVN_B(x) ((x) << S_REG_IN_DRVN_B)
9135 #define G_REG_IN_DRVN_B(x) (((x) >> S_REG_IN_DRVN_B) & M_REG_IN_DRVN_B)
9137 #define S_REG_IN_DRVN_A 0
9138 #define M_REG_IN_DRVN_A 0xfU
9139 #define V_REG_IN_DRVN_A(x) ((x) << S_REG_IN_DRVN_A)
9140 #define G_REG_IN_DRVN_A(x) (((x) >> S_REG_IN_DRVN_A) & M_REG_IN_DRVN_A)
9142 #define A_DBG_EFUSE_BYTE28_31 0x612c
9143 #define A_DBG_PVT_REG_OUT_TERMP 0x6130
9145 #define S_REG_OUT_TERMP_B 4
9146 #define M_REG_OUT_TERMP_B 0xfU
9147 #define V_REG_OUT_TERMP_B(x) ((x) << S_REG_OUT_TERMP_B)
9148 #define G_REG_OUT_TERMP_B(x) (((x) >> S_REG_OUT_TERMP_B) & M_REG_OUT_TERMP_B)
9150 #define S_REG_OUT_TERMP_A 0
9151 #define M_REG_OUT_TERMP_A 0xfU
9152 #define V_REG_OUT_TERMP_A(x) ((x) << S_REG_OUT_TERMP_A)
9153 #define G_REG_OUT_TERMP_A(x) (((x) >> S_REG_OUT_TERMP_A) & M_REG_OUT_TERMP_A)
9155 #define A_DBG_EFUSE_BYTE32_35 0x6130
9156 #define A_DBG_PVT_REG_OUT_TERMN 0x6134
9158 #define S_REG_OUT_TERMN_B 4
9159 #define M_REG_OUT_TERMN_B 0xfU
9160 #define V_REG_OUT_TERMN_B(x) ((x) << S_REG_OUT_TERMN_B)
9161 #define G_REG_OUT_TERMN_B(x) (((x) >> S_REG_OUT_TERMN_B) & M_REG_OUT_TERMN_B)
9163 #define S_REG_OUT_TERMN_A 0
9164 #define M_REG_OUT_TERMN_A 0xfU
9165 #define V_REG_OUT_TERMN_A(x) ((x) << S_REG_OUT_TERMN_A)
9166 #define G_REG_OUT_TERMN_A(x) (((x) >> S_REG_OUT_TERMN_A) & M_REG_OUT_TERMN_A)
9168 #define A_DBG_EFUSE_BYTE36_39 0x6134
9169 #define A_DBG_PVT_REG_OUT_DRVP 0x6138
9171 #define S_REG_OUT_DRVP_B 4
9172 #define M_REG_OUT_DRVP_B 0xfU
9173 #define V_REG_OUT_DRVP_B(x) ((x) << S_REG_OUT_DRVP_B)
9174 #define G_REG_OUT_DRVP_B(x) (((x) >> S_REG_OUT_DRVP_B) & M_REG_OUT_DRVP_B)
9176 #define S_REG_OUT_DRVP_A 0
9177 #define M_REG_OUT_DRVP_A 0xfU
9178 #define V_REG_OUT_DRVP_A(x) ((x) << S_REG_OUT_DRVP_A)
9179 #define G_REG_OUT_DRVP_A(x) (((x) >> S_REG_OUT_DRVP_A) & M_REG_OUT_DRVP_A)
9181 #define A_DBG_EFUSE_BYTE40_43 0x6138
9182 #define A_DBG_PVT_REG_OUT_DRVN 0x613c
9184 #define S_REG_OUT_DRVN_B 4
9185 #define M_REG_OUT_DRVN_B 0xfU
9186 #define V_REG_OUT_DRVN_B(x) ((x) << S_REG_OUT_DRVN_B)
9187 #define G_REG_OUT_DRVN_B(x) (((x) >> S_REG_OUT_DRVN_B) & M_REG_OUT_DRVN_B)
9189 #define S_REG_OUT_DRVN_A 0
9190 #define M_REG_OUT_DRVN_A 0xfU
9191 #define V_REG_OUT_DRVN_A(x) ((x) << S_REG_OUT_DRVN_A)
9192 #define G_REG_OUT_DRVN_A(x) (((x) >> S_REG_OUT_DRVN_A) & M_REG_OUT_DRVN_A)
9194 #define A_DBG_EFUSE_BYTE44_47 0x613c
9195 #define A_DBG_PVT_REG_HISTORY_TERMP 0x6140
9197 #define S_TERMP_B_HISTORY 4
9198 #define M_TERMP_B_HISTORY 0xfU
9199 #define V_TERMP_B_HISTORY(x) ((x) << S_TERMP_B_HISTORY)
9200 #define G_TERMP_B_HISTORY(x) (((x) >> S_TERMP_B_HISTORY) & M_TERMP_B_HISTORY)
9202 #define S_TERMP_A_HISTORY 0
9203 #define M_TERMP_A_HISTORY 0xfU
9204 #define V_TERMP_A_HISTORY(x) ((x) << S_TERMP_A_HISTORY)
9205 #define G_TERMP_A_HISTORY(x) (((x) >> S_TERMP_A_HISTORY) & M_TERMP_A_HISTORY)
9207 #define A_DBG_EFUSE_BYTE48_51 0x6140
9208 #define A_DBG_PVT_REG_HISTORY_TERMN 0x6144
9210 #define S_TERMN_B_HISTORY 4
9211 #define M_TERMN_B_HISTORY 0xfU
9212 #define V_TERMN_B_HISTORY(x) ((x) << S_TERMN_B_HISTORY)
9213 #define G_TERMN_B_HISTORY(x) (((x) >> S_TERMN_B_HISTORY) & M_TERMN_B_HISTORY)
9215 #define S_TERMN_A_HISTORY 0
9216 #define M_TERMN_A_HISTORY 0xfU
9217 #define V_TERMN_A_HISTORY(x) ((x) << S_TERMN_A_HISTORY)
9218 #define G_TERMN_A_HISTORY(x) (((x) >> S_TERMN_A_HISTORY) & M_TERMN_A_HISTORY)
9220 #define A_DBG_EFUSE_BYTE52_55 0x6144
9221 #define A_DBG_PVT_REG_HISTORY_DRVP 0x6148
9223 #define S_DRVP_B_HISTORY 4
9224 #define M_DRVP_B_HISTORY 0xfU
9225 #define V_DRVP_B_HISTORY(x) ((x) << S_DRVP_B_HISTORY)
9226 #define G_DRVP_B_HISTORY(x) (((x) >> S_DRVP_B_HISTORY) & M_DRVP_B_HISTORY)
9228 #define S_DRVP_A_HISTORY 0
9229 #define M_DRVP_A_HISTORY 0xfU
9230 #define V_DRVP_A_HISTORY(x) ((x) << S_DRVP_A_HISTORY)
9231 #define G_DRVP_A_HISTORY(x) (((x) >> S_DRVP_A_HISTORY) & M_DRVP_A_HISTORY)
9233 #define A_DBG_EFUSE_BYTE56_59 0x6148
9234 #define A_DBG_PVT_REG_HISTORY_DRVN 0x614c
9236 #define S_DRVN_B_HISTORY 4
9237 #define M_DRVN_B_HISTORY 0xfU
9238 #define V_DRVN_B_HISTORY(x) ((x) << S_DRVN_B_HISTORY)
9239 #define G_DRVN_B_HISTORY(x) (((x) >> S_DRVN_B_HISTORY) & M_DRVN_B_HISTORY)
9241 #define S_DRVN_A_HISTORY 0
9242 #define M_DRVN_A_HISTORY 0xfU
9243 #define V_DRVN_A_HISTORY(x) ((x) << S_DRVN_A_HISTORY)
9244 #define G_DRVN_A_HISTORY(x) (((x) >> S_DRVN_A_HISTORY) & M_DRVN_A_HISTORY)
9246 #define A_DBG_EFUSE_BYTE60_63 0x614c
9247 #define A_DBG_PVT_REG_SAMPLE_WAIT_CLKS 0x6150
9249 #define S_SAMPLE_WAIT_CLKS 0
9250 #define M_SAMPLE_WAIT_CLKS 0x1fU
9251 #define V_SAMPLE_WAIT_CLKS(x) ((x) << S_SAMPLE_WAIT_CLKS)
9252 #define G_SAMPLE_WAIT_CLKS(x) (((x) >> S_SAMPLE_WAIT_CLKS) & M_SAMPLE_WAIT_CLKS)
9254 /* registers for module MC */
9255 #define MC_BASE_ADDR 0x6200
9257 #define A_MC_PCTL_SCFG 0x6200
9259 #define S_RKINF_EN 5
9260 #define V_RKINF_EN(x) ((x) << S_RKINF_EN)
9261 #define F_RKINF_EN V_RKINF_EN(1U)
9263 #define S_DUAL_PCTL_EN 4
9264 #define V_DUAL_PCTL_EN(x) ((x) << S_DUAL_PCTL_EN)
9265 #define F_DUAL_PCTL_EN V_DUAL_PCTL_EN(1U)
9267 #define S_SLAVE_MODE 3
9268 #define V_SLAVE_MODE(x) ((x) << S_SLAVE_MODE)
9269 #define F_SLAVE_MODE V_SLAVE_MODE(1U)
9271 #define S_LOOPBACK_EN 1
9272 #define V_LOOPBACK_EN(x) ((x) << S_LOOPBACK_EN)
9273 #define F_LOOPBACK_EN V_LOOPBACK_EN(1U)
9275 #define S_HW_LOW_POWER_EN 0
9276 #define V_HW_LOW_POWER_EN(x) ((x) << S_HW_LOW_POWER_EN)
9277 #define F_HW_LOW_POWER_EN V_HW_LOW_POWER_EN(1U)
9279 #define A_MC_PCTL_SCTL 0x6204
9281 #define S_STATE_CMD 0
9282 #define M_STATE_CMD 0x7U
9283 #define V_STATE_CMD(x) ((x) << S_STATE_CMD)
9284 #define G_STATE_CMD(x) (((x) >> S_STATE_CMD) & M_STATE_CMD)
9286 #define A_MC_PCTL_STAT 0x6208
9288 #define S_CTL_STAT 0
9289 #define M_CTL_STAT 0x7U
9290 #define V_CTL_STAT(x) ((x) << S_CTL_STAT)
9291 #define G_CTL_STAT(x) (((x) >> S_CTL_STAT) & M_CTL_STAT)
9293 #define A_MC_PCTL_MCMD 0x6240
9295 #define S_START_CMD 31
9296 #define V_START_CMD(x) ((x) << S_START_CMD)
9297 #define F_START_CMD V_START_CMD(1U)
9299 #define S_CMD_ADD_DEL 24
9300 #define M_CMD_ADD_DEL 0xfU
9301 #define V_CMD_ADD_DEL(x) ((x) << S_CMD_ADD_DEL)
9302 #define G_CMD_ADD_DEL(x) (((x) >> S_CMD_ADD_DEL) & M_CMD_ADD_DEL)
9304 #define S_RANK_SEL 20
9305 #define M_RANK_SEL 0xfU
9306 #define V_RANK_SEL(x) ((x) << S_RANK_SEL)
9307 #define G_RANK_SEL(x) (((x) >> S_RANK_SEL) & M_RANK_SEL)
9309 #define S_BANK_ADDR 17
9310 #define M_BANK_ADDR 0x7U
9311 #define V_BANK_ADDR(x) ((x) << S_BANK_ADDR)
9312 #define G_BANK_ADDR(x) (((x) >> S_BANK_ADDR) & M_BANK_ADDR)
9314 #define S_CMD_ADDR 4
9315 #define M_CMD_ADDR 0x1fffU
9316 #define V_CMD_ADDR(x) ((x) << S_CMD_ADDR)
9317 #define G_CMD_ADDR(x) (((x) >> S_CMD_ADDR) & M_CMD_ADDR)
9319 #define S_CMD_OPCODE 0
9320 #define M_CMD_OPCODE 0x7U
9321 #define V_CMD_OPCODE(x) ((x) << S_CMD_OPCODE)
9322 #define G_CMD_OPCODE(x) (((x) >> S_CMD_OPCODE) & M_CMD_OPCODE)
9324 #define A_MC_PCTL_POWCTL 0x6244
9326 #define S_POWER_UP_START 0
9327 #define V_POWER_UP_START(x) ((x) << S_POWER_UP_START)
9328 #define F_POWER_UP_START V_POWER_UP_START(1U)
9330 #define A_MC_PCTL_POWSTAT 0x6248
9332 #define S_PHY_CALIBDONE 1
9333 #define V_PHY_CALIBDONE(x) ((x) << S_PHY_CALIBDONE)
9334 #define F_PHY_CALIBDONE V_PHY_CALIBDONE(1U)
9336 #define S_POWER_UP_DONE 0
9337 #define V_POWER_UP_DONE(x) ((x) << S_POWER_UP_DONE)
9338 #define F_POWER_UP_DONE V_POWER_UP_DONE(1U)
9340 #define A_MC_PCTL_MCFG 0x6280
9342 #define S_TFAW_CFG 18
9343 #define M_TFAW_CFG 0x3U
9344 #define V_TFAW_CFG(x) ((x) << S_TFAW_CFG)
9345 #define G_TFAW_CFG(x) (((x) >> S_TFAW_CFG) & M_TFAW_CFG)
9347 #define S_PD_EXIT_MODE 17
9348 #define V_PD_EXIT_MODE(x) ((x) << S_PD_EXIT_MODE)
9349 #define F_PD_EXIT_MODE V_PD_EXIT_MODE(1U)
9351 #define S_PD_TYPE 16
9352 #define V_PD_TYPE(x) ((x) << S_PD_TYPE)
9353 #define F_PD_TYPE V_PD_TYPE(1U)
9356 #define M_PD_IDLE 0xffU
9357 #define V_PD_IDLE(x) ((x) << S_PD_IDLE)
9358 #define G_PD_IDLE(x) (((x) >> S_PD_IDLE) & M_PD_IDLE)
9360 #define S_PAGE_POLICY 6
9361 #define M_PAGE_POLICY 0x3U
9362 #define V_PAGE_POLICY(x) ((x) << S_PAGE_POLICY)
9363 #define G_PAGE_POLICY(x) (((x) >> S_PAGE_POLICY) & M_PAGE_POLICY)
9366 #define V_DDR3_EN(x) ((x) << S_DDR3_EN)
9367 #define F_DDR3_EN V_DDR3_EN(1U)
9369 #define S_TWO_T_EN 3
9370 #define V_TWO_T_EN(x) ((x) << S_TWO_T_EN)
9371 #define F_TWO_T_EN V_TWO_T_EN(1U)
9373 #define S_BL8INT_EN 2
9374 #define V_BL8INT_EN(x) ((x) << S_BL8INT_EN)
9375 #define F_BL8INT_EN V_BL8INT_EN(1U)
9378 #define V_MEM_BL(x) ((x) << S_MEM_BL)
9379 #define F_MEM_BL V_MEM_BL(1U)
9381 #define A_MC_PCTL_PPCFG 0x6284
9383 #define S_RPMEM_DIS 1
9384 #define M_RPMEM_DIS 0xffU
9385 #define V_RPMEM_DIS(x) ((x) << S_RPMEM_DIS)
9386 #define G_RPMEM_DIS(x) (((x) >> S_RPMEM_DIS) & M_RPMEM_DIS)
9388 #define S_PPMEM_EN 0
9389 #define V_PPMEM_EN(x) ((x) << S_PPMEM_EN)
9390 #define F_PPMEM_EN V_PPMEM_EN(1U)
9392 #define A_MC_PCTL_MSTAT 0x6288
9394 #define S_POWER_DOWN 0
9395 #define V_POWER_DOWN(x) ((x) << S_POWER_DOWN)
9396 #define F_POWER_DOWN V_POWER_DOWN(1U)
9398 #define A_MC_PCTL_ODTCFG 0x628c
9400 #define S_RANK3_ODT_DEFAULT 28
9401 #define V_RANK3_ODT_DEFAULT(x) ((x) << S_RANK3_ODT_DEFAULT)
9402 #define F_RANK3_ODT_DEFAULT V_RANK3_ODT_DEFAULT(1U)
9404 #define S_RANK3_ODT_WRITE_SEL 27
9405 #define V_RANK3_ODT_WRITE_SEL(x) ((x) << S_RANK3_ODT_WRITE_SEL)
9406 #define F_RANK3_ODT_WRITE_SEL V_RANK3_ODT_WRITE_SEL(1U)
9408 #define S_RANK3_ODT_WRITE_NSE 26
9409 #define V_RANK3_ODT_WRITE_NSE(x) ((x) << S_RANK3_ODT_WRITE_NSE)
9410 #define F_RANK3_ODT_WRITE_NSE V_RANK3_ODT_WRITE_NSE(1U)
9412 #define S_RANK3_ODT_READ_SEL 25
9413 #define V_RANK3_ODT_READ_SEL(x) ((x) << S_RANK3_ODT_READ_SEL)
9414 #define F_RANK3_ODT_READ_SEL V_RANK3_ODT_READ_SEL(1U)
9416 #define S_RANK3_ODT_READ_NSEL 24
9417 #define V_RANK3_ODT_READ_NSEL(x) ((x) << S_RANK3_ODT_READ_NSEL)
9418 #define F_RANK3_ODT_READ_NSEL V_RANK3_ODT_READ_NSEL(1U)
9420 #define S_RANK2_ODT_DEFAULT 20
9421 #define V_RANK2_ODT_DEFAULT(x) ((x) << S_RANK2_ODT_DEFAULT)
9422 #define F_RANK2_ODT_DEFAULT V_RANK2_ODT_DEFAULT(1U)
9424 #define S_RANK2_ODT_WRITE_SEL 19
9425 #define V_RANK2_ODT_WRITE_SEL(x) ((x) << S_RANK2_ODT_WRITE_SEL)
9426 #define F_RANK2_ODT_WRITE_SEL V_RANK2_ODT_WRITE_SEL(1U)
9428 #define S_RANK2_ODT_WRITE_NSEL 18
9429 #define V_RANK2_ODT_WRITE_NSEL(x) ((x) << S_RANK2_ODT_WRITE_NSEL)
9430 #define F_RANK2_ODT_WRITE_NSEL V_RANK2_ODT_WRITE_NSEL(1U)
9432 #define S_RANK2_ODT_READ_SEL 17
9433 #define V_RANK2_ODT_READ_SEL(x) ((x) << S_RANK2_ODT_READ_SEL)
9434 #define F_RANK2_ODT_READ_SEL V_RANK2_ODT_READ_SEL(1U)
9436 #define S_RANK2_ODT_READ_NSEL 16
9437 #define V_RANK2_ODT_READ_NSEL(x) ((x) << S_RANK2_ODT_READ_NSEL)
9438 #define F_RANK2_ODT_READ_NSEL V_RANK2_ODT_READ_NSEL(1U)
9440 #define S_RANK1_ODT_DEFAULT 12
9441 #define V_RANK1_ODT_DEFAULT(x) ((x) << S_RANK1_ODT_DEFAULT)
9442 #define F_RANK1_ODT_DEFAULT V_RANK1_ODT_DEFAULT(1U)
9444 #define S_RANK1_ODT_WRITE_SEL 11
9445 #define V_RANK1_ODT_WRITE_SEL(x) ((x) << S_RANK1_ODT_WRITE_SEL)
9446 #define F_RANK1_ODT_WRITE_SEL V_RANK1_ODT_WRITE_SEL(1U)
9448 #define S_RANK1_ODT_WRITE_NSEL 10
9449 #define V_RANK1_ODT_WRITE_NSEL(x) ((x) << S_RANK1_ODT_WRITE_NSEL)
9450 #define F_RANK1_ODT_WRITE_NSEL V_RANK1_ODT_WRITE_NSEL(1U)
9452 #define S_RANK1_ODT_READ_SEL 9
9453 #define V_RANK1_ODT_READ_SEL(x) ((x) << S_RANK1_ODT_READ_SEL)
9454 #define F_RANK1_ODT_READ_SEL V_RANK1_ODT_READ_SEL(1U)
9456 #define S_RANK1_ODT_READ_NSEL 8
9457 #define V_RANK1_ODT_READ_NSEL(x) ((x) << S_RANK1_ODT_READ_NSEL)
9458 #define F_RANK1_ODT_READ_NSEL V_RANK1_ODT_READ_NSEL(1U)
9460 #define S_RANK0_ODT_DEFAULT 4
9461 #define V_RANK0_ODT_DEFAULT(x) ((x) << S_RANK0_ODT_DEFAULT)
9462 #define F_RANK0_ODT_DEFAULT V_RANK0_ODT_DEFAULT(1U)
9464 #define S_RANK0_ODT_WRITE_SEL 3
9465 #define V_RANK0_ODT_WRITE_SEL(x) ((x) << S_RANK0_ODT_WRITE_SEL)
9466 #define F_RANK0_ODT_WRITE_SEL V_RANK0_ODT_WRITE_SEL(1U)
9468 #define S_RANK0_ODT_WRITE_NSEL 2
9469 #define V_RANK0_ODT_WRITE_NSEL(x) ((x) << S_RANK0_ODT_WRITE_NSEL)
9470 #define F_RANK0_ODT_WRITE_NSEL V_RANK0_ODT_WRITE_NSEL(1U)
9472 #define S_RANK0_ODT_READ_SEL 1
9473 #define V_RANK0_ODT_READ_SEL(x) ((x) << S_RANK0_ODT_READ_SEL)
9474 #define F_RANK0_ODT_READ_SEL V_RANK0_ODT_READ_SEL(1U)
9476 #define S_RANK0_ODT_READ_NSEL 0
9477 #define V_RANK0_ODT_READ_NSEL(x) ((x) << S_RANK0_ODT_READ_NSEL)
9478 #define F_RANK0_ODT_READ_NSEL V_RANK0_ODT_READ_NSEL(1U)
9480 #define A_MC_PCTL_DQSECFG 0x6290
9482 #define S_DV_ALAT 20
9483 #define M_DV_ALAT 0xfU
9484 #define V_DV_ALAT(x) ((x) << S_DV_ALAT)
9485 #define G_DV_ALAT(x) (((x) >> S_DV_ALAT) & M_DV_ALAT)
9487 #define S_DV_ALEN 16
9488 #define M_DV_ALEN 0x3U
9489 #define V_DV_ALEN(x) ((x) << S_DV_ALEN)
9490 #define G_DV_ALEN(x) (((x) >> S_DV_ALEN) & M_DV_ALEN)
9492 #define S_DSE_ALAT 12
9493 #define M_DSE_ALAT 0xfU
9494 #define V_DSE_ALAT(x) ((x) << S_DSE_ALAT)
9495 #define G_DSE_ALAT(x) (((x) >> S_DSE_ALAT) & M_DSE_ALAT)
9497 #define S_DSE_ALEN 8
9498 #define M_DSE_ALEN 0x3U
9499 #define V_DSE_ALEN(x) ((x) << S_DSE_ALEN)
9500 #define G_DSE_ALEN(x) (((x) >> S_DSE_ALEN) & M_DSE_ALEN)
9502 #define S_QSE_ALAT 4
9503 #define M_QSE_ALAT 0xfU
9504 #define V_QSE_ALAT(x) ((x) << S_QSE_ALAT)
9505 #define G_QSE_ALAT(x) (((x) >> S_QSE_ALAT) & M_QSE_ALAT)
9507 #define S_QSE_ALEN 0
9508 #define M_QSE_ALEN 0x3U
9509 #define V_QSE_ALEN(x) ((x) << S_QSE_ALEN)
9510 #define G_QSE_ALEN(x) (((x) >> S_QSE_ALEN) & M_QSE_ALEN)
9512 #define A_MC_PCTL_DTUPDES 0x6294
9514 #define S_DTU_RD_MISSING 13
9515 #define V_DTU_RD_MISSING(x) ((x) << S_DTU_RD_MISSING)
9516 #define F_DTU_RD_MISSING V_DTU_RD_MISSING(1U)
9518 #define S_DTU_EAFFL 9
9519 #define M_DTU_EAFFL 0xfU
9520 #define V_DTU_EAFFL(x) ((x) << S_DTU_EAFFL)
9521 #define G_DTU_EAFFL(x) (((x) >> S_DTU_EAFFL) & M_DTU_EAFFL)
9523 #define S_DTU_RANDOM_ERROR 8
9524 #define V_DTU_RANDOM_ERROR(x) ((x) << S_DTU_RANDOM_ERROR)
9525 #define F_DTU_RANDOM_ERROR V_DTU_RANDOM_ERROR(1U)
9527 #define S_DTU_ERROR_B7 7
9528 #define V_DTU_ERROR_B7(x) ((x) << S_DTU_ERROR_B7)
9529 #define F_DTU_ERROR_B7 V_DTU_ERROR_B7(1U)
9531 #define S_DTU_ERR_B6 6
9532 #define V_DTU_ERR_B6(x) ((x) << S_DTU_ERR_B6)
9533 #define F_DTU_ERR_B6 V_DTU_ERR_B6(1U)
9535 #define S_DTU_ERR_B5 5
9536 #define V_DTU_ERR_B5(x) ((x) << S_DTU_ERR_B5)
9537 #define F_DTU_ERR_B5 V_DTU_ERR_B5(1U)
9539 #define S_DTU_ERR_B4 4
9540 #define V_DTU_ERR_B4(x) ((x) << S_DTU_ERR_B4)
9541 #define F_DTU_ERR_B4 V_DTU_ERR_B4(1U)
9543 #define S_DTU_ERR_B3 3
9544 #define V_DTU_ERR_B3(x) ((x) << S_DTU_ERR_B3)
9545 #define F_DTU_ERR_B3 V_DTU_ERR_B3(1U)
9547 #define S_DTU_ERR_B2 2
9548 #define V_DTU_ERR_B2(x) ((x) << S_DTU_ERR_B2)
9549 #define F_DTU_ERR_B2 V_DTU_ERR_B2(1U)
9551 #define S_DTU_ERR_B1 1
9552 #define V_DTU_ERR_B1(x) ((x) << S_DTU_ERR_B1)
9553 #define F_DTU_ERR_B1 V_DTU_ERR_B1(1U)
9555 #define S_DTU_ERR_B0 0
9556 #define V_DTU_ERR_B0(x) ((x) << S_DTU_ERR_B0)
9557 #define F_DTU_ERR_B0 V_DTU_ERR_B0(1U)
9559 #define A_MC_PCTL_DTUNA 0x6298
9560 #define A_MC_PCTL_DTUNE 0x629c
9561 #define A_MC_PCTL_DTUPRDO 0x62a0
9563 #define S_DTU_ALLBITS_1 16
9564 #define M_DTU_ALLBITS_1 0xffffU
9565 #define V_DTU_ALLBITS_1(x) ((x) << S_DTU_ALLBITS_1)
9566 #define G_DTU_ALLBITS_1(x) (((x) >> S_DTU_ALLBITS_1) & M_DTU_ALLBITS_1)
9568 #define S_DTU_ALLBITS_0 0
9569 #define M_DTU_ALLBITS_0 0xffffU
9570 #define V_DTU_ALLBITS_0(x) ((x) << S_DTU_ALLBITS_0)
9571 #define G_DTU_ALLBITS_0(x) (((x) >> S_DTU_ALLBITS_0) & M_DTU_ALLBITS_0)
9573 #define A_MC_PCTL_DTUPRD1 0x62a4
9575 #define S_DTU_ALLBITS_3 16
9576 #define M_DTU_ALLBITS_3 0xffffU
9577 #define V_DTU_ALLBITS_3(x) ((x) << S_DTU_ALLBITS_3)
9578 #define G_DTU_ALLBITS_3(x) (((x) >> S_DTU_ALLBITS_3) & M_DTU_ALLBITS_3)
9580 #define S_DTU_ALLBITS_2 0
9581 #define M_DTU_ALLBITS_2 0xffffU
9582 #define V_DTU_ALLBITS_2(x) ((x) << S_DTU_ALLBITS_2)
9583 #define G_DTU_ALLBITS_2(x) (((x) >> S_DTU_ALLBITS_2) & M_DTU_ALLBITS_2)
9585 #define A_MC_PCTL_DTUPRD2 0x62a8
9587 #define S_DTU_ALLBITS_5 16
9588 #define M_DTU_ALLBITS_5 0xffffU
9589 #define V_DTU_ALLBITS_5(x) ((x) << S_DTU_ALLBITS_5)
9590 #define G_DTU_ALLBITS_5(x) (((x) >> S_DTU_ALLBITS_5) & M_DTU_ALLBITS_5)
9592 #define S_DTU_ALLBITS_4 0
9593 #define M_DTU_ALLBITS_4 0xffffU
9594 #define V_DTU_ALLBITS_4(x) ((x) << S_DTU_ALLBITS_4)
9595 #define G_DTU_ALLBITS_4(x) (((x) >> S_DTU_ALLBITS_4) & M_DTU_ALLBITS_4)
9597 #define A_MC_PCTL_DTUPRD3 0x62ac
9599 #define S_DTU_ALLBITS_7 16
9600 #define M_DTU_ALLBITS_7 0xffffU
9601 #define V_DTU_ALLBITS_7(x) ((x) << S_DTU_ALLBITS_7)
9602 #define G_DTU_ALLBITS_7(x) (((x) >> S_DTU_ALLBITS_7) & M_DTU_ALLBITS_7)
9604 #define S_DTU_ALLBITS_6 0
9605 #define M_DTU_ALLBITS_6 0xffffU
9606 #define V_DTU_ALLBITS_6(x) ((x) << S_DTU_ALLBITS_6)
9607 #define G_DTU_ALLBITS_6(x) (((x) >> S_DTU_ALLBITS_6) & M_DTU_ALLBITS_6)
9609 #define A_MC_PCTL_DTUAWDT 0x62b0
9611 #define S_NUMBER_RANKS 9
9612 #define M_NUMBER_RANKS 0x3U
9613 #define V_NUMBER_RANKS(x) ((x) << S_NUMBER_RANKS)
9614 #define G_NUMBER_RANKS(x) (((x) >> S_NUMBER_RANKS) & M_NUMBER_RANKS)
9616 #define S_ROW_ADDR_WIDTH 6
9617 #define M_ROW_ADDR_WIDTH 0x3U
9618 #define V_ROW_ADDR_WIDTH(x) ((x) << S_ROW_ADDR_WIDTH)
9619 #define G_ROW_ADDR_WIDTH(x) (((x) >> S_ROW_ADDR_WIDTH) & M_ROW_ADDR_WIDTH)
9621 #define S_BANK_ADDR_WIDTH 3
9622 #define M_BANK_ADDR_WIDTH 0x3U
9623 #define V_BANK_ADDR_WIDTH(x) ((x) << S_BANK_ADDR_WIDTH)
9624 #define G_BANK_ADDR_WIDTH(x) (((x) >> S_BANK_ADDR_WIDTH) & M_BANK_ADDR_WIDTH)
9626 #define S_COLUMN_ADDR_WIDTH 0
9627 #define M_COLUMN_ADDR_WIDTH 0x3U
9628 #define V_COLUMN_ADDR_WIDTH(x) ((x) << S_COLUMN_ADDR_WIDTH)
9629 #define G_COLUMN_ADDR_WIDTH(x) (((x) >> S_COLUMN_ADDR_WIDTH) & M_COLUMN_ADDR_WIDTH)
9631 #define A_MC_PCTL_TOGCNT1U 0x62c0
9633 #define S_TOGGLE_COUNTER_1U 0
9634 #define M_TOGGLE_COUNTER_1U 0x3ffU
9635 #define V_TOGGLE_COUNTER_1U(x) ((x) << S_TOGGLE_COUNTER_1U)
9636 #define G_TOGGLE_COUNTER_1U(x) (((x) >> S_TOGGLE_COUNTER_1U) & M_TOGGLE_COUNTER_1U)
9638 #define A_MC_PCTL_TINIT 0x62c4
9641 #define M_T_INIT 0x1ffU
9642 #define V_T_INIT(x) ((x) << S_T_INIT)
9643 #define G_T_INIT(x) (((x) >> S_T_INIT) & M_T_INIT)
9645 #define A_MC_PCTL_TRSTH 0x62c8
9648 #define M_T_RSTH 0x3ffU
9649 #define V_T_RSTH(x) ((x) << S_T_RSTH)
9650 #define G_T_RSTH(x) (((x) >> S_T_RSTH) & M_T_RSTH)
9652 #define A_MC_PCTL_TOGCNT100N 0x62cc
9654 #define S_TOGGLE_COUNTER_100N 0
9655 #define M_TOGGLE_COUNTER_100N 0x7fU
9656 #define V_TOGGLE_COUNTER_100N(x) ((x) << S_TOGGLE_COUNTER_100N)
9657 #define G_TOGGLE_COUNTER_100N(x) (((x) >> S_TOGGLE_COUNTER_100N) & M_TOGGLE_COUNTER_100N)
9659 #define A_MC_PCTL_TREFI 0x62d0
9662 #define M_T_REFI 0xffU
9663 #define V_T_REFI(x) ((x) << S_T_REFI)
9664 #define G_T_REFI(x) (((x) >> S_T_REFI) & M_T_REFI)
9666 #define A_MC_PCTL_TMRD 0x62d4
9669 #define M_T_MRD 0x7U
9670 #define V_T_MRD(x) ((x) << S_T_MRD)
9671 #define G_T_MRD(x) (((x) >> S_T_MRD) & M_T_MRD)
9673 #define A_MC_PCTL_TRFC 0x62d8
9676 #define M_T_RFC 0xffU
9677 #define V_T_RFC(x) ((x) << S_T_RFC)
9678 #define G_T_RFC(x) (((x) >> S_T_RFC) & M_T_RFC)
9680 #define A_MC_PCTL_TRP 0x62dc
9684 #define V_T_RP(x) ((x) << S_T_RP)
9685 #define G_T_RP(x) (((x) >> S_T_RP) & M_T_RP)
9687 #define A_MC_PCTL_TRTW 0x62e0
9690 #define M_T_RTW 0x7U
9691 #define V_T_RTW(x) ((x) << S_T_RTW)
9692 #define G_T_RTW(x) (((x) >> S_T_RTW) & M_T_RTW)
9694 #define A_MC_PCTL_TAL 0x62e4
9698 #define V_T_AL(x) ((x) << S_T_AL)
9699 #define G_T_AL(x) (((x) >> S_T_AL) & M_T_AL)
9701 #define A_MC_PCTL_TCL 0x62e8
9705 #define V_T_CL(x) ((x) << S_T_CL)
9706 #define G_T_CL(x) (((x) >> S_T_CL) & M_T_CL)
9708 #define A_MC_PCTL_TCWL 0x62ec
9711 #define M_T_CWL 0xfU
9712 #define V_T_CWL(x) ((x) << S_T_CWL)
9713 #define G_T_CWL(x) (((x) >> S_T_CWL) & M_T_CWL)
9715 #define A_MC_PCTL_TRAS 0x62f0
9718 #define M_T_RAS 0x3fU
9719 #define V_T_RAS(x) ((x) << S_T_RAS)
9720 #define G_T_RAS(x) (((x) >> S_T_RAS) & M_T_RAS)
9722 #define A_MC_PCTL_TRC 0x62f4
9725 #define M_T_RC 0x3fU
9726 #define V_T_RC(x) ((x) << S_T_RC)
9727 #define G_T_RC(x) (((x) >> S_T_RC) & M_T_RC)
9729 #define A_MC_PCTL_TRCD 0x62f8
9732 #define M_T_RCD 0xfU
9733 #define V_T_RCD(x) ((x) << S_T_RCD)
9734 #define G_T_RCD(x) (((x) >> S_T_RCD) & M_T_RCD)
9736 #define A_MC_PCTL_TRRD 0x62fc
9739 #define M_T_RRD 0xfU
9740 #define V_T_RRD(x) ((x) << S_T_RRD)
9741 #define G_T_RRD(x) (((x) >> S_T_RRD) & M_T_RRD)
9743 #define A_MC_PCTL_TRTP 0x6300
9746 #define M_T_RTP 0x7U
9747 #define V_T_RTP(x) ((x) << S_T_RTP)
9748 #define G_T_RTP(x) (((x) >> S_T_RTP) & M_T_RTP)
9750 #define A_MC_PCTL_TWR 0x6304
9754 #define V_T_WR(x) ((x) << S_T_WR)
9755 #define G_T_WR(x) (((x) >> S_T_WR) & M_T_WR)
9757 #define A_MC_PCTL_TWTR 0x6308
9760 #define M_T_WTR 0x7U
9761 #define V_T_WTR(x) ((x) << S_T_WTR)
9762 #define G_T_WTR(x) (((x) >> S_T_WTR) & M_T_WTR)
9764 #define A_MC_PCTL_TEXSR 0x630c
9767 #define M_T_EXSR 0x3ffU
9768 #define V_T_EXSR(x) ((x) << S_T_EXSR)
9769 #define G_T_EXSR(x) (((x) >> S_T_EXSR) & M_T_EXSR)
9771 #define A_MC_PCTL_TXP 0x6310
9775 #define V_T_XP(x) ((x) << S_T_XP)
9776 #define G_T_XP(x) (((x) >> S_T_XP) & M_T_XP)
9778 #define A_MC_PCTL_TXPDLL 0x6314
9781 #define M_T_XPDLL 0x3fU
9782 #define V_T_XPDLL(x) ((x) << S_T_XPDLL)
9783 #define G_T_XPDLL(x) (((x) >> S_T_XPDLL) & M_T_XPDLL)
9785 #define A_MC_PCTL_TZQCS 0x6318
9788 #define M_T_ZQCS 0x7fU
9789 #define V_T_ZQCS(x) ((x) << S_T_ZQCS)
9790 #define G_T_ZQCS(x) (((x) >> S_T_ZQCS) & M_T_ZQCS)
9792 #define A_MC_PCTL_TZQCSI 0x631c
9795 #define M_T_ZQCSI 0xfffU
9796 #define V_T_ZQCSI(x) ((x) << S_T_ZQCSI)
9797 #define G_T_ZQCSI(x) (((x) >> S_T_ZQCSI) & M_T_ZQCSI)
9799 #define A_MC_PCTL_TDQS 0x6320
9802 #define M_T_DQS 0x7U
9803 #define V_T_DQS(x) ((x) << S_T_DQS)
9804 #define G_T_DQS(x) (((x) >> S_T_DQS) & M_T_DQS)
9806 #define A_MC_PCTL_TCKSRE 0x6324
9809 #define M_T_CKSRE 0xfU
9810 #define V_T_CKSRE(x) ((x) << S_T_CKSRE)
9811 #define G_T_CKSRE(x) (((x) >> S_T_CKSRE) & M_T_CKSRE)
9813 #define A_MC_PCTL_TCKSRX 0x6328
9816 #define M_T_CKSRX 0xfU
9817 #define V_T_CKSRX(x) ((x) << S_T_CKSRX)
9818 #define G_T_CKSRX(x) (((x) >> S_T_CKSRX) & M_T_CKSRX)
9820 #define A_MC_PCTL_TCKE 0x632c
9823 #define M_T_CKE 0x7U
9824 #define V_T_CKE(x) ((x) << S_T_CKE)
9825 #define G_T_CKE(x) (((x) >> S_T_CKE) & M_T_CKE)
9827 #define A_MC_PCTL_TMOD 0x6330
9830 #define M_T_MOD 0xfU
9831 #define V_T_MOD(x) ((x) << S_T_MOD)
9832 #define G_T_MOD(x) (((x) >> S_T_MOD) & M_T_MOD)
9834 #define A_MC_PCTL_TRSTL 0x6334
9837 #define M_RSTHOLD 0x7fU
9838 #define V_RSTHOLD(x) ((x) << S_RSTHOLD)
9839 #define G_RSTHOLD(x) (((x) >> S_RSTHOLD) & M_RSTHOLD)
9841 #define A_MC_PCTL_TZQCL 0x6338
9844 #define M_T_ZQCL 0x3ffU
9845 #define V_T_ZQCL(x) ((x) << S_T_ZQCL)
9846 #define G_T_ZQCL(x) (((x) >> S_T_ZQCL) & M_T_ZQCL)
9848 #define A_MC_PCTL_DWLCFG0 0x6370
9850 #define S_T_ADWL_VEC 0
9851 #define M_T_ADWL_VEC 0x1ffU
9852 #define V_T_ADWL_VEC(x) ((x) << S_T_ADWL_VEC)
9853 #define G_T_ADWL_VEC(x) (((x) >> S_T_ADWL_VEC) & M_T_ADWL_VEC)
9855 #define A_MC_PCTL_DWLCFG1 0x6374
9856 #define A_MC_PCTL_DWLCFG2 0x6378
9857 #define A_MC_PCTL_DWLCFG3 0x637c
9858 #define A_MC_PCTL_ECCCFG 0x6380
9860 #define S_INLINE_SYN_EN 4
9861 #define V_INLINE_SYN_EN(x) ((x) << S_INLINE_SYN_EN)
9862 #define F_INLINE_SYN_EN V_INLINE_SYN_EN(1U)
9865 #define V_ECC_EN(x) ((x) << S_ECC_EN)
9866 #define F_ECC_EN V_ECC_EN(1U)
9868 #define S_ECC_INTR_EN 2
9869 #define V_ECC_INTR_EN(x) ((x) << S_ECC_INTR_EN)
9870 #define F_ECC_INTR_EN V_ECC_INTR_EN(1U)
9872 #define A_MC_PCTL_ECCTST 0x6384
9874 #define S_ECC_TEST_MASK 0
9875 #define M_ECC_TEST_MASK 0xffU
9876 #define V_ECC_TEST_MASK(x) ((x) << S_ECC_TEST_MASK)
9877 #define G_ECC_TEST_MASK(x) (((x) >> S_ECC_TEST_MASK) & M_ECC_TEST_MASK)
9879 #define A_MC_PCTL_ECCCLR 0x6388
9881 #define S_CLR_ECC_LOG 1
9882 #define V_CLR_ECC_LOG(x) ((x) << S_CLR_ECC_LOG)
9883 #define F_CLR_ECC_LOG V_CLR_ECC_LOG(1U)
9885 #define S_CLR_ECC_INTR 0
9886 #define V_CLR_ECC_INTR(x) ((x) << S_CLR_ECC_INTR)
9887 #define F_CLR_ECC_INTR V_CLR_ECC_INTR(1U)
9889 #define A_MC_PCTL_ECCLOG 0x638c
9890 #define A_MC_PCTL_DTUWACTL 0x6400
9892 #define S_DTU_WR_RANK 30
9893 #define M_DTU_WR_RANK 0x3U
9894 #define V_DTU_WR_RANK(x) ((x) << S_DTU_WR_RANK)
9895 #define G_DTU_WR_RANK(x) (((x) >> S_DTU_WR_RANK) & M_DTU_WR_RANK)
9897 #define S_DTU_WR_ROW 13
9898 #define M_DTU_WR_ROW 0x1ffffU
9899 #define V_DTU_WR_ROW(x) ((x) << S_DTU_WR_ROW)
9900 #define G_DTU_WR_ROW(x) (((x) >> S_DTU_WR_ROW) & M_DTU_WR_ROW)
9902 #define S_DTU_WR_BANK 10
9903 #define M_DTU_WR_BANK 0x7U
9904 #define V_DTU_WR_BANK(x) ((x) << S_DTU_WR_BANK)
9905 #define G_DTU_WR_BANK(x) (((x) >> S_DTU_WR_BANK) & M_DTU_WR_BANK)
9907 #define S_DTU_WR_COL 0
9908 #define M_DTU_WR_COL 0x3ffU
9909 #define V_DTU_WR_COL(x) ((x) << S_DTU_WR_COL)
9910 #define G_DTU_WR_COL(x) (((x) >> S_DTU_WR_COL) & M_DTU_WR_COL)
9912 #define A_MC_PCTL_DTURACTL 0x6404
9914 #define S_DTU_RD_RANK 30
9915 #define M_DTU_RD_RANK 0x3U
9916 #define V_DTU_RD_RANK(x) ((x) << S_DTU_RD_RANK)
9917 #define G_DTU_RD_RANK(x) (((x) >> S_DTU_RD_RANK) & M_DTU_RD_RANK)
9919 #define S_DTU_RD_ROW 13
9920 #define M_DTU_RD_ROW 0x1ffffU
9921 #define V_DTU_RD_ROW(x) ((x) << S_DTU_RD_ROW)
9922 #define G_DTU_RD_ROW(x) (((x) >> S_DTU_RD_ROW) & M_DTU_RD_ROW)
9924 #define S_DTU_RD_BANK 10
9925 #define M_DTU_RD_BANK 0x7U
9926 #define V_DTU_RD_BANK(x) ((x) << S_DTU_RD_BANK)
9927 #define G_DTU_RD_BANK(x) (((x) >> S_DTU_RD_BANK) & M_DTU_RD_BANK)
9929 #define S_DTU_RD_COL 0
9930 #define M_DTU_RD_COL 0x3ffU
9931 #define V_DTU_RD_COL(x) ((x) << S_DTU_RD_COL)
9932 #define G_DTU_RD_COL(x) (((x) >> S_DTU_RD_COL) & M_DTU_RD_COL)
9934 #define A_MC_PCTL_DTUCFG 0x6408
9936 #define S_DTU_ROW_INCREMENTS 16
9937 #define M_DTU_ROW_INCREMENTS 0x7fU
9938 #define V_DTU_ROW_INCREMENTS(x) ((x) << S_DTU_ROW_INCREMENTS)
9939 #define G_DTU_ROW_INCREMENTS(x) (((x) >> S_DTU_ROW_INCREMENTS) & M_DTU_ROW_INCREMENTS)
9941 #define S_DTU_WR_MULTI_RD 15
9942 #define V_DTU_WR_MULTI_RD(x) ((x) << S_DTU_WR_MULTI_RD)
9943 #define F_DTU_WR_MULTI_RD V_DTU_WR_MULTI_RD(1U)
9945 #define S_DTU_DATA_MASK_EN 14
9946 #define V_DTU_DATA_MASK_EN(x) ((x) << S_DTU_DATA_MASK_EN)
9947 #define F_DTU_DATA_MASK_EN V_DTU_DATA_MASK_EN(1U)
9949 #define S_DTU_TARGET_LANE 10
9950 #define M_DTU_TARGET_LANE 0xfU
9951 #define V_DTU_TARGET_LANE(x) ((x) << S_DTU_TARGET_LANE)
9952 #define G_DTU_TARGET_LANE(x) (((x) >> S_DTU_TARGET_LANE) & M_DTU_TARGET_LANE)
9954 #define S_DTU_GENERATE_RANDOM 9
9955 #define V_DTU_GENERATE_RANDOM(x) ((x) << S_DTU_GENERATE_RANDOM)
9956 #define F_DTU_GENERATE_RANDOM V_DTU_GENERATE_RANDOM(1U)
9958 #define S_DTU_INCR_BANKS 8
9959 #define V_DTU_INCR_BANKS(x) ((x) << S_DTU_INCR_BANKS)
9960 #define F_DTU_INCR_BANKS V_DTU_INCR_BANKS(1U)
9962 #define S_DTU_INCR_COLS 7
9963 #define V_DTU_INCR_COLS(x) ((x) << S_DTU_INCR_COLS)
9964 #define F_DTU_INCR_COLS V_DTU_INCR_COLS(1U)
9966 #define S_DTU_NALEN 1
9967 #define M_DTU_NALEN 0x3fU
9968 #define V_DTU_NALEN(x) ((x) << S_DTU_NALEN)
9969 #define G_DTU_NALEN(x) (((x) >> S_DTU_NALEN) & M_DTU_NALEN)
9971 #define S_DTU_ENABLE 0
9972 #define V_DTU_ENABLE(x) ((x) << S_DTU_ENABLE)
9973 #define F_DTU_ENABLE V_DTU_ENABLE(1U)
9975 #define A_MC_PCTL_DTUECTL 0x640c
9977 #define S_WR_MULTI_RD_RST 2
9978 #define V_WR_MULTI_RD_RST(x) ((x) << S_WR_MULTI_RD_RST)
9979 #define F_WR_MULTI_RD_RST V_WR_MULTI_RD_RST(1U)
9981 #define S_RUN_ERROR_REPORTS 1
9982 #define V_RUN_ERROR_REPORTS(x) ((x) << S_RUN_ERROR_REPORTS)
9983 #define F_RUN_ERROR_REPORTS V_RUN_ERROR_REPORTS(1U)
9986 #define V_RUN_DTU(x) ((x) << S_RUN_DTU)
9987 #define F_RUN_DTU V_RUN_DTU(1U)
9989 #define A_MC_PCTL_DTUWD0 0x6410
9991 #define S_DTU_WR_BYTE3 24
9992 #define M_DTU_WR_BYTE3 0xffU
9993 #define V_DTU_WR_BYTE3(x) ((x) << S_DTU_WR_BYTE3)
9994 #define G_DTU_WR_BYTE3(x) (((x) >> S_DTU_WR_BYTE3) & M_DTU_WR_BYTE3)
9996 #define S_DTU_WR_BYTE2 16
9997 #define M_DTU_WR_BYTE2 0xffU
9998 #define V_DTU_WR_BYTE2(x) ((x) << S_DTU_WR_BYTE2)
9999 #define G_DTU_WR_BYTE2(x) (((x) >> S_DTU_WR_BYTE2) & M_DTU_WR_BYTE2)
10001 #define S_DTU_WR_BYTE1 8
10002 #define M_DTU_WR_BYTE1 0xffU
10003 #define V_DTU_WR_BYTE1(x) ((x) << S_DTU_WR_BYTE1)
10004 #define G_DTU_WR_BYTE1(x) (((x) >> S_DTU_WR_BYTE1) & M_DTU_WR_BYTE1)
10006 #define S_DTU_WR_BYTE0 0
10007 #define M_DTU_WR_BYTE0 0xffU
10008 #define V_DTU_WR_BYTE0(x) ((x) << S_DTU_WR_BYTE0)
10009 #define G_DTU_WR_BYTE0(x) (((x) >> S_DTU_WR_BYTE0) & M_DTU_WR_BYTE0)
10011 #define A_MC_PCTL_DTUWD1 0x6414
10013 #define S_DTU_WR_BYTE7 24
10014 #define M_DTU_WR_BYTE7 0xffU
10015 #define V_DTU_WR_BYTE7(x) ((x) << S_DTU_WR_BYTE7)
10016 #define G_DTU_WR_BYTE7(x) (((x) >> S_DTU_WR_BYTE7) & M_DTU_WR_BYTE7)
10018 #define S_DTU_WR_BYTE6 16
10019 #define M_DTU_WR_BYTE6 0xffU
10020 #define V_DTU_WR_BYTE6(x) ((x) << S_DTU_WR_BYTE6)
10021 #define G_DTU_WR_BYTE6(x) (((x) >> S_DTU_WR_BYTE6) & M_DTU_WR_BYTE6)
10023 #define S_DTU_WR_BYTE5 8
10024 #define M_DTU_WR_BYTE5 0xffU
10025 #define V_DTU_WR_BYTE5(x) ((x) << S_DTU_WR_BYTE5)
10026 #define G_DTU_WR_BYTE5(x) (((x) >> S_DTU_WR_BYTE5) & M_DTU_WR_BYTE5)
10028 #define S_DTU_WR_BYTE4 0
10029 #define M_DTU_WR_BYTE4 0xffU
10030 #define V_DTU_WR_BYTE4(x) ((x) << S_DTU_WR_BYTE4)
10031 #define G_DTU_WR_BYTE4(x) (((x) >> S_DTU_WR_BYTE4) & M_DTU_WR_BYTE4)
10033 #define A_MC_PCTL_DTUWD2 0x6418
10035 #define S_DTU_WR_BYTE11 24
10036 #define M_DTU_WR_BYTE11 0xffU
10037 #define V_DTU_WR_BYTE11(x) ((x) << S_DTU_WR_BYTE11)
10038 #define G_DTU_WR_BYTE11(x) (((x) >> S_DTU_WR_BYTE11) & M_DTU_WR_BYTE11)
10040 #define S_DTU_WR_BYTE10 16
10041 #define M_DTU_WR_BYTE10 0xffU
10042 #define V_DTU_WR_BYTE10(x) ((x) << S_DTU_WR_BYTE10)
10043 #define G_DTU_WR_BYTE10(x) (((x) >> S_DTU_WR_BYTE10) & M_DTU_WR_BYTE10)
10045 #define S_DTU_WR_BYTE9 8
10046 #define M_DTU_WR_BYTE9 0xffU
10047 #define V_DTU_WR_BYTE9(x) ((x) << S_DTU_WR_BYTE9)
10048 #define G_DTU_WR_BYTE9(x) (((x) >> S_DTU_WR_BYTE9) & M_DTU_WR_BYTE9)
10050 #define S_DTU_WR_BYTE8 0
10051 #define M_DTU_WR_BYTE8 0xffU
10052 #define V_DTU_WR_BYTE8(x) ((x) << S_DTU_WR_BYTE8)
10053 #define G_DTU_WR_BYTE8(x) (((x) >> S_DTU_WR_BYTE8) & M_DTU_WR_BYTE8)
10055 #define A_MC_PCTL_DTUWD3 0x641c
10057 #define S_DTU_WR_BYTE15 24
10058 #define M_DTU_WR_BYTE15 0xffU
10059 #define V_DTU_WR_BYTE15(x) ((x) << S_DTU_WR_BYTE15)
10060 #define G_DTU_WR_BYTE15(x) (((x) >> S_DTU_WR_BYTE15) & M_DTU_WR_BYTE15)
10062 #define S_DTU_WR_BYTE14 16
10063 #define M_DTU_WR_BYTE14 0xffU
10064 #define V_DTU_WR_BYTE14(x) ((x) << S_DTU_WR_BYTE14)
10065 #define G_DTU_WR_BYTE14(x) (((x) >> S_DTU_WR_BYTE14) & M_DTU_WR_BYTE14)
10067 #define S_DTU_WR_BYTE13 8
10068 #define M_DTU_WR_BYTE13 0xffU
10069 #define V_DTU_WR_BYTE13(x) ((x) << S_DTU_WR_BYTE13)
10070 #define G_DTU_WR_BYTE13(x) (((x) >> S_DTU_WR_BYTE13) & M_DTU_WR_BYTE13)
10072 #define S_DTU_WR_BYTE12 0
10073 #define M_DTU_WR_BYTE12 0xffU
10074 #define V_DTU_WR_BYTE12(x) ((x) << S_DTU_WR_BYTE12)
10075 #define G_DTU_WR_BYTE12(x) (((x) >> S_DTU_WR_BYTE12) & M_DTU_WR_BYTE12)
10077 #define A_MC_PCTL_DTUWDM 0x6420
10079 #define S_DM_WR_BYTE0 0
10080 #define M_DM_WR_BYTE0 0xffffU
10081 #define V_DM_WR_BYTE0(x) ((x) << S_DM_WR_BYTE0)
10082 #define G_DM_WR_BYTE0(x) (((x) >> S_DM_WR_BYTE0) & M_DM_WR_BYTE0)
10084 #define A_MC_PCTL_DTURD0 0x6424
10086 #define S_DTU_RD_BYTE3 24
10087 #define M_DTU_RD_BYTE3 0xffU
10088 #define V_DTU_RD_BYTE3(x) ((x) << S_DTU_RD_BYTE3)
10089 #define G_DTU_RD_BYTE3(x) (((x) >> S_DTU_RD_BYTE3) & M_DTU_RD_BYTE3)
10091 #define S_DTU_RD_BYTE2 16
10092 #define M_DTU_RD_BYTE2 0xffU
10093 #define V_DTU_RD_BYTE2(x) ((x) << S_DTU_RD_BYTE2)
10094 #define G_DTU_RD_BYTE2(x) (((x) >> S_DTU_RD_BYTE2) & M_DTU_RD_BYTE2)
10096 #define S_DTU_RD_BYTE1 8
10097 #define M_DTU_RD_BYTE1 0xffU
10098 #define V_DTU_RD_BYTE1(x) ((x) << S_DTU_RD_BYTE1)
10099 #define G_DTU_RD_BYTE1(x) (((x) >> S_DTU_RD_BYTE1) & M_DTU_RD_BYTE1)
10101 #define S_DTU_RD_BYTE0 0
10102 #define M_DTU_RD_BYTE0 0xffU
10103 #define V_DTU_RD_BYTE0(x) ((x) << S_DTU_RD_BYTE0)
10104 #define G_DTU_RD_BYTE0(x) (((x) >> S_DTU_RD_BYTE0) & M_DTU_RD_BYTE0)
10106 #define A_MC_PCTL_DTURD1 0x6428
10108 #define S_DTU_RD_BYTE7 24
10109 #define M_DTU_RD_BYTE7 0xffU
10110 #define V_DTU_RD_BYTE7(x) ((x) << S_DTU_RD_BYTE7)
10111 #define G_DTU_RD_BYTE7(x) (((x) >> S_DTU_RD_BYTE7) & M_DTU_RD_BYTE7)
10113 #define S_DTU_RD_BYTE6 16
10114 #define M_DTU_RD_BYTE6 0xffU
10115 #define V_DTU_RD_BYTE6(x) ((x) << S_DTU_RD_BYTE6)
10116 #define G_DTU_RD_BYTE6(x) (((x) >> S_DTU_RD_BYTE6) & M_DTU_RD_BYTE6)
10118 #define S_DTU_RD_BYTE5 8
10119 #define M_DTU_RD_BYTE5 0xffU
10120 #define V_DTU_RD_BYTE5(x) ((x) << S_DTU_RD_BYTE5)
10121 #define G_DTU_RD_BYTE5(x) (((x) >> S_DTU_RD_BYTE5) & M_DTU_RD_BYTE5)
10123 #define S_DTU_RD_BYTE4 0
10124 #define M_DTU_RD_BYTE4 0xffU
10125 #define V_DTU_RD_BYTE4(x) ((x) << S_DTU_RD_BYTE4)
10126 #define G_DTU_RD_BYTE4(x) (((x) >> S_DTU_RD_BYTE4) & M_DTU_RD_BYTE4)
10128 #define A_MC_PCTL_DTURD2 0x642c
10130 #define S_DTU_RD_BYTE11 24
10131 #define M_DTU_RD_BYTE11 0xffU
10132 #define V_DTU_RD_BYTE11(x) ((x) << S_DTU_RD_BYTE11)
10133 #define G_DTU_RD_BYTE11(x) (((x) >> S_DTU_RD_BYTE11) & M_DTU_RD_BYTE11)
10135 #define S_DTU_RD_BYTE10 16
10136 #define M_DTU_RD_BYTE10 0xffU
10137 #define V_DTU_RD_BYTE10(x) ((x) << S_DTU_RD_BYTE10)
10138 #define G_DTU_RD_BYTE10(x) (((x) >> S_DTU_RD_BYTE10) & M_DTU_RD_BYTE10)
10140 #define S_DTU_RD_BYTE9 8
10141 #define M_DTU_RD_BYTE9 0xffU
10142 #define V_DTU_RD_BYTE9(x) ((x) << S_DTU_RD_BYTE9)
10143 #define G_DTU_RD_BYTE9(x) (((x) >> S_DTU_RD_BYTE9) & M_DTU_RD_BYTE9)
10145 #define S_DTU_RD_BYTE8 0
10146 #define M_DTU_RD_BYTE8 0xffU
10147 #define V_DTU_RD_BYTE8(x) ((x) << S_DTU_RD_BYTE8)
10148 #define G_DTU_RD_BYTE8(x) (((x) >> S_DTU_RD_BYTE8) & M_DTU_RD_BYTE8)
10150 #define A_MC_PCTL_DTURD3 0x6430
10152 #define S_DTU_RD_BYTE15 24
10153 #define M_DTU_RD_BYTE15 0xffU
10154 #define V_DTU_RD_BYTE15(x) ((x) << S_DTU_RD_BYTE15)
10155 #define G_DTU_RD_BYTE15(x) (((x) >> S_DTU_RD_BYTE15) & M_DTU_RD_BYTE15)
10157 #define S_DTU_RD_BYTE14 16
10158 #define M_DTU_RD_BYTE14 0xffU
10159 #define V_DTU_RD_BYTE14(x) ((x) << S_DTU_RD_BYTE14)
10160 #define G_DTU_RD_BYTE14(x) (((x) >> S_DTU_RD_BYTE14) & M_DTU_RD_BYTE14)
10162 #define S_DTU_RD_BYTE13 8
10163 #define M_DTU_RD_BYTE13 0xffU
10164 #define V_DTU_RD_BYTE13(x) ((x) << S_DTU_RD_BYTE13)
10165 #define G_DTU_RD_BYTE13(x) (((x) >> S_DTU_RD_BYTE13) & M_DTU_RD_BYTE13)
10167 #define S_DTU_RD_BYTE12 0
10168 #define M_DTU_RD_BYTE12 0xffU
10169 #define V_DTU_RD_BYTE12(x) ((x) << S_DTU_RD_BYTE12)
10170 #define G_DTU_RD_BYTE12(x) (((x) >> S_DTU_RD_BYTE12) & M_DTU_RD_BYTE12)
10172 #define A_MC_DTULFSRWD 0x6434
10173 #define A_MC_PCTL_DTULFSRRD 0x6438
10174 #define A_MC_PCTL_DTUEAF 0x643c
10176 #define S_EA_RANK 30
10177 #define M_EA_RANK 0x3U
10178 #define V_EA_RANK(x) ((x) << S_EA_RANK)
10179 #define G_EA_RANK(x) (((x) >> S_EA_RANK) & M_EA_RANK)
10181 #define S_EA_ROW 13
10182 #define M_EA_ROW 0x1ffffU
10183 #define V_EA_ROW(x) ((x) << S_EA_ROW)
10184 #define G_EA_ROW(x) (((x) >> S_EA_ROW) & M_EA_ROW)
10186 #define S_EA_BANK 10
10187 #define M_EA_BANK 0x7U
10188 #define V_EA_BANK(x) ((x) << S_EA_BANK)
10189 #define G_EA_BANK(x) (((x) >> S_EA_BANK) & M_EA_BANK)
10191 #define S_EA_COLUMN 0
10192 #define M_EA_COLUMN 0x3ffU
10193 #define V_EA_COLUMN(x) ((x) << S_EA_COLUMN)
10194 #define G_EA_COLUMN(x) (((x) >> S_EA_COLUMN) & M_EA_COLUMN)
10196 #define A_MC_PCTL_PHYPVTCFG 0x6500
10198 #define S_PVT_UPD_REQ_EN 15
10199 #define V_PVT_UPD_REQ_EN(x) ((x) << S_PVT_UPD_REQ_EN)
10200 #define F_PVT_UPD_REQ_EN V_PVT_UPD_REQ_EN(1U)
10202 #define S_PVT_UPD_TRIG_POL 14
10203 #define V_PVT_UPD_TRIG_POL(x) ((x) << S_PVT_UPD_TRIG_POL)
10204 #define F_PVT_UPD_TRIG_POL V_PVT_UPD_TRIG_POL(1U)
10206 #define S_PVT_UPD_TRIG_TYPE 12
10207 #define V_PVT_UPD_TRIG_TYPE(x) ((x) << S_PVT_UPD_TRIG_TYPE)
10208 #define F_PVT_UPD_TRIG_TYPE V_PVT_UPD_TRIG_TYPE(1U)
10210 #define S_PVT_UPD_DONE_POL 10
10211 #define V_PVT_UPD_DONE_POL(x) ((x) << S_PVT_UPD_DONE_POL)
10212 #define F_PVT_UPD_DONE_POL V_PVT_UPD_DONE_POL(1U)
10214 #define S_PVT_UPD_DONE_TYPE 8
10215 #define M_PVT_UPD_DONE_TYPE 0x3U
10216 #define V_PVT_UPD_DONE_TYPE(x) ((x) << S_PVT_UPD_DONE_TYPE)
10217 #define G_PVT_UPD_DONE_TYPE(x) (((x) >> S_PVT_UPD_DONE_TYPE) & M_PVT_UPD_DONE_TYPE)
10219 #define S_PHY_UPD_REQ_EN 7
10220 #define V_PHY_UPD_REQ_EN(x) ((x) << S_PHY_UPD_REQ_EN)
10221 #define F_PHY_UPD_REQ_EN V_PHY_UPD_REQ_EN(1U)
10223 #define S_PHY_UPD_TRIG_POL 6
10224 #define V_PHY_UPD_TRIG_POL(x) ((x) << S_PHY_UPD_TRIG_POL)
10225 #define F_PHY_UPD_TRIG_POL V_PHY_UPD_TRIG_POL(1U)
10227 #define S_PHY_UPD_TRIG_TYPE 4
10228 #define V_PHY_UPD_TRIG_TYPE(x) ((x) << S_PHY_UPD_TRIG_TYPE)
10229 #define F_PHY_UPD_TRIG_TYPE V_PHY_UPD_TRIG_TYPE(1U)
10231 #define S_PHY_UPD_DONE_POL 2
10232 #define V_PHY_UPD_DONE_POL(x) ((x) << S_PHY_UPD_DONE_POL)
10233 #define F_PHY_UPD_DONE_POL V_PHY_UPD_DONE_POL(1U)
10235 #define S_PHY_UPD_DONE_TYPE 0
10236 #define M_PHY_UPD_DONE_TYPE 0x3U
10237 #define V_PHY_UPD_DONE_TYPE(x) ((x) << S_PHY_UPD_DONE_TYPE)
10238 #define G_PHY_UPD_DONE_TYPE(x) (((x) >> S_PHY_UPD_DONE_TYPE) & M_PHY_UPD_DONE_TYPE)
10240 #define A_MC_PCTL_PHYPVTSTAT 0x6504
10242 #define S_I_PVT_UPD_TRIG 5
10243 #define V_I_PVT_UPD_TRIG(x) ((x) << S_I_PVT_UPD_TRIG)
10244 #define F_I_PVT_UPD_TRIG V_I_PVT_UPD_TRIG(1U)
10246 #define S_I_PVT_UPD_DONE 4
10247 #define V_I_PVT_UPD_DONE(x) ((x) << S_I_PVT_UPD_DONE)
10248 #define F_I_PVT_UPD_DONE V_I_PVT_UPD_DONE(1U)
10250 #define S_I_PHY_UPD_TRIG 1
10251 #define V_I_PHY_UPD_TRIG(x) ((x) << S_I_PHY_UPD_TRIG)
10252 #define F_I_PHY_UPD_TRIG V_I_PHY_UPD_TRIG(1U)
10254 #define S_I_PHY_UPD_DONE 0
10255 #define V_I_PHY_UPD_DONE(x) ((x) << S_I_PHY_UPD_DONE)
10256 #define F_I_PHY_UPD_DONE V_I_PHY_UPD_DONE(1U)
10258 #define A_MC_PCTL_PHYTUPDON 0x6508
10260 #define S_PHY_T_UPDON 0
10261 #define M_PHY_T_UPDON 0xffU
10262 #define V_PHY_T_UPDON(x) ((x) << S_PHY_T_UPDON)
10263 #define G_PHY_T_UPDON(x) (((x) >> S_PHY_T_UPDON) & M_PHY_T_UPDON)
10265 #define A_MC_PCTL_PHYTUPDDLY 0x650c
10267 #define S_PHY_T_UPDDLY 0
10268 #define M_PHY_T_UPDDLY 0xfU
10269 #define V_PHY_T_UPDDLY(x) ((x) << S_PHY_T_UPDDLY)
10270 #define G_PHY_T_UPDDLY(x) (((x) >> S_PHY_T_UPDDLY) & M_PHY_T_UPDDLY)
10272 #define A_MC_PCTL_PVTTUPON 0x6510
10274 #define S_PVT_T_UPDON 0
10275 #define M_PVT_T_UPDON 0xffU
10276 #define V_PVT_T_UPDON(x) ((x) << S_PVT_T_UPDON)
10277 #define G_PVT_T_UPDON(x) (((x) >> S_PVT_T_UPDON) & M_PVT_T_UPDON)
10279 #define A_MC_PCTL_PVTTUPDDLY 0x6514
10281 #define S_PVT_T_UPDDLY 0
10282 #define M_PVT_T_UPDDLY 0xfU
10283 #define V_PVT_T_UPDDLY(x) ((x) << S_PVT_T_UPDDLY)
10284 #define G_PVT_T_UPDDLY(x) (((x) >> S_PVT_T_UPDDLY) & M_PVT_T_UPDDLY)
10286 #define A_MC_PCTL_PHYPVTUPDI 0x6518
10288 #define S_PHYPVT_T_UPDI 0
10289 #define M_PHYPVT_T_UPDI 0xffU
10290 #define V_PHYPVT_T_UPDI(x) ((x) << S_PHYPVT_T_UPDI)
10291 #define G_PHYPVT_T_UPDI(x) (((x) >> S_PHYPVT_T_UPDI) & M_PHYPVT_T_UPDI)
10293 #define A_MC_PCTL_PHYIOCRV1 0x651c
10295 #define S_BYTE_OE_CTL 16
10296 #define M_BYTE_OE_CTL 0x3U
10297 #define V_BYTE_OE_CTL(x) ((x) << S_BYTE_OE_CTL)
10298 #define G_BYTE_OE_CTL(x) (((x) >> S_BYTE_OE_CTL) & M_BYTE_OE_CTL)
10300 #define S_DYN_SOC_ODT_ALAT 12
10301 #define M_DYN_SOC_ODT_ALAT 0xfU
10302 #define V_DYN_SOC_ODT_ALAT(x) ((x) << S_DYN_SOC_ODT_ALAT)
10303 #define G_DYN_SOC_ODT_ALAT(x) (((x) >> S_DYN_SOC_ODT_ALAT) & M_DYN_SOC_ODT_ALAT)
10305 #define S_DYN_SOC_ODT_ATEN 8
10306 #define M_DYN_SOC_ODT_ATEN 0x3U
10307 #define V_DYN_SOC_ODT_ATEN(x) ((x) << S_DYN_SOC_ODT_ATEN)
10308 #define G_DYN_SOC_ODT_ATEN(x) (((x) >> S_DYN_SOC_ODT_ATEN) & M_DYN_SOC_ODT_ATEN)
10310 #define S_DYN_SOC_ODT 2
10311 #define V_DYN_SOC_ODT(x) ((x) << S_DYN_SOC_ODT)
10312 #define F_DYN_SOC_ODT V_DYN_SOC_ODT(1U)
10314 #define S_SOC_ODT_EN 0
10315 #define V_SOC_ODT_EN(x) ((x) << S_SOC_ODT_EN)
10316 #define F_SOC_ODT_EN V_SOC_ODT_EN(1U)
10318 #define A_MC_PCTL_PHYTUPDWAIT 0x6520
10320 #define S_PHY_T_UPDWAIT 0
10321 #define M_PHY_T_UPDWAIT 0x3fU
10322 #define V_PHY_T_UPDWAIT(x) ((x) << S_PHY_T_UPDWAIT)
10323 #define G_PHY_T_UPDWAIT(x) (((x) >> S_PHY_T_UPDWAIT) & M_PHY_T_UPDWAIT)
10325 #define A_MC_PCTL_PVTTUPDWAIT 0x6524
10327 #define S_PVT_T_UPDWAIT 0
10328 #define M_PVT_T_UPDWAIT 0x3fU
10329 #define V_PVT_T_UPDWAIT(x) ((x) << S_PVT_T_UPDWAIT)
10330 #define G_PVT_T_UPDWAIT(x) (((x) >> S_PVT_T_UPDWAIT) & M_PVT_T_UPDWAIT)
10332 #define A_MC_DDR3PHYAC_GCR 0x6a00
10335 #define M_WLRANK 0x3U
10336 #define V_WLRANK(x) ((x) << S_WLRANK)
10337 #define G_WLRANK(x) (((x) >> S_WLRANK) & M_WLRANK)
10340 #define M_FDEPTH 0x3U
10341 #define V_FDEPTH(x) ((x) << S_FDEPTH)
10342 #define G_FDEPTH(x) (((x) >> S_FDEPTH) & M_FDEPTH)
10344 #define S_LPFDEPTH 4
10345 #define M_LPFDEPTH 0x3U
10346 #define V_LPFDEPTH(x) ((x) << S_LPFDEPTH)
10347 #define G_LPFDEPTH(x) (((x) >> S_LPFDEPTH) & M_LPFDEPTH)
10350 #define V_LPFEN(x) ((x) << S_LPFEN)
10351 #define F_LPFEN V_LPFEN(1U)
10354 #define V_WL(x) ((x) << S_WL)
10355 #define F_WL V_WL(1U)
10358 #define V_CAL(x) ((x) << S_CAL)
10359 #define F_CAL V_CAL(1U)
10362 #define V_MDLEN(x) ((x) << S_MDLEN)
10363 #define F_MDLEN V_MDLEN(1U)
10365 #define A_MC_DDR3PHYAC_RCR0 0x6a04
10368 #define V_OCPONR(x) ((x) << S_OCPONR)
10369 #define F_OCPONR V_OCPONR(1U)
10372 #define V_OCPOND(x) ((x) << S_OCPOND)
10373 #define F_OCPOND V_OCPOND(1U)
10376 #define V_OCOEN(x) ((x) << S_OCOEN)
10377 #define F_OCOEN V_OCOEN(1U)
10379 #define S_CKEPONR 5
10380 #define V_CKEPONR(x) ((x) << S_CKEPONR)
10381 #define F_CKEPONR V_CKEPONR(1U)
10383 #define S_CKEPOND 4
10384 #define V_CKEPOND(x) ((x) << S_CKEPOND)
10385 #define F_CKEPOND V_CKEPOND(1U)
10388 #define V_CKEOEN(x) ((x) << S_CKEOEN)
10389 #define F_CKEOEN V_CKEOEN(1U)
10392 #define V_CKPONR(x) ((x) << S_CKPONR)
10393 #define F_CKPONR V_CKPONR(1U)
10396 #define V_CKPOND(x) ((x) << S_CKPOND)
10397 #define F_CKPOND V_CKPOND(1U)
10400 #define V_CKOEN(x) ((x) << S_CKOEN)
10401 #define F_CKOEN V_CKOEN(1U)
10403 #define A_MC_DDR3PHYAC_ACCR 0x6a14
10406 #define V_ACPONR(x) ((x) << S_ACPONR)
10407 #define F_ACPONR V_ACPONR(1U)
10410 #define V_ACPOND(x) ((x) << S_ACPOND)
10411 #define F_ACPOND V_ACPOND(1U)
10414 #define V_ACOEN(x) ((x) << S_ACOEN)
10415 #define F_ACOEN V_ACOEN(1U)
10417 #define S_CK5PONR 5
10418 #define V_CK5PONR(x) ((x) << S_CK5PONR)
10419 #define F_CK5PONR V_CK5PONR(1U)
10421 #define S_CK5POND 4
10422 #define V_CK5POND(x) ((x) << S_CK5POND)
10423 #define F_CK5POND V_CK5POND(1U)
10426 #define V_CK5OEN(x) ((x) << S_CK5OEN)
10427 #define F_CK5OEN V_CK5OEN(1U)
10429 #define S_CK4PONR 2
10430 #define V_CK4PONR(x) ((x) << S_CK4PONR)
10431 #define F_CK4PONR V_CK4PONR(1U)
10433 #define S_CK4POND 1
10434 #define V_CK4POND(x) ((x) << S_CK4POND)
10435 #define F_CK4POND V_CK4POND(1U)
10438 #define V_CK4OEN(x) ((x) << S_CK4OEN)
10439 #define F_CK4OEN V_CK4OEN(1U)
10441 #define A_MC_DDR3PHYAC_GSR 0x6a18
10444 #define V_WLERR(x) ((x) << S_WLERR)
10445 #define F_WLERR V_WLERR(1U)
10448 #define V_INIT(x) ((x) << S_INIT)
10449 #define F_INIT V_INIT(1U)
10452 #define V_ACCAL(x) ((x) << S_ACCAL)
10453 #define F_ACCAL V_ACCAL(1U)
10455 #define A_MC_DDR3PHYAC_ECSR 0x6a1c
10458 #define V_WLDEC(x) ((x) << S_WLDEC)
10459 #define F_WLDEC V_WLDEC(1U)
10462 #define V_WLINC(x) ((x) << S_WLINC)
10463 #define F_WLINC V_WLINC(1U)
10465 #define A_MC_DDR3PHYAC_OCSR 0x6a20
10466 #define A_MC_DDR3PHYAC_MDIPR 0x6a24
10469 #define M_PRD 0x3ffU
10470 #define V_PRD(x) ((x) << S_PRD)
10471 #define G_PRD(x) (((x) >> S_PRD) & M_PRD)
10473 #define A_MC_DDR3PHYAC_MDTPR 0x6a28
10474 #define A_MC_DDR3PHYAC_MDPPR0 0x6a2c
10475 #define A_MC_DDR3PHYAC_MDPPR1 0x6a30
10476 #define A_MC_DDR3PHYAC_PMBDR0 0x6a34
10478 #define S_DFLTDLY 0
10479 #define M_DFLTDLY 0x7fU
10480 #define V_DFLTDLY(x) ((x) << S_DFLTDLY)
10481 #define G_DFLTDLY(x) (((x) >> S_DFLTDLY) & M_DFLTDLY)
10483 #define A_MC_DDR3PHYAC_PMBDR1 0x6a38
10484 #define A_MC_DDR3PHYAC_ACR 0x6a60
10487 #define V_TSEL(x) ((x) << S_TSEL)
10488 #define F_TSEL V_TSEL(1U)
10491 #define M_ISEL 0x3U
10492 #define V_ISEL(x) ((x) << S_ISEL)
10493 #define G_ISEL(x) (((x) >> S_ISEL) & M_ISEL)
10496 #define V_CALBYP(x) ((x) << S_CALBYP)
10497 #define F_CALBYP V_CALBYP(1U)
10499 #define S_SDRSELINV 1
10500 #define V_SDRSELINV(x) ((x) << S_SDRSELINV)
10501 #define F_SDRSELINV V_SDRSELINV(1U)
10504 #define V_CKINV(x) ((x) << S_CKINV)
10505 #define F_CKINV V_CKINV(1U)
10507 #define A_MC_DDR3PHYAC_PSCR 0x6a64
10510 #define M_PSCALE 0x3ffU
10511 #define V_PSCALE(x) ((x) << S_PSCALE)
10512 #define G_PSCALE(x) (((x) >> S_PSCALE) & M_PSCALE)
10514 #define A_MC_DDR3PHYAC_PRCR 0x6a68
10516 #define S_PHYINIT 9
10517 #define V_PHYINIT(x) ((x) << S_PHYINIT)
10518 #define F_PHYINIT V_PHYINIT(1U)
10520 #define S_PHYHRST 7
10521 #define V_PHYHRST(x) ((x) << S_PHYHRST)
10522 #define F_PHYHRST V_PHYHRST(1U)
10524 #define S_RSTCLKS 3
10525 #define M_RSTCLKS 0xfU
10526 #define V_RSTCLKS(x) ((x) << S_RSTCLKS)
10527 #define G_RSTCLKS(x) (((x) >> S_RSTCLKS) & M_RSTCLKS)
10530 #define V_PLLPD(x) ((x) << S_PLLPD)
10531 #define F_PLLPD V_PLLPD(1U)
10534 #define V_PLLRST(x) ((x) << S_PLLRST)
10535 #define F_PLLRST V_PLLRST(1U)
10538 #define V_PHYRST(x) ((x) << S_PHYRST)
10539 #define F_PHYRST V_PHYRST(1U)
10541 #define A_MC_DDR3PHYAC_PLLCR0 0x6a6c
10543 #define S_RSTCXKS 4
10544 #define M_RSTCXKS 0x1fU
10545 #define V_RSTCXKS(x) ((x) << S_RSTCXKS)
10546 #define G_RSTCXKS(x) (((x) >> S_RSTCXKS) & M_RSTCXKS)
10549 #define V_ICPSEL(x) ((x) << S_ICPSEL)
10550 #define F_ICPSEL V_ICPSEL(1U)
10553 #define M_TESTA 0x7U
10554 #define V_TESTA(x) ((x) << S_TESTA)
10555 #define G_TESTA(x) (((x) >> S_TESTA) & M_TESTA)
10557 #define A_MC_DDR3PHYAC_PLLCR1 0x6a70
10560 #define V_BYPASS(x) ((x) << S_BYPASS)
10561 #define F_BYPASS V_BYPASS(1U)
10564 #define M_BDIV 0x3U
10565 #define V_BDIV(x) ((x) << S_BDIV)
10566 #define G_BDIV(x) (((x) >> S_BDIV) & M_BDIV)
10569 #define M_TESTD 0x7U
10570 #define V_TESTD(x) ((x) << S_TESTD)
10571 #define G_TESTD(x) (((x) >> S_TESTD) & M_TESTD)
10573 #define A_MC_DDR3PHYAC_CLKENR 0x6a78
10575 #define S_CKCLKEN 3
10576 #define M_CKCLKEN 0x3fU
10577 #define V_CKCLKEN(x) ((x) << S_CKCLKEN)
10578 #define G_CKCLKEN(x) (((x) >> S_CKCLKEN) & M_CKCLKEN)
10580 #define S_HDRCLKEN 2
10581 #define V_HDRCLKEN(x) ((x) << S_HDRCLKEN)
10582 #define F_HDRCLKEN V_HDRCLKEN(1U)
10584 #define S_SDRCLKEN 1
10585 #define V_SDRCLKEN(x) ((x) << S_SDRCLKEN)
10586 #define F_SDRCLKEN V_SDRCLKEN(1U)
10588 #define S_DDRCLKEN 0
10589 #define V_DDRCLKEN(x) ((x) << S_DDRCLKEN)
10590 #define F_DDRCLKEN V_DDRCLKEN(1U)
10592 #define A_MC_DDR3PHYDATX8_GCR 0x6b00
10595 #define V_PONR(x) ((x) << S_PONR)
10596 #define F_PONR V_PONR(1U)
10599 #define V_POND(x) ((x) << S_POND)
10600 #define F_POND V_POND(1U)
10603 #define V_RDBDVT(x) ((x) << S_RDBDVT)
10604 #define F_RDBDVT V_RDBDVT(1U)
10607 #define V_WDBDVT(x) ((x) << S_WDBDVT)
10608 #define F_WDBDVT V_WDBDVT(1U)
10611 #define V_RDSDVT(x) ((x) << S_RDSDVT)
10612 #define F_RDSDVT V_RDSDVT(1U)
10615 #define V_WDSDVT(x) ((x) << S_WDSDVT)
10616 #define F_WDSDVT V_WDSDVT(1U)
10619 #define V_WLSDVT(x) ((x) << S_WLSDVT)
10620 #define F_WLSDVT V_WLSDVT(1U)
10622 #define A_MC_DDR3PHYDATX8_WDSDR 0x6b04
10624 #define S_WDSDR_DLY 0
10625 #define M_WDSDR_DLY 0x3ffU
10626 #define V_WDSDR_DLY(x) ((x) << S_WDSDR_DLY)
10627 #define G_WDSDR_DLY(x) (((x) >> S_WDSDR_DLY) & M_WDSDR_DLY)
10629 #define A_MC_DDR3PHYDATX8_WLDPR 0x6b08
10630 #define A_MC_DDR3PHYDATX8_WLDR 0x6b0c
10633 #define M_WL_DLY 0x3ffU
10634 #define V_WL_DLY(x) ((x) << S_WL_DLY)
10635 #define G_WL_DLY(x) (((x) >> S_WL_DLY) & M_WL_DLY)
10637 #define A_MC_DDR3PHYDATX8_WDBDR0 0x6b1c
10640 #define M_DLY 0x7fU
10641 #define V_DLY(x) ((x) << S_DLY)
10642 #define G_DLY(x) (((x) >> S_DLY) & M_DLY)
10644 #define A_MC_DDR3PHYDATX8_WDBDR1 0x6b20
10645 #define A_MC_DDR3PHYDATX8_WDBDR2 0x6b24
10646 #define A_MC_DDR3PHYDATX8_WDBDR3 0x6b28
10647 #define A_MC_DDR3PHYDATX8_WDBDR4 0x6b2c
10648 #define A_MC_DDR3PHYDATX8_WDBDR5 0x6b30
10649 #define A_MC_DDR3PHYDATX8_WDBDR6 0x6b34
10650 #define A_MC_DDR3PHYDATX8_WDBDR7 0x6b38
10651 #define A_MC_DDR3PHYDATX8_WDBDR8 0x6b3c
10652 #define A_MC_DDR3PHYDATX8_WDBDMR 0x6b40
10655 #define M_MAXDLY 0x7fU
10656 #define V_MAXDLY(x) ((x) << S_MAXDLY)
10657 #define G_MAXDLY(x) (((x) >> S_MAXDLY) & M_MAXDLY)
10659 #define A_MC_DDR3PHYDATX8_RDSDR 0x6b44
10661 #define S_RDSDR_DLY 0
10662 #define M_RDSDR_DLY 0x3ffU
10663 #define V_RDSDR_DLY(x) ((x) << S_RDSDR_DLY)
10664 #define G_RDSDR_DLY(x) (((x) >> S_RDSDR_DLY) & M_RDSDR_DLY)
10666 #define A_MC_DDR3PHYDATX8_RDBDR0 0x6b48
10667 #define A_MC_DDR3PHYDATX8_RDBDR1 0x6b4c
10668 #define A_MC_DDR3PHYDATX8_RDBDR2 0x6b50
10669 #define A_MC_DDR3PHYDATX8_RDBDR3 0x6b54
10670 #define A_MC_DDR3PHYDATX8_RDBDR4 0x6b58
10671 #define A_MC_DDR3PHYDATX8_RDBDR5 0x6b5c
10672 #define A_MC_DDR3PHYDATX8_RDBDR6 0x6b60
10673 #define A_MC_DDR3PHYDATX8_RDBDR7 0x6b64
10674 #define A_MC_DDR3PHYDATX8_RDBDMR 0x6b68
10675 #define A_MC_DDR3PHYDATX8_PMBDR0 0x6b6c
10676 #define A_MC_DDR3PHYDATX8_PMBDR1 0x6b70
10677 #define A_MC_DDR3PHYDATX8_PMBDR2 0x6b74
10678 #define A_MC_DDR3PHYDATX8_PMBDR3 0x6b78
10679 #define A_MC_DDR3PHYDATX8_WDBDPR 0x6b7c
10682 #define M_DP_DLY 0x1ffU
10683 #define V_DP_DLY(x) ((x) << S_DP_DLY)
10684 #define G_DP_DLY(x) (((x) >> S_DP_DLY) & M_DP_DLY)
10686 #define A_MC_DDR3PHYDATX8_RDBDPR 0x6b80
10687 #define A_MC_DDR3PHYDATX8_GSR 0x6b84
10690 #define V_WLDONE(x) ((x) << S_WLDONE)
10691 #define F_WLDONE V_WLDONE(1U)
10694 #define V_WLCAL(x) ((x) << S_WLCAL)
10695 #define F_WLCAL V_WLCAL(1U)
10698 #define V_READ(x) ((x) << S_READ)
10699 #define F_READ V_READ(1U)
10701 #define S_RDQSCAL 0
10702 #define V_RDQSCAL(x) ((x) << S_RDQSCAL)
10703 #define F_RDQSCAL V_RDQSCAL(1U)
10705 #define A_MC_DDR3PHYDATX8_ACR 0x6bf0
10707 #define S_PHYHSRST 9
10708 #define V_PHYHSRST(x) ((x) << S_PHYHSRST)
10709 #define F_PHYHSRST V_PHYHSRST(1U)
10712 #define V_WLSTEP(x) ((x) << S_WLSTEP)
10713 #define F_WLSTEP V_WLSTEP(1U)
10715 #define S_SDR_SEL_INV 2
10716 #define V_SDR_SEL_INV(x) ((x) << S_SDR_SEL_INV)
10717 #define F_SDR_SEL_INV V_SDR_SEL_INV(1U)
10719 #define S_DDRSELINV 1
10720 #define V_DDRSELINV(x) ((x) << S_DDRSELINV)
10721 #define F_DDRSELINV V_DDRSELINV(1U)
10724 #define V_DSINV(x) ((x) << S_DSINV)
10725 #define F_DSINV V_DSINV(1U)
10727 #define A_MC_DDR3PHYDATX8_RSR 0x6bf4
10729 #define S_WLRANKSEL 9
10730 #define V_WLRANKSEL(x) ((x) << S_WLRANKSEL)
10731 #define F_WLRANKSEL V_WLRANKSEL(1U)
10734 #define M_RANK 0x3U
10735 #define V_RANK(x) ((x) << S_RANK)
10736 #define G_RANK(x) (((x) >> S_RANK) & M_RANK)
10738 #define A_MC_DDR3PHYDATX8_CLKENR 0x6bf8
10741 #define M_DTOSEL 0x3U
10742 #define V_DTOSEL(x) ((x) << S_DTOSEL)
10743 #define G_DTOSEL(x) (((x) >> S_DTOSEL) & M_DTOSEL)
10745 #define A_MC_PVT_REG_CALIBRATE_CTL 0x7400
10746 #define A_MC_PVT_REG_UPDATE_CTL 0x7404
10747 #define A_MC_PVT_REG_LAST_MEASUREMENT 0x7408
10748 #define A_MC_PVT_REG_DRVN 0x740c
10749 #define A_MC_PVT_REG_DRVP 0x7410
10750 #define A_MC_PVT_REG_TERMN 0x7414
10751 #define A_MC_PVT_REG_TERMP 0x7418
10752 #define A_MC_PVT_REG_THRESHOLD 0x741c
10753 #define A_MC_PVT_REG_IN_TERMP 0x7420
10754 #define A_MC_PVT_REG_IN_TERMN 0x7424
10755 #define A_MC_PVT_REG_IN_DRVP 0x7428
10756 #define A_MC_PVT_REG_IN_DRVN 0x742c
10757 #define A_MC_PVT_REG_OUT_TERMP 0x7430
10758 #define A_MC_PVT_REG_OUT_TERMN 0x7434
10759 #define A_MC_PVT_REG_OUT_DRVP 0x7438
10760 #define A_MC_PVT_REG_OUT_DRVN 0x743c
10761 #define A_MC_PVT_REG_HISTORY_TERMP 0x7440
10762 #define A_MC_PVT_REG_HISTORY_TERMN 0x7444
10763 #define A_MC_PVT_REG_HISTORY_DRVP 0x7448
10764 #define A_MC_PVT_REG_HISTORY_DRVN 0x744c
10765 #define A_MC_PVT_REG_SAMPLE_WAIT_CLKS 0x7450
10766 #define A_MC_DDRPHY_RST_CTRL 0x7500
10768 #define S_DDRIO_ENABLE 1
10769 #define V_DDRIO_ENABLE(x) ((x) << S_DDRIO_ENABLE)
10770 #define F_DDRIO_ENABLE V_DDRIO_ENABLE(1U)
10772 #define S_PHY_RST_N 0
10773 #define V_PHY_RST_N(x) ((x) << S_PHY_RST_N)
10774 #define F_PHY_RST_N V_PHY_RST_N(1U)
10776 #define A_MC_PERFORMANCE_CTRL 0x7504
10778 #define S_STALL_CHK_BIT 2
10779 #define V_STALL_CHK_BIT(x) ((x) << S_STALL_CHK_BIT)
10780 #define F_STALL_CHK_BIT V_STALL_CHK_BIT(1U)
10782 #define S_DDR3_BRC_MODE 1
10783 #define V_DDR3_BRC_MODE(x) ((x) << S_DDR3_BRC_MODE)
10784 #define F_DDR3_BRC_MODE V_DDR3_BRC_MODE(1U)
10786 #define S_RMW_PERF_CTRL 0
10787 #define V_RMW_PERF_CTRL(x) ((x) << S_RMW_PERF_CTRL)
10788 #define F_RMW_PERF_CTRL V_RMW_PERF_CTRL(1U)
10790 #define A_MC_ECC_CTRL 0x7508
10792 #define S_ECC_BYPASS_BIST 1
10793 #define V_ECC_BYPASS_BIST(x) ((x) << S_ECC_BYPASS_BIST)
10794 #define F_ECC_BYPASS_BIST V_ECC_BYPASS_BIST(1U)
10796 #define S_ECC_DISABLE 0
10797 #define V_ECC_DISABLE(x) ((x) << S_ECC_DISABLE)
10798 #define F_ECC_DISABLE V_ECC_DISABLE(1U)
10800 #define A_MC_PAR_ENABLE 0x750c
10802 #define S_ECC_UE_PAR_ENABLE 3
10803 #define V_ECC_UE_PAR_ENABLE(x) ((x) << S_ECC_UE_PAR_ENABLE)
10804 #define F_ECC_UE_PAR_ENABLE V_ECC_UE_PAR_ENABLE(1U)
10806 #define S_ECC_CE_PAR_ENABLE 2
10807 #define V_ECC_CE_PAR_ENABLE(x) ((x) << S_ECC_CE_PAR_ENABLE)
10808 #define F_ECC_CE_PAR_ENABLE V_ECC_CE_PAR_ENABLE(1U)
10810 #define S_PERR_REG_INT_ENABLE 1
10811 #define V_PERR_REG_INT_ENABLE(x) ((x) << S_PERR_REG_INT_ENABLE)
10812 #define F_PERR_REG_INT_ENABLE V_PERR_REG_INT_ENABLE(1U)
10814 #define S_PERR_BLK_INT_ENABLE 0
10815 #define V_PERR_BLK_INT_ENABLE(x) ((x) << S_PERR_BLK_INT_ENABLE)
10816 #define F_PERR_BLK_INT_ENABLE V_PERR_BLK_INT_ENABLE(1U)
10818 #define A_MC_PAR_CAUSE 0x7510
10820 #define S_ECC_UE_PAR_CAUSE 3
10821 #define V_ECC_UE_PAR_CAUSE(x) ((x) << S_ECC_UE_PAR_CAUSE)
10822 #define F_ECC_UE_PAR_CAUSE V_ECC_UE_PAR_CAUSE(1U)
10824 #define S_ECC_CE_PAR_CAUSE 2
10825 #define V_ECC_CE_PAR_CAUSE(x) ((x) << S_ECC_CE_PAR_CAUSE)
10826 #define F_ECC_CE_PAR_CAUSE V_ECC_CE_PAR_CAUSE(1U)
10828 #define S_FIFOR_PAR_CAUSE 1
10829 #define V_FIFOR_PAR_CAUSE(x) ((x) << S_FIFOR_PAR_CAUSE)
10830 #define F_FIFOR_PAR_CAUSE V_FIFOR_PAR_CAUSE(1U)
10832 #define S_RDATA_FIFOR_PAR_CAUSE 0
10833 #define V_RDATA_FIFOR_PAR_CAUSE(x) ((x) << S_RDATA_FIFOR_PAR_CAUSE)
10834 #define F_RDATA_FIFOR_PAR_CAUSE V_RDATA_FIFOR_PAR_CAUSE(1U)
10836 #define A_MC_INT_ENABLE 0x7514
10838 #define S_ECC_UE_INT_ENABLE 2
10839 #define V_ECC_UE_INT_ENABLE(x) ((x) << S_ECC_UE_INT_ENABLE)
10840 #define F_ECC_UE_INT_ENABLE V_ECC_UE_INT_ENABLE(1U)
10842 #define S_ECC_CE_INT_ENABLE 1
10843 #define V_ECC_CE_INT_ENABLE(x) ((x) << S_ECC_CE_INT_ENABLE)
10844 #define F_ECC_CE_INT_ENABLE V_ECC_CE_INT_ENABLE(1U)
10846 #define S_PERR_INT_ENABLE 0
10847 #define V_PERR_INT_ENABLE(x) ((x) << S_PERR_INT_ENABLE)
10848 #define F_PERR_INT_ENABLE V_PERR_INT_ENABLE(1U)
10850 #define A_MC_INT_CAUSE 0x7518
10852 #define S_ECC_UE_INT_CAUSE 2
10853 #define V_ECC_UE_INT_CAUSE(x) ((x) << S_ECC_UE_INT_CAUSE)
10854 #define F_ECC_UE_INT_CAUSE V_ECC_UE_INT_CAUSE(1U)
10856 #define S_ECC_CE_INT_CAUSE 1
10857 #define V_ECC_CE_INT_CAUSE(x) ((x) << S_ECC_CE_INT_CAUSE)
10858 #define F_ECC_CE_INT_CAUSE V_ECC_CE_INT_CAUSE(1U)
10860 #define S_PERR_INT_CAUSE 0
10861 #define V_PERR_INT_CAUSE(x) ((x) << S_PERR_INT_CAUSE)
10862 #define F_PERR_INT_CAUSE V_PERR_INT_CAUSE(1U)
10864 #define A_MC_ECC_STATUS 0x751c
10866 #define S_ECC_CECNT 16
10867 #define M_ECC_CECNT 0xffffU
10868 #define V_ECC_CECNT(x) ((x) << S_ECC_CECNT)
10869 #define G_ECC_CECNT(x) (((x) >> S_ECC_CECNT) & M_ECC_CECNT)
10871 #define S_ECC_UECNT 0
10872 #define M_ECC_UECNT 0xffffU
10873 #define V_ECC_UECNT(x) ((x) << S_ECC_UECNT)
10874 #define G_ECC_UECNT(x) (((x) >> S_ECC_UECNT) & M_ECC_UECNT)
10876 #define A_MC_PHY_CTRL 0x7520
10878 #define S_CTLPHYRR 0
10879 #define V_CTLPHYRR(x) ((x) << S_CTLPHYRR)
10880 #define F_CTLPHYRR V_CTLPHYRR(1U)
10882 #define A_MC_STATIC_CFG_STATUS 0x7524
10884 #define S_STATIC_MODE 9
10885 #define V_STATIC_MODE(x) ((x) << S_STATIC_MODE)
10886 #define F_STATIC_MODE V_STATIC_MODE(1U)
10888 #define S_STATIC_DEN 6
10889 #define M_STATIC_DEN 0x7U
10890 #define V_STATIC_DEN(x) ((x) << S_STATIC_DEN)
10891 #define G_STATIC_DEN(x) (((x) >> S_STATIC_DEN) & M_STATIC_DEN)
10893 #define S_STATIC_ORG 5
10894 #define V_STATIC_ORG(x) ((x) << S_STATIC_ORG)
10895 #define F_STATIC_ORG V_STATIC_ORG(1U)
10897 #define S_STATIC_RKS 4
10898 #define V_STATIC_RKS(x) ((x) << S_STATIC_RKS)
10899 #define F_STATIC_RKS V_STATIC_RKS(1U)
10901 #define S_STATIC_WIDTH 1
10902 #define M_STATIC_WIDTH 0x7U
10903 #define V_STATIC_WIDTH(x) ((x) << S_STATIC_WIDTH)
10904 #define G_STATIC_WIDTH(x) (((x) >> S_STATIC_WIDTH) & M_STATIC_WIDTH)
10906 #define S_STATIC_SLOW 0
10907 #define V_STATIC_SLOW(x) ((x) << S_STATIC_SLOW)
10908 #define F_STATIC_SLOW V_STATIC_SLOW(1U)
10910 #define A_MC_CORE_PCTL_STAT 0x7528
10912 #define S_PCTL_ACCESS_STAT 0
10913 #define M_PCTL_ACCESS_STAT 0x7U
10914 #define V_PCTL_ACCESS_STAT(x) ((x) << S_PCTL_ACCESS_STAT)
10915 #define G_PCTL_ACCESS_STAT(x) (((x) >> S_PCTL_ACCESS_STAT) & M_PCTL_ACCESS_STAT)
10917 #define A_MC_DEBUG_CNT 0x752c
10919 #define S_WDATA_OCNT 8
10920 #define M_WDATA_OCNT 0x1fU
10921 #define V_WDATA_OCNT(x) ((x) << S_WDATA_OCNT)
10922 #define G_WDATA_OCNT(x) (((x) >> S_WDATA_OCNT) & M_WDATA_OCNT)
10924 #define S_RDATA_OCNT 0
10925 #define M_RDATA_OCNT 0x1fU
10926 #define V_RDATA_OCNT(x) ((x) << S_RDATA_OCNT)
10927 #define G_RDATA_OCNT(x) (((x) >> S_RDATA_OCNT) & M_RDATA_OCNT)
10929 #define A_MC_BONUS 0x7530
10930 #define A_MC_BIST_CMD 0x7600
10932 #define S_START_BIST 31
10933 #define V_START_BIST(x) ((x) << S_START_BIST)
10934 #define F_START_BIST V_START_BIST(1U)
10936 #define S_BIST_CMD_GAP 8
10937 #define M_BIST_CMD_GAP 0xffU
10938 #define V_BIST_CMD_GAP(x) ((x) << S_BIST_CMD_GAP)
10939 #define G_BIST_CMD_GAP(x) (((x) >> S_BIST_CMD_GAP) & M_BIST_CMD_GAP)
10941 #define S_BIST_OPCODE 0
10942 #define M_BIST_OPCODE 0x3U
10943 #define V_BIST_OPCODE(x) ((x) << S_BIST_OPCODE)
10944 #define G_BIST_OPCODE(x) (((x) >> S_BIST_OPCODE) & M_BIST_OPCODE)
10946 #define A_MC_BIST_CMD_ADDR 0x7604
10947 #define A_MC_BIST_CMD_LEN 0x7608
10948 #define A_MC_BIST_DATA_PATTERN 0x760c
10950 #define S_BIST_DATA_TYPE 0
10951 #define M_BIST_DATA_TYPE 0xfU
10952 #define V_BIST_DATA_TYPE(x) ((x) << S_BIST_DATA_TYPE)
10953 #define G_BIST_DATA_TYPE(x) (((x) >> S_BIST_DATA_TYPE) & M_BIST_DATA_TYPE)
10955 #define A_MC_BIST_USER_WDATA0 0x7614
10956 #define A_MC_BIST_USER_WDATA1 0x7618
10957 #define A_MC_BIST_USER_WDATA2 0x761c
10959 #define S_USER_DATA2 0
10960 #define M_USER_DATA2 0xffU
10961 #define V_USER_DATA2(x) ((x) << S_USER_DATA2)
10962 #define G_USER_DATA2(x) (((x) >> S_USER_DATA2) & M_USER_DATA2)
10964 #define A_MC_BIST_NUM_ERR 0x7680
10965 #define A_MC_BIST_ERR_FIRST_ADDR 0x7684
10966 #define A_MC_BIST_STATUS_RDATA 0x7688
10968 /* registers for module MA */
10969 #define MA_BASE_ADDR 0x7700
10971 #define A_MA_CLIENT0_RD_LATENCY_THRESHOLD 0x7700
10973 #define S_THRESHOLD1 17
10974 #define M_THRESHOLD1 0x7fffU
10975 #define V_THRESHOLD1(x) ((x) << S_THRESHOLD1)
10976 #define G_THRESHOLD1(x) (((x) >> S_THRESHOLD1) & M_THRESHOLD1)
10978 #define S_THRESHOLD1_EN 16
10979 #define V_THRESHOLD1_EN(x) ((x) << S_THRESHOLD1_EN)
10980 #define F_THRESHOLD1_EN V_THRESHOLD1_EN(1U)
10982 #define S_THRESHOLD0 1
10983 #define M_THRESHOLD0 0x7fffU
10984 #define V_THRESHOLD0(x) ((x) << S_THRESHOLD0)
10985 #define G_THRESHOLD0(x) (((x) >> S_THRESHOLD0) & M_THRESHOLD0)
10987 #define S_THRESHOLD0_EN 0
10988 #define V_THRESHOLD0_EN(x) ((x) << S_THRESHOLD0_EN)
10989 #define F_THRESHOLD0_EN V_THRESHOLD0_EN(1U)
10991 #define A_MA_CLIENT0_WR_LATENCY_THRESHOLD 0x7704
10992 #define A_MA_CLIENT1_RD_LATENCY_THRESHOLD 0x7708
10993 #define A_MA_CLIENT1_WR_LATENCY_THRESHOLD 0x770c
10994 #define A_MA_CLIENT2_RD_LATENCY_THRESHOLD 0x7710
10995 #define A_MA_CLIENT2_WR_LATENCY_THRESHOLD 0x7714
10996 #define A_MA_CLIENT3_RD_LATENCY_THRESHOLD 0x7718
10997 #define A_MA_CLIENT3_WR_LATENCY_THRESHOLD 0x771c
10998 #define A_MA_CLIENT4_RD_LATENCY_THRESHOLD 0x7720
10999 #define A_MA_CLIENT4_WR_LATENCY_THRESHOLD 0x7724
11000 #define A_MA_CLIENT5_RD_LATENCY_THRESHOLD 0x7728
11001 #define A_MA_CLIENT5_WR_LATENCY_THRESHOLD 0x772c
11002 #define A_MA_CLIENT6_RD_LATENCY_THRESHOLD 0x7730
11003 #define A_MA_CLIENT6_WR_LATENCY_THRESHOLD 0x7734
11004 #define A_MA_CLIENT7_RD_LATENCY_THRESHOLD 0x7738
11005 #define A_MA_CLIENT7_WR_LATENCY_THRESHOLD 0x773c
11006 #define A_MA_CLIENT8_RD_LATENCY_THRESHOLD 0x7740
11007 #define A_MA_CLIENT8_WR_LATENCY_THRESHOLD 0x7744
11008 #define A_MA_CLIENT9_RD_LATENCY_THRESHOLD 0x7748
11009 #define A_MA_CLIENT9_WR_LATENCY_THRESHOLD 0x774c
11010 #define A_MA_CLIENT10_RD_LATENCY_THRESHOLD 0x7750
11011 #define A_MA_CLIENT10_WR_LATENCY_THRESHOLD 0x7754
11012 #define A_MA_CLIENT11_RD_LATENCY_THRESHOLD 0x7758
11013 #define A_MA_CLIENT11_WR_LATENCY_THRESHOLD 0x775c
11014 #define A_MA_CLIENT12_RD_LATENCY_THRESHOLD 0x7760
11015 #define A_MA_CLIENT12_WR_LATENCY_THRESHOLD 0x7764
11016 #define A_MA_SGE_TH0_DEBUG_CNT 0x7768
11018 #define S_DBG_READ_DATA_CNT 24
11019 #define M_DBG_READ_DATA_CNT 0xffU
11020 #define V_DBG_READ_DATA_CNT(x) ((x) << S_DBG_READ_DATA_CNT)
11021 #define G_DBG_READ_DATA_CNT(x) (((x) >> S_DBG_READ_DATA_CNT) & M_DBG_READ_DATA_CNT)
11023 #define S_DBG_READ_REQ_CNT 16
11024 #define M_DBG_READ_REQ_CNT 0xffU
11025 #define V_DBG_READ_REQ_CNT(x) ((x) << S_DBG_READ_REQ_CNT)
11026 #define G_DBG_READ_REQ_CNT(x) (((x) >> S_DBG_READ_REQ_CNT) & M_DBG_READ_REQ_CNT)
11028 #define S_DBG_WRITE_DATA_CNT 8
11029 #define M_DBG_WRITE_DATA_CNT 0xffU
11030 #define V_DBG_WRITE_DATA_CNT(x) ((x) << S_DBG_WRITE_DATA_CNT)
11031 #define G_DBG_WRITE_DATA_CNT(x) (((x) >> S_DBG_WRITE_DATA_CNT) & M_DBG_WRITE_DATA_CNT)
11033 #define S_DBG_WRITE_REQ_CNT 0
11034 #define M_DBG_WRITE_REQ_CNT 0xffU
11035 #define V_DBG_WRITE_REQ_CNT(x) ((x) << S_DBG_WRITE_REQ_CNT)
11036 #define G_DBG_WRITE_REQ_CNT(x) (((x) >> S_DBG_WRITE_REQ_CNT) & M_DBG_WRITE_REQ_CNT)
11038 #define A_MA_SGE_TH1_DEBUG_CNT 0x776c
11039 #define A_MA_ULPTX_DEBUG_CNT 0x7770
11040 #define A_MA_ULPRX_DEBUG_CNT 0x7774
11041 #define A_MA_ULPTXRX_DEBUG_CNT 0x7778
11042 #define A_MA_TP_TH0_DEBUG_CNT 0x777c
11043 #define A_MA_TP_TH1_DEBUG_CNT 0x7780
11044 #define A_MA_LE_DEBUG_CNT 0x7784
11045 #define A_MA_CIM_DEBUG_CNT 0x7788
11046 #define A_MA_PCIE_DEBUG_CNT 0x778c
11047 #define A_MA_PMTX_DEBUG_CNT 0x7790
11048 #define A_MA_PMRX_DEBUG_CNT 0x7794
11049 #define A_MA_HMA_DEBUG_CNT 0x7798
11050 #define A_MA_EDRAM0_BAR 0x77c0
11052 #define S_EDRAM0_BASE 16
11053 #define M_EDRAM0_BASE 0xfffU
11054 #define V_EDRAM0_BASE(x) ((x) << S_EDRAM0_BASE)
11055 #define G_EDRAM0_BASE(x) (((x) >> S_EDRAM0_BASE) & M_EDRAM0_BASE)
11057 #define S_EDRAM0_SIZE 0
11058 #define M_EDRAM0_SIZE 0xfffU
11059 #define V_EDRAM0_SIZE(x) ((x) << S_EDRAM0_SIZE)
11060 #define G_EDRAM0_SIZE(x) (((x) >> S_EDRAM0_SIZE) & M_EDRAM0_SIZE)
11062 #define A_MA_EDRAM1_BAR 0x77c4
11064 #define S_EDRAM1_BASE 16
11065 #define M_EDRAM1_BASE 0xfffU
11066 #define V_EDRAM1_BASE(x) ((x) << S_EDRAM1_BASE)
11067 #define G_EDRAM1_BASE(x) (((x) >> S_EDRAM1_BASE) & M_EDRAM1_BASE)
11069 #define S_EDRAM1_SIZE 0
11070 #define M_EDRAM1_SIZE 0xfffU
11071 #define V_EDRAM1_SIZE(x) ((x) << S_EDRAM1_SIZE)
11072 #define G_EDRAM1_SIZE(x) (((x) >> S_EDRAM1_SIZE) & M_EDRAM1_SIZE)
11074 #define A_MA_EXT_MEMORY_BAR 0x77c8
11076 #define S_EXT_MEM_BASE 16
11077 #define M_EXT_MEM_BASE 0xfffU
11078 #define V_EXT_MEM_BASE(x) ((x) << S_EXT_MEM_BASE)
11079 #define G_EXT_MEM_BASE(x) (((x) >> S_EXT_MEM_BASE) & M_EXT_MEM_BASE)
11081 #define S_EXT_MEM_SIZE 0
11082 #define M_EXT_MEM_SIZE 0xfffU
11083 #define V_EXT_MEM_SIZE(x) ((x) << S_EXT_MEM_SIZE)
11084 #define G_EXT_MEM_SIZE(x) (((x) >> S_EXT_MEM_SIZE) & M_EXT_MEM_SIZE)
11086 #define A_MA_EXT_MEMORY0_BAR 0x77c8
11088 #define S_EXT_MEM0_BASE 16
11089 #define M_EXT_MEM0_BASE 0xfffU
11090 #define V_EXT_MEM0_BASE(x) ((x) << S_EXT_MEM0_BASE)
11091 #define G_EXT_MEM0_BASE(x) (((x) >> S_EXT_MEM0_BASE) & M_EXT_MEM0_BASE)
11093 #define S_EXT_MEM0_SIZE 0
11094 #define M_EXT_MEM0_SIZE 0xfffU
11095 #define V_EXT_MEM0_SIZE(x) ((x) << S_EXT_MEM0_SIZE)
11096 #define G_EXT_MEM0_SIZE(x) (((x) >> S_EXT_MEM0_SIZE) & M_EXT_MEM0_SIZE)
11098 #define A_MA_HOST_MEMORY_BAR 0x77cc
11100 #define S_HMA_BASE 16
11101 #define M_HMA_BASE 0xfffU
11102 #define V_HMA_BASE(x) ((x) << S_HMA_BASE)
11103 #define G_HMA_BASE(x) (((x) >> S_HMA_BASE) & M_HMA_BASE)
11105 #define S_HMA_SIZE 0
11106 #define M_HMA_SIZE 0xfffU
11107 #define V_HMA_SIZE(x) ((x) << S_HMA_SIZE)
11108 #define G_HMA_SIZE(x) (((x) >> S_HMA_SIZE) & M_HMA_SIZE)
11110 #define A_MA_EXT_MEM_PAGE_SIZE 0x77d0
11112 #define S_BRC_MODE 2
11113 #define V_BRC_MODE(x) ((x) << S_BRC_MODE)
11114 #define F_BRC_MODE V_BRC_MODE(1U)
11116 #define S_EXT_MEM_PAGE_SIZE 0
11117 #define M_EXT_MEM_PAGE_SIZE 0x3U
11118 #define V_EXT_MEM_PAGE_SIZE(x) ((x) << S_EXT_MEM_PAGE_SIZE)
11119 #define G_EXT_MEM_PAGE_SIZE(x) (((x) >> S_EXT_MEM_PAGE_SIZE) & M_EXT_MEM_PAGE_SIZE)
11121 #define S_BRC_MODE1 6
11122 #define V_BRC_MODE1(x) ((x) << S_BRC_MODE1)
11123 #define F_BRC_MODE1 V_BRC_MODE1(1U)
11125 #define S_EXT_MEM_PAGE_SIZE1 4
11126 #define M_EXT_MEM_PAGE_SIZE1 0x3U
11127 #define V_EXT_MEM_PAGE_SIZE1(x) ((x) << S_EXT_MEM_PAGE_SIZE1)
11128 #define G_EXT_MEM_PAGE_SIZE1(x) (((x) >> S_EXT_MEM_PAGE_SIZE1) & M_EXT_MEM_PAGE_SIZE1)
11130 #define A_MA_ARB_CTRL 0x77d4
11132 #define S_DIS_PAGE_HINT 1
11133 #define V_DIS_PAGE_HINT(x) ((x) << S_DIS_PAGE_HINT)
11134 #define F_DIS_PAGE_HINT V_DIS_PAGE_HINT(1U)
11136 #define S_DIS_ADV_ARB 0
11137 #define V_DIS_ADV_ARB(x) ((x) << S_DIS_ADV_ARB)
11138 #define F_DIS_ADV_ARB V_DIS_ADV_ARB(1U)
11140 #define S_DIS_BANK_FAIR 2
11141 #define V_DIS_BANK_FAIR(x) ((x) << S_DIS_BANK_FAIR)
11142 #define F_DIS_BANK_FAIR V_DIS_BANK_FAIR(1U)
11144 #define A_MA_TARGET_MEM_ENABLE 0x77d8
11146 #define S_HMA_ENABLE 3
11147 #define V_HMA_ENABLE(x) ((x) << S_HMA_ENABLE)
11148 #define F_HMA_ENABLE V_HMA_ENABLE(1U)
11150 #define S_EXT_MEM_ENABLE 2
11151 #define V_EXT_MEM_ENABLE(x) ((x) << S_EXT_MEM_ENABLE)
11152 #define F_EXT_MEM_ENABLE V_EXT_MEM_ENABLE(1U)
11154 #define S_EDRAM1_ENABLE 1
11155 #define V_EDRAM1_ENABLE(x) ((x) << S_EDRAM1_ENABLE)
11156 #define F_EDRAM1_ENABLE V_EDRAM1_ENABLE(1U)
11158 #define S_EDRAM0_ENABLE 0
11159 #define V_EDRAM0_ENABLE(x) ((x) << S_EDRAM0_ENABLE)
11160 #define F_EDRAM0_ENABLE V_EDRAM0_ENABLE(1U)
11162 #define S_HMA_MUX 5
11163 #define V_HMA_MUX(x) ((x) << S_HMA_MUX)
11164 #define F_HMA_MUX V_HMA_MUX(1U)
11166 #define S_EXT_MEM1_ENABLE 4
11167 #define V_EXT_MEM1_ENABLE(x) ((x) << S_EXT_MEM1_ENABLE)
11168 #define F_EXT_MEM1_ENABLE V_EXT_MEM1_ENABLE(1U)
11170 #define S_EXT_MEM0_ENABLE 2
11171 #define V_EXT_MEM0_ENABLE(x) ((x) << S_EXT_MEM0_ENABLE)
11172 #define F_EXT_MEM0_ENABLE V_EXT_MEM0_ENABLE(1U)
11174 #define A_MA_INT_ENABLE 0x77dc
11176 #define S_MEM_PERR_INT_ENABLE 1
11177 #define V_MEM_PERR_INT_ENABLE(x) ((x) << S_MEM_PERR_INT_ENABLE)
11178 #define F_MEM_PERR_INT_ENABLE V_MEM_PERR_INT_ENABLE(1U)
11180 #define S_MEM_WRAP_INT_ENABLE 0
11181 #define V_MEM_WRAP_INT_ENABLE(x) ((x) << S_MEM_WRAP_INT_ENABLE)
11182 #define F_MEM_WRAP_INT_ENABLE V_MEM_WRAP_INT_ENABLE(1U)
11184 #define S_MEM_TO_INT_ENABLE 2
11185 #define V_MEM_TO_INT_ENABLE(x) ((x) << S_MEM_TO_INT_ENABLE)
11186 #define F_MEM_TO_INT_ENABLE V_MEM_TO_INT_ENABLE(1U)
11188 #define A_MA_INT_CAUSE 0x77e0
11190 #define S_MEM_PERR_INT_CAUSE 1
11191 #define V_MEM_PERR_INT_CAUSE(x) ((x) << S_MEM_PERR_INT_CAUSE)
11192 #define F_MEM_PERR_INT_CAUSE V_MEM_PERR_INT_CAUSE(1U)
11194 #define S_MEM_WRAP_INT_CAUSE 0
11195 #define V_MEM_WRAP_INT_CAUSE(x) ((x) << S_MEM_WRAP_INT_CAUSE)
11196 #define F_MEM_WRAP_INT_CAUSE V_MEM_WRAP_INT_CAUSE(1U)
11198 #define S_MEM_TO_INT_CAUSE 2
11199 #define V_MEM_TO_INT_CAUSE(x) ((x) << S_MEM_TO_INT_CAUSE)
11200 #define F_MEM_TO_INT_CAUSE V_MEM_TO_INT_CAUSE(1U)
11202 #define A_MA_INT_WRAP_STATUS 0x77e4
11204 #define S_MEM_WRAP_ADDRESS 4
11205 #define M_MEM_WRAP_ADDRESS 0xfffffffU
11206 #define V_MEM_WRAP_ADDRESS(x) ((x) << S_MEM_WRAP_ADDRESS)
11207 #define G_MEM_WRAP_ADDRESS(x) (((x) >> S_MEM_WRAP_ADDRESS) & M_MEM_WRAP_ADDRESS)
11209 #define S_MEM_WRAP_CLIENT_NUM 0
11210 #define M_MEM_WRAP_CLIENT_NUM 0xfU
11211 #define V_MEM_WRAP_CLIENT_NUM(x) ((x) << S_MEM_WRAP_CLIENT_NUM)
11212 #define G_MEM_WRAP_CLIENT_NUM(x) (((x) >> S_MEM_WRAP_CLIENT_NUM) & M_MEM_WRAP_CLIENT_NUM)
11214 #define A_MA_TP_THREAD1_MAPPER 0x77e8
11216 #define S_TP_THREAD1_EN 0
11217 #define M_TP_THREAD1_EN 0xffU
11218 #define V_TP_THREAD1_EN(x) ((x) << S_TP_THREAD1_EN)
11219 #define G_TP_THREAD1_EN(x) (((x) >> S_TP_THREAD1_EN) & M_TP_THREAD1_EN)
11221 #define A_MA_SGE_THREAD1_MAPPER 0x77ec
11223 #define S_SGE_THREAD1_EN 0
11224 #define M_SGE_THREAD1_EN 0xffU
11225 #define V_SGE_THREAD1_EN(x) ((x) << S_SGE_THREAD1_EN)
11226 #define G_SGE_THREAD1_EN(x) (((x) >> S_SGE_THREAD1_EN) & M_SGE_THREAD1_EN)
11228 #define A_MA_PARITY_ERROR_ENABLE 0x77f0
11230 #define S_TP_DMARBT_PAR_ERROR_EN 31
11231 #define V_TP_DMARBT_PAR_ERROR_EN(x) ((x) << S_TP_DMARBT_PAR_ERROR_EN)
11232 #define F_TP_DMARBT_PAR_ERROR_EN V_TP_DMARBT_PAR_ERROR_EN(1U)
11234 #define S_LOGIC_FIFO_PAR_ERROR_EN 30
11235 #define V_LOGIC_FIFO_PAR_ERROR_EN(x) ((x) << S_LOGIC_FIFO_PAR_ERROR_EN)
11236 #define F_LOGIC_FIFO_PAR_ERROR_EN V_LOGIC_FIFO_PAR_ERROR_EN(1U)
11238 #define S_ARB3_PAR_WRQUEUE_ERROR_EN 29
11239 #define V_ARB3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR_EN)
11240 #define F_ARB3_PAR_WRQUEUE_ERROR_EN V_ARB3_PAR_WRQUEUE_ERROR_EN(1U)
11242 #define S_ARB2_PAR_WRQUEUE_ERROR_EN 28
11243 #define V_ARB2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR_EN)
11244 #define F_ARB2_PAR_WRQUEUE_ERROR_EN V_ARB2_PAR_WRQUEUE_ERROR_EN(1U)
11246 #define S_ARB1_PAR_WRQUEUE_ERROR_EN 27
11247 #define V_ARB1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR_EN)
11248 #define F_ARB1_PAR_WRQUEUE_ERROR_EN V_ARB1_PAR_WRQUEUE_ERROR_EN(1U)
11250 #define S_ARB0_PAR_WRQUEUE_ERROR_EN 26
11251 #define V_ARB0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR_EN)
11252 #define F_ARB0_PAR_WRQUEUE_ERROR_EN V_ARB0_PAR_WRQUEUE_ERROR_EN(1U)
11254 #define S_ARB3_PAR_RDQUEUE_ERROR_EN 25
11255 #define V_ARB3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR_EN)
11256 #define F_ARB3_PAR_RDQUEUE_ERROR_EN V_ARB3_PAR_RDQUEUE_ERROR_EN(1U)
11258 #define S_ARB2_PAR_RDQUEUE_ERROR_EN 24
11259 #define V_ARB2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR_EN)
11260 #define F_ARB2_PAR_RDQUEUE_ERROR_EN V_ARB2_PAR_RDQUEUE_ERROR_EN(1U)
11262 #define S_ARB1_PAR_RDQUEUE_ERROR_EN 23
11263 #define V_ARB1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR_EN)
11264 #define F_ARB1_PAR_RDQUEUE_ERROR_EN V_ARB1_PAR_RDQUEUE_ERROR_EN(1U)
11266 #define S_ARB0_PAR_RDQUEUE_ERROR_EN 22
11267 #define V_ARB0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR_EN)
11268 #define F_ARB0_PAR_RDQUEUE_ERROR_EN V_ARB0_PAR_RDQUEUE_ERROR_EN(1U)
11270 #define S_CL10_PAR_WRQUEUE_ERROR_EN 21
11271 #define V_CL10_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR_EN)
11272 #define F_CL10_PAR_WRQUEUE_ERROR_EN V_CL10_PAR_WRQUEUE_ERROR_EN(1U)
11274 #define S_CL9_PAR_WRQUEUE_ERROR_EN 20
11275 #define V_CL9_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR_EN)
11276 #define F_CL9_PAR_WRQUEUE_ERROR_EN V_CL9_PAR_WRQUEUE_ERROR_EN(1U)
11278 #define S_CL8_PAR_WRQUEUE_ERROR_EN 19
11279 #define V_CL8_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR_EN)
11280 #define F_CL8_PAR_WRQUEUE_ERROR_EN V_CL8_PAR_WRQUEUE_ERROR_EN(1U)
11282 #define S_CL7_PAR_WRQUEUE_ERROR_EN 18
11283 #define V_CL7_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR_EN)
11284 #define F_CL7_PAR_WRQUEUE_ERROR_EN V_CL7_PAR_WRQUEUE_ERROR_EN(1U)
11286 #define S_CL6_PAR_WRQUEUE_ERROR_EN 17
11287 #define V_CL6_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR_EN)
11288 #define F_CL6_PAR_WRQUEUE_ERROR_EN V_CL6_PAR_WRQUEUE_ERROR_EN(1U)
11290 #define S_CL5_PAR_WRQUEUE_ERROR_EN 16
11291 #define V_CL5_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR_EN)
11292 #define F_CL5_PAR_WRQUEUE_ERROR_EN V_CL5_PAR_WRQUEUE_ERROR_EN(1U)
11294 #define S_CL4_PAR_WRQUEUE_ERROR_EN 15
11295 #define V_CL4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR_EN)
11296 #define F_CL4_PAR_WRQUEUE_ERROR_EN V_CL4_PAR_WRQUEUE_ERROR_EN(1U)
11298 #define S_CL3_PAR_WRQUEUE_ERROR_EN 14
11299 #define V_CL3_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR_EN)
11300 #define F_CL3_PAR_WRQUEUE_ERROR_EN V_CL3_PAR_WRQUEUE_ERROR_EN(1U)
11302 #define S_CL2_PAR_WRQUEUE_ERROR_EN 13
11303 #define V_CL2_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR_EN)
11304 #define F_CL2_PAR_WRQUEUE_ERROR_EN V_CL2_PAR_WRQUEUE_ERROR_EN(1U)
11306 #define S_CL1_PAR_WRQUEUE_ERROR_EN 12
11307 #define V_CL1_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR_EN)
11308 #define F_CL1_PAR_WRQUEUE_ERROR_EN V_CL1_PAR_WRQUEUE_ERROR_EN(1U)
11310 #define S_CL0_PAR_WRQUEUE_ERROR_EN 11
11311 #define V_CL0_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR_EN)
11312 #define F_CL0_PAR_WRQUEUE_ERROR_EN V_CL0_PAR_WRQUEUE_ERROR_EN(1U)
11314 #define S_CL10_PAR_RDQUEUE_ERROR_EN 10
11315 #define V_CL10_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR_EN)
11316 #define F_CL10_PAR_RDQUEUE_ERROR_EN V_CL10_PAR_RDQUEUE_ERROR_EN(1U)
11318 #define S_CL9_PAR_RDQUEUE_ERROR_EN 9
11319 #define V_CL9_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR_EN)
11320 #define F_CL9_PAR_RDQUEUE_ERROR_EN V_CL9_PAR_RDQUEUE_ERROR_EN(1U)
11322 #define S_CL8_PAR_RDQUEUE_ERROR_EN 8
11323 #define V_CL8_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR_EN)
11324 #define F_CL8_PAR_RDQUEUE_ERROR_EN V_CL8_PAR_RDQUEUE_ERROR_EN(1U)
11326 #define S_CL7_PAR_RDQUEUE_ERROR_EN 7
11327 #define V_CL7_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR_EN)
11328 #define F_CL7_PAR_RDQUEUE_ERROR_EN V_CL7_PAR_RDQUEUE_ERROR_EN(1U)
11330 #define S_CL6_PAR_RDQUEUE_ERROR_EN 6
11331 #define V_CL6_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR_EN)
11332 #define F_CL6_PAR_RDQUEUE_ERROR_EN V_CL6_PAR_RDQUEUE_ERROR_EN(1U)
11334 #define S_CL5_PAR_RDQUEUE_ERROR_EN 5
11335 #define V_CL5_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR_EN)
11336 #define F_CL5_PAR_RDQUEUE_ERROR_EN V_CL5_PAR_RDQUEUE_ERROR_EN(1U)
11338 #define S_CL4_PAR_RDQUEUE_ERROR_EN 4
11339 #define V_CL4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR_EN)
11340 #define F_CL4_PAR_RDQUEUE_ERROR_EN V_CL4_PAR_RDQUEUE_ERROR_EN(1U)
11342 #define S_CL3_PAR_RDQUEUE_ERROR_EN 3
11343 #define V_CL3_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR_EN)
11344 #define F_CL3_PAR_RDQUEUE_ERROR_EN V_CL3_PAR_RDQUEUE_ERROR_EN(1U)
11346 #define S_CL2_PAR_RDQUEUE_ERROR_EN 2
11347 #define V_CL2_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR_EN)
11348 #define F_CL2_PAR_RDQUEUE_ERROR_EN V_CL2_PAR_RDQUEUE_ERROR_EN(1U)
11350 #define S_CL1_PAR_RDQUEUE_ERROR_EN 1
11351 #define V_CL1_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR_EN)
11352 #define F_CL1_PAR_RDQUEUE_ERROR_EN V_CL1_PAR_RDQUEUE_ERROR_EN(1U)
11354 #define S_CL0_PAR_RDQUEUE_ERROR_EN 0
11355 #define V_CL0_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR_EN)
11356 #define F_CL0_PAR_RDQUEUE_ERROR_EN V_CL0_PAR_RDQUEUE_ERROR_EN(1U)
11358 #define A_MA_PARITY_ERROR_ENABLE1 0x77f0
11359 #define A_MA_PARITY_ERROR_STATUS 0x77f4
11361 #define S_TP_DMARBT_PAR_ERROR 31
11362 #define V_TP_DMARBT_PAR_ERROR(x) ((x) << S_TP_DMARBT_PAR_ERROR)
11363 #define F_TP_DMARBT_PAR_ERROR V_TP_DMARBT_PAR_ERROR(1U)
11365 #define S_LOGIC_FIFO_PAR_ERROR 30
11366 #define V_LOGIC_FIFO_PAR_ERROR(x) ((x) << S_LOGIC_FIFO_PAR_ERROR)
11367 #define F_LOGIC_FIFO_PAR_ERROR V_LOGIC_FIFO_PAR_ERROR(1U)
11369 #define S_ARB3_PAR_WRQUEUE_ERROR 29
11370 #define V_ARB3_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB3_PAR_WRQUEUE_ERROR)
11371 #define F_ARB3_PAR_WRQUEUE_ERROR V_ARB3_PAR_WRQUEUE_ERROR(1U)
11373 #define S_ARB2_PAR_WRQUEUE_ERROR 28
11374 #define V_ARB2_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB2_PAR_WRQUEUE_ERROR)
11375 #define F_ARB2_PAR_WRQUEUE_ERROR V_ARB2_PAR_WRQUEUE_ERROR(1U)
11377 #define S_ARB1_PAR_WRQUEUE_ERROR 27
11378 #define V_ARB1_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB1_PAR_WRQUEUE_ERROR)
11379 #define F_ARB1_PAR_WRQUEUE_ERROR V_ARB1_PAR_WRQUEUE_ERROR(1U)
11381 #define S_ARB0_PAR_WRQUEUE_ERROR 26
11382 #define V_ARB0_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB0_PAR_WRQUEUE_ERROR)
11383 #define F_ARB0_PAR_WRQUEUE_ERROR V_ARB0_PAR_WRQUEUE_ERROR(1U)
11385 #define S_ARB3_PAR_RDQUEUE_ERROR 25
11386 #define V_ARB3_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB3_PAR_RDQUEUE_ERROR)
11387 #define F_ARB3_PAR_RDQUEUE_ERROR V_ARB3_PAR_RDQUEUE_ERROR(1U)
11389 #define S_ARB2_PAR_RDQUEUE_ERROR 24
11390 #define V_ARB2_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB2_PAR_RDQUEUE_ERROR)
11391 #define F_ARB2_PAR_RDQUEUE_ERROR V_ARB2_PAR_RDQUEUE_ERROR(1U)
11393 #define S_ARB1_PAR_RDQUEUE_ERROR 23
11394 #define V_ARB1_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB1_PAR_RDQUEUE_ERROR)
11395 #define F_ARB1_PAR_RDQUEUE_ERROR V_ARB1_PAR_RDQUEUE_ERROR(1U)
11397 #define S_ARB0_PAR_RDQUEUE_ERROR 22
11398 #define V_ARB0_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB0_PAR_RDQUEUE_ERROR)
11399 #define F_ARB0_PAR_RDQUEUE_ERROR V_ARB0_PAR_RDQUEUE_ERROR(1U)
11401 #define S_CL10_PAR_WRQUEUE_ERROR 21
11402 #define V_CL10_PAR_WRQUEUE_ERROR(x) ((x) << S_CL10_PAR_WRQUEUE_ERROR)
11403 #define F_CL10_PAR_WRQUEUE_ERROR V_CL10_PAR_WRQUEUE_ERROR(1U)
11405 #define S_CL9_PAR_WRQUEUE_ERROR 20
11406 #define V_CL9_PAR_WRQUEUE_ERROR(x) ((x) << S_CL9_PAR_WRQUEUE_ERROR)
11407 #define F_CL9_PAR_WRQUEUE_ERROR V_CL9_PAR_WRQUEUE_ERROR(1U)
11409 #define S_CL8_PAR_WRQUEUE_ERROR 19
11410 #define V_CL8_PAR_WRQUEUE_ERROR(x) ((x) << S_CL8_PAR_WRQUEUE_ERROR)
11411 #define F_CL8_PAR_WRQUEUE_ERROR V_CL8_PAR_WRQUEUE_ERROR(1U)
11413 #define S_CL7_PAR_WRQUEUE_ERROR 18
11414 #define V_CL7_PAR_WRQUEUE_ERROR(x) ((x) << S_CL7_PAR_WRQUEUE_ERROR)
11415 #define F_CL7_PAR_WRQUEUE_ERROR V_CL7_PAR_WRQUEUE_ERROR(1U)
11417 #define S_CL6_PAR_WRQUEUE_ERROR 17
11418 #define V_CL6_PAR_WRQUEUE_ERROR(x) ((x) << S_CL6_PAR_WRQUEUE_ERROR)
11419 #define F_CL6_PAR_WRQUEUE_ERROR V_CL6_PAR_WRQUEUE_ERROR(1U)
11421 #define S_CL5_PAR_WRQUEUE_ERROR 16
11422 #define V_CL5_PAR_WRQUEUE_ERROR(x) ((x) << S_CL5_PAR_WRQUEUE_ERROR)
11423 #define F_CL5_PAR_WRQUEUE_ERROR V_CL5_PAR_WRQUEUE_ERROR(1U)
11425 #define S_CL4_PAR_WRQUEUE_ERROR 15
11426 #define V_CL4_PAR_WRQUEUE_ERROR(x) ((x) << S_CL4_PAR_WRQUEUE_ERROR)
11427 #define F_CL4_PAR_WRQUEUE_ERROR V_CL4_PAR_WRQUEUE_ERROR(1U)
11429 #define S_CL3_PAR_WRQUEUE_ERROR 14
11430 #define V_CL3_PAR_WRQUEUE_ERROR(x) ((x) << S_CL3_PAR_WRQUEUE_ERROR)
11431 #define F_CL3_PAR_WRQUEUE_ERROR V_CL3_PAR_WRQUEUE_ERROR(1U)
11433 #define S_CL2_PAR_WRQUEUE_ERROR 13
11434 #define V_CL2_PAR_WRQUEUE_ERROR(x) ((x) << S_CL2_PAR_WRQUEUE_ERROR)
11435 #define F_CL2_PAR_WRQUEUE_ERROR V_CL2_PAR_WRQUEUE_ERROR(1U)
11437 #define S_CL1_PAR_WRQUEUE_ERROR 12
11438 #define V_CL1_PAR_WRQUEUE_ERROR(x) ((x) << S_CL1_PAR_WRQUEUE_ERROR)
11439 #define F_CL1_PAR_WRQUEUE_ERROR V_CL1_PAR_WRQUEUE_ERROR(1U)
11441 #define S_CL0_PAR_WRQUEUE_ERROR 11
11442 #define V_CL0_PAR_WRQUEUE_ERROR(x) ((x) << S_CL0_PAR_WRQUEUE_ERROR)
11443 #define F_CL0_PAR_WRQUEUE_ERROR V_CL0_PAR_WRQUEUE_ERROR(1U)
11445 #define S_CL10_PAR_RDQUEUE_ERROR 10
11446 #define V_CL10_PAR_RDQUEUE_ERROR(x) ((x) << S_CL10_PAR_RDQUEUE_ERROR)
11447 #define F_CL10_PAR_RDQUEUE_ERROR V_CL10_PAR_RDQUEUE_ERROR(1U)
11449 #define S_CL9_PAR_RDQUEUE_ERROR 9
11450 #define V_CL9_PAR_RDQUEUE_ERROR(x) ((x) << S_CL9_PAR_RDQUEUE_ERROR)
11451 #define F_CL9_PAR_RDQUEUE_ERROR V_CL9_PAR_RDQUEUE_ERROR(1U)
11453 #define S_CL8_PAR_RDQUEUE_ERROR 8
11454 #define V_CL8_PAR_RDQUEUE_ERROR(x) ((x) << S_CL8_PAR_RDQUEUE_ERROR)
11455 #define F_CL8_PAR_RDQUEUE_ERROR V_CL8_PAR_RDQUEUE_ERROR(1U)
11457 #define S_CL7_PAR_RDQUEUE_ERROR 7
11458 #define V_CL7_PAR_RDQUEUE_ERROR(x) ((x) << S_CL7_PAR_RDQUEUE_ERROR)
11459 #define F_CL7_PAR_RDQUEUE_ERROR V_CL7_PAR_RDQUEUE_ERROR(1U)
11461 #define S_CL6_PAR_RDQUEUE_ERROR 6
11462 #define V_CL6_PAR_RDQUEUE_ERROR(x) ((x) << S_CL6_PAR_RDQUEUE_ERROR)
11463 #define F_CL6_PAR_RDQUEUE_ERROR V_CL6_PAR_RDQUEUE_ERROR(1U)
11465 #define S_CL5_PAR_RDQUEUE_ERROR 5
11466 #define V_CL5_PAR_RDQUEUE_ERROR(x) ((x) << S_CL5_PAR_RDQUEUE_ERROR)
11467 #define F_CL5_PAR_RDQUEUE_ERROR V_CL5_PAR_RDQUEUE_ERROR(1U)
11469 #define S_CL4_PAR_RDQUEUE_ERROR 4
11470 #define V_CL4_PAR_RDQUEUE_ERROR(x) ((x) << S_CL4_PAR_RDQUEUE_ERROR)
11471 #define F_CL4_PAR_RDQUEUE_ERROR V_CL4_PAR_RDQUEUE_ERROR(1U)
11473 #define S_CL3_PAR_RDQUEUE_ERROR 3
11474 #define V_CL3_PAR_RDQUEUE_ERROR(x) ((x) << S_CL3_PAR_RDQUEUE_ERROR)
11475 #define F_CL3_PAR_RDQUEUE_ERROR V_CL3_PAR_RDQUEUE_ERROR(1U)
11477 #define S_CL2_PAR_RDQUEUE_ERROR 2
11478 #define V_CL2_PAR_RDQUEUE_ERROR(x) ((x) << S_CL2_PAR_RDQUEUE_ERROR)
11479 #define F_CL2_PAR_RDQUEUE_ERROR V_CL2_PAR_RDQUEUE_ERROR(1U)
11481 #define S_CL1_PAR_RDQUEUE_ERROR 1
11482 #define V_CL1_PAR_RDQUEUE_ERROR(x) ((x) << S_CL1_PAR_RDQUEUE_ERROR)
11483 #define F_CL1_PAR_RDQUEUE_ERROR V_CL1_PAR_RDQUEUE_ERROR(1U)
11485 #define S_CL0_PAR_RDQUEUE_ERROR 0
11486 #define V_CL0_PAR_RDQUEUE_ERROR(x) ((x) << S_CL0_PAR_RDQUEUE_ERROR)
11487 #define F_CL0_PAR_RDQUEUE_ERROR V_CL0_PAR_RDQUEUE_ERROR(1U)
11489 #define A_MA_PARITY_ERROR_STATUS1 0x77f4
11490 #define A_MA_SGE_PCIE_COHERANCY_CTRL 0x77f8
11492 #define S_BONUS_REG 6
11493 #define M_BONUS_REG 0x3ffffffU
11494 #define V_BONUS_REG(x) ((x) << S_BONUS_REG)
11495 #define G_BONUS_REG(x) (((x) >> S_BONUS_REG) & M_BONUS_REG)
11497 #define S_COHERANCY_CMD_TYPE 4
11498 #define M_COHERANCY_CMD_TYPE 0x3U
11499 #define V_COHERANCY_CMD_TYPE(x) ((x) << S_COHERANCY_CMD_TYPE)
11500 #define G_COHERANCY_CMD_TYPE(x) (((x) >> S_COHERANCY_CMD_TYPE) & M_COHERANCY_CMD_TYPE)
11502 #define S_COHERANCY_THREAD_NUM 1
11503 #define M_COHERANCY_THREAD_NUM 0x7U
11504 #define V_COHERANCY_THREAD_NUM(x) ((x) << S_COHERANCY_THREAD_NUM)
11505 #define G_COHERANCY_THREAD_NUM(x) (((x) >> S_COHERANCY_THREAD_NUM) & M_COHERANCY_THREAD_NUM)
11507 #define S_COHERANCY_ENABLE 0
11508 #define V_COHERANCY_ENABLE(x) ((x) << S_COHERANCY_ENABLE)
11509 #define F_COHERANCY_ENABLE V_COHERANCY_ENABLE(1U)
11511 #define A_MA_ERROR_ENABLE 0x77fc
11513 #define S_UE_ENABLE 0
11514 #define V_UE_ENABLE(x) ((x) << S_UE_ENABLE)
11515 #define F_UE_ENABLE V_UE_ENABLE(1U)
11517 #define S_FUTURE_EXPANSION 1
11518 #define M_FUTURE_EXPANSION 0x7fffffffU
11519 #define V_FUTURE_EXPANSION(x) ((x) << S_FUTURE_EXPANSION)
11520 #define G_FUTURE_EXPANSION(x) (((x) >> S_FUTURE_EXPANSION) & M_FUTURE_EXPANSION)
11522 #define A_MA_PARITY_ERROR_ENABLE2 0x7800
11524 #define S_ARB4_PAR_WRQUEUE_ERROR_EN 1
11525 #define V_ARB4_PAR_WRQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR_EN)
11526 #define F_ARB4_PAR_WRQUEUE_ERROR_EN V_ARB4_PAR_WRQUEUE_ERROR_EN(1U)
11528 #define S_ARB4_PAR_RDQUEUE_ERROR_EN 0
11529 #define V_ARB4_PAR_RDQUEUE_ERROR_EN(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR_EN)
11530 #define F_ARB4_PAR_RDQUEUE_ERROR_EN V_ARB4_PAR_RDQUEUE_ERROR_EN(1U)
11532 #define A_MA_PARITY_ERROR_STATUS2 0x7804
11534 #define S_ARB4_PAR_WRQUEUE_ERROR 1
11535 #define V_ARB4_PAR_WRQUEUE_ERROR(x) ((x) << S_ARB4_PAR_WRQUEUE_ERROR)
11536 #define F_ARB4_PAR_WRQUEUE_ERROR V_ARB4_PAR_WRQUEUE_ERROR(1U)
11538 #define S_ARB4_PAR_RDQUEUE_ERROR 0
11539 #define V_ARB4_PAR_RDQUEUE_ERROR(x) ((x) << S_ARB4_PAR_RDQUEUE_ERROR)
11540 #define F_ARB4_PAR_RDQUEUE_ERROR V_ARB4_PAR_RDQUEUE_ERROR(1U)
11542 #define A_MA_EXT_MEMORY1_BAR 0x7808
11544 #define S_EXT_MEM1_BASE 16
11545 #define M_EXT_MEM1_BASE 0xfffU
11546 #define V_EXT_MEM1_BASE(x) ((x) << S_EXT_MEM1_BASE)
11547 #define G_EXT_MEM1_BASE(x) (((x) >> S_EXT_MEM1_BASE) & M_EXT_MEM1_BASE)
11549 #define S_EXT_MEM1_SIZE 0
11550 #define M_EXT_MEM1_SIZE 0xfffU
11551 #define V_EXT_MEM1_SIZE(x) ((x) << S_EXT_MEM1_SIZE)
11552 #define G_EXT_MEM1_SIZE(x) (((x) >> S_EXT_MEM1_SIZE) & M_EXT_MEM1_SIZE)
11554 #define A_MA_PMTX_THROTTLE 0x780c
11556 #define S_FL_ENABLE 31
11557 #define V_FL_ENABLE(x) ((x) << S_FL_ENABLE)
11558 #define F_FL_ENABLE V_FL_ENABLE(1U)
11560 #define S_FL_LIMIT 0
11561 #define M_FL_LIMIT 0xffU
11562 #define V_FL_LIMIT(x) ((x) << S_FL_LIMIT)
11563 #define G_FL_LIMIT(x) (((x) >> S_FL_LIMIT) & M_FL_LIMIT)
11565 #define A_MA_PMRX_THROTTLE 0x7810
11566 #define A_MA_SGE_TH0_WRDATA_CNT 0x7814
11567 #define A_MA_SGE_TH1_WRDATA_CNT 0x7818
11568 #define A_MA_ULPTX_WRDATA_CNT 0x781c
11569 #define A_MA_ULPRX_WRDATA_CNT 0x7820
11570 #define A_MA_ULPTXRX_WRDATA_CNT 0x7824
11571 #define A_MA_TP_TH0_WRDATA_CNT 0x7828
11572 #define A_MA_TP_TH1_WRDATA_CNT 0x782c
11573 #define A_MA_LE_WRDATA_CNT 0x7830
11574 #define A_MA_CIM_WRDATA_CNT 0x7834
11575 #define A_MA_PCIE_WRDATA_CNT 0x7838
11576 #define A_MA_PMTX_WRDATA_CNT 0x783c
11577 #define A_MA_PMRX_WRDATA_CNT 0x7840
11578 #define A_MA_HMA_WRDATA_CNT 0x7844
11579 #define A_MA_SGE_TH0_RDDATA_CNT 0x7848
11580 #define A_MA_SGE_TH1_RDDATA_CNT 0x784c
11581 #define A_MA_ULPTX_RDDATA_CNT 0x7850
11582 #define A_MA_ULPRX_RDDATA_CNT 0x7854
11583 #define A_MA_ULPTXRX_RDDATA_CNT 0x7858
11584 #define A_MA_TP_TH0_RDDATA_CNT 0x785c
11585 #define A_MA_TP_TH1_RDDATA_CNT 0x7860
11586 #define A_MA_LE_RDDATA_CNT 0x7864
11587 #define A_MA_CIM_RDDATA_CNT 0x7868
11588 #define A_MA_PCIE_RDDATA_CNT 0x786c
11589 #define A_MA_PMTX_RDDATA_CNT 0x7870
11590 #define A_MA_PMRX_RDDATA_CNT 0x7874
11591 #define A_MA_HMA_RDDATA_CNT 0x7878
11592 #define A_MA_EDRAM0_WRDATA_CNT1 0x787c
11593 #define A_MA_EDRAM0_WRDATA_CNT0 0x7880
11594 #define A_MA_EDRAM1_WRDATA_CNT1 0x7884
11595 #define A_MA_EDRAM1_WRDATA_CNT0 0x7888
11596 #define A_MA_EXT_MEMORY0_WRDATA_CNT1 0x788c
11597 #define A_MA_EXT_MEMORY0_WRDATA_CNT0 0x7890
11598 #define A_MA_HOST_MEMORY_WRDATA_CNT1 0x7894
11599 #define A_MA_HOST_MEMORY_WRDATA_CNT0 0x7898
11600 #define A_MA_EXT_MEMORY1_WRDATA_CNT1 0x789c
11601 #define A_MA_EXT_MEMORY1_WRDATA_CNT0 0x78a0
11602 #define A_MA_EDRAM0_RDDATA_CNT1 0x78a4
11603 #define A_MA_EDRAM0_RDDATA_CNT0 0x78a8
11604 #define A_MA_EDRAM1_RDDATA_CNT1 0x78ac
11605 #define A_MA_EDRAM1_RDDATA_CNT0 0x78b0
11606 #define A_MA_EXT_MEMORY0_RDDATA_CNT1 0x78b4
11607 #define A_MA_EXT_MEMORY0_RDDATA_CNT0 0x78b8
11608 #define A_MA_HOST_MEMORY_RDDATA_CNT1 0x78bc
11609 #define A_MA_HOST_MEMORY_RDDATA_CNT0 0x78c0
11610 #define A_MA_EXT_MEMORY1_RDDATA_CNT1 0x78c4
11611 #define A_MA_EXT_MEMORY1_RDDATA_CNT0 0x78c8
11612 #define A_MA_TIMEOUT_CFG 0x78cc
11615 #define V_CLR(x) ((x) << S_CLR)
11616 #define F_CLR V_CLR(1U)
11618 #define S_CNT_LOCK 30
11619 #define V_CNT_LOCK(x) ((x) << S_CNT_LOCK)
11620 #define F_CNT_LOCK V_CNT_LOCK(1U)
11623 #define V_WRN(x) ((x) << S_WRN)
11624 #define F_WRN V_WRN(1U)
11627 #define V_DIR(x) ((x) << S_DIR)
11628 #define F_DIR V_DIR(1U)
11630 #define S_TO_BUS 22
11631 #define V_TO_BUS(x) ((x) << S_TO_BUS)
11632 #define F_TO_BUS V_TO_BUS(1U)
11634 #define S_CLIENT 16
11635 #define M_CLIENT 0xfU
11636 #define V_CLIENT(x) ((x) << S_CLIENT)
11637 #define G_CLIENT(x) (((x) >> S_CLIENT) & M_CLIENT)
11640 #define M_DELAY 0xffffU
11641 #define V_DELAY(x) ((x) << S_DELAY)
11642 #define G_DELAY(x) (((x) >> S_DELAY) & M_DELAY)
11644 #define A_MA_TIMEOUT_CNT 0x78d0
11646 #define S_CNT_VAL 0
11647 #define M_CNT_VAL 0xffffU
11648 #define V_CNT_VAL(x) ((x) << S_CNT_VAL)
11649 #define G_CNT_VAL(x) (((x) >> S_CNT_VAL) & M_CNT_VAL)
11651 #define A_MA_WRITE_TIMEOUT_ERROR_ENABLE 0x78d4
11653 #define S_FUTURE_CEXPANSION 29
11654 #define M_FUTURE_CEXPANSION 0x7U
11655 #define V_FUTURE_CEXPANSION(x) ((x) << S_FUTURE_CEXPANSION)
11656 #define G_FUTURE_CEXPANSION(x) (((x) >> S_FUTURE_CEXPANSION) & M_FUTURE_CEXPANSION)
11658 #define S_CL12_WR_CMD_TO_EN 28
11659 #define V_CL12_WR_CMD_TO_EN(x) ((x) << S_CL12_WR_CMD_TO_EN)
11660 #define F_CL12_WR_CMD_TO_EN V_CL12_WR_CMD_TO_EN(1U)
11662 #define S_CL11_WR_CMD_TO_EN 27
11663 #define V_CL11_WR_CMD_TO_EN(x) ((x) << S_CL11_WR_CMD_TO_EN)
11664 #define F_CL11_WR_CMD_TO_EN V_CL11_WR_CMD_TO_EN(1U)
11666 #define S_CL10_WR_CMD_TO_EN 26
11667 #define V_CL10_WR_CMD_TO_EN(x) ((x) << S_CL10_WR_CMD_TO_EN)
11668 #define F_CL10_WR_CMD_TO_EN V_CL10_WR_CMD_TO_EN(1U)
11670 #define S_CL9_WR_CMD_TO_EN 25
11671 #define V_CL9_WR_CMD_TO_EN(x) ((x) << S_CL9_WR_CMD_TO_EN)
11672 #define F_CL9_WR_CMD_TO_EN V_CL9_WR_CMD_TO_EN(1U)
11674 #define S_CL8_WR_CMD_TO_EN 24
11675 #define V_CL8_WR_CMD_TO_EN(x) ((x) << S_CL8_WR_CMD_TO_EN)
11676 #define F_CL8_WR_CMD_TO_EN V_CL8_WR_CMD_TO_EN(1U)
11678 #define S_CL7_WR_CMD_TO_EN 23
11679 #define V_CL7_WR_CMD_TO_EN(x) ((x) << S_CL7_WR_CMD_TO_EN)
11680 #define F_CL7_WR_CMD_TO_EN V_CL7_WR_CMD_TO_EN(1U)
11682 #define S_CL6_WR_CMD_TO_EN 22
11683 #define V_CL6_WR_CMD_TO_EN(x) ((x) << S_CL6_WR_CMD_TO_EN)
11684 #define F_CL6_WR_CMD_TO_EN V_CL6_WR_CMD_TO_EN(1U)
11686 #define S_CL5_WR_CMD_TO_EN 21
11687 #define V_CL5_WR_CMD_TO_EN(x) ((x) << S_CL5_WR_CMD_TO_EN)
11688 #define F_CL5_WR_CMD_TO_EN V_CL5_WR_CMD_TO_EN(1U)
11690 #define S_CL4_WR_CMD_TO_EN 20
11691 #define V_CL4_WR_CMD_TO_EN(x) ((x) << S_CL4_WR_CMD_TO_EN)
11692 #define F_CL4_WR_CMD_TO_EN V_CL4_WR_CMD_TO_EN(1U)
11694 #define S_CL3_WR_CMD_TO_EN 19
11695 #define V_CL3_WR_CMD_TO_EN(x) ((x) << S_CL3_WR_CMD_TO_EN)
11696 #define F_CL3_WR_CMD_TO_EN V_CL3_WR_CMD_TO_EN(1U)
11698 #define S_CL2_WR_CMD_TO_EN 18
11699 #define V_CL2_WR_CMD_TO_EN(x) ((x) << S_CL2_WR_CMD_TO_EN)
11700 #define F_CL2_WR_CMD_TO_EN V_CL2_WR_CMD_TO_EN(1U)
11702 #define S_CL1_WR_CMD_TO_EN 17
11703 #define V_CL1_WR_CMD_TO_EN(x) ((x) << S_CL1_WR_CMD_TO_EN)
11704 #define F_CL1_WR_CMD_TO_EN V_CL1_WR_CMD_TO_EN(1U)
11706 #define S_CL0_WR_CMD_TO_EN 16
11707 #define V_CL0_WR_CMD_TO_EN(x) ((x) << S_CL0_WR_CMD_TO_EN)
11708 #define F_CL0_WR_CMD_TO_EN V_CL0_WR_CMD_TO_EN(1U)
11710 #define S_FUTURE_DEXPANSION 13
11711 #define M_FUTURE_DEXPANSION 0x7U
11712 #define V_FUTURE_DEXPANSION(x) ((x) << S_FUTURE_DEXPANSION)
11713 #define G_FUTURE_DEXPANSION(x) (((x) >> S_FUTURE_DEXPANSION) & M_FUTURE_DEXPANSION)
11715 #define S_CL12_WR_DATA_TO_EN 12
11716 #define V_CL12_WR_DATA_TO_EN(x) ((x) << S_CL12_WR_DATA_TO_EN)
11717 #define F_CL12_WR_DATA_TO_EN V_CL12_WR_DATA_TO_EN(1U)
11719 #define S_CL11_WR_DATA_TO_EN 11
11720 #define V_CL11_WR_DATA_TO_EN(x) ((x) << S_CL11_WR_DATA_TO_EN)
11721 #define F_CL11_WR_DATA_TO_EN V_CL11_WR_DATA_TO_EN(1U)
11723 #define S_CL10_WR_DATA_TO_EN 10
11724 #define V_CL10_WR_DATA_TO_EN(x) ((x) << S_CL10_WR_DATA_TO_EN)
11725 #define F_CL10_WR_DATA_TO_EN V_CL10_WR_DATA_TO_EN(1U)
11727 #define S_CL9_WR_DATA_TO_EN 9
11728 #define V_CL9_WR_DATA_TO_EN(x) ((x) << S_CL9_WR_DATA_TO_EN)
11729 #define F_CL9_WR_DATA_TO_EN V_CL9_WR_DATA_TO_EN(1U)
11731 #define S_CL8_WR_DATA_TO_EN 8
11732 #define V_CL8_WR_DATA_TO_EN(x) ((x) << S_CL8_WR_DATA_TO_EN)
11733 #define F_CL8_WR_DATA_TO_EN V_CL8_WR_DATA_TO_EN(1U)
11735 #define S_CL7_WR_DATA_TO_EN 7
11736 #define V_CL7_WR_DATA_TO_EN(x) ((x) << S_CL7_WR_DATA_TO_EN)
11737 #define F_CL7_WR_DATA_TO_EN V_CL7_WR_DATA_TO_EN(1U)
11739 #define S_CL6_WR_DATA_TO_EN 6
11740 #define V_CL6_WR_DATA_TO_EN(x) ((x) << S_CL6_WR_DATA_TO_EN)
11741 #define F_CL6_WR_DATA_TO_EN V_CL6_WR_DATA_TO_EN(1U)
11743 #define S_CL5_WR_DATA_TO_EN 5
11744 #define V_CL5_WR_DATA_TO_EN(x) ((x) << S_CL5_WR_DATA_TO_EN)
11745 #define F_CL5_WR_DATA_TO_EN V_CL5_WR_DATA_TO_EN(1U)
11747 #define S_CL4_WR_DATA_TO_EN 4
11748 #define V_CL4_WR_DATA_TO_EN(x) ((x) << S_CL4_WR_DATA_TO_EN)
11749 #define F_CL4_WR_DATA_TO_EN V_CL4_WR_DATA_TO_EN(1U)
11751 #define S_CL3_WR_DATA_TO_EN 3
11752 #define V_CL3_WR_DATA_TO_EN(x) ((x) << S_CL3_WR_DATA_TO_EN)
11753 #define F_CL3_WR_DATA_TO_EN V_CL3_WR_DATA_TO_EN(1U)
11755 #define S_CL2_WR_DATA_TO_EN 2
11756 #define V_CL2_WR_DATA_TO_EN(x) ((x) << S_CL2_WR_DATA_TO_EN)
11757 #define F_CL2_WR_DATA_TO_EN V_CL2_WR_DATA_TO_EN(1U)
11759 #define S_CL1_WR_DATA_TO_EN 1
11760 #define V_CL1_WR_DATA_TO_EN(x) ((x) << S_CL1_WR_DATA_TO_EN)
11761 #define F_CL1_WR_DATA_TO_EN V_CL1_WR_DATA_TO_EN(1U)
11763 #define S_CL0_WR_DATA_TO_EN 0
11764 #define V_CL0_WR_DATA_TO_EN(x) ((x) << S_CL0_WR_DATA_TO_EN)
11765 #define F_CL0_WR_DATA_TO_EN V_CL0_WR_DATA_TO_EN(1U)
11767 #define A_MA_WRITE_TIMEOUT_ERROR_STATUS 0x78d8
11769 #define S_CL12_WR_CMD_TO_ERROR 28
11770 #define V_CL12_WR_CMD_TO_ERROR(x) ((x) << S_CL12_WR_CMD_TO_ERROR)
11771 #define F_CL12_WR_CMD_TO_ERROR V_CL12_WR_CMD_TO_ERROR(1U)
11773 #define S_CL11_WR_CMD_TO_ERROR 27
11774 #define V_CL11_WR_CMD_TO_ERROR(x) ((x) << S_CL11_WR_CMD_TO_ERROR)
11775 #define F_CL11_WR_CMD_TO_ERROR V_CL11_WR_CMD_TO_ERROR(1U)
11777 #define S_CL10_WR_CMD_TO_ERROR 26
11778 #define V_CL10_WR_CMD_TO_ERROR(x) ((x) << S_CL10_WR_CMD_TO_ERROR)
11779 #define F_CL10_WR_CMD_TO_ERROR V_CL10_WR_CMD_TO_ERROR(1U)
11781 #define S_CL9_WR_CMD_TO_ERROR 25
11782 #define V_CL9_WR_CMD_TO_ERROR(x) ((x) << S_CL9_WR_CMD_TO_ERROR)
11783 #define F_CL9_WR_CMD_TO_ERROR V_CL9_WR_CMD_TO_ERROR(1U)
11785 #define S_CL8_WR_CMD_TO_ERROR 24
11786 #define V_CL8_WR_CMD_TO_ERROR(x) ((x) << S_CL8_WR_CMD_TO_ERROR)
11787 #define F_CL8_WR_CMD_TO_ERROR V_CL8_WR_CMD_TO_ERROR(1U)
11789 #define S_CL7_WR_CMD_TO_ERROR 23
11790 #define V_CL7_WR_CMD_TO_ERROR(x) ((x) << S_CL7_WR_CMD_TO_ERROR)
11791 #define F_CL7_WR_CMD_TO_ERROR V_CL7_WR_CMD_TO_ERROR(1U)
11793 #define S_CL6_WR_CMD_TO_ERROR 22
11794 #define V_CL6_WR_CMD_TO_ERROR(x) ((x) << S_CL6_WR_CMD_TO_ERROR)
11795 #define F_CL6_WR_CMD_TO_ERROR V_CL6_WR_CMD_TO_ERROR(1U)
11797 #define S_CL5_WR_CMD_TO_ERROR 21
11798 #define V_CL5_WR_CMD_TO_ERROR(x) ((x) << S_CL5_WR_CMD_TO_ERROR)
11799 #define F_CL5_WR_CMD_TO_ERROR V_CL5_WR_CMD_TO_ERROR(1U)
11801 #define S_CL4_WR_CMD_TO_ERROR 20
11802 #define V_CL4_WR_CMD_TO_ERROR(x) ((x) << S_CL4_WR_CMD_TO_ERROR)
11803 #define F_CL4_WR_CMD_TO_ERROR V_CL4_WR_CMD_TO_ERROR(1U)
11805 #define S_CL3_WR_CMD_TO_ERROR 19
11806 #define V_CL3_WR_CMD_TO_ERROR(x) ((x) << S_CL3_WR_CMD_TO_ERROR)
11807 #define F_CL3_WR_CMD_TO_ERROR V_CL3_WR_CMD_TO_ERROR(1U)
11809 #define S_CL2_WR_CMD_TO_ERROR 18
11810 #define V_CL2_WR_CMD_TO_ERROR(x) ((x) << S_CL2_WR_CMD_TO_ERROR)
11811 #define F_CL2_WR_CMD_TO_ERROR V_CL2_WR_CMD_TO_ERROR(1U)
11813 #define S_CL1_WR_CMD_TO_ERROR 17
11814 #define V_CL1_WR_CMD_TO_ERROR(x) ((x) << S_CL1_WR_CMD_TO_ERROR)
11815 #define F_CL1_WR_CMD_TO_ERROR V_CL1_WR_CMD_TO_ERROR(1U)
11817 #define S_CL0_WR_CMD_TO_ERROR 16
11818 #define V_CL0_WR_CMD_TO_ERROR(x) ((x) << S_CL0_WR_CMD_TO_ERROR)
11819 #define F_CL0_WR_CMD_TO_ERROR V_CL0_WR_CMD_TO_ERROR(1U)
11821 #define S_CL12_WR_DATA_TO_ERROR 12
11822 #define V_CL12_WR_DATA_TO_ERROR(x) ((x) << S_CL12_WR_DATA_TO_ERROR)
11823 #define F_CL12_WR_DATA_TO_ERROR V_CL12_WR_DATA_TO_ERROR(1U)
11825 #define S_CL11_WR_DATA_TO_ERROR 11
11826 #define V_CL11_WR_DATA_TO_ERROR(x) ((x) << S_CL11_WR_DATA_TO_ERROR)
11827 #define F_CL11_WR_DATA_TO_ERROR V_CL11_WR_DATA_TO_ERROR(1U)
11829 #define S_CL10_WR_DATA_TO_ERROR 10
11830 #define V_CL10_WR_DATA_TO_ERROR(x) ((x) << S_CL10_WR_DATA_TO_ERROR)
11831 #define F_CL10_WR_DATA_TO_ERROR V_CL10_WR_DATA_TO_ERROR(1U)
11833 #define S_CL9_WR_DATA_TO_ERROR 9
11834 #define V_CL9_WR_DATA_TO_ERROR(x) ((x) << S_CL9_WR_DATA_TO_ERROR)
11835 #define F_CL9_WR_DATA_TO_ERROR V_CL9_WR_DATA_TO_ERROR(1U)
11837 #define S_CL8_WR_DATA_TO_ERROR 8
11838 #define V_CL8_WR_DATA_TO_ERROR(x) ((x) << S_CL8_WR_DATA_TO_ERROR)
11839 #define F_CL8_WR_DATA_TO_ERROR V_CL8_WR_DATA_TO_ERROR(1U)
11841 #define S_CL7_WR_DATA_TO_ERROR 7
11842 #define V_CL7_WR_DATA_TO_ERROR(x) ((x) << S_CL7_WR_DATA_TO_ERROR)
11843 #define F_CL7_WR_DATA_TO_ERROR V_CL7_WR_DATA_TO_ERROR(1U)
11845 #define S_CL6_WR_DATA_TO_ERROR 6
11846 #define V_CL6_WR_DATA_TO_ERROR(x) ((x) << S_CL6_WR_DATA_TO_ERROR)
11847 #define F_CL6_WR_DATA_TO_ERROR V_CL6_WR_DATA_TO_ERROR(1U)
11849 #define S_CL5_WR_DATA_TO_ERROR 5
11850 #define V_CL5_WR_DATA_TO_ERROR(x) ((x) << S_CL5_WR_DATA_TO_ERROR)
11851 #define F_CL5_WR_DATA_TO_ERROR V_CL5_WR_DATA_TO_ERROR(1U)
11853 #define S_CL4_WR_DATA_TO_ERROR 4
11854 #define V_CL4_WR_DATA_TO_ERROR(x) ((x) << S_CL4_WR_DATA_TO_ERROR)
11855 #define F_CL4_WR_DATA_TO_ERROR V_CL4_WR_DATA_TO_ERROR(1U)
11857 #define S_CL3_WR_DATA_TO_ERROR 3
11858 #define V_CL3_WR_DATA_TO_ERROR(x) ((x) << S_CL3_WR_DATA_TO_ERROR)
11859 #define F_CL3_WR_DATA_TO_ERROR V_CL3_WR_DATA_TO_ERROR(1U)
11861 #define S_CL2_WR_DATA_TO_ERROR 2
11862 #define V_CL2_WR_DATA_TO_ERROR(x) ((x) << S_CL2_WR_DATA_TO_ERROR)
11863 #define F_CL2_WR_DATA_TO_ERROR V_CL2_WR_DATA_TO_ERROR(1U)
11865 #define S_CL1_WR_DATA_TO_ERROR 1
11866 #define V_CL1_WR_DATA_TO_ERROR(x) ((x) << S_CL1_WR_DATA_TO_ERROR)
11867 #define F_CL1_WR_DATA_TO_ERROR V_CL1_WR_DATA_TO_ERROR(1U)
11869 #define S_CL0_WR_DATA_TO_ERROR 0
11870 #define V_CL0_WR_DATA_TO_ERROR(x) ((x) << S_CL0_WR_DATA_TO_ERROR)
11871 #define F_CL0_WR_DATA_TO_ERROR V_CL0_WR_DATA_TO_ERROR(1U)
11873 #define A_MA_READ_TIMEOUT_ERROR_ENABLE 0x78dc
11875 #define S_CL12_RD_CMD_TO_EN 28
11876 #define V_CL12_RD_CMD_TO_EN(x) ((x) << S_CL12_RD_CMD_TO_EN)
11877 #define F_CL12_RD_CMD_TO_EN V_CL12_RD_CMD_TO_EN(1U)
11879 #define S_CL11_RD_CMD_TO_EN 27
11880 #define V_CL11_RD_CMD_TO_EN(x) ((x) << S_CL11_RD_CMD_TO_EN)
11881 #define F_CL11_RD_CMD_TO_EN V_CL11_RD_CMD_TO_EN(1U)
11883 #define S_CL10_RD_CMD_TO_EN 26
11884 #define V_CL10_RD_CMD_TO_EN(x) ((x) << S_CL10_RD_CMD_TO_EN)
11885 #define F_CL10_RD_CMD_TO_EN V_CL10_RD_CMD_TO_EN(1U)
11887 #define S_CL9_RD_CMD_TO_EN 25
11888 #define V_CL9_RD_CMD_TO_EN(x) ((x) << S_CL9_RD_CMD_TO_EN)
11889 #define F_CL9_RD_CMD_TO_EN V_CL9_RD_CMD_TO_EN(1U)
11891 #define S_CL8_RD_CMD_TO_EN 24
11892 #define V_CL8_RD_CMD_TO_EN(x) ((x) << S_CL8_RD_CMD_TO_EN)
11893 #define F_CL8_RD_CMD_TO_EN V_CL8_RD_CMD_TO_EN(1U)
11895 #define S_CL7_RD_CMD_TO_EN 23
11896 #define V_CL7_RD_CMD_TO_EN(x) ((x) << S_CL7_RD_CMD_TO_EN)
11897 #define F_CL7_RD_CMD_TO_EN V_CL7_RD_CMD_TO_EN(1U)
11899 #define S_CL6_RD_CMD_TO_EN 22
11900 #define V_CL6_RD_CMD_TO_EN(x) ((x) << S_CL6_RD_CMD_TO_EN)
11901 #define F_CL6_RD_CMD_TO_EN V_CL6_RD_CMD_TO_EN(1U)
11903 #define S_CL5_RD_CMD_TO_EN 21
11904 #define V_CL5_RD_CMD_TO_EN(x) ((x) << S_CL5_RD_CMD_TO_EN)
11905 #define F_CL5_RD_CMD_TO_EN V_CL5_RD_CMD_TO_EN(1U)
11907 #define S_CL4_RD_CMD_TO_EN 20
11908 #define V_CL4_RD_CMD_TO_EN(x) ((x) << S_CL4_RD_CMD_TO_EN)
11909 #define F_CL4_RD_CMD_TO_EN V_CL4_RD_CMD_TO_EN(1U)
11911 #define S_CL3_RD_CMD_TO_EN 19
11912 #define V_CL3_RD_CMD_TO_EN(x) ((x) << S_CL3_RD_CMD_TO_EN)
11913 #define F_CL3_RD_CMD_TO_EN V_CL3_RD_CMD_TO_EN(1U)
11915 #define S_CL2_RD_CMD_TO_EN 18
11916 #define V_CL2_RD_CMD_TO_EN(x) ((x) << S_CL2_RD_CMD_TO_EN)
11917 #define F_CL2_RD_CMD_TO_EN V_CL2_RD_CMD_TO_EN(1U)
11919 #define S_CL1_RD_CMD_TO_EN 17
11920 #define V_CL1_RD_CMD_TO_EN(x) ((x) << S_CL1_RD_CMD_TO_EN)
11921 #define F_CL1_RD_CMD_TO_EN V_CL1_RD_CMD_TO_EN(1U)
11923 #define S_CL0_RD_CMD_TO_EN 16
11924 #define V_CL0_RD_CMD_TO_EN(x) ((x) << S_CL0_RD_CMD_TO_EN)
11925 #define F_CL0_RD_CMD_TO_EN V_CL0_RD_CMD_TO_EN(1U)
11927 #define S_CL12_RD_DATA_TO_EN 12
11928 #define V_CL12_RD_DATA_TO_EN(x) ((x) << S_CL12_RD_DATA_TO_EN)
11929 #define F_CL12_RD_DATA_TO_EN V_CL12_RD_DATA_TO_EN(1U)
11931 #define S_CL11_RD_DATA_TO_EN 11
11932 #define V_CL11_RD_DATA_TO_EN(x) ((x) << S_CL11_RD_DATA_TO_EN)
11933 #define F_CL11_RD_DATA_TO_EN V_CL11_RD_DATA_TO_EN(1U)
11935 #define S_CL10_RD_DATA_TO_EN 10
11936 #define V_CL10_RD_DATA_TO_EN(x) ((x) << S_CL10_RD_DATA_TO_EN)
11937 #define F_CL10_RD_DATA_TO_EN V_CL10_RD_DATA_TO_EN(1U)
11939 #define S_CL9_RD_DATA_TO_EN 9
11940 #define V_CL9_RD_DATA_TO_EN(x) ((x) << S_CL9_RD_DATA_TO_EN)
11941 #define F_CL9_RD_DATA_TO_EN V_CL9_RD_DATA_TO_EN(1U)
11943 #define S_CL8_RD_DATA_TO_EN 8
11944 #define V_CL8_RD_DATA_TO_EN(x) ((x) << S_CL8_RD_DATA_TO_EN)
11945 #define F_CL8_RD_DATA_TO_EN V_CL8_RD_DATA_TO_EN(1U)
11947 #define S_CL7_RD_DATA_TO_EN 7
11948 #define V_CL7_RD_DATA_TO_EN(x) ((x) << S_CL7_RD_DATA_TO_EN)
11949 #define F_CL7_RD_DATA_TO_EN V_CL7_RD_DATA_TO_EN(1U)
11951 #define S_CL6_RD_DATA_TO_EN 6
11952 #define V_CL6_RD_DATA_TO_EN(x) ((x) << S_CL6_RD_DATA_TO_EN)
11953 #define F_CL6_RD_DATA_TO_EN V_CL6_RD_DATA_TO_EN(1U)
11955 #define S_CL5_RD_DATA_TO_EN 5
11956 #define V_CL5_RD_DATA_TO_EN(x) ((x) << S_CL5_RD_DATA_TO_EN)
11957 #define F_CL5_RD_DATA_TO_EN V_CL5_RD_DATA_TO_EN(1U)
11959 #define S_CL4_RD_DATA_TO_EN 4
11960 #define V_CL4_RD_DATA_TO_EN(x) ((x) << S_CL4_RD_DATA_TO_EN)
11961 #define F_CL4_RD_DATA_TO_EN V_CL4_RD_DATA_TO_EN(1U)
11963 #define S_CL3_RD_DATA_TO_EN 3
11964 #define V_CL3_RD_DATA_TO_EN(x) ((x) << S_CL3_RD_DATA_TO_EN)
11965 #define F_CL3_RD_DATA_TO_EN V_CL3_RD_DATA_TO_EN(1U)
11967 #define S_CL2_RD_DATA_TO_EN 2
11968 #define V_CL2_RD_DATA_TO_EN(x) ((x) << S_CL2_RD_DATA_TO_EN)
11969 #define F_CL2_RD_DATA_TO_EN V_CL2_RD_DATA_TO_EN(1U)
11971 #define S_CL1_RD_DATA_TO_EN 1
11972 #define V_CL1_RD_DATA_TO_EN(x) ((x) << S_CL1_RD_DATA_TO_EN)
11973 #define F_CL1_RD_DATA_TO_EN V_CL1_RD_DATA_TO_EN(1U)
11975 #define S_CL0_RD_DATA_TO_EN 0
11976 #define V_CL0_RD_DATA_TO_EN(x) ((x) << S_CL0_RD_DATA_TO_EN)
11977 #define F_CL0_RD_DATA_TO_EN V_CL0_RD_DATA_TO_EN(1U)
11979 #define A_MA_READ_TIMEOUT_ERROR_STATUS 0x78e0
11981 #define S_CL12_RD_CMD_TO_ERROR 28
11982 #define V_CL12_RD_CMD_TO_ERROR(x) ((x) << S_CL12_RD_CMD_TO_ERROR)
11983 #define F_CL12_RD_CMD_TO_ERROR V_CL12_RD_CMD_TO_ERROR(1U)
11985 #define S_CL11_RD_CMD_TO_ERROR 27
11986 #define V_CL11_RD_CMD_TO_ERROR(x) ((x) << S_CL11_RD_CMD_TO_ERROR)
11987 #define F_CL11_RD_CMD_TO_ERROR V_CL11_RD_CMD_TO_ERROR(1U)
11989 #define S_CL10_RD_CMD_TO_ERROR 26
11990 #define V_CL10_RD_CMD_TO_ERROR(x) ((x) << S_CL10_RD_CMD_TO_ERROR)
11991 #define F_CL10_RD_CMD_TO_ERROR V_CL10_RD_CMD_TO_ERROR(1U)
11993 #define S_CL9_RD_CMD_TO_ERROR 25
11994 #define V_CL9_RD_CMD_TO_ERROR(x) ((x) << S_CL9_RD_CMD_TO_ERROR)
11995 #define F_CL9_RD_CMD_TO_ERROR V_CL9_RD_CMD_TO_ERROR(1U)
11997 #define S_CL8_RD_CMD_TO_ERROR 24
11998 #define V_CL8_RD_CMD_TO_ERROR(x) ((x) << S_CL8_RD_CMD_TO_ERROR)
11999 #define F_CL8_RD_CMD_TO_ERROR V_CL8_RD_CMD_TO_ERROR(1U)
12001 #define S_CL7_RD_CMD_TO_ERROR 23
12002 #define V_CL7_RD_CMD_TO_ERROR(x) ((x) << S_CL7_RD_CMD_TO_ERROR)
12003 #define F_CL7_RD_CMD_TO_ERROR V_CL7_RD_CMD_TO_ERROR(1U)
12005 #define S_CL6_RD_CMD_TO_ERROR 22
12006 #define V_CL6_RD_CMD_TO_ERROR(x) ((x) << S_CL6_RD_CMD_TO_ERROR)
12007 #define F_CL6_RD_CMD_TO_ERROR V_CL6_RD_CMD_TO_ERROR(1U)
12009 #define S_CL5_RD_CMD_TO_ERROR 21
12010 #define V_CL5_RD_CMD_TO_ERROR(x) ((x) << S_CL5_RD_CMD_TO_ERROR)
12011 #define F_CL5_RD_CMD_TO_ERROR V_CL5_RD_CMD_TO_ERROR(1U)
12013 #define S_CL4_RD_CMD_TO_ERROR 20
12014 #define V_CL4_RD_CMD_TO_ERROR(x) ((x) << S_CL4_RD_CMD_TO_ERROR)
12015 #define F_CL4_RD_CMD_TO_ERROR V_CL4_RD_CMD_TO_ERROR(1U)
12017 #define S_CL3_RD_CMD_TO_ERROR 19
12018 #define V_CL3_RD_CMD_TO_ERROR(x) ((x) << S_CL3_RD_CMD_TO_ERROR)
12019 #define F_CL3_RD_CMD_TO_ERROR V_CL3_RD_CMD_TO_ERROR(1U)
12021 #define S_CL2_RD_CMD_TO_ERROR 18
12022 #define V_CL2_RD_CMD_TO_ERROR(x) ((x) << S_CL2_RD_CMD_TO_ERROR)
12023 #define F_CL2_RD_CMD_TO_ERROR V_CL2_RD_CMD_TO_ERROR(1U)
12025 #define S_CL1_RD_CMD_TO_ERROR 17
12026 #define V_CL1_RD_CMD_TO_ERROR(x) ((x) << S_CL1_RD_CMD_TO_ERROR)
12027 #define F_CL1_RD_CMD_TO_ERROR V_CL1_RD_CMD_TO_ERROR(1U)
12029 #define S_CL0_RD_CMD_TO_ERROR 16
12030 #define V_CL0_RD_CMD_TO_ERROR(x) ((x) << S_CL0_RD_CMD_TO_ERROR)
12031 #define F_CL0_RD_CMD_TO_ERROR V_CL0_RD_CMD_TO_ERROR(1U)
12033 #define S_CL12_RD_DATA_TO_ERROR 12
12034 #define V_CL12_RD_DATA_TO_ERROR(x) ((x) << S_CL12_RD_DATA_TO_ERROR)
12035 #define F_CL12_RD_DATA_TO_ERROR V_CL12_RD_DATA_TO_ERROR(1U)
12037 #define S_CL11_RD_DATA_TO_ERROR 11
12038 #define V_CL11_RD_DATA_TO_ERROR(x) ((x) << S_CL11_RD_DATA_TO_ERROR)
12039 #define F_CL11_RD_DATA_TO_ERROR V_CL11_RD_DATA_TO_ERROR(1U)
12041 #define S_CL10_RD_DATA_TO_ERROR 10
12042 #define V_CL10_RD_DATA_TO_ERROR(x) ((x) << S_CL10_RD_DATA_TO_ERROR)
12043 #define F_CL10_RD_DATA_TO_ERROR V_CL10_RD_DATA_TO_ERROR(1U)
12045 #define S_CL9_RD_DATA_TO_ERROR 9
12046 #define V_CL9_RD_DATA_TO_ERROR(x) ((x) << S_CL9_RD_DATA_TO_ERROR)
12047 #define F_CL9_RD_DATA_TO_ERROR V_CL9_RD_DATA_TO_ERROR(1U)
12049 #define S_CL8_RD_DATA_TO_ERROR 8
12050 #define V_CL8_RD_DATA_TO_ERROR(x) ((x) << S_CL8_RD_DATA_TO_ERROR)
12051 #define F_CL8_RD_DATA_TO_ERROR V_CL8_RD_DATA_TO_ERROR(1U)
12053 #define S_CL7_RD_DATA_TO_ERROR 7
12054 #define V_CL7_RD_DATA_TO_ERROR(x) ((x) << S_CL7_RD_DATA_TO_ERROR)
12055 #define F_CL7_RD_DATA_TO_ERROR V_CL7_RD_DATA_TO_ERROR(1U)
12057 #define S_CL6_RD_DATA_TO_ERROR 6
12058 #define V_CL6_RD_DATA_TO_ERROR(x) ((x) << S_CL6_RD_DATA_TO_ERROR)
12059 #define F_CL6_RD_DATA_TO_ERROR V_CL6_RD_DATA_TO_ERROR(1U)
12061 #define S_CL5_RD_DATA_TO_ERROR 5
12062 #define V_CL5_RD_DATA_TO_ERROR(x) ((x) << S_CL5_RD_DATA_TO_ERROR)
12063 #define F_CL5_RD_DATA_TO_ERROR V_CL5_RD_DATA_TO_ERROR(1U)
12065 #define S_CL4_RD_DATA_TO_ERROR 4
12066 #define V_CL4_RD_DATA_TO_ERROR(x) ((x) << S_CL4_RD_DATA_TO_ERROR)
12067 #define F_CL4_RD_DATA_TO_ERROR V_CL4_RD_DATA_TO_ERROR(1U)
12069 #define S_CL3_RD_DATA_TO_ERROR 3
12070 #define V_CL3_RD_DATA_TO_ERROR(x) ((x) << S_CL3_RD_DATA_TO_ERROR)
12071 #define F_CL3_RD_DATA_TO_ERROR V_CL3_RD_DATA_TO_ERROR(1U)
12073 #define S_CL2_RD_DATA_TO_ERROR 2
12074 #define V_CL2_RD_DATA_TO_ERROR(x) ((x) << S_CL2_RD_DATA_TO_ERROR)
12075 #define F_CL2_RD_DATA_TO_ERROR V_CL2_RD_DATA_TO_ERROR(1U)
12077 #define S_CL1_RD_DATA_TO_ERROR 1
12078 #define V_CL1_RD_DATA_TO_ERROR(x) ((x) << S_CL1_RD_DATA_TO_ERROR)
12079 #define F_CL1_RD_DATA_TO_ERROR V_CL1_RD_DATA_TO_ERROR(1U)
12081 #define S_CL0_RD_DATA_TO_ERROR 0
12082 #define V_CL0_RD_DATA_TO_ERROR(x) ((x) << S_CL0_RD_DATA_TO_ERROR)
12083 #define F_CL0_RD_DATA_TO_ERROR V_CL0_RD_DATA_TO_ERROR(1U)
12085 #define A_MA_BKP_CNT_SEL 0x78e4
12087 #define S_BKP_CNT_TYPE 30
12088 #define M_BKP_CNT_TYPE 0x3U
12089 #define V_BKP_CNT_TYPE(x) ((x) << S_BKP_CNT_TYPE)
12090 #define G_BKP_CNT_TYPE(x) (((x) >> S_BKP_CNT_TYPE) & M_BKP_CNT_TYPE)
12092 #define S_BKP_CLIENT 24
12093 #define M_BKP_CLIENT 0xfU
12094 #define V_BKP_CLIENT(x) ((x) << S_BKP_CLIENT)
12095 #define G_BKP_CLIENT(x) (((x) >> S_BKP_CLIENT) & M_BKP_CLIENT)
12097 #define A_MA_BKP_CNT 0x78e8
12098 #define A_MA_WRT_ARB 0x78ec
12100 #define S_WRT_EN 31
12101 #define V_WRT_EN(x) ((x) << S_WRT_EN)
12102 #define F_WRT_EN V_WRT_EN(1U)
12104 #define S_WR_TIM 16
12105 #define M_WR_TIM 0xffU
12106 #define V_WR_TIM(x) ((x) << S_WR_TIM)
12107 #define G_WR_TIM(x) (((x) >> S_WR_TIM) & M_WR_TIM)
12110 #define M_RD_WIN 0xffU
12111 #define V_RD_WIN(x) ((x) << S_RD_WIN)
12112 #define G_RD_WIN(x) (((x) >> S_RD_WIN) & M_RD_WIN)
12115 #define M_WR_WIN 0xffU
12116 #define V_WR_WIN(x) ((x) << S_WR_WIN)
12117 #define G_WR_WIN(x) (((x) >> S_WR_WIN) & M_WR_WIN)
12119 #define A_MA_IF_PARITY_ERROR_ENABLE 0x78f0
12121 #define S_CL12_IF_PAR_EN 12
12122 #define V_CL12_IF_PAR_EN(x) ((x) << S_CL12_IF_PAR_EN)
12123 #define F_CL12_IF_PAR_EN V_CL12_IF_PAR_EN(1U)
12125 #define S_CL11_IF_PAR_EN 11
12126 #define V_CL11_IF_PAR_EN(x) ((x) << S_CL11_IF_PAR_EN)
12127 #define F_CL11_IF_PAR_EN V_CL11_IF_PAR_EN(1U)
12129 #define S_CL10_IF_PAR_EN 10
12130 #define V_CL10_IF_PAR_EN(x) ((x) << S_CL10_IF_PAR_EN)
12131 #define F_CL10_IF_PAR_EN V_CL10_IF_PAR_EN(1U)
12133 #define S_CL9_IF_PAR_EN 9
12134 #define V_CL9_IF_PAR_EN(x) ((x) << S_CL9_IF_PAR_EN)
12135 #define F_CL9_IF_PAR_EN V_CL9_IF_PAR_EN(1U)
12137 #define S_CL8_IF_PAR_EN 8
12138 #define V_CL8_IF_PAR_EN(x) ((x) << S_CL8_IF_PAR_EN)
12139 #define F_CL8_IF_PAR_EN V_CL8_IF_PAR_EN(1U)
12141 #define S_CL7_IF_PAR_EN 7
12142 #define V_CL7_IF_PAR_EN(x) ((x) << S_CL7_IF_PAR_EN)
12143 #define F_CL7_IF_PAR_EN V_CL7_IF_PAR_EN(1U)
12145 #define S_CL6_IF_PAR_EN 6
12146 #define V_CL6_IF_PAR_EN(x) ((x) << S_CL6_IF_PAR_EN)
12147 #define F_CL6_IF_PAR_EN V_CL6_IF_PAR_EN(1U)
12149 #define S_CL5_IF_PAR_EN 5
12150 #define V_CL5_IF_PAR_EN(x) ((x) << S_CL5_IF_PAR_EN)
12151 #define F_CL5_IF_PAR_EN V_CL5_IF_PAR_EN(1U)
12153 #define S_CL4_IF_PAR_EN 4
12154 #define V_CL4_IF_PAR_EN(x) ((x) << S_CL4_IF_PAR_EN)
12155 #define F_CL4_IF_PAR_EN V_CL4_IF_PAR_EN(1U)
12157 #define S_CL3_IF_PAR_EN 3
12158 #define V_CL3_IF_PAR_EN(x) ((x) << S_CL3_IF_PAR_EN)
12159 #define F_CL3_IF_PAR_EN V_CL3_IF_PAR_EN(1U)
12161 #define S_CL2_IF_PAR_EN 2
12162 #define V_CL2_IF_PAR_EN(x) ((x) << S_CL2_IF_PAR_EN)
12163 #define F_CL2_IF_PAR_EN V_CL2_IF_PAR_EN(1U)
12165 #define S_CL1_IF_PAR_EN 1
12166 #define V_CL1_IF_PAR_EN(x) ((x) << S_CL1_IF_PAR_EN)
12167 #define F_CL1_IF_PAR_EN V_CL1_IF_PAR_EN(1U)
12169 #define S_CL0_IF_PAR_EN 0
12170 #define V_CL0_IF_PAR_EN(x) ((x) << S_CL0_IF_PAR_EN)
12171 #define F_CL0_IF_PAR_EN V_CL0_IF_PAR_EN(1U)
12173 #define A_MA_IF_PARITY_ERROR_STATUS 0x78f4
12175 #define S_CL12_IF_PAR_ERROR 12
12176 #define V_CL12_IF_PAR_ERROR(x) ((x) << S_CL12_IF_PAR_ERROR)
12177 #define F_CL12_IF_PAR_ERROR V_CL12_IF_PAR_ERROR(1U)
12179 #define S_CL11_IF_PAR_ERROR 11
12180 #define V_CL11_IF_PAR_ERROR(x) ((x) << S_CL11_IF_PAR_ERROR)
12181 #define F_CL11_IF_PAR_ERROR V_CL11_IF_PAR_ERROR(1U)
12183 #define S_CL10_IF_PAR_ERROR 10
12184 #define V_CL10_IF_PAR_ERROR(x) ((x) << S_CL10_IF_PAR_ERROR)
12185 #define F_CL10_IF_PAR_ERROR V_CL10_IF_PAR_ERROR(1U)
12187 #define S_CL9_IF_PAR_ERROR 9
12188 #define V_CL9_IF_PAR_ERROR(x) ((x) << S_CL9_IF_PAR_ERROR)
12189 #define F_CL9_IF_PAR_ERROR V_CL9_IF_PAR_ERROR(1U)
12191 #define S_CL8_IF_PAR_ERROR 8
12192 #define V_CL8_IF_PAR_ERROR(x) ((x) << S_CL8_IF_PAR_ERROR)
12193 #define F_CL8_IF_PAR_ERROR V_CL8_IF_PAR_ERROR(1U)
12195 #define S_CL7_IF_PAR_ERROR 7
12196 #define V_CL7_IF_PAR_ERROR(x) ((x) << S_CL7_IF_PAR_ERROR)
12197 #define F_CL7_IF_PAR_ERROR V_CL7_IF_PAR_ERROR(1U)
12199 #define S_CL6_IF_PAR_ERROR 6
12200 #define V_CL6_IF_PAR_ERROR(x) ((x) << S_CL6_IF_PAR_ERROR)
12201 #define F_CL6_IF_PAR_ERROR V_CL6_IF_PAR_ERROR(1U)
12203 #define S_CL5_IF_PAR_ERROR 5
12204 #define V_CL5_IF_PAR_ERROR(x) ((x) << S_CL5_IF_PAR_ERROR)
12205 #define F_CL5_IF_PAR_ERROR V_CL5_IF_PAR_ERROR(1U)
12207 #define S_CL4_IF_PAR_ERROR 4
12208 #define V_CL4_IF_PAR_ERROR(x) ((x) << S_CL4_IF_PAR_ERROR)
12209 #define F_CL4_IF_PAR_ERROR V_CL4_IF_PAR_ERROR(1U)
12211 #define S_CL3_IF_PAR_ERROR 3
12212 #define V_CL3_IF_PAR_ERROR(x) ((x) << S_CL3_IF_PAR_ERROR)
12213 #define F_CL3_IF_PAR_ERROR V_CL3_IF_PAR_ERROR(1U)
12215 #define S_CL2_IF_PAR_ERROR 2
12216 #define V_CL2_IF_PAR_ERROR(x) ((x) << S_CL2_IF_PAR_ERROR)
12217 #define F_CL2_IF_PAR_ERROR V_CL2_IF_PAR_ERROR(1U)
12219 #define S_CL1_IF_PAR_ERROR 1
12220 #define V_CL1_IF_PAR_ERROR(x) ((x) << S_CL1_IF_PAR_ERROR)
12221 #define F_CL1_IF_PAR_ERROR V_CL1_IF_PAR_ERROR(1U)
12223 #define S_CL0_IF_PAR_ERROR 0
12224 #define V_CL0_IF_PAR_ERROR(x) ((x) << S_CL0_IF_PAR_ERROR)
12225 #define F_CL0_IF_PAR_ERROR V_CL0_IF_PAR_ERROR(1U)
12227 #define A_MA_LOCAL_DEBUG_CFG 0x78f8
12229 #define S_DEBUG_OR 15
12230 #define V_DEBUG_OR(x) ((x) << S_DEBUG_OR)
12231 #define F_DEBUG_OR V_DEBUG_OR(1U)
12233 #define S_DEBUG_HI 14
12234 #define V_DEBUG_HI(x) ((x) << S_DEBUG_HI)
12235 #define F_DEBUG_HI V_DEBUG_HI(1U)
12237 #define S_DEBUG_RPT 13
12238 #define V_DEBUG_RPT(x) ((x) << S_DEBUG_RPT)
12239 #define F_DEBUG_RPT V_DEBUG_RPT(1U)
12241 #define S_DEBUGPAGE 10
12242 #define M_DEBUGPAGE 0x7U
12243 #define V_DEBUGPAGE(x) ((x) << S_DEBUGPAGE)
12244 #define G_DEBUGPAGE(x) (((x) >> S_DEBUGPAGE) & M_DEBUGPAGE)
12246 #define A_MA_LOCAL_DEBUG_RPT 0x78fc
12248 /* registers for module EDC_0 */
12249 #define EDC_0_BASE_ADDR 0x7900
12251 #define A_EDC_REF 0x7900
12253 #define S_EDC_INST_NUM 18
12254 #define V_EDC_INST_NUM(x) ((x) << S_EDC_INST_NUM)
12255 #define F_EDC_INST_NUM V_EDC_INST_NUM(1U)
12257 #define S_ENABLE_PERF 17
12258 #define V_ENABLE_PERF(x) ((x) << S_ENABLE_PERF)
12259 #define F_ENABLE_PERF V_ENABLE_PERF(1U)
12261 #define S_ECC_BYPASS 16
12262 #define V_ECC_BYPASS(x) ((x) << S_ECC_BYPASS)
12263 #define F_ECC_BYPASS V_ECC_BYPASS(1U)
12265 #define S_REFFREQ 0
12266 #define M_REFFREQ 0xffffU
12267 #define V_REFFREQ(x) ((x) << S_REFFREQ)
12268 #define G_REFFREQ(x) (((x) >> S_REFFREQ) & M_REFFREQ)
12270 #define A_EDC_BIST_CMD 0x7904
12271 #define A_EDC_BIST_CMD_ADDR 0x7908
12272 #define A_EDC_BIST_CMD_LEN 0x790c
12273 #define A_EDC_BIST_DATA_PATTERN 0x7910
12274 #define A_EDC_BIST_USER_WDATA0 0x7914
12275 #define A_EDC_BIST_USER_WDATA1 0x7918
12276 #define A_EDC_BIST_USER_WDATA2 0x791c
12277 #define A_EDC_BIST_NUM_ERR 0x7920
12278 #define A_EDC_BIST_ERR_FIRST_ADDR 0x7924
12279 #define A_EDC_BIST_STATUS_RDATA 0x7928
12280 #define A_EDC_PAR_ENABLE 0x7970
12283 #define V_ECC_UE(x) ((x) << S_ECC_UE)
12284 #define F_ECC_UE V_ECC_UE(1U)
12287 #define V_ECC_CE(x) ((x) << S_ECC_CE)
12288 #define F_ECC_CE V_ECC_CE(1U)
12290 #define A_EDC_INT_ENABLE 0x7974
12291 #define A_EDC_INT_CAUSE 0x7978
12293 #define S_ECC_UE_PAR 5
12294 #define V_ECC_UE_PAR(x) ((x) << S_ECC_UE_PAR)
12295 #define F_ECC_UE_PAR V_ECC_UE_PAR(1U)
12297 #define S_ECC_CE_PAR 4
12298 #define V_ECC_CE_PAR(x) ((x) << S_ECC_CE_PAR)
12299 #define F_ECC_CE_PAR V_ECC_CE_PAR(1U)
12301 #define S_PERR_PAR_CAUSE 3
12302 #define V_PERR_PAR_CAUSE(x) ((x) << S_PERR_PAR_CAUSE)
12303 #define F_PERR_PAR_CAUSE V_PERR_PAR_CAUSE(1U)
12305 #define A_EDC_ECC_STATUS 0x797c
12307 /* registers for module EDC_1 */
12308 #define EDC_1_BASE_ADDR 0x7980
12310 /* registers for module HMA */
12311 #define HMA_BASE_ADDR 0x7a00
12313 /* registers for module CIM */
12314 #define CIM_BASE_ADDR 0x7b00
12316 #define A_CIM_VF_EXT_MAILBOX_CTRL 0x0
12318 #define S_VFMBGENERIC 4
12319 #define M_VFMBGENERIC 0xfU
12320 #define V_VFMBGENERIC(x) ((x) << S_VFMBGENERIC)
12321 #define G_VFMBGENERIC(x) (((x) >> S_VFMBGENERIC) & M_VFMBGENERIC)
12323 #define A_CIM_VF_EXT_MAILBOX_STATUS 0x4
12325 #define S_MBVFREADY 0
12326 #define V_MBVFREADY(x) ((x) << S_MBVFREADY)
12327 #define F_MBVFREADY V_MBVFREADY(1U)
12329 #define A_CIM_PF_MAILBOX_DATA 0x240
12330 #define A_CIM_PF_MAILBOX_CTRL 0x280
12332 #define S_MBGENERIC 4
12333 #define M_MBGENERIC 0xfffffffU
12334 #define V_MBGENERIC(x) ((x) << S_MBGENERIC)
12335 #define G_MBGENERIC(x) (((x) >> S_MBGENERIC) & M_MBGENERIC)
12337 #define S_MBMSGVALID 3
12338 #define V_MBMSGVALID(x) ((x) << S_MBMSGVALID)
12339 #define F_MBMSGVALID V_MBMSGVALID(1U)
12341 #define S_MBINTREQ 2
12342 #define V_MBINTREQ(x) ((x) << S_MBINTREQ)
12343 #define F_MBINTREQ V_MBINTREQ(1U)
12345 #define S_MBOWNER 0
12346 #define M_MBOWNER 0x3U
12347 #define V_MBOWNER(x) ((x) << S_MBOWNER)
12348 #define G_MBOWNER(x) (((x) >> S_MBOWNER) & M_MBOWNER)
12350 #define A_CIM_PF_MAILBOX_ACC_STATUS 0x284
12352 #define S_MBWRBUSY 31
12353 #define V_MBWRBUSY(x) ((x) << S_MBWRBUSY)
12354 #define F_MBWRBUSY V_MBWRBUSY(1U)
12356 #define A_CIM_PF_HOST_INT_ENABLE 0x288
12358 #define S_MBMSGRDYINTEN 19
12359 #define V_MBMSGRDYINTEN(x) ((x) << S_MBMSGRDYINTEN)
12360 #define F_MBMSGRDYINTEN V_MBMSGRDYINTEN(1U)
12362 #define A_CIM_PF_HOST_INT_CAUSE 0x28c
12364 #define S_MBMSGRDYINT 19
12365 #define V_MBMSGRDYINT(x) ((x) << S_MBMSGRDYINT)
12366 #define F_MBMSGRDYINT V_MBMSGRDYINT(1U)
12368 #define A_CIM_PF_MAILBOX_CTRL_SHADOW_COPY 0x290
12369 #define A_CIM_BOOT_CFG 0x7b00
12371 #define S_BOOTADDR 8
12372 #define M_BOOTADDR 0xffffffU
12373 #define V_BOOTADDR(x) ((x) << S_BOOTADDR)
12374 #define G_BOOTADDR(x) (((x) >> S_BOOTADDR) & M_BOOTADDR)
12377 #define M_UPGEN 0x3fU
12378 #define V_UPGEN(x) ((x) << S_UPGEN)
12379 #define G_UPGEN(x) (((x) >> S_UPGEN) & M_UPGEN)
12381 #define S_BOOTSDRAM 1
12382 #define V_BOOTSDRAM(x) ((x) << S_BOOTSDRAM)
12383 #define F_BOOTSDRAM V_BOOTSDRAM(1U)
12386 #define V_UPCRST(x) ((x) << S_UPCRST)
12387 #define F_UPCRST V_UPCRST(1U)
12389 #define A_CIM_FLASH_BASE_ADDR 0x7b04
12391 #define S_FLASHBASEADDR 6
12392 #define M_FLASHBASEADDR 0x3ffffU
12393 #define V_FLASHBASEADDR(x) ((x) << S_FLASHBASEADDR)
12394 #define G_FLASHBASEADDR(x) (((x) >> S_FLASHBASEADDR) & M_FLASHBASEADDR)
12396 #define A_CIM_FLASH_ADDR_SIZE 0x7b08
12398 #define S_FLASHADDRSIZE 4
12399 #define M_FLASHADDRSIZE 0xfffffU
12400 #define V_FLASHADDRSIZE(x) ((x) << S_FLASHADDRSIZE)
12401 #define G_FLASHADDRSIZE(x) (((x) >> S_FLASHADDRSIZE) & M_FLASHADDRSIZE)
12403 #define A_CIM_EEPROM_BASE_ADDR 0x7b0c
12405 #define S_EEPROMBASEADDR 6
12406 #define M_EEPROMBASEADDR 0x3ffffU
12407 #define V_EEPROMBASEADDR(x) ((x) << S_EEPROMBASEADDR)
12408 #define G_EEPROMBASEADDR(x) (((x) >> S_EEPROMBASEADDR) & M_EEPROMBASEADDR)
12410 #define A_CIM_EEPROM_ADDR_SIZE 0x7b10
12412 #define S_EEPROMADDRSIZE 4
12413 #define M_EEPROMADDRSIZE 0xfffffU
12414 #define V_EEPROMADDRSIZE(x) ((x) << S_EEPROMADDRSIZE)
12415 #define G_EEPROMADDRSIZE(x) (((x) >> S_EEPROMADDRSIZE) & M_EEPROMADDRSIZE)
12417 #define A_CIM_SDRAM_BASE_ADDR 0x7b14
12419 #define S_SDRAMBASEADDR 6
12420 #define M_SDRAMBASEADDR 0x3ffffffU
12421 #define V_SDRAMBASEADDR(x) ((x) << S_SDRAMBASEADDR)
12422 #define G_SDRAMBASEADDR(x) (((x) >> S_SDRAMBASEADDR) & M_SDRAMBASEADDR)
12424 #define A_CIM_SDRAM_ADDR_SIZE 0x7b18
12426 #define S_SDRAMADDRSIZE 4
12427 #define M_SDRAMADDRSIZE 0xfffffffU
12428 #define V_SDRAMADDRSIZE(x) ((x) << S_SDRAMADDRSIZE)
12429 #define G_SDRAMADDRSIZE(x) (((x) >> S_SDRAMADDRSIZE) & M_SDRAMADDRSIZE)
12431 #define A_CIM_EXTMEM2_BASE_ADDR 0x7b1c
12433 #define S_EXTMEM2BASEADDR 6
12434 #define M_EXTMEM2BASEADDR 0x3ffffffU
12435 #define V_EXTMEM2BASEADDR(x) ((x) << S_EXTMEM2BASEADDR)
12436 #define G_EXTMEM2BASEADDR(x) (((x) >> S_EXTMEM2BASEADDR) & M_EXTMEM2BASEADDR)
12438 #define A_CIM_EXTMEM2_ADDR_SIZE 0x7b20
12440 #define S_EXTMEM2ADDRSIZE 4
12441 #define M_EXTMEM2ADDRSIZE 0xfffffffU
12442 #define V_EXTMEM2ADDRSIZE(x) ((x) << S_EXTMEM2ADDRSIZE)
12443 #define G_EXTMEM2ADDRSIZE(x) (((x) >> S_EXTMEM2ADDRSIZE) & M_EXTMEM2ADDRSIZE)
12445 #define A_CIM_UP_SPARE_INT 0x7b24
12447 #define S_TDEBUGINT 4
12448 #define V_TDEBUGINT(x) ((x) << S_TDEBUGINT)
12449 #define F_TDEBUGINT V_TDEBUGINT(1U)
12451 #define S_BOOTVECSEL 3
12452 #define V_BOOTVECSEL(x) ((x) << S_BOOTVECSEL)
12453 #define F_BOOTVECSEL V_BOOTVECSEL(1U)
12455 #define S_UPSPAREINT 0
12456 #define M_UPSPAREINT 0x7U
12457 #define V_UPSPAREINT(x) ((x) << S_UPSPAREINT)
12458 #define G_UPSPAREINT(x) (((x) >> S_UPSPAREINT) & M_UPSPAREINT)
12460 #define A_CIM_HOST_INT_ENABLE 0x7b28
12462 #define S_TIEQOUTPARERRINTEN 20
12463 #define V_TIEQOUTPARERRINTEN(x) ((x) << S_TIEQOUTPARERRINTEN)
12464 #define F_TIEQOUTPARERRINTEN V_TIEQOUTPARERRINTEN(1U)
12466 #define S_TIEQINPARERRINTEN 19
12467 #define V_TIEQINPARERRINTEN(x) ((x) << S_TIEQINPARERRINTEN)
12468 #define F_TIEQINPARERRINTEN V_TIEQINPARERRINTEN(1U)
12470 #define S_MBHOSTPARERR 18
12471 #define V_MBHOSTPARERR(x) ((x) << S_MBHOSTPARERR)
12472 #define F_MBHOSTPARERR V_MBHOSTPARERR(1U)
12474 #define S_MBUPPARERR 17
12475 #define V_MBUPPARERR(x) ((x) << S_MBUPPARERR)
12476 #define F_MBUPPARERR V_MBUPPARERR(1U)
12478 #define S_IBQTP0PARERR 16
12479 #define V_IBQTP0PARERR(x) ((x) << S_IBQTP0PARERR)
12480 #define F_IBQTP0PARERR V_IBQTP0PARERR(1U)
12482 #define S_IBQTP1PARERR 15
12483 #define V_IBQTP1PARERR(x) ((x) << S_IBQTP1PARERR)
12484 #define F_IBQTP1PARERR V_IBQTP1PARERR(1U)
12486 #define S_IBQULPPARERR 14
12487 #define V_IBQULPPARERR(x) ((x) << S_IBQULPPARERR)
12488 #define F_IBQULPPARERR V_IBQULPPARERR(1U)
12490 #define S_IBQSGELOPARERR 13
12491 #define V_IBQSGELOPARERR(x) ((x) << S_IBQSGELOPARERR)
12492 #define F_IBQSGELOPARERR V_IBQSGELOPARERR(1U)
12494 #define S_IBQSGEHIPARERR 12
12495 #define V_IBQSGEHIPARERR(x) ((x) << S_IBQSGEHIPARERR)
12496 #define F_IBQSGEHIPARERR V_IBQSGEHIPARERR(1U)
12498 #define S_IBQNCSIPARERR 11
12499 #define V_IBQNCSIPARERR(x) ((x) << S_IBQNCSIPARERR)
12500 #define F_IBQNCSIPARERR V_IBQNCSIPARERR(1U)
12502 #define S_OBQULP0PARERR 10
12503 #define V_OBQULP0PARERR(x) ((x) << S_OBQULP0PARERR)
12504 #define F_OBQULP0PARERR V_OBQULP0PARERR(1U)
12506 #define S_OBQULP1PARERR 9
12507 #define V_OBQULP1PARERR(x) ((x) << S_OBQULP1PARERR)
12508 #define F_OBQULP1PARERR V_OBQULP1PARERR(1U)
12510 #define S_OBQULP2PARERR 8
12511 #define V_OBQULP2PARERR(x) ((x) << S_OBQULP2PARERR)
12512 #define F_OBQULP2PARERR V_OBQULP2PARERR(1U)
12514 #define S_OBQULP3PARERR 7
12515 #define V_OBQULP3PARERR(x) ((x) << S_OBQULP3PARERR)
12516 #define F_OBQULP3PARERR V_OBQULP3PARERR(1U)
12518 #define S_OBQSGEPARERR 6
12519 #define V_OBQSGEPARERR(x) ((x) << S_OBQSGEPARERR)
12520 #define F_OBQSGEPARERR V_OBQSGEPARERR(1U)
12522 #define S_OBQNCSIPARERR 5
12523 #define V_OBQNCSIPARERR(x) ((x) << S_OBQNCSIPARERR)
12524 #define F_OBQNCSIPARERR V_OBQNCSIPARERR(1U)
12526 #define S_TIMER1INTEN 3
12527 #define V_TIMER1INTEN(x) ((x) << S_TIMER1INTEN)
12528 #define F_TIMER1INTEN V_TIMER1INTEN(1U)
12530 #define S_TIMER0INTEN 2
12531 #define V_TIMER0INTEN(x) ((x) << S_TIMER0INTEN)
12532 #define F_TIMER0INTEN V_TIMER0INTEN(1U)
12534 #define S_PREFDROPINTEN 1
12535 #define V_PREFDROPINTEN(x) ((x) << S_PREFDROPINTEN)
12536 #define F_PREFDROPINTEN V_PREFDROPINTEN(1U)
12538 #define S_MA_CIM_INTFPERR 28
12539 #define V_MA_CIM_INTFPERR(x) ((x) << S_MA_CIM_INTFPERR)
12540 #define F_MA_CIM_INTFPERR V_MA_CIM_INTFPERR(1U)
12542 #define S_PLCIM_MSTRSPDATAPARERR 27
12543 #define V_PLCIM_MSTRSPDATAPARERR(x) ((x) << S_PLCIM_MSTRSPDATAPARERR)
12544 #define F_PLCIM_MSTRSPDATAPARERR V_PLCIM_MSTRSPDATAPARERR(1U)
12546 #define S_NCSI2CIMINTFPARERR 26
12547 #define V_NCSI2CIMINTFPARERR(x) ((x) << S_NCSI2CIMINTFPARERR)
12548 #define F_NCSI2CIMINTFPARERR V_NCSI2CIMINTFPARERR(1U)
12550 #define S_SGE2CIMINTFPARERR 25
12551 #define V_SGE2CIMINTFPARERR(x) ((x) << S_SGE2CIMINTFPARERR)
12552 #define F_SGE2CIMINTFPARERR V_SGE2CIMINTFPARERR(1U)
12554 #define S_ULP2CIMINTFPARERR 24
12555 #define V_ULP2CIMINTFPARERR(x) ((x) << S_ULP2CIMINTFPARERR)
12556 #define F_ULP2CIMINTFPARERR V_ULP2CIMINTFPARERR(1U)
12558 #define S_TP2CIMINTFPARERR 23
12559 #define V_TP2CIMINTFPARERR(x) ((x) << S_TP2CIMINTFPARERR)
12560 #define F_TP2CIMINTFPARERR V_TP2CIMINTFPARERR(1U)
12562 #define S_OBQSGERX1PARERR 22
12563 #define V_OBQSGERX1PARERR(x) ((x) << S_OBQSGERX1PARERR)
12564 #define F_OBQSGERX1PARERR V_OBQSGERX1PARERR(1U)
12566 #define S_OBQSGERX0PARERR 21
12567 #define V_OBQSGERX0PARERR(x) ((x) << S_OBQSGERX0PARERR)
12568 #define F_OBQSGERX0PARERR V_OBQSGERX0PARERR(1U)
12570 #define A_CIM_HOST_INT_CAUSE 0x7b2c
12572 #define S_TIEQOUTPARERRINT 20
12573 #define V_TIEQOUTPARERRINT(x) ((x) << S_TIEQOUTPARERRINT)
12574 #define F_TIEQOUTPARERRINT V_TIEQOUTPARERRINT(1U)
12576 #define S_TIEQINPARERRINT 19
12577 #define V_TIEQINPARERRINT(x) ((x) << S_TIEQINPARERRINT)
12578 #define F_TIEQINPARERRINT V_TIEQINPARERRINT(1U)
12580 #define S_TIMER1INT 3
12581 #define V_TIMER1INT(x) ((x) << S_TIMER1INT)
12582 #define F_TIMER1INT V_TIMER1INT(1U)
12584 #define S_TIMER0INT 2
12585 #define V_TIMER0INT(x) ((x) << S_TIMER0INT)
12586 #define F_TIMER0INT V_TIMER0INT(1U)
12588 #define S_PREFDROPINT 1
12589 #define V_PREFDROPINT(x) ((x) << S_PREFDROPINT)
12590 #define F_PREFDROPINT V_PREFDROPINT(1U)
12592 #define S_UPACCNONZERO 0
12593 #define V_UPACCNONZERO(x) ((x) << S_UPACCNONZERO)
12594 #define F_UPACCNONZERO V_UPACCNONZERO(1U)
12596 #define A_CIM_HOST_UPACC_INT_ENABLE 0x7b30
12598 #define S_EEPROMWRINTEN 30
12599 #define V_EEPROMWRINTEN(x) ((x) << S_EEPROMWRINTEN)
12600 #define F_EEPROMWRINTEN V_EEPROMWRINTEN(1U)
12602 #define S_TIMEOUTMAINTEN 29
12603 #define V_TIMEOUTMAINTEN(x) ((x) << S_TIMEOUTMAINTEN)
12604 #define F_TIMEOUTMAINTEN V_TIMEOUTMAINTEN(1U)
12606 #define S_TIMEOUTINTEN 28
12607 #define V_TIMEOUTINTEN(x) ((x) << S_TIMEOUTINTEN)
12608 #define F_TIMEOUTINTEN V_TIMEOUTINTEN(1U)
12610 #define S_RSPOVRLOOKUPINTEN 27
12611 #define V_RSPOVRLOOKUPINTEN(x) ((x) << S_RSPOVRLOOKUPINTEN)
12612 #define F_RSPOVRLOOKUPINTEN V_RSPOVRLOOKUPINTEN(1U)
12614 #define S_REQOVRLOOKUPINTEN 26
12615 #define V_REQOVRLOOKUPINTEN(x) ((x) << S_REQOVRLOOKUPINTEN)
12616 #define F_REQOVRLOOKUPINTEN V_REQOVRLOOKUPINTEN(1U)
12618 #define S_BLKWRPLINTEN 25
12619 #define V_BLKWRPLINTEN(x) ((x) << S_BLKWRPLINTEN)
12620 #define F_BLKWRPLINTEN V_BLKWRPLINTEN(1U)
12622 #define S_BLKRDPLINTEN 24
12623 #define V_BLKRDPLINTEN(x) ((x) << S_BLKRDPLINTEN)
12624 #define F_BLKRDPLINTEN V_BLKRDPLINTEN(1U)
12626 #define S_SGLWRPLINTEN 23
12627 #define V_SGLWRPLINTEN(x) ((x) << S_SGLWRPLINTEN)
12628 #define F_SGLWRPLINTEN V_SGLWRPLINTEN(1U)
12630 #define S_SGLRDPLINTEN 22
12631 #define V_SGLRDPLINTEN(x) ((x) << S_SGLRDPLINTEN)
12632 #define F_SGLRDPLINTEN V_SGLRDPLINTEN(1U)
12634 #define S_BLKWRCTLINTEN 21
12635 #define V_BLKWRCTLINTEN(x) ((x) << S_BLKWRCTLINTEN)
12636 #define F_BLKWRCTLINTEN V_BLKWRCTLINTEN(1U)
12638 #define S_BLKRDCTLINTEN 20
12639 #define V_BLKRDCTLINTEN(x) ((x) << S_BLKRDCTLINTEN)
12640 #define F_BLKRDCTLINTEN V_BLKRDCTLINTEN(1U)
12642 #define S_SGLWRCTLINTEN 19
12643 #define V_SGLWRCTLINTEN(x) ((x) << S_SGLWRCTLINTEN)
12644 #define F_SGLWRCTLINTEN V_SGLWRCTLINTEN(1U)
12646 #define S_SGLRDCTLINTEN 18
12647 #define V_SGLRDCTLINTEN(x) ((x) << S_SGLRDCTLINTEN)
12648 #define F_SGLRDCTLINTEN V_SGLRDCTLINTEN(1U)
12650 #define S_BLKWREEPROMINTEN 17
12651 #define V_BLKWREEPROMINTEN(x) ((x) << S_BLKWREEPROMINTEN)
12652 #define F_BLKWREEPROMINTEN V_BLKWREEPROMINTEN(1U)
12654 #define S_BLKRDEEPROMINTEN 16
12655 #define V_BLKRDEEPROMINTEN(x) ((x) << S_BLKRDEEPROMINTEN)
12656 #define F_BLKRDEEPROMINTEN V_BLKRDEEPROMINTEN(1U)
12658 #define S_SGLWREEPROMINTEN 15
12659 #define V_SGLWREEPROMINTEN(x) ((x) << S_SGLWREEPROMINTEN)
12660 #define F_SGLWREEPROMINTEN V_SGLWREEPROMINTEN(1U)
12662 #define S_SGLRDEEPROMINTEN 14
12663 #define V_SGLRDEEPROMINTEN(x) ((x) << S_SGLRDEEPROMINTEN)
12664 #define F_SGLRDEEPROMINTEN V_SGLRDEEPROMINTEN(1U)
12666 #define S_BLKWRFLASHINTEN 13
12667 #define V_BLKWRFLASHINTEN(x) ((x) << S_BLKWRFLASHINTEN)
12668 #define F_BLKWRFLASHINTEN V_BLKWRFLASHINTEN(1U)
12670 #define S_BLKRDFLASHINTEN 12
12671 #define V_BLKRDFLASHINTEN(x) ((x) << S_BLKRDFLASHINTEN)
12672 #define F_BLKRDFLASHINTEN V_BLKRDFLASHINTEN(1U)
12674 #define S_SGLWRFLASHINTEN 11
12675 #define V_SGLWRFLASHINTEN(x) ((x) << S_SGLWRFLASHINTEN)
12676 #define F_SGLWRFLASHINTEN V_SGLWRFLASHINTEN(1U)
12678 #define S_SGLRDFLASHINTEN 10
12679 #define V_SGLRDFLASHINTEN(x) ((x) << S_SGLRDFLASHINTEN)
12680 #define F_SGLRDFLASHINTEN V_SGLRDFLASHINTEN(1U)
12682 #define S_BLKWRBOOTINTEN 9
12683 #define V_BLKWRBOOTINTEN(x) ((x) << S_BLKWRBOOTINTEN)
12684 #define F_BLKWRBOOTINTEN V_BLKWRBOOTINTEN(1U)
12686 #define S_BLKRDBOOTINTEN 8
12687 #define V_BLKRDBOOTINTEN(x) ((x) << S_BLKRDBOOTINTEN)
12688 #define F_BLKRDBOOTINTEN V_BLKRDBOOTINTEN(1U)
12690 #define S_SGLWRBOOTINTEN 7
12691 #define V_SGLWRBOOTINTEN(x) ((x) << S_SGLWRBOOTINTEN)
12692 #define F_SGLWRBOOTINTEN V_SGLWRBOOTINTEN(1U)
12694 #define S_SGLRDBOOTINTEN 6
12695 #define V_SGLRDBOOTINTEN(x) ((x) << S_SGLRDBOOTINTEN)
12696 #define F_SGLRDBOOTINTEN V_SGLRDBOOTINTEN(1U)
12698 #define S_ILLWRBEINTEN 5
12699 #define V_ILLWRBEINTEN(x) ((x) << S_ILLWRBEINTEN)
12700 #define F_ILLWRBEINTEN V_ILLWRBEINTEN(1U)
12702 #define S_ILLRDBEINTEN 4
12703 #define V_ILLRDBEINTEN(x) ((x) << S_ILLRDBEINTEN)
12704 #define F_ILLRDBEINTEN V_ILLRDBEINTEN(1U)
12706 #define S_ILLRDINTEN 3
12707 #define V_ILLRDINTEN(x) ((x) << S_ILLRDINTEN)
12708 #define F_ILLRDINTEN V_ILLRDINTEN(1U)
12710 #define S_ILLWRINTEN 2
12711 #define V_ILLWRINTEN(x) ((x) << S_ILLWRINTEN)
12712 #define F_ILLWRINTEN V_ILLWRINTEN(1U)
12714 #define S_ILLTRANSINTEN 1
12715 #define V_ILLTRANSINTEN(x) ((x) << S_ILLTRANSINTEN)
12716 #define F_ILLTRANSINTEN V_ILLTRANSINTEN(1U)
12718 #define S_RSVDSPACEINTEN 0
12719 #define V_RSVDSPACEINTEN(x) ((x) << S_RSVDSPACEINTEN)
12720 #define F_RSVDSPACEINTEN V_RSVDSPACEINTEN(1U)
12722 #define A_CIM_HOST_UPACC_INT_CAUSE 0x7b34
12724 #define S_EEPROMWRINT 30
12725 #define V_EEPROMWRINT(x) ((x) << S_EEPROMWRINT)
12726 #define F_EEPROMWRINT V_EEPROMWRINT(1U)
12728 #define S_TIMEOUTMAINT 29
12729 #define V_TIMEOUTMAINT(x) ((x) << S_TIMEOUTMAINT)
12730 #define F_TIMEOUTMAINT V_TIMEOUTMAINT(1U)
12732 #define S_TIMEOUTINT 28
12733 #define V_TIMEOUTINT(x) ((x) << S_TIMEOUTINT)
12734 #define F_TIMEOUTINT V_TIMEOUTINT(1U)
12736 #define S_RSPOVRLOOKUPINT 27
12737 #define V_RSPOVRLOOKUPINT(x) ((x) << S_RSPOVRLOOKUPINT)
12738 #define F_RSPOVRLOOKUPINT V_RSPOVRLOOKUPINT(1U)
12740 #define S_REQOVRLOOKUPINT 26
12741 #define V_REQOVRLOOKUPINT(x) ((x) << S_REQOVRLOOKUPINT)
12742 #define F_REQOVRLOOKUPINT V_REQOVRLOOKUPINT(1U)
12744 #define S_BLKWRPLINT 25
12745 #define V_BLKWRPLINT(x) ((x) << S_BLKWRPLINT)
12746 #define F_BLKWRPLINT V_BLKWRPLINT(1U)
12748 #define S_BLKRDPLINT 24
12749 #define V_BLKRDPLINT(x) ((x) << S_BLKRDPLINT)
12750 #define F_BLKRDPLINT V_BLKRDPLINT(1U)
12752 #define S_SGLWRPLINT 23
12753 #define V_SGLWRPLINT(x) ((x) << S_SGLWRPLINT)
12754 #define F_SGLWRPLINT V_SGLWRPLINT(1U)
12756 #define S_SGLRDPLINT 22
12757 #define V_SGLRDPLINT(x) ((x) << S_SGLRDPLINT)
12758 #define F_SGLRDPLINT V_SGLRDPLINT(1U)
12760 #define S_BLKWRCTLINT 21
12761 #define V_BLKWRCTLINT(x) ((x) << S_BLKWRCTLINT)
12762 #define F_BLKWRCTLINT V_BLKWRCTLINT(1U)
12764 #define S_BLKRDCTLINT 20
12765 #define V_BLKRDCTLINT(x) ((x) << S_BLKRDCTLINT)
12766 #define F_BLKRDCTLINT V_BLKRDCTLINT(1U)
12768 #define S_SGLWRCTLINT 19
12769 #define V_SGLWRCTLINT(x) ((x) << S_SGLWRCTLINT)
12770 #define F_SGLWRCTLINT V_SGLWRCTLINT(1U)
12772 #define S_SGLRDCTLINT 18
12773 #define V_SGLRDCTLINT(x) ((x) << S_SGLRDCTLINT)
12774 #define F_SGLRDCTLINT V_SGLRDCTLINT(1U)
12776 #define S_BLKWREEPROMINT 17
12777 #define V_BLKWREEPROMINT(x) ((x) << S_BLKWREEPROMINT)
12778 #define F_BLKWREEPROMINT V_BLKWREEPROMINT(1U)
12780 #define S_BLKRDEEPROMINT 16
12781 #define V_BLKRDEEPROMINT(x) ((x) << S_BLKRDEEPROMINT)
12782 #define F_BLKRDEEPROMINT V_BLKRDEEPROMINT(1U)
12784 #define S_SGLWREEPROMINT 15
12785 #define V_SGLWREEPROMINT(x) ((x) << S_SGLWREEPROMINT)
12786 #define F_SGLWREEPROMINT V_SGLWREEPROMINT(1U)
12788 #define S_SGLRDEEPROMINT 14
12789 #define V_SGLRDEEPROMINT(x) ((x) << S_SGLRDEEPROMINT)
12790 #define F_SGLRDEEPROMINT V_SGLRDEEPROMINT(1U)
12792 #define S_BLKWRFLASHINT 13
12793 #define V_BLKWRFLASHINT(x) ((x) << S_BLKWRFLASHINT)
12794 #define F_BLKWRFLASHINT V_BLKWRFLASHINT(1U)
12796 #define S_BLKRDFLASHINT 12
12797 #define V_BLKRDFLASHINT(x) ((x) << S_BLKRDFLASHINT)
12798 #define F_BLKRDFLASHINT V_BLKRDFLASHINT(1U)
12800 #define S_SGLWRFLASHINT 11
12801 #define V_SGLWRFLASHINT(x) ((x) << S_SGLWRFLASHINT)
12802 #define F_SGLWRFLASHINT V_SGLWRFLASHINT(1U)
12804 #define S_SGLRDFLASHINT 10
12805 #define V_SGLRDFLASHINT(x) ((x) << S_SGLRDFLASHINT)
12806 #define F_SGLRDFLASHINT V_SGLRDFLASHINT(1U)
12808 #define S_BLKWRBOOTINT 9
12809 #define V_BLKWRBOOTINT(x) ((x) << S_BLKWRBOOTINT)
12810 #define F_BLKWRBOOTINT V_BLKWRBOOTINT(1U)
12812 #define S_BLKRDBOOTINT 8
12813 #define V_BLKRDBOOTINT(x) ((x) << S_BLKRDBOOTINT)
12814 #define F_BLKRDBOOTINT V_BLKRDBOOTINT(1U)
12816 #define S_SGLWRBOOTINT 7
12817 #define V_SGLWRBOOTINT(x) ((x) << S_SGLWRBOOTINT)
12818 #define F_SGLWRBOOTINT V_SGLWRBOOTINT(1U)
12820 #define S_SGLRDBOOTINT 6
12821 #define V_SGLRDBOOTINT(x) ((x) << S_SGLRDBOOTINT)
12822 #define F_SGLRDBOOTINT V_SGLRDBOOTINT(1U)
12824 #define S_ILLWRBEINT 5
12825 #define V_ILLWRBEINT(x) ((x) << S_ILLWRBEINT)
12826 #define F_ILLWRBEINT V_ILLWRBEINT(1U)
12828 #define S_ILLRDBEINT 4
12829 #define V_ILLRDBEINT(x) ((x) << S_ILLRDBEINT)
12830 #define F_ILLRDBEINT V_ILLRDBEINT(1U)
12832 #define S_ILLRDINT 3
12833 #define V_ILLRDINT(x) ((x) << S_ILLRDINT)
12834 #define F_ILLRDINT V_ILLRDINT(1U)
12836 #define S_ILLWRINT 2
12837 #define V_ILLWRINT(x) ((x) << S_ILLWRINT)
12838 #define F_ILLWRINT V_ILLWRINT(1U)
12840 #define S_ILLTRANSINT 1
12841 #define V_ILLTRANSINT(x) ((x) << S_ILLTRANSINT)
12842 #define F_ILLTRANSINT V_ILLTRANSINT(1U)
12844 #define S_RSVDSPACEINT 0
12845 #define V_RSVDSPACEINT(x) ((x) << S_RSVDSPACEINT)
12846 #define F_RSVDSPACEINT V_RSVDSPACEINT(1U)
12848 #define A_CIM_UP_INT_ENABLE 0x7b38
12850 #define S_MSTPLINTEN 4
12851 #define V_MSTPLINTEN(x) ((x) << S_MSTPLINTEN)
12852 #define F_MSTPLINTEN V_MSTPLINTEN(1U)
12854 #define A_CIM_UP_INT_CAUSE 0x7b3c
12856 #define S_MSTPLINT 4
12857 #define V_MSTPLINT(x) ((x) << S_MSTPLINT)
12858 #define F_MSTPLINT V_MSTPLINT(1U)
12860 #define A_CIM_UP_ACC_INT_ENABLE 0x7b40
12861 #define A_CIM_UP_ACC_INT_CAUSE 0x7b44
12862 #define A_CIM_QUEUE_CONFIG_REF 0x7b48
12864 #define S_OBQSELECT 4
12865 #define V_OBQSELECT(x) ((x) << S_OBQSELECT)
12866 #define F_OBQSELECT V_OBQSELECT(1U)
12868 #define S_IBQSELECT 3
12869 #define V_IBQSELECT(x) ((x) << S_IBQSELECT)
12870 #define F_IBQSELECT V_IBQSELECT(1U)
12872 #define S_QUENUMSELECT 0
12873 #define M_QUENUMSELECT 0x7U
12874 #define V_QUENUMSELECT(x) ((x) << S_QUENUMSELECT)
12875 #define G_QUENUMSELECT(x) (((x) >> S_QUENUMSELECT) & M_QUENUMSELECT)
12877 #define A_CIM_QUEUE_CONFIG_CTRL 0x7b4c
12879 #define S_CIMQSIZE 24
12880 #define M_CIMQSIZE 0x3fU
12881 #define V_CIMQSIZE(x) ((x) << S_CIMQSIZE)
12882 #define G_CIMQSIZE(x) (((x) >> S_CIMQSIZE) & M_CIMQSIZE)
12884 #define S_CIMQBASE 16
12885 #define M_CIMQBASE 0x3fU
12886 #define V_CIMQBASE(x) ((x) << S_CIMQBASE)
12887 #define G_CIMQBASE(x) (((x) >> S_CIMQBASE) & M_CIMQBASE)
12889 #define S_CIMQDBG8BEN 9
12890 #define V_CIMQDBG8BEN(x) ((x) << S_CIMQDBG8BEN)
12891 #define F_CIMQDBG8BEN V_CIMQDBG8BEN(1U)
12893 #define S_QUEFULLTHRSH 0
12894 #define M_QUEFULLTHRSH 0x1ffU
12895 #define V_QUEFULLTHRSH(x) ((x) << S_QUEFULLTHRSH)
12896 #define G_QUEFULLTHRSH(x) (((x) >> S_QUEFULLTHRSH) & M_QUEFULLTHRSH)
12898 #define A_CIM_HOST_ACC_CTRL 0x7b50
12900 #define S_HOSTBUSY 17
12901 #define V_HOSTBUSY(x) ((x) << S_HOSTBUSY)
12902 #define F_HOSTBUSY V_HOSTBUSY(1U)
12904 #define S_HOSTWRITE 16
12905 #define V_HOSTWRITE(x) ((x) << S_HOSTWRITE)
12906 #define F_HOSTWRITE V_HOSTWRITE(1U)
12908 #define S_HOSTADDR 0
12909 #define M_HOSTADDR 0xffffU
12910 #define V_HOSTADDR(x) ((x) << S_HOSTADDR)
12911 #define G_HOSTADDR(x) (((x) >> S_HOSTADDR) & M_HOSTADDR)
12913 #define A_CIM_HOST_ACC_DATA 0x7b54
12914 #define A_CIM_CDEBUGDATA 0x7b58
12916 #define S_CDEBUGDATAH 16
12917 #define M_CDEBUGDATAH 0xffffU
12918 #define V_CDEBUGDATAH(x) ((x) << S_CDEBUGDATAH)
12919 #define G_CDEBUGDATAH(x) (((x) >> S_CDEBUGDATAH) & M_CDEBUGDATAH)
12921 #define S_CDEBUGDATAL 0
12922 #define M_CDEBUGDATAL 0xffffU
12923 #define V_CDEBUGDATAL(x) ((x) << S_CDEBUGDATAL)
12924 #define G_CDEBUGDATAL(x) (((x) >> S_CDEBUGDATAL) & M_CDEBUGDATAL)
12926 #define A_CIM_IBQ_DBG_CFG 0x7b60
12928 #define S_IBQDBGADDR 16
12929 #define M_IBQDBGADDR 0xfffU
12930 #define V_IBQDBGADDR(x) ((x) << S_IBQDBGADDR)
12931 #define G_IBQDBGADDR(x) (((x) >> S_IBQDBGADDR) & M_IBQDBGADDR)
12933 #define S_IBQDBGWR 2
12934 #define V_IBQDBGWR(x) ((x) << S_IBQDBGWR)
12935 #define F_IBQDBGWR V_IBQDBGWR(1U)
12937 #define S_IBQDBGBUSY 1
12938 #define V_IBQDBGBUSY(x) ((x) << S_IBQDBGBUSY)
12939 #define F_IBQDBGBUSY V_IBQDBGBUSY(1U)
12941 #define S_IBQDBGEN 0
12942 #define V_IBQDBGEN(x) ((x) << S_IBQDBGEN)
12943 #define F_IBQDBGEN V_IBQDBGEN(1U)
12945 #define A_CIM_OBQ_DBG_CFG 0x7b64
12947 #define S_OBQDBGADDR 16
12948 #define M_OBQDBGADDR 0xfffU
12949 #define V_OBQDBGADDR(x) ((x) << S_OBQDBGADDR)
12950 #define G_OBQDBGADDR(x) (((x) >> S_OBQDBGADDR) & M_OBQDBGADDR)
12952 #define S_OBQDBGWR 2
12953 #define V_OBQDBGWR(x) ((x) << S_OBQDBGWR)
12954 #define F_OBQDBGWR V_OBQDBGWR(1U)
12956 #define S_OBQDBGBUSY 1
12957 #define V_OBQDBGBUSY(x) ((x) << S_OBQDBGBUSY)
12958 #define F_OBQDBGBUSY V_OBQDBGBUSY(1U)
12960 #define S_OBQDBGEN 0
12961 #define V_OBQDBGEN(x) ((x) << S_OBQDBGEN)
12962 #define F_OBQDBGEN V_OBQDBGEN(1U)
12964 #define A_CIM_IBQ_DBG_DATA 0x7b68
12965 #define A_CIM_OBQ_DBG_DATA 0x7b6c
12966 #define A_CIM_DEBUGCFG 0x7b70
12968 #define S_POLADBGRDPTR 23
12969 #define M_POLADBGRDPTR 0x1ffU
12970 #define V_POLADBGRDPTR(x) ((x) << S_POLADBGRDPTR)
12971 #define G_POLADBGRDPTR(x) (((x) >> S_POLADBGRDPTR) & M_POLADBGRDPTR)
12973 #define S_PILADBGRDPTR 14
12974 #define M_PILADBGRDPTR 0x1ffU
12975 #define V_PILADBGRDPTR(x) ((x) << S_PILADBGRDPTR)
12976 #define G_PILADBGRDPTR(x) (((x) >> S_PILADBGRDPTR) & M_PILADBGRDPTR)
12978 #define S_LAMASKTRIG 13
12979 #define V_LAMASKTRIG(x) ((x) << S_LAMASKTRIG)
12980 #define F_LAMASKTRIG V_LAMASKTRIG(1U)
12982 #define S_LADBGEN 12
12983 #define V_LADBGEN(x) ((x) << S_LADBGEN)
12984 #define F_LADBGEN V_LADBGEN(1U)
12986 #define S_LAFILLONCE 11
12987 #define V_LAFILLONCE(x) ((x) << S_LAFILLONCE)
12988 #define F_LAFILLONCE V_LAFILLONCE(1U)
12990 #define S_LAMASKSTOP 10
12991 #define V_LAMASKSTOP(x) ((x) << S_LAMASKSTOP)
12992 #define F_LAMASKSTOP V_LAMASKSTOP(1U)
12994 #define S_DEBUGSELH 5
12995 #define M_DEBUGSELH 0x1fU
12996 #define V_DEBUGSELH(x) ((x) << S_DEBUGSELH)
12997 #define G_DEBUGSELH(x) (((x) >> S_DEBUGSELH) & M_DEBUGSELH)
12999 #define S_DEBUGSELL 0
13000 #define M_DEBUGSELL 0x1fU
13001 #define V_DEBUGSELL(x) ((x) << S_DEBUGSELL)
13002 #define G_DEBUGSELL(x) (((x) >> S_DEBUGSELL) & M_DEBUGSELL)
13004 #define A_CIM_DEBUGSTS 0x7b74
13006 #define S_LARESET 31
13007 #define V_LARESET(x) ((x) << S_LARESET)
13008 #define F_LARESET V_LARESET(1U)
13010 #define S_POLADBGWRPTR 16
13011 #define M_POLADBGWRPTR 0x1ffU
13012 #define V_POLADBGWRPTR(x) ((x) << S_POLADBGWRPTR)
13013 #define G_POLADBGWRPTR(x) (((x) >> S_POLADBGWRPTR) & M_POLADBGWRPTR)
13015 #define S_PILADBGWRPTR 0
13016 #define M_PILADBGWRPTR 0x1ffU
13017 #define V_PILADBGWRPTR(x) ((x) << S_PILADBGWRPTR)
13018 #define G_PILADBGWRPTR(x) (((x) >> S_PILADBGWRPTR) & M_PILADBGWRPTR)
13020 #define A_CIM_PO_LA_DEBUGDATA 0x7b78
13021 #define A_CIM_PI_LA_DEBUGDATA 0x7b7c
13022 #define A_CIM_PO_LA_MADEBUGDATA 0x7b80
13023 #define A_CIM_PI_LA_MADEBUGDATA 0x7b84
13024 #define A_CIM_PO_LA_PIFSMDEBUGDATA 0x7b8c
13025 #define A_CIM_MEM_ZONE0_VA 0x7b90
13027 #define S_MEM_ZONE_VA 4
13028 #define M_MEM_ZONE_VA 0xfffffffU
13029 #define V_MEM_ZONE_VA(x) ((x) << S_MEM_ZONE_VA)
13030 #define G_MEM_ZONE_VA(x) (((x) >> S_MEM_ZONE_VA) & M_MEM_ZONE_VA)
13032 #define A_CIM_MEM_ZONE0_BA 0x7b94
13034 #define S_MEM_ZONE_BA 6
13035 #define M_MEM_ZONE_BA 0x3ffffffU
13036 #define V_MEM_ZONE_BA(x) ((x) << S_MEM_ZONE_BA)
13037 #define G_MEM_ZONE_BA(x) (((x) >> S_MEM_ZONE_BA) & M_MEM_ZONE_BA)
13039 #define S_PBT_ENABLE 5
13040 #define V_PBT_ENABLE(x) ((x) << S_PBT_ENABLE)
13041 #define F_PBT_ENABLE V_PBT_ENABLE(1U)
13043 #define S_ZONE_DST 0
13044 #define M_ZONE_DST 0x3U
13045 #define V_ZONE_DST(x) ((x) << S_ZONE_DST)
13046 #define G_ZONE_DST(x) (((x) >> S_ZONE_DST) & M_ZONE_DST)
13048 #define A_CIM_MEM_ZONE0_LEN 0x7b98
13050 #define S_MEM_ZONE_LEN 4
13051 #define M_MEM_ZONE_LEN 0xfffffffU
13052 #define V_MEM_ZONE_LEN(x) ((x) << S_MEM_ZONE_LEN)
13053 #define G_MEM_ZONE_LEN(x) (((x) >> S_MEM_ZONE_LEN) & M_MEM_ZONE_LEN)
13055 #define A_CIM_MEM_ZONE1_VA 0x7b9c
13056 #define A_CIM_MEM_ZONE1_BA 0x7ba0
13057 #define A_CIM_MEM_ZONE1_LEN 0x7ba4
13058 #define A_CIM_MEM_ZONE2_VA 0x7ba8
13059 #define A_CIM_MEM_ZONE2_BA 0x7bac
13060 #define A_CIM_MEM_ZONE2_LEN 0x7bb0
13061 #define A_CIM_MEM_ZONE3_VA 0x7bb4
13062 #define A_CIM_MEM_ZONE3_BA 0x7bb8
13063 #define A_CIM_MEM_ZONE3_LEN 0x7bbc
13064 #define A_CIM_MEM_ZONE4_VA 0x7bc0
13065 #define A_CIM_MEM_ZONE4_BA 0x7bc4
13066 #define A_CIM_MEM_ZONE4_LEN 0x7bc8
13067 #define A_CIM_MEM_ZONE5_VA 0x7bcc
13068 #define A_CIM_MEM_ZONE5_BA 0x7bd0
13069 #define A_CIM_MEM_ZONE5_LEN 0x7bd4
13070 #define A_CIM_MEM_ZONE6_VA 0x7bd8
13071 #define A_CIM_MEM_ZONE6_BA 0x7bdc
13072 #define A_CIM_MEM_ZONE6_LEN 0x7be0
13073 #define A_CIM_MEM_ZONE7_VA 0x7be4
13074 #define A_CIM_MEM_ZONE7_BA 0x7be8
13075 #define A_CIM_MEM_ZONE7_LEN 0x7bec
13076 #define A_CIM_BOOT_LEN 0x7bf0
13078 #define S_BOOTLEN 4
13079 #define M_BOOTLEN 0xfffffffU
13080 #define V_BOOTLEN(x) ((x) << S_BOOTLEN)
13081 #define G_BOOTLEN(x) (((x) >> S_BOOTLEN) & M_BOOTLEN)
13083 #define A_CIM_GLB_TIMER_CTL 0x7bf4
13085 #define S_TIMER1EN 4
13086 #define V_TIMER1EN(x) ((x) << S_TIMER1EN)
13087 #define F_TIMER1EN V_TIMER1EN(1U)
13089 #define S_TIMER0EN 3
13090 #define V_TIMER0EN(x) ((x) << S_TIMER0EN)
13091 #define F_TIMER0EN V_TIMER0EN(1U)
13093 #define S_TIMEREN 1
13094 #define V_TIMEREN(x) ((x) << S_TIMEREN)
13095 #define F_TIMEREN V_TIMEREN(1U)
13097 #define A_CIM_GLB_TIMER 0x7bf8
13098 #define A_CIM_GLB_TIMER_TICK 0x7bfc
13100 #define S_GLBLTTICK 0
13101 #define M_GLBLTTICK 0xffffU
13102 #define V_GLBLTTICK(x) ((x) << S_GLBLTTICK)
13103 #define G_GLBLTTICK(x) (((x) >> S_GLBLTTICK) & M_GLBLTTICK)
13105 #define A_CIM_TIMER0 0x7c00
13106 #define A_CIM_TIMER1 0x7c04
13107 #define A_CIM_DEBUG_ADDR_TIMEOUT 0x7c08
13109 #define S_DADDRTIMEOUT 2
13110 #define M_DADDRTIMEOUT 0x3fffffffU
13111 #define V_DADDRTIMEOUT(x) ((x) << S_DADDRTIMEOUT)
13112 #define G_DADDRTIMEOUT(x) (((x) >> S_DADDRTIMEOUT) & M_DADDRTIMEOUT)
13114 #define A_CIM_DEBUG_ADDR_ILLEGAL 0x7c0c
13116 #define S_DADDRILLEGAL 2
13117 #define M_DADDRILLEGAL 0x3fffffffU
13118 #define V_DADDRILLEGAL(x) ((x) << S_DADDRILLEGAL)
13119 #define G_DADDRILLEGAL(x) (((x) >> S_DADDRILLEGAL) & M_DADDRILLEGAL)
13121 #define A_CIM_DEBUG_PIF_CAUSE_MASK 0x7c10
13123 #define S_DPIFHOSTMASK 0
13124 #define M_DPIFHOSTMASK 0x1fffffU
13125 #define V_DPIFHOSTMASK(x) ((x) << S_DPIFHOSTMASK)
13126 #define G_DPIFHOSTMASK(x) (((x) >> S_DPIFHOSTMASK) & M_DPIFHOSTMASK)
13128 #define S_T5_DPIFHOSTMASK 0
13129 #define M_T5_DPIFHOSTMASK 0x1fffffffU
13130 #define V_T5_DPIFHOSTMASK(x) ((x) << S_T5_DPIFHOSTMASK)
13131 #define G_T5_DPIFHOSTMASK(x) (((x) >> S_T5_DPIFHOSTMASK) & M_T5_DPIFHOSTMASK)
13133 #define A_CIM_DEBUG_PIF_UPACC_CAUSE_MASK 0x7c14
13135 #define S_DPIFHUPAMASK 0
13136 #define M_DPIFHUPAMASK 0x7fffffffU
13137 #define V_DPIFHUPAMASK(x) ((x) << S_DPIFHUPAMASK)
13138 #define G_DPIFHUPAMASK(x) (((x) >> S_DPIFHUPAMASK) & M_DPIFHUPAMASK)
13140 #define A_CIM_DEBUG_UP_CAUSE_MASK 0x7c18
13142 #define S_DUPMASK 0
13143 #define M_DUPMASK 0x1fffffU
13144 #define V_DUPMASK(x) ((x) << S_DUPMASK)
13145 #define G_DUPMASK(x) (((x) >> S_DUPMASK) & M_DUPMASK)
13147 #define S_T5_DUPMASK 0
13148 #define M_T5_DUPMASK 0x1fffffffU
13149 #define V_T5_DUPMASK(x) ((x) << S_T5_DUPMASK)
13150 #define G_T5_DUPMASK(x) (((x) >> S_T5_DUPMASK) & M_T5_DUPMASK)
13152 #define A_CIM_DEBUG_UP_UPACC_CAUSE_MASK 0x7c1c
13154 #define S_DUPUACCMASK 0
13155 #define M_DUPUACCMASK 0x7fffffffU
13156 #define V_DUPUACCMASK(x) ((x) << S_DUPUACCMASK)
13157 #define G_DUPUACCMASK(x) (((x) >> S_DUPUACCMASK) & M_DUPUACCMASK)
13159 #define A_CIM_PERR_INJECT 0x7c20
13160 #define A_CIM_PERR_ENABLE 0x7c24
13163 #define M_PERREN 0x1fffffU
13164 #define V_PERREN(x) ((x) << S_PERREN)
13165 #define G_PERREN(x) (((x) >> S_PERREN) & M_PERREN)
13167 #define S_T5_PERREN 0
13168 #define M_T5_PERREN 0x1fffffffU
13169 #define V_T5_PERREN(x) ((x) << S_T5_PERREN)
13170 #define G_T5_PERREN(x) (((x) >> S_T5_PERREN) & M_T5_PERREN)
13172 #define A_CIM_EEPROM_BUSY_BIT 0x7c28
13174 #define S_EEPROMBUSY 0
13175 #define V_EEPROMBUSY(x) ((x) << S_EEPROMBUSY)
13176 #define F_EEPROMBUSY V_EEPROMBUSY(1U)
13178 #define A_CIM_MA_TIMER_EN 0x7c2c
13180 #define S_MA_TIMER_ENABLE 0
13181 #define V_MA_TIMER_ENABLE(x) ((x) << S_MA_TIMER_ENABLE)
13182 #define F_MA_TIMER_ENABLE V_MA_TIMER_ENABLE(1U)
13184 #define A_CIM_UP_PO_SINGLE_OUTSTANDING 0x7c30
13186 #define S_UP_PO_SINGLE_OUTSTANDING 0
13187 #define V_UP_PO_SINGLE_OUTSTANDING(x) ((x) << S_UP_PO_SINGLE_OUTSTANDING)
13188 #define F_UP_PO_SINGLE_OUTSTANDING V_UP_PO_SINGLE_OUTSTANDING(1U)
13190 #define A_CIM_CIM_DEBUG_SPARE 0x7c34
13191 #define A_CIM_UP_OPERATION_FREQ 0x7c38
13192 #define A_CIM_CIM_IBQ_ERR_CODE 0x7c3c
13194 #define S_CIM_ULP_TX_PKT_ERR_CODE 16
13195 #define M_CIM_ULP_TX_PKT_ERR_CODE 0xffU
13196 #define V_CIM_ULP_TX_PKT_ERR_CODE(x) ((x) << S_CIM_ULP_TX_PKT_ERR_CODE)
13197 #define G_CIM_ULP_TX_PKT_ERR_CODE(x) (((x) >> S_CIM_ULP_TX_PKT_ERR_CODE) & M_CIM_ULP_TX_PKT_ERR_CODE)
13199 #define S_CIM_SGE1_PKT_ERR_CODE 8
13200 #define M_CIM_SGE1_PKT_ERR_CODE 0xffU
13201 #define V_CIM_SGE1_PKT_ERR_CODE(x) ((x) << S_CIM_SGE1_PKT_ERR_CODE)
13202 #define G_CIM_SGE1_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE1_PKT_ERR_CODE) & M_CIM_SGE1_PKT_ERR_CODE)
13204 #define S_CIM_SGE0_PKT_ERR_CODE 0
13205 #define M_CIM_SGE0_PKT_ERR_CODE 0xffU
13206 #define V_CIM_SGE0_PKT_ERR_CODE(x) ((x) << S_CIM_SGE0_PKT_ERR_CODE)
13207 #define G_CIM_SGE0_PKT_ERR_CODE(x) (((x) >> S_CIM_SGE0_PKT_ERR_CODE) & M_CIM_SGE0_PKT_ERR_CODE)
13209 #define A_CIM_IBQ_DBG_WAIT_COUNTER 0x7c40
13210 #define A_CIM_PIO_UP_MST_CFG_SEL 0x7c44
13212 #define S_PIO_UP_MST_CFG_SEL 0
13213 #define V_PIO_UP_MST_CFG_SEL(x) ((x) << S_PIO_UP_MST_CFG_SEL)
13214 #define F_PIO_UP_MST_CFG_SEL V_PIO_UP_MST_CFG_SEL(1U)
13216 #define A_CIM_CGEN 0x7c48
13218 #define S_TSCH_CGEN 0
13219 #define V_TSCH_CGEN(x) ((x) << S_TSCH_CGEN)
13220 #define F_TSCH_CGEN V_TSCH_CGEN(1U)
13222 #define A_CIM_QUEUE_FEATURE_DISABLE 0x7c4c
13224 #define S_OBQ_THROUTTLE_ON_EOP 4
13225 #define V_OBQ_THROUTTLE_ON_EOP(x) ((x) << S_OBQ_THROUTTLE_ON_EOP)
13226 #define F_OBQ_THROUTTLE_ON_EOP V_OBQ_THROUTTLE_ON_EOP(1U)
13228 #define S_OBQ_READ_CTL_PERF_MODE_DISABLE 3
13229 #define V_OBQ_READ_CTL_PERF_MODE_DISABLE(x) ((x) << S_OBQ_READ_CTL_PERF_MODE_DISABLE)
13230 #define F_OBQ_READ_CTL_PERF_MODE_DISABLE V_OBQ_READ_CTL_PERF_MODE_DISABLE(1U)
13232 #define S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE 2
13233 #define V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(x) ((x) << S_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE)
13234 #define F_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE V_OBQ_WAIT_FOR_EOP_FLUSH_DISABLE(1U)
13236 #define S_IBQ_RRA_DSBL 1
13237 #define V_IBQ_RRA_DSBL(x) ((x) << S_IBQ_RRA_DSBL)
13238 #define F_IBQ_RRA_DSBL V_IBQ_RRA_DSBL(1U)
13240 #define S_IBQ_SKID_FIFO_EOP_FLSH_DSBL 0
13241 #define V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(x) ((x) << S_IBQ_SKID_FIFO_EOP_FLSH_DSBL)
13242 #define F_IBQ_SKID_FIFO_EOP_FLSH_DSBL V_IBQ_SKID_FIFO_EOP_FLSH_DSBL(1U)
13244 #define A_CIM_CGEN_GLOBAL 0x7c50
13246 #define S_CGEN_GLOBAL 0
13247 #define V_CGEN_GLOBAL(x) ((x) << S_CGEN_GLOBAL)
13248 #define F_CGEN_GLOBAL V_CGEN_GLOBAL(1U)
13250 #define A_CIM_DPSLP_EN 0x7c54
13252 #define S_PIFDBGLA_DPSLP_EN 0
13253 #define V_PIFDBGLA_DPSLP_EN(x) ((x) << S_PIFDBGLA_DPSLP_EN)
13254 #define F_PIFDBGLA_DPSLP_EN V_PIFDBGLA_DPSLP_EN(1U)
13256 /* registers for module TP */
13257 #define TP_BASE_ADDR 0x7d00
13259 #define A_TP_IN_CONFIG 0x7d00
13261 #define S_TCPOPTPARSERDISCH3 27
13262 #define V_TCPOPTPARSERDISCH3(x) ((x) << S_TCPOPTPARSERDISCH3)
13263 #define F_TCPOPTPARSERDISCH3 V_TCPOPTPARSERDISCH3(1U)
13265 #define S_TCPOPTPARSERDISCH2 26
13266 #define V_TCPOPTPARSERDISCH2(x) ((x) << S_TCPOPTPARSERDISCH2)
13267 #define F_TCPOPTPARSERDISCH2 V_TCPOPTPARSERDISCH2(1U)
13269 #define S_TCPOPTPARSERDISCH1 25
13270 #define V_TCPOPTPARSERDISCH1(x) ((x) << S_TCPOPTPARSERDISCH1)
13271 #define F_TCPOPTPARSERDISCH1 V_TCPOPTPARSERDISCH1(1U)
13273 #define S_TCPOPTPARSERDISCH0 24
13274 #define V_TCPOPTPARSERDISCH0(x) ((x) << S_TCPOPTPARSERDISCH0)
13275 #define F_TCPOPTPARSERDISCH0 V_TCPOPTPARSERDISCH0(1U)
13277 #define S_CRCPASSPRT3 23
13278 #define V_CRCPASSPRT3(x) ((x) << S_CRCPASSPRT3)
13279 #define F_CRCPASSPRT3 V_CRCPASSPRT3(1U)
13281 #define S_CRCPASSPRT2 22
13282 #define V_CRCPASSPRT2(x) ((x) << S_CRCPASSPRT2)
13283 #define F_CRCPASSPRT2 V_CRCPASSPRT2(1U)
13285 #define S_CRCPASSPRT1 21
13286 #define V_CRCPASSPRT1(x) ((x) << S_CRCPASSPRT1)
13287 #define F_CRCPASSPRT1 V_CRCPASSPRT1(1U)
13289 #define S_CRCPASSPRT0 20
13290 #define V_CRCPASSPRT0(x) ((x) << S_CRCPASSPRT0)
13291 #define F_CRCPASSPRT0 V_CRCPASSPRT0(1U)
13293 #define S_VEPAMODE 19
13294 #define V_VEPAMODE(x) ((x) << S_VEPAMODE)
13295 #define F_VEPAMODE V_VEPAMODE(1U)
13297 #define S_FIPUPEN 18
13298 #define V_FIPUPEN(x) ((x) << S_FIPUPEN)
13299 #define F_FIPUPEN V_FIPUPEN(1U)
13301 #define S_FCOEUPEN 17
13302 #define V_FCOEUPEN(x) ((x) << S_FCOEUPEN)
13303 #define F_FCOEUPEN V_FCOEUPEN(1U)
13305 #define S_FCOEENABLE 16
13306 #define V_FCOEENABLE(x) ((x) << S_FCOEENABLE)
13307 #define F_FCOEENABLE V_FCOEENABLE(1U)
13309 #define S_IPV6ENABLE 15
13310 #define V_IPV6ENABLE(x) ((x) << S_IPV6ENABLE)
13311 #define F_IPV6ENABLE V_IPV6ENABLE(1U)
13313 #define S_NICMODE 14
13314 #define V_NICMODE(x) ((x) << S_NICMODE)
13315 #define F_NICMODE V_NICMODE(1U)
13317 #define S_ECHECKSUMCHECKTCP 13
13318 #define V_ECHECKSUMCHECKTCP(x) ((x) << S_ECHECKSUMCHECKTCP)
13319 #define F_ECHECKSUMCHECKTCP V_ECHECKSUMCHECKTCP(1U)
13321 #define S_ECHECKSUMCHECKIP 12
13322 #define V_ECHECKSUMCHECKIP(x) ((x) << S_ECHECKSUMCHECKIP)
13323 #define F_ECHECKSUMCHECKIP V_ECHECKSUMCHECKIP(1U)
13325 #define S_EREPORTUDPHDRLEN 11
13326 #define V_EREPORTUDPHDRLEN(x) ((x) << S_EREPORTUDPHDRLEN)
13327 #define F_EREPORTUDPHDRLEN V_EREPORTUDPHDRLEN(1U)
13329 #define S_IN_ECPL 10
13330 #define V_IN_ECPL(x) ((x) << S_IN_ECPL)
13331 #define F_IN_ECPL V_IN_ECPL(1U)
13333 #define S_VNTAGENABLE 9
13334 #define V_VNTAGENABLE(x) ((x) << S_VNTAGENABLE)
13335 #define F_VNTAGENABLE V_VNTAGENABLE(1U)
13337 #define S_IN_EETH 8
13338 #define V_IN_EETH(x) ((x) << S_IN_EETH)
13339 #define F_IN_EETH V_IN_EETH(1U)
13341 #define S_CCHECKSUMCHECKTCP 6
13342 #define V_CCHECKSUMCHECKTCP(x) ((x) << S_CCHECKSUMCHECKTCP)
13343 #define F_CCHECKSUMCHECKTCP V_CCHECKSUMCHECKTCP(1U)
13345 #define S_CCHECKSUMCHECKIP 5
13346 #define V_CCHECKSUMCHECKIP(x) ((x) << S_CCHECKSUMCHECKIP)
13347 #define F_CCHECKSUMCHECKIP V_CCHECKSUMCHECKIP(1U)
13350 #define V_CTAG(x) ((x) << S_CTAG)
13351 #define F_CTAG V_CTAG(1U)
13353 #define S_IN_CCPL 3
13354 #define V_IN_CCPL(x) ((x) << S_IN_CCPL)
13355 #define F_IN_CCPL V_IN_CCPL(1U)
13357 #define S_IN_CETH 1
13358 #define V_IN_CETH(x) ((x) << S_IN_CETH)
13359 #define F_IN_CETH V_IN_CETH(1U)
13361 #define S_CTUNNEL 0
13362 #define V_CTUNNEL(x) ((x) << S_CTUNNEL)
13363 #define F_CTUNNEL V_CTUNNEL(1U)
13365 #define S_VLANEXTENPORT3 31
13366 #define V_VLANEXTENPORT3(x) ((x) << S_VLANEXTENPORT3)
13367 #define F_VLANEXTENPORT3 V_VLANEXTENPORT3(1U)
13369 #define S_VLANEXTENPORT2 30
13370 #define V_VLANEXTENPORT2(x) ((x) << S_VLANEXTENPORT2)
13371 #define F_VLANEXTENPORT2 V_VLANEXTENPORT2(1U)
13373 #define S_VLANEXTENPORT1 29
13374 #define V_VLANEXTENPORT1(x) ((x) << S_VLANEXTENPORT1)
13375 #define F_VLANEXTENPORT1 V_VLANEXTENPORT1(1U)
13377 #define S_VLANEXTENPORT0 28
13378 #define V_VLANEXTENPORT0(x) ((x) << S_VLANEXTENPORT0)
13379 #define F_VLANEXTENPORT0 V_VLANEXTENPORT0(1U)
13381 #define S_VNTAGDEFAULTVAL 13
13382 #define V_VNTAGDEFAULTVAL(x) ((x) << S_VNTAGDEFAULTVAL)
13383 #define F_VNTAGDEFAULTVAL V_VNTAGDEFAULTVAL(1U)
13385 #define S_ECHECKUDPLEN 12
13386 #define V_ECHECKUDPLEN(x) ((x) << S_ECHECKUDPLEN)
13387 #define F_ECHECKUDPLEN V_ECHECKUDPLEN(1U)
13389 #define S_FCOEFPMA 10
13390 #define V_FCOEFPMA(x) ((x) << S_FCOEFPMA)
13391 #define F_FCOEFPMA V_FCOEFPMA(1U)
13393 #define S_VNTAGETHENABLE 8
13394 #define V_VNTAGETHENABLE(x) ((x) << S_VNTAGETHENABLE)
13395 #define F_VNTAGETHENABLE V_VNTAGETHENABLE(1U)
13397 #define S_IP_CCSM 7
13398 #define V_IP_CCSM(x) ((x) << S_IP_CCSM)
13399 #define F_IP_CCSM V_IP_CCSM(1U)
13401 #define S_CCHECKSUMCHECKUDP 6
13402 #define V_CCHECKSUMCHECKUDP(x) ((x) << S_CCHECKSUMCHECKUDP)
13403 #define F_CCHECKSUMCHECKUDP V_CCHECKSUMCHECKUDP(1U)
13405 #define S_TCP_CCSM 5
13406 #define V_TCP_CCSM(x) ((x) << S_TCP_CCSM)
13407 #define F_TCP_CCSM V_TCP_CCSM(1U)
13410 #define V_CDEMUX(x) ((x) << S_CDEMUX)
13411 #define F_CDEMUX V_CDEMUX(1U)
13413 #define S_ETHUPEN 2
13414 #define V_ETHUPEN(x) ((x) << S_ETHUPEN)
13415 #define F_ETHUPEN V_ETHUPEN(1U)
13417 #define A_TP_OUT_CONFIG 0x7d04
13419 #define S_PORTQFCEN 28
13420 #define M_PORTQFCEN 0xfU
13421 #define V_PORTQFCEN(x) ((x) << S_PORTQFCEN)
13422 #define G_PORTQFCEN(x) (((x) >> S_PORTQFCEN) & M_PORTQFCEN)
13424 #define S_EPKTDISTCHN3 23
13425 #define V_EPKTDISTCHN3(x) ((x) << S_EPKTDISTCHN3)
13426 #define F_EPKTDISTCHN3 V_EPKTDISTCHN3(1U)
13428 #define S_EPKTDISTCHN2 22
13429 #define V_EPKTDISTCHN2(x) ((x) << S_EPKTDISTCHN2)
13430 #define F_EPKTDISTCHN2 V_EPKTDISTCHN2(1U)
13432 #define S_EPKTDISTCHN1 21
13433 #define V_EPKTDISTCHN1(x) ((x) << S_EPKTDISTCHN1)
13434 #define F_EPKTDISTCHN1 V_EPKTDISTCHN1(1U)
13436 #define S_EPKTDISTCHN0 20
13437 #define V_EPKTDISTCHN0(x) ((x) << S_EPKTDISTCHN0)
13438 #define F_EPKTDISTCHN0 V_EPKTDISTCHN0(1U)
13440 #define S_TTLMODE 19
13441 #define V_TTLMODE(x) ((x) << S_TTLMODE)
13442 #define F_TTLMODE V_TTLMODE(1U)
13444 #define S_EQFCDMAC 18
13445 #define V_EQFCDMAC(x) ((x) << S_EQFCDMAC)
13446 #define F_EQFCDMAC V_EQFCDMAC(1U)
13448 #define S_ELPBKINCMPSSTAT 17
13449 #define V_ELPBKINCMPSSTAT(x) ((x) << S_ELPBKINCMPSSTAT)
13450 #define F_ELPBKINCMPSSTAT V_ELPBKINCMPSSTAT(1U)
13452 #define S_IPIDSPLITMODE 16
13453 #define V_IPIDSPLITMODE(x) ((x) << S_IPIDSPLITMODE)
13454 #define F_IPIDSPLITMODE V_IPIDSPLITMODE(1U)
13456 #define S_VLANEXTENABLEPORT3 15
13457 #define V_VLANEXTENABLEPORT3(x) ((x) << S_VLANEXTENABLEPORT3)
13458 #define F_VLANEXTENABLEPORT3 V_VLANEXTENABLEPORT3(1U)
13460 #define S_VLANEXTENABLEPORT2 14
13461 #define V_VLANEXTENABLEPORT2(x) ((x) << S_VLANEXTENABLEPORT2)
13462 #define F_VLANEXTENABLEPORT2 V_VLANEXTENABLEPORT2(1U)
13464 #define S_VLANEXTENABLEPORT1 13
13465 #define V_VLANEXTENABLEPORT1(x) ((x) << S_VLANEXTENABLEPORT1)
13466 #define F_VLANEXTENABLEPORT1 V_VLANEXTENABLEPORT1(1U)
13468 #define S_VLANEXTENABLEPORT0 12
13469 #define V_VLANEXTENABLEPORT0(x) ((x) << S_VLANEXTENABLEPORT0)
13470 #define F_VLANEXTENABLEPORT0 V_VLANEXTENABLEPORT0(1U)
13472 #define S_ECHECKSUMINSERTTCP 11
13473 #define V_ECHECKSUMINSERTTCP(x) ((x) << S_ECHECKSUMINSERTTCP)
13474 #define F_ECHECKSUMINSERTTCP V_ECHECKSUMINSERTTCP(1U)
13476 #define S_ECHECKSUMINSERTIP 10
13477 #define V_ECHECKSUMINSERTIP(x) ((x) << S_ECHECKSUMINSERTIP)
13478 #define F_ECHECKSUMINSERTIP V_ECHECKSUMINSERTIP(1U)
13481 #define V_ECPL(x) ((x) << S_ECPL)
13482 #define F_ECPL V_ECPL(1U)
13484 #define S_EPRIORITY 7
13485 #define V_EPRIORITY(x) ((x) << S_EPRIORITY)
13486 #define F_EPRIORITY V_EPRIORITY(1U)
13488 #define S_EETHERNET 6
13489 #define V_EETHERNET(x) ((x) << S_EETHERNET)
13490 #define F_EETHERNET V_EETHERNET(1U)
13492 #define S_CCHECKSUMINSERTTCP 5
13493 #define V_CCHECKSUMINSERTTCP(x) ((x) << S_CCHECKSUMINSERTTCP)
13494 #define F_CCHECKSUMINSERTTCP V_CCHECKSUMINSERTTCP(1U)
13496 #define S_CCHECKSUMINSERTIP 4
13497 #define V_CCHECKSUMINSERTIP(x) ((x) << S_CCHECKSUMINSERTIP)
13498 #define F_CCHECKSUMINSERTIP V_CCHECKSUMINSERTIP(1U)
13501 #define V_CCPL(x) ((x) << S_CCPL)
13502 #define F_CCPL V_CCPL(1U)
13504 #define S_CETHERNET 0
13505 #define V_CETHERNET(x) ((x) << S_CETHERNET)
13506 #define F_CETHERNET V_CETHERNET(1U)
13508 #define S_EVNTAGEN 9
13509 #define V_EVNTAGEN(x) ((x) << S_EVNTAGEN)
13510 #define F_EVNTAGEN V_EVNTAGEN(1U)
13512 #define A_TP_GLOBAL_CONFIG 0x7d08
13514 #define S_SYNCOOKIEPARAMS 26
13515 #define M_SYNCOOKIEPARAMS 0x3fU
13516 #define V_SYNCOOKIEPARAMS(x) ((x) << S_SYNCOOKIEPARAMS)
13517 #define G_SYNCOOKIEPARAMS(x) (((x) >> S_SYNCOOKIEPARAMS) & M_SYNCOOKIEPARAMS)
13519 #define S_RXFLOWCONTROLDISABLE 25
13520 #define V_RXFLOWCONTROLDISABLE(x) ((x) << S_RXFLOWCONTROLDISABLE)
13521 #define F_RXFLOWCONTROLDISABLE V_RXFLOWCONTROLDISABLE(1U)
13523 #define S_TXPACINGENABLE 24
13524 #define V_TXPACINGENABLE(x) ((x) << S_TXPACINGENABLE)
13525 #define F_TXPACINGENABLE V_TXPACINGENABLE(1U)
13527 #define S_ATTACKFILTERENABLE 23
13528 #define V_ATTACKFILTERENABLE(x) ((x) << S_ATTACKFILTERENABLE)
13529 #define F_ATTACKFILTERENABLE V_ATTACKFILTERENABLE(1U)
13531 #define S_SYNCOOKIENOOPTIONS 22
13532 #define V_SYNCOOKIENOOPTIONS(x) ((x) << S_SYNCOOKIENOOPTIONS)
13533 #define F_SYNCOOKIENOOPTIONS V_SYNCOOKIENOOPTIONS(1U)
13535 #define S_PROTECTEDMODE 21
13536 #define V_PROTECTEDMODE(x) ((x) << S_PROTECTEDMODE)
13537 #define F_PROTECTEDMODE V_PROTECTEDMODE(1U)
13539 #define S_PINGDROP 20
13540 #define V_PINGDROP(x) ((x) << S_PINGDROP)
13541 #define F_PINGDROP V_PINGDROP(1U)
13543 #define S_FRAGMENTDROP 19
13544 #define V_FRAGMENTDROP(x) ((x) << S_FRAGMENTDROP)
13545 #define F_FRAGMENTDROP V_FRAGMENTDROP(1U)
13547 #define S_FIVETUPLELOOKUP 17
13548 #define M_FIVETUPLELOOKUP 0x3U
13549 #define V_FIVETUPLELOOKUP(x) ((x) << S_FIVETUPLELOOKUP)
13550 #define G_FIVETUPLELOOKUP(x) (((x) >> S_FIVETUPLELOOKUP) & M_FIVETUPLELOOKUP)
13552 #define S_OFDMPSSTATS 16
13553 #define V_OFDMPSSTATS(x) ((x) << S_OFDMPSSTATS)
13554 #define F_OFDMPSSTATS V_OFDMPSSTATS(1U)
13556 #define S_DONTFRAGMENT 15
13557 #define V_DONTFRAGMENT(x) ((x) << S_DONTFRAGMENT)
13558 #define F_DONTFRAGMENT V_DONTFRAGMENT(1U)
13560 #define S_IPIDENTSPLIT 14
13561 #define V_IPIDENTSPLIT(x) ((x) << S_IPIDENTSPLIT)
13562 #define F_IPIDENTSPLIT V_IPIDENTSPLIT(1U)
13564 #define S_IPCHECKSUMOFFLOAD 13
13565 #define V_IPCHECKSUMOFFLOAD(x) ((x) << S_IPCHECKSUMOFFLOAD)
13566 #define F_IPCHECKSUMOFFLOAD V_IPCHECKSUMOFFLOAD(1U)
13568 #define S_UDPCHECKSUMOFFLOAD 12
13569 #define V_UDPCHECKSUMOFFLOAD(x) ((x) << S_UDPCHECKSUMOFFLOAD)
13570 #define F_UDPCHECKSUMOFFLOAD V_UDPCHECKSUMOFFLOAD(1U)
13572 #define S_TCPCHECKSUMOFFLOAD 11
13573 #define V_TCPCHECKSUMOFFLOAD(x) ((x) << S_TCPCHECKSUMOFFLOAD)
13574 #define F_TCPCHECKSUMOFFLOAD V_TCPCHECKSUMOFFLOAD(1U)
13576 #define S_RSSLOOPBACKENABLE 10
13577 #define V_RSSLOOPBACKENABLE(x) ((x) << S_RSSLOOPBACKENABLE)
13578 #define F_RSSLOOPBACKENABLE V_RSSLOOPBACKENABLE(1U)
13580 #define S_TCAMSERVERUSE 8
13581 #define M_TCAMSERVERUSE 0x3U
13582 #define V_TCAMSERVERUSE(x) ((x) << S_TCAMSERVERUSE)
13583 #define G_TCAMSERVERUSE(x) (((x) >> S_TCAMSERVERUSE) & M_TCAMSERVERUSE)
13586 #define M_IPTTL 0xffU
13587 #define V_IPTTL(x) ((x) << S_IPTTL)
13588 #define G_IPTTL(x) (((x) >> S_IPTTL) & M_IPTTL)
13590 #define S_RSSSYNSTEERENABLE 12
13591 #define V_RSSSYNSTEERENABLE(x) ((x) << S_RSSSYNSTEERENABLE)
13592 #define F_RSSSYNSTEERENABLE V_RSSSYNSTEERENABLE(1U)
13594 #define S_ISSFROMCPLENABLE 11
13595 #define V_ISSFROMCPLENABLE(x) ((x) << S_ISSFROMCPLENABLE)
13596 #define F_ISSFROMCPLENABLE V_ISSFROMCPLENABLE(1U)
13598 #define A_TP_DB_CONFIG 0x7d0c
13600 #define S_DBMAXOPCNT 24
13601 #define M_DBMAXOPCNT 0xffU
13602 #define V_DBMAXOPCNT(x) ((x) << S_DBMAXOPCNT)
13603 #define G_DBMAXOPCNT(x) (((x) >> S_DBMAXOPCNT) & M_DBMAXOPCNT)
13605 #define S_CXMAXOPCNTDISABLE 23
13606 #define V_CXMAXOPCNTDISABLE(x) ((x) << S_CXMAXOPCNTDISABLE)
13607 #define F_CXMAXOPCNTDISABLE V_CXMAXOPCNTDISABLE(1U)
13609 #define S_CXMAXOPCNT 16
13610 #define M_CXMAXOPCNT 0x7fU
13611 #define V_CXMAXOPCNT(x) ((x) << S_CXMAXOPCNT)
13612 #define G_CXMAXOPCNT(x) (((x) >> S_CXMAXOPCNT) & M_CXMAXOPCNT)
13614 #define S_TXMAXOPCNTDISABLE 15
13615 #define V_TXMAXOPCNTDISABLE(x) ((x) << S_TXMAXOPCNTDISABLE)
13616 #define F_TXMAXOPCNTDISABLE V_TXMAXOPCNTDISABLE(1U)
13618 #define S_TXMAXOPCNT 8
13619 #define M_TXMAXOPCNT 0x7fU
13620 #define V_TXMAXOPCNT(x) ((x) << S_TXMAXOPCNT)
13621 #define G_TXMAXOPCNT(x) (((x) >> S_TXMAXOPCNT) & M_TXMAXOPCNT)
13623 #define S_RXMAXOPCNTDISABLE 7
13624 #define V_RXMAXOPCNTDISABLE(x) ((x) << S_RXMAXOPCNTDISABLE)
13625 #define F_RXMAXOPCNTDISABLE V_RXMAXOPCNTDISABLE(1U)
13627 #define S_RXMAXOPCNT 0
13628 #define M_RXMAXOPCNT 0x7fU
13629 #define V_RXMAXOPCNT(x) ((x) << S_RXMAXOPCNT)
13630 #define G_RXMAXOPCNT(x) (((x) >> S_RXMAXOPCNT) & M_RXMAXOPCNT)
13632 #define A_TP_CMM_TCB_BASE 0x7d10
13633 #define A_TP_CMM_MM_BASE 0x7d14
13634 #define A_TP_CMM_TIMER_BASE 0x7d18
13635 #define A_TP_CMM_MM_FLST_SIZE 0x7d1c
13637 #define S_RXPOOLSIZE 16
13638 #define M_RXPOOLSIZE 0xffffU
13639 #define V_RXPOOLSIZE(x) ((x) << S_RXPOOLSIZE)
13640 #define G_RXPOOLSIZE(x) (((x) >> S_RXPOOLSIZE) & M_RXPOOLSIZE)
13642 #define S_TXPOOLSIZE 0
13643 #define M_TXPOOLSIZE 0xffffU
13644 #define V_TXPOOLSIZE(x) ((x) << S_TXPOOLSIZE)
13645 #define G_TXPOOLSIZE(x) (((x) >> S_TXPOOLSIZE) & M_TXPOOLSIZE)
13647 #define A_TP_PMM_TX_BASE 0x7d20
13648 #define A_TP_PMM_DEFRAG_BASE 0x7d24
13649 #define A_TP_PMM_RX_BASE 0x7d28
13650 #define A_TP_PMM_RX_PAGE_SIZE 0x7d2c
13651 #define A_TP_PMM_RX_MAX_PAGE 0x7d30
13653 #define S_PMRXNUMCHN 31
13654 #define V_PMRXNUMCHN(x) ((x) << S_PMRXNUMCHN)
13655 #define F_PMRXNUMCHN V_PMRXNUMCHN(1U)
13657 #define S_PMRXMAXPAGE 0
13658 #define M_PMRXMAXPAGE 0x1fffffU
13659 #define V_PMRXMAXPAGE(x) ((x) << S_PMRXMAXPAGE)
13660 #define G_PMRXMAXPAGE(x) (((x) >> S_PMRXMAXPAGE) & M_PMRXMAXPAGE)
13662 #define A_TP_PMM_TX_PAGE_SIZE 0x7d34
13663 #define A_TP_PMM_TX_MAX_PAGE 0x7d38
13665 #define S_PMTXNUMCHN 30
13666 #define M_PMTXNUMCHN 0x3U
13667 #define V_PMTXNUMCHN(x) ((x) << S_PMTXNUMCHN)
13668 #define G_PMTXNUMCHN(x) (((x) >> S_PMTXNUMCHN) & M_PMTXNUMCHN)
13670 #define S_PMTXMAXPAGE 0
13671 #define M_PMTXMAXPAGE 0x1fffffU
13672 #define V_PMTXMAXPAGE(x) ((x) << S_PMTXMAXPAGE)
13673 #define G_PMTXMAXPAGE(x) (((x) >> S_PMTXMAXPAGE) & M_PMTXMAXPAGE)
13675 #define A_TP_TCP_OPTIONS 0x7d40
13677 #define S_MTUDEFAULT 16
13678 #define M_MTUDEFAULT 0xffffU
13679 #define V_MTUDEFAULT(x) ((x) << S_MTUDEFAULT)
13680 #define G_MTUDEFAULT(x) (((x) >> S_MTUDEFAULT) & M_MTUDEFAULT)
13682 #define S_MTUENABLE 10
13683 #define V_MTUENABLE(x) ((x) << S_MTUENABLE)
13684 #define F_MTUENABLE V_MTUENABLE(1U)
13687 #define V_SACKTX(x) ((x) << S_SACKTX)
13688 #define F_SACKTX V_SACKTX(1U)
13691 #define V_SACKRX(x) ((x) << S_SACKRX)
13692 #define F_SACKRX V_SACKRX(1U)
13694 #define S_SACKMODE 4
13695 #define M_SACKMODE 0x3U
13696 #define V_SACKMODE(x) ((x) << S_SACKMODE)
13697 #define G_SACKMODE(x) (((x) >> S_SACKMODE) & M_SACKMODE)
13699 #define S_WINDOWSCALEMODE 2
13700 #define M_WINDOWSCALEMODE 0x3U
13701 #define V_WINDOWSCALEMODE(x) ((x) << S_WINDOWSCALEMODE)
13702 #define G_WINDOWSCALEMODE(x) (((x) >> S_WINDOWSCALEMODE) & M_WINDOWSCALEMODE)
13704 #define S_TIMESTAMPSMODE 0
13705 #define M_TIMESTAMPSMODE 0x3U
13706 #define V_TIMESTAMPSMODE(x) ((x) << S_TIMESTAMPSMODE)
13707 #define G_TIMESTAMPSMODE(x) (((x) >> S_TIMESTAMPSMODE) & M_TIMESTAMPSMODE)
13709 #define A_TP_DACK_CONFIG 0x7d44
13711 #define S_AUTOSTATE3 30
13712 #define M_AUTOSTATE3 0x3U
13713 #define V_AUTOSTATE3(x) ((x) << S_AUTOSTATE3)
13714 #define G_AUTOSTATE3(x) (((x) >> S_AUTOSTATE3) & M_AUTOSTATE3)
13716 #define S_AUTOSTATE2 28
13717 #define M_AUTOSTATE2 0x3U
13718 #define V_AUTOSTATE2(x) ((x) << S_AUTOSTATE2)
13719 #define G_AUTOSTATE2(x) (((x) >> S_AUTOSTATE2) & M_AUTOSTATE2)
13721 #define S_AUTOSTATE1 26
13722 #define M_AUTOSTATE1 0x3U
13723 #define V_AUTOSTATE1(x) ((x) << S_AUTOSTATE1)
13724 #define G_AUTOSTATE1(x) (((x) >> S_AUTOSTATE1) & M_AUTOSTATE1)
13726 #define S_BYTETHRESHOLD 8
13727 #define M_BYTETHRESHOLD 0x3ffffU
13728 #define V_BYTETHRESHOLD(x) ((x) << S_BYTETHRESHOLD)
13729 #define G_BYTETHRESHOLD(x) (((x) >> S_BYTETHRESHOLD) & M_BYTETHRESHOLD)
13731 #define S_MSSTHRESHOLD 4
13732 #define M_MSSTHRESHOLD 0x7U
13733 #define V_MSSTHRESHOLD(x) ((x) << S_MSSTHRESHOLD)
13734 #define G_MSSTHRESHOLD(x) (((x) >> S_MSSTHRESHOLD) & M_MSSTHRESHOLD)
13736 #define S_AUTOCAREFUL 2
13737 #define V_AUTOCAREFUL(x) ((x) << S_AUTOCAREFUL)
13738 #define F_AUTOCAREFUL V_AUTOCAREFUL(1U)
13740 #define S_AUTOENABLE 1
13741 #define V_AUTOENABLE(x) ((x) << S_AUTOENABLE)
13742 #define F_AUTOENABLE V_AUTOENABLE(1U)
13745 #define V_MODE(x) ((x) << S_MODE)
13746 #define F_MODE V_MODE(1U)
13748 #define A_TP_PC_CONFIG 0x7d48
13750 #define S_CMCACHEDISABLE 31
13751 #define V_CMCACHEDISABLE(x) ((x) << S_CMCACHEDISABLE)
13752 #define F_CMCACHEDISABLE V_CMCACHEDISABLE(1U)
13754 #define S_ENABLEOCSPIFULL 30
13755 #define V_ENABLEOCSPIFULL(x) ((x) << S_ENABLEOCSPIFULL)
13756 #define F_ENABLEOCSPIFULL V_ENABLEOCSPIFULL(1U)
13758 #define S_ENABLEFLMERRORDDP 29
13759 #define V_ENABLEFLMERRORDDP(x) ((x) << S_ENABLEFLMERRORDDP)
13760 #define F_ENABLEFLMERRORDDP V_ENABLEFLMERRORDDP(1U)
13762 #define S_LOCKTID 28
13763 #define V_LOCKTID(x) ((x) << S_LOCKTID)
13764 #define F_LOCKTID V_LOCKTID(1U)
13766 #define S_DISABLEINVPEND 27
13767 #define V_DISABLEINVPEND(x) ((x) << S_DISABLEINVPEND)
13768 #define F_DISABLEINVPEND V_DISABLEINVPEND(1U)
13770 #define S_ENABLEFILTERCOUNT 26
13771 #define V_ENABLEFILTERCOUNT(x) ((x) << S_ENABLEFILTERCOUNT)
13772 #define F_ENABLEFILTERCOUNT V_ENABLEFILTERCOUNT(1U)
13774 #define S_RDDPCONGEN 25
13775 #define V_RDDPCONGEN(x) ((x) << S_RDDPCONGEN)
13776 #define F_RDDPCONGEN V_RDDPCONGEN(1U)
13778 #define S_ENABLEONFLYPDU 24
13779 #define V_ENABLEONFLYPDU(x) ((x) << S_ENABLEONFLYPDU)
13780 #define F_ENABLEONFLYPDU V_ENABLEONFLYPDU(1U)
13782 #define S_ENABLEMINRCVWND 23
13783 #define V_ENABLEMINRCVWND(x) ((x) << S_ENABLEMINRCVWND)
13784 #define F_ENABLEMINRCVWND V_ENABLEMINRCVWND(1U)
13786 #define S_ENABLEMAXRCVWND 22
13787 #define V_ENABLEMAXRCVWND(x) ((x) << S_ENABLEMAXRCVWND)
13788 #define F_ENABLEMAXRCVWND V_ENABLEMAXRCVWND(1U)
13790 #define S_TXDATAACKRATEENABLE 21
13791 #define V_TXDATAACKRATEENABLE(x) ((x) << S_TXDATAACKRATEENABLE)
13792 #define F_TXDATAACKRATEENABLE V_TXDATAACKRATEENABLE(1U)
13794 #define S_TXDEFERENABLE 20
13795 #define V_TXDEFERENABLE(x) ((x) << S_TXDEFERENABLE)
13796 #define F_TXDEFERENABLE V_TXDEFERENABLE(1U)
13798 #define S_RXCONGESTIONMODE 19
13799 #define V_RXCONGESTIONMODE(x) ((x) << S_RXCONGESTIONMODE)
13800 #define F_RXCONGESTIONMODE V_RXCONGESTIONMODE(1U)
13802 #define S_HEARBEATONCEDACK 18
13803 #define V_HEARBEATONCEDACK(x) ((x) << S_HEARBEATONCEDACK)
13804 #define F_HEARBEATONCEDACK V_HEARBEATONCEDACK(1U)
13806 #define S_HEARBEATONCEHEAP 17
13807 #define V_HEARBEATONCEHEAP(x) ((x) << S_HEARBEATONCEHEAP)
13808 #define F_HEARBEATONCEHEAP V_HEARBEATONCEHEAP(1U)
13810 #define S_HEARBEATDACK 16
13811 #define V_HEARBEATDACK(x) ((x) << S_HEARBEATDACK)
13812 #define F_HEARBEATDACK V_HEARBEATDACK(1U)
13814 #define S_TXCONGESTIONMODE 15
13815 #define V_TXCONGESTIONMODE(x) ((x) << S_TXCONGESTIONMODE)
13816 #define F_TXCONGESTIONMODE V_TXCONGESTIONMODE(1U)
13818 #define S_ACCEPTLATESTRCVADV 14
13819 #define V_ACCEPTLATESTRCVADV(x) ((x) << S_ACCEPTLATESTRCVADV)
13820 #define F_ACCEPTLATESTRCVADV V_ACCEPTLATESTRCVADV(1U)
13822 #define S_DISABLESYNDATA 13
13823 #define V_DISABLESYNDATA(x) ((x) << S_DISABLESYNDATA)
13824 #define F_DISABLESYNDATA V_DISABLESYNDATA(1U)
13826 #define S_DISABLEWINDOWPSH 12
13827 #define V_DISABLEWINDOWPSH(x) ((x) << S_DISABLEWINDOWPSH)
13828 #define F_DISABLEWINDOWPSH V_DISABLEWINDOWPSH(1U)
13830 #define S_DISABLEFINOLDDATA 11
13831 #define V_DISABLEFINOLDDATA(x) ((x) << S_DISABLEFINOLDDATA)
13832 #define F_DISABLEFINOLDDATA V_DISABLEFINOLDDATA(1U)
13834 #define S_ENABLEFLMERROR 10
13835 #define V_ENABLEFLMERROR(x) ((x) << S_ENABLEFLMERROR)
13836 #define F_ENABLEFLMERROR V_ENABLEFLMERROR(1U)
13838 #define S_ENABLEOPTMTU 9
13839 #define V_ENABLEOPTMTU(x) ((x) << S_ENABLEOPTMTU)
13840 #define F_ENABLEOPTMTU V_ENABLEOPTMTU(1U)
13842 #define S_FILTERPEERFIN 8
13843 #define V_FILTERPEERFIN(x) ((x) << S_FILTERPEERFIN)
13844 #define F_FILTERPEERFIN V_FILTERPEERFIN(1U)
13846 #define S_ENABLEFEEDBACKSEND 7
13847 #define V_ENABLEFEEDBACKSEND(x) ((x) << S_ENABLEFEEDBACKSEND)
13848 #define F_ENABLEFEEDBACKSEND V_ENABLEFEEDBACKSEND(1U)
13850 #define S_ENABLERDMAERROR 6
13851 #define V_ENABLERDMAERROR(x) ((x) << S_ENABLERDMAERROR)
13852 #define F_ENABLERDMAERROR V_ENABLERDMAERROR(1U)
13854 #define S_ENABLEDDPFLOWCONTROL 5
13855 #define V_ENABLEDDPFLOWCONTROL(x) ((x) << S_ENABLEDDPFLOWCONTROL)
13856 #define F_ENABLEDDPFLOWCONTROL V_ENABLEDDPFLOWCONTROL(1U)
13858 #define S_DISABLEHELDFIN 4
13859 #define V_DISABLEHELDFIN(x) ((x) << S_DISABLEHELDFIN)
13860 #define F_DISABLEHELDFIN V_DISABLEHELDFIN(1U)
13862 #define S_ENABLEOFDOVLAN 3
13863 #define V_ENABLEOFDOVLAN(x) ((x) << S_ENABLEOFDOVLAN)
13864 #define F_ENABLEOFDOVLAN V_ENABLEOFDOVLAN(1U)
13866 #define S_DISABLETIMEWAIT 2
13867 #define V_DISABLETIMEWAIT(x) ((x) << S_DISABLETIMEWAIT)
13868 #define F_DISABLETIMEWAIT V_DISABLETIMEWAIT(1U)
13870 #define S_ENABLEVLANCHECK 1
13871 #define V_ENABLEVLANCHECK(x) ((x) << S_ENABLEVLANCHECK)
13872 #define F_ENABLEVLANCHECK V_ENABLEVLANCHECK(1U)
13874 #define S_TXDATAACKPAGEENABLE 0
13875 #define V_TXDATAACKPAGEENABLE(x) ((x) << S_TXDATAACKPAGEENABLE)
13876 #define F_TXDATAACKPAGEENABLE V_TXDATAACKPAGEENABLE(1U)
13878 #define S_ENABLEFILTERNAT 5
13879 #define V_ENABLEFILTERNAT(x) ((x) << S_ENABLEFILTERNAT)
13880 #define F_ENABLEFILTERNAT V_ENABLEFILTERNAT(1U)
13882 #define A_TP_PC_CONFIG2 0x7d4c
13884 #define S_ENABLEMTUVFMODE 31
13885 #define V_ENABLEMTUVFMODE(x) ((x) << S_ENABLEMTUVFMODE)
13886 #define F_ENABLEMTUVFMODE V_ENABLEMTUVFMODE(1U)
13888 #define S_ENABLEMIBVFMODE 30
13889 #define V_ENABLEMIBVFMODE(x) ((x) << S_ENABLEMIBVFMODE)
13890 #define F_ENABLEMIBVFMODE V_ENABLEMIBVFMODE(1U)
13892 #define S_DISABLELBKCHECK 29
13893 #define V_DISABLELBKCHECK(x) ((x) << S_DISABLELBKCHECK)
13894 #define F_DISABLELBKCHECK V_DISABLELBKCHECK(1U)
13896 #define S_ENABLEURGDDPOFF 28
13897 #define V_ENABLEURGDDPOFF(x) ((x) << S_ENABLEURGDDPOFF)
13898 #define F_ENABLEURGDDPOFF V_ENABLEURGDDPOFF(1U)
13900 #define S_ENABLEFILTERLPBK 27
13901 #define V_ENABLEFILTERLPBK(x) ((x) << S_ENABLEFILTERLPBK)
13902 #define F_ENABLEFILTERLPBK V_ENABLEFILTERLPBK(1U)
13904 #define S_DISABLETBLMMGR 26
13905 #define V_DISABLETBLMMGR(x) ((x) << S_DISABLETBLMMGR)
13906 #define F_DISABLETBLMMGR V_DISABLETBLMMGR(1U)
13908 #define S_CNGRECSNDNXT 25
13909 #define V_CNGRECSNDNXT(x) ((x) << S_CNGRECSNDNXT)
13910 #define F_CNGRECSNDNXT V_CNGRECSNDNXT(1U)
13912 #define S_ENABLELBKCHN 24
13913 #define V_ENABLELBKCHN(x) ((x) << S_ENABLELBKCHN)
13914 #define F_ENABLELBKCHN V_ENABLELBKCHN(1U)
13916 #define S_ENABLELROECN 23
13917 #define V_ENABLELROECN(x) ((x) << S_ENABLELROECN)
13918 #define F_ENABLELROECN V_ENABLELROECN(1U)
13920 #define S_ENABLEPCMDCHECK 22
13921 #define V_ENABLEPCMDCHECK(x) ((x) << S_ENABLEPCMDCHECK)
13922 #define F_ENABLEPCMDCHECK V_ENABLEPCMDCHECK(1U)
13924 #define S_ENABLEELBKAFULL 21
13925 #define V_ENABLEELBKAFULL(x) ((x) << S_ENABLEELBKAFULL)
13926 #define F_ENABLEELBKAFULL V_ENABLEELBKAFULL(1U)
13928 #define S_ENABLECLBKAFULL 20
13929 #define V_ENABLECLBKAFULL(x) ((x) << S_ENABLECLBKAFULL)
13930 #define F_ENABLECLBKAFULL V_ENABLECLBKAFULL(1U)
13932 #define S_ENABLEOESPIFULL 19
13933 #define V_ENABLEOESPIFULL(x) ((x) << S_ENABLEOESPIFULL)
13934 #define F_ENABLEOESPIFULL V_ENABLEOESPIFULL(1U)
13936 #define S_DISABLEHITCHECK 18
13937 #define V_DISABLEHITCHECK(x) ((x) << S_DISABLEHITCHECK)
13938 #define F_DISABLEHITCHECK V_DISABLEHITCHECK(1U)
13940 #define S_ENABLERSSERRCHECK 17
13941 #define V_ENABLERSSERRCHECK(x) ((x) << S_ENABLERSSERRCHECK)
13942 #define F_ENABLERSSERRCHECK V_ENABLERSSERRCHECK(1U)
13944 #define S_DISABLENEWPSHFLAG 16
13945 #define V_DISABLENEWPSHFLAG(x) ((x) << S_DISABLENEWPSHFLAG)
13946 #define F_DISABLENEWPSHFLAG V_DISABLENEWPSHFLAG(1U)
13948 #define S_ENABLERDDPRCVADVCLR 15
13949 #define V_ENABLERDDPRCVADVCLR(x) ((x) << S_ENABLERDDPRCVADVCLR)
13950 #define F_ENABLERDDPRCVADVCLR V_ENABLERDDPRCVADVCLR(1U)
13952 #define S_ENABLETXDATAARPMISS 14
13953 #define V_ENABLETXDATAARPMISS(x) ((x) << S_ENABLETXDATAARPMISS)
13954 #define F_ENABLETXDATAARPMISS V_ENABLETXDATAARPMISS(1U)
13956 #define S_ENABLEARPMISS 13
13957 #define V_ENABLEARPMISS(x) ((x) << S_ENABLEARPMISS)
13958 #define F_ENABLEARPMISS V_ENABLEARPMISS(1U)
13960 #define S_ENABLERSTPAWS 12
13961 #define V_ENABLERSTPAWS(x) ((x) << S_ENABLERSTPAWS)
13962 #define F_ENABLERSTPAWS V_ENABLERSTPAWS(1U)
13964 #define S_ENABLEIPV6RSS 11
13965 #define V_ENABLEIPV6RSS(x) ((x) << S_ENABLEIPV6RSS)
13966 #define F_ENABLEIPV6RSS V_ENABLEIPV6RSS(1U)
13968 #define S_ENABLENONOFDHYBRSS 10
13969 #define V_ENABLENONOFDHYBRSS(x) ((x) << S_ENABLENONOFDHYBRSS)
13970 #define F_ENABLENONOFDHYBRSS V_ENABLENONOFDHYBRSS(1U)
13972 #define S_ENABLEUDP4TUPRSS 9
13973 #define V_ENABLEUDP4TUPRSS(x) ((x) << S_ENABLEUDP4TUPRSS)
13974 #define F_ENABLEUDP4TUPRSS V_ENABLEUDP4TUPRSS(1U)
13976 #define S_ENABLERXPKTTMSTPRSS 8
13977 #define V_ENABLERXPKTTMSTPRSS(x) ((x) << S_ENABLERXPKTTMSTPRSS)
13978 #define F_ENABLERXPKTTMSTPRSS V_ENABLERXPKTTMSTPRSS(1U)
13980 #define S_ENABLEEPCMDAFULL 7
13981 #define V_ENABLEEPCMDAFULL(x) ((x) << S_ENABLEEPCMDAFULL)
13982 #define F_ENABLEEPCMDAFULL V_ENABLEEPCMDAFULL(1U)
13984 #define S_ENABLECPCMDAFULL 6
13985 #define V_ENABLECPCMDAFULL(x) ((x) << S_ENABLECPCMDAFULL)
13986 #define F_ENABLECPCMDAFULL V_ENABLECPCMDAFULL(1U)
13988 #define S_ENABLEEHDRAFULL 5
13989 #define V_ENABLEEHDRAFULL(x) ((x) << S_ENABLEEHDRAFULL)
13990 #define F_ENABLEEHDRAFULL V_ENABLEEHDRAFULL(1U)
13992 #define S_ENABLECHDRAFULL 4
13993 #define V_ENABLECHDRAFULL(x) ((x) << S_ENABLECHDRAFULL)
13994 #define F_ENABLECHDRAFULL V_ENABLECHDRAFULL(1U)
13996 #define S_ENABLEEMACAFULL 3
13997 #define V_ENABLEEMACAFULL(x) ((x) << S_ENABLEEMACAFULL)
13998 #define F_ENABLEEMACAFULL V_ENABLEEMACAFULL(1U)
14000 #define S_ENABLENONOFDTIDRSS 2
14001 #define V_ENABLENONOFDTIDRSS(x) ((x) << S_ENABLENONOFDTIDRSS)
14002 #define F_ENABLENONOFDTIDRSS V_ENABLENONOFDTIDRSS(1U)
14004 #define S_ENABLENONOFDTCBRSS 1
14005 #define V_ENABLENONOFDTCBRSS(x) ((x) << S_ENABLENONOFDTCBRSS)
14006 #define F_ENABLENONOFDTCBRSS V_ENABLENONOFDTCBRSS(1U)
14008 #define S_ENABLETNLOFDCLOSED 0
14009 #define V_ENABLETNLOFDCLOSED(x) ((x) << S_ENABLETNLOFDCLOSED)
14010 #define F_ENABLETNLOFDCLOSED V_ENABLETNLOFDCLOSED(1U)
14012 #define S_ENABLEFINDDPOFF 14
14013 #define V_ENABLEFINDDPOFF(x) ((x) << S_ENABLEFINDDPOFF)
14014 #define F_ENABLEFINDDPOFF V_ENABLEFINDDPOFF(1U)
14016 #define A_TP_TCP_BACKOFF_REG0 0x7d50
14018 #define S_TIMERBACKOFFINDEX3 24
14019 #define M_TIMERBACKOFFINDEX3 0xffU
14020 #define V_TIMERBACKOFFINDEX3(x) ((x) << S_TIMERBACKOFFINDEX3)
14021 #define G_TIMERBACKOFFINDEX3(x) (((x) >> S_TIMERBACKOFFINDEX3) & M_TIMERBACKOFFINDEX3)
14023 #define S_TIMERBACKOFFINDEX2 16
14024 #define M_TIMERBACKOFFINDEX2 0xffU
14025 #define V_TIMERBACKOFFINDEX2(x) ((x) << S_TIMERBACKOFFINDEX2)
14026 #define G_TIMERBACKOFFINDEX2(x) (((x) >> S_TIMERBACKOFFINDEX2) & M_TIMERBACKOFFINDEX2)
14028 #define S_TIMERBACKOFFINDEX1 8
14029 #define M_TIMERBACKOFFINDEX1 0xffU
14030 #define V_TIMERBACKOFFINDEX1(x) ((x) << S_TIMERBACKOFFINDEX1)
14031 #define G_TIMERBACKOFFINDEX1(x) (((x) >> S_TIMERBACKOFFINDEX1) & M_TIMERBACKOFFINDEX1)
14033 #define S_TIMERBACKOFFINDEX0 0
14034 #define M_TIMERBACKOFFINDEX0 0xffU
14035 #define V_TIMERBACKOFFINDEX0(x) ((x) << S_TIMERBACKOFFINDEX0)
14036 #define G_TIMERBACKOFFINDEX0(x) (((x) >> S_TIMERBACKOFFINDEX0) & M_TIMERBACKOFFINDEX0)
14038 #define A_TP_TCP_BACKOFF_REG1 0x7d54
14040 #define S_TIMERBACKOFFINDEX7 24
14041 #define M_TIMERBACKOFFINDEX7 0xffU
14042 #define V_TIMERBACKOFFINDEX7(x) ((x) << S_TIMERBACKOFFINDEX7)
14043 #define G_TIMERBACKOFFINDEX7(x) (((x) >> S_TIMERBACKOFFINDEX7) & M_TIMERBACKOFFINDEX7)
14045 #define S_TIMERBACKOFFINDEX6 16
14046 #define M_TIMERBACKOFFINDEX6 0xffU
14047 #define V_TIMERBACKOFFINDEX6(x) ((x) << S_TIMERBACKOFFINDEX6)
14048 #define G_TIMERBACKOFFINDEX6(x) (((x) >> S_TIMERBACKOFFINDEX6) & M_TIMERBACKOFFINDEX6)
14050 #define S_TIMERBACKOFFINDEX5 8
14051 #define M_TIMERBACKOFFINDEX5 0xffU
14052 #define V_TIMERBACKOFFINDEX5(x) ((x) << S_TIMERBACKOFFINDEX5)
14053 #define G_TIMERBACKOFFINDEX5(x) (((x) >> S_TIMERBACKOFFINDEX5) & M_TIMERBACKOFFINDEX5)
14055 #define S_TIMERBACKOFFINDEX4 0
14056 #define M_TIMERBACKOFFINDEX4 0xffU
14057 #define V_TIMERBACKOFFINDEX4(x) ((x) << S_TIMERBACKOFFINDEX4)
14058 #define G_TIMERBACKOFFINDEX4(x) (((x) >> S_TIMERBACKOFFINDEX4) & M_TIMERBACKOFFINDEX4)
14060 #define A_TP_TCP_BACKOFF_REG2 0x7d58
14062 #define S_TIMERBACKOFFINDEX11 24
14063 #define M_TIMERBACKOFFINDEX11 0xffU
14064 #define V_TIMERBACKOFFINDEX11(x) ((x) << S_TIMERBACKOFFINDEX11)
14065 #define G_TIMERBACKOFFINDEX11(x) (((x) >> S_TIMERBACKOFFINDEX11) & M_TIMERBACKOFFINDEX11)
14067 #define S_TIMERBACKOFFINDEX10 16
14068 #define M_TIMERBACKOFFINDEX10 0xffU
14069 #define V_TIMERBACKOFFINDEX10(x) ((x) << S_TIMERBACKOFFINDEX10)
14070 #define G_TIMERBACKOFFINDEX10(x) (((x) >> S_TIMERBACKOFFINDEX10) & M_TIMERBACKOFFINDEX10)
14072 #define S_TIMERBACKOFFINDEX9 8
14073 #define M_TIMERBACKOFFINDEX9 0xffU
14074 #define V_TIMERBACKOFFINDEX9(x) ((x) << S_TIMERBACKOFFINDEX9)
14075 #define G_TIMERBACKOFFINDEX9(x) (((x) >> S_TIMERBACKOFFINDEX9) & M_TIMERBACKOFFINDEX9)
14077 #define S_TIMERBACKOFFINDEX8 0
14078 #define M_TIMERBACKOFFINDEX8 0xffU
14079 #define V_TIMERBACKOFFINDEX8(x) ((x) << S_TIMERBACKOFFINDEX8)
14080 #define G_TIMERBACKOFFINDEX8(x) (((x) >> S_TIMERBACKOFFINDEX8) & M_TIMERBACKOFFINDEX8)
14082 #define A_TP_TCP_BACKOFF_REG3 0x7d5c
14084 #define S_TIMERBACKOFFINDEX15 24
14085 #define M_TIMERBACKOFFINDEX15 0xffU
14086 #define V_TIMERBACKOFFINDEX15(x) ((x) << S_TIMERBACKOFFINDEX15)
14087 #define G_TIMERBACKOFFINDEX15(x) (((x) >> S_TIMERBACKOFFINDEX15) & M_TIMERBACKOFFINDEX15)
14089 #define S_TIMERBACKOFFINDEX14 16
14090 #define M_TIMERBACKOFFINDEX14 0xffU
14091 #define V_TIMERBACKOFFINDEX14(x) ((x) << S_TIMERBACKOFFINDEX14)
14092 #define G_TIMERBACKOFFINDEX14(x) (((x) >> S_TIMERBACKOFFINDEX14) & M_TIMERBACKOFFINDEX14)
14094 #define S_TIMERBACKOFFINDEX13 8
14095 #define M_TIMERBACKOFFINDEX13 0xffU
14096 #define V_TIMERBACKOFFINDEX13(x) ((x) << S_TIMERBACKOFFINDEX13)
14097 #define G_TIMERBACKOFFINDEX13(x) (((x) >> S_TIMERBACKOFFINDEX13) & M_TIMERBACKOFFINDEX13)
14099 #define S_TIMERBACKOFFINDEX12 0
14100 #define M_TIMERBACKOFFINDEX12 0xffU
14101 #define V_TIMERBACKOFFINDEX12(x) ((x) << S_TIMERBACKOFFINDEX12)
14102 #define G_TIMERBACKOFFINDEX12(x) (((x) >> S_TIMERBACKOFFINDEX12) & M_TIMERBACKOFFINDEX12)
14104 #define A_TP_PARA_REG0 0x7d60
14106 #define S_INITCWNDIDLE 27
14107 #define V_INITCWNDIDLE(x) ((x) << S_INITCWNDIDLE)
14108 #define F_INITCWNDIDLE V_INITCWNDIDLE(1U)
14110 #define S_INITCWND 24
14111 #define M_INITCWND 0x7U
14112 #define V_INITCWND(x) ((x) << S_INITCWND)
14113 #define G_INITCWND(x) (((x) >> S_INITCWND) & M_INITCWND)
14115 #define S_DUPACKTHRESH 20
14116 #define M_DUPACKTHRESH 0xfU
14117 #define V_DUPACKTHRESH(x) ((x) << S_DUPACKTHRESH)
14118 #define G_DUPACKTHRESH(x) (((x) >> S_DUPACKTHRESH) & M_DUPACKTHRESH)
14120 #define S_CPLERRENABLE 12
14121 #define V_CPLERRENABLE(x) ((x) << S_CPLERRENABLE)
14122 #define F_CPLERRENABLE V_CPLERRENABLE(1U)
14124 #define S_FASTTNLCNT 11
14125 #define V_FASTTNLCNT(x) ((x) << S_FASTTNLCNT)
14126 #define F_FASTTNLCNT V_FASTTNLCNT(1U)
14128 #define S_FASTTBLCNT 10
14129 #define V_FASTTBLCNT(x) ((x) << S_FASTTBLCNT)
14130 #define F_FASTTBLCNT V_FASTTBLCNT(1U)
14132 #define S_TPTCAMKEY 9
14133 #define V_TPTCAMKEY(x) ((x) << S_TPTCAMKEY)
14134 #define F_TPTCAMKEY V_TPTCAMKEY(1U)
14136 #define S_SWSMODE 8
14137 #define V_SWSMODE(x) ((x) << S_SWSMODE)
14138 #define F_SWSMODE V_SWSMODE(1U)
14140 #define S_TSMPMODE 6
14141 #define M_TSMPMODE 0x3U
14142 #define V_TSMPMODE(x) ((x) << S_TSMPMODE)
14143 #define G_TSMPMODE(x) (((x) >> S_TSMPMODE) & M_TSMPMODE)
14145 #define S_BYTECOUNTLIMIT 4
14146 #define M_BYTECOUNTLIMIT 0x3U
14147 #define V_BYTECOUNTLIMIT(x) ((x) << S_BYTECOUNTLIMIT)
14148 #define G_BYTECOUNTLIMIT(x) (((x) >> S_BYTECOUNTLIMIT) & M_BYTECOUNTLIMIT)
14150 #define S_SWSSHOVE 3
14151 #define V_SWSSHOVE(x) ((x) << S_SWSSHOVE)
14152 #define F_SWSSHOVE V_SWSSHOVE(1U)
14154 #define S_TBLTIMER 2
14155 #define V_TBLTIMER(x) ((x) << S_TBLTIMER)
14156 #define F_TBLTIMER V_TBLTIMER(1U)
14158 #define S_RXTPACE 1
14159 #define V_RXTPACE(x) ((x) << S_RXTPACE)
14160 #define F_RXTPACE V_RXTPACE(1U)
14162 #define S_SWSTIMER 0
14163 #define V_SWSTIMER(x) ((x) << S_SWSTIMER)
14164 #define F_SWSTIMER V_SWSTIMER(1U)
14166 #define S_LIMTXTHRESH 28
14167 #define M_LIMTXTHRESH 0xfU
14168 #define V_LIMTXTHRESH(x) ((x) << S_LIMTXTHRESH)
14169 #define G_LIMTXTHRESH(x) (((x) >> S_LIMTXTHRESH) & M_LIMTXTHRESH)
14171 #define S_CHNERRENABLE 14
14172 #define V_CHNERRENABLE(x) ((x) << S_CHNERRENABLE)
14173 #define F_CHNERRENABLE V_CHNERRENABLE(1U)
14175 #define S_SETTIMEENABLE 13
14176 #define V_SETTIMEENABLE(x) ((x) << S_SETTIMEENABLE)
14177 #define F_SETTIMEENABLE V_SETTIMEENABLE(1U)
14179 #define A_TP_PARA_REG1 0x7d64
14181 #define S_INITRWND 16
14182 #define M_INITRWND 0xffffU
14183 #define V_INITRWND(x) ((x) << S_INITRWND)
14184 #define G_INITRWND(x) (((x) >> S_INITRWND) & M_INITRWND)
14186 #define S_INITIALSSTHRESH 0
14187 #define M_INITIALSSTHRESH 0xffffU
14188 #define V_INITIALSSTHRESH(x) ((x) << S_INITIALSSTHRESH)
14189 #define G_INITIALSSTHRESH(x) (((x) >> S_INITIALSSTHRESH) & M_INITIALSSTHRESH)
14191 #define A_TP_PARA_REG2 0x7d68
14193 #define S_MAXRXDATA 16
14194 #define M_MAXRXDATA 0xffffU
14195 #define V_MAXRXDATA(x) ((x) << S_MAXRXDATA)
14196 #define G_MAXRXDATA(x) (((x) >> S_MAXRXDATA) & M_MAXRXDATA)
14198 #define S_RXCOALESCESIZE 0
14199 #define M_RXCOALESCESIZE 0xffffU
14200 #define V_RXCOALESCESIZE(x) ((x) << S_RXCOALESCESIZE)
14201 #define G_RXCOALESCESIZE(x) (((x) >> S_RXCOALESCESIZE) & M_RXCOALESCESIZE)
14203 #define A_TP_PARA_REG3 0x7d6c
14205 #define S_ENABLETNLCNGLPBK 31
14206 #define V_ENABLETNLCNGLPBK(x) ((x) << S_ENABLETNLCNGLPBK)
14207 #define F_ENABLETNLCNGLPBK V_ENABLETNLCNGLPBK(1U)
14209 #define S_ENABLETNLCNGFIFO 30
14210 #define V_ENABLETNLCNGFIFO(x) ((x) << S_ENABLETNLCNGFIFO)
14211 #define F_ENABLETNLCNGFIFO V_ENABLETNLCNGFIFO(1U)
14213 #define S_ENABLETNLCNGHDR 29
14214 #define V_ENABLETNLCNGHDR(x) ((x) << S_ENABLETNLCNGHDR)
14215 #define F_ENABLETNLCNGHDR V_ENABLETNLCNGHDR(1U)
14217 #define S_ENABLETNLCNGSGE 28
14218 #define V_ENABLETNLCNGSGE(x) ((x) << S_ENABLETNLCNGSGE)
14219 #define F_ENABLETNLCNGSGE V_ENABLETNLCNGSGE(1U)
14221 #define S_RXMACCHECK 27
14222 #define V_RXMACCHECK(x) ((x) << S_RXMACCHECK)
14223 #define F_RXMACCHECK V_RXMACCHECK(1U)
14225 #define S_RXSYNFILTER 26
14226 #define V_RXSYNFILTER(x) ((x) << S_RXSYNFILTER)
14227 #define F_RXSYNFILTER V_RXSYNFILTER(1U)
14229 #define S_CNGCTRLECN 25
14230 #define V_CNGCTRLECN(x) ((x) << S_CNGCTRLECN)
14231 #define F_CNGCTRLECN V_CNGCTRLECN(1U)
14233 #define S_RXDDPOFFINIT 24
14234 #define V_RXDDPOFFINIT(x) ((x) << S_RXDDPOFFINIT)
14235 #define F_RXDDPOFFINIT V_RXDDPOFFINIT(1U)
14237 #define S_TUNNELCNGDROP3 23
14238 #define V_TUNNELCNGDROP3(x) ((x) << S_TUNNELCNGDROP3)
14239 #define F_TUNNELCNGDROP3 V_TUNNELCNGDROP3(1U)
14241 #define S_TUNNELCNGDROP2 22
14242 #define V_TUNNELCNGDROP2(x) ((x) << S_TUNNELCNGDROP2)
14243 #define F_TUNNELCNGDROP2 V_TUNNELCNGDROP2(1U)
14245 #define S_TUNNELCNGDROP1 21
14246 #define V_TUNNELCNGDROP1(x) ((x) << S_TUNNELCNGDROP1)
14247 #define F_TUNNELCNGDROP1 V_TUNNELCNGDROP1(1U)
14249 #define S_TUNNELCNGDROP0 20
14250 #define V_TUNNELCNGDROP0(x) ((x) << S_TUNNELCNGDROP0)
14251 #define F_TUNNELCNGDROP0 V_TUNNELCNGDROP0(1U)
14253 #define S_TXDATAACKIDX 16
14254 #define M_TXDATAACKIDX 0xfU
14255 #define V_TXDATAACKIDX(x) ((x) << S_TXDATAACKIDX)
14256 #define G_TXDATAACKIDX(x) (((x) >> S_TXDATAACKIDX) & M_TXDATAACKIDX)
14258 #define S_RXFRAGENABLE 12
14259 #define M_RXFRAGENABLE 0x7U
14260 #define V_RXFRAGENABLE(x) ((x) << S_RXFRAGENABLE)
14261 #define G_RXFRAGENABLE(x) (((x) >> S_RXFRAGENABLE) & M_RXFRAGENABLE)
14263 #define S_TXPACEFIXEDSTRICT 11
14264 #define V_TXPACEFIXEDSTRICT(x) ((x) << S_TXPACEFIXEDSTRICT)
14265 #define F_TXPACEFIXEDSTRICT V_TXPACEFIXEDSTRICT(1U)
14267 #define S_TXPACEAUTOSTRICT 10
14268 #define V_TXPACEAUTOSTRICT(x) ((x) << S_TXPACEAUTOSTRICT)
14269 #define F_TXPACEAUTOSTRICT V_TXPACEAUTOSTRICT(1U)
14271 #define S_TXPACEFIXED 9
14272 #define V_TXPACEFIXED(x) ((x) << S_TXPACEFIXED)
14273 #define F_TXPACEFIXED V_TXPACEFIXED(1U)
14275 #define S_TXPACEAUTO 8
14276 #define V_TXPACEAUTO(x) ((x) << S_TXPACEAUTO)
14277 #define F_TXPACEAUTO V_TXPACEAUTO(1U)
14279 #define S_RXCHNTUNNEL 7
14280 #define V_RXCHNTUNNEL(x) ((x) << S_RXCHNTUNNEL)
14281 #define F_RXCHNTUNNEL V_RXCHNTUNNEL(1U)
14283 #define S_RXURGTUNNEL 6
14284 #define V_RXURGTUNNEL(x) ((x) << S_RXURGTUNNEL)
14285 #define F_RXURGTUNNEL V_RXURGTUNNEL(1U)
14287 #define S_RXURGMODE 5
14288 #define V_RXURGMODE(x) ((x) << S_RXURGMODE)
14289 #define F_RXURGMODE V_RXURGMODE(1U)
14291 #define S_TXURGMODE 4
14292 #define V_TXURGMODE(x) ((x) << S_TXURGMODE)
14293 #define F_TXURGMODE V_TXURGMODE(1U)
14295 #define S_CNGCTRLMODE 2
14296 #define M_CNGCTRLMODE 0x3U
14297 #define V_CNGCTRLMODE(x) ((x) << S_CNGCTRLMODE)
14298 #define G_CNGCTRLMODE(x) (((x) >> S_CNGCTRLMODE) & M_CNGCTRLMODE)
14300 #define S_RXCOALESCEENABLE 1
14301 #define V_RXCOALESCEENABLE(x) ((x) << S_RXCOALESCEENABLE)
14302 #define F_RXCOALESCEENABLE V_RXCOALESCEENABLE(1U)
14304 #define S_RXCOALESCEPSHEN 0
14305 #define V_RXCOALESCEPSHEN(x) ((x) << S_RXCOALESCEPSHEN)
14306 #define F_RXCOALESCEPSHEN V_RXCOALESCEPSHEN(1U)
14308 #define A_TP_PARA_REG4 0x7d70
14310 #define S_HIGHSPEEDCFG 24
14311 #define M_HIGHSPEEDCFG 0xffU
14312 #define V_HIGHSPEEDCFG(x) ((x) << S_HIGHSPEEDCFG)
14313 #define G_HIGHSPEEDCFG(x) (((x) >> S_HIGHSPEEDCFG) & M_HIGHSPEEDCFG)
14315 #define S_NEWRENOCFG 16
14316 #define M_NEWRENOCFG 0xffU
14317 #define V_NEWRENOCFG(x) ((x) << S_NEWRENOCFG)
14318 #define G_NEWRENOCFG(x) (((x) >> S_NEWRENOCFG) & M_NEWRENOCFG)
14320 #define S_TAHOECFG 8
14321 #define M_TAHOECFG 0xffU
14322 #define V_TAHOECFG(x) ((x) << S_TAHOECFG)
14323 #define G_TAHOECFG(x) (((x) >> S_TAHOECFG) & M_TAHOECFG)
14325 #define S_RENOCFG 0
14326 #define M_RENOCFG 0xffU
14327 #define V_RENOCFG(x) ((x) << S_RENOCFG)
14328 #define G_RENOCFG(x) (((x) >> S_RENOCFG) & M_RENOCFG)
14330 #define S_IDLECWNDHIGHSPEED 28
14331 #define V_IDLECWNDHIGHSPEED(x) ((x) << S_IDLECWNDHIGHSPEED)
14332 #define F_IDLECWNDHIGHSPEED V_IDLECWNDHIGHSPEED(1U)
14334 #define S_RXMTCWNDHIGHSPEED 27
14335 #define V_RXMTCWNDHIGHSPEED(x) ((x) << S_RXMTCWNDHIGHSPEED)
14336 #define F_RXMTCWNDHIGHSPEED V_RXMTCWNDHIGHSPEED(1U)
14338 #define S_OVERDRIVEHIGHSPEED 25
14339 #define M_OVERDRIVEHIGHSPEED 0x3U
14340 #define V_OVERDRIVEHIGHSPEED(x) ((x) << S_OVERDRIVEHIGHSPEED)
14341 #define G_OVERDRIVEHIGHSPEED(x) (((x) >> S_OVERDRIVEHIGHSPEED) & M_OVERDRIVEHIGHSPEED)
14343 #define S_BYTECOUNTHIGHSPEED 24
14344 #define V_BYTECOUNTHIGHSPEED(x) ((x) << S_BYTECOUNTHIGHSPEED)
14345 #define F_BYTECOUNTHIGHSPEED V_BYTECOUNTHIGHSPEED(1U)
14347 #define S_IDLECWNDNEWRENO 20
14348 #define V_IDLECWNDNEWRENO(x) ((x) << S_IDLECWNDNEWRENO)
14349 #define F_IDLECWNDNEWRENO V_IDLECWNDNEWRENO(1U)
14351 #define S_RXMTCWNDNEWRENO 19
14352 #define V_RXMTCWNDNEWRENO(x) ((x) << S_RXMTCWNDNEWRENO)
14353 #define F_RXMTCWNDNEWRENO V_RXMTCWNDNEWRENO(1U)
14355 #define S_OVERDRIVENEWRENO 17
14356 #define M_OVERDRIVENEWRENO 0x3U
14357 #define V_OVERDRIVENEWRENO(x) ((x) << S_OVERDRIVENEWRENO)
14358 #define G_OVERDRIVENEWRENO(x) (((x) >> S_OVERDRIVENEWRENO) & M_OVERDRIVENEWRENO)
14360 #define S_BYTECOUNTNEWRENO 16
14361 #define V_BYTECOUNTNEWRENO(x) ((x) << S_BYTECOUNTNEWRENO)
14362 #define F_BYTECOUNTNEWRENO V_BYTECOUNTNEWRENO(1U)
14364 #define S_IDLECWNDTAHOE 12
14365 #define V_IDLECWNDTAHOE(x) ((x) << S_IDLECWNDTAHOE)
14366 #define F_IDLECWNDTAHOE V_IDLECWNDTAHOE(1U)
14368 #define S_RXMTCWNDTAHOE 11
14369 #define V_RXMTCWNDTAHOE(x) ((x) << S_RXMTCWNDTAHOE)
14370 #define F_RXMTCWNDTAHOE V_RXMTCWNDTAHOE(1U)
14372 #define S_OVERDRIVETAHOE 9
14373 #define M_OVERDRIVETAHOE 0x3U
14374 #define V_OVERDRIVETAHOE(x) ((x) << S_OVERDRIVETAHOE)
14375 #define G_OVERDRIVETAHOE(x) (((x) >> S_OVERDRIVETAHOE) & M_OVERDRIVETAHOE)
14377 #define S_BYTECOUNTTAHOE 8
14378 #define V_BYTECOUNTTAHOE(x) ((x) << S_BYTECOUNTTAHOE)
14379 #define F_BYTECOUNTTAHOE V_BYTECOUNTTAHOE(1U)
14381 #define S_IDLECWNDRENO 4
14382 #define V_IDLECWNDRENO(x) ((x) << S_IDLECWNDRENO)
14383 #define F_IDLECWNDRENO V_IDLECWNDRENO(1U)
14385 #define S_RXMTCWNDRENO 3
14386 #define V_RXMTCWNDRENO(x) ((x) << S_RXMTCWNDRENO)
14387 #define F_RXMTCWNDRENO V_RXMTCWNDRENO(1U)
14389 #define S_OVERDRIVERENO 1
14390 #define M_OVERDRIVERENO 0x3U
14391 #define V_OVERDRIVERENO(x) ((x) << S_OVERDRIVERENO)
14392 #define G_OVERDRIVERENO(x) (((x) >> S_OVERDRIVERENO) & M_OVERDRIVERENO)
14394 #define S_BYTECOUNTRENO 0
14395 #define V_BYTECOUNTRENO(x) ((x) << S_BYTECOUNTRENO)
14396 #define F_BYTECOUNTRENO V_BYTECOUNTRENO(1U)
14398 #define A_TP_PARA_REG5 0x7d74
14400 #define S_INDICATESIZE 16
14401 #define M_INDICATESIZE 0xffffU
14402 #define V_INDICATESIZE(x) ((x) << S_INDICATESIZE)
14403 #define G_INDICATESIZE(x) (((x) >> S_INDICATESIZE) & M_INDICATESIZE)
14405 #define S_MAXPROXYSIZE 12
14406 #define M_MAXPROXYSIZE 0xfU
14407 #define V_MAXPROXYSIZE(x) ((x) << S_MAXPROXYSIZE)
14408 #define G_MAXPROXYSIZE(x) (((x) >> S_MAXPROXYSIZE) & M_MAXPROXYSIZE)
14410 #define S_ENABLEREADPDU 11
14411 #define V_ENABLEREADPDU(x) ((x) << S_ENABLEREADPDU)
14412 #define F_ENABLEREADPDU V_ENABLEREADPDU(1U)
14414 #define S_RXREADAHEAD 10
14415 #define V_RXREADAHEAD(x) ((x) << S_RXREADAHEAD)
14416 #define F_RXREADAHEAD V_RXREADAHEAD(1U)
14418 #define S_EMPTYRQENABLE 9
14419 #define V_EMPTYRQENABLE(x) ((x) << S_EMPTYRQENABLE)
14420 #define F_EMPTYRQENABLE V_EMPTYRQENABLE(1U)
14422 #define S_SCHDENABLE 8
14423 #define V_SCHDENABLE(x) ((x) << S_SCHDENABLE)
14424 #define F_SCHDENABLE V_SCHDENABLE(1U)
14426 #define S_REARMDDPOFFSET 4
14427 #define V_REARMDDPOFFSET(x) ((x) << S_REARMDDPOFFSET)
14428 #define F_REARMDDPOFFSET V_REARMDDPOFFSET(1U)
14430 #define S_RESETDDPOFFSET 3
14431 #define V_RESETDDPOFFSET(x) ((x) << S_RESETDDPOFFSET)
14432 #define F_RESETDDPOFFSET V_RESETDDPOFFSET(1U)
14434 #define S_ONFLYDDPENABLE 2
14435 #define V_ONFLYDDPENABLE(x) ((x) << S_ONFLYDDPENABLE)
14436 #define F_ONFLYDDPENABLE V_ONFLYDDPENABLE(1U)
14438 #define S_DACKTIMERSPIN 1
14439 #define V_DACKTIMERSPIN(x) ((x) << S_DACKTIMERSPIN)
14440 #define F_DACKTIMERSPIN V_DACKTIMERSPIN(1U)
14442 #define S_PUSHTIMERENABLE 0
14443 #define V_PUSHTIMERENABLE(x) ((x) << S_PUSHTIMERENABLE)
14444 #define F_PUSHTIMERENABLE V_PUSHTIMERENABLE(1U)
14446 #define S_ENABLEXOFFPDU 7
14447 #define V_ENABLEXOFFPDU(x) ((x) << S_ENABLEXOFFPDU)
14448 #define F_ENABLEXOFFPDU V_ENABLEXOFFPDU(1U)
14450 #define S_ENABLENEWFAR 6
14451 #define V_ENABLENEWFAR(x) ((x) << S_ENABLENEWFAR)
14452 #define F_ENABLENEWFAR V_ENABLENEWFAR(1U)
14454 #define S_ENABLEFRAGCHECK 5
14455 #define V_ENABLEFRAGCHECK(x) ((x) << S_ENABLEFRAGCHECK)
14456 #define F_ENABLEFRAGCHECK V_ENABLEFRAGCHECK(1U)
14458 #define A_TP_PARA_REG6 0x7d78
14460 #define S_TXPDUSIZEADJ 24
14461 #define M_TXPDUSIZEADJ 0xffU
14462 #define V_TXPDUSIZEADJ(x) ((x) << S_TXPDUSIZEADJ)
14463 #define G_TXPDUSIZEADJ(x) (((x) >> S_TXPDUSIZEADJ) & M_TXPDUSIZEADJ)
14465 #define S_LIMITEDTRANSMIT 20
14466 #define M_LIMITEDTRANSMIT 0xfU
14467 #define V_LIMITEDTRANSMIT(x) ((x) << S_LIMITEDTRANSMIT)
14468 #define G_LIMITEDTRANSMIT(x) (((x) >> S_LIMITEDTRANSMIT) & M_LIMITEDTRANSMIT)
14470 #define S_ENABLECSAV 19
14471 #define V_ENABLECSAV(x) ((x) << S_ENABLECSAV)
14472 #define F_ENABLECSAV V_ENABLECSAV(1U)
14474 #define S_ENABLEDEFERPDU 18
14475 #define V_ENABLEDEFERPDU(x) ((x) << S_ENABLEDEFERPDU)
14476 #define F_ENABLEDEFERPDU V_ENABLEDEFERPDU(1U)
14478 #define S_ENABLEFLUSH 17
14479 #define V_ENABLEFLUSH(x) ((x) << S_ENABLEFLUSH)
14480 #define F_ENABLEFLUSH V_ENABLEFLUSH(1U)
14482 #define S_ENABLEBYTEPERSIST 16
14483 #define V_ENABLEBYTEPERSIST(x) ((x) << S_ENABLEBYTEPERSIST)
14484 #define F_ENABLEBYTEPERSIST V_ENABLEBYTEPERSIST(1U)
14486 #define S_DISABLETMOCNG 15
14487 #define V_DISABLETMOCNG(x) ((x) << S_DISABLETMOCNG)
14488 #define F_DISABLETMOCNG V_DISABLETMOCNG(1U)
14490 #define S_TXREADAHEAD 14
14491 #define V_TXREADAHEAD(x) ((x) << S_TXREADAHEAD)
14492 #define F_TXREADAHEAD V_TXREADAHEAD(1U)
14494 #define S_ALLOWEXEPTION 13
14495 #define V_ALLOWEXEPTION(x) ((x) << S_ALLOWEXEPTION)
14496 #define F_ALLOWEXEPTION V_ALLOWEXEPTION(1U)
14498 #define S_ENABLEDEFERACK 12
14499 #define V_ENABLEDEFERACK(x) ((x) << S_ENABLEDEFERACK)
14500 #define F_ENABLEDEFERACK V_ENABLEDEFERACK(1U)
14502 #define S_ENABLEESND 11
14503 #define V_ENABLEESND(x) ((x) << S_ENABLEESND)
14504 #define F_ENABLEESND V_ENABLEESND(1U)
14506 #define S_ENABLECSND 10
14507 #define V_ENABLECSND(x) ((x) << S_ENABLECSND)
14508 #define F_ENABLECSND V_ENABLECSND(1U)
14510 #define S_ENABLEPDUE 9
14511 #define V_ENABLEPDUE(x) ((x) << S_ENABLEPDUE)
14512 #define F_ENABLEPDUE V_ENABLEPDUE(1U)
14514 #define S_ENABLEPDUC 8
14515 #define V_ENABLEPDUC(x) ((x) << S_ENABLEPDUC)
14516 #define F_ENABLEPDUC V_ENABLEPDUC(1U)
14518 #define S_ENABLEBUFI 7
14519 #define V_ENABLEBUFI(x) ((x) << S_ENABLEBUFI)
14520 #define F_ENABLEBUFI V_ENABLEBUFI(1U)
14522 #define S_ENABLEBUFE 6
14523 #define V_ENABLEBUFE(x) ((x) << S_ENABLEBUFE)
14524 #define F_ENABLEBUFE V_ENABLEBUFE(1U)
14526 #define S_ENABLEDEFER 5
14527 #define V_ENABLEDEFER(x) ((x) << S_ENABLEDEFER)
14528 #define F_ENABLEDEFER V_ENABLEDEFER(1U)
14530 #define S_ENABLECLEARRXMTOOS 4
14531 #define V_ENABLECLEARRXMTOOS(x) ((x) << S_ENABLECLEARRXMTOOS)
14532 #define F_ENABLECLEARRXMTOOS V_ENABLECLEARRXMTOOS(1U)
14534 #define S_DISABLEPDUCNG 3
14535 #define V_DISABLEPDUCNG(x) ((x) << S_DISABLEPDUCNG)
14536 #define F_DISABLEPDUCNG V_DISABLEPDUCNG(1U)
14538 #define S_DISABLEPDUTIMEOUT 2
14539 #define V_DISABLEPDUTIMEOUT(x) ((x) << S_DISABLEPDUTIMEOUT)
14540 #define F_DISABLEPDUTIMEOUT V_DISABLEPDUTIMEOUT(1U)
14542 #define S_DISABLEPDURXMT 1
14543 #define V_DISABLEPDURXMT(x) ((x) << S_DISABLEPDURXMT)
14544 #define F_DISABLEPDURXMT V_DISABLEPDURXMT(1U)
14546 #define S_DISABLEPDUXMT 0
14547 #define V_DISABLEPDUXMT(x) ((x) << S_DISABLEPDUXMT)
14548 #define F_DISABLEPDUXMT V_DISABLEPDUXMT(1U)
14550 #define S_DISABLEPDUACK 20
14551 #define V_DISABLEPDUACK(x) ((x) << S_DISABLEPDUACK)
14552 #define F_DISABLEPDUACK V_DISABLEPDUACK(1U)
14554 #define A_TP_PARA_REG7 0x7d7c
14556 #define S_PMMAXXFERLEN1 16
14557 #define M_PMMAXXFERLEN1 0xffffU
14558 #define V_PMMAXXFERLEN1(x) ((x) << S_PMMAXXFERLEN1)
14559 #define G_PMMAXXFERLEN1(x) (((x) >> S_PMMAXXFERLEN1) & M_PMMAXXFERLEN1)
14561 #define S_PMMAXXFERLEN0 0
14562 #define M_PMMAXXFERLEN0 0xffffU
14563 #define V_PMMAXXFERLEN0(x) ((x) << S_PMMAXXFERLEN0)
14564 #define G_PMMAXXFERLEN0(x) (((x) >> S_PMMAXXFERLEN0) & M_PMMAXXFERLEN0)
14566 #define A_TP_ENG_CONFIG 0x7d80
14568 #define S_TABLELATENCYDONE 28
14569 #define M_TABLELATENCYDONE 0xfU
14570 #define V_TABLELATENCYDONE(x) ((x) << S_TABLELATENCYDONE)
14571 #define G_TABLELATENCYDONE(x) (((x) >> S_TABLELATENCYDONE) & M_TABLELATENCYDONE)
14573 #define S_TABLELATENCYSTART 24
14574 #define M_TABLELATENCYSTART 0xfU
14575 #define V_TABLELATENCYSTART(x) ((x) << S_TABLELATENCYSTART)
14576 #define G_TABLELATENCYSTART(x) (((x) >> S_TABLELATENCYSTART) & M_TABLELATENCYSTART)
14578 #define S_ENGINELATENCYDELTA 16
14579 #define M_ENGINELATENCYDELTA 0xfU
14580 #define V_ENGINELATENCYDELTA(x) ((x) << S_ENGINELATENCYDELTA)
14581 #define G_ENGINELATENCYDELTA(x) (((x) >> S_ENGINELATENCYDELTA) & M_ENGINELATENCYDELTA)
14583 #define S_ENGINELATENCYMMGR 12
14584 #define M_ENGINELATENCYMMGR 0xfU
14585 #define V_ENGINELATENCYMMGR(x) ((x) << S_ENGINELATENCYMMGR)
14586 #define G_ENGINELATENCYMMGR(x) (((x) >> S_ENGINELATENCYMMGR) & M_ENGINELATENCYMMGR)
14588 #define S_ENGINELATENCYWIREIP6 8
14589 #define M_ENGINELATENCYWIREIP6 0xfU
14590 #define V_ENGINELATENCYWIREIP6(x) ((x) << S_ENGINELATENCYWIREIP6)
14591 #define G_ENGINELATENCYWIREIP6(x) (((x) >> S_ENGINELATENCYWIREIP6) & M_ENGINELATENCYWIREIP6)
14593 #define S_ENGINELATENCYWIRE 4
14594 #define M_ENGINELATENCYWIRE 0xfU
14595 #define V_ENGINELATENCYWIRE(x) ((x) << S_ENGINELATENCYWIRE)
14596 #define G_ENGINELATENCYWIRE(x) (((x) >> S_ENGINELATENCYWIRE) & M_ENGINELATENCYWIRE)
14598 #define S_ENGINELATENCYBASE 0
14599 #define M_ENGINELATENCYBASE 0xfU
14600 #define V_ENGINELATENCYBASE(x) ((x) << S_ENGINELATENCYBASE)
14601 #define G_ENGINELATENCYBASE(x) (((x) >> S_ENGINELATENCYBASE) & M_ENGINELATENCYBASE)
14603 #define A_TP_ERR_CONFIG 0x7d8c
14605 #define S_TNLERRORPING 30
14606 #define V_TNLERRORPING(x) ((x) << S_TNLERRORPING)
14607 #define F_TNLERRORPING V_TNLERRORPING(1U)
14609 #define S_TNLERRORCSUM 29
14610 #define V_TNLERRORCSUM(x) ((x) << S_TNLERRORCSUM)
14611 #define F_TNLERRORCSUM V_TNLERRORCSUM(1U)
14613 #define S_TNLERRORCSUMIP 28
14614 #define V_TNLERRORCSUMIP(x) ((x) << S_TNLERRORCSUMIP)
14615 #define F_TNLERRORCSUMIP V_TNLERRORCSUMIP(1U)
14617 #define S_TNLERRORTCPOPT 25
14618 #define V_TNLERRORTCPOPT(x) ((x) << S_TNLERRORTCPOPT)
14619 #define F_TNLERRORTCPOPT V_TNLERRORTCPOPT(1U)
14621 #define S_TNLERRORPKTLEN 24
14622 #define V_TNLERRORPKTLEN(x) ((x) << S_TNLERRORPKTLEN)
14623 #define F_TNLERRORPKTLEN V_TNLERRORPKTLEN(1U)
14625 #define S_TNLERRORTCPHDRLEN 23
14626 #define V_TNLERRORTCPHDRLEN(x) ((x) << S_TNLERRORTCPHDRLEN)
14627 #define F_TNLERRORTCPHDRLEN V_TNLERRORTCPHDRLEN(1U)
14629 #define S_TNLERRORIPHDRLEN 22
14630 #define V_TNLERRORIPHDRLEN(x) ((x) << S_TNLERRORIPHDRLEN)
14631 #define F_TNLERRORIPHDRLEN V_TNLERRORIPHDRLEN(1U)
14633 #define S_TNLERRORETHHDRLEN 21
14634 #define V_TNLERRORETHHDRLEN(x) ((x) << S_TNLERRORETHHDRLEN)
14635 #define F_TNLERRORETHHDRLEN V_TNLERRORETHHDRLEN(1U)
14637 #define S_TNLERRORATTACK 20
14638 #define V_TNLERRORATTACK(x) ((x) << S_TNLERRORATTACK)
14639 #define F_TNLERRORATTACK V_TNLERRORATTACK(1U)
14641 #define S_TNLERRORFRAG 19
14642 #define V_TNLERRORFRAG(x) ((x) << S_TNLERRORFRAG)
14643 #define F_TNLERRORFRAG V_TNLERRORFRAG(1U)
14645 #define S_TNLERRORIPVER 18
14646 #define V_TNLERRORIPVER(x) ((x) << S_TNLERRORIPVER)
14647 #define F_TNLERRORIPVER V_TNLERRORIPVER(1U)
14649 #define S_TNLERRORMAC 17
14650 #define V_TNLERRORMAC(x) ((x) << S_TNLERRORMAC)
14651 #define F_TNLERRORMAC V_TNLERRORMAC(1U)
14653 #define S_TNLERRORANY 16
14654 #define V_TNLERRORANY(x) ((x) << S_TNLERRORANY)
14655 #define F_TNLERRORANY V_TNLERRORANY(1U)
14657 #define S_DROPERRORPING 14
14658 #define V_DROPERRORPING(x) ((x) << S_DROPERRORPING)
14659 #define F_DROPERRORPING V_DROPERRORPING(1U)
14661 #define S_DROPERRORCSUM 13
14662 #define V_DROPERRORCSUM(x) ((x) << S_DROPERRORCSUM)
14663 #define F_DROPERRORCSUM V_DROPERRORCSUM(1U)
14665 #define S_DROPERRORCSUMIP 12
14666 #define V_DROPERRORCSUMIP(x) ((x) << S_DROPERRORCSUMIP)
14667 #define F_DROPERRORCSUMIP V_DROPERRORCSUMIP(1U)
14669 #define S_DROPERRORTCPOPT 9
14670 #define V_DROPERRORTCPOPT(x) ((x) << S_DROPERRORTCPOPT)
14671 #define F_DROPERRORTCPOPT V_DROPERRORTCPOPT(1U)
14673 #define S_DROPERRORPKTLEN 8
14674 #define V_DROPERRORPKTLEN(x) ((x) << S_DROPERRORPKTLEN)
14675 #define F_DROPERRORPKTLEN V_DROPERRORPKTLEN(1U)
14677 #define S_DROPERRORTCPHDRLEN 7
14678 #define V_DROPERRORTCPHDRLEN(x) ((x) << S_DROPERRORTCPHDRLEN)
14679 #define F_DROPERRORTCPHDRLEN V_DROPERRORTCPHDRLEN(1U)
14681 #define S_DROPERRORIPHDRLEN 6
14682 #define V_DROPERRORIPHDRLEN(x) ((x) << S_DROPERRORIPHDRLEN)
14683 #define F_DROPERRORIPHDRLEN V_DROPERRORIPHDRLEN(1U)
14685 #define S_DROPERRORETHHDRLEN 5
14686 #define V_DROPERRORETHHDRLEN(x) ((x) << S_DROPERRORETHHDRLEN)
14687 #define F_DROPERRORETHHDRLEN V_DROPERRORETHHDRLEN(1U)
14689 #define S_DROPERRORATTACK 4
14690 #define V_DROPERRORATTACK(x) ((x) << S_DROPERRORATTACK)
14691 #define F_DROPERRORATTACK V_DROPERRORATTACK(1U)
14693 #define S_DROPERRORFRAG 3
14694 #define V_DROPERRORFRAG(x) ((x) << S_DROPERRORFRAG)
14695 #define F_DROPERRORFRAG V_DROPERRORFRAG(1U)
14697 #define S_DROPERRORIPVER 2
14698 #define V_DROPERRORIPVER(x) ((x) << S_DROPERRORIPVER)
14699 #define F_DROPERRORIPVER V_DROPERRORIPVER(1U)
14701 #define S_DROPERRORMAC 1
14702 #define V_DROPERRORMAC(x) ((x) << S_DROPERRORMAC)
14703 #define F_DROPERRORMAC V_DROPERRORMAC(1U)
14705 #define S_DROPERRORANY 0
14706 #define V_DROPERRORANY(x) ((x) << S_DROPERRORANY)
14707 #define F_DROPERRORANY V_DROPERRORANY(1U)
14709 #define S_TNLERRORFPMA 31
14710 #define V_TNLERRORFPMA(x) ((x) << S_TNLERRORFPMA)
14711 #define F_TNLERRORFPMA V_TNLERRORFPMA(1U)
14713 #define S_DROPERRORFPMA 15
14714 #define V_DROPERRORFPMA(x) ((x) << S_DROPERRORFPMA)
14715 #define F_DROPERRORFPMA V_DROPERRORFPMA(1U)
14717 #define A_TP_TIMER_RESOLUTION 0x7d90
14719 #define S_TIMERRESOLUTION 16
14720 #define M_TIMERRESOLUTION 0xffU
14721 #define V_TIMERRESOLUTION(x) ((x) << S_TIMERRESOLUTION)
14722 #define G_TIMERRESOLUTION(x) (((x) >> S_TIMERRESOLUTION) & M_TIMERRESOLUTION)
14724 #define S_TIMESTAMPRESOLUTION 8
14725 #define M_TIMESTAMPRESOLUTION 0xffU
14726 #define V_TIMESTAMPRESOLUTION(x) ((x) << S_TIMESTAMPRESOLUTION)
14727 #define G_TIMESTAMPRESOLUTION(x) (((x) >> S_TIMESTAMPRESOLUTION) & M_TIMESTAMPRESOLUTION)
14729 #define S_DELAYEDACKRESOLUTION 0
14730 #define M_DELAYEDACKRESOLUTION 0xffU
14731 #define V_DELAYEDACKRESOLUTION(x) ((x) << S_DELAYEDACKRESOLUTION)
14732 #define G_DELAYEDACKRESOLUTION(x) (((x) >> S_DELAYEDACKRESOLUTION) & M_DELAYEDACKRESOLUTION)
14734 #define A_TP_MSL 0x7d94
14737 #define M_MSL 0x3fffffffU
14738 #define V_MSL(x) ((x) << S_MSL)
14739 #define G_MSL(x) (((x) >> S_MSL) & M_MSL)
14741 #define A_TP_RXT_MIN 0x7d98
14744 #define M_RXTMIN 0x3fffffffU
14745 #define V_RXTMIN(x) ((x) << S_RXTMIN)
14746 #define G_RXTMIN(x) (((x) >> S_RXTMIN) & M_RXTMIN)
14748 #define A_TP_RXT_MAX 0x7d9c
14751 #define M_RXTMAX 0x3fffffffU
14752 #define V_RXTMAX(x) ((x) << S_RXTMAX)
14753 #define G_RXTMAX(x) (((x) >> S_RXTMAX) & M_RXTMAX)
14755 #define A_TP_PERS_MIN 0x7da0
14757 #define S_PERSMIN 0
14758 #define M_PERSMIN 0x3fffffffU
14759 #define V_PERSMIN(x) ((x) << S_PERSMIN)
14760 #define G_PERSMIN(x) (((x) >> S_PERSMIN) & M_PERSMIN)
14762 #define A_TP_PERS_MAX 0x7da4
14764 #define S_PERSMAX 0
14765 #define M_PERSMAX 0x3fffffffU
14766 #define V_PERSMAX(x) ((x) << S_PERSMAX)
14767 #define G_PERSMAX(x) (((x) >> S_PERSMAX) & M_PERSMAX)
14769 #define A_TP_KEEP_IDLE 0x7da8
14771 #define S_KEEPALIVEIDLE 0
14772 #define M_KEEPALIVEIDLE 0x3fffffffU
14773 #define V_KEEPALIVEIDLE(x) ((x) << S_KEEPALIVEIDLE)
14774 #define G_KEEPALIVEIDLE(x) (((x) >> S_KEEPALIVEIDLE) & M_KEEPALIVEIDLE)
14776 #define A_TP_KEEP_INTVL 0x7dac
14778 #define S_KEEPALIVEINTVL 0
14779 #define M_KEEPALIVEINTVL 0x3fffffffU
14780 #define V_KEEPALIVEINTVL(x) ((x) << S_KEEPALIVEINTVL)
14781 #define G_KEEPALIVEINTVL(x) (((x) >> S_KEEPALIVEINTVL) & M_KEEPALIVEINTVL)
14783 #define A_TP_INIT_SRTT 0x7db0
14785 #define S_MAXRTT 16
14786 #define M_MAXRTT 0xffffU
14787 #define V_MAXRTT(x) ((x) << S_MAXRTT)
14788 #define G_MAXRTT(x) (((x) >> S_MAXRTT) & M_MAXRTT)
14790 #define S_INITSRTT 0
14791 #define M_INITSRTT 0xffffU
14792 #define V_INITSRTT(x) ((x) << S_INITSRTT)
14793 #define G_INITSRTT(x) (((x) >> S_INITSRTT) & M_INITSRTT)
14795 #define A_TP_DACK_TIMER 0x7db4
14797 #define S_DACKTIME 0
14798 #define M_DACKTIME 0xfffU
14799 #define V_DACKTIME(x) ((x) << S_DACKTIME)
14800 #define G_DACKTIME(x) (((x) >> S_DACKTIME) & M_DACKTIME)
14802 #define A_TP_FINWAIT2_TIMER 0x7db8
14804 #define S_FINWAIT2TIME 0
14805 #define M_FINWAIT2TIME 0x3fffffffU
14806 #define V_FINWAIT2TIME(x) ((x) << S_FINWAIT2TIME)
14807 #define G_FINWAIT2TIME(x) (((x) >> S_FINWAIT2TIME) & M_FINWAIT2TIME)
14809 #define A_TP_FAST_FINWAIT2_TIMER 0x7dbc
14811 #define S_FASTFINWAIT2TIME 0
14812 #define M_FASTFINWAIT2TIME 0x3fffffffU
14813 #define V_FASTFINWAIT2TIME(x) ((x) << S_FASTFINWAIT2TIME)
14814 #define G_FASTFINWAIT2TIME(x) (((x) >> S_FASTFINWAIT2TIME) & M_FASTFINWAIT2TIME)
14816 #define A_TP_SHIFT_CNT 0x7dc0
14818 #define S_SYNSHIFTMAX 24
14819 #define M_SYNSHIFTMAX 0xffU
14820 #define V_SYNSHIFTMAX(x) ((x) << S_SYNSHIFTMAX)
14821 #define G_SYNSHIFTMAX(x) (((x) >> S_SYNSHIFTMAX) & M_SYNSHIFTMAX)
14823 #define S_RXTSHIFTMAXR1 20
14824 #define M_RXTSHIFTMAXR1 0xfU
14825 #define V_RXTSHIFTMAXR1(x) ((x) << S_RXTSHIFTMAXR1)
14826 #define G_RXTSHIFTMAXR1(x) (((x) >> S_RXTSHIFTMAXR1) & M_RXTSHIFTMAXR1)
14828 #define S_RXTSHIFTMAXR2 16
14829 #define M_RXTSHIFTMAXR2 0xfU
14830 #define V_RXTSHIFTMAXR2(x) ((x) << S_RXTSHIFTMAXR2)
14831 #define G_RXTSHIFTMAXR2(x) (((x) >> S_RXTSHIFTMAXR2) & M_RXTSHIFTMAXR2)
14833 #define S_PERSHIFTBACKOFFMAX 12
14834 #define M_PERSHIFTBACKOFFMAX 0xfU
14835 #define V_PERSHIFTBACKOFFMAX(x) ((x) << S_PERSHIFTBACKOFFMAX)
14836 #define G_PERSHIFTBACKOFFMAX(x) (((x) >> S_PERSHIFTBACKOFFMAX) & M_PERSHIFTBACKOFFMAX)
14838 #define S_PERSHIFTMAX 8
14839 #define M_PERSHIFTMAX 0xfU
14840 #define V_PERSHIFTMAX(x) ((x) << S_PERSHIFTMAX)
14841 #define G_PERSHIFTMAX(x) (((x) >> S_PERSHIFTMAX) & M_PERSHIFTMAX)
14843 #define S_KEEPALIVEMAXR1 4
14844 #define M_KEEPALIVEMAXR1 0xfU
14845 #define V_KEEPALIVEMAXR1(x) ((x) << S_KEEPALIVEMAXR1)
14846 #define G_KEEPALIVEMAXR1(x) (((x) >> S_KEEPALIVEMAXR1) & M_KEEPALIVEMAXR1)
14848 #define S_KEEPALIVEMAXR2 0
14849 #define M_KEEPALIVEMAXR2 0xfU
14850 #define V_KEEPALIVEMAXR2(x) ((x) << S_KEEPALIVEMAXR2)
14851 #define G_KEEPALIVEMAXR2(x) (((x) >> S_KEEPALIVEMAXR2) & M_KEEPALIVEMAXR2)
14853 #define A_TP_TM_CONFIG 0x7dc4
14855 #define S_CMTIMERMAXNUM 0
14856 #define M_CMTIMERMAXNUM 0x7U
14857 #define V_CMTIMERMAXNUM(x) ((x) << S_CMTIMERMAXNUM)
14858 #define G_CMTIMERMAXNUM(x) (((x) >> S_CMTIMERMAXNUM) & M_CMTIMERMAXNUM)
14860 #define A_TP_TIME_LO 0x7dc8
14861 #define A_TP_TIME_HI 0x7dcc
14862 #define A_TP_PORT_MTU_0 0x7dd0
14864 #define S_PORT1MTUVALUE 16
14865 #define M_PORT1MTUVALUE 0xffffU
14866 #define V_PORT1MTUVALUE(x) ((x) << S_PORT1MTUVALUE)
14867 #define G_PORT1MTUVALUE(x) (((x) >> S_PORT1MTUVALUE) & M_PORT1MTUVALUE)
14869 #define S_PORT0MTUVALUE 0
14870 #define M_PORT0MTUVALUE 0xffffU
14871 #define V_PORT0MTUVALUE(x) ((x) << S_PORT0MTUVALUE)
14872 #define G_PORT0MTUVALUE(x) (((x) >> S_PORT0MTUVALUE) & M_PORT0MTUVALUE)
14874 #define A_TP_PORT_MTU_1 0x7dd4
14876 #define S_PORT3MTUVALUE 16
14877 #define M_PORT3MTUVALUE 0xffffU
14878 #define V_PORT3MTUVALUE(x) ((x) << S_PORT3MTUVALUE)
14879 #define G_PORT3MTUVALUE(x) (((x) >> S_PORT3MTUVALUE) & M_PORT3MTUVALUE)
14881 #define S_PORT2MTUVALUE 0
14882 #define M_PORT2MTUVALUE 0xffffU
14883 #define V_PORT2MTUVALUE(x) ((x) << S_PORT2MTUVALUE)
14884 #define G_PORT2MTUVALUE(x) (((x) >> S_PORT2MTUVALUE) & M_PORT2MTUVALUE)
14886 #define A_TP_PACE_TABLE 0x7dd8
14887 #define A_TP_CCTRL_TABLE 0x7ddc
14889 #define S_ROWINDEX 16
14890 #define M_ROWINDEX 0xffffU
14891 #define V_ROWINDEX(x) ((x) << S_ROWINDEX)
14892 #define G_ROWINDEX(x) (((x) >> S_ROWINDEX) & M_ROWINDEX)
14894 #define S_ROWVALUE 0
14895 #define M_ROWVALUE 0xffffU
14896 #define V_ROWVALUE(x) ((x) << S_ROWVALUE)
14897 #define G_ROWVALUE(x) (((x) >> S_ROWVALUE) & M_ROWVALUE)
14899 #define A_TP_MTU_TABLE 0x7de4
14901 #define S_MTUINDEX 24
14902 #define M_MTUINDEX 0xffU
14903 #define V_MTUINDEX(x) ((x) << S_MTUINDEX)
14904 #define G_MTUINDEX(x) (((x) >> S_MTUINDEX) & M_MTUINDEX)
14906 #define S_MTUWIDTH 16
14907 #define M_MTUWIDTH 0xfU
14908 #define V_MTUWIDTH(x) ((x) << S_MTUWIDTH)
14909 #define G_MTUWIDTH(x) (((x) >> S_MTUWIDTH) & M_MTUWIDTH)
14911 #define S_MTUVALUE 0
14912 #define M_MTUVALUE 0x3fffU
14913 #define V_MTUVALUE(x) ((x) << S_MTUVALUE)
14914 #define G_MTUVALUE(x) (((x) >> S_MTUVALUE) & M_MTUVALUE)
14916 #define A_TP_ULP_TABLE 0x7de8
14918 #define S_ULPTYPE7FIELD 28
14919 #define M_ULPTYPE7FIELD 0xfU
14920 #define V_ULPTYPE7FIELD(x) ((x) << S_ULPTYPE7FIELD)
14921 #define G_ULPTYPE7FIELD(x) (((x) >> S_ULPTYPE7FIELD) & M_ULPTYPE7FIELD)
14923 #define S_ULPTYPE6FIELD 24
14924 #define M_ULPTYPE6FIELD 0xfU
14925 #define V_ULPTYPE6FIELD(x) ((x) << S_ULPTYPE6FIELD)
14926 #define G_ULPTYPE6FIELD(x) (((x) >> S_ULPTYPE6FIELD) & M_ULPTYPE6FIELD)
14928 #define S_ULPTYPE5FIELD 20
14929 #define M_ULPTYPE5FIELD 0xfU
14930 #define V_ULPTYPE5FIELD(x) ((x) << S_ULPTYPE5FIELD)
14931 #define G_ULPTYPE5FIELD(x) (((x) >> S_ULPTYPE5FIELD) & M_ULPTYPE5FIELD)
14933 #define S_ULPTYPE4FIELD 16
14934 #define M_ULPTYPE4FIELD 0xfU
14935 #define V_ULPTYPE4FIELD(x) ((x) << S_ULPTYPE4FIELD)
14936 #define G_ULPTYPE4FIELD(x) (((x) >> S_ULPTYPE4FIELD) & M_ULPTYPE4FIELD)
14938 #define S_ULPTYPE3FIELD 12
14939 #define M_ULPTYPE3FIELD 0xfU
14940 #define V_ULPTYPE3FIELD(x) ((x) << S_ULPTYPE3FIELD)
14941 #define G_ULPTYPE3FIELD(x) (((x) >> S_ULPTYPE3FIELD) & M_ULPTYPE3FIELD)
14943 #define S_ULPTYPE2FIELD 8
14944 #define M_ULPTYPE2FIELD 0xfU
14945 #define V_ULPTYPE2FIELD(x) ((x) << S_ULPTYPE2FIELD)
14946 #define G_ULPTYPE2FIELD(x) (((x) >> S_ULPTYPE2FIELD) & M_ULPTYPE2FIELD)
14948 #define S_ULPTYPE1FIELD 4
14949 #define M_ULPTYPE1FIELD 0xfU
14950 #define V_ULPTYPE1FIELD(x) ((x) << S_ULPTYPE1FIELD)
14951 #define G_ULPTYPE1FIELD(x) (((x) >> S_ULPTYPE1FIELD) & M_ULPTYPE1FIELD)
14953 #define S_ULPTYPE0FIELD 0
14954 #define M_ULPTYPE0FIELD 0xfU
14955 #define V_ULPTYPE0FIELD(x) ((x) << S_ULPTYPE0FIELD)
14956 #define G_ULPTYPE0FIELD(x) (((x) >> S_ULPTYPE0FIELD) & M_ULPTYPE0FIELD)
14958 #define A_TP_RSS_LKP_TABLE 0x7dec
14960 #define S_LKPTBLROWVLD 31
14961 #define V_LKPTBLROWVLD(x) ((x) << S_LKPTBLROWVLD)
14962 #define F_LKPTBLROWVLD V_LKPTBLROWVLD(1U)
14964 #define S_LKPTBLROWIDX 20
14965 #define M_LKPTBLROWIDX 0x3ffU
14966 #define V_LKPTBLROWIDX(x) ((x) << S_LKPTBLROWIDX)
14967 #define G_LKPTBLROWIDX(x) (((x) >> S_LKPTBLROWIDX) & M_LKPTBLROWIDX)
14969 #define S_LKPTBLQUEUE1 10
14970 #define M_LKPTBLQUEUE1 0x3ffU
14971 #define V_LKPTBLQUEUE1(x) ((x) << S_LKPTBLQUEUE1)
14972 #define G_LKPTBLQUEUE1(x) (((x) >> S_LKPTBLQUEUE1) & M_LKPTBLQUEUE1)
14974 #define S_LKPTBLQUEUE0 0
14975 #define M_LKPTBLQUEUE0 0x3ffU
14976 #define V_LKPTBLQUEUE0(x) ((x) << S_LKPTBLQUEUE0)
14977 #define G_LKPTBLQUEUE0(x) (((x) >> S_LKPTBLQUEUE0) & M_LKPTBLQUEUE0)
14979 #define A_TP_RSS_CONFIG 0x7df0
14981 #define S_TNL4TUPENIPV6 31
14982 #define V_TNL4TUPENIPV6(x) ((x) << S_TNL4TUPENIPV6)
14983 #define F_TNL4TUPENIPV6 V_TNL4TUPENIPV6(1U)
14985 #define S_TNL2TUPENIPV6 30
14986 #define V_TNL2TUPENIPV6(x) ((x) << S_TNL2TUPENIPV6)
14987 #define F_TNL2TUPENIPV6 V_TNL2TUPENIPV6(1U)
14989 #define S_TNL4TUPENIPV4 29
14990 #define V_TNL4TUPENIPV4(x) ((x) << S_TNL4TUPENIPV4)
14991 #define F_TNL4TUPENIPV4 V_TNL4TUPENIPV4(1U)
14993 #define S_TNL2TUPENIPV4 28
14994 #define V_TNL2TUPENIPV4(x) ((x) << S_TNL2TUPENIPV4)
14995 #define F_TNL2TUPENIPV4 V_TNL2TUPENIPV4(1U)
14997 #define S_TNLTCPSEL 27
14998 #define V_TNLTCPSEL(x) ((x) << S_TNLTCPSEL)
14999 #define F_TNLTCPSEL V_TNLTCPSEL(1U)
15001 #define S_TNLIP6SEL 26
15002 #define V_TNLIP6SEL(x) ((x) << S_TNLIP6SEL)
15003 #define F_TNLIP6SEL V_TNLIP6SEL(1U)
15005 #define S_TNLVRTSEL 25
15006 #define V_TNLVRTSEL(x) ((x) << S_TNLVRTSEL)
15007 #define F_TNLVRTSEL V_TNLVRTSEL(1U)
15009 #define S_TNLMAPEN 24
15010 #define V_TNLMAPEN(x) ((x) << S_TNLMAPEN)
15011 #define F_TNLMAPEN V_TNLMAPEN(1U)
15013 #define S_OFDHASHSAVE 19
15014 #define V_OFDHASHSAVE(x) ((x) << S_OFDHASHSAVE)
15015 #define F_OFDHASHSAVE V_OFDHASHSAVE(1U)
15017 #define S_OFDVRTSEL 18
15018 #define V_OFDVRTSEL(x) ((x) << S_OFDVRTSEL)
15019 #define F_OFDVRTSEL V_OFDVRTSEL(1U)
15021 #define S_OFDMAPEN 17
15022 #define V_OFDMAPEN(x) ((x) << S_OFDMAPEN)
15023 #define F_OFDMAPEN V_OFDMAPEN(1U)
15025 #define S_OFDLKPEN 16
15026 #define V_OFDLKPEN(x) ((x) << S_OFDLKPEN)
15027 #define F_OFDLKPEN V_OFDLKPEN(1U)
15029 #define S_SYN4TUPENIPV6 15
15030 #define V_SYN4TUPENIPV6(x) ((x) << S_SYN4TUPENIPV6)
15031 #define F_SYN4TUPENIPV6 V_SYN4TUPENIPV6(1U)
15033 #define S_SYN2TUPENIPV6 14
15034 #define V_SYN2TUPENIPV6(x) ((x) << S_SYN2TUPENIPV6)
15035 #define F_SYN2TUPENIPV6 V_SYN2TUPENIPV6(1U)
15037 #define S_SYN4TUPENIPV4 13
15038 #define V_SYN4TUPENIPV4(x) ((x) << S_SYN4TUPENIPV4)
15039 #define F_SYN4TUPENIPV4 V_SYN4TUPENIPV4(1U)
15041 #define S_SYN2TUPENIPV4 12
15042 #define V_SYN2TUPENIPV4(x) ((x) << S_SYN2TUPENIPV4)
15043 #define F_SYN2TUPENIPV4 V_SYN2TUPENIPV4(1U)
15045 #define S_SYNIP6SEL 11
15046 #define V_SYNIP6SEL(x) ((x) << S_SYNIP6SEL)
15047 #define F_SYNIP6SEL V_SYNIP6SEL(1U)
15049 #define S_SYNVRTSEL 10
15050 #define V_SYNVRTSEL(x) ((x) << S_SYNVRTSEL)
15051 #define F_SYNVRTSEL V_SYNVRTSEL(1U)
15053 #define S_SYNMAPEN 9
15054 #define V_SYNMAPEN(x) ((x) << S_SYNMAPEN)
15055 #define F_SYNMAPEN V_SYNMAPEN(1U)
15057 #define S_SYNLKPEN 8
15058 #define V_SYNLKPEN(x) ((x) << S_SYNLKPEN)
15059 #define F_SYNLKPEN V_SYNLKPEN(1U)
15061 #define S_CHANNELENABLE 7
15062 #define V_CHANNELENABLE(x) ((x) << S_CHANNELENABLE)
15063 #define F_CHANNELENABLE V_CHANNELENABLE(1U)
15065 #define S_PORTENABLE 6
15066 #define V_PORTENABLE(x) ((x) << S_PORTENABLE)
15067 #define F_PORTENABLE V_PORTENABLE(1U)
15069 #define S_TNLALLLOOKUP 5
15070 #define V_TNLALLLOOKUP(x) ((x) << S_TNLALLLOOKUP)
15071 #define F_TNLALLLOOKUP V_TNLALLLOOKUP(1U)
15073 #define S_VIRTENABLE 4
15074 #define V_VIRTENABLE(x) ((x) << S_VIRTENABLE)
15075 #define F_VIRTENABLE V_VIRTENABLE(1U)
15077 #define S_CONGESTIONENABLE 3
15078 #define V_CONGESTIONENABLE(x) ((x) << S_CONGESTIONENABLE)
15079 #define F_CONGESTIONENABLE V_CONGESTIONENABLE(1U)
15081 #define S_HASHTOEPLITZ 2
15082 #define V_HASHTOEPLITZ(x) ((x) << S_HASHTOEPLITZ)
15083 #define F_HASHTOEPLITZ V_HASHTOEPLITZ(1U)
15085 #define S_UDPENABLE 1
15086 #define V_UDPENABLE(x) ((x) << S_UDPENABLE)
15087 #define F_UDPENABLE V_UDPENABLE(1U)
15089 #define S_DISABLE 0
15090 #define V_DISABLE(x) ((x) << S_DISABLE)
15091 #define F_DISABLE V_DISABLE(1U)
15093 #define S_TNLFCOEMODE 23
15094 #define V_TNLFCOEMODE(x) ((x) << S_TNLFCOEMODE)
15095 #define F_TNLFCOEMODE V_TNLFCOEMODE(1U)
15097 #define S_TNLFCOEEN 21
15098 #define V_TNLFCOEEN(x) ((x) << S_TNLFCOEEN)
15099 #define F_TNLFCOEEN V_TNLFCOEEN(1U)
15101 #define S_HASHXOR 20
15102 #define V_HASHXOR(x) ((x) << S_HASHXOR)
15103 #define F_HASHXOR V_HASHXOR(1U)
15105 #define A_TP_RSS_CONFIG_TNL 0x7df4
15107 #define S_MASKSIZE 28
15108 #define M_MASKSIZE 0xfU
15109 #define V_MASKSIZE(x) ((x) << S_MASKSIZE)
15110 #define G_MASKSIZE(x) (((x) >> S_MASKSIZE) & M_MASKSIZE)
15112 #define S_MASKFILTER 16
15113 #define M_MASKFILTER 0x7ffU
15114 #define V_MASKFILTER(x) ((x) << S_MASKFILTER)
15115 #define G_MASKFILTER(x) (((x) >> S_MASKFILTER) & M_MASKFILTER)
15117 #define S_USEWIRECH 0
15118 #define V_USEWIRECH(x) ((x) << S_USEWIRECH)
15119 #define F_USEWIRECH V_USEWIRECH(1U)
15121 #define A_TP_RSS_CONFIG_OFD 0x7df8
15123 #define S_RRCPLMAPEN 20
15124 #define V_RRCPLMAPEN(x) ((x) << S_RRCPLMAPEN)
15125 #define F_RRCPLMAPEN V_RRCPLMAPEN(1U)
15127 #define S_RRCPLQUEWIDTH 16
15128 #define M_RRCPLQUEWIDTH 0xfU
15129 #define V_RRCPLQUEWIDTH(x) ((x) << S_RRCPLQUEWIDTH)
15130 #define G_RRCPLQUEWIDTH(x) (((x) >> S_RRCPLQUEWIDTH) & M_RRCPLQUEWIDTH)
15132 #define S_FRMWRQUEMASK 12
15133 #define M_FRMWRQUEMASK 0xfU
15134 #define V_FRMWRQUEMASK(x) ((x) << S_FRMWRQUEMASK)
15135 #define G_FRMWRQUEMASK(x) (((x) >> S_FRMWRQUEMASK) & M_FRMWRQUEMASK)
15137 #define A_TP_RSS_CONFIG_SYN 0x7dfc
15138 #define A_TP_RSS_CONFIG_VRT 0x7e00
15140 #define S_VFRDRG 25
15141 #define V_VFRDRG(x) ((x) << S_VFRDRG)
15142 #define F_VFRDRG V_VFRDRG(1U)
15144 #define S_VFRDEN 24
15145 #define V_VFRDEN(x) ((x) << S_VFRDEN)
15146 #define F_VFRDEN V_VFRDEN(1U)
15148 #define S_VFPERREN 23
15149 #define V_VFPERREN(x) ((x) << S_VFPERREN)
15150 #define F_VFPERREN V_VFPERREN(1U)
15152 #define S_KEYPERREN 22
15153 #define V_KEYPERREN(x) ((x) << S_KEYPERREN)
15154 #define F_KEYPERREN V_KEYPERREN(1U)
15156 #define S_DISABLEVLAN 21
15157 #define V_DISABLEVLAN(x) ((x) << S_DISABLEVLAN)
15158 #define F_DISABLEVLAN V_DISABLEVLAN(1U)
15160 #define S_ENABLEUP0 20
15161 #define V_ENABLEUP0(x) ((x) << S_ENABLEUP0)
15162 #define F_ENABLEUP0 V_ENABLEUP0(1U)
15164 #define S_HASHDELAY 16
15165 #define M_HASHDELAY 0xfU
15166 #define V_HASHDELAY(x) ((x) << S_HASHDELAY)
15167 #define G_HASHDELAY(x) (((x) >> S_HASHDELAY) & M_HASHDELAY)
15169 #define S_VFWRADDR 8
15170 #define M_VFWRADDR 0x7fU
15171 #define V_VFWRADDR(x) ((x) << S_VFWRADDR)
15172 #define G_VFWRADDR(x) (((x) >> S_VFWRADDR) & M_VFWRADDR)
15174 #define S_KEYMODE 6
15175 #define M_KEYMODE 0x3U
15176 #define V_KEYMODE(x) ((x) << S_KEYMODE)
15177 #define G_KEYMODE(x) (((x) >> S_KEYMODE) & M_KEYMODE)
15180 #define V_VFWREN(x) ((x) << S_VFWREN)
15181 #define F_VFWREN V_VFWREN(1U)
15183 #define S_KEYWREN 4
15184 #define V_KEYWREN(x) ((x) << S_KEYWREN)
15185 #define F_KEYWREN V_KEYWREN(1U)
15187 #define S_KEYWRADDR 0
15188 #define M_KEYWRADDR 0xfU
15189 #define V_KEYWRADDR(x) ((x) << S_KEYWRADDR)
15190 #define G_KEYWRADDR(x) (((x) >> S_KEYWRADDR) & M_KEYWRADDR)
15192 #define S_VFVLANEN 21
15193 #define V_VFVLANEN(x) ((x) << S_VFVLANEN)
15194 #define F_VFVLANEN V_VFVLANEN(1U)
15196 #define S_VFFWEN 20
15197 #define V_VFFWEN(x) ((x) << S_VFFWEN)
15198 #define F_VFFWEN V_VFFWEN(1U)
15200 #define A_TP_RSS_CONFIG_CNG 0x7e04
15202 #define S_CHNCOUNT3 31
15203 #define V_CHNCOUNT3(x) ((x) << S_CHNCOUNT3)
15204 #define F_CHNCOUNT3 V_CHNCOUNT3(1U)
15206 #define S_CHNCOUNT2 30
15207 #define V_CHNCOUNT2(x) ((x) << S_CHNCOUNT2)
15208 #define F_CHNCOUNT2 V_CHNCOUNT2(1U)
15210 #define S_CHNCOUNT1 29
15211 #define V_CHNCOUNT1(x) ((x) << S_CHNCOUNT1)
15212 #define F_CHNCOUNT1 V_CHNCOUNT1(1U)
15214 #define S_CHNCOUNT0 28
15215 #define V_CHNCOUNT0(x) ((x) << S_CHNCOUNT0)
15216 #define F_CHNCOUNT0 V_CHNCOUNT0(1U)
15218 #define S_CHNUNDFLOW3 27
15219 #define V_CHNUNDFLOW3(x) ((x) << S_CHNUNDFLOW3)
15220 #define F_CHNUNDFLOW3 V_CHNUNDFLOW3(1U)
15222 #define S_CHNUNDFLOW2 26
15223 #define V_CHNUNDFLOW2(x) ((x) << S_CHNUNDFLOW2)
15224 #define F_CHNUNDFLOW2 V_CHNUNDFLOW2(1U)
15226 #define S_CHNUNDFLOW1 25
15227 #define V_CHNUNDFLOW1(x) ((x) << S_CHNUNDFLOW1)
15228 #define F_CHNUNDFLOW1 V_CHNUNDFLOW1(1U)
15230 #define S_CHNUNDFLOW0 24
15231 #define V_CHNUNDFLOW0(x) ((x) << S_CHNUNDFLOW0)
15232 #define F_CHNUNDFLOW0 V_CHNUNDFLOW0(1U)
15234 #define S_CHNOVRFLOW3 23
15235 #define V_CHNOVRFLOW3(x) ((x) << S_CHNOVRFLOW3)
15236 #define F_CHNOVRFLOW3 V_CHNOVRFLOW3(1U)
15238 #define S_CHNOVRFLOW2 22
15239 #define V_CHNOVRFLOW2(x) ((x) << S_CHNOVRFLOW2)
15240 #define F_CHNOVRFLOW2 V_CHNOVRFLOW2(1U)
15242 #define S_CHNOVRFLOW1 21
15243 #define V_CHNOVRFLOW1(x) ((x) << S_CHNOVRFLOW1)
15244 #define F_CHNOVRFLOW1 V_CHNOVRFLOW1(1U)
15246 #define S_CHNOVRFLOW0 20
15247 #define V_CHNOVRFLOW0(x) ((x) << S_CHNOVRFLOW0)
15248 #define F_CHNOVRFLOW0 V_CHNOVRFLOW0(1U)
15250 #define S_RSTCHN3 19
15251 #define V_RSTCHN3(x) ((x) << S_RSTCHN3)
15252 #define F_RSTCHN3 V_RSTCHN3(1U)
15254 #define S_RSTCHN2 18
15255 #define V_RSTCHN2(x) ((x) << S_RSTCHN2)
15256 #define F_RSTCHN2 V_RSTCHN2(1U)
15258 #define S_RSTCHN1 17
15259 #define V_RSTCHN1(x) ((x) << S_RSTCHN1)
15260 #define F_RSTCHN1 V_RSTCHN1(1U)
15262 #define S_RSTCHN0 16
15263 #define V_RSTCHN0(x) ((x) << S_RSTCHN0)
15264 #define F_RSTCHN0 V_RSTCHN0(1U)
15266 #define S_UPDVLD 15
15267 #define V_UPDVLD(x) ((x) << S_UPDVLD)
15268 #define F_UPDVLD V_UPDVLD(1U)
15271 #define V_XOFF(x) ((x) << S_XOFF)
15272 #define F_XOFF V_XOFF(1U)
15274 #define S_UPDCHN3 13
15275 #define V_UPDCHN3(x) ((x) << S_UPDCHN3)
15276 #define F_UPDCHN3 V_UPDCHN3(1U)
15278 #define S_UPDCHN2 12
15279 #define V_UPDCHN2(x) ((x) << S_UPDCHN2)
15280 #define F_UPDCHN2 V_UPDCHN2(1U)
15282 #define S_UPDCHN1 11
15283 #define V_UPDCHN1(x) ((x) << S_UPDCHN1)
15284 #define F_UPDCHN1 V_UPDCHN1(1U)
15286 #define S_UPDCHN0 10
15287 #define V_UPDCHN0(x) ((x) << S_UPDCHN0)
15288 #define F_UPDCHN0 V_UPDCHN0(1U)
15291 #define M_QUEUE 0x3ffU
15292 #define V_QUEUE(x) ((x) << S_QUEUE)
15293 #define G_QUEUE(x) (((x) >> S_QUEUE) & M_QUEUE)
15295 #define A_TP_LA_TABLE_0 0x7e10
15297 #define S_VIRTPORT1TABLE 16
15298 #define M_VIRTPORT1TABLE 0xffffU
15299 #define V_VIRTPORT1TABLE(x) ((x) << S_VIRTPORT1TABLE)
15300 #define G_VIRTPORT1TABLE(x) (((x) >> S_VIRTPORT1TABLE) & M_VIRTPORT1TABLE)
15302 #define S_VIRTPORT0TABLE 0
15303 #define M_VIRTPORT0TABLE 0xffffU
15304 #define V_VIRTPORT0TABLE(x) ((x) << S_VIRTPORT0TABLE)
15305 #define G_VIRTPORT0TABLE(x) (((x) >> S_VIRTPORT0TABLE) & M_VIRTPORT0TABLE)
15307 #define A_TP_LA_TABLE_1 0x7e14
15309 #define S_VIRTPORT3TABLE 16
15310 #define M_VIRTPORT3TABLE 0xffffU
15311 #define V_VIRTPORT3TABLE(x) ((x) << S_VIRTPORT3TABLE)
15312 #define G_VIRTPORT3TABLE(x) (((x) >> S_VIRTPORT3TABLE) & M_VIRTPORT3TABLE)
15314 #define S_VIRTPORT2TABLE 0
15315 #define M_VIRTPORT2TABLE 0xffffU
15316 #define V_VIRTPORT2TABLE(x) ((x) << S_VIRTPORT2TABLE)
15317 #define G_VIRTPORT2TABLE(x) (((x) >> S_VIRTPORT2TABLE) & M_VIRTPORT2TABLE)
15319 #define A_TP_TM_PIO_ADDR 0x7e18
15320 #define A_TP_TM_PIO_DATA 0x7e1c
15321 #define A_TP_MOD_CONFIG 0x7e24
15323 #define S_RXCHANNELWEIGHT1 24
15324 #define M_RXCHANNELWEIGHT1 0xffU
15325 #define V_RXCHANNELWEIGHT1(x) ((x) << S_RXCHANNELWEIGHT1)
15326 #define G_RXCHANNELWEIGHT1(x) (((x) >> S_RXCHANNELWEIGHT1) & M_RXCHANNELWEIGHT1)
15328 #define S_RXCHANNELWEIGHT0 16
15329 #define M_RXCHANNELWEIGHT0 0xffU
15330 #define V_RXCHANNELWEIGHT0(x) ((x) << S_RXCHANNELWEIGHT0)
15331 #define G_RXCHANNELWEIGHT0(x) (((x) >> S_RXCHANNELWEIGHT0) & M_RXCHANNELWEIGHT0)
15333 #define S_TIMERMODE 8
15334 #define M_TIMERMODE 0xffU
15335 #define V_TIMERMODE(x) ((x) << S_TIMERMODE)
15336 #define G_TIMERMODE(x) (((x) >> S_TIMERMODE) & M_TIMERMODE)
15338 #define S_TXCHANNELXOFFEN 0
15339 #define M_TXCHANNELXOFFEN 0xfU
15340 #define V_TXCHANNELXOFFEN(x) ((x) << S_TXCHANNELXOFFEN)
15341 #define G_TXCHANNELXOFFEN(x) (((x) >> S_TXCHANNELXOFFEN) & M_TXCHANNELXOFFEN)
15343 #define A_TP_TX_MOD_QUEUE_REQ_MAP 0x7e28
15345 #define S_RX_MOD_WEIGHT 24
15346 #define M_RX_MOD_WEIGHT 0xffU
15347 #define V_RX_MOD_WEIGHT(x) ((x) << S_RX_MOD_WEIGHT)
15348 #define G_RX_MOD_WEIGHT(x) (((x) >> S_RX_MOD_WEIGHT) & M_RX_MOD_WEIGHT)
15350 #define S_TX_MOD_WEIGHT 16
15351 #define M_TX_MOD_WEIGHT 0xffU
15352 #define V_TX_MOD_WEIGHT(x) ((x) << S_TX_MOD_WEIGHT)
15353 #define G_TX_MOD_WEIGHT(x) (((x) >> S_TX_MOD_WEIGHT) & M_TX_MOD_WEIGHT)
15355 #define S_TX_MOD_QUEUE_REQ_MAP 0
15356 #define M_TX_MOD_QUEUE_REQ_MAP 0xffffU
15357 #define V_TX_MOD_QUEUE_REQ_MAP(x) ((x) << S_TX_MOD_QUEUE_REQ_MAP)
15358 #define G_TX_MOD_QUEUE_REQ_MAP(x) (((x) >> S_TX_MOD_QUEUE_REQ_MAP) & M_TX_MOD_QUEUE_REQ_MAP)
15360 #define A_TP_TX_MOD_QUEUE_WEIGHT1 0x7e2c
15362 #define S_TX_MODQ_WEIGHT7 24
15363 #define M_TX_MODQ_WEIGHT7 0xffU
15364 #define V_TX_MODQ_WEIGHT7(x) ((x) << S_TX_MODQ_WEIGHT7)
15365 #define G_TX_MODQ_WEIGHT7(x) (((x) >> S_TX_MODQ_WEIGHT7) & M_TX_MODQ_WEIGHT7)
15367 #define S_TX_MODQ_WEIGHT6 16
15368 #define M_TX_MODQ_WEIGHT6 0xffU
15369 #define V_TX_MODQ_WEIGHT6(x) ((x) << S_TX_MODQ_WEIGHT6)
15370 #define G_TX_MODQ_WEIGHT6(x) (((x) >> S_TX_MODQ_WEIGHT6) & M_TX_MODQ_WEIGHT6)
15372 #define S_TX_MODQ_WEIGHT5 8
15373 #define M_TX_MODQ_WEIGHT5 0xffU
15374 #define V_TX_MODQ_WEIGHT5(x) ((x) << S_TX_MODQ_WEIGHT5)
15375 #define G_TX_MODQ_WEIGHT5(x) (((x) >> S_TX_MODQ_WEIGHT5) & M_TX_MODQ_WEIGHT5)
15377 #define S_TX_MODQ_WEIGHT4 0
15378 #define M_TX_MODQ_WEIGHT4 0xffU
15379 #define V_TX_MODQ_WEIGHT4(x) ((x) << S_TX_MODQ_WEIGHT4)
15380 #define G_TX_MODQ_WEIGHT4(x) (((x) >> S_TX_MODQ_WEIGHT4) & M_TX_MODQ_WEIGHT4)
15382 #define A_TP_TX_MOD_QUEUE_WEIGHT0 0x7e30
15384 #define S_TX_MODQ_WEIGHT3 24
15385 #define M_TX_MODQ_WEIGHT3 0xffU
15386 #define V_TX_MODQ_WEIGHT3(x) ((x) << S_TX_MODQ_WEIGHT3)
15387 #define G_TX_MODQ_WEIGHT3(x) (((x) >> S_TX_MODQ_WEIGHT3) & M_TX_MODQ_WEIGHT3)
15389 #define S_TX_MODQ_WEIGHT2 16
15390 #define M_TX_MODQ_WEIGHT2 0xffU
15391 #define V_TX_MODQ_WEIGHT2(x) ((x) << S_TX_MODQ_WEIGHT2)
15392 #define G_TX_MODQ_WEIGHT2(x) (((x) >> S_TX_MODQ_WEIGHT2) & M_TX_MODQ_WEIGHT2)
15394 #define S_TX_MODQ_WEIGHT1 8
15395 #define M_TX_MODQ_WEIGHT1 0xffU
15396 #define V_TX_MODQ_WEIGHT1(x) ((x) << S_TX_MODQ_WEIGHT1)
15397 #define G_TX_MODQ_WEIGHT1(x) (((x) >> S_TX_MODQ_WEIGHT1) & M_TX_MODQ_WEIGHT1)
15399 #define S_TX_MODQ_WEIGHT0 0
15400 #define M_TX_MODQ_WEIGHT0 0xffU
15401 #define V_TX_MODQ_WEIGHT0(x) ((x) << S_TX_MODQ_WEIGHT0)
15402 #define G_TX_MODQ_WEIGHT0(x) (((x) >> S_TX_MODQ_WEIGHT0) & M_TX_MODQ_WEIGHT0)
15404 #define A_TP_TX_MOD_CHANNEL_WEIGHT 0x7e34
15405 #define A_TP_MOD_RATE_LIMIT 0x7e38
15407 #define S_RX_MOD_RATE_LIMIT_INC 24
15408 #define M_RX_MOD_RATE_LIMIT_INC 0xffU
15409 #define V_RX_MOD_RATE_LIMIT_INC(x) ((x) << S_RX_MOD_RATE_LIMIT_INC)
15410 #define G_RX_MOD_RATE_LIMIT_INC(x) (((x) >> S_RX_MOD_RATE_LIMIT_INC) & M_RX_MOD_RATE_LIMIT_INC)
15412 #define S_RX_MOD_RATE_LIMIT_TICK 16
15413 #define M_RX_MOD_RATE_LIMIT_TICK 0xffU
15414 #define V_RX_MOD_RATE_LIMIT_TICK(x) ((x) << S_RX_MOD_RATE_LIMIT_TICK)
15415 #define G_RX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_RX_MOD_RATE_LIMIT_TICK) & M_RX_MOD_RATE_LIMIT_TICK)
15417 #define S_TX_MOD_RATE_LIMIT_INC 8
15418 #define M_TX_MOD_RATE_LIMIT_INC 0xffU
15419 #define V_TX_MOD_RATE_LIMIT_INC(x) ((x) << S_TX_MOD_RATE_LIMIT_INC)
15420 #define G_TX_MOD_RATE_LIMIT_INC(x) (((x) >> S_TX_MOD_RATE_LIMIT_INC) & M_TX_MOD_RATE_LIMIT_INC)
15422 #define S_TX_MOD_RATE_LIMIT_TICK 0
15423 #define M_TX_MOD_RATE_LIMIT_TICK 0xffU
15424 #define V_TX_MOD_RATE_LIMIT_TICK(x) ((x) << S_TX_MOD_RATE_LIMIT_TICK)
15425 #define G_TX_MOD_RATE_LIMIT_TICK(x) (((x) >> S_TX_MOD_RATE_LIMIT_TICK) & M_TX_MOD_RATE_LIMIT_TICK)
15427 #define A_TP_PIO_ADDR 0x7e40
15428 #define A_TP_PIO_DATA 0x7e44
15429 #define A_TP_RESET 0x7e4c
15431 #define S_FLSTINITENABLE 1
15432 #define V_FLSTINITENABLE(x) ((x) << S_FLSTINITENABLE)
15433 #define F_FLSTINITENABLE V_FLSTINITENABLE(1U)
15435 #define S_TPRESET 0
15436 #define V_TPRESET(x) ((x) << S_TPRESET)
15437 #define F_TPRESET V_TPRESET(1U)
15439 #define A_TP_MIB_INDEX 0x7e50
15440 #define A_TP_MIB_DATA 0x7e54
15441 #define A_TP_SYNC_TIME_HI 0x7e58
15442 #define A_TP_SYNC_TIME_LO 0x7e5c
15443 #define A_TP_CMM_MM_RX_FLST_BASE 0x7e60
15444 #define A_TP_CMM_MM_TX_FLST_BASE 0x7e64
15445 #define A_TP_CMM_MM_PS_FLST_BASE 0x7e68
15446 #define A_TP_CMM_MM_MAX_PSTRUCT 0x7e6c
15448 #define S_CMMAXPSTRUCT 0
15449 #define M_CMMAXPSTRUCT 0x1fffffU
15450 #define V_CMMAXPSTRUCT(x) ((x) << S_CMMAXPSTRUCT)
15451 #define G_CMMAXPSTRUCT(x) (((x) >> S_CMMAXPSTRUCT) & M_CMMAXPSTRUCT)
15453 #define A_TP_INT_ENABLE 0x7e70
15455 #define S_FLMTXFLSTEMPTY 30
15456 #define V_FLMTXFLSTEMPTY(x) ((x) << S_FLMTXFLSTEMPTY)
15457 #define F_FLMTXFLSTEMPTY V_FLMTXFLSTEMPTY(1U)
15459 #define S_RSSLKPPERR 29
15460 #define V_RSSLKPPERR(x) ((x) << S_RSSLKPPERR)
15461 #define F_RSSLKPPERR V_RSSLKPPERR(1U)
15463 #define S_FLMPERRSET 28
15464 #define V_FLMPERRSET(x) ((x) << S_FLMPERRSET)
15465 #define F_FLMPERRSET V_FLMPERRSET(1U)
15467 #define S_PROTOCOLSRAMPERR 27
15468 #define V_PROTOCOLSRAMPERR(x) ((x) << S_PROTOCOLSRAMPERR)
15469 #define F_PROTOCOLSRAMPERR V_PROTOCOLSRAMPERR(1U)
15471 #define S_ARPLUTPERR 26
15472 #define V_ARPLUTPERR(x) ((x) << S_ARPLUTPERR)
15473 #define F_ARPLUTPERR V_ARPLUTPERR(1U)
15475 #define S_CMRCFOPPERR 25
15476 #define V_CMRCFOPPERR(x) ((x) << S_CMRCFOPPERR)
15477 #define F_CMRCFOPPERR V_CMRCFOPPERR(1U)
15479 #define S_CMCACHEPERR 24
15480 #define V_CMCACHEPERR(x) ((x) << S_CMCACHEPERR)
15481 #define F_CMCACHEPERR V_CMCACHEPERR(1U)
15483 #define S_CMRCFDATAPERR 23
15484 #define V_CMRCFDATAPERR(x) ((x) << S_CMRCFDATAPERR)
15485 #define F_CMRCFDATAPERR V_CMRCFDATAPERR(1U)
15487 #define S_DBL2TLUTPERR 22
15488 #define V_DBL2TLUTPERR(x) ((x) << S_DBL2TLUTPERR)
15489 #define F_DBL2TLUTPERR V_DBL2TLUTPERR(1U)
15491 #define S_DBTXTIDPERR 21
15492 #define V_DBTXTIDPERR(x) ((x) << S_DBTXTIDPERR)
15493 #define F_DBTXTIDPERR V_DBTXTIDPERR(1U)
15495 #define S_DBEXTPERR 20
15496 #define V_DBEXTPERR(x) ((x) << S_DBEXTPERR)
15497 #define F_DBEXTPERR V_DBEXTPERR(1U)
15499 #define S_DBOPPERR 19
15500 #define V_DBOPPERR(x) ((x) << S_DBOPPERR)
15501 #define F_DBOPPERR V_DBOPPERR(1U)
15503 #define S_TMCACHEPERR 18
15504 #define V_TMCACHEPERR(x) ((x) << S_TMCACHEPERR)
15505 #define F_TMCACHEPERR V_TMCACHEPERR(1U)
15507 #define S_ETPOUTCPLFIFOPERR 17
15508 #define V_ETPOUTCPLFIFOPERR(x) ((x) << S_ETPOUTCPLFIFOPERR)
15509 #define F_ETPOUTCPLFIFOPERR V_ETPOUTCPLFIFOPERR(1U)
15511 #define S_ETPOUTTCPFIFOPERR 16
15512 #define V_ETPOUTTCPFIFOPERR(x) ((x) << S_ETPOUTTCPFIFOPERR)
15513 #define F_ETPOUTTCPFIFOPERR V_ETPOUTTCPFIFOPERR(1U)
15515 #define S_ETPOUTIPFIFOPERR 15
15516 #define V_ETPOUTIPFIFOPERR(x) ((x) << S_ETPOUTIPFIFOPERR)
15517 #define F_ETPOUTIPFIFOPERR V_ETPOUTIPFIFOPERR(1U)
15519 #define S_ETPOUTETHFIFOPERR 14
15520 #define V_ETPOUTETHFIFOPERR(x) ((x) << S_ETPOUTETHFIFOPERR)
15521 #define F_ETPOUTETHFIFOPERR V_ETPOUTETHFIFOPERR(1U)
15523 #define S_ETPINCPLFIFOPERR 13
15524 #define V_ETPINCPLFIFOPERR(x) ((x) << S_ETPINCPLFIFOPERR)
15525 #define F_ETPINCPLFIFOPERR V_ETPINCPLFIFOPERR(1U)
15527 #define S_ETPINTCPOPTFIFOPERR 12
15528 #define V_ETPINTCPOPTFIFOPERR(x) ((x) << S_ETPINTCPOPTFIFOPERR)
15529 #define F_ETPINTCPOPTFIFOPERR V_ETPINTCPOPTFIFOPERR(1U)
15531 #define S_ETPINTCPFIFOPERR 11
15532 #define V_ETPINTCPFIFOPERR(x) ((x) << S_ETPINTCPFIFOPERR)
15533 #define F_ETPINTCPFIFOPERR V_ETPINTCPFIFOPERR(1U)
15535 #define S_ETPINIPFIFOPERR 10
15536 #define V_ETPINIPFIFOPERR(x) ((x) << S_ETPINIPFIFOPERR)
15537 #define F_ETPINIPFIFOPERR V_ETPINIPFIFOPERR(1U)
15539 #define S_ETPINETHFIFOPERR 9
15540 #define V_ETPINETHFIFOPERR(x) ((x) << S_ETPINETHFIFOPERR)
15541 #define F_ETPINETHFIFOPERR V_ETPINETHFIFOPERR(1U)
15543 #define S_CTPOUTCPLFIFOPERR 8
15544 #define V_CTPOUTCPLFIFOPERR(x) ((x) << S_CTPOUTCPLFIFOPERR)
15545 #define F_CTPOUTCPLFIFOPERR V_CTPOUTCPLFIFOPERR(1U)
15547 #define S_CTPOUTTCPFIFOPERR 7
15548 #define V_CTPOUTTCPFIFOPERR(x) ((x) << S_CTPOUTTCPFIFOPERR)
15549 #define F_CTPOUTTCPFIFOPERR V_CTPOUTTCPFIFOPERR(1U)
15551 #define S_CTPOUTIPFIFOPERR 6
15552 #define V_CTPOUTIPFIFOPERR(x) ((x) << S_CTPOUTIPFIFOPERR)
15553 #define F_CTPOUTIPFIFOPERR V_CTPOUTIPFIFOPERR(1U)
15555 #define S_CTPOUTETHFIFOPERR 5
15556 #define V_CTPOUTETHFIFOPERR(x) ((x) << S_CTPOUTETHFIFOPERR)
15557 #define F_CTPOUTETHFIFOPERR V_CTPOUTETHFIFOPERR(1U)
15559 #define S_CTPINCPLFIFOPERR 4
15560 #define V_CTPINCPLFIFOPERR(x) ((x) << S_CTPINCPLFIFOPERR)
15561 #define F_CTPINCPLFIFOPERR V_CTPINCPLFIFOPERR(1U)
15563 #define S_CTPINTCPOPFIFOPERR 3
15564 #define V_CTPINTCPOPFIFOPERR(x) ((x) << S_CTPINTCPOPFIFOPERR)
15565 #define F_CTPINTCPOPFIFOPERR V_CTPINTCPOPFIFOPERR(1U)
15567 #define S_PDUFBKFIFOPERR 2
15568 #define V_PDUFBKFIFOPERR(x) ((x) << S_PDUFBKFIFOPERR)
15569 #define F_PDUFBKFIFOPERR V_PDUFBKFIFOPERR(1U)
15571 #define S_CMOPEXTFIFOPERR 1
15572 #define V_CMOPEXTFIFOPERR(x) ((x) << S_CMOPEXTFIFOPERR)
15573 #define F_CMOPEXTFIFOPERR V_CMOPEXTFIFOPERR(1U)
15575 #define S_DELINVFIFOPERR 0
15576 #define V_DELINVFIFOPERR(x) ((x) << S_DELINVFIFOPERR)
15577 #define F_DELINVFIFOPERR V_DELINVFIFOPERR(1U)
15579 #define S_CTPOUTPLDFIFOPERR 7
15580 #define V_CTPOUTPLDFIFOPERR(x) ((x) << S_CTPOUTPLDFIFOPERR)
15581 #define F_CTPOUTPLDFIFOPERR V_CTPOUTPLDFIFOPERR(1U)
15583 #define A_TP_INT_CAUSE 0x7e74
15584 #define A_TP_PER_ENABLE 0x7e78
15585 #define A_TP_FLM_FREE_PS_CNT 0x7e80
15587 #define S_FREEPSTRUCTCOUNT 0
15588 #define M_FREEPSTRUCTCOUNT 0x1fffffU
15589 #define V_FREEPSTRUCTCOUNT(x) ((x) << S_FREEPSTRUCTCOUNT)
15590 #define G_FREEPSTRUCTCOUNT(x) (((x) >> S_FREEPSTRUCTCOUNT) & M_FREEPSTRUCTCOUNT)
15592 #define A_TP_FLM_FREE_RX_CNT 0x7e84
15594 #define S_FREERXPAGECHN 28
15595 #define V_FREERXPAGECHN(x) ((x) << S_FREERXPAGECHN)
15596 #define F_FREERXPAGECHN V_FREERXPAGECHN(1U)
15598 #define S_FREERXPAGECOUNT 0
15599 #define M_FREERXPAGECOUNT 0x1fffffU
15600 #define V_FREERXPAGECOUNT(x) ((x) << S_FREERXPAGECOUNT)
15601 #define G_FREERXPAGECOUNT(x) (((x) >> S_FREERXPAGECOUNT) & M_FREERXPAGECOUNT)
15603 #define A_TP_FLM_FREE_TX_CNT 0x7e88
15605 #define S_FREETXPAGECHN 28
15606 #define M_FREETXPAGECHN 0x3U
15607 #define V_FREETXPAGECHN(x) ((x) << S_FREETXPAGECHN)
15608 #define G_FREETXPAGECHN(x) (((x) >> S_FREETXPAGECHN) & M_FREETXPAGECHN)
15610 #define S_FREETXPAGECOUNT 0
15611 #define M_FREETXPAGECOUNT 0x1fffffU
15612 #define V_FREETXPAGECOUNT(x) ((x) << S_FREETXPAGECOUNT)
15613 #define G_FREETXPAGECOUNT(x) (((x) >> S_FREETXPAGECOUNT) & M_FREETXPAGECOUNT)
15615 #define A_TP_TM_HEAP_PUSH_CNT 0x7e8c
15616 #define A_TP_TM_HEAP_POP_CNT 0x7e90
15617 #define A_TP_TM_DACK_PUSH_CNT 0x7e94
15618 #define A_TP_TM_DACK_POP_CNT 0x7e98
15619 #define A_TP_TM_MOD_PUSH_CNT 0x7e9c
15620 #define A_TP_MOD_POP_CNT 0x7ea0
15621 #define A_TP_TIMER_SEPARATOR 0x7ea4
15623 #define S_TIMERSEPARATOR 16
15624 #define M_TIMERSEPARATOR 0xffffU
15625 #define V_TIMERSEPARATOR(x) ((x) << S_TIMERSEPARATOR)
15626 #define G_TIMERSEPARATOR(x) (((x) >> S_TIMERSEPARATOR) & M_TIMERSEPARATOR)
15628 #define S_DISABLETIMEFREEZE 0
15629 #define V_DISABLETIMEFREEZE(x) ((x) << S_DISABLETIMEFREEZE)
15630 #define F_DISABLETIMEFREEZE V_DISABLETIMEFREEZE(1U)
15632 #define A_TP_STAMP_TIME 0x7ea8
15633 #define A_TP_DEBUG_FLAGS 0x7eac
15635 #define S_RXTIMERDACKFIRST 26
15636 #define V_RXTIMERDACKFIRST(x) ((x) << S_RXTIMERDACKFIRST)
15637 #define F_RXTIMERDACKFIRST V_RXTIMERDACKFIRST(1U)
15639 #define S_RXTIMERDACK 25
15640 #define V_RXTIMERDACK(x) ((x) << S_RXTIMERDACK)
15641 #define F_RXTIMERDACK V_RXTIMERDACK(1U)
15643 #define S_RXTIMERHEARTBEAT 24
15644 #define V_RXTIMERHEARTBEAT(x) ((x) << S_RXTIMERHEARTBEAT)
15645 #define F_RXTIMERHEARTBEAT V_RXTIMERHEARTBEAT(1U)
15647 #define S_RXPAWSDROP 23
15648 #define V_RXPAWSDROP(x) ((x) << S_RXPAWSDROP)
15649 #define F_RXPAWSDROP V_RXPAWSDROP(1U)
15651 #define S_RXURGDATADROP 22
15652 #define V_RXURGDATADROP(x) ((x) << S_RXURGDATADROP)
15653 #define F_RXURGDATADROP V_RXURGDATADROP(1U)
15655 #define S_RXFUTUREDATA 21
15656 #define V_RXFUTUREDATA(x) ((x) << S_RXFUTUREDATA)
15657 #define F_RXFUTUREDATA V_RXFUTUREDATA(1U)
15659 #define S_RXRCVRXMDATA 20
15660 #define V_RXRCVRXMDATA(x) ((x) << S_RXRCVRXMDATA)
15661 #define F_RXRCVRXMDATA V_RXRCVRXMDATA(1U)
15663 #define S_RXRCVOOODATAFIN 19
15664 #define V_RXRCVOOODATAFIN(x) ((x) << S_RXRCVOOODATAFIN)
15665 #define F_RXRCVOOODATAFIN V_RXRCVOOODATAFIN(1U)
15667 #define S_RXRCVOOODATA 18
15668 #define V_RXRCVOOODATA(x) ((x) << S_RXRCVOOODATA)
15669 #define F_RXRCVOOODATA V_RXRCVOOODATA(1U)
15671 #define S_RXRCVWNDZERO 17
15672 #define V_RXRCVWNDZERO(x) ((x) << S_RXRCVWNDZERO)
15673 #define F_RXRCVWNDZERO V_RXRCVWNDZERO(1U)
15675 #define S_RXRCVWNDLTMSS 16
15676 #define V_RXRCVWNDLTMSS(x) ((x) << S_RXRCVWNDLTMSS)
15677 #define F_RXRCVWNDLTMSS V_RXRCVWNDLTMSS(1U)
15679 #define S_TXDUPACKINC 11
15680 #define V_TXDUPACKINC(x) ((x) << S_TXDUPACKINC)
15681 #define F_TXDUPACKINC V_TXDUPACKINC(1U)
15683 #define S_TXRXMURG 10
15684 #define V_TXRXMURG(x) ((x) << S_TXRXMURG)
15685 #define F_TXRXMURG V_TXRXMURG(1U)
15687 #define S_TXRXMFIN 9
15688 #define V_TXRXMFIN(x) ((x) << S_TXRXMFIN)
15689 #define F_TXRXMFIN V_TXRXMFIN(1U)
15691 #define S_TXRXMSYN 8
15692 #define V_TXRXMSYN(x) ((x) << S_TXRXMSYN)
15693 #define F_TXRXMSYN V_TXRXMSYN(1U)
15695 #define S_TXRXMNEWRENO 7
15696 #define V_TXRXMNEWRENO(x) ((x) << S_TXRXMNEWRENO)
15697 #define F_TXRXMNEWRENO V_TXRXMNEWRENO(1U)
15699 #define S_TXRXMFAST 6
15700 #define V_TXRXMFAST(x) ((x) << S_TXRXMFAST)
15701 #define F_TXRXMFAST V_TXRXMFAST(1U)
15703 #define S_TXRXMTIMER 5
15704 #define V_TXRXMTIMER(x) ((x) << S_TXRXMTIMER)
15705 #define F_TXRXMTIMER V_TXRXMTIMER(1U)
15707 #define S_TXRXMTIMERKEEPALIVE 4
15708 #define V_TXRXMTIMERKEEPALIVE(x) ((x) << S_TXRXMTIMERKEEPALIVE)
15709 #define F_TXRXMTIMERKEEPALIVE V_TXRXMTIMERKEEPALIVE(1U)
15711 #define S_TXRXMTIMERPERSIST 3
15712 #define V_TXRXMTIMERPERSIST(x) ((x) << S_TXRXMTIMERPERSIST)
15713 #define F_TXRXMTIMERPERSIST V_TXRXMTIMERPERSIST(1U)
15715 #define S_TXRCVADVSHRUNK 2
15716 #define V_TXRCVADVSHRUNK(x) ((x) << S_TXRCVADVSHRUNK)
15717 #define F_TXRCVADVSHRUNK V_TXRCVADVSHRUNK(1U)
15719 #define S_TXRCVADVZERO 1
15720 #define V_TXRCVADVZERO(x) ((x) << S_TXRCVADVZERO)
15721 #define F_TXRCVADVZERO V_TXRCVADVZERO(1U)
15723 #define S_TXRCVADVLTMSS 0
15724 #define V_TXRCVADVLTMSS(x) ((x) << S_TXRCVADVLTMSS)
15725 #define F_TXRCVADVLTMSS V_TXRCVADVLTMSS(1U)
15727 #define S_RXTIMERCOMPBUFFER 27
15728 #define V_RXTIMERCOMPBUFFER(x) ((x) << S_RXTIMERCOMPBUFFER)
15729 #define F_RXTIMERCOMPBUFFER V_RXTIMERCOMPBUFFER(1U)
15731 #define S_TXDFRFAST 13
15732 #define V_TXDFRFAST(x) ((x) << S_TXDFRFAST)
15733 #define F_TXDFRFAST V_TXDFRFAST(1U)
15735 #define S_TXRXMMISC 12
15736 #define V_TXRXMMISC(x) ((x) << S_TXRXMMISC)
15737 #define F_TXRXMMISC V_TXRXMMISC(1U)
15739 #define A_TP_RX_SCHED 0x7eb0
15741 #define S_RXCOMMITRESET1 31
15742 #define V_RXCOMMITRESET1(x) ((x) << S_RXCOMMITRESET1)
15743 #define F_RXCOMMITRESET1 V_RXCOMMITRESET1(1U)
15745 #define S_RXCOMMITRESET0 30
15746 #define V_RXCOMMITRESET0(x) ((x) << S_RXCOMMITRESET0)
15747 #define F_RXCOMMITRESET0 V_RXCOMMITRESET0(1U)
15749 #define S_RXFORCECONG1 29
15750 #define V_RXFORCECONG1(x) ((x) << S_RXFORCECONG1)
15751 #define F_RXFORCECONG1 V_RXFORCECONG1(1U)
15753 #define S_RXFORCECONG0 28
15754 #define V_RXFORCECONG0(x) ((x) << S_RXFORCECONG0)
15755 #define F_RXFORCECONG0 V_RXFORCECONG0(1U)
15757 #define S_ENABLELPBKFULL1 26
15758 #define M_ENABLELPBKFULL1 0x3U
15759 #define V_ENABLELPBKFULL1(x) ((x) << S_ENABLELPBKFULL1)
15760 #define G_ENABLELPBKFULL1(x) (((x) >> S_ENABLELPBKFULL1) & M_ENABLELPBKFULL1)
15762 #define S_ENABLELPBKFULL0 24
15763 #define M_ENABLELPBKFULL0 0x3U
15764 #define V_ENABLELPBKFULL0(x) ((x) << S_ENABLELPBKFULL0)
15765 #define G_ENABLELPBKFULL0(x) (((x) >> S_ENABLELPBKFULL0) & M_ENABLELPBKFULL0)
15767 #define S_ENABLEFIFOFULL1 22
15768 #define M_ENABLEFIFOFULL1 0x3U
15769 #define V_ENABLEFIFOFULL1(x) ((x) << S_ENABLEFIFOFULL1)
15770 #define G_ENABLEFIFOFULL1(x) (((x) >> S_ENABLEFIFOFULL1) & M_ENABLEFIFOFULL1)
15772 #define S_ENABLEPCMDFULL1 20
15773 #define M_ENABLEPCMDFULL1 0x3U
15774 #define V_ENABLEPCMDFULL1(x) ((x) << S_ENABLEPCMDFULL1)
15775 #define G_ENABLEPCMDFULL1(x) (((x) >> S_ENABLEPCMDFULL1) & M_ENABLEPCMDFULL1)
15777 #define S_ENABLEHDRFULL1 18
15778 #define M_ENABLEHDRFULL1 0x3U
15779 #define V_ENABLEHDRFULL1(x) ((x) << S_ENABLEHDRFULL1)
15780 #define G_ENABLEHDRFULL1(x) (((x) >> S_ENABLEHDRFULL1) & M_ENABLEHDRFULL1)
15782 #define S_ENABLEFIFOFULL0 16
15783 #define M_ENABLEFIFOFULL0 0x3U
15784 #define V_ENABLEFIFOFULL0(x) ((x) << S_ENABLEFIFOFULL0)
15785 #define G_ENABLEFIFOFULL0(x) (((x) >> S_ENABLEFIFOFULL0) & M_ENABLEFIFOFULL0)
15787 #define S_ENABLEPCMDFULL0 14
15788 #define M_ENABLEPCMDFULL0 0x3U
15789 #define V_ENABLEPCMDFULL0(x) ((x) << S_ENABLEPCMDFULL0)
15790 #define G_ENABLEPCMDFULL0(x) (((x) >> S_ENABLEPCMDFULL0) & M_ENABLEPCMDFULL0)
15792 #define S_ENABLEHDRFULL0 12
15793 #define M_ENABLEHDRFULL0 0x3U
15794 #define V_ENABLEHDRFULL0(x) ((x) << S_ENABLEHDRFULL0)
15795 #define G_ENABLEHDRFULL0(x) (((x) >> S_ENABLEHDRFULL0) & M_ENABLEHDRFULL0)
15797 #define S_COMMITLIMIT1 6
15798 #define M_COMMITLIMIT1 0x3fU
15799 #define V_COMMITLIMIT1(x) ((x) << S_COMMITLIMIT1)
15800 #define G_COMMITLIMIT1(x) (((x) >> S_COMMITLIMIT1) & M_COMMITLIMIT1)
15802 #define S_COMMITLIMIT0 0
15803 #define M_COMMITLIMIT0 0x3fU
15804 #define V_COMMITLIMIT0(x) ((x) << S_COMMITLIMIT0)
15805 #define G_COMMITLIMIT0(x) (((x) >> S_COMMITLIMIT0) & M_COMMITLIMIT0)
15807 #define A_TP_TX_SCHED 0x7eb4
15809 #define S_COMMITRESET3 31
15810 #define V_COMMITRESET3(x) ((x) << S_COMMITRESET3)
15811 #define F_COMMITRESET3 V_COMMITRESET3(1U)
15813 #define S_COMMITRESET2 30
15814 #define V_COMMITRESET2(x) ((x) << S_COMMITRESET2)
15815 #define F_COMMITRESET2 V_COMMITRESET2(1U)
15817 #define S_COMMITRESET1 29
15818 #define V_COMMITRESET1(x) ((x) << S_COMMITRESET1)
15819 #define F_COMMITRESET1 V_COMMITRESET1(1U)
15821 #define S_COMMITRESET0 28
15822 #define V_COMMITRESET0(x) ((x) << S_COMMITRESET0)
15823 #define F_COMMITRESET0 V_COMMITRESET0(1U)
15825 #define S_FORCECONG3 27
15826 #define V_FORCECONG3(x) ((x) << S_FORCECONG3)
15827 #define F_FORCECONG3 V_FORCECONG3(1U)
15829 #define S_FORCECONG2 26
15830 #define V_FORCECONG2(x) ((x) << S_FORCECONG2)
15831 #define F_FORCECONG2 V_FORCECONG2(1U)
15833 #define S_FORCECONG1 25
15834 #define V_FORCECONG1(x) ((x) << S_FORCECONG1)
15835 #define F_FORCECONG1 V_FORCECONG1(1U)
15837 #define S_FORCECONG0 24
15838 #define V_FORCECONG0(x) ((x) << S_FORCECONG0)
15839 #define F_FORCECONG0 V_FORCECONG0(1U)
15841 #define S_COMMITLIMIT3 18
15842 #define M_COMMITLIMIT3 0x3fU
15843 #define V_COMMITLIMIT3(x) ((x) << S_COMMITLIMIT3)
15844 #define G_COMMITLIMIT3(x) (((x) >> S_COMMITLIMIT3) & M_COMMITLIMIT3)
15846 #define S_COMMITLIMIT2 12
15847 #define M_COMMITLIMIT2 0x3fU
15848 #define V_COMMITLIMIT2(x) ((x) << S_COMMITLIMIT2)
15849 #define G_COMMITLIMIT2(x) (((x) >> S_COMMITLIMIT2) & M_COMMITLIMIT2)
15851 #define A_TP_FX_SCHED 0x7eb8
15853 #define S_TXCHNXOFF3 19
15854 #define V_TXCHNXOFF3(x) ((x) << S_TXCHNXOFF3)
15855 #define F_TXCHNXOFF3 V_TXCHNXOFF3(1U)
15857 #define S_TXCHNXOFF2 18
15858 #define V_TXCHNXOFF2(x) ((x) << S_TXCHNXOFF2)
15859 #define F_TXCHNXOFF2 V_TXCHNXOFF2(1U)
15861 #define S_TXCHNXOFF1 17
15862 #define V_TXCHNXOFF1(x) ((x) << S_TXCHNXOFF1)
15863 #define F_TXCHNXOFF1 V_TXCHNXOFF1(1U)
15865 #define S_TXCHNXOFF0 16
15866 #define V_TXCHNXOFF0(x) ((x) << S_TXCHNXOFF0)
15867 #define F_TXCHNXOFF0 V_TXCHNXOFF0(1U)
15869 #define S_TXMODXOFF7 15
15870 #define V_TXMODXOFF7(x) ((x) << S_TXMODXOFF7)
15871 #define F_TXMODXOFF7 V_TXMODXOFF7(1U)
15873 #define S_TXMODXOFF6 14
15874 #define V_TXMODXOFF6(x) ((x) << S_TXMODXOFF6)
15875 #define F_TXMODXOFF6 V_TXMODXOFF6(1U)
15877 #define S_TXMODXOFF5 13
15878 #define V_TXMODXOFF5(x) ((x) << S_TXMODXOFF5)
15879 #define F_TXMODXOFF5 V_TXMODXOFF5(1U)
15881 #define S_TXMODXOFF4 12
15882 #define V_TXMODXOFF4(x) ((x) << S_TXMODXOFF4)
15883 #define F_TXMODXOFF4 V_TXMODXOFF4(1U)
15885 #define S_TXMODXOFF3 11
15886 #define V_TXMODXOFF3(x) ((x) << S_TXMODXOFF3)
15887 #define F_TXMODXOFF3 V_TXMODXOFF3(1U)
15889 #define S_TXMODXOFF2 10
15890 #define V_TXMODXOFF2(x) ((x) << S_TXMODXOFF2)
15891 #define F_TXMODXOFF2 V_TXMODXOFF2(1U)
15893 #define S_TXMODXOFF1 9
15894 #define V_TXMODXOFF1(x) ((x) << S_TXMODXOFF1)
15895 #define F_TXMODXOFF1 V_TXMODXOFF1(1U)
15897 #define S_TXMODXOFF0 8
15898 #define V_TXMODXOFF0(x) ((x) << S_TXMODXOFF0)
15899 #define F_TXMODXOFF0 V_TXMODXOFF0(1U)
15901 #define S_RXCHNXOFF3 7
15902 #define V_RXCHNXOFF3(x) ((x) << S_RXCHNXOFF3)
15903 #define F_RXCHNXOFF3 V_RXCHNXOFF3(1U)
15905 #define S_RXCHNXOFF2 6
15906 #define V_RXCHNXOFF2(x) ((x) << S_RXCHNXOFF2)
15907 #define F_RXCHNXOFF2 V_RXCHNXOFF2(1U)
15909 #define S_RXCHNXOFF1 5
15910 #define V_RXCHNXOFF1(x) ((x) << S_RXCHNXOFF1)
15911 #define F_RXCHNXOFF1 V_RXCHNXOFF1(1U)
15913 #define S_RXCHNXOFF0 4
15914 #define V_RXCHNXOFF0(x) ((x) << S_RXCHNXOFF0)
15915 #define F_RXCHNXOFF0 V_RXCHNXOFF0(1U)
15917 #define S_RXMODXOFF1 1
15918 #define V_RXMODXOFF1(x) ((x) << S_RXMODXOFF1)
15919 #define F_RXMODXOFF1 V_RXMODXOFF1(1U)
15921 #define S_RXMODXOFF0 0
15922 #define V_RXMODXOFF0(x) ((x) << S_RXMODXOFF0)
15923 #define F_RXMODXOFF0 V_RXMODXOFF0(1U)
15925 #define A_TP_TX_ORATE 0x7ebc
15927 #define S_OFDRATE3 24
15928 #define M_OFDRATE3 0xffU
15929 #define V_OFDRATE3(x) ((x) << S_OFDRATE3)
15930 #define G_OFDRATE3(x) (((x) >> S_OFDRATE3) & M_OFDRATE3)
15932 #define S_OFDRATE2 16
15933 #define M_OFDRATE2 0xffU
15934 #define V_OFDRATE2(x) ((x) << S_OFDRATE2)
15935 #define G_OFDRATE2(x) (((x) >> S_OFDRATE2) & M_OFDRATE2)
15937 #define S_OFDRATE1 8
15938 #define M_OFDRATE1 0xffU
15939 #define V_OFDRATE1(x) ((x) << S_OFDRATE1)
15940 #define G_OFDRATE1(x) (((x) >> S_OFDRATE1) & M_OFDRATE1)
15942 #define S_OFDRATE0 0
15943 #define M_OFDRATE0 0xffU
15944 #define V_OFDRATE0(x) ((x) << S_OFDRATE0)
15945 #define G_OFDRATE0(x) (((x) >> S_OFDRATE0) & M_OFDRATE0)
15947 #define A_TP_IX_SCHED0 0x7ec0
15948 #define A_TP_IX_SCHED1 0x7ec4
15949 #define A_TP_IX_SCHED2 0x7ec8
15950 #define A_TP_IX_SCHED3 0x7ecc
15951 #define A_TP_TX_TRATE 0x7ed0
15953 #define S_TNLRATE3 24
15954 #define M_TNLRATE3 0xffU
15955 #define V_TNLRATE3(x) ((x) << S_TNLRATE3)
15956 #define G_TNLRATE3(x) (((x) >> S_TNLRATE3) & M_TNLRATE3)
15958 #define S_TNLRATE2 16
15959 #define M_TNLRATE2 0xffU
15960 #define V_TNLRATE2(x) ((x) << S_TNLRATE2)
15961 #define G_TNLRATE2(x) (((x) >> S_TNLRATE2) & M_TNLRATE2)
15963 #define S_TNLRATE1 8
15964 #define M_TNLRATE1 0xffU
15965 #define V_TNLRATE1(x) ((x) << S_TNLRATE1)
15966 #define G_TNLRATE1(x) (((x) >> S_TNLRATE1) & M_TNLRATE1)
15968 #define S_TNLRATE0 0
15969 #define M_TNLRATE0 0xffU
15970 #define V_TNLRATE0(x) ((x) << S_TNLRATE0)
15971 #define G_TNLRATE0(x) (((x) >> S_TNLRATE0) & M_TNLRATE0)
15973 #define A_TP_DBG_LA_CONFIG 0x7ed4
15975 #define S_DBGLAOPCENABLE 24
15976 #define M_DBGLAOPCENABLE 0xffU
15977 #define V_DBGLAOPCENABLE(x) ((x) << S_DBGLAOPCENABLE)
15978 #define G_DBGLAOPCENABLE(x) (((x) >> S_DBGLAOPCENABLE) & M_DBGLAOPCENABLE)
15980 #define S_DBGLAWHLF 23
15981 #define V_DBGLAWHLF(x) ((x) << S_DBGLAWHLF)
15982 #define F_DBGLAWHLF V_DBGLAWHLF(1U)
15984 #define S_DBGLAWPTR 16
15985 #define M_DBGLAWPTR 0x7fU
15986 #define V_DBGLAWPTR(x) ((x) << S_DBGLAWPTR)
15987 #define G_DBGLAWPTR(x) (((x) >> S_DBGLAWPTR) & M_DBGLAWPTR)
15989 #define S_DBGLAMODE 14
15990 #define M_DBGLAMODE 0x3U
15991 #define V_DBGLAMODE(x) ((x) << S_DBGLAMODE)
15992 #define G_DBGLAMODE(x) (((x) >> S_DBGLAMODE) & M_DBGLAMODE)
15994 #define S_DBGLAFATALFREEZE 13
15995 #define V_DBGLAFATALFREEZE(x) ((x) << S_DBGLAFATALFREEZE)
15996 #define F_DBGLAFATALFREEZE V_DBGLAFATALFREEZE(1U)
15998 #define S_DBGLAENABLE 12
15999 #define V_DBGLAENABLE(x) ((x) << S_DBGLAENABLE)
16000 #define F_DBGLAENABLE V_DBGLAENABLE(1U)
16002 #define S_DBGLARPTR 0
16003 #define M_DBGLARPTR 0x7fU
16004 #define V_DBGLARPTR(x) ((x) << S_DBGLARPTR)
16005 #define G_DBGLARPTR(x) (((x) >> S_DBGLARPTR) & M_DBGLARPTR)
16007 #define A_TP_DBG_LA_DATAL 0x7ed8
16008 #define A_TP_DBG_LA_DATAH 0x7edc
16009 #define A_TP_PROTOCOL_CNTRL 0x7ee8
16011 #define S_WRITEENABLE 31
16012 #define V_WRITEENABLE(x) ((x) << S_WRITEENABLE)
16013 #define F_WRITEENABLE V_WRITEENABLE(1U)
16015 #define S_TCAMENABLE 10
16016 #define V_TCAMENABLE(x) ((x) << S_TCAMENABLE)
16017 #define F_TCAMENABLE V_TCAMENABLE(1U)
16019 #define S_BLOCKSELECT 8
16020 #define M_BLOCKSELECT 0x3U
16021 #define V_BLOCKSELECT(x) ((x) << S_BLOCKSELECT)
16022 #define G_BLOCKSELECT(x) (((x) >> S_BLOCKSELECT) & M_BLOCKSELECT)
16024 #define S_LINEADDRESS 1
16025 #define M_LINEADDRESS 0x7fU
16026 #define V_LINEADDRESS(x) ((x) << S_LINEADDRESS)
16027 #define G_LINEADDRESS(x) (((x) >> S_LINEADDRESS) & M_LINEADDRESS)
16029 #define S_REQUESTDONE 0
16030 #define V_REQUESTDONE(x) ((x) << S_REQUESTDONE)
16031 #define F_REQUESTDONE V_REQUESTDONE(1U)
16033 #define A_TP_PROTOCOL_DATA0 0x7eec
16034 #define A_TP_PROTOCOL_DATA1 0x7ef0
16035 #define A_TP_PROTOCOL_DATA2 0x7ef4
16036 #define A_TP_PROTOCOL_DATA3 0x7ef8
16037 #define A_TP_PROTOCOL_DATA4 0x7efc
16039 #define S_PROTOCOLDATAFIELD 0
16040 #define M_PROTOCOLDATAFIELD 0xfU
16041 #define V_PROTOCOLDATAFIELD(x) ((x) << S_PROTOCOLDATAFIELD)
16042 #define G_PROTOCOLDATAFIELD(x) (((x) >> S_PROTOCOLDATAFIELD) & M_PROTOCOLDATAFIELD)
16044 #define A_TP_TX_MOD_Q7_Q6_TIMER_SEPARATOR 0x0
16046 #define S_TXTIMERSEPQ7 16
16047 #define M_TXTIMERSEPQ7 0xffffU
16048 #define V_TXTIMERSEPQ7(x) ((x) << S_TXTIMERSEPQ7)
16049 #define G_TXTIMERSEPQ7(x) (((x) >> S_TXTIMERSEPQ7) & M_TXTIMERSEPQ7)
16051 #define S_TXTIMERSEPQ6 0
16052 #define M_TXTIMERSEPQ6 0xffffU
16053 #define V_TXTIMERSEPQ6(x) ((x) << S_TXTIMERSEPQ6)
16054 #define G_TXTIMERSEPQ6(x) (((x) >> S_TXTIMERSEPQ6) & M_TXTIMERSEPQ6)
16056 #define A_TP_TX_MOD_Q5_Q4_TIMER_SEPARATOR 0x1
16058 #define S_TXTIMERSEPQ5 16
16059 #define M_TXTIMERSEPQ5 0xffffU
16060 #define V_TXTIMERSEPQ5(x) ((x) << S_TXTIMERSEPQ5)
16061 #define G_TXTIMERSEPQ5(x) (((x) >> S_TXTIMERSEPQ5) & M_TXTIMERSEPQ5)
16063 #define S_TXTIMERSEPQ4 0
16064 #define M_TXTIMERSEPQ4 0xffffU
16065 #define V_TXTIMERSEPQ4(x) ((x) << S_TXTIMERSEPQ4)
16066 #define G_TXTIMERSEPQ4(x) (((x) >> S_TXTIMERSEPQ4) & M_TXTIMERSEPQ4)
16068 #define A_TP_TX_MOD_Q3_Q2_TIMER_SEPARATOR 0x2
16070 #define S_TXTIMERSEPQ3 16
16071 #define M_TXTIMERSEPQ3 0xffffU
16072 #define V_TXTIMERSEPQ3(x) ((x) << S_TXTIMERSEPQ3)
16073 #define G_TXTIMERSEPQ3(x) (((x) >> S_TXTIMERSEPQ3) & M_TXTIMERSEPQ3)
16075 #define S_TXTIMERSEPQ2 0
16076 #define M_TXTIMERSEPQ2 0xffffU
16077 #define V_TXTIMERSEPQ2(x) ((x) << S_TXTIMERSEPQ2)
16078 #define G_TXTIMERSEPQ2(x) (((x) >> S_TXTIMERSEPQ2) & M_TXTIMERSEPQ2)
16080 #define A_TP_TX_MOD_Q1_Q0_TIMER_SEPARATOR 0x3
16082 #define S_TXTIMERSEPQ1 16
16083 #define M_TXTIMERSEPQ1 0xffffU
16084 #define V_TXTIMERSEPQ1(x) ((x) << S_TXTIMERSEPQ1)
16085 #define G_TXTIMERSEPQ1(x) (((x) >> S_TXTIMERSEPQ1) & M_TXTIMERSEPQ1)
16087 #define S_TXTIMERSEPQ0 0
16088 #define M_TXTIMERSEPQ0 0xffffU
16089 #define V_TXTIMERSEPQ0(x) ((x) << S_TXTIMERSEPQ0)
16090 #define G_TXTIMERSEPQ0(x) (((x) >> S_TXTIMERSEPQ0) & M_TXTIMERSEPQ0)
16092 #define A_TP_RX_MOD_Q1_Q0_TIMER_SEPARATOR 0x4
16094 #define S_RXTIMERSEPQ1 16
16095 #define M_RXTIMERSEPQ1 0xffffU
16096 #define V_RXTIMERSEPQ1(x) ((x) << S_RXTIMERSEPQ1)
16097 #define G_RXTIMERSEPQ1(x) (((x) >> S_RXTIMERSEPQ1) & M_RXTIMERSEPQ1)
16099 #define S_RXTIMERSEPQ0 0
16100 #define M_RXTIMERSEPQ0 0xffffU
16101 #define V_RXTIMERSEPQ0(x) ((x) << S_RXTIMERSEPQ0)
16102 #define G_RXTIMERSEPQ0(x) (((x) >> S_RXTIMERSEPQ0) & M_RXTIMERSEPQ0)
16104 #define A_TP_TX_MOD_Q7_Q6_RATE_LIMIT 0x5
16106 #define S_TXRATEINCQ7 24
16107 #define M_TXRATEINCQ7 0xffU
16108 #define V_TXRATEINCQ7(x) ((x) << S_TXRATEINCQ7)
16109 #define G_TXRATEINCQ7(x) (((x) >> S_TXRATEINCQ7) & M_TXRATEINCQ7)
16111 #define S_TXRATETCKQ7 16
16112 #define M_TXRATETCKQ7 0xffU
16113 #define V_TXRATETCKQ7(x) ((x) << S_TXRATETCKQ7)
16114 #define G_TXRATETCKQ7(x) (((x) >> S_TXRATETCKQ7) & M_TXRATETCKQ7)
16116 #define S_TXRATEINCQ6 8
16117 #define M_TXRATEINCQ6 0xffU
16118 #define V_TXRATEINCQ6(x) ((x) << S_TXRATEINCQ6)
16119 #define G_TXRATEINCQ6(x) (((x) >> S_TXRATEINCQ6) & M_TXRATEINCQ6)
16121 #define S_TXRATETCKQ6 0
16122 #define M_TXRATETCKQ6 0xffU
16123 #define V_TXRATETCKQ6(x) ((x) << S_TXRATETCKQ6)
16124 #define G_TXRATETCKQ6(x) (((x) >> S_TXRATETCKQ6) & M_TXRATETCKQ6)
16126 #define A_TP_TX_MOD_Q5_Q4_RATE_LIMIT 0x6
16128 #define S_TXRATEINCQ5 24
16129 #define M_TXRATEINCQ5 0xffU
16130 #define V_TXRATEINCQ5(x) ((x) << S_TXRATEINCQ5)
16131 #define G_TXRATEINCQ5(x) (((x) >> S_TXRATEINCQ5) & M_TXRATEINCQ5)
16133 #define S_TXRATETCKQ5 16
16134 #define M_TXRATETCKQ5 0xffU
16135 #define V_TXRATETCKQ5(x) ((x) << S_TXRATETCKQ5)
16136 #define G_TXRATETCKQ5(x) (((x) >> S_TXRATETCKQ5) & M_TXRATETCKQ5)
16138 #define S_TXRATEINCQ4 8
16139 #define M_TXRATEINCQ4 0xffU
16140 #define V_TXRATEINCQ4(x) ((x) << S_TXRATEINCQ4)
16141 #define G_TXRATEINCQ4(x) (((x) >> S_TXRATEINCQ4) & M_TXRATEINCQ4)
16143 #define S_TXRATETCKQ4 0
16144 #define M_TXRATETCKQ4 0xffU
16145 #define V_TXRATETCKQ4(x) ((x) << S_TXRATETCKQ4)
16146 #define G_TXRATETCKQ4(x) (((x) >> S_TXRATETCKQ4) & M_TXRATETCKQ4)
16148 #define A_TP_TX_MOD_Q3_Q2_RATE_LIMIT 0x7
16150 #define S_TXRATEINCQ3 24
16151 #define M_TXRATEINCQ3 0xffU
16152 #define V_TXRATEINCQ3(x) ((x) << S_TXRATEINCQ3)
16153 #define G_TXRATEINCQ3(x) (((x) >> S_TXRATEINCQ3) & M_TXRATEINCQ3)
16155 #define S_TXRATETCKQ3 16
16156 #define M_TXRATETCKQ3 0xffU
16157 #define V_TXRATETCKQ3(x) ((x) << S_TXRATETCKQ3)
16158 #define G_TXRATETCKQ3(x) (((x) >> S_TXRATETCKQ3) & M_TXRATETCKQ3)
16160 #define S_TXRATEINCQ2 8
16161 #define M_TXRATEINCQ2 0xffU
16162 #define V_TXRATEINCQ2(x) ((x) << S_TXRATEINCQ2)
16163 #define G_TXRATEINCQ2(x) (((x) >> S_TXRATEINCQ2) & M_TXRATEINCQ2)
16165 #define S_TXRATETCKQ2 0
16166 #define M_TXRATETCKQ2 0xffU
16167 #define V_TXRATETCKQ2(x) ((x) << S_TXRATETCKQ2)
16168 #define G_TXRATETCKQ2(x) (((x) >> S_TXRATETCKQ2) & M_TXRATETCKQ2)
16170 #define A_TP_TX_MOD_Q1_Q0_RATE_LIMIT 0x8
16172 #define S_TXRATEINCQ1 24
16173 #define M_TXRATEINCQ1 0xffU
16174 #define V_TXRATEINCQ1(x) ((x) << S_TXRATEINCQ1)
16175 #define G_TXRATEINCQ1(x) (((x) >> S_TXRATEINCQ1) & M_TXRATEINCQ1)
16177 #define S_TXRATETCKQ1 16
16178 #define M_TXRATETCKQ1 0xffU
16179 #define V_TXRATETCKQ1(x) ((x) << S_TXRATETCKQ1)
16180 #define G_TXRATETCKQ1(x) (((x) >> S_TXRATETCKQ1) & M_TXRATETCKQ1)
16182 #define S_TXRATEINCQ0 8
16183 #define M_TXRATEINCQ0 0xffU
16184 #define V_TXRATEINCQ0(x) ((x) << S_TXRATEINCQ0)
16185 #define G_TXRATEINCQ0(x) (((x) >> S_TXRATEINCQ0) & M_TXRATEINCQ0)
16187 #define S_TXRATETCKQ0 0
16188 #define M_TXRATETCKQ0 0xffU
16189 #define V_TXRATETCKQ0(x) ((x) << S_TXRATETCKQ0)
16190 #define G_TXRATETCKQ0(x) (((x) >> S_TXRATETCKQ0) & M_TXRATETCKQ0)
16192 #define A_TP_RX_MOD_Q1_Q0_RATE_LIMIT 0x9
16194 #define S_RXRATEINCQ1 24
16195 #define M_RXRATEINCQ1 0xffU
16196 #define V_RXRATEINCQ1(x) ((x) << S_RXRATEINCQ1)
16197 #define G_RXRATEINCQ1(x) (((x) >> S_RXRATEINCQ1) & M_RXRATEINCQ1)
16199 #define S_RXRATETCKQ1 16
16200 #define M_RXRATETCKQ1 0xffU
16201 #define V_RXRATETCKQ1(x) ((x) << S_RXRATETCKQ1)
16202 #define G_RXRATETCKQ1(x) (((x) >> S_RXRATETCKQ1) & M_RXRATETCKQ1)
16204 #define S_RXRATEINCQ0 8
16205 #define M_RXRATEINCQ0 0xffU
16206 #define V_RXRATEINCQ0(x) ((x) << S_RXRATEINCQ0)
16207 #define G_RXRATEINCQ0(x) (((x) >> S_RXRATEINCQ0) & M_RXRATEINCQ0)
16209 #define S_RXRATETCKQ0 0
16210 #define M_RXRATETCKQ0 0xffU
16211 #define V_RXRATETCKQ0(x) ((x) << S_RXRATETCKQ0)
16212 #define G_RXRATETCKQ0(x) (((x) >> S_RXRATETCKQ0) & M_RXRATETCKQ0)
16214 #define A_TP_TX_MOD_C3_C2_RATE_LIMIT 0xa
16215 #define A_TP_TX_MOD_C1_C0_RATE_LIMIT 0xb
16216 #define A_TP_RX_SCHED_MAP 0x20
16218 #define S_RXMAPCHANNEL3 24
16219 #define M_RXMAPCHANNEL3 0xffU
16220 #define V_RXMAPCHANNEL3(x) ((x) << S_RXMAPCHANNEL3)
16221 #define G_RXMAPCHANNEL3(x) (((x) >> S_RXMAPCHANNEL3) & M_RXMAPCHANNEL3)
16223 #define S_RXMAPCHANNEL2 16
16224 #define M_RXMAPCHANNEL2 0xffU
16225 #define V_RXMAPCHANNEL2(x) ((x) << S_RXMAPCHANNEL2)
16226 #define G_RXMAPCHANNEL2(x) (((x) >> S_RXMAPCHANNEL2) & M_RXMAPCHANNEL2)
16228 #define S_RXMAPCHANNEL1 8
16229 #define M_RXMAPCHANNEL1 0xffU
16230 #define V_RXMAPCHANNEL1(x) ((x) << S_RXMAPCHANNEL1)
16231 #define G_RXMAPCHANNEL1(x) (((x) >> S_RXMAPCHANNEL1) & M_RXMAPCHANNEL1)
16233 #define S_RXMAPCHANNEL0 0
16234 #define M_RXMAPCHANNEL0 0xffU
16235 #define V_RXMAPCHANNEL0(x) ((x) << S_RXMAPCHANNEL0)
16236 #define G_RXMAPCHANNEL0(x) (((x) >> S_RXMAPCHANNEL0) & M_RXMAPCHANNEL0)
16238 #define A_TP_RX_SCHED_SGE 0x21
16240 #define S_RXSGEMOD1 12
16241 #define M_RXSGEMOD1 0xfU
16242 #define V_RXSGEMOD1(x) ((x) << S_RXSGEMOD1)
16243 #define G_RXSGEMOD1(x) (((x) >> S_RXSGEMOD1) & M_RXSGEMOD1)
16245 #define S_RXSGEMOD0 8
16246 #define M_RXSGEMOD0 0xfU
16247 #define V_RXSGEMOD0(x) ((x) << S_RXSGEMOD0)
16248 #define G_RXSGEMOD0(x) (((x) >> S_RXSGEMOD0) & M_RXSGEMOD0)
16250 #define S_RXSGECHANNEL3 3
16251 #define V_RXSGECHANNEL3(x) ((x) << S_RXSGECHANNEL3)
16252 #define F_RXSGECHANNEL3 V_RXSGECHANNEL3(1U)
16254 #define S_RXSGECHANNEL2 2
16255 #define V_RXSGECHANNEL2(x) ((x) << S_RXSGECHANNEL2)
16256 #define F_RXSGECHANNEL2 V_RXSGECHANNEL2(1U)
16258 #define S_RXSGECHANNEL1 1
16259 #define V_RXSGECHANNEL1(x) ((x) << S_RXSGECHANNEL1)
16260 #define F_RXSGECHANNEL1 V_RXSGECHANNEL1(1U)
16262 #define S_RXSGECHANNEL0 0
16263 #define V_RXSGECHANNEL0(x) ((x) << S_RXSGECHANNEL0)
16264 #define F_RXSGECHANNEL0 V_RXSGECHANNEL0(1U)
16266 #define A_TP_TX_SCHED_MAP 0x22
16268 #define S_TXMAPCHANNEL3 12
16269 #define M_TXMAPCHANNEL3 0xfU
16270 #define V_TXMAPCHANNEL3(x) ((x) << S_TXMAPCHANNEL3)
16271 #define G_TXMAPCHANNEL3(x) (((x) >> S_TXMAPCHANNEL3) & M_TXMAPCHANNEL3)
16273 #define S_TXMAPCHANNEL2 8
16274 #define M_TXMAPCHANNEL2 0xfU
16275 #define V_TXMAPCHANNEL2(x) ((x) << S_TXMAPCHANNEL2)
16276 #define G_TXMAPCHANNEL2(x) (((x) >> S_TXMAPCHANNEL2) & M_TXMAPCHANNEL2)
16278 #define S_TXMAPCHANNEL1 4
16279 #define M_TXMAPCHANNEL1 0xfU
16280 #define V_TXMAPCHANNEL1(x) ((x) << S_TXMAPCHANNEL1)
16281 #define G_TXMAPCHANNEL1(x) (((x) >> S_TXMAPCHANNEL1) & M_TXMAPCHANNEL1)
16283 #define S_TXMAPCHANNEL0 0
16284 #define M_TXMAPCHANNEL0 0xfU
16285 #define V_TXMAPCHANNEL0(x) ((x) << S_TXMAPCHANNEL0)
16286 #define G_TXMAPCHANNEL0(x) (((x) >> S_TXMAPCHANNEL0) & M_TXMAPCHANNEL0)
16288 #define A_TP_TX_SCHED_HDR 0x23
16290 #define S_TXMAPHDRCHANNEL7 28
16291 #define M_TXMAPHDRCHANNEL7 0xfU
16292 #define V_TXMAPHDRCHANNEL7(x) ((x) << S_TXMAPHDRCHANNEL7)
16293 #define G_TXMAPHDRCHANNEL7(x) (((x) >> S_TXMAPHDRCHANNEL7) & M_TXMAPHDRCHANNEL7)
16295 #define S_TXMAPHDRCHANNEL6 24
16296 #define M_TXMAPHDRCHANNEL6 0xfU
16297 #define V_TXMAPHDRCHANNEL6(x) ((x) << S_TXMAPHDRCHANNEL6)
16298 #define G_TXMAPHDRCHANNEL6(x) (((x) >> S_TXMAPHDRCHANNEL6) & M_TXMAPHDRCHANNEL6)
16300 #define S_TXMAPHDRCHANNEL5 20
16301 #define M_TXMAPHDRCHANNEL5 0xfU
16302 #define V_TXMAPHDRCHANNEL5(x) ((x) << S_TXMAPHDRCHANNEL5)
16303 #define G_TXMAPHDRCHANNEL5(x) (((x) >> S_TXMAPHDRCHANNEL5) & M_TXMAPHDRCHANNEL5)
16305 #define S_TXMAPHDRCHANNEL4 16
16306 #define M_TXMAPHDRCHANNEL4 0xfU
16307 #define V_TXMAPHDRCHANNEL4(x) ((x) << S_TXMAPHDRCHANNEL4)
16308 #define G_TXMAPHDRCHANNEL4(x) (((x) >> S_TXMAPHDRCHANNEL4) & M_TXMAPHDRCHANNEL4)
16310 #define S_TXMAPHDRCHANNEL3 12
16311 #define M_TXMAPHDRCHANNEL3 0xfU
16312 #define V_TXMAPHDRCHANNEL3(x) ((x) << S_TXMAPHDRCHANNEL3)
16313 #define G_TXMAPHDRCHANNEL3(x) (((x) >> S_TXMAPHDRCHANNEL3) & M_TXMAPHDRCHANNEL3)
16315 #define S_TXMAPHDRCHANNEL2 8
16316 #define M_TXMAPHDRCHANNEL2 0xfU
16317 #define V_TXMAPHDRCHANNEL2(x) ((x) << S_TXMAPHDRCHANNEL2)
16318 #define G_TXMAPHDRCHANNEL2(x) (((x) >> S_TXMAPHDRCHANNEL2) & M_TXMAPHDRCHANNEL2)
16320 #define S_TXMAPHDRCHANNEL1 4
16321 #define M_TXMAPHDRCHANNEL1 0xfU
16322 #define V_TXMAPHDRCHANNEL1(x) ((x) << S_TXMAPHDRCHANNEL1)
16323 #define G_TXMAPHDRCHANNEL1(x) (((x) >> S_TXMAPHDRCHANNEL1) & M_TXMAPHDRCHANNEL1)
16325 #define S_TXMAPHDRCHANNEL0 0
16326 #define M_TXMAPHDRCHANNEL0 0xfU
16327 #define V_TXMAPHDRCHANNEL0(x) ((x) << S_TXMAPHDRCHANNEL0)
16328 #define G_TXMAPHDRCHANNEL0(x) (((x) >> S_TXMAPHDRCHANNEL0) & M_TXMAPHDRCHANNEL0)
16330 #define A_TP_TX_SCHED_FIFO 0x24
16332 #define S_TXMAPFIFOCHANNEL7 28
16333 #define M_TXMAPFIFOCHANNEL7 0xfU
16334 #define V_TXMAPFIFOCHANNEL7(x) ((x) << S_TXMAPFIFOCHANNEL7)
16335 #define G_TXMAPFIFOCHANNEL7(x) (((x) >> S_TXMAPFIFOCHANNEL7) & M_TXMAPFIFOCHANNEL7)
16337 #define S_TXMAPFIFOCHANNEL6 24
16338 #define M_TXMAPFIFOCHANNEL6 0xfU
16339 #define V_TXMAPFIFOCHANNEL6(x) ((x) << S_TXMAPFIFOCHANNEL6)
16340 #define G_TXMAPFIFOCHANNEL6(x) (((x) >> S_TXMAPFIFOCHANNEL6) & M_TXMAPFIFOCHANNEL6)
16342 #define S_TXMAPFIFOCHANNEL5 20
16343 #define M_TXMAPFIFOCHANNEL5 0xfU
16344 #define V_TXMAPFIFOCHANNEL5(x) ((x) << S_TXMAPFIFOCHANNEL5)
16345 #define G_TXMAPFIFOCHANNEL5(x) (((x) >> S_TXMAPFIFOCHANNEL5) & M_TXMAPFIFOCHANNEL5)
16347 #define S_TXMAPFIFOCHANNEL4 16
16348 #define M_TXMAPFIFOCHANNEL4 0xfU
16349 #define V_TXMAPFIFOCHANNEL4(x) ((x) << S_TXMAPFIFOCHANNEL4)
16350 #define G_TXMAPFIFOCHANNEL4(x) (((x) >> S_TXMAPFIFOCHANNEL4) & M_TXMAPFIFOCHANNEL4)
16352 #define S_TXMAPFIFOCHANNEL3 12
16353 #define M_TXMAPFIFOCHANNEL3 0xfU
16354 #define V_TXMAPFIFOCHANNEL3(x) ((x) << S_TXMAPFIFOCHANNEL3)
16355 #define G_TXMAPFIFOCHANNEL3(x) (((x) >> S_TXMAPFIFOCHANNEL3) & M_TXMAPFIFOCHANNEL3)
16357 #define S_TXMAPFIFOCHANNEL2 8
16358 #define M_TXMAPFIFOCHANNEL2 0xfU
16359 #define V_TXMAPFIFOCHANNEL2(x) ((x) << S_TXMAPFIFOCHANNEL2)
16360 #define G_TXMAPFIFOCHANNEL2(x) (((x) >> S_TXMAPFIFOCHANNEL2) & M_TXMAPFIFOCHANNEL2)
16362 #define S_TXMAPFIFOCHANNEL1 4
16363 #define M_TXMAPFIFOCHANNEL1 0xfU
16364 #define V_TXMAPFIFOCHANNEL1(x) ((x) << S_TXMAPFIFOCHANNEL1)
16365 #define G_TXMAPFIFOCHANNEL1(x) (((x) >> S_TXMAPFIFOCHANNEL1) & M_TXMAPFIFOCHANNEL1)
16367 #define S_TXMAPFIFOCHANNEL0 0
16368 #define M_TXMAPFIFOCHANNEL0 0xfU
16369 #define V_TXMAPFIFOCHANNEL0(x) ((x) << S_TXMAPFIFOCHANNEL0)
16370 #define G_TXMAPFIFOCHANNEL0(x) (((x) >> S_TXMAPFIFOCHANNEL0) & M_TXMAPFIFOCHANNEL0)
16372 #define A_TP_TX_SCHED_PCMD 0x25
16374 #define S_TXMAPPCMDCHANNEL7 28
16375 #define M_TXMAPPCMDCHANNEL7 0xfU
16376 #define V_TXMAPPCMDCHANNEL7(x) ((x) << S_TXMAPPCMDCHANNEL7)
16377 #define G_TXMAPPCMDCHANNEL7(x) (((x) >> S_TXMAPPCMDCHANNEL7) & M_TXMAPPCMDCHANNEL7)
16379 #define S_TXMAPPCMDCHANNEL6 24
16380 #define M_TXMAPPCMDCHANNEL6 0xfU
16381 #define V_TXMAPPCMDCHANNEL6(x) ((x) << S_TXMAPPCMDCHANNEL6)
16382 #define G_TXMAPPCMDCHANNEL6(x) (((x) >> S_TXMAPPCMDCHANNEL6) & M_TXMAPPCMDCHANNEL6)
16384 #define S_TXMAPPCMDCHANNEL5 20
16385 #define M_TXMAPPCMDCHANNEL5 0xfU
16386 #define V_TXMAPPCMDCHANNEL5(x) ((x) << S_TXMAPPCMDCHANNEL5)
16387 #define G_TXMAPPCMDCHANNEL5(x) (((x) >> S_TXMAPPCMDCHANNEL5) & M_TXMAPPCMDCHANNEL5)
16389 #define S_TXMAPPCMDCHANNEL4 16
16390 #define M_TXMAPPCMDCHANNEL4 0xfU
16391 #define V_TXMAPPCMDCHANNEL4(x) ((x) << S_TXMAPPCMDCHANNEL4)
16392 #define G_TXMAPPCMDCHANNEL4(x) (((x) >> S_TXMAPPCMDCHANNEL4) & M_TXMAPPCMDCHANNEL4)
16394 #define S_TXMAPPCMDCHANNEL3 12
16395 #define M_TXMAPPCMDCHANNEL3 0xfU
16396 #define V_TXMAPPCMDCHANNEL3(x) ((x) << S_TXMAPPCMDCHANNEL3)
16397 #define G_TXMAPPCMDCHANNEL3(x) (((x) >> S_TXMAPPCMDCHANNEL3) & M_TXMAPPCMDCHANNEL3)
16399 #define S_TXMAPPCMDCHANNEL2 8
16400 #define M_TXMAPPCMDCHANNEL2 0xfU
16401 #define V_TXMAPPCMDCHANNEL2(x) ((x) << S_TXMAPPCMDCHANNEL2)
16402 #define G_TXMAPPCMDCHANNEL2(x) (((x) >> S_TXMAPPCMDCHANNEL2) & M_TXMAPPCMDCHANNEL2)
16404 #define S_TXMAPPCMDCHANNEL1 4
16405 #define M_TXMAPPCMDCHANNEL1 0xfU
16406 #define V_TXMAPPCMDCHANNEL1(x) ((x) << S_TXMAPPCMDCHANNEL1)
16407 #define G_TXMAPPCMDCHANNEL1(x) (((x) >> S_TXMAPPCMDCHANNEL1) & M_TXMAPPCMDCHANNEL1)
16409 #define S_TXMAPPCMDCHANNEL0 0
16410 #define M_TXMAPPCMDCHANNEL0 0xfU
16411 #define V_TXMAPPCMDCHANNEL0(x) ((x) << S_TXMAPPCMDCHANNEL0)
16412 #define G_TXMAPPCMDCHANNEL0(x) (((x) >> S_TXMAPPCMDCHANNEL0) & M_TXMAPPCMDCHANNEL0)
16414 #define A_TP_TX_SCHED_LPBK 0x26
16416 #define S_TXMAPLPBKCHANNEL7 28
16417 #define M_TXMAPLPBKCHANNEL7 0xfU
16418 #define V_TXMAPLPBKCHANNEL7(x) ((x) << S_TXMAPLPBKCHANNEL7)
16419 #define G_TXMAPLPBKCHANNEL7(x) (((x) >> S_TXMAPLPBKCHANNEL7) & M_TXMAPLPBKCHANNEL7)
16421 #define S_TXMAPLPBKCHANNEL6 24
16422 #define M_TXMAPLPBKCHANNEL6 0xfU
16423 #define V_TXMAPLPBKCHANNEL6(x) ((x) << S_TXMAPLPBKCHANNEL6)
16424 #define G_TXMAPLPBKCHANNEL6(x) (((x) >> S_TXMAPLPBKCHANNEL6) & M_TXMAPLPBKCHANNEL6)
16426 #define S_TXMAPLPBKCHANNEL5 20
16427 #define M_TXMAPLPBKCHANNEL5 0xfU
16428 #define V_TXMAPLPBKCHANNEL5(x) ((x) << S_TXMAPLPBKCHANNEL5)
16429 #define G_TXMAPLPBKCHANNEL5(x) (((x) >> S_TXMAPLPBKCHANNEL5) & M_TXMAPLPBKCHANNEL5)
16431 #define S_TXMAPLPBKCHANNEL4 16
16432 #define M_TXMAPLPBKCHANNEL4 0xfU
16433 #define V_TXMAPLPBKCHANNEL4(x) ((x) << S_TXMAPLPBKCHANNEL4)
16434 #define G_TXMAPLPBKCHANNEL4(x) (((x) >> S_TXMAPLPBKCHANNEL4) & M_TXMAPLPBKCHANNEL4)
16436 #define S_TXMAPLPBKCHANNEL3 12
16437 #define M_TXMAPLPBKCHANNEL3 0xfU
16438 #define V_TXMAPLPBKCHANNEL3(x) ((x) << S_TXMAPLPBKCHANNEL3)
16439 #define G_TXMAPLPBKCHANNEL3(x) (((x) >> S_TXMAPLPBKCHANNEL3) & M_TXMAPLPBKCHANNEL3)
16441 #define S_TXMAPLPBKCHANNEL2 8
16442 #define M_TXMAPLPBKCHANNEL2 0xfU
16443 #define V_TXMAPLPBKCHANNEL2(x) ((x) << S_TXMAPLPBKCHANNEL2)
16444 #define G_TXMAPLPBKCHANNEL2(x) (((x) >> S_TXMAPLPBKCHANNEL2) & M_TXMAPLPBKCHANNEL2)
16446 #define S_TXMAPLPBKCHANNEL1 4
16447 #define M_TXMAPLPBKCHANNEL1 0xfU
16448 #define V_TXMAPLPBKCHANNEL1(x) ((x) << S_TXMAPLPBKCHANNEL1)
16449 #define G_TXMAPLPBKCHANNEL1(x) (((x) >> S_TXMAPLPBKCHANNEL1) & M_TXMAPLPBKCHANNEL1)
16451 #define S_TXMAPLPBKCHANNEL0 0
16452 #define M_TXMAPLPBKCHANNEL0 0xfU
16453 #define V_TXMAPLPBKCHANNEL0(x) ((x) << S_TXMAPLPBKCHANNEL0)
16454 #define G_TXMAPLPBKCHANNEL0(x) (((x) >> S_TXMAPLPBKCHANNEL0) & M_TXMAPLPBKCHANNEL0)
16456 #define A_TP_CHANNEL_MAP 0x27
16458 #define S_RXMAPCHANNELELN 16
16459 #define M_RXMAPCHANNELELN 0xfU
16460 #define V_RXMAPCHANNELELN(x) ((x) << S_RXMAPCHANNELELN)
16461 #define G_RXMAPCHANNELELN(x) (((x) >> S_RXMAPCHANNELELN) & M_RXMAPCHANNELELN)
16463 #define S_RXMAPE2LCHANNEL3 14
16464 #define M_RXMAPE2LCHANNEL3 0x3U
16465 #define V_RXMAPE2LCHANNEL3(x) ((x) << S_RXMAPE2LCHANNEL3)
16466 #define G_RXMAPE2LCHANNEL3(x) (((x) >> S_RXMAPE2LCHANNEL3) & M_RXMAPE2LCHANNEL3)
16468 #define S_RXMAPE2LCHANNEL2 12
16469 #define M_RXMAPE2LCHANNEL2 0x3U
16470 #define V_RXMAPE2LCHANNEL2(x) ((x) << S_RXMAPE2LCHANNEL2)
16471 #define G_RXMAPE2LCHANNEL2(x) (((x) >> S_RXMAPE2LCHANNEL2) & M_RXMAPE2LCHANNEL2)
16473 #define S_RXMAPE2LCHANNEL1 10
16474 #define M_RXMAPE2LCHANNEL1 0x3U
16475 #define V_RXMAPE2LCHANNEL1(x) ((x) << S_RXMAPE2LCHANNEL1)
16476 #define G_RXMAPE2LCHANNEL1(x) (((x) >> S_RXMAPE2LCHANNEL1) & M_RXMAPE2LCHANNEL1)
16478 #define S_RXMAPE2LCHANNEL0 8
16479 #define M_RXMAPE2LCHANNEL0 0x3U
16480 #define V_RXMAPE2LCHANNEL0(x) ((x) << S_RXMAPE2LCHANNEL0)
16481 #define G_RXMAPE2LCHANNEL0(x) (((x) >> S_RXMAPE2LCHANNEL0) & M_RXMAPE2LCHANNEL0)
16483 #define S_RXMAPC2CCHANNEL3 7
16484 #define V_RXMAPC2CCHANNEL3(x) ((x) << S_RXMAPC2CCHANNEL3)
16485 #define F_RXMAPC2CCHANNEL3 V_RXMAPC2CCHANNEL3(1U)
16487 #define S_RXMAPC2CCHANNEL2 6
16488 #define V_RXMAPC2CCHANNEL2(x) ((x) << S_RXMAPC2CCHANNEL2)
16489 #define F_RXMAPC2CCHANNEL2 V_RXMAPC2CCHANNEL2(1U)
16491 #define S_RXMAPC2CCHANNEL1 5
16492 #define V_RXMAPC2CCHANNEL1(x) ((x) << S_RXMAPC2CCHANNEL1)
16493 #define F_RXMAPC2CCHANNEL1 V_RXMAPC2CCHANNEL1(1U)
16495 #define S_RXMAPC2CCHANNEL0 4
16496 #define V_RXMAPC2CCHANNEL0(x) ((x) << S_RXMAPC2CCHANNEL0)
16497 #define F_RXMAPC2CCHANNEL0 V_RXMAPC2CCHANNEL0(1U)
16499 #define S_RXMAPE2CCHANNEL3 3
16500 #define V_RXMAPE2CCHANNEL3(x) ((x) << S_RXMAPE2CCHANNEL3)
16501 #define F_RXMAPE2CCHANNEL3 V_RXMAPE2CCHANNEL3(1U)
16503 #define S_RXMAPE2CCHANNEL2 2
16504 #define V_RXMAPE2CCHANNEL2(x) ((x) << S_RXMAPE2CCHANNEL2)
16505 #define F_RXMAPE2CCHANNEL2 V_RXMAPE2CCHANNEL2(1U)
16507 #define S_RXMAPE2CCHANNEL1 1
16508 #define V_RXMAPE2CCHANNEL1(x) ((x) << S_RXMAPE2CCHANNEL1)
16509 #define F_RXMAPE2CCHANNEL1 V_RXMAPE2CCHANNEL1(1U)
16511 #define S_RXMAPE2CCHANNEL0 0
16512 #define V_RXMAPE2CCHANNEL0(x) ((x) << S_RXMAPE2CCHANNEL0)
16513 #define F_RXMAPE2CCHANNEL0 V_RXMAPE2CCHANNEL0(1U)
16515 #define A_TP_RX_LPBK 0x28
16516 #define A_TP_TX_LPBK 0x29
16517 #define A_TP_TX_SCHED_PPP 0x2a
16519 #define S_TXPPPENPORT3 24
16520 #define M_TXPPPENPORT3 0xffU
16521 #define V_TXPPPENPORT3(x) ((x) << S_TXPPPENPORT3)
16522 #define G_TXPPPENPORT3(x) (((x) >> S_TXPPPENPORT3) & M_TXPPPENPORT3)
16524 #define S_TXPPPENPORT2 16
16525 #define M_TXPPPENPORT2 0xffU
16526 #define V_TXPPPENPORT2(x) ((x) << S_TXPPPENPORT2)
16527 #define G_TXPPPENPORT2(x) (((x) >> S_TXPPPENPORT2) & M_TXPPPENPORT2)
16529 #define S_TXPPPENPORT1 8
16530 #define M_TXPPPENPORT1 0xffU
16531 #define V_TXPPPENPORT1(x) ((x) << S_TXPPPENPORT1)
16532 #define G_TXPPPENPORT1(x) (((x) >> S_TXPPPENPORT1) & M_TXPPPENPORT1)
16534 #define S_TXPPPENPORT0 0
16535 #define M_TXPPPENPORT0 0xffU
16536 #define V_TXPPPENPORT0(x) ((x) << S_TXPPPENPORT0)
16537 #define G_TXPPPENPORT0(x) (((x) >> S_TXPPPENPORT0) & M_TXPPPENPORT0)
16539 #define A_TP_RX_SCHED_FIFO 0x2b
16541 #define S_COMMITLIMIT1H 24
16542 #define M_COMMITLIMIT1H 0xffU
16543 #define V_COMMITLIMIT1H(x) ((x) << S_COMMITLIMIT1H)
16544 #define G_COMMITLIMIT1H(x) (((x) >> S_COMMITLIMIT1H) & M_COMMITLIMIT1H)
16546 #define S_COMMITLIMIT1L 16
16547 #define M_COMMITLIMIT1L 0xffU
16548 #define V_COMMITLIMIT1L(x) ((x) << S_COMMITLIMIT1L)
16549 #define G_COMMITLIMIT1L(x) (((x) >> S_COMMITLIMIT1L) & M_COMMITLIMIT1L)
16551 #define S_COMMITLIMIT0H 8
16552 #define M_COMMITLIMIT0H 0xffU
16553 #define V_COMMITLIMIT0H(x) ((x) << S_COMMITLIMIT0H)
16554 #define G_COMMITLIMIT0H(x) (((x) >> S_COMMITLIMIT0H) & M_COMMITLIMIT0H)
16556 #define S_COMMITLIMIT0L 0
16557 #define M_COMMITLIMIT0L 0xffU
16558 #define V_COMMITLIMIT0L(x) ((x) << S_COMMITLIMIT0L)
16559 #define G_COMMITLIMIT0L(x) (((x) >> S_COMMITLIMIT0L) & M_COMMITLIMIT0L)
16561 #define A_TP_IPMI_CFG1 0x2e
16563 #define S_VLANENABLE 31
16564 #define V_VLANENABLE(x) ((x) << S_VLANENABLE)
16565 #define F_VLANENABLE V_VLANENABLE(1U)
16567 #define S_PRIMARYPORTENABLE 30
16568 #define V_PRIMARYPORTENABLE(x) ((x) << S_PRIMARYPORTENABLE)
16569 #define F_PRIMARYPORTENABLE V_PRIMARYPORTENABLE(1U)
16571 #define S_SECUREPORTENABLE 29
16572 #define V_SECUREPORTENABLE(x) ((x) << S_SECUREPORTENABLE)
16573 #define F_SECUREPORTENABLE V_SECUREPORTENABLE(1U)
16575 #define S_ARPENABLE 28
16576 #define V_ARPENABLE(x) ((x) << S_ARPENABLE)
16577 #define F_ARPENABLE V_ARPENABLE(1U)
16579 #define S_IPMI_VLAN 0
16580 #define M_IPMI_VLAN 0xffffU
16581 #define V_IPMI_VLAN(x) ((x) << S_IPMI_VLAN)
16582 #define G_IPMI_VLAN(x) (((x) >> S_IPMI_VLAN) & M_IPMI_VLAN)
16584 #define A_TP_IPMI_CFG2 0x2f
16586 #define S_SECUREPORT 16
16587 #define M_SECUREPORT 0xffffU
16588 #define V_SECUREPORT(x) ((x) << S_SECUREPORT)
16589 #define G_SECUREPORT(x) (((x) >> S_SECUREPORT) & M_SECUREPORT)
16591 #define S_PRIMARYPORT 0
16592 #define M_PRIMARYPORT 0xffffU
16593 #define V_PRIMARYPORT(x) ((x) << S_PRIMARYPORT)
16594 #define G_PRIMARYPORT(x) (((x) >> S_PRIMARYPORT) & M_PRIMARYPORT)
16596 #define A_TP_RSS_PF0_CONFIG 0x30
16598 #define S_MAPENABLE 31
16599 #define V_MAPENABLE(x) ((x) << S_MAPENABLE)
16600 #define F_MAPENABLE V_MAPENABLE(1U)
16602 #define S_CHNENABLE 30
16603 #define V_CHNENABLE(x) ((x) << S_CHNENABLE)
16604 #define F_CHNENABLE V_CHNENABLE(1U)
16606 #define S_PRTENABLE 29
16607 #define V_PRTENABLE(x) ((x) << S_PRTENABLE)
16608 #define F_PRTENABLE V_PRTENABLE(1U)
16610 #define S_UDPFOURTUPEN 28
16611 #define V_UDPFOURTUPEN(x) ((x) << S_UDPFOURTUPEN)
16612 #define F_UDPFOURTUPEN V_UDPFOURTUPEN(1U)
16614 #define S_IP6FOURTUPEN 27
16615 #define V_IP6FOURTUPEN(x) ((x) << S_IP6FOURTUPEN)
16616 #define F_IP6FOURTUPEN V_IP6FOURTUPEN(1U)
16618 #define S_IP6TWOTUPEN 26
16619 #define V_IP6TWOTUPEN(x) ((x) << S_IP6TWOTUPEN)
16620 #define F_IP6TWOTUPEN V_IP6TWOTUPEN(1U)
16622 #define S_IP4FOURTUPEN 25
16623 #define V_IP4FOURTUPEN(x) ((x) << S_IP4FOURTUPEN)
16624 #define F_IP4FOURTUPEN V_IP4FOURTUPEN(1U)
16626 #define S_IP4TWOTUPEN 24
16627 #define V_IP4TWOTUPEN(x) ((x) << S_IP4TWOTUPEN)
16628 #define F_IP4TWOTUPEN V_IP4TWOTUPEN(1U)
16630 #define S_IVFWIDTH 20
16631 #define M_IVFWIDTH 0xfU
16632 #define V_IVFWIDTH(x) ((x) << S_IVFWIDTH)
16633 #define G_IVFWIDTH(x) (((x) >> S_IVFWIDTH) & M_IVFWIDTH)
16635 #define S_CH1DEFAULTQUEUE 10
16636 #define M_CH1DEFAULTQUEUE 0x3ffU
16637 #define V_CH1DEFAULTQUEUE(x) ((x) << S_CH1DEFAULTQUEUE)
16638 #define G_CH1DEFAULTQUEUE(x) (((x) >> S_CH1DEFAULTQUEUE) & M_CH1DEFAULTQUEUE)
16640 #define S_CH0DEFAULTQUEUE 0
16641 #define M_CH0DEFAULTQUEUE 0x3ffU
16642 #define V_CH0DEFAULTQUEUE(x) ((x) << S_CH0DEFAULTQUEUE)
16643 #define G_CH0DEFAULTQUEUE(x) (((x) >> S_CH0DEFAULTQUEUE) & M_CH0DEFAULTQUEUE)
16645 #define A_TP_RSS_PF1_CONFIG 0x31
16646 #define A_TP_RSS_PF2_CONFIG 0x32
16647 #define A_TP_RSS_PF3_CONFIG 0x33
16648 #define A_TP_RSS_PF4_CONFIG 0x34
16649 #define A_TP_RSS_PF5_CONFIG 0x35
16650 #define A_TP_RSS_PF6_CONFIG 0x36
16651 #define A_TP_RSS_PF7_CONFIG 0x37
16652 #define A_TP_RSS_PF_MAP 0x38
16654 #define S_LKPIDXSIZE 24
16655 #define M_LKPIDXSIZE 0x3U
16656 #define V_LKPIDXSIZE(x) ((x) << S_LKPIDXSIZE)
16657 #define G_LKPIDXSIZE(x) (((x) >> S_LKPIDXSIZE) & M_LKPIDXSIZE)
16659 #define S_PF7LKPIDX 21
16660 #define M_PF7LKPIDX 0x7U
16661 #define V_PF7LKPIDX(x) ((x) << S_PF7LKPIDX)
16662 #define G_PF7LKPIDX(x) (((x) >> S_PF7LKPIDX) & M_PF7LKPIDX)
16664 #define S_PF6LKPIDX 18
16665 #define M_PF6LKPIDX 0x7U
16666 #define V_PF6LKPIDX(x) ((x) << S_PF6LKPIDX)
16667 #define G_PF6LKPIDX(x) (((x) >> S_PF6LKPIDX) & M_PF6LKPIDX)
16669 #define S_PF5LKPIDX 15
16670 #define M_PF5LKPIDX 0x7U
16671 #define V_PF5LKPIDX(x) ((x) << S_PF5LKPIDX)
16672 #define G_PF5LKPIDX(x) (((x) >> S_PF5LKPIDX) & M_PF5LKPIDX)
16674 #define S_PF4LKPIDX 12
16675 #define M_PF4LKPIDX 0x7U
16676 #define V_PF4LKPIDX(x) ((x) << S_PF4LKPIDX)
16677 #define G_PF4LKPIDX(x) (((x) >> S_PF4LKPIDX) & M_PF4LKPIDX)
16679 #define S_PF3LKPIDX 9
16680 #define M_PF3LKPIDX 0x7U
16681 #define V_PF3LKPIDX(x) ((x) << S_PF3LKPIDX)
16682 #define G_PF3LKPIDX(x) (((x) >> S_PF3LKPIDX) & M_PF3LKPIDX)
16684 #define S_PF2LKPIDX 6
16685 #define M_PF2LKPIDX 0x7U
16686 #define V_PF2LKPIDX(x) ((x) << S_PF2LKPIDX)
16687 #define G_PF2LKPIDX(x) (((x) >> S_PF2LKPIDX) & M_PF2LKPIDX)
16689 #define S_PF1LKPIDX 3
16690 #define M_PF1LKPIDX 0x7U
16691 #define V_PF1LKPIDX(x) ((x) << S_PF1LKPIDX)
16692 #define G_PF1LKPIDX(x) (((x) >> S_PF1LKPIDX) & M_PF1LKPIDX)
16694 #define S_PF0LKPIDX 0
16695 #define M_PF0LKPIDX 0x7U
16696 #define V_PF0LKPIDX(x) ((x) << S_PF0LKPIDX)
16697 #define G_PF0LKPIDX(x) (((x) >> S_PF0LKPIDX) & M_PF0LKPIDX)
16699 #define A_TP_RSS_PF_MSK 0x39
16701 #define S_PF7MSKSIZE 28
16702 #define M_PF7MSKSIZE 0xfU
16703 #define V_PF7MSKSIZE(x) ((x) << S_PF7MSKSIZE)
16704 #define G_PF7MSKSIZE(x) (((x) >> S_PF7MSKSIZE) & M_PF7MSKSIZE)
16706 #define S_PF6MSKSIZE 24
16707 #define M_PF6MSKSIZE 0xfU
16708 #define V_PF6MSKSIZE(x) ((x) << S_PF6MSKSIZE)
16709 #define G_PF6MSKSIZE(x) (((x) >> S_PF6MSKSIZE) & M_PF6MSKSIZE)
16711 #define S_PF5MSKSIZE 20
16712 #define M_PF5MSKSIZE 0xfU
16713 #define V_PF5MSKSIZE(x) ((x) << S_PF5MSKSIZE)
16714 #define G_PF5MSKSIZE(x) (((x) >> S_PF5MSKSIZE) & M_PF5MSKSIZE)
16716 #define S_PF4MSKSIZE 16
16717 #define M_PF4MSKSIZE 0xfU
16718 #define V_PF4MSKSIZE(x) ((x) << S_PF4MSKSIZE)
16719 #define G_PF4MSKSIZE(x) (((x) >> S_PF4MSKSIZE) & M_PF4MSKSIZE)
16721 #define S_PF3MSKSIZE 12
16722 #define M_PF3MSKSIZE 0xfU
16723 #define V_PF3MSKSIZE(x) ((x) << S_PF3MSKSIZE)
16724 #define G_PF3MSKSIZE(x) (((x) >> S_PF3MSKSIZE) & M_PF3MSKSIZE)
16726 #define S_PF2MSKSIZE 8
16727 #define M_PF2MSKSIZE 0xfU
16728 #define V_PF2MSKSIZE(x) ((x) << S_PF2MSKSIZE)
16729 #define G_PF2MSKSIZE(x) (((x) >> S_PF2MSKSIZE) & M_PF2MSKSIZE)
16731 #define S_PF1MSKSIZE 4
16732 #define M_PF1MSKSIZE 0xfU
16733 #define V_PF1MSKSIZE(x) ((x) << S_PF1MSKSIZE)
16734 #define G_PF1MSKSIZE(x) (((x) >> S_PF1MSKSIZE) & M_PF1MSKSIZE)
16736 #define S_PF0MSKSIZE 0
16737 #define M_PF0MSKSIZE 0xfU
16738 #define V_PF0MSKSIZE(x) ((x) << S_PF0MSKSIZE)
16739 #define G_PF0MSKSIZE(x) (((x) >> S_PF0MSKSIZE) & M_PF0MSKSIZE)
16741 #define A_TP_RSS_VFL_CONFIG 0x3a
16742 #define A_TP_RSS_VFH_CONFIG 0x3b
16744 #define S_ENABLEUDPHASH 31
16745 #define V_ENABLEUDPHASH(x) ((x) << S_ENABLEUDPHASH)
16746 #define F_ENABLEUDPHASH V_ENABLEUDPHASH(1U)
16748 #define S_VFUPEN 30
16749 #define V_VFUPEN(x) ((x) << S_VFUPEN)
16750 #define F_VFUPEN V_VFUPEN(1U)
16752 #define S_VFVLNEX 28
16753 #define V_VFVLNEX(x) ((x) << S_VFVLNEX)
16754 #define F_VFVLNEX V_VFVLNEX(1U)
16756 #define S_VFPRTEN 27
16757 #define V_VFPRTEN(x) ((x) << S_VFPRTEN)
16758 #define F_VFPRTEN V_VFPRTEN(1U)
16760 #define S_VFCHNEN 26
16761 #define V_VFCHNEN(x) ((x) << S_VFCHNEN)
16762 #define F_VFCHNEN V_VFCHNEN(1U)
16764 #define S_DEFAULTQUEUE 16
16765 #define M_DEFAULTQUEUE 0x3ffU
16766 #define V_DEFAULTQUEUE(x) ((x) << S_DEFAULTQUEUE)
16767 #define G_DEFAULTQUEUE(x) (((x) >> S_DEFAULTQUEUE) & M_DEFAULTQUEUE)
16769 #define S_VFLKPIDX 8
16770 #define M_VFLKPIDX 0xffU
16771 #define V_VFLKPIDX(x) ((x) << S_VFLKPIDX)
16772 #define G_VFLKPIDX(x) (((x) >> S_VFLKPIDX) & M_VFLKPIDX)
16774 #define S_VFIP6FOURTUPEN 7
16775 #define V_VFIP6FOURTUPEN(x) ((x) << S_VFIP6FOURTUPEN)
16776 #define F_VFIP6FOURTUPEN V_VFIP6FOURTUPEN(1U)
16778 #define S_VFIP6TWOTUPEN 6
16779 #define V_VFIP6TWOTUPEN(x) ((x) << S_VFIP6TWOTUPEN)
16780 #define F_VFIP6TWOTUPEN V_VFIP6TWOTUPEN(1U)
16782 #define S_VFIP4FOURTUPEN 5
16783 #define V_VFIP4FOURTUPEN(x) ((x) << S_VFIP4FOURTUPEN)
16784 #define F_VFIP4FOURTUPEN V_VFIP4FOURTUPEN(1U)
16786 #define S_VFIP4TWOTUPEN 4
16787 #define V_VFIP4TWOTUPEN(x) ((x) << S_VFIP4TWOTUPEN)
16788 #define F_VFIP4TWOTUPEN V_VFIP4TWOTUPEN(1U)
16790 #define S_KEYINDEX 0
16791 #define M_KEYINDEX 0xfU
16792 #define V_KEYINDEX(x) ((x) << S_KEYINDEX)
16793 #define G_KEYINDEX(x) (((x) >> S_KEYINDEX) & M_KEYINDEX)
16795 #define A_TP_RSS_SECRET_KEY0 0x40
16796 #define A_TP_RSS_SECRET_KEY1 0x41
16797 #define A_TP_RSS_SECRET_KEY2 0x42
16798 #define A_TP_RSS_SECRET_KEY3 0x43
16799 #define A_TP_RSS_SECRET_KEY4 0x44
16800 #define A_TP_RSS_SECRET_KEY5 0x45
16801 #define A_TP_RSS_SECRET_KEY6 0x46
16802 #define A_TP_RSS_SECRET_KEY7 0x47
16803 #define A_TP_RSS_SECRET_KEY8 0x48
16804 #define A_TP_RSS_SECRET_KEY9 0x49
16805 #define A_TP_ETHER_TYPE_VL 0x50
16807 #define S_CQFCTYPE 16
16808 #define M_CQFCTYPE 0xffffU
16809 #define V_CQFCTYPE(x) ((x) << S_CQFCTYPE)
16810 #define G_CQFCTYPE(x) (((x) >> S_CQFCTYPE) & M_CQFCTYPE)
16812 #define S_VLANTYPE 0
16813 #define M_VLANTYPE 0xffffU
16814 #define V_VLANTYPE(x) ((x) << S_VLANTYPE)
16815 #define G_VLANTYPE(x) (((x) >> S_VLANTYPE) & M_VLANTYPE)
16817 #define A_TP_ETHER_TYPE_IP 0x51
16819 #define S_IPV6TYPE 16
16820 #define M_IPV6TYPE 0xffffU
16821 #define V_IPV6TYPE(x) ((x) << S_IPV6TYPE)
16822 #define G_IPV6TYPE(x) (((x) >> S_IPV6TYPE) & M_IPV6TYPE)
16824 #define S_IPV4TYPE 0
16825 #define M_IPV4TYPE 0xffffU
16826 #define V_IPV4TYPE(x) ((x) << S_IPV4TYPE)
16827 #define G_IPV4TYPE(x) (((x) >> S_IPV4TYPE) & M_IPV4TYPE)
16829 #define A_TP_ETHER_TYPE_FW 0x52
16831 #define S_ETHTYPE1 16
16832 #define M_ETHTYPE1 0xffffU
16833 #define V_ETHTYPE1(x) ((x) << S_ETHTYPE1)
16834 #define G_ETHTYPE1(x) (((x) >> S_ETHTYPE1) & M_ETHTYPE1)
16836 #define S_ETHTYPE0 0
16837 #define M_ETHTYPE0 0xffffU
16838 #define V_ETHTYPE0(x) ((x) << S_ETHTYPE0)
16839 #define G_ETHTYPE0(x) (((x) >> S_ETHTYPE0) & M_ETHTYPE0)
16841 #define A_TP_CORE_POWER 0x54
16843 #define S_SLEEPRDYVNT 12
16844 #define V_SLEEPRDYVNT(x) ((x) << S_SLEEPRDYVNT)
16845 #define F_SLEEPRDYVNT V_SLEEPRDYVNT(1U)
16847 #define S_SLEEPRDYTBL 11
16848 #define V_SLEEPRDYTBL(x) ((x) << S_SLEEPRDYTBL)
16849 #define F_SLEEPRDYTBL V_SLEEPRDYTBL(1U)
16851 #define S_SLEEPRDYMIB 10
16852 #define V_SLEEPRDYMIB(x) ((x) << S_SLEEPRDYMIB)
16853 #define F_SLEEPRDYMIB V_SLEEPRDYMIB(1U)
16855 #define S_SLEEPRDYARP 9
16856 #define V_SLEEPRDYARP(x) ((x) << S_SLEEPRDYARP)
16857 #define F_SLEEPRDYARP V_SLEEPRDYARP(1U)
16859 #define S_SLEEPRDYRSS 8
16860 #define V_SLEEPRDYRSS(x) ((x) << S_SLEEPRDYRSS)
16861 #define F_SLEEPRDYRSS V_SLEEPRDYRSS(1U)
16863 #define S_SLEEPREQVNT 4
16864 #define V_SLEEPREQVNT(x) ((x) << S_SLEEPREQVNT)
16865 #define F_SLEEPREQVNT V_SLEEPREQVNT(1U)
16867 #define S_SLEEPREQTBL 3
16868 #define V_SLEEPREQTBL(x) ((x) << S_SLEEPREQTBL)
16869 #define F_SLEEPREQTBL V_SLEEPREQTBL(1U)
16871 #define S_SLEEPREQMIB 2
16872 #define V_SLEEPREQMIB(x) ((x) << S_SLEEPREQMIB)
16873 #define F_SLEEPREQMIB V_SLEEPREQMIB(1U)
16875 #define S_SLEEPREQARP 1
16876 #define V_SLEEPREQARP(x) ((x) << S_SLEEPREQARP)
16877 #define F_SLEEPREQARP V_SLEEPREQARP(1U)
16879 #define S_SLEEPREQRSS 0
16880 #define V_SLEEPREQRSS(x) ((x) << S_SLEEPREQRSS)
16881 #define F_SLEEPREQRSS V_SLEEPREQRSS(1U)
16883 #define A_TP_CORE_RDMA 0x55
16885 #define S_IMMEDIATEOP 20
16886 #define M_IMMEDIATEOP 0xfU
16887 #define V_IMMEDIATEOP(x) ((x) << S_IMMEDIATEOP)
16888 #define G_IMMEDIATEOP(x) (((x) >> S_IMMEDIATEOP) & M_IMMEDIATEOP)
16890 #define S_IMMEDIATESE 16
16891 #define M_IMMEDIATESE 0xfU
16892 #define V_IMMEDIATESE(x) ((x) << S_IMMEDIATESE)
16893 #define G_IMMEDIATESE(x) (((x) >> S_IMMEDIATESE) & M_IMMEDIATESE)
16895 #define S_ATOMICREQOP 12
16896 #define M_ATOMICREQOP 0xfU
16897 #define V_ATOMICREQOP(x) ((x) << S_ATOMICREQOP)
16898 #define G_ATOMICREQOP(x) (((x) >> S_ATOMICREQOP) & M_ATOMICREQOP)
16900 #define S_ATOMICRSPOP 8
16901 #define M_ATOMICRSPOP 0xfU
16902 #define V_ATOMICRSPOP(x) ((x) << S_ATOMICRSPOP)
16903 #define G_ATOMICRSPOP(x) (((x) >> S_ATOMICRSPOP) & M_ATOMICRSPOP)
16905 #define S_IMMEDIASEEN 1
16906 #define V_IMMEDIASEEN(x) ((x) << S_IMMEDIASEEN)
16907 #define F_IMMEDIASEEN V_IMMEDIASEEN(1U)
16909 #define S_IMMEDIATEEN 0
16910 #define V_IMMEDIATEEN(x) ((x) << S_IMMEDIATEEN)
16911 #define F_IMMEDIATEEN V_IMMEDIATEEN(1U)
16913 #define A_TP_DBG_CLEAR 0x60
16914 #define A_TP_DBG_CORE_HDR0 0x61
16916 #define S_E_TCP_OP_SRDY 16
16917 #define V_E_TCP_OP_SRDY(x) ((x) << S_E_TCP_OP_SRDY)
16918 #define F_E_TCP_OP_SRDY V_E_TCP_OP_SRDY(1U)
16920 #define S_E_PLD_TXZEROP_SRDY 15
16921 #define V_E_PLD_TXZEROP_SRDY(x) ((x) << S_E_PLD_TXZEROP_SRDY)
16922 #define F_E_PLD_TXZEROP_SRDY V_E_PLD_TXZEROP_SRDY(1U)
16924 #define S_E_PLD_RX_SRDY 14
16925 #define V_E_PLD_RX_SRDY(x) ((x) << S_E_PLD_RX_SRDY)
16926 #define F_E_PLD_RX_SRDY V_E_PLD_RX_SRDY(1U)
16928 #define S_E_RX_ERROR_SRDY 13
16929 #define V_E_RX_ERROR_SRDY(x) ((x) << S_E_RX_ERROR_SRDY)
16930 #define F_E_RX_ERROR_SRDY V_E_RX_ERROR_SRDY(1U)
16932 #define S_E_RX_ISS_SRDY 12
16933 #define V_E_RX_ISS_SRDY(x) ((x) << S_E_RX_ISS_SRDY)
16934 #define F_E_RX_ISS_SRDY V_E_RX_ISS_SRDY(1U)
16936 #define S_C_TCP_OP_SRDY 11
16937 #define V_C_TCP_OP_SRDY(x) ((x) << S_C_TCP_OP_SRDY)
16938 #define F_C_TCP_OP_SRDY V_C_TCP_OP_SRDY(1U)
16940 #define S_C_PLD_TXZEROP_SRDY 10
16941 #define V_C_PLD_TXZEROP_SRDY(x) ((x) << S_C_PLD_TXZEROP_SRDY)
16942 #define F_C_PLD_TXZEROP_SRDY V_C_PLD_TXZEROP_SRDY(1U)
16944 #define S_C_PLD_RX_SRDY 9
16945 #define V_C_PLD_RX_SRDY(x) ((x) << S_C_PLD_RX_SRDY)
16946 #define F_C_PLD_RX_SRDY V_C_PLD_RX_SRDY(1U)
16948 #define S_C_RX_ERROR_SRDY 8
16949 #define V_C_RX_ERROR_SRDY(x) ((x) << S_C_RX_ERROR_SRDY)
16950 #define F_C_RX_ERROR_SRDY V_C_RX_ERROR_SRDY(1U)
16952 #define S_C_RX_ISS_SRDY 7
16953 #define V_C_RX_ISS_SRDY(x) ((x) << S_C_RX_ISS_SRDY)
16954 #define F_C_RX_ISS_SRDY V_C_RX_ISS_SRDY(1U)
16956 #define S_E_CPL5_TXVALID 6
16957 #define V_E_CPL5_TXVALID(x) ((x) << S_E_CPL5_TXVALID)
16958 #define F_E_CPL5_TXVALID V_E_CPL5_TXVALID(1U)
16960 #define S_E_ETH_TXVALID 5
16961 #define V_E_ETH_TXVALID(x) ((x) << S_E_ETH_TXVALID)
16962 #define F_E_ETH_TXVALID V_E_ETH_TXVALID(1U)
16964 #define S_E_IP_TXVALID 4
16965 #define V_E_IP_TXVALID(x) ((x) << S_E_IP_TXVALID)
16966 #define F_E_IP_TXVALID V_E_IP_TXVALID(1U)
16968 #define S_E_TCP_TXVALID 3
16969 #define V_E_TCP_TXVALID(x) ((x) << S_E_TCP_TXVALID)
16970 #define F_E_TCP_TXVALID V_E_TCP_TXVALID(1U)
16972 #define S_C_CPL5_RXVALID 2
16973 #define V_C_CPL5_RXVALID(x) ((x) << S_C_CPL5_RXVALID)
16974 #define F_C_CPL5_RXVALID V_C_CPL5_RXVALID(1U)
16976 #define S_C_CPL5_TXVALID 1
16977 #define V_C_CPL5_TXVALID(x) ((x) << S_C_CPL5_TXVALID)
16978 #define F_C_CPL5_TXVALID V_C_CPL5_TXVALID(1U)
16980 #define S_E_TCP_OPT_RXVALID 0
16981 #define V_E_TCP_OPT_RXVALID(x) ((x) << S_E_TCP_OPT_RXVALID)
16982 #define F_E_TCP_OPT_RXVALID V_E_TCP_OPT_RXVALID(1U)
16984 #define A_TP_DBG_CORE_HDR1 0x62
16986 #define S_E_CPL5_TXFULL 6
16987 #define V_E_CPL5_TXFULL(x) ((x) << S_E_CPL5_TXFULL)
16988 #define F_E_CPL5_TXFULL V_E_CPL5_TXFULL(1U)
16990 #define S_E_ETH_TXFULL 5
16991 #define V_E_ETH_TXFULL(x) ((x) << S_E_ETH_TXFULL)
16992 #define F_E_ETH_TXFULL V_E_ETH_TXFULL(1U)
16994 #define S_E_IP_TXFULL 4
16995 #define V_E_IP_TXFULL(x) ((x) << S_E_IP_TXFULL)
16996 #define F_E_IP_TXFULL V_E_IP_TXFULL(1U)
16998 #define S_E_TCP_TXFULL 3
16999 #define V_E_TCP_TXFULL(x) ((x) << S_E_TCP_TXFULL)
17000 #define F_E_TCP_TXFULL V_E_TCP_TXFULL(1U)
17002 #define S_C_CPL5_RXFULL 2
17003 #define V_C_CPL5_RXFULL(x) ((x) << S_C_CPL5_RXFULL)
17004 #define F_C_CPL5_RXFULL V_C_CPL5_RXFULL(1U)
17006 #define S_C_CPL5_TXFULL 1
17007 #define V_C_CPL5_TXFULL(x) ((x) << S_C_CPL5_TXFULL)
17008 #define F_C_CPL5_TXFULL V_C_CPL5_TXFULL(1U)
17010 #define S_E_TCP_OPT_RXFULL 0
17011 #define V_E_TCP_OPT_RXFULL(x) ((x) << S_E_TCP_OPT_RXFULL)
17012 #define F_E_TCP_OPT_RXFULL V_E_TCP_OPT_RXFULL(1U)
17014 #define A_TP_DBG_CORE_FATAL 0x63
17016 #define S_EMSGFATAL 31
17017 #define V_EMSGFATAL(x) ((x) << S_EMSGFATAL)
17018 #define F_EMSGFATAL V_EMSGFATAL(1U)
17020 #define S_CMSGFATAL 30
17021 #define V_CMSGFATAL(x) ((x) << S_CMSGFATAL)
17022 #define F_CMSGFATAL V_CMSGFATAL(1U)
17024 #define S_PAWSFATAL 29
17025 #define V_PAWSFATAL(x) ((x) << S_PAWSFATAL)
17026 #define F_PAWSFATAL V_PAWSFATAL(1U)
17028 #define S_SRAMFATAL 28
17029 #define V_SRAMFATAL(x) ((x) << S_SRAMFATAL)
17030 #define F_SRAMFATAL V_SRAMFATAL(1U)
17032 #define S_CPCMDCONG 24
17033 #define M_CPCMDCONG 0xfU
17034 #define V_CPCMDCONG(x) ((x) << S_CPCMDCONG)
17035 #define G_CPCMDCONG(x) (((x) >> S_CPCMDCONG) & M_CPCMDCONG)
17037 #define S_EPCMDCONG 22
17038 #define M_EPCMDCONG 0x3U
17039 #define V_EPCMDCONG(x) ((x) << S_EPCMDCONG)
17040 #define G_EPCMDCONG(x) (((x) >> S_EPCMDCONG) & M_EPCMDCONG)
17042 #define S_CPCMDLENFATAL 21
17043 #define V_CPCMDLENFATAL(x) ((x) << S_CPCMDLENFATAL)
17044 #define F_CPCMDLENFATAL V_CPCMDLENFATAL(1U)
17046 #define S_EPCMDLENFATAL 20
17047 #define V_EPCMDLENFATAL(x) ((x) << S_EPCMDLENFATAL)
17048 #define F_EPCMDLENFATAL V_EPCMDLENFATAL(1U)
17050 #define S_CPCMDVALID 16
17051 #define M_CPCMDVALID 0xfU
17052 #define V_CPCMDVALID(x) ((x) << S_CPCMDVALID)
17053 #define G_CPCMDVALID(x) (((x) >> S_CPCMDVALID) & M_CPCMDVALID)
17055 #define S_CPCMDAFULL 12
17056 #define M_CPCMDAFULL 0xfU
17057 #define V_CPCMDAFULL(x) ((x) << S_CPCMDAFULL)
17058 #define G_CPCMDAFULL(x) (((x) >> S_CPCMDAFULL) & M_CPCMDAFULL)
17060 #define S_EPCMDVALID 10
17061 #define M_EPCMDVALID 0x3U
17062 #define V_EPCMDVALID(x) ((x) << S_EPCMDVALID)
17063 #define G_EPCMDVALID(x) (((x) >> S_EPCMDVALID) & M_EPCMDVALID)
17065 #define S_EPCMDAFULL 8
17066 #define M_EPCMDAFULL 0x3U
17067 #define V_EPCMDAFULL(x) ((x) << S_EPCMDAFULL)
17068 #define G_EPCMDAFULL(x) (((x) >> S_EPCMDAFULL) & M_EPCMDAFULL)
17070 #define S_CPCMDEOIFATAL 7
17071 #define V_CPCMDEOIFATAL(x) ((x) << S_CPCMDEOIFATAL)
17072 #define F_CPCMDEOIFATAL V_CPCMDEOIFATAL(1U)
17074 #define S_CMDBRQFATAL 4
17075 #define V_CMDBRQFATAL(x) ((x) << S_CMDBRQFATAL)
17076 #define F_CMDBRQFATAL V_CMDBRQFATAL(1U)
17078 #define S_CNONZEROPPOPCNT 2
17079 #define M_CNONZEROPPOPCNT 0x3U
17080 #define V_CNONZEROPPOPCNT(x) ((x) << S_CNONZEROPPOPCNT)
17081 #define G_CNONZEROPPOPCNT(x) (((x) >> S_CNONZEROPPOPCNT) & M_CNONZEROPPOPCNT)
17083 #define S_CPCMDEOICNT 0
17084 #define M_CPCMDEOICNT 0x3U
17085 #define V_CPCMDEOICNT(x) ((x) << S_CPCMDEOICNT)
17086 #define G_CPCMDEOICNT(x) (((x) >> S_CPCMDEOICNT) & M_CPCMDEOICNT)
17088 #define S_CPCMDTTLFATAL 6
17089 #define V_CPCMDTTLFATAL(x) ((x) << S_CPCMDTTLFATAL)
17090 #define F_CPCMDTTLFATAL V_CPCMDTTLFATAL(1U)
17092 #define S_CDATACHNFATAL 5
17093 #define V_CDATACHNFATAL(x) ((x) << S_CDATACHNFATAL)
17094 #define F_CDATACHNFATAL V_CDATACHNFATAL(1U)
17096 #define A_TP_DBG_CORE_OUT 0x64
17098 #define S_CCPLENC 26
17099 #define V_CCPLENC(x) ((x) << S_CCPLENC)
17100 #define F_CCPLENC V_CCPLENC(1U)
17102 #define S_CWRCPLPKT 25
17103 #define V_CWRCPLPKT(x) ((x) << S_CWRCPLPKT)
17104 #define F_CWRCPLPKT V_CWRCPLPKT(1U)
17106 #define S_CWRETHPKT 24
17107 #define V_CWRETHPKT(x) ((x) << S_CWRETHPKT)
17108 #define F_CWRETHPKT V_CWRETHPKT(1U)
17110 #define S_CWRIPPKT 23
17111 #define V_CWRIPPKT(x) ((x) << S_CWRIPPKT)
17112 #define F_CWRIPPKT V_CWRIPPKT(1U)
17114 #define S_CWRTCPPKT 22
17115 #define V_CWRTCPPKT(x) ((x) << S_CWRTCPPKT)
17116 #define F_CWRTCPPKT V_CWRTCPPKT(1U)
17118 #define S_CWRZEROP 21
17119 #define V_CWRZEROP(x) ((x) << S_CWRZEROP)
17120 #define F_CWRZEROP V_CWRZEROP(1U)
17122 #define S_CCPLTXFULL 20
17123 #define V_CCPLTXFULL(x) ((x) << S_CCPLTXFULL)
17124 #define F_CCPLTXFULL V_CCPLTXFULL(1U)
17126 #define S_CETHTXFULL 19
17127 #define V_CETHTXFULL(x) ((x) << S_CETHTXFULL)
17128 #define F_CETHTXFULL V_CETHTXFULL(1U)
17130 #define S_CIPTXFULL 18
17131 #define V_CIPTXFULL(x) ((x) << S_CIPTXFULL)
17132 #define F_CIPTXFULL V_CIPTXFULL(1U)
17134 #define S_CTCPTXFULL 17
17135 #define V_CTCPTXFULL(x) ((x) << S_CTCPTXFULL)
17136 #define F_CTCPTXFULL V_CTCPTXFULL(1U)
17138 #define S_CPLDTXZEROPDRDY 16
17139 #define V_CPLDTXZEROPDRDY(x) ((x) << S_CPLDTXZEROPDRDY)
17140 #define F_CPLDTXZEROPDRDY V_CPLDTXZEROPDRDY(1U)
17142 #define S_ECPLENC 10
17143 #define V_ECPLENC(x) ((x) << S_ECPLENC)
17144 #define F_ECPLENC V_ECPLENC(1U)
17146 #define S_EWRCPLPKT 9
17147 #define V_EWRCPLPKT(x) ((x) << S_EWRCPLPKT)
17148 #define F_EWRCPLPKT V_EWRCPLPKT(1U)
17150 #define S_EWRETHPKT 8
17151 #define V_EWRETHPKT(x) ((x) << S_EWRETHPKT)
17152 #define F_EWRETHPKT V_EWRETHPKT(1U)
17154 #define S_EWRIPPKT 7
17155 #define V_EWRIPPKT(x) ((x) << S_EWRIPPKT)
17156 #define F_EWRIPPKT V_EWRIPPKT(1U)
17158 #define S_EWRTCPPKT 6
17159 #define V_EWRTCPPKT(x) ((x) << S_EWRTCPPKT)
17160 #define F_EWRTCPPKT V_EWRTCPPKT(1U)
17162 #define S_EWRZEROP 5
17163 #define V_EWRZEROP(x) ((x) << S_EWRZEROP)
17164 #define F_EWRZEROP V_EWRZEROP(1U)
17166 #define S_ECPLTXFULL 4
17167 #define V_ECPLTXFULL(x) ((x) << S_ECPLTXFULL)
17168 #define F_ECPLTXFULL V_ECPLTXFULL(1U)
17170 #define S_EETHTXFULL 3
17171 #define V_EETHTXFULL(x) ((x) << S_EETHTXFULL)
17172 #define F_EETHTXFULL V_EETHTXFULL(1U)
17174 #define S_EIPTXFULL 2
17175 #define V_EIPTXFULL(x) ((x) << S_EIPTXFULL)
17176 #define F_EIPTXFULL V_EIPTXFULL(1U)
17178 #define S_ETCPTXFULL 1
17179 #define V_ETCPTXFULL(x) ((x) << S_ETCPTXFULL)
17180 #define F_ETCPTXFULL V_ETCPTXFULL(1U)
17182 #define S_EPLDTXZEROPDRDY 0
17183 #define V_EPLDTXZEROPDRDY(x) ((x) << S_EPLDTXZEROPDRDY)
17184 #define F_EPLDTXZEROPDRDY V_EPLDTXZEROPDRDY(1U)
17186 #define S_CRXBUSYOUT 31
17187 #define V_CRXBUSYOUT(x) ((x) << S_CRXBUSYOUT)
17188 #define F_CRXBUSYOUT V_CRXBUSYOUT(1U)
17190 #define S_CTXBUSYOUT 30
17191 #define V_CTXBUSYOUT(x) ((x) << S_CTXBUSYOUT)
17192 #define F_CTXBUSYOUT V_CTXBUSYOUT(1U)
17194 #define S_CRDCPLPKT 29
17195 #define V_CRDCPLPKT(x) ((x) << S_CRDCPLPKT)
17196 #define F_CRDCPLPKT V_CRDCPLPKT(1U)
17198 #define S_CRDTCPPKT 28
17199 #define V_CRDTCPPKT(x) ((x) << S_CRDTCPPKT)
17200 #define F_CRDTCPPKT V_CRDTCPPKT(1U)
17202 #define S_CNEWMSG 27
17203 #define V_CNEWMSG(x) ((x) << S_CNEWMSG)
17204 #define F_CNEWMSG V_CNEWMSG(1U)
17206 #define S_ERXBUSYOUT 15
17207 #define V_ERXBUSYOUT(x) ((x) << S_ERXBUSYOUT)
17208 #define F_ERXBUSYOUT V_ERXBUSYOUT(1U)
17210 #define S_ETXBUSYOUT 14
17211 #define V_ETXBUSYOUT(x) ((x) << S_ETXBUSYOUT)
17212 #define F_ETXBUSYOUT V_ETXBUSYOUT(1U)
17214 #define S_ERDCPLPKT 13
17215 #define V_ERDCPLPKT(x) ((x) << S_ERDCPLPKT)
17216 #define F_ERDCPLPKT V_ERDCPLPKT(1U)
17218 #define S_ERDTCPPKT 12
17219 #define V_ERDTCPPKT(x) ((x) << S_ERDTCPPKT)
17220 #define F_ERDTCPPKT V_ERDTCPPKT(1U)
17222 #define S_ENEWMSG 11
17223 #define V_ENEWMSG(x) ((x) << S_ENEWMSG)
17224 #define F_ENEWMSG V_ENEWMSG(1U)
17226 #define A_TP_DBG_CORE_TID 0x65
17228 #define S_LINENUMBER 24
17229 #define M_LINENUMBER 0x7fU
17230 #define V_LINENUMBER(x) ((x) << S_LINENUMBER)
17231 #define G_LINENUMBER(x) (((x) >> S_LINENUMBER) & M_LINENUMBER)
17233 #define S_SPURIOUSMSG 23
17234 #define V_SPURIOUSMSG(x) ((x) << S_SPURIOUSMSG)
17235 #define F_SPURIOUSMSG V_SPURIOUSMSG(1U)
17237 #define S_SYNLEARNED 20
17238 #define V_SYNLEARNED(x) ((x) << S_SYNLEARNED)
17239 #define F_SYNLEARNED V_SYNLEARNED(1U)
17241 #define S_TIDVALUE 0
17242 #define M_TIDVALUE 0xfffffU
17243 #define V_TIDVALUE(x) ((x) << S_TIDVALUE)
17244 #define G_TIDVALUE(x) (((x) >> S_TIDVALUE) & M_TIDVALUE)
17248 #define V_SRC(x) ((x) << S_SRC)
17249 #define G_SRC(x) (((x) >> S_SRC) & M_SRC)
17251 #define A_TP_DBG_ENG_RES0 0x66
17253 #define S_RESOURCESREADY 31
17254 #define V_RESOURCESREADY(x) ((x) << S_RESOURCESREADY)
17255 #define F_RESOURCESREADY V_RESOURCESREADY(1U)
17257 #define S_RCFOPCODEOUTSRDY 30
17258 #define V_RCFOPCODEOUTSRDY(x) ((x) << S_RCFOPCODEOUTSRDY)
17259 #define F_RCFOPCODEOUTSRDY V_RCFOPCODEOUTSRDY(1U)
17261 #define S_RCFDATAOUTSRDY 29
17262 #define V_RCFDATAOUTSRDY(x) ((x) << S_RCFDATAOUTSRDY)
17263 #define F_RCFDATAOUTSRDY V_RCFDATAOUTSRDY(1U)
17265 #define S_FLUSHINPUTMSG 28
17266 #define V_FLUSHINPUTMSG(x) ((x) << S_FLUSHINPUTMSG)
17267 #define F_FLUSHINPUTMSG V_FLUSHINPUTMSG(1U)
17269 #define S_RCFOPSRCOUT 26
17270 #define M_RCFOPSRCOUT 0x3U
17271 #define V_RCFOPSRCOUT(x) ((x) << S_RCFOPSRCOUT)
17272 #define G_RCFOPSRCOUT(x) (((x) >> S_RCFOPSRCOUT) & M_RCFOPSRCOUT)
17275 #define V_C_MSG(x) ((x) << S_C_MSG)
17276 #define F_C_MSG V_C_MSG(1U)
17279 #define V_E_MSG(x) ((x) << S_E_MSG)
17280 #define F_E_MSG V_E_MSG(1U)
17282 #define S_RCFOPCODEOUT 20
17283 #define M_RCFOPCODEOUT 0xfU
17284 #define V_RCFOPCODEOUT(x) ((x) << S_RCFOPCODEOUT)
17285 #define G_RCFOPCODEOUT(x) (((x) >> S_RCFOPCODEOUT) & M_RCFOPCODEOUT)
17287 #define S_EFFRCFOPCODEOUT 16
17288 #define M_EFFRCFOPCODEOUT 0xfU
17289 #define V_EFFRCFOPCODEOUT(x) ((x) << S_EFFRCFOPCODEOUT)
17290 #define G_EFFRCFOPCODEOUT(x) (((x) >> S_EFFRCFOPCODEOUT) & M_EFFRCFOPCODEOUT)
17292 #define S_SEENRESOURCESREADY 15
17293 #define V_SEENRESOURCESREADY(x) ((x) << S_SEENRESOURCESREADY)
17294 #define F_SEENRESOURCESREADY V_SEENRESOURCESREADY(1U)
17296 #define S_RESOURCESREADYCOPY 14
17297 #define V_RESOURCESREADYCOPY(x) ((x) << S_RESOURCESREADYCOPY)
17298 #define F_RESOURCESREADYCOPY V_RESOURCESREADYCOPY(1U)
17300 #define S_OPCODEWAITSFORDATA 13
17301 #define V_OPCODEWAITSFORDATA(x) ((x) << S_OPCODEWAITSFORDATA)
17302 #define F_OPCODEWAITSFORDATA V_OPCODEWAITSFORDATA(1U)
17304 #define S_CPLDRXSRDY 12
17305 #define V_CPLDRXSRDY(x) ((x) << S_CPLDRXSRDY)
17306 #define F_CPLDRXSRDY V_CPLDRXSRDY(1U)
17308 #define S_CPLDRXZEROPSRDY 11
17309 #define V_CPLDRXZEROPSRDY(x) ((x) << S_CPLDRXZEROPSRDY)
17310 #define F_CPLDRXZEROPSRDY V_CPLDRXZEROPSRDY(1U)
17312 #define S_EPLDRXZEROPSRDY 10
17313 #define V_EPLDRXZEROPSRDY(x) ((x) << S_EPLDRXZEROPSRDY)
17314 #define F_EPLDRXZEROPSRDY V_EPLDRXZEROPSRDY(1U)
17316 #define S_ERXERRORSRDY 9
17317 #define V_ERXERRORSRDY(x) ((x) << S_ERXERRORSRDY)
17318 #define F_ERXERRORSRDY V_ERXERRORSRDY(1U)
17320 #define S_EPLDRXSRDY 8
17321 #define V_EPLDRXSRDY(x) ((x) << S_EPLDRXSRDY)
17322 #define F_EPLDRXSRDY V_EPLDRXSRDY(1U)
17324 #define S_CRXBUSY 7
17325 #define V_CRXBUSY(x) ((x) << S_CRXBUSY)
17326 #define F_CRXBUSY V_CRXBUSY(1U)
17328 #define S_ERXBUSY 6
17329 #define V_ERXBUSY(x) ((x) << S_ERXBUSY)
17330 #define F_ERXBUSY V_ERXBUSY(1U)
17332 #define S_TIMERINSERTBUSY 5
17333 #define V_TIMERINSERTBUSY(x) ((x) << S_TIMERINSERTBUSY)
17334 #define F_TIMERINSERTBUSY V_TIMERINSERTBUSY(1U)
17336 #define S_WCFBUSY 4
17337 #define V_WCFBUSY(x) ((x) << S_WCFBUSY)
17338 #define F_WCFBUSY V_WCFBUSY(1U)
17340 #define S_CTXBUSY 3
17341 #define V_CTXBUSY(x) ((x) << S_CTXBUSY)
17342 #define F_CTXBUSY V_CTXBUSY(1U)
17344 #define S_CPCMDBUSY 2
17345 #define V_CPCMDBUSY(x) ((x) << S_CPCMDBUSY)
17346 #define F_CPCMDBUSY V_CPCMDBUSY(1U)
17348 #define S_EPCMDBUSY 1
17349 #define V_EPCMDBUSY(x) ((x) << S_EPCMDBUSY)
17350 #define F_EPCMDBUSY V_EPCMDBUSY(1U)
17352 #define S_ETXBUSY 0
17353 #define V_ETXBUSY(x) ((x) << S_ETXBUSY)
17354 #define F_ETXBUSY V_ETXBUSY(1U)
17356 #define S_EFFOPCODEOUT 16
17357 #define M_EFFOPCODEOUT 0xfU
17358 #define V_EFFOPCODEOUT(x) ((x) << S_EFFOPCODEOUT)
17359 #define G_EFFOPCODEOUT(x) (((x) >> S_EFFOPCODEOUT) & M_EFFOPCODEOUT)
17361 #define S_DELDRDY 14
17362 #define V_DELDRDY(x) ((x) << S_DELDRDY)
17363 #define F_DELDRDY V_DELDRDY(1U)
17365 #define A_TP_DBG_ENG_RES1 0x67
17367 #define S_RXCPLSRDY 31
17368 #define V_RXCPLSRDY(x) ((x) << S_RXCPLSRDY)
17369 #define F_RXCPLSRDY V_RXCPLSRDY(1U)
17371 #define S_RXOPTSRDY 30
17372 #define V_RXOPTSRDY(x) ((x) << S_RXOPTSRDY)
17373 #define F_RXOPTSRDY V_RXOPTSRDY(1U)
17375 #define S_RXPLDLENSRDY 29
17376 #define V_RXPLDLENSRDY(x) ((x) << S_RXPLDLENSRDY)
17377 #define F_RXPLDLENSRDY V_RXPLDLENSRDY(1U)
17379 #define S_RXNOTBUSY 28
17380 #define V_RXNOTBUSY(x) ((x) << S_RXNOTBUSY)
17381 #define F_RXNOTBUSY V_RXNOTBUSY(1U)
17383 #define S_CPLCMDIN 20
17384 #define M_CPLCMDIN 0xffU
17385 #define V_CPLCMDIN(x) ((x) << S_CPLCMDIN)
17386 #define G_CPLCMDIN(x) (((x) >> S_CPLCMDIN) & M_CPLCMDIN)
17388 #define S_RCFPTIDSRDY 19
17389 #define V_RCFPTIDSRDY(x) ((x) << S_RCFPTIDSRDY)
17390 #define F_RCFPTIDSRDY V_RCFPTIDSRDY(1U)
17392 #define S_EPDUHDRSRDY 18
17393 #define V_EPDUHDRSRDY(x) ((x) << S_EPDUHDRSRDY)
17394 #define F_EPDUHDRSRDY V_EPDUHDRSRDY(1U)
17396 #define S_TUNNELPKTREG 17
17397 #define V_TUNNELPKTREG(x) ((x) << S_TUNNELPKTREG)
17398 #define F_TUNNELPKTREG V_TUNNELPKTREG(1U)
17400 #define S_TXPKTCSUMSRDY 16
17401 #define V_TXPKTCSUMSRDY(x) ((x) << S_TXPKTCSUMSRDY)
17402 #define F_TXPKTCSUMSRDY V_TXPKTCSUMSRDY(1U)
17404 #define S_TABLEACCESSLATENCY 12
17405 #define M_TABLEACCESSLATENCY 0xfU
17406 #define V_TABLEACCESSLATENCY(x) ((x) << S_TABLEACCESSLATENCY)
17407 #define G_TABLEACCESSLATENCY(x) (((x) >> S_TABLEACCESSLATENCY) & M_TABLEACCESSLATENCY)
17409 #define S_MMGRDONE 11
17410 #define V_MMGRDONE(x) ((x) << S_MMGRDONE)
17411 #define F_MMGRDONE V_MMGRDONE(1U)
17413 #define S_SEENMMGRDONE 10
17414 #define V_SEENMMGRDONE(x) ((x) << S_SEENMMGRDONE)
17415 #define F_SEENMMGRDONE V_SEENMMGRDONE(1U)
17417 #define S_RXERRORSRDY 9
17418 #define V_RXERRORSRDY(x) ((x) << S_RXERRORSRDY)
17419 #define F_RXERRORSRDY V_RXERRORSRDY(1U)
17421 #define S_RCFOPTIONSTCPSRDY 8
17422 #define V_RCFOPTIONSTCPSRDY(x) ((x) << S_RCFOPTIONSTCPSRDY)
17423 #define F_RCFOPTIONSTCPSRDY V_RCFOPTIONSTCPSRDY(1U)
17425 #define S_ENGINESTATE 6
17426 #define M_ENGINESTATE 0x3U
17427 #define V_ENGINESTATE(x) ((x) << S_ENGINESTATE)
17428 #define G_ENGINESTATE(x) (((x) >> S_ENGINESTATE) & M_ENGINESTATE)
17430 #define S_TABLEACCESINCREMENT 5
17431 #define V_TABLEACCESINCREMENT(x) ((x) << S_TABLEACCESINCREMENT)
17432 #define F_TABLEACCESINCREMENT V_TABLEACCESINCREMENT(1U)
17434 #define S_TABLEACCESCOMPLETE 4
17435 #define V_TABLEACCESCOMPLETE(x) ((x) << S_TABLEACCESCOMPLETE)
17436 #define F_TABLEACCESCOMPLETE V_TABLEACCESCOMPLETE(1U)
17438 #define S_RCFOPCODEOUTUSABLE 3
17439 #define V_RCFOPCODEOUTUSABLE(x) ((x) << S_RCFOPCODEOUTUSABLE)
17440 #define F_RCFOPCODEOUTUSABLE V_RCFOPCODEOUTUSABLE(1U)
17442 #define S_RCFDATAOUTUSABLE 2
17443 #define V_RCFDATAOUTUSABLE(x) ((x) << S_RCFDATAOUTUSABLE)
17444 #define F_RCFDATAOUTUSABLE V_RCFDATAOUTUSABLE(1U)
17446 #define S_RCFDATAWAITAFTERRD 1
17447 #define V_RCFDATAWAITAFTERRD(x) ((x) << S_RCFDATAWAITAFTERRD)
17448 #define F_RCFDATAWAITAFTERRD V_RCFDATAWAITAFTERRD(1U)
17450 #define S_RCFDATACMRDY 0
17451 #define V_RCFDATACMRDY(x) ((x) << S_RCFDATACMRDY)
17452 #define F_RCFDATACMRDY V_RCFDATACMRDY(1U)
17454 #define A_TP_DBG_ENG_RES2 0x68
17456 #define S_CPLCMDRAW 24
17457 #define M_CPLCMDRAW 0xffU
17458 #define V_CPLCMDRAW(x) ((x) << S_CPLCMDRAW)
17459 #define G_CPLCMDRAW(x) (((x) >> S_CPLCMDRAW) & M_CPLCMDRAW)
17461 #define S_RXMACPORT 20
17462 #define M_RXMACPORT 0xfU
17463 #define V_RXMACPORT(x) ((x) << S_RXMACPORT)
17464 #define G_RXMACPORT(x) (((x) >> S_RXMACPORT) & M_RXMACPORT)
17466 #define S_TXECHANNEL 18
17467 #define M_TXECHANNEL 0x3U
17468 #define V_TXECHANNEL(x) ((x) << S_TXECHANNEL)
17469 #define G_TXECHANNEL(x) (((x) >> S_TXECHANNEL) & M_TXECHANNEL)
17471 #define S_RXECHANNEL 16
17472 #define M_RXECHANNEL 0x3U
17473 #define V_RXECHANNEL(x) ((x) << S_RXECHANNEL)
17474 #define G_RXECHANNEL(x) (((x) >> S_RXECHANNEL) & M_RXECHANNEL)
17476 #define S_CDATAOUT 15
17477 #define V_CDATAOUT(x) ((x) << S_CDATAOUT)
17478 #define F_CDATAOUT V_CDATAOUT(1U)
17480 #define S_CREADPDU 14
17481 #define V_CREADPDU(x) ((x) << S_CREADPDU)
17482 #define F_CREADPDU V_CREADPDU(1U)
17484 #define S_EDATAOUT 13
17485 #define V_EDATAOUT(x) ((x) << S_EDATAOUT)
17486 #define F_EDATAOUT V_EDATAOUT(1U)
17488 #define S_EREADPDU 12
17489 #define V_EREADPDU(x) ((x) << S_EREADPDU)
17490 #define F_EREADPDU V_EREADPDU(1U)
17492 #define S_ETCPOPSRDY 11
17493 #define V_ETCPOPSRDY(x) ((x) << S_ETCPOPSRDY)
17494 #define F_ETCPOPSRDY V_ETCPOPSRDY(1U)
17496 #define S_CTCPOPSRDY 10
17497 #define V_CTCPOPSRDY(x) ((x) << S_CTCPOPSRDY)
17498 #define F_CTCPOPSRDY V_CTCPOPSRDY(1U)
17500 #define S_CPKTOUT 9
17501 #define V_CPKTOUT(x) ((x) << S_CPKTOUT)
17502 #define F_CPKTOUT V_CPKTOUT(1U)
17504 #define S_CMDBRSPSRDY 8
17505 #define V_CMDBRSPSRDY(x) ((x) << S_CMDBRSPSRDY)
17506 #define F_CMDBRSPSRDY V_CMDBRSPSRDY(1U)
17508 #define S_RXPSTRUCTSFULL 6
17509 #define M_RXPSTRUCTSFULL 0x3U
17510 #define V_RXPSTRUCTSFULL(x) ((x) << S_RXPSTRUCTSFULL)
17511 #define G_RXPSTRUCTSFULL(x) (((x) >> S_RXPSTRUCTSFULL) & M_RXPSTRUCTSFULL)
17513 #define S_RXPAGEPOOLFULL 4
17514 #define M_RXPAGEPOOLFULL 0x3U
17515 #define V_RXPAGEPOOLFULL(x) ((x) << S_RXPAGEPOOLFULL)
17516 #define G_RXPAGEPOOLFULL(x) (((x) >> S_RXPAGEPOOLFULL) & M_RXPAGEPOOLFULL)
17518 #define S_RCFREASONOUT 0
17519 #define M_RCFREASONOUT 0xfU
17520 #define V_RCFREASONOUT(x) ((x) << S_RCFREASONOUT)
17521 #define G_RCFREASONOUT(x) (((x) >> S_RCFREASONOUT) & M_RCFREASONOUT)
17523 #define A_TP_DBG_CORE_PCMD 0x69
17525 #define S_CPCMDEOPCNT 30
17526 #define M_CPCMDEOPCNT 0x3U
17527 #define V_CPCMDEOPCNT(x) ((x) << S_CPCMDEOPCNT)
17528 #define G_CPCMDEOPCNT(x) (((x) >> S_CPCMDEOPCNT) & M_CPCMDEOPCNT)
17530 #define S_CPCMDLENSAVE 16
17531 #define M_CPCMDLENSAVE 0x3fffU
17532 #define V_CPCMDLENSAVE(x) ((x) << S_CPCMDLENSAVE)
17533 #define G_CPCMDLENSAVE(x) (((x) >> S_CPCMDLENSAVE) & M_CPCMDLENSAVE)
17535 #define S_EPCMDEOPCNT 14
17536 #define M_EPCMDEOPCNT 0x3U
17537 #define V_EPCMDEOPCNT(x) ((x) << S_EPCMDEOPCNT)
17538 #define G_EPCMDEOPCNT(x) (((x) >> S_EPCMDEOPCNT) & M_EPCMDEOPCNT)
17540 #define S_EPCMDLENSAVE 0
17541 #define M_EPCMDLENSAVE 0x3fffU
17542 #define V_EPCMDLENSAVE(x) ((x) << S_EPCMDLENSAVE)
17543 #define G_EPCMDLENSAVE(x) (((x) >> S_EPCMDLENSAVE) & M_EPCMDLENSAVE)
17545 #define A_TP_DBG_SCHED_TX 0x6a
17547 #define S_TXCHNXOFF 28
17548 #define M_TXCHNXOFF 0xfU
17549 #define V_TXCHNXOFF(x) ((x) << S_TXCHNXOFF)
17550 #define G_TXCHNXOFF(x) (((x) >> S_TXCHNXOFF) & M_TXCHNXOFF)
17552 #define S_TXFIFOCNG 24
17553 #define M_TXFIFOCNG 0xfU
17554 #define V_TXFIFOCNG(x) ((x) << S_TXFIFOCNG)
17555 #define G_TXFIFOCNG(x) (((x) >> S_TXFIFOCNG) & M_TXFIFOCNG)
17557 #define S_TXPCMDCNG 20
17558 #define M_TXPCMDCNG 0xfU
17559 #define V_TXPCMDCNG(x) ((x) << S_TXPCMDCNG)
17560 #define G_TXPCMDCNG(x) (((x) >> S_TXPCMDCNG) & M_TXPCMDCNG)
17562 #define S_TXLPBKCNG 16
17563 #define M_TXLPBKCNG 0xfU
17564 #define V_TXLPBKCNG(x) ((x) << S_TXLPBKCNG)
17565 #define G_TXLPBKCNG(x) (((x) >> S_TXLPBKCNG) & M_TXLPBKCNG)
17567 #define S_TXHDRCNG 8
17568 #define M_TXHDRCNG 0xffU
17569 #define V_TXHDRCNG(x) ((x) << S_TXHDRCNG)
17570 #define G_TXHDRCNG(x) (((x) >> S_TXHDRCNG) & M_TXHDRCNG)
17572 #define S_TXMODXOFF 0
17573 #define M_TXMODXOFF 0xffU
17574 #define V_TXMODXOFF(x) ((x) << S_TXMODXOFF)
17575 #define G_TXMODXOFF(x) (((x) >> S_TXMODXOFF) & M_TXMODXOFF)
17577 #define A_TP_DBG_SCHED_RX 0x6b
17579 #define S_RXCHNXOFF 28
17580 #define M_RXCHNXOFF 0xfU
17581 #define V_RXCHNXOFF(x) ((x) << S_RXCHNXOFF)
17582 #define G_RXCHNXOFF(x) (((x) >> S_RXCHNXOFF) & M_RXCHNXOFF)
17584 #define S_RXSGECNG 24
17585 #define M_RXSGECNG 0xfU
17586 #define V_RXSGECNG(x) ((x) << S_RXSGECNG)
17587 #define G_RXSGECNG(x) (((x) >> S_RXSGECNG) & M_RXSGECNG)
17589 #define S_RXFIFOCNG 22
17590 #define M_RXFIFOCNG 0x3U
17591 #define V_RXFIFOCNG(x) ((x) << S_RXFIFOCNG)
17592 #define G_RXFIFOCNG(x) (((x) >> S_RXFIFOCNG) & M_RXFIFOCNG)
17594 #define S_RXPCMDCNG 20
17595 #define M_RXPCMDCNG 0x3U
17596 #define V_RXPCMDCNG(x) ((x) << S_RXPCMDCNG)
17597 #define G_RXPCMDCNG(x) (((x) >> S_RXPCMDCNG) & M_RXPCMDCNG)
17599 #define S_RXLPBKCNG 16
17600 #define M_RXLPBKCNG 0xfU
17601 #define V_RXLPBKCNG(x) ((x) << S_RXLPBKCNG)
17602 #define G_RXLPBKCNG(x) (((x) >> S_RXLPBKCNG) & M_RXLPBKCNG)
17604 #define S_RXHDRCNG 8
17605 #define M_RXHDRCNG 0xfU
17606 #define V_RXHDRCNG(x) ((x) << S_RXHDRCNG)
17607 #define G_RXHDRCNG(x) (((x) >> S_RXHDRCNG) & M_RXHDRCNG)
17609 #define S_RXMODXOFF 0
17610 #define M_RXMODXOFF 0x3U
17611 #define V_RXMODXOFF(x) ((x) << S_RXMODXOFF)
17612 #define G_RXMODXOFF(x) (((x) >> S_RXMODXOFF) & M_RXMODXOFF)
17614 #define A_TP_DBG_ERROR_CNT 0x6c
17615 #define A_TP_MIB_DEBUG 0x6f
17618 #define V_SRC3(x) ((x) << S_SRC3)
17619 #define F_SRC3 V_SRC3(1U)
17621 #define S_LINENUM3 24
17622 #define M_LINENUM3 0x7fU
17623 #define V_LINENUM3(x) ((x) << S_LINENUM3)
17624 #define G_LINENUM3(x) (((x) >> S_LINENUM3) & M_LINENUM3)
17627 #define V_SRC2(x) ((x) << S_SRC2)
17628 #define F_SRC2 V_SRC2(1U)
17630 #define S_LINENUM2 16
17631 #define M_LINENUM2 0x7fU
17632 #define V_LINENUM2(x) ((x) << S_LINENUM2)
17633 #define G_LINENUM2(x) (((x) >> S_LINENUM2) & M_LINENUM2)
17636 #define V_SRC1(x) ((x) << S_SRC1)
17637 #define F_SRC1 V_SRC1(1U)
17639 #define S_LINENUM1 8
17640 #define M_LINENUM1 0x7fU
17641 #define V_LINENUM1(x) ((x) << S_LINENUM1)
17642 #define G_LINENUM1(x) (((x) >> S_LINENUM1) & M_LINENUM1)
17645 #define V_SRC0(x) ((x) << S_SRC0)
17646 #define F_SRC0 V_SRC0(1U)
17648 #define S_LINENUM0 0
17649 #define M_LINENUM0 0x7fU
17650 #define V_LINENUM0(x) ((x) << S_LINENUM0)
17651 #define G_LINENUM0(x) (((x) >> S_LINENUM0) & M_LINENUM0)
17653 #define A_TP_T5_TX_DROP_CNT_CH0 0x120
17654 #define A_TP_T5_TX_DROP_CNT_CH1 0x121
17655 #define A_TP_TX_DROP_CNT_CH2 0x122
17656 #define A_TP_TX_DROP_CNT_CH3 0x123
17657 #define A_TP_TX_DROP_CFG_CH0 0x12b
17659 #define S_TIMERENABLED 31
17660 #define V_TIMERENABLED(x) ((x) << S_TIMERENABLED)
17661 #define F_TIMERENABLED V_TIMERENABLED(1U)
17663 #define S_TIMERERRORENABLE 30
17664 #define V_TIMERERRORENABLE(x) ((x) << S_TIMERERRORENABLE)
17665 #define F_TIMERERRORENABLE V_TIMERERRORENABLE(1U)
17667 #define S_TIMERTHRESHOLD 4
17668 #define M_TIMERTHRESHOLD 0x3ffffffU
17669 #define V_TIMERTHRESHOLD(x) ((x) << S_TIMERTHRESHOLD)
17670 #define G_TIMERTHRESHOLD(x) (((x) >> S_TIMERTHRESHOLD) & M_TIMERTHRESHOLD)
17672 #define S_PACKETDROPS 0
17673 #define M_PACKETDROPS 0xfU
17674 #define V_PACKETDROPS(x) ((x) << S_PACKETDROPS)
17675 #define G_PACKETDROPS(x) (((x) >> S_PACKETDROPS) & M_PACKETDROPS)
17677 #define A_TP_TX_DROP_CFG_CH1 0x12c
17678 #define A_TP_TX_DROP_CNT_CH0 0x12d
17680 #define S_TXDROPCNTCH0SENT 16
17681 #define M_TXDROPCNTCH0SENT 0xffffU
17682 #define V_TXDROPCNTCH0SENT(x) ((x) << S_TXDROPCNTCH0SENT)
17683 #define G_TXDROPCNTCH0SENT(x) (((x) >> S_TXDROPCNTCH0SENT) & M_TXDROPCNTCH0SENT)
17685 #define S_TXDROPCNTCH0RCVD 0
17686 #define M_TXDROPCNTCH0RCVD 0xffffU
17687 #define V_TXDROPCNTCH0RCVD(x) ((x) << S_TXDROPCNTCH0RCVD)
17688 #define G_TXDROPCNTCH0RCVD(x) (((x) >> S_TXDROPCNTCH0RCVD) & M_TXDROPCNTCH0RCVD)
17690 #define A_TP_TX_DROP_CNT_CH1 0x12e
17692 #define S_TXDROPCNTCH1SENT 16
17693 #define M_TXDROPCNTCH1SENT 0xffffU
17694 #define V_TXDROPCNTCH1SENT(x) ((x) << S_TXDROPCNTCH1SENT)
17695 #define G_TXDROPCNTCH1SENT(x) (((x) >> S_TXDROPCNTCH1SENT) & M_TXDROPCNTCH1SENT)
17697 #define S_TXDROPCNTCH1RCVD 0
17698 #define M_TXDROPCNTCH1RCVD 0xffffU
17699 #define V_TXDROPCNTCH1RCVD(x) ((x) << S_TXDROPCNTCH1RCVD)
17700 #define G_TXDROPCNTCH1RCVD(x) (((x) >> S_TXDROPCNTCH1RCVD) & M_TXDROPCNTCH1RCVD)
17702 #define A_TP_TX_DROP_MODE 0x12f
17704 #define S_TXDROPMODECH3 3
17705 #define V_TXDROPMODECH3(x) ((x) << S_TXDROPMODECH3)
17706 #define F_TXDROPMODECH3 V_TXDROPMODECH3(1U)
17708 #define S_TXDROPMODECH2 2
17709 #define V_TXDROPMODECH2(x) ((x) << S_TXDROPMODECH2)
17710 #define F_TXDROPMODECH2 V_TXDROPMODECH2(1U)
17712 #define S_TXDROPMODECH1 1
17713 #define V_TXDROPMODECH1(x) ((x) << S_TXDROPMODECH1)
17714 #define F_TXDROPMODECH1 V_TXDROPMODECH1(1U)
17716 #define S_TXDROPMODECH0 0
17717 #define V_TXDROPMODECH0(x) ((x) << S_TXDROPMODECH0)
17718 #define F_TXDROPMODECH0 V_TXDROPMODECH0(1U)
17720 #define A_TP_DBG_ESIDE_PKT0 0x130
17722 #define S_ETXSOPCNT 28
17723 #define M_ETXSOPCNT 0xfU
17724 #define V_ETXSOPCNT(x) ((x) << S_ETXSOPCNT)
17725 #define G_ETXSOPCNT(x) (((x) >> S_ETXSOPCNT) & M_ETXSOPCNT)
17727 #define S_ETXEOPCNT 24
17728 #define M_ETXEOPCNT 0xfU
17729 #define V_ETXEOPCNT(x) ((x) << S_ETXEOPCNT)
17730 #define G_ETXEOPCNT(x) (((x) >> S_ETXEOPCNT) & M_ETXEOPCNT)
17732 #define S_ETXPLDSOPCNT 20
17733 #define M_ETXPLDSOPCNT 0xfU
17734 #define V_ETXPLDSOPCNT(x) ((x) << S_ETXPLDSOPCNT)
17735 #define G_ETXPLDSOPCNT(x) (((x) >> S_ETXPLDSOPCNT) & M_ETXPLDSOPCNT)
17737 #define S_ETXPLDEOPCNT 16
17738 #define M_ETXPLDEOPCNT 0xfU
17739 #define V_ETXPLDEOPCNT(x) ((x) << S_ETXPLDEOPCNT)
17740 #define G_ETXPLDEOPCNT(x) (((x) >> S_ETXPLDEOPCNT) & M_ETXPLDEOPCNT)
17742 #define S_ERXSOPCNT 12
17743 #define M_ERXSOPCNT 0xfU
17744 #define V_ERXSOPCNT(x) ((x) << S_ERXSOPCNT)
17745 #define G_ERXSOPCNT(x) (((x) >> S_ERXSOPCNT) & M_ERXSOPCNT)
17747 #define S_ERXEOPCNT 8
17748 #define M_ERXEOPCNT 0xfU
17749 #define V_ERXEOPCNT(x) ((x) << S_ERXEOPCNT)
17750 #define G_ERXEOPCNT(x) (((x) >> S_ERXEOPCNT) & M_ERXEOPCNT)
17752 #define S_ERXPLDSOPCNT 4
17753 #define M_ERXPLDSOPCNT 0xfU
17754 #define V_ERXPLDSOPCNT(x) ((x) << S_ERXPLDSOPCNT)
17755 #define G_ERXPLDSOPCNT(x) (((x) >> S_ERXPLDSOPCNT) & M_ERXPLDSOPCNT)
17757 #define S_ERXPLDEOPCNT 0
17758 #define M_ERXPLDEOPCNT 0xfU
17759 #define V_ERXPLDEOPCNT(x) ((x) << S_ERXPLDEOPCNT)
17760 #define G_ERXPLDEOPCNT(x) (((x) >> S_ERXPLDEOPCNT) & M_ERXPLDEOPCNT)
17762 #define A_TP_DBG_ESIDE_PKT1 0x131
17763 #define A_TP_DBG_ESIDE_PKT2 0x132
17764 #define A_TP_DBG_ESIDE_PKT3 0x133
17765 #define A_TP_DBG_ESIDE_FIFO0 0x134
17767 #define S_PLDRXCSUMVALID1 31
17768 #define V_PLDRXCSUMVALID1(x) ((x) << S_PLDRXCSUMVALID1)
17769 #define F_PLDRXCSUMVALID1 V_PLDRXCSUMVALID1(1U)
17771 #define S_PLDRXZEROPSRDY1 30
17772 #define V_PLDRXZEROPSRDY1(x) ((x) << S_PLDRXZEROPSRDY1)
17773 #define F_PLDRXZEROPSRDY1 V_PLDRXZEROPSRDY1(1U)
17775 #define S_PLDRXVALID1 29
17776 #define V_PLDRXVALID1(x) ((x) << S_PLDRXVALID1)
17777 #define F_PLDRXVALID1 V_PLDRXVALID1(1U)
17779 #define S_TCPRXVALID1 28
17780 #define V_TCPRXVALID1(x) ((x) << S_TCPRXVALID1)
17781 #define F_TCPRXVALID1 V_TCPRXVALID1(1U)
17783 #define S_IPRXVALID1 27
17784 #define V_IPRXVALID1(x) ((x) << S_IPRXVALID1)
17785 #define F_IPRXVALID1 V_IPRXVALID1(1U)
17787 #define S_ETHRXVALID1 26
17788 #define V_ETHRXVALID1(x) ((x) << S_ETHRXVALID1)
17789 #define F_ETHRXVALID1 V_ETHRXVALID1(1U)
17791 #define S_CPLRXVALID1 25
17792 #define V_CPLRXVALID1(x) ((x) << S_CPLRXVALID1)
17793 #define F_CPLRXVALID1 V_CPLRXVALID1(1U)
17795 #define S_FSTATIC1 24
17796 #define V_FSTATIC1(x) ((x) << S_FSTATIC1)
17797 #define F_FSTATIC1 V_FSTATIC1(1U)
17799 #define S_ERRORSRDY1 23
17800 #define V_ERRORSRDY1(x) ((x) << S_ERRORSRDY1)
17801 #define F_ERRORSRDY1 V_ERRORSRDY1(1U)
17803 #define S_PLDTXSRDY1 22
17804 #define V_PLDTXSRDY1(x) ((x) << S_PLDTXSRDY1)
17805 #define F_PLDTXSRDY1 V_PLDTXSRDY1(1U)
17807 #define S_DBVLD1 21
17808 #define V_DBVLD1(x) ((x) << S_DBVLD1)
17809 #define F_DBVLD1 V_DBVLD1(1U)
17811 #define S_PLDTXVALID1 20
17812 #define V_PLDTXVALID1(x) ((x) << S_PLDTXVALID1)
17813 #define F_PLDTXVALID1 V_PLDTXVALID1(1U)
17815 #define S_ETXVALID1 19
17816 #define V_ETXVALID1(x) ((x) << S_ETXVALID1)
17817 #define F_ETXVALID1 V_ETXVALID1(1U)
17819 #define S_ETXFULL1 18
17820 #define V_ETXFULL1(x) ((x) << S_ETXFULL1)
17821 #define F_ETXFULL1 V_ETXFULL1(1U)
17823 #define S_ERXVALID1 17
17824 #define V_ERXVALID1(x) ((x) << S_ERXVALID1)
17825 #define F_ERXVALID1 V_ERXVALID1(1U)
17827 #define S_ERXFULL1 16
17828 #define V_ERXFULL1(x) ((x) << S_ERXFULL1)
17829 #define F_ERXFULL1 V_ERXFULL1(1U)
17831 #define S_PLDRXCSUMVALID0 15
17832 #define V_PLDRXCSUMVALID0(x) ((x) << S_PLDRXCSUMVALID0)
17833 #define F_PLDRXCSUMVALID0 V_PLDRXCSUMVALID0(1U)
17835 #define S_PLDRXZEROPSRDY0 14
17836 #define V_PLDRXZEROPSRDY0(x) ((x) << S_PLDRXZEROPSRDY0)
17837 #define F_PLDRXZEROPSRDY0 V_PLDRXZEROPSRDY0(1U)
17839 #define S_PLDRXVALID0 13
17840 #define V_PLDRXVALID0(x) ((x) << S_PLDRXVALID0)
17841 #define F_PLDRXVALID0 V_PLDRXVALID0(1U)
17843 #define S_TCPRXVALID0 12
17844 #define V_TCPRXVALID0(x) ((x) << S_TCPRXVALID0)
17845 #define F_TCPRXVALID0 V_TCPRXVALID0(1U)
17847 #define S_IPRXVALID0 11
17848 #define V_IPRXVALID0(x) ((x) << S_IPRXVALID0)
17849 #define F_IPRXVALID0 V_IPRXVALID0(1U)
17851 #define S_ETHRXVALID0 10
17852 #define V_ETHRXVALID0(x) ((x) << S_ETHRXVALID0)
17853 #define F_ETHRXVALID0 V_ETHRXVALID0(1U)
17855 #define S_CPLRXVALID0 9
17856 #define V_CPLRXVALID0(x) ((x) << S_CPLRXVALID0)
17857 #define F_CPLRXVALID0 V_CPLRXVALID0(1U)
17859 #define S_FSTATIC0 8
17860 #define V_FSTATIC0(x) ((x) << S_FSTATIC0)
17861 #define F_FSTATIC0 V_FSTATIC0(1U)
17863 #define S_ERRORSRDY0 7
17864 #define V_ERRORSRDY0(x) ((x) << S_ERRORSRDY0)
17865 #define F_ERRORSRDY0 V_ERRORSRDY0(1U)
17867 #define S_PLDTXSRDY0 6
17868 #define V_PLDTXSRDY0(x) ((x) << S_PLDTXSRDY0)
17869 #define F_PLDTXSRDY0 V_PLDTXSRDY0(1U)
17872 #define V_DBVLD0(x) ((x) << S_DBVLD0)
17873 #define F_DBVLD0 V_DBVLD0(1U)
17875 #define S_PLDTXVALID0 4
17876 #define V_PLDTXVALID0(x) ((x) << S_PLDTXVALID0)
17877 #define F_PLDTXVALID0 V_PLDTXVALID0(1U)
17879 #define S_ETXVALID0 3
17880 #define V_ETXVALID0(x) ((x) << S_ETXVALID0)
17881 #define F_ETXVALID0 V_ETXVALID0(1U)
17883 #define S_ETXFULL0 2
17884 #define V_ETXFULL0(x) ((x) << S_ETXFULL0)
17885 #define F_ETXFULL0 V_ETXFULL0(1U)
17887 #define S_ERXVALID0 1
17888 #define V_ERXVALID0(x) ((x) << S_ERXVALID0)
17889 #define F_ERXVALID0 V_ERXVALID0(1U)
17891 #define S_ERXFULL0 0
17892 #define V_ERXFULL0(x) ((x) << S_ERXFULL0)
17893 #define F_ERXFULL0 V_ERXFULL0(1U)
17895 #define A_TP_DBG_ESIDE_FIFO1 0x135
17897 #define S_PLDRXCSUMVALID3 31
17898 #define V_PLDRXCSUMVALID3(x) ((x) << S_PLDRXCSUMVALID3)
17899 #define F_PLDRXCSUMVALID3 V_PLDRXCSUMVALID3(1U)
17901 #define S_PLDRXZEROPSRDY3 30
17902 #define V_PLDRXZEROPSRDY3(x) ((x) << S_PLDRXZEROPSRDY3)
17903 #define F_PLDRXZEROPSRDY3 V_PLDRXZEROPSRDY3(1U)
17905 #define S_PLDRXVALID3 29
17906 #define V_PLDRXVALID3(x) ((x) << S_PLDRXVALID3)
17907 #define F_PLDRXVALID3 V_PLDRXVALID3(1U)
17909 #define S_TCPRXVALID3 28
17910 #define V_TCPRXVALID3(x) ((x) << S_TCPRXVALID3)
17911 #define F_TCPRXVALID3 V_TCPRXVALID3(1U)
17913 #define S_IPRXVALID3 27
17914 #define V_IPRXVALID3(x) ((x) << S_IPRXVALID3)
17915 #define F_IPRXVALID3 V_IPRXVALID3(1U)
17917 #define S_ETHRXVALID3 26
17918 #define V_ETHRXVALID3(x) ((x) << S_ETHRXVALID3)
17919 #define F_ETHRXVALID3 V_ETHRXVALID3(1U)
17921 #define S_CPLRXVALID3 25
17922 #define V_CPLRXVALID3(x) ((x) << S_CPLRXVALID3)
17923 #define F_CPLRXVALID3 V_CPLRXVALID3(1U)
17925 #define S_FSTATIC3 24
17926 #define V_FSTATIC3(x) ((x) << S_FSTATIC3)
17927 #define F_FSTATIC3 V_FSTATIC3(1U)
17929 #define S_ERRORSRDY3 23
17930 #define V_ERRORSRDY3(x) ((x) << S_ERRORSRDY3)
17931 #define F_ERRORSRDY3 V_ERRORSRDY3(1U)
17933 #define S_PLDTXSRDY3 22
17934 #define V_PLDTXSRDY3(x) ((x) << S_PLDTXSRDY3)
17935 #define F_PLDTXSRDY3 V_PLDTXSRDY3(1U)
17937 #define S_DBVLD3 21
17938 #define V_DBVLD3(x) ((x) << S_DBVLD3)
17939 #define F_DBVLD3 V_DBVLD3(1U)
17941 #define S_PLDTXVALID3 20
17942 #define V_PLDTXVALID3(x) ((x) << S_PLDTXVALID3)
17943 #define F_PLDTXVALID3 V_PLDTXVALID3(1U)
17945 #define S_ETXVALID3 19
17946 #define V_ETXVALID3(x) ((x) << S_ETXVALID3)
17947 #define F_ETXVALID3 V_ETXVALID3(1U)
17949 #define S_ETXFULL3 18
17950 #define V_ETXFULL3(x) ((x) << S_ETXFULL3)
17951 #define F_ETXFULL3 V_ETXFULL3(1U)
17953 #define S_ERXVALID3 17
17954 #define V_ERXVALID3(x) ((x) << S_ERXVALID3)
17955 #define F_ERXVALID3 V_ERXVALID3(1U)
17957 #define S_ERXFULL3 16
17958 #define V_ERXFULL3(x) ((x) << S_ERXFULL3)
17959 #define F_ERXFULL3 V_ERXFULL3(1U)
17961 #define S_PLDRXCSUMVALID2 15
17962 #define V_PLDRXCSUMVALID2(x) ((x) << S_PLDRXCSUMVALID2)
17963 #define F_PLDRXCSUMVALID2 V_PLDRXCSUMVALID2(1U)
17965 #define S_PLDRXZEROPSRDY2 14
17966 #define V_PLDRXZEROPSRDY2(x) ((x) << S_PLDRXZEROPSRDY2)
17967 #define F_PLDRXZEROPSRDY2 V_PLDRXZEROPSRDY2(1U)
17969 #define S_PLDRXVALID2 13
17970 #define V_PLDRXVALID2(x) ((x) << S_PLDRXVALID2)
17971 #define F_PLDRXVALID2 V_PLDRXVALID2(1U)
17973 #define S_TCPRXVALID2 12
17974 #define V_TCPRXVALID2(x) ((x) << S_TCPRXVALID2)
17975 #define F_TCPRXVALID2 V_TCPRXVALID2(1U)
17977 #define S_IPRXVALID2 11
17978 #define V_IPRXVALID2(x) ((x) << S_IPRXVALID2)
17979 #define F_IPRXVALID2 V_IPRXVALID2(1U)
17981 #define S_ETHRXVALID2 10
17982 #define V_ETHRXVALID2(x) ((x) << S_ETHRXVALID2)
17983 #define F_ETHRXVALID2 V_ETHRXVALID2(1U)
17985 #define S_CPLRXVALID2 9
17986 #define V_CPLRXVALID2(x) ((x) << S_CPLRXVALID2)
17987 #define F_CPLRXVALID2 V_CPLRXVALID2(1U)
17989 #define S_FSTATIC2 8
17990 #define V_FSTATIC2(x) ((x) << S_FSTATIC2)
17991 #define F_FSTATIC2 V_FSTATIC2(1U)
17993 #define S_ERRORSRDY2 7
17994 #define V_ERRORSRDY2(x) ((x) << S_ERRORSRDY2)
17995 #define F_ERRORSRDY2 V_ERRORSRDY2(1U)
17997 #define S_PLDTXSRDY2 6
17998 #define V_PLDTXSRDY2(x) ((x) << S_PLDTXSRDY2)
17999 #define F_PLDTXSRDY2 V_PLDTXSRDY2(1U)
18002 #define V_DBVLD2(x) ((x) << S_DBVLD2)
18003 #define F_DBVLD2 V_DBVLD2(1U)
18005 #define S_PLDTXVALID2 4
18006 #define V_PLDTXVALID2(x) ((x) << S_PLDTXVALID2)
18007 #define F_PLDTXVALID2 V_PLDTXVALID2(1U)
18009 #define S_ETXVALID2 3
18010 #define V_ETXVALID2(x) ((x) << S_ETXVALID2)
18011 #define F_ETXVALID2 V_ETXVALID2(1U)
18013 #define S_ETXFULL2 2
18014 #define V_ETXFULL2(x) ((x) << S_ETXFULL2)
18015 #define F_ETXFULL2 V_ETXFULL2(1U)
18017 #define S_ERXVALID2 1
18018 #define V_ERXVALID2(x) ((x) << S_ERXVALID2)
18019 #define F_ERXVALID2 V_ERXVALID2(1U)
18021 #define S_ERXFULL2 0
18022 #define V_ERXFULL2(x) ((x) << S_ERXFULL2)
18023 #define F_ERXFULL2 V_ERXFULL2(1U)
18025 #define A_TP_DBG_ESIDE_DISP0 0x136
18027 #define S_RESRDY 31
18028 #define V_RESRDY(x) ((x) << S_RESRDY)
18029 #define F_RESRDY V_RESRDY(1U)
18032 #define M_STATE 0x7U
18033 #define V_STATE(x) ((x) << S_STATE)
18034 #define G_STATE(x) (((x) >> S_STATE) & M_STATE)
18036 #define S_FIFOCPL5RXVALID 27
18037 #define V_FIFOCPL5RXVALID(x) ((x) << S_FIFOCPL5RXVALID)
18038 #define F_FIFOCPL5RXVALID V_FIFOCPL5RXVALID(1U)
18040 #define S_FIFOETHRXVALID 26
18041 #define V_FIFOETHRXVALID(x) ((x) << S_FIFOETHRXVALID)
18042 #define F_FIFOETHRXVALID V_FIFOETHRXVALID(1U)
18044 #define S_FIFOETHRXSOCP 25
18045 #define V_FIFOETHRXSOCP(x) ((x) << S_FIFOETHRXSOCP)
18046 #define F_FIFOETHRXSOCP V_FIFOETHRXSOCP(1U)
18048 #define S_FIFOPLDRXZEROP 24
18049 #define V_FIFOPLDRXZEROP(x) ((x) << S_FIFOPLDRXZEROP)
18050 #define F_FIFOPLDRXZEROP V_FIFOPLDRXZEROP(1U)
18052 #define S_PLDRXVALID 23
18053 #define V_PLDRXVALID(x) ((x) << S_PLDRXVALID)
18054 #define F_PLDRXVALID V_PLDRXVALID(1U)
18056 #define S_FIFOPLDRXZEROP_SRDY 22
18057 #define V_FIFOPLDRXZEROP_SRDY(x) ((x) << S_FIFOPLDRXZEROP_SRDY)
18058 #define F_FIFOPLDRXZEROP_SRDY V_FIFOPLDRXZEROP_SRDY(1U)
18060 #define S_FIFOIPRXVALID 21
18061 #define V_FIFOIPRXVALID(x) ((x) << S_FIFOIPRXVALID)
18062 #define F_FIFOIPRXVALID V_FIFOIPRXVALID(1U)
18064 #define S_FIFOTCPRXVALID 20
18065 #define V_FIFOTCPRXVALID(x) ((x) << S_FIFOTCPRXVALID)
18066 #define F_FIFOTCPRXVALID V_FIFOTCPRXVALID(1U)
18068 #define S_PLDRXCSUMVALID 19
18069 #define V_PLDRXCSUMVALID(x) ((x) << S_PLDRXCSUMVALID)
18070 #define F_PLDRXCSUMVALID V_PLDRXCSUMVALID(1U)
18072 #define S_FIFOIPCSUMSRDY 18
18073 #define V_FIFOIPCSUMSRDY(x) ((x) << S_FIFOIPCSUMSRDY)
18074 #define F_FIFOIPCSUMSRDY V_FIFOIPCSUMSRDY(1U)
18076 #define S_FIFOIPPSEUDOCSUMSRDY 17
18077 #define V_FIFOIPPSEUDOCSUMSRDY(x) ((x) << S_FIFOIPPSEUDOCSUMSRDY)
18078 #define F_FIFOIPPSEUDOCSUMSRDY V_FIFOIPPSEUDOCSUMSRDY(1U)
18080 #define S_FIFOTCPCSUMSRDY 16
18081 #define V_FIFOTCPCSUMSRDY(x) ((x) << S_FIFOTCPCSUMSRDY)
18082 #define F_FIFOTCPCSUMSRDY V_FIFOTCPCSUMSRDY(1U)
18084 #define S_ESTATIC4 12
18085 #define M_ESTATIC4 0xfU
18086 #define V_ESTATIC4(x) ((x) << S_ESTATIC4)
18087 #define G_ESTATIC4(x) (((x) >> S_ESTATIC4) & M_ESTATIC4)
18089 #define S_FIFOCPLSOCPCNT 10
18090 #define M_FIFOCPLSOCPCNT 0x3U
18091 #define V_FIFOCPLSOCPCNT(x) ((x) << S_FIFOCPLSOCPCNT)
18092 #define G_FIFOCPLSOCPCNT(x) (((x) >> S_FIFOCPLSOCPCNT) & M_FIFOCPLSOCPCNT)
18094 #define S_FIFOETHSOCPCNT 8
18095 #define M_FIFOETHSOCPCNT 0x3U
18096 #define V_FIFOETHSOCPCNT(x) ((x) << S_FIFOETHSOCPCNT)
18097 #define G_FIFOETHSOCPCNT(x) (((x) >> S_FIFOETHSOCPCNT) & M_FIFOETHSOCPCNT)
18099 #define S_FIFOIPSOCPCNT 6
18100 #define M_FIFOIPSOCPCNT 0x3U
18101 #define V_FIFOIPSOCPCNT(x) ((x) << S_FIFOIPSOCPCNT)
18102 #define G_FIFOIPSOCPCNT(x) (((x) >> S_FIFOIPSOCPCNT) & M_FIFOIPSOCPCNT)
18104 #define S_FIFOTCPSOCPCNT 4
18105 #define M_FIFOTCPSOCPCNT 0x3U
18106 #define V_FIFOTCPSOCPCNT(x) ((x) << S_FIFOTCPSOCPCNT)
18107 #define G_FIFOTCPSOCPCNT(x) (((x) >> S_FIFOTCPSOCPCNT) & M_FIFOTCPSOCPCNT)
18109 #define S_PLD_RXZEROP_CNT 2
18110 #define M_PLD_RXZEROP_CNT 0x3U
18111 #define V_PLD_RXZEROP_CNT(x) ((x) << S_PLD_RXZEROP_CNT)
18112 #define G_PLD_RXZEROP_CNT(x) (((x) >> S_PLD_RXZEROP_CNT) & M_PLD_RXZEROP_CNT)
18114 #define S_ESTATIC6 1
18115 #define V_ESTATIC6(x) ((x) << S_ESTATIC6)
18116 #define F_ESTATIC6 V_ESTATIC6(1U)
18119 #define V_TXFULL(x) ((x) << S_TXFULL)
18120 #define F_TXFULL V_TXFULL(1U)
18122 #define A_TP_DBG_ESIDE_DISP1 0x137
18123 #define A_TP_MAC_MATCH_MAP0 0x138
18125 #define S_MAPVALUEWR 16
18126 #define M_MAPVALUEWR 0xffU
18127 #define V_MAPVALUEWR(x) ((x) << S_MAPVALUEWR)
18128 #define G_MAPVALUEWR(x) (((x) >> S_MAPVALUEWR) & M_MAPVALUEWR)
18130 #define S_MAPINDEX 2
18131 #define M_MAPINDEX 0x1ffU
18132 #define V_MAPINDEX(x) ((x) << S_MAPINDEX)
18133 #define G_MAPINDEX(x) (((x) >> S_MAPINDEX) & M_MAPINDEX)
18135 #define S_MAPREAD 1
18136 #define V_MAPREAD(x) ((x) << S_MAPREAD)
18137 #define F_MAPREAD V_MAPREAD(1U)
18139 #define S_MAPWRITE 0
18140 #define V_MAPWRITE(x) ((x) << S_MAPWRITE)
18141 #define F_MAPWRITE V_MAPWRITE(1U)
18143 #define A_TP_MAC_MATCH_MAP1 0x139
18145 #define S_MAPVALUERD 0
18146 #define M_MAPVALUERD 0x1ffU
18147 #define V_MAPVALUERD(x) ((x) << S_MAPVALUERD)
18148 #define G_MAPVALUERD(x) (((x) >> S_MAPVALUERD) & M_MAPVALUERD)
18150 #define A_TP_DBG_ESIDE_DISP2 0x13a
18151 #define A_TP_DBG_ESIDE_DISP3 0x13b
18152 #define A_TP_DBG_ESIDE_HDR0 0x13c
18154 #define S_TCPSOPCNT 28
18155 #define M_TCPSOPCNT 0xfU
18156 #define V_TCPSOPCNT(x) ((x) << S_TCPSOPCNT)
18157 #define G_TCPSOPCNT(x) (((x) >> S_TCPSOPCNT) & M_TCPSOPCNT)
18159 #define S_TCPEOPCNT 24
18160 #define M_TCPEOPCNT 0xfU
18161 #define V_TCPEOPCNT(x) ((x) << S_TCPEOPCNT)
18162 #define G_TCPEOPCNT(x) (((x) >> S_TCPEOPCNT) & M_TCPEOPCNT)
18164 #define S_IPSOPCNT 20
18165 #define M_IPSOPCNT 0xfU
18166 #define V_IPSOPCNT(x) ((x) << S_IPSOPCNT)
18167 #define G_IPSOPCNT(x) (((x) >> S_IPSOPCNT) & M_IPSOPCNT)
18169 #define S_IPEOPCNT 16
18170 #define M_IPEOPCNT 0xfU
18171 #define V_IPEOPCNT(x) ((x) << S_IPEOPCNT)
18172 #define G_IPEOPCNT(x) (((x) >> S_IPEOPCNT) & M_IPEOPCNT)
18174 #define S_ETHSOPCNT 12
18175 #define M_ETHSOPCNT 0xfU
18176 #define V_ETHSOPCNT(x) ((x) << S_ETHSOPCNT)
18177 #define G_ETHSOPCNT(x) (((x) >> S_ETHSOPCNT) & M_ETHSOPCNT)
18179 #define S_ETHEOPCNT 8
18180 #define M_ETHEOPCNT 0xfU
18181 #define V_ETHEOPCNT(x) ((x) << S_ETHEOPCNT)
18182 #define G_ETHEOPCNT(x) (((x) >> S_ETHEOPCNT) & M_ETHEOPCNT)
18184 #define S_CPLSOPCNT 4
18185 #define M_CPLSOPCNT 0xfU
18186 #define V_CPLSOPCNT(x) ((x) << S_CPLSOPCNT)
18187 #define G_CPLSOPCNT(x) (((x) >> S_CPLSOPCNT) & M_CPLSOPCNT)
18189 #define S_CPLEOPCNT 0
18190 #define M_CPLEOPCNT 0xfU
18191 #define V_CPLEOPCNT(x) ((x) << S_CPLEOPCNT)
18192 #define G_CPLEOPCNT(x) (((x) >> S_CPLEOPCNT) & M_CPLEOPCNT)
18194 #define A_TP_DBG_ESIDE_HDR1 0x13d
18195 #define A_TP_DBG_ESIDE_HDR2 0x13e
18196 #define A_TP_DBG_ESIDE_HDR3 0x13f
18197 #define A_TP_VLAN_PRI_MAP 0x140
18199 #define S_FRAGMENTATION 9
18200 #define V_FRAGMENTATION(x) ((x) << S_FRAGMENTATION)
18201 #define F_FRAGMENTATION V_FRAGMENTATION(1U)
18203 #define S_MPSHITTYPE 8
18204 #define V_MPSHITTYPE(x) ((x) << S_MPSHITTYPE)
18205 #define F_MPSHITTYPE V_MPSHITTYPE(1U)
18207 #define S_MACMATCH 7
18208 #define V_MACMATCH(x) ((x) << S_MACMATCH)
18209 #define F_MACMATCH V_MACMATCH(1U)
18211 #define S_ETHERTYPE 6
18212 #define V_ETHERTYPE(x) ((x) << S_ETHERTYPE)
18213 #define F_ETHERTYPE V_ETHERTYPE(1U)
18215 #define S_PROTOCOL 5
18216 #define V_PROTOCOL(x) ((x) << S_PROTOCOL)
18217 #define F_PROTOCOL V_PROTOCOL(1U)
18220 #define V_TOS(x) ((x) << S_TOS)
18221 #define F_TOS V_TOS(1U)
18224 #define V_VLAN(x) ((x) << S_VLAN)
18225 #define F_VLAN V_VLAN(1U)
18227 #define S_VNIC_ID 2
18228 #define V_VNIC_ID(x) ((x) << S_VNIC_ID)
18229 #define F_VNIC_ID V_VNIC_ID(1U)
18232 #define V_PORT(x) ((x) << S_PORT)
18233 #define F_PORT V_PORT(1U)
18236 #define V_FCOE(x) ((x) << S_FCOE)
18237 #define F_FCOE V_FCOE(1U)
18239 #define S_FILTERMODE 15
18240 #define V_FILTERMODE(x) ((x) << S_FILTERMODE)
18241 #define F_FILTERMODE V_FILTERMODE(1U)
18243 #define S_FCOEMASK 14
18244 #define V_FCOEMASK(x) ((x) << S_FCOEMASK)
18245 #define F_FCOEMASK V_FCOEMASK(1U)
18247 #define S_SRVRSRAM 13
18248 #define V_SRVRSRAM(x) ((x) << S_SRVRSRAM)
18249 #define F_SRVRSRAM V_SRVRSRAM(1U)
18251 #define A_TP_INGRESS_CONFIG 0x141
18253 #define S_OPAQUE_TYPE 16
18254 #define M_OPAQUE_TYPE 0xffffU
18255 #define V_OPAQUE_TYPE(x) ((x) << S_OPAQUE_TYPE)
18256 #define G_OPAQUE_TYPE(x) (((x) >> S_OPAQUE_TYPE) & M_OPAQUE_TYPE)
18258 #define S_OPAQUE_RM 15
18259 #define V_OPAQUE_RM(x) ((x) << S_OPAQUE_RM)
18260 #define F_OPAQUE_RM V_OPAQUE_RM(1U)
18262 #define S_OPAQUE_HDR_SIZE 14
18263 #define V_OPAQUE_HDR_SIZE(x) ((x) << S_OPAQUE_HDR_SIZE)
18264 #define F_OPAQUE_HDR_SIZE V_OPAQUE_HDR_SIZE(1U)
18266 #define S_OPAQUE_RM_MAC_IN_MAC 13
18267 #define V_OPAQUE_RM_MAC_IN_MAC(x) ((x) << S_OPAQUE_RM_MAC_IN_MAC)
18268 #define F_OPAQUE_RM_MAC_IN_MAC V_OPAQUE_RM_MAC_IN_MAC(1U)
18270 #define S_FCOE_TARGET 12
18271 #define V_FCOE_TARGET(x) ((x) << S_FCOE_TARGET)
18272 #define F_FCOE_TARGET V_FCOE_TARGET(1U)
18275 #define V_VNIC(x) ((x) << S_VNIC)
18276 #define F_VNIC V_VNIC(1U)
18278 #define S_CSUM_HAS_PSEUDO_HDR 10
18279 #define V_CSUM_HAS_PSEUDO_HDR(x) ((x) << S_CSUM_HAS_PSEUDO_HDR)
18280 #define F_CSUM_HAS_PSEUDO_HDR V_CSUM_HAS_PSEUDO_HDR(1U)
18282 #define S_RM_OVLAN 9
18283 #define V_RM_OVLAN(x) ((x) << S_RM_OVLAN)
18284 #define F_RM_OVLAN V_RM_OVLAN(1U)
18286 #define S_LOOKUPEVERYPKT 8
18287 #define V_LOOKUPEVERYPKT(x) ((x) << S_LOOKUPEVERYPKT)
18288 #define F_LOOKUPEVERYPKT V_LOOKUPEVERYPKT(1U)
18290 #define S_IPV6_EXT_HDR_SKIP 0
18291 #define M_IPV6_EXT_HDR_SKIP 0xffU
18292 #define V_IPV6_EXT_HDR_SKIP(x) ((x) << S_IPV6_EXT_HDR_SKIP)
18293 #define G_IPV6_EXT_HDR_SKIP(x) (((x) >> S_IPV6_EXT_HDR_SKIP) & M_IPV6_EXT_HDR_SKIP)
18295 #define S_FRAG_LEN_MOD8_COMPAT 12
18296 #define V_FRAG_LEN_MOD8_COMPAT(x) ((x) << S_FRAG_LEN_MOD8_COMPAT)
18297 #define F_FRAG_LEN_MOD8_COMPAT V_FRAG_LEN_MOD8_COMPAT(1U)
18299 #define A_TP_TX_DROP_CFG_CH2 0x142
18300 #define A_TP_TX_DROP_CFG_CH3 0x143
18301 #define A_TP_EGRESS_CONFIG 0x145
18303 #define S_REWRITEFORCETOSIZE 0
18304 #define V_REWRITEFORCETOSIZE(x) ((x) << S_REWRITEFORCETOSIZE)
18305 #define F_REWRITEFORCETOSIZE V_REWRITEFORCETOSIZE(1U)
18307 #define A_TP_INGRESS_CONFIG2 0x145
18309 #define S_IPV6_UDP_CSUM_COMPAT 31
18310 #define V_IPV6_UDP_CSUM_COMPAT(x) ((x) << S_IPV6_UDP_CSUM_COMPAT)
18311 #define F_IPV6_UDP_CSUM_COMPAT V_IPV6_UDP_CSUM_COMPAT(1U)
18313 #define S_VNTAGPLDENABLE 30
18314 #define V_VNTAGPLDENABLE(x) ((x) << S_VNTAGPLDENABLE)
18315 #define F_VNTAGPLDENABLE V_VNTAGPLDENABLE(1U)
18317 #define S_TCP_PLD_FILTER_OFFSET 20
18318 #define M_TCP_PLD_FILTER_OFFSET 0x3ffU
18319 #define V_TCP_PLD_FILTER_OFFSET(x) ((x) << S_TCP_PLD_FILTER_OFFSET)
18320 #define G_TCP_PLD_FILTER_OFFSET(x) (((x) >> S_TCP_PLD_FILTER_OFFSET) & M_TCP_PLD_FILTER_OFFSET)
18322 #define S_UDP_PLD_FILTER_OFFSET 10
18323 #define M_UDP_PLD_FILTER_OFFSET 0x3ffU
18324 #define V_UDP_PLD_FILTER_OFFSET(x) ((x) << S_UDP_PLD_FILTER_OFFSET)
18325 #define G_UDP_PLD_FILTER_OFFSET(x) (((x) >> S_UDP_PLD_FILTER_OFFSET) & M_UDP_PLD_FILTER_OFFSET)
18327 #define S_TNL_PLD_FILTER_OFFSET 0
18328 #define M_TNL_PLD_FILTER_OFFSET 0x3ffU
18329 #define V_TNL_PLD_FILTER_OFFSET(x) ((x) << S_TNL_PLD_FILTER_OFFSET)
18330 #define G_TNL_PLD_FILTER_OFFSET(x) (((x) >> S_TNL_PLD_FILTER_OFFSET) & M_TNL_PLD_FILTER_OFFSET)
18332 #define A_TP_EHDR_CONFIG_LO 0x146
18334 #define S_CPLLIMIT 24
18335 #define M_CPLLIMIT 0xffU
18336 #define V_CPLLIMIT(x) ((x) << S_CPLLIMIT)
18337 #define G_CPLLIMIT(x) (((x) >> S_CPLLIMIT) & M_CPLLIMIT)
18339 #define S_ETHLIMIT 16
18340 #define M_ETHLIMIT 0xffU
18341 #define V_ETHLIMIT(x) ((x) << S_ETHLIMIT)
18342 #define G_ETHLIMIT(x) (((x) >> S_ETHLIMIT) & M_ETHLIMIT)
18344 #define S_IPLIMIT 8
18345 #define M_IPLIMIT 0xffU
18346 #define V_IPLIMIT(x) ((x) << S_IPLIMIT)
18347 #define G_IPLIMIT(x) (((x) >> S_IPLIMIT) & M_IPLIMIT)
18349 #define S_TCPLIMIT 0
18350 #define M_TCPLIMIT 0xffU
18351 #define V_TCPLIMIT(x) ((x) << S_TCPLIMIT)
18352 #define G_TCPLIMIT(x) (((x) >> S_TCPLIMIT) & M_TCPLIMIT)
18354 #define A_TP_EHDR_CONFIG_HI 0x147
18355 #define A_TP_DBG_ESIDE_INT 0x148
18357 #define S_ERXSOP2X 28
18358 #define M_ERXSOP2X 0xfU
18359 #define V_ERXSOP2X(x) ((x) << S_ERXSOP2X)
18360 #define G_ERXSOP2X(x) (((x) >> S_ERXSOP2X) & M_ERXSOP2X)
18362 #define S_ERXEOP2X 24
18363 #define M_ERXEOP2X 0xfU
18364 #define V_ERXEOP2X(x) ((x) << S_ERXEOP2X)
18365 #define G_ERXEOP2X(x) (((x) >> S_ERXEOP2X) & M_ERXEOP2X)
18367 #define S_ERXVALID2X 20
18368 #define M_ERXVALID2X 0xfU
18369 #define V_ERXVALID2X(x) ((x) << S_ERXVALID2X)
18370 #define G_ERXVALID2X(x) (((x) >> S_ERXVALID2X) & M_ERXVALID2X)
18372 #define S_ERXAFULL2X 16
18373 #define M_ERXAFULL2X 0xfU
18374 #define V_ERXAFULL2X(x) ((x) << S_ERXAFULL2X)
18375 #define G_ERXAFULL2X(x) (((x) >> S_ERXAFULL2X) & M_ERXAFULL2X)
18377 #define S_PLD2XTXVALID 12
18378 #define M_PLD2XTXVALID 0xfU
18379 #define V_PLD2XTXVALID(x) ((x) << S_PLD2XTXVALID)
18380 #define G_PLD2XTXVALID(x) (((x) >> S_PLD2XTXVALID) & M_PLD2XTXVALID)
18382 #define S_PLD2XTXAFULL 8
18383 #define M_PLD2XTXAFULL 0xfU
18384 #define V_PLD2XTXAFULL(x) ((x) << S_PLD2XTXAFULL)
18385 #define G_PLD2XTXAFULL(x) (((x) >> S_PLD2XTXAFULL) & M_PLD2XTXAFULL)
18387 #define S_ERRORSRDY 7
18388 #define V_ERRORSRDY(x) ((x) << S_ERRORSRDY)
18389 #define F_ERRORSRDY V_ERRORSRDY(1U)
18391 #define S_ERRORDRDY 6
18392 #define V_ERRORDRDY(x) ((x) << S_ERRORDRDY)
18393 #define F_ERRORDRDY V_ERRORDRDY(1U)
18395 #define S_TCPOPSRDY 5
18396 #define V_TCPOPSRDY(x) ((x) << S_TCPOPSRDY)
18397 #define F_TCPOPSRDY V_TCPOPSRDY(1U)
18399 #define S_TCPOPDRDY 4
18400 #define V_TCPOPDRDY(x) ((x) << S_TCPOPDRDY)
18401 #define F_TCPOPDRDY V_TCPOPDRDY(1U)
18403 #define S_PLDTXSRDY 3
18404 #define V_PLDTXSRDY(x) ((x) << S_PLDTXSRDY)
18405 #define F_PLDTXSRDY V_PLDTXSRDY(1U)
18407 #define S_PLDTXDRDY 2
18408 #define V_PLDTXDRDY(x) ((x) << S_PLDTXDRDY)
18409 #define F_PLDTXDRDY V_PLDTXDRDY(1U)
18411 #define S_TCPOPTTXVALID 1
18412 #define V_TCPOPTTXVALID(x) ((x) << S_TCPOPTTXVALID)
18413 #define F_TCPOPTTXVALID V_TCPOPTTXVALID(1U)
18415 #define S_TCPOPTTXFULL 0
18416 #define V_TCPOPTTXFULL(x) ((x) << S_TCPOPTTXFULL)
18417 #define F_TCPOPTTXFULL V_TCPOPTTXFULL(1U)
18419 #define A_TP_DBG_ESIDE_DEMUX 0x149
18421 #define S_EALLDONE 28
18422 #define M_EALLDONE 0xfU
18423 #define V_EALLDONE(x) ((x) << S_EALLDONE)
18424 #define G_EALLDONE(x) (((x) >> S_EALLDONE) & M_EALLDONE)
18426 #define S_EFIFOPLDDONE 24
18427 #define M_EFIFOPLDDONE 0xfU
18428 #define V_EFIFOPLDDONE(x) ((x) << S_EFIFOPLDDONE)
18429 #define G_EFIFOPLDDONE(x) (((x) >> S_EFIFOPLDDONE) & M_EFIFOPLDDONE)
18431 #define S_EDBDONE 20
18432 #define M_EDBDONE 0xfU
18433 #define V_EDBDONE(x) ((x) << S_EDBDONE)
18434 #define G_EDBDONE(x) (((x) >> S_EDBDONE) & M_EDBDONE)
18436 #define S_EISSFIFODONE 16
18437 #define M_EISSFIFODONE 0xfU
18438 #define V_EISSFIFODONE(x) ((x) << S_EISSFIFODONE)
18439 #define G_EISSFIFODONE(x) (((x) >> S_EISSFIFODONE) & M_EISSFIFODONE)
18441 #define S_EACKERRFIFODONE 12
18442 #define M_EACKERRFIFODONE 0xfU
18443 #define V_EACKERRFIFODONE(x) ((x) << S_EACKERRFIFODONE)
18444 #define G_EACKERRFIFODONE(x) (((x) >> S_EACKERRFIFODONE) & M_EACKERRFIFODONE)
18446 #define S_EFIFOERRORDONE 8
18447 #define M_EFIFOERRORDONE 0xfU
18448 #define V_EFIFOERRORDONE(x) ((x) << S_EFIFOERRORDONE)
18449 #define G_EFIFOERRORDONE(x) (((x) >> S_EFIFOERRORDONE) & M_EFIFOERRORDONE)
18451 #define S_ERXPKTATTRFIFOFDONE 4
18452 #define M_ERXPKTATTRFIFOFDONE 0xfU
18453 #define V_ERXPKTATTRFIFOFDONE(x) ((x) << S_ERXPKTATTRFIFOFDONE)
18454 #define G_ERXPKTATTRFIFOFDONE(x) (((x) >> S_ERXPKTATTRFIFOFDONE) & M_ERXPKTATTRFIFOFDONE)
18456 #define S_ETCPOPDONE 0
18457 #define M_ETCPOPDONE 0xfU
18458 #define V_ETCPOPDONE(x) ((x) << S_ETCPOPDONE)
18459 #define G_ETCPOPDONE(x) (((x) >> S_ETCPOPDONE) & M_ETCPOPDONE)
18461 #define A_TP_DBG_ESIDE_IN0 0x14a
18463 #define S_RXVALID 31
18464 #define V_RXVALID(x) ((x) << S_RXVALID)
18465 #define F_RXVALID V_RXVALID(1U)
18467 #define S_RXFULL 30
18468 #define V_RXFULL(x) ((x) << S_RXFULL)
18469 #define F_RXFULL V_RXFULL(1U)
18471 #define S_RXSOCP 29
18472 #define V_RXSOCP(x) ((x) << S_RXSOCP)
18473 #define F_RXSOCP V_RXSOCP(1U)
18476 #define V_RXEOP(x) ((x) << S_RXEOP)
18477 #define F_RXEOP V_RXEOP(1U)
18479 #define S_RXVALID_I 27
18480 #define V_RXVALID_I(x) ((x) << S_RXVALID_I)
18481 #define F_RXVALID_I V_RXVALID_I(1U)
18483 #define S_RXFULL_I 26
18484 #define V_RXFULL_I(x) ((x) << S_RXFULL_I)
18485 #define F_RXFULL_I V_RXFULL_I(1U)
18487 #define S_RXSOCP_I 25
18488 #define V_RXSOCP_I(x) ((x) << S_RXSOCP_I)
18489 #define F_RXSOCP_I V_RXSOCP_I(1U)
18491 #define S_RXEOP_I 24
18492 #define V_RXEOP_I(x) ((x) << S_RXEOP_I)
18493 #define F_RXEOP_I V_RXEOP_I(1U)
18495 #define S_RXVALID_I2 23
18496 #define V_RXVALID_I2(x) ((x) << S_RXVALID_I2)
18497 #define F_RXVALID_I2 V_RXVALID_I2(1U)
18499 #define S_RXFULL_I2 22
18500 #define V_RXFULL_I2(x) ((x) << S_RXFULL_I2)
18501 #define F_RXFULL_I2 V_RXFULL_I2(1U)
18503 #define S_RXSOCP_I2 21
18504 #define V_RXSOCP_I2(x) ((x) << S_RXSOCP_I2)
18505 #define F_RXSOCP_I2 V_RXSOCP_I2(1U)
18507 #define S_RXEOP_I2 20
18508 #define V_RXEOP_I2(x) ((x) << S_RXEOP_I2)
18509 #define F_RXEOP_I2 V_RXEOP_I2(1U)
18511 #define S_CT_MPA_TXVALID_FIFO 19
18512 #define V_CT_MPA_TXVALID_FIFO(x) ((x) << S_CT_MPA_TXVALID_FIFO)
18513 #define F_CT_MPA_TXVALID_FIFO V_CT_MPA_TXVALID_FIFO(1U)
18515 #define S_CT_MPA_TXFULL_FIFO 18
18516 #define V_CT_MPA_TXFULL_FIFO(x) ((x) << S_CT_MPA_TXFULL_FIFO)
18517 #define F_CT_MPA_TXFULL_FIFO V_CT_MPA_TXFULL_FIFO(1U)
18519 #define S_CT_MPA_TXVALID 17
18520 #define V_CT_MPA_TXVALID(x) ((x) << S_CT_MPA_TXVALID)
18521 #define F_CT_MPA_TXVALID V_CT_MPA_TXVALID(1U)
18523 #define S_CT_MPA_TXFULL 16
18524 #define V_CT_MPA_TXFULL(x) ((x) << S_CT_MPA_TXFULL)
18525 #define F_CT_MPA_TXFULL V_CT_MPA_TXFULL(1U)
18527 #define S_RXVALID_BUF 15
18528 #define V_RXVALID_BUF(x) ((x) << S_RXVALID_BUF)
18529 #define F_RXVALID_BUF V_RXVALID_BUF(1U)
18531 #define S_RXFULL_BUF 14
18532 #define V_RXFULL_BUF(x) ((x) << S_RXFULL_BUF)
18533 #define F_RXFULL_BUF V_RXFULL_BUF(1U)
18535 #define S_PLD_TXVALID 13
18536 #define V_PLD_TXVALID(x) ((x) << S_PLD_TXVALID)
18537 #define F_PLD_TXVALID V_PLD_TXVALID(1U)
18539 #define S_PLD_TXFULL 12
18540 #define V_PLD_TXFULL(x) ((x) << S_PLD_TXFULL)
18541 #define F_PLD_TXFULL V_PLD_TXFULL(1U)
18543 #define S_ISS_FIFO_SRDY 11
18544 #define V_ISS_FIFO_SRDY(x) ((x) << S_ISS_FIFO_SRDY)
18545 #define F_ISS_FIFO_SRDY V_ISS_FIFO_SRDY(1U)
18547 #define S_ISS_FIFO_DRDY 10
18548 #define V_ISS_FIFO_DRDY(x) ((x) << S_ISS_FIFO_DRDY)
18549 #define F_ISS_FIFO_DRDY V_ISS_FIFO_DRDY(1U)
18551 #define S_CT_TCP_OP_ISS_SRDY 9
18552 #define V_CT_TCP_OP_ISS_SRDY(x) ((x) << S_CT_TCP_OP_ISS_SRDY)
18553 #define F_CT_TCP_OP_ISS_SRDY V_CT_TCP_OP_ISS_SRDY(1U)
18555 #define S_CT_TCP_OP_ISS_DRDY 8
18556 #define V_CT_TCP_OP_ISS_DRDY(x) ((x) << S_CT_TCP_OP_ISS_DRDY)
18557 #define F_CT_TCP_OP_ISS_DRDY V_CT_TCP_OP_ISS_DRDY(1U)
18559 #define S_P2CSUMERROR_SRDY 7
18560 #define V_P2CSUMERROR_SRDY(x) ((x) << S_P2CSUMERROR_SRDY)
18561 #define F_P2CSUMERROR_SRDY V_P2CSUMERROR_SRDY(1U)
18563 #define S_P2CSUMERROR_DRDY 6
18564 #define V_P2CSUMERROR_DRDY(x) ((x) << S_P2CSUMERROR_DRDY)
18565 #define F_P2CSUMERROR_DRDY V_P2CSUMERROR_DRDY(1U)
18567 #define S_FIFO_ERROR_SRDY 5
18568 #define V_FIFO_ERROR_SRDY(x) ((x) << S_FIFO_ERROR_SRDY)
18569 #define F_FIFO_ERROR_SRDY V_FIFO_ERROR_SRDY(1U)
18571 #define S_FIFO_ERROR_DRDY 4
18572 #define V_FIFO_ERROR_DRDY(x) ((x) << S_FIFO_ERROR_DRDY)
18573 #define F_FIFO_ERROR_DRDY V_FIFO_ERROR_DRDY(1U)
18575 #define S_PLD_SRDY 3
18576 #define V_PLD_SRDY(x) ((x) << S_PLD_SRDY)
18577 #define F_PLD_SRDY V_PLD_SRDY(1U)
18579 #define S_PLD_DRDY 2
18580 #define V_PLD_DRDY(x) ((x) << S_PLD_DRDY)
18581 #define F_PLD_DRDY V_PLD_DRDY(1U)
18583 #define S_RX_PKT_ATTR_SRDY 1
18584 #define V_RX_PKT_ATTR_SRDY(x) ((x) << S_RX_PKT_ATTR_SRDY)
18585 #define F_RX_PKT_ATTR_SRDY V_RX_PKT_ATTR_SRDY(1U)
18587 #define S_RX_PKT_ATTR_DRDY 0
18588 #define V_RX_PKT_ATTR_DRDY(x) ((x) << S_RX_PKT_ATTR_DRDY)
18589 #define F_RX_PKT_ATTR_DRDY V_RX_PKT_ATTR_DRDY(1U)
18591 #define S_RXRUNT 25
18592 #define V_RXRUNT(x) ((x) << S_RXRUNT)
18593 #define F_RXRUNT V_RXRUNT(1U)
18595 #define S_RXRUNTPARSER 24
18596 #define V_RXRUNTPARSER(x) ((x) << S_RXRUNTPARSER)
18597 #define F_RXRUNTPARSER V_RXRUNTPARSER(1U)
18599 #define S_ERROR_SRDY 5
18600 #define V_ERROR_SRDY(x) ((x) << S_ERROR_SRDY)
18601 #define F_ERROR_SRDY V_ERROR_SRDY(1U)
18603 #define S_ERROR_DRDY 4
18604 #define V_ERROR_DRDY(x) ((x) << S_ERROR_DRDY)
18605 #define F_ERROR_DRDY V_ERROR_DRDY(1U)
18607 #define A_TP_DBG_ESIDE_IN1 0x14b
18608 #define A_TP_DBG_ESIDE_IN2 0x14c
18609 #define A_TP_DBG_ESIDE_IN3 0x14d
18610 #define A_TP_DBG_ESIDE_FRM 0x14e
18612 #define S_ERX2XERROR 28
18613 #define M_ERX2XERROR 0xfU
18614 #define V_ERX2XERROR(x) ((x) << S_ERX2XERROR)
18615 #define G_ERX2XERROR(x) (((x) >> S_ERX2XERROR) & M_ERX2XERROR)
18617 #define S_EPLDTX2XERROR 24
18618 #define M_EPLDTX2XERROR 0xfU
18619 #define V_EPLDTX2XERROR(x) ((x) << S_EPLDTX2XERROR)
18620 #define G_EPLDTX2XERROR(x) (((x) >> S_EPLDTX2XERROR) & M_EPLDTX2XERROR)
18622 #define S_ETXERROR 20
18623 #define M_ETXERROR 0xfU
18624 #define V_ETXERROR(x) ((x) << S_ETXERROR)
18625 #define G_ETXERROR(x) (((x) >> S_ETXERROR) & M_ETXERROR)
18627 #define S_EPLDRXERROR 16
18628 #define M_EPLDRXERROR 0xfU
18629 #define V_EPLDRXERROR(x) ((x) << S_EPLDRXERROR)
18630 #define G_EPLDRXERROR(x) (((x) >> S_EPLDRXERROR) & M_EPLDRXERROR)
18632 #define S_ERXSIZEERROR3 12
18633 #define M_ERXSIZEERROR3 0xfU
18634 #define V_ERXSIZEERROR3(x) ((x) << S_ERXSIZEERROR3)
18635 #define G_ERXSIZEERROR3(x) (((x) >> S_ERXSIZEERROR3) & M_ERXSIZEERROR3)
18637 #define S_ERXSIZEERROR2 8
18638 #define M_ERXSIZEERROR2 0xfU
18639 #define V_ERXSIZEERROR2(x) ((x) << S_ERXSIZEERROR2)
18640 #define G_ERXSIZEERROR2(x) (((x) >> S_ERXSIZEERROR2) & M_ERXSIZEERROR2)
18642 #define S_ERXSIZEERROR1 4
18643 #define M_ERXSIZEERROR1 0xfU
18644 #define V_ERXSIZEERROR1(x) ((x) << S_ERXSIZEERROR1)
18645 #define G_ERXSIZEERROR1(x) (((x) >> S_ERXSIZEERROR1) & M_ERXSIZEERROR1)
18647 #define S_ERXSIZEERROR0 0
18648 #define M_ERXSIZEERROR0 0xfU
18649 #define V_ERXSIZEERROR0(x) ((x) << S_ERXSIZEERROR0)
18650 #define G_ERXSIZEERROR0(x) (((x) >> S_ERXSIZEERROR0) & M_ERXSIZEERROR0)
18652 #define A_TP_DBG_ESIDE_DRP 0x14f
18654 #define S_RXDROP3 24
18655 #define M_RXDROP3 0xffU
18656 #define V_RXDROP3(x) ((x) << S_RXDROP3)
18657 #define G_RXDROP3(x) (((x) >> S_RXDROP3) & M_RXDROP3)
18659 #define S_RXDROP2 16
18660 #define M_RXDROP2 0xffU
18661 #define V_RXDROP2(x) ((x) << S_RXDROP2)
18662 #define G_RXDROP2(x) (((x) >> S_RXDROP2) & M_RXDROP2)
18664 #define S_RXDROP1 8
18665 #define M_RXDROP1 0xffU
18666 #define V_RXDROP1(x) ((x) << S_RXDROP1)
18667 #define G_RXDROP1(x) (((x) >> S_RXDROP1) & M_RXDROP1)
18669 #define S_RXDROP0 0
18670 #define M_RXDROP0 0xffU
18671 #define V_RXDROP0(x) ((x) << S_RXDROP0)
18672 #define G_RXDROP0(x) (((x) >> S_RXDROP0) & M_RXDROP0)
18674 #define A_TP_DBG_ESIDE_TX 0x150
18676 #define S_ETXVALID 4
18677 #define M_ETXVALID 0xfU
18678 #define V_ETXVALID(x) ((x) << S_ETXVALID)
18679 #define G_ETXVALID(x) (((x) >> S_ETXVALID) & M_ETXVALID)
18681 #define S_ETXFULL 0
18682 #define M_ETXFULL 0xfU
18683 #define V_ETXFULL(x) ((x) << S_ETXFULL)
18684 #define G_ETXFULL(x) (((x) >> S_ETXFULL) & M_ETXFULL)
18686 #define A_TP_ESIDE_SVID_MASK 0x151
18687 #define A_TP_ESIDE_DVID_MASK 0x152
18688 #define A_TP_ESIDE_ALIGN_MASK 0x153
18690 #define S_USE_LOOP_BIT 24
18691 #define V_USE_LOOP_BIT(x) ((x) << S_USE_LOOP_BIT)
18692 #define F_USE_LOOP_BIT V_USE_LOOP_BIT(1U)
18694 #define S_LOOP_OFFSET 16
18695 #define M_LOOP_OFFSET 0xffU
18696 #define V_LOOP_OFFSET(x) ((x) << S_LOOP_OFFSET)
18697 #define G_LOOP_OFFSET(x) (((x) >> S_LOOP_OFFSET) & M_LOOP_OFFSET)
18699 #define S_DVID_ID_OFFSET 8
18700 #define M_DVID_ID_OFFSET 0xffU
18701 #define V_DVID_ID_OFFSET(x) ((x) << S_DVID_ID_OFFSET)
18702 #define G_DVID_ID_OFFSET(x) (((x) >> S_DVID_ID_OFFSET) & M_DVID_ID_OFFSET)
18704 #define S_SVID_ID_OFFSET 0
18705 #define M_SVID_ID_OFFSET 0xffU
18706 #define V_SVID_ID_OFFSET(x) ((x) << S_SVID_ID_OFFSET)
18707 #define G_SVID_ID_OFFSET(x) (((x) >> S_SVID_ID_OFFSET) & M_SVID_ID_OFFSET)
18709 #define A_TP_DBG_ESIDE_OP 0x154
18711 #define S_OPT_PARSER_FATAL_CHANNEL0 29
18712 #define V_OPT_PARSER_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL0)
18713 #define F_OPT_PARSER_FATAL_CHANNEL0 V_OPT_PARSER_FATAL_CHANNEL0(1U)
18715 #define S_OPT_PARSER_BUSY_CHANNEL0 28
18716 #define V_OPT_PARSER_BUSY_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL0)
18717 #define F_OPT_PARSER_BUSY_CHANNEL0 V_OPT_PARSER_BUSY_CHANNEL0(1U)
18719 #define S_OPT_PARSER_ITCP_STATE_CHANNEL0 26
18720 #define M_OPT_PARSER_ITCP_STATE_CHANNEL0 0x3U
18721 #define V_OPT_PARSER_ITCP_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL0)
18722 #define G_OPT_PARSER_ITCP_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL0) & M_OPT_PARSER_ITCP_STATE_CHANNEL0)
18724 #define S_OPT_PARSER_OTK_STATE_CHANNEL0 24
18725 #define M_OPT_PARSER_OTK_STATE_CHANNEL0 0x3U
18726 #define V_OPT_PARSER_OTK_STATE_CHANNEL0(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL0)
18727 #define G_OPT_PARSER_OTK_STATE_CHANNEL0(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL0) & M_OPT_PARSER_OTK_STATE_CHANNEL0)
18729 #define S_OPT_PARSER_FATAL_CHANNEL1 21
18730 #define V_OPT_PARSER_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL1)
18731 #define F_OPT_PARSER_FATAL_CHANNEL1 V_OPT_PARSER_FATAL_CHANNEL1(1U)
18733 #define S_OPT_PARSER_BUSY_CHANNEL1 20
18734 #define V_OPT_PARSER_BUSY_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL1)
18735 #define F_OPT_PARSER_BUSY_CHANNEL1 V_OPT_PARSER_BUSY_CHANNEL1(1U)
18737 #define S_OPT_PARSER_ITCP_STATE_CHANNEL1 18
18738 #define M_OPT_PARSER_ITCP_STATE_CHANNEL1 0x3U
18739 #define V_OPT_PARSER_ITCP_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL1)
18740 #define G_OPT_PARSER_ITCP_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL1) & M_OPT_PARSER_ITCP_STATE_CHANNEL1)
18742 #define S_OPT_PARSER_OTK_STATE_CHANNEL1 16
18743 #define M_OPT_PARSER_OTK_STATE_CHANNEL1 0x3U
18744 #define V_OPT_PARSER_OTK_STATE_CHANNEL1(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL1)
18745 #define G_OPT_PARSER_OTK_STATE_CHANNEL1(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL1) & M_OPT_PARSER_OTK_STATE_CHANNEL1)
18747 #define S_OPT_PARSER_FATAL_CHANNEL2 13
18748 #define V_OPT_PARSER_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL2)
18749 #define F_OPT_PARSER_FATAL_CHANNEL2 V_OPT_PARSER_FATAL_CHANNEL2(1U)
18751 #define S_OPT_PARSER_BUSY_CHANNEL2 12
18752 #define V_OPT_PARSER_BUSY_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL2)
18753 #define F_OPT_PARSER_BUSY_CHANNEL2 V_OPT_PARSER_BUSY_CHANNEL2(1U)
18755 #define S_OPT_PARSER_ITCP_STATE_CHANNEL2 10
18756 #define M_OPT_PARSER_ITCP_STATE_CHANNEL2 0x3U
18757 #define V_OPT_PARSER_ITCP_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL2)
18758 #define G_OPT_PARSER_ITCP_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL2) & M_OPT_PARSER_ITCP_STATE_CHANNEL2)
18760 #define S_OPT_PARSER_OTK_STATE_CHANNEL2 8
18761 #define M_OPT_PARSER_OTK_STATE_CHANNEL2 0x3U
18762 #define V_OPT_PARSER_OTK_STATE_CHANNEL2(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL2)
18763 #define G_OPT_PARSER_OTK_STATE_CHANNEL2(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL2) & M_OPT_PARSER_OTK_STATE_CHANNEL2)
18765 #define S_OPT_PARSER_FATAL_CHANNEL3 5
18766 #define V_OPT_PARSER_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_FATAL_CHANNEL3)
18767 #define F_OPT_PARSER_FATAL_CHANNEL3 V_OPT_PARSER_FATAL_CHANNEL3(1U)
18769 #define S_OPT_PARSER_BUSY_CHANNEL3 4
18770 #define V_OPT_PARSER_BUSY_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_CHANNEL3)
18771 #define F_OPT_PARSER_BUSY_CHANNEL3 V_OPT_PARSER_BUSY_CHANNEL3(1U)
18773 #define S_OPT_PARSER_ITCP_STATE_CHANNEL3 2
18774 #define M_OPT_PARSER_ITCP_STATE_CHANNEL3 0x3U
18775 #define V_OPT_PARSER_ITCP_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_ITCP_STATE_CHANNEL3)
18776 #define G_OPT_PARSER_ITCP_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_ITCP_STATE_CHANNEL3) & M_OPT_PARSER_ITCP_STATE_CHANNEL3)
18778 #define S_OPT_PARSER_OTK_STATE_CHANNEL3 0
18779 #define M_OPT_PARSER_OTK_STATE_CHANNEL3 0x3U
18780 #define V_OPT_PARSER_OTK_STATE_CHANNEL3(x) ((x) << S_OPT_PARSER_OTK_STATE_CHANNEL3)
18781 #define G_OPT_PARSER_OTK_STATE_CHANNEL3(x) (((x) >> S_OPT_PARSER_OTK_STATE_CHANNEL3) & M_OPT_PARSER_OTK_STATE_CHANNEL3)
18783 #define A_TP_DBG_ESIDE_OP_ALT 0x155
18785 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL0 29
18786 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL0)
18787 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL0 V_OPT_PARSER_PSTATE_FATAL_CHANNEL0(1U)
18789 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0 24
18790 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0 0x1fU
18791 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0)
18792 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL0(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL0) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL0)
18794 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL1 21
18795 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL1)
18796 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL1 V_OPT_PARSER_PSTATE_FATAL_CHANNEL1(1U)
18798 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1 16
18799 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1 0x1fU
18800 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1)
18801 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL1(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL1) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL1)
18803 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL2 13
18804 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL2)
18805 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL2 V_OPT_PARSER_PSTATE_FATAL_CHANNEL2(1U)
18807 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2 8
18808 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2 0x1fU
18809 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2)
18810 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL2(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL2) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL2)
18812 #define S_OPT_PARSER_PSTATE_FATAL_CHANNEL3 5
18813 #define V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_FATAL_CHANNEL3)
18814 #define F_OPT_PARSER_PSTATE_FATAL_CHANNEL3 V_OPT_PARSER_PSTATE_FATAL_CHANNEL3(1U)
18816 #define S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3 0
18817 #define M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3 0x1fU
18818 #define V_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) ((x) << S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3)
18819 #define G_OPT_PARSER_PSTATE_ERRNO_CHANNEL3(x) (((x) >> S_OPT_PARSER_PSTATE_ERRNO_CHANNEL3) & M_OPT_PARSER_PSTATE_ERRNO_CHANNEL3)
18821 #define A_TP_DBG_ESIDE_OP_BUSY 0x156
18823 #define S_OPT_PARSER_BUSY_VEC_CHANNEL3 24
18824 #define M_OPT_PARSER_BUSY_VEC_CHANNEL3 0xffU
18825 #define V_OPT_PARSER_BUSY_VEC_CHANNEL3(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL3)
18826 #define G_OPT_PARSER_BUSY_VEC_CHANNEL3(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL3) & M_OPT_PARSER_BUSY_VEC_CHANNEL3)
18828 #define S_OPT_PARSER_BUSY_VEC_CHANNEL2 16
18829 #define M_OPT_PARSER_BUSY_VEC_CHANNEL2 0xffU
18830 #define V_OPT_PARSER_BUSY_VEC_CHANNEL2(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL2)
18831 #define G_OPT_PARSER_BUSY_VEC_CHANNEL2(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL2) & M_OPT_PARSER_BUSY_VEC_CHANNEL2)
18833 #define S_OPT_PARSER_BUSY_VEC_CHANNEL1 8
18834 #define M_OPT_PARSER_BUSY_VEC_CHANNEL1 0xffU
18835 #define V_OPT_PARSER_BUSY_VEC_CHANNEL1(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL1)
18836 #define G_OPT_PARSER_BUSY_VEC_CHANNEL1(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL1) & M_OPT_PARSER_BUSY_VEC_CHANNEL1)
18838 #define S_OPT_PARSER_BUSY_VEC_CHANNEL0 0
18839 #define M_OPT_PARSER_BUSY_VEC_CHANNEL0 0xffU
18840 #define V_OPT_PARSER_BUSY_VEC_CHANNEL0(x) ((x) << S_OPT_PARSER_BUSY_VEC_CHANNEL0)
18841 #define G_OPT_PARSER_BUSY_VEC_CHANNEL0(x) (((x) >> S_OPT_PARSER_BUSY_VEC_CHANNEL0) & M_OPT_PARSER_BUSY_VEC_CHANNEL0)
18843 #define A_TP_DBG_ESIDE_OP_COOKIE 0x157
18845 #define S_OPT_PARSER_COOKIE_CHANNEL3 24
18846 #define M_OPT_PARSER_COOKIE_CHANNEL3 0xffU
18847 #define V_OPT_PARSER_COOKIE_CHANNEL3(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL3)
18848 #define G_OPT_PARSER_COOKIE_CHANNEL3(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL3) & M_OPT_PARSER_COOKIE_CHANNEL3)
18850 #define S_OPT_PARSER_COOKIE_CHANNEL2 16
18851 #define M_OPT_PARSER_COOKIE_CHANNEL2 0xffU
18852 #define V_OPT_PARSER_COOKIE_CHANNEL2(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL2)
18853 #define G_OPT_PARSER_COOKIE_CHANNEL2(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL2) & M_OPT_PARSER_COOKIE_CHANNEL2)
18855 #define S_OPT_PARSER_COOKIE_CHANNEL1 8
18856 #define M_OPT_PARSER_COOKIE_CHANNEL1 0xffU
18857 #define V_OPT_PARSER_COOKIE_CHANNEL1(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL1)
18858 #define G_OPT_PARSER_COOKIE_CHANNEL1(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL1) & M_OPT_PARSER_COOKIE_CHANNEL1)
18860 #define S_OPT_PARSER_COOKIE_CHANNEL0 0
18861 #define M_OPT_PARSER_COOKIE_CHANNEL0 0xffU
18862 #define V_OPT_PARSER_COOKIE_CHANNEL0(x) ((x) << S_OPT_PARSER_COOKIE_CHANNEL0)
18863 #define G_OPT_PARSER_COOKIE_CHANNEL0(x) (((x) >> S_OPT_PARSER_COOKIE_CHANNEL0) & M_OPT_PARSER_COOKIE_CHANNEL0)
18865 #define A_TP_DBG_CSIDE_RX0 0x230
18867 #define S_CRXSOPCNT 28
18868 #define M_CRXSOPCNT 0xfU
18869 #define V_CRXSOPCNT(x) ((x) << S_CRXSOPCNT)
18870 #define G_CRXSOPCNT(x) (((x) >> S_CRXSOPCNT) & M_CRXSOPCNT)
18872 #define S_CRXEOPCNT 24
18873 #define M_CRXEOPCNT 0xfU
18874 #define V_CRXEOPCNT(x) ((x) << S_CRXEOPCNT)
18875 #define G_CRXEOPCNT(x) (((x) >> S_CRXEOPCNT) & M_CRXEOPCNT)
18877 #define S_CRXPLDSOPCNT 20
18878 #define M_CRXPLDSOPCNT 0xfU
18879 #define V_CRXPLDSOPCNT(x) ((x) << S_CRXPLDSOPCNT)
18880 #define G_CRXPLDSOPCNT(x) (((x) >> S_CRXPLDSOPCNT) & M_CRXPLDSOPCNT)
18882 #define S_CRXPLDEOPCNT 16
18883 #define M_CRXPLDEOPCNT 0xfU
18884 #define V_CRXPLDEOPCNT(x) ((x) << S_CRXPLDEOPCNT)
18885 #define G_CRXPLDEOPCNT(x) (((x) >> S_CRXPLDEOPCNT) & M_CRXPLDEOPCNT)
18887 #define S_CRXARBSOPCNT 12
18888 #define M_CRXARBSOPCNT 0xfU
18889 #define V_CRXARBSOPCNT(x) ((x) << S_CRXARBSOPCNT)
18890 #define G_CRXARBSOPCNT(x) (((x) >> S_CRXARBSOPCNT) & M_CRXARBSOPCNT)
18892 #define S_CRXARBEOPCNT 8
18893 #define M_CRXARBEOPCNT 0xfU
18894 #define V_CRXARBEOPCNT(x) ((x) << S_CRXARBEOPCNT)
18895 #define G_CRXARBEOPCNT(x) (((x) >> S_CRXARBEOPCNT) & M_CRXARBEOPCNT)
18897 #define S_CRXCPLSOPCNT 4
18898 #define M_CRXCPLSOPCNT 0xfU
18899 #define V_CRXCPLSOPCNT(x) ((x) << S_CRXCPLSOPCNT)
18900 #define G_CRXCPLSOPCNT(x) (((x) >> S_CRXCPLSOPCNT) & M_CRXCPLSOPCNT)
18902 #define S_CRXCPLEOPCNT 0
18903 #define M_CRXCPLEOPCNT 0xfU
18904 #define V_CRXCPLEOPCNT(x) ((x) << S_CRXCPLEOPCNT)
18905 #define G_CRXCPLEOPCNT(x) (((x) >> S_CRXCPLEOPCNT) & M_CRXCPLEOPCNT)
18907 #define A_TP_DBG_CSIDE_RX1 0x231
18908 #define A_TP_DBG_CSIDE_RX2 0x232
18909 #define A_TP_DBG_CSIDE_RX3 0x233
18910 #define A_TP_DBG_CSIDE_TX0 0x234
18912 #define S_TXSOPCNT 28
18913 #define M_TXSOPCNT 0xfU
18914 #define V_TXSOPCNT(x) ((x) << S_TXSOPCNT)
18915 #define G_TXSOPCNT(x) (((x) >> S_TXSOPCNT) & M_TXSOPCNT)
18917 #define S_TXEOPCNT 24
18918 #define M_TXEOPCNT 0xfU
18919 #define V_TXEOPCNT(x) ((x) << S_TXEOPCNT)
18920 #define G_TXEOPCNT(x) (((x) >> S_TXEOPCNT) & M_TXEOPCNT)
18922 #define S_TXPLDSOPCNT 20
18923 #define M_TXPLDSOPCNT 0xfU
18924 #define V_TXPLDSOPCNT(x) ((x) << S_TXPLDSOPCNT)
18925 #define G_TXPLDSOPCNT(x) (((x) >> S_TXPLDSOPCNT) & M_TXPLDSOPCNT)
18927 #define S_TXPLDEOPCNT 16
18928 #define M_TXPLDEOPCNT 0xfU
18929 #define V_TXPLDEOPCNT(x) ((x) << S_TXPLDEOPCNT)
18930 #define G_TXPLDEOPCNT(x) (((x) >> S_TXPLDEOPCNT) & M_TXPLDEOPCNT)
18932 #define S_TXARBSOPCNT 12
18933 #define M_TXARBSOPCNT 0xfU
18934 #define V_TXARBSOPCNT(x) ((x) << S_TXARBSOPCNT)
18935 #define G_TXARBSOPCNT(x) (((x) >> S_TXARBSOPCNT) & M_TXARBSOPCNT)
18937 #define S_TXARBEOPCNT 8
18938 #define M_TXARBEOPCNT 0xfU
18939 #define V_TXARBEOPCNT(x) ((x) << S_TXARBEOPCNT)
18940 #define G_TXARBEOPCNT(x) (((x) >> S_TXARBEOPCNT) & M_TXARBEOPCNT)
18942 #define S_TXCPLSOPCNT 4
18943 #define M_TXCPLSOPCNT 0xfU
18944 #define V_TXCPLSOPCNT(x) ((x) << S_TXCPLSOPCNT)
18945 #define G_TXCPLSOPCNT(x) (((x) >> S_TXCPLSOPCNT) & M_TXCPLSOPCNT)
18947 #define S_TXCPLEOPCNT 0
18948 #define M_TXCPLEOPCNT 0xfU
18949 #define V_TXCPLEOPCNT(x) ((x) << S_TXCPLEOPCNT)
18950 #define G_TXCPLEOPCNT(x) (((x) >> S_TXCPLEOPCNT) & M_TXCPLEOPCNT)
18952 #define A_TP_DBG_CSIDE_TX1 0x235
18953 #define A_TP_DBG_CSIDE_TX2 0x236
18954 #define A_TP_DBG_CSIDE_TX3 0x237
18955 #define A_TP_DBG_CSIDE_FIFO0 0x238
18957 #define S_PLD_RXZEROP_SRDY1 31
18958 #define V_PLD_RXZEROP_SRDY1(x) ((x) << S_PLD_RXZEROP_SRDY1)
18959 #define F_PLD_RXZEROP_SRDY1 V_PLD_RXZEROP_SRDY1(1U)
18961 #define S_PLD_RXZEROP_DRDY1 30
18962 #define V_PLD_RXZEROP_DRDY1(x) ((x) << S_PLD_RXZEROP_DRDY1)
18963 #define F_PLD_RXZEROP_DRDY1 V_PLD_RXZEROP_DRDY1(1U)
18965 #define S_PLD_TXZEROP_SRDY1 29
18966 #define V_PLD_TXZEROP_SRDY1(x) ((x) << S_PLD_TXZEROP_SRDY1)
18967 #define F_PLD_TXZEROP_SRDY1 V_PLD_TXZEROP_SRDY1(1U)
18969 #define S_PLD_TXZEROP_DRDY1 28
18970 #define V_PLD_TXZEROP_DRDY1(x) ((x) << S_PLD_TXZEROP_DRDY1)
18971 #define F_PLD_TXZEROP_DRDY1 V_PLD_TXZEROP_DRDY1(1U)
18973 #define S_PLD_TX_SRDY1 27
18974 #define V_PLD_TX_SRDY1(x) ((x) << S_PLD_TX_SRDY1)
18975 #define F_PLD_TX_SRDY1 V_PLD_TX_SRDY1(1U)
18977 #define S_PLD_TX_DRDY1 26
18978 #define V_PLD_TX_DRDY1(x) ((x) << S_PLD_TX_DRDY1)
18979 #define F_PLD_TX_DRDY1 V_PLD_TX_DRDY1(1U)
18981 #define S_ERROR_SRDY1 25
18982 #define V_ERROR_SRDY1(x) ((x) << S_ERROR_SRDY1)
18983 #define F_ERROR_SRDY1 V_ERROR_SRDY1(1U)
18985 #define S_ERROR_DRDY1 24
18986 #define V_ERROR_DRDY1(x) ((x) << S_ERROR_DRDY1)
18987 #define F_ERROR_DRDY1 V_ERROR_DRDY1(1U)
18989 #define S_DB_VLD1 23
18990 #define V_DB_VLD1(x) ((x) << S_DB_VLD1)
18991 #define F_DB_VLD1 V_DB_VLD1(1U)
18993 #define S_DB_GT1 22
18994 #define V_DB_GT1(x) ((x) << S_DB_GT1)
18995 #define F_DB_GT1 V_DB_GT1(1U)
18997 #define S_TXVALID1 21
18998 #define V_TXVALID1(x) ((x) << S_TXVALID1)
18999 #define F_TXVALID1 V_TXVALID1(1U)
19001 #define S_TXFULL1 20
19002 #define V_TXFULL1(x) ((x) << S_TXFULL1)
19003 #define F_TXFULL1 V_TXFULL1(1U)
19005 #define S_PLD_TXVALID1 19
19006 #define V_PLD_TXVALID1(x) ((x) << S_PLD_TXVALID1)
19007 #define F_PLD_TXVALID1 V_PLD_TXVALID1(1U)
19009 #define S_PLD_TXFULL1 18
19010 #define V_PLD_TXFULL1(x) ((x) << S_PLD_TXFULL1)
19011 #define F_PLD_TXFULL1 V_PLD_TXFULL1(1U)
19013 #define S_CPL5_TXVALID1 17
19014 #define V_CPL5_TXVALID1(x) ((x) << S_CPL5_TXVALID1)
19015 #define F_CPL5_TXVALID1 V_CPL5_TXVALID1(1U)
19017 #define S_CPL5_TXFULL1 16
19018 #define V_CPL5_TXFULL1(x) ((x) << S_CPL5_TXFULL1)
19019 #define F_CPL5_TXFULL1 V_CPL5_TXFULL1(1U)
19021 #define S_PLD_RXZEROP_SRDY0 15
19022 #define V_PLD_RXZEROP_SRDY0(x) ((x) << S_PLD_RXZEROP_SRDY0)
19023 #define F_PLD_RXZEROP_SRDY0 V_PLD_RXZEROP_SRDY0(1U)
19025 #define S_PLD_RXZEROP_DRDY0 14
19026 #define V_PLD_RXZEROP_DRDY0(x) ((x) << S_PLD_RXZEROP_DRDY0)
19027 #define F_PLD_RXZEROP_DRDY0 V_PLD_RXZEROP_DRDY0(1U)
19029 #define S_PLD_TXZEROP_SRDY0 13
19030 #define V_PLD_TXZEROP_SRDY0(x) ((x) << S_PLD_TXZEROP_SRDY0)
19031 #define F_PLD_TXZEROP_SRDY0 V_PLD_TXZEROP_SRDY0(1U)
19033 #define S_PLD_TXZEROP_DRDY0 12
19034 #define V_PLD_TXZEROP_DRDY0(x) ((x) << S_PLD_TXZEROP_DRDY0)
19035 #define F_PLD_TXZEROP_DRDY0 V_PLD_TXZEROP_DRDY0(1U)
19037 #define S_PLD_TX_SRDY0 11
19038 #define V_PLD_TX_SRDY0(x) ((x) << S_PLD_TX_SRDY0)
19039 #define F_PLD_TX_SRDY0 V_PLD_TX_SRDY0(1U)
19041 #define S_PLD_TX_DRDY0 10
19042 #define V_PLD_TX_DRDY0(x) ((x) << S_PLD_TX_DRDY0)
19043 #define F_PLD_TX_DRDY0 V_PLD_TX_DRDY0(1U)
19045 #define S_ERROR_SRDY0 9
19046 #define V_ERROR_SRDY0(x) ((x) << S_ERROR_SRDY0)
19047 #define F_ERROR_SRDY0 V_ERROR_SRDY0(1U)
19049 #define S_ERROR_DRDY0 8
19050 #define V_ERROR_DRDY0(x) ((x) << S_ERROR_DRDY0)
19051 #define F_ERROR_DRDY0 V_ERROR_DRDY0(1U)
19053 #define S_DB_VLD0 7
19054 #define V_DB_VLD0(x) ((x) << S_DB_VLD0)
19055 #define F_DB_VLD0 V_DB_VLD0(1U)
19058 #define V_DB_GT0(x) ((x) << S_DB_GT0)
19059 #define F_DB_GT0 V_DB_GT0(1U)
19061 #define S_TXVALID0 5
19062 #define V_TXVALID0(x) ((x) << S_TXVALID0)
19063 #define F_TXVALID0 V_TXVALID0(1U)
19065 #define S_TXFULL0 4
19066 #define V_TXFULL0(x) ((x) << S_TXFULL0)
19067 #define F_TXFULL0 V_TXFULL0(1U)
19069 #define S_PLD_TXVALID0 3
19070 #define V_PLD_TXVALID0(x) ((x) << S_PLD_TXVALID0)
19071 #define F_PLD_TXVALID0 V_PLD_TXVALID0(1U)
19073 #define S_PLD_TXFULL0 2
19074 #define V_PLD_TXFULL0(x) ((x) << S_PLD_TXFULL0)
19075 #define F_PLD_TXFULL0 V_PLD_TXFULL0(1U)
19077 #define S_CPL5_TXVALID0 1
19078 #define V_CPL5_TXVALID0(x) ((x) << S_CPL5_TXVALID0)
19079 #define F_CPL5_TXVALID0 V_CPL5_TXVALID0(1U)
19081 #define S_CPL5_TXFULL0 0
19082 #define V_CPL5_TXFULL0(x) ((x) << S_CPL5_TXFULL0)
19083 #define F_CPL5_TXFULL0 V_CPL5_TXFULL0(1U)
19085 #define A_TP_DBG_CSIDE_FIFO1 0x239
19087 #define S_PLD_RXZEROP_SRDY3 31
19088 #define V_PLD_RXZEROP_SRDY3(x) ((x) << S_PLD_RXZEROP_SRDY3)
19089 #define F_PLD_RXZEROP_SRDY3 V_PLD_RXZEROP_SRDY3(1U)
19091 #define S_PLD_RXZEROP_DRDY3 30
19092 #define V_PLD_RXZEROP_DRDY3(x) ((x) << S_PLD_RXZEROP_DRDY3)
19093 #define F_PLD_RXZEROP_DRDY3 V_PLD_RXZEROP_DRDY3(1U)
19095 #define S_PLD_TXZEROP_SRDY3 29
19096 #define V_PLD_TXZEROP_SRDY3(x) ((x) << S_PLD_TXZEROP_SRDY3)
19097 #define F_PLD_TXZEROP_SRDY3 V_PLD_TXZEROP_SRDY3(1U)
19099 #define S_PLD_TXZEROP_DRDY3 28
19100 #define V_PLD_TXZEROP_DRDY3(x) ((x) << S_PLD_TXZEROP_DRDY3)
19101 #define F_PLD_TXZEROP_DRDY3 V_PLD_TXZEROP_DRDY3(1U)
19103 #define S_PLD_TX_SRDY3 27
19104 #define V_PLD_TX_SRDY3(x) ((x) << S_PLD_TX_SRDY3)
19105 #define F_PLD_TX_SRDY3 V_PLD_TX_SRDY3(1U)
19107 #define S_PLD_TX_DRDY3 26
19108 #define V_PLD_TX_DRDY3(x) ((x) << S_PLD_TX_DRDY3)
19109 #define F_PLD_TX_DRDY3 V_PLD_TX_DRDY3(1U)
19111 #define S_ERROR_SRDY3 25
19112 #define V_ERROR_SRDY3(x) ((x) << S_ERROR_SRDY3)
19113 #define F_ERROR_SRDY3 V_ERROR_SRDY3(1U)
19115 #define S_ERROR_DRDY3 24
19116 #define V_ERROR_DRDY3(x) ((x) << S_ERROR_DRDY3)
19117 #define F_ERROR_DRDY3 V_ERROR_DRDY3(1U)
19119 #define S_DB_VLD3 23
19120 #define V_DB_VLD3(x) ((x) << S_DB_VLD3)
19121 #define F_DB_VLD3 V_DB_VLD3(1U)
19123 #define S_DB_GT3 22
19124 #define V_DB_GT3(x) ((x) << S_DB_GT3)
19125 #define F_DB_GT3 V_DB_GT3(1U)
19127 #define S_TXVALID3 21
19128 #define V_TXVALID3(x) ((x) << S_TXVALID3)
19129 #define F_TXVALID3 V_TXVALID3(1U)
19131 #define S_TXFULL3 20
19132 #define V_TXFULL3(x) ((x) << S_TXFULL3)
19133 #define F_TXFULL3 V_TXFULL3(1U)
19135 #define S_PLD_TXVALID3 19
19136 #define V_PLD_TXVALID3(x) ((x) << S_PLD_TXVALID3)
19137 #define F_PLD_TXVALID3 V_PLD_TXVALID3(1U)
19139 #define S_PLD_TXFULL3 18
19140 #define V_PLD_TXFULL3(x) ((x) << S_PLD_TXFULL3)
19141 #define F_PLD_TXFULL3 V_PLD_TXFULL3(1U)
19143 #define S_CPL5_TXVALID3 17
19144 #define V_CPL5_TXVALID3(x) ((x) << S_CPL5_TXVALID3)
19145 #define F_CPL5_TXVALID3 V_CPL5_TXVALID3(1U)
19147 #define S_CPL5_TXFULL3 16
19148 #define V_CPL5_TXFULL3(x) ((x) << S_CPL5_TXFULL3)
19149 #define F_CPL5_TXFULL3 V_CPL5_TXFULL3(1U)
19151 #define S_PLD_RXZEROP_SRDY2 15
19152 #define V_PLD_RXZEROP_SRDY2(x) ((x) << S_PLD_RXZEROP_SRDY2)
19153 #define F_PLD_RXZEROP_SRDY2 V_PLD_RXZEROP_SRDY2(1U)
19155 #define S_PLD_RXZEROP_DRDY2 14
19156 #define V_PLD_RXZEROP_DRDY2(x) ((x) << S_PLD_RXZEROP_DRDY2)
19157 #define F_PLD_RXZEROP_DRDY2 V_PLD_RXZEROP_DRDY2(1U)
19159 #define S_PLD_TXZEROP_SRDY2 13
19160 #define V_PLD_TXZEROP_SRDY2(x) ((x) << S_PLD_TXZEROP_SRDY2)
19161 #define F_PLD_TXZEROP_SRDY2 V_PLD_TXZEROP_SRDY2(1U)
19163 #define S_PLD_TXZEROP_DRDY2 12
19164 #define V_PLD_TXZEROP_DRDY2(x) ((x) << S_PLD_TXZEROP_DRDY2)
19165 #define F_PLD_TXZEROP_DRDY2 V_PLD_TXZEROP_DRDY2(1U)
19167 #define S_PLD_TX_SRDY2 11
19168 #define V_PLD_TX_SRDY2(x) ((x) << S_PLD_TX_SRDY2)
19169 #define F_PLD_TX_SRDY2 V_PLD_TX_SRDY2(1U)
19171 #define S_PLD_TX_DRDY2 10
19172 #define V_PLD_TX_DRDY2(x) ((x) << S_PLD_TX_DRDY2)
19173 #define F_PLD_TX_DRDY2 V_PLD_TX_DRDY2(1U)
19175 #define S_ERROR_SRDY2 9
19176 #define V_ERROR_SRDY2(x) ((x) << S_ERROR_SRDY2)
19177 #define F_ERROR_SRDY2 V_ERROR_SRDY2(1U)
19179 #define S_ERROR_DRDY2 8
19180 #define V_ERROR_DRDY2(x) ((x) << S_ERROR_DRDY2)
19181 #define F_ERROR_DRDY2 V_ERROR_DRDY2(1U)
19183 #define S_DB_VLD2 7
19184 #define V_DB_VLD2(x) ((x) << S_DB_VLD2)
19185 #define F_DB_VLD2 V_DB_VLD2(1U)
19188 #define V_DB_GT2(x) ((x) << S_DB_GT2)
19189 #define F_DB_GT2 V_DB_GT2(1U)
19191 #define S_TXVALID2 5
19192 #define V_TXVALID2(x) ((x) << S_TXVALID2)
19193 #define F_TXVALID2 V_TXVALID2(1U)
19195 #define S_TXFULL2 4
19196 #define V_TXFULL2(x) ((x) << S_TXFULL2)
19197 #define F_TXFULL2 V_TXFULL2(1U)
19199 #define S_PLD_TXVALID2 3
19200 #define V_PLD_TXVALID2(x) ((x) << S_PLD_TXVALID2)
19201 #define F_PLD_TXVALID2 V_PLD_TXVALID2(1U)
19203 #define S_PLD_TXFULL2 2
19204 #define V_PLD_TXFULL2(x) ((x) << S_PLD_TXFULL2)
19205 #define F_PLD_TXFULL2 V_PLD_TXFULL2(1U)
19207 #define S_CPL5_TXVALID2 1
19208 #define V_CPL5_TXVALID2(x) ((x) << S_CPL5_TXVALID2)
19209 #define F_CPL5_TXVALID2 V_CPL5_TXVALID2(1U)
19211 #define S_CPL5_TXFULL2 0
19212 #define V_CPL5_TXFULL2(x) ((x) << S_CPL5_TXFULL2)
19213 #define F_CPL5_TXFULL2 V_CPL5_TXFULL2(1U)
19215 #define A_TP_DBG_CSIDE_DISP0 0x23a
19217 #define S_CPL5RXVALID 27
19218 #define V_CPL5RXVALID(x) ((x) << S_CPL5RXVALID)
19219 #define F_CPL5RXVALID V_CPL5RXVALID(1U)
19221 #define S_CSTATIC1 26
19222 #define V_CSTATIC1(x) ((x) << S_CSTATIC1)
19223 #define F_CSTATIC1 V_CSTATIC1(1U)
19225 #define S_CSTATIC2 25
19226 #define V_CSTATIC2(x) ((x) << S_CSTATIC2)
19227 #define F_CSTATIC2 V_CSTATIC2(1U)
19229 #define S_PLD_RXZEROP 24
19230 #define V_PLD_RXZEROP(x) ((x) << S_PLD_RXZEROP)
19231 #define F_PLD_RXZEROP V_PLD_RXZEROP(1U)
19233 #define S_DDP_IN_PROGRESS 23
19234 #define V_DDP_IN_PROGRESS(x) ((x) << S_DDP_IN_PROGRESS)
19235 #define F_DDP_IN_PROGRESS V_DDP_IN_PROGRESS(1U)
19237 #define S_PLD_RXZEROP_SRDY 22
19238 #define V_PLD_RXZEROP_SRDY(x) ((x) << S_PLD_RXZEROP_SRDY)
19239 #define F_PLD_RXZEROP_SRDY V_PLD_RXZEROP_SRDY(1U)
19241 #define S_CSTATIC3 21
19242 #define V_CSTATIC3(x) ((x) << S_CSTATIC3)
19243 #define F_CSTATIC3 V_CSTATIC3(1U)
19245 #define S_DDP_DRDY 20
19246 #define V_DDP_DRDY(x) ((x) << S_DDP_DRDY)
19247 #define F_DDP_DRDY V_DDP_DRDY(1U)
19249 #define S_DDP_PRE_STATE 17
19250 #define M_DDP_PRE_STATE 0x7U
19251 #define V_DDP_PRE_STATE(x) ((x) << S_DDP_PRE_STATE)
19252 #define G_DDP_PRE_STATE(x) (((x) >> S_DDP_PRE_STATE) & M_DDP_PRE_STATE)
19254 #define S_DDP_SRDY 16
19255 #define V_DDP_SRDY(x) ((x) << S_DDP_SRDY)
19256 #define F_DDP_SRDY V_DDP_SRDY(1U)
19258 #define S_DDP_MSG_CODE 12
19259 #define M_DDP_MSG_CODE 0xfU
19260 #define V_DDP_MSG_CODE(x) ((x) << S_DDP_MSG_CODE)
19261 #define G_DDP_MSG_CODE(x) (((x) >> S_DDP_MSG_CODE) & M_DDP_MSG_CODE)
19263 #define S_CPL5_SOCP_CNT 10
19264 #define M_CPL5_SOCP_CNT 0x3U
19265 #define V_CPL5_SOCP_CNT(x) ((x) << S_CPL5_SOCP_CNT)
19266 #define G_CPL5_SOCP_CNT(x) (((x) >> S_CPL5_SOCP_CNT) & M_CPL5_SOCP_CNT)
19268 #define S_CSTATIC4 4
19269 #define M_CSTATIC4 0x3fU
19270 #define V_CSTATIC4(x) ((x) << S_CSTATIC4)
19271 #define G_CSTATIC4(x) (((x) >> S_CSTATIC4) & M_CSTATIC4)
19273 #define S_CMD_SEL 1
19274 #define V_CMD_SEL(x) ((x) << S_CMD_SEL)
19275 #define F_CMD_SEL V_CMD_SEL(1U)
19277 #define S_CPL5RXFULL 26
19278 #define V_CPL5RXFULL(x) ((x) << S_CPL5RXFULL)
19279 #define F_CPL5RXFULL V_CPL5RXFULL(1U)
19281 #define S_PLD2XRXVALID 23
19282 #define V_PLD2XRXVALID(x) ((x) << S_PLD2XRXVALID)
19283 #define F_PLD2XRXVALID V_PLD2XRXVALID(1U)
19285 #define S_DDPSTATE 16
19286 #define M_DDPSTATE 0x1fU
19287 #define V_DDPSTATE(x) ((x) << S_DDPSTATE)
19288 #define G_DDPSTATE(x) (((x) >> S_DDPSTATE) & M_DDPSTATE)
19290 #define S_DDPMSGCODE 12
19291 #define M_DDPMSGCODE 0xfU
19292 #define V_DDPMSGCODE(x) ((x) << S_DDPMSGCODE)
19293 #define G_DDPMSGCODE(x) (((x) >> S_DDPMSGCODE) & M_DDPMSGCODE)
19295 #define S_CPL5SOCPCNT 8
19296 #define M_CPL5SOCPCNT 0xfU
19297 #define V_CPL5SOCPCNT(x) ((x) << S_CPL5SOCPCNT)
19298 #define G_CPL5SOCPCNT(x) (((x) >> S_CPL5SOCPCNT) & M_CPL5SOCPCNT)
19300 #define S_PLDRXZEROPCNT 4
19301 #define M_PLDRXZEROPCNT 0xfU
19302 #define V_PLDRXZEROPCNT(x) ((x) << S_PLDRXZEROPCNT)
19303 #define G_PLDRXZEROPCNT(x) (((x) >> S_PLDRXZEROPCNT) & M_PLDRXZEROPCNT)
19305 #define S_TXFRMERR2 3
19306 #define V_TXFRMERR2(x) ((x) << S_TXFRMERR2)
19307 #define F_TXFRMERR2 V_TXFRMERR2(1U)
19309 #define S_TXFRMERR1 2
19310 #define V_TXFRMERR1(x) ((x) << S_TXFRMERR1)
19311 #define F_TXFRMERR1 V_TXFRMERR1(1U)
19313 #define S_TXVALID2X 1
19314 #define V_TXVALID2X(x) ((x) << S_TXVALID2X)
19315 #define F_TXVALID2X V_TXVALID2X(1U)
19317 #define S_TXFULL2X 0
19318 #define V_TXFULL2X(x) ((x) << S_TXFULL2X)
19319 #define F_TXFULL2X V_TXFULL2X(1U)
19321 #define A_TP_DBG_CSIDE_DISP1 0x23b
19322 #define A_TP_DBG_CSIDE_DDP0 0x23c
19324 #define S_DDPMSGLATEST7 28
19325 #define M_DDPMSGLATEST7 0xfU
19326 #define V_DDPMSGLATEST7(x) ((x) << S_DDPMSGLATEST7)
19327 #define G_DDPMSGLATEST7(x) (((x) >> S_DDPMSGLATEST7) & M_DDPMSGLATEST7)
19329 #define S_DDPMSGLATEST6 24
19330 #define M_DDPMSGLATEST6 0xfU
19331 #define V_DDPMSGLATEST6(x) ((x) << S_DDPMSGLATEST6)
19332 #define G_DDPMSGLATEST6(x) (((x) >> S_DDPMSGLATEST6) & M_DDPMSGLATEST6)
19334 #define S_DDPMSGLATEST5 20
19335 #define M_DDPMSGLATEST5 0xfU
19336 #define V_DDPMSGLATEST5(x) ((x) << S_DDPMSGLATEST5)
19337 #define G_DDPMSGLATEST5(x) (((x) >> S_DDPMSGLATEST5) & M_DDPMSGLATEST5)
19339 #define S_DDPMSGLATEST4 16
19340 #define M_DDPMSGLATEST4 0xfU
19341 #define V_DDPMSGLATEST4(x) ((x) << S_DDPMSGLATEST4)
19342 #define G_DDPMSGLATEST4(x) (((x) >> S_DDPMSGLATEST4) & M_DDPMSGLATEST4)
19344 #define S_DDPMSGLATEST3 12
19345 #define M_DDPMSGLATEST3 0xfU
19346 #define V_DDPMSGLATEST3(x) ((x) << S_DDPMSGLATEST3)
19347 #define G_DDPMSGLATEST3(x) (((x) >> S_DDPMSGLATEST3) & M_DDPMSGLATEST3)
19349 #define S_DDPMSGLATEST2 8
19350 #define M_DDPMSGLATEST2 0xfU
19351 #define V_DDPMSGLATEST2(x) ((x) << S_DDPMSGLATEST2)
19352 #define G_DDPMSGLATEST2(x) (((x) >> S_DDPMSGLATEST2) & M_DDPMSGLATEST2)
19354 #define S_DDPMSGLATEST1 4
19355 #define M_DDPMSGLATEST1 0xfU
19356 #define V_DDPMSGLATEST1(x) ((x) << S_DDPMSGLATEST1)
19357 #define G_DDPMSGLATEST1(x) (((x) >> S_DDPMSGLATEST1) & M_DDPMSGLATEST1)
19359 #define S_DDPMSGLATEST0 0
19360 #define M_DDPMSGLATEST0 0xfU
19361 #define V_DDPMSGLATEST0(x) ((x) << S_DDPMSGLATEST0)
19362 #define G_DDPMSGLATEST0(x) (((x) >> S_DDPMSGLATEST0) & M_DDPMSGLATEST0)
19364 #define A_TP_DBG_CSIDE_DDP1 0x23d
19365 #define A_TP_DBG_CSIDE_FRM 0x23e
19367 #define S_CRX2XERROR 28
19368 #define M_CRX2XERROR 0xfU
19369 #define V_CRX2XERROR(x) ((x) << S_CRX2XERROR)
19370 #define G_CRX2XERROR(x) (((x) >> S_CRX2XERROR) & M_CRX2XERROR)
19372 #define S_CPLDTX2XERROR 24
19373 #define M_CPLDTX2XERROR 0xfU
19374 #define V_CPLDTX2XERROR(x) ((x) << S_CPLDTX2XERROR)
19375 #define G_CPLDTX2XERROR(x) (((x) >> S_CPLDTX2XERROR) & M_CPLDTX2XERROR)
19377 #define S_CTXERROR 22
19378 #define M_CTXERROR 0x3U
19379 #define V_CTXERROR(x) ((x) << S_CTXERROR)
19380 #define G_CTXERROR(x) (((x) >> S_CTXERROR) & M_CTXERROR)
19382 #define S_CPLDRXERROR 20
19383 #define M_CPLDRXERROR 0x3U
19384 #define V_CPLDRXERROR(x) ((x) << S_CPLDRXERROR)
19385 #define G_CPLDRXERROR(x) (((x) >> S_CPLDRXERROR) & M_CPLDRXERROR)
19387 #define S_CPLRXERROR 18
19388 #define M_CPLRXERROR 0x3U
19389 #define V_CPLRXERROR(x) ((x) << S_CPLRXERROR)
19390 #define G_CPLRXERROR(x) (((x) >> S_CPLRXERROR) & M_CPLRXERROR)
19392 #define S_CPLTXERROR 16
19393 #define M_CPLTXERROR 0x3U
19394 #define V_CPLTXERROR(x) ((x) << S_CPLTXERROR)
19395 #define G_CPLTXERROR(x) (((x) >> S_CPLTXERROR) & M_CPLTXERROR)
19397 #define S_CPRSERROR 0
19398 #define M_CPRSERROR 0xfU
19399 #define V_CPRSERROR(x) ((x) << S_CPRSERROR)
19400 #define G_CPRSERROR(x) (((x) >> S_CPRSERROR) & M_CPRSERROR)
19402 #define A_TP_DBG_CSIDE_INT 0x23f
19404 #define S_CRXVALID2X 28
19405 #define M_CRXVALID2X 0xfU
19406 #define V_CRXVALID2X(x) ((x) << S_CRXVALID2X)
19407 #define G_CRXVALID2X(x) (((x) >> S_CRXVALID2X) & M_CRXVALID2X)
19409 #define S_CRXAFULL2X 24
19410 #define M_CRXAFULL2X 0xfU
19411 #define V_CRXAFULL2X(x) ((x) << S_CRXAFULL2X)
19412 #define G_CRXAFULL2X(x) (((x) >> S_CRXAFULL2X) & M_CRXAFULL2X)
19414 #define S_CTXVALID2X 22
19415 #define M_CTXVALID2X 0x3U
19416 #define V_CTXVALID2X(x) ((x) << S_CTXVALID2X)
19417 #define G_CTXVALID2X(x) (((x) >> S_CTXVALID2X) & M_CTXVALID2X)
19419 #define S_CTXAFULL2X 20
19420 #define M_CTXAFULL2X 0x3U
19421 #define V_CTXAFULL2X(x) ((x) << S_CTXAFULL2X)
19422 #define G_CTXAFULL2X(x) (((x) >> S_CTXAFULL2X) & M_CTXAFULL2X)
19424 #define S_PLD2X_RXVALID 18
19425 #define M_PLD2X_RXVALID 0x3U
19426 #define V_PLD2X_RXVALID(x) ((x) << S_PLD2X_RXVALID)
19427 #define G_PLD2X_RXVALID(x) (((x) >> S_PLD2X_RXVALID) & M_PLD2X_RXVALID)
19429 #define S_PLD2X_RXAFULL 16
19430 #define M_PLD2X_RXAFULL 0x3U
19431 #define V_PLD2X_RXAFULL(x) ((x) << S_PLD2X_RXAFULL)
19432 #define G_PLD2X_RXAFULL(x) (((x) >> S_PLD2X_RXAFULL) & M_PLD2X_RXAFULL)
19434 #define S_CSIDE_DDP_VALID 14
19435 #define M_CSIDE_DDP_VALID 0x3U
19436 #define V_CSIDE_DDP_VALID(x) ((x) << S_CSIDE_DDP_VALID)
19437 #define G_CSIDE_DDP_VALID(x) (((x) >> S_CSIDE_DDP_VALID) & M_CSIDE_DDP_VALID)
19439 #define S_DDP_AFULL 12
19440 #define M_DDP_AFULL 0x3U
19441 #define V_DDP_AFULL(x) ((x) << S_DDP_AFULL)
19442 #define G_DDP_AFULL(x) (((x) >> S_DDP_AFULL) & M_DDP_AFULL)
19444 #define S_TRC_RXVALID 11
19445 #define V_TRC_RXVALID(x) ((x) << S_TRC_RXVALID)
19446 #define F_TRC_RXVALID V_TRC_RXVALID(1U)
19448 #define S_TRC_RXFULL 10
19449 #define V_TRC_RXFULL(x) ((x) << S_TRC_RXFULL)
19450 #define F_TRC_RXFULL V_TRC_RXFULL(1U)
19452 #define S_CPL5_TXVALID 9
19453 #define V_CPL5_TXVALID(x) ((x) << S_CPL5_TXVALID)
19454 #define F_CPL5_TXVALID V_CPL5_TXVALID(1U)
19456 #define S_CPL5_TXFULL 8
19457 #define V_CPL5_TXFULL(x) ((x) << S_CPL5_TXFULL)
19458 #define F_CPL5_TXFULL V_CPL5_TXFULL(1U)
19460 #define S_PLD2X_TXVALID 4
19461 #define M_PLD2X_TXVALID 0xfU
19462 #define V_PLD2X_TXVALID(x) ((x) << S_PLD2X_TXVALID)
19463 #define G_PLD2X_TXVALID(x) (((x) >> S_PLD2X_TXVALID) & M_PLD2X_TXVALID)
19465 #define S_PLD2X_TXAFULL 0
19466 #define M_PLD2X_TXAFULL 0xfU
19467 #define V_PLD2X_TXAFULL(x) ((x) << S_PLD2X_TXAFULL)
19468 #define G_PLD2X_TXAFULL(x) (((x) >> S_PLD2X_TXAFULL) & M_PLD2X_TXAFULL)
19470 #define A_TP_CHDR_CONFIG 0x240
19472 #define S_CH1HIGH 24
19473 #define M_CH1HIGH 0xffU
19474 #define V_CH1HIGH(x) ((x) << S_CH1HIGH)
19475 #define G_CH1HIGH(x) (((x) >> S_CH1HIGH) & M_CH1HIGH)
19477 #define S_CH1LOW 16
19478 #define M_CH1LOW 0xffU
19479 #define V_CH1LOW(x) ((x) << S_CH1LOW)
19480 #define G_CH1LOW(x) (((x) >> S_CH1LOW) & M_CH1LOW)
19482 #define S_CH0HIGH 8
19483 #define M_CH0HIGH 0xffU
19484 #define V_CH0HIGH(x) ((x) << S_CH0HIGH)
19485 #define G_CH0HIGH(x) (((x) >> S_CH0HIGH) & M_CH0HIGH)
19488 #define M_CH0LOW 0xffU
19489 #define V_CH0LOW(x) ((x) << S_CH0LOW)
19490 #define G_CH0LOW(x) (((x) >> S_CH0LOW) & M_CH0LOW)
19492 #define A_TP_UTRN_CONFIG 0x241
19494 #define S_CH2FIFOLIMIT 16
19495 #define M_CH2FIFOLIMIT 0xffU
19496 #define V_CH2FIFOLIMIT(x) ((x) << S_CH2FIFOLIMIT)
19497 #define G_CH2FIFOLIMIT(x) (((x) >> S_CH2FIFOLIMIT) & M_CH2FIFOLIMIT)
19499 #define S_CH1FIFOLIMIT 8
19500 #define M_CH1FIFOLIMIT 0xffU
19501 #define V_CH1FIFOLIMIT(x) ((x) << S_CH1FIFOLIMIT)
19502 #define G_CH1FIFOLIMIT(x) (((x) >> S_CH1FIFOLIMIT) & M_CH1FIFOLIMIT)
19504 #define S_CH0FIFOLIMIT 0
19505 #define M_CH0FIFOLIMIT 0xffU
19506 #define V_CH0FIFOLIMIT(x) ((x) << S_CH0FIFOLIMIT)
19507 #define G_CH0FIFOLIMIT(x) (((x) >> S_CH0FIFOLIMIT) & M_CH0FIFOLIMIT)
19509 #define A_TP_CDSP_CONFIG 0x242
19511 #define S_WRITEZEROEN 4
19512 #define V_WRITEZEROEN(x) ((x) << S_WRITEZEROEN)
19513 #define F_WRITEZEROEN V_WRITEZEROEN(1U)
19515 #define S_WRITEZEROOP 0
19516 #define M_WRITEZEROOP 0xfU
19517 #define V_WRITEZEROOP(x) ((x) << S_WRITEZEROOP)
19518 #define G_WRITEZEROOP(x) (((x) >> S_WRITEZEROOP) & M_WRITEZEROOP)
19520 #define S_STARTSKIPPLD 7
19521 #define V_STARTSKIPPLD(x) ((x) << S_STARTSKIPPLD)
19522 #define F_STARTSKIPPLD V_STARTSKIPPLD(1U)
19524 #define S_ATOMICCMDEN 5
19525 #define V_ATOMICCMDEN(x) ((x) << S_ATOMICCMDEN)
19526 #define F_ATOMICCMDEN V_ATOMICCMDEN(1U)
19528 #define A_TP_CSPI_POWER 0x243
19530 #define S_GATECHNTX3 11
19531 #define V_GATECHNTX3(x) ((x) << S_GATECHNTX3)
19532 #define F_GATECHNTX3 V_GATECHNTX3(1U)
19534 #define S_GATECHNTX2 10
19535 #define V_GATECHNTX2(x) ((x) << S_GATECHNTX2)
19536 #define F_GATECHNTX2 V_GATECHNTX2(1U)
19538 #define S_GATECHNTX1 9
19539 #define V_GATECHNTX1(x) ((x) << S_GATECHNTX1)
19540 #define F_GATECHNTX1 V_GATECHNTX1(1U)
19542 #define S_GATECHNTX0 8
19543 #define V_GATECHNTX0(x) ((x) << S_GATECHNTX0)
19544 #define F_GATECHNTX0 V_GATECHNTX0(1U)
19546 #define S_GATECHNRX1 7
19547 #define V_GATECHNRX1(x) ((x) << S_GATECHNRX1)
19548 #define F_GATECHNRX1 V_GATECHNRX1(1U)
19550 #define S_GATECHNRX0 6
19551 #define V_GATECHNRX0(x) ((x) << S_GATECHNRX0)
19552 #define F_GATECHNRX0 V_GATECHNRX0(1U)
19554 #define S_SLEEPRDYUTRN 4
19555 #define V_SLEEPRDYUTRN(x) ((x) << S_SLEEPRDYUTRN)
19556 #define F_SLEEPRDYUTRN V_SLEEPRDYUTRN(1U)
19558 #define S_SLEEPREQUTRN 0
19559 #define V_SLEEPREQUTRN(x) ((x) << S_SLEEPREQUTRN)
19560 #define F_SLEEPREQUTRN V_SLEEPREQUTRN(1U)
19562 #define A_TP_TRC_CONFIG 0x244
19565 #define V_TRCRR(x) ((x) << S_TRCRR)
19566 #define F_TRCRR V_TRCRR(1U)
19569 #define V_TRCCH(x) ((x) << S_TRCCH)
19570 #define F_TRCCH V_TRCCH(1U)
19572 #define A_TP_TAG_CONFIG 0x245
19574 #define S_ETAGTYPE 16
19575 #define M_ETAGTYPE 0xffffU
19576 #define V_ETAGTYPE(x) ((x) << S_ETAGTYPE)
19577 #define G_ETAGTYPE(x) (((x) >> S_ETAGTYPE) & M_ETAGTYPE)
19579 #define A_TP_DBG_CSIDE_PRS 0x246
19581 #define S_CPRSSTATE3 24
19582 #define M_CPRSSTATE3 0x7U
19583 #define V_CPRSSTATE3(x) ((x) << S_CPRSSTATE3)
19584 #define G_CPRSSTATE3(x) (((x) >> S_CPRSSTATE3) & M_CPRSSTATE3)
19586 #define S_CPRSSTATE2 16
19587 #define M_CPRSSTATE2 0x7U
19588 #define V_CPRSSTATE2(x) ((x) << S_CPRSSTATE2)
19589 #define G_CPRSSTATE2(x) (((x) >> S_CPRSSTATE2) & M_CPRSSTATE2)
19591 #define S_CPRSSTATE1 8
19592 #define M_CPRSSTATE1 0x7U
19593 #define V_CPRSSTATE1(x) ((x) << S_CPRSSTATE1)
19594 #define G_CPRSSTATE1(x) (((x) >> S_CPRSSTATE1) & M_CPRSSTATE1)
19596 #define S_CPRSSTATE0 0
19597 #define M_CPRSSTATE0 0x7U
19598 #define V_CPRSSTATE0(x) ((x) << S_CPRSSTATE0)
19599 #define G_CPRSSTATE0(x) (((x) >> S_CPRSSTATE0) & M_CPRSSTATE0)
19601 #define S_C4TUPBUSY3 31
19602 #define V_C4TUPBUSY3(x) ((x) << S_C4TUPBUSY3)
19603 #define F_C4TUPBUSY3 V_C4TUPBUSY3(1U)
19605 #define S_CDBVALID3 30
19606 #define V_CDBVALID3(x) ((x) << S_CDBVALID3)
19607 #define F_CDBVALID3 V_CDBVALID3(1U)
19609 #define S_CRXVALID3 29
19610 #define V_CRXVALID3(x) ((x) << S_CRXVALID3)
19611 #define F_CRXVALID3 V_CRXVALID3(1U)
19613 #define S_CRXFULL3 28
19614 #define V_CRXFULL3(x) ((x) << S_CRXFULL3)
19615 #define F_CRXFULL3 V_CRXFULL3(1U)
19617 #define S_C4TUPBUSY2 23
19618 #define V_C4TUPBUSY2(x) ((x) << S_C4TUPBUSY2)
19619 #define F_C4TUPBUSY2 V_C4TUPBUSY2(1U)
19621 #define S_CDBVALID2 22
19622 #define V_CDBVALID2(x) ((x) << S_CDBVALID2)
19623 #define F_CDBVALID2 V_CDBVALID2(1U)
19625 #define S_CRXVALID2 21
19626 #define V_CRXVALID2(x) ((x) << S_CRXVALID2)
19627 #define F_CRXVALID2 V_CRXVALID2(1U)
19629 #define S_CRXFULL2 20
19630 #define V_CRXFULL2(x) ((x) << S_CRXFULL2)
19631 #define F_CRXFULL2 V_CRXFULL2(1U)
19633 #define S_C4TUPBUSY1 15
19634 #define V_C4TUPBUSY1(x) ((x) << S_C4TUPBUSY1)
19635 #define F_C4TUPBUSY1 V_C4TUPBUSY1(1U)
19637 #define S_CDBVALID1 14
19638 #define V_CDBVALID1(x) ((x) << S_CDBVALID1)
19639 #define F_CDBVALID1 V_CDBVALID1(1U)
19641 #define S_CRXVALID1 13
19642 #define V_CRXVALID1(x) ((x) << S_CRXVALID1)
19643 #define F_CRXVALID1 V_CRXVALID1(1U)
19645 #define S_CRXFULL1 12
19646 #define V_CRXFULL1(x) ((x) << S_CRXFULL1)
19647 #define F_CRXFULL1 V_CRXFULL1(1U)
19649 #define S_C4TUPBUSY0 7
19650 #define V_C4TUPBUSY0(x) ((x) << S_C4TUPBUSY0)
19651 #define F_C4TUPBUSY0 V_C4TUPBUSY0(1U)
19653 #define S_CDBVALID0 6
19654 #define V_CDBVALID0(x) ((x) << S_CDBVALID0)
19655 #define F_CDBVALID0 V_CDBVALID0(1U)
19657 #define S_CRXVALID0 5
19658 #define V_CRXVALID0(x) ((x) << S_CRXVALID0)
19659 #define F_CRXVALID0 V_CRXVALID0(1U)
19661 #define S_CRXFULL0 4
19662 #define V_CRXFULL0(x) ((x) << S_CRXFULL0)
19663 #define F_CRXFULL0 V_CRXFULL0(1U)
19665 #define A_TP_DBG_CSIDE_DEMUX 0x247
19667 #define S_CALLDONE 28
19668 #define M_CALLDONE 0xfU
19669 #define V_CALLDONE(x) ((x) << S_CALLDONE)
19670 #define G_CALLDONE(x) (((x) >> S_CALLDONE) & M_CALLDONE)
19672 #define S_CTCPL5DONE 24
19673 #define M_CTCPL5DONE 0xfU
19674 #define V_CTCPL5DONE(x) ((x) << S_CTCPL5DONE)
19675 #define G_CTCPL5DONE(x) (((x) >> S_CTCPL5DONE) & M_CTCPL5DONE)
19677 #define S_CTXZEROPDONE 20
19678 #define M_CTXZEROPDONE 0xfU
19679 #define V_CTXZEROPDONE(x) ((x) << S_CTXZEROPDONE)
19680 #define G_CTXZEROPDONE(x) (((x) >> S_CTXZEROPDONE) & M_CTXZEROPDONE)
19682 #define S_CPLDDONE 16
19683 #define M_CPLDDONE 0xfU
19684 #define V_CPLDDONE(x) ((x) << S_CPLDDONE)
19685 #define G_CPLDDONE(x) (((x) >> S_CPLDDONE) & M_CPLDDONE)
19687 #define S_CTTCPOPDONE 12
19688 #define M_CTTCPOPDONE 0xfU
19689 #define V_CTTCPOPDONE(x) ((x) << S_CTTCPOPDONE)
19690 #define G_CTTCPOPDONE(x) (((x) >> S_CTTCPOPDONE) & M_CTTCPOPDONE)
19692 #define S_CDBDONE 8
19693 #define M_CDBDONE 0xfU
19694 #define V_CDBDONE(x) ((x) << S_CDBDONE)
19695 #define G_CDBDONE(x) (((x) >> S_CDBDONE) & M_CDBDONE)
19697 #define S_CISSFIFODONE 4
19698 #define M_CISSFIFODONE 0xfU
19699 #define V_CISSFIFODONE(x) ((x) << S_CISSFIFODONE)
19700 #define G_CISSFIFODONE(x) (((x) >> S_CISSFIFODONE) & M_CISSFIFODONE)
19702 #define S_CTXPKTCSUMDONE 0
19703 #define M_CTXPKTCSUMDONE 0xfU
19704 #define V_CTXPKTCSUMDONE(x) ((x) << S_CTXPKTCSUMDONE)
19705 #define G_CTXPKTCSUMDONE(x) (((x) >> S_CTXPKTCSUMDONE) & M_CTXPKTCSUMDONE)
19707 #define S_CARBVALID 28
19708 #define M_CARBVALID 0xfU
19709 #define V_CARBVALID(x) ((x) << S_CARBVALID)
19710 #define G_CARBVALID(x) (((x) >> S_CARBVALID) & M_CARBVALID)
19712 #define S_CCPL5DONE 24
19713 #define M_CCPL5DONE 0xfU
19714 #define V_CCPL5DONE(x) ((x) << S_CCPL5DONE)
19715 #define G_CCPL5DONE(x) (((x) >> S_CCPL5DONE) & M_CCPL5DONE)
19717 #define S_CTCPOPDONE 12
19718 #define M_CTCPOPDONE 0xfU
19719 #define V_CTCPOPDONE(x) ((x) << S_CTCPOPDONE)
19720 #define G_CTCPOPDONE(x) (((x) >> S_CTCPOPDONE) & M_CTCPOPDONE)
19722 #define A_TP_DBG_CSIDE_ARBIT 0x248
19724 #define S_CPLVALID3 31
19725 #define V_CPLVALID3(x) ((x) << S_CPLVALID3)
19726 #define F_CPLVALID3 V_CPLVALID3(1U)
19728 #define S_PLDVALID3 30
19729 #define V_PLDVALID3(x) ((x) << S_PLDVALID3)
19730 #define F_PLDVALID3 V_PLDVALID3(1U)
19732 #define S_CRCVALID3 29
19733 #define V_CRCVALID3(x) ((x) << S_CRCVALID3)
19734 #define F_CRCVALID3 V_CRCVALID3(1U)
19736 #define S_ISSVALID3 28
19737 #define V_ISSVALID3(x) ((x) << S_ISSVALID3)
19738 #define F_ISSVALID3 V_ISSVALID3(1U)
19740 #define S_DBVALID3 27
19741 #define V_DBVALID3(x) ((x) << S_DBVALID3)
19742 #define F_DBVALID3 V_DBVALID3(1U)
19744 #define S_CHKVALID3 26
19745 #define V_CHKVALID3(x) ((x) << S_CHKVALID3)
19746 #define F_CHKVALID3 V_CHKVALID3(1U)
19748 #define S_ZRPVALID3 25
19749 #define V_ZRPVALID3(x) ((x) << S_ZRPVALID3)
19750 #define F_ZRPVALID3 V_ZRPVALID3(1U)
19752 #define S_ERRVALID3 24
19753 #define V_ERRVALID3(x) ((x) << S_ERRVALID3)
19754 #define F_ERRVALID3 V_ERRVALID3(1U)
19756 #define S_CPLVALID2 23
19757 #define V_CPLVALID2(x) ((x) << S_CPLVALID2)
19758 #define F_CPLVALID2 V_CPLVALID2(1U)
19760 #define S_PLDVALID2 22
19761 #define V_PLDVALID2(x) ((x) << S_PLDVALID2)
19762 #define F_PLDVALID2 V_PLDVALID2(1U)
19764 #define S_CRCVALID2 21
19765 #define V_CRCVALID2(x) ((x) << S_CRCVALID2)
19766 #define F_CRCVALID2 V_CRCVALID2(1U)
19768 #define S_ISSVALID2 20
19769 #define V_ISSVALID2(x) ((x) << S_ISSVALID2)
19770 #define F_ISSVALID2 V_ISSVALID2(1U)
19772 #define S_DBVALID2 19
19773 #define V_DBVALID2(x) ((x) << S_DBVALID2)
19774 #define F_DBVALID2 V_DBVALID2(1U)
19776 #define S_CHKVALID2 18
19777 #define V_CHKVALID2(x) ((x) << S_CHKVALID2)
19778 #define F_CHKVALID2 V_CHKVALID2(1U)
19780 #define S_ZRPVALID2 17
19781 #define V_ZRPVALID2(x) ((x) << S_ZRPVALID2)
19782 #define F_ZRPVALID2 V_ZRPVALID2(1U)
19784 #define S_ERRVALID2 16
19785 #define V_ERRVALID2(x) ((x) << S_ERRVALID2)
19786 #define F_ERRVALID2 V_ERRVALID2(1U)
19788 #define S_CPLVALID1 15
19789 #define V_CPLVALID1(x) ((x) << S_CPLVALID1)
19790 #define F_CPLVALID1 V_CPLVALID1(1U)
19792 #define S_PLDVALID1 14
19793 #define V_PLDVALID1(x) ((x) << S_PLDVALID1)
19794 #define F_PLDVALID1 V_PLDVALID1(1U)
19796 #define S_CRCVALID1 13
19797 #define V_CRCVALID1(x) ((x) << S_CRCVALID1)
19798 #define F_CRCVALID1 V_CRCVALID1(1U)
19800 #define S_ISSVALID1 12
19801 #define V_ISSVALID1(x) ((x) << S_ISSVALID1)
19802 #define F_ISSVALID1 V_ISSVALID1(1U)
19804 #define S_DBVALID1 11
19805 #define V_DBVALID1(x) ((x) << S_DBVALID1)
19806 #define F_DBVALID1 V_DBVALID1(1U)
19808 #define S_CHKVALID1 10
19809 #define V_CHKVALID1(x) ((x) << S_CHKVALID1)
19810 #define F_CHKVALID1 V_CHKVALID1(1U)
19812 #define S_ZRPVALID1 9
19813 #define V_ZRPVALID1(x) ((x) << S_ZRPVALID1)
19814 #define F_ZRPVALID1 V_ZRPVALID1(1U)
19816 #define S_ERRVALID1 8
19817 #define V_ERRVALID1(x) ((x) << S_ERRVALID1)
19818 #define F_ERRVALID1 V_ERRVALID1(1U)
19820 #define S_CPLVALID0 7
19821 #define V_CPLVALID0(x) ((x) << S_CPLVALID0)
19822 #define F_CPLVALID0 V_CPLVALID0(1U)
19824 #define S_PLDVALID0 6
19825 #define V_PLDVALID0(x) ((x) << S_PLDVALID0)
19826 #define F_PLDVALID0 V_PLDVALID0(1U)
19828 #define S_CRCVALID0 5
19829 #define V_CRCVALID0(x) ((x) << S_CRCVALID0)
19830 #define F_CRCVALID0 V_CRCVALID0(1U)
19832 #define S_ISSVALID0 4
19833 #define V_ISSVALID0(x) ((x) << S_ISSVALID0)
19834 #define F_ISSVALID0 V_ISSVALID0(1U)
19836 #define S_DBVALID0 3
19837 #define V_DBVALID0(x) ((x) << S_DBVALID0)
19838 #define F_DBVALID0 V_DBVALID0(1U)
19840 #define S_CHKVALID0 2
19841 #define V_CHKVALID0(x) ((x) << S_CHKVALID0)
19842 #define F_CHKVALID0 V_CHKVALID0(1U)
19844 #define S_ZRPVALID0 1
19845 #define V_ZRPVALID0(x) ((x) << S_ZRPVALID0)
19846 #define F_ZRPVALID0 V_ZRPVALID0(1U)
19848 #define S_ERRVALID0 0
19849 #define V_ERRVALID0(x) ((x) << S_ERRVALID0)
19850 #define F_ERRVALID0 V_ERRVALID0(1U)
19852 #define A_TP_FIFO_CONFIG 0x8c0
19854 #define S_CH1_OUTPUT 27
19855 #define M_CH1_OUTPUT 0x1fU
19856 #define V_CH1_OUTPUT(x) ((x) << S_CH1_OUTPUT)
19857 #define G_CH1_OUTPUT(x) (((x) >> S_CH1_OUTPUT) & M_CH1_OUTPUT)
19859 #define S_CH2_OUTPUT 22
19860 #define M_CH2_OUTPUT 0x1fU
19861 #define V_CH2_OUTPUT(x) ((x) << S_CH2_OUTPUT)
19862 #define G_CH2_OUTPUT(x) (((x) >> S_CH2_OUTPUT) & M_CH2_OUTPUT)
19864 #define S_STROBE1 16
19865 #define V_STROBE1(x) ((x) << S_STROBE1)
19866 #define F_STROBE1 V_STROBE1(1U)
19868 #define S_CH1_INPUT 11
19869 #define M_CH1_INPUT 0x1fU
19870 #define V_CH1_INPUT(x) ((x) << S_CH1_INPUT)
19871 #define G_CH1_INPUT(x) (((x) >> S_CH1_INPUT) & M_CH1_INPUT)
19873 #define S_CH2_INPUT 6
19874 #define M_CH2_INPUT 0x1fU
19875 #define V_CH2_INPUT(x) ((x) << S_CH2_INPUT)
19876 #define G_CH2_INPUT(x) (((x) >> S_CH2_INPUT) & M_CH2_INPUT)
19878 #define S_CH3_INPUT 1
19879 #define M_CH3_INPUT 0x1fU
19880 #define V_CH3_INPUT(x) ((x) << S_CH3_INPUT)
19881 #define G_CH3_INPUT(x) (((x) >> S_CH3_INPUT) & M_CH3_INPUT)
19883 #define S_STROBE0 0
19884 #define V_STROBE0(x) ((x) << S_STROBE0)
19885 #define F_STROBE0 V_STROBE0(1U)
19887 #define A_TP_MIB_MAC_IN_ERR_0 0x0
19888 #define A_TP_MIB_MAC_IN_ERR_1 0x1
19889 #define A_TP_MIB_MAC_IN_ERR_2 0x2
19890 #define A_TP_MIB_MAC_IN_ERR_3 0x3
19891 #define A_TP_MIB_HDR_IN_ERR_0 0x4
19892 #define A_TP_MIB_HDR_IN_ERR_1 0x5
19893 #define A_TP_MIB_HDR_IN_ERR_2 0x6
19894 #define A_TP_MIB_HDR_IN_ERR_3 0x7
19895 #define A_TP_MIB_TCP_IN_ERR_0 0x8
19896 #define A_TP_MIB_TCP_IN_ERR_1 0x9
19897 #define A_TP_MIB_TCP_IN_ERR_2 0xa
19898 #define A_TP_MIB_TCP_IN_ERR_3 0xb
19899 #define A_TP_MIB_TCP_OUT_RST 0xc
19900 #define A_TP_MIB_TCP_IN_SEG_HI 0x10
19901 #define A_TP_MIB_TCP_IN_SEG_LO 0x11
19902 #define A_TP_MIB_TCP_OUT_SEG_HI 0x12
19903 #define A_TP_MIB_TCP_OUT_SEG_LO 0x13
19904 #define A_TP_MIB_TCP_RXT_SEG_HI 0x14
19905 #define A_TP_MIB_TCP_RXT_SEG_LO 0x15
19906 #define A_TP_MIB_TNL_CNG_DROP_0 0x18
19907 #define A_TP_MIB_TNL_CNG_DROP_1 0x19
19908 #define A_TP_MIB_TNL_CNG_DROP_2 0x1a
19909 #define A_TP_MIB_TNL_CNG_DROP_3 0x1b
19910 #define A_TP_MIB_OFD_CHN_DROP_0 0x1c
19911 #define A_TP_MIB_OFD_CHN_DROP_1 0x1d
19912 #define A_TP_MIB_OFD_CHN_DROP_2 0x1e
19913 #define A_TP_MIB_OFD_CHN_DROP_3 0x1f
19914 #define A_TP_MIB_TNL_OUT_PKT_0 0x20
19915 #define A_TP_MIB_TNL_OUT_PKT_1 0x21
19916 #define A_TP_MIB_TNL_OUT_PKT_2 0x22
19917 #define A_TP_MIB_TNL_OUT_PKT_3 0x23
19918 #define A_TP_MIB_TNL_IN_PKT_0 0x24
19919 #define A_TP_MIB_TNL_IN_PKT_1 0x25
19920 #define A_TP_MIB_TNL_IN_PKT_2 0x26
19921 #define A_TP_MIB_TNL_IN_PKT_3 0x27
19922 #define A_TP_MIB_TCP_V6IN_ERR_0 0x28
19923 #define A_TP_MIB_TCP_V6IN_ERR_1 0x29
19924 #define A_TP_MIB_TCP_V6IN_ERR_2 0x2a
19925 #define A_TP_MIB_TCP_V6IN_ERR_3 0x2b
19926 #define A_TP_MIB_TCP_V6OUT_RST 0x2c
19927 #define A_TP_MIB_TCP_V6IN_SEG_HI 0x30
19928 #define A_TP_MIB_TCP_V6IN_SEG_LO 0x31
19929 #define A_TP_MIB_TCP_V6OUT_SEG_HI 0x32
19930 #define A_TP_MIB_TCP_V6OUT_SEG_LO 0x33
19931 #define A_TP_MIB_TCP_V6RXT_SEG_HI 0x34
19932 #define A_TP_MIB_TCP_V6RXT_SEG_LO 0x35
19933 #define A_TP_MIB_OFD_ARP_DROP 0x36
19934 #define A_TP_MIB_OFD_DFR_DROP 0x37
19935 #define A_TP_MIB_CPL_IN_REQ_0 0x38
19936 #define A_TP_MIB_CPL_IN_REQ_1 0x39
19937 #define A_TP_MIB_CPL_IN_REQ_2 0x3a
19938 #define A_TP_MIB_CPL_IN_REQ_3 0x3b
19939 #define A_TP_MIB_CPL_OUT_RSP_0 0x3c
19940 #define A_TP_MIB_CPL_OUT_RSP_1 0x3d
19941 #define A_TP_MIB_CPL_OUT_RSP_2 0x3e
19942 #define A_TP_MIB_CPL_OUT_RSP_3 0x3f
19943 #define A_TP_MIB_TNL_LPBK_0 0x40
19944 #define A_TP_MIB_TNL_LPBK_1 0x41
19945 #define A_TP_MIB_TNL_LPBK_2 0x42
19946 #define A_TP_MIB_TNL_LPBK_3 0x43
19947 #define A_TP_MIB_TNL_DROP_0 0x44
19948 #define A_TP_MIB_TNL_DROP_1 0x45
19949 #define A_TP_MIB_TNL_DROP_2 0x46
19950 #define A_TP_MIB_TNL_DROP_3 0x47
19951 #define A_TP_MIB_FCOE_DDP_0 0x48
19952 #define A_TP_MIB_FCOE_DDP_1 0x49
19953 #define A_TP_MIB_FCOE_DDP_2 0x4a
19954 #define A_TP_MIB_FCOE_DDP_3 0x4b
19955 #define A_TP_MIB_FCOE_DROP_0 0x4c
19956 #define A_TP_MIB_FCOE_DROP_1 0x4d
19957 #define A_TP_MIB_FCOE_DROP_2 0x4e
19958 #define A_TP_MIB_FCOE_DROP_3 0x4f
19959 #define A_TP_MIB_FCOE_BYTE_0_HI 0x50
19960 #define A_TP_MIB_FCOE_BYTE_0_LO 0x51
19961 #define A_TP_MIB_FCOE_BYTE_1_HI 0x52
19962 #define A_TP_MIB_FCOE_BYTE_1_LO 0x53
19963 #define A_TP_MIB_FCOE_BYTE_2_HI 0x54
19964 #define A_TP_MIB_FCOE_BYTE_2_LO 0x55
19965 #define A_TP_MIB_FCOE_BYTE_3_HI 0x56
19966 #define A_TP_MIB_FCOE_BYTE_3_LO 0x57
19967 #define A_TP_MIB_OFD_VLN_DROP_0 0x58
19968 #define A_TP_MIB_OFD_VLN_DROP_1 0x59
19969 #define A_TP_MIB_OFD_VLN_DROP_2 0x5a
19970 #define A_TP_MIB_OFD_VLN_DROP_3 0x5b
19971 #define A_TP_MIB_USM_PKTS 0x5c
19972 #define A_TP_MIB_USM_DROP 0x5d
19973 #define A_TP_MIB_USM_BYTES_HI 0x5e
19974 #define A_TP_MIB_USM_BYTES_LO 0x5f
19975 #define A_TP_MIB_TID_DEL 0x60
19976 #define A_TP_MIB_TID_INV 0x61
19977 #define A_TP_MIB_TID_ACT 0x62
19978 #define A_TP_MIB_TID_PAS 0x63
19979 #define A_TP_MIB_RQE_DFR_PKT 0x64
19980 #define A_TP_MIB_RQE_DFR_MOD 0x65
19981 #define A_TP_MIB_CPL_OUT_ERR_0 0x68
19982 #define A_TP_MIB_CPL_OUT_ERR_1 0x69
19983 #define A_TP_MIB_CPL_OUT_ERR_2 0x6a
19984 #define A_TP_MIB_CPL_OUT_ERR_3 0x6b
19985 #define A_TP_MIB_ENG_LINE_0 0x6c
19986 #define A_TP_MIB_ENG_LINE_1 0x6d
19987 #define A_TP_MIB_ENG_LINE_2 0x6e
19988 #define A_TP_MIB_ENG_LINE_3 0x6f
19990 /* registers for module ULP_TX */
19991 #define ULP_TX_BASE_ADDR 0x8dc0
19993 #define A_ULP_TX_CONFIG 0x8dc0
19995 #define S_STAG_MIX_ENABLE 2
19996 #define V_STAG_MIX_ENABLE(x) ((x) << S_STAG_MIX_ENABLE)
19997 #define F_STAG_MIX_ENABLE V_STAG_MIX_ENABLE(1U)
19999 #define S_STAGF_FIX_DISABLE 1
20000 #define V_STAGF_FIX_DISABLE(x) ((x) << S_STAGF_FIX_DISABLE)
20001 #define F_STAGF_FIX_DISABLE V_STAGF_FIX_DISABLE(1U)
20003 #define S_EXTRA_TAG_INSERTION_ENABLE 0
20004 #define V_EXTRA_TAG_INSERTION_ENABLE(x) ((x) << S_EXTRA_TAG_INSERTION_ENABLE)
20005 #define F_EXTRA_TAG_INSERTION_ENABLE V_EXTRA_TAG_INSERTION_ENABLE(1U)
20007 #define S_PHYS_ADDR_RESP_EN 6
20008 #define V_PHYS_ADDR_RESP_EN(x) ((x) << S_PHYS_ADDR_RESP_EN)
20009 #define F_PHYS_ADDR_RESP_EN V_PHYS_ADDR_RESP_EN(1U)
20011 #define S_ENDIANESS_CHANGE 5
20012 #define V_ENDIANESS_CHANGE(x) ((x) << S_ENDIANESS_CHANGE)
20013 #define F_ENDIANESS_CHANGE V_ENDIANESS_CHANGE(1U)
20015 #define S_ERR_RTAG_EN 4
20016 #define V_ERR_RTAG_EN(x) ((x) << S_ERR_RTAG_EN)
20017 #define F_ERR_RTAG_EN V_ERR_RTAG_EN(1U)
20019 #define S_TSO_ETHLEN_EN 3
20020 #define V_TSO_ETHLEN_EN(x) ((x) << S_TSO_ETHLEN_EN)
20021 #define F_TSO_ETHLEN_EN V_TSO_ETHLEN_EN(1U)
20023 #define S_EMSG_MORE_INFO 2
20024 #define V_EMSG_MORE_INFO(x) ((x) << S_EMSG_MORE_INFO)
20025 #define F_EMSG_MORE_INFO V_EMSG_MORE_INFO(1U)
20028 #define V_LOSDR(x) ((x) << S_LOSDR)
20029 #define F_LOSDR V_LOSDR(1U)
20031 #define A_ULP_TX_PERR_INJECT 0x8dc4
20032 #define A_ULP_TX_INT_ENABLE 0x8dc8
20034 #define S_PBL_BOUND_ERR_CH3 31
20035 #define V_PBL_BOUND_ERR_CH3(x) ((x) << S_PBL_BOUND_ERR_CH3)
20036 #define F_PBL_BOUND_ERR_CH3 V_PBL_BOUND_ERR_CH3(1U)
20038 #define S_PBL_BOUND_ERR_CH2 30
20039 #define V_PBL_BOUND_ERR_CH2(x) ((x) << S_PBL_BOUND_ERR_CH2)
20040 #define F_PBL_BOUND_ERR_CH2 V_PBL_BOUND_ERR_CH2(1U)
20042 #define S_PBL_BOUND_ERR_CH1 29
20043 #define V_PBL_BOUND_ERR_CH1(x) ((x) << S_PBL_BOUND_ERR_CH1)
20044 #define F_PBL_BOUND_ERR_CH1 V_PBL_BOUND_ERR_CH1(1U)
20046 #define S_PBL_BOUND_ERR_CH0 28
20047 #define V_PBL_BOUND_ERR_CH0(x) ((x) << S_PBL_BOUND_ERR_CH0)
20048 #define F_PBL_BOUND_ERR_CH0 V_PBL_BOUND_ERR_CH0(1U)
20050 #define S_SGE2ULP_FIFO_PERR_SET3 27
20051 #define V_SGE2ULP_FIFO_PERR_SET3(x) ((x) << S_SGE2ULP_FIFO_PERR_SET3)
20052 #define F_SGE2ULP_FIFO_PERR_SET3 V_SGE2ULP_FIFO_PERR_SET3(1U)
20054 #define S_SGE2ULP_FIFO_PERR_SET2 26
20055 #define V_SGE2ULP_FIFO_PERR_SET2(x) ((x) << S_SGE2ULP_FIFO_PERR_SET2)
20056 #define F_SGE2ULP_FIFO_PERR_SET2 V_SGE2ULP_FIFO_PERR_SET2(1U)
20058 #define S_SGE2ULP_FIFO_PERR_SET1 25
20059 #define V_SGE2ULP_FIFO_PERR_SET1(x) ((x) << S_SGE2ULP_FIFO_PERR_SET1)
20060 #define F_SGE2ULP_FIFO_PERR_SET1 V_SGE2ULP_FIFO_PERR_SET1(1U)
20062 #define S_SGE2ULP_FIFO_PERR_SET0 24
20063 #define V_SGE2ULP_FIFO_PERR_SET0(x) ((x) << S_SGE2ULP_FIFO_PERR_SET0)
20064 #define F_SGE2ULP_FIFO_PERR_SET0 V_SGE2ULP_FIFO_PERR_SET0(1U)
20066 #define S_CIM2ULP_FIFO_PERR_SET3 23
20067 #define V_CIM2ULP_FIFO_PERR_SET3(x) ((x) << S_CIM2ULP_FIFO_PERR_SET3)
20068 #define F_CIM2ULP_FIFO_PERR_SET3 V_CIM2ULP_FIFO_PERR_SET3(1U)
20070 #define S_CIM2ULP_FIFO_PERR_SET2 22
20071 #define V_CIM2ULP_FIFO_PERR_SET2(x) ((x) << S_CIM2ULP_FIFO_PERR_SET2)
20072 #define F_CIM2ULP_FIFO_PERR_SET2 V_CIM2ULP_FIFO_PERR_SET2(1U)
20074 #define S_CIM2ULP_FIFO_PERR_SET1 21
20075 #define V_CIM2ULP_FIFO_PERR_SET1(x) ((x) << S_CIM2ULP_FIFO_PERR_SET1)
20076 #define F_CIM2ULP_FIFO_PERR_SET1 V_CIM2ULP_FIFO_PERR_SET1(1U)
20078 #define S_CIM2ULP_FIFO_PERR_SET0 20
20079 #define V_CIM2ULP_FIFO_PERR_SET0(x) ((x) << S_CIM2ULP_FIFO_PERR_SET0)
20080 #define F_CIM2ULP_FIFO_PERR_SET0 V_CIM2ULP_FIFO_PERR_SET0(1U)
20082 #define S_CQE_FIFO_PERR_SET3 19
20083 #define V_CQE_FIFO_PERR_SET3(x) ((x) << S_CQE_FIFO_PERR_SET3)
20084 #define F_CQE_FIFO_PERR_SET3 V_CQE_FIFO_PERR_SET3(1U)
20086 #define S_CQE_FIFO_PERR_SET2 18
20087 #define V_CQE_FIFO_PERR_SET2(x) ((x) << S_CQE_FIFO_PERR_SET2)
20088 #define F_CQE_FIFO_PERR_SET2 V_CQE_FIFO_PERR_SET2(1U)
20090 #define S_CQE_FIFO_PERR_SET1 17
20091 #define V_CQE_FIFO_PERR_SET1(x) ((x) << S_CQE_FIFO_PERR_SET1)
20092 #define F_CQE_FIFO_PERR_SET1 V_CQE_FIFO_PERR_SET1(1U)
20094 #define S_CQE_FIFO_PERR_SET0 16
20095 #define V_CQE_FIFO_PERR_SET0(x) ((x) << S_CQE_FIFO_PERR_SET0)
20096 #define F_CQE_FIFO_PERR_SET0 V_CQE_FIFO_PERR_SET0(1U)
20098 #define S_PBL_FIFO_PERR_SET3 15
20099 #define V_PBL_FIFO_PERR_SET3(x) ((x) << S_PBL_FIFO_PERR_SET3)
20100 #define F_PBL_FIFO_PERR_SET3 V_PBL_FIFO_PERR_SET3(1U)
20102 #define S_PBL_FIFO_PERR_SET2 14
20103 #define V_PBL_FIFO_PERR_SET2(x) ((x) << S_PBL_FIFO_PERR_SET2)
20104 #define F_PBL_FIFO_PERR_SET2 V_PBL_FIFO_PERR_SET2(1U)
20106 #define S_PBL_FIFO_PERR_SET1 13
20107 #define V_PBL_FIFO_PERR_SET1(x) ((x) << S_PBL_FIFO_PERR_SET1)
20108 #define F_PBL_FIFO_PERR_SET1 V_PBL_FIFO_PERR_SET1(1U)
20110 #define S_PBL_FIFO_PERR_SET0 12
20111 #define V_PBL_FIFO_PERR_SET0(x) ((x) << S_PBL_FIFO_PERR_SET0)
20112 #define F_PBL_FIFO_PERR_SET0 V_PBL_FIFO_PERR_SET0(1U)
20114 #define S_CMD_FIFO_PERR_SET3 11
20115 #define V_CMD_FIFO_PERR_SET3(x) ((x) << S_CMD_FIFO_PERR_SET3)
20116 #define F_CMD_FIFO_PERR_SET3 V_CMD_FIFO_PERR_SET3(1U)
20118 #define S_CMD_FIFO_PERR_SET2 10
20119 #define V_CMD_FIFO_PERR_SET2(x) ((x) << S_CMD_FIFO_PERR_SET2)
20120 #define F_CMD_FIFO_PERR_SET2 V_CMD_FIFO_PERR_SET2(1U)
20122 #define S_CMD_FIFO_PERR_SET1 9
20123 #define V_CMD_FIFO_PERR_SET1(x) ((x) << S_CMD_FIFO_PERR_SET1)
20124 #define F_CMD_FIFO_PERR_SET1 V_CMD_FIFO_PERR_SET1(1U)
20126 #define S_CMD_FIFO_PERR_SET0 8
20127 #define V_CMD_FIFO_PERR_SET0(x) ((x) << S_CMD_FIFO_PERR_SET0)
20128 #define F_CMD_FIFO_PERR_SET0 V_CMD_FIFO_PERR_SET0(1U)
20130 #define S_LSO_HDR_SRAM_PERR_SET3 7
20131 #define V_LSO_HDR_SRAM_PERR_SET3(x) ((x) << S_LSO_HDR_SRAM_PERR_SET3)
20132 #define F_LSO_HDR_SRAM_PERR_SET3 V_LSO_HDR_SRAM_PERR_SET3(1U)
20134 #define S_LSO_HDR_SRAM_PERR_SET2 6
20135 #define V_LSO_HDR_SRAM_PERR_SET2(x) ((x) << S_LSO_HDR_SRAM_PERR_SET2)
20136 #define F_LSO_HDR_SRAM_PERR_SET2 V_LSO_HDR_SRAM_PERR_SET2(1U)
20138 #define S_LSO_HDR_SRAM_PERR_SET1 5
20139 #define V_LSO_HDR_SRAM_PERR_SET1(x) ((x) << S_LSO_HDR_SRAM_PERR_SET1)
20140 #define F_LSO_HDR_SRAM_PERR_SET1 V_LSO_HDR_SRAM_PERR_SET1(1U)
20142 #define S_LSO_HDR_SRAM_PERR_SET0 4
20143 #define V_LSO_HDR_SRAM_PERR_SET0(x) ((x) << S_LSO_HDR_SRAM_PERR_SET0)
20144 #define F_LSO_HDR_SRAM_PERR_SET0 V_LSO_HDR_SRAM_PERR_SET0(1U)
20146 #define S_IMM_DATA_PERR_SET_CH3 3
20147 #define V_IMM_DATA_PERR_SET_CH3(x) ((x) << S_IMM_DATA_PERR_SET_CH3)
20148 #define F_IMM_DATA_PERR_SET_CH3 V_IMM_DATA_PERR_SET_CH3(1U)
20150 #define S_IMM_DATA_PERR_SET_CH2 2
20151 #define V_IMM_DATA_PERR_SET_CH2(x) ((x) << S_IMM_DATA_PERR_SET_CH2)
20152 #define F_IMM_DATA_PERR_SET_CH2 V_IMM_DATA_PERR_SET_CH2(1U)
20154 #define S_IMM_DATA_PERR_SET_CH1 1
20155 #define V_IMM_DATA_PERR_SET_CH1(x) ((x) << S_IMM_DATA_PERR_SET_CH1)
20156 #define F_IMM_DATA_PERR_SET_CH1 V_IMM_DATA_PERR_SET_CH1(1U)
20158 #define S_IMM_DATA_PERR_SET_CH0 0
20159 #define V_IMM_DATA_PERR_SET_CH0(x) ((x) << S_IMM_DATA_PERR_SET_CH0)
20160 #define F_IMM_DATA_PERR_SET_CH0 V_IMM_DATA_PERR_SET_CH0(1U)
20162 #define A_ULP_TX_INT_CAUSE 0x8dcc
20163 #define A_ULP_TX_PERR_ENABLE 0x8dd0
20164 #define A_ULP_TX_TPT_LLIMIT 0x8dd4
20165 #define A_ULP_TX_TPT_ULIMIT 0x8dd8
20166 #define A_ULP_TX_PBL_LLIMIT 0x8ddc
20167 #define A_ULP_TX_PBL_ULIMIT 0x8de0
20168 #define A_ULP_TX_CPL_ERR_OFFSET 0x8de4
20169 #define A_ULP_TX_CPL_ERR_MASK_L 0x8de8
20170 #define A_ULP_TX_CPL_ERR_MASK_H 0x8dec
20171 #define A_ULP_TX_CPL_ERR_VALUE_L 0x8df0
20172 #define A_ULP_TX_CPL_ERR_VALUE_H 0x8df4
20173 #define A_ULP_TX_CPL_PACK_SIZE1 0x8df8
20175 #define S_CH3SIZE1 24
20176 #define M_CH3SIZE1 0xffU
20177 #define V_CH3SIZE1(x) ((x) << S_CH3SIZE1)
20178 #define G_CH3SIZE1(x) (((x) >> S_CH3SIZE1) & M_CH3SIZE1)
20180 #define S_CH2SIZE1 16
20181 #define M_CH2SIZE1 0xffU
20182 #define V_CH2SIZE1(x) ((x) << S_CH2SIZE1)
20183 #define G_CH2SIZE1(x) (((x) >> S_CH2SIZE1) & M_CH2SIZE1)
20185 #define S_CH1SIZE1 8
20186 #define M_CH1SIZE1 0xffU
20187 #define V_CH1SIZE1(x) ((x) << S_CH1SIZE1)
20188 #define G_CH1SIZE1(x) (((x) >> S_CH1SIZE1) & M_CH1SIZE1)
20190 #define S_CH0SIZE1 0
20191 #define M_CH0SIZE1 0xffU
20192 #define V_CH0SIZE1(x) ((x) << S_CH0SIZE1)
20193 #define G_CH0SIZE1(x) (((x) >> S_CH0SIZE1) & M_CH0SIZE1)
20195 #define A_ULP_TX_CPL_PACK_SIZE2 0x8dfc
20197 #define S_CH3SIZE2 24
20198 #define M_CH3SIZE2 0xffU
20199 #define V_CH3SIZE2(x) ((x) << S_CH3SIZE2)
20200 #define G_CH3SIZE2(x) (((x) >> S_CH3SIZE2) & M_CH3SIZE2)
20202 #define S_CH2SIZE2 16
20203 #define M_CH2SIZE2 0xffU
20204 #define V_CH2SIZE2(x) ((x) << S_CH2SIZE2)
20205 #define G_CH2SIZE2(x) (((x) >> S_CH2SIZE2) & M_CH2SIZE2)
20207 #define S_CH1SIZE2 8
20208 #define M_CH1SIZE2 0xffU
20209 #define V_CH1SIZE2(x) ((x) << S_CH1SIZE2)
20210 #define G_CH1SIZE2(x) (((x) >> S_CH1SIZE2) & M_CH1SIZE2)
20212 #define S_CH0SIZE2 0
20213 #define M_CH0SIZE2 0xffU
20214 #define V_CH0SIZE2(x) ((x) << S_CH0SIZE2)
20215 #define G_CH0SIZE2(x) (((x) >> S_CH0SIZE2) & M_CH0SIZE2)
20217 #define A_ULP_TX_ERR_MSG2CIM 0x8e00
20218 #define A_ULP_TX_ERR_TABLE_BASE 0x8e04
20219 #define A_ULP_TX_ERR_CNT_CH0 0x8e10
20221 #define S_ERR_CNT0 0
20222 #define M_ERR_CNT0 0xfffffU
20223 #define V_ERR_CNT0(x) ((x) << S_ERR_CNT0)
20224 #define G_ERR_CNT0(x) (((x) >> S_ERR_CNT0) & M_ERR_CNT0)
20226 #define A_ULP_TX_ERR_CNT_CH1 0x8e14
20228 #define S_ERR_CNT1 0
20229 #define M_ERR_CNT1 0xfffffU
20230 #define V_ERR_CNT1(x) ((x) << S_ERR_CNT1)
20231 #define G_ERR_CNT1(x) (((x) >> S_ERR_CNT1) & M_ERR_CNT1)
20233 #define A_ULP_TX_ERR_CNT_CH2 0x8e18
20235 #define S_ERR_CNT2 0
20236 #define M_ERR_CNT2 0xfffffU
20237 #define V_ERR_CNT2(x) ((x) << S_ERR_CNT2)
20238 #define G_ERR_CNT2(x) (((x) >> S_ERR_CNT2) & M_ERR_CNT2)
20240 #define A_ULP_TX_ERR_CNT_CH3 0x8e1c
20242 #define S_ERR_CNT3 0
20243 #define M_ERR_CNT3 0xfffffU
20244 #define V_ERR_CNT3(x) ((x) << S_ERR_CNT3)
20245 #define G_ERR_CNT3(x) (((x) >> S_ERR_CNT3) & M_ERR_CNT3)
20247 #define A_ULP_TX_FC_SOF 0x8e20
20249 #define S_SOF_FS3 24
20250 #define M_SOF_FS3 0xffU
20251 #define V_SOF_FS3(x) ((x) << S_SOF_FS3)
20252 #define G_SOF_FS3(x) (((x) >> S_SOF_FS3) & M_SOF_FS3)
20254 #define S_SOF_FS2 16
20255 #define M_SOF_FS2 0xffU
20256 #define V_SOF_FS2(x) ((x) << S_SOF_FS2)
20257 #define G_SOF_FS2(x) (((x) >> S_SOF_FS2) & M_SOF_FS2)
20260 #define M_SOF_3 0xffU
20261 #define V_SOF_3(x) ((x) << S_SOF_3)
20262 #define G_SOF_3(x) (((x) >> S_SOF_3) & M_SOF_3)
20265 #define M_SOF_2 0xffU
20266 #define V_SOF_2(x) ((x) << S_SOF_2)
20267 #define G_SOF_2(x) (((x) >> S_SOF_2) & M_SOF_2)
20269 #define A_ULP_TX_FC_EOF 0x8e24
20271 #define S_EOF_LS3 24
20272 #define M_EOF_LS3 0xffU
20273 #define V_EOF_LS3(x) ((x) << S_EOF_LS3)
20274 #define G_EOF_LS3(x) (((x) >> S_EOF_LS3) & M_EOF_LS3)
20276 #define S_EOF_LS2 16
20277 #define M_EOF_LS2 0xffU
20278 #define V_EOF_LS2(x) ((x) << S_EOF_LS2)
20279 #define G_EOF_LS2(x) (((x) >> S_EOF_LS2) & M_EOF_LS2)
20282 #define M_EOF_3 0xffU
20283 #define V_EOF_3(x) ((x) << S_EOF_3)
20284 #define G_EOF_3(x) (((x) >> S_EOF_3) & M_EOF_3)
20287 #define M_EOF_2 0xffU
20288 #define V_EOF_2(x) ((x) << S_EOF_2)
20289 #define G_EOF_2(x) (((x) >> S_EOF_2) & M_EOF_2)
20291 #define A_ULP_TX_CGEN_GLOBAL 0x8e28
20293 #define S_ULP_TX_GLOBAL_CGEN 0
20294 #define V_ULP_TX_GLOBAL_CGEN(x) ((x) << S_ULP_TX_GLOBAL_CGEN)
20295 #define F_ULP_TX_GLOBAL_CGEN V_ULP_TX_GLOBAL_CGEN(1U)
20297 #define A_ULP_TX_CGEN 0x8e2c
20299 #define S_ULP_TX_CGEN_STORAGE 8
20300 #define M_ULP_TX_CGEN_STORAGE 0xfU
20301 #define V_ULP_TX_CGEN_STORAGE(x) ((x) << S_ULP_TX_CGEN_STORAGE)
20302 #define G_ULP_TX_CGEN_STORAGE(x) (((x) >> S_ULP_TX_CGEN_STORAGE) & M_ULP_TX_CGEN_STORAGE)
20304 #define S_ULP_TX_CGEN_RDMA 4
20305 #define M_ULP_TX_CGEN_RDMA 0xfU
20306 #define V_ULP_TX_CGEN_RDMA(x) ((x) << S_ULP_TX_CGEN_RDMA)
20307 #define G_ULP_TX_CGEN_RDMA(x) (((x) >> S_ULP_TX_CGEN_RDMA) & M_ULP_TX_CGEN_RDMA)
20309 #define S_ULP_TX_CGEN_CHANNEL 0
20310 #define M_ULP_TX_CGEN_CHANNEL 0xfU
20311 #define V_ULP_TX_CGEN_CHANNEL(x) ((x) << S_ULP_TX_CGEN_CHANNEL)
20312 #define G_ULP_TX_CGEN_CHANNEL(x) (((x) >> S_ULP_TX_CGEN_CHANNEL) & M_ULP_TX_CGEN_CHANNEL)
20314 #define A_ULP_TX_ULP2TP_BIST_CMD 0x8e30
20315 #define A_ULP_TX_MEM_CFG 0x8e30
20317 #define S_WRREQ_SZ 0
20318 #define M_WRREQ_SZ 0x7U
20319 #define V_WRREQ_SZ(x) ((x) << S_WRREQ_SZ)
20320 #define G_WRREQ_SZ(x) (((x) >> S_WRREQ_SZ) & M_WRREQ_SZ)
20322 #define A_ULP_TX_ULP2TP_BIST_ERROR_CNT 0x8e34
20323 #define A_ULP_TX_PERR_INJECT_2 0x8e34
20324 #define A_ULP_TX_FPGA_CMD_CTRL 0x8e38
20325 #define A_ULP_TX_T5_FPGA_CMD_CTRL 0x8e38
20327 #define S_CHANNEL_SEL 12
20328 #define M_CHANNEL_SEL 0x3U
20329 #define V_CHANNEL_SEL(x) ((x) << S_CHANNEL_SEL)
20330 #define G_CHANNEL_SEL(x) (((x) >> S_CHANNEL_SEL) & M_CHANNEL_SEL)
20332 #define S_INTF_SEL 4
20333 #define M_INTF_SEL 0xfU
20334 #define V_INTF_SEL(x) ((x) << S_INTF_SEL)
20335 #define G_INTF_SEL(x) (((x) >> S_INTF_SEL) & M_INTF_SEL)
20337 #define S_NUM_FLITS 1
20338 #define M_NUM_FLITS 0x7U
20339 #define V_NUM_FLITS(x) ((x) << S_NUM_FLITS)
20340 #define G_NUM_FLITS(x) (((x) >> S_NUM_FLITS) & M_NUM_FLITS)
20342 #define S_CMD_GEN_EN 0
20343 #define V_CMD_GEN_EN(x) ((x) << S_CMD_GEN_EN)
20344 #define F_CMD_GEN_EN V_CMD_GEN_EN(1U)
20346 #define A_ULP_TX_FPGA_CMD_0 0x8e3c
20347 #define A_ULP_TX_T5_FPGA_CMD_0 0x8e3c
20348 #define A_ULP_TX_FPGA_CMD_1 0x8e40
20349 #define A_ULP_TX_T5_FPGA_CMD_1 0x8e40
20350 #define A_ULP_TX_FPGA_CMD_2 0x8e44
20351 #define A_ULP_TX_T5_FPGA_CMD_2 0x8e44
20352 #define A_ULP_TX_FPGA_CMD_3 0x8e48
20353 #define A_ULP_TX_T5_FPGA_CMD_3 0x8e48
20354 #define A_ULP_TX_FPGA_CMD_4 0x8e4c
20355 #define A_ULP_TX_T5_FPGA_CMD_4 0x8e4c
20356 #define A_ULP_TX_FPGA_CMD_5 0x8e50
20357 #define A_ULP_TX_T5_FPGA_CMD_5 0x8e50
20358 #define A_ULP_TX_FPGA_CMD_6 0x8e54
20359 #define A_ULP_TX_T5_FPGA_CMD_6 0x8e54
20360 #define A_ULP_TX_FPGA_CMD_7 0x8e58
20361 #define A_ULP_TX_T5_FPGA_CMD_7 0x8e58
20362 #define A_ULP_TX_FPGA_CMD_8 0x8e5c
20363 #define A_ULP_TX_T5_FPGA_CMD_8 0x8e5c
20364 #define A_ULP_TX_FPGA_CMD_9 0x8e60
20365 #define A_ULP_TX_T5_FPGA_CMD_9 0x8e60
20366 #define A_ULP_TX_FPGA_CMD_10 0x8e64
20367 #define A_ULP_TX_T5_FPGA_CMD_10 0x8e64
20368 #define A_ULP_TX_FPGA_CMD_11 0x8e68
20369 #define A_ULP_TX_T5_FPGA_CMD_11 0x8e68
20370 #define A_ULP_TX_FPGA_CMD_12 0x8e6c
20371 #define A_ULP_TX_T5_FPGA_CMD_12 0x8e6c
20372 #define A_ULP_TX_FPGA_CMD_13 0x8e70
20373 #define A_ULP_TX_T5_FPGA_CMD_13 0x8e70
20374 #define A_ULP_TX_FPGA_CMD_14 0x8e74
20375 #define A_ULP_TX_T5_FPGA_CMD_14 0x8e74
20376 #define A_ULP_TX_FPGA_CMD_15 0x8e78
20377 #define A_ULP_TX_T5_FPGA_CMD_15 0x8e78
20378 #define A_ULP_TX_INT_ENABLE_2 0x8e7c
20380 #define S_SMARBT2ULP_DATA_PERR_SET 12
20381 #define V_SMARBT2ULP_DATA_PERR_SET(x) ((x) << S_SMARBT2ULP_DATA_PERR_SET)
20382 #define F_SMARBT2ULP_DATA_PERR_SET V_SMARBT2ULP_DATA_PERR_SET(1U)
20384 #define S_ULP2TP_DATA_PERR_SET 11
20385 #define V_ULP2TP_DATA_PERR_SET(x) ((x) << S_ULP2TP_DATA_PERR_SET)
20386 #define F_ULP2TP_DATA_PERR_SET V_ULP2TP_DATA_PERR_SET(1U)
20388 #define S_MA2ULP_DATA_PERR_SET 10
20389 #define V_MA2ULP_DATA_PERR_SET(x) ((x) << S_MA2ULP_DATA_PERR_SET)
20390 #define F_MA2ULP_DATA_PERR_SET V_MA2ULP_DATA_PERR_SET(1U)
20392 #define S_SGE2ULP_DATA_PERR_SET 9
20393 #define V_SGE2ULP_DATA_PERR_SET(x) ((x) << S_SGE2ULP_DATA_PERR_SET)
20394 #define F_SGE2ULP_DATA_PERR_SET V_SGE2ULP_DATA_PERR_SET(1U)
20396 #define S_CIM2ULP_DATA_PERR_SET 8
20397 #define V_CIM2ULP_DATA_PERR_SET(x) ((x) << S_CIM2ULP_DATA_PERR_SET)
20398 #define F_CIM2ULP_DATA_PERR_SET V_CIM2ULP_DATA_PERR_SET(1U)
20400 #define S_FSO_HDR_SRAM_PERR_SET3 7
20401 #define V_FSO_HDR_SRAM_PERR_SET3(x) ((x) << S_FSO_HDR_SRAM_PERR_SET3)
20402 #define F_FSO_HDR_SRAM_PERR_SET3 V_FSO_HDR_SRAM_PERR_SET3(1U)
20404 #define S_FSO_HDR_SRAM_PERR_SET2 6
20405 #define V_FSO_HDR_SRAM_PERR_SET2(x) ((x) << S_FSO_HDR_SRAM_PERR_SET2)
20406 #define F_FSO_HDR_SRAM_PERR_SET2 V_FSO_HDR_SRAM_PERR_SET2(1U)
20408 #define S_FSO_HDR_SRAM_PERR_SET1 5
20409 #define V_FSO_HDR_SRAM_PERR_SET1(x) ((x) << S_FSO_HDR_SRAM_PERR_SET1)
20410 #define F_FSO_HDR_SRAM_PERR_SET1 V_FSO_HDR_SRAM_PERR_SET1(1U)
20412 #define S_FSO_HDR_SRAM_PERR_SET0 4
20413 #define V_FSO_HDR_SRAM_PERR_SET0(x) ((x) << S_FSO_HDR_SRAM_PERR_SET0)
20414 #define F_FSO_HDR_SRAM_PERR_SET0 V_FSO_HDR_SRAM_PERR_SET0(1U)
20416 #define S_T10_PI_SRAM_PERR_SET3 3
20417 #define V_T10_PI_SRAM_PERR_SET3(x) ((x) << S_T10_PI_SRAM_PERR_SET3)
20418 #define F_T10_PI_SRAM_PERR_SET3 V_T10_PI_SRAM_PERR_SET3(1U)
20420 #define S_T10_PI_SRAM_PERR_SET2 2
20421 #define V_T10_PI_SRAM_PERR_SET2(x) ((x) << S_T10_PI_SRAM_PERR_SET2)
20422 #define F_T10_PI_SRAM_PERR_SET2 V_T10_PI_SRAM_PERR_SET2(1U)
20424 #define S_T10_PI_SRAM_PERR_SET1 1
20425 #define V_T10_PI_SRAM_PERR_SET1(x) ((x) << S_T10_PI_SRAM_PERR_SET1)
20426 #define F_T10_PI_SRAM_PERR_SET1 V_T10_PI_SRAM_PERR_SET1(1U)
20428 #define S_T10_PI_SRAM_PERR_SET0 0
20429 #define V_T10_PI_SRAM_PERR_SET0(x) ((x) << S_T10_PI_SRAM_PERR_SET0)
20430 #define F_T10_PI_SRAM_PERR_SET0 V_T10_PI_SRAM_PERR_SET0(1U)
20432 #define A_ULP_TX_INT_CAUSE_2 0x8e80
20433 #define A_ULP_TX_PERR_ENABLE_2 0x8e84
20434 #define A_ULP_TX_SE_CNT_ERR 0x8ea0
20436 #define S_ERR_CH3 12
20437 #define M_ERR_CH3 0xfU
20438 #define V_ERR_CH3(x) ((x) << S_ERR_CH3)
20439 #define G_ERR_CH3(x) (((x) >> S_ERR_CH3) & M_ERR_CH3)
20441 #define S_ERR_CH2 8
20442 #define M_ERR_CH2 0xfU
20443 #define V_ERR_CH2(x) ((x) << S_ERR_CH2)
20444 #define G_ERR_CH2(x) (((x) >> S_ERR_CH2) & M_ERR_CH2)
20446 #define S_ERR_CH1 4
20447 #define M_ERR_CH1 0xfU
20448 #define V_ERR_CH1(x) ((x) << S_ERR_CH1)
20449 #define G_ERR_CH1(x) (((x) >> S_ERR_CH1) & M_ERR_CH1)
20451 #define S_ERR_CH0 0
20452 #define M_ERR_CH0 0xfU
20453 #define V_ERR_CH0(x) ((x) << S_ERR_CH0)
20454 #define G_ERR_CH0(x) (((x) >> S_ERR_CH0) & M_ERR_CH0)
20456 #define A_ULP_TX_T5_SE_CNT_ERR 0x8ea0
20457 #define A_ULP_TX_SE_CNT_CLR 0x8ea4
20459 #define S_CLR_DROP 16
20460 #define M_CLR_DROP 0xfU
20461 #define V_CLR_DROP(x) ((x) << S_CLR_DROP)
20462 #define G_CLR_DROP(x) (((x) >> S_CLR_DROP) & M_CLR_DROP)
20464 #define S_CLR_CH3 12
20465 #define M_CLR_CH3 0xfU
20466 #define V_CLR_CH3(x) ((x) << S_CLR_CH3)
20467 #define G_CLR_CH3(x) (((x) >> S_CLR_CH3) & M_CLR_CH3)
20469 #define S_CLR_CH2 8
20470 #define M_CLR_CH2 0xfU
20471 #define V_CLR_CH2(x) ((x) << S_CLR_CH2)
20472 #define G_CLR_CH2(x) (((x) >> S_CLR_CH2) & M_CLR_CH2)
20474 #define S_CLR_CH1 4
20475 #define M_CLR_CH1 0xfU
20476 #define V_CLR_CH1(x) ((x) << S_CLR_CH1)
20477 #define G_CLR_CH1(x) (((x) >> S_CLR_CH1) & M_CLR_CH1)
20479 #define S_CLR_CH0 0
20480 #define M_CLR_CH0 0xfU
20481 #define V_CLR_CH0(x) ((x) << S_CLR_CH0)
20482 #define G_CLR_CH0(x) (((x) >> S_CLR_CH0) & M_CLR_CH0)
20484 #define A_ULP_TX_T5_SE_CNT_CLR 0x8ea4
20485 #define A_ULP_TX_SE_CNT_CH0 0x8ea8
20487 #define S_SOP_CNT_ULP2TP 28
20488 #define M_SOP_CNT_ULP2TP 0xfU
20489 #define V_SOP_CNT_ULP2TP(x) ((x) << S_SOP_CNT_ULP2TP)
20490 #define G_SOP_CNT_ULP2TP(x) (((x) >> S_SOP_CNT_ULP2TP) & M_SOP_CNT_ULP2TP)
20492 #define S_EOP_CNT_ULP2TP 24
20493 #define M_EOP_CNT_ULP2TP 0xfU
20494 #define V_EOP_CNT_ULP2TP(x) ((x) << S_EOP_CNT_ULP2TP)
20495 #define G_EOP_CNT_ULP2TP(x) (((x) >> S_EOP_CNT_ULP2TP) & M_EOP_CNT_ULP2TP)
20497 #define S_SOP_CNT_LSO_IN 20
20498 #define M_SOP_CNT_LSO_IN 0xfU
20499 #define V_SOP_CNT_LSO_IN(x) ((x) << S_SOP_CNT_LSO_IN)
20500 #define G_SOP_CNT_LSO_IN(x) (((x) >> S_SOP_CNT_LSO_IN) & M_SOP_CNT_LSO_IN)
20502 #define S_EOP_CNT_LSO_IN 16
20503 #define M_EOP_CNT_LSO_IN 0xfU
20504 #define V_EOP_CNT_LSO_IN(x) ((x) << S_EOP_CNT_LSO_IN)
20505 #define G_EOP_CNT_LSO_IN(x) (((x) >> S_EOP_CNT_LSO_IN) & M_EOP_CNT_LSO_IN)
20507 #define S_SOP_CNT_ALG_IN 12
20508 #define M_SOP_CNT_ALG_IN 0xfU
20509 #define V_SOP_CNT_ALG_IN(x) ((x) << S_SOP_CNT_ALG_IN)
20510 #define G_SOP_CNT_ALG_IN(x) (((x) >> S_SOP_CNT_ALG_IN) & M_SOP_CNT_ALG_IN)
20512 #define S_EOP_CNT_ALG_IN 8
20513 #define M_EOP_CNT_ALG_IN 0xfU
20514 #define V_EOP_CNT_ALG_IN(x) ((x) << S_EOP_CNT_ALG_IN)
20515 #define G_EOP_CNT_ALG_IN(x) (((x) >> S_EOP_CNT_ALG_IN) & M_EOP_CNT_ALG_IN)
20517 #define S_SOP_CNT_CIM2ULP 4
20518 #define M_SOP_CNT_CIM2ULP 0xfU
20519 #define V_SOP_CNT_CIM2ULP(x) ((x) << S_SOP_CNT_CIM2ULP)
20520 #define G_SOP_CNT_CIM2ULP(x) (((x) >> S_SOP_CNT_CIM2ULP) & M_SOP_CNT_CIM2ULP)
20522 #define S_EOP_CNT_CIM2ULP 0
20523 #define M_EOP_CNT_CIM2ULP 0xfU
20524 #define V_EOP_CNT_CIM2ULP(x) ((x) << S_EOP_CNT_CIM2ULP)
20525 #define G_EOP_CNT_CIM2ULP(x) (((x) >> S_EOP_CNT_CIM2ULP) & M_EOP_CNT_CIM2ULP)
20527 #define A_ULP_TX_T5_SE_CNT_CH0 0x8ea8
20528 #define A_ULP_TX_SE_CNT_CH1 0x8eac
20529 #define A_ULP_TX_T5_SE_CNT_CH1 0x8eac
20530 #define A_ULP_TX_SE_CNT_CH2 0x8eb0
20531 #define A_ULP_TX_T5_SE_CNT_CH2 0x8eb0
20532 #define A_ULP_TX_SE_CNT_CH3 0x8eb4
20533 #define A_ULP_TX_T5_SE_CNT_CH3 0x8eb4
20534 #define A_ULP_TX_DROP_CNT 0x8eb8
20536 #define S_DROP_CH3 12
20537 #define M_DROP_CH3 0xfU
20538 #define V_DROP_CH3(x) ((x) << S_DROP_CH3)
20539 #define G_DROP_CH3(x) (((x) >> S_DROP_CH3) & M_DROP_CH3)
20541 #define S_DROP_CH2 8
20542 #define M_DROP_CH2 0xfU
20543 #define V_DROP_CH2(x) ((x) << S_DROP_CH2)
20544 #define G_DROP_CH2(x) (((x) >> S_DROP_CH2) & M_DROP_CH2)
20546 #define S_DROP_CH1 4
20547 #define M_DROP_CH1 0xfU
20548 #define V_DROP_CH1(x) ((x) << S_DROP_CH1)
20549 #define G_DROP_CH1(x) (((x) >> S_DROP_CH1) & M_DROP_CH1)
20551 #define S_DROP_CH0 0
20552 #define M_DROP_CH0 0xfU
20553 #define V_DROP_CH0(x) ((x) << S_DROP_CH0)
20554 #define G_DROP_CH0(x) (((x) >> S_DROP_CH0) & M_DROP_CH0)
20556 #define A_ULP_TX_T5_DROP_CNT 0x8eb8
20557 #define A_ULP_TX_CSU_REVISION 0x8ebc
20558 #define A_ULP_TX_LA_RDPTR_0 0x8ec0
20559 #define A_ULP_TX_LA_RDDATA_0 0x8ec4
20560 #define A_ULP_TX_LA_WRPTR_0 0x8ec8
20561 #define A_ULP_TX_LA_RESERVED_0 0x8ecc
20562 #define A_ULP_TX_LA_RDPTR_1 0x8ed0
20563 #define A_ULP_TX_LA_RDDATA_1 0x8ed4
20564 #define A_ULP_TX_LA_WRPTR_1 0x8ed8
20565 #define A_ULP_TX_LA_RESERVED_1 0x8edc
20566 #define A_ULP_TX_LA_RDPTR_2 0x8ee0
20567 #define A_ULP_TX_LA_RDDATA_2 0x8ee4
20568 #define A_ULP_TX_LA_WRPTR_2 0x8ee8
20569 #define A_ULP_TX_LA_RESERVED_2 0x8eec
20570 #define A_ULP_TX_LA_RDPTR_3 0x8ef0
20571 #define A_ULP_TX_LA_RDDATA_3 0x8ef4
20572 #define A_ULP_TX_LA_WRPTR_3 0x8ef8
20573 #define A_ULP_TX_LA_RESERVED_3 0x8efc
20574 #define A_ULP_TX_LA_RDPTR_4 0x8f00
20575 #define A_ULP_TX_LA_RDDATA_4 0x8f04
20576 #define A_ULP_TX_LA_WRPTR_4 0x8f08
20577 #define A_ULP_TX_LA_RESERVED_4 0x8f0c
20578 #define A_ULP_TX_LA_RDPTR_5 0x8f10
20579 #define A_ULP_TX_LA_RDDATA_5 0x8f14
20580 #define A_ULP_TX_LA_WRPTR_5 0x8f18
20581 #define A_ULP_TX_LA_RESERVED_5 0x8f1c
20582 #define A_ULP_TX_LA_RDPTR_6 0x8f20
20583 #define A_ULP_TX_LA_RDDATA_6 0x8f24
20584 #define A_ULP_TX_LA_WRPTR_6 0x8f28
20585 #define A_ULP_TX_LA_RESERVED_6 0x8f2c
20586 #define A_ULP_TX_LA_RDPTR_7 0x8f30
20587 #define A_ULP_TX_LA_RDDATA_7 0x8f34
20588 #define A_ULP_TX_LA_WRPTR_7 0x8f38
20589 #define A_ULP_TX_LA_RESERVED_7 0x8f3c
20590 #define A_ULP_TX_LA_RDPTR_8 0x8f40
20591 #define A_ULP_TX_LA_RDDATA_8 0x8f44
20592 #define A_ULP_TX_LA_WRPTR_8 0x8f48
20593 #define A_ULP_TX_LA_RESERVED_8 0x8f4c
20594 #define A_ULP_TX_LA_RDPTR_9 0x8f50
20595 #define A_ULP_TX_LA_RDDATA_9 0x8f54
20596 #define A_ULP_TX_LA_WRPTR_9 0x8f58
20597 #define A_ULP_TX_LA_RESERVED_9 0x8f5c
20598 #define A_ULP_TX_LA_RDPTR_10 0x8f60
20599 #define A_ULP_TX_LA_RDDATA_10 0x8f64
20600 #define A_ULP_TX_LA_WRPTR_10 0x8f68
20601 #define A_ULP_TX_LA_RESERVED_10 0x8f6c
20602 #define A_ULP_TX_ASIC_DEBUG_CTRL 0x8f70
20605 #define V_LA_WR0(x) ((x) << S_LA_WR0)
20606 #define F_LA_WR0 V_LA_WR0(1U)
20608 #define A_ULP_TX_ASIC_DEBUG_0 0x8f74
20609 #define A_ULP_TX_ASIC_DEBUG_1 0x8f78
20610 #define A_ULP_TX_ASIC_DEBUG_2 0x8f7c
20611 #define A_ULP_TX_ASIC_DEBUG_3 0x8f80
20612 #define A_ULP_TX_ASIC_DEBUG_4 0x8f84
20614 /* registers for module PM_RX */
20615 #define PM_RX_BASE_ADDR 0x8fc0
20617 #define A_PM_RX_CFG 0x8fc0
20618 #define A_PM_RX_MODE 0x8fc4
20620 #define S_RX_USE_BUNDLE_LEN 4
20621 #define V_RX_USE_BUNDLE_LEN(x) ((x) << S_RX_USE_BUNDLE_LEN)
20622 #define F_RX_USE_BUNDLE_LEN V_RX_USE_BUNDLE_LEN(1U)
20624 #define S_STAT_TO_CH 3
20625 #define V_STAT_TO_CH(x) ((x) << S_STAT_TO_CH)
20626 #define F_STAT_TO_CH V_STAT_TO_CH(1U)
20628 #define S_STAT_FROM_CH 1
20629 #define M_STAT_FROM_CH 0x3U
20630 #define V_STAT_FROM_CH(x) ((x) << S_STAT_FROM_CH)
20631 #define G_STAT_FROM_CH(x) (((x) >> S_STAT_FROM_CH) & M_STAT_FROM_CH)
20633 #define S_PREFETCH_ENABLE 0
20634 #define V_PREFETCH_ENABLE(x) ((x) << S_PREFETCH_ENABLE)
20635 #define F_PREFETCH_ENABLE V_PREFETCH_ENABLE(1U)
20637 #define A_PM_RX_STAT_CONFIG 0x8fc8
20638 #define A_PM_RX_STAT_COUNT 0x8fcc
20639 #define A_PM_RX_STAT_LSB 0x8fd0
20640 #define A_PM_RX_DBG_CTRL 0x8fd0
20642 #define S_OSPIWRBUSY_T5 21
20643 #define M_OSPIWRBUSY_T5 0x3U
20644 #define V_OSPIWRBUSY_T5(x) ((x) << S_OSPIWRBUSY_T5)
20645 #define G_OSPIWRBUSY_T5(x) (((x) >> S_OSPIWRBUSY_T5) & M_OSPIWRBUSY_T5)
20647 #define S_ISPIWRBUSY 17
20648 #define M_ISPIWRBUSY 0xfU
20649 #define V_ISPIWRBUSY(x) ((x) << S_ISPIWRBUSY)
20650 #define G_ISPIWRBUSY(x) (((x) >> S_ISPIWRBUSY) & M_ISPIWRBUSY)
20652 #define S_PMDBGADDR 0
20653 #define M_PMDBGADDR 0x1ffffU
20654 #define V_PMDBGADDR(x) ((x) << S_PMDBGADDR)
20655 #define G_PMDBGADDR(x) (((x) >> S_PMDBGADDR) & M_PMDBGADDR)
20657 #define A_PM_RX_STAT_MSB 0x8fd4
20658 #define A_PM_RX_DBG_DATA 0x8fd4
20659 #define A_PM_RX_INT_ENABLE 0x8fd8
20661 #define S_ZERO_E_CMD_ERROR 22
20662 #define V_ZERO_E_CMD_ERROR(x) ((x) << S_ZERO_E_CMD_ERROR)
20663 #define F_ZERO_E_CMD_ERROR V_ZERO_E_CMD_ERROR(1U)
20665 #define S_IESPI0_FIFO2X_RX_FRAMING_ERROR 21
20666 #define V_IESPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_FIFO2X_RX_FRAMING_ERROR)
20667 #define F_IESPI0_FIFO2X_RX_FRAMING_ERROR V_IESPI0_FIFO2X_RX_FRAMING_ERROR(1U)
20669 #define S_IESPI1_FIFO2X_RX_FRAMING_ERROR 20
20670 #define V_IESPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_FIFO2X_RX_FRAMING_ERROR)
20671 #define F_IESPI1_FIFO2X_RX_FRAMING_ERROR V_IESPI1_FIFO2X_RX_FRAMING_ERROR(1U)
20673 #define S_IESPI2_FIFO2X_RX_FRAMING_ERROR 19
20674 #define V_IESPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_FIFO2X_RX_FRAMING_ERROR)
20675 #define F_IESPI2_FIFO2X_RX_FRAMING_ERROR V_IESPI2_FIFO2X_RX_FRAMING_ERROR(1U)
20677 #define S_IESPI3_FIFO2X_RX_FRAMING_ERROR 18
20678 #define V_IESPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_FIFO2X_RX_FRAMING_ERROR)
20679 #define F_IESPI3_FIFO2X_RX_FRAMING_ERROR V_IESPI3_FIFO2X_RX_FRAMING_ERROR(1U)
20681 #define S_IESPI0_RX_FRAMING_ERROR 17
20682 #define V_IESPI0_RX_FRAMING_ERROR(x) ((x) << S_IESPI0_RX_FRAMING_ERROR)
20683 #define F_IESPI0_RX_FRAMING_ERROR V_IESPI0_RX_FRAMING_ERROR(1U)
20685 #define S_IESPI1_RX_FRAMING_ERROR 16
20686 #define V_IESPI1_RX_FRAMING_ERROR(x) ((x) << S_IESPI1_RX_FRAMING_ERROR)
20687 #define F_IESPI1_RX_FRAMING_ERROR V_IESPI1_RX_FRAMING_ERROR(1U)
20689 #define S_IESPI2_RX_FRAMING_ERROR 15
20690 #define V_IESPI2_RX_FRAMING_ERROR(x) ((x) << S_IESPI2_RX_FRAMING_ERROR)
20691 #define F_IESPI2_RX_FRAMING_ERROR V_IESPI2_RX_FRAMING_ERROR(1U)
20693 #define S_IESPI3_RX_FRAMING_ERROR 14
20694 #define V_IESPI3_RX_FRAMING_ERROR(x) ((x) << S_IESPI3_RX_FRAMING_ERROR)
20695 #define F_IESPI3_RX_FRAMING_ERROR V_IESPI3_RX_FRAMING_ERROR(1U)
20697 #define S_IESPI0_TX_FRAMING_ERROR 13
20698 #define V_IESPI0_TX_FRAMING_ERROR(x) ((x) << S_IESPI0_TX_FRAMING_ERROR)
20699 #define F_IESPI0_TX_FRAMING_ERROR V_IESPI0_TX_FRAMING_ERROR(1U)
20701 #define S_IESPI1_TX_FRAMING_ERROR 12
20702 #define V_IESPI1_TX_FRAMING_ERROR(x) ((x) << S_IESPI1_TX_FRAMING_ERROR)
20703 #define F_IESPI1_TX_FRAMING_ERROR V_IESPI1_TX_FRAMING_ERROR(1U)
20705 #define S_IESPI2_TX_FRAMING_ERROR 11
20706 #define V_IESPI2_TX_FRAMING_ERROR(x) ((x) << S_IESPI2_TX_FRAMING_ERROR)
20707 #define F_IESPI2_TX_FRAMING_ERROR V_IESPI2_TX_FRAMING_ERROR(1U)
20709 #define S_IESPI3_TX_FRAMING_ERROR 10
20710 #define V_IESPI3_TX_FRAMING_ERROR(x) ((x) << S_IESPI3_TX_FRAMING_ERROR)
20711 #define F_IESPI3_TX_FRAMING_ERROR V_IESPI3_TX_FRAMING_ERROR(1U)
20713 #define S_OCSPI0_RX_FRAMING_ERROR 9
20714 #define V_OCSPI0_RX_FRAMING_ERROR(x) ((x) << S_OCSPI0_RX_FRAMING_ERROR)
20715 #define F_OCSPI0_RX_FRAMING_ERROR V_OCSPI0_RX_FRAMING_ERROR(1U)
20717 #define S_OCSPI1_RX_FRAMING_ERROR 8
20718 #define V_OCSPI1_RX_FRAMING_ERROR(x) ((x) << S_OCSPI1_RX_FRAMING_ERROR)
20719 #define F_OCSPI1_RX_FRAMING_ERROR V_OCSPI1_RX_FRAMING_ERROR(1U)
20721 #define S_OCSPI0_TX_FRAMING_ERROR 7
20722 #define V_OCSPI0_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_TX_FRAMING_ERROR)
20723 #define F_OCSPI0_TX_FRAMING_ERROR V_OCSPI0_TX_FRAMING_ERROR(1U)
20725 #define S_OCSPI1_TX_FRAMING_ERROR 6
20726 #define V_OCSPI1_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_TX_FRAMING_ERROR)
20727 #define F_OCSPI1_TX_FRAMING_ERROR V_OCSPI1_TX_FRAMING_ERROR(1U)
20729 #define S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR 5
20730 #define V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI0_OFIFO2X_TX_FRAMING_ERROR)
20731 #define F_OCSPI0_OFIFO2X_TX_FRAMING_ERROR V_OCSPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
20733 #define S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR 4
20734 #define V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OCSPI1_OFIFO2X_TX_FRAMING_ERROR)
20735 #define F_OCSPI1_OFIFO2X_TX_FRAMING_ERROR V_OCSPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
20737 #define S_OCSPI_PAR_ERROR 3
20738 #define V_OCSPI_PAR_ERROR(x) ((x) << S_OCSPI_PAR_ERROR)
20739 #define F_OCSPI_PAR_ERROR V_OCSPI_PAR_ERROR(1U)
20741 #define S_DB_OPTIONS_PAR_ERROR 2
20742 #define V_DB_OPTIONS_PAR_ERROR(x) ((x) << S_DB_OPTIONS_PAR_ERROR)
20743 #define F_DB_OPTIONS_PAR_ERROR V_DB_OPTIONS_PAR_ERROR(1U)
20745 #define S_IESPI_PAR_ERROR 1
20746 #define V_IESPI_PAR_ERROR(x) ((x) << S_IESPI_PAR_ERROR)
20747 #define F_IESPI_PAR_ERROR V_IESPI_PAR_ERROR(1U)
20749 #define S_E_PCMD_PAR_ERROR 0
20750 #define V_E_PCMD_PAR_ERROR(x) ((x) << S_E_PCMD_PAR_ERROR)
20751 #define F_E_PCMD_PAR_ERROR V_E_PCMD_PAR_ERROR(1U)
20753 #define S_OSPI_OVERFLOW1 28
20754 #define V_OSPI_OVERFLOW1(x) ((x) << S_OSPI_OVERFLOW1)
20755 #define F_OSPI_OVERFLOW1 V_OSPI_OVERFLOW1(1U)
20757 #define S_OSPI_OVERFLOW0 27
20758 #define V_OSPI_OVERFLOW0(x) ((x) << S_OSPI_OVERFLOW0)
20759 #define F_OSPI_OVERFLOW0 V_OSPI_OVERFLOW0(1U)
20761 #define S_MA_INTF_SDC_ERR 26
20762 #define V_MA_INTF_SDC_ERR(x) ((x) << S_MA_INTF_SDC_ERR)
20763 #define F_MA_INTF_SDC_ERR V_MA_INTF_SDC_ERR(1U)
20765 #define S_BUNDLE_LEN_PARERR 25
20766 #define V_BUNDLE_LEN_PARERR(x) ((x) << S_BUNDLE_LEN_PARERR)
20767 #define F_BUNDLE_LEN_PARERR V_BUNDLE_LEN_PARERR(1U)
20769 #define S_BUNDLE_LEN_OVFL 24
20770 #define V_BUNDLE_LEN_OVFL(x) ((x) << S_BUNDLE_LEN_OVFL)
20771 #define F_BUNDLE_LEN_OVFL V_BUNDLE_LEN_OVFL(1U)
20773 #define S_SDC_ERR 23
20774 #define V_SDC_ERR(x) ((x) << S_SDC_ERR)
20775 #define F_SDC_ERR V_SDC_ERR(1U)
20777 #define A_PM_RX_INT_CAUSE 0x8fdc
20778 #define A_PM_RX_ISPI_DBG_4B_DATA0 0x10000
20779 #define A_PM_RX_ISPI_DBG_4B_DATA1 0x10001
20780 #define A_PM_RX_ISPI_DBG_4B_DATA2 0x10002
20781 #define A_PM_RX_ISPI_DBG_4B_DATA3 0x10003
20782 #define A_PM_RX_ISPI_DBG_4B_DATA4 0x10004
20783 #define A_PM_RX_ISPI_DBG_4B_DATA5 0x10005
20784 #define A_PM_RX_ISPI_DBG_4B_DATA6 0x10006
20785 #define A_PM_RX_ISPI_DBG_4B_DATA7 0x10007
20786 #define A_PM_RX_ISPI_DBG_4B_DATA8 0x10008
20787 #define A_PM_RX_OSPI_DBG_4B_DATA0 0x10009
20788 #define A_PM_RX_OSPI_DBG_4B_DATA1 0x1000a
20789 #define A_PM_RX_OSPI_DBG_4B_DATA2 0x1000b
20790 #define A_PM_RX_OSPI_DBG_4B_DATA3 0x1000c
20791 #define A_PM_RX_OSPI_DBG_4B_DATA4 0x1000d
20792 #define A_PM_RX_OSPI_DBG_4B_DATA5 0x1000e
20793 #define A_PM_RX_OSPI_DBG_4B_DATA6 0x1000f
20794 #define A_PM_RX_OSPI_DBG_4B_DATA7 0x10010
20795 #define A_PM_RX_OSPI_DBG_4B_DATA8 0x10011
20796 #define A_PM_RX_OSPI_DBG_4B_DATA9 0x10012
20797 #define A_PM_RX_DBG_STAT_MSB 0x10013
20798 #define A_PM_RX_DBG_STAT_LSB 0x10014
20799 #define A_PM_RX_DBG_RSVD_FLIT_CNT 0x10015
20801 #define S_I_TO_O_PATH_RSVD_FLIT_BACKUP 12
20802 #define M_I_TO_O_PATH_RSVD_FLIT_BACKUP 0xfU
20803 #define V_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT_BACKUP)
20804 #define G_I_TO_O_PATH_RSVD_FLIT_BACKUP(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT_BACKUP) & M_I_TO_O_PATH_RSVD_FLIT_BACKUP)
20806 #define S_I_TO_O_PATH_RSVD_FLIT 8
20807 #define M_I_TO_O_PATH_RSVD_FLIT 0xfU
20808 #define V_I_TO_O_PATH_RSVD_FLIT(x) ((x) << S_I_TO_O_PATH_RSVD_FLIT)
20809 #define G_I_TO_O_PATH_RSVD_FLIT(x) (((x) >> S_I_TO_O_PATH_RSVD_FLIT) & M_I_TO_O_PATH_RSVD_FLIT)
20811 #define S_PRFCH_RSVD_FLIT 4
20812 #define M_PRFCH_RSVD_FLIT 0xfU
20813 #define V_PRFCH_RSVD_FLIT(x) ((x) << S_PRFCH_RSVD_FLIT)
20814 #define G_PRFCH_RSVD_FLIT(x) (((x) >> S_PRFCH_RSVD_FLIT) & M_PRFCH_RSVD_FLIT)
20816 #define S_OSPI_RSVD_FLIT 0
20817 #define M_OSPI_RSVD_FLIT 0xfU
20818 #define V_OSPI_RSVD_FLIT(x) ((x) << S_OSPI_RSVD_FLIT)
20819 #define G_OSPI_RSVD_FLIT(x) (((x) >> S_OSPI_RSVD_FLIT) & M_OSPI_RSVD_FLIT)
20821 #define A_PM_RX_SDC_EN 0x10016
20824 #define V_SDC_EN(x) ((x) << S_SDC_EN)
20825 #define F_SDC_EN V_SDC_EN(1U)
20827 #define A_PM_RX_INOUT_FIFO_DBG_CHNL_SEL 0x10017
20829 #define S_CHNL_3_SEL 3
20830 #define V_CHNL_3_SEL(x) ((x) << S_CHNL_3_SEL)
20831 #define F_CHNL_3_SEL V_CHNL_3_SEL(1U)
20833 #define S_CHNL_2_SEL 2
20834 #define V_CHNL_2_SEL(x) ((x) << S_CHNL_2_SEL)
20835 #define F_CHNL_2_SEL V_CHNL_2_SEL(1U)
20837 #define S_CHNL_1_SEL 1
20838 #define V_CHNL_1_SEL(x) ((x) << S_CHNL_1_SEL)
20839 #define F_CHNL_1_SEL V_CHNL_1_SEL(1U)
20841 #define S_CHNL_0_SEL 0
20842 #define V_CHNL_0_SEL(x) ((x) << S_CHNL_0_SEL)
20843 #define F_CHNL_0_SEL V_CHNL_0_SEL(1U)
20845 #define A_PM_RX_INOUT_FIFO_DBG_WR 0x10018
20847 #define S_O_FIFO_WRITE 3
20848 #define V_O_FIFO_WRITE(x) ((x) << S_O_FIFO_WRITE)
20849 #define F_O_FIFO_WRITE V_O_FIFO_WRITE(1U)
20851 #define S_I_FIFO_WRITE 2
20852 #define V_I_FIFO_WRITE(x) ((x) << S_I_FIFO_WRITE)
20853 #define F_I_FIFO_WRITE V_I_FIFO_WRITE(1U)
20855 #define S_O_FIFO_READ 1
20856 #define V_O_FIFO_READ(x) ((x) << S_O_FIFO_READ)
20857 #define F_O_FIFO_READ V_O_FIFO_READ(1U)
20859 #define S_I_FIFO_READ 0
20860 #define V_I_FIFO_READ(x) ((x) << S_I_FIFO_READ)
20861 #define F_I_FIFO_READ V_I_FIFO_READ(1U)
20863 #define A_PM_RX_INPUT_FIFO_STR_FWD_EN 0x10019
20865 #define S_ISPI_STR_FWD_EN 0
20866 #define V_ISPI_STR_FWD_EN(x) ((x) << S_ISPI_STR_FWD_EN)
20867 #define F_ISPI_STR_FWD_EN V_ISPI_STR_FWD_EN(1U)
20869 #define A_PM_RX_PRFTCH_ACROSS_BNDLE_EN 0x1001a
20871 #define S_PRFTCH_ACROSS_BNDLE_EN 0
20872 #define V_PRFTCH_ACROSS_BNDLE_EN(x) ((x) << S_PRFTCH_ACROSS_BNDLE_EN)
20873 #define F_PRFTCH_ACROSS_BNDLE_EN V_PRFTCH_ACROSS_BNDLE_EN(1U)
20875 #define A_PM_RX_PRFTCH_WRR_ENABLE 0x1001b
20877 #define S_PRFTCH_WRR_ENABLE 0
20878 #define V_PRFTCH_WRR_ENABLE(x) ((x) << S_PRFTCH_WRR_ENABLE)
20879 #define F_PRFTCH_WRR_ENABLE V_PRFTCH_WRR_ENABLE(1U)
20881 #define A_PM_RX_PRFTCH_WRR_MAX_DEFICIT_CNT 0x1001c
20883 #define S_CHNL1_MAX_DEFICIT_CNT 16
20884 #define M_CHNL1_MAX_DEFICIT_CNT 0xffffU
20885 #define V_CHNL1_MAX_DEFICIT_CNT(x) ((x) << S_CHNL1_MAX_DEFICIT_CNT)
20886 #define G_CHNL1_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL1_MAX_DEFICIT_CNT) & M_CHNL1_MAX_DEFICIT_CNT)
20888 #define S_CHNL0_MAX_DEFICIT_CNT 0
20889 #define M_CHNL0_MAX_DEFICIT_CNT 0xffffU
20890 #define V_CHNL0_MAX_DEFICIT_CNT(x) ((x) << S_CHNL0_MAX_DEFICIT_CNT)
20891 #define G_CHNL0_MAX_DEFICIT_CNT(x) (((x) >> S_CHNL0_MAX_DEFICIT_CNT) & M_CHNL0_MAX_DEFICIT_CNT)
20893 #define A_PM_RX_FEATURE_EN 0x1001d
20895 #define S_PIO_CH_DEFICIT_CTL_EN_RX 0
20896 #define V_PIO_CH_DEFICIT_CTL_EN_RX(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN_RX)
20897 #define F_PIO_CH_DEFICIT_CTL_EN_RX V_PIO_CH_DEFICIT_CTL_EN_RX(1U)
20899 #define A_PM_RX_CH0_OSPI_DEFICIT_THRSHLD 0x1001e
20901 #define S_CH0_OSPI_DEFICIT_THRSHLD 0
20902 #define M_CH0_OSPI_DEFICIT_THRSHLD 0xfffU
20903 #define V_CH0_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH0_OSPI_DEFICIT_THRSHLD)
20904 #define G_CH0_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH0_OSPI_DEFICIT_THRSHLD) & M_CH0_OSPI_DEFICIT_THRSHLD)
20906 #define A_PM_RX_CH1_OSPI_DEFICIT_THRSHLD 0x1001f
20908 #define S_CH1_OSPI_DEFICIT_THRSHLD 0
20909 #define M_CH1_OSPI_DEFICIT_THRSHLD 0xfffU
20910 #define V_CH1_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH1_OSPI_DEFICIT_THRSHLD)
20911 #define G_CH1_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH1_OSPI_DEFICIT_THRSHLD) & M_CH1_OSPI_DEFICIT_THRSHLD)
20913 #define A_PM_RX_INT_CAUSE_MASK_HALT 0x10020
20914 #define A_PM_RX_DBG_STAT0 0x10021
20916 #define S_RX_RD_I_BUSY 29
20917 #define V_RX_RD_I_BUSY(x) ((x) << S_RX_RD_I_BUSY)
20918 #define F_RX_RD_I_BUSY V_RX_RD_I_BUSY(1U)
20920 #define S_RX_WR_TO_O_BUSY 28
20921 #define V_RX_WR_TO_O_BUSY(x) ((x) << S_RX_WR_TO_O_BUSY)
20922 #define F_RX_WR_TO_O_BUSY V_RX_WR_TO_O_BUSY(1U)
20924 #define S_RX_M_TO_O_BUSY 27
20925 #define V_RX_M_TO_O_BUSY(x) ((x) << S_RX_M_TO_O_BUSY)
20926 #define F_RX_M_TO_O_BUSY V_RX_M_TO_O_BUSY(1U)
20928 #define S_RX_I_TO_M_BUSY 26
20929 #define V_RX_I_TO_M_BUSY(x) ((x) << S_RX_I_TO_M_BUSY)
20930 #define F_RX_I_TO_M_BUSY V_RX_I_TO_M_BUSY(1U)
20932 #define S_RX_PCMD_FB_ONLY 25
20933 #define V_RX_PCMD_FB_ONLY(x) ((x) << S_RX_PCMD_FB_ONLY)
20934 #define F_RX_PCMD_FB_ONLY V_RX_PCMD_FB_ONLY(1U)
20936 #define S_RX_PCMD_MEM 24
20937 #define V_RX_PCMD_MEM(x) ((x) << S_RX_PCMD_MEM)
20938 #define F_RX_PCMD_MEM V_RX_PCMD_MEM(1U)
20940 #define S_RX_PCMD_BYPASS 23
20941 #define V_RX_PCMD_BYPASS(x) ((x) << S_RX_PCMD_BYPASS)
20942 #define F_RX_PCMD_BYPASS V_RX_PCMD_BYPASS(1U)
20944 #define S_RX_PCMD_EOP 22
20945 #define V_RX_PCMD_EOP(x) ((x) << S_RX_PCMD_EOP)
20946 #define F_RX_PCMD_EOP V_RX_PCMD_EOP(1U)
20948 #define S_RX_DUMPLICATE_PCMD_EOP 21
20949 #define V_RX_DUMPLICATE_PCMD_EOP(x) ((x) << S_RX_DUMPLICATE_PCMD_EOP)
20950 #define F_RX_DUMPLICATE_PCMD_EOP V_RX_DUMPLICATE_PCMD_EOP(1U)
20952 #define S_RX_PCMD_EOB 20
20953 #define V_RX_PCMD_EOB(x) ((x) << S_RX_PCMD_EOB)
20954 #define F_RX_PCMD_EOB V_RX_PCMD_EOB(1U)
20956 #define S_RX_PCMD_FB 16
20957 #define M_RX_PCMD_FB 0xfU
20958 #define V_RX_PCMD_FB(x) ((x) << S_RX_PCMD_FB)
20959 #define G_RX_PCMD_FB(x) (((x) >> S_RX_PCMD_FB) & M_RX_PCMD_FB)
20961 #define S_RX_PCMD_LEN 0
20962 #define M_RX_PCMD_LEN 0xffffU
20963 #define V_RX_PCMD_LEN(x) ((x) << S_RX_PCMD_LEN)
20964 #define G_RX_PCMD_LEN(x) (((x) >> S_RX_PCMD_LEN) & M_RX_PCMD_LEN)
20966 #define A_PM_RX_DBG_STAT1 0x10022
20968 #define S_RX_PCMD0_MEM 30
20969 #define V_RX_PCMD0_MEM(x) ((x) << S_RX_PCMD0_MEM)
20970 #define F_RX_PCMD0_MEM V_RX_PCMD0_MEM(1U)
20972 #define S_RX_FREE_OSPI_CNT0 18
20973 #define M_RX_FREE_OSPI_CNT0 0xfffU
20974 #define V_RX_FREE_OSPI_CNT0(x) ((x) << S_RX_FREE_OSPI_CNT0)
20975 #define G_RX_FREE_OSPI_CNT0(x) (((x) >> S_RX_FREE_OSPI_CNT0) & M_RX_FREE_OSPI_CNT0)
20977 #define S_RX_PCMD0_FLIT_LEN 6
20978 #define M_RX_PCMD0_FLIT_LEN 0xfffU
20979 #define V_RX_PCMD0_FLIT_LEN(x) ((x) << S_RX_PCMD0_FLIT_LEN)
20980 #define G_RX_PCMD0_FLIT_LEN(x) (((x) >> S_RX_PCMD0_FLIT_LEN) & M_RX_PCMD0_FLIT_LEN)
20982 #define S_RX_PCMD0_CMD 2
20983 #define M_RX_PCMD0_CMD 0xfU
20984 #define V_RX_PCMD0_CMD(x) ((x) << S_RX_PCMD0_CMD)
20985 #define G_RX_PCMD0_CMD(x) (((x) >> S_RX_PCMD0_CMD) & M_RX_PCMD0_CMD)
20987 #define S_RX_OFIFO_FULL0 1
20988 #define V_RX_OFIFO_FULL0(x) ((x) << S_RX_OFIFO_FULL0)
20989 #define F_RX_OFIFO_FULL0 V_RX_OFIFO_FULL0(1U)
20991 #define S_RX_PCMD0_BYPASS 0
20992 #define V_RX_PCMD0_BYPASS(x) ((x) << S_RX_PCMD0_BYPASS)
20993 #define F_RX_PCMD0_BYPASS V_RX_PCMD0_BYPASS(1U)
20995 #define A_PM_RX_DBG_STAT2 0x10023
20997 #define S_RX_PCMD1_MEM 30
20998 #define V_RX_PCMD1_MEM(x) ((x) << S_RX_PCMD1_MEM)
20999 #define F_RX_PCMD1_MEM V_RX_PCMD1_MEM(1U)
21001 #define S_RX_FREE_OSPI_CNT1 18
21002 #define M_RX_FREE_OSPI_CNT1 0xfffU
21003 #define V_RX_FREE_OSPI_CNT1(x) ((x) << S_RX_FREE_OSPI_CNT1)
21004 #define G_RX_FREE_OSPI_CNT1(x) (((x) >> S_RX_FREE_OSPI_CNT1) & M_RX_FREE_OSPI_CNT1)
21006 #define S_RX_PCMD1_FLIT_LEN 6
21007 #define M_RX_PCMD1_FLIT_LEN 0xfffU
21008 #define V_RX_PCMD1_FLIT_LEN(x) ((x) << S_RX_PCMD1_FLIT_LEN)
21009 #define G_RX_PCMD1_FLIT_LEN(x) (((x) >> S_RX_PCMD1_FLIT_LEN) & M_RX_PCMD1_FLIT_LEN)
21011 #define S_RX_PCMD1_CMD 2
21012 #define M_RX_PCMD1_CMD 0xfU
21013 #define V_RX_PCMD1_CMD(x) ((x) << S_RX_PCMD1_CMD)
21014 #define G_RX_PCMD1_CMD(x) (((x) >> S_RX_PCMD1_CMD) & M_RX_PCMD1_CMD)
21016 #define S_RX_OFIFO_FULL1 1
21017 #define V_RX_OFIFO_FULL1(x) ((x) << S_RX_OFIFO_FULL1)
21018 #define F_RX_OFIFO_FULL1 V_RX_OFIFO_FULL1(1U)
21020 #define S_RX_PCMD1_BYPASS 0
21021 #define V_RX_PCMD1_BYPASS(x) ((x) << S_RX_PCMD1_BYPASS)
21022 #define F_RX_PCMD1_BYPASS V_RX_PCMD1_BYPASS(1U)
21024 #define A_PM_RX_DBG_STAT3 0x10024
21026 #define S_RX_SET_PCMD_RES_RDY_RD 10
21027 #define M_RX_SET_PCMD_RES_RDY_RD 0x3U
21028 #define V_RX_SET_PCMD_RES_RDY_RD(x) ((x) << S_RX_SET_PCMD_RES_RDY_RD)
21029 #define G_RX_SET_PCMD_RES_RDY_RD(x) (((x) >> S_RX_SET_PCMD_RES_RDY_RD) & M_RX_SET_PCMD_RES_RDY_RD)
21031 #define S_RX_ISSUED_PREFETCH_RD_E_CLR 8
21032 #define M_RX_ISSUED_PREFETCH_RD_E_CLR 0x3U
21033 #define V_RX_ISSUED_PREFETCH_RD_E_CLR(x) ((x) << S_RX_ISSUED_PREFETCH_RD_E_CLR)
21034 #define G_RX_ISSUED_PREFETCH_RD_E_CLR(x) (((x) >> S_RX_ISSUED_PREFETCH_RD_E_CLR) & M_RX_ISSUED_PREFETCH_RD_E_CLR)
21036 #define S_RX_ISSUED_PREFETCH_RD 6
21037 #define M_RX_ISSUED_PREFETCH_RD 0x3U
21038 #define V_RX_ISSUED_PREFETCH_RD(x) ((x) << S_RX_ISSUED_PREFETCH_RD)
21039 #define G_RX_ISSUED_PREFETCH_RD(x) (((x) >> S_RX_ISSUED_PREFETCH_RD) & M_RX_ISSUED_PREFETCH_RD)
21041 #define S_RX_PCMD_RES_RDY 4
21042 #define M_RX_PCMD_RES_RDY 0x3U
21043 #define V_RX_PCMD_RES_RDY(x) ((x) << S_RX_PCMD_RES_RDY)
21044 #define G_RX_PCMD_RES_RDY(x) (((x) >> S_RX_PCMD_RES_RDY) & M_RX_PCMD_RES_RDY)
21046 #define S_RX_DB_VLD 3
21047 #define V_RX_DB_VLD(x) ((x) << S_RX_DB_VLD)
21048 #define F_RX_DB_VLD V_RX_DB_VLD(1U)
21050 #define S_RX_FIRST_BUNDLE 1
21051 #define M_RX_FIRST_BUNDLE 0x3U
21052 #define V_RX_FIRST_BUNDLE(x) ((x) << S_RX_FIRST_BUNDLE)
21053 #define G_RX_FIRST_BUNDLE(x) (((x) >> S_RX_FIRST_BUNDLE) & M_RX_FIRST_BUNDLE)
21055 #define S_RX_SDC_DRDY 0
21056 #define V_RX_SDC_DRDY(x) ((x) << S_RX_SDC_DRDY)
21057 #define F_RX_SDC_DRDY V_RX_SDC_DRDY(1U)
21059 #define A_PM_RX_DBG_STAT4 0x10025
21061 #define S_RX_PCMD_VLD 26
21062 #define V_RX_PCMD_VLD(x) ((x) << S_RX_PCMD_VLD)
21063 #define F_RX_PCMD_VLD V_RX_PCMD_VLD(1U)
21065 #define S_RX_PCMD_TO_CH 25
21066 #define V_RX_PCMD_TO_CH(x) ((x) << S_RX_PCMD_TO_CH)
21067 #define F_RX_PCMD_TO_CH V_RX_PCMD_TO_CH(1U)
21069 #define S_RX_PCMD_FROM_CH 23
21070 #define M_RX_PCMD_FROM_CH 0x3U
21071 #define V_RX_PCMD_FROM_CH(x) ((x) << S_RX_PCMD_FROM_CH)
21072 #define G_RX_PCMD_FROM_CH(x) (((x) >> S_RX_PCMD_FROM_CH) & M_RX_PCMD_FROM_CH)
21074 #define S_RX_LINE 18
21075 #define M_RX_LINE 0x1fU
21076 #define V_RX_LINE(x) ((x) << S_RX_LINE)
21077 #define G_RX_LINE(x) (((x) >> S_RX_LINE) & M_RX_LINE)
21079 #define S_RX_IESPI_TXVALID 14
21080 #define M_RX_IESPI_TXVALID 0xfU
21081 #define V_RX_IESPI_TXVALID(x) ((x) << S_RX_IESPI_TXVALID)
21082 #define G_RX_IESPI_TXVALID(x) (((x) >> S_RX_IESPI_TXVALID) & M_RX_IESPI_TXVALID)
21084 #define S_RX_IESPI_TXFULL 10
21085 #define M_RX_IESPI_TXFULL 0xfU
21086 #define V_RX_IESPI_TXFULL(x) ((x) << S_RX_IESPI_TXFULL)
21087 #define G_RX_IESPI_TXFULL(x) (((x) >> S_RX_IESPI_TXFULL) & M_RX_IESPI_TXFULL)
21089 #define S_RX_PCMD_SRDY 8
21090 #define M_RX_PCMD_SRDY 0x3U
21091 #define V_RX_PCMD_SRDY(x) ((x) << S_RX_PCMD_SRDY)
21092 #define G_RX_PCMD_SRDY(x) (((x) >> S_RX_PCMD_SRDY) & M_RX_PCMD_SRDY)
21094 #define S_RX_PCMD_DRDY 6
21095 #define M_RX_PCMD_DRDY 0x3U
21096 #define V_RX_PCMD_DRDY(x) ((x) << S_RX_PCMD_DRDY)
21097 #define G_RX_PCMD_DRDY(x) (((x) >> S_RX_PCMD_DRDY) & M_RX_PCMD_DRDY)
21099 #define S_RX_PCMD_CMD 2
21100 #define M_RX_PCMD_CMD 0xfU
21101 #define V_RX_PCMD_CMD(x) ((x) << S_RX_PCMD_CMD)
21102 #define G_RX_PCMD_CMD(x) (((x) >> S_RX_PCMD_CMD) & M_RX_PCMD_CMD)
21104 #define S_DUPLICATE 0
21105 #define M_DUPLICATE 0x3U
21106 #define V_DUPLICATE(x) ((x) << S_DUPLICATE)
21107 #define G_DUPLICATE(x) (((x) >> S_DUPLICATE) & M_DUPLICATE)
21109 #define A_PM_RX_DBG_STAT5 0x10026
21111 #define S_RX_ATLST_1_PCMD_CH1 29
21112 #define V_RX_ATLST_1_PCMD_CH1(x) ((x) << S_RX_ATLST_1_PCMD_CH1)
21113 #define F_RX_ATLST_1_PCMD_CH1 V_RX_ATLST_1_PCMD_CH1(1U)
21115 #define S_RX_ATLST_1_PCMD_CH0 28
21116 #define V_RX_ATLST_1_PCMD_CH0(x) ((x) << S_RX_ATLST_1_PCMD_CH0)
21117 #define F_RX_ATLST_1_PCMD_CH0 V_RX_ATLST_1_PCMD_CH0(1U)
21119 #define S_RX_ISPI_TXVALID 20
21120 #define M_RX_ISPI_TXVALID 0xfU
21121 #define V_RX_ISPI_TXVALID(x) ((x) << S_RX_ISPI_TXVALID)
21122 #define G_RX_ISPI_TXVALID(x) (((x) >> S_RX_ISPI_TXVALID) & M_RX_ISPI_TXVALID)
21124 #define S_RX_ISPI_FULL 16
21125 #define M_RX_ISPI_FULL 0xfU
21126 #define V_RX_ISPI_FULL(x) ((x) << S_RX_ISPI_FULL)
21127 #define G_RX_ISPI_FULL(x) (((x) >> S_RX_ISPI_FULL) & M_RX_ISPI_FULL)
21129 #define S_RX_OSPI_TXVALID 14
21130 #define M_RX_OSPI_TXVALID 0x3U
21131 #define V_RX_OSPI_TXVALID(x) ((x) << S_RX_OSPI_TXVALID)
21132 #define G_RX_OSPI_TXVALID(x) (((x) >> S_RX_OSPI_TXVALID) & M_RX_OSPI_TXVALID)
21134 #define S_RX_OSPI_FULL 12
21135 #define M_RX_OSPI_FULL 0x3U
21136 #define V_RX_OSPI_FULL(x) ((x) << S_RX_OSPI_FULL)
21137 #define G_RX_OSPI_FULL(x) (((x) >> S_RX_OSPI_FULL) & M_RX_OSPI_FULL)
21139 #define S_RX_E_RXVALID 8
21140 #define M_RX_E_RXVALID 0xfU
21141 #define V_RX_E_RXVALID(x) ((x) << S_RX_E_RXVALID)
21142 #define G_RX_E_RXVALID(x) (((x) >> S_RX_E_RXVALID) & M_RX_E_RXVALID)
21144 #define S_RX_E_RXAFULL 4
21145 #define M_RX_E_RXAFULL 0xfU
21146 #define V_RX_E_RXAFULL(x) ((x) << S_RX_E_RXAFULL)
21147 #define G_RX_E_RXAFULL(x) (((x) >> S_RX_E_RXAFULL) & M_RX_E_RXAFULL)
21149 #define S_RX_C_TXVALID 2
21150 #define M_RX_C_TXVALID 0x3U
21151 #define V_RX_C_TXVALID(x) ((x) << S_RX_C_TXVALID)
21152 #define G_RX_C_TXVALID(x) (((x) >> S_RX_C_TXVALID) & M_RX_C_TXVALID)
21154 #define S_RX_C_TXAFULL 0
21155 #define M_RX_C_TXAFULL 0x3U
21156 #define V_RX_C_TXAFULL(x) ((x) << S_RX_C_TXAFULL)
21157 #define G_RX_C_TXAFULL(x) (((x) >> S_RX_C_TXAFULL) & M_RX_C_TXAFULL)
21159 #define A_PM_RX_DBG_STAT6 0x10027
21161 #define S_RX_M_INTRNL_FIFO_CNT 4
21162 #define M_RX_M_INTRNL_FIFO_CNT 0x3U
21163 #define V_RX_M_INTRNL_FIFO_CNT(x) ((x) << S_RX_M_INTRNL_FIFO_CNT)
21164 #define G_RX_M_INTRNL_FIFO_CNT(x) (((x) >> S_RX_M_INTRNL_FIFO_CNT) & M_RX_M_INTRNL_FIFO_CNT)
21166 #define S_RX_M_REQADDRRDY 3
21167 #define V_RX_M_REQADDRRDY(x) ((x) << S_RX_M_REQADDRRDY)
21168 #define F_RX_M_REQADDRRDY V_RX_M_REQADDRRDY(1U)
21170 #define S_RX_M_REQWRITE 2
21171 #define V_RX_M_REQWRITE(x) ((x) << S_RX_M_REQWRITE)
21172 #define F_RX_M_REQWRITE V_RX_M_REQWRITE(1U)
21174 #define S_RX_M_REQDATAVLD 1
21175 #define V_RX_M_REQDATAVLD(x) ((x) << S_RX_M_REQDATAVLD)
21176 #define F_RX_M_REQDATAVLD V_RX_M_REQDATAVLD(1U)
21178 #define S_RX_M_REQDATARDY 0
21179 #define V_RX_M_REQDATARDY(x) ((x) << S_RX_M_REQDATARDY)
21180 #define F_RX_M_REQDATARDY V_RX_M_REQDATARDY(1U)
21182 #define A_PM_RX_DBG_STAT7 0x10028
21184 #define S_RX_PCMD1_FREE_CNT 7
21185 #define M_RX_PCMD1_FREE_CNT 0x7fU
21186 #define V_RX_PCMD1_FREE_CNT(x) ((x) << S_RX_PCMD1_FREE_CNT)
21187 #define G_RX_PCMD1_FREE_CNT(x) (((x) >> S_RX_PCMD1_FREE_CNT) & M_RX_PCMD1_FREE_CNT)
21189 #define S_RX_PCMD0_FREE_CNT 0
21190 #define M_RX_PCMD0_FREE_CNT 0x7fU
21191 #define V_RX_PCMD0_FREE_CNT(x) ((x) << S_RX_PCMD0_FREE_CNT)
21192 #define G_RX_PCMD0_FREE_CNT(x) (((x) >> S_RX_PCMD0_FREE_CNT) & M_RX_PCMD0_FREE_CNT)
21194 #define A_PM_RX_DBG_STAT8 0x10029
21196 #define S_RX_IN_EOP_CNT3 28
21197 #define M_RX_IN_EOP_CNT3 0xfU
21198 #define V_RX_IN_EOP_CNT3(x) ((x) << S_RX_IN_EOP_CNT3)
21199 #define G_RX_IN_EOP_CNT3(x) (((x) >> S_RX_IN_EOP_CNT3) & M_RX_IN_EOP_CNT3)
21201 #define S_RX_IN_EOP_CNT2 24
21202 #define M_RX_IN_EOP_CNT2 0xfU
21203 #define V_RX_IN_EOP_CNT2(x) ((x) << S_RX_IN_EOP_CNT2)
21204 #define G_RX_IN_EOP_CNT2(x) (((x) >> S_RX_IN_EOP_CNT2) & M_RX_IN_EOP_CNT2)
21206 #define S_RX_IN_EOP_CNT1 20
21207 #define M_RX_IN_EOP_CNT1 0xfU
21208 #define V_RX_IN_EOP_CNT1(x) ((x) << S_RX_IN_EOP_CNT1)
21209 #define G_RX_IN_EOP_CNT1(x) (((x) >> S_RX_IN_EOP_CNT1) & M_RX_IN_EOP_CNT1)
21211 #define S_RX_IN_EOP_CNT0 16
21212 #define M_RX_IN_EOP_CNT0 0xfU
21213 #define V_RX_IN_EOP_CNT0(x) ((x) << S_RX_IN_EOP_CNT0)
21214 #define G_RX_IN_EOP_CNT0(x) (((x) >> S_RX_IN_EOP_CNT0) & M_RX_IN_EOP_CNT0)
21216 #define S_RX_IN_SOP_CNT3 12
21217 #define M_RX_IN_SOP_CNT3 0xfU
21218 #define V_RX_IN_SOP_CNT3(x) ((x) << S_RX_IN_SOP_CNT3)
21219 #define G_RX_IN_SOP_CNT3(x) (((x) >> S_RX_IN_SOP_CNT3) & M_RX_IN_SOP_CNT3)
21221 #define S_RX_IN_SOP_CNT2 8
21222 #define M_RX_IN_SOP_CNT2 0xfU
21223 #define V_RX_IN_SOP_CNT2(x) ((x) << S_RX_IN_SOP_CNT2)
21224 #define G_RX_IN_SOP_CNT2(x) (((x) >> S_RX_IN_SOP_CNT2) & M_RX_IN_SOP_CNT2)
21226 #define S_RX_IN_SOP_CNT1 4
21227 #define M_RX_IN_SOP_CNT1 0xfU
21228 #define V_RX_IN_SOP_CNT1(x) ((x) << S_RX_IN_SOP_CNT1)
21229 #define G_RX_IN_SOP_CNT1(x) (((x) >> S_RX_IN_SOP_CNT1) & M_RX_IN_SOP_CNT1)
21231 #define S_RX_IN_SOP_CNT0 0
21232 #define M_RX_IN_SOP_CNT0 0xfU
21233 #define V_RX_IN_SOP_CNT0(x) ((x) << S_RX_IN_SOP_CNT0)
21234 #define G_RX_IN_SOP_CNT0(x) (((x) >> S_RX_IN_SOP_CNT0) & M_RX_IN_SOP_CNT0)
21236 #define A_PM_RX_DBG_STAT9 0x1002a
21238 #define S_RX_RSVD0 28
21239 #define M_RX_RSVD0 0xfU
21240 #define V_RX_RSVD0(x) ((x) << S_RX_RSVD0)
21241 #define G_RX_RSVD0(x) (((x) >> S_RX_RSVD0) & M_RX_RSVD0)
21243 #define S_RX_RSVD1 24
21244 #define M_RX_RSVD1 0xfU
21245 #define V_RX_RSVD1(x) ((x) << S_RX_RSVD1)
21246 #define G_RX_RSVD1(x) (((x) >> S_RX_RSVD1) & M_RX_RSVD1)
21248 #define S_RX_OUT_EOP_CNT1 20
21249 #define M_RX_OUT_EOP_CNT1 0xfU
21250 #define V_RX_OUT_EOP_CNT1(x) ((x) << S_RX_OUT_EOP_CNT1)
21251 #define G_RX_OUT_EOP_CNT1(x) (((x) >> S_RX_OUT_EOP_CNT1) & M_RX_OUT_EOP_CNT1)
21253 #define S_RX_OUT_EOP_CNT0 16
21254 #define M_RX_OUT_EOP_CNT0 0xfU
21255 #define V_RX_OUT_EOP_CNT0(x) ((x) << S_RX_OUT_EOP_CNT0)
21256 #define G_RX_OUT_EOP_CNT0(x) (((x) >> S_RX_OUT_EOP_CNT0) & M_RX_OUT_EOP_CNT0)
21258 #define S_RX_RSVD2 12
21259 #define M_RX_RSVD2 0xfU
21260 #define V_RX_RSVD2(x) ((x) << S_RX_RSVD2)
21261 #define G_RX_RSVD2(x) (((x) >> S_RX_RSVD2) & M_RX_RSVD2)
21263 #define S_RX_RSVD3 8
21264 #define M_RX_RSVD3 0xfU
21265 #define V_RX_RSVD3(x) ((x) << S_RX_RSVD3)
21266 #define G_RX_RSVD3(x) (((x) >> S_RX_RSVD3) & M_RX_RSVD3)
21268 #define S_RX_OUT_SOP_CNT1 4
21269 #define M_RX_OUT_SOP_CNT1 0xfU
21270 #define V_RX_OUT_SOP_CNT1(x) ((x) << S_RX_OUT_SOP_CNT1)
21271 #define G_RX_OUT_SOP_CNT1(x) (((x) >> S_RX_OUT_SOP_CNT1) & M_RX_OUT_SOP_CNT1)
21273 #define S_RX_OUT_SOP_CNT0 0
21274 #define M_RX_OUT_SOP_CNT0 0xfU
21275 #define V_RX_OUT_SOP_CNT0(x) ((x) << S_RX_OUT_SOP_CNT0)
21276 #define G_RX_OUT_SOP_CNT0(x) (((x) >> S_RX_OUT_SOP_CNT0) & M_RX_OUT_SOP_CNT0)
21278 #define A_PM_RX_DBG_STAT10 0x1002b
21280 #define S_RX_CH_DEFICIT_BLOWED 24
21281 #define V_RX_CH_DEFICIT_BLOWED(x) ((x) << S_RX_CH_DEFICIT_BLOWED)
21282 #define F_RX_CH_DEFICIT_BLOWED V_RX_CH_DEFICIT_BLOWED(1U)
21284 #define S_RX_CH1_DEFICIT 12
21285 #define M_RX_CH1_DEFICIT 0xfffU
21286 #define V_RX_CH1_DEFICIT(x) ((x) << S_RX_CH1_DEFICIT)
21287 #define G_RX_CH1_DEFICIT(x) (((x) >> S_RX_CH1_DEFICIT) & M_RX_CH1_DEFICIT)
21289 #define S_RX_CH0_DEFICIT 0
21290 #define M_RX_CH0_DEFICIT 0xfffU
21291 #define V_RX_CH0_DEFICIT(x) ((x) << S_RX_CH0_DEFICIT)
21292 #define G_RX_CH0_DEFICIT(x) (((x) >> S_RX_CH0_DEFICIT) & M_RX_CH0_DEFICIT)
21294 #define A_PM_RX_DBG_STAT11 0x1002c
21296 #define S_RX_BUNDLE_LEN_SRDY 30
21297 #define M_RX_BUNDLE_LEN_SRDY 0x3U
21298 #define V_RX_BUNDLE_LEN_SRDY(x) ((x) << S_RX_BUNDLE_LEN_SRDY)
21299 #define G_RX_BUNDLE_LEN_SRDY(x) (((x) >> S_RX_BUNDLE_LEN_SRDY) & M_RX_BUNDLE_LEN_SRDY)
21301 #define S_RX_RSVD11_1 28
21302 #define M_RX_RSVD11_1 0x3U
21303 #define V_RX_RSVD11_1(x) ((x) << S_RX_RSVD11_1)
21304 #define G_RX_RSVD11_1(x) (((x) >> S_RX_RSVD11_1) & M_RX_RSVD11_1)
21306 #define S_RX_BUNDLE_LEN1 16
21307 #define M_RX_BUNDLE_LEN1 0xfffU
21308 #define V_RX_BUNDLE_LEN1(x) ((x) << S_RX_BUNDLE_LEN1)
21309 #define G_RX_BUNDLE_LEN1(x) (((x) >> S_RX_BUNDLE_LEN1) & M_RX_BUNDLE_LEN1)
21311 #define S_RX_RSVD11 12
21312 #define M_RX_RSVD11 0xfU
21313 #define V_RX_RSVD11(x) ((x) << S_RX_RSVD11)
21314 #define G_RX_RSVD11(x) (((x) >> S_RX_RSVD11) & M_RX_RSVD11)
21316 #define S_RX_BUNDLE_LEN0 0
21317 #define M_RX_BUNDLE_LEN0 0xfffU
21318 #define V_RX_BUNDLE_LEN0(x) ((x) << S_RX_BUNDLE_LEN0)
21319 #define G_RX_BUNDLE_LEN0(x) (((x) >> S_RX_BUNDLE_LEN0) & M_RX_BUNDLE_LEN0)
21321 /* registers for module PM_TX */
21322 #define PM_TX_BASE_ADDR 0x8fe0
21324 #define A_PM_TX_CFG 0x8fe0
21326 #define S_CH3_OUTPUT 17
21327 #define M_CH3_OUTPUT 0x1fU
21328 #define V_CH3_OUTPUT(x) ((x) << S_CH3_OUTPUT)
21329 #define G_CH3_OUTPUT(x) (((x) >> S_CH3_OUTPUT) & M_CH3_OUTPUT)
21331 #define A_PM_TX_MODE 0x8fe4
21333 #define S_CONG_THRESH3 25
21334 #define M_CONG_THRESH3 0x7fU
21335 #define V_CONG_THRESH3(x) ((x) << S_CONG_THRESH3)
21336 #define G_CONG_THRESH3(x) (((x) >> S_CONG_THRESH3) & M_CONG_THRESH3)
21338 #define S_CONG_THRESH2 18
21339 #define M_CONG_THRESH2 0x7fU
21340 #define V_CONG_THRESH2(x) ((x) << S_CONG_THRESH2)
21341 #define G_CONG_THRESH2(x) (((x) >> S_CONG_THRESH2) & M_CONG_THRESH2)
21343 #define S_CONG_THRESH1 11
21344 #define M_CONG_THRESH1 0x7fU
21345 #define V_CONG_THRESH1(x) ((x) << S_CONG_THRESH1)
21346 #define G_CONG_THRESH1(x) (((x) >> S_CONG_THRESH1) & M_CONG_THRESH1)
21348 #define S_CONG_THRESH0 4
21349 #define M_CONG_THRESH0 0x7fU
21350 #define V_CONG_THRESH0(x) ((x) << S_CONG_THRESH0)
21351 #define G_CONG_THRESH0(x) (((x) >> S_CONG_THRESH0) & M_CONG_THRESH0)
21353 #define S_TX_USE_BUNDLE_LEN 3
21354 #define V_TX_USE_BUNDLE_LEN(x) ((x) << S_TX_USE_BUNDLE_LEN)
21355 #define F_TX_USE_BUNDLE_LEN V_TX_USE_BUNDLE_LEN(1U)
21357 #define S_STAT_CHANNEL 1
21358 #define M_STAT_CHANNEL 0x3U
21359 #define V_STAT_CHANNEL(x) ((x) << S_STAT_CHANNEL)
21360 #define G_STAT_CHANNEL(x) (((x) >> S_STAT_CHANNEL) & M_STAT_CHANNEL)
21362 #define A_PM_TX_STAT_CONFIG 0x8fe8
21363 #define A_PM_TX_STAT_COUNT 0x8fec
21364 #define A_PM_TX_STAT_LSB 0x8ff0
21365 #define A_PM_TX_DBG_CTRL 0x8ff0
21367 #define S_OSPIWRBUSY 21
21368 #define M_OSPIWRBUSY 0xfU
21369 #define V_OSPIWRBUSY(x) ((x) << S_OSPIWRBUSY)
21370 #define G_OSPIWRBUSY(x) (((x) >> S_OSPIWRBUSY) & M_OSPIWRBUSY)
21372 #define A_PM_TX_STAT_MSB 0x8ff4
21373 #define A_PM_TX_DBG_DATA 0x8ff4
21374 #define A_PM_TX_INT_ENABLE 0x8ff8
21376 #define S_PCMD_LEN_OVFL0 31
21377 #define V_PCMD_LEN_OVFL0(x) ((x) << S_PCMD_LEN_OVFL0)
21378 #define F_PCMD_LEN_OVFL0 V_PCMD_LEN_OVFL0(1U)
21380 #define S_PCMD_LEN_OVFL1 30
21381 #define V_PCMD_LEN_OVFL1(x) ((x) << S_PCMD_LEN_OVFL1)
21382 #define F_PCMD_LEN_OVFL1 V_PCMD_LEN_OVFL1(1U)
21384 #define S_PCMD_LEN_OVFL2 29
21385 #define V_PCMD_LEN_OVFL2(x) ((x) << S_PCMD_LEN_OVFL2)
21386 #define F_PCMD_LEN_OVFL2 V_PCMD_LEN_OVFL2(1U)
21388 #define S_ZERO_C_CMD_ERRO 28
21389 #define V_ZERO_C_CMD_ERRO(x) ((x) << S_ZERO_C_CMD_ERRO)
21390 #define F_ZERO_C_CMD_ERRO V_ZERO_C_CMD_ERRO(1U)
21392 #define S_ICSPI0_FIFO2X_RX_FRAMING_ERROR 27
21393 #define V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_FIFO2X_RX_FRAMING_ERROR)
21394 #define F_ICSPI0_FIFO2X_RX_FRAMING_ERROR V_ICSPI0_FIFO2X_RX_FRAMING_ERROR(1U)
21396 #define S_ICSPI1_FIFO2X_RX_FRAMING_ERROR 26
21397 #define V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_FIFO2X_RX_FRAMING_ERROR)
21398 #define F_ICSPI1_FIFO2X_RX_FRAMING_ERROR V_ICSPI1_FIFO2X_RX_FRAMING_ERROR(1U)
21400 #define S_ICSPI2_FIFO2X_RX_FRAMING_ERROR 25
21401 #define V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_FIFO2X_RX_FRAMING_ERROR)
21402 #define F_ICSPI2_FIFO2X_RX_FRAMING_ERROR V_ICSPI2_FIFO2X_RX_FRAMING_ERROR(1U)
21404 #define S_ICSPI3_FIFO2X_RX_FRAMING_ERROR 24
21405 #define V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_FIFO2X_RX_FRAMING_ERROR)
21406 #define F_ICSPI3_FIFO2X_RX_FRAMING_ERROR V_ICSPI3_FIFO2X_RX_FRAMING_ERROR(1U)
21408 #define S_ICSPI0_RX_FRAMING_ERROR 23
21409 #define V_ICSPI0_RX_FRAMING_ERROR(x) ((x) << S_ICSPI0_RX_FRAMING_ERROR)
21410 #define F_ICSPI0_RX_FRAMING_ERROR V_ICSPI0_RX_FRAMING_ERROR(1U)
21412 #define S_ICSPI1_RX_FRAMING_ERROR 22
21413 #define V_ICSPI1_RX_FRAMING_ERROR(x) ((x) << S_ICSPI1_RX_FRAMING_ERROR)
21414 #define F_ICSPI1_RX_FRAMING_ERROR V_ICSPI1_RX_FRAMING_ERROR(1U)
21416 #define S_ICSPI2_RX_FRAMING_ERROR 21
21417 #define V_ICSPI2_RX_FRAMING_ERROR(x) ((x) << S_ICSPI2_RX_FRAMING_ERROR)
21418 #define F_ICSPI2_RX_FRAMING_ERROR V_ICSPI2_RX_FRAMING_ERROR(1U)
21420 #define S_ICSPI3_RX_FRAMING_ERROR 20
21421 #define V_ICSPI3_RX_FRAMING_ERROR(x) ((x) << S_ICSPI3_RX_FRAMING_ERROR)
21422 #define F_ICSPI3_RX_FRAMING_ERROR V_ICSPI3_RX_FRAMING_ERROR(1U)
21424 #define S_ICSPI0_TX_FRAMING_ERROR 19
21425 #define V_ICSPI0_TX_FRAMING_ERROR(x) ((x) << S_ICSPI0_TX_FRAMING_ERROR)
21426 #define F_ICSPI0_TX_FRAMING_ERROR V_ICSPI0_TX_FRAMING_ERROR(1U)
21428 #define S_ICSPI1_TX_FRAMING_ERROR 18
21429 #define V_ICSPI1_TX_FRAMING_ERROR(x) ((x) << S_ICSPI1_TX_FRAMING_ERROR)
21430 #define F_ICSPI1_TX_FRAMING_ERROR V_ICSPI1_TX_FRAMING_ERROR(1U)
21432 #define S_ICSPI2_TX_FRAMING_ERROR 17
21433 #define V_ICSPI2_TX_FRAMING_ERROR(x) ((x) << S_ICSPI2_TX_FRAMING_ERROR)
21434 #define F_ICSPI2_TX_FRAMING_ERROR V_ICSPI2_TX_FRAMING_ERROR(1U)
21436 #define S_ICSPI3_TX_FRAMING_ERROR 16
21437 #define V_ICSPI3_TX_FRAMING_ERROR(x) ((x) << S_ICSPI3_TX_FRAMING_ERROR)
21438 #define F_ICSPI3_TX_FRAMING_ERROR V_ICSPI3_TX_FRAMING_ERROR(1U)
21440 #define S_OESPI0_RX_FRAMING_ERROR 15
21441 #define V_OESPI0_RX_FRAMING_ERROR(x) ((x) << S_OESPI0_RX_FRAMING_ERROR)
21442 #define F_OESPI0_RX_FRAMING_ERROR V_OESPI0_RX_FRAMING_ERROR(1U)
21444 #define S_OESPI1_RX_FRAMING_ERROR 14
21445 #define V_OESPI1_RX_FRAMING_ERROR(x) ((x) << S_OESPI1_RX_FRAMING_ERROR)
21446 #define F_OESPI1_RX_FRAMING_ERROR V_OESPI1_RX_FRAMING_ERROR(1U)
21448 #define S_OESPI2_RX_FRAMING_ERROR 13
21449 #define V_OESPI2_RX_FRAMING_ERROR(x) ((x) << S_OESPI2_RX_FRAMING_ERROR)
21450 #define F_OESPI2_RX_FRAMING_ERROR V_OESPI2_RX_FRAMING_ERROR(1U)
21452 #define S_OESPI3_RX_FRAMING_ERROR 12
21453 #define V_OESPI3_RX_FRAMING_ERROR(x) ((x) << S_OESPI3_RX_FRAMING_ERROR)
21454 #define F_OESPI3_RX_FRAMING_ERROR V_OESPI3_RX_FRAMING_ERROR(1U)
21456 #define S_OESPI0_TX_FRAMING_ERROR 11
21457 #define V_OESPI0_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_TX_FRAMING_ERROR)
21458 #define F_OESPI0_TX_FRAMING_ERROR V_OESPI0_TX_FRAMING_ERROR(1U)
21460 #define S_OESPI1_TX_FRAMING_ERROR 10
21461 #define V_OESPI1_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_TX_FRAMING_ERROR)
21462 #define F_OESPI1_TX_FRAMING_ERROR V_OESPI1_TX_FRAMING_ERROR(1U)
21464 #define S_OESPI2_TX_FRAMING_ERROR 9
21465 #define V_OESPI2_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_TX_FRAMING_ERROR)
21466 #define F_OESPI2_TX_FRAMING_ERROR V_OESPI2_TX_FRAMING_ERROR(1U)
21468 #define S_OESPI3_TX_FRAMING_ERROR 8
21469 #define V_OESPI3_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_TX_FRAMING_ERROR)
21470 #define F_OESPI3_TX_FRAMING_ERROR V_OESPI3_TX_FRAMING_ERROR(1U)
21472 #define S_OESPI0_OFIFO2X_TX_FRAMING_ERROR 7
21473 #define V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI0_OFIFO2X_TX_FRAMING_ERROR)
21474 #define F_OESPI0_OFIFO2X_TX_FRAMING_ERROR V_OESPI0_OFIFO2X_TX_FRAMING_ERROR(1U)
21476 #define S_OESPI1_OFIFO2X_TX_FRAMING_ERROR 6
21477 #define V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI1_OFIFO2X_TX_FRAMING_ERROR)
21478 #define F_OESPI1_OFIFO2X_TX_FRAMING_ERROR V_OESPI1_OFIFO2X_TX_FRAMING_ERROR(1U)
21480 #define S_OESPI2_OFIFO2X_TX_FRAMING_ERROR 5
21481 #define V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI2_OFIFO2X_TX_FRAMING_ERROR)
21482 #define F_OESPI2_OFIFO2X_TX_FRAMING_ERROR V_OESPI2_OFIFO2X_TX_FRAMING_ERROR(1U)
21484 #define S_OESPI3_OFIFO2X_TX_FRAMING_ERROR 4
21485 #define V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(x) ((x) << S_OESPI3_OFIFO2X_TX_FRAMING_ERROR)
21486 #define F_OESPI3_OFIFO2X_TX_FRAMING_ERROR V_OESPI3_OFIFO2X_TX_FRAMING_ERROR(1U)
21488 #define S_OESPI_PAR_ERROR 3
21489 #define V_OESPI_PAR_ERROR(x) ((x) << S_OESPI_PAR_ERROR)
21490 #define F_OESPI_PAR_ERROR V_OESPI_PAR_ERROR(1U)
21492 #define S_ICSPI_PAR_ERROR 1
21493 #define V_ICSPI_PAR_ERROR(x) ((x) << S_ICSPI_PAR_ERROR)
21494 #define F_ICSPI_PAR_ERROR V_ICSPI_PAR_ERROR(1U)
21496 #define S_C_PCMD_PAR_ERROR 0
21497 #define V_C_PCMD_PAR_ERROR(x) ((x) << S_C_PCMD_PAR_ERROR)
21498 #define F_C_PCMD_PAR_ERROR V_C_PCMD_PAR_ERROR(1U)
21500 #define A_PM_TX_INT_CAUSE 0x8ffc
21502 #define S_ZERO_C_CMD_ERROR 28
21503 #define V_ZERO_C_CMD_ERROR(x) ((x) << S_ZERO_C_CMD_ERROR)
21504 #define F_ZERO_C_CMD_ERROR V_ZERO_C_CMD_ERROR(1U)
21506 #define S_OSPI_OR_BUNDLE_LEN_PAR_ERR 3
21507 #define V_OSPI_OR_BUNDLE_LEN_PAR_ERR(x) ((x) << S_OSPI_OR_BUNDLE_LEN_PAR_ERR)
21508 #define F_OSPI_OR_BUNDLE_LEN_PAR_ERR V_OSPI_OR_BUNDLE_LEN_PAR_ERR(1U)
21510 #define A_PM_TX_ISPI_DBG_4B_DATA0 0x10000
21511 #define A_PM_TX_ISPI_DBG_4B_DATA1 0x10001
21512 #define A_PM_TX_ISPI_DBG_4B_DATA2 0x10002
21513 #define A_PM_TX_ISPI_DBG_4B_DATA3 0x10003
21514 #define A_PM_TX_ISPI_DBG_4B_DATA4 0x10004
21515 #define A_PM_TX_ISPI_DBG_4B_DATA5 0x10005
21516 #define A_PM_TX_ISPI_DBG_4B_DATA6 0x10006
21517 #define A_PM_TX_ISPI_DBG_4B_DATA7 0x10007
21518 #define A_PM_TX_ISPI_DBG_4B_DATA8 0x10008
21519 #define A_PM_TX_OSPI_DBG_4B_DATA0 0x10009
21520 #define A_PM_TX_OSPI_DBG_4B_DATA1 0x1000a
21521 #define A_PM_TX_OSPI_DBG_4B_DATA2 0x1000b
21522 #define A_PM_TX_OSPI_DBG_4B_DATA3 0x1000c
21523 #define A_PM_TX_OSPI_DBG_4B_DATA4 0x1000d
21524 #define A_PM_TX_OSPI_DBG_4B_DATA5 0x1000e
21525 #define A_PM_TX_OSPI_DBG_4B_DATA6 0x1000f
21526 #define A_PM_TX_OSPI_DBG_4B_DATA7 0x10010
21527 #define A_PM_TX_OSPI_DBG_4B_DATA8 0x10011
21528 #define A_PM_TX_OSPI_DBG_4B_DATA9 0x10012
21529 #define A_PM_TX_OSPI_DBG_4B_DATA10 0x10013
21530 #define A_PM_TX_OSPI_DBG_4B_DATA11 0x10014
21531 #define A_PM_TX_OSPI_DBG_4B_DATA12 0x10015
21532 #define A_PM_TX_OSPI_DBG_4B_DATA13 0x10016
21533 #define A_PM_TX_OSPI_DBG_4B_DATA14 0x10017
21534 #define A_PM_TX_OSPI_DBG_4B_DATA15 0x10018
21535 #define A_PM_TX_OSPI_DBG_4B_DATA16 0x10019
21536 #define A_PM_TX_DBG_STAT_MSB 0x1001a
21537 #define A_PM_TX_DBG_STAT_LSB 0x1001b
21538 #define A_PM_TX_DBG_RSVD_FLIT_CNT 0x1001c
21539 #define A_PM_TX_SDC_EN 0x1001d
21540 #define A_PM_TX_INOUT_FIFO_DBG_CHNL_SEL 0x1001e
21541 #define A_PM_TX_INOUT_FIFO_DBG_WR 0x1001f
21542 #define A_PM_TX_INPUT_FIFO_STR_FWD_EN 0x10020
21543 #define A_PM_TX_FEATURE_EN 0x10021
21545 #define S_PIO_CH_DEFICIT_CTL_EN 2
21546 #define V_PIO_CH_DEFICIT_CTL_EN(x) ((x) << S_PIO_CH_DEFICIT_CTL_EN)
21547 #define F_PIO_CH_DEFICIT_CTL_EN V_PIO_CH_DEFICIT_CTL_EN(1U)
21549 #define S_PIO_WRR_BASED_PRFTCH_EN 1
21550 #define V_PIO_WRR_BASED_PRFTCH_EN(x) ((x) << S_PIO_WRR_BASED_PRFTCH_EN)
21551 #define F_PIO_WRR_BASED_PRFTCH_EN V_PIO_WRR_BASED_PRFTCH_EN(1U)
21553 #define A_PM_TX_T5_PM_TX_INT_ENABLE 0x10022
21555 #define S_OSPI_OVERFLOW3 7
21556 #define V_OSPI_OVERFLOW3(x) ((x) << S_OSPI_OVERFLOW3)
21557 #define F_OSPI_OVERFLOW3 V_OSPI_OVERFLOW3(1U)
21559 #define S_OSPI_OVERFLOW2 6
21560 #define V_OSPI_OVERFLOW2(x) ((x) << S_OSPI_OVERFLOW2)
21561 #define F_OSPI_OVERFLOW2 V_OSPI_OVERFLOW2(1U)
21563 #define S_M_INTFPERREN 3
21564 #define V_M_INTFPERREN(x) ((x) << S_M_INTFPERREN)
21565 #define F_M_INTFPERREN V_M_INTFPERREN(1U)
21567 #define S_BUNDLE_LEN_PARERR_EN 2
21568 #define V_BUNDLE_LEN_PARERR_EN(x) ((x) << S_BUNDLE_LEN_PARERR_EN)
21569 #define F_BUNDLE_LEN_PARERR_EN V_BUNDLE_LEN_PARERR_EN(1U)
21571 #define S_BUNDLE_LEN_OVFL_EN 1
21572 #define V_BUNDLE_LEN_OVFL_EN(x) ((x) << S_BUNDLE_LEN_OVFL_EN)
21573 #define F_BUNDLE_LEN_OVFL_EN V_BUNDLE_LEN_OVFL_EN(1U)
21575 #define S_SDC_ERR_EN 0
21576 #define V_SDC_ERR_EN(x) ((x) << S_SDC_ERR_EN)
21577 #define F_SDC_ERR_EN V_SDC_ERR_EN(1U)
21579 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD0 0x10023
21580 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD1 0x10024
21581 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD2 0x10025
21582 #define A_PM_TX_PRFTCH_WRR_WAIT_CNT_THRSHLD3 0x10026
21583 #define A_PM_TX_CH0_OSPI_DEFICIT_THRSHLD 0x10027
21584 #define A_PM_TX_CH1_OSPI_DEFICIT_THRSHLD 0x10028
21585 #define A_PM_TX_CH2_OSPI_DEFICIT_THRSHLD 0x10029
21587 #define S_CH2_OSPI_DEFICIT_THRSHLD 0
21588 #define M_CH2_OSPI_DEFICIT_THRSHLD 0xfffU
21589 #define V_CH2_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH2_OSPI_DEFICIT_THRSHLD)
21590 #define G_CH2_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH2_OSPI_DEFICIT_THRSHLD) & M_CH2_OSPI_DEFICIT_THRSHLD)
21592 #define A_PM_TX_CH3_OSPI_DEFICIT_THRSHLD 0x1002a
21594 #define S_CH3_OSPI_DEFICIT_THRSHLD 0
21595 #define M_CH3_OSPI_DEFICIT_THRSHLD 0xfffU
21596 #define V_CH3_OSPI_DEFICIT_THRSHLD(x) ((x) << S_CH3_OSPI_DEFICIT_THRSHLD)
21597 #define G_CH3_OSPI_DEFICIT_THRSHLD(x) (((x) >> S_CH3_OSPI_DEFICIT_THRSHLD) & M_CH3_OSPI_DEFICIT_THRSHLD)
21599 #define A_PM_TX_INT_CAUSE_MASK_HALT 0x1002b
21600 #define A_PM_TX_DBG_STAT0 0x1002c
21602 #define S_RD_I_BUSY 28
21603 #define V_RD_I_BUSY(x) ((x) << S_RD_I_BUSY)
21604 #define F_RD_I_BUSY V_RD_I_BUSY(1U)
21606 #define S_WR_O_ONLY 27
21607 #define V_WR_O_ONLY(x) ((x) << S_WR_O_ONLY)
21608 #define F_WR_O_ONLY V_WR_O_ONLY(1U)
21610 #define S_M_TO_BUSY 26
21611 #define V_M_TO_BUSY(x) ((x) << S_M_TO_BUSY)
21612 #define F_M_TO_BUSY V_M_TO_BUSY(1U)
21614 #define S_I_TO_M_BUSY 25
21615 #define V_I_TO_M_BUSY(x) ((x) << S_I_TO_M_BUSY)
21616 #define F_I_TO_M_BUSY V_I_TO_M_BUSY(1U)
21618 #define S_PCMD_FB_ONLY 24
21619 #define V_PCMD_FB_ONLY(x) ((x) << S_PCMD_FB_ONLY)
21620 #define F_PCMD_FB_ONLY V_PCMD_FB_ONLY(1U)
21622 #define S_PCMD_MEM 23
21623 #define V_PCMD_MEM(x) ((x) << S_PCMD_MEM)
21624 #define F_PCMD_MEM V_PCMD_MEM(1U)
21626 #define S_PCMD_BYPASS 22
21627 #define V_PCMD_BYPASS(x) ((x) << S_PCMD_BYPASS)
21628 #define F_PCMD_BYPASS V_PCMD_BYPASS(1U)
21630 #define S_PCMD_EOP 21
21631 #define V_PCMD_EOP(x) ((x) << S_PCMD_EOP)
21632 #define F_PCMD_EOP V_PCMD_EOP(1U)
21634 #define S_PCMD_END_BUNDLE 20
21635 #define V_PCMD_END_BUNDLE(x) ((x) << S_PCMD_END_BUNDLE)
21636 #define F_PCMD_END_BUNDLE V_PCMD_END_BUNDLE(1U)
21638 #define S_PCMD_FB_CMD 16
21639 #define M_PCMD_FB_CMD 0xfU
21640 #define V_PCMD_FB_CMD(x) ((x) << S_PCMD_FB_CMD)
21641 #define G_PCMD_FB_CMD(x) (((x) >> S_PCMD_FB_CMD) & M_PCMD_FB_CMD)
21643 #define S_CUR_PCMD_LEN 0
21644 #define M_CUR_PCMD_LEN 0xffffU
21645 #define V_CUR_PCMD_LEN(x) ((x) << S_CUR_PCMD_LEN)
21646 #define G_CUR_PCMD_LEN(x) (((x) >> S_CUR_PCMD_LEN) & M_CUR_PCMD_LEN)
21648 #define A_PM_TX_DBG_STAT1 0x1002d
21650 #define S_PCMD_MEM0 31
21651 #define V_PCMD_MEM0(x) ((x) << S_PCMD_MEM0)
21652 #define F_PCMD_MEM0 V_PCMD_MEM0(1U)
21654 #define S_FREE_OESPI_CNT0 19
21655 #define M_FREE_OESPI_CNT0 0xfffU
21656 #define V_FREE_OESPI_CNT0(x) ((x) << S_FREE_OESPI_CNT0)
21657 #define G_FREE_OESPI_CNT0(x) (((x) >> S_FREE_OESPI_CNT0) & M_FREE_OESPI_CNT0)
21659 #define S_PCMD_FLIT_LEN0 7
21660 #define M_PCMD_FLIT_LEN0 0xfffU
21661 #define V_PCMD_FLIT_LEN0(x) ((x) << S_PCMD_FLIT_LEN0)
21662 #define G_PCMD_FLIT_LEN0(x) (((x) >> S_PCMD_FLIT_LEN0) & M_PCMD_FLIT_LEN0)
21664 #define S_PCMD_CMD0 3
21665 #define M_PCMD_CMD0 0xfU
21666 #define V_PCMD_CMD0(x) ((x) << S_PCMD_CMD0)
21667 #define G_PCMD_CMD0(x) (((x) >> S_PCMD_CMD0) & M_PCMD_CMD0)
21669 #define S_OFIFO_FULL0 2
21670 #define V_OFIFO_FULL0(x) ((x) << S_OFIFO_FULL0)
21671 #define F_OFIFO_FULL0 V_OFIFO_FULL0(1U)
21673 #define S_GCSUM_DRDY0 1
21674 #define V_GCSUM_DRDY0(x) ((x) << S_GCSUM_DRDY0)
21675 #define F_GCSUM_DRDY0 V_GCSUM_DRDY0(1U)
21677 #define S_BYPASS0 0
21678 #define V_BYPASS0(x) ((x) << S_BYPASS0)
21679 #define F_BYPASS0 V_BYPASS0(1U)
21681 #define A_PM_TX_DBG_STAT2 0x1002e
21683 #define S_PCMD_MEM1 31
21684 #define V_PCMD_MEM1(x) ((x) << S_PCMD_MEM1)
21685 #define F_PCMD_MEM1 V_PCMD_MEM1(1U)
21687 #define S_FREE_OESPI_CNT1 19
21688 #define M_FREE_OESPI_CNT1 0xfffU
21689 #define V_FREE_OESPI_CNT1(x) ((x) << S_FREE_OESPI_CNT1)
21690 #define G_FREE_OESPI_CNT1(x) (((x) >> S_FREE_OESPI_CNT1) & M_FREE_OESPI_CNT1)
21692 #define S_PCMD_FLIT_LEN1 7
21693 #define M_PCMD_FLIT_LEN1 0xfffU
21694 #define V_PCMD_FLIT_LEN1(x) ((x) << S_PCMD_FLIT_LEN1)
21695 #define G_PCMD_FLIT_LEN1(x) (((x) >> S_PCMD_FLIT_LEN1) & M_PCMD_FLIT_LEN1)
21697 #define S_PCMD_CMD1 3
21698 #define M_PCMD_CMD1 0xfU
21699 #define V_PCMD_CMD1(x) ((x) << S_PCMD_CMD1)
21700 #define G_PCMD_CMD1(x) (((x) >> S_PCMD_CMD1) & M_PCMD_CMD1)
21702 #define S_OFIFO_FULL1 2
21703 #define V_OFIFO_FULL1(x) ((x) << S_OFIFO_FULL1)
21704 #define F_OFIFO_FULL1 V_OFIFO_FULL1(1U)
21706 #define S_GCSUM_DRDY1 1
21707 #define V_GCSUM_DRDY1(x) ((x) << S_GCSUM_DRDY1)
21708 #define F_GCSUM_DRDY1 V_GCSUM_DRDY1(1U)
21710 #define S_BYPASS1 0
21711 #define V_BYPASS1(x) ((x) << S_BYPASS1)
21712 #define F_BYPASS1 V_BYPASS1(1U)
21714 #define A_PM_TX_DBG_STAT3 0x1002f
21716 #define S_PCMD_MEM2 31
21717 #define V_PCMD_MEM2(x) ((x) << S_PCMD_MEM2)
21718 #define F_PCMD_MEM2 V_PCMD_MEM2(1U)
21720 #define S_FREE_OESPI_CNT2 19
21721 #define M_FREE_OESPI_CNT2 0xfffU
21722 #define V_FREE_OESPI_CNT2(x) ((x) << S_FREE_OESPI_CNT2)
21723 #define G_FREE_OESPI_CNT2(x) (((x) >> S_FREE_OESPI_CNT2) & M_FREE_OESPI_CNT2)
21725 #define S_PCMD_FLIT_LEN2 7
21726 #define M_PCMD_FLIT_LEN2 0xfffU
21727 #define V_PCMD_FLIT_LEN2(x) ((x) << S_PCMD_FLIT_LEN2)
21728 #define G_PCMD_FLIT_LEN2(x) (((x) >> S_PCMD_FLIT_LEN2) & M_PCMD_FLIT_LEN2)
21730 #define S_PCMD_CMD2 3
21731 #define M_PCMD_CMD2 0xfU
21732 #define V_PCMD_CMD2(x) ((x) << S_PCMD_CMD2)
21733 #define G_PCMD_CMD2(x) (((x) >> S_PCMD_CMD2) & M_PCMD_CMD2)
21735 #define S_OFIFO_FULL2 2
21736 #define V_OFIFO_FULL2(x) ((x) << S_OFIFO_FULL2)
21737 #define F_OFIFO_FULL2 V_OFIFO_FULL2(1U)
21739 #define S_GCSUM_DRDY2 1
21740 #define V_GCSUM_DRDY2(x) ((x) << S_GCSUM_DRDY2)
21741 #define F_GCSUM_DRDY2 V_GCSUM_DRDY2(1U)
21743 #define S_BYPASS2 0
21744 #define V_BYPASS2(x) ((x) << S_BYPASS2)
21745 #define F_BYPASS2 V_BYPASS2(1U)
21747 #define A_PM_TX_DBG_STAT4 0x10030
21749 #define S_PCMD_MEM3 31
21750 #define V_PCMD_MEM3(x) ((x) << S_PCMD_MEM3)
21751 #define F_PCMD_MEM3 V_PCMD_MEM3(1U)
21753 #define S_FREE_OESPI_CNT3 19
21754 #define M_FREE_OESPI_CNT3 0xfffU
21755 #define V_FREE_OESPI_CNT3(x) ((x) << S_FREE_OESPI_CNT3)
21756 #define G_FREE_OESPI_CNT3(x) (((x) >> S_FREE_OESPI_CNT3) & M_FREE_OESPI_CNT3)
21758 #define S_PCMD_FLIT_LEN3 7
21759 #define M_PCMD_FLIT_LEN3 0xfffU
21760 #define V_PCMD_FLIT_LEN3(x) ((x) << S_PCMD_FLIT_LEN3)
21761 #define G_PCMD_FLIT_LEN3(x) (((x) >> S_PCMD_FLIT_LEN3) & M_PCMD_FLIT_LEN3)
21763 #define S_PCMD_CMD3 3
21764 #define M_PCMD_CMD3 0xfU
21765 #define V_PCMD_CMD3(x) ((x) << S_PCMD_CMD3)
21766 #define G_PCMD_CMD3(x) (((x) >> S_PCMD_CMD3) & M_PCMD_CMD3)
21768 #define S_OFIFO_FULL3 2
21769 #define V_OFIFO_FULL3(x) ((x) << S_OFIFO_FULL3)
21770 #define F_OFIFO_FULL3 V_OFIFO_FULL3(1U)
21772 #define S_GCSUM_DRDY3 1
21773 #define V_GCSUM_DRDY3(x) ((x) << S_GCSUM_DRDY3)
21774 #define F_GCSUM_DRDY3 V_GCSUM_DRDY3(1U)
21776 #define S_BYPASS3 0
21777 #define V_BYPASS3(x) ((x) << S_BYPASS3)
21778 #define F_BYPASS3 V_BYPASS3(1U)
21780 #define A_PM_TX_DBG_STAT5 0x10031
21782 #define S_SET_PCMD_RES_RDY_RD 24
21783 #define M_SET_PCMD_RES_RDY_RD 0xfU
21784 #define V_SET_PCMD_RES_RDY_RD(x) ((x) << S_SET_PCMD_RES_RDY_RD)
21785 #define G_SET_PCMD_RES_RDY_RD(x) (((x) >> S_SET_PCMD_RES_RDY_RD) & M_SET_PCMD_RES_RDY_RD)
21787 #define S_ISSUED_PREF_RD_ER_CLR 20
21788 #define M_ISSUED_PREF_RD_ER_CLR 0xfU
21789 #define V_ISSUED_PREF_RD_ER_CLR(x) ((x) << S_ISSUED_PREF_RD_ER_CLR)
21790 #define G_ISSUED_PREF_RD_ER_CLR(x) (((x) >> S_ISSUED_PREF_RD_ER_CLR) & M_ISSUED_PREF_RD_ER_CLR)
21792 #define S_ISSUED_PREF_RD 16
21793 #define M_ISSUED_PREF_RD 0xfU
21794 #define V_ISSUED_PREF_RD(x) ((x) << S_ISSUED_PREF_RD)
21795 #define G_ISSUED_PREF_RD(x) (((x) >> S_ISSUED_PREF_RD) & M_ISSUED_PREF_RD)
21797 #define S_PCMD_RES_RDY 12
21798 #define M_PCMD_RES_RDY 0xfU
21799 #define V_PCMD_RES_RDY(x) ((x) << S_PCMD_RES_RDY)
21800 #define G_PCMD_RES_RDY(x) (((x) >> S_PCMD_RES_RDY) & M_PCMD_RES_RDY)
21802 #define S_DB_VLD 11
21803 #define V_DB_VLD(x) ((x) << S_DB_VLD)
21804 #define F_DB_VLD V_DB_VLD(1U)
21806 #define S_INJECT0_DRDY 10
21807 #define V_INJECT0_DRDY(x) ((x) << S_INJECT0_DRDY)
21808 #define F_INJECT0_DRDY V_INJECT0_DRDY(1U)
21810 #define S_INJECT1_DRDY 9
21811 #define V_INJECT1_DRDY(x) ((x) << S_INJECT1_DRDY)
21812 #define F_INJECT1_DRDY V_INJECT1_DRDY(1U)
21814 #define S_FIRST_BUNDLE 5
21815 #define M_FIRST_BUNDLE 0xfU
21816 #define V_FIRST_BUNDLE(x) ((x) << S_FIRST_BUNDLE)
21817 #define G_FIRST_BUNDLE(x) (((x) >> S_FIRST_BUNDLE) & M_FIRST_BUNDLE)
21819 #define S_GCSUM_MORE_THAN_2_LEFT 1
21820 #define M_GCSUM_MORE_THAN_2_LEFT 0xfU
21821 #define V_GCSUM_MORE_THAN_2_LEFT(x) ((x) << S_GCSUM_MORE_THAN_2_LEFT)
21822 #define G_GCSUM_MORE_THAN_2_LEFT(x) (((x) >> S_GCSUM_MORE_THAN_2_LEFT) & M_GCSUM_MORE_THAN_2_LEFT)
21824 #define S_SDC_DRDY 0
21825 #define V_SDC_DRDY(x) ((x) << S_SDC_DRDY)
21826 #define F_SDC_DRDY V_SDC_DRDY(1U)
21828 #define A_PM_TX_DBG_STAT6 0x10032
21830 #define S_PCMD_VLD 31
21831 #define V_PCMD_VLD(x) ((x) << S_PCMD_VLD)
21832 #define F_PCMD_VLD V_PCMD_VLD(1U)
21834 #define S_PCMD_CH 29
21835 #define M_PCMD_CH 0x3U
21836 #define V_PCMD_CH(x) ((x) << S_PCMD_CH)
21837 #define G_PCMD_CH(x) (((x) >> S_PCMD_CH) & M_PCMD_CH)
21839 #define S_STATE_MACHINE_LOC 24
21840 #define M_STATE_MACHINE_LOC 0x1fU
21841 #define V_STATE_MACHINE_LOC(x) ((x) << S_STATE_MACHINE_LOC)
21842 #define G_STATE_MACHINE_LOC(x) (((x) >> S_STATE_MACHINE_LOC) & M_STATE_MACHINE_LOC)
21844 #define S_ICSPI_TXVALID 20
21845 #define M_ICSPI_TXVALID 0xfU
21846 #define V_ICSPI_TXVALID(x) ((x) << S_ICSPI_TXVALID)
21847 #define G_ICSPI_TXVALID(x) (((x) >> S_ICSPI_TXVALID) & M_ICSPI_TXVALID)
21849 #define S_ICSPI_TXFULL 16
21850 #define M_ICSPI_TXFULL 0xfU
21851 #define V_ICSPI_TXFULL(x) ((x) << S_ICSPI_TXFULL)
21852 #define G_ICSPI_TXFULL(x) (((x) >> S_ICSPI_TXFULL) & M_ICSPI_TXFULL)
21854 #define S_PCMD_SRDY 12
21855 #define M_PCMD_SRDY 0xfU
21856 #define V_PCMD_SRDY(x) ((x) << S_PCMD_SRDY)
21857 #define G_PCMD_SRDY(x) (((x) >> S_PCMD_SRDY) & M_PCMD_SRDY)
21859 #define S_PCMD_DRDY 8
21860 #define M_PCMD_DRDY 0xfU
21861 #define V_PCMD_DRDY(x) ((x) << S_PCMD_DRDY)
21862 #define G_PCMD_DRDY(x) (((x) >> S_PCMD_DRDY) & M_PCMD_DRDY)
21864 #define S_PCMD_CMD 4
21865 #define M_PCMD_CMD 0xfU
21866 #define V_PCMD_CMD(x) ((x) << S_PCMD_CMD)
21867 #define G_PCMD_CMD(x) (((x) >> S_PCMD_CMD) & M_PCMD_CMD)
21869 #define S_OEFIFO_FULL3 3
21870 #define V_OEFIFO_FULL3(x) ((x) << S_OEFIFO_FULL3)
21871 #define F_OEFIFO_FULL3 V_OEFIFO_FULL3(1U)
21873 #define S_OEFIFO_FULL2 2
21874 #define V_OEFIFO_FULL2(x) ((x) << S_OEFIFO_FULL2)
21875 #define F_OEFIFO_FULL2 V_OEFIFO_FULL2(1U)
21877 #define S_OEFIFO_FULL1 1
21878 #define V_OEFIFO_FULL1(x) ((x) << S_OEFIFO_FULL1)
21879 #define F_OEFIFO_FULL1 V_OEFIFO_FULL1(1U)
21881 #define S_OEFIFO_FULL0 0
21882 #define V_OEFIFO_FULL0(x) ((x) << S_OEFIFO_FULL0)
21883 #define F_OEFIFO_FULL0 V_OEFIFO_FULL0(1U)
21885 #define A_PM_TX_DBG_STAT7 0x10033
21887 #define S_ICSPI_RXVALID 28
21888 #define M_ICSPI_RXVALID 0xfU
21889 #define V_ICSPI_RXVALID(x) ((x) << S_ICSPI_RXVALID)
21890 #define G_ICSPI_RXVALID(x) (((x) >> S_ICSPI_RXVALID) & M_ICSPI_RXVALID)
21892 #define S_ICSPI_RXFULL 24
21893 #define M_ICSPI_RXFULL 0xfU
21894 #define V_ICSPI_RXFULL(x) ((x) << S_ICSPI_RXFULL)
21895 #define G_ICSPI_RXFULL(x) (((x) >> S_ICSPI_RXFULL) & M_ICSPI_RXFULL)
21897 #define S_OESPI_VALID 20
21898 #define M_OESPI_VALID 0xfU
21899 #define V_OESPI_VALID(x) ((x) << S_OESPI_VALID)
21900 #define G_OESPI_VALID(x) (((x) >> S_OESPI_VALID) & M_OESPI_VALID)
21902 #define S_OESPI_FULL 16
21903 #define M_OESPI_FULL 0xfU
21904 #define V_OESPI_FULL(x) ((x) << S_OESPI_FULL)
21905 #define G_OESPI_FULL(x) (((x) >> S_OESPI_FULL) & M_OESPI_FULL)
21907 #define S_C_RXVALID 12
21908 #define M_C_RXVALID 0xfU
21909 #define V_C_RXVALID(x) ((x) << S_C_RXVALID)
21910 #define G_C_RXVALID(x) (((x) >> S_C_RXVALID) & M_C_RXVALID)
21912 #define S_C_RXAFULL 8
21913 #define M_C_RXAFULL 0xfU
21914 #define V_C_RXAFULL(x) ((x) << S_C_RXAFULL)
21915 #define G_C_RXAFULL(x) (((x) >> S_C_RXAFULL) & M_C_RXAFULL)
21917 #define S_E_TXVALID3 7
21918 #define V_E_TXVALID3(x) ((x) << S_E_TXVALID3)
21919 #define F_E_TXVALID3 V_E_TXVALID3(1U)
21921 #define S_E_TXVALID2 6
21922 #define V_E_TXVALID2(x) ((x) << S_E_TXVALID2)
21923 #define F_E_TXVALID2 V_E_TXVALID2(1U)
21925 #define S_E_TXVALID1 5
21926 #define V_E_TXVALID1(x) ((x) << S_E_TXVALID1)
21927 #define F_E_TXVALID1 V_E_TXVALID1(1U)
21929 #define S_E_TXVALID0 4
21930 #define V_E_TXVALID0(x) ((x) << S_E_TXVALID0)
21931 #define F_E_TXVALID0 V_E_TXVALID0(1U)
21933 #define S_E_TXFULL3 3
21934 #define V_E_TXFULL3(x) ((x) << S_E_TXFULL3)
21935 #define F_E_TXFULL3 V_E_TXFULL3(1U)
21937 #define S_E_TXFULL2 2
21938 #define V_E_TXFULL2(x) ((x) << S_E_TXFULL2)
21939 #define F_E_TXFULL2 V_E_TXFULL2(1U)
21941 #define S_E_TXFULL1 1
21942 #define V_E_TXFULL1(x) ((x) << S_E_TXFULL1)
21943 #define F_E_TXFULL1 V_E_TXFULL1(1U)
21945 #define S_E_TXFULL0 0
21946 #define V_E_TXFULL0(x) ((x) << S_E_TXFULL0)
21947 #define F_E_TXFULL0 V_E_TXFULL0(1U)
21949 #define A_PM_TX_DBG_STAT8 0x10034
21951 #define S_MC_RSP_FIFO_CNT 24
21952 #define M_MC_RSP_FIFO_CNT 0x3U
21953 #define V_MC_RSP_FIFO_CNT(x) ((x) << S_MC_RSP_FIFO_CNT)
21954 #define G_MC_RSP_FIFO_CNT(x) (((x) >> S_MC_RSP_FIFO_CNT) & M_MC_RSP_FIFO_CNT)
21956 #define S_PCMD_FREE_CNT0 14
21957 #define M_PCMD_FREE_CNT0 0x3ffU
21958 #define V_PCMD_FREE_CNT0(x) ((x) << S_PCMD_FREE_CNT0)
21959 #define G_PCMD_FREE_CNT0(x) (((x) >> S_PCMD_FREE_CNT0) & M_PCMD_FREE_CNT0)
21961 #define S_PCMD_FREE_CNT1 4
21962 #define M_PCMD_FREE_CNT1 0x3ffU
21963 #define V_PCMD_FREE_CNT1(x) ((x) << S_PCMD_FREE_CNT1)
21964 #define G_PCMD_FREE_CNT1(x) (((x) >> S_PCMD_FREE_CNT1) & M_PCMD_FREE_CNT1)
21966 #define S_M_REQADDRRDY 3
21967 #define V_M_REQADDRRDY(x) ((x) << S_M_REQADDRRDY)
21968 #define F_M_REQADDRRDY V_M_REQADDRRDY(1U)
21970 #define S_M_REQWRITE 2
21971 #define V_M_REQWRITE(x) ((x) << S_M_REQWRITE)
21972 #define F_M_REQWRITE V_M_REQWRITE(1U)
21974 #define S_M_REQDATAVLD 1
21975 #define V_M_REQDATAVLD(x) ((x) << S_M_REQDATAVLD)
21976 #define F_M_REQDATAVLD V_M_REQDATAVLD(1U)
21978 #define S_M_REQDATARDY 0
21979 #define V_M_REQDATARDY(x) ((x) << S_M_REQDATARDY)
21980 #define F_M_REQDATARDY V_M_REQDATARDY(1U)
21982 #define A_PM_TX_DBG_STAT9 0x10035
21984 #define S_PCMD_FREE_CNT2 10
21985 #define M_PCMD_FREE_CNT2 0x3ffU
21986 #define V_PCMD_FREE_CNT2(x) ((x) << S_PCMD_FREE_CNT2)
21987 #define G_PCMD_FREE_CNT2(x) (((x) >> S_PCMD_FREE_CNT2) & M_PCMD_FREE_CNT2)
21989 #define S_PCMD_FREE_CNT3 0
21990 #define M_PCMD_FREE_CNT3 0x3ffU
21991 #define V_PCMD_FREE_CNT3(x) ((x) << S_PCMD_FREE_CNT3)
21992 #define G_PCMD_FREE_CNT3(x) (((x) >> S_PCMD_FREE_CNT3) & M_PCMD_FREE_CNT3)
21994 #define A_PM_TX_DBG_STAT10 0x10036
21996 #define S_IN_EOP_CNT3 28
21997 #define M_IN_EOP_CNT3 0xfU
21998 #define V_IN_EOP_CNT3(x) ((x) << S_IN_EOP_CNT3)
21999 #define G_IN_EOP_CNT3(x) (((x) >> S_IN_EOP_CNT3) & M_IN_EOP_CNT3)
22001 #define S_IN_EOP_CNT2 24
22002 #define M_IN_EOP_CNT2 0xfU
22003 #define V_IN_EOP_CNT2(x) ((x) << S_IN_EOP_CNT2)
22004 #define G_IN_EOP_CNT2(x) (((x) >> S_IN_EOP_CNT2) & M_IN_EOP_CNT2)
22006 #define S_IN_EOP_CNT1 20
22007 #define M_IN_EOP_CNT1 0xfU
22008 #define V_IN_EOP_CNT1(x) ((x) << S_IN_EOP_CNT1)
22009 #define G_IN_EOP_CNT1(x) (((x) >> S_IN_EOP_CNT1) & M_IN_EOP_CNT1)
22011 #define S_IN_EOP_CNT0 16
22012 #define M_IN_EOP_CNT0 0xfU
22013 #define V_IN_EOP_CNT0(x) ((x) << S_IN_EOP_CNT0)
22014 #define G_IN_EOP_CNT0(x) (((x) >> S_IN_EOP_CNT0) & M_IN_EOP_CNT0)
22016 #define S_IN_SOP_CNT3 12
22017 #define M_IN_SOP_CNT3 0xfU
22018 #define V_IN_SOP_CNT3(x) ((x) << S_IN_SOP_CNT3)
22019 #define G_IN_SOP_CNT3(x) (((x) >> S_IN_SOP_CNT3) & M_IN_SOP_CNT3)
22021 #define S_IN_SOP_CNT2 8
22022 #define M_IN_SOP_CNT2 0xfU
22023 #define V_IN_SOP_CNT2(x) ((x) << S_IN_SOP_CNT2)
22024 #define G_IN_SOP_CNT2(x) (((x) >> S_IN_SOP_CNT2) & M_IN_SOP_CNT2)
22026 #define S_IN_SOP_CNT1 4
22027 #define M_IN_SOP_CNT1 0xfU
22028 #define V_IN_SOP_CNT1(x) ((x) << S_IN_SOP_CNT1)
22029 #define G_IN_SOP_CNT1(x) (((x) >> S_IN_SOP_CNT1) & M_IN_SOP_CNT1)
22031 #define S_IN_SOP_CNT0 0
22032 #define M_IN_SOP_CNT0 0xfU
22033 #define V_IN_SOP_CNT0(x) ((x) << S_IN_SOP_CNT0)
22034 #define G_IN_SOP_CNT0(x) (((x) >> S_IN_SOP_CNT0) & M_IN_SOP_CNT0)
22036 #define A_PM_TX_DBG_STAT11 0x10037
22038 #define S_OUT_EOP_CNT3 28
22039 #define M_OUT_EOP_CNT3 0xfU
22040 #define V_OUT_EOP_CNT3(x) ((x) << S_OUT_EOP_CNT3)
22041 #define G_OUT_EOP_CNT3(x) (((x) >> S_OUT_EOP_CNT3) & M_OUT_EOP_CNT3)
22043 #define S_OUT_EOP_CNT2 24
22044 #define M_OUT_EOP_CNT2 0xfU
22045 #define V_OUT_EOP_CNT2(x) ((x) << S_OUT_EOP_CNT2)
22046 #define G_OUT_EOP_CNT2(x) (((x) >> S_OUT_EOP_CNT2) & M_OUT_EOP_CNT2)
22048 #define S_OUT_EOP_CNT1 20
22049 #define M_OUT_EOP_CNT1 0xfU
22050 #define V_OUT_EOP_CNT1(x) ((x) << S_OUT_EOP_CNT1)
22051 #define G_OUT_EOP_CNT1(x) (((x) >> S_OUT_EOP_CNT1) & M_OUT_EOP_CNT1)
22053 #define S_OUT_EOP_CNT0 16
22054 #define M_OUT_EOP_CNT0 0xfU
22055 #define V_OUT_EOP_CNT0(x) ((x) << S_OUT_EOP_CNT0)
22056 #define G_OUT_EOP_CNT0(x) (((x) >> S_OUT_EOP_CNT0) & M_OUT_EOP_CNT0)
22058 #define S_OUT_SOP_CNT3 12
22059 #define M_OUT_SOP_CNT3 0xfU
22060 #define V_OUT_SOP_CNT3(x) ((x) << S_OUT_SOP_CNT3)
22061 #define G_OUT_SOP_CNT3(x) (((x) >> S_OUT_SOP_CNT3) & M_OUT_SOP_CNT3)
22063 #define S_OUT_SOP_CNT2 8
22064 #define M_OUT_SOP_CNT2 0xfU
22065 #define V_OUT_SOP_CNT2(x) ((x) << S_OUT_SOP_CNT2)
22066 #define G_OUT_SOP_CNT2(x) (((x) >> S_OUT_SOP_CNT2) & M_OUT_SOP_CNT2)
22068 #define S_OUT_SOP_CNT1 4
22069 #define M_OUT_SOP_CNT1 0xfU
22070 #define V_OUT_SOP_CNT1(x) ((x) << S_OUT_SOP_CNT1)
22071 #define G_OUT_SOP_CNT1(x) (((x) >> S_OUT_SOP_CNT1) & M_OUT_SOP_CNT1)
22073 #define S_OUT_SOP_CNT0 0
22074 #define M_OUT_SOP_CNT0 0xfU
22075 #define V_OUT_SOP_CNT0(x) ((x) << S_OUT_SOP_CNT0)
22076 #define G_OUT_SOP_CNT0(x) (((x) >> S_OUT_SOP_CNT0) & M_OUT_SOP_CNT0)
22078 #define A_PM_TX_DBG_STAT12 0x10038
22079 #define A_PM_TX_DBG_STAT13 0x10039
22081 #define S_CH_DEFICIT_BLOWED 31
22082 #define V_CH_DEFICIT_BLOWED(x) ((x) << S_CH_DEFICIT_BLOWED)
22083 #define F_CH_DEFICIT_BLOWED V_CH_DEFICIT_BLOWED(1U)
22085 #define S_CH1_DEFICIT 16
22086 #define M_CH1_DEFICIT 0xfffU
22087 #define V_CH1_DEFICIT(x) ((x) << S_CH1_DEFICIT)
22088 #define G_CH1_DEFICIT(x) (((x) >> S_CH1_DEFICIT) & M_CH1_DEFICIT)
22090 #define S_CH0_DEFICIT 0
22091 #define M_CH0_DEFICIT 0xfffU
22092 #define V_CH0_DEFICIT(x) ((x) << S_CH0_DEFICIT)
22093 #define G_CH0_DEFICIT(x) (((x) >> S_CH0_DEFICIT) & M_CH0_DEFICIT)
22095 #define A_PM_TX_DBG_STAT14 0x1003a
22097 #define S_CH3_DEFICIT 16
22098 #define M_CH3_DEFICIT 0xfffU
22099 #define V_CH3_DEFICIT(x) ((x) << S_CH3_DEFICIT)
22100 #define G_CH3_DEFICIT(x) (((x) >> S_CH3_DEFICIT) & M_CH3_DEFICIT)
22102 #define S_CH2_DEFICIT 0
22103 #define M_CH2_DEFICIT 0xfffU
22104 #define V_CH2_DEFICIT(x) ((x) << S_CH2_DEFICIT)
22105 #define G_CH2_DEFICIT(x) (((x) >> S_CH2_DEFICIT) & M_CH2_DEFICIT)
22107 #define A_PM_TX_DBG_STAT15 0x1003b
22109 #define S_BUNDLE_LEN_SRDY 28
22110 #define M_BUNDLE_LEN_SRDY 0xfU
22111 #define V_BUNDLE_LEN_SRDY(x) ((x) << S_BUNDLE_LEN_SRDY)
22112 #define G_BUNDLE_LEN_SRDY(x) (((x) >> S_BUNDLE_LEN_SRDY) & M_BUNDLE_LEN_SRDY)
22114 #define S_BUNDLE_LEN1 16
22115 #define M_BUNDLE_LEN1 0xfffU
22116 #define V_BUNDLE_LEN1(x) ((x) << S_BUNDLE_LEN1)
22117 #define G_BUNDLE_LEN1(x) (((x) >> S_BUNDLE_LEN1) & M_BUNDLE_LEN1)
22119 #define S_BUNDLE_LEN0 0
22120 #define M_BUNDLE_LEN0 0xfffU
22121 #define V_BUNDLE_LEN0(x) ((x) << S_BUNDLE_LEN0)
22122 #define G_BUNDLE_LEN0(x) (((x) >> S_BUNDLE_LEN0) & M_BUNDLE_LEN0)
22124 #define A_PM_TX_DBG_STAT16 0x1003c
22126 #define S_BUNDLE_LEN3 16
22127 #define M_BUNDLE_LEN3 0xfffU
22128 #define V_BUNDLE_LEN3(x) ((x) << S_BUNDLE_LEN3)
22129 #define G_BUNDLE_LEN3(x) (((x) >> S_BUNDLE_LEN3) & M_BUNDLE_LEN3)
22131 #define S_BUNDLE_LEN2 0
22132 #define M_BUNDLE_LEN2 0xfffU
22133 #define V_BUNDLE_LEN2(x) ((x) << S_BUNDLE_LEN2)
22134 #define G_BUNDLE_LEN2(x) (((x) >> S_BUNDLE_LEN2) & M_BUNDLE_LEN2)
22136 /* registers for module MPS */
22137 #define MPS_BASE_ADDR 0x9000
22139 #define A_MPS_PORT_CTL 0x0
22141 #define S_LPBKEN 31
22142 #define V_LPBKEN(x) ((x) << S_LPBKEN)
22143 #define F_LPBKEN V_LPBKEN(1U)
22145 #define S_PORTTXEN 30
22146 #define V_PORTTXEN(x) ((x) << S_PORTTXEN)
22147 #define F_PORTTXEN V_PORTTXEN(1U)
22149 #define S_PORTRXEN 29
22150 #define V_PORTRXEN(x) ((x) << S_PORTRXEN)
22151 #define F_PORTRXEN V_PORTRXEN(1U)
22154 #define V_PPPEN(x) ((x) << S_PPPEN)
22155 #define F_PPPEN V_PPPEN(1U)
22157 #define S_FCSSTRIPEN 27
22158 #define V_FCSSTRIPEN(x) ((x) << S_FCSSTRIPEN)
22159 #define F_FCSSTRIPEN V_FCSSTRIPEN(1U)
22161 #define S_PPPANDPAUSE 26
22162 #define V_PPPANDPAUSE(x) ((x) << S_PPPANDPAUSE)
22163 #define F_PPPANDPAUSE V_PPPANDPAUSE(1U)
22165 #define S_PRIOPPPENMAP 16
22166 #define M_PRIOPPPENMAP 0xffU
22167 #define V_PRIOPPPENMAP(x) ((x) << S_PRIOPPPENMAP)
22168 #define G_PRIOPPPENMAP(x) (((x) >> S_PRIOPPPENMAP) & M_PRIOPPPENMAP)
22170 #define A_MPS_VF_CTL 0x0
22171 #define A_MPS_PORT_PAUSE_CTL 0x4
22173 #define S_TIMEUNIT 0
22174 #define M_TIMEUNIT 0xffffU
22175 #define V_TIMEUNIT(x) ((x) << S_TIMEUNIT)
22176 #define G_TIMEUNIT(x) (((x) >> S_TIMEUNIT) & M_TIMEUNIT)
22178 #define A_MPS_PORT_TX_PAUSE_CTL 0x8
22180 #define S_REGSENDOFF 24
22181 #define M_REGSENDOFF 0xffU
22182 #define V_REGSENDOFF(x) ((x) << S_REGSENDOFF)
22183 #define G_REGSENDOFF(x) (((x) >> S_REGSENDOFF) & M_REGSENDOFF)
22185 #define S_REGSENDON 16
22186 #define M_REGSENDON 0xffU
22187 #define V_REGSENDON(x) ((x) << S_REGSENDON)
22188 #define G_REGSENDON(x) (((x) >> S_REGSENDON) & M_REGSENDON)
22190 #define S_SGESENDEN 8
22191 #define M_SGESENDEN 0xffU
22192 #define V_SGESENDEN(x) ((x) << S_SGESENDEN)
22193 #define G_SGESENDEN(x) (((x) >> S_SGESENDEN) & M_SGESENDEN)
22195 #define S_RXSENDEN 0
22196 #define M_RXSENDEN 0xffU
22197 #define V_RXSENDEN(x) ((x) << S_RXSENDEN)
22198 #define G_RXSENDEN(x) (((x) >> S_RXSENDEN) & M_RXSENDEN)
22200 #define A_MPS_PORT_TX_PAUSE_CTL2 0xc
22202 #define S_XOFFDISABLE 0
22203 #define V_XOFFDISABLE(x) ((x) << S_XOFFDISABLE)
22204 #define F_XOFFDISABLE V_XOFFDISABLE(1U)
22206 #define A_MPS_PORT_RX_PAUSE_CTL 0x10
22208 #define S_REGHALTON 8
22209 #define M_REGHALTON 0xffU
22210 #define V_REGHALTON(x) ((x) << S_REGHALTON)
22211 #define G_REGHALTON(x) (((x) >> S_REGHALTON) & M_REGHALTON)
22213 #define S_RXHALTEN 0
22214 #define M_RXHALTEN 0xffU
22215 #define V_RXHALTEN(x) ((x) << S_RXHALTEN)
22216 #define G_RXHALTEN(x) (((x) >> S_RXHALTEN) & M_RXHALTEN)
22218 #define A_MPS_PORT_TX_PAUSE_STATUS 0x14
22220 #define S_REGSENDING 16
22221 #define M_REGSENDING 0xffU
22222 #define V_REGSENDING(x) ((x) << S_REGSENDING)
22223 #define G_REGSENDING(x) (((x) >> S_REGSENDING) & M_REGSENDING)
22225 #define S_SGESENDING 8
22226 #define M_SGESENDING 0xffU
22227 #define V_SGESENDING(x) ((x) << S_SGESENDING)
22228 #define G_SGESENDING(x) (((x) >> S_SGESENDING) & M_SGESENDING)
22230 #define S_RXSENDING 0
22231 #define M_RXSENDING 0xffU
22232 #define V_RXSENDING(x) ((x) << S_RXSENDING)
22233 #define G_RXSENDING(x) (((x) >> S_RXSENDING) & M_RXSENDING)
22235 #define A_MPS_PORT_RX_PAUSE_STATUS 0x18
22237 #define S_REGHALTED 8
22238 #define M_REGHALTED 0xffU
22239 #define V_REGHALTED(x) ((x) << S_REGHALTED)
22240 #define G_REGHALTED(x) (((x) >> S_REGHALTED) & M_REGHALTED)
22242 #define S_RXHALTED 0
22243 #define M_RXHALTED 0xffU
22244 #define V_RXHALTED(x) ((x) << S_RXHALTED)
22245 #define G_RXHALTED(x) (((x) >> S_RXHALTED) & M_RXHALTED)
22247 #define A_MPS_PORT_TX_PAUSE_DEST_L 0x1c
22248 #define A_MPS_PORT_TX_PAUSE_DEST_H 0x20
22251 #define M_ADDR 0xffffU
22252 #define V_ADDR(x) ((x) << S_ADDR)
22253 #define G_ADDR(x) (((x) >> S_ADDR) & M_ADDR)
22255 #define A_MPS_PORT_TX_PAUSE_SOURCE_L 0x24
22256 #define A_MPS_PORT_TX_PAUSE_SOURCE_H 0x28
22257 #define A_MPS_PORT_PRTY_BUFFER_GROUP_MAP 0x2c
22260 #define M_PRTY7 0x3U
22261 #define V_PRTY7(x) ((x) << S_PRTY7)
22262 #define G_PRTY7(x) (((x) >> S_PRTY7) & M_PRTY7)
22265 #define M_PRTY6 0x3U
22266 #define V_PRTY6(x) ((x) << S_PRTY6)
22267 #define G_PRTY6(x) (((x) >> S_PRTY6) & M_PRTY6)
22270 #define M_PRTY5 0x3U
22271 #define V_PRTY5(x) ((x) << S_PRTY5)
22272 #define G_PRTY5(x) (((x) >> S_PRTY5) & M_PRTY5)
22275 #define M_PRTY4 0x3U
22276 #define V_PRTY4(x) ((x) << S_PRTY4)
22277 #define G_PRTY4(x) (((x) >> S_PRTY4) & M_PRTY4)
22280 #define M_PRTY3 0x3U
22281 #define V_PRTY3(x) ((x) << S_PRTY3)
22282 #define G_PRTY3(x) (((x) >> S_PRTY3) & M_PRTY3)
22285 #define M_PRTY2 0x3U
22286 #define V_PRTY2(x) ((x) << S_PRTY2)
22287 #define G_PRTY2(x) (((x) >> S_PRTY2) & M_PRTY2)
22290 #define M_PRTY1 0x3U
22291 #define V_PRTY1(x) ((x) << S_PRTY1)
22292 #define G_PRTY1(x) (((x) >> S_PRTY1) & M_PRTY1)
22295 #define M_PRTY0 0x3U
22296 #define V_PRTY0(x) ((x) << S_PRTY0)
22297 #define G_PRTY0(x) (((x) >> S_PRTY0) & M_PRTY0)
22299 #define A_MPS_PORT_PRTY_BUFFER_GROUP_TH_MAP 0x30
22301 #define S_TXPRTY7 28
22302 #define M_TXPRTY7 0xfU
22303 #define V_TXPRTY7(x) ((x) << S_TXPRTY7)
22304 #define G_TXPRTY7(x) (((x) >> S_TXPRTY7) & M_TXPRTY7)
22306 #define S_TXPRTY6 24
22307 #define M_TXPRTY6 0xfU
22308 #define V_TXPRTY6(x) ((x) << S_TXPRTY6)
22309 #define G_TXPRTY6(x) (((x) >> S_TXPRTY6) & M_TXPRTY6)
22311 #define S_TXPRTY5 20
22312 #define M_TXPRTY5 0xfU
22313 #define V_TXPRTY5(x) ((x) << S_TXPRTY5)
22314 #define G_TXPRTY5(x) (((x) >> S_TXPRTY5) & M_TXPRTY5)
22316 #define S_TXPRTY4 16
22317 #define M_TXPRTY4 0xfU
22318 #define V_TXPRTY4(x) ((x) << S_TXPRTY4)
22319 #define G_TXPRTY4(x) (((x) >> S_TXPRTY4) & M_TXPRTY4)
22321 #define S_TXPRTY3 12
22322 #define M_TXPRTY3 0xfU
22323 #define V_TXPRTY3(x) ((x) << S_TXPRTY3)
22324 #define G_TXPRTY3(x) (((x) >> S_TXPRTY3) & M_TXPRTY3)
22326 #define S_TXPRTY2 8
22327 #define M_TXPRTY2 0xfU
22328 #define V_TXPRTY2(x) ((x) << S_TXPRTY2)
22329 #define G_TXPRTY2(x) (((x) >> S_TXPRTY2) & M_TXPRTY2)
22331 #define S_TXPRTY1 4
22332 #define M_TXPRTY1 0xfU
22333 #define V_TXPRTY1(x) ((x) << S_TXPRTY1)
22334 #define G_TXPRTY1(x) (((x) >> S_TXPRTY1) & M_TXPRTY1)
22336 #define S_TXPRTY0 0
22337 #define M_TXPRTY0 0xfU
22338 #define V_TXPRTY0(x) ((x) << S_TXPRTY0)
22339 #define G_TXPRTY0(x) (((x) >> S_TXPRTY0) & M_TXPRTY0)
22341 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L 0x80
22342 #define A_MPS_VF_STAT_TX_VF_BCAST_BYTES_H 0x84
22343 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_L 0x88
22344 #define A_MPS_VF_STAT_TX_VF_BCAST_FRAMES_H 0x8c
22345 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_L 0x90
22346 #define A_MPS_VF_STAT_TX_VF_MCAST_BYTES_H 0x94
22347 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_L 0x98
22348 #define A_MPS_VF_STAT_TX_VF_MCAST_FRAMES_H 0x9c
22349 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_L 0xa0
22350 #define A_MPS_VF_STAT_TX_VF_UCAST_BYTES_H 0xa4
22351 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_L 0xa8
22352 #define A_MPS_VF_STAT_TX_VF_UCAST_FRAMES_H 0xac
22353 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_L 0xb0
22354 #define A_MPS_VF_STAT_TX_VF_DROP_FRAMES_H 0xb4
22355 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L 0xb8
22356 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H 0xbc
22357 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L 0xc0
22358 #define A_MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H 0xc4
22359 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_L 0xc8
22360 #define A_MPS_VF_STAT_RX_VF_BCAST_BYTES_H 0xcc
22361 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_L 0xd0
22362 #define A_MPS_VF_STAT_RX_VF_BCAST_FRAMES_H 0xd4
22363 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_L 0xd8
22364 #define A_MPS_VF_STAT_RX_VF_MCAST_BYTES_H 0xdc
22365 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_L 0xe0
22366 #define A_MPS_VF_STAT_RX_VF_MCAST_FRAMES_H 0xe4
22367 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_L 0xe8
22368 #define A_MPS_VF_STAT_RX_VF_UCAST_BYTES_H 0xec
22369 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_L 0xf0
22370 #define A_MPS_VF_STAT_RX_VF_UCAST_FRAMES_H 0xf4
22371 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_L 0xf8
22372 #define A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H 0xfc
22373 #define A_MPS_PORT_RX_CTL 0x100
22375 #define S_NO_RPLCT_M 20
22376 #define V_NO_RPLCT_M(x) ((x) << S_NO_RPLCT_M)
22377 #define F_NO_RPLCT_M V_NO_RPLCT_M(1U)
22379 #define S_RPLCT_SEL_L 18
22380 #define M_RPLCT_SEL_L 0x3U
22381 #define V_RPLCT_SEL_L(x) ((x) << S_RPLCT_SEL_L)
22382 #define G_RPLCT_SEL_L(x) (((x) >> S_RPLCT_SEL_L) & M_RPLCT_SEL_L)
22384 #define S_FLTR_VLAN_SEL 17
22385 #define V_FLTR_VLAN_SEL(x) ((x) << S_FLTR_VLAN_SEL)
22386 #define F_FLTR_VLAN_SEL V_FLTR_VLAN_SEL(1U)
22388 #define S_PRIO_VLAN_SEL 16
22389 #define V_PRIO_VLAN_SEL(x) ((x) << S_PRIO_VLAN_SEL)
22390 #define F_PRIO_VLAN_SEL V_PRIO_VLAN_SEL(1U)
22392 #define S_CHK_8023_LEN_M 15
22393 #define V_CHK_8023_LEN_M(x) ((x) << S_CHK_8023_LEN_M)
22394 #define F_CHK_8023_LEN_M V_CHK_8023_LEN_M(1U)
22396 #define S_CHK_8023_LEN_L 14
22397 #define V_CHK_8023_LEN_L(x) ((x) << S_CHK_8023_LEN_L)
22398 #define F_CHK_8023_LEN_L V_CHK_8023_LEN_L(1U)
22400 #define S_NIV_DROP 13
22401 #define V_NIV_DROP(x) ((x) << S_NIV_DROP)
22402 #define F_NIV_DROP V_NIV_DROP(1U)
22404 #define S_NOV_DROP 12
22405 #define V_NOV_DROP(x) ((x) << S_NOV_DROP)
22406 #define F_NOV_DROP V_NOV_DROP(1U)
22408 #define S_CLS_PRT 11
22409 #define V_CLS_PRT(x) ((x) << S_CLS_PRT)
22410 #define F_CLS_PRT V_CLS_PRT(1U)
22412 #define S_RX_QFC_EN 10
22413 #define V_RX_QFC_EN(x) ((x) << S_RX_QFC_EN)
22414 #define F_RX_QFC_EN V_RX_QFC_EN(1U)
22416 #define S_QFC_FWD_UP 9
22417 #define V_QFC_FWD_UP(x) ((x) << S_QFC_FWD_UP)
22418 #define F_QFC_FWD_UP V_QFC_FWD_UP(1U)
22420 #define S_PPP_FWD_UP 8
22421 #define V_PPP_FWD_UP(x) ((x) << S_PPP_FWD_UP)
22422 #define F_PPP_FWD_UP V_PPP_FWD_UP(1U)
22424 #define S_PAUSE_FWD_UP 7
22425 #define V_PAUSE_FWD_UP(x) ((x) << S_PAUSE_FWD_UP)
22426 #define F_PAUSE_FWD_UP V_PAUSE_FWD_UP(1U)
22428 #define S_LPBK_BP 6
22429 #define V_LPBK_BP(x) ((x) << S_LPBK_BP)
22430 #define F_LPBK_BP V_LPBK_BP(1U)
22432 #define S_PASS_NO_MATCH 5
22433 #define V_PASS_NO_MATCH(x) ((x) << S_PASS_NO_MATCH)
22434 #define F_PASS_NO_MATCH V_PASS_NO_MATCH(1U)
22436 #define S_IVLAN_EN 4
22437 #define V_IVLAN_EN(x) ((x) << S_IVLAN_EN)
22438 #define F_IVLAN_EN V_IVLAN_EN(1U)
22440 #define S_OVLAN_EN3 3
22441 #define V_OVLAN_EN3(x) ((x) << S_OVLAN_EN3)
22442 #define F_OVLAN_EN3 V_OVLAN_EN3(1U)
22444 #define S_OVLAN_EN2 2
22445 #define V_OVLAN_EN2(x) ((x) << S_OVLAN_EN2)
22446 #define F_OVLAN_EN2 V_OVLAN_EN2(1U)
22448 #define S_OVLAN_EN1 1
22449 #define V_OVLAN_EN1(x) ((x) << S_OVLAN_EN1)
22450 #define F_OVLAN_EN1 V_OVLAN_EN1(1U)
22452 #define S_OVLAN_EN0 0
22453 #define V_OVLAN_EN0(x) ((x) << S_OVLAN_EN0)
22454 #define F_OVLAN_EN0 V_OVLAN_EN0(1U)
22456 #define S_PTP_FWD_UP 21
22457 #define V_PTP_FWD_UP(x) ((x) << S_PTP_FWD_UP)
22458 #define F_PTP_FWD_UP V_PTP_FWD_UP(1U)
22460 #define A_MPS_PORT_RX_MTU 0x104
22461 #define A_MPS_PORT_RX_PF_MAP 0x108
22462 #define A_MPS_PORT_RX_VF_MAP0 0x10c
22463 #define A_MPS_PORT_RX_VF_MAP1 0x110
22464 #define A_MPS_PORT_RX_VF_MAP2 0x114
22465 #define A_MPS_PORT_RX_VF_MAP3 0x118
22466 #define A_MPS_PORT_RX_IVLAN 0x11c
22468 #define S_IVLAN_ETYPE 0
22469 #define M_IVLAN_ETYPE 0xffffU
22470 #define V_IVLAN_ETYPE(x) ((x) << S_IVLAN_ETYPE)
22471 #define G_IVLAN_ETYPE(x) (((x) >> S_IVLAN_ETYPE) & M_IVLAN_ETYPE)
22473 #define A_MPS_PORT_RX_OVLAN0 0x120
22475 #define S_OVLAN_MASK 16
22476 #define M_OVLAN_MASK 0xffffU
22477 #define V_OVLAN_MASK(x) ((x) << S_OVLAN_MASK)
22478 #define G_OVLAN_MASK(x) (((x) >> S_OVLAN_MASK) & M_OVLAN_MASK)
22480 #define S_OVLAN_ETYPE 0
22481 #define M_OVLAN_ETYPE 0xffffU
22482 #define V_OVLAN_ETYPE(x) ((x) << S_OVLAN_ETYPE)
22483 #define G_OVLAN_ETYPE(x) (((x) >> S_OVLAN_ETYPE) & M_OVLAN_ETYPE)
22485 #define A_MPS_PORT_RX_OVLAN1 0x124
22486 #define A_MPS_PORT_RX_OVLAN2 0x128
22487 #define A_MPS_PORT_RX_OVLAN3 0x12c
22488 #define A_MPS_PORT_RX_RSS_HASH 0x130
22489 #define A_MPS_PORT_RX_RSS_CONTROL 0x134
22491 #define S_RSS_CTRL 16
22492 #define M_RSS_CTRL 0xffU
22493 #define V_RSS_CTRL(x) ((x) << S_RSS_CTRL)
22494 #define G_RSS_CTRL(x) (((x) >> S_RSS_CTRL) & M_RSS_CTRL)
22496 #define S_QUE_NUM 0
22497 #define M_QUE_NUM 0xffffU
22498 #define V_QUE_NUM(x) ((x) << S_QUE_NUM)
22499 #define G_QUE_NUM(x) (((x) >> S_QUE_NUM) & M_QUE_NUM)
22501 #define A_MPS_PORT_RX_CTL1 0x138
22503 #define S_FIXED_PFVF_MAC 13
22504 #define V_FIXED_PFVF_MAC(x) ((x) << S_FIXED_PFVF_MAC)
22505 #define F_FIXED_PFVF_MAC V_FIXED_PFVF_MAC(1U)
22507 #define S_FIXED_PFVF_LPBK 12
22508 #define V_FIXED_PFVF_LPBK(x) ((x) << S_FIXED_PFVF_LPBK)
22509 #define F_FIXED_PFVF_LPBK V_FIXED_PFVF_LPBK(1U)
22511 #define S_FIXED_PFVF_LPBK_OV 11
22512 #define V_FIXED_PFVF_LPBK_OV(x) ((x) << S_FIXED_PFVF_LPBK_OV)
22513 #define F_FIXED_PFVF_LPBK_OV V_FIXED_PFVF_LPBK_OV(1U)
22515 #define S_FIXED_PF 8
22516 #define M_FIXED_PF 0x7U
22517 #define V_FIXED_PF(x) ((x) << S_FIXED_PF)
22518 #define G_FIXED_PF(x) (((x) >> S_FIXED_PF) & M_FIXED_PF)
22520 #define S_FIXED_VF_VLD 7
22521 #define V_FIXED_VF_VLD(x) ((x) << S_FIXED_VF_VLD)
22522 #define F_FIXED_VF_VLD V_FIXED_VF_VLD(1U)
22524 #define S_FIXED_VF 0
22525 #define M_FIXED_VF 0x7fU
22526 #define V_FIXED_VF(x) ((x) << S_FIXED_VF)
22527 #define G_FIXED_VF(x) (((x) >> S_FIXED_VF) & M_FIXED_VF)
22529 #define A_MPS_PORT_RX_SPARE 0x13c
22530 #define A_MPS_PORT_RX_PTP_RSS_HASH 0x140
22531 #define A_MPS_PORT_RX_PTP_RSS_CONTROL 0x144
22532 #define A_MPS_PORT_TX_MAC_RELOAD_CH0 0x190
22535 #define M_CREDIT 0xffffU
22536 #define V_CREDIT(x) ((x) << S_CREDIT)
22537 #define G_CREDIT(x) (((x) >> S_CREDIT) & M_CREDIT)
22539 #define A_MPS_PORT_TX_MAC_RELOAD_CH1 0x194
22540 #define A_MPS_PORT_TX_MAC_RELOAD_CH2 0x198
22541 #define A_MPS_PORT_TX_MAC_RELOAD_CH3 0x19c
22542 #define A_MPS_PORT_TX_MAC_RELOAD_CH4 0x1a0
22543 #define A_MPS_PORT_TX_LPBK_RELOAD_CH0 0x1a8
22544 #define A_MPS_PORT_TX_LPBK_RELOAD_CH1 0x1ac
22545 #define A_MPS_PORT_TX_LPBK_RELOAD_CH2 0x1b0
22546 #define A_MPS_PORT_TX_LPBK_RELOAD_CH3 0x1b4
22547 #define A_MPS_PORT_TX_LPBK_RELOAD_CH4 0x1b8
22548 #define A_MPS_PORT_TX_FIFO_CTL 0x1c4
22551 #define M_FIFOTH 0x1ffU
22552 #define V_FIFOTH(x) ((x) << S_FIFOTH)
22553 #define G_FIFOTH(x) (((x) >> S_FIFOTH) & M_FIFOTH)
22556 #define V_FIFOEN(x) ((x) << S_FIFOEN)
22557 #define F_FIFOEN V_FIFOEN(1U)
22559 #define S_MAXPKTCNT 0
22560 #define M_MAXPKTCNT 0xfU
22561 #define V_MAXPKTCNT(x) ((x) << S_MAXPKTCNT)
22562 #define G_MAXPKTCNT(x) (((x) >> S_MAXPKTCNT) & M_MAXPKTCNT)
22564 #define A_MPS_PORT_FPGA_PAUSE_CTL 0x1c8
22566 #define S_FPGAPAUSEEN 0
22567 #define V_FPGAPAUSEEN(x) ((x) << S_FPGAPAUSEEN)
22568 #define F_FPGAPAUSEEN V_FPGAPAUSEEN(1U)
22570 #define A_MPS_PORT_TX_PAUSE_PENDING_STATUS 0x1d0
22572 #define S_OFF_PENDING 8
22573 #define M_OFF_PENDING 0xffU
22574 #define V_OFF_PENDING(x) ((x) << S_OFF_PENDING)
22575 #define G_OFF_PENDING(x) (((x) >> S_OFF_PENDING) & M_OFF_PENDING)
22577 #define S_ON_PENDING 0
22578 #define M_ON_PENDING 0xffU
22579 #define V_ON_PENDING(x) ((x) << S_ON_PENDING)
22580 #define G_ON_PENDING(x) (((x) >> S_ON_PENDING) & M_ON_PENDING)
22582 #define A_MPS_PORT_CLS_HASH_SRAM 0x200
22585 #define V_VALID(x) ((x) << S_VALID)
22586 #define F_VALID V_VALID(1U)
22588 #define S_HASHPORTMAP 16
22589 #define M_HASHPORTMAP 0xfU
22590 #define V_HASHPORTMAP(x) ((x) << S_HASHPORTMAP)
22591 #define G_HASHPORTMAP(x) (((x) >> S_HASHPORTMAP) & M_HASHPORTMAP)
22593 #define S_MULTILISTEN 15
22594 #define V_MULTILISTEN(x) ((x) << S_MULTILISTEN)
22595 #define F_MULTILISTEN V_MULTILISTEN(1U)
22597 #define S_PRIORITY 12
22598 #define M_PRIORITY 0x7U
22599 #define V_PRIORITY(x) ((x) << S_PRIORITY)
22600 #define G_PRIORITY(x) (((x) >> S_PRIORITY) & M_PRIORITY)
22602 #define S_REPLICATE 11
22603 #define V_REPLICATE(x) ((x) << S_REPLICATE)
22604 #define F_REPLICATE V_REPLICATE(1U)
22608 #define V_PF(x) ((x) << S_PF)
22609 #define G_PF(x) (((x) >> S_PF) & M_PF)
22611 #define S_VF_VALID 7
22612 #define V_VF_VALID(x) ((x) << S_VF_VALID)
22613 #define F_VF_VALID V_VF_VALID(1U)
22617 #define V_VF(x) ((x) << S_VF)
22618 #define G_VF(x) (((x) >> S_VF) & M_VF)
22620 #define A_MPS_PF_CTL 0x2c0
22623 #define V_TXEN(x) ((x) << S_TXEN)
22624 #define F_TXEN V_TXEN(1U)
22627 #define V_RXEN(x) ((x) << S_RXEN)
22628 #define F_RXEN V_RXEN(1U)
22630 #define A_MPS_PF_TX_QINQ_VLAN 0x2e0
22632 #define S_PROTOCOLID 16
22633 #define M_PROTOCOLID 0xffffU
22634 #define V_PROTOCOLID(x) ((x) << S_PROTOCOLID)
22635 #define G_PROTOCOLID(x) (((x) >> S_PROTOCOLID) & M_PROTOCOLID)
22637 #define S_VLAN_PRIO 13
22638 #define M_VLAN_PRIO 0x7U
22639 #define V_VLAN_PRIO(x) ((x) << S_VLAN_PRIO)
22640 #define G_VLAN_PRIO(x) (((x) >> S_VLAN_PRIO) & M_VLAN_PRIO)
22643 #define V_CFI(x) ((x) << S_CFI)
22644 #define F_CFI V_CFI(1U)
22647 #define M_TAG 0xfffU
22648 #define V_TAG(x) ((x) << S_TAG)
22649 #define G_TAG(x) (((x) >> S_TAG) & M_TAG)
22651 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_L 0x300
22652 #define A_MPS_PF_STAT_TX_PF_BCAST_BYTES_H 0x304
22653 #define A_MPS_PORT_CLS_HASH_CTL 0x304
22655 #define S_UNICASTENABLE 31
22656 #define V_UNICASTENABLE(x) ((x) << S_UNICASTENABLE)
22657 #define F_UNICASTENABLE V_UNICASTENABLE(1U)
22659 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_L 0x308
22660 #define A_MPS_PORT_CLS_PROMISCUOUS_CTL 0x308
22662 #define S_PROMISCEN 31
22663 #define V_PROMISCEN(x) ((x) << S_PROMISCEN)
22664 #define F_PROMISCEN V_PROMISCEN(1U)
22666 #define A_MPS_PF_STAT_TX_PF_BCAST_FRAMES_H 0x30c
22667 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_L 0x30c
22668 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_L 0x310
22669 #define A_MPS_PORT_CLS_BMC_MAC_ADDR_H 0x310
22671 #define S_MATCHBOTH 17
22672 #define V_MATCHBOTH(x) ((x) << S_MATCHBOTH)
22673 #define F_MATCHBOTH V_MATCHBOTH(1U)
22675 #define S_BMC_VLD 16
22676 #define V_BMC_VLD(x) ((x) << S_BMC_VLD)
22677 #define F_BMC_VLD V_BMC_VLD(1U)
22679 #define A_MPS_PF_STAT_TX_PF_MCAST_BYTES_H 0x314
22680 #define A_MPS_PORT_CLS_BMC_VLAN 0x314
22682 #define S_BMC_VLAN_SEL 13
22683 #define V_BMC_VLAN_SEL(x) ((x) << S_BMC_VLAN_SEL)
22684 #define F_BMC_VLAN_SEL V_BMC_VLAN_SEL(1U)
22686 #define S_VLAN_VLD 12
22687 #define V_VLAN_VLD(x) ((x) << S_VLAN_VLD)
22688 #define F_VLAN_VLD V_VLAN_VLD(1U)
22690 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_L 0x318
22691 #define A_MPS_PORT_CLS_CTL 0x318
22693 #define S_PF_VLAN_SEL 0
22694 #define V_PF_VLAN_SEL(x) ((x) << S_PF_VLAN_SEL)
22695 #define F_PF_VLAN_SEL V_PF_VLAN_SEL(1U)
22697 #define S_LPBK_TCAM1_HIT_PRIORITY 14
22698 #define V_LPBK_TCAM1_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM1_HIT_PRIORITY)
22699 #define F_LPBK_TCAM1_HIT_PRIORITY V_LPBK_TCAM1_HIT_PRIORITY(1U)
22701 #define S_LPBK_TCAM0_HIT_PRIORITY 13
22702 #define V_LPBK_TCAM0_HIT_PRIORITY(x) ((x) << S_LPBK_TCAM0_HIT_PRIORITY)
22703 #define F_LPBK_TCAM0_HIT_PRIORITY V_LPBK_TCAM0_HIT_PRIORITY(1U)
22705 #define S_LPBK_TCAM_PRIORITY 12
22706 #define V_LPBK_TCAM_PRIORITY(x) ((x) << S_LPBK_TCAM_PRIORITY)
22707 #define F_LPBK_TCAM_PRIORITY V_LPBK_TCAM_PRIORITY(1U)
22709 #define S_LPBK_SMAC_TCAM_SEL 10
22710 #define M_LPBK_SMAC_TCAM_SEL 0x3U
22711 #define V_LPBK_SMAC_TCAM_SEL(x) ((x) << S_LPBK_SMAC_TCAM_SEL)
22712 #define G_LPBK_SMAC_TCAM_SEL(x) (((x) >> S_LPBK_SMAC_TCAM_SEL) & M_LPBK_SMAC_TCAM_SEL)
22714 #define S_LPBK_DMAC_TCAM_SEL 8
22715 #define M_LPBK_DMAC_TCAM_SEL 0x3U
22716 #define V_LPBK_DMAC_TCAM_SEL(x) ((x) << S_LPBK_DMAC_TCAM_SEL)
22717 #define G_LPBK_DMAC_TCAM_SEL(x) (((x) >> S_LPBK_DMAC_TCAM_SEL) & M_LPBK_DMAC_TCAM_SEL)
22719 #define S_TCAM1_HIT_PRIORITY 7
22720 #define V_TCAM1_HIT_PRIORITY(x) ((x) << S_TCAM1_HIT_PRIORITY)
22721 #define F_TCAM1_HIT_PRIORITY V_TCAM1_HIT_PRIORITY(1U)
22723 #define S_TCAM0_HIT_PRIORITY 6
22724 #define V_TCAM0_HIT_PRIORITY(x) ((x) << S_TCAM0_HIT_PRIORITY)
22725 #define F_TCAM0_HIT_PRIORITY V_TCAM0_HIT_PRIORITY(1U)
22727 #define S_TCAM_PRIORITY 5
22728 #define V_TCAM_PRIORITY(x) ((x) << S_TCAM_PRIORITY)
22729 #define F_TCAM_PRIORITY V_TCAM_PRIORITY(1U)
22731 #define S_SMAC_TCAM_SEL 3
22732 #define M_SMAC_TCAM_SEL 0x3U
22733 #define V_SMAC_TCAM_SEL(x) ((x) << S_SMAC_TCAM_SEL)
22734 #define G_SMAC_TCAM_SEL(x) (((x) >> S_SMAC_TCAM_SEL) & M_SMAC_TCAM_SEL)
22736 #define S_DMAC_TCAM_SEL 1
22737 #define M_DMAC_TCAM_SEL 0x3U
22738 #define V_DMAC_TCAM_SEL(x) ((x) << S_DMAC_TCAM_SEL)
22739 #define G_DMAC_TCAM_SEL(x) (((x) >> S_DMAC_TCAM_SEL) & M_DMAC_TCAM_SEL)
22741 #define A_MPS_PF_STAT_TX_PF_MCAST_FRAMES_H 0x31c
22742 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_L 0x320
22743 #define A_MPS_PF_STAT_TX_PF_UCAST_BYTES_H 0x324
22744 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_L 0x328
22745 #define A_MPS_PF_STAT_TX_PF_UCAST_FRAMES_H 0x32c
22746 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_L 0x330
22747 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_BYTES_H 0x334
22748 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_L 0x338
22749 #define A_MPS_PF_STAT_TX_PF_OFFLOAD_FRAMES_H 0x33c
22750 #define A_MPS_PF_STAT_RX_PF_BYTES_L 0x340
22751 #define A_MPS_PF_STAT_RX_PF_BYTES_H 0x344
22752 #define A_MPS_PF_STAT_RX_PF_FRAMES_L 0x348
22753 #define A_MPS_PF_STAT_RX_PF_FRAMES_H 0x34c
22754 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_L 0x350
22755 #define A_MPS_PF_STAT_RX_PF_BCAST_BYTES_H 0x354
22756 #define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_L 0x358
22757 #define A_MPS_PF_STAT_RX_PF_BCAST_FRAMES_H 0x35c
22758 #define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_L 0x360
22759 #define A_MPS_PF_STAT_RX_PF_MCAST_BYTES_H 0x364
22760 #define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_L 0x368
22761 #define A_MPS_PF_STAT_RX_PF_MCAST_FRAMES_H 0x36c
22762 #define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_L 0x370
22763 #define A_MPS_PF_STAT_RX_PF_UCAST_BYTES_H 0x374
22764 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_L 0x378
22765 #define A_MPS_PF_STAT_RX_PF_UCAST_FRAMES_H 0x37c
22766 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_L 0x380
22767 #define A_MPS_PF_STAT_RX_PF_ERR_FRAMES_H 0x384
22768 #define A_MPS_PORT_STAT_TX_PORT_BYTES_L 0x400
22769 #define A_MPS_PORT_STAT_TX_PORT_BYTES_H 0x404
22770 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_L 0x408
22771 #define A_MPS_PORT_STAT_TX_PORT_FRAMES_H 0x40c
22772 #define A_MPS_PORT_STAT_TX_PORT_BCAST_L 0x410
22773 #define A_MPS_PORT_STAT_TX_PORT_BCAST_H 0x414
22774 #define A_MPS_PORT_STAT_TX_PORT_MCAST_L 0x418
22775 #define A_MPS_PORT_STAT_TX_PORT_MCAST_H 0x41c
22776 #define A_MPS_PORT_STAT_TX_PORT_UCAST_L 0x420
22777 #define A_MPS_PORT_STAT_TX_PORT_UCAST_H 0x424
22778 #define A_MPS_PORT_STAT_TX_PORT_ERROR_L 0x428
22779 #define A_MPS_PORT_STAT_TX_PORT_ERROR_H 0x42c
22780 #define A_MPS_PORT_STAT_TX_PORT_64B_L 0x430
22781 #define A_MPS_PORT_STAT_TX_PORT_64B_H 0x434
22782 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_L 0x438
22783 #define A_MPS_PORT_STAT_TX_PORT_65B_127B_H 0x43c
22784 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_L 0x440
22785 #define A_MPS_PORT_STAT_TX_PORT_128B_255B_H 0x444
22786 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_L 0x448
22787 #define A_MPS_PORT_STAT_TX_PORT_256B_511B_H 0x44c
22788 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_L 0x450
22789 #define A_MPS_PORT_STAT_TX_PORT_512B_1023B_H 0x454
22790 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L 0x458
22791 #define A_MPS_PORT_STAT_TX_PORT_1024B_1518B_H 0x45c
22792 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L 0x460
22793 #define A_MPS_PORT_STAT_TX_PORT_1519B_MAX_H 0x464
22794 #define A_MPS_PORT_STAT_TX_PORT_DROP_L 0x468
22795 #define A_MPS_PORT_STAT_TX_PORT_DROP_H 0x46c
22796 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_L 0x470
22797 #define A_MPS_PORT_STAT_TX_PORT_PAUSE_H 0x474
22798 #define A_MPS_PORT_STAT_TX_PORT_PPP0_L 0x478
22799 #define A_MPS_PORT_STAT_TX_PORT_PPP0_H 0x47c
22800 #define A_MPS_PORT_STAT_TX_PORT_PPP1_L 0x480
22801 #define A_MPS_PORT_STAT_TX_PORT_PPP1_H 0x484
22802 #define A_MPS_PORT_STAT_TX_PORT_PPP2_L 0x488
22803 #define A_MPS_PORT_STAT_TX_PORT_PPP2_H 0x48c
22804 #define A_MPS_PORT_STAT_TX_PORT_PPP3_L 0x490
22805 #define A_MPS_PORT_STAT_TX_PORT_PPP3_H 0x494
22806 #define A_MPS_PORT_STAT_TX_PORT_PPP4_L 0x498
22807 #define A_MPS_PORT_STAT_TX_PORT_PPP4_H 0x49c
22808 #define A_MPS_PORT_STAT_TX_PORT_PPP5_L 0x4a0
22809 #define A_MPS_PORT_STAT_TX_PORT_PPP5_H 0x4a4
22810 #define A_MPS_PORT_STAT_TX_PORT_PPP6_L 0x4a8
22811 #define A_MPS_PORT_STAT_TX_PORT_PPP6_H 0x4ac
22812 #define A_MPS_PORT_STAT_TX_PORT_PPP7_L 0x4b0
22813 #define A_MPS_PORT_STAT_TX_PORT_PPP7_H 0x4b4
22814 #define A_MPS_PORT_STAT_LB_PORT_BYTES_L 0x4c0
22815 #define A_MPS_PORT_STAT_LB_PORT_BYTES_H 0x4c4
22816 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_L 0x4c8
22817 #define A_MPS_PORT_STAT_LB_PORT_FRAMES_H 0x4cc
22818 #define A_MPS_PORT_STAT_LB_PORT_BCAST_L 0x4d0
22819 #define A_MPS_PORT_STAT_LB_PORT_BCAST_H 0x4d4
22820 #define A_MPS_PORT_STAT_LB_PORT_MCAST_L 0x4d8
22821 #define A_MPS_PORT_STAT_LB_PORT_MCAST_H 0x4dc
22822 #define A_MPS_PORT_STAT_LB_PORT_UCAST_L 0x4e0
22823 #define A_MPS_PORT_STAT_LB_PORT_UCAST_H 0x4e4
22824 #define A_MPS_PORT_STAT_LB_PORT_ERROR_L 0x4e8
22825 #define A_MPS_PORT_STAT_LB_PORT_ERROR_H 0x4ec
22826 #define A_MPS_PORT_STAT_LB_PORT_64B_L 0x4f0
22827 #define A_MPS_PORT_STAT_LB_PORT_64B_H 0x4f4
22828 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_L 0x4f8
22829 #define A_MPS_PORT_STAT_LB_PORT_65B_127B_H 0x4fc
22830 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_L 0x500
22831 #define A_MPS_PORT_STAT_LB_PORT_128B_255B_H 0x504
22832 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_L 0x508
22833 #define A_MPS_PORT_STAT_LB_PORT_256B_511B_H 0x50c
22834 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_L 0x510
22835 #define A_MPS_PORT_STAT_LB_PORT_512B_1023B_H 0x514
22836 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_L 0x518
22837 #define A_MPS_PORT_STAT_LB_PORT_1024B_1518B_H 0x51c
22838 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_L 0x520
22839 #define A_MPS_PORT_STAT_LB_PORT_1519B_MAX_H 0x524
22840 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES 0x528
22841 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_L 0x528
22842 #define A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES_H 0x52c
22843 #define A_MPS_PORT_STAT_RX_PORT_BYTES_L 0x540
22844 #define A_MPS_PORT_STAT_RX_PORT_BYTES_H 0x544
22845 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_L 0x548
22846 #define A_MPS_PORT_STAT_RX_PORT_FRAMES_H 0x54c
22847 #define A_MPS_PORT_STAT_RX_PORT_BCAST_L 0x550
22848 #define A_MPS_PORT_STAT_RX_PORT_BCAST_H 0x554
22849 #define A_MPS_PORT_STAT_RX_PORT_MCAST_L 0x558
22850 #define A_MPS_PORT_STAT_RX_PORT_MCAST_H 0x55c
22851 #define A_MPS_PORT_STAT_RX_PORT_UCAST_L 0x560
22852 #define A_MPS_PORT_STAT_RX_PORT_UCAST_H 0x564
22853 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L 0x568
22854 #define A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_H 0x56c
22855 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L 0x570
22856 #define A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_H 0x574
22857 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L 0x578
22858 #define A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_H 0x57c
22859 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L 0x580
22860 #define A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_H 0x584
22861 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L 0x588
22862 #define A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_H 0x58c
22863 #define A_MPS_PORT_STAT_RX_PORT_64B_L 0x590
22864 #define A_MPS_PORT_STAT_RX_PORT_64B_H 0x594
22865 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_L 0x598
22866 #define A_MPS_PORT_STAT_RX_PORT_65B_127B_H 0x59c
22867 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_L 0x5a0
22868 #define A_MPS_PORT_STAT_RX_PORT_128B_255B_H 0x5a4
22869 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_L 0x5a8
22870 #define A_MPS_PORT_STAT_RX_PORT_256B_511B_H 0x5ac
22871 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_L 0x5b0
22872 #define A_MPS_PORT_STAT_RX_PORT_512B_1023B_H 0x5b4
22873 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L 0x5b8
22874 #define A_MPS_PORT_STAT_RX_PORT_1024B_1518B_H 0x5bc
22875 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L 0x5c0
22876 #define A_MPS_PORT_STAT_RX_PORT_1519B_MAX_H 0x5c4
22877 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_L 0x5c8
22878 #define A_MPS_PORT_STAT_RX_PORT_PAUSE_H 0x5cc
22879 #define A_MPS_PORT_STAT_RX_PORT_PPP0_L 0x5d0
22880 #define A_MPS_PORT_STAT_RX_PORT_PPP0_H 0x5d4
22881 #define A_MPS_PORT_STAT_RX_PORT_PPP1_L 0x5d8
22882 #define A_MPS_PORT_STAT_RX_PORT_PPP1_H 0x5dc
22883 #define A_MPS_PORT_STAT_RX_PORT_PPP2_L 0x5e0
22884 #define A_MPS_PORT_STAT_RX_PORT_PPP2_H 0x5e4
22885 #define A_MPS_PORT_STAT_RX_PORT_PPP3_L 0x5e8
22886 #define A_MPS_PORT_STAT_RX_PORT_PPP3_H 0x5ec
22887 #define A_MPS_PORT_STAT_RX_PORT_PPP4_L 0x5f0
22888 #define A_MPS_PORT_STAT_RX_PORT_PPP4_H 0x5f4
22889 #define A_MPS_PORT_STAT_RX_PORT_PPP5_L 0x5f8
22890 #define A_MPS_PORT_STAT_RX_PORT_PPP5_H 0x5fc
22891 #define A_MPS_PORT_STAT_RX_PORT_PPP6_L 0x600
22892 #define A_MPS_PORT_STAT_RX_PORT_PPP6_H 0x604
22893 #define A_MPS_PORT_STAT_RX_PORT_PPP7_L 0x608
22894 #define A_MPS_PORT_STAT_RX_PORT_PPP7_H 0x60c
22895 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_L 0x610
22896 #define A_MPS_PORT_STAT_RX_PORT_LESS_64B_H 0x614
22897 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_L 0x618
22898 #define A_MPS_PORT_STAT_RX_PORT_MAC_ERROR_H 0x61c
22899 #define A_MPS_CMN_CTL 0x9000
22901 #define S_DETECT8023 3
22902 #define V_DETECT8023(x) ((x) << S_DETECT8023)
22903 #define F_DETECT8023 V_DETECT8023(1U)
22905 #define S_VFDIRECTACCESS 2
22906 #define V_VFDIRECTACCESS(x) ((x) << S_VFDIRECTACCESS)
22907 #define F_VFDIRECTACCESS V_VFDIRECTACCESS(1U)
22909 #define S_NUMPORTS 0
22910 #define M_NUMPORTS 0x3U
22911 #define V_NUMPORTS(x) ((x) << S_NUMPORTS)
22912 #define G_NUMPORTS(x) (((x) >> S_NUMPORTS) & M_NUMPORTS)
22914 #define S_LPBKCRDTCTRL 4
22915 #define V_LPBKCRDTCTRL(x) ((x) << S_LPBKCRDTCTRL)
22916 #define F_LPBKCRDTCTRL V_LPBKCRDTCTRL(1U)
22918 #define A_MPS_INT_ENABLE 0x9004
22920 #define S_STATINTENB 5
22921 #define V_STATINTENB(x) ((x) << S_STATINTENB)
22922 #define F_STATINTENB V_STATINTENB(1U)
22924 #define S_TXINTENB 4
22925 #define V_TXINTENB(x) ((x) << S_TXINTENB)
22926 #define F_TXINTENB V_TXINTENB(1U)
22928 #define S_RXINTENB 3
22929 #define V_RXINTENB(x) ((x) << S_RXINTENB)
22930 #define F_RXINTENB V_RXINTENB(1U)
22932 #define S_TRCINTENB 2
22933 #define V_TRCINTENB(x) ((x) << S_TRCINTENB)
22934 #define F_TRCINTENB V_TRCINTENB(1U)
22936 #define S_CLSINTENB 1
22937 #define V_CLSINTENB(x) ((x) << S_CLSINTENB)
22938 #define F_CLSINTENB V_CLSINTENB(1U)
22940 #define S_PLINTENB 0
22941 #define V_PLINTENB(x) ((x) << S_PLINTENB)
22942 #define F_PLINTENB V_PLINTENB(1U)
22944 #define A_MPS_INT_CAUSE 0x9008
22946 #define S_STATINT 5
22947 #define V_STATINT(x) ((x) << S_STATINT)
22948 #define F_STATINT V_STATINT(1U)
22951 #define V_TXINT(x) ((x) << S_TXINT)
22952 #define F_TXINT V_TXINT(1U)
22955 #define V_RXINT(x) ((x) << S_RXINT)
22956 #define F_RXINT V_RXINT(1U)
22959 #define V_TRCINT(x) ((x) << S_TRCINT)
22960 #define F_TRCINT V_TRCINT(1U)
22963 #define V_CLSINT(x) ((x) << S_CLSINT)
22964 #define F_CLSINT V_CLSINT(1U)
22967 #define V_PLINT(x) ((x) << S_PLINT)
22968 #define F_PLINT V_PLINT(1U)
22970 #define A_MPS_CGEN_GLOBAL 0x900c
22972 #define S_MPS_GLOBAL_CGEN 0
22973 #define V_MPS_GLOBAL_CGEN(x) ((x) << S_MPS_GLOBAL_CGEN)
22974 #define F_MPS_GLOBAL_CGEN V_MPS_GLOBAL_CGEN(1U)
22976 #define A_MPS_VF_TX_CTL_31_0 0x9010
22977 #define A_MPS_VF_TX_CTL_63_32 0x9014
22978 #define A_MPS_VF_TX_CTL_95_64 0x9018
22979 #define A_MPS_VF_TX_CTL_127_96 0x901c
22980 #define A_MPS_VF_RX_CTL_31_0 0x9020
22981 #define A_MPS_VF_RX_CTL_63_32 0x9024
22982 #define A_MPS_VF_RX_CTL_95_64 0x9028
22983 #define A_MPS_VF_RX_CTL_127_96 0x902c
22984 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP0 0x9030
22987 #define M_VALUE 0xffffU
22988 #define V_VALUE(x) ((x) << S_VALUE)
22989 #define G_VALUE(x) (((x) >> S_VALUE) & M_VALUE)
22991 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP1 0x9034
22992 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP2 0x9038
22993 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP3 0x903c
22994 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP0 0x9040
22995 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP1 0x9044
22996 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP2 0x9048
22997 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP3 0x904c
22998 #define A_MPS_TP_CSIDE_MUX_CTL_P0 0x9050
23001 #define M_WEIGHT 0xfffU
23002 #define V_WEIGHT(x) ((x) << S_WEIGHT)
23003 #define G_WEIGHT(x) (((x) >> S_WEIGHT) & M_WEIGHT)
23005 #define A_MPS_TP_CSIDE_MUX_CTL_P1 0x9054
23006 #define A_MPS_WOL_CTL_MODE 0x9058
23008 #define S_WOL_MODE 0
23009 #define V_WOL_MODE(x) ((x) << S_WOL_MODE)
23010 #define F_WOL_MODE V_WOL_MODE(1U)
23012 #define A_MPS_FPGA_DEBUG 0x9060
23014 #define S_LPBK_EN 8
23015 #define V_LPBK_EN(x) ((x) << S_LPBK_EN)
23016 #define F_LPBK_EN V_LPBK_EN(1U)
23018 #define S_CH_MAP3 6
23019 #define M_CH_MAP3 0x3U
23020 #define V_CH_MAP3(x) ((x) << S_CH_MAP3)
23021 #define G_CH_MAP3(x) (((x) >> S_CH_MAP3) & M_CH_MAP3)
23023 #define S_CH_MAP2 4
23024 #define M_CH_MAP2 0x3U
23025 #define V_CH_MAP2(x) ((x) << S_CH_MAP2)
23026 #define G_CH_MAP2(x) (((x) >> S_CH_MAP2) & M_CH_MAP2)
23028 #define S_CH_MAP1 2
23029 #define M_CH_MAP1 0x3U
23030 #define V_CH_MAP1(x) ((x) << S_CH_MAP1)
23031 #define G_CH_MAP1(x) (((x) >> S_CH_MAP1) & M_CH_MAP1)
23033 #define S_CH_MAP0 0
23034 #define M_CH_MAP0 0x3U
23035 #define V_CH_MAP0(x) ((x) << S_CH_MAP0)
23036 #define G_CH_MAP0(x) (((x) >> S_CH_MAP0) & M_CH_MAP0)
23038 #define S_FPGA_PTP_PORT 9
23039 #define M_FPGA_PTP_PORT 0x3U
23040 #define V_FPGA_PTP_PORT(x) ((x) << S_FPGA_PTP_PORT)
23041 #define G_FPGA_PTP_PORT(x) (((x) >> S_FPGA_PTP_PORT) & M_FPGA_PTP_PORT)
23043 #define A_MPS_DEBUG_CTL 0x9068
23045 #define S_DBGMODECTL_H 11
23046 #define V_DBGMODECTL_H(x) ((x) << S_DBGMODECTL_H)
23047 #define F_DBGMODECTL_H V_DBGMODECTL_H(1U)
23049 #define S_DBGSEL_H 6
23050 #define M_DBGSEL_H 0x1fU
23051 #define V_DBGSEL_H(x) ((x) << S_DBGSEL_H)
23052 #define G_DBGSEL_H(x) (((x) >> S_DBGSEL_H) & M_DBGSEL_H)
23054 #define S_DBGMODECTL_L 5
23055 #define V_DBGMODECTL_L(x) ((x) << S_DBGMODECTL_L)
23056 #define F_DBGMODECTL_L V_DBGMODECTL_L(1U)
23058 #define S_DBGSEL_L 0
23059 #define M_DBGSEL_L 0x1fU
23060 #define V_DBGSEL_L(x) ((x) << S_DBGSEL_L)
23061 #define G_DBGSEL_L(x) (((x) >> S_DBGSEL_L) & M_DBGSEL_L)
23063 #define A_MPS_DEBUG_DATA_REG_L 0x906c
23064 #define A_MPS_DEBUG_DATA_REG_H 0x9070
23065 #define A_MPS_TOP_SPARE 0x9074
23067 #define S_TOPSPARE 8
23068 #define M_TOPSPARE 0xffffffU
23069 #define V_TOPSPARE(x) ((x) << S_TOPSPARE)
23070 #define G_TOPSPARE(x) (((x) >> S_TOPSPARE) & M_TOPSPARE)
23072 #define S_OVLANSELLPBK3 7
23073 #define V_OVLANSELLPBK3(x) ((x) << S_OVLANSELLPBK3)
23074 #define F_OVLANSELLPBK3 V_OVLANSELLPBK3(1U)
23076 #define S_OVLANSELLPBK2 6
23077 #define V_OVLANSELLPBK2(x) ((x) << S_OVLANSELLPBK2)
23078 #define F_OVLANSELLPBK2 V_OVLANSELLPBK2(1U)
23080 #define S_OVLANSELLPBK1 5
23081 #define V_OVLANSELLPBK1(x) ((x) << S_OVLANSELLPBK1)
23082 #define F_OVLANSELLPBK1 V_OVLANSELLPBK1(1U)
23084 #define S_OVLANSELLPBK0 4
23085 #define V_OVLANSELLPBK0(x) ((x) << S_OVLANSELLPBK0)
23086 #define F_OVLANSELLPBK0 V_OVLANSELLPBK0(1U)
23088 #define S_OVLANSELMAC3 3
23089 #define V_OVLANSELMAC3(x) ((x) << S_OVLANSELMAC3)
23090 #define F_OVLANSELMAC3 V_OVLANSELMAC3(1U)
23092 #define S_OVLANSELMAC2 2
23093 #define V_OVLANSELMAC2(x) ((x) << S_OVLANSELMAC2)
23094 #define F_OVLANSELMAC2 V_OVLANSELMAC2(1U)
23096 #define S_OVLANSELMAC1 1
23097 #define V_OVLANSELMAC1(x) ((x) << S_OVLANSELMAC1)
23098 #define F_OVLANSELMAC1 V_OVLANSELMAC1(1U)
23100 #define S_OVLANSELMAC0 0
23101 #define V_OVLANSELMAC0(x) ((x) << S_OVLANSELMAC0)
23102 #define F_OVLANSELMAC0 V_OVLANSELMAC0(1U)
23104 #define S_T5_TOPSPARE 8
23105 #define M_T5_TOPSPARE 0xffffffU
23106 #define V_T5_TOPSPARE(x) ((x) << S_T5_TOPSPARE)
23107 #define G_T5_TOPSPARE(x) (((x) >> S_T5_TOPSPARE) & M_T5_TOPSPARE)
23109 #define A_MPS_T5_BUILD_REVISION 0x9078
23110 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH0 0x907c
23111 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH1 0x9080
23112 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH2 0x9084
23113 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH3 0x9088
23114 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH4 0x908c
23115 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH5 0x9090
23116 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH6 0x9094
23117 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH7 0x9098
23118 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH8 0x909c
23119 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH9 0x90a0
23120 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH10 0x90a4
23121 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH11 0x90a8
23122 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH12 0x90ac
23123 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH13 0x90b0
23124 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH14 0x90b4
23125 #define A_MPS_TX_PAUSE_DURATION_BUF_GRP_TH15 0x90b8
23126 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH0 0x90bc
23127 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH1 0x90c0
23128 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH2 0x90c4
23129 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH3 0x90c8
23130 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH4 0x90cc
23131 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH5 0x90d0
23132 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH6 0x90d4
23133 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH7 0x90d8
23134 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH8 0x90dc
23135 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH9 0x90e0
23136 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH10 0x90e4
23137 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH11 0x90e8
23138 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH12 0x90ec
23139 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH13 0x90f0
23140 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH14 0x90f4
23141 #define A_MPS_TX_PAUSE_RETRANS_BUF_GRP_TH15 0x90f8
23142 #define A_MPS_BUILD_REVISION 0x90fc
23143 #define A_MPS_TX_PRTY_SEL 0x9400
23145 #define S_CH4_PRTY 20
23146 #define M_CH4_PRTY 0x7U
23147 #define V_CH4_PRTY(x) ((x) << S_CH4_PRTY)
23148 #define G_CH4_PRTY(x) (((x) >> S_CH4_PRTY) & M_CH4_PRTY)
23150 #define S_CH3_PRTY 16
23151 #define M_CH3_PRTY 0x7U
23152 #define V_CH3_PRTY(x) ((x) << S_CH3_PRTY)
23153 #define G_CH3_PRTY(x) (((x) >> S_CH3_PRTY) & M_CH3_PRTY)
23155 #define S_CH2_PRTY 12
23156 #define M_CH2_PRTY 0x7U
23157 #define V_CH2_PRTY(x) ((x) << S_CH2_PRTY)
23158 #define G_CH2_PRTY(x) (((x) >> S_CH2_PRTY) & M_CH2_PRTY)
23160 #define S_CH1_PRTY 8
23161 #define M_CH1_PRTY 0x7U
23162 #define V_CH1_PRTY(x) ((x) << S_CH1_PRTY)
23163 #define G_CH1_PRTY(x) (((x) >> S_CH1_PRTY) & M_CH1_PRTY)
23165 #define S_CH0_PRTY 4
23166 #define M_CH0_PRTY 0x7U
23167 #define V_CH0_PRTY(x) ((x) << S_CH0_PRTY)
23168 #define G_CH0_PRTY(x) (((x) >> S_CH0_PRTY) & M_CH0_PRTY)
23170 #define S_TP_SOURCE 2
23171 #define M_TP_SOURCE 0x3U
23172 #define V_TP_SOURCE(x) ((x) << S_TP_SOURCE)
23173 #define G_TP_SOURCE(x) (((x) >> S_TP_SOURCE) & M_TP_SOURCE)
23175 #define S_NCSI_SOURCE 0
23176 #define M_NCSI_SOURCE 0x3U
23177 #define V_NCSI_SOURCE(x) ((x) << S_NCSI_SOURCE)
23178 #define G_NCSI_SOURCE(x) (((x) >> S_NCSI_SOURCE) & M_NCSI_SOURCE)
23180 #define A_MPS_TX_INT_ENABLE 0x9404
23182 #define S_PORTERR 16
23183 #define V_PORTERR(x) ((x) << S_PORTERR)
23184 #define F_PORTERR V_PORTERR(1U)
23186 #define S_FRMERR 15
23187 #define V_FRMERR(x) ((x) << S_FRMERR)
23188 #define F_FRMERR V_FRMERR(1U)
23190 #define S_SECNTERR 14
23191 #define V_SECNTERR(x) ((x) << S_SECNTERR)
23192 #define F_SECNTERR V_SECNTERR(1U)
23194 #define S_BUBBLE 13
23195 #define V_BUBBLE(x) ((x) << S_BUBBLE)
23196 #define F_BUBBLE V_BUBBLE(1U)
23198 #define S_TXDESCFIFO 9
23199 #define M_TXDESCFIFO 0xfU
23200 #define V_TXDESCFIFO(x) ((x) << S_TXDESCFIFO)
23201 #define G_TXDESCFIFO(x) (((x) >> S_TXDESCFIFO) & M_TXDESCFIFO)
23203 #define S_TXDATAFIFO 5
23204 #define M_TXDATAFIFO 0xfU
23205 #define V_TXDATAFIFO(x) ((x) << S_TXDATAFIFO)
23206 #define G_TXDATAFIFO(x) (((x) >> S_TXDATAFIFO) & M_TXDATAFIFO)
23208 #define S_NCSIFIFO 4
23209 #define V_NCSIFIFO(x) ((x) << S_NCSIFIFO)
23210 #define F_NCSIFIFO V_NCSIFIFO(1U)
23213 #define M_TPFIFO 0xfU
23214 #define V_TPFIFO(x) ((x) << S_TPFIFO)
23215 #define G_TPFIFO(x) (((x) >> S_TPFIFO) & M_TPFIFO)
23217 #define A_MPS_TX_INT_CAUSE 0x9408
23218 #define A_MPS_TX_PERR_ENABLE 0x9410
23219 #define A_MPS_TX_PERR_INJECT 0x9414
23221 #define S_MPSTXMEMSEL 1
23222 #define M_MPSTXMEMSEL 0x1fU
23223 #define V_MPSTXMEMSEL(x) ((x) << S_MPSTXMEMSEL)
23224 #define G_MPSTXMEMSEL(x) (((x) >> S_MPSTXMEMSEL) & M_MPSTXMEMSEL)
23226 #define A_MPS_TX_SE_CNT_TP01 0x9418
23227 #define A_MPS_TX_SE_CNT_TP23 0x941c
23228 #define A_MPS_TX_SE_CNT_MAC01 0x9420
23229 #define A_MPS_TX_SE_CNT_MAC23 0x9424
23230 #define A_MPS_TX_SECNT_SPI_BUBBLE_ERR 0x9428
23232 #define S_BUBBLEERR 16
23233 #define M_BUBBLEERR 0xffU
23234 #define V_BUBBLEERR(x) ((x) << S_BUBBLEERR)
23235 #define G_BUBBLEERR(x) (((x) >> S_BUBBLEERR) & M_BUBBLEERR)
23238 #define M_SPI 0xffU
23239 #define V_SPI(x) ((x) << S_SPI)
23240 #define G_SPI(x) (((x) >> S_SPI) & M_SPI)
23243 #define M_SECNT 0xffU
23244 #define V_SECNT(x) ((x) << S_SECNT)
23245 #define G_SECNT(x) (((x) >> S_SECNT) & M_SECNT)
23247 #define A_MPS_TX_SECNT_BUBBLE_CLR 0x942c
23249 #define S_BUBBLECLR 8
23250 #define M_BUBBLECLR 0xffU
23251 #define V_BUBBLECLR(x) ((x) << S_BUBBLECLR)
23252 #define G_BUBBLECLR(x) (((x) >> S_BUBBLECLR) & M_BUBBLECLR)
23254 #define S_NCSISECNT 20
23255 #define V_NCSISECNT(x) ((x) << S_NCSISECNT)
23256 #define F_NCSISECNT V_NCSISECNT(1U)
23258 #define S_LPBKSECNT 16
23259 #define M_LPBKSECNT 0xfU
23260 #define V_LPBKSECNT(x) ((x) << S_LPBKSECNT)
23261 #define G_LPBKSECNT(x) (((x) >> S_LPBKSECNT) & M_LPBKSECNT)
23263 #define A_MPS_TX_PORT_ERR 0x9430
23265 #define S_LPBKPT3 7
23266 #define V_LPBKPT3(x) ((x) << S_LPBKPT3)
23267 #define F_LPBKPT3 V_LPBKPT3(1U)
23269 #define S_LPBKPT2 6
23270 #define V_LPBKPT2(x) ((x) << S_LPBKPT2)
23271 #define F_LPBKPT2 V_LPBKPT2(1U)
23273 #define S_LPBKPT1 5
23274 #define V_LPBKPT1(x) ((x) << S_LPBKPT1)
23275 #define F_LPBKPT1 V_LPBKPT1(1U)
23277 #define S_LPBKPT0 4
23278 #define V_LPBKPT0(x) ((x) << S_LPBKPT0)
23279 #define F_LPBKPT0 V_LPBKPT0(1U)
23282 #define V_PT3(x) ((x) << S_PT3)
23283 #define F_PT3 V_PT3(1U)
23286 #define V_PT2(x) ((x) << S_PT2)
23287 #define F_PT2 V_PT2(1U)
23290 #define V_PT1(x) ((x) << S_PT1)
23291 #define F_PT1 V_PT1(1U)
23294 #define V_PT0(x) ((x) << S_PT0)
23295 #define F_PT0 V_PT0(1U)
23297 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH0 0x9434
23300 #define V_BPEN(x) ((x) << S_BPEN)
23301 #define F_BPEN V_BPEN(1U)
23304 #define V_DROPEN(x) ((x) << S_DROPEN)
23305 #define F_DROPEN V_DROPEN(1U)
23307 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH1 0x9438
23308 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH2 0x943c
23309 #define A_MPS_TX_LPBK_DROP_BP_CTL_CH3 0x9440
23310 #define A_MPS_TX_DEBUG_REG_TP2TX_10 0x9444
23312 #define S_SOPCH1 31
23313 #define V_SOPCH1(x) ((x) << S_SOPCH1)
23314 #define F_SOPCH1 V_SOPCH1(1U)
23316 #define S_EOPCH1 30
23317 #define V_EOPCH1(x) ((x) << S_EOPCH1)
23318 #define F_EOPCH1 V_EOPCH1(1U)
23320 #define S_SIZECH1 27
23321 #define M_SIZECH1 0x7U
23322 #define V_SIZECH1(x) ((x) << S_SIZECH1)
23323 #define G_SIZECH1(x) (((x) >> S_SIZECH1) & M_SIZECH1)
23325 #define S_ERRCH1 26
23326 #define V_ERRCH1(x) ((x) << S_ERRCH1)
23327 #define F_ERRCH1 V_ERRCH1(1U)
23329 #define S_FULLCH1 25
23330 #define V_FULLCH1(x) ((x) << S_FULLCH1)
23331 #define F_FULLCH1 V_FULLCH1(1U)
23333 #define S_VALIDCH1 24
23334 #define V_VALIDCH1(x) ((x) << S_VALIDCH1)
23335 #define F_VALIDCH1 V_VALIDCH1(1U)
23337 #define S_DATACH1 16
23338 #define M_DATACH1 0xffU
23339 #define V_DATACH1(x) ((x) << S_DATACH1)
23340 #define G_DATACH1(x) (((x) >> S_DATACH1) & M_DATACH1)
23342 #define S_SOPCH0 15
23343 #define V_SOPCH0(x) ((x) << S_SOPCH0)
23344 #define F_SOPCH0 V_SOPCH0(1U)
23346 #define S_EOPCH0 14
23347 #define V_EOPCH0(x) ((x) << S_EOPCH0)
23348 #define F_EOPCH0 V_EOPCH0(1U)
23350 #define S_SIZECH0 11
23351 #define M_SIZECH0 0x7U
23352 #define V_SIZECH0(x) ((x) << S_SIZECH0)
23353 #define G_SIZECH0(x) (((x) >> S_SIZECH0) & M_SIZECH0)
23355 #define S_ERRCH0 10
23356 #define V_ERRCH0(x) ((x) << S_ERRCH0)
23357 #define F_ERRCH0 V_ERRCH0(1U)
23359 #define S_FULLCH0 9
23360 #define V_FULLCH0(x) ((x) << S_FULLCH0)
23361 #define F_FULLCH0 V_FULLCH0(1U)
23363 #define S_VALIDCH0 8
23364 #define V_VALIDCH0(x) ((x) << S_VALIDCH0)
23365 #define F_VALIDCH0 V_VALIDCH0(1U)
23367 #define S_DATACH0 0
23368 #define M_DATACH0 0xffU
23369 #define V_DATACH0(x) ((x) << S_DATACH0)
23370 #define G_DATACH0(x) (((x) >> S_DATACH0) & M_DATACH0)
23372 #define A_MPS_TX_DEBUG_REG_TP2TX_32 0x9448
23374 #define S_SOPCH3 31
23375 #define V_SOPCH3(x) ((x) << S_SOPCH3)
23376 #define F_SOPCH3 V_SOPCH3(1U)
23378 #define S_EOPCH3 30
23379 #define V_EOPCH3(x) ((x) << S_EOPCH3)
23380 #define F_EOPCH3 V_EOPCH3(1U)
23382 #define S_SIZECH3 27
23383 #define M_SIZECH3 0x7U
23384 #define V_SIZECH3(x) ((x) << S_SIZECH3)
23385 #define G_SIZECH3(x) (((x) >> S_SIZECH3) & M_SIZECH3)
23387 #define S_ERRCH3 26
23388 #define V_ERRCH3(x) ((x) << S_ERRCH3)
23389 #define F_ERRCH3 V_ERRCH3(1U)
23391 #define S_FULLCH3 25
23392 #define V_FULLCH3(x) ((x) << S_FULLCH3)
23393 #define F_FULLCH3 V_FULLCH3(1U)
23395 #define S_VALIDCH3 24
23396 #define V_VALIDCH3(x) ((x) << S_VALIDCH3)
23397 #define F_VALIDCH3 V_VALIDCH3(1U)
23399 #define S_DATACH3 16
23400 #define M_DATACH3 0xffU
23401 #define V_DATACH3(x) ((x) << S_DATACH3)
23402 #define G_DATACH3(x) (((x) >> S_DATACH3) & M_DATACH3)
23404 #define S_SOPCH2 15
23405 #define V_SOPCH2(x) ((x) << S_SOPCH2)
23406 #define F_SOPCH2 V_SOPCH2(1U)
23408 #define S_EOPCH2 14
23409 #define V_EOPCH2(x) ((x) << S_EOPCH2)
23410 #define F_EOPCH2 V_EOPCH2(1U)
23412 #define S_SIZECH2 11
23413 #define M_SIZECH2 0x7U
23414 #define V_SIZECH2(x) ((x) << S_SIZECH2)
23415 #define G_SIZECH2(x) (((x) >> S_SIZECH2) & M_SIZECH2)
23417 #define S_ERRCH2 10
23418 #define V_ERRCH2(x) ((x) << S_ERRCH2)
23419 #define F_ERRCH2 V_ERRCH2(1U)
23421 #define S_FULLCH2 9
23422 #define V_FULLCH2(x) ((x) << S_FULLCH2)
23423 #define F_FULLCH2 V_FULLCH2(1U)
23425 #define S_VALIDCH2 8
23426 #define V_VALIDCH2(x) ((x) << S_VALIDCH2)
23427 #define F_VALIDCH2 V_VALIDCH2(1U)
23429 #define S_DATACH2 0
23430 #define M_DATACH2 0xffU
23431 #define V_DATACH2(x) ((x) << S_DATACH2)
23432 #define G_DATACH2(x) (((x) >> S_DATACH2) & M_DATACH2)
23434 #define A_MPS_TX_DEBUG_REG_TX2MAC_10 0x944c
23436 #define S_SOPPT1 31
23437 #define V_SOPPT1(x) ((x) << S_SOPPT1)
23438 #define F_SOPPT1 V_SOPPT1(1U)
23440 #define S_EOPPT1 30
23441 #define V_EOPPT1(x) ((x) << S_EOPPT1)
23442 #define F_EOPPT1 V_EOPPT1(1U)
23444 #define S_SIZEPT1 27
23445 #define M_SIZEPT1 0x7U
23446 #define V_SIZEPT1(x) ((x) << S_SIZEPT1)
23447 #define G_SIZEPT1(x) (((x) >> S_SIZEPT1) & M_SIZEPT1)
23449 #define S_ERRPT1 26
23450 #define V_ERRPT1(x) ((x) << S_ERRPT1)
23451 #define F_ERRPT1 V_ERRPT1(1U)
23453 #define S_FULLPT1 25
23454 #define V_FULLPT1(x) ((x) << S_FULLPT1)
23455 #define F_FULLPT1 V_FULLPT1(1U)
23457 #define S_VALIDPT1 24
23458 #define V_VALIDPT1(x) ((x) << S_VALIDPT1)
23459 #define F_VALIDPT1 V_VALIDPT1(1U)
23461 #define S_DATAPT1 16
23462 #define M_DATAPT1 0xffU
23463 #define V_DATAPT1(x) ((x) << S_DATAPT1)
23464 #define G_DATAPT1(x) (((x) >> S_DATAPT1) & M_DATAPT1)
23466 #define S_SOPPT0 15
23467 #define V_SOPPT0(x) ((x) << S_SOPPT0)
23468 #define F_SOPPT0 V_SOPPT0(1U)
23470 #define S_EOPPT0 14
23471 #define V_EOPPT0(x) ((x) << S_EOPPT0)
23472 #define F_EOPPT0 V_EOPPT0(1U)
23474 #define S_SIZEPT0 11
23475 #define M_SIZEPT0 0x7U
23476 #define V_SIZEPT0(x) ((x) << S_SIZEPT0)
23477 #define G_SIZEPT0(x) (((x) >> S_SIZEPT0) & M_SIZEPT0)
23479 #define S_ERRPT0 10
23480 #define V_ERRPT0(x) ((x) << S_ERRPT0)
23481 #define F_ERRPT0 V_ERRPT0(1U)
23483 #define S_FULLPT0 9
23484 #define V_FULLPT0(x) ((x) << S_FULLPT0)
23485 #define F_FULLPT0 V_FULLPT0(1U)
23487 #define S_VALIDPT0 8
23488 #define V_VALIDPT0(x) ((x) << S_VALIDPT0)
23489 #define F_VALIDPT0 V_VALIDPT0(1U)
23491 #define S_DATAPT0 0
23492 #define M_DATAPT0 0xffU
23493 #define V_DATAPT0(x) ((x) << S_DATAPT0)
23494 #define G_DATAPT0(x) (((x) >> S_DATAPT0) & M_DATAPT0)
23496 #define A_MPS_TX_DEBUG_REG_TX2MAC_32 0x9450
23498 #define S_SOPPT3 31
23499 #define V_SOPPT3(x) ((x) << S_SOPPT3)
23500 #define F_SOPPT3 V_SOPPT3(1U)
23502 #define S_EOPPT3 30
23503 #define V_EOPPT3(x) ((x) << S_EOPPT3)
23504 #define F_EOPPT3 V_EOPPT3(1U)
23506 #define S_SIZEPT3 27
23507 #define M_SIZEPT3 0x7U
23508 #define V_SIZEPT3(x) ((x) << S_SIZEPT3)
23509 #define G_SIZEPT3(x) (((x) >> S_SIZEPT3) & M_SIZEPT3)
23511 #define S_ERRPT3 26
23512 #define V_ERRPT3(x) ((x) << S_ERRPT3)
23513 #define F_ERRPT3 V_ERRPT3(1U)
23515 #define S_FULLPT3 25
23516 #define V_FULLPT3(x) ((x) << S_FULLPT3)
23517 #define F_FULLPT3 V_FULLPT3(1U)
23519 #define S_VALIDPT3 24
23520 #define V_VALIDPT3(x) ((x) << S_VALIDPT3)
23521 #define F_VALIDPT3 V_VALIDPT3(1U)
23523 #define S_DATAPT3 16
23524 #define M_DATAPT3 0xffU
23525 #define V_DATAPT3(x) ((x) << S_DATAPT3)
23526 #define G_DATAPT3(x) (((x) >> S_DATAPT3) & M_DATAPT3)
23528 #define S_SOPPT2 15
23529 #define V_SOPPT2(x) ((x) << S_SOPPT2)
23530 #define F_SOPPT2 V_SOPPT2(1U)
23532 #define S_EOPPT2 14
23533 #define V_EOPPT2(x) ((x) << S_EOPPT2)
23534 #define F_EOPPT2 V_EOPPT2(1U)
23536 #define S_SIZEPT2 11
23537 #define M_SIZEPT2 0x7U
23538 #define V_SIZEPT2(x) ((x) << S_SIZEPT2)
23539 #define G_SIZEPT2(x) (((x) >> S_SIZEPT2) & M_SIZEPT2)
23541 #define S_ERRPT2 10
23542 #define V_ERRPT2(x) ((x) << S_ERRPT2)
23543 #define F_ERRPT2 V_ERRPT2(1U)
23545 #define S_FULLPT2 9
23546 #define V_FULLPT2(x) ((x) << S_FULLPT2)
23547 #define F_FULLPT2 V_FULLPT2(1U)
23549 #define S_VALIDPT2 8
23550 #define V_VALIDPT2(x) ((x) << S_VALIDPT2)
23551 #define F_VALIDPT2 V_VALIDPT2(1U)
23553 #define S_DATAPT2 0
23554 #define M_DATAPT2 0xffU
23555 #define V_DATAPT2(x) ((x) << S_DATAPT2)
23556 #define G_DATAPT2(x) (((x) >> S_DATAPT2) & M_DATAPT2)
23558 #define A_MPS_TX_SGE_CH_PAUSE_IGNR 0x9454
23560 #define S_SGEPAUSEIGNR 0
23561 #define M_SGEPAUSEIGNR 0xfU
23562 #define V_SGEPAUSEIGNR(x) ((x) << S_SGEPAUSEIGNR)
23563 #define G_SGEPAUSEIGNR(x) (((x) >> S_SGEPAUSEIGNR) & M_SGEPAUSEIGNR)
23565 #define A_MPS_T5_TX_SGE_CH_PAUSE_IGNR 0x9454
23567 #define S_T5SGEPAUSEIGNR 0
23568 #define M_T5SGEPAUSEIGNR 0xffffU
23569 #define V_T5SGEPAUSEIGNR(x) ((x) << S_T5SGEPAUSEIGNR)
23570 #define G_T5SGEPAUSEIGNR(x) (((x) >> S_T5SGEPAUSEIGNR) & M_T5SGEPAUSEIGNR)
23572 #define A_MPS_TX_DEBUG_SUBPART_SEL 0x9458
23574 #define S_SUBPRTH 11
23575 #define M_SUBPRTH 0x1fU
23576 #define V_SUBPRTH(x) ((x) << S_SUBPRTH)
23577 #define G_SUBPRTH(x) (((x) >> S_SUBPRTH) & M_SUBPRTH)
23580 #define M_PORTH 0x7U
23581 #define V_PORTH(x) ((x) << S_PORTH)
23582 #define G_PORTH(x) (((x) >> S_PORTH) & M_PORTH)
23584 #define S_SUBPRTL 3
23585 #define M_SUBPRTL 0x1fU
23586 #define V_SUBPRTL(x) ((x) << S_SUBPRTL)
23587 #define G_SUBPRTL(x) (((x) >> S_SUBPRTL) & M_SUBPRTL)
23590 #define M_PORTL 0x7U
23591 #define V_PORTL(x) ((x) << S_PORTL)
23592 #define G_PORTL(x) (((x) >> S_PORTL) & M_PORTL)
23594 #define A_MPS_TX_PAD_CTL 0x945c
23596 #define S_LPBKPADENPT3 7
23597 #define V_LPBKPADENPT3(x) ((x) << S_LPBKPADENPT3)
23598 #define F_LPBKPADENPT3 V_LPBKPADENPT3(1U)
23600 #define S_LPBKPADENPT2 6
23601 #define V_LPBKPADENPT2(x) ((x) << S_LPBKPADENPT2)
23602 #define F_LPBKPADENPT2 V_LPBKPADENPT2(1U)
23604 #define S_LPBKPADENPT1 5
23605 #define V_LPBKPADENPT1(x) ((x) << S_LPBKPADENPT1)
23606 #define F_LPBKPADENPT1 V_LPBKPADENPT1(1U)
23608 #define S_LPBKPADENPT0 4
23609 #define V_LPBKPADENPT0(x) ((x) << S_LPBKPADENPT0)
23610 #define F_LPBKPADENPT0 V_LPBKPADENPT0(1U)
23612 #define S_MACPADENPT3 3
23613 #define V_MACPADENPT3(x) ((x) << S_MACPADENPT3)
23614 #define F_MACPADENPT3 V_MACPADENPT3(1U)
23616 #define S_MACPADENPT2 2
23617 #define V_MACPADENPT2(x) ((x) << S_MACPADENPT2)
23618 #define F_MACPADENPT2 V_MACPADENPT2(1U)
23620 #define S_MACPADENPT1 1
23621 #define V_MACPADENPT1(x) ((x) << S_MACPADENPT1)
23622 #define F_MACPADENPT1 V_MACPADENPT1(1U)
23624 #define S_MACPADENPT0 0
23625 #define V_MACPADENPT0(x) ((x) << S_MACPADENPT0)
23626 #define F_MACPADENPT0 V_MACPADENPT0(1U)
23628 #define A_MPS_TX_PFVF_PORT_DROP_TP 0x9460
23630 #define S_TP2MPS_CH3 24
23631 #define M_TP2MPS_CH3 0xffU
23632 #define V_TP2MPS_CH3(x) ((x) << S_TP2MPS_CH3)
23633 #define G_TP2MPS_CH3(x) (((x) >> S_TP2MPS_CH3) & M_TP2MPS_CH3)
23635 #define S_TP2MPS_CH2 16
23636 #define M_TP2MPS_CH2 0xffU
23637 #define V_TP2MPS_CH2(x) ((x) << S_TP2MPS_CH2)
23638 #define G_TP2MPS_CH2(x) (((x) >> S_TP2MPS_CH2) & M_TP2MPS_CH2)
23640 #define S_TP2MPS_CH1 8
23641 #define M_TP2MPS_CH1 0xffU
23642 #define V_TP2MPS_CH1(x) ((x) << S_TP2MPS_CH1)
23643 #define G_TP2MPS_CH1(x) (((x) >> S_TP2MPS_CH1) & M_TP2MPS_CH1)
23645 #define S_TP2MPS_CH0 0
23646 #define M_TP2MPS_CH0 0xffU
23647 #define V_TP2MPS_CH0(x) ((x) << S_TP2MPS_CH0)
23648 #define G_TP2MPS_CH0(x) (((x) >> S_TP2MPS_CH0) & M_TP2MPS_CH0)
23650 #define A_MPS_TX_PFVF_PORT_DROP_NCSI 0x9464
23652 #define S_NCSI_CH4 0
23653 #define M_NCSI_CH4 0xffU
23654 #define V_NCSI_CH4(x) ((x) << S_NCSI_CH4)
23655 #define G_NCSI_CH4(x) (((x) >> S_NCSI_CH4) & M_NCSI_CH4)
23657 #define A_MPS_TX_PFVF_PORT_DROP_CTL 0x9468
23659 #define S_PFNOVFDROP 5
23660 #define V_PFNOVFDROP(x) ((x) << S_PFNOVFDROP)
23661 #define F_PFNOVFDROP V_PFNOVFDROP(1U)
23663 #define S_NCSI_CH4_CLR 4
23664 #define V_NCSI_CH4_CLR(x) ((x) << S_NCSI_CH4_CLR)
23665 #define F_NCSI_CH4_CLR V_NCSI_CH4_CLR(1U)
23667 #define S_TP2MPS_CH3_CLR 3
23668 #define V_TP2MPS_CH3_CLR(x) ((x) << S_TP2MPS_CH3_CLR)
23669 #define F_TP2MPS_CH3_CLR V_TP2MPS_CH3_CLR(1U)
23671 #define S_TP2MPS_CH2_CLR 2
23672 #define V_TP2MPS_CH2_CLR(x) ((x) << S_TP2MPS_CH2_CLR)
23673 #define F_TP2MPS_CH2_CLR V_TP2MPS_CH2_CLR(1U)
23675 #define S_TP2MPS_CH1_CLR 1
23676 #define V_TP2MPS_CH1_CLR(x) ((x) << S_TP2MPS_CH1_CLR)
23677 #define F_TP2MPS_CH1_CLR V_TP2MPS_CH1_CLR(1U)
23679 #define S_TP2MPS_CH0_CLR 0
23680 #define V_TP2MPS_CH0_CLR(x) ((x) << S_TP2MPS_CH0_CLR)
23681 #define F_TP2MPS_CH0_CLR V_TP2MPS_CH0_CLR(1U)
23683 #define A_MPS_TX_CGEN 0x946c
23685 #define S_TXOUTLPBK3_CGEN 31
23686 #define V_TXOUTLPBK3_CGEN(x) ((x) << S_TXOUTLPBK3_CGEN)
23687 #define F_TXOUTLPBK3_CGEN V_TXOUTLPBK3_CGEN(1U)
23689 #define S_TXOUTLPBK2_CGEN 30
23690 #define V_TXOUTLPBK2_CGEN(x) ((x) << S_TXOUTLPBK2_CGEN)
23691 #define F_TXOUTLPBK2_CGEN V_TXOUTLPBK2_CGEN(1U)
23693 #define S_TXOUTLPBK1_CGEN 29
23694 #define V_TXOUTLPBK1_CGEN(x) ((x) << S_TXOUTLPBK1_CGEN)
23695 #define F_TXOUTLPBK1_CGEN V_TXOUTLPBK1_CGEN(1U)
23697 #define S_TXOUTLPBK0_CGEN 28
23698 #define V_TXOUTLPBK0_CGEN(x) ((x) << S_TXOUTLPBK0_CGEN)
23699 #define F_TXOUTLPBK0_CGEN V_TXOUTLPBK0_CGEN(1U)
23701 #define S_TXOUTMAC3_CGEN 27
23702 #define V_TXOUTMAC3_CGEN(x) ((x) << S_TXOUTMAC3_CGEN)
23703 #define F_TXOUTMAC3_CGEN V_TXOUTMAC3_CGEN(1U)
23705 #define S_TXOUTMAC2_CGEN 26
23706 #define V_TXOUTMAC2_CGEN(x) ((x) << S_TXOUTMAC2_CGEN)
23707 #define F_TXOUTMAC2_CGEN V_TXOUTMAC2_CGEN(1U)
23709 #define S_TXOUTMAC1_CGEN 25
23710 #define V_TXOUTMAC1_CGEN(x) ((x) << S_TXOUTMAC1_CGEN)
23711 #define F_TXOUTMAC1_CGEN V_TXOUTMAC1_CGEN(1U)
23713 #define S_TXOUTMAC0_CGEN 24
23714 #define V_TXOUTMAC0_CGEN(x) ((x) << S_TXOUTMAC0_CGEN)
23715 #define F_TXOUTMAC0_CGEN V_TXOUTMAC0_CGEN(1U)
23717 #define S_TXSCHLPBK3_CGEN 23
23718 #define V_TXSCHLPBK3_CGEN(x) ((x) << S_TXSCHLPBK3_CGEN)
23719 #define F_TXSCHLPBK3_CGEN V_TXSCHLPBK3_CGEN(1U)
23721 #define S_TXSCHLPBK2_CGEN 22
23722 #define V_TXSCHLPBK2_CGEN(x) ((x) << S_TXSCHLPBK2_CGEN)
23723 #define F_TXSCHLPBK2_CGEN V_TXSCHLPBK2_CGEN(1U)
23725 #define S_TXSCHLPBK1_CGEN 21
23726 #define V_TXSCHLPBK1_CGEN(x) ((x) << S_TXSCHLPBK1_CGEN)
23727 #define F_TXSCHLPBK1_CGEN V_TXSCHLPBK1_CGEN(1U)
23729 #define S_TXSCHLPBK0_CGEN 20
23730 #define V_TXSCHLPBK0_CGEN(x) ((x) << S_TXSCHLPBK0_CGEN)
23731 #define F_TXSCHLPBK0_CGEN V_TXSCHLPBK0_CGEN(1U)
23733 #define S_TXSCHMAC3_CGEN 19
23734 #define V_TXSCHMAC3_CGEN(x) ((x) << S_TXSCHMAC3_CGEN)
23735 #define F_TXSCHMAC3_CGEN V_TXSCHMAC3_CGEN(1U)
23737 #define S_TXSCHMAC2_CGEN 18
23738 #define V_TXSCHMAC2_CGEN(x) ((x) << S_TXSCHMAC2_CGEN)
23739 #define F_TXSCHMAC2_CGEN V_TXSCHMAC2_CGEN(1U)
23741 #define S_TXSCHMAC1_CGEN 17
23742 #define V_TXSCHMAC1_CGEN(x) ((x) << S_TXSCHMAC1_CGEN)
23743 #define F_TXSCHMAC1_CGEN V_TXSCHMAC1_CGEN(1U)
23745 #define S_TXSCHMAC0_CGEN 16
23746 #define V_TXSCHMAC0_CGEN(x) ((x) << S_TXSCHMAC0_CGEN)
23747 #define F_TXSCHMAC0_CGEN V_TXSCHMAC0_CGEN(1U)
23749 #define S_TXINCH4_CGEN 15
23750 #define V_TXINCH4_CGEN(x) ((x) << S_TXINCH4_CGEN)
23751 #define F_TXINCH4_CGEN V_TXINCH4_CGEN(1U)
23753 #define S_TXINCH3_CGEN 14
23754 #define V_TXINCH3_CGEN(x) ((x) << S_TXINCH3_CGEN)
23755 #define F_TXINCH3_CGEN V_TXINCH3_CGEN(1U)
23757 #define S_TXINCH2_CGEN 13
23758 #define V_TXINCH2_CGEN(x) ((x) << S_TXINCH2_CGEN)
23759 #define F_TXINCH2_CGEN V_TXINCH2_CGEN(1U)
23761 #define S_TXINCH1_CGEN 12
23762 #define V_TXINCH1_CGEN(x) ((x) << S_TXINCH1_CGEN)
23763 #define F_TXINCH1_CGEN V_TXINCH1_CGEN(1U)
23765 #define S_TXINCH0_CGEN 11
23766 #define V_TXINCH0_CGEN(x) ((x) << S_TXINCH0_CGEN)
23767 #define F_TXINCH0_CGEN V_TXINCH0_CGEN(1U)
23769 #define A_MPS_TX_CGEN_DYNAMIC 0x9470
23770 #define A_MPS_STAT_CTL 0x9600
23772 #define S_COUNTVFINPF 1
23773 #define V_COUNTVFINPF(x) ((x) << S_COUNTVFINPF)
23774 #define F_COUNTVFINPF V_COUNTVFINPF(1U)
23776 #define S_LPBKERRSTAT 0
23777 #define V_LPBKERRSTAT(x) ((x) << S_LPBKERRSTAT)
23778 #define F_LPBKERRSTAT V_LPBKERRSTAT(1U)
23780 #define S_STATSTOPCTRL 10
23781 #define V_STATSTOPCTRL(x) ((x) << S_STATSTOPCTRL)
23782 #define F_STATSTOPCTRL V_STATSTOPCTRL(1U)
23784 #define S_STOPSTAT 9
23785 #define V_STOPSTAT(x) ((x) << S_STOPSTAT)
23786 #define F_STOPSTAT V_STOPSTAT(1U)
23788 #define S_STATWRITECTRL 8
23789 #define V_STATWRITECTRL(x) ((x) << S_STATWRITECTRL)
23790 #define F_STATWRITECTRL V_STATWRITECTRL(1U)
23792 #define S_COUNTLBPF 7
23793 #define V_COUNTLBPF(x) ((x) << S_COUNTLBPF)
23794 #define F_COUNTLBPF V_COUNTLBPF(1U)
23796 #define S_COUNTLBVF 6
23797 #define V_COUNTLBVF(x) ((x) << S_COUNTLBVF)
23798 #define F_COUNTLBVF V_COUNTLBVF(1U)
23800 #define S_COUNTPAUSEMCRX 5
23801 #define V_COUNTPAUSEMCRX(x) ((x) << S_COUNTPAUSEMCRX)
23802 #define F_COUNTPAUSEMCRX V_COUNTPAUSEMCRX(1U)
23804 #define S_COUNTPAUSESTATRX 4
23805 #define V_COUNTPAUSESTATRX(x) ((x) << S_COUNTPAUSESTATRX)
23806 #define F_COUNTPAUSESTATRX V_COUNTPAUSESTATRX(1U)
23808 #define S_COUNTPAUSEMCTX 3
23809 #define V_COUNTPAUSEMCTX(x) ((x) << S_COUNTPAUSEMCTX)
23810 #define F_COUNTPAUSEMCTX V_COUNTPAUSEMCTX(1U)
23812 #define S_COUNTPAUSESTATTX 2
23813 #define V_COUNTPAUSESTATTX(x) ((x) << S_COUNTPAUSESTATTX)
23814 #define F_COUNTPAUSESTATTX V_COUNTPAUSESTATTX(1U)
23816 #define A_MPS_STAT_INT_ENABLE 0x9608
23818 #define S_PLREADSYNCERR 0
23819 #define V_PLREADSYNCERR(x) ((x) << S_PLREADSYNCERR)
23820 #define F_PLREADSYNCERR V_PLREADSYNCERR(1U)
23822 #define A_MPS_STAT_INT_CAUSE 0x960c
23823 #define A_MPS_STAT_PERR_INT_ENABLE_SRAM 0x9610
23826 #define V_RXBG(x) ((x) << S_RXBG)
23827 #define F_RXBG V_RXBG(1U)
23830 #define M_RXVF 0x3U
23831 #define V_RXVF(x) ((x) << S_RXVF)
23832 #define G_RXVF(x) (((x) >> S_RXVF) & M_RXVF)
23835 #define M_TXVF 0x3U
23836 #define V_TXVF(x) ((x) << S_TXVF)
23837 #define G_TXVF(x) (((x) >> S_TXVF) & M_TXVF)
23840 #define M_RXPF 0x7U
23841 #define V_RXPF(x) ((x) << S_RXPF)
23842 #define G_RXPF(x) (((x) >> S_RXPF) & M_RXPF)
23845 #define M_TXPF 0x3U
23846 #define V_TXPF(x) ((x) << S_TXPF)
23847 #define G_TXPF(x) (((x) >> S_TXPF) & M_TXPF)
23850 #define M_RXPORT 0xfU
23851 #define V_RXPORT(x) ((x) << S_RXPORT)
23852 #define G_RXPORT(x) (((x) >> S_RXPORT) & M_RXPORT)
23855 #define M_LBPORT 0x7U
23856 #define V_LBPORT(x) ((x) << S_LBPORT)
23857 #define G_LBPORT(x) (((x) >> S_LBPORT) & M_LBPORT)
23860 #define M_TXPORT 0xfU
23861 #define V_TXPORT(x) ((x) << S_TXPORT)
23862 #define G_TXPORT(x) (((x) >> S_TXPORT) & M_TXPORT)
23864 #define S_T5_RXBG 27
23865 #define M_T5_RXBG 0x3U
23866 #define V_T5_RXBG(x) ((x) << S_T5_RXBG)
23867 #define G_T5_RXBG(x) (((x) >> S_T5_RXBG) & M_T5_RXBG)
23869 #define S_T5_RXPF 22
23870 #define M_T5_RXPF 0x1fU
23871 #define V_T5_RXPF(x) ((x) << S_T5_RXPF)
23872 #define G_T5_RXPF(x) (((x) >> S_T5_RXPF) & M_T5_RXPF)
23874 #define S_T5_TXPF 18
23875 #define M_T5_TXPF 0xfU
23876 #define V_T5_TXPF(x) ((x) << S_T5_TXPF)
23877 #define G_T5_TXPF(x) (((x) >> S_T5_TXPF) & M_T5_TXPF)
23879 #define S_T5_RXPORT 11
23880 #define M_T5_RXPORT 0x7fU
23881 #define V_T5_RXPORT(x) ((x) << S_T5_RXPORT)
23882 #define G_T5_RXPORT(x) (((x) >> S_T5_RXPORT) & M_T5_RXPORT)
23884 #define S_T5_LBPORT 6
23885 #define M_T5_LBPORT 0x1fU
23886 #define V_T5_LBPORT(x) ((x) << S_T5_LBPORT)
23887 #define G_T5_LBPORT(x) (((x) >> S_T5_LBPORT) & M_T5_LBPORT)
23889 #define S_T5_TXPORT 0
23890 #define M_T5_TXPORT 0x3fU
23891 #define V_T5_TXPORT(x) ((x) << S_T5_TXPORT)
23892 #define G_T5_TXPORT(x) (((x) >> S_T5_TXPORT) & M_T5_TXPORT)
23894 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM 0x9614
23895 #define A_MPS_STAT_PERR_ENABLE_SRAM 0x9618
23896 #define A_MPS_STAT_PERR_INT_ENABLE_TX_FIFO 0x961c
23900 #define V_TX(x) ((x) << S_TX)
23901 #define G_TX(x) (((x) >> S_TX) & M_TX)
23903 #define S_TXPAUSEFIFO 8
23904 #define M_TXPAUSEFIFO 0xfU
23905 #define V_TXPAUSEFIFO(x) ((x) << S_TXPAUSEFIFO)
23906 #define G_TXPAUSEFIFO(x) (((x) >> S_TXPAUSEFIFO) & M_TXPAUSEFIFO)
23909 #define M_DROP 0xffU
23910 #define V_DROP(x) ((x) << S_DROP)
23911 #define G_DROP(x) (((x) >> S_DROP) & M_DROP)
23914 #define M_TXCH 0xfU
23915 #define V_TXCH(x) ((x) << S_TXCH)
23916 #define G_TXCH(x) (((x) >> S_TXCH) & M_TXCH)
23918 #define A_MPS_STAT_PERR_INT_CAUSE_TX_FIFO 0x9620
23919 #define A_MPS_STAT_PERR_ENABLE_TX_FIFO 0x9624
23920 #define A_MPS_STAT_PERR_INT_ENABLE_RX_FIFO 0x9628
23922 #define S_PAUSEFIFO 20
23923 #define M_PAUSEFIFO 0xfU
23924 #define V_PAUSEFIFO(x) ((x) << S_PAUSEFIFO)
23925 #define G_PAUSEFIFO(x) (((x) >> S_PAUSEFIFO) & M_PAUSEFIFO)
23928 #define M_LPBK 0xfU
23929 #define V_LPBK(x) ((x) << S_LPBK)
23930 #define G_LPBK(x) (((x) >> S_LPBK) & M_LPBK)
23934 #define V_NQ(x) ((x) << S_NQ)
23935 #define G_NQ(x) (((x) >> S_NQ) & M_NQ)
23939 #define V_PV(x) ((x) << S_PV)
23940 #define G_PV(x) (((x) >> S_PV) & M_PV)
23944 #define V_MAC(x) ((x) << S_MAC)
23945 #define G_MAC(x) (((x) >> S_MAC) & M_MAC)
23947 #define A_MPS_STAT_PERR_INT_CAUSE_RX_FIFO 0x962c
23948 #define A_MPS_STAT_PERR_ENABLE_RX_FIFO 0x9630
23949 #define A_MPS_STAT_PERR_INJECT 0x9634
23951 #define S_STATMEMSEL 1
23952 #define M_STATMEMSEL 0x7fU
23953 #define V_STATMEMSEL(x) ((x) << S_STATMEMSEL)
23954 #define G_STATMEMSEL(x) (((x) >> S_STATMEMSEL) & M_STATMEMSEL)
23956 #define A_MPS_STAT_DEBUG_SUB_SEL 0x9638
23958 #define S_STATSSUBPRTH 5
23959 #define M_STATSSUBPRTH 0x1fU
23960 #define V_STATSSUBPRTH(x) ((x) << S_STATSSUBPRTH)
23961 #define G_STATSSUBPRTH(x) (((x) >> S_STATSSUBPRTH) & M_STATSSUBPRTH)
23963 #define S_STATSSUBPRTL 0
23964 #define M_STATSSUBPRTL 0x1fU
23965 #define V_STATSSUBPRTL(x) ((x) << S_STATSSUBPRTL)
23966 #define G_STATSSUBPRTL(x) (((x) >> S_STATSSUBPRTL) & M_STATSSUBPRTL)
23968 #define S_STATSUBPRTH 5
23969 #define M_STATSUBPRTH 0x1fU
23970 #define V_STATSUBPRTH(x) ((x) << S_STATSUBPRTH)
23971 #define G_STATSUBPRTH(x) (((x) >> S_STATSUBPRTH) & M_STATSUBPRTH)
23973 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L 0x9640
23974 #define A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_H 0x9644
23975 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_L 0x9648
23976 #define A_MPS_STAT_RX_BG_1_MAC_DROP_FRAME_H 0x964c
23977 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_L 0x9650
23978 #define A_MPS_STAT_RX_BG_2_MAC_DROP_FRAME_H 0x9654
23979 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_L 0x9658
23980 #define A_MPS_STAT_RX_BG_3_MAC_DROP_FRAME_H 0x965c
23981 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L 0x9660
23982 #define A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_H 0x9664
23983 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_L 0x9668
23984 #define A_MPS_STAT_RX_BG_1_LB_DROP_FRAME_H 0x966c
23985 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_L 0x9670
23986 #define A_MPS_STAT_RX_BG_2_LB_DROP_FRAME_H 0x9674
23987 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_L 0x9678
23988 #define A_MPS_STAT_RX_BG_3_LB_DROP_FRAME_H 0x967c
23989 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L 0x9680
23990 #define A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_H 0x9684
23991 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_L 0x9688
23992 #define A_MPS_STAT_RX_BG_1_MAC_TRUNC_FRAME_H 0x968c
23993 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_L 0x9690
23994 #define A_MPS_STAT_RX_BG_2_MAC_TRUNC_FRAME_H 0x9694
23995 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_L 0x9698
23996 #define A_MPS_STAT_RX_BG_3_MAC_TRUNC_FRAME_H 0x969c
23997 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L 0x96a0
23998 #define A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_H 0x96a4
23999 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_L 0x96a8
24000 #define A_MPS_STAT_RX_BG_1_LB_TRUNC_FRAME_H 0x96ac
24001 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_L 0x96b0
24002 #define A_MPS_STAT_RX_BG_2_LB_TRUNC_FRAME_H 0x96b4
24003 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_L 0x96b8
24004 #define A_MPS_STAT_RX_BG_3_LB_TRUNC_FRAME_H 0x96bc
24005 #define A_MPS_STAT_PERR_INT_ENABLE_SRAM1 0x96c0
24007 #define S_T5_RXVF 5
24008 #define M_T5_RXVF 0x7U
24009 #define V_T5_RXVF(x) ((x) << S_T5_RXVF)
24010 #define G_T5_RXVF(x) (((x) >> S_T5_RXVF) & M_T5_RXVF)
24012 #define S_T5_TXVF 0
24013 #define M_T5_TXVF 0x1fU
24014 #define V_T5_TXVF(x) ((x) << S_T5_TXVF)
24015 #define G_T5_TXVF(x) (((x) >> S_T5_TXVF) & M_T5_TXVF)
24017 #define A_MPS_STAT_PERR_INT_CAUSE_SRAM1 0x96c4
24018 #define A_MPS_STAT_PERR_ENABLE_SRAM1 0x96c8
24019 #define A_MPS_STAT_STOP_UPD_BG 0x96cc
24022 #define M_BGRX 0xfU
24023 #define V_BGRX(x) ((x) << S_BGRX)
24024 #define G_BGRX(x) (((x) >> S_BGRX) & M_BGRX)
24026 #define A_MPS_STAT_STOP_UPD_PORT 0x96d0
24029 #define M_PTLPBK 0xfU
24030 #define V_PTLPBK(x) ((x) << S_PTLPBK)
24031 #define G_PTLPBK(x) (((x) >> S_PTLPBK) & M_PTLPBK)
24034 #define M_PTTX 0xfU
24035 #define V_PTTX(x) ((x) << S_PTTX)
24036 #define G_PTTX(x) (((x) >> S_PTTX) & M_PTTX)
24039 #define M_PTRX 0xfU
24040 #define V_PTRX(x) ((x) << S_PTRX)
24041 #define G_PTRX(x) (((x) >> S_PTRX) & M_PTRX)
24043 #define A_MPS_STAT_STOP_UPD_PF 0x96d4
24046 #define M_PFTX 0xffU
24047 #define V_PFTX(x) ((x) << S_PFTX)
24048 #define G_PFTX(x) (((x) >> S_PFTX) & M_PFTX)
24051 #define M_PFRX 0xffU
24052 #define V_PFRX(x) ((x) << S_PFRX)
24053 #define G_PFRX(x) (((x) >> S_PFRX) & M_PFRX)
24055 #define A_MPS_STAT_STOP_UPD_TX_VF_0_31 0x96d8
24056 #define A_MPS_STAT_STOP_UPD_TX_VF_32_63 0x96dc
24057 #define A_MPS_STAT_STOP_UPD_TX_VF_64_95 0x96e0
24058 #define A_MPS_STAT_STOP_UPD_TX_VF_96_127 0x96e4
24059 #define A_MPS_STAT_STOP_UPD_RX_VF_0_31 0x96e8
24060 #define A_MPS_STAT_STOP_UPD_RX_VF_32_63 0x96ec
24061 #define A_MPS_STAT_STOP_UPD_RX_VF_64_95 0x96f0
24062 #define A_MPS_STAT_STOP_UPD_RX_VF_96_127 0x96f4
24063 #define A_MPS_TRC_CFG 0x9800
24065 #define S_TRCFIFOEMPTY 4
24066 #define V_TRCFIFOEMPTY(x) ((x) << S_TRCFIFOEMPTY)
24067 #define F_TRCFIFOEMPTY V_TRCFIFOEMPTY(1U)
24069 #define S_TRCIGNOREDROPINPUT 3
24070 #define V_TRCIGNOREDROPINPUT(x) ((x) << S_TRCIGNOREDROPINPUT)
24071 #define F_TRCIGNOREDROPINPUT V_TRCIGNOREDROPINPUT(1U)
24073 #define S_TRCKEEPDUPLICATES 2
24074 #define V_TRCKEEPDUPLICATES(x) ((x) << S_TRCKEEPDUPLICATES)
24075 #define F_TRCKEEPDUPLICATES V_TRCKEEPDUPLICATES(1U)
24078 #define V_TRCEN(x) ((x) << S_TRCEN)
24079 #define F_TRCEN V_TRCEN(1U)
24081 #define S_TRCMULTIFILTER 0
24082 #define V_TRCMULTIFILTER(x) ((x) << S_TRCMULTIFILTER)
24083 #define F_TRCMULTIFILTER V_TRCMULTIFILTER(1U)
24085 #define S_TRCMULTIRSSFILTER 5
24086 #define V_TRCMULTIRSSFILTER(x) ((x) << S_TRCMULTIRSSFILTER)
24087 #define F_TRCMULTIRSSFILTER V_TRCMULTIRSSFILTER(1U)
24089 #define A_MPS_TRC_RSS_HASH 0x9804
24090 #define A_MPS_TRC_FILTER0_RSS_HASH 0x9804
24091 #define A_MPS_TRC_RSS_CONTROL 0x9808
24093 #define S_RSSCONTROL 16
24094 #define M_RSSCONTROL 0xffU
24095 #define V_RSSCONTROL(x) ((x) << S_RSSCONTROL)
24096 #define G_RSSCONTROL(x) (((x) >> S_RSSCONTROL) & M_RSSCONTROL)
24098 #define S_QUEUENUMBER 0
24099 #define M_QUEUENUMBER 0xffffU
24100 #define V_QUEUENUMBER(x) ((x) << S_QUEUENUMBER)
24101 #define G_QUEUENUMBER(x) (((x) >> S_QUEUENUMBER) & M_QUEUENUMBER)
24103 #define A_MPS_TRC_FILTER0_RSS_CONTROL 0x9808
24104 #define A_MPS_TRC_FILTER_MATCH_CTL_A 0x9810
24106 #define S_TFINVERTMATCH 24
24107 #define V_TFINVERTMATCH(x) ((x) << S_TFINVERTMATCH)
24108 #define F_TFINVERTMATCH V_TFINVERTMATCH(1U)
24110 #define S_TFPKTTOOLARGE 23
24111 #define V_TFPKTTOOLARGE(x) ((x) << S_TFPKTTOOLARGE)
24112 #define F_TFPKTTOOLARGE V_TFPKTTOOLARGE(1U)
24115 #define V_TFEN(x) ((x) << S_TFEN)
24116 #define F_TFEN V_TFEN(1U)
24118 #define S_TFPORT 18
24119 #define M_TFPORT 0xfU
24120 #define V_TFPORT(x) ((x) << S_TFPORT)
24121 #define G_TFPORT(x) (((x) >> S_TFPORT) & M_TFPORT)
24123 #define S_TFDROP 17
24124 #define V_TFDROP(x) ((x) << S_TFDROP)
24125 #define F_TFDROP V_TFDROP(1U)
24127 #define S_TFSOPEOPERR 16
24128 #define V_TFSOPEOPERR(x) ((x) << S_TFSOPEOPERR)
24129 #define F_TFSOPEOPERR V_TFSOPEOPERR(1U)
24131 #define S_TFLENGTH 8
24132 #define M_TFLENGTH 0x1fU
24133 #define V_TFLENGTH(x) ((x) << S_TFLENGTH)
24134 #define G_TFLENGTH(x) (((x) >> S_TFLENGTH) & M_TFLENGTH)
24136 #define S_TFOFFSET 0
24137 #define M_TFOFFSET 0x1fU
24138 #define V_TFOFFSET(x) ((x) << S_TFOFFSET)
24139 #define G_TFOFFSET(x) (((x) >> S_TFOFFSET) & M_TFOFFSET)
24141 #define S_TFINSERTACTLEN 27
24142 #define V_TFINSERTACTLEN(x) ((x) << S_TFINSERTACTLEN)
24143 #define F_TFINSERTACTLEN V_TFINSERTACTLEN(1U)
24145 #define S_TFINSERTTIMER 26
24146 #define V_TFINSERTTIMER(x) ((x) << S_TFINSERTTIMER)
24147 #define F_TFINSERTTIMER V_TFINSERTTIMER(1U)
24149 #define S_T5_TFINVERTMATCH 25
24150 #define V_T5_TFINVERTMATCH(x) ((x) << S_T5_TFINVERTMATCH)
24151 #define F_T5_TFINVERTMATCH V_T5_TFINVERTMATCH(1U)
24153 #define S_T5_TFPKTTOOLARGE 24
24154 #define V_T5_TFPKTTOOLARGE(x) ((x) << S_T5_TFPKTTOOLARGE)
24155 #define F_T5_TFPKTTOOLARGE V_T5_TFPKTTOOLARGE(1U)
24157 #define S_T5_TFEN 23
24158 #define V_T5_TFEN(x) ((x) << S_T5_TFEN)
24159 #define F_T5_TFEN V_T5_TFEN(1U)
24161 #define S_T5_TFPORT 18
24162 #define M_T5_TFPORT 0x1fU
24163 #define V_T5_TFPORT(x) ((x) << S_T5_TFPORT)
24164 #define G_T5_TFPORT(x) (((x) >> S_T5_TFPORT) & M_T5_TFPORT)
24166 #define A_MPS_TRC_FILTER_MATCH_CTL_B 0x9820
24168 #define S_TFMINPKTSIZE 16
24169 #define M_TFMINPKTSIZE 0x1ffU
24170 #define V_TFMINPKTSIZE(x) ((x) << S_TFMINPKTSIZE)
24171 #define G_TFMINPKTSIZE(x) (((x) >> S_TFMINPKTSIZE) & M_TFMINPKTSIZE)
24173 #define S_TFCAPTUREMAX 0
24174 #define M_TFCAPTUREMAX 0x3fffU
24175 #define V_TFCAPTUREMAX(x) ((x) << S_TFCAPTUREMAX)
24176 #define G_TFCAPTUREMAX(x) (((x) >> S_TFCAPTUREMAX) & M_TFCAPTUREMAX)
24178 #define A_MPS_TRC_FILTER_RUNT_CTL 0x9830
24180 #define S_TFRUNTSIZE 0
24181 #define M_TFRUNTSIZE 0x3fU
24182 #define V_TFRUNTSIZE(x) ((x) << S_TFRUNTSIZE)
24183 #define G_TFRUNTSIZE(x) (((x) >> S_TFRUNTSIZE) & M_TFRUNTSIZE)
24185 #define A_MPS_TRC_FILTER_DROP 0x9840
24187 #define S_TFDROPINPCOUNT 16
24188 #define M_TFDROPINPCOUNT 0xffffU
24189 #define V_TFDROPINPCOUNT(x) ((x) << S_TFDROPINPCOUNT)
24190 #define G_TFDROPINPCOUNT(x) (((x) >> S_TFDROPINPCOUNT) & M_TFDROPINPCOUNT)
24192 #define S_TFDROPBUFFERCOUNT 0
24193 #define M_TFDROPBUFFERCOUNT 0xffffU
24194 #define V_TFDROPBUFFERCOUNT(x) ((x) << S_TFDROPBUFFERCOUNT)
24195 #define G_TFDROPBUFFERCOUNT(x) (((x) >> S_TFDROPBUFFERCOUNT) & M_TFDROPBUFFERCOUNT)
24197 #define A_MPS_TRC_PERR_INJECT 0x9850
24199 #define S_TRCMEMSEL 1
24200 #define M_TRCMEMSEL 0xfU
24201 #define V_TRCMEMSEL(x) ((x) << S_TRCMEMSEL)
24202 #define G_TRCMEMSEL(x) (((x) >> S_TRCMEMSEL) & M_TRCMEMSEL)
24204 #define A_MPS_TRC_PERR_ENABLE 0x9854
24206 #define S_MISCPERR 8
24207 #define V_MISCPERR(x) ((x) << S_MISCPERR)
24208 #define F_MISCPERR V_MISCPERR(1U)
24210 #define S_PKTFIFO 4
24211 #define M_PKTFIFO 0xfU
24212 #define V_PKTFIFO(x) ((x) << S_PKTFIFO)
24213 #define G_PKTFIFO(x) (((x) >> S_PKTFIFO) & M_PKTFIFO)
24215 #define S_FILTMEM 0
24216 #define M_FILTMEM 0xfU
24217 #define V_FILTMEM(x) ((x) << S_FILTMEM)
24218 #define G_FILTMEM(x) (((x) >> S_FILTMEM) & M_FILTMEM)
24220 #define A_MPS_TRC_INT_ENABLE 0x9858
24222 #define S_TRCPLERRENB 9
24223 #define V_TRCPLERRENB(x) ((x) << S_TRCPLERRENB)
24224 #define F_TRCPLERRENB V_TRCPLERRENB(1U)
24226 #define A_MPS_TRC_INT_CAUSE 0x985c
24227 #define A_MPS_TRC_TIMESTAMP_L 0x9860
24228 #define A_MPS_TRC_TIMESTAMP_H 0x9864
24229 #define A_MPS_TRC_FILTER0_MATCH 0x9c00
24230 #define A_MPS_TRC_FILTER0_DONT_CARE 0x9c80
24231 #define A_MPS_TRC_FILTER1_MATCH 0x9d00
24232 #define A_MPS_TRC_FILTER1_DONT_CARE 0x9d80
24233 #define A_MPS_TRC_FILTER2_MATCH 0x9e00
24234 #define A_MPS_TRC_FILTER2_DONT_CARE 0x9e80
24235 #define A_MPS_TRC_FILTER3_MATCH 0x9f00
24236 #define A_MPS_TRC_FILTER3_DONT_CARE 0x9f80
24237 #define A_MPS_TRC_FILTER1_RSS_HASH 0x9ff0
24238 #define A_MPS_TRC_FILTER1_RSS_CONTROL 0x9ff4
24239 #define A_MPS_TRC_FILTER2_RSS_HASH 0x9ff8
24240 #define A_MPS_TRC_FILTER2_RSS_CONTROL 0x9ffc
24241 #define A_MPS_TRC_FILTER3_RSS_HASH 0xa000
24242 #define A_MPS_TRC_FILTER3_RSS_CONTROL 0xa004
24243 #define A_MPS_T5_TRC_RSS_HASH 0xa008
24244 #define A_MPS_T5_TRC_RSS_CONTROL 0xa00c
24245 #define A_MPS_TRC_VF_OFF_FILTER_0 0xa010
24247 #define S_TRCMPS2TP_MACONLY 20
24248 #define V_TRCMPS2TP_MACONLY(x) ((x) << S_TRCMPS2TP_MACONLY)
24249 #define F_TRCMPS2TP_MACONLY V_TRCMPS2TP_MACONLY(1U)
24251 #define S_TRCALLMPS2TP 19
24252 #define V_TRCALLMPS2TP(x) ((x) << S_TRCALLMPS2TP)
24253 #define F_TRCALLMPS2TP V_TRCALLMPS2TP(1U)
24255 #define S_TRCALLTP2MPS 18
24256 #define V_TRCALLTP2MPS(x) ((x) << S_TRCALLTP2MPS)
24257 #define F_TRCALLTP2MPS V_TRCALLTP2MPS(1U)
24259 #define S_TRCALLVF 17
24260 #define V_TRCALLVF(x) ((x) << S_TRCALLVF)
24261 #define F_TRCALLVF V_TRCALLVF(1U)
24263 #define S_TRC_OFLD_EN 16
24264 #define V_TRC_OFLD_EN(x) ((x) << S_TRC_OFLD_EN)
24265 #define F_TRC_OFLD_EN V_TRC_OFLD_EN(1U)
24267 #define S_VFFILTEN 15
24268 #define V_VFFILTEN(x) ((x) << S_VFFILTEN)
24269 #define F_VFFILTEN V_VFFILTEN(1U)
24271 #define S_VFFILTMASK 8
24272 #define M_VFFILTMASK 0x7fU
24273 #define V_VFFILTMASK(x) ((x) << S_VFFILTMASK)
24274 #define G_VFFILTMASK(x) (((x) >> S_VFFILTMASK) & M_VFFILTMASK)
24276 #define S_VFFILTVALID 7
24277 #define V_VFFILTVALID(x) ((x) << S_VFFILTVALID)
24278 #define F_VFFILTVALID V_VFFILTVALID(1U)
24280 #define S_VFFILTDATA 0
24281 #define M_VFFILTDATA 0x7fU
24282 #define V_VFFILTDATA(x) ((x) << S_VFFILTDATA)
24283 #define G_VFFILTDATA(x) (((x) >> S_VFFILTDATA) & M_VFFILTDATA)
24285 #define A_MPS_TRC_VF_OFF_FILTER_1 0xa014
24286 #define A_MPS_TRC_VF_OFF_FILTER_2 0xa018
24287 #define A_MPS_TRC_VF_OFF_FILTER_3 0xa01c
24288 #define A_MPS_TRC_CGEN 0xa020
24290 #define S_MPSTRCCGEN 0
24291 #define M_MPSTRCCGEN 0xfU
24292 #define V_MPSTRCCGEN(x) ((x) << S_MPSTRCCGEN)
24293 #define G_MPSTRCCGEN(x) (((x) >> S_MPSTRCCGEN) & M_MPSTRCCGEN)
24295 #define A_MPS_CLS_CTL 0xd000
24297 #define S_MEMWRITEFAULT 4
24298 #define V_MEMWRITEFAULT(x) ((x) << S_MEMWRITEFAULT)
24299 #define F_MEMWRITEFAULT V_MEMWRITEFAULT(1U)
24301 #define S_MEMWRITEWAITING 3
24302 #define V_MEMWRITEWAITING(x) ((x) << S_MEMWRITEWAITING)
24303 #define F_MEMWRITEWAITING V_MEMWRITEWAITING(1U)
24305 #define S_CIMNOPROMISCUOUS 2
24306 #define V_CIMNOPROMISCUOUS(x) ((x) << S_CIMNOPROMISCUOUS)
24307 #define F_CIMNOPROMISCUOUS V_CIMNOPROMISCUOUS(1U)
24309 #define S_HYPERVISORONLY 1
24310 #define V_HYPERVISORONLY(x) ((x) << S_HYPERVISORONLY)
24311 #define F_HYPERVISORONLY V_HYPERVISORONLY(1U)
24313 #define S_VLANCLSEN 0
24314 #define V_VLANCLSEN(x) ((x) << S_VLANCLSEN)
24315 #define F_VLANCLSEN V_VLANCLSEN(1U)
24317 #define A_MPS_CLS_ARB_WEIGHT 0xd004
24319 #define S_PLWEIGHT 16
24320 #define M_PLWEIGHT 0x1fU
24321 #define V_PLWEIGHT(x) ((x) << S_PLWEIGHT)
24322 #define G_PLWEIGHT(x) (((x) >> S_PLWEIGHT) & M_PLWEIGHT)
24324 #define S_CIMWEIGHT 8
24325 #define M_CIMWEIGHT 0x1fU
24326 #define V_CIMWEIGHT(x) ((x) << S_CIMWEIGHT)
24327 #define G_CIMWEIGHT(x) (((x) >> S_CIMWEIGHT) & M_CIMWEIGHT)
24329 #define S_LPBKWEIGHT 0
24330 #define M_LPBKWEIGHT 0x1fU
24331 #define V_LPBKWEIGHT(x) ((x) << S_LPBKWEIGHT)
24332 #define G_LPBKWEIGHT(x) (((x) >> S_LPBKWEIGHT) & M_LPBKWEIGHT)
24334 #define A_MPS_CLS_BMC_MAC_ADDR_L 0xd010
24335 #define A_MPS_CLS_BMC_MAC_ADDR_H 0xd014
24336 #define A_MPS_CLS_BMC_VLAN 0xd018
24337 #define A_MPS_CLS_PERR_INJECT 0xd01c
24339 #define S_CLS_MEMSEL 1
24340 #define M_CLS_MEMSEL 0x3U
24341 #define V_CLS_MEMSEL(x) ((x) << S_CLS_MEMSEL)
24342 #define G_CLS_MEMSEL(x) (((x) >> S_CLS_MEMSEL) & M_CLS_MEMSEL)
24344 #define A_MPS_CLS_PERR_ENABLE 0xd020
24346 #define S_HASHSRAM 2
24347 #define V_HASHSRAM(x) ((x) << S_HASHSRAM)
24348 #define F_HASHSRAM V_HASHSRAM(1U)
24350 #define S_MATCHTCAM 1
24351 #define V_MATCHTCAM(x) ((x) << S_MATCHTCAM)
24352 #define F_MATCHTCAM V_MATCHTCAM(1U)
24354 #define S_MATCHSRAM 0
24355 #define V_MATCHSRAM(x) ((x) << S_MATCHSRAM)
24356 #define F_MATCHSRAM V_MATCHSRAM(1U)
24358 #define A_MPS_CLS_INT_ENABLE 0xd024
24360 #define S_PLERRENB 3
24361 #define V_PLERRENB(x) ((x) << S_PLERRENB)
24362 #define F_PLERRENB V_PLERRENB(1U)
24364 #define A_MPS_CLS_INT_CAUSE 0xd028
24365 #define A_MPS_CLS_PL_TEST_DATA_L 0xd02c
24366 #define A_MPS_CLS_PL_TEST_DATA_H 0xd030
24367 #define A_MPS_CLS_PL_TEST_RES_DATA 0xd034
24369 #define S_CLS_PRIORITY 24
24370 #define M_CLS_PRIORITY 0x7U
24371 #define V_CLS_PRIORITY(x) ((x) << S_CLS_PRIORITY)
24372 #define G_CLS_PRIORITY(x) (((x) >> S_CLS_PRIORITY) & M_CLS_PRIORITY)
24374 #define S_CLS_REPLICATE 23
24375 #define V_CLS_REPLICATE(x) ((x) << S_CLS_REPLICATE)
24376 #define F_CLS_REPLICATE V_CLS_REPLICATE(1U)
24378 #define S_CLS_INDEX 14
24379 #define M_CLS_INDEX 0x1ffU
24380 #define V_CLS_INDEX(x) ((x) << S_CLS_INDEX)
24381 #define G_CLS_INDEX(x) (((x) >> S_CLS_INDEX) & M_CLS_INDEX)
24384 #define M_CLS_VF 0x7fU
24385 #define V_CLS_VF(x) ((x) << S_CLS_VF)
24386 #define G_CLS_VF(x) (((x) >> S_CLS_VF) & M_CLS_VF)
24388 #define S_CLS_VF_VLD 6
24389 #define V_CLS_VF_VLD(x) ((x) << S_CLS_VF_VLD)
24390 #define F_CLS_VF_VLD V_CLS_VF_VLD(1U)
24393 #define M_CLS_PF 0x7U
24394 #define V_CLS_PF(x) ((x) << S_CLS_PF)
24395 #define G_CLS_PF(x) (((x) >> S_CLS_PF) & M_CLS_PF)
24397 #define S_CLS_MATCH 0
24398 #define M_CLS_MATCH 0x7U
24399 #define V_CLS_MATCH(x) ((x) << S_CLS_MATCH)
24400 #define G_CLS_MATCH(x) (((x) >> S_CLS_MATCH) & M_CLS_MATCH)
24402 #define A_MPS_CLS_PL_TEST_CTL 0xd038
24404 #define S_PLTESTCTL 0
24405 #define V_PLTESTCTL(x) ((x) << S_PLTESTCTL)
24406 #define F_PLTESTCTL V_PLTESTCTL(1U)
24408 #define A_MPS_CLS_PORT_BMC_CTL 0xd03c
24410 #define S_PRTBMCCTL 0
24411 #define V_PRTBMCCTL(x) ((x) << S_PRTBMCCTL)
24412 #define F_PRTBMCCTL V_PRTBMCCTL(1U)
24414 #define A_MPS_CLS_VLAN_TABLE 0xdfc0
24416 #define S_VLAN_MASK 16
24417 #define M_VLAN_MASK 0xfffU
24418 #define V_VLAN_MASK(x) ((x) << S_VLAN_MASK)
24419 #define G_VLAN_MASK(x) (((x) >> S_VLAN_MASK) & M_VLAN_MASK)
24421 #define S_VLANPF 13
24422 #define M_VLANPF 0x7U
24423 #define V_VLANPF(x) ((x) << S_VLANPF)
24424 #define G_VLANPF(x) (((x) >> S_VLANPF) & M_VLANPF)
24426 #define S_VLAN_VALID 12
24427 #define V_VLAN_VALID(x) ((x) << S_VLAN_VALID)
24428 #define F_VLAN_VALID V_VLAN_VALID(1U)
24430 #define A_MPS_CLS_SRAM_L 0xe000
24432 #define S_MULTILISTEN3 28
24433 #define V_MULTILISTEN3(x) ((x) << S_MULTILISTEN3)
24434 #define F_MULTILISTEN3 V_MULTILISTEN3(1U)
24436 #define S_MULTILISTEN2 27
24437 #define V_MULTILISTEN2(x) ((x) << S_MULTILISTEN2)
24438 #define F_MULTILISTEN2 V_MULTILISTEN2(1U)
24440 #define S_MULTILISTEN1 26
24441 #define V_MULTILISTEN1(x) ((x) << S_MULTILISTEN1)
24442 #define F_MULTILISTEN1 V_MULTILISTEN1(1U)
24444 #define S_MULTILISTEN0 25
24445 #define V_MULTILISTEN0(x) ((x) << S_MULTILISTEN0)
24446 #define F_MULTILISTEN0 V_MULTILISTEN0(1U)
24448 #define S_SRAM_PRIO3 22
24449 #define M_SRAM_PRIO3 0x7U
24450 #define V_SRAM_PRIO3(x) ((x) << S_SRAM_PRIO3)
24451 #define G_SRAM_PRIO3(x) (((x) >> S_SRAM_PRIO3) & M_SRAM_PRIO3)
24453 #define S_SRAM_PRIO2 19
24454 #define M_SRAM_PRIO2 0x7U
24455 #define V_SRAM_PRIO2(x) ((x) << S_SRAM_PRIO2)
24456 #define G_SRAM_PRIO2(x) (((x) >> S_SRAM_PRIO2) & M_SRAM_PRIO2)
24458 #define S_SRAM_PRIO1 16
24459 #define M_SRAM_PRIO1 0x7U
24460 #define V_SRAM_PRIO1(x) ((x) << S_SRAM_PRIO1)
24461 #define G_SRAM_PRIO1(x) (((x) >> S_SRAM_PRIO1) & M_SRAM_PRIO1)
24463 #define S_SRAM_PRIO0 13
24464 #define M_SRAM_PRIO0 0x7U
24465 #define V_SRAM_PRIO0(x) ((x) << S_SRAM_PRIO0)
24466 #define G_SRAM_PRIO0(x) (((x) >> S_SRAM_PRIO0) & M_SRAM_PRIO0)
24468 #define S_SRAM_VLD 12
24469 #define V_SRAM_VLD(x) ((x) << S_SRAM_VLD)
24470 #define F_SRAM_VLD V_SRAM_VLD(1U)
24472 #define A_MPS_T5_CLS_SRAM_L 0xe000
24473 #define A_MPS_CLS_SRAM_H 0xe004
24475 #define S_MACPARITY1 9
24476 #define V_MACPARITY1(x) ((x) << S_MACPARITY1)
24477 #define F_MACPARITY1 V_MACPARITY1(1U)
24479 #define S_MACPARITY0 8
24480 #define V_MACPARITY0(x) ((x) << S_MACPARITY0)
24481 #define F_MACPARITY0 V_MACPARITY0(1U)
24483 #define S_MACPARITYMASKSIZE 4
24484 #define M_MACPARITYMASKSIZE 0xfU
24485 #define V_MACPARITYMASKSIZE(x) ((x) << S_MACPARITYMASKSIZE)
24486 #define G_MACPARITYMASKSIZE(x) (((x) >> S_MACPARITYMASKSIZE) & M_MACPARITYMASKSIZE)
24488 #define S_PORTMAP 0
24489 #define M_PORTMAP 0xfU
24490 #define V_PORTMAP(x) ((x) << S_PORTMAP)
24491 #define G_PORTMAP(x) (((x) >> S_PORTMAP) & M_PORTMAP)
24493 #define A_MPS_T5_CLS_SRAM_H 0xe004
24494 #define A_MPS_CLS_TCAM_Y_L 0xf000
24495 #define A_MPS_CLS_TCAM_Y_H 0xf004
24498 #define M_TCAMYH 0xffffU
24499 #define V_TCAMYH(x) ((x) << S_TCAMYH)
24500 #define G_TCAMYH(x) (((x) >> S_TCAMYH) & M_TCAMYH)
24502 #define A_MPS_CLS_TCAM_X_L 0xf008
24503 #define A_MPS_CLS_TCAM_X_H 0xf00c
24506 #define M_TCAMXH 0xffffU
24507 #define V_TCAMXH(x) ((x) << S_TCAMXH)
24508 #define G_TCAMXH(x) (((x) >> S_TCAMXH) & M_TCAMXH)
24510 #define A_MPS_RX_CTL 0x11000
24512 #define S_FILT_VLAN_SEL 17
24513 #define V_FILT_VLAN_SEL(x) ((x) << S_FILT_VLAN_SEL)
24514 #define F_FILT_VLAN_SEL V_FILT_VLAN_SEL(1U)
24516 #define S_CBA_EN 16
24517 #define V_CBA_EN(x) ((x) << S_CBA_EN)
24518 #define F_CBA_EN V_CBA_EN(1U)
24520 #define S_BLK_SNDR 12
24521 #define M_BLK_SNDR 0xfU
24522 #define V_BLK_SNDR(x) ((x) << S_BLK_SNDR)
24523 #define G_BLK_SNDR(x) (((x) >> S_BLK_SNDR) & M_BLK_SNDR)
24526 #define M_CMPRS 0xfU
24527 #define V_CMPRS(x) ((x) << S_CMPRS)
24528 #define G_CMPRS(x) (((x) >> S_CMPRS) & M_CMPRS)
24531 #define M_SNF 0xffU
24532 #define V_SNF(x) ((x) << S_SNF)
24533 #define G_SNF(x) (((x) >> S_SNF) & M_SNF)
24535 #define A_MPS_RX_PORT_MUX_CTL 0x11004
24537 #define S_CTL_P3 12
24538 #define M_CTL_P3 0xfU
24539 #define V_CTL_P3(x) ((x) << S_CTL_P3)
24540 #define G_CTL_P3(x) (((x) >> S_CTL_P3) & M_CTL_P3)
24543 #define M_CTL_P2 0xfU
24544 #define V_CTL_P2(x) ((x) << S_CTL_P2)
24545 #define G_CTL_P2(x) (((x) >> S_CTL_P2) & M_CTL_P2)
24548 #define M_CTL_P1 0xfU
24549 #define V_CTL_P1(x) ((x) << S_CTL_P1)
24550 #define G_CTL_P1(x) (((x) >> S_CTL_P1) & M_CTL_P1)
24553 #define M_CTL_P0 0xfU
24554 #define V_CTL_P0(x) ((x) << S_CTL_P0)
24555 #define G_CTL_P0(x) (((x) >> S_CTL_P0) & M_CTL_P0)
24557 #define A_MPS_RX_PG_FL 0x11008
24560 #define V_RST(x) ((x) << S_RST)
24561 #define F_RST V_RST(1U)
24564 #define M_CNT 0xffffU
24565 #define V_CNT(x) ((x) << S_CNT)
24566 #define G_CNT(x) (((x) >> S_CNT) & M_CNT)
24568 #define A_MPS_RX_PKT_FL 0x1100c
24569 #define A_MPS_RX_PG_RSV0 0x11010
24571 #define S_CLR_INTR 31
24572 #define V_CLR_INTR(x) ((x) << S_CLR_INTR)
24573 #define F_CLR_INTR V_CLR_INTR(1U)
24575 #define S_SET_INTR 30
24576 #define V_SET_INTR(x) ((x) << S_SET_INTR)
24577 #define F_SET_INTR V_SET_INTR(1U)
24580 #define M_USED 0x7ffU
24581 #define V_USED(x) ((x) << S_USED)
24582 #define G_USED(x) (((x) >> S_USED) & M_USED)
24585 #define M_ALLOC 0x7ffU
24586 #define V_ALLOC(x) ((x) << S_ALLOC)
24587 #define G_ALLOC(x) (((x) >> S_ALLOC) & M_ALLOC)
24589 #define S_T5_USED 16
24590 #define M_T5_USED 0xfffU
24591 #define V_T5_USED(x) ((x) << S_T5_USED)
24592 #define G_T5_USED(x) (((x) >> S_T5_USED) & M_T5_USED)
24594 #define S_T5_ALLOC 0
24595 #define M_T5_ALLOC 0xfffU
24596 #define V_T5_ALLOC(x) ((x) << S_T5_ALLOC)
24597 #define G_T5_ALLOC(x) (((x) >> S_T5_ALLOC) & M_T5_ALLOC)
24599 #define A_MPS_RX_PG_RSV1 0x11014
24600 #define A_MPS_RX_PG_RSV2 0x11018
24601 #define A_MPS_RX_PG_RSV3 0x1101c
24602 #define A_MPS_RX_PG_RSV4 0x11020
24603 #define A_MPS_RX_PG_RSV5 0x11024
24604 #define A_MPS_RX_PG_RSV6 0x11028
24605 #define A_MPS_RX_PG_RSV7 0x1102c
24606 #define A_MPS_RX_PG_SHR_BG0 0x11030
24609 #define V_EN(x) ((x) << S_EN)
24610 #define F_EN V_EN(1U)
24613 #define V_SEL(x) ((x) << S_SEL)
24614 #define F_SEL V_SEL(1U)
24617 #define M_MAX 0x7ffU
24618 #define V_MAX(x) ((x) << S_MAX)
24619 #define G_MAX(x) (((x) >> S_MAX) & M_MAX)
24622 #define M_BORW 0x7ffU
24623 #define V_BORW(x) ((x) << S_BORW)
24624 #define G_BORW(x) (((x) >> S_BORW) & M_BORW)
24626 #define S_T5_MAX 16
24627 #define M_T5_MAX 0xfffU
24628 #define V_T5_MAX(x) ((x) << S_T5_MAX)
24629 #define G_T5_MAX(x) (((x) >> S_T5_MAX) & M_T5_MAX)
24631 #define S_T5_BORW 0
24632 #define M_T5_BORW 0xfffU
24633 #define V_T5_BORW(x) ((x) << S_T5_BORW)
24634 #define G_T5_BORW(x) (((x) >> S_T5_BORW) & M_T5_BORW)
24636 #define A_MPS_RX_PG_SHR_BG1 0x11034
24637 #define A_MPS_RX_PG_SHR_BG2 0x11038
24638 #define A_MPS_RX_PG_SHR_BG3 0x1103c
24639 #define A_MPS_RX_PG_SHR0 0x11040
24642 #define M_QUOTA 0x7ffU
24643 #define V_QUOTA(x) ((x) << S_QUOTA)
24644 #define G_QUOTA(x) (((x) >> S_QUOTA) & M_QUOTA)
24646 #define S_SHR_USED 0
24647 #define M_SHR_USED 0x7ffU
24648 #define V_SHR_USED(x) ((x) << S_SHR_USED)
24649 #define G_SHR_USED(x) (((x) >> S_SHR_USED) & M_SHR_USED)
24651 #define S_T5_QUOTA 16
24652 #define M_T5_QUOTA 0xfffU
24653 #define V_T5_QUOTA(x) ((x) << S_T5_QUOTA)
24654 #define G_T5_QUOTA(x) (((x) >> S_T5_QUOTA) & M_T5_QUOTA)
24656 #define S_T5_SHR_USED 0
24657 #define M_T5_SHR_USED 0xfffU
24658 #define V_T5_SHR_USED(x) ((x) << S_T5_SHR_USED)
24659 #define G_T5_SHR_USED(x) (((x) >> S_T5_SHR_USED) & M_T5_SHR_USED)
24661 #define A_MPS_RX_PG_SHR1 0x11044
24662 #define A_MPS_RX_PG_HYST_BG0 0x11048
24665 #define M_TH 0x7ffU
24666 #define V_TH(x) ((x) << S_TH)
24667 #define G_TH(x) (((x) >> S_TH) & M_TH)
24670 #define M_T5_TH 0xfffU
24671 #define V_T5_TH(x) ((x) << S_T5_TH)
24672 #define G_T5_TH(x) (((x) >> S_T5_TH) & M_T5_TH)
24674 #define A_MPS_RX_PG_HYST_BG1 0x1104c
24675 #define A_MPS_RX_PG_HYST_BG2 0x11050
24676 #define A_MPS_RX_PG_HYST_BG3 0x11054
24677 #define A_MPS_RX_OCH_CTL 0x11058
24679 #define S_DROP_WT 27
24680 #define M_DROP_WT 0x1fU
24681 #define V_DROP_WT(x) ((x) << S_DROP_WT)
24682 #define G_DROP_WT(x) (((x) >> S_DROP_WT) & M_DROP_WT)
24684 #define S_TRUNC_WT 22
24685 #define M_TRUNC_WT 0x1fU
24686 #define V_TRUNC_WT(x) ((x) << S_TRUNC_WT)
24687 #define G_TRUNC_WT(x) (((x) >> S_TRUNC_WT) & M_TRUNC_WT)
24689 #define S_OCH_DRAIN 13
24690 #define M_OCH_DRAIN 0x1fU
24691 #define V_OCH_DRAIN(x) ((x) << S_OCH_DRAIN)
24692 #define G_OCH_DRAIN(x) (((x) >> S_OCH_DRAIN) & M_OCH_DRAIN)
24694 #define S_OCH_DROP 8
24695 #define M_OCH_DROP 0x1fU
24696 #define V_OCH_DROP(x) ((x) << S_OCH_DROP)
24697 #define G_OCH_DROP(x) (((x) >> S_OCH_DROP) & M_OCH_DROP)
24700 #define M_STOP 0x1fU
24701 #define V_STOP(x) ((x) << S_STOP)
24702 #define G_STOP(x) (((x) >> S_STOP) & M_STOP)
24704 #define A_MPS_RX_LPBK_BP0 0x1105c
24707 #define M_THRESH 0x7ffU
24708 #define V_THRESH(x) ((x) << S_THRESH)
24709 #define G_THRESH(x) (((x) >> S_THRESH) & M_THRESH)
24711 #define A_MPS_RX_LPBK_BP1 0x11060
24712 #define A_MPS_RX_LPBK_BP2 0x11064
24713 #define A_MPS_RX_LPBK_BP3 0x11068
24714 #define A_MPS_RX_PORT_GAP 0x1106c
24717 #define M_GAP 0xfffffU
24718 #define V_GAP(x) ((x) << S_GAP)
24719 #define G_GAP(x) (((x) >> S_GAP) & M_GAP)
24721 #define A_MPS_RX_CHMN_CNT 0x11070
24722 #define A_MPS_RX_PERR_INT_CAUSE 0x11074
24725 #define V_FF(x) ((x) << S_FF)
24726 #define F_FF V_FF(1U)
24729 #define V_PGMO(x) ((x) << S_PGMO)
24730 #define F_PGMO V_PGMO(1U)
24733 #define V_PGME(x) ((x) << S_PGME)
24734 #define F_PGME V_PGME(1U)
24737 #define V_CHMN(x) ((x) << S_CHMN)
24738 #define F_CHMN V_CHMN(1U)
24741 #define V_RPLC(x) ((x) << S_RPLC)
24742 #define F_RPLC V_RPLC(1U)
24745 #define V_ATRB(x) ((x) << S_ATRB)
24746 #define F_ATRB V_ATRB(1U)
24749 #define V_PSMX(x) ((x) << S_PSMX)
24750 #define F_PSMX V_PSMX(1U)
24753 #define V_PGLL(x) ((x) << S_PGLL)
24754 #define F_PGLL V_PGLL(1U)
24757 #define V_PGFL(x) ((x) << S_PGFL)
24758 #define F_PGFL V_PGFL(1U)
24761 #define V_PKTQ(x) ((x) << S_PKTQ)
24762 #define F_PKTQ V_PKTQ(1U)
24765 #define V_PKFL(x) ((x) << S_PKFL)
24766 #define F_PKFL V_PKFL(1U)
24769 #define V_PPM3(x) ((x) << S_PPM3)
24770 #define F_PPM3 V_PPM3(1U)
24773 #define V_PPM2(x) ((x) << S_PPM2)
24774 #define F_PPM2 V_PPM2(1U)
24777 #define V_PPM1(x) ((x) << S_PPM1)
24778 #define F_PPM1 V_PPM1(1U)
24781 #define V_PPM0(x) ((x) << S_PPM0)
24782 #define F_PPM0 V_PPM0(1U)
24785 #define V_SPMX(x) ((x) << S_SPMX)
24786 #define F_SPMX V_SPMX(1U)
24789 #define V_CDL3(x) ((x) << S_CDL3)
24790 #define F_CDL3 V_CDL3(1U)
24793 #define V_CDL2(x) ((x) << S_CDL2)
24794 #define F_CDL2 V_CDL2(1U)
24797 #define V_CDL1(x) ((x) << S_CDL1)
24798 #define F_CDL1 V_CDL1(1U)
24801 #define V_CDL0(x) ((x) << S_CDL0)
24802 #define F_CDL0 V_CDL0(1U)
24805 #define V_CDM3(x) ((x) << S_CDM3)
24806 #define F_CDM3 V_CDM3(1U)
24809 #define V_CDM2(x) ((x) << S_CDM2)
24810 #define F_CDM2 V_CDM2(1U)
24813 #define V_CDM1(x) ((x) << S_CDM1)
24814 #define F_CDM1 V_CDM1(1U)
24817 #define V_CDM0(x) ((x) << S_CDM0)
24818 #define F_CDM0 V_CDM0(1U)
24820 #define A_MPS_RX_PERR_INT_ENABLE 0x11078
24821 #define A_MPS_RX_PERR_ENABLE 0x1107c
24822 #define A_MPS_RX_PERR_INJECT 0x11080
24823 #define A_MPS_RX_FUNC_INT_CAUSE 0x11084
24825 #define S_INT_ERR_INT 8
24826 #define M_INT_ERR_INT 0x1fU
24827 #define V_INT_ERR_INT(x) ((x) << S_INT_ERR_INT)
24828 #define G_INT_ERR_INT(x) (((x) >> S_INT_ERR_INT) & M_INT_ERR_INT)
24830 #define S_PG_TH_INT7 7
24831 #define V_PG_TH_INT7(x) ((x) << S_PG_TH_INT7)
24832 #define F_PG_TH_INT7 V_PG_TH_INT7(1U)
24834 #define S_PG_TH_INT6 6
24835 #define V_PG_TH_INT6(x) ((x) << S_PG_TH_INT6)
24836 #define F_PG_TH_INT6 V_PG_TH_INT6(1U)
24838 #define S_PG_TH_INT5 5
24839 #define V_PG_TH_INT5(x) ((x) << S_PG_TH_INT5)
24840 #define F_PG_TH_INT5 V_PG_TH_INT5(1U)
24842 #define S_PG_TH_INT4 4
24843 #define V_PG_TH_INT4(x) ((x) << S_PG_TH_INT4)
24844 #define F_PG_TH_INT4 V_PG_TH_INT4(1U)
24846 #define S_PG_TH_INT3 3
24847 #define V_PG_TH_INT3(x) ((x) << S_PG_TH_INT3)
24848 #define F_PG_TH_INT3 V_PG_TH_INT3(1U)
24850 #define S_PG_TH_INT2 2
24851 #define V_PG_TH_INT2(x) ((x) << S_PG_TH_INT2)
24852 #define F_PG_TH_INT2 V_PG_TH_INT2(1U)
24854 #define S_PG_TH_INT1 1
24855 #define V_PG_TH_INT1(x) ((x) << S_PG_TH_INT1)
24856 #define F_PG_TH_INT1 V_PG_TH_INT1(1U)
24858 #define S_PG_TH_INT0 0
24859 #define V_PG_TH_INT0(x) ((x) << S_PG_TH_INT0)
24860 #define F_PG_TH_INT0 V_PG_TH_INT0(1U)
24862 #define S_MTU_ERR_INT3 19
24863 #define V_MTU_ERR_INT3(x) ((x) << S_MTU_ERR_INT3)
24864 #define F_MTU_ERR_INT3 V_MTU_ERR_INT3(1U)
24866 #define S_MTU_ERR_INT2 18
24867 #define V_MTU_ERR_INT2(x) ((x) << S_MTU_ERR_INT2)
24868 #define F_MTU_ERR_INT2 V_MTU_ERR_INT2(1U)
24870 #define S_MTU_ERR_INT1 17
24871 #define V_MTU_ERR_INT1(x) ((x) << S_MTU_ERR_INT1)
24872 #define F_MTU_ERR_INT1 V_MTU_ERR_INT1(1U)
24874 #define S_MTU_ERR_INT0 16
24875 #define V_MTU_ERR_INT0(x) ((x) << S_MTU_ERR_INT0)
24876 #define F_MTU_ERR_INT0 V_MTU_ERR_INT0(1U)
24878 #define S_SE_CNT_ERR_INT 15
24879 #define V_SE_CNT_ERR_INT(x) ((x) << S_SE_CNT_ERR_INT)
24880 #define F_SE_CNT_ERR_INT V_SE_CNT_ERR_INT(1U)
24882 #define S_FRM_ERR_INT 14
24883 #define V_FRM_ERR_INT(x) ((x) << S_FRM_ERR_INT)
24884 #define F_FRM_ERR_INT V_FRM_ERR_INT(1U)
24886 #define S_LEN_ERR_INT 13
24887 #define V_LEN_ERR_INT(x) ((x) << S_LEN_ERR_INT)
24888 #define F_LEN_ERR_INT V_LEN_ERR_INT(1U)
24890 #define A_MPS_RX_FUNC_INT_ENABLE 0x11088
24891 #define A_MPS_RX_PAUSE_GEN_TH_0 0x1108c
24893 #define S_TH_HIGH 16
24894 #define M_TH_HIGH 0xffffU
24895 #define V_TH_HIGH(x) ((x) << S_TH_HIGH)
24896 #define G_TH_HIGH(x) (((x) >> S_TH_HIGH) & M_TH_HIGH)
24899 #define M_TH_LOW 0xffffU
24900 #define V_TH_LOW(x) ((x) << S_TH_LOW)
24901 #define G_TH_LOW(x) (((x) >> S_TH_LOW) & M_TH_LOW)
24903 #define A_MPS_RX_PAUSE_GEN_TH_1 0x11090
24904 #define A_MPS_RX_PAUSE_GEN_TH_2 0x11094
24905 #define A_MPS_RX_PAUSE_GEN_TH_3 0x11098
24906 #define A_MPS_RX_PPP_ATRB 0x1109c
24909 #define M_ETYPE 0xffffU
24910 #define V_ETYPE(x) ((x) << S_ETYPE)
24911 #define G_ETYPE(x) (((x) >> S_ETYPE) & M_ETYPE)
24914 #define M_OPCODE 0xffffU
24915 #define V_OPCODE(x) ((x) << S_OPCODE)
24916 #define G_OPCODE(x) (((x) >> S_OPCODE) & M_OPCODE)
24918 #define A_MPS_RX_QFC0_ATRB 0x110a0
24921 #define M_DA 0xffffU
24922 #define V_DA(x) ((x) << S_DA)
24923 #define G_DA(x) (((x) >> S_DA) & M_DA)
24925 #define A_MPS_RX_QFC1_ATRB 0x110a4
24926 #define A_MPS_RX_PT_ARB0 0x110a8
24928 #define S_LPBK_WT 16
24929 #define M_LPBK_WT 0x3fffU
24930 #define V_LPBK_WT(x) ((x) << S_LPBK_WT)
24931 #define G_LPBK_WT(x) (((x) >> S_LPBK_WT) & M_LPBK_WT)
24934 #define M_MAC_WT 0x3fffU
24935 #define V_MAC_WT(x) ((x) << S_MAC_WT)
24936 #define G_MAC_WT(x) (((x) >> S_MAC_WT) & M_MAC_WT)
24938 #define A_MPS_RX_PT_ARB1 0x110ac
24939 #define A_MPS_RX_PT_ARB2 0x110b0
24940 #define A_MPS_RX_PT_ARB3 0x110b4
24941 #define A_MPS_RX_PT_ARB4 0x110b8
24942 #define A_MPS_PF_OUT_EN 0x110bc
24945 #define M_OUTEN 0xffU
24946 #define V_OUTEN(x) ((x) << S_OUTEN)
24947 #define G_OUTEN(x) (((x) >> S_OUTEN) & M_OUTEN)
24949 #define A_MPS_BMC_MTU 0x110c0
24952 #define M_MTU 0x3fffU
24953 #define V_MTU(x) ((x) << S_MTU)
24954 #define G_MTU(x) (((x) >> S_MTU) & M_MTU)
24956 #define A_MPS_BMC_PKT_CNT 0x110c4
24957 #define A_MPS_BMC_BYTE_CNT 0x110c8
24958 #define A_MPS_PFVF_ATRB_CTL 0x110cc
24960 #define S_RD_WRN 31
24961 #define V_RD_WRN(x) ((x) << S_RD_WRN)
24962 #define F_RD_WRN V_RD_WRN(1U)
24965 #define M_PFVF 0xffU
24966 #define V_PFVF(x) ((x) << S_PFVF)
24967 #define G_PFVF(x) (((x) >> S_PFVF) & M_PFVF)
24969 #define A_MPS_PFVF_ATRB 0x110d0
24971 #define S_ATTR_PF 28
24972 #define M_ATTR_PF 0x7U
24973 #define V_ATTR_PF(x) ((x) << S_ATTR_PF)
24974 #define G_ATTR_PF(x) (((x) >> S_ATTR_PF) & M_ATTR_PF)
24977 #define V_OFF(x) ((x) << S_OFF)
24978 #define F_OFF V_OFF(1U)
24980 #define S_NV_DROP 17
24981 #define V_NV_DROP(x) ((x) << S_NV_DROP)
24982 #define F_NV_DROP V_NV_DROP(1U)
24984 #define S_ATTR_MODE 16
24985 #define V_ATTR_MODE(x) ((x) << S_ATTR_MODE)
24986 #define F_ATTR_MODE V_ATTR_MODE(1U)
24988 #define A_MPS_PFVF_ATRB_FLTR0 0x110d4
24990 #define S_VLAN_EN 16
24991 #define V_VLAN_EN(x) ((x) << S_VLAN_EN)
24992 #define F_VLAN_EN V_VLAN_EN(1U)
24994 #define S_VLAN_ID 0
24995 #define M_VLAN_ID 0xfffU
24996 #define V_VLAN_ID(x) ((x) << S_VLAN_ID)
24997 #define G_VLAN_ID(x) (((x) >> S_VLAN_ID) & M_VLAN_ID)
24999 #define A_MPS_PFVF_ATRB_FLTR1 0x110d8
25000 #define A_MPS_PFVF_ATRB_FLTR2 0x110dc
25001 #define A_MPS_PFVF_ATRB_FLTR3 0x110e0
25002 #define A_MPS_PFVF_ATRB_FLTR4 0x110e4
25003 #define A_MPS_PFVF_ATRB_FLTR5 0x110e8
25004 #define A_MPS_PFVF_ATRB_FLTR6 0x110ec
25005 #define A_MPS_PFVF_ATRB_FLTR7 0x110f0
25006 #define A_MPS_PFVF_ATRB_FLTR8 0x110f4
25007 #define A_MPS_PFVF_ATRB_FLTR9 0x110f8
25008 #define A_MPS_PFVF_ATRB_FLTR10 0x110fc
25009 #define A_MPS_PFVF_ATRB_FLTR11 0x11100
25010 #define A_MPS_PFVF_ATRB_FLTR12 0x11104
25011 #define A_MPS_PFVF_ATRB_FLTR13 0x11108
25012 #define A_MPS_PFVF_ATRB_FLTR14 0x1110c
25013 #define A_MPS_PFVF_ATRB_FLTR15 0x11110
25014 #define A_MPS_RPLC_MAP_CTL 0x11114
25016 #define S_RPLC_MAP_ADDR 0
25017 #define M_RPLC_MAP_ADDR 0x3ffU
25018 #define V_RPLC_MAP_ADDR(x) ((x) << S_RPLC_MAP_ADDR)
25019 #define G_RPLC_MAP_ADDR(x) (((x) >> S_RPLC_MAP_ADDR) & M_RPLC_MAP_ADDR)
25021 #define A_MPS_PF_RPLCT_MAP 0x11118
25024 #define M_PF_EN 0xffU
25025 #define V_PF_EN(x) ((x) << S_PF_EN)
25026 #define G_PF_EN(x) (((x) >> S_PF_EN) & M_PF_EN)
25028 #define A_MPS_VF_RPLCT_MAP0 0x1111c
25029 #define A_MPS_VF_RPLCT_MAP1 0x11120
25030 #define A_MPS_VF_RPLCT_MAP2 0x11124
25031 #define A_MPS_VF_RPLCT_MAP3 0x11128
25032 #define A_MPS_MEM_DBG_CTL 0x1112c
25035 #define V_PKD(x) ((x) << S_PKD)
25036 #define F_PKD V_PKD(1U)
25039 #define V_PGD(x) ((x) << S_PGD)
25040 #define F_PGD V_PGD(1U)
25042 #define A_MPS_PKD_MEM_DATA0 0x11130
25043 #define A_MPS_PKD_MEM_DATA1 0x11134
25044 #define A_MPS_PKD_MEM_DATA2 0x11138
25045 #define A_MPS_PGD_MEM_DATA 0x1113c
25046 #define A_MPS_RX_SE_CNT_ERR 0x11140
25048 #define S_RX_SE_ERRMAP 0
25049 #define M_RX_SE_ERRMAP 0xfffffU
25050 #define V_RX_SE_ERRMAP(x) ((x) << S_RX_SE_ERRMAP)
25051 #define G_RX_SE_ERRMAP(x) (((x) >> S_RX_SE_ERRMAP) & M_RX_SE_ERRMAP)
25053 #define A_MPS_RX_SE_CNT_CLR 0x11144
25054 #define A_MPS_RX_SE_CNT_IN0 0x11148
25056 #define S_SOP_CNT_PM 24
25057 #define M_SOP_CNT_PM 0xffU
25058 #define V_SOP_CNT_PM(x) ((x) << S_SOP_CNT_PM)
25059 #define G_SOP_CNT_PM(x) (((x) >> S_SOP_CNT_PM) & M_SOP_CNT_PM)
25061 #define S_EOP_CNT_PM 16
25062 #define M_EOP_CNT_PM 0xffU
25063 #define V_EOP_CNT_PM(x) ((x) << S_EOP_CNT_PM)
25064 #define G_EOP_CNT_PM(x) (((x) >> S_EOP_CNT_PM) & M_EOP_CNT_PM)
25066 #define S_SOP_CNT_IN 8
25067 #define M_SOP_CNT_IN 0xffU
25068 #define V_SOP_CNT_IN(x) ((x) << S_SOP_CNT_IN)
25069 #define G_SOP_CNT_IN(x) (((x) >> S_SOP_CNT_IN) & M_SOP_CNT_IN)
25071 #define S_EOP_CNT_IN 0
25072 #define M_EOP_CNT_IN 0xffU
25073 #define V_EOP_CNT_IN(x) ((x) << S_EOP_CNT_IN)
25074 #define G_EOP_CNT_IN(x) (((x) >> S_EOP_CNT_IN) & M_EOP_CNT_IN)
25076 #define A_MPS_RX_SE_CNT_IN1 0x1114c
25077 #define A_MPS_RX_SE_CNT_IN2 0x11150
25078 #define A_MPS_RX_SE_CNT_IN3 0x11154
25079 #define A_MPS_RX_SE_CNT_IN4 0x11158
25080 #define A_MPS_RX_SE_CNT_IN5 0x1115c
25081 #define A_MPS_RX_SE_CNT_IN6 0x11160
25082 #define A_MPS_RX_SE_CNT_IN7 0x11164
25083 #define A_MPS_RX_SE_CNT_OUT01 0x11168
25085 #define S_SOP_CNT_1 24
25086 #define M_SOP_CNT_1 0xffU
25087 #define V_SOP_CNT_1(x) ((x) << S_SOP_CNT_1)
25088 #define G_SOP_CNT_1(x) (((x) >> S_SOP_CNT_1) & M_SOP_CNT_1)
25090 #define S_EOP_CNT_1 16
25091 #define M_EOP_CNT_1 0xffU
25092 #define V_EOP_CNT_1(x) ((x) << S_EOP_CNT_1)
25093 #define G_EOP_CNT_1(x) (((x) >> S_EOP_CNT_1) & M_EOP_CNT_1)
25095 #define S_SOP_CNT_0 8
25096 #define M_SOP_CNT_0 0xffU
25097 #define V_SOP_CNT_0(x) ((x) << S_SOP_CNT_0)
25098 #define G_SOP_CNT_0(x) (((x) >> S_SOP_CNT_0) & M_SOP_CNT_0)
25100 #define S_EOP_CNT_0 0
25101 #define M_EOP_CNT_0 0xffU
25102 #define V_EOP_CNT_0(x) ((x) << S_EOP_CNT_0)
25103 #define G_EOP_CNT_0(x) (((x) >> S_EOP_CNT_0) & M_EOP_CNT_0)
25105 #define A_MPS_RX_SE_CNT_OUT23 0x1116c
25107 #define S_SOP_CNT_3 24
25108 #define M_SOP_CNT_3 0xffU
25109 #define V_SOP_CNT_3(x) ((x) << S_SOP_CNT_3)
25110 #define G_SOP_CNT_3(x) (((x) >> S_SOP_CNT_3) & M_SOP_CNT_3)
25112 #define S_EOP_CNT_3 16
25113 #define M_EOP_CNT_3 0xffU
25114 #define V_EOP_CNT_3(x) ((x) << S_EOP_CNT_3)
25115 #define G_EOP_CNT_3(x) (((x) >> S_EOP_CNT_3) & M_EOP_CNT_3)
25117 #define S_SOP_CNT_2 8
25118 #define M_SOP_CNT_2 0xffU
25119 #define V_SOP_CNT_2(x) ((x) << S_SOP_CNT_2)
25120 #define G_SOP_CNT_2(x) (((x) >> S_SOP_CNT_2) & M_SOP_CNT_2)
25122 #define S_EOP_CNT_2 0
25123 #define M_EOP_CNT_2 0xffU
25124 #define V_EOP_CNT_2(x) ((x) << S_EOP_CNT_2)
25125 #define G_EOP_CNT_2(x) (((x) >> S_EOP_CNT_2) & M_EOP_CNT_2)
25127 #define A_MPS_RX_SPI_ERR 0x11170
25129 #define S_LENERR 21
25130 #define M_LENERR 0xfU
25131 #define V_LENERR(x) ((x) << S_LENERR)
25132 #define G_LENERR(x) (((x) >> S_LENERR) & M_LENERR)
25135 #define M_SPIERR 0x1fffffU
25136 #define V_SPIERR(x) ((x) << S_SPIERR)
25137 #define G_SPIERR(x) (((x) >> S_SPIERR) & M_SPIERR)
25139 #define A_MPS_RX_IN_BUS_STATE 0x11174
25142 #define M_ST3 0xffU
25143 #define V_ST3(x) ((x) << S_ST3)
25144 #define G_ST3(x) (((x) >> S_ST3) & M_ST3)
25147 #define M_ST2 0xffU
25148 #define V_ST2(x) ((x) << S_ST2)
25149 #define G_ST2(x) (((x) >> S_ST2) & M_ST2)
25152 #define M_ST1 0xffU
25153 #define V_ST1(x) ((x) << S_ST1)
25154 #define G_ST1(x) (((x) >> S_ST1) & M_ST1)
25157 #define M_ST0 0xffU
25158 #define V_ST0(x) ((x) << S_ST0)
25159 #define G_ST0(x) (((x) >> S_ST0) & M_ST0)
25161 #define A_MPS_RX_OUT_BUS_STATE 0x11178
25163 #define S_ST_NCSI 23
25164 #define M_ST_NCSI 0x1ffU
25165 #define V_ST_NCSI(x) ((x) << S_ST_NCSI)
25166 #define G_ST_NCSI(x) (((x) >> S_ST_NCSI) & M_ST_NCSI)
25169 #define M_ST_TP 0x7fffffU
25170 #define V_ST_TP(x) ((x) << S_ST_TP)
25171 #define G_ST_TP(x) (((x) >> S_ST_TP) & M_ST_TP)
25173 #define A_MPS_RX_DBG_CTL 0x1117c
25175 #define S_OUT_DBG_CHNL 8
25176 #define M_OUT_DBG_CHNL 0x7U
25177 #define V_OUT_DBG_CHNL(x) ((x) << S_OUT_DBG_CHNL)
25178 #define G_OUT_DBG_CHNL(x) (((x) >> S_OUT_DBG_CHNL) & M_OUT_DBG_CHNL)
25180 #define S_DBG_PKD_QSEL 7
25181 #define V_DBG_PKD_QSEL(x) ((x) << S_DBG_PKD_QSEL)
25182 #define F_DBG_PKD_QSEL V_DBG_PKD_QSEL(1U)
25184 #define S_DBG_CDS_INV 6
25185 #define V_DBG_CDS_INV(x) ((x) << S_DBG_CDS_INV)
25186 #define F_DBG_CDS_INV V_DBG_CDS_INV(1U)
25188 #define S_IN_DBG_PORT 3
25189 #define M_IN_DBG_PORT 0x7U
25190 #define V_IN_DBG_PORT(x) ((x) << S_IN_DBG_PORT)
25191 #define G_IN_DBG_PORT(x) (((x) >> S_IN_DBG_PORT) & M_IN_DBG_PORT)
25193 #define S_IN_DBG_CHNL 0
25194 #define M_IN_DBG_CHNL 0x7U
25195 #define V_IN_DBG_CHNL(x) ((x) << S_IN_DBG_CHNL)
25196 #define G_IN_DBG_CHNL(x) (((x) >> S_IN_DBG_CHNL) & M_IN_DBG_CHNL)
25198 #define A_MPS_RX_CLS_DROP_CNT0 0x11180
25200 #define S_LPBK_CNT0 16
25201 #define M_LPBK_CNT0 0xffffU
25202 #define V_LPBK_CNT0(x) ((x) << S_LPBK_CNT0)
25203 #define G_LPBK_CNT0(x) (((x) >> S_LPBK_CNT0) & M_LPBK_CNT0)
25205 #define S_MAC_CNT0 0
25206 #define M_MAC_CNT0 0xffffU
25207 #define V_MAC_CNT0(x) ((x) << S_MAC_CNT0)
25208 #define G_MAC_CNT0(x) (((x) >> S_MAC_CNT0) & M_MAC_CNT0)
25210 #define A_MPS_RX_CLS_DROP_CNT1 0x11184
25212 #define S_LPBK_CNT1 16
25213 #define M_LPBK_CNT1 0xffffU
25214 #define V_LPBK_CNT1(x) ((x) << S_LPBK_CNT1)
25215 #define G_LPBK_CNT1(x) (((x) >> S_LPBK_CNT1) & M_LPBK_CNT1)
25217 #define S_MAC_CNT1 0
25218 #define M_MAC_CNT1 0xffffU
25219 #define V_MAC_CNT1(x) ((x) << S_MAC_CNT1)
25220 #define G_MAC_CNT1(x) (((x) >> S_MAC_CNT1) & M_MAC_CNT1)
25222 #define A_MPS_RX_CLS_DROP_CNT2 0x11188
25224 #define S_LPBK_CNT2 16
25225 #define M_LPBK_CNT2 0xffffU
25226 #define V_LPBK_CNT2(x) ((x) << S_LPBK_CNT2)
25227 #define G_LPBK_CNT2(x) (((x) >> S_LPBK_CNT2) & M_LPBK_CNT2)
25229 #define S_MAC_CNT2 0
25230 #define M_MAC_CNT2 0xffffU
25231 #define V_MAC_CNT2(x) ((x) << S_MAC_CNT2)
25232 #define G_MAC_CNT2(x) (((x) >> S_MAC_CNT2) & M_MAC_CNT2)
25234 #define A_MPS_RX_CLS_DROP_CNT3 0x1118c
25236 #define S_LPBK_CNT3 16
25237 #define M_LPBK_CNT3 0xffffU
25238 #define V_LPBK_CNT3(x) ((x) << S_LPBK_CNT3)
25239 #define G_LPBK_CNT3(x) (((x) >> S_LPBK_CNT3) & M_LPBK_CNT3)
25241 #define S_MAC_CNT3 0
25242 #define M_MAC_CNT3 0xffffU
25243 #define V_MAC_CNT3(x) ((x) << S_MAC_CNT3)
25244 #define G_MAC_CNT3(x) (((x) >> S_MAC_CNT3) & M_MAC_CNT3)
25246 #define A_MPS_RX_SPARE 0x11190
25247 #define A_MPS_RX_PTP_ETYPE 0x11194
25249 #define S_PETYPE2 16
25250 #define M_PETYPE2 0xffffU
25251 #define V_PETYPE2(x) ((x) << S_PETYPE2)
25252 #define G_PETYPE2(x) (((x) >> S_PETYPE2) & M_PETYPE2)
25254 #define S_PETYPE1 0
25255 #define M_PETYPE1 0xffffU
25256 #define V_PETYPE1(x) ((x) << S_PETYPE1)
25257 #define G_PETYPE1(x) (((x) >> S_PETYPE1) & M_PETYPE1)
25259 #define A_MPS_RX_PTP_TCP 0x11198
25261 #define S_PTCPORT2 16
25262 #define M_PTCPORT2 0xffffU
25263 #define V_PTCPORT2(x) ((x) << S_PTCPORT2)
25264 #define G_PTCPORT2(x) (((x) >> S_PTCPORT2) & M_PTCPORT2)
25266 #define S_PTCPORT1 0
25267 #define M_PTCPORT1 0xffffU
25268 #define V_PTCPORT1(x) ((x) << S_PTCPORT1)
25269 #define G_PTCPORT1(x) (((x) >> S_PTCPORT1) & M_PTCPORT1)
25271 #define A_MPS_RX_PTP_UDP 0x1119c
25273 #define S_PUDPORT2 16
25274 #define M_PUDPORT2 0xffffU
25275 #define V_PUDPORT2(x) ((x) << S_PUDPORT2)
25276 #define G_PUDPORT2(x) (((x) >> S_PUDPORT2) & M_PUDPORT2)
25278 #define S_PUDPORT1 0
25279 #define M_PUDPORT1 0xffffU
25280 #define V_PUDPORT1(x) ((x) << S_PUDPORT1)
25281 #define G_PUDPORT1(x) (((x) >> S_PUDPORT1) & M_PUDPORT1)
25283 #define A_MPS_RX_PTP_CTL 0x111a0
25285 #define S_MIN_PTP_SPACE 24
25286 #define M_MIN_PTP_SPACE 0x7fU
25287 #define V_MIN_PTP_SPACE(x) ((x) << S_MIN_PTP_SPACE)
25288 #define G_MIN_PTP_SPACE(x) (((x) >> S_MIN_PTP_SPACE) & M_MIN_PTP_SPACE)
25290 #define S_PUDP2EN 20
25291 #define M_PUDP2EN 0xfU
25292 #define V_PUDP2EN(x) ((x) << S_PUDP2EN)
25293 #define G_PUDP2EN(x) (((x) >> S_PUDP2EN) & M_PUDP2EN)
25295 #define S_PUDP1EN 16
25296 #define M_PUDP1EN 0xfU
25297 #define V_PUDP1EN(x) ((x) << S_PUDP1EN)
25298 #define G_PUDP1EN(x) (((x) >> S_PUDP1EN) & M_PUDP1EN)
25300 #define S_PTCP2EN 12
25301 #define M_PTCP2EN 0xfU
25302 #define V_PTCP2EN(x) ((x) << S_PTCP2EN)
25303 #define G_PTCP2EN(x) (((x) >> S_PTCP2EN) & M_PTCP2EN)
25305 #define S_PTCP1EN 8
25306 #define M_PTCP1EN 0xfU
25307 #define V_PTCP1EN(x) ((x) << S_PTCP1EN)
25308 #define G_PTCP1EN(x) (((x) >> S_PTCP1EN) & M_PTCP1EN)
25310 #define S_PETYPE2EN 4
25311 #define M_PETYPE2EN 0xfU
25312 #define V_PETYPE2EN(x) ((x) << S_PETYPE2EN)
25313 #define G_PETYPE2EN(x) (((x) >> S_PETYPE2EN) & M_PETYPE2EN)
25315 #define S_PETYPE1EN 0
25316 #define M_PETYPE1EN 0xfU
25317 #define V_PETYPE1EN(x) ((x) << S_PETYPE1EN)
25318 #define G_PETYPE1EN(x) (((x) >> S_PETYPE1EN) & M_PETYPE1EN)
25320 #define A_MPS_RX_PAUSE_GEN_TH_0_0 0x111a4
25321 #define A_MPS_RX_PAUSE_GEN_TH_0_1 0x111a8
25322 #define A_MPS_RX_PAUSE_GEN_TH_0_2 0x111ac
25323 #define A_MPS_RX_PAUSE_GEN_TH_0_3 0x111b0
25324 #define A_MPS_RX_PAUSE_GEN_TH_1_0 0x111b4
25325 #define A_MPS_RX_PAUSE_GEN_TH_1_1 0x111b8
25326 #define A_MPS_RX_PAUSE_GEN_TH_1_2 0x111bc
25327 #define A_MPS_RX_PAUSE_GEN_TH_1_3 0x111c0
25328 #define A_MPS_RX_PAUSE_GEN_TH_2_0 0x111c4
25329 #define A_MPS_RX_PAUSE_GEN_TH_2_1 0x111c8
25330 #define A_MPS_RX_PAUSE_GEN_TH_2_2 0x111cc
25331 #define A_MPS_RX_PAUSE_GEN_TH_2_3 0x111d0
25332 #define A_MPS_RX_PAUSE_GEN_TH_3_0 0x111d4
25333 #define A_MPS_RX_PAUSE_GEN_TH_3_1 0x111d8
25334 #define A_MPS_RX_PAUSE_GEN_TH_3_2 0x111dc
25335 #define A_MPS_RX_PAUSE_GEN_TH_3_3 0x111e0
25336 #define A_MPS_RX_MAC_CLS_DROP_CNT0 0x111e4
25337 #define A_MPS_RX_MAC_CLS_DROP_CNT1 0x111e8
25338 #define A_MPS_RX_MAC_CLS_DROP_CNT2 0x111ec
25339 #define A_MPS_RX_MAC_CLS_DROP_CNT3 0x111f0
25340 #define A_MPS_RX_LPBK_CLS_DROP_CNT0 0x111f4
25341 #define A_MPS_RX_LPBK_CLS_DROP_CNT1 0x111f8
25342 #define A_MPS_RX_LPBK_CLS_DROP_CNT2 0x111fc
25343 #define A_MPS_RX_LPBK_CLS_DROP_CNT3 0x11200
25344 #define A_MPS_RX_CGEN 0x11204
25346 #define S_MPS_RX_CGEN_NCSI 12
25347 #define V_MPS_RX_CGEN_NCSI(x) ((x) << S_MPS_RX_CGEN_NCSI)
25348 #define F_MPS_RX_CGEN_NCSI V_MPS_RX_CGEN_NCSI(1U)
25350 #define S_MPS_RX_CGEN_OUT 8
25351 #define M_MPS_RX_CGEN_OUT 0xfU
25352 #define V_MPS_RX_CGEN_OUT(x) ((x) << S_MPS_RX_CGEN_OUT)
25353 #define G_MPS_RX_CGEN_OUT(x) (((x) >> S_MPS_RX_CGEN_OUT) & M_MPS_RX_CGEN_OUT)
25355 #define S_MPS_RX_CGEN_LPBK_IN 4
25356 #define M_MPS_RX_CGEN_LPBK_IN 0xfU
25357 #define V_MPS_RX_CGEN_LPBK_IN(x) ((x) << S_MPS_RX_CGEN_LPBK_IN)
25358 #define G_MPS_RX_CGEN_LPBK_IN(x) (((x) >> S_MPS_RX_CGEN_LPBK_IN) & M_MPS_RX_CGEN_LPBK_IN)
25360 #define S_MPS_RX_CGEN_MAC_IN 0
25361 #define M_MPS_RX_CGEN_MAC_IN 0xfU
25362 #define V_MPS_RX_CGEN_MAC_IN(x) ((x) << S_MPS_RX_CGEN_MAC_IN)
25363 #define G_MPS_RX_CGEN_MAC_IN(x) (((x) >> S_MPS_RX_CGEN_MAC_IN) & M_MPS_RX_CGEN_MAC_IN)
25365 /* registers for module CPL_SWITCH */
25366 #define CPL_SWITCH_BASE_ADDR 0x19040
25368 #define A_CPL_SWITCH_CNTRL 0x19040
25370 #define S_CPL_PKT_TID 8
25371 #define M_CPL_PKT_TID 0xffffffU
25372 #define V_CPL_PKT_TID(x) ((x) << S_CPL_PKT_TID)
25373 #define G_CPL_PKT_TID(x) (((x) >> S_CPL_PKT_TID) & M_CPL_PKT_TID)
25375 #define S_CIM_TRUNCATE_ENABLE 5
25376 #define V_CIM_TRUNCATE_ENABLE(x) ((x) << S_CIM_TRUNCATE_ENABLE)
25377 #define F_CIM_TRUNCATE_ENABLE V_CIM_TRUNCATE_ENABLE(1U)
25379 #define S_CIM_TO_UP_FULL_SIZE 4
25380 #define V_CIM_TO_UP_FULL_SIZE(x) ((x) << S_CIM_TO_UP_FULL_SIZE)
25381 #define F_CIM_TO_UP_FULL_SIZE V_CIM_TO_UP_FULL_SIZE(1U)
25383 #define S_CPU_NO_ENABLE 3
25384 #define V_CPU_NO_ENABLE(x) ((x) << S_CPU_NO_ENABLE)
25385 #define F_CPU_NO_ENABLE V_CPU_NO_ENABLE(1U)
25387 #define S_SWITCH_TABLE_ENABLE 2
25388 #define V_SWITCH_TABLE_ENABLE(x) ((x) << S_SWITCH_TABLE_ENABLE)
25389 #define F_SWITCH_TABLE_ENABLE V_SWITCH_TABLE_ENABLE(1U)
25391 #define S_SGE_ENABLE 1
25392 #define V_SGE_ENABLE(x) ((x) << S_SGE_ENABLE)
25393 #define F_SGE_ENABLE V_SGE_ENABLE(1U)
25395 #define S_CIM_ENABLE 0
25396 #define V_CIM_ENABLE(x) ((x) << S_CIM_ENABLE)
25397 #define F_CIM_ENABLE V_CIM_ENABLE(1U)
25399 #define S_CIM_SPLIT_ENABLE 6
25400 #define V_CIM_SPLIT_ENABLE(x) ((x) << S_CIM_SPLIT_ENABLE)
25401 #define F_CIM_SPLIT_ENABLE V_CIM_SPLIT_ENABLE(1U)
25403 #define A_CPL_SWITCH_TBL_IDX 0x19044
25405 #define S_SWITCH_TBL_IDX 0
25406 #define M_SWITCH_TBL_IDX 0xfU
25407 #define V_SWITCH_TBL_IDX(x) ((x) << S_SWITCH_TBL_IDX)
25408 #define G_SWITCH_TBL_IDX(x) (((x) >> S_SWITCH_TBL_IDX) & M_SWITCH_TBL_IDX)
25410 #define A_CPL_SWITCH_TBL_DATA 0x19048
25411 #define A_CPL_SWITCH_ZERO_ERROR 0x1904c
25413 #define S_ZERO_CMD_CH1 8
25414 #define M_ZERO_CMD_CH1 0xffU
25415 #define V_ZERO_CMD_CH1(x) ((x) << S_ZERO_CMD_CH1)
25416 #define G_ZERO_CMD_CH1(x) (((x) >> S_ZERO_CMD_CH1) & M_ZERO_CMD_CH1)
25418 #define S_ZERO_CMD_CH0 0
25419 #define M_ZERO_CMD_CH0 0xffU
25420 #define V_ZERO_CMD_CH0(x) ((x) << S_ZERO_CMD_CH0)
25421 #define G_ZERO_CMD_CH0(x) (((x) >> S_ZERO_CMD_CH0) & M_ZERO_CMD_CH0)
25423 #define A_CPL_INTR_ENABLE 0x19050
25425 #define S_CIM_OP_MAP_PERR 5
25426 #define V_CIM_OP_MAP_PERR(x) ((x) << S_CIM_OP_MAP_PERR)
25427 #define F_CIM_OP_MAP_PERR V_CIM_OP_MAP_PERR(1U)
25429 #define S_CIM_OVFL_ERROR 4
25430 #define V_CIM_OVFL_ERROR(x) ((x) << S_CIM_OVFL_ERROR)
25431 #define F_CIM_OVFL_ERROR V_CIM_OVFL_ERROR(1U)
25433 #define S_TP_FRAMING_ERROR 3
25434 #define V_TP_FRAMING_ERROR(x) ((x) << S_TP_FRAMING_ERROR)
25435 #define F_TP_FRAMING_ERROR V_TP_FRAMING_ERROR(1U)
25437 #define S_SGE_FRAMING_ERROR 2
25438 #define V_SGE_FRAMING_ERROR(x) ((x) << S_SGE_FRAMING_ERROR)
25439 #define F_SGE_FRAMING_ERROR V_SGE_FRAMING_ERROR(1U)
25441 #define S_CIM_FRAMING_ERROR 1
25442 #define V_CIM_FRAMING_ERROR(x) ((x) << S_CIM_FRAMING_ERROR)
25443 #define F_CIM_FRAMING_ERROR V_CIM_FRAMING_ERROR(1U)
25445 #define S_ZERO_SWITCH_ERROR 0
25446 #define V_ZERO_SWITCH_ERROR(x) ((x) << S_ZERO_SWITCH_ERROR)
25447 #define F_ZERO_SWITCH_ERROR V_ZERO_SWITCH_ERROR(1U)
25449 #define S_PERR_CPL_128TO128_1 7
25450 #define V_PERR_CPL_128TO128_1(x) ((x) << S_PERR_CPL_128TO128_1)
25451 #define F_PERR_CPL_128TO128_1 V_PERR_CPL_128TO128_1(1U)
25453 #define S_PERR_CPL_128TO128_0 6
25454 #define V_PERR_CPL_128TO128_0(x) ((x) << S_PERR_CPL_128TO128_0)
25455 #define F_PERR_CPL_128TO128_0 V_PERR_CPL_128TO128_0(1U)
25457 #define A_CPL_INTR_CAUSE 0x19054
25458 #define A_CPL_MAP_TBL_IDX 0x19058
25460 #define S_MAP_TBL_IDX 0
25461 #define M_MAP_TBL_IDX 0xffU
25462 #define V_MAP_TBL_IDX(x) ((x) << S_MAP_TBL_IDX)
25463 #define G_MAP_TBL_IDX(x) (((x) >> S_MAP_TBL_IDX) & M_MAP_TBL_IDX)
25465 #define S_CIM_SPLIT_OPCODE_PROGRAM 8
25466 #define V_CIM_SPLIT_OPCODE_PROGRAM(x) ((x) << S_CIM_SPLIT_OPCODE_PROGRAM)
25467 #define F_CIM_SPLIT_OPCODE_PROGRAM V_CIM_SPLIT_OPCODE_PROGRAM(1U)
25469 #define A_CPL_MAP_TBL_DATA 0x1905c
25471 #define S_MAP_TBL_DATA 0
25472 #define M_MAP_TBL_DATA 0xffU
25473 #define V_MAP_TBL_DATA(x) ((x) << S_MAP_TBL_DATA)
25474 #define G_MAP_TBL_DATA(x) (((x) >> S_MAP_TBL_DATA) & M_MAP_TBL_DATA)
25476 /* registers for module SMB */
25477 #define SMB_BASE_ADDR 0x19060
25479 #define A_SMB_GLOBAL_TIME_CFG 0x19060
25481 #define S_MACROCNTCFG 8
25482 #define M_MACROCNTCFG 0x1fU
25483 #define V_MACROCNTCFG(x) ((x) << S_MACROCNTCFG)
25484 #define G_MACROCNTCFG(x) (((x) >> S_MACROCNTCFG) & M_MACROCNTCFG)
25486 #define S_MICROCNTCFG 0
25487 #define M_MICROCNTCFG 0xffU
25488 #define V_MICROCNTCFG(x) ((x) << S_MICROCNTCFG)
25489 #define G_MICROCNTCFG(x) (((x) >> S_MICROCNTCFG) & M_MICROCNTCFG)
25491 #define A_SMB_MST_TIMEOUT_CFG 0x19064
25493 #define S_MSTTIMEOUTCFG 0
25494 #define M_MSTTIMEOUTCFG 0xffffffU
25495 #define V_MSTTIMEOUTCFG(x) ((x) << S_MSTTIMEOUTCFG)
25496 #define G_MSTTIMEOUTCFG(x) (((x) >> S_MSTTIMEOUTCFG) & M_MSTTIMEOUTCFG)
25498 #define A_SMB_MST_CTL_CFG 0x19068
25500 #define S_MSTFIFODBG 31
25501 #define V_MSTFIFODBG(x) ((x) << S_MSTFIFODBG)
25502 #define F_MSTFIFODBG V_MSTFIFODBG(1U)
25504 #define S_MSTFIFODBGCLR 30
25505 #define V_MSTFIFODBGCLR(x) ((x) << S_MSTFIFODBGCLR)
25506 #define F_MSTFIFODBGCLR V_MSTFIFODBGCLR(1U)
25508 #define S_MSTRXBYTECFG 12
25509 #define M_MSTRXBYTECFG 0x3fU
25510 #define V_MSTRXBYTECFG(x) ((x) << S_MSTRXBYTECFG)
25511 #define G_MSTRXBYTECFG(x) (((x) >> S_MSTRXBYTECFG) & M_MSTRXBYTECFG)
25513 #define S_MSTTXBYTECFG 6
25514 #define M_MSTTXBYTECFG 0x3fU
25515 #define V_MSTTXBYTECFG(x) ((x) << S_MSTTXBYTECFG)
25516 #define G_MSTTXBYTECFG(x) (((x) >> S_MSTTXBYTECFG) & M_MSTTXBYTECFG)
25518 #define S_MSTRESET 1
25519 #define V_MSTRESET(x) ((x) << S_MSTRESET)
25520 #define F_MSTRESET V_MSTRESET(1U)
25522 #define S_MSTCTLEN 0
25523 #define V_MSTCTLEN(x) ((x) << S_MSTCTLEN)
25524 #define F_MSTCTLEN V_MSTCTLEN(1U)
25526 #define A_SMB_MST_CTL_STS 0x1906c
25528 #define S_MSTRXBYTECNT 12
25529 #define M_MSTRXBYTECNT 0x3fU
25530 #define V_MSTRXBYTECNT(x) ((x) << S_MSTRXBYTECNT)
25531 #define G_MSTRXBYTECNT(x) (((x) >> S_MSTRXBYTECNT) & M_MSTRXBYTECNT)
25533 #define S_MSTTXBYTECNT 6
25534 #define M_MSTTXBYTECNT 0x3fU
25535 #define V_MSTTXBYTECNT(x) ((x) << S_MSTTXBYTECNT)
25536 #define G_MSTTXBYTECNT(x) (((x) >> S_MSTTXBYTECNT) & M_MSTTXBYTECNT)
25538 #define S_MSTBUSYSTS 0
25539 #define V_MSTBUSYSTS(x) ((x) << S_MSTBUSYSTS)
25540 #define F_MSTBUSYSTS V_MSTBUSYSTS(1U)
25542 #define A_SMB_MST_TX_FIFO_RDWR 0x19070
25543 #define A_SMB_MST_RX_FIFO_RDWR 0x19074
25544 #define A_SMB_SLV_TIMEOUT_CFG 0x19078
25546 #define S_SLVTIMEOUTCFG 0
25547 #define M_SLVTIMEOUTCFG 0xffffffU
25548 #define V_SLVTIMEOUTCFG(x) ((x) << S_SLVTIMEOUTCFG)
25549 #define G_SLVTIMEOUTCFG(x) (((x) >> S_SLVTIMEOUTCFG) & M_SLVTIMEOUTCFG)
25551 #define A_SMB_SLV_CTL_CFG 0x1907c
25553 #define S_SLVFIFODBG 31
25554 #define V_SLVFIFODBG(x) ((x) << S_SLVFIFODBG)
25555 #define F_SLVFIFODBG V_SLVFIFODBG(1U)
25557 #define S_SLVFIFODBGCLR 30
25558 #define V_SLVFIFODBGCLR(x) ((x) << S_SLVFIFODBGCLR)
25559 #define F_SLVFIFODBGCLR V_SLVFIFODBGCLR(1U)
25561 #define S_SLVCRCOUTBITINV 21
25562 #define V_SLVCRCOUTBITINV(x) ((x) << S_SLVCRCOUTBITINV)
25563 #define F_SLVCRCOUTBITINV V_SLVCRCOUTBITINV(1U)
25565 #define S_SLVCRCOUTBITREV 20
25566 #define V_SLVCRCOUTBITREV(x) ((x) << S_SLVCRCOUTBITREV)
25567 #define F_SLVCRCOUTBITREV V_SLVCRCOUTBITREV(1U)
25569 #define S_SLVCRCINBITREV 19
25570 #define V_SLVCRCINBITREV(x) ((x) << S_SLVCRCINBITREV)
25571 #define F_SLVCRCINBITREV V_SLVCRCINBITREV(1U)
25573 #define S_SLVCRCPRESET 11
25574 #define M_SLVCRCPRESET 0xffU
25575 #define V_SLVCRCPRESET(x) ((x) << S_SLVCRCPRESET)
25576 #define G_SLVCRCPRESET(x) (((x) >> S_SLVCRCPRESET) & M_SLVCRCPRESET)
25578 #define S_SLVADDRCFG 4
25579 #define M_SLVADDRCFG 0x7fU
25580 #define V_SLVADDRCFG(x) ((x) << S_SLVADDRCFG)
25581 #define G_SLVADDRCFG(x) (((x) >> S_SLVADDRCFG) & M_SLVADDRCFG)
25583 #define S_SLVALRTSET 2
25584 #define V_SLVALRTSET(x) ((x) << S_SLVALRTSET)
25585 #define F_SLVALRTSET V_SLVALRTSET(1U)
25587 #define S_SLVRESET 1
25588 #define V_SLVRESET(x) ((x) << S_SLVRESET)
25589 #define F_SLVRESET V_SLVRESET(1U)
25591 #define S_SLVCTLEN 0
25592 #define V_SLVCTLEN(x) ((x) << S_SLVCTLEN)
25593 #define F_SLVCTLEN V_SLVCTLEN(1U)
25595 #define A_SMB_SLV_CTL_STS 0x19080
25597 #define S_SLVFIFOTXCNT 12
25598 #define M_SLVFIFOTXCNT 0x3fU
25599 #define V_SLVFIFOTXCNT(x) ((x) << S_SLVFIFOTXCNT)
25600 #define G_SLVFIFOTXCNT(x) (((x) >> S_SLVFIFOTXCNT) & M_SLVFIFOTXCNT)
25602 #define S_SLVFIFOCNT 6
25603 #define M_SLVFIFOCNT 0x3fU
25604 #define V_SLVFIFOCNT(x) ((x) << S_SLVFIFOCNT)
25605 #define G_SLVFIFOCNT(x) (((x) >> S_SLVFIFOCNT) & M_SLVFIFOCNT)
25607 #define S_SLVALRTSTS 2
25608 #define V_SLVALRTSTS(x) ((x) << S_SLVALRTSTS)
25609 #define F_SLVALRTSTS V_SLVALRTSTS(1U)
25611 #define S_SLVBUSYSTS 0
25612 #define V_SLVBUSYSTS(x) ((x) << S_SLVBUSYSTS)
25613 #define F_SLVBUSYSTS V_SLVBUSYSTS(1U)
25615 #define A_SMB_SLV_FIFO_RDWR 0x19084
25616 #define A_SMB_INT_ENABLE 0x1908c
25618 #define S_MSTTXFIFOPAREN 21
25619 #define V_MSTTXFIFOPAREN(x) ((x) << S_MSTTXFIFOPAREN)
25620 #define F_MSTTXFIFOPAREN V_MSTTXFIFOPAREN(1U)
25622 #define S_MSTRXFIFOPAREN 20
25623 #define V_MSTRXFIFOPAREN(x) ((x) << S_MSTRXFIFOPAREN)
25624 #define F_MSTRXFIFOPAREN V_MSTRXFIFOPAREN(1U)
25626 #define S_SLVFIFOPAREN 19
25627 #define V_SLVFIFOPAREN(x) ((x) << S_SLVFIFOPAREN)
25628 #define F_SLVFIFOPAREN V_SLVFIFOPAREN(1U)
25630 #define S_SLVUNEXPBUSSTOPEN 18
25631 #define V_SLVUNEXPBUSSTOPEN(x) ((x) << S_SLVUNEXPBUSSTOPEN)
25632 #define F_SLVUNEXPBUSSTOPEN V_SLVUNEXPBUSSTOPEN(1U)
25634 #define S_SLVUNEXPBUSSTARTEN 17
25635 #define V_SLVUNEXPBUSSTARTEN(x) ((x) << S_SLVUNEXPBUSSTARTEN)
25636 #define F_SLVUNEXPBUSSTARTEN V_SLVUNEXPBUSSTARTEN(1U)
25638 #define S_SLVCOMMANDCODEINVEN 16
25639 #define V_SLVCOMMANDCODEINVEN(x) ((x) << S_SLVCOMMANDCODEINVEN)
25640 #define F_SLVCOMMANDCODEINVEN V_SLVCOMMANDCODEINVEN(1U)
25642 #define S_SLVBYTECNTERREN 15
25643 #define V_SLVBYTECNTERREN(x) ((x) << S_SLVBYTECNTERREN)
25644 #define F_SLVBYTECNTERREN V_SLVBYTECNTERREN(1U)
25646 #define S_SLVUNEXPACKMSTEN 14
25647 #define V_SLVUNEXPACKMSTEN(x) ((x) << S_SLVUNEXPACKMSTEN)
25648 #define F_SLVUNEXPACKMSTEN V_SLVUNEXPACKMSTEN(1U)
25650 #define S_SLVUNEXPNACKMSTEN 13
25651 #define V_SLVUNEXPNACKMSTEN(x) ((x) << S_SLVUNEXPNACKMSTEN)
25652 #define F_SLVUNEXPNACKMSTEN V_SLVUNEXPNACKMSTEN(1U)
25654 #define S_SLVNOBUSSTOPEN 12
25655 #define V_SLVNOBUSSTOPEN(x) ((x) << S_SLVNOBUSSTOPEN)
25656 #define F_SLVNOBUSSTOPEN V_SLVNOBUSSTOPEN(1U)
25658 #define S_SLVNOREPSTARTEN 11
25659 #define V_SLVNOREPSTARTEN(x) ((x) << S_SLVNOREPSTARTEN)
25660 #define F_SLVNOREPSTARTEN V_SLVNOREPSTARTEN(1U)
25662 #define S_SLVRXADDRINTEN 10
25663 #define V_SLVRXADDRINTEN(x) ((x) << S_SLVRXADDRINTEN)
25664 #define F_SLVRXADDRINTEN V_SLVRXADDRINTEN(1U)
25666 #define S_SLVRXPECERRINTEN 9
25667 #define V_SLVRXPECERRINTEN(x) ((x) << S_SLVRXPECERRINTEN)
25668 #define F_SLVRXPECERRINTEN V_SLVRXPECERRINTEN(1U)
25670 #define S_SLVPREPTOARPINTEN 8
25671 #define V_SLVPREPTOARPINTEN(x) ((x) << S_SLVPREPTOARPINTEN)
25672 #define F_SLVPREPTOARPINTEN V_SLVPREPTOARPINTEN(1U)
25674 #define S_SLVTIMEOUTINTEN 7
25675 #define V_SLVTIMEOUTINTEN(x) ((x) << S_SLVTIMEOUTINTEN)
25676 #define F_SLVTIMEOUTINTEN V_SLVTIMEOUTINTEN(1U)
25678 #define S_SLVERRINTEN 6
25679 #define V_SLVERRINTEN(x) ((x) << S_SLVERRINTEN)
25680 #define F_SLVERRINTEN V_SLVERRINTEN(1U)
25682 #define S_SLVDONEINTEN 5
25683 #define V_SLVDONEINTEN(x) ((x) << S_SLVDONEINTEN)
25684 #define F_SLVDONEINTEN V_SLVDONEINTEN(1U)
25686 #define S_SLVRXRDYINTEN 4
25687 #define V_SLVRXRDYINTEN(x) ((x) << S_SLVRXRDYINTEN)
25688 #define F_SLVRXRDYINTEN V_SLVRXRDYINTEN(1U)
25690 #define S_MSTTIMEOUTINTEN 3
25691 #define V_MSTTIMEOUTINTEN(x) ((x) << S_MSTTIMEOUTINTEN)
25692 #define F_MSTTIMEOUTINTEN V_MSTTIMEOUTINTEN(1U)
25694 #define S_MSTNACKINTEN 2
25695 #define V_MSTNACKINTEN(x) ((x) << S_MSTNACKINTEN)
25696 #define F_MSTNACKINTEN V_MSTNACKINTEN(1U)
25698 #define S_MSTLOSTARBINTEN 1
25699 #define V_MSTLOSTARBINTEN(x) ((x) << S_MSTLOSTARBINTEN)
25700 #define F_MSTLOSTARBINTEN V_MSTLOSTARBINTEN(1U)
25702 #define S_MSTDONEINTEN 0
25703 #define V_MSTDONEINTEN(x) ((x) << S_MSTDONEINTEN)
25704 #define F_MSTDONEINTEN V_MSTDONEINTEN(1U)
25706 #define A_SMB_INT_CAUSE 0x19090
25708 #define S_MSTTXFIFOPARINT 21
25709 #define V_MSTTXFIFOPARINT(x) ((x) << S_MSTTXFIFOPARINT)
25710 #define F_MSTTXFIFOPARINT V_MSTTXFIFOPARINT(1U)
25712 #define S_MSTRXFIFOPARINT 20
25713 #define V_MSTRXFIFOPARINT(x) ((x) << S_MSTRXFIFOPARINT)
25714 #define F_MSTRXFIFOPARINT V_MSTRXFIFOPARINT(1U)
25716 #define S_SLVFIFOPARINT 19
25717 #define V_SLVFIFOPARINT(x) ((x) << S_SLVFIFOPARINT)
25718 #define F_SLVFIFOPARINT V_SLVFIFOPARINT(1U)
25720 #define S_SLVUNEXPBUSSTOPINT 18
25721 #define V_SLVUNEXPBUSSTOPINT(x) ((x) << S_SLVUNEXPBUSSTOPINT)
25722 #define F_SLVUNEXPBUSSTOPINT V_SLVUNEXPBUSSTOPINT(1U)
25724 #define S_SLVUNEXPBUSSTARTINT 17
25725 #define V_SLVUNEXPBUSSTARTINT(x) ((x) << S_SLVUNEXPBUSSTARTINT)
25726 #define F_SLVUNEXPBUSSTARTINT V_SLVUNEXPBUSSTARTINT(1U)
25728 #define S_SLVCOMMANDCODEINVINT 16
25729 #define V_SLVCOMMANDCODEINVINT(x) ((x) << S_SLVCOMMANDCODEINVINT)
25730 #define F_SLVCOMMANDCODEINVINT V_SLVCOMMANDCODEINVINT(1U)
25732 #define S_SLVBYTECNTERRINT 15
25733 #define V_SLVBYTECNTERRINT(x) ((x) << S_SLVBYTECNTERRINT)
25734 #define F_SLVBYTECNTERRINT V_SLVBYTECNTERRINT(1U)
25736 #define S_SLVUNEXPACKMSTINT 14
25737 #define V_SLVUNEXPACKMSTINT(x) ((x) << S_SLVUNEXPACKMSTINT)
25738 #define F_SLVUNEXPACKMSTINT V_SLVUNEXPACKMSTINT(1U)
25740 #define S_SLVUNEXPNACKMSTINT 13
25741 #define V_SLVUNEXPNACKMSTINT(x) ((x) << S_SLVUNEXPNACKMSTINT)
25742 #define F_SLVUNEXPNACKMSTINT V_SLVUNEXPNACKMSTINT(1U)
25744 #define S_SLVNOBUSSTOPINT 12
25745 #define V_SLVNOBUSSTOPINT(x) ((x) << S_SLVNOBUSSTOPINT)
25746 #define F_SLVNOBUSSTOPINT V_SLVNOBUSSTOPINT(1U)
25748 #define S_SLVNOREPSTARTINT 11
25749 #define V_SLVNOREPSTARTINT(x) ((x) << S_SLVNOREPSTARTINT)
25750 #define F_SLVNOREPSTARTINT V_SLVNOREPSTARTINT(1U)
25752 #define S_SLVRXADDRINT 10
25753 #define V_SLVRXADDRINT(x) ((x) << S_SLVRXADDRINT)
25754 #define F_SLVRXADDRINT V_SLVRXADDRINT(1U)
25756 #define S_SLVRXPECERRINT 9
25757 #define V_SLVRXPECERRINT(x) ((x) << S_SLVRXPECERRINT)
25758 #define F_SLVRXPECERRINT V_SLVRXPECERRINT(1U)
25760 #define S_SLVPREPTOARPINT 8
25761 #define V_SLVPREPTOARPINT(x) ((x) << S_SLVPREPTOARPINT)
25762 #define F_SLVPREPTOARPINT V_SLVPREPTOARPINT(1U)
25764 #define S_SLVTIMEOUTINT 7
25765 #define V_SLVTIMEOUTINT(x) ((x) << S_SLVTIMEOUTINT)
25766 #define F_SLVTIMEOUTINT V_SLVTIMEOUTINT(1U)
25768 #define S_SLVERRINT 6
25769 #define V_SLVERRINT(x) ((x) << S_SLVERRINT)
25770 #define F_SLVERRINT V_SLVERRINT(1U)
25772 #define S_SLVDONEINT 5
25773 #define V_SLVDONEINT(x) ((x) << S_SLVDONEINT)
25774 #define F_SLVDONEINT V_SLVDONEINT(1U)
25776 #define S_SLVRXRDYINT 4
25777 #define V_SLVRXRDYINT(x) ((x) << S_SLVRXRDYINT)
25778 #define F_SLVRXRDYINT V_SLVRXRDYINT(1U)
25780 #define S_MSTTIMEOUTINT 3
25781 #define V_MSTTIMEOUTINT(x) ((x) << S_MSTTIMEOUTINT)
25782 #define F_MSTTIMEOUTINT V_MSTTIMEOUTINT(1U)
25784 #define S_MSTNACKINT 2
25785 #define V_MSTNACKINT(x) ((x) << S_MSTNACKINT)
25786 #define F_MSTNACKINT V_MSTNACKINT(1U)
25788 #define S_MSTLOSTARBINT 1
25789 #define V_MSTLOSTARBINT(x) ((x) << S_MSTLOSTARBINT)
25790 #define F_MSTLOSTARBINT V_MSTLOSTARBINT(1U)
25792 #define S_MSTDONEINT 0
25793 #define V_MSTDONEINT(x) ((x) << S_MSTDONEINT)
25794 #define F_MSTDONEINT V_MSTDONEINT(1U)
25796 #define A_SMB_DEBUG_DATA 0x19094
25798 #define S_DEBUGDATAH 16
25799 #define M_DEBUGDATAH 0xffffU
25800 #define V_DEBUGDATAH(x) ((x) << S_DEBUGDATAH)
25801 #define G_DEBUGDATAH(x) (((x) >> S_DEBUGDATAH) & M_DEBUGDATAH)
25803 #define S_DEBUGDATAL 0
25804 #define M_DEBUGDATAL 0xffffU
25805 #define V_DEBUGDATAL(x) ((x) << S_DEBUGDATAL)
25806 #define G_DEBUGDATAL(x) (((x) >> S_DEBUGDATAL) & M_DEBUGDATAL)
25808 #define A_SMB_PERR_EN 0x19098
25810 #define S_MSTTXFIFOPERREN 2
25811 #define V_MSTTXFIFOPERREN(x) ((x) << S_MSTTXFIFOPERREN)
25812 #define F_MSTTXFIFOPERREN V_MSTTXFIFOPERREN(1U)
25814 #define S_MSTRXFIFOPERREN 1
25815 #define V_MSTRXFIFOPERREN(x) ((x) << S_MSTRXFIFOPERREN)
25816 #define F_MSTRXFIFOPERREN V_MSTRXFIFOPERREN(1U)
25818 #define S_SLVFIFOPERREN 0
25819 #define V_SLVFIFOPERREN(x) ((x) << S_SLVFIFOPERREN)
25820 #define F_SLVFIFOPERREN V_SLVFIFOPERREN(1U)
25822 #define S_MSTTXFIFO 21
25823 #define V_MSTTXFIFO(x) ((x) << S_MSTTXFIFO)
25824 #define F_MSTTXFIFO V_MSTTXFIFO(1U)
25826 #define S_MSTRXFIFO 19
25827 #define V_MSTRXFIFO(x) ((x) << S_MSTRXFIFO)
25828 #define F_MSTRXFIFO V_MSTRXFIFO(1U)
25830 #define S_SLVFIFO 18
25831 #define V_SLVFIFO(x) ((x) << S_SLVFIFO)
25832 #define F_SLVFIFO V_SLVFIFO(1U)
25834 #define A_SMB_PERR_INJ 0x1909c
25836 #define S_MSTTXINJDATAERR 3
25837 #define V_MSTTXINJDATAERR(x) ((x) << S_MSTTXINJDATAERR)
25838 #define F_MSTTXINJDATAERR V_MSTTXINJDATAERR(1U)
25840 #define S_MSTRXINJDATAERR 2
25841 #define V_MSTRXINJDATAERR(x) ((x) << S_MSTRXINJDATAERR)
25842 #define F_MSTRXINJDATAERR V_MSTRXINJDATAERR(1U)
25844 #define S_SLVINJDATAERR 1
25845 #define V_SLVINJDATAERR(x) ((x) << S_SLVINJDATAERR)
25846 #define F_SLVINJDATAERR V_SLVINJDATAERR(1U)
25848 #define S_FIFOINJDATAERREN 0
25849 #define V_FIFOINJDATAERREN(x) ((x) << S_FIFOINJDATAERREN)
25850 #define F_FIFOINJDATAERREN V_FIFOINJDATAERREN(1U)
25852 #define A_SMB_SLV_ARP_CTL 0x190a0
25854 #define S_ARPCOMMANDCODE 2
25855 #define M_ARPCOMMANDCODE 0xffU
25856 #define V_ARPCOMMANDCODE(x) ((x) << S_ARPCOMMANDCODE)
25857 #define G_ARPCOMMANDCODE(x) (((x) >> S_ARPCOMMANDCODE) & M_ARPCOMMANDCODE)
25859 #define S_ARPADDRRES 1
25860 #define V_ARPADDRRES(x) ((x) << S_ARPADDRRES)
25861 #define F_ARPADDRRES V_ARPADDRRES(1U)
25863 #define S_ARPADDRVAL 0
25864 #define V_ARPADDRVAL(x) ((x) << S_ARPADDRVAL)
25865 #define F_ARPADDRVAL V_ARPADDRVAL(1U)
25867 #define A_SMB_ARP_UDID0 0x190a4
25868 #define A_SMB_ARP_UDID1 0x190a8
25870 #define S_SUBSYSTEMVENDORID 16
25871 #define M_SUBSYSTEMVENDORID 0xffffU
25872 #define V_SUBSYSTEMVENDORID(x) ((x) << S_SUBSYSTEMVENDORID)
25873 #define G_SUBSYSTEMVENDORID(x) (((x) >> S_SUBSYSTEMVENDORID) & M_SUBSYSTEMVENDORID)
25875 #define S_SUBSYSTEMDEVICEID 0
25876 #define M_SUBSYSTEMDEVICEID 0xffffU
25877 #define V_SUBSYSTEMDEVICEID(x) ((x) << S_SUBSYSTEMDEVICEID)
25878 #define G_SUBSYSTEMDEVICEID(x) (((x) >> S_SUBSYSTEMDEVICEID) & M_SUBSYSTEMDEVICEID)
25880 #define A_SMB_ARP_UDID2 0x190ac
25882 #define S_DEVICEID 16
25883 #define M_DEVICEID 0xffffU
25884 #define V_DEVICEID(x) ((x) << S_DEVICEID)
25885 #define G_DEVICEID(x) (((x) >> S_DEVICEID) & M_DEVICEID)
25887 #define S_INTERFACE 0
25888 #define M_INTERFACE 0xffffU
25889 #define V_INTERFACE(x) ((x) << S_INTERFACE)
25890 #define G_INTERFACE(x) (((x) >> S_INTERFACE) & M_INTERFACE)
25892 #define A_SMB_ARP_UDID3 0x190b0
25894 #define S_DEVICECAP 24
25895 #define M_DEVICECAP 0xffU
25896 #define V_DEVICECAP(x) ((x) << S_DEVICECAP)
25897 #define G_DEVICECAP(x) (((x) >> S_DEVICECAP) & M_DEVICECAP)
25899 #define S_VERSIONID 16
25900 #define M_VERSIONID 0xffU
25901 #define V_VERSIONID(x) ((x) << S_VERSIONID)
25902 #define G_VERSIONID(x) (((x) >> S_VERSIONID) & M_VERSIONID)
25904 #define S_VENDORID 0
25905 #define M_VENDORID 0xffffU
25906 #define V_VENDORID(x) ((x) << S_VENDORID)
25907 #define G_VENDORID(x) (((x) >> S_VENDORID) & M_VENDORID)
25909 #define A_SMB_SLV_AUX_ADDR0 0x190b4
25911 #define S_AUXADDR0VAL 6
25912 #define V_AUXADDR0VAL(x) ((x) << S_AUXADDR0VAL)
25913 #define F_AUXADDR0VAL V_AUXADDR0VAL(1U)
25915 #define S_AUXADDR0 0
25916 #define M_AUXADDR0 0x3fU
25917 #define V_AUXADDR0(x) ((x) << S_AUXADDR0)
25918 #define G_AUXADDR0(x) (((x) >> S_AUXADDR0) & M_AUXADDR0)
25920 #define A_SMB_SLV_AUX_ADDR1 0x190b8
25922 #define S_AUXADDR1VAL 6
25923 #define V_AUXADDR1VAL(x) ((x) << S_AUXADDR1VAL)
25924 #define F_AUXADDR1VAL V_AUXADDR1VAL(1U)
25926 #define S_AUXADDR1 0
25927 #define M_AUXADDR1 0x3fU
25928 #define V_AUXADDR1(x) ((x) << S_AUXADDR1)
25929 #define G_AUXADDR1(x) (((x) >> S_AUXADDR1) & M_AUXADDR1)
25931 #define A_SMB_SLV_AUX_ADDR2 0x190bc
25933 #define S_AUXADDR2VAL 6
25934 #define V_AUXADDR2VAL(x) ((x) << S_AUXADDR2VAL)
25935 #define F_AUXADDR2VAL V_AUXADDR2VAL(1U)
25937 #define S_AUXADDR2 0
25938 #define M_AUXADDR2 0x3fU
25939 #define V_AUXADDR2(x) ((x) << S_AUXADDR2)
25940 #define G_AUXADDR2(x) (((x) >> S_AUXADDR2) & M_AUXADDR2)
25942 #define A_SMB_SLV_AUX_ADDR3 0x190c0
25944 #define S_AUXADDR3VAL 6
25945 #define V_AUXADDR3VAL(x) ((x) << S_AUXADDR3VAL)
25946 #define F_AUXADDR3VAL V_AUXADDR3VAL(1U)
25948 #define S_AUXADDR3 0
25949 #define M_AUXADDR3 0x3fU
25950 #define V_AUXADDR3(x) ((x) << S_AUXADDR3)
25951 #define G_AUXADDR3(x) (((x) >> S_AUXADDR3) & M_AUXADDR3)
25953 #define A_SMB_COMMAND_CODE0 0x190c4
25955 #define S_SMBUSCOMMANDCODE0 0
25956 #define M_SMBUSCOMMANDCODE0 0xffU
25957 #define V_SMBUSCOMMANDCODE0(x) ((x) << S_SMBUSCOMMANDCODE0)
25958 #define G_SMBUSCOMMANDCODE0(x) (((x) >> S_SMBUSCOMMANDCODE0) & M_SMBUSCOMMANDCODE0)
25960 #define A_SMB_COMMAND_CODE1 0x190c8
25962 #define S_SMBUSCOMMANDCODE1 0
25963 #define M_SMBUSCOMMANDCODE1 0xffU
25964 #define V_SMBUSCOMMANDCODE1(x) ((x) << S_SMBUSCOMMANDCODE1)
25965 #define G_SMBUSCOMMANDCODE1(x) (((x) >> S_SMBUSCOMMANDCODE1) & M_SMBUSCOMMANDCODE1)
25967 #define A_SMB_COMMAND_CODE2 0x190cc
25969 #define S_SMBUSCOMMANDCODE2 0
25970 #define M_SMBUSCOMMANDCODE2 0xffU
25971 #define V_SMBUSCOMMANDCODE2(x) ((x) << S_SMBUSCOMMANDCODE2)
25972 #define G_SMBUSCOMMANDCODE2(x) (((x) >> S_SMBUSCOMMANDCODE2) & M_SMBUSCOMMANDCODE2)
25974 #define A_SMB_COMMAND_CODE3 0x190d0
25976 #define S_SMBUSCOMMANDCODE3 0
25977 #define M_SMBUSCOMMANDCODE3 0xffU
25978 #define V_SMBUSCOMMANDCODE3(x) ((x) << S_SMBUSCOMMANDCODE3)
25979 #define G_SMBUSCOMMANDCODE3(x) (((x) >> S_SMBUSCOMMANDCODE3) & M_SMBUSCOMMANDCODE3)
25981 #define A_SMB_COMMAND_CODE4 0x190d4
25983 #define S_SMBUSCOMMANDCODE4 0
25984 #define M_SMBUSCOMMANDCODE4 0xffU
25985 #define V_SMBUSCOMMANDCODE4(x) ((x) << S_SMBUSCOMMANDCODE4)
25986 #define G_SMBUSCOMMANDCODE4(x) (((x) >> S_SMBUSCOMMANDCODE4) & M_SMBUSCOMMANDCODE4)
25988 #define A_SMB_COMMAND_CODE5 0x190d8
25990 #define S_SMBUSCOMMANDCODE5 0
25991 #define M_SMBUSCOMMANDCODE5 0xffU
25992 #define V_SMBUSCOMMANDCODE5(x) ((x) << S_SMBUSCOMMANDCODE5)
25993 #define G_SMBUSCOMMANDCODE5(x) (((x) >> S_SMBUSCOMMANDCODE5) & M_SMBUSCOMMANDCODE5)
25995 #define A_SMB_COMMAND_CODE6 0x190dc
25997 #define S_SMBUSCOMMANDCODE6 0
25998 #define M_SMBUSCOMMANDCODE6 0xffU
25999 #define V_SMBUSCOMMANDCODE6(x) ((x) << S_SMBUSCOMMANDCODE6)
26000 #define G_SMBUSCOMMANDCODE6(x) (((x) >> S_SMBUSCOMMANDCODE6) & M_SMBUSCOMMANDCODE6)
26002 #define A_SMB_COMMAND_CODE7 0x190e0
26004 #define S_SMBUSCOMMANDCODE7 0
26005 #define M_SMBUSCOMMANDCODE7 0xffU
26006 #define V_SMBUSCOMMANDCODE7(x) ((x) << S_SMBUSCOMMANDCODE7)
26007 #define G_SMBUSCOMMANDCODE7(x) (((x) >> S_SMBUSCOMMANDCODE7) & M_SMBUSCOMMANDCODE7)
26009 #define A_SMB_MICRO_CNT_CLK_CFG 0x190e4
26011 #define S_MACROCNTCLKCFG 8
26012 #define M_MACROCNTCLKCFG 0x1fU
26013 #define V_MACROCNTCLKCFG(x) ((x) << S_MACROCNTCLKCFG)
26014 #define G_MACROCNTCLKCFG(x) (((x) >> S_MACROCNTCLKCFG) & M_MACROCNTCLKCFG)
26016 #define S_MICROCNTCLKCFG 0
26017 #define M_MICROCNTCLKCFG 0xffU
26018 #define V_MICROCNTCLKCFG(x) ((x) << S_MICROCNTCLKCFG)
26019 #define G_MICROCNTCLKCFG(x) (((x) >> S_MICROCNTCLKCFG) & M_MICROCNTCLKCFG)
26021 #define A_SMB_CTL_STATUS 0x190e8
26023 #define S_MSTBUSBUSY 2
26024 #define V_MSTBUSBUSY(x) ((x) << S_MSTBUSBUSY)
26025 #define F_MSTBUSBUSY V_MSTBUSBUSY(1U)
26027 #define S_SLVBUSBUSY 1
26028 #define V_SLVBUSBUSY(x) ((x) << S_SLVBUSBUSY)
26029 #define F_SLVBUSBUSY V_SLVBUSBUSY(1U)
26031 #define S_BUSBUSY 0
26032 #define V_BUSBUSY(x) ((x) << S_BUSBUSY)
26033 #define F_BUSBUSY V_BUSBUSY(1U)
26035 /* registers for module I2CM */
26036 #define I2CM_BASE_ADDR 0x190f0
26038 #define A_I2CM_CFG 0x190f0
26040 #define S_I2C_CLKDIV 0
26041 #define M_I2C_CLKDIV 0xfffU
26042 #define V_I2C_CLKDIV(x) ((x) << S_I2C_CLKDIV)
26043 #define G_I2C_CLKDIV(x) (((x) >> S_I2C_CLKDIV) & M_I2C_CLKDIV)
26045 #define S_I2C_CLKDIV16B 0
26046 #define M_I2C_CLKDIV16B 0xffffU
26047 #define V_I2C_CLKDIV16B(x) ((x) << S_I2C_CLKDIV16B)
26048 #define G_I2C_CLKDIV16B(x) (((x) >> S_I2C_CLKDIV16B) & M_I2C_CLKDIV16B)
26050 #define A_I2CM_DATA 0x190f4
26052 #define S_I2C_DATA 0
26053 #define M_I2C_DATA 0xffU
26054 #define V_I2C_DATA(x) ((x) << S_I2C_DATA)
26055 #define G_I2C_DATA(x) (((x) >> S_I2C_DATA) & M_I2C_DATA)
26057 #define A_I2CM_OP 0x190f8
26059 #define S_I2C_ACK 30
26060 #define V_I2C_ACK(x) ((x) << S_I2C_ACK)
26061 #define F_I2C_ACK V_I2C_ACK(1U)
26063 #define S_I2C_CONT 1
26064 #define V_I2C_CONT(x) ((x) << S_I2C_CONT)
26065 #define F_I2C_CONT V_I2C_CONT(1U)
26068 #define V_OP(x) ((x) << S_OP)
26069 #define F_OP V_OP(1U)
26071 /* registers for module MI */
26072 #define MI_BASE_ADDR 0x19100
26074 #define A_MI_CFG 0x19100
26077 #define V_T4_ST(x) ((x) << S_T4_ST)
26078 #define F_T4_ST V_T4_ST(1U)
26081 #define M_CLKDIV 0xffU
26082 #define V_CLKDIV(x) ((x) << S_CLKDIV)
26083 #define G_CLKDIV(x) (((x) >> S_CLKDIV) & M_CLKDIV)
26087 #define V_ST(x) ((x) << S_ST)
26088 #define G_ST(x) (((x) >> S_ST) & M_ST)
26091 #define V_PREEN(x) ((x) << S_PREEN)
26092 #define F_PREEN V_PREEN(1U)
26095 #define V_MDIINV(x) ((x) << S_MDIINV)
26096 #define F_MDIINV V_MDIINV(1U)
26098 #define S_MDIO_1P2V_SEL 0
26099 #define V_MDIO_1P2V_SEL(x) ((x) << S_MDIO_1P2V_SEL)
26100 #define F_MDIO_1P2V_SEL V_MDIO_1P2V_SEL(1U)
26102 #define A_MI_ADDR 0x19104
26104 #define S_PHYADDR 5
26105 #define M_PHYADDR 0x1fU
26106 #define V_PHYADDR(x) ((x) << S_PHYADDR)
26107 #define G_PHYADDR(x) (((x) >> S_PHYADDR) & M_PHYADDR)
26109 #define S_REGADDR 0
26110 #define M_REGADDR 0x1fU
26111 #define V_REGADDR(x) ((x) << S_REGADDR)
26112 #define G_REGADDR(x) (((x) >> S_REGADDR) & M_REGADDR)
26114 #define A_MI_DATA 0x19108
26116 #define S_MDIDATA 0
26117 #define M_MDIDATA 0xffffU
26118 #define V_MDIDATA(x) ((x) << S_MDIDATA)
26119 #define G_MDIDATA(x) (((x) >> S_MDIDATA) & M_MDIDATA)
26121 #define A_MI_OP 0x1910c
26124 #define V_INC(x) ((x) << S_INC)
26125 #define F_INC V_INC(1U)
26128 #define M_MDIOP 0x3U
26129 #define V_MDIOP(x) ((x) << S_MDIOP)
26130 #define G_MDIOP(x) (((x) >> S_MDIOP) & M_MDIOP)
26132 /* registers for module UART */
26133 #define UART_BASE_ADDR 0x19110
26135 #define A_UART_CONFIG 0x19110
26137 #define S_STOPBITS 22
26138 #define M_STOPBITS 0x3U
26139 #define V_STOPBITS(x) ((x) << S_STOPBITS)
26140 #define G_STOPBITS(x) (((x) >> S_STOPBITS) & M_STOPBITS)
26142 #define S_PARITY 20
26143 #define M_PARITY 0x3U
26144 #define V_PARITY(x) ((x) << S_PARITY)
26145 #define G_PARITY(x) (((x) >> S_PARITY) & M_PARITY)
26147 #define S_DATABITS 16
26148 #define M_DATABITS 0xfU
26149 #define V_DATABITS(x) ((x) << S_DATABITS)
26150 #define G_DATABITS(x) (((x) >> S_DATABITS) & M_DATABITS)
26152 #define S_UART_CLKDIV 0
26153 #define M_UART_CLKDIV 0xfffU
26154 #define V_UART_CLKDIV(x) ((x) << S_UART_CLKDIV)
26155 #define G_UART_CLKDIV(x) (((x) >> S_UART_CLKDIV) & M_UART_CLKDIV)
26157 /* registers for module PMU */
26158 #define PMU_BASE_ADDR 0x19120
26160 #define A_PMU_PART_CG_PWRMODE 0x19120
26162 #define S_TPPARTCGEN 14
26163 #define V_TPPARTCGEN(x) ((x) << S_TPPARTCGEN)
26164 #define F_TPPARTCGEN V_TPPARTCGEN(1U)
26166 #define S_PDPPARTCGEN 13
26167 #define V_PDPPARTCGEN(x) ((x) << S_PDPPARTCGEN)
26168 #define F_PDPPARTCGEN V_PDPPARTCGEN(1U)
26170 #define S_PCIEPARTCGEN 12
26171 #define V_PCIEPARTCGEN(x) ((x) << S_PCIEPARTCGEN)
26172 #define F_PCIEPARTCGEN V_PCIEPARTCGEN(1U)
26174 #define S_EDC1PARTCGEN 11
26175 #define V_EDC1PARTCGEN(x) ((x) << S_EDC1PARTCGEN)
26176 #define F_EDC1PARTCGEN V_EDC1PARTCGEN(1U)
26178 #define S_MCPARTCGEN 10
26179 #define V_MCPARTCGEN(x) ((x) << S_MCPARTCGEN)
26180 #define F_MCPARTCGEN V_MCPARTCGEN(1U)
26182 #define S_EDC0PARTCGEN 9
26183 #define V_EDC0PARTCGEN(x) ((x) << S_EDC0PARTCGEN)
26184 #define F_EDC0PARTCGEN V_EDC0PARTCGEN(1U)
26186 #define S_LEPARTCGEN 8
26187 #define V_LEPARTCGEN(x) ((x) << S_LEPARTCGEN)
26188 #define F_LEPARTCGEN V_LEPARTCGEN(1U)
26190 #define S_INITPOWERMODE 0
26191 #define M_INITPOWERMODE 0x3U
26192 #define V_INITPOWERMODE(x) ((x) << S_INITPOWERMODE)
26193 #define G_INITPOWERMODE(x) (((x) >> S_INITPOWERMODE) & M_INITPOWERMODE)
26195 #define S_SGE_PART_CGEN 19
26196 #define V_SGE_PART_CGEN(x) ((x) << S_SGE_PART_CGEN)
26197 #define F_SGE_PART_CGEN V_SGE_PART_CGEN(1U)
26199 #define S_PDP_PART_CGEN 18
26200 #define V_PDP_PART_CGEN(x) ((x) << S_PDP_PART_CGEN)
26201 #define F_PDP_PART_CGEN V_PDP_PART_CGEN(1U)
26203 #define S_TP_PART_CGEN 17
26204 #define V_TP_PART_CGEN(x) ((x) << S_TP_PART_CGEN)
26205 #define F_TP_PART_CGEN V_TP_PART_CGEN(1U)
26207 #define S_EDC0_PART_CGEN 16
26208 #define V_EDC0_PART_CGEN(x) ((x) << S_EDC0_PART_CGEN)
26209 #define F_EDC0_PART_CGEN V_EDC0_PART_CGEN(1U)
26211 #define S_EDC1_PART_CGEN 15
26212 #define V_EDC1_PART_CGEN(x) ((x) << S_EDC1_PART_CGEN)
26213 #define F_EDC1_PART_CGEN V_EDC1_PART_CGEN(1U)
26215 #define S_LE_PART_CGEN 14
26216 #define V_LE_PART_CGEN(x) ((x) << S_LE_PART_CGEN)
26217 #define F_LE_PART_CGEN V_LE_PART_CGEN(1U)
26219 #define S_MA_PART_CGEN 13
26220 #define V_MA_PART_CGEN(x) ((x) << S_MA_PART_CGEN)
26221 #define F_MA_PART_CGEN V_MA_PART_CGEN(1U)
26223 #define S_MC0_PART_CGEN 12
26224 #define V_MC0_PART_CGEN(x) ((x) << S_MC0_PART_CGEN)
26225 #define F_MC0_PART_CGEN V_MC0_PART_CGEN(1U)
26227 #define S_MC1_PART_CGEN 11
26228 #define V_MC1_PART_CGEN(x) ((x) << S_MC1_PART_CGEN)
26229 #define F_MC1_PART_CGEN V_MC1_PART_CGEN(1U)
26231 #define S_PCIE_PART_CGEN 10
26232 #define V_PCIE_PART_CGEN(x) ((x) << S_PCIE_PART_CGEN)
26233 #define F_PCIE_PART_CGEN V_PCIE_PART_CGEN(1U)
26235 #define A_PMU_SLEEPMODE_WAKEUP 0x19124
26237 #define S_HWWAKEUPEN 5
26238 #define V_HWWAKEUPEN(x) ((x) << S_HWWAKEUPEN)
26239 #define F_HWWAKEUPEN V_HWWAKEUPEN(1U)
26241 #define S_PORT3SLEEPMODE 4
26242 #define V_PORT3SLEEPMODE(x) ((x) << S_PORT3SLEEPMODE)
26243 #define F_PORT3SLEEPMODE V_PORT3SLEEPMODE(1U)
26245 #define S_PORT2SLEEPMODE 3
26246 #define V_PORT2SLEEPMODE(x) ((x) << S_PORT2SLEEPMODE)
26247 #define F_PORT2SLEEPMODE V_PORT2SLEEPMODE(1U)
26249 #define S_PORT1SLEEPMODE 2
26250 #define V_PORT1SLEEPMODE(x) ((x) << S_PORT1SLEEPMODE)
26251 #define F_PORT1SLEEPMODE V_PORT1SLEEPMODE(1U)
26253 #define S_PORT0SLEEPMODE 1
26254 #define V_PORT0SLEEPMODE(x) ((x) << S_PORT0SLEEPMODE)
26255 #define F_PORT0SLEEPMODE V_PORT0SLEEPMODE(1U)
26258 #define V_WAKEUP(x) ((x) << S_WAKEUP)
26259 #define F_WAKEUP V_WAKEUP(1U)
26261 #define S_GLOBALDEEPSLEEPEN 6
26262 #define V_GLOBALDEEPSLEEPEN(x) ((x) << S_GLOBALDEEPSLEEPEN)
26263 #define F_GLOBALDEEPSLEEPEN V_GLOBALDEEPSLEEPEN(1U)
26265 /* registers for module ULP_RX */
26266 #define ULP_RX_BASE_ADDR 0x19150
26268 #define A_ULP_RX_CTL 0x19150
26270 #define S_PCMD1THRESHOLD 24
26271 #define M_PCMD1THRESHOLD 0xffU
26272 #define V_PCMD1THRESHOLD(x) ((x) << S_PCMD1THRESHOLD)
26273 #define G_PCMD1THRESHOLD(x) (((x) >> S_PCMD1THRESHOLD) & M_PCMD1THRESHOLD)
26275 #define S_PCMD0THRESHOLD 16
26276 #define M_PCMD0THRESHOLD 0xffU
26277 #define V_PCMD0THRESHOLD(x) ((x) << S_PCMD0THRESHOLD)
26278 #define G_PCMD0THRESHOLD(x) (((x) >> S_PCMD0THRESHOLD) & M_PCMD0THRESHOLD)
26280 #define S_DISABLE_0B_STAG_ERR 14
26281 #define V_DISABLE_0B_STAG_ERR(x) ((x) << S_DISABLE_0B_STAG_ERR)
26282 #define F_DISABLE_0B_STAG_ERR V_DISABLE_0B_STAG_ERR(1U)
26284 #define S_RDMA_0B_WR_OPCODE 10
26285 #define M_RDMA_0B_WR_OPCODE 0xfU
26286 #define V_RDMA_0B_WR_OPCODE(x) ((x) << S_RDMA_0B_WR_OPCODE)
26287 #define G_RDMA_0B_WR_OPCODE(x) (((x) >> S_RDMA_0B_WR_OPCODE) & M_RDMA_0B_WR_OPCODE)
26289 #define S_RDMA_0B_WR_PASS 9
26290 #define V_RDMA_0B_WR_PASS(x) ((x) << S_RDMA_0B_WR_PASS)
26291 #define F_RDMA_0B_WR_PASS V_RDMA_0B_WR_PASS(1U)
26293 #define S_STAG_RQE 8
26294 #define V_STAG_RQE(x) ((x) << S_STAG_RQE)
26295 #define F_STAG_RQE V_STAG_RQE(1U)
26297 #define S_RDMA_STATE_EN 7
26298 #define V_RDMA_STATE_EN(x) ((x) << S_RDMA_STATE_EN)
26299 #define F_RDMA_STATE_EN V_RDMA_STATE_EN(1U)
26301 #define S_CRC1_EN 6
26302 #define V_CRC1_EN(x) ((x) << S_CRC1_EN)
26303 #define F_CRC1_EN V_CRC1_EN(1U)
26305 #define S_RDMA_0B_WR_CQE 5
26306 #define V_RDMA_0B_WR_CQE(x) ((x) << S_RDMA_0B_WR_CQE)
26307 #define F_RDMA_0B_WR_CQE V_RDMA_0B_WR_CQE(1U)
26309 #define S_PCIE_ATRB_EN 4
26310 #define V_PCIE_ATRB_EN(x) ((x) << S_PCIE_ATRB_EN)
26311 #define F_PCIE_ATRB_EN V_PCIE_ATRB_EN(1U)
26313 #define S_RDMA_PERMISSIVE_MODE 3
26314 #define V_RDMA_PERMISSIVE_MODE(x) ((x) << S_RDMA_PERMISSIVE_MODE)
26315 #define F_RDMA_PERMISSIVE_MODE V_RDMA_PERMISSIVE_MODE(1U)
26317 #define S_PAGEPODME 2
26318 #define V_PAGEPODME(x) ((x) << S_PAGEPODME)
26319 #define F_PAGEPODME V_PAGEPODME(1U)
26321 #define S_ISCSITAGTCB 1
26322 #define V_ISCSITAGTCB(x) ((x) << S_ISCSITAGTCB)
26323 #define F_ISCSITAGTCB V_ISCSITAGTCB(1U)
26325 #define S_TDDPTAGTCB 0
26326 #define V_TDDPTAGTCB(x) ((x) << S_TDDPTAGTCB)
26327 #define F_TDDPTAGTCB V_TDDPTAGTCB(1U)
26329 #define A_ULP_RX_INT_ENABLE 0x19154
26331 #define S_ENABLE_CTX_1 24
26332 #define V_ENABLE_CTX_1(x) ((x) << S_ENABLE_CTX_1)
26333 #define F_ENABLE_CTX_1 V_ENABLE_CTX_1(1U)
26335 #define S_ENABLE_CTX_0 23
26336 #define V_ENABLE_CTX_0(x) ((x) << S_ENABLE_CTX_0)
26337 #define F_ENABLE_CTX_0 V_ENABLE_CTX_0(1U)
26339 #define S_ENABLE_FF 22
26340 #define V_ENABLE_FF(x) ((x) << S_ENABLE_FF)
26341 #define F_ENABLE_FF V_ENABLE_FF(1U)
26343 #define S_ENABLE_APF_1 21
26344 #define V_ENABLE_APF_1(x) ((x) << S_ENABLE_APF_1)
26345 #define F_ENABLE_APF_1 V_ENABLE_APF_1(1U)
26347 #define S_ENABLE_APF_0 20
26348 #define V_ENABLE_APF_0(x) ((x) << S_ENABLE_APF_0)
26349 #define F_ENABLE_APF_0 V_ENABLE_APF_0(1U)
26351 #define S_ENABLE_AF_1 19
26352 #define V_ENABLE_AF_1(x) ((x) << S_ENABLE_AF_1)
26353 #define F_ENABLE_AF_1 V_ENABLE_AF_1(1U)
26355 #define S_ENABLE_AF_0 18
26356 #define V_ENABLE_AF_0(x) ((x) << S_ENABLE_AF_0)
26357 #define F_ENABLE_AF_0 V_ENABLE_AF_0(1U)
26359 #define S_ENABLE_DDPDF_1 17
26360 #define V_ENABLE_DDPDF_1(x) ((x) << S_ENABLE_DDPDF_1)
26361 #define F_ENABLE_DDPDF_1 V_ENABLE_DDPDF_1(1U)
26363 #define S_ENABLE_DDPMF_1 16
26364 #define V_ENABLE_DDPMF_1(x) ((x) << S_ENABLE_DDPMF_1)
26365 #define F_ENABLE_DDPMF_1 V_ENABLE_DDPMF_1(1U)
26367 #define S_ENABLE_MEMRF_1 15
26368 #define V_ENABLE_MEMRF_1(x) ((x) << S_ENABLE_MEMRF_1)
26369 #define F_ENABLE_MEMRF_1 V_ENABLE_MEMRF_1(1U)
26371 #define S_ENABLE_PRSDF_1 14
26372 #define V_ENABLE_PRSDF_1(x) ((x) << S_ENABLE_PRSDF_1)
26373 #define F_ENABLE_PRSDF_1 V_ENABLE_PRSDF_1(1U)
26375 #define S_ENABLE_DDPDF_0 13
26376 #define V_ENABLE_DDPDF_0(x) ((x) << S_ENABLE_DDPDF_0)
26377 #define F_ENABLE_DDPDF_0 V_ENABLE_DDPDF_0(1U)
26379 #define S_ENABLE_DDPMF_0 12
26380 #define V_ENABLE_DDPMF_0(x) ((x) << S_ENABLE_DDPMF_0)
26381 #define F_ENABLE_DDPMF_0 V_ENABLE_DDPMF_0(1U)
26383 #define S_ENABLE_MEMRF_0 11
26384 #define V_ENABLE_MEMRF_0(x) ((x) << S_ENABLE_MEMRF_0)
26385 #define F_ENABLE_MEMRF_0 V_ENABLE_MEMRF_0(1U)
26387 #define S_ENABLE_PRSDF_0 10
26388 #define V_ENABLE_PRSDF_0(x) ((x) << S_ENABLE_PRSDF_0)
26389 #define F_ENABLE_PRSDF_0 V_ENABLE_PRSDF_0(1U)
26391 #define S_ENABLE_PCMDF_1 9
26392 #define V_ENABLE_PCMDF_1(x) ((x) << S_ENABLE_PCMDF_1)
26393 #define F_ENABLE_PCMDF_1 V_ENABLE_PCMDF_1(1U)
26395 #define S_ENABLE_TPTCF_1 8
26396 #define V_ENABLE_TPTCF_1(x) ((x) << S_ENABLE_TPTCF_1)
26397 #define F_ENABLE_TPTCF_1 V_ENABLE_TPTCF_1(1U)
26399 #define S_ENABLE_DDPCF_1 7
26400 #define V_ENABLE_DDPCF_1(x) ((x) << S_ENABLE_DDPCF_1)
26401 #define F_ENABLE_DDPCF_1 V_ENABLE_DDPCF_1(1U)
26403 #define S_ENABLE_MPARF_1 6
26404 #define V_ENABLE_MPARF_1(x) ((x) << S_ENABLE_MPARF_1)
26405 #define F_ENABLE_MPARF_1 V_ENABLE_MPARF_1(1U)
26407 #define S_ENABLE_MPARC_1 5
26408 #define V_ENABLE_MPARC_1(x) ((x) << S_ENABLE_MPARC_1)
26409 #define F_ENABLE_MPARC_1 V_ENABLE_MPARC_1(1U)
26411 #define S_ENABLE_PCMDF_0 4
26412 #define V_ENABLE_PCMDF_0(x) ((x) << S_ENABLE_PCMDF_0)
26413 #define F_ENABLE_PCMDF_0 V_ENABLE_PCMDF_0(1U)
26415 #define S_ENABLE_TPTCF_0 3
26416 #define V_ENABLE_TPTCF_0(x) ((x) << S_ENABLE_TPTCF_0)
26417 #define F_ENABLE_TPTCF_0 V_ENABLE_TPTCF_0(1U)
26419 #define S_ENABLE_DDPCF_0 2
26420 #define V_ENABLE_DDPCF_0(x) ((x) << S_ENABLE_DDPCF_0)
26421 #define F_ENABLE_DDPCF_0 V_ENABLE_DDPCF_0(1U)
26423 #define S_ENABLE_MPARF_0 1
26424 #define V_ENABLE_MPARF_0(x) ((x) << S_ENABLE_MPARF_0)
26425 #define F_ENABLE_MPARF_0 V_ENABLE_MPARF_0(1U)
26427 #define S_ENABLE_MPARC_0 0
26428 #define V_ENABLE_MPARC_0(x) ((x) << S_ENABLE_MPARC_0)
26429 #define F_ENABLE_MPARC_0 V_ENABLE_MPARC_0(1U)
26431 #define S_SE_CNT_MISMATCH_1 26
26432 #define V_SE_CNT_MISMATCH_1(x) ((x) << S_SE_CNT_MISMATCH_1)
26433 #define F_SE_CNT_MISMATCH_1 V_SE_CNT_MISMATCH_1(1U)
26435 #define S_SE_CNT_MISMATCH_0 25
26436 #define V_SE_CNT_MISMATCH_0(x) ((x) << S_SE_CNT_MISMATCH_0)
26437 #define F_SE_CNT_MISMATCH_0 V_SE_CNT_MISMATCH_0(1U)
26439 #define A_ULP_RX_INT_CAUSE 0x19158
26441 #define S_CAUSE_CTX_1 24
26442 #define V_CAUSE_CTX_1(x) ((x) << S_CAUSE_CTX_1)
26443 #define F_CAUSE_CTX_1 V_CAUSE_CTX_1(1U)
26445 #define S_CAUSE_CTX_0 23
26446 #define V_CAUSE_CTX_0(x) ((x) << S_CAUSE_CTX_0)
26447 #define F_CAUSE_CTX_0 V_CAUSE_CTX_0(1U)
26449 #define S_CAUSE_FF 22
26450 #define V_CAUSE_FF(x) ((x) << S_CAUSE_FF)
26451 #define F_CAUSE_FF V_CAUSE_FF(1U)
26453 #define S_CAUSE_APF_1 21
26454 #define V_CAUSE_APF_1(x) ((x) << S_CAUSE_APF_1)
26455 #define F_CAUSE_APF_1 V_CAUSE_APF_1(1U)
26457 #define S_CAUSE_APF_0 20
26458 #define V_CAUSE_APF_0(x) ((x) << S_CAUSE_APF_0)
26459 #define F_CAUSE_APF_0 V_CAUSE_APF_0(1U)
26461 #define S_CAUSE_AF_1 19
26462 #define V_CAUSE_AF_1(x) ((x) << S_CAUSE_AF_1)
26463 #define F_CAUSE_AF_1 V_CAUSE_AF_1(1U)
26465 #define S_CAUSE_AF_0 18
26466 #define V_CAUSE_AF_0(x) ((x) << S_CAUSE_AF_0)
26467 #define F_CAUSE_AF_0 V_CAUSE_AF_0(1U)
26469 #define S_CAUSE_DDPDF_1 17
26470 #define V_CAUSE_DDPDF_1(x) ((x) << S_CAUSE_DDPDF_1)
26471 #define F_CAUSE_DDPDF_1 V_CAUSE_DDPDF_1(1U)
26473 #define S_CAUSE_DDPMF_1 16
26474 #define V_CAUSE_DDPMF_1(x) ((x) << S_CAUSE_DDPMF_1)
26475 #define F_CAUSE_DDPMF_1 V_CAUSE_DDPMF_1(1U)
26477 #define S_CAUSE_MEMRF_1 15
26478 #define V_CAUSE_MEMRF_1(x) ((x) << S_CAUSE_MEMRF_1)
26479 #define F_CAUSE_MEMRF_1 V_CAUSE_MEMRF_1(1U)
26481 #define S_CAUSE_PRSDF_1 14
26482 #define V_CAUSE_PRSDF_1(x) ((x) << S_CAUSE_PRSDF_1)
26483 #define F_CAUSE_PRSDF_1 V_CAUSE_PRSDF_1(1U)
26485 #define S_CAUSE_DDPDF_0 13
26486 #define V_CAUSE_DDPDF_0(x) ((x) << S_CAUSE_DDPDF_0)
26487 #define F_CAUSE_DDPDF_0 V_CAUSE_DDPDF_0(1U)
26489 #define S_CAUSE_DDPMF_0 12
26490 #define V_CAUSE_DDPMF_0(x) ((x) << S_CAUSE_DDPMF_0)
26491 #define F_CAUSE_DDPMF_0 V_CAUSE_DDPMF_0(1U)
26493 #define S_CAUSE_MEMRF_0 11
26494 #define V_CAUSE_MEMRF_0(x) ((x) << S_CAUSE_MEMRF_0)
26495 #define F_CAUSE_MEMRF_0 V_CAUSE_MEMRF_0(1U)
26497 #define S_CAUSE_PRSDF_0 10
26498 #define V_CAUSE_PRSDF_0(x) ((x) << S_CAUSE_PRSDF_0)
26499 #define F_CAUSE_PRSDF_0 V_CAUSE_PRSDF_0(1U)
26501 #define S_CAUSE_PCMDF_1 9
26502 #define V_CAUSE_PCMDF_1(x) ((x) << S_CAUSE_PCMDF_1)
26503 #define F_CAUSE_PCMDF_1 V_CAUSE_PCMDF_1(1U)
26505 #define S_CAUSE_TPTCF_1 8
26506 #define V_CAUSE_TPTCF_1(x) ((x) << S_CAUSE_TPTCF_1)
26507 #define F_CAUSE_TPTCF_1 V_CAUSE_TPTCF_1(1U)
26509 #define S_CAUSE_DDPCF_1 7
26510 #define V_CAUSE_DDPCF_1(x) ((x) << S_CAUSE_DDPCF_1)
26511 #define F_CAUSE_DDPCF_1 V_CAUSE_DDPCF_1(1U)
26513 #define S_CAUSE_MPARF_1 6
26514 #define V_CAUSE_MPARF_1(x) ((x) << S_CAUSE_MPARF_1)
26515 #define F_CAUSE_MPARF_1 V_CAUSE_MPARF_1(1U)
26517 #define S_CAUSE_MPARC_1 5
26518 #define V_CAUSE_MPARC_1(x) ((x) << S_CAUSE_MPARC_1)
26519 #define F_CAUSE_MPARC_1 V_CAUSE_MPARC_1(1U)
26521 #define S_CAUSE_PCMDF_0 4
26522 #define V_CAUSE_PCMDF_0(x) ((x) << S_CAUSE_PCMDF_0)
26523 #define F_CAUSE_PCMDF_0 V_CAUSE_PCMDF_0(1U)
26525 #define S_CAUSE_TPTCF_0 3
26526 #define V_CAUSE_TPTCF_0(x) ((x) << S_CAUSE_TPTCF_0)
26527 #define F_CAUSE_TPTCF_0 V_CAUSE_TPTCF_0(1U)
26529 #define S_CAUSE_DDPCF_0 2
26530 #define V_CAUSE_DDPCF_0(x) ((x) << S_CAUSE_DDPCF_0)
26531 #define F_CAUSE_DDPCF_0 V_CAUSE_DDPCF_0(1U)
26533 #define S_CAUSE_MPARF_0 1
26534 #define V_CAUSE_MPARF_0(x) ((x) << S_CAUSE_MPARF_0)
26535 #define F_CAUSE_MPARF_0 V_CAUSE_MPARF_0(1U)
26537 #define S_CAUSE_MPARC_0 0
26538 #define V_CAUSE_MPARC_0(x) ((x) << S_CAUSE_MPARC_0)
26539 #define F_CAUSE_MPARC_0 V_CAUSE_MPARC_0(1U)
26541 #define A_ULP_RX_ISCSI_LLIMIT 0x1915c
26543 #define S_ISCSILLIMIT 6
26544 #define M_ISCSILLIMIT 0x3ffffffU
26545 #define V_ISCSILLIMIT(x) ((x) << S_ISCSILLIMIT)
26546 #define G_ISCSILLIMIT(x) (((x) >> S_ISCSILLIMIT) & M_ISCSILLIMIT)
26548 #define A_ULP_RX_ISCSI_ULIMIT 0x19160
26550 #define S_ISCSIULIMIT 6
26551 #define M_ISCSIULIMIT 0x3ffffffU
26552 #define V_ISCSIULIMIT(x) ((x) << S_ISCSIULIMIT)
26553 #define G_ISCSIULIMIT(x) (((x) >> S_ISCSIULIMIT) & M_ISCSIULIMIT)
26555 #define A_ULP_RX_ISCSI_TAGMASK 0x19164
26557 #define S_ISCSITAGMASK 6
26558 #define M_ISCSITAGMASK 0x3ffffffU
26559 #define V_ISCSITAGMASK(x) ((x) << S_ISCSITAGMASK)
26560 #define G_ISCSITAGMASK(x) (((x) >> S_ISCSITAGMASK) & M_ISCSITAGMASK)
26562 #define A_ULP_RX_ISCSI_PSZ 0x19168
26565 #define M_HPZ3 0xfU
26566 #define V_HPZ3(x) ((x) << S_HPZ3)
26567 #define G_HPZ3(x) (((x) >> S_HPZ3) & M_HPZ3)
26570 #define M_HPZ2 0xfU
26571 #define V_HPZ2(x) ((x) << S_HPZ2)
26572 #define G_HPZ2(x) (((x) >> S_HPZ2) & M_HPZ2)
26575 #define M_HPZ1 0xfU
26576 #define V_HPZ1(x) ((x) << S_HPZ1)
26577 #define G_HPZ1(x) (((x) >> S_HPZ1) & M_HPZ1)
26580 #define M_HPZ0 0xfU
26581 #define V_HPZ0(x) ((x) << S_HPZ0)
26582 #define G_HPZ0(x) (((x) >> S_HPZ0) & M_HPZ0)
26584 #define A_ULP_RX_TDDP_LLIMIT 0x1916c
26586 #define S_TDDPLLIMIT 6
26587 #define M_TDDPLLIMIT 0x3ffffffU
26588 #define V_TDDPLLIMIT(x) ((x) << S_TDDPLLIMIT)
26589 #define G_TDDPLLIMIT(x) (((x) >> S_TDDPLLIMIT) & M_TDDPLLIMIT)
26591 #define A_ULP_RX_TDDP_ULIMIT 0x19170
26593 #define S_TDDPULIMIT 6
26594 #define M_TDDPULIMIT 0x3ffffffU
26595 #define V_TDDPULIMIT(x) ((x) << S_TDDPULIMIT)
26596 #define G_TDDPULIMIT(x) (((x) >> S_TDDPULIMIT) & M_TDDPULIMIT)
26598 #define A_ULP_RX_TDDP_TAGMASK 0x19174
26600 #define S_TDDPTAGMASK 6
26601 #define M_TDDPTAGMASK 0x3ffffffU
26602 #define V_TDDPTAGMASK(x) ((x) << S_TDDPTAGMASK)
26603 #define G_TDDPTAGMASK(x) (((x) >> S_TDDPTAGMASK) & M_TDDPTAGMASK)
26605 #define A_ULP_RX_TDDP_PSZ 0x19178
26606 #define A_ULP_RX_STAG_LLIMIT 0x1917c
26607 #define A_ULP_RX_STAG_ULIMIT 0x19180
26608 #define A_ULP_RX_RQ_LLIMIT 0x19184
26609 #define A_ULP_RX_RQ_ULIMIT 0x19188
26610 #define A_ULP_RX_PBL_LLIMIT 0x1918c
26611 #define A_ULP_RX_PBL_ULIMIT 0x19190
26612 #define A_ULP_RX_CTX_BASE 0x19194
26613 #define A_ULP_RX_PERR_ENABLE 0x1919c
26615 #define S_PERR_ENABLE_FF 22
26616 #define V_PERR_ENABLE_FF(x) ((x) << S_PERR_ENABLE_FF)
26617 #define F_PERR_ENABLE_FF V_PERR_ENABLE_FF(1U)
26619 #define S_PERR_ENABLE_APF_1 21
26620 #define V_PERR_ENABLE_APF_1(x) ((x) << S_PERR_ENABLE_APF_1)
26621 #define F_PERR_ENABLE_APF_1 V_PERR_ENABLE_APF_1(1U)
26623 #define S_PERR_ENABLE_APF_0 20
26624 #define V_PERR_ENABLE_APF_0(x) ((x) << S_PERR_ENABLE_APF_0)
26625 #define F_PERR_ENABLE_APF_0 V_PERR_ENABLE_APF_0(1U)
26627 #define S_PERR_ENABLE_AF_1 19
26628 #define V_PERR_ENABLE_AF_1(x) ((x) << S_PERR_ENABLE_AF_1)
26629 #define F_PERR_ENABLE_AF_1 V_PERR_ENABLE_AF_1(1U)
26631 #define S_PERR_ENABLE_AF_0 18
26632 #define V_PERR_ENABLE_AF_0(x) ((x) << S_PERR_ENABLE_AF_0)
26633 #define F_PERR_ENABLE_AF_0 V_PERR_ENABLE_AF_0(1U)
26635 #define S_PERR_ENABLE_DDPDF_1 17
26636 #define V_PERR_ENABLE_DDPDF_1(x) ((x) << S_PERR_ENABLE_DDPDF_1)
26637 #define F_PERR_ENABLE_DDPDF_1 V_PERR_ENABLE_DDPDF_1(1U)
26639 #define S_PERR_ENABLE_DDPMF_1 16
26640 #define V_PERR_ENABLE_DDPMF_1(x) ((x) << S_PERR_ENABLE_DDPMF_1)
26641 #define F_PERR_ENABLE_DDPMF_1 V_PERR_ENABLE_DDPMF_1(1U)
26643 #define S_PERR_ENABLE_MEMRF_1 15
26644 #define V_PERR_ENABLE_MEMRF_1(x) ((x) << S_PERR_ENABLE_MEMRF_1)
26645 #define F_PERR_ENABLE_MEMRF_1 V_PERR_ENABLE_MEMRF_1(1U)
26647 #define S_PERR_ENABLE_PRSDF_1 14
26648 #define V_PERR_ENABLE_PRSDF_1(x) ((x) << S_PERR_ENABLE_PRSDF_1)
26649 #define F_PERR_ENABLE_PRSDF_1 V_PERR_ENABLE_PRSDF_1(1U)
26651 #define S_PERR_ENABLE_DDPDF_0 13
26652 #define V_PERR_ENABLE_DDPDF_0(x) ((x) << S_PERR_ENABLE_DDPDF_0)
26653 #define F_PERR_ENABLE_DDPDF_0 V_PERR_ENABLE_DDPDF_0(1U)
26655 #define S_PERR_ENABLE_DDPMF_0 12
26656 #define V_PERR_ENABLE_DDPMF_0(x) ((x) << S_PERR_ENABLE_DDPMF_0)
26657 #define F_PERR_ENABLE_DDPMF_0 V_PERR_ENABLE_DDPMF_0(1U)
26659 #define S_PERR_ENABLE_MEMRF_0 11
26660 #define V_PERR_ENABLE_MEMRF_0(x) ((x) << S_PERR_ENABLE_MEMRF_0)
26661 #define F_PERR_ENABLE_MEMRF_0 V_PERR_ENABLE_MEMRF_0(1U)
26663 #define S_PERR_ENABLE_PRSDF_0 10
26664 #define V_PERR_ENABLE_PRSDF_0(x) ((x) << S_PERR_ENABLE_PRSDF_0)
26665 #define F_PERR_ENABLE_PRSDF_0 V_PERR_ENABLE_PRSDF_0(1U)
26667 #define S_PERR_ENABLE_PCMDF_1 9
26668 #define V_PERR_ENABLE_PCMDF_1(x) ((x) << S_PERR_ENABLE_PCMDF_1)
26669 #define F_PERR_ENABLE_PCMDF_1 V_PERR_ENABLE_PCMDF_1(1U)
26671 #define S_PERR_ENABLE_TPTCF_1 8
26672 #define V_PERR_ENABLE_TPTCF_1(x) ((x) << S_PERR_ENABLE_TPTCF_1)
26673 #define F_PERR_ENABLE_TPTCF_1 V_PERR_ENABLE_TPTCF_1(1U)
26675 #define S_PERR_ENABLE_DDPCF_1 7
26676 #define V_PERR_ENABLE_DDPCF_1(x) ((x) << S_PERR_ENABLE_DDPCF_1)
26677 #define F_PERR_ENABLE_DDPCF_1 V_PERR_ENABLE_DDPCF_1(1U)
26679 #define S_PERR_ENABLE_MPARF_1 6
26680 #define V_PERR_ENABLE_MPARF_1(x) ((x) << S_PERR_ENABLE_MPARF_1)
26681 #define F_PERR_ENABLE_MPARF_1 V_PERR_ENABLE_MPARF_1(1U)
26683 #define S_PERR_ENABLE_MPARC_1 5
26684 #define V_PERR_ENABLE_MPARC_1(x) ((x) << S_PERR_ENABLE_MPARC_1)
26685 #define F_PERR_ENABLE_MPARC_1 V_PERR_ENABLE_MPARC_1(1U)
26687 #define S_PERR_ENABLE_PCMDF_0 4
26688 #define V_PERR_ENABLE_PCMDF_0(x) ((x) << S_PERR_ENABLE_PCMDF_0)
26689 #define F_PERR_ENABLE_PCMDF_0 V_PERR_ENABLE_PCMDF_0(1U)
26691 #define S_PERR_ENABLE_TPTCF_0 3
26692 #define V_PERR_ENABLE_TPTCF_0(x) ((x) << S_PERR_ENABLE_TPTCF_0)
26693 #define F_PERR_ENABLE_TPTCF_0 V_PERR_ENABLE_TPTCF_0(1U)
26695 #define S_PERR_ENABLE_DDPCF_0 2
26696 #define V_PERR_ENABLE_DDPCF_0(x) ((x) << S_PERR_ENABLE_DDPCF_0)
26697 #define F_PERR_ENABLE_DDPCF_0 V_PERR_ENABLE_DDPCF_0(1U)
26699 #define S_PERR_ENABLE_MPARF_0 1
26700 #define V_PERR_ENABLE_MPARF_0(x) ((x) << S_PERR_ENABLE_MPARF_0)
26701 #define F_PERR_ENABLE_MPARF_0 V_PERR_ENABLE_MPARF_0(1U)
26703 #define S_PERR_ENABLE_MPARC_0 0
26704 #define V_PERR_ENABLE_MPARC_0(x) ((x) << S_PERR_ENABLE_MPARC_0)
26705 #define F_PERR_ENABLE_MPARC_0 V_PERR_ENABLE_MPARC_0(1U)
26707 #define S_PERR_SE_CNT_MISMATCH_1 26
26708 #define V_PERR_SE_CNT_MISMATCH_1(x) ((x) << S_PERR_SE_CNT_MISMATCH_1)
26709 #define F_PERR_SE_CNT_MISMATCH_1 V_PERR_SE_CNT_MISMATCH_1(1U)
26711 #define S_PERR_SE_CNT_MISMATCH_0 25
26712 #define V_PERR_SE_CNT_MISMATCH_0(x) ((x) << S_PERR_SE_CNT_MISMATCH_0)
26713 #define F_PERR_SE_CNT_MISMATCH_0 V_PERR_SE_CNT_MISMATCH_0(1U)
26715 #define S_PERR_RSVD0 24
26716 #define V_PERR_RSVD0(x) ((x) << S_PERR_RSVD0)
26717 #define F_PERR_RSVD0 V_PERR_RSVD0(1U)
26719 #define S_PERR_RSVD1 23
26720 #define V_PERR_RSVD1(x) ((x) << S_PERR_RSVD1)
26721 #define F_PERR_RSVD1 V_PERR_RSVD1(1U)
26723 #define A_ULP_RX_PERR_INJECT 0x191a0
26724 #define A_ULP_RX_RQUDP_LLIMIT 0x191a4
26725 #define A_ULP_RX_RQUDP_ULIMIT 0x191a8
26726 #define A_ULP_RX_CTX_ACC_CH0 0x191ac
26729 #define V_REQ(x) ((x) << S_REQ)
26730 #define F_REQ V_REQ(1U)
26733 #define V_WB(x) ((x) << S_WB)
26734 #define F_WB V_WB(1U)
26736 #define S_ULPRX_TID 0
26737 #define M_ULPRX_TID 0xfffffU
26738 #define V_ULPRX_TID(x) ((x) << S_ULPRX_TID)
26739 #define G_ULPRX_TID(x) (((x) >> S_ULPRX_TID) & M_ULPRX_TID)
26741 #define A_ULP_RX_CTX_ACC_CH1 0x191b0
26742 #define A_ULP_RX_SE_CNT_ERR 0x191d0
26743 #define A_ULP_RX_SE_CNT_CLR 0x191d4
26745 #define S_CLRCHAN0 4
26746 #define M_CLRCHAN0 0xfU
26747 #define V_CLRCHAN0(x) ((x) << S_CLRCHAN0)
26748 #define G_CLRCHAN0(x) (((x) >> S_CLRCHAN0) & M_CLRCHAN0)
26750 #define S_CLRCHAN1 0
26751 #define M_CLRCHAN1 0xfU
26752 #define V_CLRCHAN1(x) ((x) << S_CLRCHAN1)
26753 #define G_CLRCHAN1(x) (((x) >> S_CLRCHAN1) & M_CLRCHAN1)
26755 #define A_ULP_RX_SE_CNT_CH0 0x191d8
26757 #define S_SOP_CNT_OUT0 28
26758 #define M_SOP_CNT_OUT0 0xfU
26759 #define V_SOP_CNT_OUT0(x) ((x) << S_SOP_CNT_OUT0)
26760 #define G_SOP_CNT_OUT0(x) (((x) >> S_SOP_CNT_OUT0) & M_SOP_CNT_OUT0)
26762 #define S_EOP_CNT_OUT0 24
26763 #define M_EOP_CNT_OUT0 0xfU
26764 #define V_EOP_CNT_OUT0(x) ((x) << S_EOP_CNT_OUT0)
26765 #define G_EOP_CNT_OUT0(x) (((x) >> S_EOP_CNT_OUT0) & M_EOP_CNT_OUT0)
26767 #define S_SOP_CNT_AL0 20
26768 #define M_SOP_CNT_AL0 0xfU
26769 #define V_SOP_CNT_AL0(x) ((x) << S_SOP_CNT_AL0)
26770 #define G_SOP_CNT_AL0(x) (((x) >> S_SOP_CNT_AL0) & M_SOP_CNT_AL0)
26772 #define S_EOP_CNT_AL0 16
26773 #define M_EOP_CNT_AL0 0xfU
26774 #define V_EOP_CNT_AL0(x) ((x) << S_EOP_CNT_AL0)
26775 #define G_EOP_CNT_AL0(x) (((x) >> S_EOP_CNT_AL0) & M_EOP_CNT_AL0)
26777 #define S_SOP_CNT_MR0 12
26778 #define M_SOP_CNT_MR0 0xfU
26779 #define V_SOP_CNT_MR0(x) ((x) << S_SOP_CNT_MR0)
26780 #define G_SOP_CNT_MR0(x) (((x) >> S_SOP_CNT_MR0) & M_SOP_CNT_MR0)
26782 #define S_EOP_CNT_MR0 8
26783 #define M_EOP_CNT_MR0 0xfU
26784 #define V_EOP_CNT_MR0(x) ((x) << S_EOP_CNT_MR0)
26785 #define G_EOP_CNT_MR0(x) (((x) >> S_EOP_CNT_MR0) & M_EOP_CNT_MR0)
26787 #define S_SOP_CNT_IN0 4
26788 #define M_SOP_CNT_IN0 0xfU
26789 #define V_SOP_CNT_IN0(x) ((x) << S_SOP_CNT_IN0)
26790 #define G_SOP_CNT_IN0(x) (((x) >> S_SOP_CNT_IN0) & M_SOP_CNT_IN0)
26792 #define S_EOP_CNT_IN0 0
26793 #define M_EOP_CNT_IN0 0xfU
26794 #define V_EOP_CNT_IN0(x) ((x) << S_EOP_CNT_IN0)
26795 #define G_EOP_CNT_IN0(x) (((x) >> S_EOP_CNT_IN0) & M_EOP_CNT_IN0)
26797 #define A_ULP_RX_SE_CNT_CH1 0x191dc
26799 #define S_SOP_CNT_OUT1 28
26800 #define M_SOP_CNT_OUT1 0xfU
26801 #define V_SOP_CNT_OUT1(x) ((x) << S_SOP_CNT_OUT1)
26802 #define G_SOP_CNT_OUT1(x) (((x) >> S_SOP_CNT_OUT1) & M_SOP_CNT_OUT1)
26804 #define S_EOP_CNT_OUT1 24
26805 #define M_EOP_CNT_OUT1 0xfU
26806 #define V_EOP_CNT_OUT1(x) ((x) << S_EOP_CNT_OUT1)
26807 #define G_EOP_CNT_OUT1(x) (((x) >> S_EOP_CNT_OUT1) & M_EOP_CNT_OUT1)
26809 #define S_SOP_CNT_AL1 20
26810 #define M_SOP_CNT_AL1 0xfU
26811 #define V_SOP_CNT_AL1(x) ((x) << S_SOP_CNT_AL1)
26812 #define G_SOP_CNT_AL1(x) (((x) >> S_SOP_CNT_AL1) & M_SOP_CNT_AL1)
26814 #define S_EOP_CNT_AL1 16
26815 #define M_EOP_CNT_AL1 0xfU
26816 #define V_EOP_CNT_AL1(x) ((x) << S_EOP_CNT_AL1)
26817 #define G_EOP_CNT_AL1(x) (((x) >> S_EOP_CNT_AL1) & M_EOP_CNT_AL1)
26819 #define S_SOP_CNT_MR1 12
26820 #define M_SOP_CNT_MR1 0xfU
26821 #define V_SOP_CNT_MR1(x) ((x) << S_SOP_CNT_MR1)
26822 #define G_SOP_CNT_MR1(x) (((x) >> S_SOP_CNT_MR1) & M_SOP_CNT_MR1)
26824 #define S_EOP_CNT_MR1 8
26825 #define M_EOP_CNT_MR1 0xfU
26826 #define V_EOP_CNT_MR1(x) ((x) << S_EOP_CNT_MR1)
26827 #define G_EOP_CNT_MR1(x) (((x) >> S_EOP_CNT_MR1) & M_EOP_CNT_MR1)
26829 #define S_SOP_CNT_IN1 4
26830 #define M_SOP_CNT_IN1 0xfU
26831 #define V_SOP_CNT_IN1(x) ((x) << S_SOP_CNT_IN1)
26832 #define G_SOP_CNT_IN1(x) (((x) >> S_SOP_CNT_IN1) & M_SOP_CNT_IN1)
26834 #define S_EOP_CNT_IN1 0
26835 #define M_EOP_CNT_IN1 0xfU
26836 #define V_EOP_CNT_IN1(x) ((x) << S_EOP_CNT_IN1)
26837 #define G_EOP_CNT_IN1(x) (((x) >> S_EOP_CNT_IN1) & M_EOP_CNT_IN1)
26839 #define A_ULP_RX_DBG_CTL 0x191e0
26841 #define S_EN_DBG_H 17
26842 #define V_EN_DBG_H(x) ((x) << S_EN_DBG_H)
26843 #define F_EN_DBG_H V_EN_DBG_H(1U)
26845 #define S_EN_DBG_L 16
26846 #define V_EN_DBG_L(x) ((x) << S_EN_DBG_L)
26847 #define F_EN_DBG_L V_EN_DBG_L(1U)
26850 #define M_SEL_H 0xffU
26851 #define V_SEL_H(x) ((x) << S_SEL_H)
26852 #define G_SEL_H(x) (((x) >> S_SEL_H) & M_SEL_H)
26855 #define M_SEL_L 0xffU
26856 #define V_SEL_L(x) ((x) << S_SEL_L)
26857 #define G_SEL_L(x) (((x) >> S_SEL_L) & M_SEL_L)
26859 #define A_ULP_RX_DBG_DATAH 0x191e4
26860 #define A_ULP_RX_DBG_DATAL 0x191e8
26861 #define A_ULP_RX_LA_CHNL 0x19238
26863 #define S_CHNL_SEL 0
26864 #define V_CHNL_SEL(x) ((x) << S_CHNL_SEL)
26865 #define F_CHNL_SEL V_CHNL_SEL(1U)
26867 #define A_ULP_RX_LA_CTL 0x1923c
26869 #define S_TRC_SEL 0
26870 #define V_TRC_SEL(x) ((x) << S_TRC_SEL)
26871 #define F_TRC_SEL V_TRC_SEL(1U)
26873 #define A_ULP_RX_LA_RDPTR 0x19240
26876 #define M_RD_PTR 0x1ffU
26877 #define V_RD_PTR(x) ((x) << S_RD_PTR)
26878 #define G_RD_PTR(x) (((x) >> S_RD_PTR) & M_RD_PTR)
26880 #define A_ULP_RX_LA_RDDATA 0x19244
26881 #define A_ULP_RX_LA_WRPTR 0x19248
26884 #define M_WR_PTR 0x1ffU
26885 #define V_WR_PTR(x) ((x) << S_WR_PTR)
26886 #define G_WR_PTR(x) (((x) >> S_WR_PTR) & M_WR_PTR)
26888 #define A_ULP_RX_LA_RESERVED 0x1924c
26889 #define A_ULP_RX_CQE_GEN_EN 0x19250
26891 #define S_TERMIMATE_MSG 1
26892 #define V_TERMIMATE_MSG(x) ((x) << S_TERMIMATE_MSG)
26893 #define F_TERMIMATE_MSG V_TERMIMATE_MSG(1U)
26895 #define S_TERMINATE_WITH_ERR 0
26896 #define V_TERMINATE_WITH_ERR(x) ((x) << S_TERMINATE_WITH_ERR)
26897 #define F_TERMINATE_WITH_ERR V_TERMINATE_WITH_ERR(1U)
26899 #define A_ULP_RX_ATOMIC_OPCODES 0x19254
26901 #define S_ATOMIC_REQ_QNO 22
26902 #define M_ATOMIC_REQ_QNO 0x3U
26903 #define V_ATOMIC_REQ_QNO(x) ((x) << S_ATOMIC_REQ_QNO)
26904 #define G_ATOMIC_REQ_QNO(x) (((x) >> S_ATOMIC_REQ_QNO) & M_ATOMIC_REQ_QNO)
26906 #define S_ATOMIC_RSP_QNO 20
26907 #define M_ATOMIC_RSP_QNO 0x3U
26908 #define V_ATOMIC_RSP_QNO(x) ((x) << S_ATOMIC_RSP_QNO)
26909 #define G_ATOMIC_RSP_QNO(x) (((x) >> S_ATOMIC_RSP_QNO) & M_ATOMIC_RSP_QNO)
26911 #define S_IMMEDIATE_QNO 18
26912 #define M_IMMEDIATE_QNO 0x3U
26913 #define V_IMMEDIATE_QNO(x) ((x) << S_IMMEDIATE_QNO)
26914 #define G_IMMEDIATE_QNO(x) (((x) >> S_IMMEDIATE_QNO) & M_IMMEDIATE_QNO)
26916 #define S_IMMEDIATE_WITH_SE_QNO 16
26917 #define M_IMMEDIATE_WITH_SE_QNO 0x3U
26918 #define V_IMMEDIATE_WITH_SE_QNO(x) ((x) << S_IMMEDIATE_WITH_SE_QNO)
26919 #define G_IMMEDIATE_WITH_SE_QNO(x) (((x) >> S_IMMEDIATE_WITH_SE_QNO) & M_IMMEDIATE_WITH_SE_QNO)
26921 #define S_ATOMIC_WR_OPCODE 12
26922 #define M_ATOMIC_WR_OPCODE 0xfU
26923 #define V_ATOMIC_WR_OPCODE(x) ((x) << S_ATOMIC_WR_OPCODE)
26924 #define G_ATOMIC_WR_OPCODE(x) (((x) >> S_ATOMIC_WR_OPCODE) & M_ATOMIC_WR_OPCODE)
26926 #define S_ATOMIC_RD_OPCODE 8
26927 #define M_ATOMIC_RD_OPCODE 0xfU
26928 #define V_ATOMIC_RD_OPCODE(x) ((x) << S_ATOMIC_RD_OPCODE)
26929 #define G_ATOMIC_RD_OPCODE(x) (((x) >> S_ATOMIC_RD_OPCODE) & M_ATOMIC_RD_OPCODE)
26931 #define S_IMMEDIATE_OPCODE 4
26932 #define M_IMMEDIATE_OPCODE 0xfU
26933 #define V_IMMEDIATE_OPCODE(x) ((x) << S_IMMEDIATE_OPCODE)
26934 #define G_IMMEDIATE_OPCODE(x) (((x) >> S_IMMEDIATE_OPCODE) & M_IMMEDIATE_OPCODE)
26936 #define S_IMMEDIATE_WITH_SE_OPCODE 0
26937 #define M_IMMEDIATE_WITH_SE_OPCODE 0xfU
26938 #define V_IMMEDIATE_WITH_SE_OPCODE(x) ((x) << S_IMMEDIATE_WITH_SE_OPCODE)
26939 #define G_IMMEDIATE_WITH_SE_OPCODE(x) (((x) >> S_IMMEDIATE_WITH_SE_OPCODE) & M_IMMEDIATE_WITH_SE_OPCODE)
26941 #define A_ULP_RX_T10_CRC_ENDIAN_SWITCHING 0x19258
26943 #define S_EN_ORIG_DATA 0
26944 #define V_EN_ORIG_DATA(x) ((x) << S_EN_ORIG_DATA)
26945 #define F_EN_ORIG_DATA V_EN_ORIG_DATA(1U)
26947 #define A_ULP_RX_MISC_FEATURE_ENABLE 0x1925c
26949 #define S_TERMINATE_STATUS_EN 4
26950 #define V_TERMINATE_STATUS_EN(x) ((x) << S_TERMINATE_STATUS_EN)
26951 #define F_TERMINATE_STATUS_EN V_TERMINATE_STATUS_EN(1U)
26953 #define S_MULTIPLE_PREF_ENABLE 3
26954 #define V_MULTIPLE_PREF_ENABLE(x) ((x) << S_MULTIPLE_PREF_ENABLE)
26955 #define F_MULTIPLE_PREF_ENABLE V_MULTIPLE_PREF_ENABLE(1U)
26957 #define S_UMUDP_PBL_PREF_ENABLE 2
26958 #define V_UMUDP_PBL_PREF_ENABLE(x) ((x) << S_UMUDP_PBL_PREF_ENABLE)
26959 #define F_UMUDP_PBL_PREF_ENABLE V_UMUDP_PBL_PREF_ENABLE(1U)
26961 #define S_RDMA_PBL_PREF_EN 1
26962 #define V_RDMA_PBL_PREF_EN(x) ((x) << S_RDMA_PBL_PREF_EN)
26963 #define F_RDMA_PBL_PREF_EN V_RDMA_PBL_PREF_EN(1U)
26965 #define S_SDC_CRC_PROT_EN 0
26966 #define V_SDC_CRC_PROT_EN(x) ((x) << S_SDC_CRC_PROT_EN)
26967 #define F_SDC_CRC_PROT_EN V_SDC_CRC_PROT_EN(1U)
26969 #define A_ULP_RX_CH0_CGEN 0x19260
26971 #define S_BYPASS_CGEN 7
26972 #define V_BYPASS_CGEN(x) ((x) << S_BYPASS_CGEN)
26973 #define F_BYPASS_CGEN V_BYPASS_CGEN(1U)
26975 #define S_TDDP_CGEN 6
26976 #define V_TDDP_CGEN(x) ((x) << S_TDDP_CGEN)
26977 #define F_TDDP_CGEN V_TDDP_CGEN(1U)
26979 #define S_ISCSI_CGEN 5
26980 #define V_ISCSI_CGEN(x) ((x) << S_ISCSI_CGEN)
26981 #define F_ISCSI_CGEN V_ISCSI_CGEN(1U)
26983 #define S_RDMA_CGEN 4
26984 #define V_RDMA_CGEN(x) ((x) << S_RDMA_CGEN)
26985 #define F_RDMA_CGEN V_RDMA_CGEN(1U)
26987 #define S_CHANNEL_CGEN 3
26988 #define V_CHANNEL_CGEN(x) ((x) << S_CHANNEL_CGEN)
26989 #define F_CHANNEL_CGEN V_CHANNEL_CGEN(1U)
26991 #define S_ALL_DATAPATH_CGEN 2
26992 #define V_ALL_DATAPATH_CGEN(x) ((x) << S_ALL_DATAPATH_CGEN)
26993 #define F_ALL_DATAPATH_CGEN V_ALL_DATAPATH_CGEN(1U)
26995 #define S_T10DIFF_DATAPATH_CGEN 1
26996 #define V_T10DIFF_DATAPATH_CGEN(x) ((x) << S_T10DIFF_DATAPATH_CGEN)
26997 #define F_T10DIFF_DATAPATH_CGEN V_T10DIFF_DATAPATH_CGEN(1U)
26999 #define S_RDMA_DATAPATH_CGEN 0
27000 #define V_RDMA_DATAPATH_CGEN(x) ((x) << S_RDMA_DATAPATH_CGEN)
27001 #define F_RDMA_DATAPATH_CGEN V_RDMA_DATAPATH_CGEN(1U)
27003 #define A_ULP_RX_CH1_CGEN 0x19264
27004 #define A_ULP_RX_RFE_DISABLE 0x19268
27006 #define S_RQE_LIM_CHECK_RFE_DISABLE 0
27007 #define V_RQE_LIM_CHECK_RFE_DISABLE(x) ((x) << S_RQE_LIM_CHECK_RFE_DISABLE)
27008 #define F_RQE_LIM_CHECK_RFE_DISABLE V_RQE_LIM_CHECK_RFE_DISABLE(1U)
27010 #define A_ULP_RX_INT_ENABLE_2 0x1926c
27012 #define S_ULPRX2MA_INTFPERR 8
27013 #define V_ULPRX2MA_INTFPERR(x) ((x) << S_ULPRX2MA_INTFPERR)
27014 #define F_ULPRX2MA_INTFPERR V_ULPRX2MA_INTFPERR(1U)
27016 #define S_ALN_SDC_ERR_1 7
27017 #define V_ALN_SDC_ERR_1(x) ((x) << S_ALN_SDC_ERR_1)
27018 #define F_ALN_SDC_ERR_1 V_ALN_SDC_ERR_1(1U)
27020 #define S_ALN_SDC_ERR_0 6
27021 #define V_ALN_SDC_ERR_0(x) ((x) << S_ALN_SDC_ERR_0)
27022 #define F_ALN_SDC_ERR_0 V_ALN_SDC_ERR_0(1U)
27024 #define S_PF_UNTAGGED_TPT_1 5
27025 #define V_PF_UNTAGGED_TPT_1(x) ((x) << S_PF_UNTAGGED_TPT_1)
27026 #define F_PF_UNTAGGED_TPT_1 V_PF_UNTAGGED_TPT_1(1U)
27028 #define S_PF_UNTAGGED_TPT_0 4
27029 #define V_PF_UNTAGGED_TPT_0(x) ((x) << S_PF_UNTAGGED_TPT_0)
27030 #define F_PF_UNTAGGED_TPT_0 V_PF_UNTAGGED_TPT_0(1U)
27032 #define S_PF_PBL_1 3
27033 #define V_PF_PBL_1(x) ((x) << S_PF_PBL_1)
27034 #define F_PF_PBL_1 V_PF_PBL_1(1U)
27036 #define S_PF_PBL_0 2
27037 #define V_PF_PBL_0(x) ((x) << S_PF_PBL_0)
27038 #define F_PF_PBL_0 V_PF_PBL_0(1U)
27040 #define S_DDP_HINT_1 1
27041 #define V_DDP_HINT_1(x) ((x) << S_DDP_HINT_1)
27042 #define F_DDP_HINT_1 V_DDP_HINT_1(1U)
27044 #define S_DDP_HINT_0 0
27045 #define V_DDP_HINT_0(x) ((x) << S_DDP_HINT_0)
27046 #define F_DDP_HINT_0 V_DDP_HINT_0(1U)
27048 #define A_ULP_RX_INT_CAUSE_2 0x19270
27049 #define A_ULP_RX_PERR_ENABLE_2 0x19274
27051 #define S_ENABLE_ULPRX2MA_INTFPERR 8
27052 #define V_ENABLE_ULPRX2MA_INTFPERR(x) ((x) << S_ENABLE_ULPRX2MA_INTFPERR)
27053 #define F_ENABLE_ULPRX2MA_INTFPERR V_ENABLE_ULPRX2MA_INTFPERR(1U)
27055 #define S_ENABLE_ALN_SDC_ERR_1 7
27056 #define V_ENABLE_ALN_SDC_ERR_1(x) ((x) << S_ENABLE_ALN_SDC_ERR_1)
27057 #define F_ENABLE_ALN_SDC_ERR_1 V_ENABLE_ALN_SDC_ERR_1(1U)
27059 #define S_ENABLE_ALN_SDC_ERR_0 6
27060 #define V_ENABLE_ALN_SDC_ERR_0(x) ((x) << S_ENABLE_ALN_SDC_ERR_0)
27061 #define F_ENABLE_ALN_SDC_ERR_0 V_ENABLE_ALN_SDC_ERR_0(1U)
27063 #define S_ENABLE_PF_UNTAGGED_TPT_1 5
27064 #define V_ENABLE_PF_UNTAGGED_TPT_1(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_1)
27065 #define F_ENABLE_PF_UNTAGGED_TPT_1 V_ENABLE_PF_UNTAGGED_TPT_1(1U)
27067 #define S_ENABLE_PF_UNTAGGED_TPT_0 4
27068 #define V_ENABLE_PF_UNTAGGED_TPT_0(x) ((x) << S_ENABLE_PF_UNTAGGED_TPT_0)
27069 #define F_ENABLE_PF_UNTAGGED_TPT_0 V_ENABLE_PF_UNTAGGED_TPT_0(1U)
27071 #define S_ENABLE_PF_PBL_1 3
27072 #define V_ENABLE_PF_PBL_1(x) ((x) << S_ENABLE_PF_PBL_1)
27073 #define F_ENABLE_PF_PBL_1 V_ENABLE_PF_PBL_1(1U)
27075 #define S_ENABLE_PF_PBL_0 2
27076 #define V_ENABLE_PF_PBL_0(x) ((x) << S_ENABLE_PF_PBL_0)
27077 #define F_ENABLE_PF_PBL_0 V_ENABLE_PF_PBL_0(1U)
27079 #define S_ENABLE_DDP_HINT_1 1
27080 #define V_ENABLE_DDP_HINT_1(x) ((x) << S_ENABLE_DDP_HINT_1)
27081 #define F_ENABLE_DDP_HINT_1 V_ENABLE_DDP_HINT_1(1U)
27083 #define S_ENABLE_DDP_HINT_0 0
27084 #define V_ENABLE_DDP_HINT_0(x) ((x) << S_ENABLE_DDP_HINT_0)
27085 #define F_ENABLE_DDP_HINT_0 V_ENABLE_DDP_HINT_0(1U)
27087 #define A_ULP_RX_RQE_PBL_MULTIPLE_OUTSTANDING_CNT 0x19278
27089 #define S_PIO_RQE_PBL_MULTIPLE_CNT 0
27090 #define M_PIO_RQE_PBL_MULTIPLE_CNT 0xfU
27091 #define V_PIO_RQE_PBL_MULTIPLE_CNT(x) ((x) << S_PIO_RQE_PBL_MULTIPLE_CNT)
27092 #define G_PIO_RQE_PBL_MULTIPLE_CNT(x) (((x) >> S_PIO_RQE_PBL_MULTIPLE_CNT) & M_PIO_RQE_PBL_MULTIPLE_CNT)
27094 #define A_ULP_RX_ATOMIC_LEN 0x1927c
27096 #define S_ATOMIC_RPL_LEN 16
27097 #define M_ATOMIC_RPL_LEN 0xffU
27098 #define V_ATOMIC_RPL_LEN(x) ((x) << S_ATOMIC_RPL_LEN)
27099 #define G_ATOMIC_RPL_LEN(x) (((x) >> S_ATOMIC_RPL_LEN) & M_ATOMIC_RPL_LEN)
27101 #define S_ATOMIC_REQ_LEN 8
27102 #define M_ATOMIC_REQ_LEN 0xffU
27103 #define V_ATOMIC_REQ_LEN(x) ((x) << S_ATOMIC_REQ_LEN)
27104 #define G_ATOMIC_REQ_LEN(x) (((x) >> S_ATOMIC_REQ_LEN) & M_ATOMIC_REQ_LEN)
27106 #define S_ATOMIC_IMMEDIATE_LEN 0
27107 #define M_ATOMIC_IMMEDIATE_LEN 0xffU
27108 #define V_ATOMIC_IMMEDIATE_LEN(x) ((x) << S_ATOMIC_IMMEDIATE_LEN)
27109 #define G_ATOMIC_IMMEDIATE_LEN(x) (((x) >> S_ATOMIC_IMMEDIATE_LEN) & M_ATOMIC_IMMEDIATE_LEN)
27111 #define A_ULP_RX_CGEN_GLOBAL 0x19280
27112 #define A_ULP_RX_CTX_SKIP_MA_REQ 0x19284
27114 #define S_CLEAR_CTX_ERR_CNT1 3
27115 #define V_CLEAR_CTX_ERR_CNT1(x) ((x) << S_CLEAR_CTX_ERR_CNT1)
27116 #define F_CLEAR_CTX_ERR_CNT1 V_CLEAR_CTX_ERR_CNT1(1U)
27118 #define S_CLEAR_CTX_ERR_CNT0 2
27119 #define V_CLEAR_CTX_ERR_CNT0(x) ((x) << S_CLEAR_CTX_ERR_CNT0)
27120 #define F_CLEAR_CTX_ERR_CNT0 V_CLEAR_CTX_ERR_CNT0(1U)
27122 #define S_SKIP_MA_REQ_EN1 1
27123 #define V_SKIP_MA_REQ_EN1(x) ((x) << S_SKIP_MA_REQ_EN1)
27124 #define F_SKIP_MA_REQ_EN1 V_SKIP_MA_REQ_EN1(1U)
27126 #define S_SKIP_MA_REQ_EN0 0
27127 #define V_SKIP_MA_REQ_EN0(x) ((x) << S_SKIP_MA_REQ_EN0)
27128 #define F_SKIP_MA_REQ_EN0 V_SKIP_MA_REQ_EN0(1U)
27130 #define A_ULP_RX_CHNL0_CTX_ERROR_COUNT_PER_TID 0x19288
27131 #define A_ULP_RX_CHNL1_CTX_ERROR_COUNT_PER_TID 0x1928c
27132 #define A_ULP_RX_MSN_CHECK_ENABLE 0x19290
27134 #define S_RD_OR_TERM_MSN_CHECK_ENABLE 2
27135 #define V_RD_OR_TERM_MSN_CHECK_ENABLE(x) ((x) << S_RD_OR_TERM_MSN_CHECK_ENABLE)
27136 #define F_RD_OR_TERM_MSN_CHECK_ENABLE V_RD_OR_TERM_MSN_CHECK_ENABLE(1U)
27138 #define S_ATOMIC_OP_MSN_CHECK_ENABLE 1
27139 #define V_ATOMIC_OP_MSN_CHECK_ENABLE(x) ((x) << S_ATOMIC_OP_MSN_CHECK_ENABLE)
27140 #define F_ATOMIC_OP_MSN_CHECK_ENABLE V_ATOMIC_OP_MSN_CHECK_ENABLE(1U)
27142 #define S_SEND_MSN_CHECK_ENABLE 0
27143 #define V_SEND_MSN_CHECK_ENABLE(x) ((x) << S_SEND_MSN_CHECK_ENABLE)
27144 #define F_SEND_MSN_CHECK_ENABLE V_SEND_MSN_CHECK_ENABLE(1U)
27146 /* registers for module SF */
27147 #define SF_BASE_ADDR 0x193f8
27149 #define A_SF_DATA 0x193f8
27150 #define A_SF_OP 0x193fc
27152 #define S_SF_LOCK 4
27153 #define V_SF_LOCK(x) ((x) << S_SF_LOCK)
27154 #define F_SF_LOCK V_SF_LOCK(1U)
27157 #define V_CONT(x) ((x) << S_CONT)
27158 #define F_CONT V_CONT(1U)
27160 #define S_BYTECNT 1
27161 #define M_BYTECNT 0x3U
27162 #define V_BYTECNT(x) ((x) << S_BYTECNT)
27163 #define G_BYTECNT(x) (((x) >> S_BYTECNT) & M_BYTECNT)
27165 /* registers for module PL */
27166 #define PL_BASE_ADDR 0x19400
27168 #define A_PL_VF_WHOAMI 0x0
27170 #define S_PORTXMAP 24
27171 #define M_PORTXMAP 0x7U
27172 #define V_PORTXMAP(x) ((x) << S_PORTXMAP)
27173 #define G_PORTXMAP(x) (((x) >> S_PORTXMAP) & M_PORTXMAP)
27175 #define S_SOURCEBUS 16
27176 #define M_SOURCEBUS 0x3U
27177 #define V_SOURCEBUS(x) ((x) << S_SOURCEBUS)
27178 #define G_SOURCEBUS(x) (((x) >> S_SOURCEBUS) & M_SOURCEBUS)
27180 #define S_SOURCEPF 8
27181 #define M_SOURCEPF 0x7U
27182 #define V_SOURCEPF(x) ((x) << S_SOURCEPF)
27183 #define G_SOURCEPF(x) (((x) >> S_SOURCEPF) & M_SOURCEPF)
27186 #define V_ISVF(x) ((x) << S_ISVF)
27187 #define F_ISVF V_ISVF(1U)
27190 #define M_VFID 0x7fU
27191 #define V_VFID(x) ((x) << S_VFID)
27192 #define G_VFID(x) (((x) >> S_VFID) & M_VFID)
27194 #define A_PL_VF_REV 0x4
27197 #define M_CHIPID 0xfU
27198 #define V_CHIPID(x) ((x) << S_CHIPID)
27199 #define G_CHIPID(x) (((x) >> S_CHIPID) & M_CHIPID)
27201 #define A_PL_VF_REVISION 0x8
27202 #define A_PL_PF_INT_CAUSE 0x3c0
27205 #define V_PFSW(x) ((x) << S_PFSW)
27206 #define F_PFSW V_PFSW(1U)
27209 #define V_PFSGE(x) ((x) << S_PFSGE)
27210 #define F_PFSGE V_PFSGE(1U)
27213 #define V_PFCIM(x) ((x) << S_PFCIM)
27214 #define F_PFCIM V_PFCIM(1U)
27217 #define V_PFMPS(x) ((x) << S_PFMPS)
27218 #define F_PFMPS V_PFMPS(1U)
27220 #define A_PL_PF_INT_ENABLE 0x3c4
27221 #define A_PL_PF_CTL 0x3c8
27224 #define V_SWINT(x) ((x) << S_SWINT)
27225 #define F_SWINT V_SWINT(1U)
27227 #define A_PL_WHOAMI 0x19400
27228 #define A_PL_PERR_CAUSE 0x19404
27231 #define V_UART(x) ((x) << S_UART)
27232 #define F_UART V_UART(1U)
27234 #define S_ULP_TX 27
27235 #define V_ULP_TX(x) ((x) << S_ULP_TX)
27236 #define F_ULP_TX V_ULP_TX(1U)
27239 #define V_SGE(x) ((x) << S_SGE)
27240 #define F_SGE V_SGE(1U)
27243 #define V_HMA(x) ((x) << S_HMA)
27244 #define F_HMA V_HMA(1U)
27246 #define S_CPL_SWITCH 24
27247 #define V_CPL_SWITCH(x) ((x) << S_CPL_SWITCH)
27248 #define F_CPL_SWITCH V_CPL_SWITCH(1U)
27250 #define S_ULP_RX 23
27251 #define V_ULP_RX(x) ((x) << S_ULP_RX)
27252 #define F_ULP_RX V_ULP_RX(1U)
27255 #define V_PM_RX(x) ((x) << S_PM_RX)
27256 #define F_PM_RX V_PM_RX(1U)
27259 #define V_PM_TX(x) ((x) << S_PM_TX)
27260 #define F_PM_TX V_PM_TX(1U)
27263 #define V_MA(x) ((x) << S_MA)
27264 #define F_MA V_MA(1U)
27267 #define V_TP(x) ((x) << S_TP)
27268 #define F_TP V_TP(1U)
27271 #define V_LE(x) ((x) << S_LE)
27272 #define F_LE V_LE(1U)
27275 #define V_EDC1(x) ((x) << S_EDC1)
27276 #define F_EDC1 V_EDC1(1U)
27279 #define V_EDC0(x) ((x) << S_EDC0)
27280 #define F_EDC0 V_EDC0(1U)
27283 #define V_MC(x) ((x) << S_MC)
27284 #define F_MC V_MC(1U)
27287 #define V_PCIE(x) ((x) << S_PCIE)
27288 #define F_PCIE V_PCIE(1U)
27291 #define V_PMU(x) ((x) << S_PMU)
27292 #define F_PMU V_PMU(1U)
27294 #define S_XGMAC_KR1 12
27295 #define V_XGMAC_KR1(x) ((x) << S_XGMAC_KR1)
27296 #define F_XGMAC_KR1 V_XGMAC_KR1(1U)
27298 #define S_XGMAC_KR0 11
27299 #define V_XGMAC_KR0(x) ((x) << S_XGMAC_KR0)
27300 #define F_XGMAC_KR0 V_XGMAC_KR0(1U)
27302 #define S_XGMAC1 10
27303 #define V_XGMAC1(x) ((x) << S_XGMAC1)
27304 #define F_XGMAC1 V_XGMAC1(1U)
27307 #define V_XGMAC0(x) ((x) << S_XGMAC0)
27308 #define F_XGMAC0 V_XGMAC0(1U)
27311 #define V_SMB(x) ((x) << S_SMB)
27312 #define F_SMB V_SMB(1U)
27315 #define V_SF(x) ((x) << S_SF)
27316 #define F_SF V_SF(1U)
27319 #define V_PL(x) ((x) << S_PL)
27320 #define F_PL V_PL(1U)
27323 #define V_NCSI(x) ((x) << S_NCSI)
27324 #define F_NCSI V_NCSI(1U)
27327 #define V_MPS(x) ((x) << S_MPS)
27328 #define F_MPS V_MPS(1U)
27331 #define V_MI(x) ((x) << S_MI)
27332 #define F_MI V_MI(1U)
27335 #define V_DBG(x) ((x) << S_DBG)
27336 #define F_DBG V_DBG(1U)
27339 #define V_I2CM(x) ((x) << S_I2CM)
27340 #define F_I2CM V_I2CM(1U)
27343 #define V_CIM(x) ((x) << S_CIM)
27344 #define F_CIM V_CIM(1U)
27347 #define V_MC1(x) ((x) << S_MC1)
27348 #define F_MC1 V_MC1(1U)
27351 #define V_MC0(x) ((x) << S_MC0)
27352 #define F_MC0 V_MC0(1U)
27355 #define V_ANYMAC(x) ((x) << S_ANYMAC)
27356 #define F_ANYMAC V_ANYMAC(1U)
27358 #define A_PL_PERR_ENABLE 0x19408
27359 #define A_PL_INT_CAUSE 0x1940c
27362 #define V_FLR(x) ((x) << S_FLR)
27363 #define F_FLR V_FLR(1U)
27365 #define S_SW_CIM 29
27366 #define V_SW_CIM(x) ((x) << S_SW_CIM)
27367 #define F_SW_CIM V_SW_CIM(1U)
27370 #define V_MAC3(x) ((x) << S_MAC3)
27371 #define F_MAC3 V_MAC3(1U)
27374 #define V_MAC2(x) ((x) << S_MAC2)
27375 #define F_MAC2 V_MAC2(1U)
27378 #define V_MAC1(x) ((x) << S_MAC1)
27379 #define F_MAC1 V_MAC1(1U)
27382 #define V_MAC0(x) ((x) << S_MAC0)
27383 #define F_MAC0 V_MAC0(1U)
27385 #define A_PL_INT_ENABLE 0x19410
27386 #define A_PL_INT_MAP0 0x19414
27388 #define S_MAPNCSI 16
27389 #define M_MAPNCSI 0x1ffU
27390 #define V_MAPNCSI(x) ((x) << S_MAPNCSI)
27391 #define G_MAPNCSI(x) (((x) >> S_MAPNCSI) & M_MAPNCSI)
27393 #define S_MAPDEFAULT 0
27394 #define M_MAPDEFAULT 0x1ffU
27395 #define V_MAPDEFAULT(x) ((x) << S_MAPDEFAULT)
27396 #define G_MAPDEFAULT(x) (((x) >> S_MAPDEFAULT) & M_MAPDEFAULT)
27398 #define A_PL_INT_MAP1 0x19418
27400 #define S_MAPXGMAC1 16
27401 #define M_MAPXGMAC1 0x1ffU
27402 #define V_MAPXGMAC1(x) ((x) << S_MAPXGMAC1)
27403 #define G_MAPXGMAC1(x) (((x) >> S_MAPXGMAC1) & M_MAPXGMAC1)
27405 #define S_MAPXGMAC0 0
27406 #define M_MAPXGMAC0 0x1ffU
27407 #define V_MAPXGMAC0(x) ((x) << S_MAPXGMAC0)
27408 #define G_MAPXGMAC0(x) (((x) >> S_MAPXGMAC0) & M_MAPXGMAC0)
27410 #define S_MAPMAC1 16
27411 #define M_MAPMAC1 0x1ffU
27412 #define V_MAPMAC1(x) ((x) << S_MAPMAC1)
27413 #define G_MAPMAC1(x) (((x) >> S_MAPMAC1) & M_MAPMAC1)
27415 #define S_MAPMAC0 0
27416 #define M_MAPMAC0 0x1ffU
27417 #define V_MAPMAC0(x) ((x) << S_MAPMAC0)
27418 #define G_MAPMAC0(x) (((x) >> S_MAPMAC0) & M_MAPMAC0)
27420 #define A_PL_INT_MAP2 0x1941c
27422 #define S_MAPXGMAC_KR1 16
27423 #define M_MAPXGMAC_KR1 0x1ffU
27424 #define V_MAPXGMAC_KR1(x) ((x) << S_MAPXGMAC_KR1)
27425 #define G_MAPXGMAC_KR1(x) (((x) >> S_MAPXGMAC_KR1) & M_MAPXGMAC_KR1)
27427 #define S_MAPXGMAC_KR0 0
27428 #define M_MAPXGMAC_KR0 0x1ffU
27429 #define V_MAPXGMAC_KR0(x) ((x) << S_MAPXGMAC_KR0)
27430 #define G_MAPXGMAC_KR0(x) (((x) >> S_MAPXGMAC_KR0) & M_MAPXGMAC_KR0)
27432 #define S_MAPMAC3 16
27433 #define M_MAPMAC3 0x1ffU
27434 #define V_MAPMAC3(x) ((x) << S_MAPMAC3)
27435 #define G_MAPMAC3(x) (((x) >> S_MAPMAC3) & M_MAPMAC3)
27437 #define S_MAPMAC2 0
27438 #define M_MAPMAC2 0x1ffU
27439 #define V_MAPMAC2(x) ((x) << S_MAPMAC2)
27440 #define G_MAPMAC2(x) (((x) >> S_MAPMAC2) & M_MAPMAC2)
27442 #define A_PL_INT_MAP3 0x19420
27445 #define M_MAPMI 0x1ffU
27446 #define V_MAPMI(x) ((x) << S_MAPMI)
27447 #define G_MAPMI(x) (((x) >> S_MAPMI) & M_MAPMI)
27450 #define M_MAPSMB 0x1ffU
27451 #define V_MAPSMB(x) ((x) << S_MAPSMB)
27452 #define G_MAPSMB(x) (((x) >> S_MAPSMB) & M_MAPSMB)
27454 #define A_PL_INT_MAP4 0x19424
27456 #define S_MAPDBG 16
27457 #define M_MAPDBG 0x1ffU
27458 #define V_MAPDBG(x) ((x) << S_MAPDBG)
27459 #define G_MAPDBG(x) (((x) >> S_MAPDBG) & M_MAPDBG)
27461 #define S_MAPI2CM 0
27462 #define M_MAPI2CM 0x1ffU
27463 #define V_MAPI2CM(x) ((x) << S_MAPI2CM)
27464 #define G_MAPI2CM(x) (((x) >> S_MAPI2CM) & M_MAPI2CM)
27466 #define A_PL_RST 0x19428
27468 #define S_FATALPERREN 3
27469 #define V_FATALPERREN(x) ((x) << S_FATALPERREN)
27470 #define F_FATALPERREN V_FATALPERREN(1U)
27472 #define S_SWINTCIM 2
27473 #define V_SWINTCIM(x) ((x) << S_SWINTCIM)
27474 #define F_SWINTCIM V_SWINTCIM(1U)
27477 #define V_PIORST(x) ((x) << S_PIORST)
27478 #define F_PIORST V_PIORST(1U)
27480 #define S_PIORSTMODE 0
27481 #define V_PIORSTMODE(x) ((x) << S_PIORSTMODE)
27482 #define F_PIORSTMODE V_PIORSTMODE(1U)
27484 #define S_AUTOPCIEPAUSE 4
27485 #define V_AUTOPCIEPAUSE(x) ((x) << S_AUTOPCIEPAUSE)
27486 #define F_AUTOPCIEPAUSE V_AUTOPCIEPAUSE(1U)
27488 #define A_PL_PL_PERR_INJECT 0x1942c
27490 #define S_PL_MEMSEL 1
27491 #define V_PL_MEMSEL(x) ((x) << S_PL_MEMSEL)
27492 #define F_PL_MEMSEL V_PL_MEMSEL(1U)
27494 #define A_PL_PL_INT_CAUSE 0x19430
27496 #define S_PF_ENABLEERR 5
27497 #define V_PF_ENABLEERR(x) ((x) << S_PF_ENABLEERR)
27498 #define F_PF_ENABLEERR V_PF_ENABLEERR(1U)
27500 #define S_FATALPERR 4
27501 #define V_FATALPERR(x) ((x) << S_FATALPERR)
27502 #define F_FATALPERR V_FATALPERR(1U)
27504 #define S_INVALIDACCESS 3
27505 #define V_INVALIDACCESS(x) ((x) << S_INVALIDACCESS)
27506 #define F_INVALIDACCESS V_INVALIDACCESS(1U)
27508 #define S_TIMEOUT 2
27509 #define V_TIMEOUT(x) ((x) << S_TIMEOUT)
27510 #define F_TIMEOUT V_TIMEOUT(1U)
27513 #define V_PLERR(x) ((x) << S_PLERR)
27514 #define F_PLERR V_PLERR(1U)
27516 #define S_PERRVFID 0
27517 #define V_PERRVFID(x) ((x) << S_PERRVFID)
27518 #define F_PERRVFID V_PERRVFID(1U)
27520 #define S_PL_BUSPERR 6
27521 #define V_PL_BUSPERR(x) ((x) << S_PL_BUSPERR)
27522 #define F_PL_BUSPERR V_PL_BUSPERR(1U)
27524 #define A_PL_PL_INT_ENABLE 0x19434
27525 #define A_PL_PL_PERR_ENABLE 0x19438
27526 #define A_PL_REV 0x1943c
27530 #define V_REV(x) ((x) << S_REV)
27531 #define G_REV(x) (((x) >> S_REV) & M_REV)
27533 #define A_PL_PCIE_LINK 0x19440
27535 #define S_LN0_AESTAT 26
27536 #define M_LN0_AESTAT 0x7U
27537 #define V_LN0_AESTAT(x) ((x) << S_LN0_AESTAT)
27538 #define G_LN0_AESTAT(x) (((x) >> S_LN0_AESTAT) & M_LN0_AESTAT)
27540 #define S_LN0_AECMD 23
27541 #define M_LN0_AECMD 0x7U
27542 #define V_LN0_AECMD(x) ((x) << S_LN0_AECMD)
27543 #define G_LN0_AECMD(x) (((x) >> S_LN0_AECMD) & M_LN0_AECMD)
27545 #define S_PCIE_SPEED 8
27546 #define M_PCIE_SPEED 0x3U
27547 #define V_PCIE_SPEED(x) ((x) << S_PCIE_SPEED)
27548 #define G_PCIE_SPEED(x) (((x) >> S_PCIE_SPEED) & M_PCIE_SPEED)
27551 #define M_LTSSM 0x3fU
27552 #define V_LTSSM(x) ((x) << S_LTSSM)
27553 #define G_LTSSM(x) (((x) >> S_LTSSM) & M_LTSSM)
27555 #define A_PL_PCIE_CTL_STAT 0x19444
27557 #define S_PCIE_STATUS 16
27558 #define M_PCIE_STATUS 0xffffU
27559 #define V_PCIE_STATUS(x) ((x) << S_PCIE_STATUS)
27560 #define G_PCIE_STATUS(x) (((x) >> S_PCIE_STATUS) & M_PCIE_STATUS)
27562 #define S_PCIE_CONTROL 0
27563 #define M_PCIE_CONTROL 0xffffU
27564 #define V_PCIE_CONTROL(x) ((x) << S_PCIE_CONTROL)
27565 #define G_PCIE_CONTROL(x) (((x) >> S_PCIE_CONTROL) & M_PCIE_CONTROL)
27567 #define A_PL_SEMAPHORE_CTL 0x1944c
27569 #define S_LOCKSTATUS 16
27570 #define M_LOCKSTATUS 0xffU
27571 #define V_LOCKSTATUS(x) ((x) << S_LOCKSTATUS)
27572 #define G_LOCKSTATUS(x) (((x) >> S_LOCKSTATUS) & M_LOCKSTATUS)
27574 #define S_OWNEROVERRIDE 8
27575 #define V_OWNEROVERRIDE(x) ((x) << S_OWNEROVERRIDE)
27576 #define F_OWNEROVERRIDE V_OWNEROVERRIDE(1U)
27578 #define S_ENABLEPF 0
27579 #define M_ENABLEPF 0xffU
27580 #define V_ENABLEPF(x) ((x) << S_ENABLEPF)
27581 #define G_ENABLEPF(x) (((x) >> S_ENABLEPF) & M_ENABLEPF)
27583 #define A_PL_SEMAPHORE_LOCK 0x19450
27585 #define S_SEMLOCK 31
27586 #define V_SEMLOCK(x) ((x) << S_SEMLOCK)
27587 #define F_SEMLOCK V_SEMLOCK(1U)
27589 #define S_SEMSRCBUS 3
27590 #define M_SEMSRCBUS 0x3U
27591 #define V_SEMSRCBUS(x) ((x) << S_SEMSRCBUS)
27592 #define G_SEMSRCBUS(x) (((x) >> S_SEMSRCBUS) & M_SEMSRCBUS)
27594 #define S_SEMSRCPF 0
27595 #define M_SEMSRCPF 0x7U
27596 #define V_SEMSRCPF(x) ((x) << S_SEMSRCPF)
27597 #define G_SEMSRCPF(x) (((x) >> S_SEMSRCPF) & M_SEMSRCPF)
27599 #define A_PL_PF_ENABLE 0x19470
27601 #define S_PF_ENABLE 0
27602 #define M_PF_ENABLE 0xffU
27603 #define V_PF_ENABLE(x) ((x) << S_PF_ENABLE)
27604 #define G_PF_ENABLE(x) (((x) >> S_PF_ENABLE) & M_PF_ENABLE)
27606 #define A_PL_PORTX_MAP 0x19474
27609 #define M_MAP7 0x7U
27610 #define V_MAP7(x) ((x) << S_MAP7)
27611 #define G_MAP7(x) (((x) >> S_MAP7) & M_MAP7)
27614 #define M_MAP6 0x7U
27615 #define V_MAP6(x) ((x) << S_MAP6)
27616 #define G_MAP6(x) (((x) >> S_MAP6) & M_MAP6)
27619 #define M_MAP5 0x7U
27620 #define V_MAP5(x) ((x) << S_MAP5)
27621 #define G_MAP5(x) (((x) >> S_MAP5) & M_MAP5)
27624 #define M_MAP4 0x7U
27625 #define V_MAP4(x) ((x) << S_MAP4)
27626 #define G_MAP4(x) (((x) >> S_MAP4) & M_MAP4)
27629 #define M_MAP3 0x7U
27630 #define V_MAP3(x) ((x) << S_MAP3)
27631 #define G_MAP3(x) (((x) >> S_MAP3) & M_MAP3)
27634 #define M_MAP2 0x7U
27635 #define V_MAP2(x) ((x) << S_MAP2)
27636 #define G_MAP2(x) (((x) >> S_MAP2) & M_MAP2)
27639 #define M_MAP1 0x7U
27640 #define V_MAP1(x) ((x) << S_MAP1)
27641 #define G_MAP1(x) (((x) >> S_MAP1) & M_MAP1)
27644 #define M_MAP0 0x7U
27645 #define V_MAP0(x) ((x) << S_MAP0)
27646 #define G_MAP0(x) (((x) >> S_MAP0) & M_MAP0)
27648 #define A_PL_VF_SLICE_L 0x19490
27650 #define S_LIMITADDR 16
27651 #define M_LIMITADDR 0x3ffU
27652 #define V_LIMITADDR(x) ((x) << S_LIMITADDR)
27653 #define G_LIMITADDR(x) (((x) >> S_LIMITADDR) & M_LIMITADDR)
27655 #define S_SLICEBASEADDR 0
27656 #define M_SLICEBASEADDR 0x3ffU
27657 #define V_SLICEBASEADDR(x) ((x) << S_SLICEBASEADDR)
27658 #define G_SLICEBASEADDR(x) (((x) >> S_SLICEBASEADDR) & M_SLICEBASEADDR)
27660 #define A_PL_VF_SLICE_H 0x19494
27662 #define S_MODINDX 16
27663 #define M_MODINDX 0x7U
27664 #define V_MODINDX(x) ((x) << S_MODINDX)
27665 #define G_MODINDX(x) (((x) >> S_MODINDX) & M_MODINDX)
27667 #define S_MODOFFSET 0
27668 #define M_MODOFFSET 0x3ffU
27669 #define V_MODOFFSET(x) ((x) << S_MODOFFSET)
27670 #define G_MODOFFSET(x) (((x) >> S_MODOFFSET) & M_MODOFFSET)
27672 #define A_PL_FLR_VF_STATUS 0x194d0
27673 #define A_PL_FLR_PF_STATUS 0x194e0
27676 #define M_FLR_PF 0xffU
27677 #define V_FLR_PF(x) ((x) << S_FLR_PF)
27678 #define G_FLR_PF(x) (((x) >> S_FLR_PF) & M_FLR_PF)
27680 #define A_PL_TIMEOUT_CTL 0x194f0
27682 #define S_PL_TIMEOUT 0
27683 #define M_PL_TIMEOUT 0xffffU
27684 #define V_PL_TIMEOUT(x) ((x) << S_PL_TIMEOUT)
27685 #define G_PL_TIMEOUT(x) (((x) >> S_PL_TIMEOUT) & M_PL_TIMEOUT)
27687 #define S_PERRCAPTURE 16
27688 #define V_PERRCAPTURE(x) ((x) << S_PERRCAPTURE)
27689 #define F_PERRCAPTURE V_PERRCAPTURE(1U)
27691 #define A_PL_TIMEOUT_STATUS0 0x194f4
27693 #define S_PL_TOADDR 2
27694 #define M_PL_TOADDR 0xfffffffU
27695 #define V_PL_TOADDR(x) ((x) << S_PL_TOADDR)
27696 #define G_PL_TOADDR(x) (((x) >> S_PL_TOADDR) & M_PL_TOADDR)
27698 #define A_PL_TIMEOUT_STATUS1 0x194f8
27700 #define S_PL_TOVALID 31
27701 #define V_PL_TOVALID(x) ((x) << S_PL_TOVALID)
27702 #define F_PL_TOVALID V_PL_TOVALID(1U)
27705 #define V_WRITE(x) ((x) << S_WRITE)
27706 #define F_WRITE V_WRITE(1U)
27708 #define S_PL_TOBUS 20
27709 #define M_PL_TOBUS 0x3U
27710 #define V_PL_TOBUS(x) ((x) << S_PL_TOBUS)
27711 #define G_PL_TOBUS(x) (((x) >> S_PL_TOBUS) & M_PL_TOBUS)
27714 #define V_RGN(x) ((x) << S_RGN)
27715 #define F_RGN V_RGN(1U)
27717 #define S_PL_TOPF 16
27718 #define M_PL_TOPF 0x7U
27719 #define V_PL_TOPF(x) ((x) << S_PL_TOPF)
27720 #define G_PL_TOPF(x) (((x) >> S_PL_TOPF) & M_PL_TOPF)
27722 #define S_PL_TORID 0
27723 #define M_PL_TORID 0xffffU
27724 #define V_PL_TORID(x) ((x) << S_PL_TORID)
27725 #define G_PL_TORID(x) (((x) >> S_PL_TORID) & M_PL_TORID)
27727 #define S_VALIDPERR 30
27728 #define V_VALIDPERR(x) ((x) << S_VALIDPERR)
27729 #define F_VALIDPERR V_VALIDPERR(1U)
27731 #define S_PL_TOVFID 0
27732 #define M_PL_TOVFID 0xffU
27733 #define V_PL_TOVFID(x) ((x) << S_PL_TOVFID)
27734 #define G_PL_TOVFID(x) (((x) >> S_PL_TOVFID) & M_PL_TOVFID)
27736 #define A_PL_VFID_MAP 0x19800
27738 #define S_VFID_VLD 7
27739 #define V_VFID_VLD(x) ((x) << S_VFID_VLD)
27740 #define F_VFID_VLD V_VFID_VLD(1U)
27742 /* registers for module LE */
27743 #define LE_BASE_ADDR 0x19c00
27745 #define A_LE_BUF_CONFIG 0x19c00
27746 #define A_LE_DB_CONFIG 0x19c04
27748 #define S_TCAMCMDOVLAPEN 21
27749 #define V_TCAMCMDOVLAPEN(x) ((x) << S_TCAMCMDOVLAPEN)
27750 #define F_TCAMCMDOVLAPEN V_TCAMCMDOVLAPEN(1U)
27752 #define S_HASHEN 20
27753 #define V_HASHEN(x) ((x) << S_HASHEN)
27754 #define F_HASHEN V_HASHEN(1U)
27756 #define S_ASBOTHSRCHEN 18
27757 #define V_ASBOTHSRCHEN(x) ((x) << S_ASBOTHSRCHEN)
27758 #define F_ASBOTHSRCHEN V_ASBOTHSRCHEN(1U)
27760 #define S_ASLIPCOMPEN 17
27761 #define V_ASLIPCOMPEN(x) ((x) << S_ASLIPCOMPEN)
27762 #define F_ASLIPCOMPEN V_ASLIPCOMPEN(1U)
27765 #define V_BUILD(x) ((x) << S_BUILD)
27766 #define F_BUILD V_BUILD(1U)
27768 #define S_FILTEREN 11
27769 #define V_FILTEREN(x) ((x) << S_FILTEREN)
27770 #define F_FILTEREN V_FILTEREN(1U)
27772 #define S_SYNMODE 7
27773 #define M_SYNMODE 0x3U
27774 #define V_SYNMODE(x) ((x) << S_SYNMODE)
27775 #define G_SYNMODE(x) (((x) >> S_SYNMODE) & M_SYNMODE)
27777 #define S_LEBUSEN 5
27778 #define V_LEBUSEN(x) ((x) << S_LEBUSEN)
27779 #define F_LEBUSEN V_LEBUSEN(1U)
27781 #define S_ELOOKDUMEN 4
27782 #define V_ELOOKDUMEN(x) ((x) << S_ELOOKDUMEN)
27783 #define F_ELOOKDUMEN V_ELOOKDUMEN(1U)
27785 #define S_IPV4ONLYEN 3
27786 #define V_IPV4ONLYEN(x) ((x) << S_IPV4ONLYEN)
27787 #define F_IPV4ONLYEN V_IPV4ONLYEN(1U)
27789 #define S_MOSTCMDOEN 2
27790 #define V_MOSTCMDOEN(x) ((x) << S_MOSTCMDOEN)
27791 #define F_MOSTCMDOEN V_MOSTCMDOEN(1U)
27793 #define S_DELACTSYNOEN 1
27794 #define V_DELACTSYNOEN(x) ((x) << S_DELACTSYNOEN)
27795 #define F_DELACTSYNOEN V_DELACTSYNOEN(1U)
27797 #define S_CMDOVERLAPDIS 0
27798 #define V_CMDOVERLAPDIS(x) ((x) << S_CMDOVERLAPDIS)
27799 #define F_CMDOVERLAPDIS V_CMDOVERLAPDIS(1U)
27801 #define S_MASKCMDOLAPDIS 26
27802 #define V_MASKCMDOLAPDIS(x) ((x) << S_MASKCMDOLAPDIS)
27803 #define F_MASKCMDOLAPDIS V_MASKCMDOLAPDIS(1U)
27805 #define S_IPV4HASHSIZEEN 25
27806 #define V_IPV4HASHSIZEEN(x) ((x) << S_IPV4HASHSIZEEN)
27807 #define F_IPV4HASHSIZEEN V_IPV4HASHSIZEEN(1U)
27809 #define S_PROTOCOLMASKEN 24
27810 #define V_PROTOCOLMASKEN(x) ((x) << S_PROTOCOLMASKEN)
27811 #define F_PROTOCOLMASKEN V_PROTOCOLMASKEN(1U)
27813 #define S_TUPLESIZEEN 23
27814 #define V_TUPLESIZEEN(x) ((x) << S_TUPLESIZEEN)
27815 #define F_TUPLESIZEEN V_TUPLESIZEEN(1U)
27817 #define S_SRVRSRAMEN 22
27818 #define V_SRVRSRAMEN(x) ((x) << S_SRVRSRAMEN)
27819 #define F_SRVRSRAMEN V_SRVRSRAMEN(1U)
27821 #define S_ASBOTHSRCHENPR 19
27822 #define V_ASBOTHSRCHENPR(x) ((x) << S_ASBOTHSRCHENPR)
27823 #define F_ASBOTHSRCHENPR V_ASBOTHSRCHENPR(1U)
27825 #define S_POCLIPTID0 15
27826 #define V_POCLIPTID0(x) ((x) << S_POCLIPTID0)
27827 #define F_POCLIPTID0 V_POCLIPTID0(1U)
27829 #define S_TCAMARBOFF 14
27830 #define V_TCAMARBOFF(x) ((x) << S_TCAMARBOFF)
27831 #define F_TCAMARBOFF V_TCAMARBOFF(1U)
27833 #define S_ACCNTFULLEN 13
27834 #define V_ACCNTFULLEN(x) ((x) << S_ACCNTFULLEN)
27835 #define F_ACCNTFULLEN V_ACCNTFULLEN(1U)
27837 #define S_FILTERRWNOCLIP 12
27838 #define V_FILTERRWNOCLIP(x) ((x) << S_FILTERRWNOCLIP)
27839 #define F_FILTERRWNOCLIP V_FILTERRWNOCLIP(1U)
27841 #define S_CRCHASH 10
27842 #define V_CRCHASH(x) ((x) << S_CRCHASH)
27843 #define F_CRCHASH V_CRCHASH(1U)
27845 #define S_COMPTID 9
27846 #define V_COMPTID(x) ((x) << S_COMPTID)
27847 #define F_COMPTID V_COMPTID(1U)
27849 #define S_SINGLETHREAD 6
27850 #define V_SINGLETHREAD(x) ((x) << S_SINGLETHREAD)
27851 #define F_SINGLETHREAD V_SINGLETHREAD(1U)
27853 #define A_LE_MISC 0x19c08
27855 #define S_CMPUNVAIL 0
27856 #define M_CMPUNVAIL 0xfU
27857 #define V_CMPUNVAIL(x) ((x) << S_CMPUNVAIL)
27858 #define G_CMPUNVAIL(x) (((x) >> S_CMPUNVAIL) & M_CMPUNVAIL)
27860 #define S_SRAMDEEPSLEEP_STAT 11
27861 #define V_SRAMDEEPSLEEP_STAT(x) ((x) << S_SRAMDEEPSLEEP_STAT)
27862 #define F_SRAMDEEPSLEEP_STAT V_SRAMDEEPSLEEP_STAT(1U)
27864 #define S_TCAMDEEPSLEEP1_STAT 10
27865 #define V_TCAMDEEPSLEEP1_STAT(x) ((x) << S_TCAMDEEPSLEEP1_STAT)
27866 #define F_TCAMDEEPSLEEP1_STAT V_TCAMDEEPSLEEP1_STAT(1U)
27868 #define S_TCAMDEEPSLEEP0_STAT 9
27869 #define V_TCAMDEEPSLEEP0_STAT(x) ((x) << S_TCAMDEEPSLEEP0_STAT)
27870 #define F_TCAMDEEPSLEEP0_STAT V_TCAMDEEPSLEEP0_STAT(1U)
27872 #define S_SRAMDEEPSLEEP 8
27873 #define V_SRAMDEEPSLEEP(x) ((x) << S_SRAMDEEPSLEEP)
27874 #define F_SRAMDEEPSLEEP V_SRAMDEEPSLEEP(1U)
27876 #define S_TCAMDEEPSLEEP1 7
27877 #define V_TCAMDEEPSLEEP1(x) ((x) << S_TCAMDEEPSLEEP1)
27878 #define F_TCAMDEEPSLEEP1 V_TCAMDEEPSLEEP1(1U)
27880 #define S_TCAMDEEPSLEEP0 6
27881 #define V_TCAMDEEPSLEEP0(x) ((x) << S_TCAMDEEPSLEEP0)
27882 #define F_TCAMDEEPSLEEP0 V_TCAMDEEPSLEEP0(1U)
27884 #define S_SRVRAMCLKOFF 5
27885 #define V_SRVRAMCLKOFF(x) ((x) << S_SRVRAMCLKOFF)
27886 #define F_SRVRAMCLKOFF V_SRVRAMCLKOFF(1U)
27888 #define S_HASHCLKOFF 4
27889 #define V_HASHCLKOFF(x) ((x) << S_HASHCLKOFF)
27890 #define F_HASHCLKOFF V_HASHCLKOFF(1U)
27892 #define A_LE_DB_ROUTING_TABLE_INDEX 0x19c10
27895 #define M_RTINDX 0x3fU
27896 #define V_RTINDX(x) ((x) << S_RTINDX)
27897 #define G_RTINDX(x) (((x) >> S_RTINDX) & M_RTINDX)
27899 #define A_LE_DB_FILTER_TABLE_INDEX 0x19c14
27902 #define M_FTINDX 0x3fU
27903 #define V_FTINDX(x) ((x) << S_FTINDX)
27904 #define G_FTINDX(x) (((x) >> S_FTINDX) & M_FTINDX)
27906 #define A_LE_DB_SERVER_INDEX 0x19c18
27909 #define M_SRINDX 0x3fU
27910 #define V_SRINDX(x) ((x) << S_SRINDX)
27911 #define G_SRINDX(x) (((x) >> S_SRINDX) & M_SRINDX)
27913 #define A_LE_DB_CLIP_TABLE_INDEX 0x19c1c
27915 #define S_CLIPTINDX 7
27916 #define M_CLIPTINDX 0x3fU
27917 #define V_CLIPTINDX(x) ((x) << S_CLIPTINDX)
27918 #define G_CLIPTINDX(x) (((x) >> S_CLIPTINDX) & M_CLIPTINDX)
27920 #define A_LE_DB_ACT_CNT_IPV4 0x19c20
27922 #define S_ACTCNTIPV4 0
27923 #define M_ACTCNTIPV4 0xfffffU
27924 #define V_ACTCNTIPV4(x) ((x) << S_ACTCNTIPV4)
27925 #define G_ACTCNTIPV4(x) (((x) >> S_ACTCNTIPV4) & M_ACTCNTIPV4)
27927 #define A_LE_DB_ACT_CNT_IPV6 0x19c24
27929 #define S_ACTCNTIPV6 0
27930 #define M_ACTCNTIPV6 0xfffffU
27931 #define V_ACTCNTIPV6(x) ((x) << S_ACTCNTIPV6)
27932 #define G_ACTCNTIPV6(x) (((x) >> S_ACTCNTIPV6) & M_ACTCNTIPV6)
27934 #define A_LE_DB_HASH_CONFIG 0x19c28
27936 #define S_HASHTIDSIZE 16
27937 #define M_HASHTIDSIZE 0x3fU
27938 #define V_HASHTIDSIZE(x) ((x) << S_HASHTIDSIZE)
27939 #define G_HASHTIDSIZE(x) (((x) >> S_HASHTIDSIZE) & M_HASHTIDSIZE)
27941 #define S_HASHSIZE 0
27942 #define M_HASHSIZE 0x3fU
27943 #define V_HASHSIZE(x) ((x) << S_HASHSIZE)
27944 #define G_HASHSIZE(x) (((x) >> S_HASHSIZE) & M_HASHSIZE)
27946 #define A_LE_DB_HASH_TABLE_BASE 0x19c2c
27947 #define A_LE_DB_HASH_TID_BASE 0x19c30
27948 #define A_LE_DB_SIZE 0x19c34
27949 #define A_LE_DB_INT_ENABLE 0x19c38
27951 #define S_MSGSEL 27
27952 #define M_MSGSEL 0x1fU
27953 #define V_MSGSEL(x) ((x) << S_MSGSEL)
27954 #define G_MSGSEL(x) (((x) >> S_MSGSEL) & M_MSGSEL)
27956 #define S_REQQPARERR 16
27957 #define V_REQQPARERR(x) ((x) << S_REQQPARERR)
27958 #define F_REQQPARERR V_REQQPARERR(1U)
27960 #define S_UNKNOWNCMD 15
27961 #define V_UNKNOWNCMD(x) ((x) << S_UNKNOWNCMD)
27962 #define F_UNKNOWNCMD V_UNKNOWNCMD(1U)
27964 #define S_DROPFILTERHIT 13
27965 #define V_DROPFILTERHIT(x) ((x) << S_DROPFILTERHIT)
27966 #define F_DROPFILTERHIT V_DROPFILTERHIT(1U)
27968 #define S_FILTERHIT 12
27969 #define V_FILTERHIT(x) ((x) << S_FILTERHIT)
27970 #define F_FILTERHIT V_FILTERHIT(1U)
27972 #define S_SYNCOOKIEOFF 11
27973 #define V_SYNCOOKIEOFF(x) ((x) << S_SYNCOOKIEOFF)
27974 #define F_SYNCOOKIEOFF V_SYNCOOKIEOFF(1U)
27976 #define S_SYNCOOKIEBAD 10
27977 #define V_SYNCOOKIEBAD(x) ((x) << S_SYNCOOKIEBAD)
27978 #define F_SYNCOOKIEBAD V_SYNCOOKIEBAD(1U)
27980 #define S_SYNCOOKIE 9
27981 #define V_SYNCOOKIE(x) ((x) << S_SYNCOOKIE)
27982 #define F_SYNCOOKIE V_SYNCOOKIE(1U)
27984 #define S_NFASRCHFAIL 8
27985 #define V_NFASRCHFAIL(x) ((x) << S_NFASRCHFAIL)
27986 #define F_NFASRCHFAIL V_NFASRCHFAIL(1U)
27988 #define S_ACTRGNFULL 7
27989 #define V_ACTRGNFULL(x) ((x) << S_ACTRGNFULL)
27990 #define F_ACTRGNFULL V_ACTRGNFULL(1U)
27992 #define S_PARITYERR 6
27993 #define V_PARITYERR(x) ((x) << S_PARITYERR)
27994 #define F_PARITYERR V_PARITYERR(1U)
27996 #define S_LIPMISS 5
27997 #define V_LIPMISS(x) ((x) << S_LIPMISS)
27998 #define F_LIPMISS V_LIPMISS(1U)
28001 #define V_LIP0(x) ((x) << S_LIP0)
28002 #define F_LIP0 V_LIP0(1U)
28005 #define V_MISS(x) ((x) << S_MISS)
28006 #define F_MISS V_MISS(1U)
28008 #define S_ROUTINGHIT 2
28009 #define V_ROUTINGHIT(x) ((x) << S_ROUTINGHIT)
28010 #define F_ROUTINGHIT V_ROUTINGHIT(1U)
28012 #define S_ACTIVEHIT 1
28013 #define V_ACTIVEHIT(x) ((x) << S_ACTIVEHIT)
28014 #define F_ACTIVEHIT V_ACTIVEHIT(1U)
28016 #define S_SERVERHIT 0
28017 #define V_SERVERHIT(x) ((x) << S_SERVERHIT)
28018 #define F_SERVERHIT V_SERVERHIT(1U)
28020 #define S_ACTCNTIPV6TZERO 21
28021 #define V_ACTCNTIPV6TZERO(x) ((x) << S_ACTCNTIPV6TZERO)
28022 #define F_ACTCNTIPV6TZERO V_ACTCNTIPV6TZERO(1U)
28024 #define S_ACTCNTIPV4TZERO 20
28025 #define V_ACTCNTIPV4TZERO(x) ((x) << S_ACTCNTIPV4TZERO)
28026 #define F_ACTCNTIPV4TZERO V_ACTCNTIPV4TZERO(1U)
28028 #define S_ACTCNTIPV6ZERO 19
28029 #define V_ACTCNTIPV6ZERO(x) ((x) << S_ACTCNTIPV6ZERO)
28030 #define F_ACTCNTIPV6ZERO V_ACTCNTIPV6ZERO(1U)
28032 #define S_ACTCNTIPV4ZERO 18
28033 #define V_ACTCNTIPV4ZERO(x) ((x) << S_ACTCNTIPV4ZERO)
28034 #define F_ACTCNTIPV4ZERO V_ACTCNTIPV4ZERO(1U)
28036 #define S_MARSPPARERR 17
28037 #define V_MARSPPARERR(x) ((x) << S_MARSPPARERR)
28038 #define F_MARSPPARERR V_MARSPPARERR(1U)
28040 #define S_VFPARERR 14
28041 #define V_VFPARERR(x) ((x) << S_VFPARERR)
28042 #define F_VFPARERR V_VFPARERR(1U)
28044 #define A_LE_DB_INT_CAUSE 0x19c3c
28045 #define A_LE_DB_INT_TID 0x19c40
28048 #define M_INTTID 0xfffffU
28049 #define V_INTTID(x) ((x) << S_INTTID)
28050 #define G_INTTID(x) (((x) >> S_INTTID) & M_INTTID)
28052 #define A_LE_DB_INT_PTID 0x19c44
28054 #define S_INTPTID 0
28055 #define M_INTPTID 0xfffffU
28056 #define V_INTPTID(x) ((x) << S_INTPTID)
28057 #define G_INTPTID(x) (((x) >> S_INTPTID) & M_INTPTID)
28059 #define A_LE_DB_INT_INDEX 0x19c48
28061 #define S_INTINDEX 0
28062 #define M_INTINDEX 0xfffffU
28063 #define V_INTINDEX(x) ((x) << S_INTINDEX)
28064 #define G_INTINDEX(x) (((x) >> S_INTINDEX) & M_INTINDEX)
28066 #define A_LE_DB_INT_CMD 0x19c4c
28069 #define M_INTCMD 0xfU
28070 #define V_INTCMD(x) ((x) << S_INTCMD)
28071 #define G_INTCMD(x) (((x) >> S_INTCMD) & M_INTCMD)
28073 #define A_LE_DB_MASK_IPV4 0x19c50
28074 #define A_LE_T5_DB_MASK_IPV4 0x19c50
28075 #define A_LE_DB_ACT_CNT_IPV4_TCAM 0x19c94
28076 #define A_LE_DB_ACT_CNT_IPV6_TCAM 0x19c98
28077 #define A_LE_ACT_CNT_THRSH 0x19c9c
28079 #define S_ACT_CNT_THRSH 0
28080 #define M_ACT_CNT_THRSH 0x1fffffU
28081 #define V_ACT_CNT_THRSH(x) ((x) << S_ACT_CNT_THRSH)
28082 #define G_ACT_CNT_THRSH(x) (((x) >> S_ACT_CNT_THRSH) & M_ACT_CNT_THRSH)
28084 #define A_LE_DB_MASK_IPV6 0x19ca0
28085 #define A_LE_DB_REQ_RSP_CNT 0x19ce4
28087 #define S_RSPCNTLE 16
28088 #define M_RSPCNTLE 0xffffU
28089 #define V_RSPCNTLE(x) ((x) << S_RSPCNTLE)
28090 #define G_RSPCNTLE(x) (((x) >> S_RSPCNTLE) & M_RSPCNTLE)
28092 #define S_REQCNTLE 0
28093 #define M_REQCNTLE 0xffffU
28094 #define V_REQCNTLE(x) ((x) << S_REQCNTLE)
28095 #define G_REQCNTLE(x) (((x) >> S_REQCNTLE) & M_REQCNTLE)
28097 #define A_LE_DB_DBGI_CONFIG 0x19cf0
28099 #define S_DBGICMDPERR 31
28100 #define V_DBGICMDPERR(x) ((x) << S_DBGICMDPERR)
28101 #define F_DBGICMDPERR V_DBGICMDPERR(1U)
28103 #define S_DBGICMDRANGE 22
28104 #define M_DBGICMDRANGE 0x7U
28105 #define V_DBGICMDRANGE(x) ((x) << S_DBGICMDRANGE)
28106 #define G_DBGICMDRANGE(x) (((x) >> S_DBGICMDRANGE) & M_DBGICMDRANGE)
28108 #define S_DBGICMDMSKTYPE 21
28109 #define V_DBGICMDMSKTYPE(x) ((x) << S_DBGICMDMSKTYPE)
28110 #define F_DBGICMDMSKTYPE V_DBGICMDMSKTYPE(1U)
28112 #define S_DBGICMDSEARCH 20
28113 #define V_DBGICMDSEARCH(x) ((x) << S_DBGICMDSEARCH)
28114 #define F_DBGICMDSEARCH V_DBGICMDSEARCH(1U)
28116 #define S_DBGICMDREAD 19
28117 #define V_DBGICMDREAD(x) ((x) << S_DBGICMDREAD)
28118 #define F_DBGICMDREAD V_DBGICMDREAD(1U)
28120 #define S_DBGICMDLEARN 18
28121 #define V_DBGICMDLEARN(x) ((x) << S_DBGICMDLEARN)
28122 #define F_DBGICMDLEARN V_DBGICMDLEARN(1U)
28124 #define S_DBGICMDERASE 17
28125 #define V_DBGICMDERASE(x) ((x) << S_DBGICMDERASE)
28126 #define F_DBGICMDERASE V_DBGICMDERASE(1U)
28128 #define S_DBGICMDIPV6 16
28129 #define V_DBGICMDIPV6(x) ((x) << S_DBGICMDIPV6)
28130 #define F_DBGICMDIPV6 V_DBGICMDIPV6(1U)
28132 #define S_DBGICMDTYPE 13
28133 #define M_DBGICMDTYPE 0x7U
28134 #define V_DBGICMDTYPE(x) ((x) << S_DBGICMDTYPE)
28135 #define G_DBGICMDTYPE(x) (((x) >> S_DBGICMDTYPE) & M_DBGICMDTYPE)
28137 #define S_DBGICMDACKERR 12
28138 #define V_DBGICMDACKERR(x) ((x) << S_DBGICMDACKERR)
28139 #define F_DBGICMDACKERR V_DBGICMDACKERR(1U)
28141 #define S_DBGICMDBUSY 3
28142 #define V_DBGICMDBUSY(x) ((x) << S_DBGICMDBUSY)
28143 #define F_DBGICMDBUSY V_DBGICMDBUSY(1U)
28145 #define S_DBGICMDSTRT 2
28146 #define V_DBGICMDSTRT(x) ((x) << S_DBGICMDSTRT)
28147 #define F_DBGICMDSTRT V_DBGICMDSTRT(1U)
28149 #define S_DBGICMDMODE 0
28150 #define M_DBGICMDMODE 0x3U
28151 #define V_DBGICMDMODE(x) ((x) << S_DBGICMDMODE)
28152 #define G_DBGICMDMODE(x) (((x) >> S_DBGICMDMODE) & M_DBGICMDMODE)
28154 #define A_LE_DB_DBGI_REQ_TCAM_CMD 0x19cf4
28156 #define S_DBGICMD 20
28157 #define M_DBGICMD 0xfU
28158 #define V_DBGICMD(x) ((x) << S_DBGICMD)
28159 #define G_DBGICMD(x) (((x) >> S_DBGICMD) & M_DBGICMD)
28161 #define S_DBGITINDEX 0
28162 #define M_DBGITINDEX 0xfffffU
28163 #define V_DBGITINDEX(x) ((x) << S_DBGITINDEX)
28164 #define G_DBGITINDEX(x) (((x) >> S_DBGITINDEX) & M_DBGITINDEX)
28166 #define A_LE_PERR_ENABLE 0x19cf8
28168 #define S_REQQUEUE 1
28169 #define V_REQQUEUE(x) ((x) << S_REQQUEUE)
28170 #define F_REQQUEUE V_REQQUEUE(1U)
28173 #define V_TCAM(x) ((x) << S_TCAM)
28174 #define F_TCAM V_TCAM(1U)
28176 #define S_MARSPPARERRLE 17
28177 #define V_MARSPPARERRLE(x) ((x) << S_MARSPPARERRLE)
28178 #define F_MARSPPARERRLE V_MARSPPARERRLE(1U)
28180 #define S_REQQUEUELE 16
28181 #define V_REQQUEUELE(x) ((x) << S_REQQUEUELE)
28182 #define F_REQQUEUELE V_REQQUEUELE(1U)
28184 #define S_VFPARERRLE 14
28185 #define V_VFPARERRLE(x) ((x) << S_VFPARERRLE)
28186 #define F_VFPARERRLE V_VFPARERRLE(1U)
28189 #define V_TCAMLE(x) ((x) << S_TCAMLE)
28190 #define F_TCAMLE V_TCAMLE(1U)
28192 #define A_LE_SPARE 0x19cfc
28193 #define A_LE_DB_DBGI_REQ_DATA 0x19d00
28194 #define A_LE_DB_DBGI_REQ_MASK 0x19d50
28195 #define A_LE_DB_DBGI_RSP_STATUS 0x19d94
28197 #define S_DBGIRSPINDEX 12
28198 #define M_DBGIRSPINDEX 0xfffffU
28199 #define V_DBGIRSPINDEX(x) ((x) << S_DBGIRSPINDEX)
28200 #define G_DBGIRSPINDEX(x) (((x) >> S_DBGIRSPINDEX) & M_DBGIRSPINDEX)
28202 #define S_DBGIRSPMSG 8
28203 #define M_DBGIRSPMSG 0xfU
28204 #define V_DBGIRSPMSG(x) ((x) << S_DBGIRSPMSG)
28205 #define G_DBGIRSPMSG(x) (((x) >> S_DBGIRSPMSG) & M_DBGIRSPMSG)
28207 #define S_DBGIRSPMSGVLD 7
28208 #define V_DBGIRSPMSGVLD(x) ((x) << S_DBGIRSPMSGVLD)
28209 #define F_DBGIRSPMSGVLD V_DBGIRSPMSGVLD(1U)
28211 #define S_DBGIRSPMHIT 2
28212 #define V_DBGIRSPMHIT(x) ((x) << S_DBGIRSPMHIT)
28213 #define F_DBGIRSPMHIT V_DBGIRSPMHIT(1U)
28215 #define S_DBGIRSPHIT 1
28216 #define V_DBGIRSPHIT(x) ((x) << S_DBGIRSPHIT)
28217 #define F_DBGIRSPHIT V_DBGIRSPHIT(1U)
28219 #define S_DBGIRSPVALID 0
28220 #define V_DBGIRSPVALID(x) ((x) << S_DBGIRSPVALID)
28221 #define F_DBGIRSPVALID V_DBGIRSPVALID(1U)
28223 #define A_LE_DB_DBGI_RSP_DATA 0x19da0
28224 #define A_LE_DB_DBGI_RSP_LAST_CMD 0x19de4
28226 #define S_LASTCMDB 16
28227 #define M_LASTCMDB 0x7ffU
28228 #define V_LASTCMDB(x) ((x) << S_LASTCMDB)
28229 #define G_LASTCMDB(x) (((x) >> S_LASTCMDB) & M_LASTCMDB)
28231 #define S_LASTCMDA 0
28232 #define M_LASTCMDA 0x7ffU
28233 #define V_LASTCMDA(x) ((x) << S_LASTCMDA)
28234 #define G_LASTCMDA(x) (((x) >> S_LASTCMDA) & M_LASTCMDA)
28236 #define A_LE_DB_DROP_FILTER_ENTRY 0x19de8
28238 #define S_DROPFILTEREN 31
28239 #define V_DROPFILTEREN(x) ((x) << S_DROPFILTEREN)
28240 #define F_DROPFILTEREN V_DROPFILTEREN(1U)
28242 #define S_DROPFILTERCLEAR 17
28243 #define V_DROPFILTERCLEAR(x) ((x) << S_DROPFILTERCLEAR)
28244 #define F_DROPFILTERCLEAR V_DROPFILTERCLEAR(1U)
28246 #define S_DROPFILTERSET 16
28247 #define V_DROPFILTERSET(x) ((x) << S_DROPFILTERSET)
28248 #define F_DROPFILTERSET V_DROPFILTERSET(1U)
28250 #define S_DROPFILTERFIDX 0
28251 #define M_DROPFILTERFIDX 0x1fffU
28252 #define V_DROPFILTERFIDX(x) ((x) << S_DROPFILTERFIDX)
28253 #define G_DROPFILTERFIDX(x) (((x) >> S_DROPFILTERFIDX) & M_DROPFILTERFIDX)
28255 #define A_LE_DB_PTID_SVRBASE 0x19df0
28257 #define S_SVRBASE_ADDR 2
28258 #define M_SVRBASE_ADDR 0x3ffffU
28259 #define V_SVRBASE_ADDR(x) ((x) << S_SVRBASE_ADDR)
28260 #define G_SVRBASE_ADDR(x) (((x) >> S_SVRBASE_ADDR) & M_SVRBASE_ADDR)
28262 #define A_LE_DB_FTID_FLTRBASE 0x19df4
28264 #define S_FLTRBASE_ADDR 2
28265 #define M_FLTRBASE_ADDR 0x3ffffU
28266 #define V_FLTRBASE_ADDR(x) ((x) << S_FLTRBASE_ADDR)
28267 #define G_FLTRBASE_ADDR(x) (((x) >> S_FLTRBASE_ADDR) & M_FLTRBASE_ADDR)
28269 #define A_LE_DB_TID_HASHBASE 0x19df8
28271 #define S_HASHBASE_ADDR 2
28272 #define M_HASHBASE_ADDR 0xfffffU
28273 #define V_HASHBASE_ADDR(x) ((x) << S_HASHBASE_ADDR)
28274 #define G_HASHBASE_ADDR(x) (((x) >> S_HASHBASE_ADDR) & M_HASHBASE_ADDR)
28276 #define A_LE_PERR_INJECT 0x19dfc
28278 #define S_LEMEMSEL 1
28279 #define M_LEMEMSEL 0x7U
28280 #define V_LEMEMSEL(x) ((x) << S_LEMEMSEL)
28281 #define G_LEMEMSEL(x) (((x) >> S_LEMEMSEL) & M_LEMEMSEL)
28283 #define A_LE_DB_ACTIVE_MASK_IPV4 0x19e00
28284 #define A_LE_T5_DB_ACTIVE_MASK_IPV4 0x19e00
28285 #define A_LE_DB_ACTIVE_MASK_IPV6 0x19e50
28286 #define A_LE_HASH_MASK_GEN_IPV4 0x19ea0
28287 #define A_LE_HASH_MASK_GEN_IPV4T5 0x19ea0
28288 #define A_LE_HASH_MASK_GEN_IPV6 0x19eb0
28289 #define A_LE_HASH_MASK_GEN_IPV6T5 0x19eb4
28290 #define A_LE_HASH_MASK_CMP_IPV4 0x19ee0
28291 #define A_LE_HASH_MASK_CMP_IPV4T5 0x19ee4
28292 #define A_LE_HASH_MASK_CMP_IPV6 0x19ef0
28293 #define A_LE_HASH_MASK_CMP_IPV6T5 0x19ef8
28294 #define A_LE_DEBUG_LA_CONFIG 0x19f20
28295 #define A_LE_REQ_DEBUG_LA_DATA 0x19f24
28296 #define A_LE_REQ_DEBUG_LA_WRPTR 0x19f28
28297 #define A_LE_RSP_DEBUG_LA_DATA 0x19f2c
28298 #define A_LE_RSP_DEBUG_LA_WRPTR 0x19f30
28299 #define A_LE_DEBUG_LA_SELECTOR 0x19f34
28300 #define A_LE_SRVR_SRAM_INIT 0x19f34
28302 #define S_SRVRSRAMBASE 2
28303 #define M_SRVRSRAMBASE 0xfffffU
28304 #define V_SRVRSRAMBASE(x) ((x) << S_SRVRSRAMBASE)
28305 #define G_SRVRSRAMBASE(x) (((x) >> S_SRVRSRAMBASE) & M_SRVRSRAMBASE)
28307 #define S_SRVRINITBUSY 1
28308 #define V_SRVRINITBUSY(x) ((x) << S_SRVRINITBUSY)
28309 #define F_SRVRINITBUSY V_SRVRINITBUSY(1U)
28311 #define S_SRVRINIT 0
28312 #define V_SRVRINIT(x) ((x) << S_SRVRINIT)
28313 #define F_SRVRINIT V_SRVRINIT(1U)
28315 #define A_LE_DEBUG_LA_CAPTURED_DATA 0x19f38
28316 #define A_LE_SRVR_VF_SRCH_TABLE 0x19f38
28319 #define V_RDWR(x) ((x) << S_RDWR)
28320 #define F_RDWR V_RDWR(1U)
28322 #define S_VFINDEX 14
28323 #define M_VFINDEX 0x7fU
28324 #define V_VFINDEX(x) ((x) << S_VFINDEX)
28325 #define G_VFINDEX(x) (((x) >> S_VFINDEX) & M_VFINDEX)
28327 #define S_SRCHHADDR 7
28328 #define M_SRCHHADDR 0x7fU
28329 #define V_SRCHHADDR(x) ((x) << S_SRCHHADDR)
28330 #define G_SRCHHADDR(x) (((x) >> S_SRCHHADDR) & M_SRCHHADDR)
28332 #define S_SRCHLADDR 0
28333 #define M_SRCHLADDR 0x7fU
28334 #define V_SRCHLADDR(x) ((x) << S_SRCHLADDR)
28335 #define G_SRCHLADDR(x) (((x) >> S_SRCHLADDR) & M_SRCHLADDR)
28337 #define A_LE_MA_DEBUG_LA_DATA 0x19f3c
28338 #define A_LE_RSP_DEBUG_LA_HASH_WRPTR 0x19f40
28339 #define A_LE_DB_SECOND_ACTIVE_MASK_IPV4 0x19f40
28340 #define A_LE_HASH_DEBUG_LA_DATA 0x19f44
28341 #define A_LE_RSP_DEBUG_LA_TCAM_WRPTR 0x19f48
28342 #define A_LE_TCAM_DEBUG_LA_DATA 0x19f4c
28343 #define A_LE_DB_SECOND_GEN_HASH_MASK_IPV4 0x19f90
28344 #define A_LE_DB_SECOND_CMP_HASH_MASK_IPV4 0x19fa4
28345 #define A_LE_HASH_COLLISION 0x19fc4
28346 #define A_LE_GLOBAL_COLLISION 0x19fc8
28347 #define A_LE_FULL_CNT_COLLISION 0x19fcc
28348 #define A_LE_DEBUG_LA_CONFIGT5 0x19fd0
28349 #define A_LE_REQ_DEBUG_LA_DATAT5 0x19fd4
28350 #define A_LE_REQ_DEBUG_LA_WRPTRT5 0x19fd8
28351 #define A_LE_RSP_DEBUG_LA_DATAT5 0x19fdc
28352 #define A_LE_RSP_DEBUG_LA_WRPTRT5 0x19fe0
28353 #define A_LE_DEBUG_LA_SEL_DATA 0x19fe4
28355 /* registers for module NCSI */
28356 #define NCSI_BASE_ADDR 0x1a000
28358 #define A_NCSI_PORT_CFGREG 0x1a000
28360 #define S_WIREEN 28
28361 #define M_WIREEN 0xfU
28362 #define V_WIREEN(x) ((x) << S_WIREEN)
28363 #define G_WIREEN(x) (((x) >> S_WIREEN) & M_WIREEN)
28365 #define S_STRP_CRC 24
28366 #define M_STRP_CRC 0xfU
28367 #define V_STRP_CRC(x) ((x) << S_STRP_CRC)
28368 #define G_STRP_CRC(x) (((x) >> S_STRP_CRC) & M_STRP_CRC)
28370 #define S_RX_HALT 22
28371 #define V_RX_HALT(x) ((x) << S_RX_HALT)
28372 #define F_RX_HALT V_RX_HALT(1U)
28374 #define S_FLUSH_RX_FIFO 21
28375 #define V_FLUSH_RX_FIFO(x) ((x) << S_FLUSH_RX_FIFO)
28376 #define F_FLUSH_RX_FIFO V_FLUSH_RX_FIFO(1U)
28378 #define S_HW_ARB_EN 20
28379 #define V_HW_ARB_EN(x) ((x) << S_HW_ARB_EN)
28380 #define F_HW_ARB_EN V_HW_ARB_EN(1U)
28382 #define S_SOFT_PKG_SEL 19
28383 #define V_SOFT_PKG_SEL(x) ((x) << S_SOFT_PKG_SEL)
28384 #define F_SOFT_PKG_SEL V_SOFT_PKG_SEL(1U)
28386 #define S_ERR_DISCARD_EN 18
28387 #define V_ERR_DISCARD_EN(x) ((x) << S_ERR_DISCARD_EN)
28388 #define F_ERR_DISCARD_EN V_ERR_DISCARD_EN(1U)
28390 #define S_MAX_PKT_SIZE 4
28391 #define M_MAX_PKT_SIZE 0x3fffU
28392 #define V_MAX_PKT_SIZE(x) ((x) << S_MAX_PKT_SIZE)
28393 #define G_MAX_PKT_SIZE(x) (((x) >> S_MAX_PKT_SIZE) & M_MAX_PKT_SIZE)
28395 #define S_RX_BYTE_SWAP 3
28396 #define V_RX_BYTE_SWAP(x) ((x) << S_RX_BYTE_SWAP)
28397 #define F_RX_BYTE_SWAP V_RX_BYTE_SWAP(1U)
28399 #define S_TX_BYTE_SWAP 2
28400 #define V_TX_BYTE_SWAP(x) ((x) << S_TX_BYTE_SWAP)
28401 #define F_TX_BYTE_SWAP V_TX_BYTE_SWAP(1U)
28403 #define A_NCSI_RST_CTRL 0x1a004
28405 #define S_MAC_REF_RST 2
28406 #define V_MAC_REF_RST(x) ((x) << S_MAC_REF_RST)
28407 #define F_MAC_REF_RST V_MAC_REF_RST(1U)
28409 #define S_MAC_RX_RST 1
28410 #define V_MAC_RX_RST(x) ((x) << S_MAC_RX_RST)
28411 #define F_MAC_RX_RST V_MAC_RX_RST(1U)
28413 #define S_MAC_TX_RST 0
28414 #define V_MAC_TX_RST(x) ((x) << S_MAC_TX_RST)
28415 #define F_MAC_TX_RST V_MAC_TX_RST(1U)
28417 #define A_NCSI_CH0_SADDR_LOW 0x1a010
28418 #define A_NCSI_CH0_SADDR_HIGH 0x1a014
28420 #define S_CHO_SADDR_EN 31
28421 #define V_CHO_SADDR_EN(x) ((x) << S_CHO_SADDR_EN)
28422 #define F_CHO_SADDR_EN V_CHO_SADDR_EN(1U)
28424 #define S_CH0_SADDR_HIGH 0
28425 #define M_CH0_SADDR_HIGH 0xffffU
28426 #define V_CH0_SADDR_HIGH(x) ((x) << S_CH0_SADDR_HIGH)
28427 #define G_CH0_SADDR_HIGH(x) (((x) >> S_CH0_SADDR_HIGH) & M_CH0_SADDR_HIGH)
28429 #define A_NCSI_CH1_SADDR_LOW 0x1a018
28430 #define A_NCSI_CH1_SADDR_HIGH 0x1a01c
28432 #define S_CH1_SADDR_EN 31
28433 #define V_CH1_SADDR_EN(x) ((x) << S_CH1_SADDR_EN)
28434 #define F_CH1_SADDR_EN V_CH1_SADDR_EN(1U)
28436 #define S_CH1_SADDR_HIGH 0
28437 #define M_CH1_SADDR_HIGH 0xffffU
28438 #define V_CH1_SADDR_HIGH(x) ((x) << S_CH1_SADDR_HIGH)
28439 #define G_CH1_SADDR_HIGH(x) (((x) >> S_CH1_SADDR_HIGH) & M_CH1_SADDR_HIGH)
28441 #define A_NCSI_CH2_SADDR_LOW 0x1a020
28442 #define A_NCSI_CH2_SADDR_HIGH 0x1a024
28444 #define S_CH2_SADDR_EN 31
28445 #define V_CH2_SADDR_EN(x) ((x) << S_CH2_SADDR_EN)
28446 #define F_CH2_SADDR_EN V_CH2_SADDR_EN(1U)
28448 #define S_CH2_SADDR_HIGH 0
28449 #define M_CH2_SADDR_HIGH 0xffffU
28450 #define V_CH2_SADDR_HIGH(x) ((x) << S_CH2_SADDR_HIGH)
28451 #define G_CH2_SADDR_HIGH(x) (((x) >> S_CH2_SADDR_HIGH) & M_CH2_SADDR_HIGH)
28453 #define A_NCSI_CH3_SADDR_LOW 0x1a028
28454 #define A_NCSI_CH3_SADDR_HIGH 0x1a02c
28456 #define S_CH3_SADDR_EN 31
28457 #define V_CH3_SADDR_EN(x) ((x) << S_CH3_SADDR_EN)
28458 #define F_CH3_SADDR_EN V_CH3_SADDR_EN(1U)
28460 #define S_CH3_SADDR_HIGH 0
28461 #define M_CH3_SADDR_HIGH 0xffffU
28462 #define V_CH3_SADDR_HIGH(x) ((x) << S_CH3_SADDR_HIGH)
28463 #define G_CH3_SADDR_HIGH(x) (((x) >> S_CH3_SADDR_HIGH) & M_CH3_SADDR_HIGH)
28465 #define A_NCSI_WORK_REQHDR_0 0x1a030
28466 #define A_NCSI_WORK_REQHDR_1 0x1a034
28467 #define A_NCSI_WORK_REQHDR_2 0x1a038
28468 #define A_NCSI_WORK_REQHDR_3 0x1a03c
28469 #define A_NCSI_MPS_HDR_LO 0x1a040
28470 #define A_NCSI_MPS_HDR_HI 0x1a044
28471 #define A_NCSI_CTL 0x1a048
28473 #define S_STRIP_OVLAN 3
28474 #define V_STRIP_OVLAN(x) ((x) << S_STRIP_OVLAN)
28475 #define F_STRIP_OVLAN V_STRIP_OVLAN(1U)
28477 #define S_BMC_DROP_NON_BC 2
28478 #define V_BMC_DROP_NON_BC(x) ((x) << S_BMC_DROP_NON_BC)
28479 #define F_BMC_DROP_NON_BC V_BMC_DROP_NON_BC(1U)
28481 #define S_BMC_RX_FWD_ALL 1
28482 #define V_BMC_RX_FWD_ALL(x) ((x) << S_BMC_RX_FWD_ALL)
28483 #define F_BMC_RX_FWD_ALL V_BMC_RX_FWD_ALL(1U)
28485 #define S_FWD_BMC 0
28486 #define V_FWD_BMC(x) ((x) << S_FWD_BMC)
28487 #define F_FWD_BMC V_FWD_BMC(1U)
28489 #define A_NCSI_NCSI_ETYPE 0x1a04c
28491 #define S_NCSI_ETHERTYPE 0
28492 #define M_NCSI_ETHERTYPE 0xffffU
28493 #define V_NCSI_ETHERTYPE(x) ((x) << S_NCSI_ETHERTYPE)
28494 #define G_NCSI_ETHERTYPE(x) (((x) >> S_NCSI_ETHERTYPE) & M_NCSI_ETHERTYPE)
28496 #define A_NCSI_RX_FIFO_CNT 0x1a050
28498 #define S_NCSI_RXFIFO_CNT 0
28499 #define M_NCSI_RXFIFO_CNT 0x7ffU
28500 #define V_NCSI_RXFIFO_CNT(x) ((x) << S_NCSI_RXFIFO_CNT)
28501 #define G_NCSI_RXFIFO_CNT(x) (((x) >> S_NCSI_RXFIFO_CNT) & M_NCSI_RXFIFO_CNT)
28503 #define A_NCSI_RX_ERR_CNT 0x1a054
28504 #define A_NCSI_RX_OF_CNT 0x1a058
28505 #define A_NCSI_RX_MS_CNT 0x1a05c
28506 #define A_NCSI_RX_IE_CNT 0x1a060
28507 #define A_NCSI_MPS_DEMUX_CNT 0x1a064
28509 #define S_MPS2CIM_CNT 16
28510 #define M_MPS2CIM_CNT 0x1ffU
28511 #define V_MPS2CIM_CNT(x) ((x) << S_MPS2CIM_CNT)
28512 #define G_MPS2CIM_CNT(x) (((x) >> S_MPS2CIM_CNT) & M_MPS2CIM_CNT)
28514 #define S_MPS2BMC_CNT 0
28515 #define M_MPS2BMC_CNT 0x1ffU
28516 #define V_MPS2BMC_CNT(x) ((x) << S_MPS2BMC_CNT)
28517 #define G_MPS2BMC_CNT(x) (((x) >> S_MPS2BMC_CNT) & M_MPS2BMC_CNT)
28519 #define A_NCSI_CIM_DEMUX_CNT 0x1a068
28521 #define S_CIM2MPS_CNT 16
28522 #define M_CIM2MPS_CNT 0x1ffU
28523 #define V_CIM2MPS_CNT(x) ((x) << S_CIM2MPS_CNT)
28524 #define G_CIM2MPS_CNT(x) (((x) >> S_CIM2MPS_CNT) & M_CIM2MPS_CNT)
28526 #define S_CIM2BMC_CNT 0
28527 #define M_CIM2BMC_CNT 0x1ffU
28528 #define V_CIM2BMC_CNT(x) ((x) << S_CIM2BMC_CNT)
28529 #define G_CIM2BMC_CNT(x) (((x) >> S_CIM2BMC_CNT) & M_CIM2BMC_CNT)
28531 #define A_NCSI_TX_FIFO_CNT 0x1a06c
28533 #define S_TX_FIFO_CNT 0
28534 #define M_TX_FIFO_CNT 0x3ffU
28535 #define V_TX_FIFO_CNT(x) ((x) << S_TX_FIFO_CNT)
28536 #define G_TX_FIFO_CNT(x) (((x) >> S_TX_FIFO_CNT) & M_TX_FIFO_CNT)
28538 #define A_NCSI_SE_CNT_CTL 0x1a0b0
28540 #define S_SE_CNT_CLR 0
28541 #define M_SE_CNT_CLR 0xfU
28542 #define V_SE_CNT_CLR(x) ((x) << S_SE_CNT_CLR)
28543 #define G_SE_CNT_CLR(x) (((x) >> S_SE_CNT_CLR) & M_SE_CNT_CLR)
28545 #define A_NCSI_SE_CNT_MPS 0x1a0b4
28547 #define S_NC2MPS_SOP_CNT 24
28548 #define M_NC2MPS_SOP_CNT 0xffU
28549 #define V_NC2MPS_SOP_CNT(x) ((x) << S_NC2MPS_SOP_CNT)
28550 #define G_NC2MPS_SOP_CNT(x) (((x) >> S_NC2MPS_SOP_CNT) & M_NC2MPS_SOP_CNT)
28552 #define S_NC2MPS_EOP_CNT 16
28553 #define M_NC2MPS_EOP_CNT 0x3fU
28554 #define V_NC2MPS_EOP_CNT(x) ((x) << S_NC2MPS_EOP_CNT)
28555 #define G_NC2MPS_EOP_CNT(x) (((x) >> S_NC2MPS_EOP_CNT) & M_NC2MPS_EOP_CNT)
28557 #define S_MPS2NC_SOP_CNT 8
28558 #define M_MPS2NC_SOP_CNT 0xffU
28559 #define V_MPS2NC_SOP_CNT(x) ((x) << S_MPS2NC_SOP_CNT)
28560 #define G_MPS2NC_SOP_CNT(x) (((x) >> S_MPS2NC_SOP_CNT) & M_MPS2NC_SOP_CNT)
28562 #define S_MPS2NC_EOP_CNT 0
28563 #define M_MPS2NC_EOP_CNT 0xffU
28564 #define V_MPS2NC_EOP_CNT(x) ((x) << S_MPS2NC_EOP_CNT)
28565 #define G_MPS2NC_EOP_CNT(x) (((x) >> S_MPS2NC_EOP_CNT) & M_MPS2NC_EOP_CNT)
28567 #define A_NCSI_SE_CNT_CIM 0x1a0b8
28569 #define S_NC2CIM_SOP_CNT 24
28570 #define M_NC2CIM_SOP_CNT 0xffU
28571 #define V_NC2CIM_SOP_CNT(x) ((x) << S_NC2CIM_SOP_CNT)
28572 #define G_NC2CIM_SOP_CNT(x) (((x) >> S_NC2CIM_SOP_CNT) & M_NC2CIM_SOP_CNT)
28574 #define S_NC2CIM_EOP_CNT 16
28575 #define M_NC2CIM_EOP_CNT 0x3fU
28576 #define V_NC2CIM_EOP_CNT(x) ((x) << S_NC2CIM_EOP_CNT)
28577 #define G_NC2CIM_EOP_CNT(x) (((x) >> S_NC2CIM_EOP_CNT) & M_NC2CIM_EOP_CNT)
28579 #define S_CIM2NC_SOP_CNT 8
28580 #define M_CIM2NC_SOP_CNT 0xffU
28581 #define V_CIM2NC_SOP_CNT(x) ((x) << S_CIM2NC_SOP_CNT)
28582 #define G_CIM2NC_SOP_CNT(x) (((x) >> S_CIM2NC_SOP_CNT) & M_CIM2NC_SOP_CNT)
28584 #define S_CIM2NC_EOP_CNT 0
28585 #define M_CIM2NC_EOP_CNT 0xffU
28586 #define V_CIM2NC_EOP_CNT(x) ((x) << S_CIM2NC_EOP_CNT)
28587 #define G_CIM2NC_EOP_CNT(x) (((x) >> S_CIM2NC_EOP_CNT) & M_CIM2NC_EOP_CNT)
28589 #define A_NCSI_BUS_DEBUG 0x1a0bc
28591 #define S_SOP_CNT_ERR 12
28592 #define M_SOP_CNT_ERR 0xfU
28593 #define V_SOP_CNT_ERR(x) ((x) << S_SOP_CNT_ERR)
28594 #define G_SOP_CNT_ERR(x) (((x) >> S_SOP_CNT_ERR) & M_SOP_CNT_ERR)
28596 #define S_BUS_STATE_MPS_OUT 6
28597 #define M_BUS_STATE_MPS_OUT 0x3U
28598 #define V_BUS_STATE_MPS_OUT(x) ((x) << S_BUS_STATE_MPS_OUT)
28599 #define G_BUS_STATE_MPS_OUT(x) (((x) >> S_BUS_STATE_MPS_OUT) & M_BUS_STATE_MPS_OUT)
28601 #define S_BUS_STATE_MPS_IN 4
28602 #define M_BUS_STATE_MPS_IN 0x3U
28603 #define V_BUS_STATE_MPS_IN(x) ((x) << S_BUS_STATE_MPS_IN)
28604 #define G_BUS_STATE_MPS_IN(x) (((x) >> S_BUS_STATE_MPS_IN) & M_BUS_STATE_MPS_IN)
28606 #define S_BUS_STATE_CIM_OUT 2
28607 #define M_BUS_STATE_CIM_OUT 0x3U
28608 #define V_BUS_STATE_CIM_OUT(x) ((x) << S_BUS_STATE_CIM_OUT)
28609 #define G_BUS_STATE_CIM_OUT(x) (((x) >> S_BUS_STATE_CIM_OUT) & M_BUS_STATE_CIM_OUT)
28611 #define S_BUS_STATE_CIM_IN 0
28612 #define M_BUS_STATE_CIM_IN 0x3U
28613 #define V_BUS_STATE_CIM_IN(x) ((x) << S_BUS_STATE_CIM_IN)
28614 #define G_BUS_STATE_CIM_IN(x) (((x) >> S_BUS_STATE_CIM_IN) & M_BUS_STATE_CIM_IN)
28616 #define A_NCSI_LA_RDPTR 0x1a0c0
28617 #define A_NCSI_LA_RDDATA 0x1a0c4
28618 #define A_NCSI_LA_WRPTR 0x1a0c8
28619 #define A_NCSI_LA_RESERVED 0x1a0cc
28620 #define A_NCSI_LA_CTL 0x1a0d0
28621 #define A_NCSI_INT_ENABLE 0x1a0d4
28623 #define S_CIM_DM_PRTY_ERR 8
28624 #define V_CIM_DM_PRTY_ERR(x) ((x) << S_CIM_DM_PRTY_ERR)
28625 #define F_CIM_DM_PRTY_ERR V_CIM_DM_PRTY_ERR(1U)
28627 #define S_MPS_DM_PRTY_ERR 7
28628 #define V_MPS_DM_PRTY_ERR(x) ((x) << S_MPS_DM_PRTY_ERR)
28629 #define F_MPS_DM_PRTY_ERR V_MPS_DM_PRTY_ERR(1U)
28632 #define V_TOKEN(x) ((x) << S_TOKEN)
28633 #define F_TOKEN V_TOKEN(1U)
28635 #define S_ARB_DONE 5
28636 #define V_ARB_DONE(x) ((x) << S_ARB_DONE)
28637 #define F_ARB_DONE V_ARB_DONE(1U)
28639 #define S_ARB_STARTED 4
28640 #define V_ARB_STARTED(x) ((x) << S_ARB_STARTED)
28641 #define F_ARB_STARTED V_ARB_STARTED(1U)
28644 #define V_WOL(x) ((x) << S_WOL)
28645 #define F_WOL V_WOL(1U)
28648 #define V_MACINT(x) ((x) << S_MACINT)
28649 #define F_MACINT V_MACINT(1U)
28651 #define S_TXFIFO_PRTY_ERR 1
28652 #define V_TXFIFO_PRTY_ERR(x) ((x) << S_TXFIFO_PRTY_ERR)
28653 #define F_TXFIFO_PRTY_ERR V_TXFIFO_PRTY_ERR(1U)
28655 #define S_RXFIFO_PRTY_ERR 0
28656 #define V_RXFIFO_PRTY_ERR(x) ((x) << S_RXFIFO_PRTY_ERR)
28657 #define F_RXFIFO_PRTY_ERR V_RXFIFO_PRTY_ERR(1U)
28659 #define A_NCSI_INT_CAUSE 0x1a0d8
28660 #define A_NCSI_STATUS 0x1a0dc
28663 #define V_MASTER(x) ((x) << S_MASTER)
28664 #define F_MASTER V_MASTER(1U)
28666 #define S_ARB_STATUS 0
28667 #define V_ARB_STATUS(x) ((x) << S_ARB_STATUS)
28668 #define F_ARB_STATUS V_ARB_STATUS(1U)
28670 #define A_NCSI_PAUSE_CTRL 0x1a0e0
28672 #define S_FORCEPAUSE 0
28673 #define V_FORCEPAUSE(x) ((x) << S_FORCEPAUSE)
28674 #define F_FORCEPAUSE V_FORCEPAUSE(1U)
28676 #define A_NCSI_PAUSE_TIMEOUT 0x1a0e4
28677 #define A_NCSI_PAUSE_WM 0x1a0ec
28679 #define S_PAUSEHWM 16
28680 #define M_PAUSEHWM 0x7ffU
28681 #define V_PAUSEHWM(x) ((x) << S_PAUSEHWM)
28682 #define G_PAUSEHWM(x) (((x) >> S_PAUSEHWM) & M_PAUSEHWM)
28684 #define S_PAUSELWM 0
28685 #define M_PAUSELWM 0x7ffU
28686 #define V_PAUSELWM(x) ((x) << S_PAUSELWM)
28687 #define G_PAUSELWM(x) (((x) >> S_PAUSELWM) & M_PAUSELWM)
28689 #define A_NCSI_DEBUG 0x1a0f0
28691 #define S_DEBUGSEL 0
28692 #define M_DEBUGSEL 0x3fU
28693 #define V_DEBUGSEL(x) ((x) << S_DEBUGSEL)
28694 #define G_DEBUGSEL(x) (((x) >> S_DEBUGSEL) & M_DEBUGSEL)
28696 #define S_TXFIFO_EMPTY 4
28697 #define V_TXFIFO_EMPTY(x) ((x) << S_TXFIFO_EMPTY)
28698 #define F_TXFIFO_EMPTY V_TXFIFO_EMPTY(1U)
28700 #define S_TXFIFO_FULL 3
28701 #define V_TXFIFO_FULL(x) ((x) << S_TXFIFO_FULL)
28702 #define F_TXFIFO_FULL V_TXFIFO_FULL(1U)
28705 #define M_PKG_ID 0x7U
28706 #define V_PKG_ID(x) ((x) << S_PKG_ID)
28707 #define G_PKG_ID(x) (((x) >> S_PKG_ID) & M_PKG_ID)
28709 #define A_NCSI_PERR_INJECT 0x1a0f4
28711 #define S_MCSIMELSEL 1
28712 #define V_MCSIMELSEL(x) ((x) << S_MCSIMELSEL)
28713 #define F_MCSIMELSEL V_MCSIMELSEL(1U)
28715 #define A_NCSI_PERR_ENABLE 0x1a0f8
28716 #define A_NCSI_MACB_NETWORK_CTRL 0x1a100
28718 #define S_TXSNDZEROPAUSE 12
28719 #define V_TXSNDZEROPAUSE(x) ((x) << S_TXSNDZEROPAUSE)
28720 #define F_TXSNDZEROPAUSE V_TXSNDZEROPAUSE(1U)
28722 #define S_TXSNDPAUSE 11
28723 #define V_TXSNDPAUSE(x) ((x) << S_TXSNDPAUSE)
28724 #define F_TXSNDPAUSE V_TXSNDPAUSE(1U)
28726 #define S_TXSTOP 10
28727 #define V_TXSTOP(x) ((x) << S_TXSTOP)
28728 #define F_TXSTOP V_TXSTOP(1U)
28730 #define S_TXSTART 9
28731 #define V_TXSTART(x) ((x) << S_TXSTART)
28732 #define F_TXSTART V_TXSTART(1U)
28734 #define S_BACKPRESS 8
28735 #define V_BACKPRESS(x) ((x) << S_BACKPRESS)
28736 #define F_BACKPRESS V_BACKPRESS(1U)
28738 #define S_STATWREN 7
28739 #define V_STATWREN(x) ((x) << S_STATWREN)
28740 #define F_STATWREN V_STATWREN(1U)
28742 #define S_INCRSTAT 6
28743 #define V_INCRSTAT(x) ((x) << S_INCRSTAT)
28744 #define F_INCRSTAT V_INCRSTAT(1U)
28746 #define S_CLEARSTAT 5
28747 #define V_CLEARSTAT(x) ((x) << S_CLEARSTAT)
28748 #define F_CLEARSTAT V_CLEARSTAT(1U)
28750 #define S_ENMGMTPORT 4
28751 #define V_ENMGMTPORT(x) ((x) << S_ENMGMTPORT)
28752 #define F_ENMGMTPORT V_ENMGMTPORT(1U)
28754 #define S_NCSITXEN 3
28755 #define V_NCSITXEN(x) ((x) << S_NCSITXEN)
28756 #define F_NCSITXEN V_NCSITXEN(1U)
28758 #define S_NCSIRXEN 2
28759 #define V_NCSIRXEN(x) ((x) << S_NCSIRXEN)
28760 #define F_NCSIRXEN V_NCSIRXEN(1U)
28762 #define S_LOOPLOCAL 1
28763 #define V_LOOPLOCAL(x) ((x) << S_LOOPLOCAL)
28764 #define F_LOOPLOCAL V_LOOPLOCAL(1U)
28766 #define S_LOOPPHY 0
28767 #define V_LOOPPHY(x) ((x) << S_LOOPPHY)
28768 #define F_LOOPPHY V_LOOPPHY(1U)
28770 #define A_NCSI_MACB_NETWORK_CFG 0x1a104
28772 #define S_PCLKDIV128 22
28773 #define V_PCLKDIV128(x) ((x) << S_PCLKDIV128)
28774 #define F_PCLKDIV128 V_PCLKDIV128(1U)
28776 #define S_COPYPAUSE 21
28777 #define V_COPYPAUSE(x) ((x) << S_COPYPAUSE)
28778 #define F_COPYPAUSE V_COPYPAUSE(1U)
28780 #define S_NONSTDPREOK 20
28781 #define V_NONSTDPREOK(x) ((x) << S_NONSTDPREOK)
28782 #define F_NONSTDPREOK V_NONSTDPREOK(1U)
28785 #define V_NOFCS(x) ((x) << S_NOFCS)
28786 #define F_NOFCS V_NOFCS(1U)
28788 #define S_RXENHALFDUP 18
28789 #define V_RXENHALFDUP(x) ((x) << S_RXENHALFDUP)
28790 #define F_RXENHALFDUP V_RXENHALFDUP(1U)
28792 #define S_NOCOPYFCS 17
28793 #define V_NOCOPYFCS(x) ((x) << S_NOCOPYFCS)
28794 #define F_NOCOPYFCS V_NOCOPYFCS(1U)
28796 #define S_LENCHKEN 16
28797 #define V_LENCHKEN(x) ((x) << S_LENCHKEN)
28798 #define F_LENCHKEN V_LENCHKEN(1U)
28800 #define S_RXBUFOFFSET 14
28801 #define M_RXBUFOFFSET 0x3U
28802 #define V_RXBUFOFFSET(x) ((x) << S_RXBUFOFFSET)
28803 #define G_RXBUFOFFSET(x) (((x) >> S_RXBUFOFFSET) & M_RXBUFOFFSET)
28805 #define S_PAUSEEN 13
28806 #define V_PAUSEEN(x) ((x) << S_PAUSEEN)
28807 #define F_PAUSEEN V_PAUSEEN(1U)
28809 #define S_RETRYTEST 12
28810 #define V_RETRYTEST(x) ((x) << S_RETRYTEST)
28811 #define F_RETRYTEST V_RETRYTEST(1U)
28813 #define S_PCLKDIV 10
28814 #define M_PCLKDIV 0x3U
28815 #define V_PCLKDIV(x) ((x) << S_PCLKDIV)
28816 #define G_PCLKDIV(x) (((x) >> S_PCLKDIV) & M_PCLKDIV)
28818 #define S_EXTCLASS 9
28819 #define V_EXTCLASS(x) ((x) << S_EXTCLASS)
28820 #define F_EXTCLASS V_EXTCLASS(1U)
28822 #define S_EN1536FRAME 8
28823 #define V_EN1536FRAME(x) ((x) << S_EN1536FRAME)
28824 #define F_EN1536FRAME V_EN1536FRAME(1U)
28826 #define S_UCASTHASHEN 7
28827 #define V_UCASTHASHEN(x) ((x) << S_UCASTHASHEN)
28828 #define F_UCASTHASHEN V_UCASTHASHEN(1U)
28830 #define S_MCASTHASHEN 6
28831 #define V_MCASTHASHEN(x) ((x) << S_MCASTHASHEN)
28832 #define F_MCASTHASHEN V_MCASTHASHEN(1U)
28834 #define S_RXBCASTDIS 5
28835 #define V_RXBCASTDIS(x) ((x) << S_RXBCASTDIS)
28836 #define F_RXBCASTDIS V_RXBCASTDIS(1U)
28838 #define S_NCSICOPYALLFRAMES 4
28839 #define V_NCSICOPYALLFRAMES(x) ((x) << S_NCSICOPYALLFRAMES)
28840 #define F_NCSICOPYALLFRAMES V_NCSICOPYALLFRAMES(1U)
28842 #define S_JUMBOEN 3
28843 #define V_JUMBOEN(x) ((x) << S_JUMBOEN)
28844 #define F_JUMBOEN V_JUMBOEN(1U)
28847 #define V_SEREN(x) ((x) << S_SEREN)
28848 #define F_SEREN V_SEREN(1U)
28850 #define S_FULLDUPLEX 1
28851 #define V_FULLDUPLEX(x) ((x) << S_FULLDUPLEX)
28852 #define F_FULLDUPLEX V_FULLDUPLEX(1U)
28855 #define V_SPEED(x) ((x) << S_SPEED)
28856 #define F_SPEED V_SPEED(1U)
28858 #define A_NCSI_MACB_NETWORK_STATUS 0x1a108
28860 #define S_PHYMGMTSTATUS 2
28861 #define V_PHYMGMTSTATUS(x) ((x) << S_PHYMGMTSTATUS)
28862 #define F_PHYMGMTSTATUS V_PHYMGMTSTATUS(1U)
28864 #define S_MDISTATUS 1
28865 #define V_MDISTATUS(x) ((x) << S_MDISTATUS)
28866 #define F_MDISTATUS V_MDISTATUS(1U)
28868 #define S_LINKSTATUS 0
28869 #define V_LINKSTATUS(x) ((x) << S_LINKSTATUS)
28870 #define F_LINKSTATUS V_LINKSTATUS(1U)
28872 #define A_NCSI_MACB_TX_STATUS 0x1a114
28874 #define S_UNDERRUNERR 6
28875 #define V_UNDERRUNERR(x) ((x) << S_UNDERRUNERR)
28876 #define F_UNDERRUNERR V_UNDERRUNERR(1U)
28878 #define S_TXCOMPLETE 5
28879 #define V_TXCOMPLETE(x) ((x) << S_TXCOMPLETE)
28880 #define F_TXCOMPLETE V_TXCOMPLETE(1U)
28882 #define S_BUFFEREXHAUSTED 4
28883 #define V_BUFFEREXHAUSTED(x) ((x) << S_BUFFEREXHAUSTED)
28884 #define F_BUFFEREXHAUSTED V_BUFFEREXHAUSTED(1U)
28886 #define S_TXPROGRESS 3
28887 #define V_TXPROGRESS(x) ((x) << S_TXPROGRESS)
28888 #define F_TXPROGRESS V_TXPROGRESS(1U)
28890 #define S_RETRYLIMIT 2
28891 #define V_RETRYLIMIT(x) ((x) << S_RETRYLIMIT)
28892 #define F_RETRYLIMIT V_RETRYLIMIT(1U)
28894 #define S_COLEVENT 1
28895 #define V_COLEVENT(x) ((x) << S_COLEVENT)
28896 #define F_COLEVENT V_COLEVENT(1U)
28898 #define S_USEDBITREAD 0
28899 #define V_USEDBITREAD(x) ((x) << S_USEDBITREAD)
28900 #define F_USEDBITREAD V_USEDBITREAD(1U)
28902 #define A_NCSI_MACB_RX_BUF_QPTR 0x1a118
28904 #define S_RXBUFQPTR 2
28905 #define M_RXBUFQPTR 0x3fffffffU
28906 #define V_RXBUFQPTR(x) ((x) << S_RXBUFQPTR)
28907 #define G_RXBUFQPTR(x) (((x) >> S_RXBUFQPTR) & M_RXBUFQPTR)
28909 #define A_NCSI_MACB_TX_BUF_QPTR 0x1a11c
28911 #define S_TXBUFQPTR 2
28912 #define M_TXBUFQPTR 0x3fffffffU
28913 #define V_TXBUFQPTR(x) ((x) << S_TXBUFQPTR)
28914 #define G_TXBUFQPTR(x) (((x) >> S_TXBUFQPTR) & M_TXBUFQPTR)
28916 #define A_NCSI_MACB_RX_STATUS 0x1a120
28918 #define S_RXOVERRUNERR 2
28919 #define V_RXOVERRUNERR(x) ((x) << S_RXOVERRUNERR)
28920 #define F_RXOVERRUNERR V_RXOVERRUNERR(1U)
28922 #define S_MACB_FRAMERCVD 1
28923 #define V_MACB_FRAMERCVD(x) ((x) << S_MACB_FRAMERCVD)
28924 #define F_MACB_FRAMERCVD V_MACB_FRAMERCVD(1U)
28926 #define S_NORXBUF 0
28927 #define V_NORXBUF(x) ((x) << S_NORXBUF)
28928 #define F_NORXBUF V_NORXBUF(1U)
28930 #define A_NCSI_MACB_INT_STATUS 0x1a124
28932 #define S_PAUSETIMEZERO 13
28933 #define V_PAUSETIMEZERO(x) ((x) << S_PAUSETIMEZERO)
28934 #define F_PAUSETIMEZERO V_PAUSETIMEZERO(1U)
28936 #define S_PAUSERCVD 12
28937 #define V_PAUSERCVD(x) ((x) << S_PAUSERCVD)
28938 #define F_PAUSERCVD V_PAUSERCVD(1U)
28940 #define S_HRESPNOTOK 11
28941 #define V_HRESPNOTOK(x) ((x) << S_HRESPNOTOK)
28942 #define F_HRESPNOTOK V_HRESPNOTOK(1U)
28944 #define S_RXOVERRUN 10
28945 #define V_RXOVERRUN(x) ((x) << S_RXOVERRUN)
28946 #define F_RXOVERRUN V_RXOVERRUN(1U)
28948 #define S_LINKCHANGE 9
28949 #define V_LINKCHANGE(x) ((x) << S_LINKCHANGE)
28950 #define F_LINKCHANGE V_LINKCHANGE(1U)
28952 #define S_INT_TXCOMPLETE 7
28953 #define V_INT_TXCOMPLETE(x) ((x) << S_INT_TXCOMPLETE)
28954 #define F_INT_TXCOMPLETE V_INT_TXCOMPLETE(1U)
28956 #define S_TXBUFERR 6
28957 #define V_TXBUFERR(x) ((x) << S_TXBUFERR)
28958 #define F_TXBUFERR V_TXBUFERR(1U)
28960 #define S_RETRYLIMITERR 5
28961 #define V_RETRYLIMITERR(x) ((x) << S_RETRYLIMITERR)
28962 #define F_RETRYLIMITERR V_RETRYLIMITERR(1U)
28964 #define S_TXBUFUNDERRUN 4
28965 #define V_TXBUFUNDERRUN(x) ((x) << S_TXBUFUNDERRUN)
28966 #define F_TXBUFUNDERRUN V_TXBUFUNDERRUN(1U)
28968 #define S_TXUSEDBITREAD 3
28969 #define V_TXUSEDBITREAD(x) ((x) << S_TXUSEDBITREAD)
28970 #define F_TXUSEDBITREAD V_TXUSEDBITREAD(1U)
28972 #define S_RXUSEDBITREAD 2
28973 #define V_RXUSEDBITREAD(x) ((x) << S_RXUSEDBITREAD)
28974 #define F_RXUSEDBITREAD V_RXUSEDBITREAD(1U)
28976 #define S_RXCOMPLETE 1
28977 #define V_RXCOMPLETE(x) ((x) << S_RXCOMPLETE)
28978 #define F_RXCOMPLETE V_RXCOMPLETE(1U)
28980 #define S_MGMTFRAMESENT 0
28981 #define V_MGMTFRAMESENT(x) ((x) << S_MGMTFRAMESENT)
28982 #define F_MGMTFRAMESENT V_MGMTFRAMESENT(1U)
28984 #define A_NCSI_MACB_INT_EN 0x1a128
28985 #define A_NCSI_MACB_INT_DIS 0x1a12c
28986 #define A_NCSI_MACB_INT_MASK 0x1a130
28987 #define A_NCSI_MACB_PAUSE_TIME 0x1a138
28989 #define S_PAUSETIME 0
28990 #define M_PAUSETIME 0xffffU
28991 #define V_PAUSETIME(x) ((x) << S_PAUSETIME)
28992 #define G_PAUSETIME(x) (((x) >> S_PAUSETIME) & M_PAUSETIME)
28994 #define A_NCSI_MACB_PAUSE_FRAMES_RCVD 0x1a13c
28996 #define S_PAUSEFRRCVD 0
28997 #define M_PAUSEFRRCVD 0xffffU
28998 #define V_PAUSEFRRCVD(x) ((x) << S_PAUSEFRRCVD)
28999 #define G_PAUSEFRRCVD(x) (((x) >> S_PAUSEFRRCVD) & M_PAUSEFRRCVD)
29001 #define A_NCSI_MACB_TX_FRAMES_OK 0x1a140
29003 #define S_TXFRAMESOK 0
29004 #define M_TXFRAMESOK 0xffffffU
29005 #define V_TXFRAMESOK(x) ((x) << S_TXFRAMESOK)
29006 #define G_TXFRAMESOK(x) (((x) >> S_TXFRAMESOK) & M_TXFRAMESOK)
29008 #define A_NCSI_MACB_SINGLE_COL_FRAMES 0x1a144
29010 #define S_SINGLECOLTXFRAMES 0
29011 #define M_SINGLECOLTXFRAMES 0xffffU
29012 #define V_SINGLECOLTXFRAMES(x) ((x) << S_SINGLECOLTXFRAMES)
29013 #define G_SINGLECOLTXFRAMES(x) (((x) >> S_SINGLECOLTXFRAMES) & M_SINGLECOLTXFRAMES)
29015 #define A_NCSI_MACB_MUL_COL_FRAMES 0x1a148
29017 #define S_MULCOLTXFRAMES 0
29018 #define M_MULCOLTXFRAMES 0xffffU
29019 #define V_MULCOLTXFRAMES(x) ((x) << S_MULCOLTXFRAMES)
29020 #define G_MULCOLTXFRAMES(x) (((x) >> S_MULCOLTXFRAMES) & M_MULCOLTXFRAMES)
29022 #define A_NCSI_MACB_RX_FRAMES_OK 0x1a14c
29024 #define S_RXFRAMESOK 0
29025 #define M_RXFRAMESOK 0xffffffU
29026 #define V_RXFRAMESOK(x) ((x) << S_RXFRAMESOK)
29027 #define G_RXFRAMESOK(x) (((x) >> S_RXFRAMESOK) & M_RXFRAMESOK)
29029 #define A_NCSI_MACB_FCS_ERR 0x1a150
29031 #define S_RXFCSERR 0
29032 #define M_RXFCSERR 0xffU
29033 #define V_RXFCSERR(x) ((x) << S_RXFCSERR)
29034 #define G_RXFCSERR(x) (((x) >> S_RXFCSERR) & M_RXFCSERR)
29036 #define A_NCSI_MACB_ALIGN_ERR 0x1a154
29038 #define S_RXALIGNERR 0
29039 #define M_RXALIGNERR 0xffU
29040 #define V_RXALIGNERR(x) ((x) << S_RXALIGNERR)
29041 #define G_RXALIGNERR(x) (((x) >> S_RXALIGNERR) & M_RXALIGNERR)
29043 #define A_NCSI_MACB_DEF_TX_FRAMES 0x1a158
29045 #define S_TXDEFERREDFRAMES 0
29046 #define M_TXDEFERREDFRAMES 0xffffU
29047 #define V_TXDEFERREDFRAMES(x) ((x) << S_TXDEFERREDFRAMES)
29048 #define G_TXDEFERREDFRAMES(x) (((x) >> S_TXDEFERREDFRAMES) & M_TXDEFERREDFRAMES)
29050 #define A_NCSI_MACB_LATE_COL 0x1a15c
29052 #define S_LATECOLLISIONS 0
29053 #define M_LATECOLLISIONS 0xffffU
29054 #define V_LATECOLLISIONS(x) ((x) << S_LATECOLLISIONS)
29055 #define G_LATECOLLISIONS(x) (((x) >> S_LATECOLLISIONS) & M_LATECOLLISIONS)
29057 #define A_NCSI_MACB_EXCESSIVE_COL 0x1a160
29059 #define S_EXCESSIVECOLLISIONS 0
29060 #define M_EXCESSIVECOLLISIONS 0xffU
29061 #define V_EXCESSIVECOLLISIONS(x) ((x) << S_EXCESSIVECOLLISIONS)
29062 #define G_EXCESSIVECOLLISIONS(x) (((x) >> S_EXCESSIVECOLLISIONS) & M_EXCESSIVECOLLISIONS)
29064 #define A_NCSI_MACB_TX_UNDERRUN_ERR 0x1a164
29066 #define S_TXUNDERRUNERR 0
29067 #define M_TXUNDERRUNERR 0xffU
29068 #define V_TXUNDERRUNERR(x) ((x) << S_TXUNDERRUNERR)
29069 #define G_TXUNDERRUNERR(x) (((x) >> S_TXUNDERRUNERR) & M_TXUNDERRUNERR)
29071 #define A_NCSI_MACB_CARRIER_SENSE_ERR 0x1a168
29073 #define S_CARRIERSENSEERRS 0
29074 #define M_CARRIERSENSEERRS 0xffU
29075 #define V_CARRIERSENSEERRS(x) ((x) << S_CARRIERSENSEERRS)
29076 #define G_CARRIERSENSEERRS(x) (((x) >> S_CARRIERSENSEERRS) & M_CARRIERSENSEERRS)
29078 #define A_NCSI_MACB_RX_RESOURCE_ERR 0x1a16c
29080 #define S_RXRESOURCEERR 0
29081 #define M_RXRESOURCEERR 0xffffU
29082 #define V_RXRESOURCEERR(x) ((x) << S_RXRESOURCEERR)
29083 #define G_RXRESOURCEERR(x) (((x) >> S_RXRESOURCEERR) & M_RXRESOURCEERR)
29085 #define A_NCSI_MACB_RX_OVERRUN_ERR 0x1a170
29087 #define S_RXOVERRUNERRCNT 0
29088 #define M_RXOVERRUNERRCNT 0xffU
29089 #define V_RXOVERRUNERRCNT(x) ((x) << S_RXOVERRUNERRCNT)
29090 #define G_RXOVERRUNERRCNT(x) (((x) >> S_RXOVERRUNERRCNT) & M_RXOVERRUNERRCNT)
29092 #define A_NCSI_MACB_RX_SYMBOL_ERR 0x1a174
29094 #define S_RXSYMBOLERR 0
29095 #define M_RXSYMBOLERR 0xffU
29096 #define V_RXSYMBOLERR(x) ((x) << S_RXSYMBOLERR)
29097 #define G_RXSYMBOLERR(x) (((x) >> S_RXSYMBOLERR) & M_RXSYMBOLERR)
29099 #define A_NCSI_MACB_RX_OVERSIZE_FRAME 0x1a178
29101 #define S_RXOVERSIZEERR 0
29102 #define M_RXOVERSIZEERR 0xffU
29103 #define V_RXOVERSIZEERR(x) ((x) << S_RXOVERSIZEERR)
29104 #define G_RXOVERSIZEERR(x) (((x) >> S_RXOVERSIZEERR) & M_RXOVERSIZEERR)
29106 #define A_NCSI_MACB_RX_JABBER_ERR 0x1a17c
29108 #define S_RXJABBERERR 0
29109 #define M_RXJABBERERR 0xffU
29110 #define V_RXJABBERERR(x) ((x) << S_RXJABBERERR)
29111 #define G_RXJABBERERR(x) (((x) >> S_RXJABBERERR) & M_RXJABBERERR)
29113 #define A_NCSI_MACB_RX_UNDERSIZE_FRAME 0x1a180
29115 #define S_RXUNDERSIZEFR 0
29116 #define M_RXUNDERSIZEFR 0xffU
29117 #define V_RXUNDERSIZEFR(x) ((x) << S_RXUNDERSIZEFR)
29118 #define G_RXUNDERSIZEFR(x) (((x) >> S_RXUNDERSIZEFR) & M_RXUNDERSIZEFR)
29120 #define A_NCSI_MACB_SQE_TEST_ERR 0x1a184
29122 #define S_SQETESTERR 0
29123 #define M_SQETESTERR 0xffU
29124 #define V_SQETESTERR(x) ((x) << S_SQETESTERR)
29125 #define G_SQETESTERR(x) (((x) >> S_SQETESTERR) & M_SQETESTERR)
29127 #define A_NCSI_MACB_LENGTH_ERR 0x1a188
29129 #define S_LENGTHERR 0
29130 #define M_LENGTHERR 0xffU
29131 #define V_LENGTHERR(x) ((x) << S_LENGTHERR)
29132 #define G_LENGTHERR(x) (((x) >> S_LENGTHERR) & M_LENGTHERR)
29134 #define A_NCSI_MACB_TX_PAUSE_FRAMES 0x1a18c
29136 #define S_TXPAUSEFRAMES 0
29137 #define M_TXPAUSEFRAMES 0xffffU
29138 #define V_TXPAUSEFRAMES(x) ((x) << S_TXPAUSEFRAMES)
29139 #define G_TXPAUSEFRAMES(x) (((x) >> S_TXPAUSEFRAMES) & M_TXPAUSEFRAMES)
29141 #define A_NCSI_MACB_HASH_LOW 0x1a190
29142 #define A_NCSI_MACB_HASH_HIGH 0x1a194
29143 #define A_NCSI_MACB_SPECIFIC_1_LOW 0x1a198
29144 #define A_NCSI_MACB_SPECIFIC_1_HIGH 0x1a19c
29146 #define S_MATCHHIGH 0
29147 #define M_MATCHHIGH 0xffffU
29148 #define V_MATCHHIGH(x) ((x) << S_MATCHHIGH)
29149 #define G_MATCHHIGH(x) (((x) >> S_MATCHHIGH) & M_MATCHHIGH)
29151 #define A_NCSI_MACB_SPECIFIC_2_LOW 0x1a1a0
29152 #define A_NCSI_MACB_SPECIFIC_2_HIGH 0x1a1a4
29153 #define A_NCSI_MACB_SPECIFIC_3_LOW 0x1a1a8
29154 #define A_NCSI_MACB_SPECIFIC_3_HIGH 0x1a1ac
29155 #define A_NCSI_MACB_SPECIFIC_4_LOW 0x1a1b0
29156 #define A_NCSI_MACB_SPECIFIC_4_HIGH 0x1a1b4
29157 #define A_NCSI_MACB_TYPE_ID 0x1a1b8
29160 #define M_TYPEID 0xffffU
29161 #define V_TYPEID(x) ((x) << S_TYPEID)
29162 #define G_TYPEID(x) (((x) >> S_TYPEID) & M_TYPEID)
29164 #define A_NCSI_MACB_TX_PAUSE_QUANTUM 0x1a1bc
29166 #define S_TXPAUSEQUANTUM 0
29167 #define M_TXPAUSEQUANTUM 0xffffU
29168 #define V_TXPAUSEQUANTUM(x) ((x) << S_TXPAUSEQUANTUM)
29169 #define G_TXPAUSEQUANTUM(x) (((x) >> S_TXPAUSEQUANTUM) & M_TXPAUSEQUANTUM)
29171 #define A_NCSI_MACB_USER_IO 0x1a1c0
29173 #define S_USERPROGINPUT 16
29174 #define M_USERPROGINPUT 0xffffU
29175 #define V_USERPROGINPUT(x) ((x) << S_USERPROGINPUT)
29176 #define G_USERPROGINPUT(x) (((x) >> S_USERPROGINPUT) & M_USERPROGINPUT)
29178 #define S_USERPROGOUTPUT 0
29179 #define M_USERPROGOUTPUT 0xffffU
29180 #define V_USERPROGOUTPUT(x) ((x) << S_USERPROGOUTPUT)
29181 #define G_USERPROGOUTPUT(x) (((x) >> S_USERPROGOUTPUT) & M_USERPROGOUTPUT)
29183 #define A_NCSI_MACB_WOL_CFG 0x1a1c4
29185 #define S_MCHASHEN 19
29186 #define V_MCHASHEN(x) ((x) << S_MCHASHEN)
29187 #define F_MCHASHEN V_MCHASHEN(1U)
29189 #define S_SPECIFIC1EN 18
29190 #define V_SPECIFIC1EN(x) ((x) << S_SPECIFIC1EN)
29191 #define F_SPECIFIC1EN V_SPECIFIC1EN(1U)
29194 #define V_ARPEN(x) ((x) << S_ARPEN)
29195 #define F_ARPEN V_ARPEN(1U)
29197 #define S_MAGICPKTEN 16
29198 #define V_MAGICPKTEN(x) ((x) << S_MAGICPKTEN)
29199 #define F_MAGICPKTEN V_MAGICPKTEN(1U)
29201 #define S_ARPIPADDR 0
29202 #define M_ARPIPADDR 0xffffU
29203 #define V_ARPIPADDR(x) ((x) << S_ARPIPADDR)
29204 #define G_ARPIPADDR(x) (((x) >> S_ARPIPADDR) & M_ARPIPADDR)
29206 #define A_NCSI_MACB_REV_STATUS 0x1a1fc
29208 #define S_PARTREF 16
29209 #define M_PARTREF 0xffffU
29210 #define V_PARTREF(x) ((x) << S_PARTREF)
29211 #define G_PARTREF(x) (((x) >> S_PARTREF) & M_PARTREF)
29214 #define M_DESREV 0xffffU
29215 #define V_DESREV(x) ((x) << S_DESREV)
29216 #define G_DESREV(x) (((x) >> S_DESREV) & M_DESREV)
29218 /* registers for module XGMAC */
29219 #define XGMAC_BASE_ADDR 0x0
29221 #define A_XGMAC_PORT_CFG 0x1000
29223 #define S_XGMII_CLK_SEL 29
29224 #define M_XGMII_CLK_SEL 0x7U
29225 #define V_XGMII_CLK_SEL(x) ((x) << S_XGMII_CLK_SEL)
29226 #define G_XGMII_CLK_SEL(x) (((x) >> S_XGMII_CLK_SEL) & M_XGMII_CLK_SEL)
29228 #define S_SINKTX 27
29229 #define V_SINKTX(x) ((x) << S_SINKTX)
29230 #define F_SINKTX V_SINKTX(1U)
29232 #define S_SINKTXONLINKDOWN 26
29233 #define V_SINKTXONLINKDOWN(x) ((x) << S_SINKTXONLINKDOWN)
29234 #define F_SINKTXONLINKDOWN V_SINKTXONLINKDOWN(1U)
29236 #define S_XG2G_SPEED_MODE 25
29237 #define V_XG2G_SPEED_MODE(x) ((x) << S_XG2G_SPEED_MODE)
29238 #define F_XG2G_SPEED_MODE V_XG2G_SPEED_MODE(1U)
29240 #define S_LOOPNOFWD 24
29241 #define V_LOOPNOFWD(x) ((x) << S_LOOPNOFWD)
29242 #define F_LOOPNOFWD V_LOOPNOFWD(1U)
29244 #define S_XGM_TX_PAUSE_SIZE 23
29245 #define V_XGM_TX_PAUSE_SIZE(x) ((x) << S_XGM_TX_PAUSE_SIZE)
29246 #define F_XGM_TX_PAUSE_SIZE V_XGM_TX_PAUSE_SIZE(1U)
29248 #define S_XGM_TX_PAUSE_FRAME 22
29249 #define V_XGM_TX_PAUSE_FRAME(x) ((x) << S_XGM_TX_PAUSE_FRAME)
29250 #define F_XGM_TX_PAUSE_FRAME V_XGM_TX_PAUSE_FRAME(1U)
29252 #define S_XGM_TX_DISABLE_PRE 21
29253 #define V_XGM_TX_DISABLE_PRE(x) ((x) << S_XGM_TX_DISABLE_PRE)
29254 #define F_XGM_TX_DISABLE_PRE V_XGM_TX_DISABLE_PRE(1U)
29256 #define S_XGM_TX_DISABLE_CRC 20
29257 #define V_XGM_TX_DISABLE_CRC(x) ((x) << S_XGM_TX_DISABLE_CRC)
29258 #define F_XGM_TX_DISABLE_CRC V_XGM_TX_DISABLE_CRC(1U)
29260 #define S_SMUX_RX_LOOP 19
29261 #define V_SMUX_RX_LOOP(x) ((x) << S_SMUX_RX_LOOP)
29262 #define F_SMUX_RX_LOOP V_SMUX_RX_LOOP(1U)
29264 #define S_RX_LANE_SWAP 18
29265 #define V_RX_LANE_SWAP(x) ((x) << S_RX_LANE_SWAP)
29266 #define F_RX_LANE_SWAP V_RX_LANE_SWAP(1U)
29268 #define S_TX_LANE_SWAP 17
29269 #define V_TX_LANE_SWAP(x) ((x) << S_TX_LANE_SWAP)
29270 #define F_TX_LANE_SWAP V_TX_LANE_SWAP(1U)
29272 #define S_SIGNAL_DET 14
29273 #define V_SIGNAL_DET(x) ((x) << S_SIGNAL_DET)
29274 #define F_SIGNAL_DET V_SIGNAL_DET(1U)
29276 #define S_PMUX_RX_LOOP 13
29277 #define V_PMUX_RX_LOOP(x) ((x) << S_PMUX_RX_LOOP)
29278 #define F_PMUX_RX_LOOP V_PMUX_RX_LOOP(1U)
29280 #define S_PMUX_TX_LOOP 12
29281 #define V_PMUX_TX_LOOP(x) ((x) << S_PMUX_TX_LOOP)
29282 #define F_PMUX_TX_LOOP V_PMUX_TX_LOOP(1U)
29284 #define S_XGM_RX_SEL 10
29285 #define M_XGM_RX_SEL 0x3U
29286 #define V_XGM_RX_SEL(x) ((x) << S_XGM_RX_SEL)
29287 #define G_XGM_RX_SEL(x) (((x) >> S_XGM_RX_SEL) & M_XGM_RX_SEL)
29289 #define S_PCS_TX_SEL 8
29290 #define M_PCS_TX_SEL 0x3U
29291 #define V_PCS_TX_SEL(x) ((x) << S_PCS_TX_SEL)
29292 #define G_PCS_TX_SEL(x) (((x) >> S_PCS_TX_SEL) & M_PCS_TX_SEL)
29294 #define S_XAUI20_REM_PRE 5
29295 #define V_XAUI20_REM_PRE(x) ((x) << S_XAUI20_REM_PRE)
29296 #define F_XAUI20_REM_PRE V_XAUI20_REM_PRE(1U)
29298 #define S_XAUI20_XGMII_SEL 4
29299 #define V_XAUI20_XGMII_SEL(x) ((x) << S_XAUI20_XGMII_SEL)
29300 #define F_XAUI20_XGMII_SEL V_XAUI20_XGMII_SEL(1U)
29302 #define S_PORT_SEL 0
29303 #define V_PORT_SEL(x) ((x) << S_PORT_SEL)
29304 #define F_PORT_SEL V_PORT_SEL(1U)
29306 #define A_XGMAC_PORT_RESET_CTRL 0x1004
29308 #define S_AUXEXT_RESET 10
29309 #define V_AUXEXT_RESET(x) ((x) << S_AUXEXT_RESET)
29310 #define F_AUXEXT_RESET V_AUXEXT_RESET(1U)
29312 #define S_TXFIFO_RESET 9
29313 #define V_TXFIFO_RESET(x) ((x) << S_TXFIFO_RESET)
29314 #define F_TXFIFO_RESET V_TXFIFO_RESET(1U)
29316 #define S_RXFIFO_RESET 8
29317 #define V_RXFIFO_RESET(x) ((x) << S_RXFIFO_RESET)
29318 #define F_RXFIFO_RESET V_RXFIFO_RESET(1U)
29320 #define S_BEAN_RESET 7
29321 #define V_BEAN_RESET(x) ((x) << S_BEAN_RESET)
29322 #define F_BEAN_RESET V_BEAN_RESET(1U)
29324 #define S_XAUI_RESET 6
29325 #define V_XAUI_RESET(x) ((x) << S_XAUI_RESET)
29326 #define F_XAUI_RESET V_XAUI_RESET(1U)
29328 #define S_AE_RESET 5
29329 #define V_AE_RESET(x) ((x) << S_AE_RESET)
29330 #define F_AE_RESET V_AE_RESET(1U)
29332 #define S_XGM_RESET 4
29333 #define V_XGM_RESET(x) ((x) << S_XGM_RESET)
29334 #define F_XGM_RESET V_XGM_RESET(1U)
29336 #define S_XG2G_RESET 3
29337 #define V_XG2G_RESET(x) ((x) << S_XG2G_RESET)
29338 #define F_XG2G_RESET V_XG2G_RESET(1U)
29340 #define S_WOL_RESET 2
29341 #define V_WOL_RESET(x) ((x) << S_WOL_RESET)
29342 #define F_WOL_RESET V_WOL_RESET(1U)
29344 #define S_XFI_PCS_RESET 1
29345 #define V_XFI_PCS_RESET(x) ((x) << S_XFI_PCS_RESET)
29346 #define F_XFI_PCS_RESET V_XFI_PCS_RESET(1U)
29348 #define S_HSS_RESET 0
29349 #define V_HSS_RESET(x) ((x) << S_HSS_RESET)
29350 #define F_HSS_RESET V_HSS_RESET(1U)
29352 #define A_XGMAC_PORT_LED_CFG 0x1008
29354 #define S_LED1_CFG 5
29355 #define M_LED1_CFG 0x7U
29356 #define V_LED1_CFG(x) ((x) << S_LED1_CFG)
29357 #define G_LED1_CFG(x) (((x) >> S_LED1_CFG) & M_LED1_CFG)
29359 #define S_LED1_POLARITY_INV 4
29360 #define V_LED1_POLARITY_INV(x) ((x) << S_LED1_POLARITY_INV)
29361 #define F_LED1_POLARITY_INV V_LED1_POLARITY_INV(1U)
29363 #define S_LED0_CFG 1
29364 #define M_LED0_CFG 0x7U
29365 #define V_LED0_CFG(x) ((x) << S_LED0_CFG)
29366 #define G_LED0_CFG(x) (((x) >> S_LED0_CFG) & M_LED0_CFG)
29368 #define S_LED0_POLARITY_INV 0
29369 #define V_LED0_POLARITY_INV(x) ((x) << S_LED0_POLARITY_INV)
29370 #define F_LED0_POLARITY_INV V_LED0_POLARITY_INV(1U)
29372 #define A_XGMAC_PORT_LED_COUNTHI 0x100c
29374 #define S_LED_COUNT_HI 0
29375 #define M_LED_COUNT_HI 0x1ffffffU
29376 #define V_LED_COUNT_HI(x) ((x) << S_LED_COUNT_HI)
29377 #define G_LED_COUNT_HI(x) (((x) >> S_LED_COUNT_HI) & M_LED_COUNT_HI)
29379 #define A_XGMAC_PORT_LED_COUNTLO 0x1010
29381 #define S_LED_COUNT_LO 0
29382 #define M_LED_COUNT_LO 0x1ffffffU
29383 #define V_LED_COUNT_LO(x) ((x) << S_LED_COUNT_LO)
29384 #define G_LED_COUNT_LO(x) (((x) >> S_LED_COUNT_LO) & M_LED_COUNT_LO)
29386 #define A_XGMAC_PORT_DEBUG_CFG 0x1014
29388 #define S_TESTCLK_SEL 0
29389 #define M_TESTCLK_SEL 0xfU
29390 #define V_TESTCLK_SEL(x) ((x) << S_TESTCLK_SEL)
29391 #define G_TESTCLK_SEL(x) (((x) >> S_TESTCLK_SEL) & M_TESTCLK_SEL)
29393 #define A_XGMAC_PORT_CFG2 0x1018
29395 #define S_RX_POLARITY_INV 28
29396 #define M_RX_POLARITY_INV 0xfU
29397 #define V_RX_POLARITY_INV(x) ((x) << S_RX_POLARITY_INV)
29398 #define G_RX_POLARITY_INV(x) (((x) >> S_RX_POLARITY_INV) & M_RX_POLARITY_INV)
29400 #define S_TX_POLARITY_INV 24
29401 #define M_TX_POLARITY_INV 0xfU
29402 #define V_TX_POLARITY_INV(x) ((x) << S_TX_POLARITY_INV)
29403 #define G_TX_POLARITY_INV(x) (((x) >> S_TX_POLARITY_INV) & M_TX_POLARITY_INV)
29405 #define S_INSTANCENUM 22
29406 #define M_INSTANCENUM 0x3U
29407 #define V_INSTANCENUM(x) ((x) << S_INSTANCENUM)
29408 #define G_INSTANCENUM(x) (((x) >> S_INSTANCENUM) & M_INSTANCENUM)
29410 #define S_STOPONPERR 21
29411 #define V_STOPONPERR(x) ((x) << S_STOPONPERR)
29412 #define F_STOPONPERR V_STOPONPERR(1U)
29414 #define S_MACTXEN 20
29415 #define V_MACTXEN(x) ((x) << S_MACTXEN)
29416 #define F_MACTXEN V_MACTXEN(1U)
29418 #define S_MACRXEN 19
29419 #define V_MACRXEN(x) ((x) << S_MACRXEN)
29420 #define F_MACRXEN V_MACRXEN(1U)
29423 #define V_PATEN(x) ((x) << S_PATEN)
29424 #define F_PATEN V_PATEN(1U)
29426 #define S_MAGICEN 17
29427 #define V_MAGICEN(x) ((x) << S_MAGICEN)
29428 #define F_MAGICEN V_MAGICEN(1U)
29431 #define M_TX_IPG 0x1fffU
29432 #define V_TX_IPG(x) ((x) << S_TX_IPG)
29433 #define G_TX_IPG(x) (((x) >> S_TX_IPG) & M_TX_IPG)
29435 #define S_AEC_PMA_TX_READY 1
29436 #define V_AEC_PMA_TX_READY(x) ((x) << S_AEC_PMA_TX_READY)
29437 #define F_AEC_PMA_TX_READY V_AEC_PMA_TX_READY(1U)
29439 #define S_AEC_PMA_RX_READY 0
29440 #define V_AEC_PMA_RX_READY(x) ((x) << S_AEC_PMA_RX_READY)
29441 #define F_AEC_PMA_RX_READY V_AEC_PMA_RX_READY(1U)
29443 #define A_XGMAC_PORT_PKT_COUNT 0x101c
29445 #define S_TX_SOP_COUNT 24
29446 #define M_TX_SOP_COUNT 0xffU
29447 #define V_TX_SOP_COUNT(x) ((x) << S_TX_SOP_COUNT)
29448 #define G_TX_SOP_COUNT(x) (((x) >> S_TX_SOP_COUNT) & M_TX_SOP_COUNT)
29450 #define S_TX_EOP_COUNT 16
29451 #define M_TX_EOP_COUNT 0xffU
29452 #define V_TX_EOP_COUNT(x) ((x) << S_TX_EOP_COUNT)
29453 #define G_TX_EOP_COUNT(x) (((x) >> S_TX_EOP_COUNT) & M_TX_EOP_COUNT)
29455 #define S_RX_SOP_COUNT 8
29456 #define M_RX_SOP_COUNT 0xffU
29457 #define V_RX_SOP_COUNT(x) ((x) << S_RX_SOP_COUNT)
29458 #define G_RX_SOP_COUNT(x) (((x) >> S_RX_SOP_COUNT) & M_RX_SOP_COUNT)
29460 #define S_RX_EOP_COUNT 0
29461 #define M_RX_EOP_COUNT 0xffU
29462 #define V_RX_EOP_COUNT(x) ((x) << S_RX_EOP_COUNT)
29463 #define G_RX_EOP_COUNT(x) (((x) >> S_RX_EOP_COUNT) & M_RX_EOP_COUNT)
29465 #define A_XGMAC_PORT_PERR_INJECT 0x1020
29467 #define S_XGMMEMSEL 1
29468 #define V_XGMMEMSEL(x) ((x) << S_XGMMEMSEL)
29469 #define F_XGMMEMSEL V_XGMMEMSEL(1U)
29471 #define A_XGMAC_PORT_MAGIC_MACID_LO 0x1024
29472 #define A_XGMAC_PORT_MAGIC_MACID_HI 0x1028
29474 #define S_MAC_WOL_DA 0
29475 #define M_MAC_WOL_DA 0xffffU
29476 #define V_MAC_WOL_DA(x) ((x) << S_MAC_WOL_DA)
29477 #define G_MAC_WOL_DA(x) (((x) >> S_MAC_WOL_DA) & M_MAC_WOL_DA)
29479 #define A_XGMAC_PORT_BUILD_REVISION 0x102c
29480 #define A_XGMAC_PORT_XGMII_SE_COUNT 0x1030
29483 #define M_TXSOP 0xffU
29484 #define V_TXSOP(x) ((x) << S_TXSOP)
29485 #define G_TXSOP(x) (((x) >> S_TXSOP) & M_TXSOP)
29488 #define M_TXEOP 0xffU
29489 #define V_TXEOP(x) ((x) << S_TXEOP)
29490 #define G_TXEOP(x) (((x) >> S_TXEOP) & M_TXEOP)
29493 #define M_RXSOP 0xffU
29494 #define V_RXSOP(x) ((x) << S_RXSOP)
29495 #define G_RXSOP(x) (((x) >> S_RXSOP) & M_RXSOP)
29497 #define A_XGMAC_PORT_LINK_STATUS 0x1034
29500 #define V_REMFLT(x) ((x) << S_REMFLT)
29501 #define F_REMFLT V_REMFLT(1U)
29504 #define V_LOCFLT(x) ((x) << S_LOCFLT)
29505 #define F_LOCFLT V_LOCFLT(1U)
29508 #define V_LINKUP(x) ((x) << S_LINKUP)
29509 #define F_LINKUP V_LINKUP(1U)
29512 #define V_LINKDN(x) ((x) << S_LINKDN)
29513 #define F_LINKDN V_LINKDN(1U)
29515 #define A_XGMAC_PORT_CHECKIN 0x1038
29517 #define S_PREAMBLE 1
29518 #define V_PREAMBLE(x) ((x) << S_PREAMBLE)
29519 #define F_PREAMBLE V_PREAMBLE(1U)
29521 #define S_CHECKIN 0
29522 #define V_CHECKIN(x) ((x) << S_CHECKIN)
29523 #define F_CHECKIN V_CHECKIN(1U)
29525 #define A_XGMAC_PORT_FAULT_TEST 0x103c
29527 #define S_FLTTYPE 1
29528 #define V_FLTTYPE(x) ((x) << S_FLTTYPE)
29529 #define F_FLTTYPE V_FLTTYPE(1U)
29531 #define S_FLTCTRL 0
29532 #define V_FLTCTRL(x) ((x) << S_FLTCTRL)
29533 #define F_FLTCTRL V_FLTCTRL(1U)
29535 #define A_XGMAC_PORT_SPARE 0x1040
29536 #define A_XGMAC_PORT_HSS_SIGDET_STATUS 0x1044
29538 #define S_SIGNALDETECT 0
29539 #define M_SIGNALDETECT 0xfU
29540 #define V_SIGNALDETECT(x) ((x) << S_SIGNALDETECT)
29541 #define G_SIGNALDETECT(x) (((x) >> S_SIGNALDETECT) & M_SIGNALDETECT)
29543 #define A_XGMAC_PORT_EXT_LOS_STATUS 0x1048
29544 #define A_XGMAC_PORT_EXT_LOS_CTRL 0x104c
29547 #define M_CTRL 0xfU
29548 #define V_CTRL(x) ((x) << S_CTRL)
29549 #define G_CTRL(x) (((x) >> S_CTRL) & M_CTRL)
29551 #define A_XGMAC_PORT_FPGA_PAUSE_CTL 0x1050
29554 #define V_CTL(x) ((x) << S_CTL)
29555 #define F_CTL V_CTL(1U)
29558 #define M_HWM 0x1fffU
29559 #define V_HWM(x) ((x) << S_HWM)
29560 #define G_HWM(x) (((x) >> S_HWM) & M_HWM)
29563 #define M_LWM 0x1fffU
29564 #define V_LWM(x) ((x) << S_LWM)
29565 #define G_LWM(x) (((x) >> S_LWM) & M_LWM)
29567 #define A_XGMAC_PORT_FPGA_ERRPKT_CNT 0x1054
29568 #define A_XGMAC_PORT_LA_TX_0 0x1058
29569 #define A_XGMAC_PORT_LA_RX_0 0x105c
29570 #define A_XGMAC_PORT_FPGA_LA_CTL 0x1060
29573 #define V_RXRST(x) ((x) << S_RXRST)
29574 #define F_RXRST V_RXRST(1U)
29577 #define V_TXRST(x) ((x) << S_TXRST)
29578 #define F_TXRST V_TXRST(1U)
29581 #define V_XGMII(x) ((x) << S_XGMII)
29582 #define F_XGMII V_XGMII(1U)
29584 #define S_LAPAUSE 2
29585 #define V_LAPAUSE(x) ((x) << S_LAPAUSE)
29586 #define F_LAPAUSE V_LAPAUSE(1U)
29588 #define S_STOPERR 1
29589 #define V_STOPERR(x) ((x) << S_STOPERR)
29590 #define F_STOPERR V_STOPERR(1U)
29593 #define V_LASTOP(x) ((x) << S_LASTOP)
29594 #define F_LASTOP V_LASTOP(1U)
29596 #define A_XGMAC_PORT_EPIO_DATA0 0x10c0
29597 #define A_XGMAC_PORT_EPIO_DATA1 0x10c4
29598 #define A_XGMAC_PORT_EPIO_DATA2 0x10c8
29599 #define A_XGMAC_PORT_EPIO_DATA3 0x10cc
29600 #define A_XGMAC_PORT_EPIO_OP 0x10d0
29603 #define V_EPIOWR(x) ((x) << S_EPIOWR)
29604 #define F_EPIOWR V_EPIOWR(1U)
29606 #define S_ADDRESS 0
29607 #define M_ADDRESS 0xffU
29608 #define V_ADDRESS(x) ((x) << S_ADDRESS)
29609 #define G_ADDRESS(x) (((x) >> S_ADDRESS) & M_ADDRESS)
29611 #define A_XGMAC_PORT_WOL_STATUS 0x10d4
29613 #define S_MAGICDETECTED 31
29614 #define V_MAGICDETECTED(x) ((x) << S_MAGICDETECTED)
29615 #define F_MAGICDETECTED V_MAGICDETECTED(1U)
29617 #define S_PATDETECTED 30
29618 #define V_PATDETECTED(x) ((x) << S_PATDETECTED)
29619 #define F_PATDETECTED V_PATDETECTED(1U)
29621 #define S_CLEARMAGIC 4
29622 #define V_CLEARMAGIC(x) ((x) << S_CLEARMAGIC)
29623 #define F_CLEARMAGIC V_CLEARMAGIC(1U)
29625 #define S_CLEARMATCH 3
29626 #define V_CLEARMATCH(x) ((x) << S_CLEARMATCH)
29627 #define F_CLEARMATCH V_CLEARMATCH(1U)
29629 #define S_MATCHEDFILTER 0
29630 #define M_MATCHEDFILTER 0x7U
29631 #define V_MATCHEDFILTER(x) ((x) << S_MATCHEDFILTER)
29632 #define G_MATCHEDFILTER(x) (((x) >> S_MATCHEDFILTER) & M_MATCHEDFILTER)
29634 #define A_XGMAC_PORT_INT_EN 0x10d8
29636 #define S_EXT_LOS 28
29637 #define V_EXT_LOS(x) ((x) << S_EXT_LOS)
29638 #define F_EXT_LOS V_EXT_LOS(1U)
29640 #define S_INCMPTBL_LINK 27
29641 #define V_INCMPTBL_LINK(x) ((x) << S_INCMPTBL_LINK)
29642 #define F_INCMPTBL_LINK V_INCMPTBL_LINK(1U)
29644 #define S_PATDETWAKE 26
29645 #define V_PATDETWAKE(x) ((x) << S_PATDETWAKE)
29646 #define F_PATDETWAKE V_PATDETWAKE(1U)
29648 #define S_MAGICWAKE 25
29649 #define V_MAGICWAKE(x) ((x) << S_MAGICWAKE)
29650 #define F_MAGICWAKE V_MAGICWAKE(1U)
29652 #define S_SIGDETCHG 24
29653 #define V_SIGDETCHG(x) ((x) << S_SIGDETCHG)
29654 #define F_SIGDETCHG V_SIGDETCHG(1U)
29656 #define S_PCSR_FEC_CORR 23
29657 #define V_PCSR_FEC_CORR(x) ((x) << S_PCSR_FEC_CORR)
29658 #define F_PCSR_FEC_CORR V_PCSR_FEC_CORR(1U)
29660 #define S_AE_TRAIN_LOCAL 22
29661 #define V_AE_TRAIN_LOCAL(x) ((x) << S_AE_TRAIN_LOCAL)
29662 #define F_AE_TRAIN_LOCAL V_AE_TRAIN_LOCAL(1U)
29664 #define S_HSSPLL_LOCK 21
29665 #define V_HSSPLL_LOCK(x) ((x) << S_HSSPLL_LOCK)
29666 #define F_HSSPLL_LOCK V_HSSPLL_LOCK(1U)
29668 #define S_HSSPRT_READY 20
29669 #define V_HSSPRT_READY(x) ((x) << S_HSSPRT_READY)
29670 #define F_HSSPRT_READY V_HSSPRT_READY(1U)
29672 #define S_AUTONEG_DONE 19
29673 #define V_AUTONEG_DONE(x) ((x) << S_AUTONEG_DONE)
29674 #define F_AUTONEG_DONE V_AUTONEG_DONE(1U)
29676 #define S_PCSR_HI_BER 18
29677 #define V_PCSR_HI_BER(x) ((x) << S_PCSR_HI_BER)
29678 #define F_PCSR_HI_BER V_PCSR_HI_BER(1U)
29680 #define S_PCSR_FEC_ERROR 17
29681 #define V_PCSR_FEC_ERROR(x) ((x) << S_PCSR_FEC_ERROR)
29682 #define F_PCSR_FEC_ERROR V_PCSR_FEC_ERROR(1U)
29684 #define S_PCSR_LINK_FAIL 16
29685 #define V_PCSR_LINK_FAIL(x) ((x) << S_PCSR_LINK_FAIL)
29686 #define F_PCSR_LINK_FAIL V_PCSR_LINK_FAIL(1U)
29688 #define S_XAUI_DEC_ERROR 15
29689 #define V_XAUI_DEC_ERROR(x) ((x) << S_XAUI_DEC_ERROR)
29690 #define F_XAUI_DEC_ERROR V_XAUI_DEC_ERROR(1U)
29692 #define S_XAUI_LINK_FAIL 14
29693 #define V_XAUI_LINK_FAIL(x) ((x) << S_XAUI_LINK_FAIL)
29694 #define F_XAUI_LINK_FAIL V_XAUI_LINK_FAIL(1U)
29696 #define S_PCS_CTC_ERROR 13
29697 #define V_PCS_CTC_ERROR(x) ((x) << S_PCS_CTC_ERROR)
29698 #define F_PCS_CTC_ERROR V_PCS_CTC_ERROR(1U)
29700 #define S_PCS_LINK_GOOD 12
29701 #define V_PCS_LINK_GOOD(x) ((x) << S_PCS_LINK_GOOD)
29702 #define F_PCS_LINK_GOOD V_PCS_LINK_GOOD(1U)
29704 #define S_PCS_LINK_FAIL 11
29705 #define V_PCS_LINK_FAIL(x) ((x) << S_PCS_LINK_FAIL)
29706 #define F_PCS_LINK_FAIL V_PCS_LINK_FAIL(1U)
29708 #define S_RXFIFOOVERFLOW 10
29709 #define V_RXFIFOOVERFLOW(x) ((x) << S_RXFIFOOVERFLOW)
29710 #define F_RXFIFOOVERFLOW V_RXFIFOOVERFLOW(1U)
29712 #define S_HSSPRBSERR 9
29713 #define V_HSSPRBSERR(x) ((x) << S_HSSPRBSERR)
29714 #define F_HSSPRBSERR V_HSSPRBSERR(1U)
29716 #define S_HSSEYEQUAL 8
29717 #define V_HSSEYEQUAL(x) ((x) << S_HSSEYEQUAL)
29718 #define F_HSSEYEQUAL V_HSSEYEQUAL(1U)
29720 #define S_REMOTEFAULT 7
29721 #define V_REMOTEFAULT(x) ((x) << S_REMOTEFAULT)
29722 #define F_REMOTEFAULT V_REMOTEFAULT(1U)
29724 #define S_LOCALFAULT 6
29725 #define V_LOCALFAULT(x) ((x) << S_LOCALFAULT)
29726 #define F_LOCALFAULT V_LOCALFAULT(1U)
29728 #define S_MAC_LINK_DOWN 5
29729 #define V_MAC_LINK_DOWN(x) ((x) << S_MAC_LINK_DOWN)
29730 #define F_MAC_LINK_DOWN V_MAC_LINK_DOWN(1U)
29732 #define S_MAC_LINK_UP 4
29733 #define V_MAC_LINK_UP(x) ((x) << S_MAC_LINK_UP)
29734 #define F_MAC_LINK_UP V_MAC_LINK_UP(1U)
29736 #define S_BEAN_INT 3
29737 #define V_BEAN_INT(x) ((x) << S_BEAN_INT)
29738 #define F_BEAN_INT V_BEAN_INT(1U)
29740 #define S_XGM_INT 2
29741 #define V_XGM_INT(x) ((x) << S_XGM_INT)
29742 #define F_XGM_INT V_XGM_INT(1U)
29744 #define A_XGMAC_PORT_INT_CAUSE 0x10dc
29745 #define A_XGMAC_PORT_HSS_CFG0 0x10e0
29748 #define V_TXDTS(x) ((x) << S_TXDTS)
29749 #define F_TXDTS V_TXDTS(1U)
29752 #define V_TXCTS(x) ((x) << S_TXCTS)
29753 #define F_TXCTS V_TXCTS(1U)
29756 #define V_TXBTS(x) ((x) << S_TXBTS)
29757 #define F_TXBTS V_TXBTS(1U)
29760 #define V_TXATS(x) ((x) << S_TXATS)
29761 #define F_TXATS V_TXATS(1U)
29763 #define S_TXDOBS 27
29764 #define V_TXDOBS(x) ((x) << S_TXDOBS)
29765 #define F_TXDOBS V_TXDOBS(1U)
29767 #define S_TXCOBS 26
29768 #define V_TXCOBS(x) ((x) << S_TXCOBS)
29769 #define F_TXCOBS V_TXCOBS(1U)
29771 #define S_TXBOBS 25
29772 #define V_TXBOBS(x) ((x) << S_TXBOBS)
29773 #define F_TXBOBS V_TXBOBS(1U)
29775 #define S_TXAOBS 24
29776 #define V_TXAOBS(x) ((x) << S_TXAOBS)
29777 #define F_TXAOBS V_TXAOBS(1U)
29779 #define S_HSSREFCLKSEL 20
29780 #define V_HSSREFCLKSEL(x) ((x) << S_HSSREFCLKSEL)
29781 #define F_HSSREFCLKSEL V_HSSREFCLKSEL(1U)
29783 #define S_HSSAVDHI 17
29784 #define V_HSSAVDHI(x) ((x) << S_HSSAVDHI)
29785 #define F_HSSAVDHI V_HSSAVDHI(1U)
29787 #define S_HSSRXTS 16
29788 #define V_HSSRXTS(x) ((x) << S_HSSRXTS)
29789 #define F_HSSRXTS V_HSSRXTS(1U)
29791 #define S_HSSTXACMODE 15
29792 #define V_HSSTXACMODE(x) ((x) << S_HSSTXACMODE)
29793 #define F_HSSTXACMODE V_HSSTXACMODE(1U)
29795 #define S_HSSRXACMODE 14
29796 #define V_HSSRXACMODE(x) ((x) << S_HSSRXACMODE)
29797 #define F_HSSRXACMODE V_HSSRXACMODE(1U)
29799 #define S_HSSRESYNC 13
29800 #define V_HSSRESYNC(x) ((x) << S_HSSRESYNC)
29801 #define F_HSSRESYNC V_HSSRESYNC(1U)
29803 #define S_HSSRECCAL 12
29804 #define V_HSSRECCAL(x) ((x) << S_HSSRECCAL)
29805 #define F_HSSRECCAL V_HSSRECCAL(1U)
29807 #define S_HSSPDWNPLL 11
29808 #define V_HSSPDWNPLL(x) ((x) << S_HSSPDWNPLL)
29809 #define F_HSSPDWNPLL V_HSSPDWNPLL(1U)
29811 #define S_HSSDIVSEL 9
29812 #define M_HSSDIVSEL 0x3U
29813 #define V_HSSDIVSEL(x) ((x) << S_HSSDIVSEL)
29814 #define G_HSSDIVSEL(x) (((x) >> S_HSSDIVSEL) & M_HSSDIVSEL)
29816 #define S_HSSREFDIV 8
29817 #define V_HSSREFDIV(x) ((x) << S_HSSREFDIV)
29818 #define F_HSSREFDIV V_HSSREFDIV(1U)
29820 #define S_HSSPLLBYP 7
29821 #define V_HSSPLLBYP(x) ((x) << S_HSSPLLBYP)
29822 #define F_HSSPLLBYP V_HSSPLLBYP(1U)
29824 #define S_HSSLOFREQPLL 6
29825 #define V_HSSLOFREQPLL(x) ((x) << S_HSSLOFREQPLL)
29826 #define F_HSSLOFREQPLL V_HSSLOFREQPLL(1U)
29828 #define S_HSSLOFREQ2PLL 5
29829 #define V_HSSLOFREQ2PLL(x) ((x) << S_HSSLOFREQ2PLL)
29830 #define F_HSSLOFREQ2PLL V_HSSLOFREQ2PLL(1U)
29832 #define S_HSSEXTC16SEL 4
29833 #define V_HSSEXTC16SEL(x) ((x) << S_HSSEXTC16SEL)
29834 #define F_HSSEXTC16SEL V_HSSEXTC16SEL(1U)
29836 #define S_HSSRSTCONFIG 1
29837 #define M_HSSRSTCONFIG 0x7U
29838 #define V_HSSRSTCONFIG(x) ((x) << S_HSSRSTCONFIG)
29839 #define G_HSSRSTCONFIG(x) (((x) >> S_HSSRSTCONFIG) & M_HSSRSTCONFIG)
29841 #define S_HSSPRBSEN 0
29842 #define V_HSSPRBSEN(x) ((x) << S_HSSPRBSEN)
29843 #define F_HSSPRBSEN V_HSSPRBSEN(1U)
29845 #define A_XGMAC_PORT_HSS_CFG1 0x10e4
29847 #define S_RXDPRBSRST 28
29848 #define V_RXDPRBSRST(x) ((x) << S_RXDPRBSRST)
29849 #define F_RXDPRBSRST V_RXDPRBSRST(1U)
29851 #define S_RXDPRBSEN 27
29852 #define V_RXDPRBSEN(x) ((x) << S_RXDPRBSEN)
29853 #define F_RXDPRBSEN V_RXDPRBSEN(1U)
29855 #define S_RXDPRBSFRCERR 26
29856 #define V_RXDPRBSFRCERR(x) ((x) << S_RXDPRBSFRCERR)
29857 #define F_RXDPRBSFRCERR V_RXDPRBSFRCERR(1U)
29859 #define S_TXDPRBSRST 25
29860 #define V_TXDPRBSRST(x) ((x) << S_TXDPRBSRST)
29861 #define F_TXDPRBSRST V_TXDPRBSRST(1U)
29863 #define S_TXDPRBSEN 24
29864 #define V_TXDPRBSEN(x) ((x) << S_TXDPRBSEN)
29865 #define F_TXDPRBSEN V_TXDPRBSEN(1U)
29867 #define S_RXCPRBSRST 20
29868 #define V_RXCPRBSRST(x) ((x) << S_RXCPRBSRST)
29869 #define F_RXCPRBSRST V_RXCPRBSRST(1U)
29871 #define S_RXCPRBSEN 19
29872 #define V_RXCPRBSEN(x) ((x) << S_RXCPRBSEN)
29873 #define F_RXCPRBSEN V_RXCPRBSEN(1U)
29875 #define S_RXCPRBSFRCERR 18
29876 #define V_RXCPRBSFRCERR(x) ((x) << S_RXCPRBSFRCERR)
29877 #define F_RXCPRBSFRCERR V_RXCPRBSFRCERR(1U)
29879 #define S_TXCPRBSRST 17
29880 #define V_TXCPRBSRST(x) ((x) << S_TXCPRBSRST)
29881 #define F_TXCPRBSRST V_TXCPRBSRST(1U)
29883 #define S_TXCPRBSEN 16
29884 #define V_TXCPRBSEN(x) ((x) << S_TXCPRBSEN)
29885 #define F_TXCPRBSEN V_TXCPRBSEN(1U)
29887 #define S_RXBPRBSRST 12
29888 #define V_RXBPRBSRST(x) ((x) << S_RXBPRBSRST)
29889 #define F_RXBPRBSRST V_RXBPRBSRST(1U)
29891 #define S_RXBPRBSEN 11
29892 #define V_RXBPRBSEN(x) ((x) << S_RXBPRBSEN)
29893 #define F_RXBPRBSEN V_RXBPRBSEN(1U)
29895 #define S_RXBPRBSFRCERR 10
29896 #define V_RXBPRBSFRCERR(x) ((x) << S_RXBPRBSFRCERR)
29897 #define F_RXBPRBSFRCERR V_RXBPRBSFRCERR(1U)
29899 #define S_TXBPRBSRST 9
29900 #define V_TXBPRBSRST(x) ((x) << S_TXBPRBSRST)
29901 #define F_TXBPRBSRST V_TXBPRBSRST(1U)
29903 #define S_TXBPRBSEN 8
29904 #define V_TXBPRBSEN(x) ((x) << S_TXBPRBSEN)
29905 #define F_TXBPRBSEN V_TXBPRBSEN(1U)
29907 #define S_RXAPRBSRST 4
29908 #define V_RXAPRBSRST(x) ((x) << S_RXAPRBSRST)
29909 #define F_RXAPRBSRST V_RXAPRBSRST(1U)
29911 #define S_RXAPRBSEN 3
29912 #define V_RXAPRBSEN(x) ((x) << S_RXAPRBSEN)
29913 #define F_RXAPRBSEN V_RXAPRBSEN(1U)
29915 #define S_RXAPRBSFRCERR 2
29916 #define V_RXAPRBSFRCERR(x) ((x) << S_RXAPRBSFRCERR)
29917 #define F_RXAPRBSFRCERR V_RXAPRBSFRCERR(1U)
29919 #define S_TXAPRBSRST 1
29920 #define V_TXAPRBSRST(x) ((x) << S_TXAPRBSRST)
29921 #define F_TXAPRBSRST V_TXAPRBSRST(1U)
29923 #define S_TXAPRBSEN 0
29924 #define V_TXAPRBSEN(x) ((x) << S_TXAPRBSEN)
29925 #define F_TXAPRBSEN V_TXAPRBSEN(1U)
29927 #define A_XGMAC_PORT_HSS_CFG2 0x10e8
29929 #define S_RXDDATASYNC 23
29930 #define V_RXDDATASYNC(x) ((x) << S_RXDDATASYNC)
29931 #define F_RXDDATASYNC V_RXDDATASYNC(1U)
29933 #define S_RXCDATASYNC 22
29934 #define V_RXCDATASYNC(x) ((x) << S_RXCDATASYNC)
29935 #define F_RXCDATASYNC V_RXCDATASYNC(1U)
29937 #define S_RXBDATASYNC 21
29938 #define V_RXBDATASYNC(x) ((x) << S_RXBDATASYNC)
29939 #define F_RXBDATASYNC V_RXBDATASYNC(1U)
29941 #define S_RXADATASYNC 20
29942 #define V_RXADATASYNC(x) ((x) << S_RXADATASYNC)
29943 #define F_RXADATASYNC V_RXADATASYNC(1U)
29945 #define S_RXDEARLYIN 19
29946 #define V_RXDEARLYIN(x) ((x) << S_RXDEARLYIN)
29947 #define F_RXDEARLYIN V_RXDEARLYIN(1U)
29949 #define S_RXDLATEIN 18
29950 #define V_RXDLATEIN(x) ((x) << S_RXDLATEIN)
29951 #define F_RXDLATEIN V_RXDLATEIN(1U)
29953 #define S_RXDPHSLOCK 17
29954 #define V_RXDPHSLOCK(x) ((x) << S_RXDPHSLOCK)
29955 #define F_RXDPHSLOCK V_RXDPHSLOCK(1U)
29957 #define S_RXDPHSDNIN 16
29958 #define V_RXDPHSDNIN(x) ((x) << S_RXDPHSDNIN)
29959 #define F_RXDPHSDNIN V_RXDPHSDNIN(1U)
29961 #define S_RXDPHSUPIN 15
29962 #define V_RXDPHSUPIN(x) ((x) << S_RXDPHSUPIN)
29963 #define F_RXDPHSUPIN V_RXDPHSUPIN(1U)
29965 #define S_RXCEARLYIN 14
29966 #define V_RXCEARLYIN(x) ((x) << S_RXCEARLYIN)
29967 #define F_RXCEARLYIN V_RXCEARLYIN(1U)
29969 #define S_RXCLATEIN 13
29970 #define V_RXCLATEIN(x) ((x) << S_RXCLATEIN)
29971 #define F_RXCLATEIN V_RXCLATEIN(1U)
29973 #define S_RXCPHSLOCK 12
29974 #define V_RXCPHSLOCK(x) ((x) << S_RXCPHSLOCK)
29975 #define F_RXCPHSLOCK V_RXCPHSLOCK(1U)
29977 #define S_RXCPHSDNIN 11
29978 #define V_RXCPHSDNIN(x) ((x) << S_RXCPHSDNIN)
29979 #define F_RXCPHSDNIN V_RXCPHSDNIN(1U)
29981 #define S_RXCPHSUPIN 10
29982 #define V_RXCPHSUPIN(x) ((x) << S_RXCPHSUPIN)
29983 #define F_RXCPHSUPIN V_RXCPHSUPIN(1U)
29985 #define S_RXBEARLYIN 9
29986 #define V_RXBEARLYIN(x) ((x) << S_RXBEARLYIN)
29987 #define F_RXBEARLYIN V_RXBEARLYIN(1U)
29989 #define S_RXBLATEIN 8
29990 #define V_RXBLATEIN(x) ((x) << S_RXBLATEIN)
29991 #define F_RXBLATEIN V_RXBLATEIN(1U)
29993 #define S_RXBPHSLOCK 7
29994 #define V_RXBPHSLOCK(x) ((x) << S_RXBPHSLOCK)
29995 #define F_RXBPHSLOCK V_RXBPHSLOCK(1U)
29997 #define S_RXBPHSDNIN 6
29998 #define V_RXBPHSDNIN(x) ((x) << S_RXBPHSDNIN)
29999 #define F_RXBPHSDNIN V_RXBPHSDNIN(1U)
30001 #define S_RXBPHSUPIN 5
30002 #define V_RXBPHSUPIN(x) ((x) << S_RXBPHSUPIN)
30003 #define F_RXBPHSUPIN V_RXBPHSUPIN(1U)
30005 #define S_RXAEARLYIN 4
30006 #define V_RXAEARLYIN(x) ((x) << S_RXAEARLYIN)
30007 #define F_RXAEARLYIN V_RXAEARLYIN(1U)
30009 #define S_RXALATEIN 3
30010 #define V_RXALATEIN(x) ((x) << S_RXALATEIN)
30011 #define F_RXALATEIN V_RXALATEIN(1U)
30013 #define S_RXAPHSLOCK 2
30014 #define V_RXAPHSLOCK(x) ((x) << S_RXAPHSLOCK)
30015 #define F_RXAPHSLOCK V_RXAPHSLOCK(1U)
30017 #define S_RXAPHSDNIN 1
30018 #define V_RXAPHSDNIN(x) ((x) << S_RXAPHSDNIN)
30019 #define F_RXAPHSDNIN V_RXAPHSDNIN(1U)
30021 #define S_RXAPHSUPIN 0
30022 #define V_RXAPHSUPIN(x) ((x) << S_RXAPHSUPIN)
30023 #define F_RXAPHSUPIN V_RXAPHSUPIN(1U)
30025 #define A_XGMAC_PORT_HSS_STATUS 0x10ec
30027 #define S_RXDPRBSSYNC 15
30028 #define V_RXDPRBSSYNC(x) ((x) << S_RXDPRBSSYNC)
30029 #define F_RXDPRBSSYNC V_RXDPRBSSYNC(1U)
30031 #define S_RXCPRBSSYNC 14
30032 #define V_RXCPRBSSYNC(x) ((x) << S_RXCPRBSSYNC)
30033 #define F_RXCPRBSSYNC V_RXCPRBSSYNC(1U)
30035 #define S_RXBPRBSSYNC 13
30036 #define V_RXBPRBSSYNC(x) ((x) << S_RXBPRBSSYNC)
30037 #define F_RXBPRBSSYNC V_RXBPRBSSYNC(1U)
30039 #define S_RXAPRBSSYNC 12
30040 #define V_RXAPRBSSYNC(x) ((x) << S_RXAPRBSSYNC)
30041 #define F_RXAPRBSSYNC V_RXAPRBSSYNC(1U)
30043 #define S_RXDPRBSERR 11
30044 #define V_RXDPRBSERR(x) ((x) << S_RXDPRBSERR)
30045 #define F_RXDPRBSERR V_RXDPRBSERR(1U)
30047 #define S_RXCPRBSERR 10
30048 #define V_RXCPRBSERR(x) ((x) << S_RXCPRBSERR)
30049 #define F_RXCPRBSERR V_RXCPRBSERR(1U)
30051 #define S_RXBPRBSERR 9
30052 #define V_RXBPRBSERR(x) ((x) << S_RXBPRBSERR)
30053 #define F_RXBPRBSERR V_RXBPRBSERR(1U)
30055 #define S_RXAPRBSERR 8
30056 #define V_RXAPRBSERR(x) ((x) << S_RXAPRBSERR)
30057 #define F_RXAPRBSERR V_RXAPRBSERR(1U)
30059 #define S_RXDSIGDET 7
30060 #define V_RXDSIGDET(x) ((x) << S_RXDSIGDET)
30061 #define F_RXDSIGDET V_RXDSIGDET(1U)
30063 #define S_RXCSIGDET 6
30064 #define V_RXCSIGDET(x) ((x) << S_RXCSIGDET)
30065 #define F_RXCSIGDET V_RXCSIGDET(1U)
30067 #define S_RXBSIGDET 5
30068 #define V_RXBSIGDET(x) ((x) << S_RXBSIGDET)
30069 #define F_RXBSIGDET V_RXBSIGDET(1U)
30071 #define S_RXASIGDET 4
30072 #define V_RXASIGDET(x) ((x) << S_RXASIGDET)
30073 #define F_RXASIGDET V_RXASIGDET(1U)
30075 #define S_HSSPLLLOCK 1
30076 #define V_HSSPLLLOCK(x) ((x) << S_HSSPLLLOCK)
30077 #define F_HSSPLLLOCK V_HSSPLLLOCK(1U)
30079 #define S_HSSPRTREADY 0
30080 #define V_HSSPRTREADY(x) ((x) << S_HSSPRTREADY)
30081 #define F_HSSPRTREADY V_HSSPRTREADY(1U)
30083 #define A_XGMAC_PORT_XGM_TX_CTRL 0x1200
30085 #define S_SENDPAUSE 2
30086 #define V_SENDPAUSE(x) ((x) << S_SENDPAUSE)
30087 #define F_SENDPAUSE V_SENDPAUSE(1U)
30089 #define S_SENDZEROPAUSE 1
30090 #define V_SENDZEROPAUSE(x) ((x) << S_SENDZEROPAUSE)
30091 #define F_SENDZEROPAUSE V_SENDZEROPAUSE(1U)
30093 #define S_XGM_TXEN 0
30094 #define V_XGM_TXEN(x) ((x) << S_XGM_TXEN)
30095 #define F_XGM_TXEN V_XGM_TXEN(1U)
30097 #define A_XGMAC_PORT_XGM_TX_CFG 0x1204
30100 #define M_CRCCAL 0x3U
30101 #define V_CRCCAL(x) ((x) << S_CRCCAL)
30102 #define G_CRCCAL(x) (((x) >> S_CRCCAL) & M_CRCCAL)
30104 #define S_DISDEFIDLECNT 7
30105 #define V_DISDEFIDLECNT(x) ((x) << S_DISDEFIDLECNT)
30106 #define F_DISDEFIDLECNT V_DISDEFIDLECNT(1U)
30108 #define S_DECAVGTXIPG 6
30109 #define V_DECAVGTXIPG(x) ((x) << S_DECAVGTXIPG)
30110 #define F_DECAVGTXIPG V_DECAVGTXIPG(1U)
30112 #define S_UNIDIRTXEN 5
30113 #define V_UNIDIRTXEN(x) ((x) << S_UNIDIRTXEN)
30114 #define F_UNIDIRTXEN V_UNIDIRTXEN(1U)
30116 #define S_CFGCLKSPEED 2
30117 #define M_CFGCLKSPEED 0x7U
30118 #define V_CFGCLKSPEED(x) ((x) << S_CFGCLKSPEED)
30119 #define G_CFGCLKSPEED(x) (((x) >> S_CFGCLKSPEED) & M_CFGCLKSPEED)
30121 #define S_STRETCHMODE 1
30122 #define V_STRETCHMODE(x) ((x) << S_STRETCHMODE)
30123 #define F_STRETCHMODE V_STRETCHMODE(1U)
30125 #define S_TXPAUSEEN 0
30126 #define V_TXPAUSEEN(x) ((x) << S_TXPAUSEEN)
30127 #define F_TXPAUSEEN V_TXPAUSEEN(1U)
30129 #define A_XGMAC_PORT_XGM_TX_PAUSE_QUANTA 0x1208
30131 #define S_TXPAUSEQUANTA 0
30132 #define M_TXPAUSEQUANTA 0xffffU
30133 #define V_TXPAUSEQUANTA(x) ((x) << S_TXPAUSEQUANTA)
30134 #define G_TXPAUSEQUANTA(x) (((x) >> S_TXPAUSEQUANTA) & M_TXPAUSEQUANTA)
30136 #define A_XGMAC_PORT_XGM_RX_CTRL 0x120c
30137 #define A_XGMAC_PORT_XGM_RX_CFG 0x1210
30139 #define S_RXCRCCAL 16
30140 #define M_RXCRCCAL 0x3U
30141 #define V_RXCRCCAL(x) ((x) << S_RXCRCCAL)
30142 #define G_RXCRCCAL(x) (((x) >> S_RXCRCCAL) & M_RXCRCCAL)
30144 #define S_STATLOCALFAULT 15
30145 #define V_STATLOCALFAULT(x) ((x) << S_STATLOCALFAULT)
30146 #define F_STATLOCALFAULT V_STATLOCALFAULT(1U)
30148 #define S_STATREMOTEFAULT 14
30149 #define V_STATREMOTEFAULT(x) ((x) << S_STATREMOTEFAULT)
30150 #define F_STATREMOTEFAULT V_STATREMOTEFAULT(1U)
30152 #define S_LENERRFRAMEDIS 13
30153 #define V_LENERRFRAMEDIS(x) ((x) << S_LENERRFRAMEDIS)
30154 #define F_LENERRFRAMEDIS V_LENERRFRAMEDIS(1U)
30156 #define S_CON802_3PREAMBLE 12
30157 #define V_CON802_3PREAMBLE(x) ((x) << S_CON802_3PREAMBLE)
30158 #define F_CON802_3PREAMBLE V_CON802_3PREAMBLE(1U)
30160 #define S_ENNON802_3PREAMBLE 11
30161 #define V_ENNON802_3PREAMBLE(x) ((x) << S_ENNON802_3PREAMBLE)
30162 #define F_ENNON802_3PREAMBLE V_ENNON802_3PREAMBLE(1U)
30164 #define S_COPYPREAMBLE 10
30165 #define V_COPYPREAMBLE(x) ((x) << S_COPYPREAMBLE)
30166 #define F_COPYPREAMBLE V_COPYPREAMBLE(1U)
30168 #define S_DISPAUSEFRAMES 9
30169 #define V_DISPAUSEFRAMES(x) ((x) << S_DISPAUSEFRAMES)
30170 #define F_DISPAUSEFRAMES V_DISPAUSEFRAMES(1U)
30172 #define S_EN1536BFRAMES 8
30173 #define V_EN1536BFRAMES(x) ((x) << S_EN1536BFRAMES)
30174 #define F_EN1536BFRAMES V_EN1536BFRAMES(1U)
30176 #define S_ENJUMBO 7
30177 #define V_ENJUMBO(x) ((x) << S_ENJUMBO)
30178 #define F_ENJUMBO V_ENJUMBO(1U)
30181 #define V_RMFCS(x) ((x) << S_RMFCS)
30182 #define F_RMFCS V_RMFCS(1U)
30184 #define S_DISNONVLAN 5
30185 #define V_DISNONVLAN(x) ((x) << S_DISNONVLAN)
30186 #define F_DISNONVLAN V_DISNONVLAN(1U)
30188 #define S_ENEXTMATCH 4
30189 #define V_ENEXTMATCH(x) ((x) << S_ENEXTMATCH)
30190 #define F_ENEXTMATCH V_ENEXTMATCH(1U)
30192 #define S_ENHASHUCAST 3
30193 #define V_ENHASHUCAST(x) ((x) << S_ENHASHUCAST)
30194 #define F_ENHASHUCAST V_ENHASHUCAST(1U)
30196 #define S_ENHASHMCAST 2
30197 #define V_ENHASHMCAST(x) ((x) << S_ENHASHMCAST)
30198 #define F_ENHASHMCAST V_ENHASHMCAST(1U)
30200 #define S_DISBCAST 1
30201 #define V_DISBCAST(x) ((x) << S_DISBCAST)
30202 #define F_DISBCAST V_DISBCAST(1U)
30204 #define S_COPYALLFRAMES 0
30205 #define V_COPYALLFRAMES(x) ((x) << S_COPYALLFRAMES)
30206 #define F_COPYALLFRAMES V_COPYALLFRAMES(1U)
30208 #define A_XGMAC_PORT_XGM_RX_HASH_LOW 0x1214
30209 #define A_XGMAC_PORT_XGM_RX_HASH_HIGH 0x1218
30210 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_1 0x121c
30211 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_1 0x1220
30213 #define S_ADDRESS_HIGH 0
30214 #define M_ADDRESS_HIGH 0xffffU
30215 #define V_ADDRESS_HIGH(x) ((x) << S_ADDRESS_HIGH)
30216 #define G_ADDRESS_HIGH(x) (((x) >> S_ADDRESS_HIGH) & M_ADDRESS_HIGH)
30218 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_2 0x1224
30219 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_2 0x1228
30220 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_3 0x122c
30221 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_3 0x1230
30222 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_4 0x1234
30223 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_4 0x1238
30224 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_5 0x123c
30225 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_5 0x1240
30226 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_6 0x1244
30227 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_6 0x1248
30228 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_7 0x124c
30229 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_7 0x1250
30230 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_LOW_8 0x1254
30231 #define A_XGMAC_PORT_XGM_RX_EXACT_MATCH_HIGH_8 0x1258
30232 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_1 0x125c
30234 #define S_ENTYPEMATCH 31
30235 #define V_ENTYPEMATCH(x) ((x) << S_ENTYPEMATCH)
30236 #define F_ENTYPEMATCH V_ENTYPEMATCH(1U)
30239 #define M_TYPE 0xffffU
30240 #define V_TYPE(x) ((x) << S_TYPE)
30241 #define G_TYPE(x) (((x) >> S_TYPE) & M_TYPE)
30243 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_2 0x1260
30244 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_3 0x1264
30245 #define A_XGMAC_PORT_XGM_RX_TYPE_MATCH_4 0x1268
30246 #define A_XGMAC_PORT_XGM_INT_STATUS 0x126c
30248 #define S_XGMIIEXTINT 10
30249 #define V_XGMIIEXTINT(x) ((x) << S_XGMIIEXTINT)
30250 #define F_XGMIIEXTINT V_XGMIIEXTINT(1U)
30252 #define S_LINKFAULTCHANGE 9
30253 #define V_LINKFAULTCHANGE(x) ((x) << S_LINKFAULTCHANGE)
30254 #define F_LINKFAULTCHANGE V_LINKFAULTCHANGE(1U)
30256 #define S_PHYFRAMECOMPLETE 8
30257 #define V_PHYFRAMECOMPLETE(x) ((x) << S_PHYFRAMECOMPLETE)
30258 #define F_PHYFRAMECOMPLETE V_PHYFRAMECOMPLETE(1U)
30260 #define S_PAUSEFRAMETXMT 7
30261 #define V_PAUSEFRAMETXMT(x) ((x) << S_PAUSEFRAMETXMT)
30262 #define F_PAUSEFRAMETXMT V_PAUSEFRAMETXMT(1U)
30264 #define S_PAUSECNTRTIMEOUT 6
30265 #define V_PAUSECNTRTIMEOUT(x) ((x) << S_PAUSECNTRTIMEOUT)
30266 #define F_PAUSECNTRTIMEOUT V_PAUSECNTRTIMEOUT(1U)
30268 #define S_NON0PAUSERCVD 5
30269 #define V_NON0PAUSERCVD(x) ((x) << S_NON0PAUSERCVD)
30270 #define F_NON0PAUSERCVD V_NON0PAUSERCVD(1U)
30272 #define S_STATOFLOW 4
30273 #define V_STATOFLOW(x) ((x) << S_STATOFLOW)
30274 #define F_STATOFLOW V_STATOFLOW(1U)
30276 #define S_TXERRFIFO 3
30277 #define V_TXERRFIFO(x) ((x) << S_TXERRFIFO)
30278 #define F_TXERRFIFO V_TXERRFIFO(1U)
30280 #define S_TXUFLOW 2
30281 #define V_TXUFLOW(x) ((x) << S_TXUFLOW)
30282 #define F_TXUFLOW V_TXUFLOW(1U)
30284 #define S_FRAMETXMT 1
30285 #define V_FRAMETXMT(x) ((x) << S_FRAMETXMT)
30286 #define F_FRAMETXMT V_FRAMETXMT(1U)
30288 #define S_FRAMERCVD 0
30289 #define V_FRAMERCVD(x) ((x) << S_FRAMERCVD)
30290 #define F_FRAMERCVD V_FRAMERCVD(1U)
30292 #define A_XGMAC_PORT_XGM_INT_MASK 0x1270
30293 #define A_XGMAC_PORT_XGM_INT_EN 0x1274
30294 #define A_XGMAC_PORT_XGM_INT_DISABLE 0x1278
30295 #define A_XGMAC_PORT_XGM_TX_PAUSE_TIMER 0x127c
30297 #define S_CURPAUSETIMER 0
30298 #define M_CURPAUSETIMER 0xffffU
30299 #define V_CURPAUSETIMER(x) ((x) << S_CURPAUSETIMER)
30300 #define G_CURPAUSETIMER(x) (((x) >> S_CURPAUSETIMER) & M_CURPAUSETIMER)
30302 #define A_XGMAC_PORT_XGM_STAT_CTRL 0x1280
30304 #define S_READSNPSHOT 4
30305 #define V_READSNPSHOT(x) ((x) << S_READSNPSHOT)
30306 #define F_READSNPSHOT V_READSNPSHOT(1U)
30308 #define S_TAKESNPSHOT 3
30309 #define V_TAKESNPSHOT(x) ((x) << S_TAKESNPSHOT)
30310 #define F_TAKESNPSHOT V_TAKESNPSHOT(1U)
30312 #define S_CLRSTATS 2
30313 #define V_CLRSTATS(x) ((x) << S_CLRSTATS)
30314 #define F_CLRSTATS V_CLRSTATS(1U)
30316 #define S_INCRSTATS 1
30317 #define V_INCRSTATS(x) ((x) << S_INCRSTATS)
30318 #define F_INCRSTATS V_INCRSTATS(1U)
30320 #define S_ENTESTMODEWR 0
30321 #define V_ENTESTMODEWR(x) ((x) << S_ENTESTMODEWR)
30322 #define F_ENTESTMODEWR V_ENTESTMODEWR(1U)
30324 #define A_XGMAC_PORT_XGM_MDIO_CTRL 0x1284
30326 #define S_FRAMETYPE 30
30327 #define M_FRAMETYPE 0x3U
30328 #define V_FRAMETYPE(x) ((x) << S_FRAMETYPE)
30329 #define G_FRAMETYPE(x) (((x) >> S_FRAMETYPE) & M_FRAMETYPE)
30331 #define S_OPERATION 28
30332 #define M_OPERATION 0x3U
30333 #define V_OPERATION(x) ((x) << S_OPERATION)
30334 #define G_OPERATION(x) (((x) >> S_OPERATION) & M_OPERATION)
30336 #define S_PORTADDR 23
30337 #define M_PORTADDR 0x1fU
30338 #define V_PORTADDR(x) ((x) << S_PORTADDR)
30339 #define G_PORTADDR(x) (((x) >> S_PORTADDR) & M_PORTADDR)
30341 #define S_DEVADDR 18
30342 #define M_DEVADDR 0x1fU
30343 #define V_DEVADDR(x) ((x) << S_DEVADDR)
30344 #define G_DEVADDR(x) (((x) >> S_DEVADDR) & M_DEVADDR)
30347 #define M_RESRV 0x3U
30348 #define V_RESRV(x) ((x) << S_RESRV)
30349 #define G_RESRV(x) (((x) >> S_RESRV) & M_RESRV)
30352 #define M_DATA 0xffffU
30353 #define V_DATA(x) ((x) << S_DATA)
30354 #define G_DATA(x) (((x) >> S_DATA) & M_DATA)
30356 #define A_XGMAC_PORT_XGM_MODULE_ID 0x12fc
30358 #define S_MODULEID 16
30359 #define M_MODULEID 0xffffU
30360 #define V_MODULEID(x) ((x) << S_MODULEID)
30361 #define G_MODULEID(x) (((x) >> S_MODULEID) & M_MODULEID)
30363 #define S_MODULEREV 0
30364 #define M_MODULEREV 0xffffU
30365 #define V_MODULEREV(x) ((x) << S_MODULEREV)
30366 #define G_MODULEREV(x) (((x) >> S_MODULEREV) & M_MODULEREV)
30368 #define A_XGMAC_PORT_XGM_STAT_TX_BYTE_LOW 0x1300
30369 #define A_XGMAC_PORT_XGM_STAT_TX_BYTE_HIGH 0x1304
30371 #define S_TXBYTES_HIGH 0
30372 #define M_TXBYTES_HIGH 0x1fffU
30373 #define V_TXBYTES_HIGH(x) ((x) << S_TXBYTES_HIGH)
30374 #define G_TXBYTES_HIGH(x) (((x) >> S_TXBYTES_HIGH) & M_TXBYTES_HIGH)
30376 #define A_XGMAC_PORT_XGM_STAT_TX_FRAME_LOW 0x1308
30377 #define A_XGMAC_PORT_XGM_STAT_TX_FRAME_HIGH 0x130c
30379 #define S_TXFRAMES_HIGH 0
30380 #define M_TXFRAMES_HIGH 0xfU
30381 #define V_TXFRAMES_HIGH(x) ((x) << S_TXFRAMES_HIGH)
30382 #define G_TXFRAMES_HIGH(x) (((x) >> S_TXFRAMES_HIGH) & M_TXFRAMES_HIGH)
30384 #define A_XGMAC_PORT_XGM_STAT_TX_BCAST 0x1310
30385 #define A_XGMAC_PORT_XGM_STAT_TX_MCAST 0x1314
30386 #define A_XGMAC_PORT_XGM_STAT_TX_PAUSE 0x1318
30387 #define A_XGMAC_PORT_XGM_STAT_TX_64B_FRAMES 0x131c
30388 #define A_XGMAC_PORT_XGM_STAT_TX_65_127B_FRAMES 0x1320
30389 #define A_XGMAC_PORT_XGM_STAT_TX_128_255B_FRAMES 0x1324
30390 #define A_XGMAC_PORT_XGM_STAT_TX_256_511B_FRAMES 0x1328
30391 #define A_XGMAC_PORT_XGM_STAT_TX_512_1023B_FRAMES 0x132c
30392 #define A_XGMAC_PORT_XGM_STAT_TX_1024_1518B_FRAMES 0x1330
30393 #define A_XGMAC_PORT_XGM_STAT_TX_1519_MAXB_FRAMES 0x1334
30394 #define A_XGMAC_PORT_XGM_STAT_TX_ERR_FRAMES 0x1338
30395 #define A_XGMAC_PORT_XGM_STAT_RX_BYTES_LOW 0x133c
30396 #define A_XGMAC_PORT_XGM_STAT_RX_BYTES_HIGH 0x1340
30398 #define S_RXBYTES_HIGH 0
30399 #define M_RXBYTES_HIGH 0x1fffU
30400 #define V_RXBYTES_HIGH(x) ((x) << S_RXBYTES_HIGH)
30401 #define G_RXBYTES_HIGH(x) (((x) >> S_RXBYTES_HIGH) & M_RXBYTES_HIGH)
30403 #define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_LOW 0x1344
30404 #define A_XGMAC_PORT_XGM_STAT_RX_FRAMES_HIGH 0x1348
30406 #define S_RXFRAMES_HIGH 0
30407 #define M_RXFRAMES_HIGH 0xfU
30408 #define V_RXFRAMES_HIGH(x) ((x) << S_RXFRAMES_HIGH)
30409 #define G_RXFRAMES_HIGH(x) (((x) >> S_RXFRAMES_HIGH) & M_RXFRAMES_HIGH)
30411 #define A_XGMAC_PORT_XGM_STAT_RX_BCAST_FRAMES 0x134c
30412 #define A_XGMAC_PORT_XGM_STAT_RX_MCAST_FRAMES 0x1350
30413 #define A_XGMAC_PORT_XGM_STAT_RX_PAUSE_FRAMES 0x1354
30415 #define S_RXPAUSEFRAMES 0
30416 #define M_RXPAUSEFRAMES 0xffffU
30417 #define V_RXPAUSEFRAMES(x) ((x) << S_RXPAUSEFRAMES)
30418 #define G_RXPAUSEFRAMES(x) (((x) >> S_RXPAUSEFRAMES) & M_RXPAUSEFRAMES)
30420 #define A_XGMAC_PORT_XGM_STAT_RX_64B_FRAMES 0x1358
30421 #define A_XGMAC_PORT_XGM_STAT_RX_65_127B_FRAMES 0x135c
30422 #define A_XGMAC_PORT_XGM_STAT_RX_128_255B_FRAMES 0x1360
30423 #define A_XGMAC_PORT_XGM_STAT_RX_256_511B_FRAMES 0x1364
30424 #define A_XGMAC_PORT_XGM_STAT_RX_512_1023B_FRAMES 0x1368
30425 #define A_XGMAC_PORT_XGM_STAT_RX_1024_1518B_FRAMES 0x136c
30426 #define A_XGMAC_PORT_XGM_STAT_RX_1519_MAXB_FRAMES 0x1370
30427 #define A_XGMAC_PORT_XGM_STAT_RX_SHORT_FRAMES 0x1374
30429 #define S_RXSHORTFRAMES 0
30430 #define M_RXSHORTFRAMES 0xffffU
30431 #define V_RXSHORTFRAMES(x) ((x) << S_RXSHORTFRAMES)
30432 #define G_RXSHORTFRAMES(x) (((x) >> S_RXSHORTFRAMES) & M_RXSHORTFRAMES)
30434 #define A_XGMAC_PORT_XGM_STAT_RX_OVERSIZE_FRAMES 0x1378
30436 #define S_RXOVERSIZEFRAMES 0
30437 #define M_RXOVERSIZEFRAMES 0xffffU
30438 #define V_RXOVERSIZEFRAMES(x) ((x) << S_RXOVERSIZEFRAMES)
30439 #define G_RXOVERSIZEFRAMES(x) (((x) >> S_RXOVERSIZEFRAMES) & M_RXOVERSIZEFRAMES)
30441 #define A_XGMAC_PORT_XGM_STAT_RX_JABBER_FRAMES 0x137c
30443 #define S_RXJABBERFRAMES 0
30444 #define M_RXJABBERFRAMES 0xffffU
30445 #define V_RXJABBERFRAMES(x) ((x) << S_RXJABBERFRAMES)
30446 #define G_RXJABBERFRAMES(x) (((x) >> S_RXJABBERFRAMES) & M_RXJABBERFRAMES)
30448 #define A_XGMAC_PORT_XGM_STAT_RX_CRC_ERR_FRAMES 0x1380
30450 #define S_RXCRCERRFRAMES 0
30451 #define M_RXCRCERRFRAMES 0xffffU
30452 #define V_RXCRCERRFRAMES(x) ((x) << S_RXCRCERRFRAMES)
30453 #define G_RXCRCERRFRAMES(x) (((x) >> S_RXCRCERRFRAMES) & M_RXCRCERRFRAMES)
30455 #define A_XGMAC_PORT_XGM_STAT_RX_LENGTH_ERR_FRAMES 0x1384
30457 #define S_RXLENGTHERRFRAMES 0
30458 #define M_RXLENGTHERRFRAMES 0xffffU
30459 #define V_RXLENGTHERRFRAMES(x) ((x) << S_RXLENGTHERRFRAMES)
30460 #define G_RXLENGTHERRFRAMES(x) (((x) >> S_RXLENGTHERRFRAMES) & M_RXLENGTHERRFRAMES)
30462 #define A_XGMAC_PORT_XGM_STAT_RX_SYM_CODE_ERR_FRAMES 0x1388
30464 #define S_RXSYMCODEERRFRAMES 0
30465 #define M_RXSYMCODEERRFRAMES 0xffffU
30466 #define V_RXSYMCODEERRFRAMES(x) ((x) << S_RXSYMCODEERRFRAMES)
30467 #define G_RXSYMCODEERRFRAMES(x) (((x) >> S_RXSYMCODEERRFRAMES) & M_RXSYMCODEERRFRAMES)
30469 #define A_XGMAC_PORT_XAUI_CTRL 0x1400
30471 #define S_POLARITY_INV_RX 8
30472 #define M_POLARITY_INV_RX 0xfU
30473 #define V_POLARITY_INV_RX(x) ((x) << S_POLARITY_INV_RX)
30474 #define G_POLARITY_INV_RX(x) (((x) >> S_POLARITY_INV_RX) & M_POLARITY_INV_RX)
30476 #define S_POLARITY_INV_TX 4
30477 #define M_POLARITY_INV_TX 0xfU
30478 #define V_POLARITY_INV_TX(x) ((x) << S_POLARITY_INV_TX)
30479 #define G_POLARITY_INV_TX(x) (((x) >> S_POLARITY_INV_TX) & M_POLARITY_INV_TX)
30481 #define S_TEST_SEL 2
30482 #define M_TEST_SEL 0x3U
30483 #define V_TEST_SEL(x) ((x) << S_TEST_SEL)
30484 #define G_TEST_SEL(x) (((x) >> S_TEST_SEL) & M_TEST_SEL)
30486 #define S_TEST_EN 0
30487 #define V_TEST_EN(x) ((x) << S_TEST_EN)
30488 #define F_TEST_EN V_TEST_EN(1U)
30490 #define A_XGMAC_PORT_XAUI_STATUS 0x1404
30492 #define S_DECODE_ERROR 12
30493 #define M_DECODE_ERROR 0xffU
30494 #define V_DECODE_ERROR(x) ((x) << S_DECODE_ERROR)
30495 #define G_DECODE_ERROR(x) (((x) >> S_DECODE_ERROR) & M_DECODE_ERROR)
30497 #define S_LANE3_CTC_STATUS 11
30498 #define V_LANE3_CTC_STATUS(x) ((x) << S_LANE3_CTC_STATUS)
30499 #define F_LANE3_CTC_STATUS V_LANE3_CTC_STATUS(1U)
30501 #define S_LANE2_CTC_STATUS 10
30502 #define V_LANE2_CTC_STATUS(x) ((x) << S_LANE2_CTC_STATUS)
30503 #define F_LANE2_CTC_STATUS V_LANE2_CTC_STATUS(1U)
30505 #define S_LANE1_CTC_STATUS 9
30506 #define V_LANE1_CTC_STATUS(x) ((x) << S_LANE1_CTC_STATUS)
30507 #define F_LANE1_CTC_STATUS V_LANE1_CTC_STATUS(1U)
30509 #define S_LANE0_CTC_STATUS 8
30510 #define V_LANE0_CTC_STATUS(x) ((x) << S_LANE0_CTC_STATUS)
30511 #define F_LANE0_CTC_STATUS V_LANE0_CTC_STATUS(1U)
30513 #define S_ALIGN_STATUS 4
30514 #define V_ALIGN_STATUS(x) ((x) << S_ALIGN_STATUS)
30515 #define F_ALIGN_STATUS V_ALIGN_STATUS(1U)
30517 #define S_LANE3_SYNC_STATUS 3
30518 #define V_LANE3_SYNC_STATUS(x) ((x) << S_LANE3_SYNC_STATUS)
30519 #define F_LANE3_SYNC_STATUS V_LANE3_SYNC_STATUS(1U)
30521 #define S_LANE2_SYNC_STATUS 2
30522 #define V_LANE2_SYNC_STATUS(x) ((x) << S_LANE2_SYNC_STATUS)
30523 #define F_LANE2_SYNC_STATUS V_LANE2_SYNC_STATUS(1U)
30525 #define S_LANE1_SYNC_STATUS 1
30526 #define V_LANE1_SYNC_STATUS(x) ((x) << S_LANE1_SYNC_STATUS)
30527 #define F_LANE1_SYNC_STATUS V_LANE1_SYNC_STATUS(1U)
30529 #define S_LANE0_SYNC_STATUS 0
30530 #define V_LANE0_SYNC_STATUS(x) ((x) << S_LANE0_SYNC_STATUS)
30531 #define F_LANE0_SYNC_STATUS V_LANE0_SYNC_STATUS(1U)
30533 #define A_XGMAC_PORT_PCSR_CTRL 0x1500
30535 #define S_RX_CLK_SPEED 7
30536 #define V_RX_CLK_SPEED(x) ((x) << S_RX_CLK_SPEED)
30537 #define F_RX_CLK_SPEED V_RX_CLK_SPEED(1U)
30539 #define S_SCRBYPASS 6
30540 #define V_SCRBYPASS(x) ((x) << S_SCRBYPASS)
30541 #define F_SCRBYPASS V_SCRBYPASS(1U)
30543 #define S_FECERRINDEN 5
30544 #define V_FECERRINDEN(x) ((x) << S_FECERRINDEN)
30545 #define F_FECERRINDEN V_FECERRINDEN(1U)
30548 #define V_FECEN(x) ((x) << S_FECEN)
30549 #define F_FECEN V_FECEN(1U)
30551 #define S_TESTSEL 2
30552 #define M_TESTSEL 0x3U
30553 #define V_TESTSEL(x) ((x) << S_TESTSEL)
30554 #define G_TESTSEL(x) (((x) >> S_TESTSEL) & M_TESTSEL)
30556 #define S_SCRLOOPEN 1
30557 #define V_SCRLOOPEN(x) ((x) << S_SCRLOOPEN)
30558 #define F_SCRLOOPEN V_SCRLOOPEN(1U)
30560 #define S_XGMIILOOPEN 0
30561 #define V_XGMIILOOPEN(x) ((x) << S_XGMIILOOPEN)
30562 #define F_XGMIILOOPEN V_XGMIILOOPEN(1U)
30564 #define A_XGMAC_PORT_PCSR_TXTEST_CTRL 0x1510
30566 #define S_TX_PRBS9_EN 4
30567 #define V_TX_PRBS9_EN(x) ((x) << S_TX_PRBS9_EN)
30568 #define F_TX_PRBS9_EN V_TX_PRBS9_EN(1U)
30570 #define S_TX_PRBS31_EN 3
30571 #define V_TX_PRBS31_EN(x) ((x) << S_TX_PRBS31_EN)
30572 #define F_TX_PRBS31_EN V_TX_PRBS31_EN(1U)
30574 #define S_TX_TST_DAT_SEL 2
30575 #define V_TX_TST_DAT_SEL(x) ((x) << S_TX_TST_DAT_SEL)
30576 #define F_TX_TST_DAT_SEL V_TX_TST_DAT_SEL(1U)
30578 #define S_TX_TST_SEL 1
30579 #define V_TX_TST_SEL(x) ((x) << S_TX_TST_SEL)
30580 #define F_TX_TST_SEL V_TX_TST_SEL(1U)
30582 #define S_TX_TST_EN 0
30583 #define V_TX_TST_EN(x) ((x) << S_TX_TST_EN)
30584 #define F_TX_TST_EN V_TX_TST_EN(1U)
30586 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_LOWER 0x1514
30587 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDA_UPPER 0x1518
30589 #define S_SEEDA_UPPER 0
30590 #define M_SEEDA_UPPER 0x3ffffffU
30591 #define V_SEEDA_UPPER(x) ((x) << S_SEEDA_UPPER)
30592 #define G_SEEDA_UPPER(x) (((x) >> S_SEEDA_UPPER) & M_SEEDA_UPPER)
30594 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_LOWER 0x152c
30595 #define A_XGMAC_PORT_PCSR_TXTEST_SEEDB_UPPER 0x1530
30597 #define S_SEEDB_UPPER 0
30598 #define M_SEEDB_UPPER 0x3ffffffU
30599 #define V_SEEDB_UPPER(x) ((x) << S_SEEDB_UPPER)
30600 #define G_SEEDB_UPPER(x) (((x) >> S_SEEDB_UPPER) & M_SEEDB_UPPER)
30602 #define A_XGMAC_PORT_PCSR_RXTEST_CTRL 0x153c
30604 #define S_TPTER_CNT_RST 7
30605 #define V_TPTER_CNT_RST(x) ((x) << S_TPTER_CNT_RST)
30606 #define F_TPTER_CNT_RST V_TPTER_CNT_RST(1U)
30608 #define S_TEST_CNT_125US 6
30609 #define V_TEST_CNT_125US(x) ((x) << S_TEST_CNT_125US)
30610 #define F_TEST_CNT_125US V_TEST_CNT_125US(1U)
30612 #define S_TEST_CNT_PRE 5
30613 #define V_TEST_CNT_PRE(x) ((x) << S_TEST_CNT_PRE)
30614 #define F_TEST_CNT_PRE V_TEST_CNT_PRE(1U)
30616 #define S_BER_CNT_RST 4
30617 #define V_BER_CNT_RST(x) ((x) << S_BER_CNT_RST)
30618 #define F_BER_CNT_RST V_BER_CNT_RST(1U)
30620 #define S_ERR_BLK_CNT_RST 3
30621 #define V_ERR_BLK_CNT_RST(x) ((x) << S_ERR_BLK_CNT_RST)
30622 #define F_ERR_BLK_CNT_RST V_ERR_BLK_CNT_RST(1U)
30624 #define S_RX_PRBS31_EN 2
30625 #define V_RX_PRBS31_EN(x) ((x) << S_RX_PRBS31_EN)
30626 #define F_RX_PRBS31_EN V_RX_PRBS31_EN(1U)
30628 #define S_RX_TST_DAT_SEL 1
30629 #define V_RX_TST_DAT_SEL(x) ((x) << S_RX_TST_DAT_SEL)
30630 #define F_RX_TST_DAT_SEL V_RX_TST_DAT_SEL(1U)
30632 #define S_RX_TST_EN 0
30633 #define V_RX_TST_EN(x) ((x) << S_RX_TST_EN)
30634 #define F_RX_TST_EN V_RX_TST_EN(1U)
30636 #define A_XGMAC_PORT_PCSR_STATUS 0x1550
30638 #define S_ERR_BLK_CNT 16
30639 #define M_ERR_BLK_CNT 0xffU
30640 #define V_ERR_BLK_CNT(x) ((x) << S_ERR_BLK_CNT)
30641 #define G_ERR_BLK_CNT(x) (((x) >> S_ERR_BLK_CNT) & M_ERR_BLK_CNT)
30643 #define S_BER_COUNT 8
30644 #define M_BER_COUNT 0x3fU
30645 #define V_BER_COUNT(x) ((x) << S_BER_COUNT)
30646 #define G_BER_COUNT(x) (((x) >> S_BER_COUNT) & M_BER_COUNT)
30649 #define V_HI_BER(x) ((x) << S_HI_BER)
30650 #define F_HI_BER V_HI_BER(1U)
30652 #define S_RX_FAULT 1
30653 #define V_RX_FAULT(x) ((x) << S_RX_FAULT)
30654 #define F_RX_FAULT V_RX_FAULT(1U)
30656 #define S_TX_FAULT 0
30657 #define V_TX_FAULT(x) ((x) << S_TX_FAULT)
30658 #define F_TX_FAULT V_TX_FAULT(1U)
30660 #define A_XGMAC_PORT_PCSR_TEST_STATUS 0x1554
30662 #define S_TPT_ERR_CNT 0
30663 #define M_TPT_ERR_CNT 0xffffU
30664 #define V_TPT_ERR_CNT(x) ((x) << S_TPT_ERR_CNT)
30665 #define G_TPT_ERR_CNT(x) (((x) >> S_TPT_ERR_CNT) & M_TPT_ERR_CNT)
30667 #define A_XGMAC_PORT_AN_CONTROL 0x1600
30669 #define S_SOFT_RESET 15
30670 #define V_SOFT_RESET(x) ((x) << S_SOFT_RESET)
30671 #define F_SOFT_RESET V_SOFT_RESET(1U)
30673 #define S_AN_ENABLE 12
30674 #define V_AN_ENABLE(x) ((x) << S_AN_ENABLE)
30675 #define F_AN_ENABLE V_AN_ENABLE(1U)
30677 #define S_RESTART_AN 9
30678 #define V_RESTART_AN(x) ((x) << S_RESTART_AN)
30679 #define F_RESTART_AN V_RESTART_AN(1U)
30681 #define A_XGMAC_PORT_AN_STATUS 0x1604
30683 #define S_NONCER_MATCH 31
30684 #define V_NONCER_MATCH(x) ((x) << S_NONCER_MATCH)
30685 #define F_NONCER_MATCH V_NONCER_MATCH(1U)
30687 #define S_PARALLEL_DET_FAULT 9
30688 #define V_PARALLEL_DET_FAULT(x) ((x) << S_PARALLEL_DET_FAULT)
30689 #define F_PARALLEL_DET_FAULT V_PARALLEL_DET_FAULT(1U)
30691 #define S_PAGE_RECEIVED 6
30692 #define V_PAGE_RECEIVED(x) ((x) << S_PAGE_RECEIVED)
30693 #define F_PAGE_RECEIVED V_PAGE_RECEIVED(1U)
30695 #define S_AN_COMPLETE 5
30696 #define V_AN_COMPLETE(x) ((x) << S_AN_COMPLETE)
30697 #define F_AN_COMPLETE V_AN_COMPLETE(1U)
30699 #define S_STAT_REMFAULT 4
30700 #define V_STAT_REMFAULT(x) ((x) << S_STAT_REMFAULT)
30701 #define F_STAT_REMFAULT V_STAT_REMFAULT(1U)
30703 #define S_AN_ABILITY 3
30704 #define V_AN_ABILITY(x) ((x) << S_AN_ABILITY)
30705 #define F_AN_ABILITY V_AN_ABILITY(1U)
30707 #define S_LINK_STATUS 2
30708 #define V_LINK_STATUS(x) ((x) << S_LINK_STATUS)
30709 #define F_LINK_STATUS V_LINK_STATUS(1U)
30711 #define S_PARTNER_AN_ABILITY 0
30712 #define V_PARTNER_AN_ABILITY(x) ((x) << S_PARTNER_AN_ABILITY)
30713 #define F_PARTNER_AN_ABILITY V_PARTNER_AN_ABILITY(1U)
30715 #define A_XGMAC_PORT_AN_ADVERTISEMENT 0x1608
30717 #define S_FEC_ENABLE 31
30718 #define V_FEC_ENABLE(x) ((x) << S_FEC_ENABLE)
30719 #define F_FEC_ENABLE V_FEC_ENABLE(1U)
30721 #define S_FEC_ABILITY 30
30722 #define V_FEC_ABILITY(x) ((x) << S_FEC_ABILITY)
30723 #define F_FEC_ABILITY V_FEC_ABILITY(1U)
30725 #define S_10GBASE_KR_CAPABLE 23
30726 #define V_10GBASE_KR_CAPABLE(x) ((x) << S_10GBASE_KR_CAPABLE)
30727 #define F_10GBASE_KR_CAPABLE V_10GBASE_KR_CAPABLE(1U)
30729 #define S_10GBASE_KX4_CAPABLE 22
30730 #define V_10GBASE_KX4_CAPABLE(x) ((x) << S_10GBASE_KX4_CAPABLE)
30731 #define F_10GBASE_KX4_CAPABLE V_10GBASE_KX4_CAPABLE(1U)
30733 #define S_1000BASE_KX_CAPABLE 21
30734 #define V_1000BASE_KX_CAPABLE(x) ((x) << S_1000BASE_KX_CAPABLE)
30735 #define F_1000BASE_KX_CAPABLE V_1000BASE_KX_CAPABLE(1U)
30737 #define S_TRANSMITTED_NONCE 16
30738 #define M_TRANSMITTED_NONCE 0x1fU
30739 #define V_TRANSMITTED_NONCE(x) ((x) << S_TRANSMITTED_NONCE)
30740 #define G_TRANSMITTED_NONCE(x) (((x) >> S_TRANSMITTED_NONCE) & M_TRANSMITTED_NONCE)
30743 #define V_NP(x) ((x) << S_NP)
30744 #define F_NP V_NP(1U)
30747 #define V_ACK(x) ((x) << S_ACK)
30748 #define F_ACK V_ACK(1U)
30750 #define S_REMOTE_FAULT 13
30751 #define V_REMOTE_FAULT(x) ((x) << S_REMOTE_FAULT)
30752 #define F_REMOTE_FAULT V_REMOTE_FAULT(1U)
30754 #define S_ASM_DIR 11
30755 #define V_ASM_DIR(x) ((x) << S_ASM_DIR)
30756 #define F_ASM_DIR V_ASM_DIR(1U)
30759 #define V_PAUSE(x) ((x) << S_PAUSE)
30760 #define F_PAUSE V_PAUSE(1U)
30762 #define S_ECHOED_NONCE 5
30763 #define M_ECHOED_NONCE 0x1fU
30764 #define V_ECHOED_NONCE(x) ((x) << S_ECHOED_NONCE)
30765 #define G_ECHOED_NONCE(x) (((x) >> S_ECHOED_NONCE) & M_ECHOED_NONCE)
30767 #define A_XGMAC_PORT_AN_LINK_PARTNER_ABILITY 0x160c
30769 #define S_SELECTOR_FIELD 0
30770 #define M_SELECTOR_FIELD 0x1fU
30771 #define V_SELECTOR_FIELD(x) ((x) << S_SELECTOR_FIELD)
30772 #define G_SELECTOR_FIELD(x) (((x) >> S_SELECTOR_FIELD) & M_SELECTOR_FIELD)
30774 #define A_XGMAC_PORT_AN_NP_LOWER_TRANSMIT 0x1610
30776 #define S_NP_INFO 16
30777 #define M_NP_INFO 0xffffU
30778 #define V_NP_INFO(x) ((x) << S_NP_INFO)
30779 #define G_NP_INFO(x) (((x) >> S_NP_INFO) & M_NP_INFO)
30781 #define S_NP_INDICATION 15
30782 #define V_NP_INDICATION(x) ((x) << S_NP_INDICATION)
30783 #define F_NP_INDICATION V_NP_INDICATION(1U)
30785 #define S_MESSAGE_PAGE 13
30786 #define V_MESSAGE_PAGE(x) ((x) << S_MESSAGE_PAGE)
30787 #define F_MESSAGE_PAGE V_MESSAGE_PAGE(1U)
30790 #define V_ACK_2(x) ((x) << S_ACK_2)
30791 #define F_ACK_2 V_ACK_2(1U)
30793 #define S_TOGGLE 11
30794 #define V_TOGGLE(x) ((x) << S_TOGGLE)
30795 #define F_TOGGLE V_TOGGLE(1U)
30797 #define A_XGMAC_PORT_AN_NP_UPPER_TRANSMIT 0x1614
30799 #define S_NP_INFO_HI 0
30800 #define M_NP_INFO_HI 0xffffU
30801 #define V_NP_INFO_HI(x) ((x) << S_NP_INFO_HI)
30802 #define G_NP_INFO_HI(x) (((x) >> S_NP_INFO_HI) & M_NP_INFO_HI)
30804 #define A_XGMAC_PORT_AN_LP_NP_LOWER 0x1618
30805 #define A_XGMAC_PORT_AN_LP_NP_UPPER 0x161c
30806 #define A_XGMAC_PORT_AN_BACKPLANE_ETHERNET_STATUS 0x1624
30808 #define S_TX_PAUSE_OKAY 6
30809 #define V_TX_PAUSE_OKAY(x) ((x) << S_TX_PAUSE_OKAY)
30810 #define F_TX_PAUSE_OKAY V_TX_PAUSE_OKAY(1U)
30812 #define S_RX_PAUSE_OKAY 5
30813 #define V_RX_PAUSE_OKAY(x) ((x) << S_RX_PAUSE_OKAY)
30814 #define F_RX_PAUSE_OKAY V_RX_PAUSE_OKAY(1U)
30816 #define S_10GBASE_KR_FEC_NEG 4
30817 #define V_10GBASE_KR_FEC_NEG(x) ((x) << S_10GBASE_KR_FEC_NEG)
30818 #define F_10GBASE_KR_FEC_NEG V_10GBASE_KR_FEC_NEG(1U)
30820 #define S_10GBASE_KR_NEG 3
30821 #define V_10GBASE_KR_NEG(x) ((x) << S_10GBASE_KR_NEG)
30822 #define F_10GBASE_KR_NEG V_10GBASE_KR_NEG(1U)
30824 #define S_10GBASE_KX4_NEG 2
30825 #define V_10GBASE_KX4_NEG(x) ((x) << S_10GBASE_KX4_NEG)
30826 #define F_10GBASE_KX4_NEG V_10GBASE_KX4_NEG(1U)
30828 #define S_1000BASE_KX_NEG 1
30829 #define V_1000BASE_KX_NEG(x) ((x) << S_1000BASE_KX_NEG)
30830 #define F_1000BASE_KX_NEG V_1000BASE_KX_NEG(1U)
30832 #define S_BP_AN_ABILITY 0
30833 #define V_BP_AN_ABILITY(x) ((x) << S_BP_AN_ABILITY)
30834 #define F_BP_AN_ABILITY V_BP_AN_ABILITY(1U)
30836 #define A_XGMAC_PORT_AN_TX_NONCE_CONTROL 0x1628
30838 #define S_BYPASS_LFSR 15
30839 #define V_BYPASS_LFSR(x) ((x) << S_BYPASS_LFSR)
30840 #define F_BYPASS_LFSR V_BYPASS_LFSR(1U)
30842 #define S_LFSR_INIT 0
30843 #define M_LFSR_INIT 0x7fffU
30844 #define V_LFSR_INIT(x) ((x) << S_LFSR_INIT)
30845 #define G_LFSR_INIT(x) (((x) >> S_LFSR_INIT) & M_LFSR_INIT)
30847 #define A_XGMAC_PORT_AN_INTERRUPT_STATUS 0x162c
30849 #define S_NP_FROM_LP 3
30850 #define V_NP_FROM_LP(x) ((x) << S_NP_FROM_LP)
30851 #define F_NP_FROM_LP V_NP_FROM_LP(1U)
30853 #define S_PARALLELDETFAULTINT 2
30854 #define V_PARALLELDETFAULTINT(x) ((x) << S_PARALLELDETFAULTINT)
30855 #define F_PARALLELDETFAULTINT V_PARALLELDETFAULTINT(1U)
30857 #define S_BP_FROM_LP 1
30858 #define V_BP_FROM_LP(x) ((x) << S_BP_FROM_LP)
30859 #define F_BP_FROM_LP V_BP_FROM_LP(1U)
30861 #define S_PCS_AN_COMPLETE 0
30862 #define V_PCS_AN_COMPLETE(x) ((x) << S_PCS_AN_COMPLETE)
30863 #define F_PCS_AN_COMPLETE V_PCS_AN_COMPLETE(1U)
30865 #define A_XGMAC_PORT_AN_GENERIC_TIMER_TIMEOUT 0x1630
30867 #define S_GENERIC_TIMEOUT 0
30868 #define M_GENERIC_TIMEOUT 0x7fffffU
30869 #define V_GENERIC_TIMEOUT(x) ((x) << S_GENERIC_TIMEOUT)
30870 #define G_GENERIC_TIMEOUT(x) (((x) >> S_GENERIC_TIMEOUT) & M_GENERIC_TIMEOUT)
30872 #define A_XGMAC_PORT_AN_BREAK_LINK_TIMEOUT 0x1634
30874 #define S_BREAK_LINK_TIMEOUT 0
30875 #define M_BREAK_LINK_TIMEOUT 0xffffffU
30876 #define V_BREAK_LINK_TIMEOUT(x) ((x) << S_BREAK_LINK_TIMEOUT)
30877 #define G_BREAK_LINK_TIMEOUT(x) (((x) >> S_BREAK_LINK_TIMEOUT) & M_BREAK_LINK_TIMEOUT)
30879 #define A_XGMAC_PORT_AN_MODULE_ID 0x163c
30881 #define S_MODULE_ID 16
30882 #define M_MODULE_ID 0xffffU
30883 #define V_MODULE_ID(x) ((x) << S_MODULE_ID)
30884 #define G_MODULE_ID(x) (((x) >> S_MODULE_ID) & M_MODULE_ID)
30886 #define S_MODULE_REVISION 0
30887 #define M_MODULE_REVISION 0xffffU
30888 #define V_MODULE_REVISION(x) ((x) << S_MODULE_REVISION)
30889 #define G_MODULE_REVISION(x) (((x) >> S_MODULE_REVISION) & M_MODULE_REVISION)
30891 #define A_XGMAC_PORT_AE_RX_COEF_REQ 0x1700
30893 #define S_RXREQ_CPRE 13
30894 #define V_RXREQ_CPRE(x) ((x) << S_RXREQ_CPRE)
30895 #define F_RXREQ_CPRE V_RXREQ_CPRE(1U)
30897 #define S_RXREQ_CINIT 12
30898 #define V_RXREQ_CINIT(x) ((x) << S_RXREQ_CINIT)
30899 #define F_RXREQ_CINIT V_RXREQ_CINIT(1U)
30901 #define S_RXREQ_C0 4
30902 #define M_RXREQ_C0 0x3U
30903 #define V_RXREQ_C0(x) ((x) << S_RXREQ_C0)
30904 #define G_RXREQ_C0(x) (((x) >> S_RXREQ_C0) & M_RXREQ_C0)
30906 #define S_RXREQ_C1 2
30907 #define M_RXREQ_C1 0x3U
30908 #define V_RXREQ_C1(x) ((x) << S_RXREQ_C1)
30909 #define G_RXREQ_C1(x) (((x) >> S_RXREQ_C1) & M_RXREQ_C1)
30911 #define S_RXREQ_C2 0
30912 #define M_RXREQ_C2 0x3U
30913 #define V_RXREQ_C2(x) ((x) << S_RXREQ_C2)
30914 #define G_RXREQ_C2(x) (((x) >> S_RXREQ_C2) & M_RXREQ_C2)
30916 #define A_XGMAC_PORT_AE_RX_COEF_STAT 0x1704
30918 #define S_RXSTAT_RDY 15
30919 #define V_RXSTAT_RDY(x) ((x) << S_RXSTAT_RDY)
30920 #define F_RXSTAT_RDY V_RXSTAT_RDY(1U)
30922 #define S_RXSTAT_C0 4
30923 #define M_RXSTAT_C0 0x3U
30924 #define V_RXSTAT_C0(x) ((x) << S_RXSTAT_C0)
30925 #define G_RXSTAT_C0(x) (((x) >> S_RXSTAT_C0) & M_RXSTAT_C0)
30927 #define S_RXSTAT_C1 2
30928 #define M_RXSTAT_C1 0x3U
30929 #define V_RXSTAT_C1(x) ((x) << S_RXSTAT_C1)
30930 #define G_RXSTAT_C1(x) (((x) >> S_RXSTAT_C1) & M_RXSTAT_C1)
30932 #define S_RXSTAT_C2 0
30933 #define M_RXSTAT_C2 0x3U
30934 #define V_RXSTAT_C2(x) ((x) << S_RXSTAT_C2)
30935 #define G_RXSTAT_C2(x) (((x) >> S_RXSTAT_C2) & M_RXSTAT_C2)
30937 #define A_XGMAC_PORT_AE_TX_COEF_REQ 0x1708
30939 #define S_TXREQ_CPRE 13
30940 #define V_TXREQ_CPRE(x) ((x) << S_TXREQ_CPRE)
30941 #define F_TXREQ_CPRE V_TXREQ_CPRE(1U)
30943 #define S_TXREQ_CINIT 12
30944 #define V_TXREQ_CINIT(x) ((x) << S_TXREQ_CINIT)
30945 #define F_TXREQ_CINIT V_TXREQ_CINIT(1U)
30947 #define S_TXREQ_C0 4
30948 #define M_TXREQ_C0 0x3U
30949 #define V_TXREQ_C0(x) ((x) << S_TXREQ_C0)
30950 #define G_TXREQ_C0(x) (((x) >> S_TXREQ_C0) & M_TXREQ_C0)
30952 #define S_TXREQ_C1 2
30953 #define M_TXREQ_C1 0x3U
30954 #define V_TXREQ_C1(x) ((x) << S_TXREQ_C1)
30955 #define G_TXREQ_C1(x) (((x) >> S_TXREQ_C1) & M_TXREQ_C1)
30957 #define S_TXREQ_C2 0
30958 #define M_TXREQ_C2 0x3U
30959 #define V_TXREQ_C2(x) ((x) << S_TXREQ_C2)
30960 #define G_TXREQ_C2(x) (((x) >> S_TXREQ_C2) & M_TXREQ_C2)
30962 #define A_XGMAC_PORT_AE_TX_COEF_STAT 0x170c
30964 #define S_TXSTAT_RDY 15
30965 #define V_TXSTAT_RDY(x) ((x) << S_TXSTAT_RDY)
30966 #define F_TXSTAT_RDY V_TXSTAT_RDY(1U)
30968 #define S_TXSTAT_C0 4
30969 #define M_TXSTAT_C0 0x3U
30970 #define V_TXSTAT_C0(x) ((x) << S_TXSTAT_C0)
30971 #define G_TXSTAT_C0(x) (((x) >> S_TXSTAT_C0) & M_TXSTAT_C0)
30973 #define S_TXSTAT_C1 2
30974 #define M_TXSTAT_C1 0x3U
30975 #define V_TXSTAT_C1(x) ((x) << S_TXSTAT_C1)
30976 #define G_TXSTAT_C1(x) (((x) >> S_TXSTAT_C1) & M_TXSTAT_C1)
30978 #define S_TXSTAT_C2 0
30979 #define M_TXSTAT_C2 0x3U
30980 #define V_TXSTAT_C2(x) ((x) << S_TXSTAT_C2)
30981 #define G_TXSTAT_C2(x) (((x) >> S_TXSTAT_C2) & M_TXSTAT_C2)
30983 #define A_XGMAC_PORT_AE_REG_MODE 0x1710
30985 #define S_MAN_DEC 4
30986 #define M_MAN_DEC 0x3U
30987 #define V_MAN_DEC(x) ((x) << S_MAN_DEC)
30988 #define G_MAN_DEC(x) (((x) >> S_MAN_DEC) & M_MAN_DEC)
30990 #define S_MANUAL_RDY 3
30991 #define V_MANUAL_RDY(x) ((x) << S_MANUAL_RDY)
30992 #define F_MANUAL_RDY V_MANUAL_RDY(1U)
30994 #define S_MWT_DISABLE 2
30995 #define V_MWT_DISABLE(x) ((x) << S_MWT_DISABLE)
30996 #define F_MWT_DISABLE V_MWT_DISABLE(1U)
30998 #define S_MDIO_OVR 1
30999 #define V_MDIO_OVR(x) ((x) << S_MDIO_OVR)
31000 #define F_MDIO_OVR V_MDIO_OVR(1U)
31002 #define S_STICKY_MODE 0
31003 #define V_STICKY_MODE(x) ((x) << S_STICKY_MODE)
31004 #define F_STICKY_MODE V_STICKY_MODE(1U)
31006 #define A_XGMAC_PORT_AE_PRBS_CTL 0x1714
31008 #define S_PRBS_CHK_ERRCNT 8
31009 #define M_PRBS_CHK_ERRCNT 0xffU
31010 #define V_PRBS_CHK_ERRCNT(x) ((x) << S_PRBS_CHK_ERRCNT)
31011 #define G_PRBS_CHK_ERRCNT(x) (((x) >> S_PRBS_CHK_ERRCNT) & M_PRBS_CHK_ERRCNT)
31013 #define S_PRBS_SYNCCNT 5
31014 #define M_PRBS_SYNCCNT 0x7U
31015 #define V_PRBS_SYNCCNT(x) ((x) << S_PRBS_SYNCCNT)
31016 #define G_PRBS_SYNCCNT(x) (((x) >> S_PRBS_SYNCCNT) & M_PRBS_SYNCCNT)
31018 #define S_PRBS_CHK_SYNC 4
31019 #define V_PRBS_CHK_SYNC(x) ((x) << S_PRBS_CHK_SYNC)
31020 #define F_PRBS_CHK_SYNC V_PRBS_CHK_SYNC(1U)
31022 #define S_PRBS_CHK_RST 3
31023 #define V_PRBS_CHK_RST(x) ((x) << S_PRBS_CHK_RST)
31024 #define F_PRBS_CHK_RST V_PRBS_CHK_RST(1U)
31026 #define S_PRBS_CHK_OFF 2
31027 #define V_PRBS_CHK_OFF(x) ((x) << S_PRBS_CHK_OFF)
31028 #define F_PRBS_CHK_OFF V_PRBS_CHK_OFF(1U)
31030 #define S_PRBS_GEN_FRCERR 1
31031 #define V_PRBS_GEN_FRCERR(x) ((x) << S_PRBS_GEN_FRCERR)
31032 #define F_PRBS_GEN_FRCERR V_PRBS_GEN_FRCERR(1U)
31034 #define S_PRBS_GEN_OFF 0
31035 #define V_PRBS_GEN_OFF(x) ((x) << S_PRBS_GEN_OFF)
31036 #define F_PRBS_GEN_OFF V_PRBS_GEN_OFF(1U)
31038 #define A_XGMAC_PORT_AE_FSM_CTL 0x1718
31040 #define S_FSM_TR_LCL 14
31041 #define V_FSM_TR_LCL(x) ((x) << S_FSM_TR_LCL)
31042 #define F_FSM_TR_LCL V_FSM_TR_LCL(1U)
31044 #define S_FSM_GDMRK 11
31045 #define M_FSM_GDMRK 0x7U
31046 #define V_FSM_GDMRK(x) ((x) << S_FSM_GDMRK)
31047 #define G_FSM_GDMRK(x) (((x) >> S_FSM_GDMRK) & M_FSM_GDMRK)
31049 #define S_FSM_BADMRK 8
31050 #define M_FSM_BADMRK 0x7U
31051 #define V_FSM_BADMRK(x) ((x) << S_FSM_BADMRK)
31052 #define G_FSM_BADMRK(x) (((x) >> S_FSM_BADMRK) & M_FSM_BADMRK)
31054 #define S_FSM_TR_FAIL 7
31055 #define V_FSM_TR_FAIL(x) ((x) << S_FSM_TR_FAIL)
31056 #define F_FSM_TR_FAIL V_FSM_TR_FAIL(1U)
31058 #define S_FSM_TR_ACT 6
31059 #define V_FSM_TR_ACT(x) ((x) << S_FSM_TR_ACT)
31060 #define F_FSM_TR_ACT V_FSM_TR_ACT(1U)
31062 #define S_FSM_FRM_LCK 5
31063 #define V_FSM_FRM_LCK(x) ((x) << S_FSM_FRM_LCK)
31064 #define F_FSM_FRM_LCK V_FSM_FRM_LCK(1U)
31066 #define S_FSM_TR_COMP 4
31067 #define V_FSM_TR_COMP(x) ((x) << S_FSM_TR_COMP)
31068 #define F_FSM_TR_COMP V_FSM_TR_COMP(1U)
31070 #define S_MC_RX_RDY 3
31071 #define V_MC_RX_RDY(x) ((x) << S_MC_RX_RDY)
31072 #define F_MC_RX_RDY V_MC_RX_RDY(1U)
31074 #define S_FSM_CU_DIS 2
31075 #define V_FSM_CU_DIS(x) ((x) << S_FSM_CU_DIS)
31076 #define F_FSM_CU_DIS V_FSM_CU_DIS(1U)
31078 #define S_FSM_TR_RST 1
31079 #define V_FSM_TR_RST(x) ((x) << S_FSM_TR_RST)
31080 #define F_FSM_TR_RST V_FSM_TR_RST(1U)
31082 #define S_FSM_TR_EN 0
31083 #define V_FSM_TR_EN(x) ((x) << S_FSM_TR_EN)
31084 #define F_FSM_TR_EN V_FSM_TR_EN(1U)
31086 #define A_XGMAC_PORT_AE_FSM_STATE 0x171c
31088 #define S_CC2FSM_STATE 13
31089 #define M_CC2FSM_STATE 0x7U
31090 #define V_CC2FSM_STATE(x) ((x) << S_CC2FSM_STATE)
31091 #define G_CC2FSM_STATE(x) (((x) >> S_CC2FSM_STATE) & M_CC2FSM_STATE)
31093 #define S_CC1FSM_STATE 10
31094 #define M_CC1FSM_STATE 0x7U
31095 #define V_CC1FSM_STATE(x) ((x) << S_CC1FSM_STATE)
31096 #define G_CC1FSM_STATE(x) (((x) >> S_CC1FSM_STATE) & M_CC1FSM_STATE)
31098 #define S_CC0FSM_STATE 7
31099 #define M_CC0FSM_STATE 0x7U
31100 #define V_CC0FSM_STATE(x) ((x) << S_CC0FSM_STATE)
31101 #define G_CC0FSM_STATE(x) (((x) >> S_CC0FSM_STATE) & M_CC0FSM_STATE)
31103 #define S_FLFSM_STATE 4
31104 #define M_FLFSM_STATE 0x7U
31105 #define V_FLFSM_STATE(x) ((x) << S_FLFSM_STATE)
31106 #define G_FLFSM_STATE(x) (((x) >> S_FLFSM_STATE) & M_FLFSM_STATE)
31108 #define S_TFSM_STATE 0
31109 #define M_TFSM_STATE 0x7U
31110 #define V_TFSM_STATE(x) ((x) << S_TFSM_STATE)
31111 #define G_TFSM_STATE(x) (((x) >> S_TFSM_STATE) & M_TFSM_STATE)
31113 #define A_XGMAC_PORT_AE_TX_DIS 0x1780
31115 #define S_PMD_TX_DIS 0
31116 #define V_PMD_TX_DIS(x) ((x) << S_PMD_TX_DIS)
31117 #define F_PMD_TX_DIS V_PMD_TX_DIS(1U)
31119 #define A_XGMAC_PORT_AE_KR_CTRL 0x1784
31121 #define S_TRAINING_ENABLE 1
31122 #define V_TRAINING_ENABLE(x) ((x) << S_TRAINING_ENABLE)
31123 #define F_TRAINING_ENABLE V_TRAINING_ENABLE(1U)
31125 #define S_RESTART_TRAINING 0
31126 #define V_RESTART_TRAINING(x) ((x) << S_RESTART_TRAINING)
31127 #define F_RESTART_TRAINING V_RESTART_TRAINING(1U)
31129 #define A_XGMAC_PORT_AE_RX_SIGDET 0x1788
31131 #define S_PMD_SIGDET 0
31132 #define V_PMD_SIGDET(x) ((x) << S_PMD_SIGDET)
31133 #define F_PMD_SIGDET V_PMD_SIGDET(1U)
31135 #define A_XGMAC_PORT_AE_KR_STATUS 0x178c
31137 #define S_TRAINING_FAILURE 3
31138 #define V_TRAINING_FAILURE(x) ((x) << S_TRAINING_FAILURE)
31139 #define F_TRAINING_FAILURE V_TRAINING_FAILURE(1U)
31141 #define S_TRAINING 2
31142 #define V_TRAINING(x) ((x) << S_TRAINING)
31143 #define F_TRAINING V_TRAINING(1U)
31145 #define S_FRAME_LOCK 1
31146 #define V_FRAME_LOCK(x) ((x) << S_FRAME_LOCK)
31147 #define F_FRAME_LOCK V_FRAME_LOCK(1U)
31149 #define S_RX_TRAINED 0
31150 #define V_RX_TRAINED(x) ((x) << S_RX_TRAINED)
31151 #define F_RX_TRAINED V_RX_TRAINED(1U)
31153 #define A_XGMAC_PORT_HSS_TXA_MODE_CFG 0x1800
31156 #define M_BWSEL 0x3U
31157 #define V_BWSEL(x) ((x) << S_BWSEL)
31158 #define G_BWSEL(x) (((x) >> S_BWSEL) & M_BWSEL)
31161 #define M_RTSEL 0x3U
31162 #define V_RTSEL(x) ((x) << S_RTSEL)
31163 #define G_RTSEL(x) (((x) >> S_RTSEL) & M_RTSEL)
31165 #define A_XGMAC_PORT_HSS_TXA_TEST_CTRL 0x1804
31168 #define V_TWDP(x) ((x) << S_TWDP)
31169 #define F_TWDP V_TWDP(1U)
31172 #define V_TPGRST(x) ((x) << S_TPGRST)
31173 #define F_TPGRST V_TPGRST(1U)
31176 #define V_TPGEN(x) ((x) << S_TPGEN)
31177 #define F_TPGEN V_TPGEN(1U)
31180 #define M_TPSEL 0x7U
31181 #define V_TPSEL(x) ((x) << S_TPSEL)
31182 #define G_TPSEL(x) (((x) >> S_TPSEL) & M_TPSEL)
31184 #define A_XGMAC_PORT_HSS_TXA_COEFF_CTRL 0x1808
31186 #define S_AEINVPOL 6
31187 #define V_AEINVPOL(x) ((x) << S_AEINVPOL)
31188 #define F_AEINVPOL V_AEINVPOL(1U)
31190 #define S_AESOURCE 5
31191 #define V_AESOURCE(x) ((x) << S_AESOURCE)
31192 #define F_AESOURCE V_AESOURCE(1U)
31195 #define V_EQMODE(x) ((x) << S_EQMODE)
31196 #define F_EQMODE V_EQMODE(1U)
31199 #define V_OCOEF(x) ((x) << S_OCOEF)
31200 #define F_OCOEF V_OCOEF(1U)
31202 #define S_COEFRST 2
31203 #define V_COEFRST(x) ((x) << S_COEFRST)
31204 #define F_COEFRST V_COEFRST(1U)
31207 #define V_SPEN(x) ((x) << S_SPEN)
31208 #define F_SPEN V_SPEN(1U)
31211 #define V_ALOAD(x) ((x) << S_ALOAD)
31212 #define F_ALOAD V_ALOAD(1U)
31214 #define A_XGMAC_PORT_HSS_TXA_DRIVER_MODE 0x180c
31216 #define S_DRVOFFT 5
31217 #define V_DRVOFFT(x) ((x) << S_DRVOFFT)
31218 #define F_DRVOFFT V_DRVOFFT(1U)
31221 #define M_SLEW 0x7U
31222 #define V_SLEW(x) ((x) << S_SLEW)
31223 #define G_SLEW(x) (((x) >> S_SLEW) & M_SLEW)
31227 #define V_FFE(x) ((x) << S_FFE)
31228 #define G_FFE(x) (((x) >> S_FFE) & M_FFE)
31230 #define A_XGMAC_PORT_HSS_TXA_DRIVER_OVR_CTRL 0x1810
31233 #define V_VLINC(x) ((x) << S_VLINC)
31234 #define F_VLINC V_VLINC(1U)
31237 #define V_VLDEC(x) ((x) << S_VLDEC)
31238 #define F_VLDEC V_VLDEC(1U)
31241 #define V_LOPWR(x) ((x) << S_LOPWR)
31242 #define F_LOPWR V_LOPWR(1U)
31245 #define V_TDMEN(x) ((x) << S_TDMEN)
31246 #define F_TDMEN V_TDMEN(1U)
31249 #define V_DCCEN(x) ((x) << S_DCCEN)
31250 #define F_DCCEN V_DCCEN(1U)
31253 #define V_VHSEL(x) ((x) << S_VHSEL)
31254 #define F_VHSEL V_VHSEL(1U)
31257 #define M_IDAC 0x3U
31258 #define V_IDAC(x) ((x) << S_IDAC)
31259 #define G_IDAC(x) (((x) >> S_IDAC) & M_IDAC)
31261 #define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_STANDBY_TIMER 0x1814
31264 #define M_STBY 0xffffU
31265 #define V_STBY(x) ((x) << S_STBY)
31266 #define G_STBY(x) (((x) >> S_STBY) & M_STBY)
31268 #define A_XGMAC_PORT_HSS_TXA_TDM_BIASGEN_PWRON_TIMER 0x1818
31271 #define M_PON 0xffffU
31272 #define V_PON(x) ((x) << S_PON)
31273 #define G_PON(x) (((x) >> S_PON) & M_PON)
31275 #define A_XGMAC_PORT_HSS_TXA_TAP0_COEFF 0x1820
31278 #define M_NXTT0 0xfU
31279 #define V_NXTT0(x) ((x) << S_NXTT0)
31280 #define G_NXTT0(x) (((x) >> S_NXTT0) & M_NXTT0)
31282 #define A_XGMAC_PORT_HSS_TXA_TAP1_COEFF 0x1824
31285 #define M_NXTT1 0x3fU
31286 #define V_NXTT1(x) ((x) << S_NXTT1)
31287 #define G_NXTT1(x) (((x) >> S_NXTT1) & M_NXTT1)
31289 #define A_XGMAC_PORT_HSS_TXA_TAP2_COEFF 0x1828
31292 #define M_NXTT2 0x1fU
31293 #define V_NXTT2(x) ((x) << S_NXTT2)
31294 #define G_NXTT2(x) (((x) >> S_NXTT2) & M_NXTT2)
31296 #define A_XGMAC_PORT_HSS_TXA_PWR 0x1830
31299 #define M_TXPWR 0x7fU
31300 #define V_TXPWR(x) ((x) << S_TXPWR)
31301 #define G_TXPWR(x) (((x) >> S_TXPWR) & M_TXPWR)
31303 #define A_XGMAC_PORT_HSS_TXA_POLARITY 0x1834
31306 #define M_TXPOL 0x7U
31307 #define V_TXPOL(x) ((x) << S_TXPOL)
31308 #define G_TXPOL(x) (((x) >> S_TXPOL) & M_TXPOL)
31311 #define M_NTXPOL 0x7U
31312 #define V_NTXPOL(x) ((x) << S_NTXPOL)
31313 #define G_NTXPOL(x) (((x) >> S_NTXPOL) & M_NTXPOL)
31315 #define A_XGMAC_PORT_HSS_TXA_8023AP_AE_CMD 0x1838
31317 #define S_CXPRESET 13
31318 #define V_CXPRESET(x) ((x) << S_CXPRESET)
31319 #define F_CXPRESET V_CXPRESET(1U)
31321 #define S_CXINIT 12
31322 #define V_CXINIT(x) ((x) << S_CXINIT)
31323 #define F_CXINIT V_CXINIT(1U)
31326 #define M_C2UPDT 0x3U
31327 #define V_C2UPDT(x) ((x) << S_C2UPDT)
31328 #define G_C2UPDT(x) (((x) >> S_C2UPDT) & M_C2UPDT)
31331 #define M_C1UPDT 0x3U
31332 #define V_C1UPDT(x) ((x) << S_C1UPDT)
31333 #define G_C1UPDT(x) (((x) >> S_C1UPDT) & M_C1UPDT)
31336 #define M_C0UPDT 0x3U
31337 #define V_C0UPDT(x) ((x) << S_C0UPDT)
31338 #define G_C0UPDT(x) (((x) >> S_C0UPDT) & M_C0UPDT)
31340 #define A_XGMAC_PORT_HSS_TXA_8023AP_AE_STATUS 0x183c
31343 #define M_C2STAT 0x3U
31344 #define V_C2STAT(x) ((x) << S_C2STAT)
31345 #define G_C2STAT(x) (((x) >> S_C2STAT) & M_C2STAT)
31348 #define M_C1STAT 0x3U
31349 #define V_C1STAT(x) ((x) << S_C1STAT)
31350 #define G_C1STAT(x) (((x) >> S_C1STAT) & M_C1STAT)
31353 #define M_C0STAT 0x3U
31354 #define V_C0STAT(x) ((x) << S_C0STAT)
31355 #define G_C0STAT(x) (((x) >> S_C0STAT) & M_C0STAT)
31357 #define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_OVR 0x1840
31360 #define M_NIDAC0 0x1fU
31361 #define V_NIDAC0(x) ((x) << S_NIDAC0)
31362 #define G_NIDAC0(x) (((x) >> S_NIDAC0) & M_NIDAC0)
31364 #define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_OVR 0x1844
31367 #define M_NIDAC1 0x7fU
31368 #define V_NIDAC1(x) ((x) << S_NIDAC1)
31369 #define G_NIDAC1(x) (((x) >> S_NIDAC1) & M_NIDAC1)
31371 #define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_OVR 0x1848
31374 #define M_NIDAC2 0x3fU
31375 #define V_NIDAC2(x) ((x) << S_NIDAC2)
31376 #define G_NIDAC2(x) (((x) >> S_NIDAC2) & M_NIDAC2)
31378 #define A_XGMAC_PORT_HSS_TXA_PWR_DAC_OVR 0x1850
31381 #define V_OPEN(x) ((x) << S_OPEN)
31382 #define F_OPEN V_OPEN(1U)
31385 #define M_OPVAL 0x1fU
31386 #define V_OPVAL(x) ((x) << S_OPVAL)
31387 #define G_OPVAL(x) (((x) >> S_OPVAL) & M_OPVAL)
31389 #define A_XGMAC_PORT_HSS_TXA_PWR_DAC 0x1854
31392 #define M_PDAC 0x1fU
31393 #define V_PDAC(x) ((x) << S_PDAC)
31394 #define G_PDAC(x) (((x) >> S_PDAC) & M_PDAC)
31396 #define A_XGMAC_PORT_HSS_TXA_TAP0_IDAC_APP 0x1860
31399 #define M_AIDAC0 0x1fU
31400 #define V_AIDAC0(x) ((x) << S_AIDAC0)
31401 #define G_AIDAC0(x) (((x) >> S_AIDAC0) & M_AIDAC0)
31403 #define A_XGMAC_PORT_HSS_TXA_TAP1_IDAC_APP 0x1864
31406 #define M_AIDAC1 0x1fU
31407 #define V_AIDAC1(x) ((x) << S_AIDAC1)
31408 #define G_AIDAC1(x) (((x) >> S_AIDAC1) & M_AIDAC1)
31410 #define A_XGMAC_PORT_HSS_TXA_TAP2_IDAC_APP 0x1868
31412 #define S_TXA_AIDAC2 0
31413 #define M_TXA_AIDAC2 0x1fU
31414 #define V_TXA_AIDAC2(x) ((x) << S_TXA_AIDAC2)
31415 #define G_TXA_AIDAC2(x) (((x) >> S_TXA_AIDAC2) & M_TXA_AIDAC2)
31417 #define A_XGMAC_PORT_HSS_TXA_SEG_DIS_APP 0x1870
31420 #define M_CURSD 0x7fU
31421 #define V_CURSD(x) ((x) << S_CURSD)
31422 #define G_CURSD(x) (((x) >> S_CURSD) & M_CURSD)
31424 #define A_XGMAC_PORT_HSS_TXA_EXT_ADDR_DATA 0x1878
31427 #define M_XDATA 0xffffU
31428 #define V_XDATA(x) ((x) << S_XDATA)
31429 #define G_XDATA(x) (((x) >> S_XDATA) & M_XDATA)
31431 #define A_XGMAC_PORT_HSS_TXA_EXT_ADDR 0x187c
31433 #define S_EXTADDR 1
31434 #define M_EXTADDR 0x1fU
31435 #define V_EXTADDR(x) ((x) << S_EXTADDR)
31436 #define G_EXTADDR(x) (((x) >> S_EXTADDR) & M_EXTADDR)
31439 #define V_XWR(x) ((x) << S_XWR)
31440 #define F_XWR V_XWR(1U)
31442 #define A_XGMAC_PORT_HSS_TXB_MODE_CFG 0x1880
31443 #define A_XGMAC_PORT_HSS_TXB_TEST_CTRL 0x1884
31444 #define A_XGMAC_PORT_HSS_TXB_COEFF_CTRL 0x1888
31445 #define A_XGMAC_PORT_HSS_TXB_DRIVER_MODE 0x188c
31446 #define A_XGMAC_PORT_HSS_TXB_DRIVER_OVR_CTRL 0x1890
31447 #define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_STANDBY_TIMER 0x1894
31448 #define A_XGMAC_PORT_HSS_TXB_TDM_BIASGEN_PWRON_TIMER 0x1898
31449 #define A_XGMAC_PORT_HSS_TXB_TAP0_COEFF 0x18a0
31450 #define A_XGMAC_PORT_HSS_TXB_TAP1_COEFF 0x18a4
31451 #define A_XGMAC_PORT_HSS_TXB_TAP2_COEFF 0x18a8
31452 #define A_XGMAC_PORT_HSS_TXB_PWR 0x18b0
31453 #define A_XGMAC_PORT_HSS_TXB_POLARITY 0x18b4
31454 #define A_XGMAC_PORT_HSS_TXB_8023AP_AE_CMD 0x18b8
31455 #define A_XGMAC_PORT_HSS_TXB_8023AP_AE_STATUS 0x18bc
31456 #define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_OVR 0x18c0
31457 #define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_OVR 0x18c4
31458 #define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_OVR 0x18c8
31459 #define A_XGMAC_PORT_HSS_TXB_PWR_DAC_OVR 0x18d0
31460 #define A_XGMAC_PORT_HSS_TXB_PWR_DAC 0x18d4
31461 #define A_XGMAC_PORT_HSS_TXB_TAP0_IDAC_APP 0x18e0
31462 #define A_XGMAC_PORT_HSS_TXB_TAP1_IDAC_APP 0x18e4
31463 #define A_XGMAC_PORT_HSS_TXB_TAP2_IDAC_APP 0x18e8
31466 #define M_AIDAC2 0x3fU
31467 #define V_AIDAC2(x) ((x) << S_AIDAC2)
31468 #define G_AIDAC2(x) (((x) >> S_AIDAC2) & M_AIDAC2)
31470 #define A_XGMAC_PORT_HSS_TXB_SEG_DIS_APP 0x18f0
31471 #define A_XGMAC_PORT_HSS_TXB_EXT_ADDR_DATA 0x18f8
31472 #define A_XGMAC_PORT_HSS_TXB_EXT_ADDR 0x18fc
31475 #define M_XADDR 0xfU
31476 #define V_XADDR(x) ((x) << S_XADDR)
31477 #define G_XADDR(x) (((x) >> S_XADDR) & M_XADDR)
31479 #define A_XGMAC_PORT_HSS_RXA_CFG_MODE 0x1900
31482 #define V_BW810(x) ((x) << S_BW810)
31483 #define F_BW810 V_BW810(1U)
31486 #define V_AUXCLK(x) ((x) << S_AUXCLK)
31487 #define F_AUXCLK V_AUXCLK(1U)
31490 #define M_DMSEL 0x7U
31491 #define V_DMSEL(x) ((x) << S_DMSEL)
31492 #define G_DMSEL(x) (((x) >> S_DMSEL) & M_DMSEL)
31494 #define A_XGMAC_PORT_HSS_RXA_TEST_CTRL 0x1904
31496 #define S_RCLKEN 15
31497 #define V_RCLKEN(x) ((x) << S_RCLKEN)
31498 #define F_RCLKEN V_RCLKEN(1U)
31501 #define M_RRATE 0x3U
31502 #define V_RRATE(x) ((x) << S_RRATE)
31503 #define G_RRATE(x) (((x) >> S_RRATE) & M_RRATE)
31505 #define S_LBFRCERROR 10
31506 #define V_LBFRCERROR(x) ((x) << S_LBFRCERROR)
31507 #define F_LBFRCERROR V_LBFRCERROR(1U)
31509 #define S_LBERROR 9
31510 #define V_LBERROR(x) ((x) << S_LBERROR)
31511 #define F_LBERROR V_LBERROR(1U)
31514 #define V_LBSYNC(x) ((x) << S_LBSYNC)
31515 #define F_LBSYNC V_LBSYNC(1U)
31517 #define S_FDWRAPCLK 7
31518 #define V_FDWRAPCLK(x) ((x) << S_FDWRAPCLK)
31519 #define F_FDWRAPCLK V_FDWRAPCLK(1U)
31522 #define V_FDWRAP(x) ((x) << S_FDWRAP)
31523 #define F_FDWRAP V_FDWRAP(1U)
31526 #define V_PRST(x) ((x) << S_PRST)
31527 #define F_PRST V_PRST(1U)
31530 #define V_PCHKEN(x) ((x) << S_PCHKEN)
31531 #define F_PCHKEN V_PCHKEN(1U)
31533 #define S_PRBSSEL 0
31534 #define M_PRBSSEL 0x7U
31535 #define V_PRBSSEL(x) ((x) << S_PRBSSEL)
31536 #define G_PRBSSEL(x) (((x) >> S_PRBSSEL) & M_PRBSSEL)
31538 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_CTRL 0x1908
31540 #define S_FTHROT 12
31541 #define M_FTHROT 0xfU
31542 #define V_FTHROT(x) ((x) << S_FTHROT)
31543 #define G_FTHROT(x) (((x) >> S_FTHROT) & M_FTHROT)
31545 #define S_RTHROT 11
31546 #define V_RTHROT(x) ((x) << S_RTHROT)
31547 #define F_RTHROT V_RTHROT(1U)
31549 #define S_FILTCTL 7
31550 #define M_FILTCTL 0xfU
31551 #define V_FILTCTL(x) ((x) << S_FILTCTL)
31552 #define G_FILTCTL(x) (((x) >> S_FILTCTL) & M_FILTCTL)
31555 #define M_RSRVO 0x3U
31556 #define V_RSRVO(x) ((x) << S_RSRVO)
31557 #define G_RSRVO(x) (((x) >> S_RSRVO) & M_RSRVO)
31560 #define V_EXTEL(x) ((x) << S_EXTEL)
31561 #define F_EXTEL V_EXTEL(1U)
31563 #define S_RSTONSTUCK 3
31564 #define V_RSTONSTUCK(x) ((x) << S_RSTONSTUCK)
31565 #define F_RSTONSTUCK V_RSTONSTUCK(1U)
31567 #define S_FREEZEFW 2
31568 #define V_FREEZEFW(x) ((x) << S_FREEZEFW)
31569 #define F_FREEZEFW V_FREEZEFW(1U)
31571 #define S_RESETFW 1
31572 #define V_RESETFW(x) ((x) << S_RESETFW)
31573 #define F_RESETFW V_RESETFW(1U)
31575 #define S_SSCENABLE 0
31576 #define V_SSCENABLE(x) ((x) << S_SSCENABLE)
31577 #define F_SSCENABLE V_SSCENABLE(1U)
31579 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_OFFSET_CTRL 0x190c
31582 #define V_RSNP(x) ((x) << S_RSNP)
31583 #define F_RSNP V_RSNP(1U)
31586 #define V_TSOEN(x) ((x) << S_TSOEN)
31587 #define F_TSOEN V_TSOEN(1U)
31590 #define V_OFFEN(x) ((x) << S_OFFEN)
31591 #define F_OFFEN V_OFFEN(1U)
31594 #define M_TMSCAL 0x3U
31595 #define V_TMSCAL(x) ((x) << S_TMSCAL)
31596 #define G_TMSCAL(x) (((x) >> S_TMSCAL) & M_TMSCAL)
31599 #define V_APADJ(x) ((x) << S_APADJ)
31600 #define F_APADJ V_APADJ(1U)
31603 #define V_RSEL(x) ((x) << S_RSEL)
31604 #define F_RSEL V_RSEL(1U)
31607 #define M_PHOFFS 0x1fU
31608 #define V_PHOFFS(x) ((x) << S_PHOFFS)
31609 #define G_PHOFFS(x) (((x) >> S_PHOFFS) & M_PHOFFS)
31611 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION1 0x1910
31614 #define M_ROT0A 0x3fU
31615 #define V_ROT0A(x) ((x) << S_ROT0A)
31616 #define G_ROT0A(x) (((x) >> S_ROT0A) & M_ROT0A)
31618 #define S_RTSEL_SNAPSHOT 0
31619 #define M_RTSEL_SNAPSHOT 0x3fU
31620 #define V_RTSEL_SNAPSHOT(x) ((x) << S_RTSEL_SNAPSHOT)
31621 #define G_RTSEL_SNAPSHOT(x) (((x) >> S_RTSEL_SNAPSHOT) & M_RTSEL_SNAPSHOT)
31623 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_POSITION2 0x1914
31626 #define M_ROT90 0x3fU
31627 #define V_ROT90(x) ((x) << S_ROT90)
31628 #define G_ROT90(x) (((x) >> S_ROT90) & M_ROT90)
31630 #define A_XGMAC_PORT_HSS_RXA_PH_ROTATOR_STATIC_PH_OFFSET 0x1918
31632 #define S_RCALER 15
31633 #define V_RCALER(x) ((x) << S_RCALER)
31634 #define F_RCALER V_RCALER(1U)
31636 #define S_RAOOFF 10
31637 #define M_RAOOFF 0x1fU
31638 #define V_RAOOFF(x) ((x) << S_RAOOFF)
31639 #define G_RAOOFF(x) (((x) >> S_RAOOFF) & M_RAOOFF)
31642 #define M_RAEOFF 0x1fU
31643 #define V_RAEOFF(x) ((x) << S_RAEOFF)
31644 #define G_RAEOFF(x) (((x) >> S_RAEOFF) & M_RAEOFF)
31647 #define M_RDOFF 0x1fU
31648 #define V_RDOFF(x) ((x) << S_RDOFF)
31649 #define G_RDOFF(x) (((x) >> S_RDOFF) & M_RDOFF)
31651 #define A_XGMAC_PORT_HSS_RXA_SIGDET_CTRL 0x191c
31653 #define S_SIGNSD 13
31654 #define M_SIGNSD 0x3U
31655 #define V_SIGNSD(x) ((x) << S_SIGNSD)
31656 #define G_SIGNSD(x) (((x) >> S_SIGNSD) & M_SIGNSD)
31659 #define M_DACSD 0x1fU
31660 #define V_DACSD(x) ((x) << S_DACSD)
31661 #define G_DACSD(x) (((x) >> S_DACSD) & M_DACSD)
31664 #define V_SDPDN(x) ((x) << S_SDPDN)
31665 #define F_SDPDN V_SDPDN(1U)
31668 #define V_SIGDET(x) ((x) << S_SIGDET)
31669 #define F_SIGDET V_SIGDET(1U)
31672 #define M_SDLVL 0x1fU
31673 #define V_SDLVL(x) ((x) << S_SDLVL)
31674 #define G_SDLVL(x) (((x) >> S_SDLVL) & M_SDLVL)
31676 #define A_XGMAC_PORT_HSS_RXA_DFE_CTRL 0x1920
31678 #define S_REQCMP 15
31679 #define V_REQCMP(x) ((x) << S_REQCMP)
31680 #define F_REQCMP V_REQCMP(1U)
31682 #define S_DFEREQ 14
31683 #define V_DFEREQ(x) ((x) << S_DFEREQ)
31684 #define F_DFEREQ V_DFEREQ(1U)
31687 #define V_SPCEN(x) ((x) << S_SPCEN)
31688 #define F_SPCEN V_SPCEN(1U)
31690 #define S_GATEEN 12
31691 #define V_GATEEN(x) ((x) << S_GATEEN)
31692 #define F_GATEEN V_GATEEN(1U)
31695 #define M_SPIFMT 0x7U
31696 #define V_SPIFMT(x) ((x) << S_SPIFMT)
31697 #define G_SPIFMT(x) (((x) >> S_SPIFMT) & M_SPIFMT)
31700 #define M_DFEPWR 0x7U
31701 #define V_DFEPWR(x) ((x) << S_DFEPWR)
31702 #define G_DFEPWR(x) (((x) >> S_DFEPWR) & M_DFEPWR)
31705 #define V_STNDBY(x) ((x) << S_STNDBY)
31706 #define F_STNDBY V_STNDBY(1U)
31709 #define V_FRCH(x) ((x) << S_FRCH)
31710 #define F_FRCH V_FRCH(1U)
31713 #define V_NONRND(x) ((x) << S_NONRND)
31714 #define F_NONRND V_NONRND(1U)
31717 #define V_NONRNF(x) ((x) << S_NONRNF)
31718 #define F_NONRNF V_NONRNF(1U)
31721 #define V_FSTLCK(x) ((x) << S_FSTLCK)
31722 #define F_FSTLCK V_FSTLCK(1U)
31725 #define V_DFERST(x) ((x) << S_DFERST)
31726 #define F_DFERST V_DFERST(1U)
31728 #define A_XGMAC_PORT_HSS_RXA_DFE_DATA_EDGE_SAMPLE 0x1924
31731 #define M_ESAMP 0xffU
31732 #define V_ESAMP(x) ((x) << S_ESAMP)
31733 #define G_ESAMP(x) (((x) >> S_ESAMP) & M_ESAMP)
31736 #define M_DSAMP 0xffU
31737 #define V_DSAMP(x) ((x) << S_DSAMP)
31738 #define G_DSAMP(x) (((x) >> S_DSAMP) & M_DSAMP)
31740 #define A_XGMAC_PORT_HSS_RXA_DFE_AMP_SAMPLE 0x1928
31743 #define M_SMODE 0xfU
31744 #define V_SMODE(x) ((x) << S_SMODE)
31745 #define G_SMODE(x) (((x) >> S_SMODE) & M_SMODE)
31748 #define V_ADCORR(x) ((x) << S_ADCORR)
31749 #define F_ADCORR V_ADCORR(1U)
31751 #define S_TRAINEN 6
31752 #define V_TRAINEN(x) ((x) << S_TRAINEN)
31753 #define F_TRAINEN V_TRAINEN(1U)
31756 #define M_ASAMPQ 0x7U
31757 #define V_ASAMPQ(x) ((x) << S_ASAMPQ)
31758 #define G_ASAMPQ(x) (((x) >> S_ASAMPQ) & M_ASAMPQ)
31761 #define M_ASAMP 0x7U
31762 #define V_ASAMP(x) ((x) << S_ASAMP)
31763 #define G_ASAMP(x) (((x) >> S_ASAMP) & M_ASAMP)
31765 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL1 0x192c
31768 #define M_POLE 0x3U
31769 #define V_POLE(x) ((x) << S_POLE)
31770 #define G_POLE(x) (((x) >> S_POLE) & M_POLE)
31773 #define M_PEAK 0x7U
31774 #define V_PEAK(x) ((x) << S_PEAK)
31775 #define G_PEAK(x) (((x) >> S_PEAK) & M_PEAK)
31778 #define M_VOFFSN 0x3U
31779 #define V_VOFFSN(x) ((x) << S_VOFFSN)
31780 #define G_VOFFSN(x) (((x) >> S_VOFFSN) & M_VOFFSN)
31783 #define M_VOFFA 0x3fU
31784 #define V_VOFFA(x) ((x) << S_VOFFA)
31785 #define G_VOFFA(x) (((x) >> S_VOFFA) & M_VOFFA)
31787 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL2 0x1930
31789 #define S_SHORTV 10
31790 #define V_SHORTV(x) ((x) << S_SHORTV)
31791 #define F_SHORTV V_SHORTV(1U)
31794 #define M_VGAIN 0xfU
31795 #define V_VGAIN(x) ((x) << S_VGAIN)
31796 #define G_VGAIN(x) (((x) >> S_VGAIN) & M_VGAIN)
31798 #define A_XGMAC_PORT_HSS_RXA_VGA_CTRL3 0x1934
31801 #define V_HBND1(x) ((x) << S_HBND1)
31802 #define F_HBND1 V_HBND1(1U)
31805 #define V_HBND0(x) ((x) << S_HBND0)
31806 #define F_HBND0 V_HBND0(1U)
31809 #define V_VLCKD(x) ((x) << S_VLCKD)
31810 #define F_VLCKD V_VLCKD(1U)
31813 #define V_VLCKDF(x) ((x) << S_VLCKDF)
31814 #define F_VLCKDF V_VLCKDF(1U)
31817 #define M_AMAXT 0x7fU
31818 #define V_AMAXT(x) ((x) << S_AMAXT)
31819 #define G_AMAXT(x) (((x) >> S_AMAXT) & M_AMAXT)
31821 #define A_XGMAC_PORT_HSS_RXA_DFE_D00_D01_OFFSET 0x1938
31824 #define M_D01SN 0x3U
31825 #define V_D01SN(x) ((x) << S_D01SN)
31826 #define G_D01SN(x) (((x) >> S_D01SN) & M_D01SN)
31829 #define M_D01AMP 0x1fU
31830 #define V_D01AMP(x) ((x) << S_D01AMP)
31831 #define G_D01AMP(x) (((x) >> S_D01AMP) & M_D01AMP)
31834 #define M_D00SN 0x3U
31835 #define V_D00SN(x) ((x) << S_D00SN)
31836 #define G_D00SN(x) (((x) >> S_D00SN) & M_D00SN)
31839 #define M_D00AMP 0x1fU
31840 #define V_D00AMP(x) ((x) << S_D00AMP)
31841 #define G_D00AMP(x) (((x) >> S_D00AMP) & M_D00AMP)
31843 #define A_XGMAC_PORT_HSS_RXA_DFE_D10_D11_OFFSET 0x193c
31846 #define M_D11SN 0x3U
31847 #define V_D11SN(x) ((x) << S_D11SN)
31848 #define G_D11SN(x) (((x) >> S_D11SN) & M_D11SN)
31851 #define M_D11AMP 0x1fU
31852 #define V_D11AMP(x) ((x) << S_D11AMP)
31853 #define G_D11AMP(x) (((x) >> S_D11AMP) & M_D11AMP)
31856 #define M_D10SN 0x3U
31857 #define V_D10SN(x) ((x) << S_D10SN)
31858 #define G_D10SN(x) (((x) >> S_D10SN) & M_D10SN)
31861 #define M_D10AMP 0x1fU
31862 #define V_D10AMP(x) ((x) << S_D10AMP)
31863 #define G_D10AMP(x) (((x) >> S_D10AMP) & M_D10AMP)
31865 #define A_XGMAC_PORT_HSS_RXA_DFE_E0_E1_OFFSET 0x1940
31868 #define M_E1SN 0x3U
31869 #define V_E1SN(x) ((x) << S_E1SN)
31870 #define G_E1SN(x) (((x) >> S_E1SN) & M_E1SN)
31873 #define M_E1AMP 0x1fU
31874 #define V_E1AMP(x) ((x) << S_E1AMP)
31875 #define G_E1AMP(x) (((x) >> S_E1AMP) & M_E1AMP)
31878 #define M_E0SN 0x3U
31879 #define V_E0SN(x) ((x) << S_E0SN)
31880 #define G_E0SN(x) (((x) >> S_E0SN) & M_E0SN)
31883 #define M_E0AMP 0x1fU
31884 #define V_E0AMP(x) ((x) << S_E0AMP)
31885 #define G_E0AMP(x) (((x) >> S_E0AMP) & M_E0AMP)
31887 #define A_XGMAC_PORT_HSS_RXA_DACA_OFFSET 0x1944
31890 #define M_AOFFO 0x3fU
31891 #define V_AOFFO(x) ((x) << S_AOFFO)
31892 #define G_AOFFO(x) (((x) >> S_AOFFO) & M_AOFFO)
31895 #define M_AOFFE 0x3fU
31896 #define V_AOFFE(x) ((x) << S_AOFFE)
31897 #define G_AOFFE(x) (((x) >> S_AOFFE) & M_AOFFE)
31899 #define A_XGMAC_PORT_HSS_RXA_DACAP_DAC_AN_OFFSET 0x1948
31902 #define M_DACAN 0xffU
31903 #define V_DACAN(x) ((x) << S_DACAN)
31904 #define G_DACAN(x) (((x) >> S_DACAN) & M_DACAN)
31907 #define M_DACAP 0xffU
31908 #define V_DACAP(x) ((x) << S_DACAP)
31909 #define G_DACAP(x) (((x) >> S_DACAP) & M_DACAP)
31911 #define A_XGMAC_PORT_HSS_RXA_DACA_MIN 0x194c
31914 #define M_DACAZ 0xffU
31915 #define V_DACAZ(x) ((x) << S_DACAZ)
31916 #define G_DACAZ(x) (((x) >> S_DACAZ) & M_DACAZ)
31919 #define M_DACAM 0xffU
31920 #define V_DACAM(x) ((x) << S_DACAM)
31921 #define G_DACAM(x) (((x) >> S_DACAM) & M_DACAM)
31923 #define A_XGMAC_PORT_HSS_RXA_ADAC_CTRL 0x1950
31926 #define M_ADSN 0x3U
31927 #define V_ADSN(x) ((x) << S_ADSN)
31928 #define G_ADSN(x) (((x) >> S_ADSN) & M_ADSN)
31931 #define M_ADMAG 0x7fU
31932 #define V_ADMAG(x) ((x) << S_ADMAG)
31933 #define G_ADMAG(x) (((x) >> S_ADMAG) & M_ADMAG)
31935 #define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_CTRL 0x1954
31938 #define V_BLKAZ(x) ((x) << S_BLKAZ)
31939 #define F_BLKAZ V_BLKAZ(1U)
31942 #define M_WIDTH 0x1fU
31943 #define V_WIDTH(x) ((x) << S_WIDTH)
31944 #define G_WIDTH(x) (((x) >> S_WIDTH) & M_WIDTH)
31946 #define S_MINWIDTH 5
31947 #define M_MINWIDTH 0x1fU
31948 #define V_MINWIDTH(x) ((x) << S_MINWIDTH)
31949 #define G_MINWIDTH(x) (((x) >> S_MINWIDTH) & M_MINWIDTH)
31952 #define M_MINAMP 0x1fU
31953 #define V_MINAMP(x) ((x) << S_MINAMP)
31954 #define G_MINAMP(x) (((x) >> S_MINAMP) & M_MINAMP)
31956 #define A_XGMAC_PORT_HSS_RXA_DIGITAL_EYE_METRICS 0x1958
31958 #define S_EMBRDY 10
31959 #define V_EMBRDY(x) ((x) << S_EMBRDY)
31960 #define F_EMBRDY V_EMBRDY(1U)
31963 #define V_EMBUMP(x) ((x) << S_EMBUMP)
31964 #define F_EMBUMP V_EMBUMP(1U)
31967 #define M_EMMD 0x3U
31968 #define V_EMMD(x) ((x) << S_EMMD)
31969 #define G_EMMD(x) (((x) >> S_EMMD) & M_EMMD)
31972 #define V_EMPAT(x) ((x) << S_EMPAT)
31973 #define F_EMPAT V_EMPAT(1U)
31976 #define V_EMEN(x) ((x) << S_EMEN)
31977 #define F_EMEN V_EMEN(1U)
31979 #define A_XGMAC_PORT_HSS_RXA_DFE_H1 0x195c
31982 #define M_H1OSN 0x3U
31983 #define V_H1OSN(x) ((x) << S_H1OSN)
31984 #define G_H1OSN(x) (((x) >> S_H1OSN) & M_H1OSN)
31987 #define M_H1OMAG 0x3fU
31988 #define V_H1OMAG(x) ((x) << S_H1OMAG)
31989 #define G_H1OMAG(x) (((x) >> S_H1OMAG) & M_H1OMAG)
31992 #define M_H1ESN 0x3U
31993 #define V_H1ESN(x) ((x) << S_H1ESN)
31994 #define G_H1ESN(x) (((x) >> S_H1ESN) & M_H1ESN)
31997 #define M_H1EMAG 0x3fU
31998 #define V_H1EMAG(x) ((x) << S_H1EMAG)
31999 #define G_H1EMAG(x) (((x) >> S_H1EMAG) & M_H1EMAG)
32001 #define A_XGMAC_PORT_HSS_RXA_DFE_H2 0x1960
32004 #define M_H2OSN 0x3U
32005 #define V_H2OSN(x) ((x) << S_H2OSN)
32006 #define G_H2OSN(x) (((x) >> S_H2OSN) & M_H2OSN)
32009 #define M_H2OMAG 0x1fU
32010 #define V_H2OMAG(x) ((x) << S_H2OMAG)
32011 #define G_H2OMAG(x) (((x) >> S_H2OMAG) & M_H2OMAG)
32014 #define M_H2ESN 0x3U
32015 #define V_H2ESN(x) ((x) << S_H2ESN)
32016 #define G_H2ESN(x) (((x) >> S_H2ESN) & M_H2ESN)
32019 #define M_H2EMAG 0x1fU
32020 #define V_H2EMAG(x) ((x) << S_H2EMAG)
32021 #define G_H2EMAG(x) (((x) >> S_H2EMAG) & M_H2EMAG)
32023 #define A_XGMAC_PORT_HSS_RXA_DFE_H3 0x1964
32026 #define M_H3OSN 0x3U
32027 #define V_H3OSN(x) ((x) << S_H3OSN)
32028 #define G_H3OSN(x) (((x) >> S_H3OSN) & M_H3OSN)
32031 #define M_H3OMAG 0xfU
32032 #define V_H3OMAG(x) ((x) << S_H3OMAG)
32033 #define G_H3OMAG(x) (((x) >> S_H3OMAG) & M_H3OMAG)
32036 #define M_H3ESN 0x3U
32037 #define V_H3ESN(x) ((x) << S_H3ESN)
32038 #define G_H3ESN(x) (((x) >> S_H3ESN) & M_H3ESN)
32041 #define M_H3EMAG 0xfU
32042 #define V_H3EMAG(x) ((x) << S_H3EMAG)
32043 #define G_H3EMAG(x) (((x) >> S_H3EMAG) & M_H3EMAG)
32045 #define A_XGMAC_PORT_HSS_RXA_DFE_H4 0x1968
32048 #define M_H4OSN 0x3U
32049 #define V_H4OSN(x) ((x) << S_H4OSN)
32050 #define G_H4OSN(x) (((x) >> S_H4OSN) & M_H4OSN)
32053 #define M_H4OMAG 0xfU
32054 #define V_H4OMAG(x) ((x) << S_H4OMAG)
32055 #define G_H4OMAG(x) (((x) >> S_H4OMAG) & M_H4OMAG)
32058 #define M_H4ESN 0x3U
32059 #define V_H4ESN(x) ((x) << S_H4ESN)
32060 #define G_H4ESN(x) (((x) >> S_H4ESN) & M_H4ESN)
32063 #define M_H4EMAG 0xfU
32064 #define V_H4EMAG(x) ((x) << S_H4EMAG)
32065 #define G_H4EMAG(x) (((x) >> S_H4EMAG) & M_H4EMAG)
32067 #define A_XGMAC_PORT_HSS_RXA_DFE_H5 0x196c
32070 #define M_H5OSN 0x3U
32071 #define V_H5OSN(x) ((x) << S_H5OSN)
32072 #define G_H5OSN(x) (((x) >> S_H5OSN) & M_H5OSN)
32075 #define M_H5OMAG 0xfU
32076 #define V_H5OMAG(x) ((x) << S_H5OMAG)
32077 #define G_H5OMAG(x) (((x) >> S_H5OMAG) & M_H5OMAG)
32080 #define M_H5ESN 0x3U
32081 #define V_H5ESN(x) ((x) << S_H5ESN)
32082 #define G_H5ESN(x) (((x) >> S_H5ESN) & M_H5ESN)
32085 #define M_H5EMAG 0xfU
32086 #define V_H5EMAG(x) ((x) << S_H5EMAG)
32087 #define G_H5EMAG(x) (((x) >> S_H5EMAG) & M_H5EMAG)
32089 #define A_XGMAC_PORT_HSS_RXA_DAC_DPC 0x1970
32091 #define S_DPCCVG 13
32092 #define V_DPCCVG(x) ((x) << S_DPCCVG)
32093 #define F_DPCCVG V_DPCCVG(1U)
32095 #define S_DACCVG 12
32096 #define V_DACCVG(x) ((x) << S_DACCVG)
32097 #define F_DACCVG V_DACCVG(1U)
32100 #define M_DPCTGT 0x7U
32101 #define V_DPCTGT(x) ((x) << S_DPCTGT)
32102 #define G_DPCTGT(x) (((x) >> S_DPCTGT) & M_DPCTGT)
32105 #define V_BLKH1T(x) ((x) << S_BLKH1T)
32106 #define F_BLKH1T V_BLKH1T(1U)
32109 #define V_BLKOAE(x) ((x) << S_BLKOAE)
32110 #define F_BLKOAE V_BLKOAE(1U)
32113 #define M_H1TGT 0x7U
32114 #define V_H1TGT(x) ((x) << S_H1TGT)
32115 #define G_H1TGT(x) (((x) >> S_H1TGT) & M_H1TGT)
32119 #define V_OAE(x) ((x) << S_OAE)
32120 #define G_OAE(x) (((x) >> S_OAE) & M_OAE)
32122 #define A_XGMAC_PORT_HSS_RXA_DDC 0x1974
32125 #define M_OLS 0x1fU
32126 #define V_OLS(x) ((x) << S_OLS)
32127 #define G_OLS(x) (((x) >> S_OLS) & M_OLS)
32130 #define M_OES 0x1fU
32131 #define V_OES(x) ((x) << S_OES)
32132 #define G_OES(x) (((x) >> S_OES) & M_OES)
32134 #define S_BLKODEC 5
32135 #define V_BLKODEC(x) ((x) << S_BLKODEC)
32136 #define F_BLKODEC V_BLKODEC(1U)
32139 #define M_ODEC 0x1fU
32140 #define V_ODEC(x) ((x) << S_ODEC)
32141 #define G_ODEC(x) (((x) >> S_ODEC) & M_ODEC)
32143 #define A_XGMAC_PORT_HSS_RXA_INTERNAL_STATUS 0x1978
32146 #define V_BER6(x) ((x) << S_BER6)
32147 #define F_BER6 V_BER6(1U)
32149 #define S_BER6VAL 14
32150 #define V_BER6VAL(x) ((x) << S_BER6VAL)
32151 #define F_BER6VAL V_BER6VAL(1U)
32153 #define S_BER3VAL 13
32154 #define V_BER3VAL(x) ((x) << S_BER3VAL)
32155 #define F_BER3VAL V_BER3VAL(1U)
32158 #define V_DPCCMP(x) ((x) << S_DPCCMP)
32159 #define F_DPCCMP V_DPCCMP(1U)
32162 #define V_DACCMP(x) ((x) << S_DACCMP)
32163 #define F_DACCMP V_DACCMP(1U)
32166 #define V_DDCCMP(x) ((x) << S_DDCCMP)
32167 #define F_DDCCMP V_DDCCMP(1U)
32169 #define S_AERRFLG 6
32170 #define V_AERRFLG(x) ((x) << S_AERRFLG)
32171 #define F_AERRFLG V_AERRFLG(1U)
32173 #define S_WERRFLG 5
32174 #define V_WERRFLG(x) ((x) << S_WERRFLG)
32175 #define F_WERRFLG V_WERRFLG(1U)
32178 #define V_TRCMP(x) ((x) << S_TRCMP)
32179 #define F_TRCMP V_TRCMP(1U)
32182 #define V_VLCKF(x) ((x) << S_VLCKF)
32183 #define F_VLCKF V_VLCKF(1U)
32186 #define V_ROCADJ(x) ((x) << S_ROCADJ)
32187 #define F_ROCADJ V_ROCADJ(1U)
32190 #define V_ROCCMP(x) ((x) << S_ROCCMP)
32191 #define F_ROCCMP V_ROCCMP(1U)
32194 #define V_OCCMP(x) ((x) << S_OCCMP)
32195 #define F_OCCMP V_OCCMP(1U)
32197 #define A_XGMAC_PORT_HSS_RXA_DFE_FUNC_CTRL 0x197c
32200 #define V_FDPC(x) ((x) << S_FDPC)
32201 #define F_FDPC V_FDPC(1U)
32204 #define V_FDAC(x) ((x) << S_FDAC)
32205 #define F_FDAC V_FDAC(1U)
32208 #define V_FDDC(x) ((x) << S_FDDC)
32209 #define F_FDDC V_FDDC(1U)
32212 #define V_FNRND(x) ((x) << S_FNRND)
32213 #define F_FNRND V_FNRND(1U)
32215 #define S_FVGAIN 11
32216 #define V_FVGAIN(x) ((x) << S_FVGAIN)
32217 #define F_FVGAIN V_FVGAIN(1U)
32220 #define V_FVOFF(x) ((x) << S_FVOFF)
32221 #define F_FVOFF V_FVOFF(1U)
32224 #define V_FSDET(x) ((x) << S_FSDET)
32225 #define F_FSDET V_FSDET(1U)
32228 #define V_FBER6(x) ((x) << S_FBER6)
32229 #define F_FBER6 V_FBER6(1U)
32232 #define V_FROTO(x) ((x) << S_FROTO)
32233 #define F_FROTO V_FROTO(1U)
32236 #define V_FH4H5(x) ((x) << S_FH4H5)
32237 #define F_FH4H5 V_FH4H5(1U)
32240 #define V_FH2H3(x) ((x) << S_FH2H3)
32241 #define F_FH2H3 V_FH2H3(1U)
32244 #define V_FH1(x) ((x) << S_FH1)
32245 #define F_FH1 V_FH1(1U)
32248 #define V_FH1SN(x) ((x) << S_FH1SN)
32249 #define F_FH1SN V_FH1SN(1U)
32252 #define V_FNRDF(x) ((x) << S_FNRDF)
32253 #define F_FNRDF V_FNRDF(1U)
32256 #define V_FADAC(x) ((x) << S_FADAC)
32257 #define F_FADAC V_FADAC(1U)
32259 #define A_XGMAC_PORT_HSS_RXB_CFG_MODE 0x1980
32260 #define A_XGMAC_PORT_HSS_RXB_TEST_CTRL 0x1984
32261 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_CTRL 0x1988
32262 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_OFFSET_CTRL 0x198c
32263 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION1 0x1990
32264 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_POSITION2 0x1994
32265 #define A_XGMAC_PORT_HSS_RXB_PH_ROTATOR_STATIC_PH_OFFSET 0x1998
32266 #define A_XGMAC_PORT_HSS_RXB_SIGDET_CTRL 0x199c
32267 #define A_XGMAC_PORT_HSS_RXB_DFE_CTRL 0x19a0
32268 #define A_XGMAC_PORT_HSS_RXB_DFE_DATA_EDGE_SAMPLE 0x19a4
32269 #define A_XGMAC_PORT_HSS_RXB_DFE_AMP_SAMPLE 0x19a8
32270 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL1 0x19ac
32271 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL2 0x19b0
32272 #define A_XGMAC_PORT_HSS_RXB_VGA_CTRL3 0x19b4
32273 #define A_XGMAC_PORT_HSS_RXB_DFE_D00_D01_OFFSET 0x19b8
32274 #define A_XGMAC_PORT_HSS_RXB_DFE_D10_D11_OFFSET 0x19bc
32275 #define A_XGMAC_PORT_HSS_RXB_DFE_E0_E1_OFFSET 0x19c0
32276 #define A_XGMAC_PORT_HSS_RXB_DACA_OFFSET 0x19c4
32277 #define A_XGMAC_PORT_HSS_RXB_DACAP_DAC_AN_OFFSET 0x19c8
32278 #define A_XGMAC_PORT_HSS_RXB_DACA_MIN 0x19cc
32279 #define A_XGMAC_PORT_HSS_RXB_ADAC_CTRL 0x19d0
32280 #define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_CTRL 0x19d4
32281 #define A_XGMAC_PORT_HSS_RXB_DIGITAL_EYE_METRICS 0x19d8
32282 #define A_XGMAC_PORT_HSS_RXB_DFE_H1 0x19dc
32283 #define A_XGMAC_PORT_HSS_RXB_DFE_H2 0x19e0
32284 #define A_XGMAC_PORT_HSS_RXB_DFE_H3 0x19e4
32285 #define A_XGMAC_PORT_HSS_RXB_DFE_H4 0x19e8
32286 #define A_XGMAC_PORT_HSS_RXB_DFE_H5 0x19ec
32287 #define A_XGMAC_PORT_HSS_RXB_DAC_DPC 0x19f0
32288 #define A_XGMAC_PORT_HSS_RXB_DDC 0x19f4
32289 #define A_XGMAC_PORT_HSS_RXB_INTERNAL_STATUS 0x19f8
32290 #define A_XGMAC_PORT_HSS_RXB_DFE_FUNC_CTRL 0x19fc
32291 #define A_XGMAC_PORT_HSS_TXC_MODE_CFG 0x1a00
32292 #define A_XGMAC_PORT_HSS_TXC_TEST_CTRL 0x1a04
32293 #define A_XGMAC_PORT_HSS_TXC_COEFF_CTRL 0x1a08
32294 #define A_XGMAC_PORT_HSS_TXC_DRIVER_MODE 0x1a0c
32295 #define A_XGMAC_PORT_HSS_TXC_DRIVER_OVR_CTRL 0x1a10
32296 #define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_STANDBY_TIMER 0x1a14
32297 #define A_XGMAC_PORT_HSS_TXC_TDM_BIASGEN_PWRON_TIMER 0x1a18
32298 #define A_XGMAC_PORT_HSS_TXC_TAP0_COEFF 0x1a20
32299 #define A_XGMAC_PORT_HSS_TXC_TAP1_COEFF 0x1a24
32300 #define A_XGMAC_PORT_HSS_TXC_TAP2_COEFF 0x1a28
32301 #define A_XGMAC_PORT_HSS_TXC_PWR 0x1a30
32302 #define A_XGMAC_PORT_HSS_TXC_POLARITY 0x1a34
32303 #define A_XGMAC_PORT_HSS_TXC_8023AP_AE_CMD 0x1a38
32304 #define A_XGMAC_PORT_HSS_TXC_8023AP_AE_STATUS 0x1a3c
32305 #define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_OVR 0x1a40
32306 #define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_OVR 0x1a44
32307 #define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_OVR 0x1a48
32308 #define A_XGMAC_PORT_HSS_TXC_PWR_DAC_OVR 0x1a50
32309 #define A_XGMAC_PORT_HSS_TXC_PWR_DAC 0x1a54
32310 #define A_XGMAC_PORT_HSS_TXC_TAP0_IDAC_APP 0x1a60
32311 #define A_XGMAC_PORT_HSS_TXC_TAP1_IDAC_APP 0x1a64
32312 #define A_XGMAC_PORT_HSS_TXC_TAP2_IDAC_APP 0x1a68
32313 #define A_XGMAC_PORT_HSS_TXC_SEG_DIS_APP 0x1a70
32314 #define A_XGMAC_PORT_HSS_TXC_EXT_ADDR_DATA 0x1a78
32315 #define A_XGMAC_PORT_HSS_TXC_EXT_ADDR 0x1a7c
32316 #define A_XGMAC_PORT_HSS_TXD_MODE_CFG 0x1a80
32317 #define A_XGMAC_PORT_HSS_TXD_TEST_CTRL 0x1a84
32318 #define A_XGMAC_PORT_HSS_TXD_COEFF_CTRL 0x1a88
32319 #define A_XGMAC_PORT_HSS_TXD_DRIVER_MODE 0x1a8c
32320 #define A_XGMAC_PORT_HSS_TXD_DRIVER_OVR_CTRL 0x1a90
32321 #define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_STANDBY_TIMER 0x1a94
32322 #define A_XGMAC_PORT_HSS_TXD_TDM_BIASGEN_PWRON_TIMER 0x1a98
32323 #define A_XGMAC_PORT_HSS_TXD_TAP0_COEFF 0x1aa0
32324 #define A_XGMAC_PORT_HSS_TXD_TAP1_COEFF 0x1aa4
32325 #define A_XGMAC_PORT_HSS_TXD_TAP2_COEFF 0x1aa8
32326 #define A_XGMAC_PORT_HSS_TXD_PWR 0x1ab0
32327 #define A_XGMAC_PORT_HSS_TXD_POLARITY 0x1ab4
32328 #define A_XGMAC_PORT_HSS_TXD_8023AP_AE_CMD 0x1ab8
32329 #define A_XGMAC_PORT_HSS_TXD_8023AP_AE_STATUS 0x1abc
32330 #define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_OVR 0x1ac0
32331 #define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_OVR 0x1ac4
32332 #define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_OVR 0x1ac8
32333 #define A_XGMAC_PORT_HSS_TXD_PWR_DAC_OVR 0x1ad0
32334 #define A_XGMAC_PORT_HSS_TXD_PWR_DAC 0x1ad4
32335 #define A_XGMAC_PORT_HSS_TXD_TAP0_IDAC_APP 0x1ae0
32336 #define A_XGMAC_PORT_HSS_TXD_TAP1_IDAC_APP 0x1ae4
32337 #define A_XGMAC_PORT_HSS_TXD_TAP2_IDAC_APP 0x1ae8
32338 #define A_XGMAC_PORT_HSS_TXD_SEG_DIS_APP 0x1af0
32339 #define A_XGMAC_PORT_HSS_TXD_EXT_ADDR_DATA 0x1af8
32340 #define A_XGMAC_PORT_HSS_TXD_EXT_ADDR 0x1afc
32341 #define A_XGMAC_PORT_HSS_RXC_CFG_MODE 0x1b00
32342 #define A_XGMAC_PORT_HSS_RXC_TEST_CTRL 0x1b04
32343 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_CTRL 0x1b08
32344 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_OFFSET_CTRL 0x1b0c
32345 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION1 0x1b10
32346 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_POSITION2 0x1b14
32347 #define A_XGMAC_PORT_HSS_RXC_PH_ROTATOR_STATIC_PH_OFFSET 0x1b18
32348 #define A_XGMAC_PORT_HSS_RXC_SIGDET_CTRL 0x1b1c
32349 #define A_XGMAC_PORT_HSS_RXC_DFE_CTRL 0x1b20
32350 #define A_XGMAC_PORT_HSS_RXC_DFE_DATA_EDGE_SAMPLE 0x1b24
32351 #define A_XGMAC_PORT_HSS_RXC_DFE_AMP_SAMPLE 0x1b28
32352 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL1 0x1b2c
32353 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL2 0x1b30
32354 #define A_XGMAC_PORT_HSS_RXC_VGA_CTRL3 0x1b34
32355 #define A_XGMAC_PORT_HSS_RXC_DFE_D00_D01_OFFSET 0x1b38
32356 #define A_XGMAC_PORT_HSS_RXC_DFE_D10_D11_OFFSET 0x1b3c
32357 #define A_XGMAC_PORT_HSS_RXC_DFE_E0_E1_OFFSET 0x1b40
32358 #define A_XGMAC_PORT_HSS_RXC_DACA_OFFSET 0x1b44
32359 #define A_XGMAC_PORT_HSS_RXC_DACAP_DAC_AN_OFFSET 0x1b48
32360 #define A_XGMAC_PORT_HSS_RXC_DACA_MIN 0x1b4c
32361 #define A_XGMAC_PORT_HSS_RXC_ADAC_CTRL 0x1b50
32362 #define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_CTRL 0x1b54
32363 #define A_XGMAC_PORT_HSS_RXC_DIGITAL_EYE_METRICS 0x1b58
32364 #define A_XGMAC_PORT_HSS_RXC_DFE_H1 0x1b5c
32365 #define A_XGMAC_PORT_HSS_RXC_DFE_H2 0x1b60
32366 #define A_XGMAC_PORT_HSS_RXC_DFE_H3 0x1b64
32367 #define A_XGMAC_PORT_HSS_RXC_DFE_H4 0x1b68
32368 #define A_XGMAC_PORT_HSS_RXC_DFE_H5 0x1b6c
32369 #define A_XGMAC_PORT_HSS_RXC_DAC_DPC 0x1b70
32370 #define A_XGMAC_PORT_HSS_RXC_DDC 0x1b74
32371 #define A_XGMAC_PORT_HSS_RXC_INTERNAL_STATUS 0x1b78
32372 #define A_XGMAC_PORT_HSS_RXC_DFE_FUNC_CTRL 0x1b7c
32373 #define A_XGMAC_PORT_HSS_RXD_CFG_MODE 0x1b80
32374 #define A_XGMAC_PORT_HSS_RXD_TEST_CTRL 0x1b84
32375 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_CTRL 0x1b88
32376 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_OFFSET_CTRL 0x1b8c
32377 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION1 0x1b90
32378 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_POSITION2 0x1b94
32379 #define A_XGMAC_PORT_HSS_RXD_PH_ROTATOR_STATIC_PH_OFFSET 0x1b98
32380 #define A_XGMAC_PORT_HSS_RXD_SIGDET_CTRL 0x1b9c
32381 #define A_XGMAC_PORT_HSS_RXD_DFE_CTRL 0x1ba0
32382 #define A_XGMAC_PORT_HSS_RXD_DFE_DATA_EDGE_SAMPLE 0x1ba4
32383 #define A_XGMAC_PORT_HSS_RXD_DFE_AMP_SAMPLE 0x1ba8
32384 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL1 0x1bac
32385 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL2 0x1bb0
32386 #define A_XGMAC_PORT_HSS_RXD_VGA_CTRL3 0x1bb4
32387 #define A_XGMAC_PORT_HSS_RXD_DFE_D00_D01_OFFSET 0x1bb8
32388 #define A_XGMAC_PORT_HSS_RXD_DFE_D10_D11_OFFSET 0x1bbc
32389 #define A_XGMAC_PORT_HSS_RXD_DFE_E0_E1_OFFSET 0x1bc0
32390 #define A_XGMAC_PORT_HSS_RXD_DACA_OFFSET 0x1bc4
32391 #define A_XGMAC_PORT_HSS_RXD_DACAP_DAC_AN_OFFSET 0x1bc8
32392 #define A_XGMAC_PORT_HSS_RXD_DACA_MIN 0x1bcc
32393 #define A_XGMAC_PORT_HSS_RXD_ADAC_CTRL 0x1bd0
32394 #define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_CTRL 0x1bd4
32395 #define A_XGMAC_PORT_HSS_RXD_DIGITAL_EYE_METRICS 0x1bd8
32396 #define A_XGMAC_PORT_HSS_RXD_DFE_H1 0x1bdc
32397 #define A_XGMAC_PORT_HSS_RXD_DFE_H2 0x1be0
32398 #define A_XGMAC_PORT_HSS_RXD_DFE_H3 0x1be4
32399 #define A_XGMAC_PORT_HSS_RXD_DFE_H4 0x1be8
32400 #define A_XGMAC_PORT_HSS_RXD_DFE_H5 0x1bec
32401 #define A_XGMAC_PORT_HSS_RXD_DAC_DPC 0x1bf0
32402 #define A_XGMAC_PORT_HSS_RXD_DDC 0x1bf4
32403 #define A_XGMAC_PORT_HSS_RXD_INTERNAL_STATUS 0x1bf8
32404 #define A_XGMAC_PORT_HSS_RXD_DFE_FUNC_CTRL 0x1bfc
32405 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_0 0x1c00
32408 #define M_BSELO 0xfU
32409 #define V_BSELO(x) ((x) << S_BSELO)
32410 #define G_BSELO(x) (((x) >> S_BSELO) & M_BSELO)
32412 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_1 0x1c04
32415 #define V_LDET(x) ((x) << S_LDET)
32416 #define F_LDET V_LDET(1U)
32419 #define V_CCERR(x) ((x) << S_CCERR)
32420 #define F_CCERR V_CCERR(1U)
32423 #define V_CCCMP(x) ((x) << S_CCCMP)
32424 #define F_CCCMP V_CCCMP(1U)
32426 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_2 0x1c08
32429 #define M_BSELI 0xfU
32430 #define V_BSELI(x) ((x) << S_BSELI)
32431 #define G_BSELI(x) (((x) >> S_BSELI) & M_BSELI)
32433 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_3 0x1c0c
32436 #define V_VISEL(x) ((x) << S_VISEL)
32437 #define F_VISEL V_VISEL(1U)
32440 #define V_FMIN(x) ((x) << S_FMIN)
32441 #define F_FMIN V_FMIN(1U)
32444 #define V_FMAX(x) ((x) << S_FMAX)
32445 #define F_FMAX V_FMAX(1U)
32448 #define V_CVHOLD(x) ((x) << S_CVHOLD)
32449 #define F_CVHOLD V_CVHOLD(1U)
32452 #define V_TCDIS(x) ((x) << S_TCDIS)
32453 #define F_TCDIS V_TCDIS(1U)
32455 #define A_XGMAC_PORT_HSS_VCO_COARSE_CALIBRATION_4 0x1c10
32458 #define V_CMETH(x) ((x) << S_CMETH)
32459 #define F_CMETH V_CMETH(1U)
32462 #define V_RECAL(x) ((x) << S_RECAL)
32463 #define F_RECAL V_RECAL(1U)
32466 #define V_CCLD(x) ((x) << S_CCLD)
32467 #define F_CCLD V_CCLD(1U)
32469 #define A_XGMAC_PORT_HSS_ANALOG_TEST_MUX 0x1c14
32472 #define M_ATST 0x1fU
32473 #define V_ATST(x) ((x) << S_ATST)
32474 #define G_ATST(x) (((x) >> S_ATST) & M_ATST)
32476 #define A_XGMAC_PORT_HSS_PORT_EN_0 0x1c18
32479 #define V_RXDEN(x) ((x) << S_RXDEN)
32480 #define F_RXDEN V_RXDEN(1U)
32483 #define V_RXCEN(x) ((x) << S_RXCEN)
32484 #define F_RXCEN V_RXCEN(1U)
32487 #define V_TXDEN(x) ((x) << S_TXDEN)
32488 #define F_TXDEN V_TXDEN(1U)
32491 #define V_TXCEN(x) ((x) << S_TXCEN)
32492 #define F_TXCEN V_TXCEN(1U)
32495 #define V_RXBEN(x) ((x) << S_RXBEN)
32496 #define F_RXBEN V_RXBEN(1U)
32499 #define V_RXAEN(x) ((x) << S_RXAEN)
32500 #define F_RXAEN V_RXAEN(1U)
32503 #define V_TXBEN(x) ((x) << S_TXBEN)
32504 #define F_TXBEN V_TXBEN(1U)
32507 #define V_TXAEN(x) ((x) << S_TXAEN)
32508 #define F_TXAEN V_TXAEN(1U)
32510 #define A_XGMAC_PORT_HSS_PORT_RESET_0 0x1c20
32513 #define V_RXDRST(x) ((x) << S_RXDRST)
32514 #define F_RXDRST V_RXDRST(1U)
32517 #define V_RXCRST(x) ((x) << S_RXCRST)
32518 #define F_RXCRST V_RXCRST(1U)
32521 #define V_TXDRST(x) ((x) << S_TXDRST)
32522 #define F_TXDRST V_TXDRST(1U)
32525 #define V_TXCRST(x) ((x) << S_TXCRST)
32526 #define F_TXCRST V_TXCRST(1U)
32529 #define V_RXBRST(x) ((x) << S_RXBRST)
32530 #define F_RXBRST V_RXBRST(1U)
32533 #define V_RXARST(x) ((x) << S_RXARST)
32534 #define F_RXARST V_RXARST(1U)
32537 #define V_TXBRST(x) ((x) << S_TXBRST)
32538 #define F_TXBRST V_TXBRST(1U)
32541 #define V_TXARST(x) ((x) << S_TXARST)
32542 #define F_TXARST V_TXARST(1U)
32544 #define A_XGMAC_PORT_HSS_CHARGE_PUMP_CTRL 0x1c28
32547 #define V_ENCPIS(x) ((x) << S_ENCPIS)
32548 #define F_ENCPIS V_ENCPIS(1U)
32551 #define M_CPISEL 0x3U
32552 #define V_CPISEL(x) ((x) << S_CPISEL)
32553 #define G_CPISEL(x) (((x) >> S_CPISEL) & M_CPISEL)
32555 #define A_XGMAC_PORT_HSS_BAND_GAP_CTRL 0x1c2c
32558 #define M_BGCTL 0x1fU
32559 #define V_BGCTL(x) ((x) << S_BGCTL)
32560 #define G_BGCTL(x) (((x) >> S_BGCTL) & M_BGCTL)
32562 #define A_XGMAC_PORT_HSS_LOFREQ_OVR 0x1c30
32565 #define V_LFREQ2(x) ((x) << S_LFREQ2)
32566 #define F_LFREQ2 V_LFREQ2(1U)
32569 #define V_LFREQ1(x) ((x) << S_LFREQ1)
32570 #define F_LFREQ1 V_LFREQ1(1U)
32573 #define V_LFREQO(x) ((x) << S_LFREQO)
32574 #define F_LFREQO V_LFREQO(1U)
32577 #define V_LFSEL(x) ((x) << S_LFSEL)
32578 #define F_LFSEL V_LFSEL(1U)
32580 #define A_XGMAC_PORT_HSS_VOLTAGE_BOOST_CTRL 0x1c38
32583 #define V_PFVAL(x) ((x) << S_PFVAL)
32584 #define F_PFVAL V_PFVAL(1U)
32587 #define V_PFEN(x) ((x) << S_PFEN)
32588 #define F_PFEN V_PFEN(1U)
32591 #define V_VBADJ(x) ((x) << S_VBADJ)
32592 #define F_VBADJ V_VBADJ(1U)
32594 #define A_XGMAC_PORT_HSS_TX_MODE_CFG 0x1c80
32595 #define A_XGMAC_PORT_HSS_TXTEST_CTRL 0x1c84
32596 #define A_XGMAC_PORT_HSS_TX_COEFF_CTRL 0x1c88
32597 #define A_XGMAC_PORT_HSS_TX_DRIVER_MODE 0x1c8c
32598 #define A_XGMAC_PORT_HSS_TX_DRIVER_OVR_CTRL 0x1c90
32599 #define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_STANDBY_TIMER 0x1c94
32600 #define A_XGMAC_PORT_HSS_TX_TDM_BIASGEN_PWRON_TIMER 0x1c98
32601 #define A_XGMAC_PORT_HSS_TX_TAP0_COEFF 0x1ca0
32602 #define A_XGMAC_PORT_HSS_TX_TAP1_COEFF 0x1ca4
32603 #define A_XGMAC_PORT_HSS_TX_TAP2_COEFF 0x1ca8
32604 #define A_XGMAC_PORT_HSS_TX_PWR 0x1cb0
32605 #define A_XGMAC_PORT_HSS_TX_POLARITY 0x1cb4
32606 #define A_XGMAC_PORT_HSS_TX_8023AP_AE_CMD 0x1cb8
32607 #define A_XGMAC_PORT_HSS_TX_8023AP_AE_STATUS 0x1cbc
32608 #define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_OVR 0x1cc0
32609 #define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_OVR 0x1cc4
32610 #define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_OVR 0x1cc8
32611 #define A_XGMAC_PORT_HSS_TX_PWR_DAC_OVR 0x1cd0
32612 #define A_XGMAC_PORT_HSS_TX_PWR_DAC 0x1cd4
32613 #define A_XGMAC_PORT_HSS_TX_TAP0_IDAC_APP 0x1ce0
32614 #define A_XGMAC_PORT_HSS_TX_TAP1_IDAC_APP 0x1ce4
32615 #define A_XGMAC_PORT_HSS_TX_TAP2_IDAC_APP 0x1ce8
32616 #define A_XGMAC_PORT_HSS_TX_SEG_DIS_APP 0x1cf0
32617 #define A_XGMAC_PORT_HSS_TX_EXT_ADDR_DATA 0x1cf8
32618 #define A_XGMAC_PORT_HSS_TX_EXT_ADDR 0x1cfc
32619 #define A_XGMAC_PORT_HSS_RX_CFG_MODE 0x1d00
32620 #define A_XGMAC_PORT_HSS_RXTEST_CTRL 0x1d04
32621 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_CTRL 0x1d08
32622 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_OFFSET_CTRL 0x1d0c
32623 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION1 0x1d10
32624 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_POSITION2 0x1d14
32625 #define A_XGMAC_PORT_HSS_RX_PH_ROTATOR_STATIC_PH_OFFSET 0x1d18
32626 #define A_XGMAC_PORT_HSS_RX_SIGDET_CTRL 0x1d1c
32627 #define A_XGMAC_PORT_HSS_RX_DFE_CTRL 0x1d20
32628 #define A_XGMAC_PORT_HSS_RX_DFE_DATA_EDGE_SAMPLE 0x1d24
32629 #define A_XGMAC_PORT_HSS_RX_DFE_AMP_SAMPLE 0x1d28
32630 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL1 0x1d2c
32631 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL2 0x1d30
32632 #define A_XGMAC_PORT_HSS_RX_VGA_CTRL3 0x1d34
32633 #define A_XGMAC_PORT_HSS_RX_DFE_D00_D01_OFFSET 0x1d38
32634 #define A_XGMAC_PORT_HSS_RX_DFE_D10_D11_OFFSET 0x1d3c
32635 #define A_XGMAC_PORT_HSS_RX_DFE_E0_E1_OFFSET 0x1d40
32636 #define A_XGMAC_PORT_HSS_RX_DACA_OFFSET 0x1d44
32637 #define A_XGMAC_PORT_HSS_RX_DACAP_DAC_AN_OFFSET 0x1d48
32638 #define A_XGMAC_PORT_HSS_RX_DACA_MIN 0x1d4c
32639 #define A_XGMAC_PORT_HSS_RX_ADAC_CTRL 0x1d50
32640 #define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_CTRL 0x1d54
32641 #define A_XGMAC_PORT_HSS_RX_DIGITAL_EYE_METRICS 0x1d58
32642 #define A_XGMAC_PORT_HSS_RX_DFE_H1 0x1d5c
32643 #define A_XGMAC_PORT_HSS_RX_DFE_H2 0x1d60
32644 #define A_XGMAC_PORT_HSS_RX_DFE_H3 0x1d64
32645 #define A_XGMAC_PORT_HSS_RX_DFE_H4 0x1d68
32646 #define A_XGMAC_PORT_HSS_RX_DFE_H5 0x1d6c
32647 #define A_XGMAC_PORT_HSS_RX_DAC_DPC 0x1d70
32648 #define A_XGMAC_PORT_HSS_RX_DDC 0x1d74
32649 #define A_XGMAC_PORT_HSS_RX_INTERNAL_STATUS 0x1d78
32650 #define A_XGMAC_PORT_HSS_RX_DFE_FUNC_CTRL 0x1d7c
32651 #define A_XGMAC_PORT_HSS_TXRX_CFG_MODE 0x1e00
32652 #define A_XGMAC_PORT_HSS_TXRXTEST_CTRL 0x1e04
32654 /* registers for module UP */
32655 #define UP_BASE_ADDR 0x0
32657 #define A_UP_IBQ_CONFIG 0x0
32659 #define S_IBQGEN2 2
32660 #define M_IBQGEN2 0x3fffffffU
32661 #define V_IBQGEN2(x) ((x) << S_IBQGEN2)
32662 #define G_IBQGEN2(x) (((x) >> S_IBQGEN2) & M_IBQGEN2)
32664 #define S_IBQBUSY 1
32665 #define V_IBQBUSY(x) ((x) << S_IBQBUSY)
32666 #define F_IBQBUSY V_IBQBUSY(1U)
32669 #define V_IBQEN(x) ((x) << S_IBQEN)
32670 #define F_IBQEN V_IBQEN(1U)
32672 #define A_UP_OBQ_CONFIG 0x4
32674 #define S_OBQGEN2 2
32675 #define M_OBQGEN2 0x3fffffffU
32676 #define V_OBQGEN2(x) ((x) << S_OBQGEN2)
32677 #define G_OBQGEN2(x) (((x) >> S_OBQGEN2) & M_OBQGEN2)
32679 #define S_OBQBUSY 1
32680 #define V_OBQBUSY(x) ((x) << S_OBQBUSY)
32681 #define F_OBQBUSY V_OBQBUSY(1U)
32684 #define V_OBQEN(x) ((x) << S_OBQEN)
32685 #define F_OBQEN V_OBQEN(1U)
32687 #define A_UP_IBQ_GEN 0x8
32689 #define S_IBQGEN0 22
32690 #define M_IBQGEN0 0x3ffU
32691 #define V_IBQGEN0(x) ((x) << S_IBQGEN0)
32692 #define G_IBQGEN0(x) (((x) >> S_IBQGEN0) & M_IBQGEN0)
32694 #define S_IBQTSCHCHNLRDY 18
32695 #define M_IBQTSCHCHNLRDY 0xfU
32696 #define V_IBQTSCHCHNLRDY(x) ((x) << S_IBQTSCHCHNLRDY)
32697 #define G_IBQTSCHCHNLRDY(x) (((x) >> S_IBQTSCHCHNLRDY) & M_IBQTSCHCHNLRDY)
32699 #define S_IBQMBVFSTATUS 17
32700 #define V_IBQMBVFSTATUS(x) ((x) << S_IBQMBVFSTATUS)
32701 #define F_IBQMBVFSTATUS V_IBQMBVFSTATUS(1U)
32703 #define S_IBQMBSTATUS 16
32704 #define V_IBQMBSTATUS(x) ((x) << S_IBQMBSTATUS)
32705 #define F_IBQMBSTATUS V_IBQMBSTATUS(1U)
32707 #define S_IBQGEN1 6
32708 #define M_IBQGEN1 0x3ffU
32709 #define V_IBQGEN1(x) ((x) << S_IBQGEN1)
32710 #define G_IBQGEN1(x) (((x) >> S_IBQGEN1) & M_IBQGEN1)
32712 #define S_IBQEMPTY 0
32713 #define M_IBQEMPTY 0x3fU
32714 #define V_IBQEMPTY(x) ((x) << S_IBQEMPTY)
32715 #define G_IBQEMPTY(x) (((x) >> S_IBQEMPTY) & M_IBQEMPTY)
32717 #define A_UP_OBQ_GEN 0xc
32720 #define M_OBQGEN 0x3ffffffU
32721 #define V_OBQGEN(x) ((x) << S_OBQGEN)
32722 #define G_OBQGEN(x) (((x) >> S_OBQGEN) & M_OBQGEN)
32724 #define S_OBQFULL 0
32725 #define M_OBQFULL 0x3fU
32726 #define V_OBQFULL(x) ((x) << S_OBQFULL)
32727 #define G_OBQFULL(x) (((x) >> S_OBQFULL) & M_OBQFULL)
32729 #define S_T5_OBQGEN 8
32730 #define M_T5_OBQGEN 0xffffffU
32731 #define V_T5_OBQGEN(x) ((x) << S_T5_OBQGEN)
32732 #define G_T5_OBQGEN(x) (((x) >> S_T5_OBQGEN) & M_T5_OBQGEN)
32734 #define S_T5_OBQFULL 0
32735 #define M_T5_OBQFULL 0xffU
32736 #define V_T5_OBQFULL(x) ((x) << S_T5_OBQFULL)
32737 #define G_T5_OBQFULL(x) (((x) >> S_T5_OBQFULL) & M_T5_OBQFULL)
32739 #define A_UP_IBQ_0_RDADDR 0x10
32742 #define M_QUEID 0x7ffffU
32743 #define V_QUEID(x) ((x) << S_QUEID)
32744 #define G_QUEID(x) (((x) >> S_QUEID) & M_QUEID)
32746 #define S_IBQRDADDR 0
32747 #define M_IBQRDADDR 0x1fffU
32748 #define V_IBQRDADDR(x) ((x) << S_IBQRDADDR)
32749 #define G_IBQRDADDR(x) (((x) >> S_IBQRDADDR) & M_IBQRDADDR)
32751 #define A_UP_IBQ_0_WRADDR 0x14
32753 #define S_IBQWRADDR 0
32754 #define M_IBQWRADDR 0x1fffU
32755 #define V_IBQWRADDR(x) ((x) << S_IBQWRADDR)
32756 #define G_IBQWRADDR(x) (((x) >> S_IBQWRADDR) & M_IBQWRADDR)
32758 #define A_UP_IBQ_0_STATUS 0x18
32760 #define S_QUEERRFRAME 31
32761 #define V_QUEERRFRAME(x) ((x) << S_QUEERRFRAME)
32762 #define F_QUEERRFRAME V_QUEERRFRAME(1U)
32764 #define S_QUEREMFLITS 0
32765 #define M_QUEREMFLITS 0x7ffU
32766 #define V_QUEREMFLITS(x) ((x) << S_QUEREMFLITS)
32767 #define G_QUEREMFLITS(x) (((x) >> S_QUEREMFLITS) & M_QUEREMFLITS)
32769 #define A_UP_IBQ_0_PKTCNT 0x1c
32771 #define S_QUEEOPCNT 16
32772 #define M_QUEEOPCNT 0xfffU
32773 #define V_QUEEOPCNT(x) ((x) << S_QUEEOPCNT)
32774 #define G_QUEEOPCNT(x) (((x) >> S_QUEEOPCNT) & M_QUEEOPCNT)
32776 #define S_QUESOPCNT 0
32777 #define M_QUESOPCNT 0xfffU
32778 #define V_QUESOPCNT(x) ((x) << S_QUESOPCNT)
32779 #define G_QUESOPCNT(x) (((x) >> S_QUESOPCNT) & M_QUESOPCNT)
32781 #define A_UP_IBQ_1_RDADDR 0x20
32782 #define A_UP_IBQ_1_WRADDR 0x24
32783 #define A_UP_IBQ_1_STATUS 0x28
32784 #define A_UP_IBQ_1_PKTCNT 0x2c
32785 #define A_UP_IBQ_2_RDADDR 0x30
32786 #define A_UP_IBQ_2_WRADDR 0x34
32787 #define A_UP_IBQ_2_STATUS 0x38
32788 #define A_UP_IBQ_2_PKTCNT 0x3c
32789 #define A_UP_IBQ_3_RDADDR 0x40
32790 #define A_UP_IBQ_3_WRADDR 0x44
32791 #define A_UP_IBQ_3_STATUS 0x48
32792 #define A_UP_IBQ_3_PKTCNT 0x4c
32793 #define A_UP_IBQ_4_RDADDR 0x50
32794 #define A_UP_IBQ_4_WRADDR 0x54
32795 #define A_UP_IBQ_4_STATUS 0x58
32796 #define A_UP_IBQ_4_PKTCNT 0x5c
32797 #define A_UP_IBQ_5_RDADDR 0x60
32798 #define A_UP_IBQ_5_WRADDR 0x64
32799 #define A_UP_IBQ_5_STATUS 0x68
32800 #define A_UP_IBQ_5_PKTCNT 0x6c
32801 #define A_UP_OBQ_0_RDADDR 0x70
32804 #define M_OBQID 0x1ffffU
32805 #define V_OBQID(x) ((x) << S_OBQID)
32806 #define G_OBQID(x) (((x) >> S_OBQID) & M_OBQID)
32808 #define S_QUERDADDR 0
32809 #define M_QUERDADDR 0x7fffU
32810 #define V_QUERDADDR(x) ((x) << S_QUERDADDR)
32811 #define G_QUERDADDR(x) (((x) >> S_QUERDADDR) & M_QUERDADDR)
32813 #define A_UP_OBQ_0_WRADDR 0x74
32815 #define S_QUEWRADDR 0
32816 #define M_QUEWRADDR 0x7fffU
32817 #define V_QUEWRADDR(x) ((x) << S_QUEWRADDR)
32818 #define G_QUEWRADDR(x) (((x) >> S_QUEWRADDR) & M_QUEWRADDR)
32820 #define A_UP_OBQ_0_STATUS 0x78
32821 #define A_UP_OBQ_0_PKTCNT 0x7c
32822 #define A_UP_OBQ_1_RDADDR 0x80
32823 #define A_UP_OBQ_1_WRADDR 0x84
32824 #define A_UP_OBQ_1_STATUS 0x88
32825 #define A_UP_OBQ_1_PKTCNT 0x8c
32826 #define A_UP_OBQ_2_RDADDR 0x90
32827 #define A_UP_OBQ_2_WRADDR 0x94
32828 #define A_UP_OBQ_2_STATUS 0x98
32829 #define A_UP_OBQ_2_PKTCNT 0x9c
32830 #define A_UP_OBQ_3_RDADDR 0xa0
32831 #define A_UP_OBQ_3_WRADDR 0xa4
32832 #define A_UP_OBQ_3_STATUS 0xa8
32833 #define A_UP_OBQ_3_PKTCNT 0xac
32834 #define A_UP_OBQ_4_RDADDR 0xb0
32835 #define A_UP_OBQ_4_WRADDR 0xb4
32836 #define A_UP_OBQ_4_STATUS 0xb8
32837 #define A_UP_OBQ_4_PKTCNT 0xbc
32838 #define A_UP_OBQ_5_RDADDR 0xc0
32839 #define A_UP_OBQ_5_WRADDR 0xc4
32840 #define A_UP_OBQ_5_STATUS 0xc8
32841 #define A_UP_OBQ_5_PKTCNT 0xcc
32842 #define A_UP_IBQ_0_CONFIG 0xd0
32844 #define S_QUESIZE 26
32845 #define M_QUESIZE 0x3fU
32846 #define V_QUESIZE(x) ((x) << S_QUESIZE)
32847 #define G_QUESIZE(x) (((x) >> S_QUESIZE) & M_QUESIZE)
32849 #define S_QUEBASE 8
32850 #define M_QUEBASE 0x3fU
32851 #define V_QUEBASE(x) ((x) << S_QUEBASE)
32852 #define G_QUEBASE(x) (((x) >> S_QUEBASE) & M_QUEBASE)
32854 #define S_QUEDBG8BEN 7
32855 #define V_QUEDBG8BEN(x) ((x) << S_QUEDBG8BEN)
32856 #define F_QUEDBG8BEN V_QUEDBG8BEN(1U)
32858 #define S_QUEBAREADDR 0
32859 #define V_QUEBAREADDR(x) ((x) << S_QUEBAREADDR)
32860 #define F_QUEBAREADDR V_QUEBAREADDR(1U)
32862 #define A_UP_IBQ_0_REALADDR 0xd4
32864 #define S_QUERDADDRWRAP 31
32865 #define V_QUERDADDRWRAP(x) ((x) << S_QUERDADDRWRAP)
32866 #define F_QUERDADDRWRAP V_QUERDADDRWRAP(1U)
32868 #define S_QUEWRADDRWRAP 30
32869 #define V_QUEWRADDRWRAP(x) ((x) << S_QUEWRADDRWRAP)
32870 #define F_QUEWRADDRWRAP V_QUEWRADDRWRAP(1U)
32872 #define S_QUEMEMADDR 3
32873 #define M_QUEMEMADDR 0x7ffU
32874 #define V_QUEMEMADDR(x) ((x) << S_QUEMEMADDR)
32875 #define G_QUEMEMADDR(x) (((x) >> S_QUEMEMADDR) & M_QUEMEMADDR)
32877 #define A_UP_IBQ_1_CONFIG 0xd8
32878 #define A_UP_IBQ_1_REALADDR 0xdc
32879 #define A_UP_IBQ_2_CONFIG 0xe0
32880 #define A_UP_IBQ_2_REALADDR 0xe4
32881 #define A_UP_IBQ_3_CONFIG 0xe8
32882 #define A_UP_IBQ_3_REALADDR 0xec
32883 #define A_UP_IBQ_4_CONFIG 0xf0
32884 #define A_UP_IBQ_4_REALADDR 0xf4
32885 #define A_UP_IBQ_5_CONFIG 0xf8
32886 #define A_UP_IBQ_5_REALADDR 0xfc
32887 #define A_UP_OBQ_0_CONFIG 0x100
32888 #define A_UP_OBQ_0_REALADDR 0x104
32889 #define A_UP_OBQ_1_CONFIG 0x108
32890 #define A_UP_OBQ_1_REALADDR 0x10c
32891 #define A_UP_OBQ_2_CONFIG 0x110
32892 #define A_UP_OBQ_2_REALADDR 0x114
32893 #define A_UP_OBQ_3_CONFIG 0x118
32894 #define A_UP_OBQ_3_REALADDR 0x11c
32895 #define A_UP_OBQ_4_CONFIG 0x120
32896 #define A_UP_OBQ_4_REALADDR 0x124
32897 #define A_UP_OBQ_5_CONFIG 0x128
32898 #define A_UP_OBQ_5_REALADDR 0x12c
32899 #define A_UP_MAILBOX_STATUS 0x130
32901 #define S_MBGEN0 20
32902 #define M_MBGEN0 0xfffU
32903 #define V_MBGEN0(x) ((x) << S_MBGEN0)
32904 #define G_MBGEN0(x) (((x) >> S_MBGEN0) & M_MBGEN0)
32906 #define S_GENTIMERTRIGGER 16
32907 #define M_GENTIMERTRIGGER 0xfU
32908 #define V_GENTIMERTRIGGER(x) ((x) << S_GENTIMERTRIGGER)
32909 #define G_GENTIMERTRIGGER(x) (((x) >> S_GENTIMERTRIGGER) & M_GENTIMERTRIGGER)
32912 #define M_MBGEN1 0xffU
32913 #define V_MBGEN1(x) ((x) << S_MBGEN1)
32914 #define G_MBGEN1(x) (((x) >> S_MBGEN1) & M_MBGEN1)
32916 #define S_MBPFINT 0
32917 #define M_MBPFINT 0xffU
32918 #define V_MBPFINT(x) ((x) << S_MBPFINT)
32919 #define G_MBPFINT(x) (((x) >> S_MBPFINT) & M_MBPFINT)
32921 #define A_UP_UP_DBG_LA_CFG 0x140
32923 #define S_UPDBGLACAPTBUB 31
32924 #define V_UPDBGLACAPTBUB(x) ((x) << S_UPDBGLACAPTBUB)
32925 #define F_UPDBGLACAPTBUB V_UPDBGLACAPTBUB(1U)
32927 #define S_UPDBGLACAPTPCONLY 30
32928 #define V_UPDBGLACAPTPCONLY(x) ((x) << S_UPDBGLACAPTPCONLY)
32929 #define F_UPDBGLACAPTPCONLY V_UPDBGLACAPTPCONLY(1U)
32931 #define S_UPDBGLAMASKSTOP 29
32932 #define V_UPDBGLAMASKSTOP(x) ((x) << S_UPDBGLAMASKSTOP)
32933 #define F_UPDBGLAMASKSTOP V_UPDBGLAMASKSTOP(1U)
32935 #define S_UPDBGLAMASKTRIG 28
32936 #define V_UPDBGLAMASKTRIG(x) ((x) << S_UPDBGLAMASKTRIG)
32937 #define F_UPDBGLAMASKTRIG V_UPDBGLAMASKTRIG(1U)
32939 #define S_UPDBGLAWRPTR 16
32940 #define M_UPDBGLAWRPTR 0xfffU
32941 #define V_UPDBGLAWRPTR(x) ((x) << S_UPDBGLAWRPTR)
32942 #define G_UPDBGLAWRPTR(x) (((x) >> S_UPDBGLAWRPTR) & M_UPDBGLAWRPTR)
32944 #define S_UPDBGLARDPTR 2
32945 #define M_UPDBGLARDPTR 0xfffU
32946 #define V_UPDBGLARDPTR(x) ((x) << S_UPDBGLARDPTR)
32947 #define G_UPDBGLARDPTR(x) (((x) >> S_UPDBGLARDPTR) & M_UPDBGLARDPTR)
32949 #define S_UPDBGLARDEN 1
32950 #define V_UPDBGLARDEN(x) ((x) << S_UPDBGLARDEN)
32951 #define F_UPDBGLARDEN V_UPDBGLARDEN(1U)
32953 #define S_UPDBGLAEN 0
32954 #define V_UPDBGLAEN(x) ((x) << S_UPDBGLAEN)
32955 #define F_UPDBGLAEN V_UPDBGLAEN(1U)
32957 #define S_UPDBGLABUSY 14
32958 #define V_UPDBGLABUSY(x) ((x) << S_UPDBGLABUSY)
32959 #define F_UPDBGLABUSY V_UPDBGLABUSY(1U)
32961 #define A_UP_UP_DBG_LA_DATA 0x144
32962 #define A_UP_PIO_MST_CONFIG 0x148
32965 #define M_FLSRC 0x7U
32966 #define V_FLSRC(x) ((x) << S_FLSRC)
32967 #define G_FLSRC(x) (((x) >> S_FLSRC) & M_FLSRC)
32969 #define S_SEPROT 23
32970 #define V_SEPROT(x) ((x) << S_SEPROT)
32971 #define F_SEPROT V_SEPROT(1U)
32974 #define M_SESRC 0x7U
32975 #define V_SESRC(x) ((x) << S_SESRC)
32976 #define G_SESRC(x) (((x) >> S_SESRC) & M_SESRC)
32979 #define V_UPRGN(x) ((x) << S_UPRGN)
32980 #define F_UPRGN V_UPRGN(1U)
32983 #define M_UPPF 0x7U
32984 #define V_UPPF(x) ((x) << S_UPPF)
32985 #define G_UPPF(x) (((x) >> S_UPPF) & M_UPPF)
32988 #define M_UPRID 0xffffU
32989 #define V_UPRID(x) ((x) << S_UPRID)
32990 #define G_UPRID(x) (((x) >> S_UPRID) & M_UPRID)
32992 #define S_REQVFVLD 27
32993 #define V_REQVFVLD(x) ((x) << S_REQVFVLD)
32994 #define F_REQVFVLD V_REQVFVLD(1U)
32996 #define S_T5_UPRID 0
32997 #define M_T5_UPRID 0xffU
32998 #define V_T5_UPRID(x) ((x) << S_T5_UPRID)
32999 #define G_T5_UPRID(x) (((x) >> S_T5_UPRID) & M_T5_UPRID)
33001 #define A_UP_UP_SELF_CONTROL 0x14c
33003 #define S_UPSELFRESET 0
33004 #define V_UPSELFRESET(x) ((x) << S_UPSELFRESET)
33005 #define F_UPSELFRESET V_UPSELFRESET(1U)
33007 #define A_UP_MAILBOX_PF0_CTL 0x180
33008 #define A_UP_MAILBOX_PF1_CTL 0x190
33009 #define A_UP_MAILBOX_PF2_CTL 0x1a0
33010 #define A_UP_MAILBOX_PF3_CTL 0x1b0
33011 #define A_UP_MAILBOX_PF4_CTL 0x1c0
33012 #define A_UP_MAILBOX_PF5_CTL 0x1d0
33013 #define A_UP_MAILBOX_PF6_CTL 0x1e0
33014 #define A_UP_MAILBOX_PF7_CTL 0x1f0
33015 #define A_UP_TSCH_CHNLN_CLASS_RDY 0x200
33017 #define S_ECO_15444_SGE_DB_BUSY 31
33018 #define V_ECO_15444_SGE_DB_BUSY(x) ((x) << S_ECO_15444_SGE_DB_BUSY)
33019 #define F_ECO_15444_SGE_DB_BUSY V_ECO_15444_SGE_DB_BUSY(1U)
33021 #define S_ECO_15444_PL_INTF_BUSY 30
33022 #define V_ECO_15444_PL_INTF_BUSY(x) ((x) << S_ECO_15444_PL_INTF_BUSY)
33023 #define F_ECO_15444_PL_INTF_BUSY V_ECO_15444_PL_INTF_BUSY(1U)
33025 #define S_TSCHCHNLCRDY 0
33026 #define M_TSCHCHNLCRDY 0x3fffffffU
33027 #define V_TSCHCHNLCRDY(x) ((x) << S_TSCHCHNLCRDY)
33028 #define G_TSCHCHNLCRDY(x) (((x) >> S_TSCHCHNLCRDY) & M_TSCHCHNLCRDY)
33030 #define A_UP_TSCH_CHNLN_CLASS_WATCH_RDY 0x204
33032 #define S_TSCHWRRLIMIT 16
33033 #define M_TSCHWRRLIMIT 0xffffU
33034 #define V_TSCHWRRLIMIT(x) ((x) << S_TSCHWRRLIMIT)
33035 #define G_TSCHWRRLIMIT(x) (((x) >> S_TSCHWRRLIMIT) & M_TSCHWRRLIMIT)
33037 #define S_TSCHCHNLCWRDY 0
33038 #define M_TSCHCHNLCWRDY 0xffffU
33039 #define V_TSCHCHNLCWRDY(x) ((x) << S_TSCHCHNLCWRDY)
33040 #define G_TSCHCHNLCWRDY(x) (((x) >> S_TSCHCHNLCWRDY) & M_TSCHCHNLCWRDY)
33042 #define A_UP_TSCH_CHNLN_CLASS_WATCH_LIST 0x208
33044 #define S_TSCHWRRRELOAD 16
33045 #define M_TSCHWRRRELOAD 0xffffU
33046 #define V_TSCHWRRRELOAD(x) ((x) << S_TSCHWRRRELOAD)
33047 #define G_TSCHWRRRELOAD(x) (((x) >> S_TSCHWRRRELOAD) & M_TSCHWRRRELOAD)
33049 #define S_TSCHCHNLCWATCH 0
33050 #define M_TSCHCHNLCWATCH 0xffffU
33051 #define V_TSCHCHNLCWATCH(x) ((x) << S_TSCHCHNLCWATCH)
33052 #define G_TSCHCHNLCWATCH(x) (((x) >> S_TSCHCHNLCWATCH) & M_TSCHCHNLCWATCH)
33054 #define A_UP_TSCH_CHNLN_CLASS_TAKE 0x20c
33056 #define S_TSCHCHNLCNUM 24
33057 #define M_TSCHCHNLCNUM 0x1fU
33058 #define V_TSCHCHNLCNUM(x) ((x) << S_TSCHCHNLCNUM)
33059 #define G_TSCHCHNLCNUM(x) (((x) >> S_TSCHCHNLCNUM) & M_TSCHCHNLCNUM)
33061 #define S_TSCHCHNLCCNT 0
33062 #define M_TSCHCHNLCCNT 0xffffffU
33063 #define V_TSCHCHNLCCNT(x) ((x) << S_TSCHCHNLCCNT)
33064 #define G_TSCHCHNLCCNT(x) (((x) >> S_TSCHCHNLCCNT) & M_TSCHCHNLCCNT)
33066 #define A_UP_UPLADBGPCCHKDATA_0 0x240
33067 #define A_UP_UPLADBGPCCHKMASK_0 0x244
33068 #define A_UP_UPLADBGPCCHKDATA_1 0x250
33069 #define A_UP_UPLADBGPCCHKMASK_1 0x254
33070 #define A_UP_UPLADBGPCCHKDATA_2 0x260
33071 #define A_UP_UPLADBGPCCHKMASK_2 0x264
33072 #define A_UP_UPLADBGPCCHKDATA_3 0x270
33073 #define A_UP_UPLADBGPCCHKMASK_3 0x274
33074 #define A_UP_IBQ_0_SHADOW_RDADDR 0x280
33075 #define A_UP_IBQ_0_SHADOW_WRADDR 0x284
33076 #define A_UP_IBQ_0_SHADOW_STATUS 0x288
33077 #define A_UP_IBQ_0_SHADOW_PKTCNT 0x28c
33078 #define A_UP_IBQ_1_SHADOW_RDADDR 0x290
33079 #define A_UP_IBQ_1_SHADOW_WRADDR 0x294
33080 #define A_UP_IBQ_1_SHADOW_STATUS 0x298
33081 #define A_UP_IBQ_1_SHADOW_PKTCNT 0x29c
33082 #define A_UP_IBQ_2_SHADOW_RDADDR 0x2a0
33083 #define A_UP_IBQ_2_SHADOW_WRADDR 0x2a4
33084 #define A_UP_IBQ_2_SHADOW_STATUS 0x2a8
33085 #define A_UP_IBQ_2_SHADOW_PKTCNT 0x2ac
33086 #define A_UP_IBQ_3_SHADOW_RDADDR 0x2b0
33087 #define A_UP_IBQ_3_SHADOW_WRADDR 0x2b4
33088 #define A_UP_IBQ_3_SHADOW_STATUS 0x2b8
33089 #define A_UP_IBQ_3_SHADOW_PKTCNT 0x2bc
33090 #define A_UP_IBQ_4_SHADOW_RDADDR 0x2c0
33091 #define A_UP_IBQ_4_SHADOW_WRADDR 0x2c4
33092 #define A_UP_IBQ_4_SHADOW_STATUS 0x2c8
33093 #define A_UP_IBQ_4_SHADOW_PKTCNT 0x2cc
33094 #define A_UP_IBQ_5_SHADOW_RDADDR 0x2d0
33095 #define A_UP_IBQ_5_SHADOW_WRADDR 0x2d4
33096 #define A_UP_IBQ_5_SHADOW_STATUS 0x2d8
33097 #define A_UP_IBQ_5_SHADOW_PKTCNT 0x2dc
33098 #define A_UP_OBQ_0_SHADOW_RDADDR 0x2e0
33099 #define A_UP_OBQ_0_SHADOW_WRADDR 0x2e4
33100 #define A_UP_OBQ_0_SHADOW_STATUS 0x2e8
33101 #define A_UP_OBQ_0_SHADOW_PKTCNT 0x2ec
33102 #define A_UP_OBQ_1_SHADOW_RDADDR 0x2f0
33103 #define A_UP_OBQ_1_SHADOW_WRADDR 0x2f4
33104 #define A_UP_OBQ_1_SHADOW_STATUS 0x2f8
33105 #define A_UP_OBQ_1_SHADOW_PKTCNT 0x2fc
33106 #define A_UP_OBQ_2_SHADOW_RDADDR 0x300
33107 #define A_UP_OBQ_2_SHADOW_WRADDR 0x304
33108 #define A_UP_OBQ_2_SHADOW_STATUS 0x308
33109 #define A_UP_OBQ_2_SHADOW_PKTCNT 0x30c
33110 #define A_UP_OBQ_3_SHADOW_RDADDR 0x310
33111 #define A_UP_OBQ_3_SHADOW_WRADDR 0x314
33112 #define A_UP_OBQ_3_SHADOW_STATUS 0x318
33113 #define A_UP_OBQ_3_SHADOW_PKTCNT 0x31c
33114 #define A_UP_OBQ_4_SHADOW_RDADDR 0x320
33115 #define A_UP_OBQ_4_SHADOW_WRADDR 0x324
33116 #define A_UP_OBQ_4_SHADOW_STATUS 0x328
33117 #define A_UP_OBQ_4_SHADOW_PKTCNT 0x32c
33118 #define A_UP_OBQ_5_SHADOW_RDADDR 0x330
33119 #define A_UP_OBQ_5_SHADOW_WRADDR 0x334
33120 #define A_UP_OBQ_5_SHADOW_STATUS 0x338
33121 #define A_UP_OBQ_5_SHADOW_PKTCNT 0x33c
33122 #define A_UP_OBQ_6_SHADOW_RDADDR 0x340
33123 #define A_UP_OBQ_6_SHADOW_WRADDR 0x344
33124 #define A_UP_OBQ_6_SHADOW_STATUS 0x348
33125 #define A_UP_OBQ_6_SHADOW_PKTCNT 0x34c
33126 #define A_UP_OBQ_7_SHADOW_RDADDR 0x350
33127 #define A_UP_OBQ_7_SHADOW_WRADDR 0x354
33128 #define A_UP_OBQ_7_SHADOW_STATUS 0x358
33129 #define A_UP_OBQ_7_SHADOW_PKTCNT 0x35c
33130 #define A_UP_IBQ_0_SHADOW_CONFIG 0x360
33131 #define A_UP_IBQ_0_SHADOW_REALADDR 0x364
33132 #define A_UP_IBQ_1_SHADOW_CONFIG 0x368
33133 #define A_UP_IBQ_1_SHADOW_REALADDR 0x36c
33134 #define A_UP_IBQ_2_SHADOW_CONFIG 0x370
33135 #define A_UP_IBQ_2_SHADOW_REALADDR 0x374
33136 #define A_UP_IBQ_3_SHADOW_CONFIG 0x378
33137 #define A_UP_IBQ_3_SHADOW_REALADDR 0x37c
33138 #define A_UP_IBQ_4_SHADOW_CONFIG 0x380
33139 #define A_UP_IBQ_4_SHADOW_REALADDR 0x384
33140 #define A_UP_IBQ_5_SHADOW_CONFIG 0x388
33141 #define A_UP_IBQ_5_SHADOW_REALADDR 0x38c
33142 #define A_UP_OBQ_0_SHADOW_CONFIG 0x390
33143 #define A_UP_OBQ_0_SHADOW_REALADDR 0x394
33144 #define A_UP_OBQ_1_SHADOW_CONFIG 0x398
33145 #define A_UP_OBQ_1_SHADOW_REALADDR 0x39c
33146 #define A_UP_OBQ_2_SHADOW_CONFIG 0x3a0
33147 #define A_UP_OBQ_2_SHADOW_REALADDR 0x3a4
33148 #define A_UP_OBQ_3_SHADOW_CONFIG 0x3a8
33149 #define A_UP_OBQ_3_SHADOW_REALADDR 0x3ac
33150 #define A_UP_OBQ_4_SHADOW_CONFIG 0x3b0
33151 #define A_UP_OBQ_4_SHADOW_REALADDR 0x3b4
33152 #define A_UP_OBQ_5_SHADOW_CONFIG 0x3b8
33153 #define A_UP_OBQ_5_SHADOW_REALADDR 0x3bc
33154 #define A_UP_OBQ_6_SHADOW_CONFIG 0x3c0
33155 #define A_UP_OBQ_6_SHADOW_REALADDR 0x3c4
33156 #define A_UP_OBQ_7_SHADOW_CONFIG 0x3c8
33157 #define A_UP_OBQ_7_SHADOW_REALADDR 0x3cc
33159 /* registers for module CIM_CTL */
33160 #define CIM_CTL_BASE_ADDR 0x0
33162 #define A_CIM_CTL_CONFIG 0x0
33164 #define S_AUTOPREFLOC 17
33165 #define M_AUTOPREFLOC 0x1fU
33166 #define V_AUTOPREFLOC(x) ((x) << S_AUTOPREFLOC)
33167 #define G_AUTOPREFLOC(x) (((x) >> S_AUTOPREFLOC) & M_AUTOPREFLOC)
33169 #define S_AUTOPREFEN 16
33170 #define V_AUTOPREFEN(x) ((x) << S_AUTOPREFEN)
33171 #define F_AUTOPREFEN V_AUTOPREFEN(1U)
33173 #define S_DISMATIMEOUT 15
33174 #define V_DISMATIMEOUT(x) ((x) << S_DISMATIMEOUT)
33175 #define F_DISMATIMEOUT V_DISMATIMEOUT(1U)
33177 #define S_PIFMULTICMD 8
33178 #define V_PIFMULTICMD(x) ((x) << S_PIFMULTICMD)
33179 #define F_PIFMULTICMD V_PIFMULTICMD(1U)
33181 #define S_UPSELFRESETTOUT 7
33182 #define V_UPSELFRESETTOUT(x) ((x) << S_UPSELFRESETTOUT)
33183 #define F_UPSELFRESETTOUT V_UPSELFRESETTOUT(1U)
33185 #define S_PLSWAPDISWR 6
33186 #define V_PLSWAPDISWR(x) ((x) << S_PLSWAPDISWR)
33187 #define F_PLSWAPDISWR V_PLSWAPDISWR(1U)
33189 #define S_PLSWAPDISRD 5
33190 #define V_PLSWAPDISRD(x) ((x) << S_PLSWAPDISRD)
33191 #define F_PLSWAPDISRD V_PLSWAPDISRD(1U)
33194 #define V_PREFEN(x) ((x) << S_PREFEN)
33195 #define F_PREFEN V_PREFEN(1U)
33197 #define A_CIM_CTL_PREFADDR 0x4
33198 #define A_CIM_CTL_ALLOCADDR 0x8
33199 #define A_CIM_CTL_INVLDTADDR 0xc
33200 #define A_CIM_CTL_STATIC_PREFADDR0 0x10
33201 #define A_CIM_CTL_STATIC_PREFADDR1 0x14
33202 #define A_CIM_CTL_STATIC_PREFADDR2 0x18
33203 #define A_CIM_CTL_STATIC_PREFADDR3 0x1c
33204 #define A_CIM_CTL_STATIC_PREFADDR4 0x20
33205 #define A_CIM_CTL_STATIC_PREFADDR5 0x24
33206 #define A_CIM_CTL_STATIC_PREFADDR6 0x28
33207 #define A_CIM_CTL_STATIC_PREFADDR7 0x2c
33208 #define A_CIM_CTL_STATIC_PREFADDR8 0x30
33209 #define A_CIM_CTL_STATIC_PREFADDR9 0x34
33210 #define A_CIM_CTL_STATIC_PREFADDR10 0x38
33211 #define A_CIM_CTL_STATIC_PREFADDR11 0x3c
33212 #define A_CIM_CTL_STATIC_PREFADDR12 0x40
33213 #define A_CIM_CTL_STATIC_PREFADDR13 0x44
33214 #define A_CIM_CTL_STATIC_PREFADDR14 0x48
33215 #define A_CIM_CTL_STATIC_PREFADDR15 0x4c
33216 #define A_CIM_CTL_STATIC_ALLOCADDR0 0x50
33217 #define A_CIM_CTL_STATIC_ALLOCADDR1 0x54
33218 #define A_CIM_CTL_STATIC_ALLOCADDR2 0x58
33219 #define A_CIM_CTL_STATIC_ALLOCADDR3 0x5c
33220 #define A_CIM_CTL_STATIC_ALLOCADDR4 0x60
33221 #define A_CIM_CTL_STATIC_ALLOCADDR5 0x64
33222 #define A_CIM_CTL_STATIC_ALLOCADDR6 0x68
33223 #define A_CIM_CTL_STATIC_ALLOCADDR7 0x6c
33224 #define A_CIM_CTL_STATIC_ALLOCADDR8 0x70
33225 #define A_CIM_CTL_STATIC_ALLOCADDR9 0x74
33226 #define A_CIM_CTL_STATIC_ALLOCADDR10 0x78
33227 #define A_CIM_CTL_STATIC_ALLOCADDR11 0x7c
33228 #define A_CIM_CTL_STATIC_ALLOCADDR12 0x80
33229 #define A_CIM_CTL_STATIC_ALLOCADDR13 0x84
33230 #define A_CIM_CTL_STATIC_ALLOCADDR14 0x88
33231 #define A_CIM_CTL_STATIC_ALLOCADDR15 0x8c
33232 #define A_CIM_CTL_FIFO_CNT 0x90
33234 #define S_CTLFIFOCNT 0
33235 #define M_CTLFIFOCNT 0xfU
33236 #define V_CTLFIFOCNT(x) ((x) << S_CTLFIFOCNT)
33237 #define G_CTLFIFOCNT(x) (((x) >> S_CTLFIFOCNT) & M_CTLFIFOCNT)
33239 #define A_CIM_CTL_GLB_TIMER 0x94
33240 #define A_CIM_CTL_TIMER0 0x98
33241 #define A_CIM_CTL_TIMER1 0x9c
33242 #define A_CIM_CTL_GEN0 0xa0
33243 #define A_CIM_CTL_GEN1 0xa4
33244 #define A_CIM_CTL_GEN2 0xa8
33245 #define A_CIM_CTL_GEN3 0xac
33246 #define A_CIM_CTL_GLB_TIMER_TICK 0xb0
33247 #define A_CIM_CTL_GEN_TIMER0_CTL 0xb4
33249 #define S_GENTIMERRUN 7
33250 #define V_GENTIMERRUN(x) ((x) << S_GENTIMERRUN)
33251 #define F_GENTIMERRUN V_GENTIMERRUN(1U)
33253 #define S_GENTIMERTRIG 6
33254 #define V_GENTIMERTRIG(x) ((x) << S_GENTIMERTRIG)
33255 #define F_GENTIMERTRIG V_GENTIMERTRIG(1U)
33257 #define S_GENTIMERACT 4
33258 #define M_GENTIMERACT 0x3U
33259 #define V_GENTIMERACT(x) ((x) << S_GENTIMERACT)
33260 #define G_GENTIMERACT(x) (((x) >> S_GENTIMERACT) & M_GENTIMERACT)
33262 #define S_GENTIMERCFG 2
33263 #define M_GENTIMERCFG 0x3U
33264 #define V_GENTIMERCFG(x) ((x) << S_GENTIMERCFG)
33265 #define G_GENTIMERCFG(x) (((x) >> S_GENTIMERCFG) & M_GENTIMERCFG)
33267 #define S_GENTIMERSTOP 1
33268 #define V_GENTIMERSTOP(x) ((x) << S_GENTIMERSTOP)
33269 #define F_GENTIMERSTOP V_GENTIMERSTOP(1U)
33271 #define S_GENTIMERSTRT 0
33272 #define V_GENTIMERSTRT(x) ((x) << S_GENTIMERSTRT)
33273 #define F_GENTIMERSTRT V_GENTIMERSTRT(1U)
33275 #define A_CIM_CTL_GEN_TIMER0 0xb8
33276 #define A_CIM_CTL_GEN_TIMER1_CTL 0xbc
33277 #define A_CIM_CTL_GEN_TIMER1 0xc0
33278 #define A_CIM_CTL_GEN_TIMER2_CTL 0xc4
33279 #define A_CIM_CTL_GEN_TIMER2 0xc8
33280 #define A_CIM_CTL_GEN_TIMER3_CTL 0xcc
33281 #define A_CIM_CTL_GEN_TIMER3 0xd0
33282 #define A_CIM_CTL_MAILBOX_VF_STATUS 0xe0
33283 #define A_CIM_CTL_MAILBOX_VFN_CTL 0x100
33284 #define A_CIM_CTL_TSCH_CHNLN_CTL 0x900
33286 #define S_TSCHNLEN 31
33287 #define V_TSCHNLEN(x) ((x) << S_TSCHNLEN)
33288 #define F_TSCHNLEN V_TSCHNLEN(1U)
33290 #define S_TSCHNRESET 30
33291 #define V_TSCHNRESET(x) ((x) << S_TSCHNRESET)
33292 #define F_TSCHNRESET V_TSCHNRESET(1U)
33294 #define A_CIM_CTL_TSCH_CHNLN_TICK 0x904
33296 #define S_TSCHNLTICK 0
33297 #define M_TSCHNLTICK 0xffffU
33298 #define V_TSCHNLTICK(x) ((x) << S_TSCHNLTICK)
33299 #define G_TSCHNLTICK(x) (((x) >> S_TSCHNLTICK) & M_TSCHNLTICK)
33301 #define A_CIM_CTL_TSCH_CHNLN_CLASS_ENABLE_A 0x908
33303 #define S_TSC15WRREN 31
33304 #define V_TSC15WRREN(x) ((x) << S_TSC15WRREN)
33305 #define F_TSC15WRREN V_TSC15WRREN(1U)
33307 #define S_TSC15RATEEN 30
33308 #define V_TSC15RATEEN(x) ((x) << S_TSC15RATEEN)
33309 #define F_TSC15RATEEN V_TSC15RATEEN(1U)
33311 #define S_TSC14WRREN 29
33312 #define V_TSC14WRREN(x) ((x) << S_TSC14WRREN)
33313 #define F_TSC14WRREN V_TSC14WRREN(1U)
33315 #define S_TSC14RATEEN 28
33316 #define V_TSC14RATEEN(x) ((x) << S_TSC14RATEEN)
33317 #define F_TSC14RATEEN V_TSC14RATEEN(1U)
33319 #define S_TSC13WRREN 27
33320 #define V_TSC13WRREN(x) ((x) << S_TSC13WRREN)
33321 #define F_TSC13WRREN V_TSC13WRREN(1U)
33323 #define S_TSC13RATEEN 26
33324 #define V_TSC13RATEEN(x) ((x) << S_TSC13RATEEN)
33325 #define F_TSC13RATEEN V_TSC13RATEEN(1U)
33327 #define S_TSC12WRREN 25
33328 #define V_TSC12WRREN(x) ((x) << S_TSC12WRREN)
33329 #define F_TSC12WRREN V_TSC12WRREN(1U)
33331 #define S_TSC12RATEEN 24
33332 #define V_TSC12RATEEN(x) ((x) << S_TSC12RATEEN)
33333 #define F_TSC12RATEEN V_TSC12RATEEN(1U)
33335 #define S_TSC11WRREN 23
33336 #define V_TSC11WRREN(x) ((x) << S_TSC11WRREN)
33337 #define F_TSC11WRREN V_TSC11WRREN(1U)
33339 #define S_TSC11RATEEN 22
33340 #define V_TSC11RATEEN(x) ((x) << S_TSC11RATEEN)
33341 #define F_TSC11RATEEN V_TSC11RATEEN(1U)
33343 #define S_TSC10WRREN 21
33344 #define V_TSC10WRREN(x) ((x) << S_TSC10WRREN)
33345 #define F_TSC10WRREN V_TSC10WRREN(1U)
33347 #define S_TSC10RATEEN 20
33348 #define V_TSC10RATEEN(x) ((x) << S_TSC10RATEEN)
33349 #define F_TSC10RATEEN V_TSC10RATEEN(1U)
33351 #define S_TSC9WRREN 19
33352 #define V_TSC9WRREN(x) ((x) << S_TSC9WRREN)
33353 #define F_TSC9WRREN V_TSC9WRREN(1U)
33355 #define S_TSC9RATEEN 18
33356 #define V_TSC9RATEEN(x) ((x) << S_TSC9RATEEN)
33357 #define F_TSC9RATEEN V_TSC9RATEEN(1U)
33359 #define S_TSC8WRREN 17
33360 #define V_TSC8WRREN(x) ((x) << S_TSC8WRREN)
33361 #define F_TSC8WRREN V_TSC8WRREN(1U)
33363 #define S_TSC8RATEEN 16
33364 #define V_TSC8RATEEN(x) ((x) << S_TSC8RATEEN)
33365 #define F_TSC8RATEEN V_TSC8RATEEN(1U)
33367 #define S_TSC7WRREN 15
33368 #define V_TSC7WRREN(x) ((x) << S_TSC7WRREN)
33369 #define F_TSC7WRREN V_TSC7WRREN(1U)
33371 #define S_TSC7RATEEN 14
33372 #define V_TSC7RATEEN(x) ((x) << S_TSC7RATEEN)
33373 #define F_TSC7RATEEN V_TSC7RATEEN(1U)
33375 #define S_TSC6WRREN 13
33376 #define V_TSC6WRREN(x) ((x) << S_TSC6WRREN)
33377 #define F_TSC6WRREN V_TSC6WRREN(1U)
33379 #define S_TSC6RATEEN 12
33380 #define V_TSC6RATEEN(x) ((x) << S_TSC6RATEEN)
33381 #define F_TSC6RATEEN V_TSC6RATEEN(1U)
33383 #define S_TSC5WRREN 11
33384 #define V_TSC5WRREN(x) ((x) << S_TSC5WRREN)
33385 #define F_TSC5WRREN V_TSC5WRREN(1U)
33387 #define S_TSC5RATEEN 10
33388 #define V_TSC5RATEEN(x) ((x) << S_TSC5RATEEN)
33389 #define F_TSC5RATEEN V_TSC5RATEEN(1U)
33391 #define S_TSC4WRREN 9
33392 #define V_TSC4WRREN(x) ((x) << S_TSC4WRREN)
33393 #define F_TSC4WRREN V_TSC4WRREN(1U)
33395 #define S_TSC4RATEEN 8
33396 #define V_TSC4RATEEN(x) ((x) << S_TSC4RATEEN)
33397 #define F_TSC4RATEEN V_TSC4RATEEN(1U)
33399 #define S_TSC3WRREN 7
33400 #define V_TSC3WRREN(x) ((x) << S_TSC3WRREN)
33401 #define F_TSC3WRREN V_TSC3WRREN(1U)
33403 #define S_TSC3RATEEN 6
33404 #define V_TSC3RATEEN(x) ((x) << S_TSC3RATEEN)
33405 #define F_TSC3RATEEN V_TSC3RATEEN(1U)
33407 #define S_TSC2WRREN 5
33408 #define V_TSC2WRREN(x) ((x) << S_TSC2WRREN)
33409 #define F_TSC2WRREN V_TSC2WRREN(1U)
33411 #define S_TSC2RATEEN 4
33412 #define V_TSC2RATEEN(x) ((x) << S_TSC2RATEEN)
33413 #define F_TSC2RATEEN V_TSC2RATEEN(1U)
33415 #define S_TSC1WRREN 3
33416 #define V_TSC1WRREN(x) ((x) << S_TSC1WRREN)
33417 #define F_TSC1WRREN V_TSC1WRREN(1U)
33419 #define S_TSC1RATEEN 2
33420 #define V_TSC1RATEEN(x) ((x) << S_TSC1RATEEN)
33421 #define F_TSC1RATEEN V_TSC1RATEEN(1U)
33423 #define S_TSC0WRREN 1
33424 #define V_TSC0WRREN(x) ((x) << S_TSC0WRREN)
33425 #define F_TSC0WRREN V_TSC0WRREN(1U)
33427 #define S_TSC0RATEEN 0
33428 #define V_TSC0RATEEN(x) ((x) << S_TSC0RATEEN)
33429 #define F_TSC0RATEEN V_TSC0RATEEN(1U)
33431 #define A_CIM_CTL_TSCH_MIN_MAX_EN 0x90c
33433 #define S_MIN_MAX_EN 0
33434 #define V_MIN_MAX_EN(x) ((x) << S_MIN_MAX_EN)
33435 #define F_MIN_MAX_EN V_MIN_MAX_EN(1U)
33437 #define A_CIM_CTL_TSCH_CHNLN_RATE_LIMITER 0x910
33439 #define S_TSCHNLRATENEG 31
33440 #define V_TSCHNLRATENEG(x) ((x) << S_TSCHNLRATENEG)
33441 #define F_TSCHNLRATENEG V_TSCHNLRATENEG(1U)
33443 #define S_TSCHNLRATEL 0
33444 #define M_TSCHNLRATEL 0x7fffffffU
33445 #define V_TSCHNLRATEL(x) ((x) << S_TSCHNLRATEL)
33446 #define G_TSCHNLRATEL(x) (((x) >> S_TSCHNLRATEL) & M_TSCHNLRATEL)
33448 #define A_CIM_CTL_TSCH_CHNLN_RATE_PROPERTIES 0x914
33450 #define S_TSCHNLRMAX 16
33451 #define M_TSCHNLRMAX 0xffffU
33452 #define V_TSCHNLRMAX(x) ((x) << S_TSCHNLRMAX)
33453 #define G_TSCHNLRMAX(x) (((x) >> S_TSCHNLRMAX) & M_TSCHNLRMAX)
33455 #define S_TSCHNLRINCR 0
33456 #define M_TSCHNLRINCR 0xffffU
33457 #define V_TSCHNLRINCR(x) ((x) << S_TSCHNLRINCR)
33458 #define G_TSCHNLRINCR(x) (((x) >> S_TSCHNLRINCR) & M_TSCHNLRINCR)
33460 #define A_CIM_CTL_TSCH_CHNLN_WRR 0x918
33461 #define A_CIM_CTL_TSCH_CHNLN_WEIGHT 0x91c
33463 #define S_TSCHNLWEIGHT 0
33464 #define M_TSCHNLWEIGHT 0x3fffffU
33465 #define V_TSCHNLWEIGHT(x) ((x) << S_TSCHNLWEIGHT)
33466 #define G_TSCHNLWEIGHT(x) (((x) >> S_TSCHNLWEIGHT) & M_TSCHNLWEIGHT)
33468 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_LIMITER 0x920
33470 #define S_TSCCLRATENEG 31
33471 #define V_TSCCLRATENEG(x) ((x) << S_TSCCLRATENEG)
33472 #define F_TSCCLRATENEG V_TSCCLRATENEG(1U)
33474 #define S_TSCCLRATEL 0
33475 #define M_TSCCLRATEL 0xffffffU
33476 #define V_TSCCLRATEL(x) ((x) << S_TSCCLRATEL)
33477 #define G_TSCCLRATEL(x) (((x) >> S_TSCCLRATEL) & M_TSCCLRATEL)
33479 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_RATE_PROPERTIES 0x924
33481 #define S_TSCCLRMAX 16
33482 #define M_TSCCLRMAX 0xffffU
33483 #define V_TSCCLRMAX(x) ((x) << S_TSCCLRMAX)
33484 #define G_TSCCLRMAX(x) (((x) >> S_TSCCLRMAX) & M_TSCCLRMAX)
33486 #define S_TSCCLRINCR 0
33487 #define M_TSCCLRINCR 0xffffU
33488 #define V_TSCCLRINCR(x) ((x) << S_TSCCLRINCR)
33489 #define G_TSCCLRINCR(x) (((x) >> S_TSCCLRINCR) & M_TSCCLRINCR)
33491 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WRR 0x928
33493 #define S_TSCCLWRRNEG 31
33494 #define V_TSCCLWRRNEG(x) ((x) << S_TSCCLWRRNEG)
33495 #define F_TSCCLWRRNEG V_TSCCLWRRNEG(1U)
33497 #define S_TSCCLWRR 0
33498 #define M_TSCCLWRR 0x3ffffffU
33499 #define V_TSCCLWRR(x) ((x) << S_TSCCLWRR)
33500 #define G_TSCCLWRR(x) (((x) >> S_TSCCLWRR) & M_TSCCLWRR)
33502 #define A_CIM_CTL_TSCH_CHNLN_CLASSM_WEIGHT 0x92c
33504 #define S_TSCCLWEIGHT 0
33505 #define M_TSCCLWEIGHT 0xffffU
33506 #define V_TSCCLWEIGHT(x) ((x) << S_TSCCLWEIGHT)
33507 #define G_TSCCLWEIGHT(x) (((x) >> S_TSCCLWEIGHT) & M_TSCCLWEIGHT)
33509 #define A_CIM_CTL_MAILBOX_PF0_CTL 0xd84
33510 #define A_CIM_CTL_MAILBOX_PF1_CTL 0xd88
33511 #define A_CIM_CTL_MAILBOX_PF2_CTL 0xd8c
33512 #define A_CIM_CTL_MAILBOX_PF3_CTL 0xd90
33513 #define A_CIM_CTL_MAILBOX_PF4_CTL 0xd94
33514 #define A_CIM_CTL_MAILBOX_PF5_CTL 0xd98
33515 #define A_CIM_CTL_MAILBOX_PF6_CTL 0xd9c
33516 #define A_CIM_CTL_MAILBOX_PF7_CTL 0xda0
33517 #define A_CIM_CTL_MAILBOX_CTL_OWNER_COPY 0xda4
33519 #define S_PF7_OWNER_PL 15
33520 #define V_PF7_OWNER_PL(x) ((x) << S_PF7_OWNER_PL)
33521 #define F_PF7_OWNER_PL V_PF7_OWNER_PL(1U)
33523 #define S_PF6_OWNER_PL 14
33524 #define V_PF6_OWNER_PL(x) ((x) << S_PF6_OWNER_PL)
33525 #define F_PF6_OWNER_PL V_PF6_OWNER_PL(1U)
33527 #define S_PF5_OWNER_PL 13
33528 #define V_PF5_OWNER_PL(x) ((x) << S_PF5_OWNER_PL)
33529 #define F_PF5_OWNER_PL V_PF5_OWNER_PL(1U)
33531 #define S_PF4_OWNER_PL 12
33532 #define V_PF4_OWNER_PL(x) ((x) << S_PF4_OWNER_PL)
33533 #define F_PF4_OWNER_PL V_PF4_OWNER_PL(1U)
33535 #define S_PF3_OWNER_PL 11
33536 #define V_PF3_OWNER_PL(x) ((x) << S_PF3_OWNER_PL)
33537 #define F_PF3_OWNER_PL V_PF3_OWNER_PL(1U)
33539 #define S_PF2_OWNER_PL 10
33540 #define V_PF2_OWNER_PL(x) ((x) << S_PF2_OWNER_PL)
33541 #define F_PF2_OWNER_PL V_PF2_OWNER_PL(1U)
33543 #define S_PF1_OWNER_PL 9
33544 #define V_PF1_OWNER_PL(x) ((x) << S_PF1_OWNER_PL)
33545 #define F_PF1_OWNER_PL V_PF1_OWNER_PL(1U)
33547 #define S_PF0_OWNER_PL 8
33548 #define V_PF0_OWNER_PL(x) ((x) << S_PF0_OWNER_PL)
33549 #define F_PF0_OWNER_PL V_PF0_OWNER_PL(1U)
33551 #define S_PF7_OWNER_UP 7
33552 #define V_PF7_OWNER_UP(x) ((x) << S_PF7_OWNER_UP)
33553 #define F_PF7_OWNER_UP V_PF7_OWNER_UP(1U)
33555 #define S_PF6_OWNER_UP 6
33556 #define V_PF6_OWNER_UP(x) ((x) << S_PF6_OWNER_UP)
33557 #define F_PF6_OWNER_UP V_PF6_OWNER_UP(1U)
33559 #define S_PF5_OWNER_UP 5
33560 #define V_PF5_OWNER_UP(x) ((x) << S_PF5_OWNER_UP)
33561 #define F_PF5_OWNER_UP V_PF5_OWNER_UP(1U)
33563 #define S_PF4_OWNER_UP 4
33564 #define V_PF4_OWNER_UP(x) ((x) << S_PF4_OWNER_UP)
33565 #define F_PF4_OWNER_UP V_PF4_OWNER_UP(1U)
33567 #define S_PF3_OWNER_UP 3
33568 #define V_PF3_OWNER_UP(x) ((x) << S_PF3_OWNER_UP)
33569 #define F_PF3_OWNER_UP V_PF3_OWNER_UP(1U)
33571 #define S_PF2_OWNER_UP 2
33572 #define V_PF2_OWNER_UP(x) ((x) << S_PF2_OWNER_UP)
33573 #define F_PF2_OWNER_UP V_PF2_OWNER_UP(1U)
33575 #define S_PF1_OWNER_UP 1
33576 #define V_PF1_OWNER_UP(x) ((x) << S_PF1_OWNER_UP)
33577 #define F_PF1_OWNER_UP V_PF1_OWNER_UP(1U)
33579 #define S_PF0_OWNER_UP 0
33580 #define V_PF0_OWNER_UP(x) ((x) << S_PF0_OWNER_UP)
33581 #define F_PF0_OWNER_UP V_PF0_OWNER_UP(1U)
33583 #define A_CIM_CTL_PIO_MST_CONFIG 0xda8
33585 #define S_T5_CTLRID 0
33586 #define M_T5_CTLRID 0xffU
33587 #define V_T5_CTLRID(x) ((x) << S_T5_CTLRID)
33588 #define G_T5_CTLRID(x) (((x) >> S_T5_CTLRID) & M_T5_CTLRID)
33590 /* registers for module MAC */
33591 #define MAC_BASE_ADDR 0x0
33593 #define A_MAC_PORT_CFG 0x800
33595 #define S_MAC_CLK_SEL 29
33596 #define M_MAC_CLK_SEL 0x7U
33597 #define V_MAC_CLK_SEL(x) ((x) << S_MAC_CLK_SEL)
33598 #define G_MAC_CLK_SEL(x) (((x) >> S_MAC_CLK_SEL) & M_MAC_CLK_SEL)
33600 #define S_SMUXTXSEL 9
33601 #define V_SMUXTXSEL(x) ((x) << S_SMUXTXSEL)
33602 #define F_SMUXTXSEL V_SMUXTXSEL(1U)
33604 #define S_SMUXRXSEL 8
33605 #define V_SMUXRXSEL(x) ((x) << S_SMUXRXSEL)
33606 #define F_SMUXRXSEL V_SMUXRXSEL(1U)
33608 #define S_PORTSPEED 4
33609 #define M_PORTSPEED 0x3U
33610 #define V_PORTSPEED(x) ((x) << S_PORTSPEED)
33611 #define G_PORTSPEED(x) (((x) >> S_PORTSPEED) & M_PORTSPEED)
33613 #define A_MAC_PORT_RESET_CTRL 0x804
33615 #define S_TWGDSK_HSSC16B 31
33616 #define V_TWGDSK_HSSC16B(x) ((x) << S_TWGDSK_HSSC16B)
33617 #define F_TWGDSK_HSSC16B V_TWGDSK_HSSC16B(1U)
33619 #define S_EEE_RESET 30
33620 #define V_EEE_RESET(x) ((x) << S_EEE_RESET)
33621 #define F_EEE_RESET V_EEE_RESET(1U)
33623 #define S_PTP_TIMER 29
33624 #define V_PTP_TIMER(x) ((x) << S_PTP_TIMER)
33625 #define F_PTP_TIMER V_PTP_TIMER(1U)
33627 #define S_MTIPREFRESET 28
33628 #define V_MTIPREFRESET(x) ((x) << S_MTIPREFRESET)
33629 #define F_MTIPREFRESET V_MTIPREFRESET(1U)
33631 #define S_MTIPTXFFRESET 27
33632 #define V_MTIPTXFFRESET(x) ((x) << S_MTIPTXFFRESET)
33633 #define F_MTIPTXFFRESET V_MTIPTXFFRESET(1U)
33635 #define S_MTIPRXFFRESET 26
33636 #define V_MTIPRXFFRESET(x) ((x) << S_MTIPRXFFRESET)
33637 #define F_MTIPRXFFRESET V_MTIPRXFFRESET(1U)
33639 #define S_MTIPREGRESET 25
33640 #define V_MTIPREGRESET(x) ((x) << S_MTIPREGRESET)
33641 #define F_MTIPREGRESET V_MTIPREGRESET(1U)
33643 #define S_AEC3RESET 23
33644 #define V_AEC3RESET(x) ((x) << S_AEC3RESET)
33645 #define F_AEC3RESET V_AEC3RESET(1U)
33647 #define S_AEC2RESET 22
33648 #define V_AEC2RESET(x) ((x) << S_AEC2RESET)
33649 #define F_AEC2RESET V_AEC2RESET(1U)
33651 #define S_AEC1RESET 21
33652 #define V_AEC1RESET(x) ((x) << S_AEC1RESET)
33653 #define F_AEC1RESET V_AEC1RESET(1U)
33655 #define S_AEC0RESET 20
33656 #define V_AEC0RESET(x) ((x) << S_AEC0RESET)
33657 #define F_AEC0RESET V_AEC0RESET(1U)
33659 #define S_AET3RESET 19
33660 #define V_AET3RESET(x) ((x) << S_AET3RESET)
33661 #define F_AET3RESET V_AET3RESET(1U)
33663 #define S_AET2RESET 18
33664 #define V_AET2RESET(x) ((x) << S_AET2RESET)
33665 #define F_AET2RESET V_AET2RESET(1U)
33667 #define S_AET1RESET 17
33668 #define V_AET1RESET(x) ((x) << S_AET1RESET)
33669 #define F_AET1RESET V_AET1RESET(1U)
33671 #define S_AET0RESET 16
33672 #define V_AET0RESET(x) ((x) << S_AET0RESET)
33673 #define F_AET0RESET V_AET0RESET(1U)
33675 #define S_TXIF_RESET 12
33676 #define V_TXIF_RESET(x) ((x) << S_TXIF_RESET)
33677 #define F_TXIF_RESET V_TXIF_RESET(1U)
33679 #define S_RXIF_RESET 11
33680 #define V_RXIF_RESET(x) ((x) << S_RXIF_RESET)
33681 #define F_RXIF_RESET V_RXIF_RESET(1U)
33683 #define S_MTIPSD3TXRST 9
33684 #define V_MTIPSD3TXRST(x) ((x) << S_MTIPSD3TXRST)
33685 #define F_MTIPSD3TXRST V_MTIPSD3TXRST(1U)
33687 #define S_MTIPSD2TXRST 8
33688 #define V_MTIPSD2TXRST(x) ((x) << S_MTIPSD2TXRST)
33689 #define F_MTIPSD2TXRST V_MTIPSD2TXRST(1U)
33691 #define S_MTIPSD1TXRST 7
33692 #define V_MTIPSD1TXRST(x) ((x) << S_MTIPSD1TXRST)
33693 #define F_MTIPSD1TXRST V_MTIPSD1TXRST(1U)
33695 #define S_MTIPSD0TXRST 6
33696 #define V_MTIPSD0TXRST(x) ((x) << S_MTIPSD0TXRST)
33697 #define F_MTIPSD0TXRST V_MTIPSD0TXRST(1U)
33699 #define S_MTIPSD3RXRST 5
33700 #define V_MTIPSD3RXRST(x) ((x) << S_MTIPSD3RXRST)
33701 #define F_MTIPSD3RXRST V_MTIPSD3RXRST(1U)
33703 #define S_MTIPSD2RXRST 4
33704 #define V_MTIPSD2RXRST(x) ((x) << S_MTIPSD2RXRST)
33705 #define F_MTIPSD2RXRST V_MTIPSD2RXRST(1U)
33707 #define S_MTIPSD1RXRST 3
33708 #define V_MTIPSD1RXRST(x) ((x) << S_MTIPSD1RXRST)
33709 #define F_MTIPSD1RXRST V_MTIPSD1RXRST(1U)
33711 #define S_MTIPSD0RXRST 1
33712 #define V_MTIPSD0RXRST(x) ((x) << S_MTIPSD0RXRST)
33713 #define F_MTIPSD0RXRST V_MTIPSD0RXRST(1U)
33715 #define A_MAC_PORT_LED_CFG 0x808
33716 #define A_MAC_PORT_LED_COUNTHI 0x80c
33717 #define A_MAC_PORT_LED_COUNTLO 0x810
33718 #define A_MAC_PORT_CFG3 0x814
33720 #define S_FCSDISCTRL 25
33721 #define V_FCSDISCTRL(x) ((x) << S_FCSDISCTRL)
33722 #define F_FCSDISCTRL V_FCSDISCTRL(1U)
33724 #define S_SIGDETCTRL 24
33725 #define V_SIGDETCTRL(x) ((x) << S_SIGDETCTRL)
33726 #define F_SIGDETCTRL V_SIGDETCTRL(1U)
33728 #define S_TX_LANE 23
33729 #define V_TX_LANE(x) ((x) << S_TX_LANE)
33730 #define F_TX_LANE V_TX_LANE(1U)
33732 #define S_RX_LANE 22
33733 #define V_RX_LANE(x) ((x) << S_RX_LANE)
33734 #define F_RX_LANE V_RX_LANE(1U)
33736 #define S_SE_CLR 21
33737 #define V_SE_CLR(x) ((x) << S_SE_CLR)
33738 #define F_SE_CLR V_SE_CLR(1U)
33740 #define S_AN_ENA 17
33741 #define M_AN_ENA 0xfU
33742 #define V_AN_ENA(x) ((x) << S_AN_ENA)
33743 #define G_AN_ENA(x) (((x) >> S_AN_ENA) & M_AN_ENA)
33745 #define S_SD_RX_CLK_ENA 13
33746 #define M_SD_RX_CLK_ENA 0xfU
33747 #define V_SD_RX_CLK_ENA(x) ((x) << S_SD_RX_CLK_ENA)
33748 #define G_SD_RX_CLK_ENA(x) (((x) >> S_SD_RX_CLK_ENA) & M_SD_RX_CLK_ENA)
33750 #define S_SD_TX_CLK_ENA 9
33751 #define M_SD_TX_CLK_ENA 0xfU
33752 #define V_SD_TX_CLK_ENA(x) ((x) << S_SD_TX_CLK_ENA)
33753 #define G_SD_TX_CLK_ENA(x) (((x) >> S_SD_TX_CLK_ENA) & M_SD_TX_CLK_ENA)
33755 #define S_SGMIISEL 8
33756 #define V_SGMIISEL(x) ((x) << S_SGMIISEL)
33757 #define F_SGMIISEL V_SGMIISEL(1U)
33759 #define S_HSSPLLSEL 4
33760 #define M_HSSPLLSEL 0xfU
33761 #define V_HSSPLLSEL(x) ((x) << S_HSSPLLSEL)
33762 #define G_HSSPLLSEL(x) (((x) >> S_HSSPLLSEL) & M_HSSPLLSEL)
33764 #define S_HSSC16C20SEL 0
33765 #define M_HSSC16C20SEL 0xfU
33766 #define V_HSSC16C20SEL(x) ((x) << S_HSSC16C20SEL)
33767 #define G_HSSC16C20SEL(x) (((x) >> S_HSSC16C20SEL) & M_HSSC16C20SEL)
33769 #define A_MAC_PORT_CFG2 0x818
33771 #define S_T5_AEC_PMA_TX_READY 4
33772 #define M_T5_AEC_PMA_TX_READY 0xfU
33773 #define V_T5_AEC_PMA_TX_READY(x) ((x) << S_T5_AEC_PMA_TX_READY)
33774 #define G_T5_AEC_PMA_TX_READY(x) (((x) >> S_T5_AEC_PMA_TX_READY) & M_T5_AEC_PMA_TX_READY)
33776 #define S_T5_AEC_PMA_RX_READY 0
33777 #define M_T5_AEC_PMA_RX_READY 0xfU
33778 #define V_T5_AEC_PMA_RX_READY(x) ((x) << S_T5_AEC_PMA_RX_READY)
33779 #define G_T5_AEC_PMA_RX_READY(x) (((x) >> S_T5_AEC_PMA_RX_READY) & M_T5_AEC_PMA_RX_READY)
33781 #define A_MAC_PORT_PKT_COUNT 0x81c
33782 #define A_MAC_PORT_CFG4 0x820
33784 #define S_AEC3_RX_WIDTH 14
33785 #define M_AEC3_RX_WIDTH 0x3U
33786 #define V_AEC3_RX_WIDTH(x) ((x) << S_AEC3_RX_WIDTH)
33787 #define G_AEC3_RX_WIDTH(x) (((x) >> S_AEC3_RX_WIDTH) & M_AEC3_RX_WIDTH)
33789 #define S_AEC2_RX_WIDTH 12
33790 #define M_AEC2_RX_WIDTH 0x3U
33791 #define V_AEC2_RX_WIDTH(x) ((x) << S_AEC2_RX_WIDTH)
33792 #define G_AEC2_RX_WIDTH(x) (((x) >> S_AEC2_RX_WIDTH) & M_AEC2_RX_WIDTH)
33794 #define S_AEC1_RX_WIDTH 10
33795 #define M_AEC1_RX_WIDTH 0x3U
33796 #define V_AEC1_RX_WIDTH(x) ((x) << S_AEC1_RX_WIDTH)
33797 #define G_AEC1_RX_WIDTH(x) (((x) >> S_AEC1_RX_WIDTH) & M_AEC1_RX_WIDTH)
33799 #define S_AEC0_RX_WIDTH 8
33800 #define M_AEC0_RX_WIDTH 0x3U
33801 #define V_AEC0_RX_WIDTH(x) ((x) << S_AEC0_RX_WIDTH)
33802 #define G_AEC0_RX_WIDTH(x) (((x) >> S_AEC0_RX_WIDTH) & M_AEC0_RX_WIDTH)
33804 #define S_AEC3_TX_WIDTH 6
33805 #define M_AEC3_TX_WIDTH 0x3U
33806 #define V_AEC3_TX_WIDTH(x) ((x) << S_AEC3_TX_WIDTH)
33807 #define G_AEC3_TX_WIDTH(x) (((x) >> S_AEC3_TX_WIDTH) & M_AEC3_TX_WIDTH)
33809 #define S_AEC2_TX_WIDTH 4
33810 #define M_AEC2_TX_WIDTH 0x3U
33811 #define V_AEC2_TX_WIDTH(x) ((x) << S_AEC2_TX_WIDTH)
33812 #define G_AEC2_TX_WIDTH(x) (((x) >> S_AEC2_TX_WIDTH) & M_AEC2_TX_WIDTH)
33814 #define S_AEC1_TX_WIDTH 2
33815 #define M_AEC1_TX_WIDTH 0x3U
33816 #define V_AEC1_TX_WIDTH(x) ((x) << S_AEC1_TX_WIDTH)
33817 #define G_AEC1_TX_WIDTH(x) (((x) >> S_AEC1_TX_WIDTH) & M_AEC1_TX_WIDTH)
33819 #define S_AEC0_TX_WIDTH 0
33820 #define M_AEC0_TX_WIDTH 0x3U
33821 #define V_AEC0_TX_WIDTH(x) ((x) << S_AEC0_TX_WIDTH)
33822 #define G_AEC0_TX_WIDTH(x) (((x) >> S_AEC0_TX_WIDTH) & M_AEC0_TX_WIDTH)
33824 #define A_MAC_PORT_MAGIC_MACID_LO 0x824
33825 #define A_MAC_PORT_MAGIC_MACID_HI 0x828
33826 #define A_MAC_PORT_LINK_STATUS 0x834
33828 #define S_AN_DONE 6
33829 #define V_AN_DONE(x) ((x) << S_AN_DONE)
33830 #define F_AN_DONE V_AN_DONE(1U)
33832 #define S_ALIGN_DONE 5
33833 #define V_ALIGN_DONE(x) ((x) << S_ALIGN_DONE)
33834 #define F_ALIGN_DONE V_ALIGN_DONE(1U)
33836 #define S_BLOCK_LOCK 4
33837 #define V_BLOCK_LOCK(x) ((x) << S_BLOCK_LOCK)
33838 #define F_BLOCK_LOCK V_BLOCK_LOCK(1U)
33840 #define A_MAC_PORT_EPIO_DATA0 0x8c0
33841 #define A_MAC_PORT_EPIO_DATA1 0x8c4
33842 #define A_MAC_PORT_EPIO_DATA2 0x8c8
33843 #define A_MAC_PORT_EPIO_DATA3 0x8cc
33844 #define A_MAC_PORT_EPIO_OP 0x8d0
33845 #define A_MAC_PORT_WOL_STATUS 0x8d4
33846 #define A_MAC_PORT_INT_EN 0x8d8
33848 #define S_TX_TS_AVAIL 29
33849 #define V_TX_TS_AVAIL(x) ((x) << S_TX_TS_AVAIL)
33850 #define F_TX_TS_AVAIL V_TX_TS_AVAIL(1U)
33852 #define S_AN_PAGE_RCVD 2
33853 #define V_AN_PAGE_RCVD(x) ((x) << S_AN_PAGE_RCVD)
33854 #define F_AN_PAGE_RCVD V_AN_PAGE_RCVD(1U)
33856 #define A_MAC_PORT_INT_CAUSE 0x8dc
33857 #define A_MAC_PORT_PERR_INT_EN 0x8e0
33859 #define S_PERR_PKT_RAM 24
33860 #define V_PERR_PKT_RAM(x) ((x) << S_PERR_PKT_RAM)
33861 #define F_PERR_PKT_RAM V_PERR_PKT_RAM(1U)
33863 #define S_PERR_MASK_RAM 23
33864 #define V_PERR_MASK_RAM(x) ((x) << S_PERR_MASK_RAM)
33865 #define F_PERR_MASK_RAM V_PERR_MASK_RAM(1U)
33867 #define S_PERR_CRC_RAM 22
33868 #define V_PERR_CRC_RAM(x) ((x) << S_PERR_CRC_RAM)
33869 #define F_PERR_CRC_RAM V_PERR_CRC_RAM(1U)
33871 #define S_RX_DFF_SEG0 21
33872 #define V_RX_DFF_SEG0(x) ((x) << S_RX_DFF_SEG0)
33873 #define F_RX_DFF_SEG0 V_RX_DFF_SEG0(1U)
33875 #define S_RX_SFF_SEG0 20
33876 #define V_RX_SFF_SEG0(x) ((x) << S_RX_SFF_SEG0)
33877 #define F_RX_SFF_SEG0 V_RX_SFF_SEG0(1U)
33879 #define S_RX_DFF_MAC10 19
33880 #define V_RX_DFF_MAC10(x) ((x) << S_RX_DFF_MAC10)
33881 #define F_RX_DFF_MAC10 V_RX_DFF_MAC10(1U)
33883 #define S_RX_SFF_MAC10 18
33884 #define V_RX_SFF_MAC10(x) ((x) << S_RX_SFF_MAC10)
33885 #define F_RX_SFF_MAC10 V_RX_SFF_MAC10(1U)
33887 #define S_TX_DFF_SEG0 17
33888 #define V_TX_DFF_SEG0(x) ((x) << S_TX_DFF_SEG0)
33889 #define F_TX_DFF_SEG0 V_TX_DFF_SEG0(1U)
33891 #define S_TX_SFF_SEG0 16
33892 #define V_TX_SFF_SEG0(x) ((x) << S_TX_SFF_SEG0)
33893 #define F_TX_SFF_SEG0 V_TX_SFF_SEG0(1U)
33895 #define S_TX_DFF_MAC10 15
33896 #define V_TX_DFF_MAC10(x) ((x) << S_TX_DFF_MAC10)
33897 #define F_TX_DFF_MAC10 V_TX_DFF_MAC10(1U)
33899 #define S_TX_SFF_MAC10 14
33900 #define V_TX_SFF_MAC10(x) ((x) << S_TX_SFF_MAC10)
33901 #define F_TX_SFF_MAC10 V_TX_SFF_MAC10(1U)
33903 #define S_RX_STATS 13
33904 #define V_RX_STATS(x) ((x) << S_RX_STATS)
33905 #define F_RX_STATS V_RX_STATS(1U)
33907 #define S_TX_STATS 12
33908 #define V_TX_STATS(x) ((x) << S_TX_STATS)
33909 #define F_TX_STATS V_TX_STATS(1U)
33911 #define S_PERR3_RX_MIX 11
33912 #define V_PERR3_RX_MIX(x) ((x) << S_PERR3_RX_MIX)
33913 #define F_PERR3_RX_MIX V_PERR3_RX_MIX(1U)
33915 #define S_PERR3_RX_SD 10
33916 #define V_PERR3_RX_SD(x) ((x) << S_PERR3_RX_SD)
33917 #define F_PERR3_RX_SD V_PERR3_RX_SD(1U)
33919 #define S_PERR3_TX 9
33920 #define V_PERR3_TX(x) ((x) << S_PERR3_TX)
33921 #define F_PERR3_TX V_PERR3_TX(1U)
33923 #define S_PERR2_RX_MIX 8
33924 #define V_PERR2_RX_MIX(x) ((x) << S_PERR2_RX_MIX)
33925 #define F_PERR2_RX_MIX V_PERR2_RX_MIX(1U)
33927 #define S_PERR2_RX_SD 7
33928 #define V_PERR2_RX_SD(x) ((x) << S_PERR2_RX_SD)
33929 #define F_PERR2_RX_SD V_PERR2_RX_SD(1U)
33931 #define S_PERR2_TX 6
33932 #define V_PERR2_TX(x) ((x) << S_PERR2_TX)
33933 #define F_PERR2_TX V_PERR2_TX(1U)
33935 #define S_PERR1_RX_MIX 5
33936 #define V_PERR1_RX_MIX(x) ((x) << S_PERR1_RX_MIX)
33937 #define F_PERR1_RX_MIX V_PERR1_RX_MIX(1U)
33939 #define S_PERR1_RX_SD 4
33940 #define V_PERR1_RX_SD(x) ((x) << S_PERR1_RX_SD)
33941 #define F_PERR1_RX_SD V_PERR1_RX_SD(1U)
33943 #define S_PERR1_TX 3
33944 #define V_PERR1_TX(x) ((x) << S_PERR1_TX)
33945 #define F_PERR1_TX V_PERR1_TX(1U)
33947 #define S_PERR0_RX_MIX 2
33948 #define V_PERR0_RX_MIX(x) ((x) << S_PERR0_RX_MIX)
33949 #define F_PERR0_RX_MIX V_PERR0_RX_MIX(1U)
33951 #define S_PERR0_RX_SD 1
33952 #define V_PERR0_RX_SD(x) ((x) << S_PERR0_RX_SD)
33953 #define F_PERR0_RX_SD V_PERR0_RX_SD(1U)
33955 #define S_PERR0_TX 0
33956 #define V_PERR0_TX(x) ((x) << S_PERR0_TX)
33957 #define F_PERR0_TX V_PERR0_TX(1U)
33959 #define A_MAC_PORT_PERR_INT_CAUSE 0x8e4
33960 #define A_MAC_PORT_PERR_ENABLE 0x8e8
33961 #define A_MAC_PORT_PERR_INJECT 0x8ec
33962 #define A_MAC_PORT_HSS_CFG0 0x8f0
33964 #define S_HSSREFCLKVALIDA 20
33965 #define V_HSSREFCLKVALIDA(x) ((x) << S_HSSREFCLKVALIDA)
33966 #define F_HSSREFCLKVALIDA V_HSSREFCLKVALIDA(1U)
33968 #define S_HSSREFCLKVALIDB 19
33969 #define V_HSSREFCLKVALIDB(x) ((x) << S_HSSREFCLKVALIDB)
33970 #define F_HSSREFCLKVALIDB V_HSSREFCLKVALIDB(1U)
33972 #define S_HSSRESYNCA 18
33973 #define V_HSSRESYNCA(x) ((x) << S_HSSRESYNCA)
33974 #define F_HSSRESYNCA V_HSSRESYNCA(1U)
33976 #define S_HSSRESYNCB 16
33977 #define V_HSSRESYNCB(x) ((x) << S_HSSRESYNCB)
33978 #define F_HSSRESYNCB V_HSSRESYNCB(1U)
33980 #define S_HSSRECCALA 15
33981 #define V_HSSRECCALA(x) ((x) << S_HSSRECCALA)
33982 #define F_HSSRECCALA V_HSSRECCALA(1U)
33984 #define S_HSSRECCALB 13
33985 #define V_HSSRECCALB(x) ((x) << S_HSSRECCALB)
33986 #define F_HSSRECCALB V_HSSRECCALB(1U)
33988 #define S_HSSPLLBYPA 12
33989 #define V_HSSPLLBYPA(x) ((x) << S_HSSPLLBYPA)
33990 #define F_HSSPLLBYPA V_HSSPLLBYPA(1U)
33992 #define S_HSSPLLBYPB 11
33993 #define V_HSSPLLBYPB(x) ((x) << S_HSSPLLBYPB)
33994 #define F_HSSPLLBYPB V_HSSPLLBYPB(1U)
33996 #define S_HSSPDWNPLLA 10
33997 #define V_HSSPDWNPLLA(x) ((x) << S_HSSPDWNPLLA)
33998 #define F_HSSPDWNPLLA V_HSSPDWNPLLA(1U)
34000 #define S_HSSPDWNPLLB 9
34001 #define V_HSSPDWNPLLB(x) ((x) << S_HSSPDWNPLLB)
34002 #define F_HSSPDWNPLLB V_HSSPDWNPLLB(1U)
34004 #define S_HSSVCOSELA 8
34005 #define V_HSSVCOSELA(x) ((x) << S_HSSVCOSELA)
34006 #define F_HSSVCOSELA V_HSSVCOSELA(1U)
34008 #define S_HSSVCOSELB 7
34009 #define V_HSSVCOSELB(x) ((x) << S_HSSVCOSELB)
34010 #define F_HSSVCOSELB V_HSSVCOSELB(1U)
34012 #define S_HSSCALCOMP 6
34013 #define V_HSSCALCOMP(x) ((x) << S_HSSCALCOMP)
34014 #define F_HSSCALCOMP V_HSSCALCOMP(1U)
34016 #define S_HSSCALENAB 5
34017 #define V_HSSCALENAB(x) ((x) << S_HSSCALENAB)
34018 #define F_HSSCALENAB V_HSSCALENAB(1U)
34020 #define A_MAC_PORT_HSS_CFG1 0x8f4
34022 #define S_RXACONFIGSEL 30
34023 #define M_RXACONFIGSEL 0x3U
34024 #define V_RXACONFIGSEL(x) ((x) << S_RXACONFIGSEL)
34025 #define G_RXACONFIGSEL(x) (((x) >> S_RXACONFIGSEL) & M_RXACONFIGSEL)
34027 #define S_RXAQUIET 29
34028 #define V_RXAQUIET(x) ((x) << S_RXAQUIET)
34029 #define F_RXAQUIET V_RXAQUIET(1U)
34031 #define S_RXAREFRESH 28
34032 #define V_RXAREFRESH(x) ((x) << S_RXAREFRESH)
34033 #define F_RXAREFRESH V_RXAREFRESH(1U)
34035 #define S_RXBCONFIGSEL 26
34036 #define M_RXBCONFIGSEL 0x3U
34037 #define V_RXBCONFIGSEL(x) ((x) << S_RXBCONFIGSEL)
34038 #define G_RXBCONFIGSEL(x) (((x) >> S_RXBCONFIGSEL) & M_RXBCONFIGSEL)
34040 #define S_RXBQUIET 25
34041 #define V_RXBQUIET(x) ((x) << S_RXBQUIET)
34042 #define F_RXBQUIET V_RXBQUIET(1U)
34044 #define S_RXBREFRESH 24
34045 #define V_RXBREFRESH(x) ((x) << S_RXBREFRESH)
34046 #define F_RXBREFRESH V_RXBREFRESH(1U)
34048 #define S_RXCCONFIGSEL 22
34049 #define M_RXCCONFIGSEL 0x3U
34050 #define V_RXCCONFIGSEL(x) ((x) << S_RXCCONFIGSEL)
34051 #define G_RXCCONFIGSEL(x) (((x) >> S_RXCCONFIGSEL) & M_RXCCONFIGSEL)
34053 #define S_RXCQUIET 21
34054 #define V_RXCQUIET(x) ((x) << S_RXCQUIET)
34055 #define F_RXCQUIET V_RXCQUIET(1U)
34057 #define S_RXCREFRESH 20
34058 #define V_RXCREFRESH(x) ((x) << S_RXCREFRESH)
34059 #define F_RXCREFRESH V_RXCREFRESH(1U)
34061 #define S_RXDCONFIGSEL 18
34062 #define M_RXDCONFIGSEL 0x3U
34063 #define V_RXDCONFIGSEL(x) ((x) << S_RXDCONFIGSEL)
34064 #define G_RXDCONFIGSEL(x) (((x) >> S_RXDCONFIGSEL) & M_RXDCONFIGSEL)
34066 #define S_RXDQUIET 17
34067 #define V_RXDQUIET(x) ((x) << S_RXDQUIET)
34068 #define F_RXDQUIET V_RXDQUIET(1U)
34070 #define S_RXDREFRESH 16
34071 #define V_RXDREFRESH(x) ((x) << S_RXDREFRESH)
34072 #define F_RXDREFRESH V_RXDREFRESH(1U)
34074 #define S_TXACONFIGSEL 14
34075 #define M_TXACONFIGSEL 0x3U
34076 #define V_TXACONFIGSEL(x) ((x) << S_TXACONFIGSEL)
34077 #define G_TXACONFIGSEL(x) (((x) >> S_TXACONFIGSEL) & M_TXACONFIGSEL)
34079 #define S_TXAQUIET 13
34080 #define V_TXAQUIET(x) ((x) << S_TXAQUIET)
34081 #define F_TXAQUIET V_TXAQUIET(1U)
34083 #define S_TXAREFRESH 12
34084 #define V_TXAREFRESH(x) ((x) << S_TXAREFRESH)
34085 #define F_TXAREFRESH V_TXAREFRESH(1U)
34087 #define S_TXBCONFIGSEL 10
34088 #define M_TXBCONFIGSEL 0x3U
34089 #define V_TXBCONFIGSEL(x) ((x) << S_TXBCONFIGSEL)
34090 #define G_TXBCONFIGSEL(x) (((x) >> S_TXBCONFIGSEL) & M_TXBCONFIGSEL)
34092 #define S_TXBQUIET 9
34093 #define V_TXBQUIET(x) ((x) << S_TXBQUIET)
34094 #define F_TXBQUIET V_TXBQUIET(1U)
34096 #define S_TXBREFRESH 8
34097 #define V_TXBREFRESH(x) ((x) << S_TXBREFRESH)
34098 #define F_TXBREFRESH V_TXBREFRESH(1U)
34100 #define S_TXCCONFIGSEL 6
34101 #define M_TXCCONFIGSEL 0x3U
34102 #define V_TXCCONFIGSEL(x) ((x) << S_TXCCONFIGSEL)
34103 #define G_TXCCONFIGSEL(x) (((x) >> S_TXCCONFIGSEL) & M_TXCCONFIGSEL)
34105 #define S_TXCQUIET 5
34106 #define V_TXCQUIET(x) ((x) << S_TXCQUIET)
34107 #define F_TXCQUIET V_TXCQUIET(1U)
34109 #define S_TXCREFRESH 4
34110 #define V_TXCREFRESH(x) ((x) << S_TXCREFRESH)
34111 #define F_TXCREFRESH V_TXCREFRESH(1U)
34113 #define S_TXDCONFIGSEL 2
34114 #define M_TXDCONFIGSEL 0x3U
34115 #define V_TXDCONFIGSEL(x) ((x) << S_TXDCONFIGSEL)
34116 #define G_TXDCONFIGSEL(x) (((x) >> S_TXDCONFIGSEL) & M_TXDCONFIGSEL)
34118 #define S_TXDQUIET 1
34119 #define V_TXDQUIET(x) ((x) << S_TXDQUIET)
34120 #define F_TXDQUIET V_TXDQUIET(1U)
34122 #define S_TXDREFRESH 0
34123 #define V_TXDREFRESH(x) ((x) << S_TXDREFRESH)
34124 #define F_TXDREFRESH V_TXDREFRESH(1U)
34126 #define A_MAC_PORT_HSS_CFG2 0x8f8
34128 #define S_RXAASSTCLK 31
34129 #define V_RXAASSTCLK(x) ((x) << S_RXAASSTCLK)
34130 #define F_RXAASSTCLK V_RXAASSTCLK(1U)
34132 #define S_T5RXAPRBSRST 30
34133 #define V_T5RXAPRBSRST(x) ((x) << S_T5RXAPRBSRST)
34134 #define F_T5RXAPRBSRST V_T5RXAPRBSRST(1U)
34136 #define S_RXBASSTCLK 29
34137 #define V_RXBASSTCLK(x) ((x) << S_RXBASSTCLK)
34138 #define F_RXBASSTCLK V_RXBASSTCLK(1U)
34140 #define S_T5RXBPRBSRST 28
34141 #define V_T5RXBPRBSRST(x) ((x) << S_T5RXBPRBSRST)
34142 #define F_T5RXBPRBSRST V_T5RXBPRBSRST(1U)
34144 #define S_RXCASSTCLK 27
34145 #define V_RXCASSTCLK(x) ((x) << S_RXCASSTCLK)
34146 #define F_RXCASSTCLK V_RXCASSTCLK(1U)
34148 #define S_T5RXCPRBSRST 26
34149 #define V_T5RXCPRBSRST(x) ((x) << S_T5RXCPRBSRST)
34150 #define F_T5RXCPRBSRST V_T5RXCPRBSRST(1U)
34152 #define S_RXDASSTCLK 25
34153 #define V_RXDASSTCLK(x) ((x) << S_RXDASSTCLK)
34154 #define F_RXDASSTCLK V_RXDASSTCLK(1U)
34156 #define S_T5RXDPRBSRST 24
34157 #define V_T5RXDPRBSRST(x) ((x) << S_T5RXDPRBSRST)
34158 #define F_T5RXDPRBSRST V_T5RXDPRBSRST(1U)
34160 #define A_MAC_PORT_HSS_CFG3 0x8fc
34162 #define S_HSSCALSSTN 25
34163 #define M_HSSCALSSTN 0x7U
34164 #define V_HSSCALSSTN(x) ((x) << S_HSSCALSSTN)
34165 #define G_HSSCALSSTN(x) (((x) >> S_HSSCALSSTN) & M_HSSCALSSTN)
34167 #define S_HSSCALSSTP 22
34168 #define M_HSSCALSSTP 0x7U
34169 #define V_HSSCALSSTP(x) ((x) << S_HSSCALSSTP)
34170 #define G_HSSCALSSTP(x) (((x) >> S_HSSCALSSTP) & M_HSSCALSSTP)
34172 #define S_HSSVBOOSTDIVB 19
34173 #define M_HSSVBOOSTDIVB 0x7U
34174 #define V_HSSVBOOSTDIVB(x) ((x) << S_HSSVBOOSTDIVB)
34175 #define G_HSSVBOOSTDIVB(x) (((x) >> S_HSSVBOOSTDIVB) & M_HSSVBOOSTDIVB)
34177 #define S_HSSVBOOSTDIVA 16
34178 #define M_HSSVBOOSTDIVA 0x7U
34179 #define V_HSSVBOOSTDIVA(x) ((x) << S_HSSVBOOSTDIVA)
34180 #define G_HSSVBOOSTDIVA(x) (((x) >> S_HSSVBOOSTDIVA) & M_HSSVBOOSTDIVA)
34182 #define S_HSSPLLCONFIGB 8
34183 #define M_HSSPLLCONFIGB 0xffU
34184 #define V_HSSPLLCONFIGB(x) ((x) << S_HSSPLLCONFIGB)
34185 #define G_HSSPLLCONFIGB(x) (((x) >> S_HSSPLLCONFIGB) & M_HSSPLLCONFIGB)
34187 #define S_HSSPLLCONFIGA 0
34188 #define M_HSSPLLCONFIGA 0xffU
34189 #define V_HSSPLLCONFIGA(x) ((x) << S_HSSPLLCONFIGA)
34190 #define G_HSSPLLCONFIGA(x) (((x) >> S_HSSPLLCONFIGA) & M_HSSPLLCONFIGA)
34192 #define A_MAC_PORT_HSS_CFG4 0x900
34194 #define S_HSSDIVSELA 9
34195 #define M_HSSDIVSELA 0x1ffU
34196 #define V_HSSDIVSELA(x) ((x) << S_HSSDIVSELA)
34197 #define G_HSSDIVSELA(x) (((x) >> S_HSSDIVSELA) & M_HSSDIVSELA)
34199 #define S_HSSDIVSELB 0
34200 #define M_HSSDIVSELB 0x1ffU
34201 #define V_HSSDIVSELB(x) ((x) << S_HSSDIVSELB)
34202 #define G_HSSDIVSELB(x) (((x) >> S_HSSDIVSELB) & M_HSSDIVSELB)
34204 #define A_MAC_PORT_HSS_STATUS 0x904
34206 #define S_HSSPLLLOCKB 3
34207 #define V_HSSPLLLOCKB(x) ((x) << S_HSSPLLLOCKB)
34208 #define F_HSSPLLLOCKB V_HSSPLLLOCKB(1U)
34210 #define S_HSSPLLLOCKA 2
34211 #define V_HSSPLLLOCKA(x) ((x) << S_HSSPLLLOCKA)
34212 #define F_HSSPLLLOCKA V_HSSPLLLOCKA(1U)
34214 #define S_HSSPRTREADYB 1
34215 #define V_HSSPRTREADYB(x) ((x) << S_HSSPRTREADYB)
34216 #define F_HSSPRTREADYB V_HSSPRTREADYB(1U)
34218 #define S_HSSPRTREADYA 0
34219 #define V_HSSPRTREADYA(x) ((x) << S_HSSPRTREADYA)
34220 #define F_HSSPRTREADYA V_HSSPRTREADYA(1U)
34222 #define A_MAC_PORT_HSS_EEE_STATUS 0x908
34224 #define S_RXAQUIET_STATUS 15
34225 #define V_RXAQUIET_STATUS(x) ((x) << S_RXAQUIET_STATUS)
34226 #define F_RXAQUIET_STATUS V_RXAQUIET_STATUS(1U)
34228 #define S_RXAREFRESH_STATUS 14
34229 #define V_RXAREFRESH_STATUS(x) ((x) << S_RXAREFRESH_STATUS)
34230 #define F_RXAREFRESH_STATUS V_RXAREFRESH_STATUS(1U)
34232 #define S_RXBQUIET_STATUS 13
34233 #define V_RXBQUIET_STATUS(x) ((x) << S_RXBQUIET_STATUS)
34234 #define F_RXBQUIET_STATUS V_RXBQUIET_STATUS(1U)
34236 #define S_RXBREFRESH_STATUS 12
34237 #define V_RXBREFRESH_STATUS(x) ((x) << S_RXBREFRESH_STATUS)
34238 #define F_RXBREFRESH_STATUS V_RXBREFRESH_STATUS(1U)
34240 #define S_RXCQUIET_STATUS 11
34241 #define V_RXCQUIET_STATUS(x) ((x) << S_RXCQUIET_STATUS)
34242 #define F_RXCQUIET_STATUS V_RXCQUIET_STATUS(1U)
34244 #define S_RXCREFRESH_STATUS 10
34245 #define V_RXCREFRESH_STATUS(x) ((x) << S_RXCREFRESH_STATUS)
34246 #define F_RXCREFRESH_STATUS V_RXCREFRESH_STATUS(1U)
34248 #define S_RXDQUIET_STATUS 9
34249 #define V_RXDQUIET_STATUS(x) ((x) << S_RXDQUIET_STATUS)
34250 #define F_RXDQUIET_STATUS V_RXDQUIET_STATUS(1U)
34252 #define S_RXDREFRESH_STATUS 8
34253 #define V_RXDREFRESH_STATUS(x) ((x) << S_RXDREFRESH_STATUS)
34254 #define F_RXDREFRESH_STATUS V_RXDREFRESH_STATUS(1U)
34256 #define S_TXAQUIET_STATUS 7
34257 #define V_TXAQUIET_STATUS(x) ((x) << S_TXAQUIET_STATUS)
34258 #define F_TXAQUIET_STATUS V_TXAQUIET_STATUS(1U)
34260 #define S_TXAREFRESH_STATUS 6
34261 #define V_TXAREFRESH_STATUS(x) ((x) << S_TXAREFRESH_STATUS)
34262 #define F_TXAREFRESH_STATUS V_TXAREFRESH_STATUS(1U)
34264 #define S_TXBQUIET_STATUS 5
34265 #define V_TXBQUIET_STATUS(x) ((x) << S_TXBQUIET_STATUS)
34266 #define F_TXBQUIET_STATUS V_TXBQUIET_STATUS(1U)
34268 #define S_TXBREFRESH_STATUS 4
34269 #define V_TXBREFRESH_STATUS(x) ((x) << S_TXBREFRESH_STATUS)
34270 #define F_TXBREFRESH_STATUS V_TXBREFRESH_STATUS(1U)
34272 #define S_TXCQUIET_STATUS 3
34273 #define V_TXCQUIET_STATUS(x) ((x) << S_TXCQUIET_STATUS)
34274 #define F_TXCQUIET_STATUS V_TXCQUIET_STATUS(1U)
34276 #define S_TXCREFRESH_STATUS 2
34277 #define V_TXCREFRESH_STATUS(x) ((x) << S_TXCREFRESH_STATUS)
34278 #define F_TXCREFRESH_STATUS V_TXCREFRESH_STATUS(1U)
34280 #define S_TXDQUIET_STATUS 1
34281 #define V_TXDQUIET_STATUS(x) ((x) << S_TXDQUIET_STATUS)
34282 #define F_TXDQUIET_STATUS V_TXDQUIET_STATUS(1U)
34284 #define S_TXDREFRESH_STATUS 0
34285 #define V_TXDREFRESH_STATUS(x) ((x) << S_TXDREFRESH_STATUS)
34286 #define F_TXDREFRESH_STATUS V_TXDREFRESH_STATUS(1U)
34288 #define A_MAC_PORT_HSS_SIGDET_STATUS 0x90c
34289 #define A_MAC_PORT_HSS_PL_CTL 0x910
34292 #define M_TOV 0xffU
34293 #define V_TOV(x) ((x) << S_TOV)
34294 #define G_TOV(x) (((x) >> S_TOV) & M_TOV)
34297 #define M_TSU 0xffU
34298 #define V_TSU(x) ((x) << S_TSU)
34299 #define G_TSU(x) (((x) >> S_TSU) & M_TSU)
34302 #define M_IPW 0xffU
34303 #define V_IPW(x) ((x) << S_IPW)
34304 #define G_IPW(x) (((x) >> S_IPW) & M_IPW)
34306 #define A_MAC_PORT_RUNT_FRAME 0x914
34308 #define S_RUNTCLEAR 16
34309 #define V_RUNTCLEAR(x) ((x) << S_RUNTCLEAR)
34310 #define F_RUNTCLEAR V_RUNTCLEAR(1U)
34313 #define M_RUNT 0xffffU
34314 #define V_RUNT(x) ((x) << S_RUNT)
34315 #define G_RUNT(x) (((x) >> S_RUNT) & M_RUNT)
34317 #define A_MAC_PORT_EEE_STATUS 0x918
34319 #define S_EEE_TX_10G_STATE 10
34320 #define M_EEE_TX_10G_STATE 0x3U
34321 #define V_EEE_TX_10G_STATE(x) ((x) << S_EEE_TX_10G_STATE)
34322 #define G_EEE_TX_10G_STATE(x) (((x) >> S_EEE_TX_10G_STATE) & M_EEE_TX_10G_STATE)
34324 #define S_EEE_RX_10G_STATE 8
34325 #define M_EEE_RX_10G_STATE 0x3U
34326 #define V_EEE_RX_10G_STATE(x) ((x) << S_EEE_RX_10G_STATE)
34327 #define G_EEE_RX_10G_STATE(x) (((x) >> S_EEE_RX_10G_STATE) & M_EEE_RX_10G_STATE)
34329 #define S_EEE_TX_1G_STATE 6
34330 #define M_EEE_TX_1G_STATE 0x3U
34331 #define V_EEE_TX_1G_STATE(x) ((x) << S_EEE_TX_1G_STATE)
34332 #define G_EEE_TX_1G_STATE(x) (((x) >> S_EEE_TX_1G_STATE) & M_EEE_TX_1G_STATE)
34334 #define S_EEE_RX_1G_STATE 4
34335 #define M_EEE_RX_1G_STATE 0x3U
34336 #define V_EEE_RX_1G_STATE(x) ((x) << S_EEE_RX_1G_STATE)
34337 #define G_EEE_RX_1G_STATE(x) (((x) >> S_EEE_RX_1G_STATE) & M_EEE_RX_1G_STATE)
34339 #define S_PMA_RX_REFRESH 3
34340 #define V_PMA_RX_REFRESH(x) ((x) << S_PMA_RX_REFRESH)
34341 #define F_PMA_RX_REFRESH V_PMA_RX_REFRESH(1U)
34343 #define S_PMA_RX_QUIET 2
34344 #define V_PMA_RX_QUIET(x) ((x) << S_PMA_RX_QUIET)
34345 #define F_PMA_RX_QUIET V_PMA_RX_QUIET(1U)
34347 #define S_PMA_TX_REFRESH 1
34348 #define V_PMA_TX_REFRESH(x) ((x) << S_PMA_TX_REFRESH)
34349 #define F_PMA_TX_REFRESH V_PMA_TX_REFRESH(1U)
34351 #define S_PMA_TX_QUIET 0
34352 #define V_PMA_TX_QUIET(x) ((x) << S_PMA_TX_QUIET)
34353 #define F_PMA_TX_QUIET V_PMA_TX_QUIET(1U)
34355 #define A_MAC_PORT_CGEN 0x91c
34358 #define V_CGEN(x) ((x) << S_CGEN)
34359 #define F_CGEN V_CGEN(1U)
34361 #define S_SD7_CGEN 7
34362 #define V_SD7_CGEN(x) ((x) << S_SD7_CGEN)
34363 #define F_SD7_CGEN V_SD7_CGEN(1U)
34365 #define S_SD6_CGEN 6
34366 #define V_SD6_CGEN(x) ((x) << S_SD6_CGEN)
34367 #define F_SD6_CGEN V_SD6_CGEN(1U)
34369 #define S_SD5_CGEN 5
34370 #define V_SD5_CGEN(x) ((x) << S_SD5_CGEN)
34371 #define F_SD5_CGEN V_SD5_CGEN(1U)
34373 #define S_SD4_CGEN 4
34374 #define V_SD4_CGEN(x) ((x) << S_SD4_CGEN)
34375 #define F_SD4_CGEN V_SD4_CGEN(1U)
34377 #define S_SD3_CGEN 3
34378 #define V_SD3_CGEN(x) ((x) << S_SD3_CGEN)
34379 #define F_SD3_CGEN V_SD3_CGEN(1U)
34381 #define S_SD2_CGEN 2
34382 #define V_SD2_CGEN(x) ((x) << S_SD2_CGEN)
34383 #define F_SD2_CGEN V_SD2_CGEN(1U)
34385 #define S_SD1_CGEN 1
34386 #define V_SD1_CGEN(x) ((x) << S_SD1_CGEN)
34387 #define F_SD1_CGEN V_SD1_CGEN(1U)
34389 #define S_SD0_CGEN 0
34390 #define V_SD0_CGEN(x) ((x) << S_SD0_CGEN)
34391 #define F_SD0_CGEN V_SD0_CGEN(1U)
34393 #define A_MAC_PORT_CGEN_MTIP 0x920
34395 #define S_MACSEG5_CGEN 11
34396 #define V_MACSEG5_CGEN(x) ((x) << S_MACSEG5_CGEN)
34397 #define F_MACSEG5_CGEN V_MACSEG5_CGEN(1U)
34399 #define S_PCSSEG5_CGEN 10
34400 #define V_PCSSEG5_CGEN(x) ((x) << S_PCSSEG5_CGEN)
34401 #define F_PCSSEG5_CGEN V_PCSSEG5_CGEN(1U)
34403 #define S_MACSEG4_CGEN 9
34404 #define V_MACSEG4_CGEN(x) ((x) << S_MACSEG4_CGEN)
34405 #define F_MACSEG4_CGEN V_MACSEG4_CGEN(1U)
34407 #define S_PCSSEG4_CGEN 8
34408 #define V_PCSSEG4_CGEN(x) ((x) << S_PCSSEG4_CGEN)
34409 #define F_PCSSEG4_CGEN V_PCSSEG4_CGEN(1U)
34411 #define S_MACSEG3_CGEN 7
34412 #define V_MACSEG3_CGEN(x) ((x) << S_MACSEG3_CGEN)
34413 #define F_MACSEG3_CGEN V_MACSEG3_CGEN(1U)
34415 #define S_PCSSEG3_CGEN 6
34416 #define V_PCSSEG3_CGEN(x) ((x) << S_PCSSEG3_CGEN)
34417 #define F_PCSSEG3_CGEN V_PCSSEG3_CGEN(1U)
34419 #define S_MACSEG2_CGEN 5
34420 #define V_MACSEG2_CGEN(x) ((x) << S_MACSEG2_CGEN)
34421 #define F_MACSEG2_CGEN V_MACSEG2_CGEN(1U)
34423 #define S_PCSSEG2_CGEN 4
34424 #define V_PCSSEG2_CGEN(x) ((x) << S_PCSSEG2_CGEN)
34425 #define F_PCSSEG2_CGEN V_PCSSEG2_CGEN(1U)
34427 #define S_MACSEG1_CGEN 3
34428 #define V_MACSEG1_CGEN(x) ((x) << S_MACSEG1_CGEN)
34429 #define F_MACSEG1_CGEN V_MACSEG1_CGEN(1U)
34431 #define S_PCSSEG1_CGEN 2
34432 #define V_PCSSEG1_CGEN(x) ((x) << S_PCSSEG1_CGEN)
34433 #define F_PCSSEG1_CGEN V_PCSSEG1_CGEN(1U)
34435 #define S_MACSEG0_CGEN 1
34436 #define V_MACSEG0_CGEN(x) ((x) << S_MACSEG0_CGEN)
34437 #define F_MACSEG0_CGEN V_MACSEG0_CGEN(1U)
34439 #define S_PCSSEG0_CGEN 0
34440 #define V_PCSSEG0_CGEN(x) ((x) << S_PCSSEG0_CGEN)
34441 #define F_PCSSEG0_CGEN V_PCSSEG0_CGEN(1U)
34443 #define A_MAC_PORT_TX_TS_ID 0x924
34446 #define M_TS_ID 0x7U
34447 #define V_TS_ID(x) ((x) << S_TS_ID)
34448 #define G_TS_ID(x) (((x) >> S_TS_ID) & M_TS_ID)
34450 #define A_MAC_PORT_TX_TS_VAL_LO 0x928
34451 #define A_MAC_PORT_TX_TS_VAL_HI 0x92c
34452 #define A_MAC_PORT_EEE_CTL 0x930
34454 #define S_EEE_CTRL 2
34455 #define M_EEE_CTRL 0x3fffffffU
34456 #define V_EEE_CTRL(x) ((x) << S_EEE_CTRL)
34457 #define G_EEE_CTRL(x) (((x) >> S_EEE_CTRL) & M_EEE_CTRL)
34459 #define S_TICK_START 1
34460 #define V_TICK_START(x) ((x) << S_TICK_START)
34461 #define F_TICK_START V_TICK_START(1U)
34463 #define S_EEE_ENABLE 0
34464 #define V_EEE_ENABLE(x) ((x) << S_EEE_ENABLE)
34465 #define F_EEE_ENABLE V_EEE_ENABLE(1U)
34467 #define A_MAC_PORT_EEE_TX_CTL 0x934
34469 #define S_WAKE_TIMER 16
34470 #define M_WAKE_TIMER 0xffffU
34471 #define V_WAKE_TIMER(x) ((x) << S_WAKE_TIMER)
34472 #define G_WAKE_TIMER(x) (((x) >> S_WAKE_TIMER) & M_WAKE_TIMER)
34474 #define S_HSS_TIMER 5
34475 #define M_HSS_TIMER 0xfU
34476 #define V_HSS_TIMER(x) ((x) << S_HSS_TIMER)
34477 #define G_HSS_TIMER(x) (((x) >> S_HSS_TIMER) & M_HSS_TIMER)
34479 #define S_HSS_CTL 4
34480 #define V_HSS_CTL(x) ((x) << S_HSS_CTL)
34481 #define F_HSS_CTL V_HSS_CTL(1U)
34483 #define S_LPI_ACTIVE 3
34484 #define V_LPI_ACTIVE(x) ((x) << S_LPI_ACTIVE)
34485 #define F_LPI_ACTIVE V_LPI_ACTIVE(1U)
34487 #define S_LPI_TXHOLD 2
34488 #define V_LPI_TXHOLD(x) ((x) << S_LPI_TXHOLD)
34489 #define F_LPI_TXHOLD V_LPI_TXHOLD(1U)
34491 #define S_LPI_REQ 1
34492 #define V_LPI_REQ(x) ((x) << S_LPI_REQ)
34493 #define F_LPI_REQ V_LPI_REQ(1U)
34495 #define S_EEE_TX_RESET 0
34496 #define V_EEE_TX_RESET(x) ((x) << S_EEE_TX_RESET)
34497 #define F_EEE_TX_RESET V_EEE_TX_RESET(1U)
34499 #define A_MAC_PORT_EEE_RX_CTL 0x938
34501 #define S_LPI_IND 1
34502 #define V_LPI_IND(x) ((x) << S_LPI_IND)
34503 #define F_LPI_IND V_LPI_IND(1U)
34505 #define S_EEE_RX_RESET 0
34506 #define V_EEE_RX_RESET(x) ((x) << S_EEE_RX_RESET)
34507 #define F_EEE_RX_RESET V_EEE_RX_RESET(1U)
34509 #define A_MAC_PORT_EEE_TX_10G_SLEEP_TIMER 0x93c
34510 #define A_MAC_PORT_EEE_TX_10G_QUIET_TIMER 0x940
34511 #define A_MAC_PORT_EEE_TX_10G_WAKE_TIMER 0x944
34512 #define A_MAC_PORT_EEE_TX_1G_SLEEP_TIMER 0x948
34513 #define A_MAC_PORT_EEE_TX_1G_QUIET_TIMER 0x94c
34514 #define A_MAC_PORT_EEE_TX_1G_REFRESH_TIMER 0x950
34515 #define A_MAC_PORT_EEE_RX_10G_QUIET_TIMER 0x954
34516 #define A_MAC_PORT_EEE_RX_10G_WAKE_TIMER 0x958
34517 #define A_MAC_PORT_EEE_RX_10G_WF_TIMER 0x95c
34518 #define A_MAC_PORT_EEE_RX_1G_QUIET_TIMER 0x960
34519 #define A_MAC_PORT_EEE_RX_1G_WAKE_TIMER 0x964
34520 #define A_MAC_PORT_EEE_WF_COUNT 0x968
34522 #define S_WAKE_CNT_CLR 16
34523 #define V_WAKE_CNT_CLR(x) ((x) << S_WAKE_CNT_CLR)
34524 #define F_WAKE_CNT_CLR V_WAKE_CNT_CLR(1U)
34526 #define S_WAKE_CNT 0
34527 #define M_WAKE_CNT 0xffffU
34528 #define V_WAKE_CNT(x) ((x) << S_WAKE_CNT)
34529 #define G_WAKE_CNT(x) (((x) >> S_WAKE_CNT) & M_WAKE_CNT)
34531 #define A_MAC_PORT_PTP_TIMER_RD0_LO 0x96c
34532 #define A_MAC_PORT_PTP_TIMER_RD0_HI 0x970
34533 #define A_MAC_PORT_PTP_TIMER_RD1_LO 0x974
34534 #define A_MAC_PORT_PTP_TIMER_RD1_HI 0x978
34535 #define A_MAC_PORT_PTP_TIMER_WR_LO 0x97c
34536 #define A_MAC_PORT_PTP_TIMER_WR_HI 0x980
34537 #define A_MAC_PORT_PTP_TIMER_OFFSET_0 0x984
34538 #define A_MAC_PORT_PTP_TIMER_OFFSET_1 0x988
34539 #define A_MAC_PORT_PTP_TIMER_OFFSET_2 0x98c
34541 #define S_PTP_OFFSET 0
34542 #define M_PTP_OFFSET 0xffU
34543 #define V_PTP_OFFSET(x) ((x) << S_PTP_OFFSET)
34544 #define G_PTP_OFFSET(x) (((x) >> S_PTP_OFFSET) & M_PTP_OFFSET)
34546 #define A_MAC_PORT_PTP_SUM_LO 0x990
34547 #define A_MAC_PORT_PTP_SUM_HI 0x994
34548 #define A_MAC_PORT_PTP_TIMER_INCR0 0x998
34551 #define M_Y 0xffffU
34552 #define V_Y(x) ((x) << S_Y)
34553 #define G_Y(x) (((x) >> S_Y) & M_Y)
34556 #define M_X 0xffffU
34557 #define V_X(x) ((x) << S_X)
34558 #define G_X(x) (((x) >> S_X) & M_X)
34560 #define A_MAC_PORT_PTP_TIMER_INCR1 0x99c
34562 #define S_Y_TICK 16
34563 #define M_Y_TICK 0xffffU
34564 #define V_Y_TICK(x) ((x) << S_Y_TICK)
34565 #define G_Y_TICK(x) (((x) >> S_Y_TICK) & M_Y_TICK)
34568 #define M_X_TICK 0xffffU
34569 #define V_X_TICK(x) ((x) << S_X_TICK)
34570 #define G_X_TICK(x) (((x) >> S_X_TICK) & M_X_TICK)
34572 #define A_MAC_PORT_PTP_DRIFT_ADJUST_COUNT 0x9a0
34573 #define A_MAC_PORT_PTP_OFFSET_ADJUST_FINE 0x9a4
34576 #define M_B 0xffffU
34577 #define V_B(x) ((x) << S_B)
34578 #define G_B(x) (((x) >> S_B) & M_B)
34581 #define M_A 0xffffU
34582 #define V_A(x) ((x) << S_A)
34583 #define G_A(x) (((x) >> S_A) & M_A)
34585 #define A_MAC_PORT_PTP_OFFSET_ADJUST_TOTAL 0x9a8
34586 #define A_MAC_PORT_PTP_CFG 0x9ac
34589 #define V_FRZ(x) ((x) << S_FRZ)
34590 #define F_FRZ V_FRZ(1U)
34592 #define S_OFFSER_ADJUST_SIGN 17
34593 #define V_OFFSER_ADJUST_SIGN(x) ((x) << S_OFFSER_ADJUST_SIGN)
34594 #define F_OFFSER_ADJUST_SIGN V_OFFSER_ADJUST_SIGN(1U)
34596 #define S_ADD_OFFSET 16
34597 #define V_ADD_OFFSET(x) ((x) << S_ADD_OFFSET)
34598 #define F_ADD_OFFSET V_ADD_OFFSET(1U)
34601 #define M_CYCLE1 0xffU
34602 #define V_CYCLE1(x) ((x) << S_CYCLE1)
34603 #define G_CYCLE1(x) (((x) >> S_CYCLE1) & M_CYCLE1)
34607 #define V_Q(x) ((x) << S_Q)
34608 #define G_Q(x) (((x) >> S_Q) & M_Q)
34610 #define A_MAC_PORT_MTIP_REVISION 0xa00
34612 #define S_CUSTREV 16
34613 #define M_CUSTREV 0xffffU
34614 #define V_CUSTREV(x) ((x) << S_CUSTREV)
34615 #define G_CUSTREV(x) (((x) >> S_CUSTREV) & M_CUSTREV)
34618 #define M_VER 0xffU
34619 #define V_VER(x) ((x) << S_VER)
34620 #define G_VER(x) (((x) >> S_VER) & M_VER)
34622 #define S_MTIP_REV 0
34623 #define M_MTIP_REV 0xffU
34624 #define V_MTIP_REV(x) ((x) << S_MTIP_REV)
34625 #define G_MTIP_REV(x) (((x) >> S_MTIP_REV) & M_MTIP_REV)
34627 #define A_MAC_PORT_MTIP_SCRATCH 0xa04
34628 #define A_MAC_PORT_MTIP_COMMAND_CONFIG 0xa08
34630 #define S_TX_FLUSH_ENABLE 22
34631 #define V_TX_FLUSH_ENABLE(x) ((x) << S_TX_FLUSH_ENABLE)
34632 #define F_TX_FLUSH_ENABLE V_TX_FLUSH_ENABLE(1U)
34634 #define S_RX_SFD_ANY 21
34635 #define V_RX_SFD_ANY(x) ((x) << S_RX_SFD_ANY)
34636 #define F_RX_SFD_ANY V_RX_SFD_ANY(1U)
34638 #define S_PAUSE_PFC_COMP 20
34639 #define V_PAUSE_PFC_COMP(x) ((x) << S_PAUSE_PFC_COMP)
34640 #define F_PAUSE_PFC_COMP V_PAUSE_PFC_COMP(1U)
34642 #define S_PFC_MODE 19
34643 #define V_PFC_MODE(x) ((x) << S_PFC_MODE)
34644 #define F_PFC_MODE V_PFC_MODE(1U)
34646 #define S_RS_COL_CNT_EXT 18
34647 #define V_RS_COL_CNT_EXT(x) ((x) << S_RS_COL_CNT_EXT)
34648 #define F_RS_COL_CNT_EXT V_RS_COL_CNT_EXT(1U)
34650 #define S_NO_LGTH_CHECK 17
34651 #define V_NO_LGTH_CHECK(x) ((x) << S_NO_LGTH_CHECK)
34652 #define F_NO_LGTH_CHECK V_NO_LGTH_CHECK(1U)
34654 #define S_SEND_IDLE 16
34655 #define V_SEND_IDLE(x) ((x) << S_SEND_IDLE)
34656 #define F_SEND_IDLE V_SEND_IDLE(1U)
34658 #define S_PHY_TXENA 15
34659 #define V_PHY_TXENA(x) ((x) << S_PHY_TXENA)
34660 #define F_PHY_TXENA V_PHY_TXENA(1U)
34662 #define S_RX_ERR_DISC 14
34663 #define V_RX_ERR_DISC(x) ((x) << S_RX_ERR_DISC)
34664 #define F_RX_ERR_DISC V_RX_ERR_DISC(1U)
34666 #define S_CMD_FRAME_ENA 13
34667 #define V_CMD_FRAME_ENA(x) ((x) << S_CMD_FRAME_ENA)
34668 #define F_CMD_FRAME_ENA V_CMD_FRAME_ENA(1U)
34670 #define S_SW_RESET 12
34671 #define V_SW_RESET(x) ((x) << S_SW_RESET)
34672 #define F_SW_RESET V_SW_RESET(1U)
34674 #define S_TX_PAD_EN 11
34675 #define V_TX_PAD_EN(x) ((x) << S_TX_PAD_EN)
34676 #define F_TX_PAD_EN V_TX_PAD_EN(1U)
34678 #define S_PHY_LOOPBACK_EN 10
34679 #define V_PHY_LOOPBACK_EN(x) ((x) << S_PHY_LOOPBACK_EN)
34680 #define F_PHY_LOOPBACK_EN V_PHY_LOOPBACK_EN(1U)
34682 #define S_TX_ADDR_INS 9
34683 #define V_TX_ADDR_INS(x) ((x) << S_TX_ADDR_INS)
34684 #define F_TX_ADDR_INS V_TX_ADDR_INS(1U)
34686 #define S_PAUSE_IGNORE 8
34687 #define V_PAUSE_IGNORE(x) ((x) << S_PAUSE_IGNORE)
34688 #define F_PAUSE_IGNORE V_PAUSE_IGNORE(1U)
34690 #define S_PAUSE_FWD 7
34691 #define V_PAUSE_FWD(x) ((x) << S_PAUSE_FWD)
34692 #define F_PAUSE_FWD V_PAUSE_FWD(1U)
34694 #define S_CRC_FWD 6
34695 #define V_CRC_FWD(x) ((x) << S_CRC_FWD)
34696 #define F_CRC_FWD V_CRC_FWD(1U)
34699 #define V_PAD_EN(x) ((x) << S_PAD_EN)
34700 #define F_PAD_EN V_PAD_EN(1U)
34702 #define S_PROMIS_EN 4
34703 #define V_PROMIS_EN(x) ((x) << S_PROMIS_EN)
34704 #define F_PROMIS_EN V_PROMIS_EN(1U)
34706 #define S_WAN_MODE 3
34707 #define V_WAN_MODE(x) ((x) << S_WAN_MODE)
34708 #define F_WAN_MODE V_WAN_MODE(1U)
34711 #define V_RX_ENA(x) ((x) << S_RX_ENA)
34712 #define F_RX_ENA V_RX_ENA(1U)
34715 #define V_TX_ENA(x) ((x) << S_TX_ENA)
34716 #define F_TX_ENA V_TX_ENA(1U)
34718 #define A_MAC_PORT_MTIP_MAC_ADDR_0 0xa0c
34719 #define A_MAC_PORT_MTIP_MAC_ADDR_1 0xa10
34721 #define S_MACADDRHI 0
34722 #define M_MACADDRHI 0xffffU
34723 #define V_MACADDRHI(x) ((x) << S_MACADDRHI)
34724 #define G_MACADDRHI(x) (((x) >> S_MACADDRHI) & M_MACADDRHI)
34726 #define A_MAC_PORT_MTIP_FRM_LENGTH 0xa14
34729 #define M_LEN 0xffffU
34730 #define V_LEN(x) ((x) << S_LEN)
34731 #define G_LEN(x) (((x) >> S_LEN) & M_LEN)
34733 #define A_MAC_PORT_MTIP_RX_FIFO_SECTIONS 0xa1c
34736 #define M_AVAIL 0xffffU
34737 #define V_AVAIL(x) ((x) << S_AVAIL)
34738 #define G_AVAIL(x) (((x) >> S_AVAIL) & M_AVAIL)
34741 #define M_EMPTY 0xffffU
34742 #define V_EMPTY(x) ((x) << S_EMPTY)
34743 #define G_EMPTY(x) (((x) >> S_EMPTY) & M_EMPTY)
34745 #define A_MAC_PORT_MTIP_TX_FIFO_SECTIONS 0xa20
34746 #define A_MAC_PORT_MTIP_RX_FIFO_ALMOST_F_E 0xa24
34748 #define S_ALMSTFULL 16
34749 #define M_ALMSTFULL 0xffffU
34750 #define V_ALMSTFULL(x) ((x) << S_ALMSTFULL)
34751 #define G_ALMSTFULL(x) (((x) >> S_ALMSTFULL) & M_ALMSTFULL)
34753 #define S_ALMSTEMPTY 0
34754 #define M_ALMSTEMPTY 0xffffU
34755 #define V_ALMSTEMPTY(x) ((x) << S_ALMSTEMPTY)
34756 #define G_ALMSTEMPTY(x) (((x) >> S_ALMSTEMPTY) & M_ALMSTEMPTY)
34758 #define A_MAC_PORT_MTIP_TX_FIFO_ALMOST_F_E 0xa28
34759 #define A_MAC_PORT_MTIP_HASHTABLE_LOAD 0xa2c
34761 #define S_ENABLE_MCAST_RX 8
34762 #define V_ENABLE_MCAST_RX(x) ((x) << S_ENABLE_MCAST_RX)
34763 #define F_ENABLE_MCAST_RX V_ENABLE_MCAST_RX(1U)
34765 #define S_HASHTABLE_ADDR 0
34766 #define M_HASHTABLE_ADDR 0x3fU
34767 #define V_HASHTABLE_ADDR(x) ((x) << S_HASHTABLE_ADDR)
34768 #define G_HASHTABLE_ADDR(x) (((x) >> S_HASHTABLE_ADDR) & M_HASHTABLE_ADDR)
34770 #define A_MAC_PORT_MTIP_MAC_STATUS 0xa40
34772 #define S_TS_AVAIL 3
34773 #define V_TS_AVAIL(x) ((x) << S_TS_AVAIL)
34774 #define F_TS_AVAIL V_TS_AVAIL(1U)
34776 #define S_PHY_LOS 2
34777 #define V_PHY_LOS(x) ((x) << S_PHY_LOS)
34778 #define F_PHY_LOS V_PHY_LOS(1U)
34780 #define S_RX_REM_FAULT 1
34781 #define V_RX_REM_FAULT(x) ((x) << S_RX_REM_FAULT)
34782 #define F_RX_REM_FAULT V_RX_REM_FAULT(1U)
34784 #define S_RX_LOC_FAULT 0
34785 #define V_RX_LOC_FAULT(x) ((x) << S_RX_LOC_FAULT)
34786 #define F_RX_LOC_FAULT V_RX_LOC_FAULT(1U)
34788 #define A_MAC_PORT_MTIP_TX_IPG_LENGTH 0xa44
34791 #define M_IPG 0x7fU
34792 #define V_IPG(x) ((x) << S_IPG)
34793 #define G_IPG(x) (((x) >> S_IPG) & M_IPG)
34795 #define A_MAC_PORT_MTIP_MAC_CREDIT_TRIGGER 0xa48
34797 #define S_RXFIFORST 0
34798 #define V_RXFIFORST(x) ((x) << S_RXFIFORST)
34799 #define F_RXFIFORST V_RXFIFORST(1U)
34801 #define A_MAC_PORT_MTIP_INIT_CREDIT 0xa4c
34803 #define S_MACCRDRST 0
34804 #define M_MACCRDRST 0xffU
34805 #define V_MACCRDRST(x) ((x) << S_MACCRDRST)
34806 #define G_MACCRDRST(x) (((x) >> S_MACCRDRST) & M_MACCRDRST)
34808 #define A_MAC_PORT_MTIP_CURRENT_CREDIT 0xa50
34810 #define S_INITCREDIT 0
34811 #define M_INITCREDIT 0xffU
34812 #define V_INITCREDIT(x) ((x) << S_INITCREDIT)
34813 #define G_INITCREDIT(x) (((x) >> S_INITCREDIT) & M_INITCREDIT)
34815 #define A_MAC_PORT_RX_PAUSE_STATUS 0xa74
34818 #define M_STATUS 0xffU
34819 #define V_STATUS(x) ((x) << S_STATUS)
34820 #define G_STATUS(x) (((x) >> S_STATUS) & M_STATUS)
34822 #define A_MAC_PORT_MTIP_TS_TIMESTAMP 0xa7c
34823 #define A_MAC_PORT_AFRAMESTRANSMITTEDOK 0xa80
34824 #define A_MAC_PORT_AFRAMESTRANSMITTEDOKHI 0xa84
34825 #define A_MAC_PORT_AFRAMESRECEIVEDOK 0xa88
34826 #define A_MAC_PORT_AFRAMESRECEIVEDOKHI 0xa8c
34827 #define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORS 0xa90
34828 #define A_MAC_PORT_AFRAMECHECKSEQUENCEERRORSHI 0xa94
34829 #define A_MAC_PORT_AALIGNMENTERRORS 0xa98
34830 #define A_MAC_PORT_AALIGNMENTERRORSHI 0xa9c
34831 #define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTED 0xaa0
34832 #define A_MAC_PORT_APAUSEMACCTRLFRAMESTRANSMITTEDHI 0xaa4
34833 #define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVED 0xaa8
34834 #define A_MAC_PORT_APAUSEMACCTRLFRAMESRECEIVEDHI 0xaac
34835 #define A_MAC_PORT_AFRAMETOOLONGERRORS 0xab0
34836 #define A_MAC_PORT_AFRAMETOOLONGERRORSHI 0xab4
34837 #define A_MAC_PORT_AINRANGELENGTHERRORS 0xab8
34838 #define A_MAC_PORT_AINRANGELENGTHERRORSHI 0xabc
34839 #define A_MAC_PORT_VLANTRANSMITTEDOK 0xac0
34840 #define A_MAC_PORT_VLANTRANSMITTEDOKHI 0xac4
34841 #define A_MAC_PORT_VLANRECEIVEDOK 0xac8
34842 #define A_MAC_PORT_VLANRECEIVEDOKHI 0xacc
34843 #define A_MAC_PORT_AOCTETSTRANSMITTEDOK 0xad0
34844 #define A_MAC_PORT_AOCTETSTRANSMITTEDOKHI 0xad4
34845 #define A_MAC_PORT_AOCTETSRECEIVEDOK 0xad8
34846 #define A_MAC_PORT_AOCTETSRECEIVEDOKHI 0xadc
34847 #define A_MAC_PORT_IFINUCASTPKTS 0xae0
34848 #define A_MAC_PORT_IFINUCASTPKTSHI 0xae4
34849 #define A_MAC_PORT_IFINMULTICASTPKTS 0xae8
34850 #define A_MAC_PORT_IFINMULTICASTPKTSHI 0xaec
34851 #define A_MAC_PORT_IFINBROADCASTPKTS 0xaf0
34852 #define A_MAC_PORT_IFINBROADCASTPKTSHI 0xaf4
34853 #define A_MAC_PORT_IFOUTERRORS 0xaf8
34854 #define A_MAC_PORT_IFOUTERRORSHI 0xafc
34855 #define A_MAC_PORT_IFOUTUCASTPKTS 0xb08
34856 #define A_MAC_PORT_IFOUTUCASTPKTSHI 0xb0c
34857 #define A_MAC_PORT_IFOUTMULTICASTPKTS 0xb10
34858 #define A_MAC_PORT_IFOUTMULTICASTPKTSHI 0xb14
34859 #define A_MAC_PORT_IFOUTBROADCASTPKTS 0xb18
34860 #define A_MAC_PORT_IFOUTBROADCASTPKTSHI 0xb1c
34861 #define A_MAC_PORT_ETHERSTATSDROPEVENTS 0xb20
34862 #define A_MAC_PORT_ETHERSTATSDROPEVENTSHI 0xb24
34863 #define A_MAC_PORT_ETHERSTATSOCTETS 0xb28
34864 #define A_MAC_PORT_ETHERSTATSOCTETSHI 0xb2c
34865 #define A_MAC_PORT_ETHERSTATSPKTS 0xb30
34866 #define A_MAC_PORT_ETHERSTATSPKTSHI 0xb34
34867 #define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTS 0xb38
34868 #define A_MAC_PORT_ETHERSTATSUNDERSIZEPKTSHI 0xb3c
34869 #define A_MAC_PORT_ETHERSTATSPKTS64OCTETS 0xb40
34870 #define A_MAC_PORT_ETHERSTATSPKTS64OCTETSHI 0xb44
34871 #define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETS 0xb48
34872 #define A_MAC_PORT_ETHERSTATSPKTS65TO127OCTETSHI 0xb4c
34873 #define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETS 0xb50
34874 #define A_MAC_PORT_ETHERSTATSPKTS128TO255OCTETSHI 0xb54
34875 #define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETS 0xb58
34876 #define A_MAC_PORT_ETHERSTATSPKTS256TO511OCTETSHI 0xb5c
34877 #define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETS 0xb60
34878 #define A_MAC_PORT_ETHERSTATSPKTS512TO1023OCTETSHI 0xb64
34879 #define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETS 0xb68
34880 #define A_MAC_PORT_ETHERSTATSPKTS1024TO1518OCTETSHI 0xb6c
34881 #define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETS 0xb70
34882 #define A_MAC_PORT_ETHERSTATSPKTS1519TOMAXOCTETSHI 0xb74
34883 #define A_MAC_PORT_ETHERSTATSOVERSIZEPKTS 0xb78
34884 #define A_MAC_PORT_ETHERSTATSOVERSIZEPKTSHI 0xb7c
34885 #define A_MAC_PORT_ETHERSTATSJABBERS 0xb80
34886 #define A_MAC_PORT_ETHERSTATSJABBERSHI 0xb84
34887 #define A_MAC_PORT_ETHERSTATSFRAGMENTS 0xb88
34888 #define A_MAC_PORT_ETHERSTATSFRAGMENTSHI 0xb8c
34889 #define A_MAC_PORT_IFINERRORS 0xb90
34890 #define A_MAC_PORT_IFINERRORSHI 0xb94
34891 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0 0xb98
34892 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_0HI 0xb9c
34893 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1 0xba0
34894 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_1HI 0xba4
34895 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2 0xba8
34896 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_2HI 0xbac
34897 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3 0xbb0
34898 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_3HI 0xbb4
34899 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4 0xbb8
34900 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_4HI 0xbbc
34901 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5 0xbc0
34902 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_5HI 0xbc4
34903 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6 0xbc8
34904 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_6HI 0xbcc
34905 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7 0xbd0
34906 #define A_MAC_PORT_ACBFCPAUSEFRAMESTRANSMITTED_7HI 0xbd4
34907 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0 0xbd8
34908 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_0HI 0xbdc
34909 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1 0xbe0
34910 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_1HI 0xbe4
34911 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2 0xbe8
34912 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_2HI 0xbec
34913 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3 0xbf0
34914 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_3HI 0xbf4
34915 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4 0xbf8
34916 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_4HI 0xbfc
34917 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5 0xc00
34918 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_5HI 0xc04
34919 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6 0xc08
34920 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_6HI 0xc0c
34921 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7 0xc10
34922 #define A_MAC_PORT_ACBFCPAUSEFRAMESRECEIVED_7HI 0xc14
34923 #define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTED 0xc18
34924 #define A_MAC_PORT_AMACCONTROLFRAMESTRANSMITTEDHI 0xc1c
34925 #define A_MAC_PORT_AMACCONTROLFRAMESRECEIVED 0xc20
34926 #define A_MAC_PORT_AMACCONTROLFRAMESRECEIVEDHI 0xc24
34927 #define A_MAC_PORT_MTIP_SGMII_CONTROL 0xd00
34930 #define V_RESET(x) ((x) << S_RESET)
34931 #define F_RESET V_RESET(1U)
34933 #define S_LOOPBACK 14
34934 #define V_LOOPBACK(x) ((x) << S_LOOPBACK)
34935 #define F_LOOPBACK V_LOOPBACK(1U)
34937 #define S_SPPEDSEL1 13
34938 #define V_SPPEDSEL1(x) ((x) << S_SPPEDSEL1)
34939 #define F_SPPEDSEL1 V_SPPEDSEL1(1U)
34942 #define V_AN_EN(x) ((x) << S_AN_EN)
34943 #define F_AN_EN V_AN_EN(1U)
34945 #define S_PWRDWN 11
34946 #define V_PWRDWN(x) ((x) << S_PWRDWN)
34947 #define F_PWRDWN V_PWRDWN(1U)
34949 #define S_ISOLATE 10
34950 #define V_ISOLATE(x) ((x) << S_ISOLATE)
34951 #define F_ISOLATE V_ISOLATE(1U)
34953 #define S_AN_RESTART 9
34954 #define V_AN_RESTART(x) ((x) << S_AN_RESTART)
34955 #define F_AN_RESTART V_AN_RESTART(1U)
34958 #define V_DPLX(x) ((x) << S_DPLX)
34959 #define F_DPLX V_DPLX(1U)
34961 #define S_COLLISIONTEST 7
34962 #define V_COLLISIONTEST(x) ((x) << S_COLLISIONTEST)
34963 #define F_COLLISIONTEST V_COLLISIONTEST(1U)
34965 #define S_SPEEDSEL0 6
34966 #define V_SPEEDSEL0(x) ((x) << S_SPEEDSEL0)
34967 #define F_SPEEDSEL0 V_SPEEDSEL0(1U)
34969 #define A_MAC_PORT_MTIP_SGMII_STATUS 0xd04
34971 #define S_100BASET4 15
34972 #define V_100BASET4(x) ((x) << S_100BASET4)
34973 #define F_100BASET4 V_100BASET4(1U)
34975 #define S_100BASEXFULLDPLX 14
34976 #define V_100BASEXFULLDPLX(x) ((x) << S_100BASEXFULLDPLX)
34977 #define F_100BASEXFULLDPLX V_100BASEXFULLDPLX(1U)
34979 #define S_100BASEXHALFDPLX 13
34980 #define V_100BASEXHALFDPLX(x) ((x) << S_100BASEXHALFDPLX)
34981 #define F_100BASEXHALFDPLX V_100BASEXHALFDPLX(1U)
34983 #define S_10MBPSFULLDPLX 12
34984 #define V_10MBPSFULLDPLX(x) ((x) << S_10MBPSFULLDPLX)
34985 #define F_10MBPSFULLDPLX V_10MBPSFULLDPLX(1U)
34987 #define S_10MBPSHALFDPLX 11
34988 #define V_10MBPSHALFDPLX(x) ((x) << S_10MBPSHALFDPLX)
34989 #define F_10MBPSHALFDPLX V_10MBPSHALFDPLX(1U)
34991 #define S_100BASET2FULLDPLX 10
34992 #define V_100BASET2FULLDPLX(x) ((x) << S_100BASET2FULLDPLX)
34993 #define F_100BASET2FULLDPLX V_100BASET2FULLDPLX(1U)
34995 #define S_100BASET2HALFDPLX 9
34996 #define V_100BASET2HALFDPLX(x) ((x) << S_100BASET2HALFDPLX)
34997 #define F_100BASET2HALFDPLX V_100BASET2HALFDPLX(1U)
34999 #define S_EXTDSTATUS 8
35000 #define V_EXTDSTATUS(x) ((x) << S_EXTDSTATUS)
35001 #define F_EXTDSTATUS V_EXTDSTATUS(1U)
35003 #define S_SGMII_REM_FAULT 4
35004 #define V_SGMII_REM_FAULT(x) ((x) << S_SGMII_REM_FAULT)
35005 #define F_SGMII_REM_FAULT V_SGMII_REM_FAULT(1U)
35007 #define S_JABBERDETECT 1
35008 #define V_JABBERDETECT(x) ((x) << S_JABBERDETECT)
35009 #define F_JABBERDETECT V_JABBERDETECT(1U)
35011 #define S_EXTDCAPABILITY 0
35012 #define V_EXTDCAPABILITY(x) ((x) << S_EXTDCAPABILITY)
35013 #define F_EXTDCAPABILITY V_EXTDCAPABILITY(1U)
35015 #define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_0 0xd08
35016 #define A_MAC_PORT_MTIP_SGMII_PHY_IDENTIFIER_1 0xd0c
35017 #define A_MAC_PORT_MTIP_SGMII_DEV_ABILITY 0xd10
35020 #define V_RF2(x) ((x) << S_RF2)
35021 #define F_RF2 V_RF2(1U)
35024 #define V_RF1(x) ((x) << S_RF1)
35025 #define F_RF1 V_RF1(1U)
35028 #define V_PS2(x) ((x) << S_PS2)
35029 #define F_PS2 V_PS2(1U)
35032 #define V_PS1(x) ((x) << S_PS1)
35033 #define F_PS1 V_PS1(1U)
35036 #define V_HD(x) ((x) << S_HD)
35037 #define F_HD V_HD(1U)
35040 #define V_FD(x) ((x) << S_FD)
35041 #define F_FD V_FD(1U)
35043 #define A_MAC_PORT_MTIP_SGMII_PARTNER_ABILITY 0xd14
35045 #define S_CULINKSTATUS 15
35046 #define V_CULINKSTATUS(x) ((x) << S_CULINKSTATUS)
35047 #define F_CULINKSTATUS V_CULINKSTATUS(1U)
35049 #define S_CUDPLXSTATUS 12
35050 #define V_CUDPLXSTATUS(x) ((x) << S_CUDPLXSTATUS)
35051 #define F_CUDPLXSTATUS V_CUDPLXSTATUS(1U)
35053 #define S_CUSPEED 10
35054 #define M_CUSPEED 0x3U
35055 #define V_CUSPEED(x) ((x) << S_CUSPEED)
35056 #define G_CUSPEED(x) (((x) >> S_CUSPEED) & M_CUSPEED)
35058 #define A_MAC_PORT_MTIP_SGMII_AN_EXPANSION 0xd18
35061 #define V_PGRCVD(x) ((x) << S_PGRCVD)
35062 #define F_PGRCVD V_PGRCVD(1U)
35064 #define S_REALTIMEPGRCVD 0
35065 #define V_REALTIMEPGRCVD(x) ((x) << S_REALTIMEPGRCVD)
35066 #define F_REALTIMEPGRCVD V_REALTIMEPGRCVD(1U)
35068 #define A_MAC_PORT_MTIP_SGMII_DEVICE_NP 0xd1c
35069 #define A_MAC_PORT_MTIP_SGMII_PARTNER_NP 0xd20
35070 #define A_MAC_PORT_MTIP_SGMII_EXTENDED_STATUS 0xd3c
35071 #define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_LO 0xd48
35073 #define S_COUNT_LO 0
35074 #define M_COUNT_LO 0xffffU
35075 #define V_COUNT_LO(x) ((x) << S_COUNT_LO)
35076 #define G_COUNT_LO(x) (((x) >> S_COUNT_LO) & M_COUNT_LO)
35078 #define A_MAC_PORT_MTIP_SGMII_LINK_TIMER_HI 0xd4c
35080 #define S_COUNT_HI 0
35081 #define M_COUNT_HI 0x1fU
35082 #define V_COUNT_HI(x) ((x) << S_COUNT_HI)
35083 #define G_COUNT_HI(x) (((x) >> S_COUNT_HI) & M_COUNT_HI)
35085 #define A_MAC_PORT_MTIP_SGMII_IF_MODE 0xd50
35087 #define S_SGMII_PCS_ENABLE 5
35088 #define V_SGMII_PCS_ENABLE(x) ((x) << S_SGMII_PCS_ENABLE)
35089 #define F_SGMII_PCS_ENABLE V_SGMII_PCS_ENABLE(1U)
35091 #define S_SGMII_HDUPLEX 4
35092 #define V_SGMII_HDUPLEX(x) ((x) << S_SGMII_HDUPLEX)
35093 #define F_SGMII_HDUPLEX V_SGMII_HDUPLEX(1U)
35095 #define S_SGMII_SPEED 2
35096 #define M_SGMII_SPEED 0x3U
35097 #define V_SGMII_SPEED(x) ((x) << S_SGMII_SPEED)
35098 #define G_SGMII_SPEED(x) (((x) >> S_SGMII_SPEED) & M_SGMII_SPEED)
35100 #define S_USE_SGMII_AN 1
35101 #define V_USE_SGMII_AN(x) ((x) << S_USE_SGMII_AN)
35102 #define F_USE_SGMII_AN V_USE_SGMII_AN(1U)
35104 #define S_SGMII_ENA 0
35105 #define V_SGMII_ENA(x) ((x) << S_SGMII_ENA)
35106 #define F_SGMII_ENA V_SGMII_ENA(1U)
35108 #define A_MAC_PORT_MTIP_ACT_CTL_SEG 0x1200
35111 #define M_ACTIVE 0x3fU
35112 #define V_ACTIVE(x) ((x) << S_ACTIVE)
35113 #define G_ACTIVE(x) (((x) >> S_ACTIVE) & M_ACTIVE)
35115 #define A_MAC_PORT_MTIP_MODE_CTL_SEG 0x1204
35117 #define S_MODE_CTL 0
35118 #define M_MODE_CTL 0x3U
35119 #define V_MODE_CTL(x) ((x) << S_MODE_CTL)
35120 #define G_MODE_CTL(x) (((x) >> S_MODE_CTL) & M_MODE_CTL)
35122 #define A_MAC_PORT_MTIP_TXCLK_CTL_SEG 0x1208
35124 #define S_TXCLK_CTL 0
35125 #define M_TXCLK_CTL 0xffffU
35126 #define V_TXCLK_CTL(x) ((x) << S_TXCLK_CTL)
35127 #define G_TXCLK_CTL(x) (((x) >> S_TXCLK_CTL) & M_TXCLK_CTL)
35129 #define A_MAC_PORT_MTIP_TX_PRMBL_CTL_SEG 0x120c
35130 #define A_MAC_PORT_MTIP_WAN_RS_COL_CNT 0x1220
35132 #define S_COL_CNT 0
35133 #define M_COL_CNT 0xffffU
35134 #define V_COL_CNT(x) ((x) << S_COL_CNT)
35135 #define G_COL_CNT(x) (((x) >> S_COL_CNT) & M_COL_CNT)
35137 #define A_MAC_PORT_MTIP_VL_INTVL 0x1240
35139 #define S_VL_INTVL 1
35140 #define V_VL_INTVL(x) ((x) << S_VL_INTVL)
35141 #define F_VL_INTVL V_VL_INTVL(1U)
35143 #define A_MAC_PORT_MTIP_MDIO_CFG_STATUS 0x1600
35145 #define S_CLK_DIV 7
35146 #define M_CLK_DIV 0x1ffU
35147 #define V_CLK_DIV(x) ((x) << S_CLK_DIV)
35148 #define G_CLK_DIV(x) (((x) >> S_CLK_DIV) & M_CLK_DIV)
35150 #define S_CL45_EN 6
35151 #define V_CL45_EN(x) ((x) << S_CL45_EN)
35152 #define F_CL45_EN V_CL45_EN(1U)
35154 #define S_DISABLE_PREAMBLE 5
35155 #define V_DISABLE_PREAMBLE(x) ((x) << S_DISABLE_PREAMBLE)
35156 #define F_DISABLE_PREAMBLE V_DISABLE_PREAMBLE(1U)
35158 #define S_MDIO_HOLD_TIME 2
35159 #define M_MDIO_HOLD_TIME 0x7U
35160 #define V_MDIO_HOLD_TIME(x) ((x) << S_MDIO_HOLD_TIME)
35161 #define G_MDIO_HOLD_TIME(x) (((x) >> S_MDIO_HOLD_TIME) & M_MDIO_HOLD_TIME)
35163 #define S_MDIO_READ_ERR 1
35164 #define V_MDIO_READ_ERR(x) ((x) << S_MDIO_READ_ERR)
35165 #define F_MDIO_READ_ERR V_MDIO_READ_ERR(1U)
35167 #define S_MDIO_BUSY 0
35168 #define V_MDIO_BUSY(x) ((x) << S_MDIO_BUSY)
35169 #define F_MDIO_BUSY V_MDIO_BUSY(1U)
35171 #define A_MAC_PORT_MTIP_MDIO_COMMAND 0x1604
35173 #define S_MDIO_CMD_READ 15
35174 #define V_MDIO_CMD_READ(x) ((x) << S_MDIO_CMD_READ)
35175 #define F_MDIO_CMD_READ V_MDIO_CMD_READ(1U)
35177 #define S_READ_INCR 14
35178 #define V_READ_INCR(x) ((x) << S_READ_INCR)
35179 #define F_READ_INCR V_READ_INCR(1U)
35181 #define S_PORT_ADDR 5
35182 #define M_PORT_ADDR 0x1fU
35183 #define V_PORT_ADDR(x) ((x) << S_PORT_ADDR)
35184 #define G_PORT_ADDR(x) (((x) >> S_PORT_ADDR) & M_PORT_ADDR)
35186 #define S_DEV_ADDR 0
35187 #define M_DEV_ADDR 0x1fU
35188 #define V_DEV_ADDR(x) ((x) << S_DEV_ADDR)
35189 #define G_DEV_ADDR(x) (((x) >> S_DEV_ADDR) & M_DEV_ADDR)
35191 #define A_MAC_PORT_MTIP_MDIO_DATA 0x1608
35193 #define S_READBUSY 31
35194 #define V_READBUSY(x) ((x) << S_READBUSY)
35195 #define F_READBUSY V_READBUSY(1U)
35197 #define S_DATA_WORD 0
35198 #define M_DATA_WORD 0xffffU
35199 #define V_DATA_WORD(x) ((x) << S_DATA_WORD)
35200 #define G_DATA_WORD(x) (((x) >> S_DATA_WORD) & M_DATA_WORD)
35202 #define A_MAC_PORT_MTIP_MDIO_REGADDR 0x160c
35204 #define S_MDIO_ADDR 0
35205 #define M_MDIO_ADDR 0xffffU
35206 #define V_MDIO_ADDR(x) ((x) << S_MDIO_ADDR)
35207 #define G_MDIO_ADDR(x) (((x) >> S_MDIO_ADDR) & M_MDIO_ADDR)
35209 #define A_MAC_PORT_MTIP_VLAN_TPID_0 0x1a00
35211 #if 0 /* M_VLANTAG collides with M_VLANTAG in sys/mbuf.h */
35212 #define S_VLANTAG 0
35213 #define M_VLANTAG 0xffffU
35214 #define V_VLANTAG(x) ((x) << S_VLANTAG)
35215 #define G_VLANTAG(x) (((x) >> S_VLANTAG) & M_VLANTAG)
35218 #define A_MAC_PORT_MTIP_VLAN_TPID_1 0x1a04
35219 #define A_MAC_PORT_MTIP_VLAN_TPID_2 0x1a08
35220 #define A_MAC_PORT_MTIP_VLAN_TPID_3 0x1a0c
35221 #define A_MAC_PORT_MTIP_VLAN_TPID_4 0x1a10
35222 #define A_MAC_PORT_MTIP_VLAN_TPID_5 0x1a14
35223 #define A_MAC_PORT_MTIP_VLAN_TPID_6 0x1a18
35224 #define A_MAC_PORT_MTIP_VLAN_TPID_7 0x1a1c
35225 #define A_MAC_PORT_MTIP_PCS_CTL 0x1e00
35227 #define S_PCS_LPBK 14
35228 #define V_PCS_LPBK(x) ((x) << S_PCS_LPBK)
35229 #define F_PCS_LPBK V_PCS_LPBK(1U)
35231 #define S_SPEED_SEL1 13
35232 #define V_SPEED_SEL1(x) ((x) << S_SPEED_SEL1)
35233 #define F_SPEED_SEL1 V_SPEED_SEL1(1U)
35235 #define S_LP_MODE 11
35236 #define V_LP_MODE(x) ((x) << S_LP_MODE)
35237 #define F_LP_MODE V_LP_MODE(1U)
35239 #define S_SPEED_SEL0 6
35240 #define V_SPEED_SEL0(x) ((x) << S_SPEED_SEL0)
35241 #define F_SPEED_SEL0 V_SPEED_SEL0(1U)
35243 #define S_PCS_SPEED 2
35244 #define M_PCS_SPEED 0xfU
35245 #define V_PCS_SPEED(x) ((x) << S_PCS_SPEED)
35246 #define G_PCS_SPEED(x) (((x) >> S_PCS_SPEED) & M_PCS_SPEED)
35248 #define A_MAC_PORT_MTIP_PCS_STATUS1 0x1e04
35250 #define S_FAULTDET 7
35251 #define V_FAULTDET(x) ((x) << S_FAULTDET)
35252 #define F_FAULTDET V_FAULTDET(1U)
35254 #define S_RX_LINK_STATUS 2
35255 #define V_RX_LINK_STATUS(x) ((x) << S_RX_LINK_STATUS)
35256 #define F_RX_LINK_STATUS V_RX_LINK_STATUS(1U)
35258 #define S_LOPWRABL 1
35259 #define V_LOPWRABL(x) ((x) << S_LOPWRABL)
35260 #define F_LOPWRABL V_LOPWRABL(1U)
35262 #define A_MAC_PORT_MTIP_PCS_DEVICE_ID0 0x1e08
35264 #define S_DEVICE_ID0 0
35265 #define M_DEVICE_ID0 0xffffU
35266 #define V_DEVICE_ID0(x) ((x) << S_DEVICE_ID0)
35267 #define G_DEVICE_ID0(x) (((x) >> S_DEVICE_ID0) & M_DEVICE_ID0)
35269 #define A_MAC_PORT_MTIP_PCS_DEVICE_ID1 0x1e0c
35271 #define S_DEVICE_ID1 0
35272 #define M_DEVICE_ID1 0xffffU
35273 #define V_DEVICE_ID1(x) ((x) << S_DEVICE_ID1)
35274 #define G_DEVICE_ID1(x) (((x) >> S_DEVICE_ID1) & M_DEVICE_ID1)
35276 #define A_MAC_PORT_MTIP_PCS_SPEED_ABILITY 0x1e10
35279 #define V_100G(x) ((x) << S_100G)
35280 #define F_100G V_100G(1U)
35283 #define V_40G(x) ((x) << S_40G)
35284 #define F_40G V_40G(1U)
35286 #define S_10BASE_TL 1
35287 #define V_10BASE_TL(x) ((x) << S_10BASE_TL)
35288 #define F_10BASE_TL V_10BASE_TL(1U)
35291 #define V_10G(x) ((x) << S_10G)
35292 #define F_10G V_10G(1U)
35294 #define A_MAC_PORT_MTIP_PCS_DEVICE_PKG1 0x1e14
35296 #define S_TC_PRESENT 6
35297 #define V_TC_PRESENT(x) ((x) << S_TC_PRESENT)
35298 #define F_TC_PRESENT V_TC_PRESENT(1U)
35301 #define V_DTEXS(x) ((x) << S_DTEXS)
35302 #define F_DTEXS V_DTEXS(1U)
35305 #define V_PHYXS(x) ((x) << S_PHYXS)
35306 #define F_PHYXS V_PHYXS(1U)
35309 #define V_PCS(x) ((x) << S_PCS)
35310 #define F_PCS V_PCS(1U)
35313 #define V_WIS(x) ((x) << S_WIS)
35314 #define F_WIS V_WIS(1U)
35316 #define S_PMD_PMA 1
35317 #define V_PMD_PMA(x) ((x) << S_PMD_PMA)
35318 #define F_PMD_PMA V_PMD_PMA(1U)
35321 #define V_CL22(x) ((x) << S_CL22)
35322 #define F_CL22 V_CL22(1U)
35324 #define A_MAC_PORT_MTIP_PCS_DEVICE_PKG2 0x1e18
35326 #define S_VENDDEV2 15
35327 #define V_VENDDEV2(x) ((x) << S_VENDDEV2)
35328 #define F_VENDDEV2 V_VENDDEV2(1U)
35330 #define S_VENDDEV1 14
35331 #define V_VENDDEV1(x) ((x) << S_VENDDEV1)
35332 #define F_VENDDEV1 V_VENDDEV1(1U)
35334 #define S_CL22EXT 13
35335 #define V_CL22EXT(x) ((x) << S_CL22EXT)
35336 #define F_CL22EXT V_CL22EXT(1U)
35338 #define A_MAC_PORT_MTIP_PCS_CTL2 0x1e1c
35340 #define S_PCSTYPE 0
35341 #define M_PCSTYPE 0x7U
35342 #define V_PCSTYPE(x) ((x) << S_PCSTYPE)
35343 #define G_PCSTYPE(x) (((x) >> S_PCSTYPE) & M_PCSTYPE)
35345 #define A_MAC_PORT_MTIP_PCS_STATUS2 0x1e20
35347 #define S_PCS_STAT2_DEVICE 15
35348 #define V_PCS_STAT2_DEVICE(x) ((x) << S_PCS_STAT2_DEVICE)
35349 #define F_PCS_STAT2_DEVICE V_PCS_STAT2_DEVICE(1U)
35351 #define S_TXFAULT 7
35352 #define V_TXFAULT(x) ((x) << S_TXFAULT)
35353 #define F_TXFAULT V_TXFAULT(1U)
35355 #define S_RXFAULT 6
35356 #define V_RXFAULT(x) ((x) << S_RXFAULT)
35357 #define F_RXFAULT V_RXFAULT(1U)
35359 #define S_100BASE_R 5
35360 #define V_100BASE_R(x) ((x) << S_100BASE_R)
35361 #define F_100BASE_R V_100BASE_R(1U)
35363 #define S_40GBASE_R 4
35364 #define V_40GBASE_R(x) ((x) << S_40GBASE_R)
35365 #define F_40GBASE_R V_40GBASE_R(1U)
35367 #define S_10GBASE_T 3
35368 #define V_10GBASE_T(x) ((x) << S_10GBASE_T)
35369 #define F_10GBASE_T V_10GBASE_T(1U)
35371 #define S_10GBASE_W 2
35372 #define V_10GBASE_W(x) ((x) << S_10GBASE_W)
35373 #define F_10GBASE_W V_10GBASE_W(1U)
35375 #define S_10GBASE_X 1
35376 #define V_10GBASE_X(x) ((x) << S_10GBASE_X)
35377 #define F_10GBASE_X V_10GBASE_X(1U)
35379 #define S_10GBASE_R 0
35380 #define V_10GBASE_R(x) ((x) << S_10GBASE_R)
35381 #define F_10GBASE_R V_10GBASE_R(1U)
35383 #define A_MAC_PORT_MTIP_PCS_PKG_ID0 0x1e38
35385 #define S_PKG_ID0 0
35386 #define M_PKG_ID0 0xffffU
35387 #define V_PKG_ID0(x) ((x) << S_PKG_ID0)
35388 #define G_PKG_ID0(x) (((x) >> S_PKG_ID0) & M_PKG_ID0)
35390 #define A_MAC_PORT_MTIP_PCS_PKG_ID1 0x1e3c
35392 #define S_PKG_ID1 0
35393 #define M_PKG_ID1 0xffffU
35394 #define V_PKG_ID1(x) ((x) << S_PKG_ID1)
35395 #define G_PKG_ID1(x) (((x) >> S_PKG_ID1) & M_PKG_ID1)
35397 #define A_MAC_PORT_MTIP_PCS_BASER_STATUS1 0x1e80
35399 #define S_RXLINKSTATUS 12
35400 #define V_RXLINKSTATUS(x) ((x) << S_RXLINKSTATUS)
35401 #define F_RXLINKSTATUS V_RXLINKSTATUS(1U)
35403 #define S_RESEREVED 4
35404 #define M_RESEREVED 0xffU
35405 #define V_RESEREVED(x) ((x) << S_RESEREVED)
35406 #define G_RESEREVED(x) (((x) >> S_RESEREVED) & M_RESEREVED)
35408 #define S_10GPRBS9 3
35409 #define V_10GPRBS9(x) ((x) << S_10GPRBS9)
35410 #define F_10GPRBS9 V_10GPRBS9(1U)
35412 #define S_10GPRBS31 2
35413 #define V_10GPRBS31(x) ((x) << S_10GPRBS31)
35414 #define F_10GPRBS31 V_10GPRBS31(1U)
35417 #define V_HIBER(x) ((x) << S_HIBER)
35418 #define F_HIBER V_HIBER(1U)
35420 #define S_BLOCKLOCK 0
35421 #define V_BLOCKLOCK(x) ((x) << S_BLOCKLOCK)
35422 #define F_BLOCKLOCK V_BLOCKLOCK(1U)
35424 #define A_MAC_PORT_MTIP_PCS_BASER_STATUS2 0x1e84
35426 #define S_BLOCKLOCKLL 15
35427 #define V_BLOCKLOCKLL(x) ((x) << S_BLOCKLOCKLL)
35428 #define F_BLOCKLOCKLL V_BLOCKLOCKLL(1U)
35430 #define S_HIBERLH 14
35431 #define V_HIBERLH(x) ((x) << S_HIBERLH)
35432 #define F_HIBERLH V_HIBERLH(1U)
35434 #define S_HIBERCOUNT 8
35435 #define M_HIBERCOUNT 0x3fU
35436 #define V_HIBERCOUNT(x) ((x) << S_HIBERCOUNT)
35437 #define G_HIBERCOUNT(x) (((x) >> S_HIBERCOUNT) & M_HIBERCOUNT)
35439 #define S_ERRBLKCNT 0
35440 #define M_ERRBLKCNT 0xffU
35441 #define V_ERRBLKCNT(x) ((x) << S_ERRBLKCNT)
35442 #define G_ERRBLKCNT(x) (((x) >> S_ERRBLKCNT) & M_ERRBLKCNT)
35444 #define A_MAC_PORT_MTIP_10GBASER_SEED_A 0x1e88
35447 #define M_SEEDA 0xffffU
35448 #define V_SEEDA(x) ((x) << S_SEEDA)
35449 #define G_SEEDA(x) (((x) >> S_SEEDA) & M_SEEDA)
35451 #define A_MAC_PORT_MTIP_10GBASER_SEED_A1 0x1e8c
35454 #define M_SEEDA1 0xffffU
35455 #define V_SEEDA1(x) ((x) << S_SEEDA1)
35456 #define G_SEEDA1(x) (((x) >> S_SEEDA1) & M_SEEDA1)
35458 #define A_MAC_PORT_MTIP_10GBASER_SEED_A2 0x1e90
35461 #define M_SEEDA2 0xffffU
35462 #define V_SEEDA2(x) ((x) << S_SEEDA2)
35463 #define G_SEEDA2(x) (((x) >> S_SEEDA2) & M_SEEDA2)
35465 #define A_MAC_PORT_MTIP_10GBASER_SEED_A3 0x1e94
35468 #define M_SEEDA3 0x3ffU
35469 #define V_SEEDA3(x) ((x) << S_SEEDA3)
35470 #define G_SEEDA3(x) (((x) >> S_SEEDA3) & M_SEEDA3)
35472 #define A_MAC_PORT_MTIP_10GBASER_SEED_B 0x1e98
35475 #define M_SEEDB 0xffffU
35476 #define V_SEEDB(x) ((x) << S_SEEDB)
35477 #define G_SEEDB(x) (((x) >> S_SEEDB) & M_SEEDB)
35479 #define A_MAC_PORT_MTIP_10GBASER_SEED_B1 0x1e9c
35482 #define M_SEEDB1 0xffffU
35483 #define V_SEEDB1(x) ((x) << S_SEEDB1)
35484 #define G_SEEDB1(x) (((x) >> S_SEEDB1) & M_SEEDB1)
35486 #define A_MAC_PORT_MTIP_10GBASER_SEED_B2 0x1ea0
35489 #define M_SEEDB2 0xffffU
35490 #define V_SEEDB2(x) ((x) << S_SEEDB2)
35491 #define G_SEEDB2(x) (((x) >> S_SEEDB2) & M_SEEDB2)
35493 #define A_MAC_PORT_MTIP_10GBASER_SEED_B3 0x1ea4
35496 #define M_SEEDB3 0x3ffU
35497 #define V_SEEDB3(x) ((x) << S_SEEDB3)
35498 #define G_SEEDB3(x) (((x) >> S_SEEDB3) & M_SEEDB3)
35500 #define A_MAC_PORT_MTIP_BASER_TEST_CTRL 0x1ea8
35502 #define S_TXPRBS9 6
35503 #define V_TXPRBS9(x) ((x) << S_TXPRBS9)
35504 #define F_TXPRBS9 V_TXPRBS9(1U)
35506 #define S_RXPRBS31 5
35507 #define V_RXPRBS31(x) ((x) << S_RXPRBS31)
35508 #define F_RXPRBS31 V_RXPRBS31(1U)
35510 #define S_TXPRBS31 4
35511 #define V_TXPRBS31(x) ((x) << S_TXPRBS31)
35512 #define F_TXPRBS31 V_TXPRBS31(1U)
35514 #define S_TXTESTPATEN 3
35515 #define V_TXTESTPATEN(x) ((x) << S_TXTESTPATEN)
35516 #define F_TXTESTPATEN V_TXTESTPATEN(1U)
35518 #define S_RXTESTPATEN 2
35519 #define V_RXTESTPATEN(x) ((x) << S_RXTESTPATEN)
35520 #define F_RXTESTPATEN V_RXTESTPATEN(1U)
35522 #define S_TESTPATSEL 1
35523 #define V_TESTPATSEL(x) ((x) << S_TESTPATSEL)
35524 #define F_TESTPATSEL V_TESTPATSEL(1U)
35526 #define S_DATAPATSEL 0
35527 #define V_DATAPATSEL(x) ((x) << S_DATAPATSEL)
35528 #define F_DATAPATSEL V_DATAPATSEL(1U)
35530 #define A_MAC_PORT_MTIP_BASER_TEST_ERR_CNT 0x1eac
35532 #define S_TEST_ERR_CNT 0
35533 #define M_TEST_ERR_CNT 0xffffU
35534 #define V_TEST_ERR_CNT(x) ((x) << S_TEST_ERR_CNT)
35535 #define G_TEST_ERR_CNT(x) (((x) >> S_TEST_ERR_CNT) & M_TEST_ERR_CNT)
35537 #define A_MAC_PORT_MTIP_BER_HIGH_ORDER_CNT 0x1eb0
35539 #define S_BER_CNT_HI 0
35540 #define M_BER_CNT_HI 0xffffU
35541 #define V_BER_CNT_HI(x) ((x) << S_BER_CNT_HI)
35542 #define G_BER_CNT_HI(x) (((x) >> S_BER_CNT_HI) & M_BER_CNT_HI)
35544 #define A_MAC_PORT_MTIP_BLK_HIGH_ORDER_CNT 0x1eb4
35546 #define S_HICOUNTPRSNT 15
35547 #define V_HICOUNTPRSNT(x) ((x) << S_HICOUNTPRSNT)
35548 #define F_HICOUNTPRSNT V_HICOUNTPRSNT(1U)
35550 #define S_BLOCK_CNT_HI 0
35551 #define M_BLOCK_CNT_HI 0x3fffU
35552 #define V_BLOCK_CNT_HI(x) ((x) << S_BLOCK_CNT_HI)
35553 #define G_BLOCK_CNT_HI(x) (((x) >> S_BLOCK_CNT_HI) & M_BLOCK_CNT_HI)
35555 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS1 0x1ec8
35557 #define S_ALIGNSTATUS 12
35558 #define V_ALIGNSTATUS(x) ((x) << S_ALIGNSTATUS)
35559 #define F_ALIGNSTATUS V_ALIGNSTATUS(1U)
35562 #define V_LANE7(x) ((x) << S_LANE7)
35563 #define F_LANE7 V_LANE7(1U)
35566 #define V_LANE6(x) ((x) << S_LANE6)
35567 #define F_LANE6 V_LANE6(1U)
35570 #define V_LANE5(x) ((x) << S_LANE5)
35571 #define F_LANE5 V_LANE5(1U)
35574 #define V_LANE4(x) ((x) << S_LANE4)
35575 #define F_LANE4 V_LANE4(1U)
35578 #define V_LANE3(x) ((x) << S_LANE3)
35579 #define F_LANE3 V_LANE3(1U)
35582 #define V_LANE2(x) ((x) << S_LANE2)
35583 #define F_LANE2 V_LANE2(1U)
35586 #define V_LANE1(x) ((x) << S_LANE1)
35587 #define F_LANE1 V_LANE1(1U)
35590 #define V_LANE0(x) ((x) << S_LANE0)
35591 #define F_LANE0 V_LANE0(1U)
35593 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS2 0x1ecc
35595 #define S_LANE19 11
35596 #define V_LANE19(x) ((x) << S_LANE19)
35597 #define F_LANE19 V_LANE19(1U)
35599 #define S_LANE18 10
35600 #define V_LANE18(x) ((x) << S_LANE18)
35601 #define F_LANE18 V_LANE18(1U)
35604 #define V_LANE17(x) ((x) << S_LANE17)
35605 #define F_LANE17 V_LANE17(1U)
35608 #define V_LANE16(x) ((x) << S_LANE16)
35609 #define F_LANE16 V_LANE16(1U)
35612 #define V_LANE15(x) ((x) << S_LANE15)
35613 #define F_LANE15 V_LANE15(1U)
35616 #define V_LANE14(x) ((x) << S_LANE14)
35617 #define F_LANE14 V_LANE14(1U)
35620 #define V_LANE13(x) ((x) << S_LANE13)
35621 #define F_LANE13 V_LANE13(1U)
35624 #define V_LANE12(x) ((x) << S_LANE12)
35625 #define F_LANE12 V_LANE12(1U)
35628 #define V_LANE11(x) ((x) << S_LANE11)
35629 #define F_LANE11 V_LANE11(1U)
35632 #define V_LANE10(x) ((x) << S_LANE10)
35633 #define F_LANE10 V_LANE10(1U)
35636 #define V_LANE9(x) ((x) << S_LANE9)
35637 #define F_LANE9 V_LANE9(1U)
35640 #define V_LANE8(x) ((x) << S_LANE8)
35641 #define F_LANE8 V_LANE8(1U)
35643 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS3 0x1ed0
35645 #define S_AMLOCK7 7
35646 #define V_AMLOCK7(x) ((x) << S_AMLOCK7)
35647 #define F_AMLOCK7 V_AMLOCK7(1U)
35649 #define S_AMLOCK6 6
35650 #define V_AMLOCK6(x) ((x) << S_AMLOCK6)
35651 #define F_AMLOCK6 V_AMLOCK6(1U)
35653 #define S_AMLOCK5 5
35654 #define V_AMLOCK5(x) ((x) << S_AMLOCK5)
35655 #define F_AMLOCK5 V_AMLOCK5(1U)
35657 #define S_AMLOCK4 4
35658 #define V_AMLOCK4(x) ((x) << S_AMLOCK4)
35659 #define F_AMLOCK4 V_AMLOCK4(1U)
35661 #define S_AMLOCK3 3
35662 #define V_AMLOCK3(x) ((x) << S_AMLOCK3)
35663 #define F_AMLOCK3 V_AMLOCK3(1U)
35665 #define S_AMLOCK2 2
35666 #define V_AMLOCK2(x) ((x) << S_AMLOCK2)
35667 #define F_AMLOCK2 V_AMLOCK2(1U)
35669 #define S_AMLOCK1 1
35670 #define V_AMLOCK1(x) ((x) << S_AMLOCK1)
35671 #define F_AMLOCK1 V_AMLOCK1(1U)
35673 #define S_AMLOCK0 0
35674 #define V_AMLOCK0(x) ((x) << S_AMLOCK0)
35675 #define F_AMLOCK0 V_AMLOCK0(1U)
35677 #define A_MAC_PORT_MTIP_PCS_MULTI_LANE_ALIGN_STATUS4 0x1ed4
35679 #define S_AMLOCK19 11
35680 #define V_AMLOCK19(x) ((x) << S_AMLOCK19)
35681 #define F_AMLOCK19 V_AMLOCK19(1U)
35683 #define S_AMLOCK18 10
35684 #define V_AMLOCK18(x) ((x) << S_AMLOCK18)
35685 #define F_AMLOCK18 V_AMLOCK18(1U)
35687 #define S_AMLOCK17 9
35688 #define V_AMLOCK17(x) ((x) << S_AMLOCK17)
35689 #define F_AMLOCK17 V_AMLOCK17(1U)
35691 #define S_AMLOCK16 8
35692 #define V_AMLOCK16(x) ((x) << S_AMLOCK16)
35693 #define F_AMLOCK16 V_AMLOCK16(1U)
35695 #define S_AMLOCK15 7
35696 #define V_AMLOCK15(x) ((x) << S_AMLOCK15)
35697 #define F_AMLOCK15 V_AMLOCK15(1U)
35699 #define S_AMLOCK14 6
35700 #define V_AMLOCK14(x) ((x) << S_AMLOCK14)
35701 #define F_AMLOCK14 V_AMLOCK14(1U)
35703 #define S_AMLOCK13 5
35704 #define V_AMLOCK13(x) ((x) << S_AMLOCK13)
35705 #define F_AMLOCK13 V_AMLOCK13(1U)
35707 #define S_AMLOCK12 4
35708 #define V_AMLOCK12(x) ((x) << S_AMLOCK12)
35709 #define F_AMLOCK12 V_AMLOCK12(1U)
35711 #define S_AMLOCK11 3
35712 #define V_AMLOCK11(x) ((x) << S_AMLOCK11)
35713 #define F_AMLOCK11 V_AMLOCK11(1U)
35715 #define S_AMLOCK10 2
35716 #define V_AMLOCK10(x) ((x) << S_AMLOCK10)
35717 #define F_AMLOCK10 V_AMLOCK10(1U)
35719 #define S_AMLOCK9 1
35720 #define V_AMLOCK9(x) ((x) << S_AMLOCK9)
35721 #define F_AMLOCK9 V_AMLOCK9(1U)
35723 #define S_AMLOCK8 0
35724 #define V_AMLOCK8(x) ((x) << S_AMLOCK8)
35725 #define F_AMLOCK8 V_AMLOCK8(1U)
35727 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_0 0x1f68
35729 #define S_BIPERR_CNT 0
35730 #define M_BIPERR_CNT 0xffffU
35731 #define V_BIPERR_CNT(x) ((x) << S_BIPERR_CNT)
35732 #define G_BIPERR_CNT(x) (((x) >> S_BIPERR_CNT) & M_BIPERR_CNT)
35734 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_1 0x1f6c
35735 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_2 0x1f70
35736 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_3 0x1f74
35737 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_4 0x1f78
35738 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_5 0x1f7c
35739 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_6 0x1f80
35740 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_7 0x1f84
35741 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_8 0x1f88
35742 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_9 0x1f8c
35743 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_10 0x1f90
35744 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_11 0x1f94
35745 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_12 0x1f98
35746 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_13 0x1f9c
35747 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_14 0x1fa0
35748 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_15 0x1fa4
35749 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_16 0x1fa8
35750 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_17 0x1fac
35751 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_18 0x1fb0
35752 #define A_MAC_PORT_MTIP_PCS_BIP_ERR_CNT_19 0x1fb4
35753 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_0 0x1fb8
35756 #define M_MAP 0x1fU
35757 #define V_MAP(x) ((x) << S_MAP)
35758 #define G_MAP(x) (((x) >> S_MAP) & M_MAP)
35760 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_1 0x1fbc
35761 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_2 0x1fc0
35762 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_3 0x1fc4
35763 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_4 0x1fc8
35764 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_5 0x1fcc
35765 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_6 0x1fd0
35766 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_7 0x1fd4
35767 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_8 0x1fd8
35768 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_9 0x1fdc
35769 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_10 0x1fe0
35770 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_11 0x1fe4
35771 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_12 0x1fe8
35772 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_13 0x1fec
35773 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_14 0x1ff0
35774 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_15 0x1ff4
35775 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_16 0x1ff8
35776 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_17 0x1ffc
35777 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_18 0x2000
35778 #define A_MAC_PORT_MTIP_PCS_LANE_MAP_19 0x2004
35779 #define A_MAC_PORT_BEAN_CTL 0x2200
35781 #define S_AN_RESET 15
35782 #define V_AN_RESET(x) ((x) << S_AN_RESET)
35783 #define F_AN_RESET V_AN_RESET(1U)
35785 #define S_EXT_NXP_CTRL 13
35786 #define V_EXT_NXP_CTRL(x) ((x) << S_EXT_NXP_CTRL)
35787 #define F_EXT_NXP_CTRL V_EXT_NXP_CTRL(1U)
35789 #define S_BEAN_EN 12
35790 #define V_BEAN_EN(x) ((x) << S_BEAN_EN)
35791 #define F_BEAN_EN V_BEAN_EN(1U)
35793 #define S_RESTART_BEAN 9
35794 #define V_RESTART_BEAN(x) ((x) << S_RESTART_BEAN)
35795 #define F_RESTART_BEAN V_RESTART_BEAN(1U)
35797 #define A_MAC_PORT_BEAN_STATUS 0x2204
35800 #define V_PDF(x) ((x) << S_PDF)
35801 #define F_PDF V_PDF(1U)
35803 #define S_EXT_NXP_STATUS 7
35804 #define V_EXT_NXP_STATUS(x) ((x) << S_EXT_NXP_STATUS)
35805 #define F_EXT_NXP_STATUS V_EXT_NXP_STATUS(1U)
35807 #define S_PAGE_RCVD 6
35808 #define V_PAGE_RCVD(x) ((x) << S_PAGE_RCVD)
35809 #define F_PAGE_RCVD V_PAGE_RCVD(1U)
35811 #define S_BEAN_COMPLETE 5
35812 #define V_BEAN_COMPLETE(x) ((x) << S_BEAN_COMPLETE)
35813 #define F_BEAN_COMPLETE V_BEAN_COMPLETE(1U)
35815 #define S_REM_FAULT_STATUS 4
35816 #define V_REM_FAULT_STATUS(x) ((x) << S_REM_FAULT_STATUS)
35817 #define F_REM_FAULT_STATUS V_REM_FAULT_STATUS(1U)
35819 #define S_BEAN_ABILITY 3
35820 #define V_BEAN_ABILITY(x) ((x) << S_BEAN_ABILITY)
35821 #define F_BEAN_ABILITY V_BEAN_ABILITY(1U)
35823 #define S_LP_BEAN_ABILITY 0
35824 #define V_LP_BEAN_ABILITY(x) ((x) << S_LP_BEAN_ABILITY)
35825 #define F_LP_BEAN_ABILITY V_LP_BEAN_ABILITY(1U)
35827 #define A_MAC_PORT_BEAN_ABILITY_0 0x2208
35830 #define V_NXP(x) ((x) << S_NXP)
35831 #define F_NXP V_NXP(1U)
35833 #define S_REM_FAULT 13
35834 #define V_REM_FAULT(x) ((x) << S_REM_FAULT)
35835 #define F_REM_FAULT V_REM_FAULT(1U)
35837 #define S_PAUSE_ABILITY 10
35838 #define M_PAUSE_ABILITY 0x7U
35839 #define V_PAUSE_ABILITY(x) ((x) << S_PAUSE_ABILITY)
35840 #define G_PAUSE_ABILITY(x) (((x) >> S_PAUSE_ABILITY) & M_PAUSE_ABILITY)
35842 #define S_ECHO_NONCE 5
35843 #define M_ECHO_NONCE 0x1fU
35844 #define V_ECHO_NONCE(x) ((x) << S_ECHO_NONCE)
35845 #define G_ECHO_NONCE(x) (((x) >> S_ECHO_NONCE) & M_ECHO_NONCE)
35847 #define S_SELECTOR 0
35848 #define M_SELECTOR 0x1fU
35849 #define V_SELECTOR(x) ((x) << S_SELECTOR)
35850 #define G_SELECTOR(x) (((x) >> S_SELECTOR) & M_SELECTOR)
35852 #define A_MAC_PORT_BEAN_ABILITY_1 0x220c
35854 #define S_TECH_ABILITY_1 5
35855 #define M_TECH_ABILITY_1 0x7ffU
35856 #define V_TECH_ABILITY_1(x) ((x) << S_TECH_ABILITY_1)
35857 #define G_TECH_ABILITY_1(x) (((x) >> S_TECH_ABILITY_1) & M_TECH_ABILITY_1)
35859 #define S_TX_NONCE 0
35860 #define M_TX_NONCE 0x1fU
35861 #define V_TX_NONCE(x) ((x) << S_TX_NONCE)
35862 #define G_TX_NONCE(x) (((x) >> S_TX_NONCE) & M_TX_NONCE)
35864 #define A_MAC_PORT_BEAN_ABILITY_2 0x2210
35866 #define S_T5_FEC_ABILITY 14
35867 #define M_T5_FEC_ABILITY 0x3U
35868 #define V_T5_FEC_ABILITY(x) ((x) << S_T5_FEC_ABILITY)
35869 #define G_T5_FEC_ABILITY(x) (((x) >> S_T5_FEC_ABILITY) & M_T5_FEC_ABILITY)
35871 #define S_TECH_ABILITY_2 0
35872 #define M_TECH_ABILITY_2 0x3fffU
35873 #define V_TECH_ABILITY_2(x) ((x) << S_TECH_ABILITY_2)
35874 #define G_TECH_ABILITY_2(x) (((x) >> S_TECH_ABILITY_2) & M_TECH_ABILITY_2)
35876 #define A_MAC_PORT_BEAN_REM_ABILITY_0 0x2214
35877 #define A_MAC_PORT_BEAN_REM_ABILITY_1 0x2218
35878 #define A_MAC_PORT_BEAN_REM_ABILITY_2 0x221c
35879 #define A_MAC_PORT_BEAN_MS_COUNT 0x2220
35881 #define S_MS_COUNT 0
35882 #define M_MS_COUNT 0xffffU
35883 #define V_MS_COUNT(x) ((x) << S_MS_COUNT)
35884 #define G_MS_COUNT(x) (((x) >> S_MS_COUNT) & M_MS_COUNT)
35886 #define A_MAC_PORT_BEAN_XNP_0 0x2224
35889 #define V_XNP(x) ((x) << S_XNP)
35890 #define F_XNP V_XNP(1U)
35892 #define S_ACKNOWLEDGE 14
35893 #define V_ACKNOWLEDGE(x) ((x) << S_ACKNOWLEDGE)
35894 #define F_ACKNOWLEDGE V_ACKNOWLEDGE(1U)
35897 #define V_MP(x) ((x) << S_MP)
35898 #define F_MP V_MP(1U)
35901 #define V_ACK2(x) ((x) << S_ACK2)
35902 #define F_ACK2 V_ACK2(1U)
35905 #define M_MU 0x7ffU
35906 #define V_MU(x) ((x) << S_MU)
35907 #define G_MU(x) (((x) >> S_MU) & M_MU)
35909 #define A_MAC_PORT_BEAN_XNP_1 0x2228
35911 #define S_UNFORMATED 0
35912 #define M_UNFORMATED 0xffffU
35913 #define V_UNFORMATED(x) ((x) << S_UNFORMATED)
35914 #define G_UNFORMATED(x) (((x) >> S_UNFORMATED) & M_UNFORMATED)
35916 #define A_MAC_PORT_BEAN_XNP_2 0x222c
35917 #define A_MAC_PORT_LP_BEAN_XNP_0 0x2230
35918 #define A_MAC_PORT_LP_BEAN_XNP_1 0x2234
35919 #define A_MAC_PORT_LP_BEAN_XNP_2 0x2238
35920 #define A_MAC_PORT_BEAN_ETH_STATUS 0x223c
35922 #define S_100GCR10 8
35923 #define V_100GCR10(x) ((x) << S_100GCR10)
35924 #define F_100GCR10 V_100GCR10(1U)
35927 #define V_40GCR4(x) ((x) << S_40GCR4)
35928 #define F_40GCR4 V_40GCR4(1U)
35931 #define V_40GKR4(x) ((x) << S_40GKR4)
35932 #define F_40GKR4 V_40GKR4(1U)
35935 #define V_FEC(x) ((x) << S_FEC)
35936 #define F_FEC V_FEC(1U)
35939 #define V_10GKR(x) ((x) << S_10GKR)
35940 #define F_10GKR V_10GKR(1U)
35943 #define V_10GKX4(x) ((x) << S_10GKX4)
35944 #define F_10GKX4 V_10GKX4(1U)
35947 #define V_1GKX(x) ((x) << S_1GKX)
35948 #define F_1GKX V_1GKX(1U)
35950 #define A_MAC_PORT_BEAN_CTL_LANE1 0x2240
35951 #define A_MAC_PORT_BEAN_STATUS_LANE1 0x2244
35952 #define A_MAC_PORT_BEAN_ABILITY_0_LANE1 0x2248
35953 #define A_MAC_PORT_BEAN_ABILITY_1_LANE1 0x224c
35954 #define A_MAC_PORT_BEAN_ABILITY_2_LANE1 0x2250
35955 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE1 0x2254
35956 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE1 0x2258
35957 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE1 0x225c
35958 #define A_MAC_PORT_BEAN_MS_COUNT_LANE1 0x2260
35959 #define A_MAC_PORT_BEAN_XNP_0_LANE1 0x2264
35960 #define A_MAC_PORT_BEAN_XNP_1_LANE1 0x2268
35961 #define A_MAC_PORT_BEAN_XNP_2_LANE1 0x226c
35962 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE1 0x2270
35963 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE1 0x2274
35964 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE1 0x2278
35965 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE1 0x227c
35966 #define A_MAC_PORT_BEAN_CTL_LANE2 0x2280
35967 #define A_MAC_PORT_BEAN_STATUS_LANE2 0x2284
35968 #define A_MAC_PORT_BEAN_ABILITY_0_LANE2 0x2288
35969 #define A_MAC_PORT_BEAN_ABILITY_1_LANE2 0x228c
35970 #define A_MAC_PORT_BEAN_ABILITY_2_LANE2 0x2290
35971 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE2 0x2294
35972 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE2 0x2298
35973 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE2 0x229c
35974 #define A_MAC_PORT_BEAN_MS_COUNT_LANE2 0x22a0
35975 #define A_MAC_PORT_BEAN_XNP_0_LANE2 0x22a4
35976 #define A_MAC_PORT_BEAN_XNP_1_LANE2 0x22a8
35977 #define A_MAC_PORT_BEAN_XNP_2_LANE2 0x22ac
35978 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE2 0x22b0
35979 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE2 0x22b4
35980 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE2 0x22b8
35981 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE2 0x22bc
35982 #define A_MAC_PORT_BEAN_CTL_LANE3 0x22c0
35983 #define A_MAC_PORT_BEAN_STATUS_LANE3 0x22c4
35984 #define A_MAC_PORT_BEAN_ABILITY_0_LANE3 0x22c8
35985 #define A_MAC_PORT_BEAN_ABILITY_1_LANE3 0x22cc
35986 #define A_MAC_PORT_BEAN_ABILITY_2_LANE3 0x22d0
35987 #define A_MAC_PORT_BEAN_REM_ABILITY_0_LANE3 0x22d4
35988 #define A_MAC_PORT_BEAN_REM_ABILITY_1_LANE3 0x22d8
35989 #define A_MAC_PORT_BEAN_REM_ABILITY_2_LANE3 0x22dc
35990 #define A_MAC_PORT_BEAN_MS_COUNT_LANE3 0x22e0
35991 #define A_MAC_PORT_BEAN_XNP_0_LANE3 0x22e4
35992 #define A_MAC_PORT_BEAN_XNP_1_LANE3 0x22e8
35993 #define A_MAC_PORT_BEAN_XNP_2_LANE3 0x22ec
35994 #define A_MAC_PORT_LP_BEAN_XNP_0_LANE3 0x22f0
35995 #define A_MAC_PORT_LP_BEAN_XNP_1_LANE3 0x22f4
35996 #define A_MAC_PORT_LP_BEAN_XNP_2_LANE3 0x22f8
35997 #define A_MAC_PORT_BEAN_ETH_STATUS_LANE3 0x22fc
35998 #define A_MAC_PORT_FEC_KR_CONTROL 0x2600
36000 #define S_ENABLE_TR 1
36001 #define V_ENABLE_TR(x) ((x) << S_ENABLE_TR)
36002 #define F_ENABLE_TR V_ENABLE_TR(1U)
36004 #define S_RESTART_TR 0
36005 #define V_RESTART_TR(x) ((x) << S_RESTART_TR)
36006 #define F_RESTART_TR V_RESTART_TR(1U)
36008 #define A_MAC_PORT_FEC_KR_STATUS 0x2604
36010 #define S_FECKRSIGDET 15
36011 #define V_FECKRSIGDET(x) ((x) << S_FECKRSIGDET)
36012 #define F_FECKRSIGDET V_FECKRSIGDET(1U)
36014 #define S_TRAIN_FAIL 3
36015 #define V_TRAIN_FAIL(x) ((x) << S_TRAIN_FAIL)
36016 #define F_TRAIN_FAIL V_TRAIN_FAIL(1U)
36018 #define S_STARTUP_STATUS 2
36019 #define V_STARTUP_STATUS(x) ((x) << S_STARTUP_STATUS)
36020 #define F_STARTUP_STATUS V_STARTUP_STATUS(1U)
36022 #define S_RX_STATUS 0
36023 #define V_RX_STATUS(x) ((x) << S_RX_STATUS)
36024 #define F_RX_STATUS V_RX_STATUS(1U)
36026 #define A_MAC_PORT_FEC_KR_LP_COEFF 0x2608
36028 #define S_PRESET 13
36029 #define V_PRESET(x) ((x) << S_PRESET)
36030 #define F_PRESET V_PRESET(1U)
36032 #define S_INITIALIZE 12
36033 #define V_INITIALIZE(x) ((x) << S_INITIALIZE)
36034 #define F_INITIALIZE V_INITIALIZE(1U)
36036 #define S_CP1_UPD 4
36037 #define M_CP1_UPD 0x3U
36038 #define V_CP1_UPD(x) ((x) << S_CP1_UPD)
36039 #define G_CP1_UPD(x) (((x) >> S_CP1_UPD) & M_CP1_UPD)
36042 #define M_C0_UPD 0x3U
36043 #define V_C0_UPD(x) ((x) << S_C0_UPD)
36044 #define G_C0_UPD(x) (((x) >> S_C0_UPD) & M_C0_UPD)
36046 #define S_CN1_UPD 0
36047 #define M_CN1_UPD 0x3U
36048 #define V_CN1_UPD(x) ((x) << S_CN1_UPD)
36049 #define G_CN1_UPD(x) (((x) >> S_CN1_UPD) & M_CN1_UPD)
36051 #define A_MAC_PORT_FEC_KR_LP_STAT 0x260c
36053 #define S_RX_READY 15
36054 #define V_RX_READY(x) ((x) << S_RX_READY)
36055 #define F_RX_READY V_RX_READY(1U)
36057 #define S_CP1_STAT 4
36058 #define M_CP1_STAT 0x3U
36059 #define V_CP1_STAT(x) ((x) << S_CP1_STAT)
36060 #define G_CP1_STAT(x) (((x) >> S_CP1_STAT) & M_CP1_STAT)
36062 #define S_C0_STAT 2
36063 #define M_C0_STAT 0x3U
36064 #define V_C0_STAT(x) ((x) << S_C0_STAT)
36065 #define G_C0_STAT(x) (((x) >> S_C0_STAT) & M_C0_STAT)
36067 #define S_CN1_STAT 0
36068 #define M_CN1_STAT 0x3U
36069 #define V_CN1_STAT(x) ((x) << S_CN1_STAT)
36070 #define G_CN1_STAT(x) (((x) >> S_CN1_STAT) & M_CN1_STAT)
36072 #define A_MAC_PORT_FEC_KR_LD_COEFF 0x2610
36073 #define A_MAC_PORT_FEC_KR_LD_STAT 0x2614
36074 #define A_MAC_PORT_FEC_ABILITY 0x2618
36076 #define S_FEC_IND_ABILITY 1
36077 #define V_FEC_IND_ABILITY(x) ((x) << S_FEC_IND_ABILITY)
36078 #define F_FEC_IND_ABILITY V_FEC_IND_ABILITY(1U)
36080 #define S_ABILITY 0
36081 #define V_ABILITY(x) ((x) << S_ABILITY)
36082 #define F_ABILITY V_ABILITY(1U)
36084 #define A_MAC_PORT_FEC_CONTROL 0x261c
36086 #define S_FEC_EN_ERR_IND 1
36087 #define V_FEC_EN_ERR_IND(x) ((x) << S_FEC_EN_ERR_IND)
36088 #define F_FEC_EN_ERR_IND V_FEC_EN_ERR_IND(1U)
36091 #define V_FEC_EN(x) ((x) << S_FEC_EN)
36092 #define F_FEC_EN V_FEC_EN(1U)
36094 #define A_MAC_PORT_FEC_STATUS 0x2620
36096 #define S_FEC_LOCKED_100 1
36097 #define V_FEC_LOCKED_100(x) ((x) << S_FEC_LOCKED_100)
36098 #define F_FEC_LOCKED_100 V_FEC_LOCKED_100(1U)
36100 #define S_FEC_LOCKED 0
36101 #define V_FEC_LOCKED(x) ((x) << S_FEC_LOCKED)
36102 #define F_FEC_LOCKED V_FEC_LOCKED(1U)
36104 #define A_MAC_PORT_FEC_CERR_CNT_0 0x2624
36106 #define S_FEC_CERR_CNT_0 0
36107 #define M_FEC_CERR_CNT_0 0xffffU
36108 #define V_FEC_CERR_CNT_0(x) ((x) << S_FEC_CERR_CNT_0)
36109 #define G_FEC_CERR_CNT_0(x) (((x) >> S_FEC_CERR_CNT_0) & M_FEC_CERR_CNT_0)
36111 #define A_MAC_PORT_FEC_CERR_CNT_1 0x2628
36113 #define S_FEC_CERR_CNT_1 0
36114 #define M_FEC_CERR_CNT_1 0xffffU
36115 #define V_FEC_CERR_CNT_1(x) ((x) << S_FEC_CERR_CNT_1)
36116 #define G_FEC_CERR_CNT_1(x) (((x) >> S_FEC_CERR_CNT_1) & M_FEC_CERR_CNT_1)
36118 #define A_MAC_PORT_FEC_NCERR_CNT_0 0x262c
36120 #define S_FEC_NCERR_CNT_0 0
36121 #define M_FEC_NCERR_CNT_0 0xffffU
36122 #define V_FEC_NCERR_CNT_0(x) ((x) << S_FEC_NCERR_CNT_0)
36123 #define G_FEC_NCERR_CNT_0(x) (((x) >> S_FEC_NCERR_CNT_0) & M_FEC_NCERR_CNT_0)
36125 #define A_MAC_PORT_FEC_NCERR_CNT_1 0x2630
36127 #define S_FEC_NCERR_CNT_1 0
36128 #define M_FEC_NCERR_CNT_1 0xffffU
36129 #define V_FEC_NCERR_CNT_1(x) ((x) << S_FEC_NCERR_CNT_1)
36130 #define G_FEC_NCERR_CNT_1(x) (((x) >> S_FEC_NCERR_CNT_1) & M_FEC_NCERR_CNT_1)
36132 #define A_MAC_PORT_AE_RX_COEF_REQ 0x2a00
36134 #define S_T5_RXREQ_C2 4
36135 #define M_T5_RXREQ_C2 0x3U
36136 #define V_T5_RXREQ_C2(x) ((x) << S_T5_RXREQ_C2)
36137 #define G_T5_RXREQ_C2(x) (((x) >> S_T5_RXREQ_C2) & M_T5_RXREQ_C2)
36139 #define S_T5_RXREQ_C1 2
36140 #define M_T5_RXREQ_C1 0x3U
36141 #define V_T5_RXREQ_C1(x) ((x) << S_T5_RXREQ_C1)
36142 #define G_T5_RXREQ_C1(x) (((x) >> S_T5_RXREQ_C1) & M_T5_RXREQ_C1)
36144 #define S_T5_RXREQ_C0 0
36145 #define M_T5_RXREQ_C0 0x3U
36146 #define V_T5_RXREQ_C0(x) ((x) << S_T5_RXREQ_C0)
36147 #define G_T5_RXREQ_C0(x) (((x) >> S_T5_RXREQ_C0) & M_T5_RXREQ_C0)
36149 #define A_MAC_PORT_AE_RX_COEF_STAT 0x2a04
36151 #define S_T5_AE0_RXSTAT_RDY 15
36152 #define V_T5_AE0_RXSTAT_RDY(x) ((x) << S_T5_AE0_RXSTAT_RDY)
36153 #define F_T5_AE0_RXSTAT_RDY V_T5_AE0_RXSTAT_RDY(1U)
36155 #define S_T5_AE0_RXSTAT_C2 4
36156 #define M_T5_AE0_RXSTAT_C2 0x3U
36157 #define V_T5_AE0_RXSTAT_C2(x) ((x) << S_T5_AE0_RXSTAT_C2)
36158 #define G_T5_AE0_RXSTAT_C2(x) (((x) >> S_T5_AE0_RXSTAT_C2) & M_T5_AE0_RXSTAT_C2)
36160 #define S_T5_AE0_RXSTAT_C1 2
36161 #define M_T5_AE0_RXSTAT_C1 0x3U
36162 #define V_T5_AE0_RXSTAT_C1(x) ((x) << S_T5_AE0_RXSTAT_C1)
36163 #define G_T5_AE0_RXSTAT_C1(x) (((x) >> S_T5_AE0_RXSTAT_C1) & M_T5_AE0_RXSTAT_C1)
36165 #define S_T5_AE0_RXSTAT_C0 0
36166 #define M_T5_AE0_RXSTAT_C0 0x3U
36167 #define V_T5_AE0_RXSTAT_C0(x) ((x) << S_T5_AE0_RXSTAT_C0)
36168 #define G_T5_AE0_RXSTAT_C0(x) (((x) >> S_T5_AE0_RXSTAT_C0) & M_T5_AE0_RXSTAT_C0)
36170 #define A_MAC_PORT_AE_TX_COEF_REQ 0x2a08
36172 #define S_T5_TXREQ_C2 4
36173 #define M_T5_TXREQ_C2 0x3U
36174 #define V_T5_TXREQ_C2(x) ((x) << S_T5_TXREQ_C2)
36175 #define G_T5_TXREQ_C2(x) (((x) >> S_T5_TXREQ_C2) & M_T5_TXREQ_C2)
36177 #define S_T5_TXREQ_C1 2
36178 #define M_T5_TXREQ_C1 0x3U
36179 #define V_T5_TXREQ_C1(x) ((x) << S_T5_TXREQ_C1)
36180 #define G_T5_TXREQ_C1(x) (((x) >> S_T5_TXREQ_C1) & M_T5_TXREQ_C1)
36182 #define S_T5_TXREQ_C0 0
36183 #define M_T5_TXREQ_C0 0x3U
36184 #define V_T5_TXREQ_C0(x) ((x) << S_T5_TXREQ_C0)
36185 #define G_T5_TXREQ_C0(x) (((x) >> S_T5_TXREQ_C0) & M_T5_TXREQ_C0)
36187 #define A_MAC_PORT_AE_TX_COEF_STAT 0x2a0c
36189 #define S_T5_TXSTAT_C2 4
36190 #define M_T5_TXSTAT_C2 0x3U
36191 #define V_T5_TXSTAT_C2(x) ((x) << S_T5_TXSTAT_C2)
36192 #define G_T5_TXSTAT_C2(x) (((x) >> S_T5_TXSTAT_C2) & M_T5_TXSTAT_C2)
36194 #define S_T5_TXSTAT_C1 2
36195 #define M_T5_TXSTAT_C1 0x3U
36196 #define V_T5_TXSTAT_C1(x) ((x) << S_T5_TXSTAT_C1)
36197 #define G_T5_TXSTAT_C1(x) (((x) >> S_T5_TXSTAT_C1) & M_T5_TXSTAT_C1)
36199 #define S_T5_TXSTAT_C0 0
36200 #define M_T5_TXSTAT_C0 0x3U
36201 #define V_T5_TXSTAT_C0(x) ((x) << S_T5_TXSTAT_C0)
36202 #define G_T5_TXSTAT_C0(x) (((x) >> S_T5_TXSTAT_C0) & M_T5_TXSTAT_C0)
36204 #define A_MAC_PORT_AE_REG_MODE 0x2a10
36206 #define S_AET_RSVD 7
36207 #define V_AET_RSVD(x) ((x) << S_AET_RSVD)
36208 #define F_AET_RSVD V_AET_RSVD(1U)
36210 #define S_AET_ENABLE 6
36211 #define V_AET_ENABLE(x) ((x) << S_AET_ENABLE)
36212 #define F_AET_ENABLE V_AET_ENABLE(1U)
36214 #define A_MAC_PORT_AE_PRBS_CTL 0x2a14
36215 #define A_MAC_PORT_AE_FSM_CTL 0x2a18
36217 #define S_CIN_ENABLE 15
36218 #define V_CIN_ENABLE(x) ((x) << S_CIN_ENABLE)
36219 #define F_CIN_ENABLE V_CIN_ENABLE(1U)
36221 #define A_MAC_PORT_AE_FSM_STATE 0x2a1c
36222 #define A_MAC_PORT_AE_RX_COEF_REQ_1 0x2a20
36223 #define A_MAC_PORT_AE_RX_COEF_STAT_1 0x2a24
36225 #define S_T5_AE1_RXSTAT_RDY 15
36226 #define V_T5_AE1_RXSTAT_RDY(x) ((x) << S_T5_AE1_RXSTAT_RDY)
36227 #define F_T5_AE1_RXSTAT_RDY V_T5_AE1_RXSTAT_RDY(1U)
36229 #define S_T5_AE1_RXSTAT_C2 4
36230 #define M_T5_AE1_RXSTAT_C2 0x3U
36231 #define V_T5_AE1_RXSTAT_C2(x) ((x) << S_T5_AE1_RXSTAT_C2)
36232 #define G_T5_AE1_RXSTAT_C2(x) (((x) >> S_T5_AE1_RXSTAT_C2) & M_T5_AE1_RXSTAT_C2)
36234 #define S_T5_AE1_RXSTAT_C1 2
36235 #define M_T5_AE1_RXSTAT_C1 0x3U
36236 #define V_T5_AE1_RXSTAT_C1(x) ((x) << S_T5_AE1_RXSTAT_C1)
36237 #define G_T5_AE1_RXSTAT_C1(x) (((x) >> S_T5_AE1_RXSTAT_C1) & M_T5_AE1_RXSTAT_C1)
36239 #define S_T5_AE1_RXSTAT_C0 0
36240 #define M_T5_AE1_RXSTAT_C0 0x3U
36241 #define V_T5_AE1_RXSTAT_C0(x) ((x) << S_T5_AE1_RXSTAT_C0)
36242 #define G_T5_AE1_RXSTAT_C0(x) (((x) >> S_T5_AE1_RXSTAT_C0) & M_T5_AE1_RXSTAT_C0)
36244 #define A_MAC_PORT_AE_TX_COEF_REQ_1 0x2a28
36245 #define A_MAC_PORT_AE_TX_COEF_STAT_1 0x2a2c
36246 #define A_MAC_PORT_AE_REG_MODE_1 0x2a30
36247 #define A_MAC_PORT_AE_PRBS_CTL_1 0x2a34
36248 #define A_MAC_PORT_AE_FSM_CTL_1 0x2a38
36249 #define A_MAC_PORT_AE_FSM_STATE_1 0x2a3c
36250 #define A_MAC_PORT_AE_RX_COEF_REQ_2 0x2a40
36251 #define A_MAC_PORT_AE_RX_COEF_STAT_2 0x2a44
36253 #define S_T5_AE2_RXSTAT_RDY 15
36254 #define V_T5_AE2_RXSTAT_RDY(x) ((x) << S_T5_AE2_RXSTAT_RDY)
36255 #define F_T5_AE2_RXSTAT_RDY V_T5_AE2_RXSTAT_RDY(1U)
36257 #define S_T5_AE2_RXSTAT_C2 4
36258 #define M_T5_AE2_RXSTAT_C2 0x3U
36259 #define V_T5_AE2_RXSTAT_C2(x) ((x) << S_T5_AE2_RXSTAT_C2)
36260 #define G_T5_AE2_RXSTAT_C2(x) (((x) >> S_T5_AE2_RXSTAT_C2) & M_T5_AE2_RXSTAT_C2)
36262 #define S_T5_AE2_RXSTAT_C1 2
36263 #define M_T5_AE2_RXSTAT_C1 0x3U
36264 #define V_T5_AE2_RXSTAT_C1(x) ((x) << S_T5_AE2_RXSTAT_C1)
36265 #define G_T5_AE2_RXSTAT_C1(x) (((x) >> S_T5_AE2_RXSTAT_C1) & M_T5_AE2_RXSTAT_C1)
36267 #define S_T5_AE2_RXSTAT_C0 0
36268 #define M_T5_AE2_RXSTAT_C0 0x3U
36269 #define V_T5_AE2_RXSTAT_C0(x) ((x) << S_T5_AE2_RXSTAT_C0)
36270 #define G_T5_AE2_RXSTAT_C0(x) (((x) >> S_T5_AE2_RXSTAT_C0) & M_T5_AE2_RXSTAT_C0)
36272 #define A_MAC_PORT_AE_TX_COEF_REQ_2 0x2a48
36273 #define A_MAC_PORT_AE_TX_COEF_STAT_2 0x2a4c
36274 #define A_MAC_PORT_AE_REG_MODE_2 0x2a50
36275 #define A_MAC_PORT_AE_PRBS_CTL_2 0x2a54
36276 #define A_MAC_PORT_AE_FSM_CTL_2 0x2a58
36277 #define A_MAC_PORT_AE_FSM_STATE_2 0x2a5c
36278 #define A_MAC_PORT_AE_RX_COEF_REQ_3 0x2a60
36279 #define A_MAC_PORT_AE_RX_COEF_STAT_3 0x2a64
36281 #define S_T5_AE3_RXSTAT_RDY 15
36282 #define V_T5_AE3_RXSTAT_RDY(x) ((x) << S_T5_AE3_RXSTAT_RDY)
36283 #define F_T5_AE3_RXSTAT_RDY V_T5_AE3_RXSTAT_RDY(1U)
36285 #define S_T5_AE3_RXSTAT_C2 4
36286 #define M_T5_AE3_RXSTAT_C2 0x3U
36287 #define V_T5_AE3_RXSTAT_C2(x) ((x) << S_T5_AE3_RXSTAT_C2)
36288 #define G_T5_AE3_RXSTAT_C2(x) (((x) >> S_T5_AE3_RXSTAT_C2) & M_T5_AE3_RXSTAT_C2)
36290 #define S_T5_AE3_RXSTAT_C1 2
36291 #define M_T5_AE3_RXSTAT_C1 0x3U
36292 #define V_T5_AE3_RXSTAT_C1(x) ((x) << S_T5_AE3_RXSTAT_C1)
36293 #define G_T5_AE3_RXSTAT_C1(x) (((x) >> S_T5_AE3_RXSTAT_C1) & M_T5_AE3_RXSTAT_C1)
36295 #define S_T5_AE3_RXSTAT_C0 0
36296 #define M_T5_AE3_RXSTAT_C0 0x3U
36297 #define V_T5_AE3_RXSTAT_C0(x) ((x) << S_T5_AE3_RXSTAT_C0)
36298 #define G_T5_AE3_RXSTAT_C0(x) (((x) >> S_T5_AE3_RXSTAT_C0) & M_T5_AE3_RXSTAT_C0)
36300 #define A_MAC_PORT_AE_TX_COEF_REQ_3 0x2a68
36301 #define A_MAC_PORT_AE_TX_COEF_STAT_3 0x2a6c
36302 #define A_MAC_PORT_AE_REG_MODE_3 0x2a70
36303 #define A_MAC_PORT_AE_PRBS_CTL_3 0x2a74
36304 #define A_MAC_PORT_AE_FSM_CTL_3 0x2a78
36305 #define A_MAC_PORT_AE_FSM_STATE_3 0x2a7c
36306 #define A_MAC_PORT_AE_TX_DIS 0x2a80
36307 #define A_MAC_PORT_AE_KR_CTRL 0x2a84
36308 #define A_MAC_PORT_AE_RX_SIGDET 0x2a88
36309 #define A_MAC_PORT_AE_KR_STATUS 0x2a8c
36310 #define A_MAC_PORT_AE_TX_DIS_1 0x2a90
36311 #define A_MAC_PORT_AE_KR_CTRL_1 0x2a94
36312 #define A_MAC_PORT_AE_RX_SIGDET_1 0x2a98
36313 #define A_MAC_PORT_AE_KR_STATUS_1 0x2a9c
36314 #define A_MAC_PORT_AE_TX_DIS_2 0x2aa0
36315 #define A_MAC_PORT_AE_KR_CTRL_2 0x2aa4
36316 #define A_MAC_PORT_AE_RX_SIGDET_2 0x2aa8
36317 #define A_MAC_PORT_AE_KR_STATUS_2 0x2aac
36318 #define A_MAC_PORT_AE_TX_DIS_3 0x2ab0
36319 #define A_MAC_PORT_AE_KR_CTRL_3 0x2ab4
36320 #define A_MAC_PORT_AE_RX_SIGDET_3 0x2ab8
36321 #define A_MAC_PORT_AE_KR_STATUS_3 0x2abc
36322 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_0 0x2b00
36324 #define S_EN_HOLD_FAIL 14
36325 #define V_EN_HOLD_FAIL(x) ((x) << S_EN_HOLD_FAIL)
36326 #define F_EN_HOLD_FAIL V_EN_HOLD_FAIL(1U)
36328 #define S_INIT_METH 12
36329 #define M_INIT_METH 0x3U
36330 #define V_INIT_METH(x) ((x) << S_INIT_METH)
36331 #define G_INIT_METH(x) (((x) >> S_INIT_METH) & M_INIT_METH)
36333 #define S_CE_DECS 8
36334 #define M_CE_DECS 0xfU
36335 #define V_CE_DECS(x) ((x) << S_CE_DECS)
36336 #define G_CE_DECS(x) (((x) >> S_CE_DECS) & M_CE_DECS)
36339 #define V_EN_ZFE(x) ((x) << S_EN_ZFE)
36340 #define F_EN_ZFE V_EN_ZFE(1U)
36342 #define S_EN_GAIN_TOG 6
36343 #define V_EN_GAIN_TOG(x) ((x) << S_EN_GAIN_TOG)
36344 #define F_EN_GAIN_TOG V_EN_GAIN_TOG(1U)
36346 #define S_EN_AI_C1 5
36347 #define V_EN_AI_C1(x) ((x) << S_EN_AI_C1)
36348 #define F_EN_AI_C1 V_EN_AI_C1(1U)
36350 #define S_EN_MAX_ST 4
36351 #define V_EN_MAX_ST(x) ((x) << S_EN_MAX_ST)
36352 #define F_EN_MAX_ST V_EN_MAX_ST(1U)
36354 #define S_EN_H1T_EQ 3
36355 #define V_EN_H1T_EQ(x) ((x) << S_EN_H1T_EQ)
36356 #define F_EN_H1T_EQ V_EN_H1T_EQ(1U)
36358 #define S_H1TEQ_GOAL 0
36359 #define M_H1TEQ_GOAL 0x7U
36360 #define V_H1TEQ_GOAL(x) ((x) << S_H1TEQ_GOAL)
36361 #define G_H1TEQ_GOAL(x) (((x) >> S_H1TEQ_GOAL) & M_H1TEQ_GOAL)
36363 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_0 0x2b04
36365 #define S_GAIN_TH 6
36366 #define M_GAIN_TH 0x1fU
36367 #define V_GAIN_TH(x) ((x) << S_GAIN_TH)
36368 #define G_GAIN_TH(x) (((x) >> S_GAIN_TH) & M_GAIN_TH)
36370 #define S_EN_SD_TH 5
36371 #define V_EN_SD_TH(x) ((x) << S_EN_SD_TH)
36372 #define F_EN_SD_TH V_EN_SD_TH(1U)
36374 #define S_EN_AMIN_TH 4
36375 #define V_EN_AMIN_TH(x) ((x) << S_EN_AMIN_TH)
36376 #define F_EN_AMIN_TH V_EN_AMIN_TH(1U)
36378 #define S_AMIN_TH 0
36379 #define M_AMIN_TH 0xfU
36380 #define V_AMIN_TH(x) ((x) << S_AMIN_TH)
36381 #define G_AMIN_TH(x) (((x) >> S_AMIN_TH) & M_AMIN_TH)
36383 #define A_MAC_PORT_AET_ZFE_LIMITS_0 0x2b08
36385 #define S_ACC_LIM 8
36386 #define M_ACC_LIM 0xfU
36387 #define V_ACC_LIM(x) ((x) << S_ACC_LIM)
36388 #define G_ACC_LIM(x) (((x) >> S_ACC_LIM) & M_ACC_LIM)
36390 #define S_CNV_LIM 4
36391 #define M_CNV_LIM 0xfU
36392 #define V_CNV_LIM(x) ((x) << S_CNV_LIM)
36393 #define G_CNV_LIM(x) (((x) >> S_CNV_LIM) & M_CNV_LIM)
36395 #define S_TOG_LIM 0
36396 #define M_TOG_LIM 0xfU
36397 #define V_TOG_LIM(x) ((x) << S_TOG_LIM)
36398 #define G_TOG_LIM(x) (((x) >> S_TOG_LIM) & M_TOG_LIM)
36400 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_0 0x2b0c
36402 #define S_BOOT_LUT7 12
36403 #define M_BOOT_LUT7 0xfU
36404 #define V_BOOT_LUT7(x) ((x) << S_BOOT_LUT7)
36405 #define G_BOOT_LUT7(x) (((x) >> S_BOOT_LUT7) & M_BOOT_LUT7)
36407 #define S_BOOT_LUT6 8
36408 #define M_BOOT_LUT6 0xfU
36409 #define V_BOOT_LUT6(x) ((x) << S_BOOT_LUT6)
36410 #define G_BOOT_LUT6(x) (((x) >> S_BOOT_LUT6) & M_BOOT_LUT6)
36412 #define S_BOOT_LUT45 4
36413 #define M_BOOT_LUT45 0xfU
36414 #define V_BOOT_LUT45(x) ((x) << S_BOOT_LUT45)
36415 #define G_BOOT_LUT45(x) (((x) >> S_BOOT_LUT45) & M_BOOT_LUT45)
36417 #define S_BOOT_LUT0123 2
36418 #define M_BOOT_LUT0123 0x3U
36419 #define V_BOOT_LUT0123(x) ((x) << S_BOOT_LUT0123)
36420 #define G_BOOT_LUT0123(x) (((x) >> S_BOOT_LUT0123) & M_BOOT_LUT0123)
36422 #define S_BOOT_DEC_C0 1
36423 #define V_BOOT_DEC_C0(x) ((x) << S_BOOT_DEC_C0)
36424 #define F_BOOT_DEC_C0 V_BOOT_DEC_C0(1U)
36426 #define A_MAC_PORT_AET_STATUS_0 0x2b10
36428 #define S_AET_STAT 9
36429 #define M_AET_STAT 0xfU
36430 #define V_AET_STAT(x) ((x) << S_AET_STAT)
36431 #define G_AET_STAT(x) (((x) >> S_AET_STAT) & M_AET_STAT)
36433 #define S_NEU_STATE 5
36434 #define M_NEU_STATE 0xfU
36435 #define V_NEU_STATE(x) ((x) << S_NEU_STATE)
36436 #define G_NEU_STATE(x) (((x) >> S_NEU_STATE) & M_NEU_STATE)
36438 #define S_CTRL_STATE 0
36439 #define M_CTRL_STATE 0x1fU
36440 #define V_CTRL_STATE(x) ((x) << S_CTRL_STATE)
36441 #define G_CTRL_STATE(x) (((x) >> S_CTRL_STATE) & M_CTRL_STATE)
36443 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_1 0x2b20
36444 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_1 0x2b24
36445 #define A_MAC_PORT_AET_ZFE_LIMITS_1 0x2b28
36446 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_1 0x2b2c
36447 #define A_MAC_PORT_AET_STATUS_1 0x2b30
36448 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_2 0x2b40
36449 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_2 0x2b44
36450 #define A_MAC_PORT_AET_ZFE_LIMITS_2 0x2b48
36451 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_2 0x2b4c
36452 #define A_MAC_PORT_AET_STATUS_2 0x2b50
36453 #define A_MAC_PORT_AET_STAGE_CONFIGURATION_3 0x2b60
36454 #define A_MAC_PORT_AET_SIGNAL_LOSS_DETECTION_3 0x2b64
36455 #define A_MAC_PORT_AET_ZFE_LIMITS_3 0x2b68
36456 #define A_MAC_PORT_AET_BOOTSTRAP_LOOKUP_TABLE_3 0x2b6c
36457 #define A_MAC_PORT_AET_STATUS_3 0x2b70
36458 #define A_MAC_PORT_TX_LINKA_TRANSMIT_CONFIGURATION_MODE 0x3000
36460 #define S_T5_TX_LINKEN 15
36461 #define V_T5_TX_LINKEN(x) ((x) << S_T5_TX_LINKEN)
36462 #define F_T5_TX_LINKEN V_T5_TX_LINKEN(1U)
36464 #define S_T5_TX_LINKRST 14
36465 #define V_T5_TX_LINKRST(x) ((x) << S_T5_TX_LINKRST)
36466 #define F_T5_TX_LINKRST V_T5_TX_LINKRST(1U)
36468 #define S_T5_TX_CFGWRT 13
36469 #define V_T5_TX_CFGWRT(x) ((x) << S_T5_TX_CFGWRT)
36470 #define F_T5_TX_CFGWRT V_T5_TX_CFGWRT(1U)
36472 #define S_T5_TX_CFGPTR 11
36473 #define M_T5_TX_CFGPTR 0x3U
36474 #define V_T5_TX_CFGPTR(x) ((x) << S_T5_TX_CFGPTR)
36475 #define G_T5_TX_CFGPTR(x) (((x) >> S_T5_TX_CFGPTR) & M_T5_TX_CFGPTR)
36477 #define S_T5_TX_CFGEXT 10
36478 #define V_T5_TX_CFGEXT(x) ((x) << S_T5_TX_CFGEXT)
36479 #define F_T5_TX_CFGEXT V_T5_TX_CFGEXT(1U)
36481 #define S_T5_TX_CFGACT 9
36482 #define V_T5_TX_CFGACT(x) ((x) << S_T5_TX_CFGACT)
36483 #define F_T5_TX_CFGACT V_T5_TX_CFGACT(1U)
36485 #define S_T5_TX_RSYNCC 8
36486 #define V_T5_TX_RSYNCC(x) ((x) << S_T5_TX_RSYNCC)
36487 #define F_T5_TX_RSYNCC V_T5_TX_RSYNCC(1U)
36489 #define S_T5_TX_PLLSEL 6
36490 #define M_T5_TX_PLLSEL 0x3U
36491 #define V_T5_TX_PLLSEL(x) ((x) << S_T5_TX_PLLSEL)
36492 #define G_T5_TX_PLLSEL(x) (((x) >> S_T5_TX_PLLSEL) & M_T5_TX_PLLSEL)
36494 #define S_T5_TX_EXTC16 5
36495 #define V_T5_TX_EXTC16(x) ((x) << S_T5_TX_EXTC16)
36496 #define F_T5_TX_EXTC16 V_T5_TX_EXTC16(1U)
36498 #define S_T5_TX_DCKSEL 4
36499 #define V_T5_TX_DCKSEL(x) ((x) << S_T5_TX_DCKSEL)
36500 #define F_T5_TX_DCKSEL V_T5_TX_DCKSEL(1U)
36502 #define S_T5_TX_RXLOOP 3
36503 #define V_T5_TX_RXLOOP(x) ((x) << S_T5_TX_RXLOOP)
36504 #define F_T5_TX_RXLOOP V_T5_TX_RXLOOP(1U)
36506 #define S_T5_TX_BWSEL 2
36507 #define V_T5_TX_BWSEL(x) ((x) << S_T5_TX_BWSEL)
36508 #define F_T5_TX_BWSEL V_T5_TX_BWSEL(1U)
36510 #define S_T5_TX_RTSEL 0
36511 #define M_T5_TX_RTSEL 0x3U
36512 #define V_T5_TX_RTSEL(x) ((x) << S_T5_TX_RTSEL)
36513 #define G_T5_TX_RTSEL(x) (((x) >> S_T5_TX_RTSEL) & M_T5_TX_RTSEL)
36515 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TEST_CONTROL 0x3004
36518 #define M_SPSEL 0x7U
36519 #define V_SPSEL(x) ((x) << S_SPSEL)
36520 #define G_SPSEL(x) (((x) >> S_SPSEL) & M_SPSEL)
36523 #define V_AFDWEN(x) ((x) << S_AFDWEN)
36524 #define F_AFDWEN V_AFDWEN(1U)
36527 #define V_TPGMD(x) ((x) << S_TPGMD)
36528 #define F_TPGMD V_TPGMD(1U)
36530 #define A_MAC_PORT_TX_LINKA_TRANSMIT_COEFFICIENT_CONTROL 0x3008
36532 #define S_ZCALOVRD 8
36533 #define V_ZCALOVRD(x) ((x) << S_ZCALOVRD)
36534 #define F_ZCALOVRD V_ZCALOVRD(1U)
36537 #define V_AMMODE(x) ((x) << S_AMMODE)
36538 #define F_AMMODE V_AMMODE(1U)
36541 #define V_AEPOL(x) ((x) << S_AEPOL)
36542 #define F_AEPOL V_AEPOL(1U)
36545 #define V_AESRC(x) ((x) << S_AESRC)
36546 #define F_AESRC V_AESRC(1U)
36548 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_MODE_CONTROL 0x300c
36550 #define S_T5DRVHIZ 5
36551 #define V_T5DRVHIZ(x) ((x) << S_T5DRVHIZ)
36552 #define F_T5DRVHIZ V_T5DRVHIZ(1U)
36554 #define S_T5SASIMP 4
36555 #define V_T5SASIMP(x) ((x) << S_T5SASIMP)
36556 #define F_T5SASIMP V_T5SASIMP(1U)
36559 #define M_T5SLEW 0x3U
36560 #define V_T5SLEW(x) ((x) << S_T5SLEW)
36561 #define G_T5SLEW(x) (((x) >> S_T5SLEW) & M_T5SLEW)
36563 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3010
36565 #define S_T5C2BUFDCEN 5
36566 #define V_T5C2BUFDCEN(x) ((x) << S_T5C2BUFDCEN)
36567 #define F_T5C2BUFDCEN V_T5C2BUFDCEN(1U)
36569 #define S_T5DCCEN 4
36570 #define V_T5DCCEN(x) ((x) << S_T5DCCEN)
36571 #define F_T5DCCEN V_T5DCCEN(1U)
36573 #define S_T5REGBYP 3
36574 #define V_T5REGBYP(x) ((x) << S_T5REGBYP)
36575 #define F_T5REGBYP V_T5REGBYP(1U)
36577 #define S_T5REGAEN 2
36578 #define V_T5REGAEN(x) ((x) << S_T5REGAEN)
36579 #define F_T5REGAEN V_T5REGAEN(1U)
36581 #define S_T5REGAMP 0
36582 #define M_T5REGAMP 0x3U
36583 #define V_T5REGAMP(x) ((x) << S_T5REGAMP)
36584 #define G_T5REGAMP(x) (((x) >> S_T5REGAMP) & M_T5REGAMP)
36586 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3014
36589 #define V_RSTEP(x) ((x) << S_RSTEP)
36590 #define F_RSTEP V_RSTEP(1U)
36593 #define V_RLOCK(x) ((x) << S_RLOCK)
36594 #define F_RLOCK V_RLOCK(1U)
36597 #define M_RPOS 0x3fU
36598 #define V_RPOS(x) ((x) << S_RPOS)
36599 #define G_RPOS(x) (((x) >> S_RPOS) & M_RPOS)
36601 #define S_DCLKSAM 7
36602 #define V_DCLKSAM(x) ((x) << S_DCLKSAM)
36603 #define F_DCLKSAM V_DCLKSAM(1U)
36605 #define A_MAC_PORT_TX_LINKA_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3018
36607 #define S_CALSSTN 3
36608 #define M_CALSSTN 0x7U
36609 #define V_CALSSTN(x) ((x) << S_CALSSTN)
36610 #define G_CALSSTN(x) (((x) >> S_CALSSTN) & M_CALSSTN)
36612 #define S_CALSSTP 0
36613 #define M_CALSSTP 0x7U
36614 #define V_CALSSTP(x) ((x) << S_CALSSTP)
36615 #define G_CALSSTP(x) (((x) >> S_CALSSTP) & M_CALSSTP)
36617 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x301c
36620 #define M_DRTOL 0x1fU
36621 #define V_DRTOL(x) ((x) << S_DRTOL)
36622 #define G_DRTOL(x) (((x) >> S_DRTOL) & M_DRTOL)
36624 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT 0x3020
36626 #define S_T5NXTT0 0
36627 #define M_T5NXTT0 0x1fU
36628 #define V_T5NXTT0(x) ((x) << S_T5NXTT0)
36629 #define G_T5NXTT0(x) (((x) >> S_T5NXTT0) & M_T5NXTT0)
36631 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT 0x3024
36633 #define S_T5NXTT1 0
36634 #define M_T5NXTT1 0x3fU
36635 #define V_T5NXTT1(x) ((x) << S_T5NXTT1)
36636 #define G_T5NXTT1(x) (((x) >> S_T5NXTT1) & M_T5NXTT1)
36638 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT 0x3028
36640 #define S_T5NXTT2 0
36641 #define M_T5NXTT2 0x3fU
36642 #define V_T5NXTT2(x) ((x) << S_T5NXTT2)
36643 #define G_T5NXTT2(x) (((x) >> S_T5NXTT2) & M_T5NXTT2)
36645 #define A_MAC_PORT_TX_LINKA_TRANSMIT_AMPLITUDE 0x3030
36647 #define S_T5TXPWR 0
36648 #define M_T5TXPWR 0x3fU
36649 #define V_T5TXPWR(x) ((x) << S_T5TXPWR)
36650 #define G_T5TXPWR(x) (((x) >> S_T5TXPWR) & M_T5TXPWR)
36652 #define A_MAC_PORT_TX_LINKA_TRANSMIT_POLARITY 0x3034
36655 #define M_NXTPOL 0x7U
36656 #define V_NXTPOL(x) ((x) << S_NXTPOL)
36657 #define G_NXTPOL(x) (((x) >> S_NXTPOL) & M_NXTPOL)
36659 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3038
36661 #define S_CPREST 13
36662 #define V_CPREST(x) ((x) << S_CPREST)
36663 #define F_CPREST V_CPREST(1U)
36666 #define V_CINIT(x) ((x) << S_CINIT)
36667 #define F_CINIT V_CINIT(1U)
36669 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x303c
36670 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3040
36671 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3044
36673 #define S_T5NIDAC1 0
36674 #define M_T5NIDAC1 0x3fU
36675 #define V_T5NIDAC1(x) ((x) << S_T5NIDAC1)
36676 #define G_T5NIDAC1(x) (((x) >> S_T5NIDAC1) & M_T5NIDAC1)
36678 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3048
36680 #define S_T5NIDAC2 0
36681 #define M_T5NIDAC2 0x3fU
36682 #define V_T5NIDAC2(x) ((x) << S_T5NIDAC2)
36683 #define G_T5NIDAC2(x) (((x) >> S_T5NIDAC2) & M_T5NIDAC2)
36685 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3060
36686 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3064
36688 #define S_T5AIDAC1 0
36689 #define M_T5AIDAC1 0x3fU
36690 #define V_T5AIDAC1(x) ((x) << S_T5AIDAC1)
36691 #define G_T5AIDAC1(x) (((x) >> S_T5AIDAC1) & M_T5AIDAC1)
36693 #define A_MAC_PORT_TX_LINKA_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3068
36694 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3070
36697 #define M_MAINSC 0x3fU
36698 #define V_MAINSC(x) ((x) << S_MAINSC)
36699 #define G_MAINSC(x) (((x) >> S_MAINSC) & M_MAINSC)
36702 #define M_POSTSC 0x3fU
36703 #define V_POSTSC(x) ((x) << S_POSTSC)
36704 #define G_POSTSC(x) (((x) >> S_POSTSC) & M_POSTSC)
36706 #define A_MAC_PORT_TX_LINKA_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3074
36709 #define M_PRESC 0x1fU
36710 #define V_PRESC(x) ((x) << S_PRESC)
36711 #define G_PRESC(x) (((x) >> S_PRESC) & M_PRESC)
36713 #define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3078
36714 #define A_MAC_PORT_TX_LINKA_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x307c
36716 #define S_T5XADDR 1
36717 #define M_T5XADDR 0x1fU
36718 #define V_T5XADDR(x) ((x) << S_T5XADDR)
36719 #define G_T5XADDR(x) (((x) >> S_T5XADDR) & M_T5XADDR)
36722 #define V_T5XWR(x) ((x) << S_T5XWR)
36723 #define F_T5XWR V_T5XWR(1U)
36725 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3080
36728 #define M_XDAT10 0xffffU
36729 #define V_XDAT10(x) ((x) << S_XDAT10)
36730 #define G_XDAT10(x) (((x) >> S_XDAT10) & M_XDAT10)
36732 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3084
36735 #define M_XDAT32 0xffffU
36736 #define V_XDAT32(x) ((x) << S_XDAT32)
36737 #define G_XDAT32(x) (((x) >> S_XDAT32) & M_XDAT32)
36739 #define A_MAC_PORT_TX_LINKA_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3088
36742 #define M_XDAT4 0xffU
36743 #define V_XDAT4(x) ((x) << S_XDAT4)
36744 #define G_XDAT4(x) (((x) >> S_XDAT4) & M_XDAT4)
36746 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_CONTROL 0x308c
36748 #define S_DCCTIMEDOUT 15
36749 #define V_DCCTIMEDOUT(x) ((x) << S_DCCTIMEDOUT)
36750 #define F_DCCTIMEDOUT V_DCCTIMEDOUT(1U)
36752 #define S_DCCTIMEEN 14
36753 #define V_DCCTIMEEN(x) ((x) << S_DCCTIMEEN)
36754 #define F_DCCTIMEEN V_DCCTIMEEN(1U)
36756 #define S_DCCLOCK 13
36757 #define V_DCCLOCK(x) ((x) << S_DCCLOCK)
36758 #define F_DCCLOCK V_DCCLOCK(1U)
36760 #define S_DCCOFFSET 8
36761 #define M_DCCOFFSET 0x1fU
36762 #define V_DCCOFFSET(x) ((x) << S_DCCOFFSET)
36763 #define G_DCCOFFSET(x) (((x) >> S_DCCOFFSET) & M_DCCOFFSET)
36765 #define S_DCCSTEP 6
36766 #define M_DCCSTEP 0x3U
36767 #define V_DCCSTEP(x) ((x) << S_DCCSTEP)
36768 #define G_DCCSTEP(x) (((x) >> S_DCCSTEP) & M_DCCSTEP)
36770 #define S_DCCASTEP 1
36771 #define M_DCCASTEP 0x1fU
36772 #define V_DCCASTEP(x) ((x) << S_DCCASTEP)
36773 #define G_DCCASTEP(x) (((x) >> S_DCCASTEP) & M_DCCASTEP)
36776 #define V_DCCAEN(x) ((x) << S_DCCAEN)
36777 #define F_DCCAEN V_DCCAEN(1U)
36779 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_OVERRIDE 0x3090
36781 #define S_DCCOUT 12
36782 #define V_DCCOUT(x) ((x) << S_DCCOUT)
36783 #define F_DCCOUT V_DCCOUT(1U)
36785 #define S_DCCCLK 11
36786 #define V_DCCCLK(x) ((x) << S_DCCCLK)
36787 #define F_DCCCLK V_DCCCLK(1U)
36789 #define S_DCCHOLD 10
36790 #define V_DCCHOLD(x) ((x) << S_DCCHOLD)
36791 #define F_DCCHOLD V_DCCHOLD(1U)
36793 #define S_DCCSIGN 8
36794 #define M_DCCSIGN 0x3U
36795 #define V_DCCSIGN(x) ((x) << S_DCCSIGN)
36796 #define G_DCCSIGN(x) (((x) >> S_DCCSIGN) & M_DCCSIGN)
36799 #define M_DCCAMP 0x7fU
36800 #define V_DCCAMP(x) ((x) << S_DCCAMP)
36801 #define G_DCCAMP(x) (((x) >> S_DCCAMP) & M_DCCAMP)
36804 #define V_DCCOEN(x) ((x) << S_DCCOEN)
36805 #define F_DCCOEN V_DCCOEN(1U)
36807 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_APPLIED 0x3094
36809 #define S_DCCASIGN 7
36810 #define M_DCCASIGN 0x3U
36811 #define V_DCCASIGN(x) ((x) << S_DCCASIGN)
36812 #define G_DCCASIGN(x) (((x) >> S_DCCASIGN) & M_DCCASIGN)
36814 #define S_DCCAAMP 0
36815 #define M_DCCAAMP 0x7fU
36816 #define V_DCCAAMP(x) ((x) << S_DCCAAMP)
36817 #define G_DCCAAMP(x) (((x) >> S_DCCAAMP) & M_DCCAAMP)
36819 #define A_MAC_PORT_TX_LINKA_TRANSMIT_DCC_TIME_OUT 0x3098
36821 #define S_DCCTIMEOUTVAL 0
36822 #define M_DCCTIMEOUTVAL 0xffffU
36823 #define V_DCCTIMEOUTVAL(x) ((x) << S_DCCTIMEOUTVAL)
36824 #define G_DCCTIMEOUTVAL(x) (((x) >> S_DCCTIMEOUTVAL) & M_DCCTIMEOUTVAL)
36826 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AZ_CONTROL 0x309c
36828 #define S_LPIDCLK 4
36829 #define V_LPIDCLK(x) ((x) << S_LPIDCLK)
36830 #define F_LPIDCLK V_LPIDCLK(1U)
36832 #define S_LPITERM 2
36833 #define M_LPITERM 0x3U
36834 #define V_LPITERM(x) ((x) << S_LPITERM)
36835 #define G_LPITERM(x) (((x) >> S_LPITERM) & M_LPITERM)
36837 #define S_LPIPRCD 0
36838 #define M_LPIPRCD 0x3U
36839 #define V_LPIPRCD(x) ((x) << S_LPIPRCD)
36840 #define G_LPIPRCD(x) (((x) >> S_LPIPRCD) & M_LPIPRCD)
36842 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_4 0x30f0
36844 #define S_SDOVRDEN 8
36845 #define V_SDOVRDEN(x) ((x) << S_SDOVRDEN)
36846 #define F_SDOVRDEN V_SDOVRDEN(1U)
36849 #define M_SDOVRD 0xffU
36850 #define V_SDOVRD(x) ((x) << S_SDOVRD)
36851 #define G_SDOVRD(x) (((x) >> S_SDOVRD) & M_SDOVRD)
36853 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_3 0x30f4
36855 #define S_SLEWCODE 1
36856 #define M_SLEWCODE 0x3U
36857 #define V_SLEWCODE(x) ((x) << S_SLEWCODE)
36858 #define G_SLEWCODE(x) (((x) >> S_SLEWCODE) & M_SLEWCODE)
36861 #define V_ASEGEN(x) ((x) << S_ASEGEN)
36862 #define F_ASEGEN V_ASEGEN(1U)
36864 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_2 0x30f8
36866 #define S_AECMDVAL 14
36867 #define V_AECMDVAL(x) ((x) << S_AECMDVAL)
36868 #define F_AECMDVAL V_AECMDVAL(1U)
36870 #define S_AECMD1312 12
36871 #define M_AECMD1312 0x3U
36872 #define V_AECMD1312(x) ((x) << S_AECMD1312)
36873 #define G_AECMD1312(x) (((x) >> S_AECMD1312) & M_AECMD1312)
36875 #define S_AECMD70 0
36876 #define M_AECMD70 0xffU
36877 #define V_AECMD70(x) ((x) << S_AECMD70)
36878 #define G_AECMD70(x) (((x) >> S_AECMD70) & M_AECMD70)
36880 #define A_MAC_PORT_TX_LINKA_TRANSMIT_MACRO_TEST_CONTROL_1 0x30fc
36882 #define S_C48DIVCTL 12
36883 #define M_C48DIVCTL 0x7U
36884 #define V_C48DIVCTL(x) ((x) << S_C48DIVCTL)
36885 #define G_C48DIVCTL(x) (((x) >> S_C48DIVCTL) & M_C48DIVCTL)
36887 #define S_RATEDIVCTL 9
36888 #define M_RATEDIVCTL 0x7U
36889 #define V_RATEDIVCTL(x) ((x) << S_RATEDIVCTL)
36890 #define G_RATEDIVCTL(x) (((x) >> S_RATEDIVCTL) & M_RATEDIVCTL)
36892 #define S_ANLGFLSH 8
36893 #define V_ANLGFLSH(x) ((x) << S_ANLGFLSH)
36894 #define F_ANLGFLSH V_ANLGFLSH(1U)
36896 #define S_DCCTSTOUT 7
36897 #define V_DCCTSTOUT(x) ((x) << S_DCCTSTOUT)
36898 #define F_DCCTSTOUT V_DCCTSTOUT(1U)
36901 #define V_BSOUT(x) ((x) << S_BSOUT)
36902 #define F_BSOUT V_BSOUT(1U)
36905 #define V_BSIN(x) ((x) << S_BSIN)
36906 #define F_BSIN V_BSIN(1U)
36908 #define S_JTAGAMPL 3
36909 #define M_JTAGAMPL 0x3U
36910 #define V_JTAGAMPL(x) ((x) << S_JTAGAMPL)
36911 #define G_JTAGAMPL(x) (((x) >> S_JTAGAMPL) & M_JTAGAMPL)
36914 #define V_JTAGTS(x) ((x) << S_JTAGTS)
36915 #define F_JTAGTS V_JTAGTS(1U)
36918 #define V_TS(x) ((x) << S_TS)
36919 #define F_TS V_TS(1U)
36922 #define V_OBS(x) ((x) << S_OBS)
36923 #define F_OBS V_OBS(1U)
36925 #define A_MAC_PORT_TX_LINKB_TRANSMIT_CONFIGURATION_MODE 0x3100
36926 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TEST_CONTROL 0x3104
36927 #define A_MAC_PORT_TX_LINKB_TRANSMIT_COEFFICIENT_CONTROL 0x3108
36928 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_MODE_CONTROL 0x310c
36929 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3110
36930 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3114
36931 #define A_MAC_PORT_TX_LINKB_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3118
36932 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x311c
36933 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT 0x3120
36934 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT 0x3124
36935 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT 0x3128
36936 #define A_MAC_PORT_TX_LINKB_TRANSMIT_AMPLITUDE 0x3130
36937 #define A_MAC_PORT_TX_LINKB_TRANSMIT_POLARITY 0x3134
36938 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3138
36939 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x313c
36940 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3140
36941 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3144
36942 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3148
36943 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3160
36944 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3164
36945 #define A_MAC_PORT_TX_LINKB_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3168
36946 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3170
36947 #define A_MAC_PORT_TX_LINKB_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3174
36948 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3178
36949 #define A_MAC_PORT_TX_LINKB_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x317c
36950 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3180
36951 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3184
36952 #define A_MAC_PORT_TX_LINKB_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3188
36953 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_CONTROL 0x318c
36954 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_OVERRIDE 0x3190
36955 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_APPLIED 0x3194
36956 #define A_MAC_PORT_TX_LINKB_TRANSMIT_DCC_TIME_OUT 0x3198
36957 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AZ_CONTROL 0x319c
36958 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_4 0x31f0
36959 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_3 0x31f4
36960 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_2 0x31f8
36961 #define A_MAC_PORT_TX_LINKB_TRANSMIT_MACRO_TEST_CONTROL_1 0x31fc
36962 #define A_MAC_PORT_RX_LINKA_RECEIVER_CONFIGURATION_MODE 0x3200
36964 #define S_T5_RX_LINKEN 15
36965 #define V_T5_RX_LINKEN(x) ((x) << S_T5_RX_LINKEN)
36966 #define F_T5_RX_LINKEN V_T5_RX_LINKEN(1U)
36968 #define S_T5_RX_LINKRST 14
36969 #define V_T5_RX_LINKRST(x) ((x) << S_T5_RX_LINKRST)
36970 #define F_T5_RX_LINKRST V_T5_RX_LINKRST(1U)
36972 #define S_T5_RX_CFGWRT 13
36973 #define V_T5_RX_CFGWRT(x) ((x) << S_T5_RX_CFGWRT)
36974 #define F_T5_RX_CFGWRT V_T5_RX_CFGWRT(1U)
36976 #define S_T5_RX_CFGPTR 11
36977 #define M_T5_RX_CFGPTR 0x3U
36978 #define V_T5_RX_CFGPTR(x) ((x) << S_T5_RX_CFGPTR)
36979 #define G_T5_RX_CFGPTR(x) (((x) >> S_T5_RX_CFGPTR) & M_T5_RX_CFGPTR)
36981 #define S_T5_RX_CFGEXT 10
36982 #define V_T5_RX_CFGEXT(x) ((x) << S_T5_RX_CFGEXT)
36983 #define F_T5_RX_CFGEXT V_T5_RX_CFGEXT(1U)
36985 #define S_T5_RX_CFGACT 9
36986 #define V_T5_RX_CFGACT(x) ((x) << S_T5_RX_CFGACT)
36987 #define F_T5_RX_CFGACT V_T5_RX_CFGACT(1U)
36989 #define S_T5_RX_AUXCLK 8
36990 #define V_T5_RX_AUXCLK(x) ((x) << S_T5_RX_AUXCLK)
36991 #define F_T5_RX_AUXCLK V_T5_RX_AUXCLK(1U)
36993 #define S_T5_RX_PLLSEL 6
36994 #define M_T5_RX_PLLSEL 0x3U
36995 #define V_T5_RX_PLLSEL(x) ((x) << S_T5_RX_PLLSEL)
36996 #define G_T5_RX_PLLSEL(x) (((x) >> S_T5_RX_PLLSEL) & M_T5_RX_PLLSEL)
36998 #define S_T5_RX_DMSEL 4
36999 #define M_T5_RX_DMSEL 0x3U
37000 #define V_T5_RX_DMSEL(x) ((x) << S_T5_RX_DMSEL)
37001 #define G_T5_RX_DMSEL(x) (((x) >> S_T5_RX_DMSEL) & M_T5_RX_DMSEL)
37003 #define S_T5_RX_BWSEL 2
37004 #define M_T5_RX_BWSEL 0x3U
37005 #define V_T5_RX_BWSEL(x) ((x) << S_T5_RX_BWSEL)
37006 #define G_T5_RX_BWSEL(x) (((x) >> S_T5_RX_BWSEL) & M_T5_RX_BWSEL)
37008 #define S_T5_RX_RTSEL 0
37009 #define M_T5_RX_RTSEL 0x3U
37010 #define V_T5_RX_RTSEL(x) ((x) << S_T5_RX_RTSEL)
37011 #define G_T5_RX_RTSEL(x) (((x) >> S_T5_RX_RTSEL) & M_T5_RX_RTSEL)
37013 #define A_MAC_PORT_RX_LINKA_RECEIVER_TEST_CONTROL 0x3204
37015 #define S_FERRST 10
37016 #define V_FERRST(x) ((x) << S_FERRST)
37017 #define F_FERRST V_FERRST(1U)
37020 #define V_ERRST(x) ((x) << S_ERRST)
37021 #define F_ERRST V_ERRST(1U)
37024 #define V_SYNCST(x) ((x) << S_SYNCST)
37025 #define F_SYNCST V_SYNCST(1U)
37028 #define V_WRPSM(x) ((x) << S_WRPSM)
37029 #define F_WRPSM V_WRPSM(1U)
37032 #define V_WPLPEN(x) ((x) << S_WPLPEN)
37033 #define F_WPLPEN V_WPLPEN(1U)
37036 #define V_WRPMD(x) ((x) << S_WRPMD)
37037 #define F_WRPMD V_WRPMD(1U)
37040 #define M_PATSEL 0x7U
37041 #define V_PATSEL(x) ((x) << S_PATSEL)
37042 #define G_PATSEL(x) (((x) >> S_PATSEL) & M_PATSEL)
37044 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_CONTROL 0x3208
37047 #define V_RSTUCK(x) ((x) << S_RSTUCK)
37048 #define F_RSTUCK V_RSTUCK(1U)
37051 #define V_FRZFW(x) ((x) << S_FRZFW)
37052 #define F_FRZFW V_FRZFW(1U)
37055 #define V_RSTFW(x) ((x) << S_RSTFW)
37056 #define F_RSTFW V_RSTFW(1U)
37059 #define V_SSCEN(x) ((x) << S_SSCEN)
37060 #define F_SSCEN V_SSCEN(1U)
37062 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_OFFSET_CONTROL 0x320c
37063 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_1 0x3210
37066 #define M_ROT00 0x3fU
37067 #define V_ROT00(x) ((x) << S_ROT00)
37068 #define G_ROT00(x) (((x) >> S_ROT00) & M_ROT00)
37070 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_POSITION_2 0x3214
37073 #define M_FREQFW 0xffU
37074 #define V_FREQFW(x) ((x) << S_FREQFW)
37075 #define G_FREQFW(x) (((x) >> S_FREQFW) & M_FREQFW)
37078 #define V_FWSNAP(x) ((x) << S_FWSNAP)
37079 #define F_FWSNAP V_FWSNAP(1U)
37081 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3218
37082 #define A_MAC_PORT_RX_LINKA_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x321c
37084 #define S_RBOOFF 10
37085 #define M_RBOOFF 0x1fU
37086 #define V_RBOOFF(x) ((x) << S_RBOOFF)
37087 #define G_RBOOFF(x) (((x) >> S_RBOOFF) & M_RBOOFF)
37090 #define M_RBEOFF 0x1fU
37091 #define V_RBEOFF(x) ((x) << S_RBEOFF)
37092 #define G_RBEOFF(x) (((x) >> S_RBEOFF) & M_RBEOFF)
37094 #define A_MAC_PORT_RX_LINKA_DFE_CONTROL 0x3220
37095 #define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_1 0x3224
37097 #define S_T5BYTE1 8
37098 #define M_T5BYTE1 0xffU
37099 #define V_T5BYTE1(x) ((x) << S_T5BYTE1)
37100 #define G_T5BYTE1(x) (((x) >> S_T5BYTE1) & M_T5BYTE1)
37102 #define S_T5BYTE0 0
37103 #define M_T5BYTE0 0xffU
37104 #define V_T5BYTE0(x) ((x) << S_T5BYTE0)
37105 #define G_T5BYTE0(x) (((x) >> S_T5BYTE0) & M_T5BYTE0)
37107 #define A_MAC_PORT_RX_LINKA_DFE_SAMPLE_SNAPSHOT_2 0x3228
37109 #define S_T5_RX_SMODE 8
37110 #define M_T5_RX_SMODE 0x7U
37111 #define V_T5_RX_SMODE(x) ((x) << S_T5_RX_SMODE)
37112 #define G_T5_RX_SMODE(x) (((x) >> S_T5_RX_SMODE) & M_T5_RX_SMODE)
37114 #define S_T5_RX_ADCORR 7
37115 #define V_T5_RX_ADCORR(x) ((x) << S_T5_RX_ADCORR)
37116 #define F_T5_RX_ADCORR V_T5_RX_ADCORR(1U)
37118 #define S_T5_RX_TRAINEN 6
37119 #define V_T5_RX_TRAINEN(x) ((x) << S_T5_RX_TRAINEN)
37120 #define F_T5_RX_TRAINEN V_T5_RX_TRAINEN(1U)
37122 #define S_T5_RX_ASAMPQ 3
37123 #define M_T5_RX_ASAMPQ 0x7U
37124 #define V_T5_RX_ASAMPQ(x) ((x) << S_T5_RX_ASAMPQ)
37125 #define G_T5_RX_ASAMPQ(x) (((x) >> S_T5_RX_ASAMPQ) & M_T5_RX_ASAMPQ)
37127 #define S_T5_RX_ASAMP 0
37128 #define M_T5_RX_ASAMP 0x7U
37129 #define V_T5_RX_ASAMP(x) ((x) << S_T5_RX_ASAMP)
37130 #define G_T5_RX_ASAMP(x) (((x) >> S_T5_RX_ASAMP) & M_T5_RX_ASAMP)
37132 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_1 0x322c
37133 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_2 0x3230
37135 #define S_T5SHORTV 10
37136 #define V_T5SHORTV(x) ((x) << S_T5SHORTV)
37137 #define F_T5SHORTV V_T5SHORTV(1U)
37139 #define S_T5VGAIN 0
37140 #define M_T5VGAIN 0x1fU
37141 #define V_T5VGAIN(x) ((x) << S_T5VGAIN)
37142 #define G_T5VGAIN(x) (((x) >> S_T5VGAIN) & M_T5VGAIN)
37144 #define A_MAC_PORT_RX_LINKA_RECEIVER_VGA_CONTROL_3 0x3234
37145 #define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_1 0x3238
37148 #define M_IQSEP 0x1fU
37149 #define V_IQSEP(x) ((x) << S_IQSEP)
37150 #define G_IQSEP(x) (((x) >> S_IQSEP) & M_IQSEP)
37153 #define M_DUTYQ 0x1fU
37154 #define V_DUTYQ(x) ((x) << S_DUTYQ)
37155 #define G_DUTYQ(x) (((x) >> S_DUTYQ) & M_DUTYQ)
37158 #define M_DUTYI 0x1fU
37159 #define V_DUTYI(x) ((x) << S_DUTYI)
37160 #define G_DUTYI(x) (((x) >> S_DUTYI) & M_DUTYI)
37162 #define A_MAC_PORT_RX_LINKA_RECEIVER_DQCC_CONTROL_3 0x3240
37165 #define M_DTHR 0x3fU
37166 #define V_DTHR(x) ((x) << S_DTHR)
37167 #define G_DTHR(x) (((x) >> S_DTHR) & M_DTHR)
37170 #define M_SNUL 0x1fU
37171 #define V_SNUL(x) ((x) << S_SNUL)
37172 #define G_SNUL(x) (((x) >> S_SNUL) & M_SNUL)
37174 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACAP_AND_DACAN 0x3248
37175 #define A_MAC_PORT_RX_LINKA_RECEIVER_DACA_MIN_AND_DACAZ 0x324c
37176 #define A_MAC_PORT_RX_LINKA_RECEIVER_ADAC_CONTROL 0x3250
37178 #define S_ADSN_READWRITE 8
37179 #define V_ADSN_READWRITE(x) ((x) << S_ADSN_READWRITE)
37180 #define F_ADSN_READWRITE V_ADSN_READWRITE(1U)
37182 #define S_ADSN_READONLY 7
37183 #define V_ADSN_READONLY(x) ((x) << S_ADSN_READONLY)
37184 #define F_ADSN_READONLY V_ADSN_READONLY(1U)
37186 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x325c
37189 #define M_H1O2 0x3fU
37190 #define V_H1O2(x) ((x) << S_H1O2)
37191 #define G_H1O2(x) (((x) >> S_H1O2) & M_H1O2)
37194 #define M_H1E2 0x3fU
37195 #define V_H1E2(x) ((x) << S_H1E2)
37196 #define G_H1E2(x) (((x) >> S_H1E2) & M_H1E2)
37198 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3260
37201 #define M_H1O3 0x3fU
37202 #define V_H1O3(x) ((x) << S_H1O3)
37203 #define G_H1O3(x) (((x) >> S_H1O3) & M_H1O3)
37206 #define M_H1E3 0x3fU
37207 #define V_H1E3(x) ((x) << S_H1E3)
37208 #define G_H1E3(x) (((x) >> S_H1E3) & M_H1E3)
37210 #define A_MAC_PORT_RX_LINKA_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3264
37213 #define M_H1O4 0x3fU
37214 #define V_H1O4(x) ((x) << S_H1O4)
37215 #define G_H1O4(x) (((x) >> S_H1O4) & M_H1O4)
37218 #define M_H1E4 0x3fU
37219 #define V_H1E4(x) ((x) << S_H1E4)
37220 #define G_H1E4(x) (((x) >> S_H1E4) & M_H1E4)
37222 #define A_MAC_PORT_RX_LINKA_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3270
37225 #define V_DPCMD(x) ((x) << S_DPCMD)
37226 #define F_DPCMD V_DPCMD(1U)
37228 #define A_MAC_PORT_RX_LINKA_DYNAMIC_DATA_CENTERING_DDC 0x3274
37229 #define A_MAC_PORT_RX_LINKA_RECEIVER_INTERNAL_STATUS 0x3278
37231 #define S_T5BER6VAL 15
37232 #define V_T5BER6VAL(x) ((x) << S_T5BER6VAL)
37233 #define F_T5BER6VAL V_T5BER6VAL(1U)
37235 #define S_T5BER6 14
37236 #define V_T5BER6(x) ((x) << S_T5BER6)
37237 #define F_T5BER6 V_T5BER6(1U)
37239 #define S_T5BER3VAL 13
37240 #define V_T5BER3VAL(x) ((x) << S_T5BER3VAL)
37241 #define F_T5BER3VAL V_T5BER3VAL(1U)
37243 #define S_T5TOOFAST 12
37244 #define V_T5TOOFAST(x) ((x) << S_T5TOOFAST)
37245 #define F_T5TOOFAST V_T5TOOFAST(1U)
37247 #define S_T5DPCCMP 9
37248 #define V_T5DPCCMP(x) ((x) << S_T5DPCCMP)
37249 #define F_T5DPCCMP V_T5DPCCMP(1U)
37251 #define S_T5DACCMP 8
37252 #define V_T5DACCMP(x) ((x) << S_T5DACCMP)
37253 #define F_T5DACCMP V_T5DACCMP(1U)
37255 #define S_T5DDCCMP 7
37256 #define V_T5DDCCMP(x) ((x) << S_T5DDCCMP)
37257 #define F_T5DDCCMP V_T5DDCCMP(1U)
37259 #define S_T5AERRFLG 6
37260 #define V_T5AERRFLG(x) ((x) << S_T5AERRFLG)
37261 #define F_T5AERRFLG V_T5AERRFLG(1U)
37263 #define S_T5WERRFLG 5
37264 #define V_T5WERRFLG(x) ((x) << S_T5WERRFLG)
37265 #define F_T5WERRFLG V_T5WERRFLG(1U)
37267 #define S_T5TRCMP 4
37268 #define V_T5TRCMP(x) ((x) << S_T5TRCMP)
37269 #define F_T5TRCMP V_T5TRCMP(1U)
37271 #define S_T5VLCKF 3
37272 #define V_T5VLCKF(x) ((x) << S_T5VLCKF)
37273 #define F_T5VLCKF V_T5VLCKF(1U)
37275 #define S_T5ROCCMP 2
37276 #define V_T5ROCCMP(x) ((x) << S_T5ROCCMP)
37277 #define F_T5ROCCMP V_T5ROCCMP(1U)
37279 #define S_T5DQCCCMP 1
37280 #define V_T5DQCCCMP(x) ((x) << S_T5DQCCCMP)
37281 #define F_T5DQCCCMP V_T5DQCCCMP(1U)
37283 #define S_T5OCCMP 0
37284 #define V_T5OCCMP(x) ((x) << S_T5OCCMP)
37285 #define F_T5OCCMP V_T5OCCMP(1U)
37287 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_1 0x327c
37290 #define V_FLOFF(x) ((x) << S_FLOFF)
37291 #define F_FLOFF V_FLOFF(1U)
37293 #define A_MAC_PORT_RX_LINKA_DFE_FUNCTION_CONTROL_2 0x3280
37295 #define S_H25SPC 15
37296 #define V_H25SPC(x) ((x) << S_H25SPC)
37297 #define F_H25SPC V_H25SPC(1U)
37299 #define S_FTOOFAST 8
37300 #define V_FTOOFAST(x) ((x) << S_FTOOFAST)
37301 #define F_FTOOFAST V_FTOOFAST(1U)
37303 #define S_FINTTRIM 7
37304 #define V_FINTTRIM(x) ((x) << S_FINTTRIM)
37305 #define F_FINTTRIM V_FINTTRIM(1U)
37308 #define V_FDINV(x) ((x) << S_FDINV)
37309 #define F_FDINV V_FDINV(1U)
37312 #define V_FHGS(x) ((x) << S_FHGS)
37313 #define F_FHGS V_FHGS(1U)
37316 #define V_FH6H12(x) ((x) << S_FH6H12)
37317 #define F_FH6H12 V_FH6H12(1U)
37320 #define V_FH1CAL(x) ((x) << S_FH1CAL)
37321 #define F_FH1CAL V_FH1CAL(1U)
37323 #define S_FINTCAL 2
37324 #define V_FINTCAL(x) ((x) << S_FINTCAL)
37325 #define F_FINTCAL V_FINTCAL(1U)
37328 #define V_FDCA(x) ((x) << S_FDCA)
37329 #define F_FDCA V_FDCA(1U)
37332 #define V_FDQCC(x) ((x) << S_FDQCC)
37333 #define F_FDQCC V_FDQCC(1U)
37335 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN1_EVN2 0x3284
37337 #define S_LOFE2S_READWRITE 16
37338 #define V_LOFE2S_READWRITE(x) ((x) << S_LOFE2S_READWRITE)
37339 #define F_LOFE2S_READWRITE V_LOFE2S_READWRITE(1U)
37341 #define S_LOFE2S_READONLY 14
37342 #define M_LOFE2S_READONLY 0x3U
37343 #define V_LOFE2S_READONLY(x) ((x) << S_LOFE2S_READONLY)
37344 #define G_LOFE2S_READONLY(x) (((x) >> S_LOFE2S_READONLY) & M_LOFE2S_READONLY)
37347 #define M_LOFE2 0x3fU
37348 #define V_LOFE2(x) ((x) << S_LOFE2)
37349 #define G_LOFE2(x) (((x) >> S_LOFE2) & M_LOFE2)
37351 #define S_LOFE1S_READWRITE 7
37352 #define V_LOFE1S_READWRITE(x) ((x) << S_LOFE1S_READWRITE)
37353 #define F_LOFE1S_READWRITE V_LOFE1S_READWRITE(1U)
37355 #define S_LOFE1S_READONLY 6
37356 #define V_LOFE1S_READONLY(x) ((x) << S_LOFE1S_READONLY)
37357 #define F_LOFE1S_READONLY V_LOFE1S_READONLY(1U)
37360 #define M_LOFE1 0x3fU
37361 #define V_LOFE1(x) ((x) << S_LOFE1)
37362 #define G_LOFE1(x) (((x) >> S_LOFE1) & M_LOFE1)
37364 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD1_ODD2 0x3288
37366 #define S_LOFO2S_READWRITE 15
37367 #define V_LOFO2S_READWRITE(x) ((x) << S_LOFO2S_READWRITE)
37368 #define F_LOFO2S_READWRITE V_LOFO2S_READWRITE(1U)
37370 #define S_LOFO2S_READONLY 14
37371 #define V_LOFO2S_READONLY(x) ((x) << S_LOFO2S_READONLY)
37372 #define F_LOFO2S_READONLY V_LOFO2S_READONLY(1U)
37375 #define M_LOFO2 0x3fU
37376 #define V_LOFO2(x) ((x) << S_LOFO2)
37377 #define G_LOFO2(x) (((x) >> S_LOFO2) & M_LOFO2)
37379 #define S_LOFO1S_READWRITE 7
37380 #define V_LOFO1S_READWRITE(x) ((x) << S_LOFO1S_READWRITE)
37381 #define F_LOFO1S_READWRITE V_LOFO1S_READWRITE(1U)
37383 #define S_LOFO1S_READONLY 6
37384 #define V_LOFO1S_READONLY(x) ((x) << S_LOFO1S_READONLY)
37385 #define F_LOFO1S_READONLY V_LOFO1S_READONLY(1U)
37388 #define M_LOFO1 0x3fU
37389 #define V_LOFO1(x) ((x) << S_LOFO1)
37390 #define G_LOFO1(x) (((x) >> S_LOFO1) & M_LOFO1)
37392 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_EVN3_EVN4 0x328c
37394 #define S_LOFE4S_READWRITE 15
37395 #define V_LOFE4S_READWRITE(x) ((x) << S_LOFE4S_READWRITE)
37396 #define F_LOFE4S_READWRITE V_LOFE4S_READWRITE(1U)
37398 #define S_LOFE4S_READONLY 14
37399 #define V_LOFE4S_READONLY(x) ((x) << S_LOFE4S_READONLY)
37400 #define F_LOFE4S_READONLY V_LOFE4S_READONLY(1U)
37403 #define M_LOFE 0x3fU
37404 #define V_LOFE(x) ((x) << S_LOFE)
37405 #define G_LOFE(x) (((x) >> S_LOFE) & M_LOFE)
37407 #define S_LOFE3S_READWRITE 7
37408 #define V_LOFE3S_READWRITE(x) ((x) << S_LOFE3S_READWRITE)
37409 #define F_LOFE3S_READWRITE V_LOFE3S_READWRITE(1U)
37411 #define S_LOFE3S_READONLY 6
37412 #define V_LOFE3S_READONLY(x) ((x) << S_LOFE3S_READONLY)
37413 #define F_LOFE3S_READONLY V_LOFE3S_READONLY(1U)
37416 #define M_LOFE3 0x3fU
37417 #define V_LOFE3(x) ((x) << S_LOFE3)
37418 #define G_LOFE3(x) (((x) >> S_LOFE3) & M_LOFE3)
37420 #define A_MAC_PORT_RX_LINKA_DFE_OFFSET_ODD3_ODD4 0x3290
37422 #define S_LOFO4S_READWRITE 15
37423 #define V_LOFO4S_READWRITE(x) ((x) << S_LOFO4S_READWRITE)
37424 #define F_LOFO4S_READWRITE V_LOFO4S_READWRITE(1U)
37426 #define S_LOFO4S_READONLY 14
37427 #define V_LOFO4S_READONLY(x) ((x) << S_LOFO4S_READONLY)
37428 #define F_LOFO4S_READONLY V_LOFO4S_READONLY(1U)
37431 #define M_LOFO4 0x3fU
37432 #define V_LOFO4(x) ((x) << S_LOFO4)
37433 #define G_LOFO4(x) (((x) >> S_LOFO4) & M_LOFO4)
37435 #define S_LOFO3S_READWRITE 7
37436 #define V_LOFO3S_READWRITE(x) ((x) << S_LOFO3S_READWRITE)
37437 #define F_LOFO3S_READWRITE V_LOFO3S_READWRITE(1U)
37439 #define S_LOFO3S_READONLY 6
37440 #define V_LOFO3S_READONLY(x) ((x) << S_LOFO3S_READONLY)
37441 #define F_LOFO3S_READONLY V_LOFO3S_READONLY(1U)
37444 #define M_LOFO3 0x3fU
37445 #define V_LOFO3(x) ((x) << S_LOFO3)
37446 #define G_LOFO3(x) (((x) >> S_LOFO3) & M_LOFO3)
37448 #define A_MAC_PORT_RX_LINKA_DFE_E0_AND_E1_OFFSET 0x3294
37450 #define S_T5E1SN_READWRITE 15
37451 #define V_T5E1SN_READWRITE(x) ((x) << S_T5E1SN_READWRITE)
37452 #define F_T5E1SN_READWRITE V_T5E1SN_READWRITE(1U)
37454 #define S_T5E1SN_READONLY 14
37455 #define V_T5E1SN_READONLY(x) ((x) << S_T5E1SN_READONLY)
37456 #define F_T5E1SN_READONLY V_T5E1SN_READONLY(1U)
37458 #define S_T5E1AMP 8
37459 #define M_T5E1AMP 0x3fU
37460 #define V_T5E1AMP(x) ((x) << S_T5E1AMP)
37461 #define G_T5E1AMP(x) (((x) >> S_T5E1AMP) & M_T5E1AMP)
37463 #define S_T5E0SN_READWRITE 7
37464 #define V_T5E0SN_READWRITE(x) ((x) << S_T5E0SN_READWRITE)
37465 #define F_T5E0SN_READWRITE V_T5E0SN_READWRITE(1U)
37467 #define S_T5E0SN_READONLY 6
37468 #define V_T5E0SN_READONLY(x) ((x) << S_T5E0SN_READONLY)
37469 #define F_T5E0SN_READONLY V_T5E0SN_READONLY(1U)
37471 #define S_T5E0AMP 0
37472 #define M_T5E0AMP 0x3fU
37473 #define V_T5E0AMP(x) ((x) << S_T5E0AMP)
37474 #define G_T5E0AMP(x) (((x) >> S_T5E0AMP) & M_T5E0AMP)
37476 #define A_MAC_PORT_RX_LINKA_RECEIVER_LOFF_CONTROL 0x3298
37478 #define S_T5LFREG 12
37479 #define V_T5LFREG(x) ((x) << S_T5LFREG)
37480 #define F_T5LFREG V_T5LFREG(1U)
37482 #define S_T5LFRC 11
37483 #define V_T5LFRC(x) ((x) << S_T5LFRC)
37484 #define F_T5LFRC V_T5LFRC(1U)
37486 #define S_T5LFSEL 8
37487 #define M_T5LFSEL 0x7U
37488 #define V_T5LFSEL(x) ((x) << S_T5LFSEL)
37489 #define G_T5LFSEL(x) (((x) >> S_T5LFSEL) & M_T5LFSEL)
37491 #define A_MAC_PORT_RX_LINKA_RECEIVER_SIGDET_CONTROL 0x329c
37493 #define S_OFFSN_READWRITE 14
37494 #define V_OFFSN_READWRITE(x) ((x) << S_OFFSN_READWRITE)
37495 #define F_OFFSN_READWRITE V_OFFSN_READWRITE(1U)
37497 #define S_OFFSN_READONLY 13
37498 #define V_OFFSN_READONLY(x) ((x) << S_OFFSN_READONLY)
37499 #define F_OFFSN_READONLY V_OFFSN_READONLY(1U)
37502 #define M_OFFAMP 0x1fU
37503 #define V_OFFAMP(x) ((x) << S_OFFAMP)
37504 #define G_OFFAMP(x) (((x) >> S_OFFAMP) & M_OFFAMP)
37507 #define V_SDACDC(x) ((x) << S_SDACDC)
37508 #define F_SDACDC V_SDACDC(1U)
37510 #define A_MAC_PORT_RX_LINKA_RECEIVER_ANALOG_CONTROL_SWITCH 0x32a0
37512 #define S_T5_RX_SETHDIS 7
37513 #define V_T5_RX_SETHDIS(x) ((x) << S_T5_RX_SETHDIS)
37514 #define F_T5_RX_SETHDIS V_T5_RX_SETHDIS(1U)
37516 #define S_T5_RX_PDTERM 6
37517 #define V_T5_RX_PDTERM(x) ((x) << S_T5_RX_PDTERM)
37518 #define F_T5_RX_PDTERM V_T5_RX_PDTERM(1U)
37520 #define S_T5_RX_BYPASS 5
37521 #define V_T5_RX_BYPASS(x) ((x) << S_T5_RX_BYPASS)
37522 #define F_T5_RX_BYPASS V_T5_RX_BYPASS(1U)
37524 #define S_T5_RX_LPFEN 4
37525 #define V_T5_RX_LPFEN(x) ((x) << S_T5_RX_LPFEN)
37526 #define F_T5_RX_LPFEN V_T5_RX_LPFEN(1U)
37528 #define S_T5_RX_VGABOD 3
37529 #define V_T5_RX_VGABOD(x) ((x) << S_T5_RX_VGABOD)
37530 #define F_T5_RX_VGABOD V_T5_RX_VGABOD(1U)
37532 #define S_T5_RX_VTBYP 2
37533 #define V_T5_RX_VTBYP(x) ((x) << S_T5_RX_VTBYP)
37534 #define F_T5_RX_VTBYP V_T5_RX_VTBYP(1U)
37536 #define S_T5_RX_VTERM 0
37537 #define M_T5_RX_VTERM 0x3U
37538 #define V_T5_RX_VTERM(x) ((x) << S_T5_RX_VTERM)
37539 #define G_T5_RX_VTERM(x) (((x) >> S_T5_RX_VTERM) & M_T5_RX_VTERM)
37541 #define A_MAC_PORT_RX_LINKA_INTEGRATOR_DAC_OFFSET 0x32a4
37543 #define S_ISTRIMS 14
37544 #define M_ISTRIMS 0x3U
37545 #define V_ISTRIMS(x) ((x) << S_ISTRIMS)
37546 #define G_ISTRIMS(x) (((x) >> S_ISTRIMS) & M_ISTRIMS)
37549 #define M_ISTRIM 0x3fU
37550 #define V_ISTRIM(x) ((x) << S_ISTRIM)
37551 #define G_ISTRIM(x) (((x) >> S_ISTRIM) & M_ISTRIM)
37554 #define V_HALF1(x) ((x) << S_HALF1)
37555 #define F_HALF1 V_HALF1(1U)
37558 #define V_HALF2(x) ((x) << S_HALF2)
37559 #define F_HALF2 V_HALF2(1U)
37562 #define M_INTDAC 0x3fU
37563 #define V_INTDAC(x) ((x) << S_INTDAC)
37564 #define G_INTDAC(x) (((x) >> S_INTDAC) & M_INTDAC)
37566 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_CONTROL 0x32a8
37568 #define S_MINWDTH 5
37569 #define M_MINWDTH 0x1fU
37570 #define V_MINWDTH(x) ((x) << S_MINWDTH)
37571 #define G_MINWDTH(x) (((x) >> S_MINWDTH) & M_MINWDTH)
37573 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS 0x32ac
37575 #define S_T5SMQM 13
37576 #define M_T5SMQM 0x7U
37577 #define V_T5SMQM(x) ((x) << S_T5SMQM)
37578 #define G_T5SMQM(x) (((x) >> S_T5SMQM) & M_T5SMQM)
37581 #define M_T5SMQ 0xffU
37582 #define V_T5SMQ(x) ((x) << S_T5SMQ)
37583 #define G_T5SMQ(x) (((x) >> S_T5SMQ) & M_T5SMQ)
37586 #define M_T5EMMD 0x3U
37587 #define V_T5EMMD(x) ((x) << S_T5EMMD)
37588 #define G_T5EMMD(x) (((x) >> S_T5EMMD) & M_T5EMMD)
37590 #define S_T5EMBRDY 2
37591 #define V_T5EMBRDY(x) ((x) << S_T5EMBRDY)
37592 #define F_T5EMBRDY V_T5EMBRDY(1U)
37594 #define S_T5EMBUMP 1
37595 #define V_T5EMBUMP(x) ((x) << S_T5EMBUMP)
37596 #define F_T5EMBUMP V_T5EMBUMP(1U)
37599 #define V_T5EMEN(x) ((x) << S_T5EMEN)
37600 #define F_T5EMEN V_T5EMEN(1U)
37602 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_ERROR_COUNT 0x32b0
37605 #define V_EMF8(x) ((x) << S_EMF8)
37606 #define F_EMF8 V_EMF8(1U)
37609 #define M_EMCNT 0xffU
37610 #define V_EMCNT(x) ((x) << S_EMCNT)
37611 #define G_EMCNT(x) (((x) >> S_EMCNT) & M_EMCNT)
37614 #define V_EMOFLO(x) ((x) << S_EMOFLO)
37615 #define F_EMOFLO V_EMOFLO(1U)
37618 #define V_EMCRST(x) ((x) << S_EMCRST)
37619 #define F_EMCRST V_EMCRST(1U)
37622 #define V_EMCEN(x) ((x) << S_EMCEN)
37623 #define F_EMCEN V_EMCEN(1U)
37625 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x32b4
37627 #define S_SM2RDY 15
37628 #define V_SM2RDY(x) ((x) << S_SM2RDY)
37629 #define F_SM2RDY V_SM2RDY(1U)
37631 #define S_SM2RST 14
37632 #define V_SM2RST(x) ((x) << S_SM2RST)
37633 #define F_SM2RST V_SM2RST(1U)
37636 #define M_APDF 0xfffU
37637 #define V_APDF(x) ((x) << S_APDF)
37638 #define G_APDF(x) (((x) >> S_APDF) & M_APDF)
37640 #define A_MAC_PORT_RX_LINKA_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x32b8
37643 #define M_SM0LEN 0x7fffU
37644 #define V_SM0LEN(x) ((x) << S_SM0LEN)
37645 #define G_SM0LEN(x) (((x) >> S_SM0LEN) & M_SM0LEN)
37647 #define A_MAC_PORT_RX_LINKA_DFE_TAP_ENABLE 0x32c0
37650 #define M_H_EN 0xfffU
37651 #define V_H_EN(x) ((x) << S_H_EN)
37652 #define G_H_EN(x) (((x) >> S_H_EN) & M_H_EN)
37654 #define A_MAC_PORT_RX_LINKA_DFE_H1 0x32c4
37655 #define A_MAC_PORT_RX_LINKA_DFE_H2 0x32c8
37657 #define S_H2OSN_READWRITE 14
37658 #define V_H2OSN_READWRITE(x) ((x) << S_H2OSN_READWRITE)
37659 #define F_H2OSN_READWRITE V_H2OSN_READWRITE(1U)
37661 #define S_H2OSN_READONLY 13
37662 #define V_H2OSN_READONLY(x) ((x) << S_H2OSN_READONLY)
37663 #define F_H2OSN_READONLY V_H2OSN_READONLY(1U)
37665 #define S_H2ESN_READWRITE 6
37666 #define V_H2ESN_READWRITE(x) ((x) << S_H2ESN_READWRITE)
37667 #define F_H2ESN_READWRITE V_H2ESN_READWRITE(1U)
37669 #define S_H2ESN_READONLY 5
37670 #define V_H2ESN_READONLY(x) ((x) << S_H2ESN_READONLY)
37671 #define F_H2ESN_READONLY V_H2ESN_READONLY(1U)
37673 #define A_MAC_PORT_RX_LINKA_DFE_H3 0x32cc
37675 #define S_H3OSN_READWRITE 13
37676 #define V_H3OSN_READWRITE(x) ((x) << S_H3OSN_READWRITE)
37677 #define F_H3OSN_READWRITE V_H3OSN_READWRITE(1U)
37679 #define S_H3OSN_READONLY 12
37680 #define V_H3OSN_READONLY(x) ((x) << S_H3OSN_READONLY)
37681 #define F_H3OSN_READONLY V_H3OSN_READONLY(1U)
37683 #define S_H3ESN_READWRITE 5
37684 #define V_H3ESN_READWRITE(x) ((x) << S_H3ESN_READWRITE)
37685 #define F_H3ESN_READWRITE V_H3ESN_READWRITE(1U)
37687 #define S_H3ESN_READONLY 4
37688 #define V_H3ESN_READONLY(x) ((x) << S_H3ESN_READONLY)
37689 #define F_H3ESN_READONLY V_H3ESN_READONLY(1U)
37691 #define A_MAC_PORT_RX_LINKA_DFE_H4 0x32d0
37694 #define M_H4OGS 0x3U
37695 #define V_H4OGS(x) ((x) << S_H4OGS)
37696 #define G_H4OGS(x) (((x) >> S_H4OGS) & M_H4OGS)
37698 #define S_H4OSN_READWRITE 13
37699 #define V_H4OSN_READWRITE(x) ((x) << S_H4OSN_READWRITE)
37700 #define F_H4OSN_READWRITE V_H4OSN_READWRITE(1U)
37702 #define S_H4OSN_READONLY 12
37703 #define V_H4OSN_READONLY(x) ((x) << S_H4OSN_READONLY)
37704 #define F_H4OSN_READONLY V_H4OSN_READONLY(1U)
37707 #define M_H4EGS 0x3U
37708 #define V_H4EGS(x) ((x) << S_H4EGS)
37709 #define G_H4EGS(x) (((x) >> S_H4EGS) & M_H4EGS)
37711 #define S_H4ESN_READWRITE 5
37712 #define V_H4ESN_READWRITE(x) ((x) << S_H4ESN_READWRITE)
37713 #define F_H4ESN_READWRITE V_H4ESN_READWRITE(1U)
37715 #define S_H4ESN_READONLY 4
37716 #define V_H4ESN_READONLY(x) ((x) << S_H4ESN_READONLY)
37717 #define F_H4ESN_READONLY V_H4ESN_READONLY(1U)
37719 #define A_MAC_PORT_RX_LINKA_DFE_H5 0x32d4
37722 #define M_H5OGS 0x3U
37723 #define V_H5OGS(x) ((x) << S_H5OGS)
37724 #define G_H5OGS(x) (((x) >> S_H5OGS) & M_H5OGS)
37726 #define S_H5OSN_READWRITE 13
37727 #define V_H5OSN_READWRITE(x) ((x) << S_H5OSN_READWRITE)
37728 #define F_H5OSN_READWRITE V_H5OSN_READWRITE(1U)
37730 #define S_H5OSN_READONLY 12
37731 #define V_H5OSN_READONLY(x) ((x) << S_H5OSN_READONLY)
37732 #define F_H5OSN_READONLY V_H5OSN_READONLY(1U)
37735 #define M_H5EGS 0x3U
37736 #define V_H5EGS(x) ((x) << S_H5EGS)
37737 #define G_H5EGS(x) (((x) >> S_H5EGS) & M_H5EGS)
37739 #define S_H5ESN_READWRITE 5
37740 #define V_H5ESN_READWRITE(x) ((x) << S_H5ESN_READWRITE)
37741 #define F_H5ESN_READWRITE V_H5ESN_READWRITE(1U)
37743 #define S_H5ESN_READONLY 4
37744 #define V_H5ESN_READONLY(x) ((x) << S_H5ESN_READONLY)
37745 #define F_H5ESN_READONLY V_H5ESN_READONLY(1U)
37747 #define A_MAC_PORT_RX_LINKA_DFE_H6_AND_H7 0x32d8
37750 #define M_H7GS 0x3U
37751 #define V_H7GS(x) ((x) << S_H7GS)
37752 #define G_H7GS(x) (((x) >> S_H7GS) & M_H7GS)
37754 #define S_H7SN_READWRITE 13
37755 #define V_H7SN_READWRITE(x) ((x) << S_H7SN_READWRITE)
37756 #define F_H7SN_READWRITE V_H7SN_READWRITE(1U)
37758 #define S_H7SN_READONLY 12
37759 #define V_H7SN_READONLY(x) ((x) << S_H7SN_READONLY)
37760 #define F_H7SN_READONLY V_H7SN_READONLY(1U)
37763 #define M_H7MAG 0xfU
37764 #define V_H7MAG(x) ((x) << S_H7MAG)
37765 #define G_H7MAG(x) (((x) >> S_H7MAG) & M_H7MAG)
37768 #define M_H6GS 0x3U
37769 #define V_H6GS(x) ((x) << S_H6GS)
37770 #define G_H6GS(x) (((x) >> S_H6GS) & M_H6GS)
37772 #define S_H6SN_READWRITE 5
37773 #define V_H6SN_READWRITE(x) ((x) << S_H6SN_READWRITE)
37774 #define F_H6SN_READWRITE V_H6SN_READWRITE(1U)
37776 #define S_H6SN_READONLY 4
37777 #define V_H6SN_READONLY(x) ((x) << S_H6SN_READONLY)
37778 #define F_H6SN_READONLY V_H6SN_READONLY(1U)
37781 #define M_H6MAG 0xfU
37782 #define V_H6MAG(x) ((x) << S_H6MAG)
37783 #define G_H6MAG(x) (((x) >> S_H6MAG) & M_H6MAG)
37785 #define A_MAC_PORT_RX_LINKA_DFE_H8_AND_H9 0x32dc
37788 #define M_H9GS 0x3U
37789 #define V_H9GS(x) ((x) << S_H9GS)
37790 #define G_H9GS(x) (((x) >> S_H9GS) & M_H9GS)
37792 #define S_H9SN_READWRITE 13
37793 #define V_H9SN_READWRITE(x) ((x) << S_H9SN_READWRITE)
37794 #define F_H9SN_READWRITE V_H9SN_READWRITE(1U)
37796 #define S_H9SN_READONLY 12
37797 #define V_H9SN_READONLY(x) ((x) << S_H9SN_READONLY)
37798 #define F_H9SN_READONLY V_H9SN_READONLY(1U)
37801 #define M_H9MAG 0xfU
37802 #define V_H9MAG(x) ((x) << S_H9MAG)
37803 #define G_H9MAG(x) (((x) >> S_H9MAG) & M_H9MAG)
37806 #define M_H8GS 0x3U
37807 #define V_H8GS(x) ((x) << S_H8GS)
37808 #define G_H8GS(x) (((x) >> S_H8GS) & M_H8GS)
37810 #define S_H8SN_READWRITE 5
37811 #define V_H8SN_READWRITE(x) ((x) << S_H8SN_READWRITE)
37812 #define F_H8SN_READWRITE V_H8SN_READWRITE(1U)
37814 #define S_H8SN_READONLY 4
37815 #define V_H8SN_READONLY(x) ((x) << S_H8SN_READONLY)
37816 #define F_H8SN_READONLY V_H8SN_READONLY(1U)
37819 #define M_H8MAG 0xfU
37820 #define V_H8MAG(x) ((x) << S_H8MAG)
37821 #define G_H8MAG(x) (((x) >> S_H8MAG) & M_H8MAG)
37823 #define A_MAC_PORT_RX_LINKA_DFE_H10_AND_H11 0x32e0
37826 #define M_H11GS 0x3U
37827 #define V_H11GS(x) ((x) << S_H11GS)
37828 #define G_H11GS(x) (((x) >> S_H11GS) & M_H11GS)
37830 #define S_H11SN_READWRITE 13
37831 #define V_H11SN_READWRITE(x) ((x) << S_H11SN_READWRITE)
37832 #define F_H11SN_READWRITE V_H11SN_READWRITE(1U)
37834 #define S_H11SN_READONLY 12
37835 #define V_H11SN_READONLY(x) ((x) << S_H11SN_READONLY)
37836 #define F_H11SN_READONLY V_H11SN_READONLY(1U)
37839 #define M_H11MAG 0xfU
37840 #define V_H11MAG(x) ((x) << S_H11MAG)
37841 #define G_H11MAG(x) (((x) >> S_H11MAG) & M_H11MAG)
37844 #define M_H10GS 0x3U
37845 #define V_H10GS(x) ((x) << S_H10GS)
37846 #define G_H10GS(x) (((x) >> S_H10GS) & M_H10GS)
37848 #define S_H10SN_READWRITE 5
37849 #define V_H10SN_READWRITE(x) ((x) << S_H10SN_READWRITE)
37850 #define F_H10SN_READWRITE V_H10SN_READWRITE(1U)
37852 #define S_H10SN_READONLY 4
37853 #define V_H10SN_READONLY(x) ((x) << S_H10SN_READONLY)
37854 #define F_H10SN_READONLY V_H10SN_READONLY(1U)
37857 #define M_H10MAG 0xfU
37858 #define V_H10MAG(x) ((x) << S_H10MAG)
37859 #define G_H10MAG(x) (((x) >> S_H10MAG) & M_H10MAG)
37861 #define A_MAC_PORT_RX_LINKA_DFE_H12 0x32e4
37864 #define M_H12GS 0x3U
37865 #define V_H12GS(x) ((x) << S_H12GS)
37866 #define G_H12GS(x) (((x) >> S_H12GS) & M_H12GS)
37868 #define S_H12SN_READWRITE 5
37869 #define V_H12SN_READWRITE(x) ((x) << S_H12SN_READWRITE)
37870 #define F_H12SN_READWRITE V_H12SN_READWRITE(1U)
37872 #define S_H12SN_READONLY 4
37873 #define V_H12SN_READONLY(x) ((x) << S_H12SN_READONLY)
37874 #define F_H12SN_READONLY V_H12SN_READONLY(1U)
37877 #define M_H12MAG 0xfU
37878 #define V_H12MAG(x) ((x) << S_H12MAG)
37879 #define G_H12MAG(x) (((x) >> S_H12MAG) & M_H12MAG)
37881 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_2 0x32f8
37883 #define S_DFEDACLSSD 6
37884 #define V_DFEDACLSSD(x) ((x) << S_DFEDACLSSD)
37885 #define F_DFEDACLSSD V_DFEDACLSSD(1U)
37888 #define V_SDLSSD(x) ((x) << S_SDLSSD)
37889 #define F_SDLSSD V_SDLSSD(1U)
37891 #define S_DFEOBSBIAS 4
37892 #define V_DFEOBSBIAS(x) ((x) << S_DFEOBSBIAS)
37893 #define F_DFEOBSBIAS V_DFEOBSBIAS(1U)
37895 #define S_GBOFSTLSSD 3
37896 #define V_GBOFSTLSSD(x) ((x) << S_GBOFSTLSSD)
37897 #define F_GBOFSTLSSD V_GBOFSTLSSD(1U)
37900 #define V_RXDOBS(x) ((x) << S_RXDOBS)
37901 #define F_RXDOBS V_RXDOBS(1U)
37904 #define V_ACJZPT(x) ((x) << S_ACJZPT)
37905 #define F_ACJZPT V_ACJZPT(1U)
37908 #define V_ACJZNT(x) ((x) << S_ACJZNT)
37909 #define F_ACJZNT V_ACJZNT(1U)
37911 #define A_MAC_PORT_RX_LINKA_RECEIVER_MACRO_TEST_CONTROL_1 0x32fc
37913 #define S_PHSLOCK 10
37914 #define V_PHSLOCK(x) ((x) << S_PHSLOCK)
37915 #define F_PHSLOCK V_PHSLOCK(1U)
37917 #define S_TESTMODE 9
37918 #define V_TESTMODE(x) ((x) << S_TESTMODE)
37919 #define F_TESTMODE V_TESTMODE(1U)
37921 #define S_CALMODE 8
37922 #define V_CALMODE(x) ((x) << S_CALMODE)
37923 #define F_CALMODE V_CALMODE(1U)
37926 #define V_AMPSEL(x) ((x) << S_AMPSEL)
37927 #define F_AMPSEL V_AMPSEL(1U)
37929 #define S_WHICHNRZ 6
37930 #define V_WHICHNRZ(x) ((x) << S_WHICHNRZ)
37931 #define F_WHICHNRZ V_WHICHNRZ(1U)
37934 #define V_BANKA(x) ((x) << S_BANKA)
37935 #define F_BANKA V_BANKA(1U)
37938 #define V_BANKB(x) ((x) << S_BANKB)
37939 #define F_BANKB V_BANKB(1U)
37942 #define V_ACJPDP(x) ((x) << S_ACJPDP)
37943 #define F_ACJPDP V_ACJPDP(1U)
37946 #define V_ACJPDN(x) ((x) << S_ACJPDN)
37947 #define F_ACJPDN V_ACJPDN(1U)
37950 #define V_LSSDT(x) ((x) << S_LSSDT)
37951 #define F_LSSDT V_LSSDT(1U)
37954 #define V_MTHOLD(x) ((x) << S_MTHOLD)
37955 #define F_MTHOLD V_MTHOLD(1U)
37957 #define A_MAC_PORT_RX_LINKB_RECEIVER_CONFIGURATION_MODE 0x3300
37958 #define A_MAC_PORT_RX_LINKB_RECEIVER_TEST_CONTROL 0x3304
37959 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_CONTROL 0x3308
37960 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_OFFSET_CONTROL 0x330c
37961 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_1 0x3310
37962 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_POSITION_2 0x3314
37963 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3318
37964 #define A_MAC_PORT_RX_LINKB_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x331c
37965 #define A_MAC_PORT_RX_LINKB_DFE_CONTROL 0x3320
37966 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_1 0x3324
37967 #define A_MAC_PORT_RX_LINKB_DFE_SAMPLE_SNAPSHOT_2 0x3328
37968 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_1 0x332c
37969 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_2 0x3330
37970 #define A_MAC_PORT_RX_LINKB_RECEIVER_VGA_CONTROL_3 0x3334
37971 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_1 0x3338
37972 #define A_MAC_PORT_RX_LINKB_RECEIVER_DQCC_CONTROL_3 0x3340
37973 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACAP_AND_DACAN 0x3348
37974 #define A_MAC_PORT_RX_LINKB_RECEIVER_DACA_MIN_AND_DACAZ 0x334c
37975 #define A_MAC_PORT_RX_LINKB_RECEIVER_ADAC_CONTROL 0x3350
37976 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x335c
37977 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3360
37978 #define A_MAC_PORT_RX_LINKB_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3364
37979 #define A_MAC_PORT_RX_LINKB_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3370
37980 #define A_MAC_PORT_RX_LINKB_DYNAMIC_DATA_CENTERING_DDC 0x3374
37981 #define A_MAC_PORT_RX_LINKB_RECEIVER_INTERNAL_STATUS 0x3378
37982 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_1 0x337c
37983 #define A_MAC_PORT_RX_LINKB_DFE_FUNCTION_CONTROL_2 0x3380
37984 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN1_EVN2 0x3384
37985 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD1_ODD2 0x3388
37986 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_EVN3_EVN4 0x338c
37987 #define A_MAC_PORT_RX_LINKB_DFE_OFFSET_ODD3_ODD4 0x3390
37988 #define A_MAC_PORT_RX_LINKB_DFE_E0_AND_E1_OFFSET 0x3394
37989 #define A_MAC_PORT_RX_LINKB_RECEIVER_LOFF_CONTROL 0x3398
37990 #define A_MAC_PORT_RX_LINKB_RECEIVER_SIGDET_CONTROL 0x339c
37991 #define A_MAC_PORT_RX_LINKB_RECEIVER_ANALOG_CONTROL_SWITCH 0x33a0
37992 #define A_MAC_PORT_RX_LINKB_INTEGRATOR_DAC_OFFSET 0x33a4
37993 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_CONTROL 0x33a8
37994 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS 0x33ac
37995 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_ERROR_COUNT 0x33b0
37996 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x33b4
37997 #define A_MAC_PORT_RX_LINKB_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x33b8
37998 #define A_MAC_PORT_RX_LINKB_DFE_TAP_ENABLE 0x33c0
37999 #define A_MAC_PORT_RX_LINKB_DFE_H1 0x33c4
38000 #define A_MAC_PORT_RX_LINKB_DFE_H2 0x33c8
38001 #define A_MAC_PORT_RX_LINKB_DFE_H3 0x33cc
38002 #define A_MAC_PORT_RX_LINKB_DFE_H4 0x33d0
38003 #define A_MAC_PORT_RX_LINKB_DFE_H5 0x33d4
38004 #define A_MAC_PORT_RX_LINKB_DFE_H6_AND_H7 0x33d8
38005 #define A_MAC_PORT_RX_LINKB_DFE_H8_AND_H9 0x33dc
38006 #define A_MAC_PORT_RX_LINKB_DFE_H10_AND_H11 0x33e0
38007 #define A_MAC_PORT_RX_LINKB_DFE_H12 0x33e4
38008 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_2 0x33f8
38009 #define A_MAC_PORT_RX_LINKB_RECEIVER_MACRO_TEST_CONTROL_1 0x33fc
38010 #define A_MAC_PORT_TX_LINKC_TRANSMIT_CONFIGURATION_MODE 0x3400
38011 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TEST_CONTROL 0x3404
38012 #define A_MAC_PORT_TX_LINKC_TRANSMIT_COEFFICIENT_CONTROL 0x3408
38013 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_MODE_CONTROL 0x340c
38014 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3410
38015 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3414
38016 #define A_MAC_PORT_TX_LINKC_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3418
38017 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x341c
38018 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT 0x3420
38019 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT 0x3424
38020 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT 0x3428
38021 #define A_MAC_PORT_TX_LINKC_TRANSMIT_AMPLITUDE 0x3430
38022 #define A_MAC_PORT_TX_LINKC_TRANSMIT_POLARITY 0x3434
38023 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3438
38024 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x343c
38025 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3440
38026 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3444
38027 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3448
38028 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3460
38029 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3464
38030 #define A_MAC_PORT_TX_LINKC_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3468
38031 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3470
38032 #define A_MAC_PORT_TX_LINKC_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3474
38033 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3478
38034 #define A_MAC_PORT_TX_LINKC_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x347c
38035 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3480
38036 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3484
38037 #define A_MAC_PORT_TX_LINKC_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3488
38038 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_CONTROL 0x348c
38039 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_OVERRIDE 0x3490
38040 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_APPLIED 0x3494
38041 #define A_MAC_PORT_TX_LINKC_TRANSMIT_DCC_TIME_OUT 0x3498
38042 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AZ_CONTROL 0x349c
38043 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_4 0x34f0
38044 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_3 0x34f4
38045 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_2 0x34f8
38046 #define A_MAC_PORT_TX_LINKC_TRANSMIT_MACRO_TEST_CONTROL_1 0x34fc
38047 #define A_MAC_PORT_TX_LINKD_TRANSMIT_CONFIGURATION_MODE 0x3500
38048 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TEST_CONTROL 0x3504
38049 #define A_MAC_PORT_TX_LINKD_TRANSMIT_COEFFICIENT_CONTROL 0x3508
38050 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_MODE_CONTROL 0x350c
38051 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3510
38052 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3514
38053 #define A_MAC_PORT_TX_LINKD_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3518
38054 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x351c
38055 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT 0x3520
38056 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT 0x3524
38057 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT 0x3528
38058 #define A_MAC_PORT_TX_LINKD_TRANSMIT_AMPLITUDE 0x3530
38059 #define A_MAC_PORT_TX_LINKD_TRANSMIT_POLARITY 0x3534
38060 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3538
38061 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x353c
38062 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3540
38063 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3544
38064 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3548
38065 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3560
38066 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3564
38067 #define A_MAC_PORT_TX_LINKD_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3568
38068 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3570
38069 #define A_MAC_PORT_TX_LINKD_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3574
38070 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3578
38071 #define A_MAC_PORT_TX_LINKD_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x357c
38072 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3580
38073 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3584
38074 #define A_MAC_PORT_TX_LINKD_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3588
38075 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_CONTROL 0x358c
38076 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_OVERRIDE 0x3590
38077 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_APPLIED 0x3594
38078 #define A_MAC_PORT_TX_LINKD_TRANSMIT_DCC_TIME_OUT 0x3598
38079 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AZ_CONTROL 0x359c
38080 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_4 0x35f0
38081 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_3 0x35f4
38082 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_2 0x35f8
38083 #define A_MAC_PORT_TX_LINKD_TRANSMIT_MACRO_TEST_CONTROL_1 0x35fc
38084 #define A_MAC_PORT_RX_LINKC_RECEIVER_CONFIGURATION_MODE 0x3600
38085 #define A_MAC_PORT_RX_LINKC_RECEIVER_TEST_CONTROL 0x3604
38086 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_CONTROL 0x3608
38087 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_OFFSET_CONTROL 0x360c
38088 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_1 0x3610
38089 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_POSITION_2 0x3614
38090 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3618
38091 #define A_MAC_PORT_RX_LINKC_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x361c
38092 #define A_MAC_PORT_RX_LINKC_DFE_CONTROL 0x3620
38093 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_1 0x3624
38094 #define A_MAC_PORT_RX_LINKC_DFE_SAMPLE_SNAPSHOT_2 0x3628
38095 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_1 0x362c
38096 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_2 0x3630
38097 #define A_MAC_PORT_RX_LINKC_RECEIVER_VGA_CONTROL_3 0x3634
38098 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_1 0x3638
38099 #define A_MAC_PORT_RX_LINKC_RECEIVER_DQCC_CONTROL_3 0x3640
38100 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACAP_AND_DACAN 0x3648
38101 #define A_MAC_PORT_RX_LINKC_RECEIVER_DACA_MIN_AND_DACAZ 0x364c
38102 #define A_MAC_PORT_RX_LINKC_RECEIVER_ADAC_CONTROL 0x3650
38103 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x365c
38104 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3660
38105 #define A_MAC_PORT_RX_LINKC_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3664
38106 #define A_MAC_PORT_RX_LINKC_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3670
38107 #define A_MAC_PORT_RX_LINKC_DYNAMIC_DATA_CENTERING_DDC 0x3674
38108 #define A_MAC_PORT_RX_LINKC_RECEIVER_INTERNAL_STATUS 0x3678
38109 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_1 0x367c
38110 #define A_MAC_PORT_RX_LINKC_DFE_FUNCTION_CONTROL_2 0x3680
38111 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN1_EVN2 0x3684
38112 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD1_ODD2 0x3688
38113 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_EVN3_EVN4 0x368c
38114 #define A_MAC_PORT_RX_LINKC_DFE_OFFSET_ODD3_ODD4 0x3690
38115 #define A_MAC_PORT_RX_LINKC_DFE_E0_AND_E1_OFFSET 0x3694
38116 #define A_MAC_PORT_RX_LINKC_RECEIVER_LOFF_CONTROL 0x3698
38117 #define A_MAC_PORT_RX_LINKC_RECEIVER_SIGDET_CONTROL 0x369c
38118 #define A_MAC_PORT_RX_LINKC_RECEIVER_ANALOG_CONTROL_SWITCH 0x36a0
38119 #define A_MAC_PORT_RX_LINKC_INTEGRATOR_DAC_OFFSET 0x36a4
38120 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_CONTROL 0x36a8
38121 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS 0x36ac
38122 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_ERROR_COUNT 0x36b0
38123 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x36b4
38124 #define A_MAC_PORT_RX_LINKC_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x36b8
38125 #define A_MAC_PORT_RX_LINKC_DFE_TAP_ENABLE 0x36c0
38126 #define A_MAC_PORT_RX_LINKC_DFE_H1 0x36c4
38127 #define A_MAC_PORT_RX_LINKC_DFE_H2 0x36c8
38128 #define A_MAC_PORT_RX_LINKC_DFE_H3 0x36cc
38129 #define A_MAC_PORT_RX_LINKC_DFE_H4 0x36d0
38130 #define A_MAC_PORT_RX_LINKC_DFE_H5 0x36d4
38131 #define A_MAC_PORT_RX_LINKC_DFE_H6_AND_H7 0x36d8
38132 #define A_MAC_PORT_RX_LINKC_DFE_H8_AND_H9 0x36dc
38133 #define A_MAC_PORT_RX_LINKC_DFE_H10_AND_H11 0x36e0
38134 #define A_MAC_PORT_RX_LINKC_DFE_H12 0x36e4
38135 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_2 0x36f8
38136 #define A_MAC_PORT_RX_LINKC_RECEIVER_MACRO_TEST_CONTROL_1 0x36fc
38137 #define A_MAC_PORT_RX_LINKD_RECEIVER_CONFIGURATION_MODE 0x3700
38138 #define A_MAC_PORT_RX_LINKD_RECEIVER_TEST_CONTROL 0x3704
38139 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_CONTROL 0x3708
38140 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_OFFSET_CONTROL 0x370c
38141 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_1 0x3710
38142 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_POSITION_2 0x3714
38143 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3718
38144 #define A_MAC_PORT_RX_LINKD_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x371c
38145 #define A_MAC_PORT_RX_LINKD_DFE_CONTROL 0x3720
38146 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_1 0x3724
38147 #define A_MAC_PORT_RX_LINKD_DFE_SAMPLE_SNAPSHOT_2 0x3728
38148 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_1 0x372c
38149 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_2 0x3730
38150 #define A_MAC_PORT_RX_LINKD_RECEIVER_VGA_CONTROL_3 0x3734
38151 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_1 0x3738
38152 #define A_MAC_PORT_RX_LINKD_RECEIVER_DQCC_CONTROL_3 0x3740
38153 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACAP_AND_DACAN 0x3748
38154 #define A_MAC_PORT_RX_LINKD_RECEIVER_DACA_MIN_AND_DACAZ 0x374c
38155 #define A_MAC_PORT_RX_LINKD_RECEIVER_ADAC_CONTROL 0x3750
38156 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x375c
38157 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3760
38158 #define A_MAC_PORT_RX_LINKD_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3764
38159 #define A_MAC_PORT_RX_LINKD_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3770
38160 #define A_MAC_PORT_RX_LINKD_DYNAMIC_DATA_CENTERING_DDC 0x3774
38161 #define A_MAC_PORT_RX_LINKD_RECEIVER_INTERNAL_STATUS 0x3778
38162 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_1 0x377c
38163 #define A_MAC_PORT_RX_LINKD_DFE_FUNCTION_CONTROL_2 0x3780
38164 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN1_EVN2 0x3784
38165 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD1_ODD2 0x3788
38166 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_EVN3_EVN4 0x378c
38167 #define A_MAC_PORT_RX_LINKD_DFE_OFFSET_ODD3_ODD4 0x3790
38168 #define A_MAC_PORT_RX_LINKD_DFE_E0_AND_E1_OFFSET 0x3794
38169 #define A_MAC_PORT_RX_LINKD_RECEIVER_LOFF_CONTROL 0x3798
38170 #define A_MAC_PORT_RX_LINKD_RECEIVER_SIGDET_CONTROL 0x379c
38171 #define A_MAC_PORT_RX_LINKD_RECEIVER_ANALOG_CONTROL_SWITCH 0x37a0
38172 #define A_MAC_PORT_RX_LINKD_INTEGRATOR_DAC_OFFSET 0x37a4
38173 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_CONTROL 0x37a8
38174 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS 0x37ac
38175 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_ERROR_COUNT 0x37b0
38176 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x37b4
38177 #define A_MAC_PORT_RX_LINKD_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x37b8
38178 #define A_MAC_PORT_RX_LINKD_DFE_TAP_ENABLE 0x37c0
38179 #define A_MAC_PORT_RX_LINKD_DFE_H1 0x37c4
38180 #define A_MAC_PORT_RX_LINKD_DFE_H2 0x37c8
38181 #define A_MAC_PORT_RX_LINKD_DFE_H3 0x37cc
38182 #define A_MAC_PORT_RX_LINKD_DFE_H4 0x37d0
38183 #define A_MAC_PORT_RX_LINKD_DFE_H5 0x37d4
38184 #define A_MAC_PORT_RX_LINKD_DFE_H6_AND_H7 0x37d8
38185 #define A_MAC_PORT_RX_LINKD_DFE_H8_AND_H9 0x37dc
38186 #define A_MAC_PORT_RX_LINKD_DFE_H10_AND_H11 0x37e0
38187 #define A_MAC_PORT_RX_LINKD_DFE_H12 0x37e4
38188 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_2 0x37f8
38189 #define A_MAC_PORT_RX_LINKD_RECEIVER_MACRO_TEST_CONTROL_1 0x37fc
38190 #define A_MAC_PORT_ANALOG_TEST_MUX 0x3814
38191 #define A_MAC_PORT_BANDGAP_CONTROL 0x382c
38193 #define S_T5BGCTL 0
38194 #define M_T5BGCTL 0xfU
38195 #define V_T5BGCTL(x) ((x) << S_T5BGCTL)
38196 #define G_T5BGCTL(x) (((x) >> S_T5BGCTL) & M_T5BGCTL)
38198 #define A_MAC_PORT_RESISTOR_CALIBRATION_CONTROL 0x3880
38201 #define V_RCCTL1(x) ((x) << S_RCCTL1)
38202 #define F_RCCTL1 V_RCCTL1(1U)
38205 #define V_RCCTL0(x) ((x) << S_RCCTL0)
38206 #define F_RCCTL0 V_RCCTL0(1U)
38209 #define V_RCAMP1(x) ((x) << S_RCAMP1)
38210 #define F_RCAMP1 V_RCAMP1(1U)
38213 #define V_RCAMP0(x) ((x) << S_RCAMP0)
38214 #define F_RCAMP0 V_RCAMP0(1U)
38216 #define S_RCAMPEN 1
38217 #define V_RCAMPEN(x) ((x) << S_RCAMPEN)
38218 #define F_RCAMPEN V_RCAMPEN(1U)
38221 #define V_RCRST(x) ((x) << S_RCRST)
38222 #define F_RCRST V_RCRST(1U)
38224 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_1 0x3884
38227 #define V_RCERR(x) ((x) << S_RCERR)
38228 #define F_RCERR V_RCERR(1U)
38231 #define V_RCCOMP(x) ((x) << S_RCCOMP)
38232 #define F_RCCOMP V_RCCOMP(1U)
38234 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_2 0x3888
38236 #define S_RESREG2 0
38237 #define M_RESREG2 0xffU
38238 #define V_RESREG2(x) ((x) << S_RESREG2)
38239 #define G_RESREG2(x) (((x) >> S_RESREG2) & M_RESREG2)
38241 #define A_MAC_PORT_RESISTOR_CALIBRATION_STATUS_3 0x388c
38243 #define S_RESREG3 0
38244 #define M_RESREG3 0xffU
38245 #define V_RESREG3(x) ((x) << S_RESREG3)
38246 #define G_RESREG3(x) (((x) >> S_RESREG3) & M_RESREG3)
38248 #define A_MAC_PORT_MACRO_TEST_CONTROL_6 0x38e8
38251 #define V_LBIST(x) ((x) << S_LBIST)
38252 #define F_LBIST V_LBIST(1U)
38254 #define S_LOGICTEST 6
38255 #define V_LOGICTEST(x) ((x) << S_LOGICTEST)
38256 #define F_LOGICTEST V_LOGICTEST(1U)
38259 #define V_MAVDHI(x) ((x) << S_MAVDHI)
38260 #define F_MAVDHI V_MAVDHI(1U)
38263 #define V_AUXEN(x) ((x) << S_AUXEN)
38264 #define F_AUXEN V_AUXEN(1U)
38267 #define V_JTAGMD(x) ((x) << S_JTAGMD)
38268 #define F_JTAGMD V_JTAGMD(1U)
38270 #define S_RXACMODE 2
38271 #define V_RXACMODE(x) ((x) << S_RXACMODE)
38272 #define F_RXACMODE V_RXACMODE(1U)
38274 #define S_HSSACJPC 1
38275 #define V_HSSACJPC(x) ((x) << S_HSSACJPC)
38276 #define F_HSSACJPC V_HSSACJPC(1U)
38278 #define S_HSSACJAC 0
38279 #define V_HSSACJAC(x) ((x) << S_HSSACJAC)
38280 #define F_HSSACJAC V_HSSACJAC(1U)
38282 #define A_MAC_PORT_MACRO_TEST_CONTROL_5 0x38ec
38284 #define S_REFVALIDD 6
38285 #define V_REFVALIDD(x) ((x) << S_REFVALIDD)
38286 #define F_REFVALIDD V_REFVALIDD(1U)
38288 #define S_REFVALIDC 5
38289 #define V_REFVALIDC(x) ((x) << S_REFVALIDC)
38290 #define F_REFVALIDC V_REFVALIDC(1U)
38292 #define S_REFVALIDB 4
38293 #define V_REFVALIDB(x) ((x) << S_REFVALIDB)
38294 #define F_REFVALIDB V_REFVALIDB(1U)
38296 #define S_REFVALIDA 3
38297 #define V_REFVALIDA(x) ((x) << S_REFVALIDA)
38298 #define F_REFVALIDA V_REFVALIDA(1U)
38300 #define S_REFSELRESET 2
38301 #define V_REFSELRESET(x) ((x) << S_REFSELRESET)
38302 #define F_REFSELRESET V_REFSELRESET(1U)
38304 #define S_SOFTRESET 1
38305 #define V_SOFTRESET(x) ((x) << S_SOFTRESET)
38306 #define F_SOFTRESET V_SOFTRESET(1U)
38308 #define S_MACROTEST 0
38309 #define V_MACROTEST(x) ((x) << S_MACROTEST)
38310 #define F_MACROTEST V_MACROTEST(1U)
38312 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_CONFIGURATION_MODE 0x3900
38313 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TEST_CONTROL 0x3904
38314 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_COEFFICIENT_CONTROL 0x3908
38315 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_MODE_CONTROL 0x390c
38316 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DRIVER_OVERRIDE_CONTROL 0x3910
38317 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_ROTATOR_OVERRIDE 0x3914
38318 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_IMPEDANCE_CALIBRATION_OVERRIDE 0x3918
38319 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCLK_DRIFT_TOLERANCE 0x391c
38320 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT 0x3920
38321 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT 0x3924
38322 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT 0x3928
38323 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_AMPLITUDE 0x3930
38324 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_POLARITY 0x3934
38325 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_COMMAND 0x3938
38326 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_ADAPTIVE_EQUALIZATION_STATUS 0x393c
38327 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_OVERRIDE 0x3940
38328 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_OVERRIDE 0x3944
38329 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_OVERRIDE 0x3948
38330 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_0_COEFFICIENT_APPLIED 0x3960
38331 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_1_COEFFICIENT_APPLIED 0x3964
38332 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_TAP_2_COEFFICIENT_APPLIED 0x3968
38333 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_1 0x3970
38334 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_SEGMENT_DISABLE_APPLIED_2 0x3974
38335 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_DATA 0x3978
38336 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_EXTENDED_ADDRESS_ADDR 0x397c
38337 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_1_0 0x3980
38338 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTES_3_2 0x3984
38339 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_PATTERN_BUFFER_BYTE_4 0x3988
38340 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_CONTROL 0x398c
38341 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_OVERRIDE 0x3990
38342 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_APPLIED 0x3994
38343 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_DCC_TIME_OUT 0x3998
38344 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AZ_CONTROL 0x399c
38345 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_4 0x39f0
38346 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_3 0x39f4
38347 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_2 0x39f8
38348 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_MACRO_TEST_CONTROL_1 0x39fc
38349 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_CONFIGURATION_MODE 0x3a00
38350 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_TEST_CONTROL 0x3a04
38351 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_CONTROL 0x3a08
38352 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_OFFSET_CONTROL 0x3a0c
38353 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_1 0x3a10
38354 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_POSITION_2 0x3a14
38355 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_1 0x3a18
38356 #define A_MAC_PORT_RX_LINK_BCST_PHASE_ROTATOR_STATIC_PHASE_OFFSET_2 0x3a1c
38357 #define A_MAC_PORT_RX_LINK_BCST_DFE_CONTROL 0x3a20
38358 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_1 0x3a24
38359 #define A_MAC_PORT_RX_LINK_BCST_DFE_SAMPLE_SNAPSHOT_2 0x3a28
38360 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_1 0x3a2c
38361 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_2 0x3a30
38362 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_VGA_CONTROL_3 0x3a34
38363 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_1 0x3a38
38364 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DQCC_CONTROL_3 0x3a40
38365 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACAP_AND_DACAN 0x3a48
38366 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_DACA_MIN_AND_DACAZ 0x3a4c
38367 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ADAC_CONTROL 0x3a50
38368 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD2_EVN2 0x3a5c
38369 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD3_EVN3 0x3a60
38370 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1_LOCAL_OFFSET_ODD4_EVN4 0x3a64
38371 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_AMPLITUDE_CENTERING_DAC_AND_DYNAMIC_PEAKING_CONTROL_DPC 0x3a70
38372 #define A_MAC_PORT_RX_LINK_BCST_DYNAMIC_DATA_CENTERING_DDC 0x3a74
38373 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_INTERNAL_STATUS 0x3a78
38374 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_1 0x3a7c
38375 #define A_MAC_PORT_RX_LINK_BCST_DFE_FUNCTION_CONTROL_2 0x3a80
38376 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN1_EVN2 0x3a84
38377 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD1_ODD2 0x3a88
38378 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_EVN3_EVN4 0x3a8c
38379 #define A_MAC_PORT_RX_LINK_BCST_DFE_OFFSET_ODD3_ODD4 0x3a90
38380 #define A_MAC_PORT_RX_LINK_BCST_DFE_E0_AND_E1_OFFSET 0x3a94
38381 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_LOFF_CONTROL 0x3a98
38382 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_SIGDET_CONTROL 0x3a9c
38383 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_ANALOG_CONTROL_SWITCH 0x3aa0
38384 #define A_MAC_PORT_RX_LINK_BCST_INTEGRATOR_DAC_OFFSET 0x3aa4
38385 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_CONTROL 0x3aa8
38386 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS 0x3aac
38387 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_ERROR_COUNT 0x3ab0
38388 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PDF_EYE_COUNT 0x3ab4
38389 #define A_MAC_PORT_RX_LINK_BCST_DIGITAL_EYE_METRICS_PATTERN_LENGTH 0x3ab8
38390 #define A_MAC_PORT_RX_LINK_BCST_DFE_TAP_ENABLE 0x3ac0
38391 #define A_MAC_PORT_RX_LINK_BCST_DFE_H1 0x3ac4
38392 #define A_MAC_PORT_RX_LINK_BCST_DFE_H2 0x3ac8
38393 #define A_MAC_PORT_RX_LINK_BCST_DFE_H3 0x3acc
38394 #define A_MAC_PORT_RX_LINK_BCST_DFE_H4 0x3ad0
38395 #define A_MAC_PORT_RX_LINK_BCST_DFE_H5 0x3ad4
38396 #define A_MAC_PORT_RX_LINK_BCST_DFE_H6_AND_H7 0x3ad8
38397 #define A_MAC_PORT_RX_LINK_BCST_DFE_H8_AND_H9 0x3adc
38398 #define A_MAC_PORT_RX_LINK_BCST_DFE_H10_AND_H11 0x3ae0
38399 #define A_MAC_PORT_RX_LINK_BCST_DFE_H12 0x3ae4
38400 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_2 0x3af8
38401 #define A_MAC_PORT_RX_LINK_BCST_RECEIVER_MACRO_TEST_CONTROL_1 0x3afc
38402 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_0 0x3b00
38403 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_1 0x3b04
38404 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_2 0x3b08
38405 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_3 0x3b0c
38406 #define A_MAC_PORT_PLLA_VCO_COARSE_CALIBRATION_4 0x3b10
38407 #define A_MAC_PORT_PLLA_CHARGE_PUMP_CONTROL 0x3b28
38409 #define S_T5CPISEL 0
38410 #define M_T5CPISEL 0x7U
38411 #define V_T5CPISEL(x) ((x) << S_T5CPISEL)
38412 #define G_T5CPISEL(x) (((x) >> S_T5CPISEL) & M_T5CPISEL)
38414 #define A_MAC_PORT_PLLA_PCLK_CONTROL 0x3b3c
38417 #define M_SPEDIV 0x1fU
38418 #define V_SPEDIV(x) ((x) << S_SPEDIV)
38419 #define G_SPEDIV(x) (((x) >> S_SPEDIV) & M_SPEDIV)
38422 #define M_PCKSEL 0x7U
38423 #define V_PCKSEL(x) ((x) << S_PCKSEL)
38424 #define G_PCKSEL(x) (((x) >> S_PCKSEL) & M_PCKSEL)
38426 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_CONTROL 0x3b40
38429 #define V_EMIL(x) ((x) << S_EMIL)
38430 #define F_EMIL V_EMIL(1U)
38433 #define V_EMID(x) ((x) << S_EMID)
38434 #define F_EMID V_EMID(1U)
38437 #define V_EMIS(x) ((x) << S_EMIS)
38438 #define F_EMIS V_EMIS(1U)
38440 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_1 0x3b44
38443 #define M_EMIL1 0xffU
38444 #define V_EMIL1(x) ((x) << S_EMIL1)
38445 #define G_EMIL1(x) (((x) >> S_EMIL1) & M_EMIL1)
38447 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_2 0x3b48
38450 #define M_EMIL2 0xffU
38451 #define V_EMIL2(x) ((x) << S_EMIL2)
38452 #define G_EMIL2(x) (((x) >> S_EMIL2) & M_EMIL2)
38454 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_3 0x3b4c
38457 #define M_EMIL3 0xffU
38458 #define V_EMIL3(x) ((x) << S_EMIL3)
38459 #define G_EMIL3(x) (((x) >> S_EMIL3) & M_EMIL3)
38461 #define A_MAC_PORT_PLLA_EYE_METRICS_INTERVAL_LIMIT_4 0x3b50
38464 #define M_EMIL4 0xffU
38465 #define V_EMIL4(x) ((x) << S_EMIL4)
38466 #define G_EMIL4(x) (((x) >> S_EMIL4) & M_EMIL4)
38468 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_4 0x3bf0
38471 #define M_VBST 0x7U
38472 #define V_VBST(x) ((x) << S_VBST)
38473 #define G_VBST(x) (((x) >> S_VBST) & M_VBST)
38475 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_3 0x3bf4
38478 #define V_RESYNC(x) ((x) << S_RESYNC)
38479 #define F_RESYNC V_RESYNC(1U)
38481 #define S_RXCLKSEL 5
38482 #define V_RXCLKSEL(x) ((x) << S_RXCLKSEL)
38483 #define F_RXCLKSEL V_RXCLKSEL(1U)
38485 #define S_FRCBAND 4
38486 #define V_FRCBAND(x) ((x) << S_FRCBAND)
38487 #define F_FRCBAND V_FRCBAND(1U)
38490 #define V_PLLBYP(x) ((x) << S_PLLBYP)
38491 #define F_PLLBYP V_PLLBYP(1U)
38494 #define V_PDWNP(x) ((x) << S_PDWNP)
38495 #define F_PDWNP V_PDWNP(1U)
38498 #define V_VCOSEL(x) ((x) << S_VCOSEL)
38499 #define F_VCOSEL V_VCOSEL(1U)
38501 #define S_DIVSEL8 0
38502 #define V_DIVSEL8(x) ((x) << S_DIVSEL8)
38503 #define F_DIVSEL8 V_DIVSEL8(1U)
38505 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_2 0x3bf8
38508 #define M_DIVSEL 0xffU
38509 #define V_DIVSEL(x) ((x) << S_DIVSEL)
38510 #define G_DIVSEL(x) (((x) >> S_DIVSEL) & M_DIVSEL)
38512 #define A_MAC_PORT_PLLA_MACRO_TEST_CONTROL_1 0x3bfc
38515 #define M_CONFIG 0xffU
38516 #define V_CONFIG(x) ((x) << S_CONFIG)
38517 #define G_CONFIG(x) (((x) >> S_CONFIG) & M_CONFIG)
38519 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_0 0x3c00
38520 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_1 0x3c04
38521 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_2 0x3c08
38522 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_3 0x3c0c
38523 #define A_MAC_PORT_PLLB_VCO_COARSE_CALIBRATION_4 0x3c10
38524 #define A_MAC_PORT_PLLB_CHARGE_PUMP_CONTROL 0x3c28
38525 #define A_MAC_PORT_PLLB_PCLK_CONTROL 0x3c3c
38526 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_CONTROL 0x3c40
38527 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_1 0x3c44
38528 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_2 0x3c48
38529 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_3 0x3c4c
38530 #define A_MAC_PORT_PLLB_EYE_METRICS_INTERVAL_LIMIT_4 0x3c50
38531 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_4 0x3cf0
38532 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_3 0x3cf4
38533 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_2 0x3cf8
38534 #define A_MAC_PORT_PLLB_MACRO_TEST_CONTROL_1 0x3cfc
38535 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
38538 #define M_STEP 0x7U
38539 #define V_STEP(x) ((x) << S_STEP)
38540 #define G_STEP(x) (((x) >> S_STEP) & M_STEP)
38542 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
38545 #define M_C0INIT 0x1fU
38546 #define V_C0INIT(x) ((x) << S_C0INIT)
38547 #define G_C0INIT(x) (((x) >> S_C0INIT) & M_C0INIT)
38549 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
38552 #define M_C0MAX 0x1fU
38553 #define V_C0MAX(x) ((x) << S_C0MAX)
38554 #define G_C0MAX(x) (((x) >> S_C0MAX) & M_C0MAX)
38557 #define M_C0MIN 0x1fU
38558 #define V_C0MIN(x) ((x) << S_C0MIN)
38559 #define G_C0MIN(x) (((x) >> S_C0MIN) & M_C0MIN)
38561 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
38564 #define M_C1INIT 0x7fU
38565 #define V_C1INIT(x) ((x) << S_C1INIT)
38566 #define G_C1INIT(x) (((x) >> S_C1INIT) & M_C1INIT)
38568 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
38571 #define M_C1MAX 0x7fU
38572 #define V_C1MAX(x) ((x) << S_C1MAX)
38573 #define G_C1MAX(x) (((x) >> S_C1MAX) & M_C1MAX)
38576 #define M_C1MIN 0x7fU
38577 #define V_C1MIN(x) ((x) << S_C1MIN)
38578 #define G_C1MIN(x) (((x) >> S_C1MIN) & M_C1MIN)
38580 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
38583 #define M_C2INIT 0x3fU
38584 #define V_C2INIT(x) ((x) << S_C2INIT)
38585 #define G_C2INIT(x) (((x) >> S_C2INIT) & M_C2INIT)
38587 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
38590 #define M_C2MAX 0x3fU
38591 #define V_C2MAX(x) ((x) << S_C2MAX)
38592 #define G_C2MAX(x) (((x) >> S_C2MAX) & M_C2MAX)
38595 #define M_C2MIN 0x3fU
38596 #define V_C2MIN(x) ((x) << S_C2MIN)
38597 #define G_C2MIN(x) (((x) >> S_C2MIN) & M_C2MIN)
38599 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
38602 #define M_VMMAX 0x7fU
38603 #define V_VMMAX(x) ((x) << S_VMMAX)
38604 #define G_VMMAX(x) (((x) >> S_VMMAX) & M_VMMAX)
38606 #define A_MAC_PORT_TX_LINKA_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
38609 #define M_V2MIN 0x7fU
38610 #define V_V2MIN(x) ((x) << S_V2MIN)
38611 #define G_V2MIN(x) (((x) >> S_V2MIN) & M_V2MIN)
38613 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
38614 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
38615 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
38616 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
38617 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
38618 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
38619 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
38620 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
38621 #define A_MAC_PORT_TX_LINKB_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
38622 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
38623 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
38624 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
38625 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
38626 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
38627 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
38628 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
38629 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
38630 #define A_MAC_PORT_TX_LINKC_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
38631 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
38632 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
38633 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
38634 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
38635 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
38636 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
38637 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
38638 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
38639 #define A_MAC_PORT_TX_LINKD_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
38640 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_STEP_SIZE_EXTENDED 0x0
38641 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_INIT_EXTENDED 0x8
38642 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C0_LIMIT_EXTENDED 0x10
38643 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_INIT_EXTENDED 0x18
38644 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C1_LIMIT_EXTENDED 0x20
38645 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_INIT_EXTENDED 0x28
38646 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_C2_LIMIT_EXTENDED 0x30
38647 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_VM_LIMIT_EXTENDED 0x38
38648 #define A_MAC_PORT_TX_LINK_BCST_TRANSMIT_802_3AP_V2_LIMIT_EXTENDED 0x40
38650 /* registers for module MC_0 */
38651 #define MC_0_BASE_ADDR 0x40000
38653 #define A_MC_UPCTL_SCFG 0x40000
38655 #define S_BBFLAGS_TIMING 8
38656 #define M_BBFLAGS_TIMING 0xfU
38657 #define V_BBFLAGS_TIMING(x) ((x) << S_BBFLAGS_TIMING)
38658 #define G_BBFLAGS_TIMING(x) (((x) >> S_BBFLAGS_TIMING) & M_BBFLAGS_TIMING)
38660 #define S_NFIFO_NIF1_DIS 6
38661 #define V_NFIFO_NIF1_DIS(x) ((x) << S_NFIFO_NIF1_DIS)
38662 #define F_NFIFO_NIF1_DIS V_NFIFO_NIF1_DIS(1U)
38664 #define A_MC_UPCTL_SCTL 0x40004
38665 #define A_MC_UPCTL_STAT 0x40008
38667 #define S_LP_TRIG 4
38668 #define M_LP_TRIG 0x7U
38669 #define V_LP_TRIG(x) ((x) << S_LP_TRIG)
38670 #define G_LP_TRIG(x) (((x) >> S_LP_TRIG) & M_LP_TRIG)
38672 #define A_MC_UPCTL_INTRSTAT 0x4000c
38674 #define S_PARITY_INTR 1
38675 #define V_PARITY_INTR(x) ((x) << S_PARITY_INTR)
38676 #define F_PARITY_INTR V_PARITY_INTR(1U)
38678 #define S_ECC_INTR 0
38679 #define V_ECC_INTR(x) ((x) << S_ECC_INTR)
38680 #define F_ECC_INTR V_ECC_INTR(1U)
38682 #define A_MC_UPCTL_MCMD 0x40040
38684 #define S_CMD_OPCODE0 0
38685 #define M_CMD_OPCODE0 0xfU
38686 #define V_CMD_OPCODE0(x) ((x) << S_CMD_OPCODE0)
38687 #define G_CMD_OPCODE0(x) (((x) >> S_CMD_OPCODE0) & M_CMD_OPCODE0)
38689 #define A_MC_UPCTL_POWCTL 0x40044
38690 #define A_MC_UPCTL_POWSTAT 0x40048
38691 #define A_MC_UPCTL_CMDTSTAT 0x4004c
38693 #define S_CMD_TSTAT 0
38694 #define V_CMD_TSTAT(x) ((x) << S_CMD_TSTAT)
38695 #define F_CMD_TSTAT V_CMD_TSTAT(1U)
38697 #define A_MC_UPCTL_CMDTSTATEN 0x40050
38699 #define S_CMD_TSTAT_EN 0
38700 #define V_CMD_TSTAT_EN(x) ((x) << S_CMD_TSTAT_EN)
38701 #define F_CMD_TSTAT_EN V_CMD_TSTAT_EN(1U)
38703 #define A_MC_UPCTL_MRRCFG0 0x40060
38705 #define S_MRR_BYTE_SEL 0
38706 #define M_MRR_BYTE_SEL 0xfU
38707 #define V_MRR_BYTE_SEL(x) ((x) << S_MRR_BYTE_SEL)
38708 #define G_MRR_BYTE_SEL(x) (((x) >> S_MRR_BYTE_SEL) & M_MRR_BYTE_SEL)
38710 #define A_MC_UPCTL_MRRSTAT0 0x40064
38712 #define S_MRRSTAT_BEAT3 24
38713 #define M_MRRSTAT_BEAT3 0xffU
38714 #define V_MRRSTAT_BEAT3(x) ((x) << S_MRRSTAT_BEAT3)
38715 #define G_MRRSTAT_BEAT3(x) (((x) >> S_MRRSTAT_BEAT3) & M_MRRSTAT_BEAT3)
38717 #define S_MRRSTAT_BEAT2 16
38718 #define M_MRRSTAT_BEAT2 0xffU
38719 #define V_MRRSTAT_BEAT2(x) ((x) << S_MRRSTAT_BEAT2)
38720 #define G_MRRSTAT_BEAT2(x) (((x) >> S_MRRSTAT_BEAT2) & M_MRRSTAT_BEAT2)
38722 #define S_MRRSTAT_BEAT1 8
38723 #define M_MRRSTAT_BEAT1 0xffU
38724 #define V_MRRSTAT_BEAT1(x) ((x) << S_MRRSTAT_BEAT1)
38725 #define G_MRRSTAT_BEAT1(x) (((x) >> S_MRRSTAT_BEAT1) & M_MRRSTAT_BEAT1)
38727 #define S_MRRSTAT_BEAT0 0
38728 #define M_MRRSTAT_BEAT0 0xffU
38729 #define V_MRRSTAT_BEAT0(x) ((x) << S_MRRSTAT_BEAT0)
38730 #define G_MRRSTAT_BEAT0(x) (((x) >> S_MRRSTAT_BEAT0) & M_MRRSTAT_BEAT0)
38732 #define A_MC_UPCTL_MRRSTAT1 0x40068
38734 #define S_MRRSTAT_BEAT7 24
38735 #define M_MRRSTAT_BEAT7 0xffU
38736 #define V_MRRSTAT_BEAT7(x) ((x) << S_MRRSTAT_BEAT7)
38737 #define G_MRRSTAT_BEAT7(x) (((x) >> S_MRRSTAT_BEAT7) & M_MRRSTAT_BEAT7)
38739 #define S_MRRSTAT_BEAT6 16
38740 #define M_MRRSTAT_BEAT6 0xffU
38741 #define V_MRRSTAT_BEAT6(x) ((x) << S_MRRSTAT_BEAT6)
38742 #define G_MRRSTAT_BEAT6(x) (((x) >> S_MRRSTAT_BEAT6) & M_MRRSTAT_BEAT6)
38744 #define S_MRRSTAT_BEAT5 8
38745 #define M_MRRSTAT_BEAT5 0xffU
38746 #define V_MRRSTAT_BEAT5(x) ((x) << S_MRRSTAT_BEAT5)
38747 #define G_MRRSTAT_BEAT5(x) (((x) >> S_MRRSTAT_BEAT5) & M_MRRSTAT_BEAT5)
38749 #define S_MRRSTAT_BEAT4 0
38750 #define M_MRRSTAT_BEAT4 0xffU
38751 #define V_MRRSTAT_BEAT4(x) ((x) << S_MRRSTAT_BEAT4)
38752 #define G_MRRSTAT_BEAT4(x) (((x) >> S_MRRSTAT_BEAT4) & M_MRRSTAT_BEAT4)
38754 #define A_MC_UPCTL_MCFG1 0x4007c
38756 #define S_HW_EXIT_IDLE_EN 31
38757 #define V_HW_EXIT_IDLE_EN(x) ((x) << S_HW_EXIT_IDLE_EN)
38758 #define F_HW_EXIT_IDLE_EN V_HW_EXIT_IDLE_EN(1U)
38760 #define S_HW_IDLE 16
38761 #define M_HW_IDLE 0xffU
38762 #define V_HW_IDLE(x) ((x) << S_HW_IDLE)
38763 #define G_HW_IDLE(x) (((x) >> S_HW_IDLE) & M_HW_IDLE)
38765 #define S_SR_IDLE 0
38766 #define M_SR_IDLE 0xffU
38767 #define V_SR_IDLE(x) ((x) << S_SR_IDLE)
38768 #define G_SR_IDLE(x) (((x) >> S_SR_IDLE) & M_SR_IDLE)
38770 #define A_MC_UPCTL_MCFG 0x40080
38772 #define S_MDDR_LPDDR2_CLK_STOP_IDLE 24
38773 #define M_MDDR_LPDDR2_CLK_STOP_IDLE 0xffU
38774 #define V_MDDR_LPDDR2_CLK_STOP_IDLE(x) ((x) << S_MDDR_LPDDR2_CLK_STOP_IDLE)
38775 #define G_MDDR_LPDDR2_CLK_STOP_IDLE(x) (((x) >> S_MDDR_LPDDR2_CLK_STOP_IDLE) & M_MDDR_LPDDR2_CLK_STOP_IDLE)
38777 #define S_MDDR_LPDDR2_EN 22
38778 #define M_MDDR_LPDDR2_EN 0x3U
38779 #define V_MDDR_LPDDR2_EN(x) ((x) << S_MDDR_LPDDR2_EN)
38780 #define G_MDDR_LPDDR2_EN(x) (((x) >> S_MDDR_LPDDR2_EN) & M_MDDR_LPDDR2_EN)
38782 #define S_MDDR_LPDDR2_BL 20
38783 #define M_MDDR_LPDDR2_BL 0x3U
38784 #define V_MDDR_LPDDR2_BL(x) ((x) << S_MDDR_LPDDR2_BL)
38785 #define G_MDDR_LPDDR2_BL(x) (((x) >> S_MDDR_LPDDR2_BL) & M_MDDR_LPDDR2_BL)
38787 #define S_LPDDR2_S4 6
38788 #define V_LPDDR2_S4(x) ((x) << S_LPDDR2_S4)
38789 #define F_LPDDR2_S4 V_LPDDR2_S4(1U)
38791 #define S_STAGGER_CS 4
38792 #define V_STAGGER_CS(x) ((x) << S_STAGGER_CS)
38793 #define F_STAGGER_CS V_STAGGER_CS(1U)
38795 #define S_CKE_OR_EN 1
38796 #define V_CKE_OR_EN(x) ((x) << S_CKE_OR_EN)
38797 #define F_CKE_OR_EN V_CKE_OR_EN(1U)
38799 #define A_MC_UPCTL_PPCFG 0x40084
38800 #define A_MC_UPCTL_MSTAT 0x40088
38802 #define S_SELF_REFRESH 2
38803 #define V_SELF_REFRESH(x) ((x) << S_SELF_REFRESH)
38804 #define F_SELF_REFRESH V_SELF_REFRESH(1U)
38806 #define S_CLOCK_STOP 1
38807 #define V_CLOCK_STOP(x) ((x) << S_CLOCK_STOP)
38808 #define F_CLOCK_STOP V_CLOCK_STOP(1U)
38810 #define A_MC_UPCTL_LPDDR2ZQCFG 0x4008c
38812 #define S_ZQCL_OP 24
38813 #define M_ZQCL_OP 0xffU
38814 #define V_ZQCL_OP(x) ((x) << S_ZQCL_OP)
38815 #define G_ZQCL_OP(x) (((x) >> S_ZQCL_OP) & M_ZQCL_OP)
38817 #define S_ZQCL_MA 16
38818 #define M_ZQCL_MA 0xffU
38819 #define V_ZQCL_MA(x) ((x) << S_ZQCL_MA)
38820 #define G_ZQCL_MA(x) (((x) >> S_ZQCL_MA) & M_ZQCL_MA)
38822 #define S_ZQCS_OP 8
38823 #define M_ZQCS_OP 0xffU
38824 #define V_ZQCS_OP(x) ((x) << S_ZQCS_OP)
38825 #define G_ZQCS_OP(x) (((x) >> S_ZQCS_OP) & M_ZQCS_OP)
38827 #define S_ZQCS_MA 0
38828 #define M_ZQCS_MA 0xffU
38829 #define V_ZQCS_MA(x) ((x) << S_ZQCS_MA)
38830 #define G_ZQCS_MA(x) (((x) >> S_ZQCS_MA) & M_ZQCS_MA)
38832 #define A_MC_UPCTL_DTUPDES 0x40094
38834 #define S_DTU_ERR_B7 7
38835 #define V_DTU_ERR_B7(x) ((x) << S_DTU_ERR_B7)
38836 #define F_DTU_ERR_B7 V_DTU_ERR_B7(1U)
38838 #define A_MC_UPCTL_DTUNA 0x40098
38839 #define A_MC_UPCTL_DTUNE 0x4009c
38840 #define A_MC_UPCTL_DTUPRD0 0x400a0
38841 #define A_MC_UPCTL_DTUPRD1 0x400a4
38842 #define A_MC_UPCTL_DTUPRD2 0x400a8
38843 #define A_MC_UPCTL_DTUPRD3 0x400ac
38844 #define A_MC_UPCTL_DTUAWDT 0x400b0
38845 #define A_MC_UPCTL_TOGCNT1U 0x400c0
38846 #define A_MC_UPCTL_TINIT 0x400c4
38847 #define A_MC_UPCTL_TRSTH 0x400c8
38848 #define A_MC_UPCTL_TOGCNT100N 0x400cc
38849 #define A_MC_UPCTL_TREFI 0x400d0
38850 #define A_MC_UPCTL_TMRD 0x400d4
38851 #define A_MC_UPCTL_TRFC 0x400d8
38854 #define M_T_RFC0 0x1ffU
38855 #define V_T_RFC0(x) ((x) << S_T_RFC0)
38856 #define G_T_RFC0(x) (((x) >> S_T_RFC0) & M_T_RFC0)
38858 #define A_MC_UPCTL_TRP 0x400dc
38860 #define S_PREA_EXTRA 16
38861 #define M_PREA_EXTRA 0x3U
38862 #define V_PREA_EXTRA(x) ((x) << S_PREA_EXTRA)
38863 #define G_PREA_EXTRA(x) (((x) >> S_PREA_EXTRA) & M_PREA_EXTRA)
38865 #define A_MC_UPCTL_TRTW 0x400e0
38868 #define M_T_RTW0 0xfU
38869 #define V_T_RTW0(x) ((x) << S_T_RTW0)
38870 #define G_T_RTW0(x) (((x) >> S_T_RTW0) & M_T_RTW0)
38872 #define A_MC_UPCTL_TAL 0x400e4
38873 #define A_MC_UPCTL_TCL 0x400e8
38874 #define A_MC_UPCTL_TCWL 0x400ec
38875 #define A_MC_UPCTL_TRAS 0x400f0
38876 #define A_MC_UPCTL_TRC 0x400f4
38877 #define A_MC_UPCTL_TRCD 0x400f8
38878 #define A_MC_UPCTL_TRRD 0x400fc
38879 #define A_MC_UPCTL_TRTP 0x40100
38882 #define M_T_RTP0 0xfU
38883 #define V_T_RTP0(x) ((x) << S_T_RTP0)
38884 #define G_T_RTP0(x) (((x) >> S_T_RTP0) & M_T_RTP0)
38886 #define A_MC_UPCTL_TWR 0x40104
38889 #define M_U_T_WR 0x1fU
38890 #define V_U_T_WR(x) ((x) << S_U_T_WR)
38891 #define G_U_T_WR(x) (((x) >> S_U_T_WR) & M_U_T_WR)
38893 #define A_MC_UPCTL_TWTR 0x40108
38896 #define M_T_WTR0 0xfU
38897 #define V_T_WTR0(x) ((x) << S_T_WTR0)
38898 #define G_T_WTR0(x) (((x) >> S_T_WTR0) & M_T_WTR0)
38900 #define A_MC_UPCTL_TEXSR 0x4010c
38901 #define A_MC_UPCTL_TXP 0x40110
38902 #define A_MC_UPCTL_TXPDLL 0x40114
38903 #define A_MC_UPCTL_TZQCS 0x40118
38904 #define A_MC_UPCTL_TZQCSI 0x4011c
38905 #define A_MC_UPCTL_TDQS 0x40120
38906 #define A_MC_UPCTL_TCKSRE 0x40124
38908 #define S_T_CKSRE0 0
38909 #define M_T_CKSRE0 0x1fU
38910 #define V_T_CKSRE0(x) ((x) << S_T_CKSRE0)
38911 #define G_T_CKSRE0(x) (((x) >> S_T_CKSRE0) & M_T_CKSRE0)
38913 #define A_MC_UPCTL_TCKSRX 0x40128
38915 #define S_T_CKSRX0 0
38916 #define M_T_CKSRX0 0x1fU
38917 #define V_T_CKSRX0(x) ((x) << S_T_CKSRX0)
38918 #define G_T_CKSRX0(x) (((x) >> S_T_CKSRX0) & M_T_CKSRX0)
38920 #define A_MC_UPCTL_TCKE 0x4012c
38921 #define A_MC_UPCTL_TMOD 0x40130
38924 #define M_T_MOD0 0x1fU
38925 #define V_T_MOD0(x) ((x) << S_T_MOD0)
38926 #define G_T_MOD0(x) (((x) >> S_T_MOD0) & M_T_MOD0)
38928 #define A_MC_UPCTL_TRSTL 0x40134
38931 #define M_T_RSTL 0x7fU
38932 #define V_T_RSTL(x) ((x) << S_T_RSTL)
38933 #define G_T_RSTL(x) (((x) >> S_T_RSTL) & M_T_RSTL)
38935 #define A_MC_UPCTL_TZQCL 0x40138
38936 #define A_MC_UPCTL_TMRR 0x4013c
38939 #define M_T_MRR 0xffU
38940 #define V_T_MRR(x) ((x) << S_T_MRR)
38941 #define G_T_MRR(x) (((x) >> S_T_MRR) & M_T_MRR)
38943 #define A_MC_UPCTL_TCKESR 0x40140
38945 #define S_T_CKESR 0
38946 #define M_T_CKESR 0xfU
38947 #define V_T_CKESR(x) ((x) << S_T_CKESR)
38948 #define G_T_CKESR(x) (((x) >> S_T_CKESR) & M_T_CKESR)
38950 #define A_MC_UPCTL_TDPD 0x40144
38953 #define M_T_DPD 0x3ffU
38954 #define V_T_DPD(x) ((x) << S_T_DPD)
38955 #define G_T_DPD(x) (((x) >> S_T_DPD) & M_T_DPD)
38957 #define A_MC_UPCTL_ECCCFG 0x40180
38958 #define A_MC_UPCTL_ECCTST 0x40184
38960 #define S_ECC_TEST_MASK0 0
38961 #define M_ECC_TEST_MASK0 0x7fU
38962 #define V_ECC_TEST_MASK0(x) ((x) << S_ECC_TEST_MASK0)
38963 #define G_ECC_TEST_MASK0(x) (((x) >> S_ECC_TEST_MASK0) & M_ECC_TEST_MASK0)
38965 #define A_MC_UPCTL_ECCCLR 0x40188
38966 #define A_MC_UPCTL_ECCLOG 0x4018c
38967 #define A_MC_UPCTL_DTUWACTL 0x40200
38969 #define S_DTU_WR_ROW0 13
38970 #define M_DTU_WR_ROW0 0xffffU
38971 #define V_DTU_WR_ROW0(x) ((x) << S_DTU_WR_ROW0)
38972 #define G_DTU_WR_ROW0(x) (((x) >> S_DTU_WR_ROW0) & M_DTU_WR_ROW0)
38974 #define A_MC_UPCTL_DTURACTL 0x40204
38976 #define S_DTU_RD_ROW0 13
38977 #define M_DTU_RD_ROW0 0xffffU
38978 #define V_DTU_RD_ROW0(x) ((x) << S_DTU_RD_ROW0)
38979 #define G_DTU_RD_ROW0(x) (((x) >> S_DTU_RD_ROW0) & M_DTU_RD_ROW0)
38981 #define A_MC_UPCTL_DTUCFG 0x40208
38982 #define A_MC_UPCTL_DTUECTL 0x4020c
38983 #define A_MC_UPCTL_DTUWD0 0x40210
38984 #define A_MC_UPCTL_DTUWD1 0x40214
38985 #define A_MC_UPCTL_DTUWD2 0x40218
38986 #define A_MC_UPCTL_DTUWD3 0x4021c
38987 #define A_MC_UPCTL_DTUWDM 0x40220
38988 #define A_MC_UPCTL_DTURD0 0x40224
38989 #define A_MC_UPCTL_DTURD1 0x40228
38990 #define A_MC_UPCTL_DTURD2 0x4022c
38991 #define A_MC_UPCTL_DTURD3 0x40230
38992 #define A_MC_UPCTL_DTULFSRWD 0x40234
38993 #define A_MC_UPCTL_DTULFSRRD 0x40238
38994 #define A_MC_UPCTL_DTUEAF 0x4023c
38996 #define S_EA_ROW0 13
38997 #define M_EA_ROW0 0xffffU
38998 #define V_EA_ROW0(x) ((x) << S_EA_ROW0)
38999 #define G_EA_ROW0(x) (((x) >> S_EA_ROW0) & M_EA_ROW0)
39001 #define A_MC_UPCTL_DFITCTRLDELAY 0x40240
39003 #define S_TCTRL_DELAY 0
39004 #define M_TCTRL_DELAY 0xfU
39005 #define V_TCTRL_DELAY(x) ((x) << S_TCTRL_DELAY)
39006 #define G_TCTRL_DELAY(x) (((x) >> S_TCTRL_DELAY) & M_TCTRL_DELAY)
39008 #define A_MC_UPCTL_DFIODTCFG 0x40244
39010 #define S_RANK3_ODT_WRITE_NSEL 26
39011 #define V_RANK3_ODT_WRITE_NSEL(x) ((x) << S_RANK3_ODT_WRITE_NSEL)
39012 #define F_RANK3_ODT_WRITE_NSEL V_RANK3_ODT_WRITE_NSEL(1U)
39014 #define A_MC_UPCTL_DFIODTCFG1 0x40248
39016 #define S_ODT_LEN_B8_R 24
39017 #define M_ODT_LEN_B8_R 0x7U
39018 #define V_ODT_LEN_B8_R(x) ((x) << S_ODT_LEN_B8_R)
39019 #define G_ODT_LEN_B8_R(x) (((x) >> S_ODT_LEN_B8_R) & M_ODT_LEN_B8_R)
39021 #define S_ODT_LEN_BL8_W 16
39022 #define M_ODT_LEN_BL8_W 0x7U
39023 #define V_ODT_LEN_BL8_W(x) ((x) << S_ODT_LEN_BL8_W)
39024 #define G_ODT_LEN_BL8_W(x) (((x) >> S_ODT_LEN_BL8_W) & M_ODT_LEN_BL8_W)
39026 #define S_ODT_LAT_R 8
39027 #define M_ODT_LAT_R 0x1fU
39028 #define V_ODT_LAT_R(x) ((x) << S_ODT_LAT_R)
39029 #define G_ODT_LAT_R(x) (((x) >> S_ODT_LAT_R) & M_ODT_LAT_R)
39031 #define S_ODT_LAT_W 0
39032 #define M_ODT_LAT_W 0x1fU
39033 #define V_ODT_LAT_W(x) ((x) << S_ODT_LAT_W)
39034 #define G_ODT_LAT_W(x) (((x) >> S_ODT_LAT_W) & M_ODT_LAT_W)
39036 #define A_MC_UPCTL_DFIODTRANKMAP 0x4024c
39038 #define S_ODT_RANK_MAP3 12
39039 #define M_ODT_RANK_MAP3 0xfU
39040 #define V_ODT_RANK_MAP3(x) ((x) << S_ODT_RANK_MAP3)
39041 #define G_ODT_RANK_MAP3(x) (((x) >> S_ODT_RANK_MAP3) & M_ODT_RANK_MAP3)
39043 #define S_ODT_RANK_MAP2 8
39044 #define M_ODT_RANK_MAP2 0xfU
39045 #define V_ODT_RANK_MAP2(x) ((x) << S_ODT_RANK_MAP2)
39046 #define G_ODT_RANK_MAP2(x) (((x) >> S_ODT_RANK_MAP2) & M_ODT_RANK_MAP2)
39048 #define S_ODT_RANK_MAP1 4
39049 #define M_ODT_RANK_MAP1 0xfU
39050 #define V_ODT_RANK_MAP1(x) ((x) << S_ODT_RANK_MAP1)
39051 #define G_ODT_RANK_MAP1(x) (((x) >> S_ODT_RANK_MAP1) & M_ODT_RANK_MAP1)
39053 #define S_ODT_RANK_MAP0 0
39054 #define M_ODT_RANK_MAP0 0xfU
39055 #define V_ODT_RANK_MAP0(x) ((x) << S_ODT_RANK_MAP0)
39056 #define G_ODT_RANK_MAP0(x) (((x) >> S_ODT_RANK_MAP0) & M_ODT_RANK_MAP0)
39058 #define A_MC_UPCTL_DFITPHYWRDATA 0x40250
39060 #define S_TPHY_WRDATA 0
39061 #define M_TPHY_WRDATA 0x1fU
39062 #define V_TPHY_WRDATA(x) ((x) << S_TPHY_WRDATA)
39063 #define G_TPHY_WRDATA(x) (((x) >> S_TPHY_WRDATA) & M_TPHY_WRDATA)
39065 #define A_MC_UPCTL_DFITPHYWRLAT 0x40254
39067 #define S_TPHY_WRLAT 0
39068 #define M_TPHY_WRLAT 0x1fU
39069 #define V_TPHY_WRLAT(x) ((x) << S_TPHY_WRLAT)
39070 #define G_TPHY_WRLAT(x) (((x) >> S_TPHY_WRLAT) & M_TPHY_WRLAT)
39072 #define A_MC_UPCTL_DFITRDDATAEN 0x40260
39074 #define S_TRDDATA_EN 0
39075 #define M_TRDDATA_EN 0x1fU
39076 #define V_TRDDATA_EN(x) ((x) << S_TRDDATA_EN)
39077 #define G_TRDDATA_EN(x) (((x) >> S_TRDDATA_EN) & M_TRDDATA_EN)
39079 #define A_MC_UPCTL_DFITPHYRDLAT 0x40264
39081 #define S_TPHY_RDLAT 0
39082 #define M_TPHY_RDLAT 0x3fU
39083 #define V_TPHY_RDLAT(x) ((x) << S_TPHY_RDLAT)
39084 #define G_TPHY_RDLAT(x) (((x) >> S_TPHY_RDLAT) & M_TPHY_RDLAT)
39086 #define A_MC_UPCTL_DFITPHYUPDTYPE0 0x40270
39088 #define S_TPHYUPD_TYPE0 0
39089 #define M_TPHYUPD_TYPE0 0xfffU
39090 #define V_TPHYUPD_TYPE0(x) ((x) << S_TPHYUPD_TYPE0)
39091 #define G_TPHYUPD_TYPE0(x) (((x) >> S_TPHYUPD_TYPE0) & M_TPHYUPD_TYPE0)
39093 #define A_MC_UPCTL_DFITPHYUPDTYPE1 0x40274
39095 #define S_TPHYUPD_TYPE1 0
39096 #define M_TPHYUPD_TYPE1 0xfffU
39097 #define V_TPHYUPD_TYPE1(x) ((x) << S_TPHYUPD_TYPE1)
39098 #define G_TPHYUPD_TYPE1(x) (((x) >> S_TPHYUPD_TYPE1) & M_TPHYUPD_TYPE1)
39100 #define A_MC_UPCTL_DFITPHYUPDTYPE2 0x40278
39102 #define S_TPHYUPD_TYPE2 0
39103 #define M_TPHYUPD_TYPE2 0xfffU
39104 #define V_TPHYUPD_TYPE2(x) ((x) << S_TPHYUPD_TYPE2)
39105 #define G_TPHYUPD_TYPE2(x) (((x) >> S_TPHYUPD_TYPE2) & M_TPHYUPD_TYPE2)
39107 #define A_MC_UPCTL_DFITPHYUPDTYPE3 0x4027c
39109 #define S_TPHYUPD_TYPE3 0
39110 #define M_TPHYUPD_TYPE3 0xfffU
39111 #define V_TPHYUPD_TYPE3(x) ((x) << S_TPHYUPD_TYPE3)
39112 #define G_TPHYUPD_TYPE3(x) (((x) >> S_TPHYUPD_TYPE3) & M_TPHYUPD_TYPE3)
39114 #define A_MC_UPCTL_DFITCTRLUPDMIN 0x40280
39116 #define S_TCTRLUPD_MIN 0
39117 #define M_TCTRLUPD_MIN 0xffffU
39118 #define V_TCTRLUPD_MIN(x) ((x) << S_TCTRLUPD_MIN)
39119 #define G_TCTRLUPD_MIN(x) (((x) >> S_TCTRLUPD_MIN) & M_TCTRLUPD_MIN)
39121 #define A_MC_UPCTL_DFITCTRLUPDMAX 0x40284
39123 #define S_TCTRLUPD_MAX 0
39124 #define M_TCTRLUPD_MAX 0xffffU
39125 #define V_TCTRLUPD_MAX(x) ((x) << S_TCTRLUPD_MAX)
39126 #define G_TCTRLUPD_MAX(x) (((x) >> S_TCTRLUPD_MAX) & M_TCTRLUPD_MAX)
39128 #define A_MC_UPCTL_DFITCTRLUPDDLY 0x40288
39130 #define S_TCTRLUPD_DLY 0
39131 #define M_TCTRLUPD_DLY 0xfU
39132 #define V_TCTRLUPD_DLY(x) ((x) << S_TCTRLUPD_DLY)
39133 #define G_TCTRLUPD_DLY(x) (((x) >> S_TCTRLUPD_DLY) & M_TCTRLUPD_DLY)
39135 #define A_MC_UPCTL_DFIUPDCFG 0x40290
39137 #define S_DFI_PHYUPD_EN 1
39138 #define V_DFI_PHYUPD_EN(x) ((x) << S_DFI_PHYUPD_EN)
39139 #define F_DFI_PHYUPD_EN V_DFI_PHYUPD_EN(1U)
39141 #define S_DFI_CTRLUPD_EN 0
39142 #define V_DFI_CTRLUPD_EN(x) ((x) << S_DFI_CTRLUPD_EN)
39143 #define F_DFI_CTRLUPD_EN V_DFI_CTRLUPD_EN(1U)
39145 #define A_MC_UPCTL_DFITREFMSKI 0x40294
39147 #define S_TREFMSKI 0
39148 #define M_TREFMSKI 0xffU
39149 #define V_TREFMSKI(x) ((x) << S_TREFMSKI)
39150 #define G_TREFMSKI(x) (((x) >> S_TREFMSKI) & M_TREFMSKI)
39152 #define A_MC_UPCTL_DFITCTRLUPDI 0x40298
39153 #define A_MC_UPCTL_DFITRCFG0 0x402ac
39155 #define S_DFI_WRLVL_RANK_SEL 16
39156 #define M_DFI_WRLVL_RANK_SEL 0xfU
39157 #define V_DFI_WRLVL_RANK_SEL(x) ((x) << S_DFI_WRLVL_RANK_SEL)
39158 #define G_DFI_WRLVL_RANK_SEL(x) (((x) >> S_DFI_WRLVL_RANK_SEL) & M_DFI_WRLVL_RANK_SEL)
39160 #define S_DFI_RDLVL_EDGE 4
39161 #define M_DFI_RDLVL_EDGE 0x1ffU
39162 #define V_DFI_RDLVL_EDGE(x) ((x) << S_DFI_RDLVL_EDGE)
39163 #define G_DFI_RDLVL_EDGE(x) (((x) >> S_DFI_RDLVL_EDGE) & M_DFI_RDLVL_EDGE)
39165 #define S_DFI_RDLVL_RANK_SEL 0
39166 #define M_DFI_RDLVL_RANK_SEL 0xfU
39167 #define V_DFI_RDLVL_RANK_SEL(x) ((x) << S_DFI_RDLVL_RANK_SEL)
39168 #define G_DFI_RDLVL_RANK_SEL(x) (((x) >> S_DFI_RDLVL_RANK_SEL) & M_DFI_RDLVL_RANK_SEL)
39170 #define A_MC_UPCTL_DFITRSTAT0 0x402b0
39172 #define S_DFI_WRLVL_MODE 16
39173 #define M_DFI_WRLVL_MODE 0x3U
39174 #define V_DFI_WRLVL_MODE(x) ((x) << S_DFI_WRLVL_MODE)
39175 #define G_DFI_WRLVL_MODE(x) (((x) >> S_DFI_WRLVL_MODE) & M_DFI_WRLVL_MODE)
39177 #define S_DFI_RDLVL_GATE_MODE 8
39178 #define M_DFI_RDLVL_GATE_MODE 0x3U
39179 #define V_DFI_RDLVL_GATE_MODE(x) ((x) << S_DFI_RDLVL_GATE_MODE)
39180 #define G_DFI_RDLVL_GATE_MODE(x) (((x) >> S_DFI_RDLVL_GATE_MODE) & M_DFI_RDLVL_GATE_MODE)
39182 #define S_DFI_RDLVL_MODE 0
39183 #define M_DFI_RDLVL_MODE 0x3U
39184 #define V_DFI_RDLVL_MODE(x) ((x) << S_DFI_RDLVL_MODE)
39185 #define G_DFI_RDLVL_MODE(x) (((x) >> S_DFI_RDLVL_MODE) & M_DFI_RDLVL_MODE)
39187 #define A_MC_UPCTL_DFITRWRLVLEN 0x402b4
39189 #define S_DFI_WRLVL_EN 0
39190 #define M_DFI_WRLVL_EN 0x1ffU
39191 #define V_DFI_WRLVL_EN(x) ((x) << S_DFI_WRLVL_EN)
39192 #define G_DFI_WRLVL_EN(x) (((x) >> S_DFI_WRLVL_EN) & M_DFI_WRLVL_EN)
39194 #define A_MC_UPCTL_DFITRRDLVLEN 0x402b8
39196 #define S_DFI_RDLVL_EN 0
39197 #define M_DFI_RDLVL_EN 0x1ffU
39198 #define V_DFI_RDLVL_EN(x) ((x) << S_DFI_RDLVL_EN)
39199 #define G_DFI_RDLVL_EN(x) (((x) >> S_DFI_RDLVL_EN) & M_DFI_RDLVL_EN)
39201 #define A_MC_UPCTL_DFITRRDLVLGATEEN 0x402bc
39203 #define S_DFI_RDLVL_GATE_EN 0
39204 #define M_DFI_RDLVL_GATE_EN 0x1ffU
39205 #define V_DFI_RDLVL_GATE_EN(x) ((x) << S_DFI_RDLVL_GATE_EN)
39206 #define G_DFI_RDLVL_GATE_EN(x) (((x) >> S_DFI_RDLVL_GATE_EN) & M_DFI_RDLVL_GATE_EN)
39208 #define A_MC_UPCTL_DFISTSTAT0 0x402c0
39210 #define S_DFI_DATA_BYTE_DISABLE 16
39211 #define M_DFI_DATA_BYTE_DISABLE 0x1ffU
39212 #define V_DFI_DATA_BYTE_DISABLE(x) ((x) << S_DFI_DATA_BYTE_DISABLE)
39213 #define G_DFI_DATA_BYTE_DISABLE(x) (((x) >> S_DFI_DATA_BYTE_DISABLE) & M_DFI_DATA_BYTE_DISABLE)
39215 #define S_DFI_FREQ_RATIO 4
39216 #define M_DFI_FREQ_RATIO 0x3U
39217 #define V_DFI_FREQ_RATIO(x) ((x) << S_DFI_FREQ_RATIO)
39218 #define G_DFI_FREQ_RATIO(x) (((x) >> S_DFI_FREQ_RATIO) & M_DFI_FREQ_RATIO)
39220 #define S_DFI_INIT_START0 1
39221 #define V_DFI_INIT_START0(x) ((x) << S_DFI_INIT_START0)
39222 #define F_DFI_INIT_START0 V_DFI_INIT_START0(1U)
39224 #define S_DFI_INIT_COMPLETE 0
39225 #define V_DFI_INIT_COMPLETE(x) ((x) << S_DFI_INIT_COMPLETE)
39226 #define F_DFI_INIT_COMPLETE V_DFI_INIT_COMPLETE(1U)
39228 #define A_MC_UPCTL_DFISTCFG0 0x402c4
39230 #define S_DFI_DATA_BYTE_DISABLE_EN 2
39231 #define V_DFI_DATA_BYTE_DISABLE_EN(x) ((x) << S_DFI_DATA_BYTE_DISABLE_EN)
39232 #define F_DFI_DATA_BYTE_DISABLE_EN V_DFI_DATA_BYTE_DISABLE_EN(1U)
39234 #define S_DFI_FREQ_RATIO_EN 1
39235 #define V_DFI_FREQ_RATIO_EN(x) ((x) << S_DFI_FREQ_RATIO_EN)
39236 #define F_DFI_FREQ_RATIO_EN V_DFI_FREQ_RATIO_EN(1U)
39238 #define S_DFI_INIT_START 0
39239 #define V_DFI_INIT_START(x) ((x) << S_DFI_INIT_START)
39240 #define F_DFI_INIT_START V_DFI_INIT_START(1U)
39242 #define A_MC_UPCTL_DFISTCFG1 0x402c8
39244 #define S_DFI_DRAM_CLK_DISABLE_EN_DPD 1
39245 #define V_DFI_DRAM_CLK_DISABLE_EN_DPD(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN_DPD)
39246 #define F_DFI_DRAM_CLK_DISABLE_EN_DPD V_DFI_DRAM_CLK_DISABLE_EN_DPD(1U)
39248 #define S_DFI_DRAM_CLK_DISABLE_EN 0
39249 #define V_DFI_DRAM_CLK_DISABLE_EN(x) ((x) << S_DFI_DRAM_CLK_DISABLE_EN)
39250 #define F_DFI_DRAM_CLK_DISABLE_EN V_DFI_DRAM_CLK_DISABLE_EN(1U)
39252 #define A_MC_UPCTL_DFITDRAMCLKEN 0x402d0
39254 #define S_TDRAM_CLK_ENABLE 0
39255 #define M_TDRAM_CLK_ENABLE 0xfU
39256 #define V_TDRAM_CLK_ENABLE(x) ((x) << S_TDRAM_CLK_ENABLE)
39257 #define G_TDRAM_CLK_ENABLE(x) (((x) >> S_TDRAM_CLK_ENABLE) & M_TDRAM_CLK_ENABLE)
39259 #define A_MC_UPCTL_DFITDRAMCLKDIS 0x402d4
39261 #define S_TDRAM_CLK_DISABLE 0
39262 #define M_TDRAM_CLK_DISABLE 0xfU
39263 #define V_TDRAM_CLK_DISABLE(x) ((x) << S_TDRAM_CLK_DISABLE)
39264 #define G_TDRAM_CLK_DISABLE(x) (((x) >> S_TDRAM_CLK_DISABLE) & M_TDRAM_CLK_DISABLE)
39266 #define A_MC_UPCTL_DFISTCFG2 0x402d8
39268 #define S_PARITY_EN 1
39269 #define V_PARITY_EN(x) ((x) << S_PARITY_EN)
39270 #define F_PARITY_EN V_PARITY_EN(1U)
39272 #define S_PARITY_INTR_EN 0
39273 #define V_PARITY_INTR_EN(x) ((x) << S_PARITY_INTR_EN)
39274 #define F_PARITY_INTR_EN V_PARITY_INTR_EN(1U)
39276 #define A_MC_UPCTL_DFISTPARCLR 0x402dc
39278 #define S_PARITY_LOG_CLR 1
39279 #define V_PARITY_LOG_CLR(x) ((x) << S_PARITY_LOG_CLR)
39280 #define F_PARITY_LOG_CLR V_PARITY_LOG_CLR(1U)
39282 #define S_PARITY_INTR_CLR 0
39283 #define V_PARITY_INTR_CLR(x) ((x) << S_PARITY_INTR_CLR)
39284 #define F_PARITY_INTR_CLR V_PARITY_INTR_CLR(1U)
39286 #define A_MC_UPCTL_DFISTPARLOG 0x402e0
39287 #define A_MC_UPCTL_DFILPCFG0 0x402f0
39289 #define S_DFI_LP_WAKEUP_DPD 28
39290 #define M_DFI_LP_WAKEUP_DPD 0xfU
39291 #define V_DFI_LP_WAKEUP_DPD(x) ((x) << S_DFI_LP_WAKEUP_DPD)
39292 #define G_DFI_LP_WAKEUP_DPD(x) (((x) >> S_DFI_LP_WAKEUP_DPD) & M_DFI_LP_WAKEUP_DPD)
39294 #define S_DFI_LP_EN_DPD 24
39295 #define V_DFI_LP_EN_DPD(x) ((x) << S_DFI_LP_EN_DPD)
39296 #define F_DFI_LP_EN_DPD V_DFI_LP_EN_DPD(1U)
39298 #define S_DFI_TLP_RESP 16
39299 #define M_DFI_TLP_RESP 0xfU
39300 #define V_DFI_TLP_RESP(x) ((x) << S_DFI_TLP_RESP)
39301 #define G_DFI_TLP_RESP(x) (((x) >> S_DFI_TLP_RESP) & M_DFI_TLP_RESP)
39303 #define S_DFI_LP_EN_SR 8
39304 #define V_DFI_LP_EN_SR(x) ((x) << S_DFI_LP_EN_SR)
39305 #define F_DFI_LP_EN_SR V_DFI_LP_EN_SR(1U)
39307 #define S_DFI_LP_WAKEUP_PD 4
39308 #define M_DFI_LP_WAKEUP_PD 0xfU
39309 #define V_DFI_LP_WAKEUP_PD(x) ((x) << S_DFI_LP_WAKEUP_PD)
39310 #define G_DFI_LP_WAKEUP_PD(x) (((x) >> S_DFI_LP_WAKEUP_PD) & M_DFI_LP_WAKEUP_PD)
39312 #define S_DFI_LP_EN_PD 0
39313 #define V_DFI_LP_EN_PD(x) ((x) << S_DFI_LP_EN_PD)
39314 #define F_DFI_LP_EN_PD V_DFI_LP_EN_PD(1U)
39316 #define A_MC_UPCTL_DFITRWRLVLRESP0 0x40300
39317 #define A_MC_UPCTL_DFITRWRLVLRESP1 0x40304
39318 #define A_MC_UPCTL_DFITRWRLVLRESP2 0x40308
39320 #define S_DFI_WRLVL_RESP2 0
39321 #define M_DFI_WRLVL_RESP2 0xffU
39322 #define V_DFI_WRLVL_RESP2(x) ((x) << S_DFI_WRLVL_RESP2)
39323 #define G_DFI_WRLVL_RESP2(x) (((x) >> S_DFI_WRLVL_RESP2) & M_DFI_WRLVL_RESP2)
39325 #define A_MC_UPCTL_DFITRRDLVLRESP0 0x4030c
39326 #define A_MC_UPCTL_DFITRRDLVLRESP1 0x40310
39327 #define A_MC_UPCTL_DFITRRDLVLRESP2 0x40314
39329 #define S_DFI_RDLVL_RESP2 0
39330 #define M_DFI_RDLVL_RESP2 0xffU
39331 #define V_DFI_RDLVL_RESP2(x) ((x) << S_DFI_RDLVL_RESP2)
39332 #define G_DFI_RDLVL_RESP2(x) (((x) >> S_DFI_RDLVL_RESP2) & M_DFI_RDLVL_RESP2)
39334 #define A_MC_UPCTL_DFITRWRLVLDELAY0 0x40318
39335 #define A_MC_UPCTL_DFITRWRLVLDELAY1 0x4031c
39336 #define A_MC_UPCTL_DFITRWRLVLDELAY2 0x40320
39338 #define S_DFI_WRLVL_DELAY2 0
39339 #define M_DFI_WRLVL_DELAY2 0xffU
39340 #define V_DFI_WRLVL_DELAY2(x) ((x) << S_DFI_WRLVL_DELAY2)
39341 #define G_DFI_WRLVL_DELAY2(x) (((x) >> S_DFI_WRLVL_DELAY2) & M_DFI_WRLVL_DELAY2)
39343 #define A_MC_UPCTL_DFITRRDLVLDELAY0 0x40324
39344 #define A_MC_UPCTL_DFITRRDLVLDELAY1 0x40328
39345 #define A_MC_UPCTL_DFITRRDLVLDELAY2 0x4032c
39347 #define S_DFI_RDLVL_DELAY2 0
39348 #define M_DFI_RDLVL_DELAY2 0xffU
39349 #define V_DFI_RDLVL_DELAY2(x) ((x) << S_DFI_RDLVL_DELAY2)
39350 #define G_DFI_RDLVL_DELAY2(x) (((x) >> S_DFI_RDLVL_DELAY2) & M_DFI_RDLVL_DELAY2)
39352 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY0 0x40330
39353 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY1 0x40334
39354 #define A_MC_UPCTL_DFITRRDLVLGATEDELAY2 0x40338
39356 #define S_DFI_RDLVL_GATE_DELAY2 0
39357 #define M_DFI_RDLVL_GATE_DELAY2 0xffU
39358 #define V_DFI_RDLVL_GATE_DELAY2(x) ((x) << S_DFI_RDLVL_GATE_DELAY2)
39359 #define G_DFI_RDLVL_GATE_DELAY2(x) (((x) >> S_DFI_RDLVL_GATE_DELAY2) & M_DFI_RDLVL_GATE_DELAY2)
39361 #define A_MC_UPCTL_DFITRCMD 0x4033c
39363 #define S_DFITRCMD_START 31
39364 #define V_DFITRCMD_START(x) ((x) << S_DFITRCMD_START)
39365 #define F_DFITRCMD_START V_DFITRCMD_START(1U)
39367 #define S_DFITRCMD_EN 4
39368 #define M_DFITRCMD_EN 0x1ffU
39369 #define V_DFITRCMD_EN(x) ((x) << S_DFITRCMD_EN)
39370 #define G_DFITRCMD_EN(x) (((x) >> S_DFITRCMD_EN) & M_DFITRCMD_EN)
39372 #define S_DFITRCMD_OPCODE 0
39373 #define M_DFITRCMD_OPCODE 0x3U
39374 #define V_DFITRCMD_OPCODE(x) ((x) << S_DFITRCMD_OPCODE)
39375 #define G_DFITRCMD_OPCODE(x) (((x) >> S_DFITRCMD_OPCODE) & M_DFITRCMD_OPCODE)
39377 #define A_MC_UPCTL_IPVR 0x403f8
39378 #define A_MC_UPCTL_IPTR 0x403fc
39379 #define A_MC_P_DDRPHY_RST_CTRL 0x41300
39381 #define S_PHY_DRAM_WL 17
39382 #define M_PHY_DRAM_WL 0x1fU
39383 #define V_PHY_DRAM_WL(x) ((x) << S_PHY_DRAM_WL)
39384 #define G_PHY_DRAM_WL(x) (((x) >> S_PHY_DRAM_WL) & M_PHY_DRAM_WL)
39386 #define S_PHY_CALIB_DONE 5
39387 #define V_PHY_CALIB_DONE(x) ((x) << S_PHY_CALIB_DONE)
39388 #define F_PHY_CALIB_DONE V_PHY_CALIB_DONE(1U)
39390 #define S_CTL_CAL_REQ 4
39391 #define V_CTL_CAL_REQ(x) ((x) << S_CTL_CAL_REQ)
39392 #define F_CTL_CAL_REQ V_CTL_CAL_REQ(1U)
39394 #define S_CTL_CKE 3
39395 #define V_CTL_CKE(x) ((x) << S_CTL_CKE)
39396 #define F_CTL_CKE V_CTL_CKE(1U)
39398 #define S_CTL_RST_N 2
39399 #define V_CTL_RST_N(x) ((x) << S_CTL_RST_N)
39400 #define F_CTL_RST_N V_CTL_RST_N(1U)
39402 #define A_MC_P_PERFORMANCE_CTRL 0x41304
39403 #define A_MC_P_ECC_CTRL 0x41308
39404 #define A_MC_P_PAR_ENABLE 0x4130c
39405 #define A_MC_P_PAR_CAUSE 0x41310
39406 #define A_MC_P_INT_ENABLE 0x41314
39407 #define A_MC_P_INT_CAUSE 0x41318
39408 #define A_MC_P_ECC_STATUS 0x4131c
39409 #define A_MC_P_PHY_CTRL 0x41320
39410 #define A_MC_P_STATIC_CFG_STATUS 0x41324
39412 #define S_STATIC_AWEN 23
39413 #define V_STATIC_AWEN(x) ((x) << S_STATIC_AWEN)
39414 #define F_STATIC_AWEN V_STATIC_AWEN(1U)
39416 #define S_STATIC_SWLAT 18
39417 #define M_STATIC_SWLAT 0x1fU
39418 #define V_STATIC_SWLAT(x) ((x) << S_STATIC_SWLAT)
39419 #define G_STATIC_SWLAT(x) (((x) >> S_STATIC_SWLAT) & M_STATIC_SWLAT)
39421 #define S_STATIC_WLAT 17
39422 #define V_STATIC_WLAT(x) ((x) << S_STATIC_WLAT)
39423 #define F_STATIC_WLAT V_STATIC_WLAT(1U)
39425 #define S_STATIC_ALIGN 16
39426 #define V_STATIC_ALIGN(x) ((x) << S_STATIC_ALIGN)
39427 #define F_STATIC_ALIGN V_STATIC_ALIGN(1U)
39429 #define S_STATIC_SLAT 11
39430 #define M_STATIC_SLAT 0x1fU
39431 #define V_STATIC_SLAT(x) ((x) << S_STATIC_SLAT)
39432 #define G_STATIC_SLAT(x) (((x) >> S_STATIC_SLAT) & M_STATIC_SLAT)
39434 #define S_STATIC_LAT 10
39435 #define V_STATIC_LAT(x) ((x) << S_STATIC_LAT)
39436 #define F_STATIC_LAT V_STATIC_LAT(1U)
39438 #define A_MC_P_CORE_PCTL_STAT 0x41328
39439 #define A_MC_P_DEBUG_CNT 0x4132c
39440 #define A_MC_CE_ERR_DATA_RDATA 0x41330
39441 #define A_MC_CE_COR_DATA_RDATA 0x41350
39442 #define A_MC_UE_ERR_DATA_RDATA 0x41370
39443 #define A_MC_UE_COR_DATA_RDATA 0x41390
39444 #define A_MC_CE_ADDR 0x413b0
39445 #define A_MC_UE_ADDR 0x413b4
39446 #define A_MC_P_DEEP_SLEEP 0x413b8
39448 #define S_SLEEPSTATUS 1
39449 #define V_SLEEPSTATUS(x) ((x) << S_SLEEPSTATUS)
39450 #define F_SLEEPSTATUS V_SLEEPSTATUS(1U)
39452 #define S_SLEEPREQ 0
39453 #define V_SLEEPREQ(x) ((x) << S_SLEEPREQ)
39454 #define F_SLEEPREQ V_SLEEPREQ(1U)
39456 #define A_MC_P_FPGA_BONUS 0x413bc
39457 #define A_MC_P_DEBUG_CFG 0x413c0
39458 #define A_MC_P_DEBUG_RPT 0x413c4
39459 #define A_MC_P_BIST_CMD 0x41400
39461 #define S_BURST_LEN 16
39462 #define M_BURST_LEN 0x3U
39463 #define V_BURST_LEN(x) ((x) << S_BURST_LEN)
39464 #define G_BURST_LEN(x) (((x) >> S_BURST_LEN) & M_BURST_LEN)
39466 #define A_MC_P_BIST_CMD_ADDR 0x41404
39467 #define A_MC_P_BIST_CMD_LEN 0x41408
39468 #define A_MC_P_BIST_DATA_PATTERN 0x4140c
39469 #define A_MC_P_BIST_USER_WDATA0 0x41414
39470 #define A_MC_P_BIST_USER_WDATA1 0x41418
39471 #define A_MC_P_BIST_USER_WDATA2 0x4141c
39473 #define S_USER_DATA_MASK 8
39474 #define M_USER_DATA_MASK 0x1ffU
39475 #define V_USER_DATA_MASK(x) ((x) << S_USER_DATA_MASK)
39476 #define G_USER_DATA_MASK(x) (((x) >> S_USER_DATA_MASK) & M_USER_DATA_MASK)
39478 #define A_MC_P_BIST_NUM_ERR 0x41480
39479 #define A_MC_P_BIST_ERR_FIRST_ADDR 0x41484
39480 #define A_MC_P_BIST_STATUS_RDATA 0x41488
39481 #define A_MC_P_BIST_CRC_SEED 0x414d0
39482 #define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE0 0x44000
39484 #define S_DATA_BIT_ENABLE_0_15 0
39485 #define M_DATA_BIT_ENABLE_0_15 0xffffU
39486 #define V_DATA_BIT_ENABLE_0_15(x) ((x) << S_DATA_BIT_ENABLE_0_15)
39487 #define G_DATA_BIT_ENABLE_0_15(x) (((x) >> S_DATA_BIT_ENABLE_0_15) & M_DATA_BIT_ENABLE_0_15)
39489 #define A_MC_DDRPHY_DP18_DATA_BIT_ENABLE1 0x44004
39491 #define S_DATA_BIT_ENABLE_16_23 8
39492 #define M_DATA_BIT_ENABLE_16_23 0xffU
39493 #define V_DATA_BIT_ENABLE_16_23(x) ((x) << S_DATA_BIT_ENABLE_16_23)
39494 #define G_DATA_BIT_ENABLE_16_23(x) (((x) >> S_DATA_BIT_ENABLE_16_23) & M_DATA_BIT_ENABLE_16_23)
39496 #define S_DFT_FORCE_OUTPUTS 7
39497 #define V_DFT_FORCE_OUTPUTS(x) ((x) << S_DFT_FORCE_OUTPUTS)
39498 #define F_DFT_FORCE_OUTPUTS V_DFT_FORCE_OUTPUTS(1U)
39500 #define S_DFT_PRBS7_GEN_EN 6
39501 #define V_DFT_PRBS7_GEN_EN(x) ((x) << S_DFT_PRBS7_GEN_EN)
39502 #define F_DFT_PRBS7_GEN_EN V_DFT_PRBS7_GEN_EN(1U)
39504 #define S_WRAPSEL 5
39505 #define V_WRAPSEL(x) ((x) << S_WRAPSEL)
39506 #define F_WRAPSEL V_WRAPSEL(1U)
39508 #define S_MRS_CMD_DATA_N0 3
39509 #define V_MRS_CMD_DATA_N0(x) ((x) << S_MRS_CMD_DATA_N0)
39510 #define F_MRS_CMD_DATA_N0 V_MRS_CMD_DATA_N0(1U)
39512 #define S_MRS_CMD_DATA_N1 2
39513 #define V_MRS_CMD_DATA_N1(x) ((x) << S_MRS_CMD_DATA_N1)
39514 #define F_MRS_CMD_DATA_N1 V_MRS_CMD_DATA_N1(1U)
39516 #define S_MRS_CMD_DATA_N2 1
39517 #define V_MRS_CMD_DATA_N2(x) ((x) << S_MRS_CMD_DATA_N2)
39518 #define F_MRS_CMD_DATA_N2 V_MRS_CMD_DATA_N2(1U)
39520 #define S_MRS_CMD_DATA_N3 0
39521 #define V_MRS_CMD_DATA_N3(x) ((x) << S_MRS_CMD_DATA_N3)
39522 #define F_MRS_CMD_DATA_N3 V_MRS_CMD_DATA_N3(1U)
39524 #define A_MC_DDRPHY_DP18_DATA_BIT_DIR0 0x44008
39526 #define S_DATA_BIT_DIR_0_15 0
39527 #define M_DATA_BIT_DIR_0_15 0xffffU
39528 #define V_DATA_BIT_DIR_0_15(x) ((x) << S_DATA_BIT_DIR_0_15)
39529 #define G_DATA_BIT_DIR_0_15(x) (((x) >> S_DATA_BIT_DIR_0_15) & M_DATA_BIT_DIR_0_15)
39531 #define A_MC_DDRPHY_DP18_DATA_BIT_DIR1 0x4400c
39533 #define S_DATA_BIT_DIR_16_23 8
39534 #define M_DATA_BIT_DIR_16_23 0xffU
39535 #define V_DATA_BIT_DIR_16_23(x) ((x) << S_DATA_BIT_DIR_16_23)
39536 #define G_DATA_BIT_DIR_16_23(x) (((x) >> S_DATA_BIT_DIR_16_23) & M_DATA_BIT_DIR_16_23)
39538 #define S_WL_ADVANCE_DISABLE 7
39539 #define V_WL_ADVANCE_DISABLE(x) ((x) << S_WL_ADVANCE_DISABLE)
39540 #define F_WL_ADVANCE_DISABLE V_WL_ADVANCE_DISABLE(1U)
39542 #define S_DISABLE_PING_PONG 6
39543 #define V_DISABLE_PING_PONG(x) ((x) << S_DISABLE_PING_PONG)
39544 #define F_DISABLE_PING_PONG V_DISABLE_PING_PONG(1U)
39546 #define S_DELAY_PING_PONG_HALF 5
39547 #define V_DELAY_PING_PONG_HALF(x) ((x) << S_DELAY_PING_PONG_HALF)
39548 #define F_DELAY_PING_PONG_HALF V_DELAY_PING_PONG_HALF(1U)
39550 #define S_ADVANCE_PING_PONG 4
39551 #define V_ADVANCE_PING_PONG(x) ((x) << S_ADVANCE_PING_PONG)
39552 #define F_ADVANCE_PING_PONG V_ADVANCE_PING_PONG(1U)
39554 #define S_ATEST_MUX_CTL0 3
39555 #define V_ATEST_MUX_CTL0(x) ((x) << S_ATEST_MUX_CTL0)
39556 #define F_ATEST_MUX_CTL0 V_ATEST_MUX_CTL0(1U)
39558 #define S_ATEST_MUX_CTL1 2
39559 #define V_ATEST_MUX_CTL1(x) ((x) << S_ATEST_MUX_CTL1)
39560 #define F_ATEST_MUX_CTL1 V_ATEST_MUX_CTL1(1U)
39562 #define S_ATEST_MUX_CTL2 1
39563 #define V_ATEST_MUX_CTL2(x) ((x) << S_ATEST_MUX_CTL2)
39564 #define F_ATEST_MUX_CTL2 V_ATEST_MUX_CTL2(1U)
39566 #define S_ATEST_MUX_CTL3 0
39567 #define V_ATEST_MUX_CTL3(x) ((x) << S_ATEST_MUX_CTL3)
39568 #define F_ATEST_MUX_CTL3 V_ATEST_MUX_CTL3(1U)
39570 #define A_MC_DDRPHY_DP18_READ_CLOCK_RANK_PAIR 0x44010
39572 #define S_QUAD0_CLK16_BIT0 15
39573 #define V_QUAD0_CLK16_BIT0(x) ((x) << S_QUAD0_CLK16_BIT0)
39574 #define F_QUAD0_CLK16_BIT0 V_QUAD0_CLK16_BIT0(1U)
39576 #define S_QUAD1_CLK16_BIT1 14
39577 #define V_QUAD1_CLK16_BIT1(x) ((x) << S_QUAD1_CLK16_BIT1)
39578 #define F_QUAD1_CLK16_BIT1 V_QUAD1_CLK16_BIT1(1U)
39580 #define S_QUAD2_CLK16_BIT2 13
39581 #define V_QUAD2_CLK16_BIT2(x) ((x) << S_QUAD2_CLK16_BIT2)
39582 #define F_QUAD2_CLK16_BIT2 V_QUAD2_CLK16_BIT2(1U)
39584 #define S_QUAD3_CLK16_BIT3 12
39585 #define V_QUAD3_CLK16_BIT3(x) ((x) << S_QUAD3_CLK16_BIT3)
39586 #define F_QUAD3_CLK16_BIT3 V_QUAD3_CLK16_BIT3(1U)
39588 #define S_QUAD0_CLK18_BIT4 11
39589 #define V_QUAD0_CLK18_BIT4(x) ((x) << S_QUAD0_CLK18_BIT4)
39590 #define F_QUAD0_CLK18_BIT4 V_QUAD0_CLK18_BIT4(1U)
39592 #define S_QUAD1_CLK18_BIT5 10
39593 #define V_QUAD1_CLK18_BIT5(x) ((x) << S_QUAD1_CLK18_BIT5)
39594 #define F_QUAD1_CLK18_BIT5 V_QUAD1_CLK18_BIT5(1U)
39596 #define S_QUAD2_CLK20_BIT6 9
39597 #define V_QUAD2_CLK20_BIT6(x) ((x) << S_QUAD2_CLK20_BIT6)
39598 #define F_QUAD2_CLK20_BIT6 V_QUAD2_CLK20_BIT6(1U)
39600 #define S_QUAD3_CLK20_BIT7 8
39601 #define V_QUAD3_CLK20_BIT7(x) ((x) << S_QUAD3_CLK20_BIT7)
39602 #define F_QUAD3_CLK20_BIT7 V_QUAD3_CLK20_BIT7(1U)
39604 #define S_QUAD2_CLK22_BIT8 7
39605 #define V_QUAD2_CLK22_BIT8(x) ((x) << S_QUAD2_CLK22_BIT8)
39606 #define F_QUAD2_CLK22_BIT8 V_QUAD2_CLK22_BIT8(1U)
39608 #define S_QUAD3_CLK22_BIT9 6
39609 #define V_QUAD3_CLK22_BIT9(x) ((x) << S_QUAD3_CLK22_BIT9)
39610 #define F_QUAD3_CLK22_BIT9 V_QUAD3_CLK22_BIT9(1U)
39612 #define S_CLK16_SINGLE_ENDED_BIT10 5
39613 #define V_CLK16_SINGLE_ENDED_BIT10(x) ((x) << S_CLK16_SINGLE_ENDED_BIT10)
39614 #define F_CLK16_SINGLE_ENDED_BIT10 V_CLK16_SINGLE_ENDED_BIT10(1U)
39616 #define S_CLK18_SINGLE_ENDED_BIT11 4
39617 #define V_CLK18_SINGLE_ENDED_BIT11(x) ((x) << S_CLK18_SINGLE_ENDED_BIT11)
39618 #define F_CLK18_SINGLE_ENDED_BIT11 V_CLK18_SINGLE_ENDED_BIT11(1U)
39620 #define S_CLK20_SINGLE_ENDED_BIT12 3
39621 #define V_CLK20_SINGLE_ENDED_BIT12(x) ((x) << S_CLK20_SINGLE_ENDED_BIT12)
39622 #define F_CLK20_SINGLE_ENDED_BIT12 V_CLK20_SINGLE_ENDED_BIT12(1U)
39624 #define S_CLK22_SINGLE_ENDED_BIT13 2
39625 #define V_CLK22_SINGLE_ENDED_BIT13(x) ((x) << S_CLK22_SINGLE_ENDED_BIT13)
39626 #define F_CLK22_SINGLE_ENDED_BIT13 V_CLK22_SINGLE_ENDED_BIT13(1U)
39628 #define A_MC_DDRPHY_DP18_WRCLK_EN_RP 0x44014
39630 #define S_QUAD2_CLK18_BIT14 1
39631 #define V_QUAD2_CLK18_BIT14(x) ((x) << S_QUAD2_CLK18_BIT14)
39632 #define F_QUAD2_CLK18_BIT14 V_QUAD2_CLK18_BIT14(1U)
39634 #define S_QUAD3_CLK18_BIT15 0
39635 #define V_QUAD3_CLK18_BIT15(x) ((x) << S_QUAD3_CLK18_BIT15)
39636 #define F_QUAD3_CLK18_BIT15 V_QUAD3_CLK18_BIT15(1U)
39638 #define A_MC_DDRPHY_DP18_RX_PEAK_AMP 0x44018
39640 #define S_PEAK_AMP_CTL_SIDE0 13
39641 #define M_PEAK_AMP_CTL_SIDE0 0x7U
39642 #define V_PEAK_AMP_CTL_SIDE0(x) ((x) << S_PEAK_AMP_CTL_SIDE0)
39643 #define G_PEAK_AMP_CTL_SIDE0(x) (((x) >> S_PEAK_AMP_CTL_SIDE0) & M_PEAK_AMP_CTL_SIDE0)
39645 #define S_PEAK_AMP_CTL_SIDE1 9
39646 #define M_PEAK_AMP_CTL_SIDE1 0x7U
39647 #define V_PEAK_AMP_CTL_SIDE1(x) ((x) << S_PEAK_AMP_CTL_SIDE1)
39648 #define G_PEAK_AMP_CTL_SIDE1(x) (((x) >> S_PEAK_AMP_CTL_SIDE1) & M_PEAK_AMP_CTL_SIDE1)
39650 #define S_SXMCVREF_0_3 4
39651 #define M_SXMCVREF_0_3 0xfU
39652 #define V_SXMCVREF_0_3(x) ((x) << S_SXMCVREF_0_3)
39653 #define G_SXMCVREF_0_3(x) (((x) >> S_SXMCVREF_0_3) & M_SXMCVREF_0_3)
39655 #define S_SXPODVREF 3
39656 #define V_SXPODVREF(x) ((x) << S_SXPODVREF)
39657 #define F_SXPODVREF V_SXPODVREF(1U)
39659 #define S_DISABLE_TERMINATION 2
39660 #define V_DISABLE_TERMINATION(x) ((x) << S_DISABLE_TERMINATION)
39661 #define F_DISABLE_TERMINATION V_DISABLE_TERMINATION(1U)
39663 #define S_READ_CENTERING_MODE 0
39664 #define M_READ_CENTERING_MODE 0x3U
39665 #define V_READ_CENTERING_MODE(x) ((x) << S_READ_CENTERING_MODE)
39666 #define G_READ_CENTERING_MODE(x) (((x) >> S_READ_CENTERING_MODE) & M_READ_CENTERING_MODE)
39668 #define A_MC_DDRPHY_DP18_SYSCLK_PR 0x4401c
39670 #define S_SYSCLK_PHASE_ALIGN_RESET 6
39671 #define V_SYSCLK_PHASE_ALIGN_RESET(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESET)
39672 #define F_SYSCLK_PHASE_ALIGN_RESET V_SYSCLK_PHASE_ALIGN_RESET(1U)
39674 #define A_MC_DDRPHY_DP18_DFT_DIG_EYE 0x44020
39676 #define S_DIGITAL_EYE_EN 15
39677 #define V_DIGITAL_EYE_EN(x) ((x) << S_DIGITAL_EYE_EN)
39678 #define F_DIGITAL_EYE_EN V_DIGITAL_EYE_EN(1U)
39681 #define V_BUMP(x) ((x) << S_BUMP)
39682 #define F_BUMP V_BUMP(1U)
39684 #define S_TRIG_PERIOD 13
39685 #define V_TRIG_PERIOD(x) ((x) << S_TRIG_PERIOD)
39686 #define F_TRIG_PERIOD V_TRIG_PERIOD(1U)
39688 #define S_CNTL_POL 12
39689 #define V_CNTL_POL(x) ((x) << S_CNTL_POL)
39690 #define F_CNTL_POL V_CNTL_POL(1U)
39692 #define S_CNTL_SRC 8
39693 #define V_CNTL_SRC(x) ((x) << S_CNTL_SRC)
39694 #define F_CNTL_SRC V_CNTL_SRC(1U)
39696 #define S_DIGITAL_EYE_VALUE 0
39697 #define M_DIGITAL_EYE_VALUE 0xffU
39698 #define V_DIGITAL_EYE_VALUE(x) ((x) << S_DIGITAL_EYE_VALUE)
39699 #define G_DIGITAL_EYE_VALUE(x) (((x) >> S_DIGITAL_EYE_VALUE) & M_DIGITAL_EYE_VALUE)
39701 #define A_MC_DDRPHY_DP18_DQS_RD_PHASE_SELECT_RANK_PAIR 0x44024
39703 #define S_DQSCLK_SELECT0 14
39704 #define M_DQSCLK_SELECT0 0x3U
39705 #define V_DQSCLK_SELECT0(x) ((x) << S_DQSCLK_SELECT0)
39706 #define G_DQSCLK_SELECT0(x) (((x) >> S_DQSCLK_SELECT0) & M_DQSCLK_SELECT0)
39708 #define S_RDCLK_SELECT0 12
39709 #define M_RDCLK_SELECT0 0x3U
39710 #define V_RDCLK_SELECT0(x) ((x) << S_RDCLK_SELECT0)
39711 #define G_RDCLK_SELECT0(x) (((x) >> S_RDCLK_SELECT0) & M_RDCLK_SELECT0)
39713 #define S_DQSCLK_SELECT1 10
39714 #define M_DQSCLK_SELECT1 0x3U
39715 #define V_DQSCLK_SELECT1(x) ((x) << S_DQSCLK_SELECT1)
39716 #define G_DQSCLK_SELECT1(x) (((x) >> S_DQSCLK_SELECT1) & M_DQSCLK_SELECT1)
39718 #define S_RDCLK_SELECT1 8
39719 #define M_RDCLK_SELECT1 0x3U
39720 #define V_RDCLK_SELECT1(x) ((x) << S_RDCLK_SELECT1)
39721 #define G_RDCLK_SELECT1(x) (((x) >> S_RDCLK_SELECT1) & M_RDCLK_SELECT1)
39723 #define S_DQSCLK_SELECT2 6
39724 #define M_DQSCLK_SELECT2 0x3U
39725 #define V_DQSCLK_SELECT2(x) ((x) << S_DQSCLK_SELECT2)
39726 #define G_DQSCLK_SELECT2(x) (((x) >> S_DQSCLK_SELECT2) & M_DQSCLK_SELECT2)
39728 #define S_RDCLK_SELECT2 4
39729 #define M_RDCLK_SELECT2 0x3U
39730 #define V_RDCLK_SELECT2(x) ((x) << S_RDCLK_SELECT2)
39731 #define G_RDCLK_SELECT2(x) (((x) >> S_RDCLK_SELECT2) & M_RDCLK_SELECT2)
39733 #define S_DQSCLK_SELECT3 2
39734 #define M_DQSCLK_SELECT3 0x3U
39735 #define V_DQSCLK_SELECT3(x) ((x) << S_DQSCLK_SELECT3)
39736 #define G_DQSCLK_SELECT3(x) (((x) >> S_DQSCLK_SELECT3) & M_DQSCLK_SELECT3)
39738 #define S_RDCLK_SELECT3 0
39739 #define M_RDCLK_SELECT3 0x3U
39740 #define V_RDCLK_SELECT3(x) ((x) << S_RDCLK_SELECT3)
39741 #define G_RDCLK_SELECT3(x) (((x) >> S_RDCLK_SELECT3) & M_RDCLK_SELECT3)
39743 #define A_MC_DDRPHY_DP18_DRIFT_LIMITS 0x44028
39745 #define S_MIN_RD_EYE_SIZE 8
39746 #define M_MIN_RD_EYE_SIZE 0x3fU
39747 #define V_MIN_RD_EYE_SIZE(x) ((x) << S_MIN_RD_EYE_SIZE)
39748 #define G_MIN_RD_EYE_SIZE(x) (((x) >> S_MIN_RD_EYE_SIZE) & M_MIN_RD_EYE_SIZE)
39750 #define S_MAX_DQS_DRIFT 0
39751 #define M_MAX_DQS_DRIFT 0x3fU
39752 #define V_MAX_DQS_DRIFT(x) ((x) << S_MAX_DQS_DRIFT)
39753 #define G_MAX_DQS_DRIFT(x) (((x) >> S_MAX_DQS_DRIFT) & M_MAX_DQS_DRIFT)
39755 #define A_MC_DDRPHY_DP18_DEBUG_SEL 0x4402c
39757 #define S_HS_PROBE_A_SEL 11
39758 #define M_HS_PROBE_A_SEL 0x1fU
39759 #define V_HS_PROBE_A_SEL(x) ((x) << S_HS_PROBE_A_SEL)
39760 #define G_HS_PROBE_A_SEL(x) (((x) >> S_HS_PROBE_A_SEL) & M_HS_PROBE_A_SEL)
39762 #define S_HS_PROBE_B_SEL 6
39763 #define M_HS_PROBE_B_SEL 0x1fU
39764 #define V_HS_PROBE_B_SEL(x) ((x) << S_HS_PROBE_B_SEL)
39765 #define G_HS_PROBE_B_SEL(x) (((x) >> S_HS_PROBE_B_SEL) & M_HS_PROBE_B_SEL)
39767 #define S_RD_DEBUG_SEL 3
39768 #define M_RD_DEBUG_SEL 0x7U
39769 #define V_RD_DEBUG_SEL(x) ((x) << S_RD_DEBUG_SEL)
39770 #define G_RD_DEBUG_SEL(x) (((x) >> S_RD_DEBUG_SEL) & M_RD_DEBUG_SEL)
39772 #define S_WR_DEBUG_SEL 0
39773 #define M_WR_DEBUG_SEL 0x7U
39774 #define V_WR_DEBUG_SEL(x) ((x) << S_WR_DEBUG_SEL)
39775 #define G_WR_DEBUG_SEL(x) (((x) >> S_WR_DEBUG_SEL) & M_WR_DEBUG_SEL)
39777 #define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET0_RANK_PAIR 0x44030
39779 #define S_OFFSET_BITS1_7 8
39780 #define M_OFFSET_BITS1_7 0x7fU
39781 #define V_OFFSET_BITS1_7(x) ((x) << S_OFFSET_BITS1_7)
39782 #define G_OFFSET_BITS1_7(x) (((x) >> S_OFFSET_BITS1_7) & M_OFFSET_BITS1_7)
39784 #define S_OFFSET_BITS9_15 0
39785 #define M_OFFSET_BITS9_15 0x7fU
39786 #define V_OFFSET_BITS9_15(x) ((x) << S_OFFSET_BITS9_15)
39787 #define G_OFFSET_BITS9_15(x) (((x) >> S_OFFSET_BITS9_15) & M_OFFSET_BITS9_15)
39789 #define A_MC_DDRPHY_DP18_READ_DELAY_OFFSET1_RANK_PAIR 0x44034
39790 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS0 0x44038
39792 #define S_LEADING_EDGE_NOT_FOUND_0 0
39793 #define M_LEADING_EDGE_NOT_FOUND_0 0xffffU
39794 #define V_LEADING_EDGE_NOT_FOUND_0(x) ((x) << S_LEADING_EDGE_NOT_FOUND_0)
39795 #define G_LEADING_EDGE_NOT_FOUND_0(x) (((x) >> S_LEADING_EDGE_NOT_FOUND_0) & M_LEADING_EDGE_NOT_FOUND_0)
39797 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS1 0x4403c
39799 #define S_LEADING_EDGE_NOT_FOUND_1 8
39800 #define M_LEADING_EDGE_NOT_FOUND_1 0xffU
39801 #define V_LEADING_EDGE_NOT_FOUND_1(x) ((x) << S_LEADING_EDGE_NOT_FOUND_1)
39802 #define G_LEADING_EDGE_NOT_FOUND_1(x) (((x) >> S_LEADING_EDGE_NOT_FOUND_1) & M_LEADING_EDGE_NOT_FOUND_1)
39804 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS2 0x44040
39806 #define S_TRAILING_EDGE_NOT_FOUND 0
39807 #define M_TRAILING_EDGE_NOT_FOUND 0xffffU
39808 #define V_TRAILING_EDGE_NOT_FOUND(x) ((x) << S_TRAILING_EDGE_NOT_FOUND)
39809 #define G_TRAILING_EDGE_NOT_FOUND(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND) & M_TRAILING_EDGE_NOT_FOUND)
39811 #define A_MC_DDRPHY_DP18_RD_LVL_STATUS3 0x44044
39813 #define S_TRAILING_EDGE_NOT_FOUND_16_23 8
39814 #define M_TRAILING_EDGE_NOT_FOUND_16_23 0xffU
39815 #define V_TRAILING_EDGE_NOT_FOUND_16_23(x) ((x) << S_TRAILING_EDGE_NOT_FOUND_16_23)
39816 #define G_TRAILING_EDGE_NOT_FOUND_16_23(x) (((x) >> S_TRAILING_EDGE_NOT_FOUND_16_23) & M_TRAILING_EDGE_NOT_FOUND_16_23)
39818 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG5 0x44048
39820 #define S_DYN_POWER_CNTL_EN 15
39821 #define V_DYN_POWER_CNTL_EN(x) ((x) << S_DYN_POWER_CNTL_EN)
39822 #define F_DYN_POWER_CNTL_EN V_DYN_POWER_CNTL_EN(1U)
39824 #define S_DYN_MCTERM_CNTL_EN 14
39825 #define V_DYN_MCTERM_CNTL_EN(x) ((x) << S_DYN_MCTERM_CNTL_EN)
39826 #define F_DYN_MCTERM_CNTL_EN V_DYN_MCTERM_CNTL_EN(1U)
39828 #define S_DYN_RX_GATE_CNTL_EN 13
39829 #define V_DYN_RX_GATE_CNTL_EN(x) ((x) << S_DYN_RX_GATE_CNTL_EN)
39830 #define F_DYN_RX_GATE_CNTL_EN V_DYN_RX_GATE_CNTL_EN(1U)
39832 #define S_CALGATE_ON 12
39833 #define V_CALGATE_ON(x) ((x) << S_CALGATE_ON)
39834 #define F_CALGATE_ON V_CALGATE_ON(1U)
39836 #define S_PER_RDCLK_UPDATE_DIS 11
39837 #define V_PER_RDCLK_UPDATE_DIS(x) ((x) << S_PER_RDCLK_UPDATE_DIS)
39838 #define F_PER_RDCLK_UPDATE_DIS V_PER_RDCLK_UPDATE_DIS(1U)
39840 #define A_MC_DDRPHY_DP18_DQS_GATE_DELAY_RP 0x4404c
39842 #define S_DQS_GATE_DELAY_N0 12
39843 #define M_DQS_GATE_DELAY_N0 0x7U
39844 #define V_DQS_GATE_DELAY_N0(x) ((x) << S_DQS_GATE_DELAY_N0)
39845 #define G_DQS_GATE_DELAY_N0(x) (((x) >> S_DQS_GATE_DELAY_N0) & M_DQS_GATE_DELAY_N0)
39847 #define S_DQS_GATE_DELAY_N1 8
39848 #define M_DQS_GATE_DELAY_N1 0x7U
39849 #define V_DQS_GATE_DELAY_N1(x) ((x) << S_DQS_GATE_DELAY_N1)
39850 #define G_DQS_GATE_DELAY_N1(x) (((x) >> S_DQS_GATE_DELAY_N1) & M_DQS_GATE_DELAY_N1)
39852 #define S_DQS_GATE_DELAY_N2 4
39853 #define M_DQS_GATE_DELAY_N2 0x7U
39854 #define V_DQS_GATE_DELAY_N2(x) ((x) << S_DQS_GATE_DELAY_N2)
39855 #define G_DQS_GATE_DELAY_N2(x) (((x) >> S_DQS_GATE_DELAY_N2) & M_DQS_GATE_DELAY_N2)
39857 #define S_DQS_GATE_DELAY_N3 0
39858 #define M_DQS_GATE_DELAY_N3 0x7U
39859 #define V_DQS_GATE_DELAY_N3(x) ((x) << S_DQS_GATE_DELAY_N3)
39860 #define G_DQS_GATE_DELAY_N3(x) (((x) >> S_DQS_GATE_DELAY_N3) & M_DQS_GATE_DELAY_N3)
39862 #define A_MC_DDRPHY_DP18_RD_STATUS0 0x44050
39864 #define S_NO_EYE_DETECTED 15
39865 #define V_NO_EYE_DETECTED(x) ((x) << S_NO_EYE_DETECTED)
39866 #define F_NO_EYE_DETECTED V_NO_EYE_DETECTED(1U)
39868 #define S_LEADING_EDGE_FOUND 14
39869 #define V_LEADING_EDGE_FOUND(x) ((x) << S_LEADING_EDGE_FOUND)
39870 #define F_LEADING_EDGE_FOUND V_LEADING_EDGE_FOUND(1U)
39872 #define S_TRAILING_EDGE_FOUND 13
39873 #define V_TRAILING_EDGE_FOUND(x) ((x) << S_TRAILING_EDGE_FOUND)
39874 #define F_TRAILING_EDGE_FOUND V_TRAILING_EDGE_FOUND(1U)
39876 #define S_INCOMPLETE_RD_CAL_N0 12
39877 #define V_INCOMPLETE_RD_CAL_N0(x) ((x) << S_INCOMPLETE_RD_CAL_N0)
39878 #define F_INCOMPLETE_RD_CAL_N0 V_INCOMPLETE_RD_CAL_N0(1U)
39880 #define S_INCOMPLETE_RD_CAL_N1 11
39881 #define V_INCOMPLETE_RD_CAL_N1(x) ((x) << S_INCOMPLETE_RD_CAL_N1)
39882 #define F_INCOMPLETE_RD_CAL_N1 V_INCOMPLETE_RD_CAL_N1(1U)
39884 #define S_INCOMPLETE_RD_CAL_N2 10
39885 #define V_INCOMPLETE_RD_CAL_N2(x) ((x) << S_INCOMPLETE_RD_CAL_N2)
39886 #define F_INCOMPLETE_RD_CAL_N2 V_INCOMPLETE_RD_CAL_N2(1U)
39888 #define S_INCOMPLETE_RD_CAL_N3 9
39889 #define V_INCOMPLETE_RD_CAL_N3(x) ((x) << S_INCOMPLETE_RD_CAL_N3)
39890 #define F_INCOMPLETE_RD_CAL_N3 V_INCOMPLETE_RD_CAL_N3(1U)
39892 #define S_COARSE_PATTERN_ERR_N0 8
39893 #define V_COARSE_PATTERN_ERR_N0(x) ((x) << S_COARSE_PATTERN_ERR_N0)
39894 #define F_COARSE_PATTERN_ERR_N0 V_COARSE_PATTERN_ERR_N0(1U)
39896 #define S_COARSE_PATTERN_ERR_N1 7
39897 #define V_COARSE_PATTERN_ERR_N1(x) ((x) << S_COARSE_PATTERN_ERR_N1)
39898 #define F_COARSE_PATTERN_ERR_N1 V_COARSE_PATTERN_ERR_N1(1U)
39900 #define S_COARSE_PATTERN_ERR_N2 6
39901 #define V_COARSE_PATTERN_ERR_N2(x) ((x) << S_COARSE_PATTERN_ERR_N2)
39902 #define F_COARSE_PATTERN_ERR_N2 V_COARSE_PATTERN_ERR_N2(1U)
39904 #define S_COARSE_PATTERN_ERR_N3 5
39905 #define V_COARSE_PATTERN_ERR_N3(x) ((x) << S_COARSE_PATTERN_ERR_N3)
39906 #define F_COARSE_PATTERN_ERR_N3 V_COARSE_PATTERN_ERR_N3(1U)
39908 #define S_EYE_CLIPPING 4
39909 #define V_EYE_CLIPPING(x) ((x) << S_EYE_CLIPPING)
39910 #define F_EYE_CLIPPING V_EYE_CLIPPING(1U)
39913 #define V_NO_DQS(x) ((x) << S_NO_DQS)
39914 #define F_NO_DQS V_NO_DQS(1U)
39916 #define S_NO_LOCK 2
39917 #define V_NO_LOCK(x) ((x) << S_NO_LOCK)
39918 #define F_NO_LOCK V_NO_LOCK(1U)
39920 #define S_DRIFT_ERROR 1
39921 #define V_DRIFT_ERROR(x) ((x) << S_DRIFT_ERROR)
39922 #define F_DRIFT_ERROR V_DRIFT_ERROR(1U)
39924 #define S_MIN_EYE 0
39925 #define V_MIN_EYE(x) ((x) << S_MIN_EYE)
39926 #define F_MIN_EYE V_MIN_EYE(1U)
39928 #define A_MC_DDRPHY_DP18_RD_ERROR_MASK0 0x44054
39930 #define S_NO_EYE_DETECTED_MASK 15
39931 #define V_NO_EYE_DETECTED_MASK(x) ((x) << S_NO_EYE_DETECTED_MASK)
39932 #define F_NO_EYE_DETECTED_MASK V_NO_EYE_DETECTED_MASK(1U)
39934 #define S_LEADING_EDGE_FOUND_MASK 14
39935 #define V_LEADING_EDGE_FOUND_MASK(x) ((x) << S_LEADING_EDGE_FOUND_MASK)
39936 #define F_LEADING_EDGE_FOUND_MASK V_LEADING_EDGE_FOUND_MASK(1U)
39938 #define S_TRAILING_EDGE_FOUND_MASK 13
39939 #define V_TRAILING_EDGE_FOUND_MASK(x) ((x) << S_TRAILING_EDGE_FOUND_MASK)
39940 #define F_TRAILING_EDGE_FOUND_MASK V_TRAILING_EDGE_FOUND_MASK(1U)
39942 #define S_INCOMPLETE_RD_CAL_N0_MASK 12
39943 #define V_INCOMPLETE_RD_CAL_N0_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N0_MASK)
39944 #define F_INCOMPLETE_RD_CAL_N0_MASK V_INCOMPLETE_RD_CAL_N0_MASK(1U)
39946 #define S_INCOMPLETE_RD_CAL_N1_MASK 11
39947 #define V_INCOMPLETE_RD_CAL_N1_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N1_MASK)
39948 #define F_INCOMPLETE_RD_CAL_N1_MASK V_INCOMPLETE_RD_CAL_N1_MASK(1U)
39950 #define S_INCOMPLETE_RD_CAL_N2_MASK 10
39951 #define V_INCOMPLETE_RD_CAL_N2_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N2_MASK)
39952 #define F_INCOMPLETE_RD_CAL_N2_MASK V_INCOMPLETE_RD_CAL_N2_MASK(1U)
39954 #define S_INCOMPLETE_RD_CAL_N3_MASK 9
39955 #define V_INCOMPLETE_RD_CAL_N3_MASK(x) ((x) << S_INCOMPLETE_RD_CAL_N3_MASK)
39956 #define F_INCOMPLETE_RD_CAL_N3_MASK V_INCOMPLETE_RD_CAL_N3_MASK(1U)
39958 #define S_COARSE_PATTERN_ERR_N0_MASK 8
39959 #define V_COARSE_PATTERN_ERR_N0_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N0_MASK)
39960 #define F_COARSE_PATTERN_ERR_N0_MASK V_COARSE_PATTERN_ERR_N0_MASK(1U)
39962 #define S_COARSE_PATTERN_ERR_N1_MASK 7
39963 #define V_COARSE_PATTERN_ERR_N1_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N1_MASK)
39964 #define F_COARSE_PATTERN_ERR_N1_MASK V_COARSE_PATTERN_ERR_N1_MASK(1U)
39966 #define S_COARSE_PATTERN_ERR_N2_MASK 6
39967 #define V_COARSE_PATTERN_ERR_N2_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N2_MASK)
39968 #define F_COARSE_PATTERN_ERR_N2_MASK V_COARSE_PATTERN_ERR_N2_MASK(1U)
39970 #define S_COARSE_PATTERN_ERR_N3_MASK 5
39971 #define V_COARSE_PATTERN_ERR_N3_MASK(x) ((x) << S_COARSE_PATTERN_ERR_N3_MASK)
39972 #define F_COARSE_PATTERN_ERR_N3_MASK V_COARSE_PATTERN_ERR_N3_MASK(1U)
39974 #define S_EYE_CLIPPING_MASK 4
39975 #define V_EYE_CLIPPING_MASK(x) ((x) << S_EYE_CLIPPING_MASK)
39976 #define F_EYE_CLIPPING_MASK V_EYE_CLIPPING_MASK(1U)
39978 #define S_NO_DQS_MASK 3
39979 #define V_NO_DQS_MASK(x) ((x) << S_NO_DQS_MASK)
39980 #define F_NO_DQS_MASK V_NO_DQS_MASK(1U)
39982 #define S_NO_LOCK_MASK 2
39983 #define V_NO_LOCK_MASK(x) ((x) << S_NO_LOCK_MASK)
39984 #define F_NO_LOCK_MASK V_NO_LOCK_MASK(1U)
39986 #define S_DRIFT_ERROR_MASK 1
39987 #define V_DRIFT_ERROR_MASK(x) ((x) << S_DRIFT_ERROR_MASK)
39988 #define F_DRIFT_ERROR_MASK V_DRIFT_ERROR_MASK(1U)
39990 #define S_MIN_EYE_MASK 0
39991 #define V_MIN_EYE_MASK(x) ((x) << S_MIN_EYE_MASK)
39992 #define F_MIN_EYE_MASK V_MIN_EYE_MASK(1U)
39994 #define A_MC_DDRPHY_DP18_WR_LVL_STATUS0 0x4405c
39996 #define S_CLK_LEVEL 14
39997 #define M_CLK_LEVEL 0x3U
39998 #define V_CLK_LEVEL(x) ((x) << S_CLK_LEVEL)
39999 #define G_CLK_LEVEL(x) (((x) >> S_CLK_LEVEL) & M_CLK_LEVEL)
40001 #define S_FINE_STEPPING 13
40002 #define V_FINE_STEPPING(x) ((x) << S_FINE_STEPPING)
40003 #define F_FINE_STEPPING V_FINE_STEPPING(1U)
40006 #define V_DONE(x) ((x) << S_DONE)
40007 #define F_DONE V_DONE(1U)
40009 #define S_WL_ERR_CLK16_ST 11
40010 #define V_WL_ERR_CLK16_ST(x) ((x) << S_WL_ERR_CLK16_ST)
40011 #define F_WL_ERR_CLK16_ST V_WL_ERR_CLK16_ST(1U)
40013 #define S_WL_ERR_CLK18_ST 10
40014 #define V_WL_ERR_CLK18_ST(x) ((x) << S_WL_ERR_CLK18_ST)
40015 #define F_WL_ERR_CLK18_ST V_WL_ERR_CLK18_ST(1U)
40017 #define S_WL_ERR_CLK20_ST 9
40018 #define V_WL_ERR_CLK20_ST(x) ((x) << S_WL_ERR_CLK20_ST)
40019 #define F_WL_ERR_CLK20_ST V_WL_ERR_CLK20_ST(1U)
40021 #define S_WL_ERR_CLK22_ST 8
40022 #define V_WL_ERR_CLK22_ST(x) ((x) << S_WL_ERR_CLK22_ST)
40023 #define F_WL_ERR_CLK22_ST V_WL_ERR_CLK22_ST(1U)
40025 #define S_ZERO_DETECTED 7
40026 #define V_ZERO_DETECTED(x) ((x) << S_ZERO_DETECTED)
40027 #define F_ZERO_DETECTED V_ZERO_DETECTED(1U)
40029 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS0 0x44060
40031 #define S_BIT_CENTERED 11
40032 #define M_BIT_CENTERED 0x1fU
40033 #define V_BIT_CENTERED(x) ((x) << S_BIT_CENTERED)
40034 #define G_BIT_CENTERED(x) (((x) >> S_BIT_CENTERED) & M_BIT_CENTERED)
40036 #define S_SMALL_STEP_LEFT 10
40037 #define V_SMALL_STEP_LEFT(x) ((x) << S_SMALL_STEP_LEFT)
40038 #define F_SMALL_STEP_LEFT V_SMALL_STEP_LEFT(1U)
40040 #define S_BIG_STEP_RIGHT 9
40041 #define V_BIG_STEP_RIGHT(x) ((x) << S_BIG_STEP_RIGHT)
40042 #define F_BIG_STEP_RIGHT V_BIG_STEP_RIGHT(1U)
40044 #define S_MATCH_STEP_RIGHT 8
40045 #define V_MATCH_STEP_RIGHT(x) ((x) << S_MATCH_STEP_RIGHT)
40046 #define F_MATCH_STEP_RIGHT V_MATCH_STEP_RIGHT(1U)
40048 #define S_JUMP_BACK_RIGHT 7
40049 #define V_JUMP_BACK_RIGHT(x) ((x) << S_JUMP_BACK_RIGHT)
40050 #define F_JUMP_BACK_RIGHT V_JUMP_BACK_RIGHT(1U)
40052 #define S_SMALL_STEP_RIGHT 6
40053 #define V_SMALL_STEP_RIGHT(x) ((x) << S_SMALL_STEP_RIGHT)
40054 #define F_SMALL_STEP_RIGHT V_SMALL_STEP_RIGHT(1U)
40057 #define V_DDONE(x) ((x) << S_DDONE)
40058 #define F_DDONE V_DDONE(1U)
40060 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS1 0x44064
40062 #define S_FW_LEFT_SIDE 5
40063 #define M_FW_LEFT_SIDE 0x7ffU
40064 #define V_FW_LEFT_SIDE(x) ((x) << S_FW_LEFT_SIDE)
40065 #define G_FW_LEFT_SIDE(x) (((x) >> S_FW_LEFT_SIDE) & M_FW_LEFT_SIDE)
40067 #define A_MC_DDRPHY_DP18_WR_CNTR_STATUS2 0x44068
40069 #define S_FW_RIGHT_SIDE 5
40070 #define M_FW_RIGHT_SIDE 0x7ffU
40071 #define V_FW_RIGHT_SIDE(x) ((x) << S_FW_RIGHT_SIDE)
40072 #define G_FW_RIGHT_SIDE(x) (((x) >> S_FW_RIGHT_SIDE) & M_FW_RIGHT_SIDE)
40074 #define A_MC_DDRPHY_DP18_WR_ERROR0 0x4406c
40076 #define S_WL_ERR_CLK16 15
40077 #define V_WL_ERR_CLK16(x) ((x) << S_WL_ERR_CLK16)
40078 #define F_WL_ERR_CLK16 V_WL_ERR_CLK16(1U)
40080 #define S_WL_ERR_CLK18 14
40081 #define V_WL_ERR_CLK18(x) ((x) << S_WL_ERR_CLK18)
40082 #define F_WL_ERR_CLK18 V_WL_ERR_CLK18(1U)
40084 #define S_WL_ERR_CLK20 13
40085 #define V_WL_ERR_CLK20(x) ((x) << S_WL_ERR_CLK20)
40086 #define F_WL_ERR_CLK20 V_WL_ERR_CLK20(1U)
40088 #define S_WL_ERR_CLK22 12
40089 #define V_WL_ERR_CLK22(x) ((x) << S_WL_ERR_CLK22)
40090 #define F_WL_ERR_CLK22 V_WL_ERR_CLK22(1U)
40092 #define S_VALID_NS_BIG_L 7
40093 #define V_VALID_NS_BIG_L(x) ((x) << S_VALID_NS_BIG_L)
40094 #define F_VALID_NS_BIG_L V_VALID_NS_BIG_L(1U)
40096 #define S_INVALID_NS_SMALL_L 6
40097 #define V_INVALID_NS_SMALL_L(x) ((x) << S_INVALID_NS_SMALL_L)
40098 #define F_INVALID_NS_SMALL_L V_INVALID_NS_SMALL_L(1U)
40100 #define S_VALID_NS_BIG_R 5
40101 #define V_VALID_NS_BIG_R(x) ((x) << S_VALID_NS_BIG_R)
40102 #define F_VALID_NS_BIG_R V_VALID_NS_BIG_R(1U)
40104 #define S_INVALID_NS_BIG_R 4
40105 #define V_INVALID_NS_BIG_R(x) ((x) << S_INVALID_NS_BIG_R)
40106 #define F_INVALID_NS_BIG_R V_INVALID_NS_BIG_R(1U)
40108 #define S_VALID_NS_JUMP_BACK 3
40109 #define V_VALID_NS_JUMP_BACK(x) ((x) << S_VALID_NS_JUMP_BACK)
40110 #define F_VALID_NS_JUMP_BACK V_VALID_NS_JUMP_BACK(1U)
40112 #define S_INVALID_NS_SMALL_R 2
40113 #define V_INVALID_NS_SMALL_R(x) ((x) << S_INVALID_NS_SMALL_R)
40114 #define F_INVALID_NS_SMALL_R V_INVALID_NS_SMALL_R(1U)
40116 #define S_OFFSET_ERR 1
40117 #define V_OFFSET_ERR(x) ((x) << S_OFFSET_ERR)
40118 #define F_OFFSET_ERR V_OFFSET_ERR(1U)
40120 #define A_MC_DDRPHY_DP18_WR_ERROR_MASK0 0x44070
40122 #define S_WL_ERR_CLK16_MASK 15
40123 #define V_WL_ERR_CLK16_MASK(x) ((x) << S_WL_ERR_CLK16_MASK)
40124 #define F_WL_ERR_CLK16_MASK V_WL_ERR_CLK16_MASK(1U)
40126 #define S_WL_ERR_CLK18_MASK 14
40127 #define V_WL_ERR_CLK18_MASK(x) ((x) << S_WL_ERR_CLK18_MASK)
40128 #define F_WL_ERR_CLK18_MASK V_WL_ERR_CLK18_MASK(1U)
40130 #define S_WL_ERR_CLK20_MASK 13
40131 #define V_WL_ERR_CLK20_MASK(x) ((x) << S_WL_ERR_CLK20_MASK)
40132 #define F_WL_ERR_CLK20_MASK V_WL_ERR_CLK20_MASK(1U)
40134 #define S_WR_ERR_CLK22_MASK 12
40135 #define V_WR_ERR_CLK22_MASK(x) ((x) << S_WR_ERR_CLK22_MASK)
40136 #define F_WR_ERR_CLK22_MASK V_WR_ERR_CLK22_MASK(1U)
40138 #define S_VALID_NS_BIG_L_MASK 7
40139 #define V_VALID_NS_BIG_L_MASK(x) ((x) << S_VALID_NS_BIG_L_MASK)
40140 #define F_VALID_NS_BIG_L_MASK V_VALID_NS_BIG_L_MASK(1U)
40142 #define S_INVALID_NS_SMALL_L_MASK 6
40143 #define V_INVALID_NS_SMALL_L_MASK(x) ((x) << S_INVALID_NS_SMALL_L_MASK)
40144 #define F_INVALID_NS_SMALL_L_MASK V_INVALID_NS_SMALL_L_MASK(1U)
40146 #define S_VALID_NS_BIG_R_MASK 5
40147 #define V_VALID_NS_BIG_R_MASK(x) ((x) << S_VALID_NS_BIG_R_MASK)
40148 #define F_VALID_NS_BIG_R_MASK V_VALID_NS_BIG_R_MASK(1U)
40150 #define S_INVALID_NS_BIG_R_MASK 4
40151 #define V_INVALID_NS_BIG_R_MASK(x) ((x) << S_INVALID_NS_BIG_R_MASK)
40152 #define F_INVALID_NS_BIG_R_MASK V_INVALID_NS_BIG_R_MASK(1U)
40154 #define S_VALID_NS_JUMP_BACK_MASK 3
40155 #define V_VALID_NS_JUMP_BACK_MASK(x) ((x) << S_VALID_NS_JUMP_BACK_MASK)
40156 #define F_VALID_NS_JUMP_BACK_MASK V_VALID_NS_JUMP_BACK_MASK(1U)
40158 #define S_INVALID_NS_SMALL_R_MASK 2
40159 #define V_INVALID_NS_SMALL_R_MASK(x) ((x) << S_INVALID_NS_SMALL_R_MASK)
40160 #define F_INVALID_NS_SMALL_R_MASK V_INVALID_NS_SMALL_R_MASK(1U)
40162 #define S_OFFSET_ERR_MASK 1
40163 #define V_OFFSET_ERR_MASK(x) ((x) << S_OFFSET_ERR_MASK)
40164 #define F_OFFSET_ERR_MASK V_OFFSET_ERR_MASK(1U)
40166 #define A_MC_DDRPHY_DP18_DFT_WRAP_STATUS 0x44074
40168 #define S_CHECKER_RESET 14
40169 #define V_CHECKER_RESET(x) ((x) << S_CHECKER_RESET)
40170 #define F_CHECKER_RESET V_CHECKER_RESET(1U)
40172 #define S_DP18_DFT_SYNC 6
40173 #define M_DP18_DFT_SYNC 0x3fU
40174 #define V_DP18_DFT_SYNC(x) ((x) << S_DP18_DFT_SYNC)
40175 #define G_DP18_DFT_SYNC(x) (((x) >> S_DP18_DFT_SYNC) & M_DP18_DFT_SYNC)
40178 #define M_ERROR 0x3fU
40179 #define V_ERROR(x) ((x) << S_ERROR)
40180 #define G_ERROR(x) (((x) >> S_ERROR) & M_ERROR)
40182 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG0 0x44078
40183 #define A_MC_DDRPHY_DP18_DQSCLK_PR0_RANK_PAIR 0x440c0
40185 #define S_DQSCLK_ROT_CLK_N0_N2 8
40186 #define M_DQSCLK_ROT_CLK_N0_N2 0x7fU
40187 #define V_DQSCLK_ROT_CLK_N0_N2(x) ((x) << S_DQSCLK_ROT_CLK_N0_N2)
40188 #define G_DQSCLK_ROT_CLK_N0_N2(x) (((x) >> S_DQSCLK_ROT_CLK_N0_N2) & M_DQSCLK_ROT_CLK_N0_N2)
40190 #define S_DQSCLK_ROT_CLK_N1_N3 0
40191 #define M_DQSCLK_ROT_CLK_N1_N3 0x7fU
40192 #define V_DQSCLK_ROT_CLK_N1_N3(x) ((x) << S_DQSCLK_ROT_CLK_N1_N3)
40193 #define G_DQSCLK_ROT_CLK_N1_N3(x) (((x) >> S_DQSCLK_ROT_CLK_N1_N3) & M_DQSCLK_ROT_CLK_N1_N3)
40195 #define A_MC_DDRPHY_DP18_DQSCLK_PR1_RANK_PAIR 0x440c4
40196 #define A_MC_DDRPHY_DP18_PATTERN_POS_0 0x440c8
40198 #define S_MEMINTD00_POS 14
40199 #define M_MEMINTD00_POS 0x3U
40200 #define V_MEMINTD00_POS(x) ((x) << S_MEMINTD00_POS)
40201 #define G_MEMINTD00_POS(x) (((x) >> S_MEMINTD00_POS) & M_MEMINTD00_POS)
40203 #define S_MEMINTD01_PO 12
40204 #define M_MEMINTD01_PO 0x3U
40205 #define V_MEMINTD01_PO(x) ((x) << S_MEMINTD01_PO)
40206 #define G_MEMINTD01_PO(x) (((x) >> S_MEMINTD01_PO) & M_MEMINTD01_PO)
40208 #define S_MEMINTD02_POS 10
40209 #define M_MEMINTD02_POS 0x3U
40210 #define V_MEMINTD02_POS(x) ((x) << S_MEMINTD02_POS)
40211 #define G_MEMINTD02_POS(x) (((x) >> S_MEMINTD02_POS) & M_MEMINTD02_POS)
40213 #define S_MEMINTD03_POS 8
40214 #define M_MEMINTD03_POS 0x3U
40215 #define V_MEMINTD03_POS(x) ((x) << S_MEMINTD03_POS)
40216 #define G_MEMINTD03_POS(x) (((x) >> S_MEMINTD03_POS) & M_MEMINTD03_POS)
40218 #define S_MEMINTD04_POS 6
40219 #define M_MEMINTD04_POS 0x3U
40220 #define V_MEMINTD04_POS(x) ((x) << S_MEMINTD04_POS)
40221 #define G_MEMINTD04_POS(x) (((x) >> S_MEMINTD04_POS) & M_MEMINTD04_POS)
40223 #define S_MEMINTD05_POS 4
40224 #define M_MEMINTD05_POS 0x3U
40225 #define V_MEMINTD05_POS(x) ((x) << S_MEMINTD05_POS)
40226 #define G_MEMINTD05_POS(x) (((x) >> S_MEMINTD05_POS) & M_MEMINTD05_POS)
40228 #define S_MEMINTD06_POS 2
40229 #define M_MEMINTD06_POS 0x3U
40230 #define V_MEMINTD06_POS(x) ((x) << S_MEMINTD06_POS)
40231 #define G_MEMINTD06_POS(x) (((x) >> S_MEMINTD06_POS) & M_MEMINTD06_POS)
40233 #define S_MEMINTD07_POS 0
40234 #define M_MEMINTD07_POS 0x3U
40235 #define V_MEMINTD07_POS(x) ((x) << S_MEMINTD07_POS)
40236 #define G_MEMINTD07_POS(x) (((x) >> S_MEMINTD07_POS) & M_MEMINTD07_POS)
40238 #define A_MC_DDRPHY_DP18_PATTERN_POS_1 0x440cc
40240 #define S_MEMINTD08_POS 14
40241 #define M_MEMINTD08_POS 0x3U
40242 #define V_MEMINTD08_POS(x) ((x) << S_MEMINTD08_POS)
40243 #define G_MEMINTD08_POS(x) (((x) >> S_MEMINTD08_POS) & M_MEMINTD08_POS)
40245 #define S_MEMINTD09_POS 12
40246 #define M_MEMINTD09_POS 0x3U
40247 #define V_MEMINTD09_POS(x) ((x) << S_MEMINTD09_POS)
40248 #define G_MEMINTD09_POS(x) (((x) >> S_MEMINTD09_POS) & M_MEMINTD09_POS)
40250 #define S_MEMINTD10_POS 10
40251 #define M_MEMINTD10_POS 0x3U
40252 #define V_MEMINTD10_POS(x) ((x) << S_MEMINTD10_POS)
40253 #define G_MEMINTD10_POS(x) (((x) >> S_MEMINTD10_POS) & M_MEMINTD10_POS)
40255 #define S_MEMINTD11_POS 8
40256 #define M_MEMINTD11_POS 0x3U
40257 #define V_MEMINTD11_POS(x) ((x) << S_MEMINTD11_POS)
40258 #define G_MEMINTD11_POS(x) (((x) >> S_MEMINTD11_POS) & M_MEMINTD11_POS)
40260 #define S_MEMINTD12_POS 6
40261 #define M_MEMINTD12_POS 0x3U
40262 #define V_MEMINTD12_POS(x) ((x) << S_MEMINTD12_POS)
40263 #define G_MEMINTD12_POS(x) (((x) >> S_MEMINTD12_POS) & M_MEMINTD12_POS)
40265 #define S_MEMINTD13_POS 4
40266 #define M_MEMINTD13_POS 0x3U
40267 #define V_MEMINTD13_POS(x) ((x) << S_MEMINTD13_POS)
40268 #define G_MEMINTD13_POS(x) (((x) >> S_MEMINTD13_POS) & M_MEMINTD13_POS)
40270 #define S_MEMINTD14_POS 2
40271 #define M_MEMINTD14_POS 0x3U
40272 #define V_MEMINTD14_POS(x) ((x) << S_MEMINTD14_POS)
40273 #define G_MEMINTD14_POS(x) (((x) >> S_MEMINTD14_POS) & M_MEMINTD14_POS)
40275 #define S_MEMINTD15_POS 0
40276 #define M_MEMINTD15_POS 0x3U
40277 #define V_MEMINTD15_POS(x) ((x) << S_MEMINTD15_POS)
40278 #define G_MEMINTD15_POS(x) (((x) >> S_MEMINTD15_POS) & M_MEMINTD15_POS)
40280 #define A_MC_DDRPHY_DP18_PATTERN_POS_2 0x440d0
40282 #define S_MEMINTD16_POS 14
40283 #define M_MEMINTD16_POS 0x3U
40284 #define V_MEMINTD16_POS(x) ((x) << S_MEMINTD16_POS)
40285 #define G_MEMINTD16_POS(x) (((x) >> S_MEMINTD16_POS) & M_MEMINTD16_POS)
40287 #define S_MEMINTD17_POS 12
40288 #define M_MEMINTD17_POS 0x3U
40289 #define V_MEMINTD17_POS(x) ((x) << S_MEMINTD17_POS)
40290 #define G_MEMINTD17_POS(x) (((x) >> S_MEMINTD17_POS) & M_MEMINTD17_POS)
40292 #define S_MEMINTD18_POS 10
40293 #define M_MEMINTD18_POS 0x3U
40294 #define V_MEMINTD18_POS(x) ((x) << S_MEMINTD18_POS)
40295 #define G_MEMINTD18_POS(x) (((x) >> S_MEMINTD18_POS) & M_MEMINTD18_POS)
40297 #define S_MEMINTD19_POS 8
40298 #define M_MEMINTD19_POS 0x3U
40299 #define V_MEMINTD19_POS(x) ((x) << S_MEMINTD19_POS)
40300 #define G_MEMINTD19_POS(x) (((x) >> S_MEMINTD19_POS) & M_MEMINTD19_POS)
40302 #define S_MEMINTD20_POS 6
40303 #define M_MEMINTD20_POS 0x3U
40304 #define V_MEMINTD20_POS(x) ((x) << S_MEMINTD20_POS)
40305 #define G_MEMINTD20_POS(x) (((x) >> S_MEMINTD20_POS) & M_MEMINTD20_POS)
40307 #define S_MEMINTD21_POS 4
40308 #define M_MEMINTD21_POS 0x3U
40309 #define V_MEMINTD21_POS(x) ((x) << S_MEMINTD21_POS)
40310 #define G_MEMINTD21_POS(x) (((x) >> S_MEMINTD21_POS) & M_MEMINTD21_POS)
40312 #define S_MEMINTD22_POS 2
40313 #define M_MEMINTD22_POS 0x3U
40314 #define V_MEMINTD22_POS(x) ((x) << S_MEMINTD22_POS)
40315 #define G_MEMINTD22_POS(x) (((x) >> S_MEMINTD22_POS) & M_MEMINTD22_POS)
40317 #define S_MEMINTD23_POS 0
40318 #define M_MEMINTD23_POS 0x3U
40319 #define V_MEMINTD23_POS(x) ((x) << S_MEMINTD23_POS)
40320 #define G_MEMINTD23_POS(x) (((x) >> S_MEMINTD23_POS) & M_MEMINTD23_POS)
40322 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG1 0x440d4
40323 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG2 0x440d8
40324 #define A_MC_DDRPHY_DP18_DQSCLK_OFFSET 0x440dc
40326 #define S_DQS_OFFSET 8
40327 #define M_DQS_OFFSET 0x7fU
40328 #define V_DQS_OFFSET(x) ((x) << S_DQS_OFFSET)
40329 #define G_DQS_OFFSET(x) (((x) >> S_DQS_OFFSET) & M_DQS_OFFSET)
40331 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_0_RP 0x440e0
40333 #define S_WR_DELAY 6
40334 #define M_WR_DELAY 0x3ffU
40335 #define V_WR_DELAY(x) ((x) << S_WR_DELAY)
40336 #define G_WR_DELAY(x) (((x) >> S_WR_DELAY) & M_WR_DELAY)
40338 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_1_RP 0x440e4
40339 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_2_RP 0x440e8
40340 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_3_RP 0x440ec
40341 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_4_RP 0x440f0
40342 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_5_RP 0x440f4
40343 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_6_RP 0x440f8
40344 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_7_RP 0x440fc
40345 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_8_RP 0x44100
40346 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_9_RP 0x44104
40347 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_10_RP 0x44108
40348 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_11_RP 0x4410c
40349 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_12_RP 0x44110
40350 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_13_RP 0x44114
40351 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_14_RP 0x44118
40352 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_15_RP 0x4411c
40353 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_16_RP 0x44120
40354 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_17_RP 0x44124
40355 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_18_RP 0x44128
40356 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_19_RP 0x4412c
40357 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_20_RP 0x44130
40358 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_21_RP 0x44134
40359 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_22_RP 0x44138
40360 #define A_MC_DDRPHY_DP18_WR_DELAY_VALUE_23_RP 0x4413c
40361 #define A_MC_DDRPHY_DP18_READ_DELAY0_RANK_PAIR 0x44140
40363 #define S_RD_DELAY_BITS0_6 9
40364 #define M_RD_DELAY_BITS0_6 0x7fU
40365 #define V_RD_DELAY_BITS0_6(x) ((x) << S_RD_DELAY_BITS0_6)
40366 #define G_RD_DELAY_BITS0_6(x) (((x) >> S_RD_DELAY_BITS0_6) & M_RD_DELAY_BITS0_6)
40368 #define S_RD_DELAY_BITS8_14 1
40369 #define M_RD_DELAY_BITS8_14 0x7fU
40370 #define V_RD_DELAY_BITS8_14(x) ((x) << S_RD_DELAY_BITS8_14)
40371 #define G_RD_DELAY_BITS8_14(x) (((x) >> S_RD_DELAY_BITS8_14) & M_RD_DELAY_BITS8_14)
40373 #define A_MC_DDRPHY_DP18_READ_DELAY1_RANK_PAIR 0x44144
40374 #define A_MC_DDRPHY_DP18_READ_DELAY2_RANK_PAIR 0x44148
40375 #define A_MC_DDRPHY_DP18_READ_DELAY3_RANK_PAIR 0x4414c
40376 #define A_MC_DDRPHY_DP18_READ_DELAY4_RANK_PAIR 0x44150
40377 #define A_MC_DDRPHY_DP18_READ_DELAY5_RANK_PAIR 0x44154
40378 #define A_MC_DDRPHY_DP18_READ_DELAY6_RANK_PAIR 0x44158
40379 #define A_MC_DDRPHY_DP18_READ_DELAY7_RANK_PAIR 0x4415c
40380 #define A_MC_DDRPHY_DP18_READ_DELAY8_RANK_PAIR 0x44160
40381 #define A_MC_DDRPHY_DP18_READ_DELAY9_RANK_PAIR 0x44164
40382 #define A_MC_DDRPHY_DP18_READ_DELAY10_RANK_PAIR 0x44168
40383 #define A_MC_DDRPHY_DP18_READ_DELAY11_RANK_PAIR 0x4416c
40384 #define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN0_RANK_PAIR 0x44170
40386 #define S_INITIAL_DQS_ROT_N0_N2 8
40387 #define M_INITIAL_DQS_ROT_N0_N2 0x7fU
40388 #define V_INITIAL_DQS_ROT_N0_N2(x) ((x) << S_INITIAL_DQS_ROT_N0_N2)
40389 #define G_INITIAL_DQS_ROT_N0_N2(x) (((x) >> S_INITIAL_DQS_ROT_N0_N2) & M_INITIAL_DQS_ROT_N0_N2)
40391 #define S_INITIAL_DQS_ROT_N1_N3 0
40392 #define M_INITIAL_DQS_ROT_N1_N3 0x7fU
40393 #define V_INITIAL_DQS_ROT_N1_N3(x) ((x) << S_INITIAL_DQS_ROT_N1_N3)
40394 #define G_INITIAL_DQS_ROT_N1_N3(x) (((x) >> S_INITIAL_DQS_ROT_N1_N3) & M_INITIAL_DQS_ROT_N1_N3)
40396 #define A_MC_DDRPHY_DP18_INITIAL_DQS_ALIGN1_RANK_PAIR 0x44174
40397 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE0_RANK_PAIR 0x44180
40399 #define S_RD_EYE_SIZE_BITS2_7 8
40400 #define M_RD_EYE_SIZE_BITS2_7 0x3fU
40401 #define V_RD_EYE_SIZE_BITS2_7(x) ((x) << S_RD_EYE_SIZE_BITS2_7)
40402 #define G_RD_EYE_SIZE_BITS2_7(x) (((x) >> S_RD_EYE_SIZE_BITS2_7) & M_RD_EYE_SIZE_BITS2_7)
40404 #define S_RD_EYE_SIZE_BITS10_15 0
40405 #define M_RD_EYE_SIZE_BITS10_15 0x3fU
40406 #define V_RD_EYE_SIZE_BITS10_15(x) ((x) << S_RD_EYE_SIZE_BITS10_15)
40407 #define G_RD_EYE_SIZE_BITS10_15(x) (((x) >> S_RD_EYE_SIZE_BITS10_15) & M_RD_EYE_SIZE_BITS10_15)
40409 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE1_RANK_PAIR 0x44184
40410 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE2_RANK_PAIR 0x44188
40411 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE3_RANK_PAIR 0x4418c
40412 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE4_RANK_PAIR 0x44190
40413 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE5_RANK_PAIR 0x44194
40414 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE6_RANK_PAIR 0x44198
40415 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE7_RANK_PAIR 0x4419c
40416 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE8_RANK_PAIR 0x441a0
40417 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE9_RANK_PAIR 0x441a4
40418 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE10_RANK_PAIR 0x441a8
40419 #define A_MC_DDRPHY_DP18_READ_EYE_SIZE11_RANK_PAIR 0x441ac
40420 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG3 0x441b4
40421 #define A_MC_DDRPHY_DP18_RD_DIA_CONFIG4 0x441b8
40422 #define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE0 0x441c0
40424 #define S_REFERENCE_BITS1_7 8
40425 #define M_REFERENCE_BITS1_7 0x7fU
40426 #define V_REFERENCE_BITS1_7(x) ((x) << S_REFERENCE_BITS1_7)
40427 #define G_REFERENCE_BITS1_7(x) (((x) >> S_REFERENCE_BITS1_7) & M_REFERENCE_BITS1_7)
40429 #define S_REFERENCE_BITS9_15 0
40430 #define M_REFERENCE_BITS9_15 0x7fU
40431 #define V_REFERENCE_BITS9_15(x) ((x) << S_REFERENCE_BITS9_15)
40432 #define G_REFERENCE_BITS9_15(x) (((x) >> S_REFERENCE_BITS9_15) & M_REFERENCE_BITS9_15)
40434 #define A_MC_DDRPHY_DP18_READ_TIMING_REFERENCE1 0x441c4
40435 #define A_MC_DDRPHY_DP18_READ_DQS_TIMING_REFERENCE 0x441c8
40437 #define S_REFERENCE 8
40438 #define M_REFERENCE 0x7fU
40439 #define V_REFERENCE(x) ((x) << S_REFERENCE)
40440 #define G_REFERENCE(x) (((x) >> S_REFERENCE) & M_REFERENCE)
40442 #define A_MC_DDRPHY_DP18_SYSCLK_PR_VALUE 0x441cc
40443 #define A_MC_DDRPHY_DP18_WRCLK_PR 0x441d0
40444 #define A_MC_DDRPHY_DP18_IO_TX_CONFIG0 0x441d4
40446 #define S_INTERP_SIG_SLEW 12
40447 #define M_INTERP_SIG_SLEW 0xfU
40448 #define V_INTERP_SIG_SLEW(x) ((x) << S_INTERP_SIG_SLEW)
40449 #define G_INTERP_SIG_SLEW(x) (((x) >> S_INTERP_SIG_SLEW) & M_INTERP_SIG_SLEW)
40451 #define S_POST_CURSOR 8
40452 #define M_POST_CURSOR 0xfU
40453 #define V_POST_CURSOR(x) ((x) << S_POST_CURSOR)
40454 #define G_POST_CURSOR(x) (((x) >> S_POST_CURSOR) & M_POST_CURSOR)
40456 #define S_SLEW_CTL 4
40457 #define M_SLEW_CTL 0xfU
40458 #define V_SLEW_CTL(x) ((x) << S_SLEW_CTL)
40459 #define G_SLEW_CTL(x) (((x) >> S_SLEW_CTL) & M_SLEW_CTL)
40461 #define A_MC_DDRPHY_DP18_PLL_CONFIG0 0x441d8
40462 #define A_MC_DDRPHY_DP18_PLL_CONFIG1 0x441dc
40464 #define S_CE0DLTVCCA 7
40465 #define V_CE0DLTVCCA(x) ((x) << S_CE0DLTVCCA)
40466 #define F_CE0DLTVCCA V_CE0DLTVCCA(1U)
40468 #define S_CE0DLTVCCD1 4
40469 #define V_CE0DLTVCCD1(x) ((x) << S_CE0DLTVCCD1)
40470 #define F_CE0DLTVCCD1 V_CE0DLTVCCD1(1U)
40472 #define S_CE0DLTVCCD2 3
40473 #define V_CE0DLTVCCD2(x) ((x) << S_CE0DLTVCCD2)
40474 #define F_CE0DLTVCCD2 V_CE0DLTVCCD2(1U)
40476 #define S_S0INSDLYTAP 2
40477 #define V_S0INSDLYTAP(x) ((x) << S_S0INSDLYTAP)
40478 #define F_S0INSDLYTAP V_S0INSDLYTAP(1U)
40480 #define S_S1INSDLYTAP 1
40481 #define V_S1INSDLYTAP(x) ((x) << S_S1INSDLYTAP)
40482 #define F_S1INSDLYTAP V_S1INSDLYTAP(1U)
40484 #define A_MC_DDRPHY_DP18_IO_TX_NFET_SLICE 0x441e0
40486 #define S_EN_SLICE_N_WR 8
40487 #define M_EN_SLICE_N_WR 0xffU
40488 #define V_EN_SLICE_N_WR(x) ((x) << S_EN_SLICE_N_WR)
40489 #define G_EN_SLICE_N_WR(x) (((x) >> S_EN_SLICE_N_WR) & M_EN_SLICE_N_WR)
40491 #define A_MC_DDRPHY_DP18_IO_TX_PFET_SLICE 0x441e4
40492 #define A_MC_DDRPHY_DP18_IO_TX_NFET_TERM 0x441e8
40494 #define S_EN_TERM_N_WR 8
40495 #define M_EN_TERM_N_WR 0xffU
40496 #define V_EN_TERM_N_WR(x) ((x) << S_EN_TERM_N_WR)
40497 #define G_EN_TERM_N_WR(x) (((x) >> S_EN_TERM_N_WR) & M_EN_TERM_N_WR)
40499 #define S_EN_TERM_N_WR_FFE 4
40500 #define M_EN_TERM_N_WR_FFE 0xfU
40501 #define V_EN_TERM_N_WR_FFE(x) ((x) << S_EN_TERM_N_WR_FFE)
40502 #define G_EN_TERM_N_WR_FFE(x) (((x) >> S_EN_TERM_N_WR_FFE) & M_EN_TERM_N_WR_FFE)
40504 #define A_MC_DDRPHY_DP18_IO_TX_PFET_TERM 0x441ec
40506 #define S_EN_TERM_P_WR 8
40507 #define M_EN_TERM_P_WR 0xffU
40508 #define V_EN_TERM_P_WR(x) ((x) << S_EN_TERM_P_WR)
40509 #define G_EN_TERM_P_WR(x) (((x) >> S_EN_TERM_P_WR) & M_EN_TERM_P_WR)
40511 #define S_EN_TERM_P_WR_FFE 4
40512 #define M_EN_TERM_P_WR_FFE 0xfU
40513 #define V_EN_TERM_P_WR_FFE(x) ((x) << S_EN_TERM_P_WR_FFE)
40514 #define G_EN_TERM_P_WR_FFE(x) (((x) >> S_EN_TERM_P_WR_FFE) & M_EN_TERM_P_WR_FFE)
40516 #define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE0_RP 0x441f0
40518 #define S_DATA_BIT_DISABLE_0_15 0
40519 #define M_DATA_BIT_DISABLE_0_15 0xffffU
40520 #define V_DATA_BIT_DISABLE_0_15(x) ((x) << S_DATA_BIT_DISABLE_0_15)
40521 #define G_DATA_BIT_DISABLE_0_15(x) (((x) >> S_DATA_BIT_DISABLE_0_15) & M_DATA_BIT_DISABLE_0_15)
40523 #define A_MC_DDRPHY_DP18_DATA_BIT_DISABLE1_RP 0x441f4
40525 #define S_DATA_BIT_DISABLE_16_23 8
40526 #define M_DATA_BIT_DISABLE_16_23 0xffU
40527 #define V_DATA_BIT_DISABLE_16_23(x) ((x) << S_DATA_BIT_DISABLE_16_23)
40528 #define G_DATA_BIT_DISABLE_16_23(x) (((x) >> S_DATA_BIT_DISABLE_16_23) & M_DATA_BIT_DISABLE_16_23)
40530 #define A_MC_DDRPHY_DP18_DQ_WR_OFFSET_RP 0x441f8
40532 #define S_DQ_WR_OFFSET_N0 12
40533 #define M_DQ_WR_OFFSET_N0 0xfU
40534 #define V_DQ_WR_OFFSET_N0(x) ((x) << S_DQ_WR_OFFSET_N0)
40535 #define G_DQ_WR_OFFSET_N0(x) (((x) >> S_DQ_WR_OFFSET_N0) & M_DQ_WR_OFFSET_N0)
40537 #define S_DQ_WR_OFFSET_N1 8
40538 #define M_DQ_WR_OFFSET_N1 0xfU
40539 #define V_DQ_WR_OFFSET_N1(x) ((x) << S_DQ_WR_OFFSET_N1)
40540 #define G_DQ_WR_OFFSET_N1(x) (((x) >> S_DQ_WR_OFFSET_N1) & M_DQ_WR_OFFSET_N1)
40542 #define S_DQ_WR_OFFSET_N2 4
40543 #define M_DQ_WR_OFFSET_N2 0xfU
40544 #define V_DQ_WR_OFFSET_N2(x) ((x) << S_DQ_WR_OFFSET_N2)
40545 #define G_DQ_WR_OFFSET_N2(x) (((x) >> S_DQ_WR_OFFSET_N2) & M_DQ_WR_OFFSET_N2)
40547 #define S_DQ_WR_OFFSET_N3 0
40548 #define M_DQ_WR_OFFSET_N3 0xfU
40549 #define V_DQ_WR_OFFSET_N3(x) ((x) << S_DQ_WR_OFFSET_N3)
40550 #define G_DQ_WR_OFFSET_N3(x) (((x) >> S_DQ_WR_OFFSET_N3) & M_DQ_WR_OFFSET_N3)
40552 #define A_MC_DDRPHY_DP18_POWERDOWN_1 0x441fc
40553 #define A_MC_ADR_DDRPHY_ADR_BIT_ENABLE 0x45000
40555 #define S_BIT_ENABLE_0_11 4
40556 #define M_BIT_ENABLE_0_11 0xfffU
40557 #define V_BIT_ENABLE_0_11(x) ((x) << S_BIT_ENABLE_0_11)
40558 #define G_BIT_ENABLE_0_11(x) (((x) >> S_BIT_ENABLE_0_11) & M_BIT_ENABLE_0_11)
40560 #define S_BIT_ENABLE_12_15 0
40561 #define M_BIT_ENABLE_12_15 0xfU
40562 #define V_BIT_ENABLE_12_15(x) ((x) << S_BIT_ENABLE_12_15)
40563 #define G_BIT_ENABLE_12_15(x) (((x) >> S_BIT_ENABLE_12_15) & M_BIT_ENABLE_12_15)
40565 #define A_MC_ADR_DDRPHY_ADR_DIFFPAIR_ENABLE 0x45004
40567 #define S_DI_ADR0_ADR1 15
40568 #define V_DI_ADR0_ADR1(x) ((x) << S_DI_ADR0_ADR1)
40569 #define F_DI_ADR0_ADR1 V_DI_ADR0_ADR1(1U)
40571 #define S_DI_ADR2_ADR3 14
40572 #define V_DI_ADR2_ADR3(x) ((x) << S_DI_ADR2_ADR3)
40573 #define F_DI_ADR2_ADR3 V_DI_ADR2_ADR3(1U)
40575 #define S_DI_ADR4_ADR5 13
40576 #define V_DI_ADR4_ADR5(x) ((x) << S_DI_ADR4_ADR5)
40577 #define F_DI_ADR4_ADR5 V_DI_ADR4_ADR5(1U)
40579 #define S_DI_ADR6_ADR7 12
40580 #define V_DI_ADR6_ADR7(x) ((x) << S_DI_ADR6_ADR7)
40581 #define F_DI_ADR6_ADR7 V_DI_ADR6_ADR7(1U)
40583 #define S_DI_ADR8_ADR9 11
40584 #define V_DI_ADR8_ADR9(x) ((x) << S_DI_ADR8_ADR9)
40585 #define F_DI_ADR8_ADR9 V_DI_ADR8_ADR9(1U)
40587 #define S_DI_ADR10_ADR11 10
40588 #define V_DI_ADR10_ADR11(x) ((x) << S_DI_ADR10_ADR11)
40589 #define F_DI_ADR10_ADR11 V_DI_ADR10_ADR11(1U)
40591 #define S_DI_ADR12_ADR13 9
40592 #define V_DI_ADR12_ADR13(x) ((x) << S_DI_ADR12_ADR13)
40593 #define F_DI_ADR12_ADR13 V_DI_ADR12_ADR13(1U)
40595 #define S_DI_ADR14_ADR15 8
40596 #define V_DI_ADR14_ADR15(x) ((x) << S_DI_ADR14_ADR15)
40597 #define F_DI_ADR14_ADR15 V_DI_ADR14_ADR15(1U)
40599 #define A_MC_ADR_DDRPHY_ADR_DELAY0 0x45010
40601 #define S_ADR_DELAY_BITS1_7 8
40602 #define M_ADR_DELAY_BITS1_7 0x7fU
40603 #define V_ADR_DELAY_BITS1_7(x) ((x) << S_ADR_DELAY_BITS1_7)
40604 #define G_ADR_DELAY_BITS1_7(x) (((x) >> S_ADR_DELAY_BITS1_7) & M_ADR_DELAY_BITS1_7)
40606 #define S_ADR_DELAY_BITS9_15 0
40607 #define M_ADR_DELAY_BITS9_15 0x7fU
40608 #define V_ADR_DELAY_BITS9_15(x) ((x) << S_ADR_DELAY_BITS9_15)
40609 #define G_ADR_DELAY_BITS9_15(x) (((x) >> S_ADR_DELAY_BITS9_15) & M_ADR_DELAY_BITS9_15)
40611 #define A_MC_ADR_DDRPHY_ADR_DELAY1 0x45014
40612 #define A_MC_ADR_DDRPHY_ADR_DELAY2 0x45018
40613 #define A_MC_ADR_DDRPHY_ADR_DELAY3 0x4501c
40614 #define A_MC_ADR_DDRPHY_ADR_DELAY4 0x45020
40615 #define A_MC_ADR_DDRPHY_ADR_DELAY5 0x45024
40616 #define A_MC_ADR_DDRPHY_ADR_DELAY6 0x45028
40617 #define A_MC_ADR_DDRPHY_ADR_DELAY7 0x4502c
40618 #define A_MC_ADR_DDRPHY_ADR_DFT_WRAP_STATUS_CONTROL 0x45030
40620 #define S_ADR_TEST_LANE_PAIR_FAIL 8
40621 #define M_ADR_TEST_LANE_PAIR_FAIL 0xffU
40622 #define V_ADR_TEST_LANE_PAIR_FAIL(x) ((x) << S_ADR_TEST_LANE_PAIR_FAIL)
40623 #define G_ADR_TEST_LANE_PAIR_FAIL(x) (((x) >> S_ADR_TEST_LANE_PAIR_FAIL) & M_ADR_TEST_LANE_PAIR_FAIL)
40625 #define S_ADR_TEST_DATA_EN 7
40626 #define V_ADR_TEST_DATA_EN(x) ((x) << S_ADR_TEST_DATA_EN)
40627 #define F_ADR_TEST_DATA_EN V_ADR_TEST_DATA_EN(1U)
40629 #define S_DADR_TEST_MODE 5
40630 #define M_DADR_TEST_MODE 0x3U
40631 #define V_DADR_TEST_MODE(x) ((x) << S_DADR_TEST_MODE)
40632 #define G_DADR_TEST_MODE(x) (((x) >> S_DADR_TEST_MODE) & M_DADR_TEST_MODE)
40634 #define S_ADR_TEST_4TO1_MODE 4
40635 #define V_ADR_TEST_4TO1_MODE(x) ((x) << S_ADR_TEST_4TO1_MODE)
40636 #define F_ADR_TEST_4TO1_MODE V_ADR_TEST_4TO1_MODE(1U)
40638 #define S_ADR_TEST_RESET 3
40639 #define V_ADR_TEST_RESET(x) ((x) << S_ADR_TEST_RESET)
40640 #define F_ADR_TEST_RESET V_ADR_TEST_RESET(1U)
40642 #define S_ADR_TEST_GEN_EN 2
40643 #define V_ADR_TEST_GEN_EN(x) ((x) << S_ADR_TEST_GEN_EN)
40644 #define F_ADR_TEST_GEN_EN V_ADR_TEST_GEN_EN(1U)
40646 #define S_ADR_TEST_CLEAR_ERROR 1
40647 #define V_ADR_TEST_CLEAR_ERROR(x) ((x) << S_ADR_TEST_CLEAR_ERROR)
40648 #define F_ADR_TEST_CLEAR_ERROR V_ADR_TEST_CLEAR_ERROR(1U)
40650 #define S_ADR_TEST_CHECK_EN 0
40651 #define V_ADR_TEST_CHECK_EN(x) ((x) << S_ADR_TEST_CHECK_EN)
40652 #define F_ADR_TEST_CHECK_EN V_ADR_TEST_CHECK_EN(1U)
40654 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN0 0x45040
40656 #define S_EN_SLICE_N_WR_0 8
40657 #define M_EN_SLICE_N_WR_0 0xffU
40658 #define V_EN_SLICE_N_WR_0(x) ((x) << S_EN_SLICE_N_WR_0)
40659 #define G_EN_SLICE_N_WR_0(x) (((x) >> S_EN_SLICE_N_WR_0) & M_EN_SLICE_N_WR_0)
40661 #define S_EN_SLICE_N_WR_FFE 4
40662 #define M_EN_SLICE_N_WR_FFE 0xfU
40663 #define V_EN_SLICE_N_WR_FFE(x) ((x) << S_EN_SLICE_N_WR_FFE)
40664 #define G_EN_SLICE_N_WR_FFE(x) (((x) >> S_EN_SLICE_N_WR_FFE) & M_EN_SLICE_N_WR_FFE)
40666 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN1 0x45044
40668 #define S_EN_SLICE_N_WR_1 8
40669 #define M_EN_SLICE_N_WR_1 0xffU
40670 #define V_EN_SLICE_N_WR_1(x) ((x) << S_EN_SLICE_N_WR_1)
40671 #define G_EN_SLICE_N_WR_1(x) (((x) >> S_EN_SLICE_N_WR_1) & M_EN_SLICE_N_WR_1)
40673 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN2 0x45048
40675 #define S_EN_SLICE_N_WR_2 8
40676 #define M_EN_SLICE_N_WR_2 0xffU
40677 #define V_EN_SLICE_N_WR_2(x) ((x) << S_EN_SLICE_N_WR_2)
40678 #define G_EN_SLICE_N_WR_2(x) (((x) >> S_EN_SLICE_N_WR_2) & M_EN_SLICE_N_WR_2)
40680 #define A_MC_ADR_DDRPHY_ADR_IO_NFET_SLICE_EN3 0x4504c
40682 #define S_EN_SLICE_N_WR_3 8
40683 #define M_EN_SLICE_N_WR_3 0xffU
40684 #define V_EN_SLICE_N_WR_3(x) ((x) << S_EN_SLICE_N_WR_3)
40685 #define G_EN_SLICE_N_WR_3(x) (((x) >> S_EN_SLICE_N_WR_3) & M_EN_SLICE_N_WR_3)
40687 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN0 0x45050
40689 #define S_EN_SLICE_P_WR 8
40690 #define M_EN_SLICE_P_WR 0xffU
40691 #define V_EN_SLICE_P_WR(x) ((x) << S_EN_SLICE_P_WR)
40692 #define G_EN_SLICE_P_WR(x) (((x) >> S_EN_SLICE_P_WR) & M_EN_SLICE_P_WR)
40694 #define S_EN_SLICE_P_WR_FFE 4
40695 #define M_EN_SLICE_P_WR_FFE 0xfU
40696 #define V_EN_SLICE_P_WR_FFE(x) ((x) << S_EN_SLICE_P_WR_FFE)
40697 #define G_EN_SLICE_P_WR_FFE(x) (((x) >> S_EN_SLICE_P_WR_FFE) & M_EN_SLICE_P_WR_FFE)
40699 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN1 0x45054
40700 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN2 0x45058
40701 #define A_MC_ADR_DDRPHY_ADR_IO_PFET_SLICE_EN3 0x4505c
40702 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE 0x45060
40704 #define S_POST_CURSOR0 12
40705 #define M_POST_CURSOR0 0xfU
40706 #define V_POST_CURSOR0(x) ((x) << S_POST_CURSOR0)
40707 #define G_POST_CURSOR0(x) (((x) >> S_POST_CURSOR0) & M_POST_CURSOR0)
40709 #define S_POST_CURSOR1 8
40710 #define M_POST_CURSOR1 0xfU
40711 #define V_POST_CURSOR1(x) ((x) << S_POST_CURSOR1)
40712 #define G_POST_CURSOR1(x) (((x) >> S_POST_CURSOR1) & M_POST_CURSOR1)
40714 #define S_POST_CURSOR2 4
40715 #define M_POST_CURSOR2 0xfU
40716 #define V_POST_CURSOR2(x) ((x) << S_POST_CURSOR2)
40717 #define G_POST_CURSOR2(x) (((x) >> S_POST_CURSOR2) & M_POST_CURSOR2)
40719 #define S_POST_CURSOR3 0
40720 #define M_POST_CURSOR3 0xfU
40721 #define V_POST_CURSOR3(x) ((x) << S_POST_CURSOR3)
40722 #define G_POST_CURSOR3(x) (((x) >> S_POST_CURSOR3) & M_POST_CURSOR3)
40724 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE 0x45068
40726 #define S_SLEW_CTL0 12
40727 #define M_SLEW_CTL0 0xfU
40728 #define V_SLEW_CTL0(x) ((x) << S_SLEW_CTL0)
40729 #define G_SLEW_CTL0(x) (((x) >> S_SLEW_CTL0) & M_SLEW_CTL0)
40731 #define S_SLEW_CTL1 8
40732 #define M_SLEW_CTL1 0xfU
40733 #define V_SLEW_CTL1(x) ((x) << S_SLEW_CTL1)
40734 #define G_SLEW_CTL1(x) (((x) >> S_SLEW_CTL1) & M_SLEW_CTL1)
40736 #define S_SLEW_CTL2 4
40737 #define M_SLEW_CTL2 0xfU
40738 #define V_SLEW_CTL2(x) ((x) << S_SLEW_CTL2)
40739 #define G_SLEW_CTL2(x) (((x) >> S_SLEW_CTL2) & M_SLEW_CTL2)
40741 #define S_SLEW_CTL3 0
40742 #define M_SLEW_CTL3 0xfU
40743 #define V_SLEW_CTL3(x) ((x) << S_SLEW_CTL3)
40744 #define G_SLEW_CTL3(x) (((x) >> S_SLEW_CTL3) & M_SLEW_CTL3)
40746 #define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP0 0x45080
40748 #define S_SLICE_SEL_REG_BITS0_1 14
40749 #define M_SLICE_SEL_REG_BITS0_1 0x3U
40750 #define V_SLICE_SEL_REG_BITS0_1(x) ((x) << S_SLICE_SEL_REG_BITS0_1)
40751 #define G_SLICE_SEL_REG_BITS0_1(x) (((x) >> S_SLICE_SEL_REG_BITS0_1) & M_SLICE_SEL_REG_BITS0_1)
40753 #define S_SLICE_SEL_REG_BITS2_3 12
40754 #define M_SLICE_SEL_REG_BITS2_3 0x3U
40755 #define V_SLICE_SEL_REG_BITS2_3(x) ((x) << S_SLICE_SEL_REG_BITS2_3)
40756 #define G_SLICE_SEL_REG_BITS2_3(x) (((x) >> S_SLICE_SEL_REG_BITS2_3) & M_SLICE_SEL_REG_BITS2_3)
40758 #define S_SLICE_SEL_REG_BITS4_5 10
40759 #define M_SLICE_SEL_REG_BITS4_5 0x3U
40760 #define V_SLICE_SEL_REG_BITS4_5(x) ((x) << S_SLICE_SEL_REG_BITS4_5)
40761 #define G_SLICE_SEL_REG_BITS4_5(x) (((x) >> S_SLICE_SEL_REG_BITS4_5) & M_SLICE_SEL_REG_BITS4_5)
40763 #define S_SLICE_SEL_REG_BITS6_7 8
40764 #define M_SLICE_SEL_REG_BITS6_7 0x3U
40765 #define V_SLICE_SEL_REG_BITS6_7(x) ((x) << S_SLICE_SEL_REG_BITS6_7)
40766 #define G_SLICE_SEL_REG_BITS6_7(x) (((x) >> S_SLICE_SEL_REG_BITS6_7) & M_SLICE_SEL_REG_BITS6_7)
40768 #define S_SLICE_SEL_REG_BITS8_9 6
40769 #define M_SLICE_SEL_REG_BITS8_9 0x3U
40770 #define V_SLICE_SEL_REG_BITS8_9(x) ((x) << S_SLICE_SEL_REG_BITS8_9)
40771 #define G_SLICE_SEL_REG_BITS8_9(x) (((x) >> S_SLICE_SEL_REG_BITS8_9) & M_SLICE_SEL_REG_BITS8_9)
40773 #define S_SLICE_SEL_REG_BITS10_11 4
40774 #define M_SLICE_SEL_REG_BITS10_11 0x3U
40775 #define V_SLICE_SEL_REG_BITS10_11(x) ((x) << S_SLICE_SEL_REG_BITS10_11)
40776 #define G_SLICE_SEL_REG_BITS10_11(x) (((x) >> S_SLICE_SEL_REG_BITS10_11) & M_SLICE_SEL_REG_BITS10_11)
40778 #define S_SLICE_SEL_REG_BITS12_13 2
40779 #define M_SLICE_SEL_REG_BITS12_13 0x3U
40780 #define V_SLICE_SEL_REG_BITS12_13(x) ((x) << S_SLICE_SEL_REG_BITS12_13)
40781 #define G_SLICE_SEL_REG_BITS12_13(x) (((x) >> S_SLICE_SEL_REG_BITS12_13) & M_SLICE_SEL_REG_BITS12_13)
40783 #define S_SLICE_SEL_REG_BITS14_15 0
40784 #define M_SLICE_SEL_REG_BITS14_15 0x3U
40785 #define V_SLICE_SEL_REG_BITS14_15(x) ((x) << S_SLICE_SEL_REG_BITS14_15)
40786 #define G_SLICE_SEL_REG_BITS14_15(x) (((x) >> S_SLICE_SEL_REG_BITS14_15) & M_SLICE_SEL_REG_BITS14_15)
40788 #define A_MC_ADR_DDRPHY_ADR_IO_FET_SLICE_EN_MAP1 0x45084
40789 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP0 0x450a0
40791 #define S_POST_CUR_SEL_BITS0_1 14
40792 #define M_POST_CUR_SEL_BITS0_1 0x3U
40793 #define V_POST_CUR_SEL_BITS0_1(x) ((x) << S_POST_CUR_SEL_BITS0_1)
40794 #define G_POST_CUR_SEL_BITS0_1(x) (((x) >> S_POST_CUR_SEL_BITS0_1) & M_POST_CUR_SEL_BITS0_1)
40796 #define S_POST_CUR_SEL_BITS2_3 12
40797 #define M_POST_CUR_SEL_BITS2_3 0x3U
40798 #define V_POST_CUR_SEL_BITS2_3(x) ((x) << S_POST_CUR_SEL_BITS2_3)
40799 #define G_POST_CUR_SEL_BITS2_3(x) (((x) >> S_POST_CUR_SEL_BITS2_3) & M_POST_CUR_SEL_BITS2_3)
40801 #define S_POST_CUR_SEL_BITS4_5 10
40802 #define M_POST_CUR_SEL_BITS4_5 0x3U
40803 #define V_POST_CUR_SEL_BITS4_5(x) ((x) << S_POST_CUR_SEL_BITS4_5)
40804 #define G_POST_CUR_SEL_BITS4_5(x) (((x) >> S_POST_CUR_SEL_BITS4_5) & M_POST_CUR_SEL_BITS4_5)
40806 #define S_POST_CUR_SEL_BITS6_7 8
40807 #define M_POST_CUR_SEL_BITS6_7 0x3U
40808 #define V_POST_CUR_SEL_BITS6_7(x) ((x) << S_POST_CUR_SEL_BITS6_7)
40809 #define G_POST_CUR_SEL_BITS6_7(x) (((x) >> S_POST_CUR_SEL_BITS6_7) & M_POST_CUR_SEL_BITS6_7)
40811 #define S_POST_CUR_SEL_BITS8_9 6
40812 #define M_POST_CUR_SEL_BITS8_9 0x3U
40813 #define V_POST_CUR_SEL_BITS8_9(x) ((x) << S_POST_CUR_SEL_BITS8_9)
40814 #define G_POST_CUR_SEL_BITS8_9(x) (((x) >> S_POST_CUR_SEL_BITS8_9) & M_POST_CUR_SEL_BITS8_9)
40816 #define S_POST_CUR_SEL_BITS10_11 4
40817 #define M_POST_CUR_SEL_BITS10_11 0x3U
40818 #define V_POST_CUR_SEL_BITS10_11(x) ((x) << S_POST_CUR_SEL_BITS10_11)
40819 #define G_POST_CUR_SEL_BITS10_11(x) (((x) >> S_POST_CUR_SEL_BITS10_11) & M_POST_CUR_SEL_BITS10_11)
40821 #define S_POST_CUR_SEL_BITS12_13 2
40822 #define M_POST_CUR_SEL_BITS12_13 0x3U
40823 #define V_POST_CUR_SEL_BITS12_13(x) ((x) << S_POST_CUR_SEL_BITS12_13)
40824 #define G_POST_CUR_SEL_BITS12_13(x) (((x) >> S_POST_CUR_SEL_BITS12_13) & M_POST_CUR_SEL_BITS12_13)
40826 #define S_POST_CUR_SEL_BITS14_15 0
40827 #define M_POST_CUR_SEL_BITS14_15 0x3U
40828 #define V_POST_CUR_SEL_BITS14_15(x) ((x) << S_POST_CUR_SEL_BITS14_15)
40829 #define G_POST_CUR_SEL_BITS14_15(x) (((x) >> S_POST_CUR_SEL_BITS14_15) & M_POST_CUR_SEL_BITS14_15)
40831 #define A_MC_ADR_DDRPHY_ADR_IO_POST_CURSOR_VALUE_MAP1 0x450a4
40832 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP0 0x450a8
40834 #define S_SLEW_CTL_SEL_BITS0_1 14
40835 #define M_SLEW_CTL_SEL_BITS0_1 0x3U
40836 #define V_SLEW_CTL_SEL_BITS0_1(x) ((x) << S_SLEW_CTL_SEL_BITS0_1)
40837 #define G_SLEW_CTL_SEL_BITS0_1(x) (((x) >> S_SLEW_CTL_SEL_BITS0_1) & M_SLEW_CTL_SEL_BITS0_1)
40839 #define S_SLEW_CTL_SEL_BITS2_3 12
40840 #define M_SLEW_CTL_SEL_BITS2_3 0x3U
40841 #define V_SLEW_CTL_SEL_BITS2_3(x) ((x) << S_SLEW_CTL_SEL_BITS2_3)
40842 #define G_SLEW_CTL_SEL_BITS2_3(x) (((x) >> S_SLEW_CTL_SEL_BITS2_3) & M_SLEW_CTL_SEL_BITS2_3)
40844 #define S_SLEW_CTL_SEL_BITS4_5 10
40845 #define M_SLEW_CTL_SEL_BITS4_5 0x3U
40846 #define V_SLEW_CTL_SEL_BITS4_5(x) ((x) << S_SLEW_CTL_SEL_BITS4_5)
40847 #define G_SLEW_CTL_SEL_BITS4_5(x) (((x) >> S_SLEW_CTL_SEL_BITS4_5) & M_SLEW_CTL_SEL_BITS4_5)
40849 #define S_SLEW_CTL_SEL_BITS6_7 8
40850 #define M_SLEW_CTL_SEL_BITS6_7 0x3U
40851 #define V_SLEW_CTL_SEL_BITS6_7(x) ((x) << S_SLEW_CTL_SEL_BITS6_7)
40852 #define G_SLEW_CTL_SEL_BITS6_7(x) (((x) >> S_SLEW_CTL_SEL_BITS6_7) & M_SLEW_CTL_SEL_BITS6_7)
40854 #define S_SLEW_CTL_SEL_BITS8_9 6
40855 #define M_SLEW_CTL_SEL_BITS8_9 0x3U
40856 #define V_SLEW_CTL_SEL_BITS8_9(x) ((x) << S_SLEW_CTL_SEL_BITS8_9)
40857 #define G_SLEW_CTL_SEL_BITS8_9(x) (((x) >> S_SLEW_CTL_SEL_BITS8_9) & M_SLEW_CTL_SEL_BITS8_9)
40859 #define S_SLEW_CTL_SEL_BITS10_11 4
40860 #define M_SLEW_CTL_SEL_BITS10_11 0x3U
40861 #define V_SLEW_CTL_SEL_BITS10_11(x) ((x) << S_SLEW_CTL_SEL_BITS10_11)
40862 #define G_SLEW_CTL_SEL_BITS10_11(x) (((x) >> S_SLEW_CTL_SEL_BITS10_11) & M_SLEW_CTL_SEL_BITS10_11)
40864 #define S_SLEW_CTL_SEL_BITS12_13 2
40865 #define M_SLEW_CTL_SEL_BITS12_13 0x3U
40866 #define V_SLEW_CTL_SEL_BITS12_13(x) ((x) << S_SLEW_CTL_SEL_BITS12_13)
40867 #define G_SLEW_CTL_SEL_BITS12_13(x) (((x) >> S_SLEW_CTL_SEL_BITS12_13) & M_SLEW_CTL_SEL_BITS12_13)
40869 #define S_SLEW_CTL_SEL_BITS14_15 0
40870 #define M_SLEW_CTL_SEL_BITS14_15 0x3U
40871 #define V_SLEW_CTL_SEL_BITS14_15(x) ((x) << S_SLEW_CTL_SEL_BITS14_15)
40872 #define G_SLEW_CTL_SEL_BITS14_15(x) (((x) >> S_SLEW_CTL_SEL_BITS14_15) & M_SLEW_CTL_SEL_BITS14_15)
40874 #define A_MC_ADR_DDRPHY_ADR_IO_SLEW_CTL_VALUE_MAP1 0x450ac
40875 #define A_MC_ADR_DDRPHY_ADR_POWERDOWN_2 0x450b0
40877 #define S_ADR_LANE_0_11_PD 4
40878 #define M_ADR_LANE_0_11_PD 0xfffU
40879 #define V_ADR_LANE_0_11_PD(x) ((x) << S_ADR_LANE_0_11_PD)
40880 #define G_ADR_LANE_0_11_PD(x) (((x) >> S_ADR_LANE_0_11_PD) & M_ADR_LANE_0_11_PD)
40882 #define S_ADR_LANE_12_15_PD 0
40883 #define M_ADR_LANE_12_15_PD 0xfU
40884 #define V_ADR_LANE_12_15_PD(x) ((x) << S_ADR_LANE_12_15_PD)
40885 #define G_ADR_LANE_12_15_PD(x) (((x) >> S_ADR_LANE_12_15_PD) & M_ADR_LANE_12_15_PD)
40887 #define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_0 0x460c0
40889 #define S_PLL_TUNE_0_2 13
40890 #define M_PLL_TUNE_0_2 0x7U
40891 #define V_PLL_TUNE_0_2(x) ((x) << S_PLL_TUNE_0_2)
40892 #define G_PLL_TUNE_0_2(x) (((x) >> S_PLL_TUNE_0_2) & M_PLL_TUNE_0_2)
40894 #define S_PLL_TUNECP_0_2 10
40895 #define M_PLL_TUNECP_0_2 0x7U
40896 #define V_PLL_TUNECP_0_2(x) ((x) << S_PLL_TUNECP_0_2)
40897 #define G_PLL_TUNECP_0_2(x) (((x) >> S_PLL_TUNECP_0_2) & M_PLL_TUNECP_0_2)
40899 #define S_PLL_TUNEF_0_5 4
40900 #define M_PLL_TUNEF_0_5 0x3fU
40901 #define V_PLL_TUNEF_0_5(x) ((x) << S_PLL_TUNEF_0_5)
40902 #define G_PLL_TUNEF_0_5(x) (((x) >> S_PLL_TUNEF_0_5) & M_PLL_TUNEF_0_5)
40904 #define S_PLL_TUNEVCO_0_1 2
40905 #define M_PLL_TUNEVCO_0_1 0x3U
40906 #define V_PLL_TUNEVCO_0_1(x) ((x) << S_PLL_TUNEVCO_0_1)
40907 #define G_PLL_TUNEVCO_0_1(x) (((x) >> S_PLL_TUNEVCO_0_1) & M_PLL_TUNEVCO_0_1)
40909 #define S_PLL_PLLXTR_0_1 0
40910 #define M_PLL_PLLXTR_0_1 0x3U
40911 #define V_PLL_PLLXTR_0_1(x) ((x) << S_PLL_PLLXTR_0_1)
40912 #define G_PLL_PLLXTR_0_1(x) (((x) >> S_PLL_PLLXTR_0_1) & M_PLL_PLLXTR_0_1)
40914 #define A_MC_DDRPHY_ADR_PLL_VREG_CONFIG_1 0x460c4
40916 #define S_PLL_TUNETDIV_0_2 13
40917 #define M_PLL_TUNETDIV_0_2 0x7U
40918 #define V_PLL_TUNETDIV_0_2(x) ((x) << S_PLL_TUNETDIV_0_2)
40919 #define G_PLL_TUNETDIV_0_2(x) (((x) >> S_PLL_TUNETDIV_0_2) & M_PLL_TUNETDIV_0_2)
40921 #define S_PLL_TUNEMDIV_0_1 11
40922 #define M_PLL_TUNEMDIV_0_1 0x3U
40923 #define V_PLL_TUNEMDIV_0_1(x) ((x) << S_PLL_TUNEMDIV_0_1)
40924 #define G_PLL_TUNEMDIV_0_1(x) (((x) >> S_PLL_TUNEMDIV_0_1) & M_PLL_TUNEMDIV_0_1)
40926 #define S_PLL_TUNEATST 10
40927 #define V_PLL_TUNEATST(x) ((x) << S_PLL_TUNEATST)
40928 #define F_PLL_TUNEATST V_PLL_TUNEATST(1U)
40930 #define S_VREG_RANGE_0_1 8
40931 #define M_VREG_RANGE_0_1 0x3U
40932 #define V_VREG_RANGE_0_1(x) ((x) << S_VREG_RANGE_0_1)
40933 #define G_VREG_RANGE_0_1(x) (((x) >> S_VREG_RANGE_0_1) & M_VREG_RANGE_0_1)
40935 #define S_VREG_VREGSPARE 7
40936 #define V_VREG_VREGSPARE(x) ((x) << S_VREG_VREGSPARE)
40937 #define F_VREG_VREGSPARE V_VREG_VREGSPARE(1U)
40939 #define S_VREG_VCCTUNE_0_1 5
40940 #define M_VREG_VCCTUNE_0_1 0x3U
40941 #define V_VREG_VCCTUNE_0_1(x) ((x) << S_VREG_VCCTUNE_0_1)
40942 #define G_VREG_VCCTUNE_0_1(x) (((x) >> S_VREG_VCCTUNE_0_1) & M_VREG_VCCTUNE_0_1)
40944 #define S_INTERP_SIG_SLEW_0_3 1
40945 #define M_INTERP_SIG_SLEW_0_3 0xfU
40946 #define V_INTERP_SIG_SLEW_0_3(x) ((x) << S_INTERP_SIG_SLEW_0_3)
40947 #define G_INTERP_SIG_SLEW_0_3(x) (((x) >> S_INTERP_SIG_SLEW_0_3) & M_INTERP_SIG_SLEW_0_3)
40949 #define S_ANALOG_WRAPON 0
40950 #define V_ANALOG_WRAPON(x) ((x) << S_ANALOG_WRAPON)
40951 #define F_ANALOG_WRAPON V_ANALOG_WRAPON(1U)
40953 #define A_MC_DDRPHY_ADR_SYSCLK_CNTL_PR 0x460c8
40955 #define S_SYSCLK_ENABLE 15
40956 #define V_SYSCLK_ENABLE(x) ((x) << S_SYSCLK_ENABLE)
40957 #define F_SYSCLK_ENABLE V_SYSCLK_ENABLE(1U)
40959 #define S_SYSCLK_ROT_OVERRIDE 8
40960 #define M_SYSCLK_ROT_OVERRIDE 0x7fU
40961 #define V_SYSCLK_ROT_OVERRIDE(x) ((x) << S_SYSCLK_ROT_OVERRIDE)
40962 #define G_SYSCLK_ROT_OVERRIDE(x) (((x) >> S_SYSCLK_ROT_OVERRIDE) & M_SYSCLK_ROT_OVERRIDE)
40964 #define S_SYSCLK_ROT_OVERRIDE_EN 7
40965 #define V_SYSCLK_ROT_OVERRIDE_EN(x) ((x) << S_SYSCLK_ROT_OVERRIDE_EN)
40966 #define F_SYSCLK_ROT_OVERRIDE_EN V_SYSCLK_ROT_OVERRIDE_EN(1U)
40968 #define S_SYSCLK_PHASE_ALIGN_RESE 6
40969 #define V_SYSCLK_PHASE_ALIGN_RESE(x) ((x) << S_SYSCLK_PHASE_ALIGN_RESE)
40970 #define F_SYSCLK_PHASE_ALIGN_RESE V_SYSCLK_PHASE_ALIGN_RESE(1U)
40972 #define S_SYSCLK_PHASE_CNTL_EN 5
40973 #define V_SYSCLK_PHASE_CNTL_EN(x) ((x) << S_SYSCLK_PHASE_CNTL_EN)
40974 #define F_SYSCLK_PHASE_CNTL_EN V_SYSCLK_PHASE_CNTL_EN(1U)
40976 #define S_SYSCLK_PHASE_DEFAULT_EN 4
40977 #define V_SYSCLK_PHASE_DEFAULT_EN(x) ((x) << S_SYSCLK_PHASE_DEFAULT_EN)
40978 #define F_SYSCLK_PHASE_DEFAULT_EN V_SYSCLK_PHASE_DEFAULT_EN(1U)
40980 #define S_SYSCLK_POS_EDGE_ALIGN 3
40981 #define V_SYSCLK_POS_EDGE_ALIGN(x) ((x) << S_SYSCLK_POS_EDGE_ALIGN)
40982 #define F_SYSCLK_POS_EDGE_ALIGN V_SYSCLK_POS_EDGE_ALIGN(1U)
40984 #define S_CONTINUOUS_UPDATE 2
40985 #define V_CONTINUOUS_UPDATE(x) ((x) << S_CONTINUOUS_UPDATE)
40986 #define F_CONTINUOUS_UPDATE V_CONTINUOUS_UPDATE(1U)
40988 #define S_CE0DLTVCC 0
40989 #define M_CE0DLTVCC 0x3U
40990 #define V_CE0DLTVCC(x) ((x) << S_CE0DLTVCC)
40991 #define G_CE0DLTVCC(x) (((x) >> S_CE0DLTVCC) & M_CE0DLTVCC)
40993 #define A_MC_DDRPHY_ADR_MCCLK_WRCLK_PR_STATIC_OFFSET 0x460cc
40995 #define S_TSYS_WRCLK 8
40996 #define M_TSYS_WRCLK 0x7fU
40997 #define V_TSYS_WRCLK(x) ((x) << S_TSYS_WRCLK)
40998 #define G_TSYS_WRCLK(x) (((x) >> S_TSYS_WRCLK) & M_TSYS_WRCLK)
41000 #define A_MC_DDRPHY_ADR_SYSCLK_PR_VALUE_RO 0x460d0
41002 #define S_SLEW_LATE_SAMPLE 15
41003 #define V_SLEW_LATE_SAMPLE(x) ((x) << S_SLEW_LATE_SAMPLE)
41004 #define F_SLEW_LATE_SAMPLE V_SLEW_LATE_SAMPLE(1U)
41006 #define S_SYSCLK_ROT 8
41007 #define M_SYSCLK_ROT 0x7fU
41008 #define V_SYSCLK_ROT(x) ((x) << S_SYSCLK_ROT)
41009 #define G_SYSCLK_ROT(x) (((x) >> S_SYSCLK_ROT) & M_SYSCLK_ROT)
41011 #define S_BB_LOCK 7
41012 #define V_BB_LOCK(x) ((x) << S_BB_LOCK)
41013 #define F_BB_LOCK V_BB_LOCK(1U)
41015 #define S_SLEW_EARLY_SAMPLE 6
41016 #define V_SLEW_EARLY_SAMPLE(x) ((x) << S_SLEW_EARLY_SAMPLE)
41017 #define F_SLEW_EARLY_SAMPLE V_SLEW_EARLY_SAMPLE(1U)
41019 #define S_SLEW_DONE_STATUS 4
41020 #define M_SLEW_DONE_STATUS 0x3U
41021 #define V_SLEW_DONE_STATUS(x) ((x) << S_SLEW_DONE_STATUS)
41022 #define G_SLEW_DONE_STATUS(x) (((x) >> S_SLEW_DONE_STATUS) & M_SLEW_DONE_STATUS)
41024 #define S_SLEW_CNTL 0
41025 #define M_SLEW_CNTL 0xfU
41026 #define V_SLEW_CNTL(x) ((x) << S_SLEW_CNTL)
41027 #define G_SLEW_CNTL(x) (((x) >> S_SLEW_CNTL) & M_SLEW_CNTL)
41029 #define A_MC_DDRPHY_ADR_GMTEST_ATEST_CNTL 0x460d4
41032 #define V_FLUSH(x) ((x) << S_FLUSH)
41033 #define F_FLUSH V_FLUSH(1U)
41035 #define S_GIANT_MUX_TEST_EN 14
41036 #define V_GIANT_MUX_TEST_EN(x) ((x) << S_GIANT_MUX_TEST_EN)
41037 #define F_GIANT_MUX_TEST_EN V_GIANT_MUX_TEST_EN(1U)
41039 #define S_GIANT_MUX_TEST_VAL 13
41040 #define V_GIANT_MUX_TEST_VAL(x) ((x) << S_GIANT_MUX_TEST_VAL)
41041 #define F_GIANT_MUX_TEST_VAL V_GIANT_MUX_TEST_VAL(1U)
41043 #define S_HS_PROBE_A_SEL_ 8
41044 #define M_HS_PROBE_A_SEL_ 0xfU
41045 #define V_HS_PROBE_A_SEL_(x) ((x) << S_HS_PROBE_A_SEL_)
41046 #define G_HS_PROBE_A_SEL_(x) (((x) >> S_HS_PROBE_A_SEL_) & M_HS_PROBE_A_SEL_)
41048 #define S_HS_PROBE_B_SEL_ 4
41049 #define M_HS_PROBE_B_SEL_ 0xfU
41050 #define V_HS_PROBE_B_SEL_(x) ((x) << S_HS_PROBE_B_SEL_)
41051 #define G_HS_PROBE_B_SEL_(x) (((x) >> S_HS_PROBE_B_SEL_) & M_HS_PROBE_B_SEL_)
41053 #define S_ATEST1CTL0 3
41054 #define V_ATEST1CTL0(x) ((x) << S_ATEST1CTL0)
41055 #define F_ATEST1CTL0 V_ATEST1CTL0(1U)
41057 #define S_ATEST1CTL1 2
41058 #define V_ATEST1CTL1(x) ((x) << S_ATEST1CTL1)
41059 #define F_ATEST1CTL1 V_ATEST1CTL1(1U)
41061 #define S_ATEST1CTL2 1
41062 #define V_ATEST1CTL2(x) ((x) << S_ATEST1CTL2)
41063 #define F_ATEST1CTL2 V_ATEST1CTL2(1U)
41065 #define S_ATEST1CTL3 0
41066 #define V_ATEST1CTL3(x) ((x) << S_ATEST1CTL3)
41067 #define F_ATEST1CTL3 V_ATEST1CTL3(1U)
41069 #define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A0 0x460d8
41071 #define S_GIANT_MUX_TEST_RESULTS 0
41072 #define M_GIANT_MUX_TEST_RESULTS 0xffffU
41073 #define V_GIANT_MUX_TEST_RESULTS(x) ((x) << S_GIANT_MUX_TEST_RESULTS)
41074 #define G_GIANT_MUX_TEST_RESULTS(x) (((x) >> S_GIANT_MUX_TEST_RESULTS) & M_GIANT_MUX_TEST_RESULTS)
41076 #define A_MC_DDRPHY_ADR_GIANT_MUX_RESULTS_A1 0x460dc
41077 #define A_MC_DDRPHY_ADR_POWERDOWN_1 0x460e0
41079 #define S_MASTER_PD_CNTL 15
41080 #define V_MASTER_PD_CNTL(x) ((x) << S_MASTER_PD_CNTL)
41081 #define F_MASTER_PD_CNTL V_MASTER_PD_CNTL(1U)
41083 #define S_ANALOG_INPUT_STAB2 14
41084 #define V_ANALOG_INPUT_STAB2(x) ((x) << S_ANALOG_INPUT_STAB2)
41085 #define F_ANALOG_INPUT_STAB2 V_ANALOG_INPUT_STAB2(1U)
41087 #define S_ANALOG_INPUT_STAB1 8
41088 #define V_ANALOG_INPUT_STAB1(x) ((x) << S_ANALOG_INPUT_STAB1)
41089 #define F_ANALOG_INPUT_STAB1 V_ANALOG_INPUT_STAB1(1U)
41091 #define S_SYSCLK_CLK_GATE 6
41092 #define M_SYSCLK_CLK_GATE 0x3U
41093 #define V_SYSCLK_CLK_GATE(x) ((x) << S_SYSCLK_CLK_GATE)
41094 #define G_SYSCLK_CLK_GATE(x) (((x) >> S_SYSCLK_CLK_GATE) & M_SYSCLK_CLK_GATE)
41096 #define S_WR_FIFO_STAB 5
41097 #define V_WR_FIFO_STAB(x) ((x) << S_WR_FIFO_STAB)
41098 #define F_WR_FIFO_STAB V_WR_FIFO_STAB(1U)
41100 #define S_ADR_RX_PD 4
41101 #define V_ADR_RX_PD(x) ((x) << S_ADR_RX_PD)
41102 #define F_ADR_RX_PD V_ADR_RX_PD(1U)
41104 #define S_TX_TRISTATE_CNTL 1
41105 #define V_TX_TRISTATE_CNTL(x) ((x) << S_TX_TRISTATE_CNTL)
41106 #define F_TX_TRISTATE_CNTL V_TX_TRISTATE_CNTL(1U)
41108 #define S_DVCC_REG_PD 0
41109 #define V_DVCC_REG_PD(x) ((x) << S_DVCC_REG_PD)
41110 #define F_DVCC_REG_PD V_DVCC_REG_PD(1U)
41112 #define A_MC_DDRPHY_ADR_SLEW_CAL_CNTL 0x460e4
41114 #define S_SLEW_CAL_ENABLE 15
41115 #define V_SLEW_CAL_ENABLE(x) ((x) << S_SLEW_CAL_ENABLE)
41116 #define F_SLEW_CAL_ENABLE V_SLEW_CAL_ENABLE(1U)
41118 #define S_SLEW_CAL_START 14
41119 #define V_SLEW_CAL_START(x) ((x) << S_SLEW_CAL_START)
41120 #define F_SLEW_CAL_START V_SLEW_CAL_START(1U)
41122 #define S_SLEW_CAL_OVERRIDE_EN 12
41123 #define V_SLEW_CAL_OVERRIDE_EN(x) ((x) << S_SLEW_CAL_OVERRIDE_EN)
41124 #define F_SLEW_CAL_OVERRIDE_EN V_SLEW_CAL_OVERRIDE_EN(1U)
41126 #define S_SLEW_CAL_OVERRIDE 8
41127 #define M_SLEW_CAL_OVERRIDE 0xfU
41128 #define V_SLEW_CAL_OVERRIDE(x) ((x) << S_SLEW_CAL_OVERRIDE)
41129 #define G_SLEW_CAL_OVERRIDE(x) (((x) >> S_SLEW_CAL_OVERRIDE) & M_SLEW_CAL_OVERRIDE)
41131 #define S_SLEW_TARGET_PR_OFFSET 0
41132 #define M_SLEW_TARGET_PR_OFFSET 0x1fU
41133 #define V_SLEW_TARGET_PR_OFFSET(x) ((x) << S_SLEW_TARGET_PR_OFFSET)
41134 #define G_SLEW_TARGET_PR_OFFSET(x) (((x) >> S_SLEW_TARGET_PR_OFFSET) & M_SLEW_TARGET_PR_OFFSET)
41136 #define A_MC_DDRPHY_PC_DP18_PLL_LOCK_STATUS 0x47000
41138 #define S_DP18_PLL_LOCK 1
41139 #define M_DP18_PLL_LOCK 0x7fffU
41140 #define V_DP18_PLL_LOCK(x) ((x) << S_DP18_PLL_LOCK)
41141 #define G_DP18_PLL_LOCK(x) (((x) >> S_DP18_PLL_LOCK) & M_DP18_PLL_LOCK)
41143 #define A_MC_DDRPHY_PC_AD32S_PLL_LOCK_STATUS 0x47004
41145 #define S_AD32S_PLL_LOCK 14
41146 #define M_AD32S_PLL_LOCK 0x3U
41147 #define V_AD32S_PLL_LOCK(x) ((x) << S_AD32S_PLL_LOCK)
41148 #define G_AD32S_PLL_LOCK(x) (((x) >> S_AD32S_PLL_LOCK) & M_AD32S_PLL_LOCK)
41150 #define A_MC_DDRPHY_PC_RANK_PAIR0 0x47008
41152 #define S_RANK_PAIR0_PRI 13
41153 #define M_RANK_PAIR0_PRI 0x7U
41154 #define V_RANK_PAIR0_PRI(x) ((x) << S_RANK_PAIR0_PRI)
41155 #define G_RANK_PAIR0_PRI(x) (((x) >> S_RANK_PAIR0_PRI) & M_RANK_PAIR0_PRI)
41157 #define S_RANK_PAIR0_PRI_V 12
41158 #define V_RANK_PAIR0_PRI_V(x) ((x) << S_RANK_PAIR0_PRI_V)
41159 #define F_RANK_PAIR0_PRI_V V_RANK_PAIR0_PRI_V(1U)
41161 #define S_RANK_PAIR0_SEC 9
41162 #define M_RANK_PAIR0_SEC 0x7U
41163 #define V_RANK_PAIR0_SEC(x) ((x) << S_RANK_PAIR0_SEC)
41164 #define G_RANK_PAIR0_SEC(x) (((x) >> S_RANK_PAIR0_SEC) & M_RANK_PAIR0_SEC)
41166 #define S_RANK_PAIR0_SEC_V 8
41167 #define V_RANK_PAIR0_SEC_V(x) ((x) << S_RANK_PAIR0_SEC_V)
41168 #define F_RANK_PAIR0_SEC_V V_RANK_PAIR0_SEC_V(1U)
41170 #define S_RANK_PAIR1_PRI 5
41171 #define M_RANK_PAIR1_PRI 0x7U
41172 #define V_RANK_PAIR1_PRI(x) ((x) << S_RANK_PAIR1_PRI)
41173 #define G_RANK_PAIR1_PRI(x) (((x) >> S_RANK_PAIR1_PRI) & M_RANK_PAIR1_PRI)
41175 #define S_RANK_PAIR1_PRI_V 4
41176 #define V_RANK_PAIR1_PRI_V(x) ((x) << S_RANK_PAIR1_PRI_V)
41177 #define F_RANK_PAIR1_PRI_V V_RANK_PAIR1_PRI_V(1U)
41179 #define S_RANK_PAIR1_SEC 1
41180 #define M_RANK_PAIR1_SEC 0x7U
41181 #define V_RANK_PAIR1_SEC(x) ((x) << S_RANK_PAIR1_SEC)
41182 #define G_RANK_PAIR1_SEC(x) (((x) >> S_RANK_PAIR1_SEC) & M_RANK_PAIR1_SEC)
41184 #define S_RANK_PAIR1_SEC_V 0
41185 #define V_RANK_PAIR1_SEC_V(x) ((x) << S_RANK_PAIR1_SEC_V)
41186 #define F_RANK_PAIR1_SEC_V V_RANK_PAIR1_SEC_V(1U)
41188 #define A_MC_DDRPHY_PC_RANK_PAIR1 0x4700c
41190 #define S_RANK_PAIR2_PRI 13
41191 #define M_RANK_PAIR2_PRI 0x7U
41192 #define V_RANK_PAIR2_PRI(x) ((x) << S_RANK_PAIR2_PRI)
41193 #define G_RANK_PAIR2_PRI(x) (((x) >> S_RANK_PAIR2_PRI) & M_RANK_PAIR2_PRI)
41195 #define S_RANK_PAIR2_PRI_V 12
41196 #define V_RANK_PAIR2_PRI_V(x) ((x) << S_RANK_PAIR2_PRI_V)
41197 #define F_RANK_PAIR2_PRI_V V_RANK_PAIR2_PRI_V(1U)
41199 #define S_RANK_PAIR2_SEC 9
41200 #define M_RANK_PAIR2_SEC 0x7U
41201 #define V_RANK_PAIR2_SEC(x) ((x) << S_RANK_PAIR2_SEC)
41202 #define G_RANK_PAIR2_SEC(x) (((x) >> S_RANK_PAIR2_SEC) & M_RANK_PAIR2_SEC)
41204 #define S_RANK_PAIR2_SEC_V 8
41205 #define V_RANK_PAIR2_SEC_V(x) ((x) << S_RANK_PAIR2_SEC_V)
41206 #define F_RANK_PAIR2_SEC_V V_RANK_PAIR2_SEC_V(1U)
41208 #define S_RANK_PAIR3_PRI 5
41209 #define M_RANK_PAIR3_PRI 0x7U
41210 #define V_RANK_PAIR3_PRI(x) ((x) << S_RANK_PAIR3_PRI)
41211 #define G_RANK_PAIR3_PRI(x) (((x) >> S_RANK_PAIR3_PRI) & M_RANK_PAIR3_PRI)
41213 #define S_RANK_PAIR3_PRI_V 4
41214 #define V_RANK_PAIR3_PRI_V(x) ((x) << S_RANK_PAIR3_PRI_V)
41215 #define F_RANK_PAIR3_PRI_V V_RANK_PAIR3_PRI_V(1U)
41217 #define S_RANK_PAIR3_SEC 1
41218 #define M_RANK_PAIR3_SEC 0x7U
41219 #define V_RANK_PAIR3_SEC(x) ((x) << S_RANK_PAIR3_SEC)
41220 #define G_RANK_PAIR3_SEC(x) (((x) >> S_RANK_PAIR3_SEC) & M_RANK_PAIR3_SEC)
41222 #define S_RANK_PAIR3_SEC_V 0
41223 #define V_RANK_PAIR3_SEC_V(x) ((x) << S_RANK_PAIR3_SEC_V)
41224 #define F_RANK_PAIR3_SEC_V V_RANK_PAIR3_SEC_V(1U)
41226 #define A_MC_DDRPHY_PC_BASE_CNTR0 0x47010
41228 #define S_PERIODIC_BASE_CNTR0 0
41229 #define M_PERIODIC_BASE_CNTR0 0xffffU
41230 #define V_PERIODIC_BASE_CNTR0(x) ((x) << S_PERIODIC_BASE_CNTR0)
41231 #define G_PERIODIC_BASE_CNTR0(x) (((x) >> S_PERIODIC_BASE_CNTR0) & M_PERIODIC_BASE_CNTR0)
41233 #define A_MC_DDRPHY_PC_RELOAD_VALUE0 0x47014
41235 #define S_PERIODIC_CAL_REQ_EN 15
41236 #define V_PERIODIC_CAL_REQ_EN(x) ((x) << S_PERIODIC_CAL_REQ_EN)
41237 #define F_PERIODIC_CAL_REQ_EN V_PERIODIC_CAL_REQ_EN(1U)
41239 #define S_PERIODIC_RELOAD_VALUE0 0
41240 #define M_PERIODIC_RELOAD_VALUE0 0x7fffU
41241 #define V_PERIODIC_RELOAD_VALUE0(x) ((x) << S_PERIODIC_RELOAD_VALUE0)
41242 #define G_PERIODIC_RELOAD_VALUE0(x) (((x) >> S_PERIODIC_RELOAD_VALUE0) & M_PERIODIC_RELOAD_VALUE0)
41244 #define A_MC_DDRPHY_PC_BASE_CNTR1 0x47018
41246 #define S_PERIODIC_BASE_CNTR1 0
41247 #define M_PERIODIC_BASE_CNTR1 0xffffU
41248 #define V_PERIODIC_BASE_CNTR1(x) ((x) << S_PERIODIC_BASE_CNTR1)
41249 #define G_PERIODIC_BASE_CNTR1(x) (((x) >> S_PERIODIC_BASE_CNTR1) & M_PERIODIC_BASE_CNTR1)
41251 #define A_MC_DDRPHY_PC_CAL_TIMER 0x4701c
41253 #define S_PERIODIC_CAL_TIMER 0
41254 #define M_PERIODIC_CAL_TIMER 0xffffU
41255 #define V_PERIODIC_CAL_TIMER(x) ((x) << S_PERIODIC_CAL_TIMER)
41256 #define G_PERIODIC_CAL_TIMER(x) (((x) >> S_PERIODIC_CAL_TIMER) & M_PERIODIC_CAL_TIMER)
41258 #define A_MC_DDRPHY_PC_CAL_TIMER_RELOAD_VALUE 0x47020
41260 #define S_PERIODIC_TIMER_RELOAD_VALUE 0
41261 #define M_PERIODIC_TIMER_RELOAD_VALUE 0xffffU
41262 #define V_PERIODIC_TIMER_RELOAD_VALUE(x) ((x) << S_PERIODIC_TIMER_RELOAD_VALUE)
41263 #define G_PERIODIC_TIMER_RELOAD_VALUE(x) (((x) >> S_PERIODIC_TIMER_RELOAD_VALUE) & M_PERIODIC_TIMER_RELOAD_VALUE)
41265 #define A_MC_DDRPHY_PC_ZCAL_TIMER 0x47024
41267 #define S_PERIODIC_ZCAL_TIMER 0
41268 #define M_PERIODIC_ZCAL_TIMER 0xffffU
41269 #define V_PERIODIC_ZCAL_TIMER(x) ((x) << S_PERIODIC_ZCAL_TIMER)
41270 #define G_PERIODIC_ZCAL_TIMER(x) (((x) >> S_PERIODIC_ZCAL_TIMER) & M_PERIODIC_ZCAL_TIMER)
41272 #define A_MC_DDRPHY_PC_ZCAL_TIMER_RELOAD_VALUE 0x47028
41273 #define A_MC_DDRPHY_PC_PER_CAL_CONFIG 0x4702c
41275 #define S_PER_ENA_RANK_PAIR 12
41276 #define M_PER_ENA_RANK_PAIR 0xfU
41277 #define V_PER_ENA_RANK_PAIR(x) ((x) << S_PER_ENA_RANK_PAIR)
41278 #define G_PER_ENA_RANK_PAIR(x) (((x) >> S_PER_ENA_RANK_PAIR) & M_PER_ENA_RANK_PAIR)
41280 #define S_PER_ENA_ZCAL 11
41281 #define V_PER_ENA_ZCAL(x) ((x) << S_PER_ENA_ZCAL)
41282 #define F_PER_ENA_ZCAL V_PER_ENA_ZCAL(1U)
41284 #define S_PER_ENA_SYSCLK_ALIGN 10
41285 #define V_PER_ENA_SYSCLK_ALIGN(x) ((x) << S_PER_ENA_SYSCLK_ALIGN)
41286 #define F_PER_ENA_SYSCLK_ALIGN V_PER_ENA_SYSCLK_ALIGN(1U)
41288 #define S_ENA_PER_RDCLK_ALIGN 9
41289 #define V_ENA_PER_RDCLK_ALIGN(x) ((x) << S_ENA_PER_RDCLK_ALIGN)
41290 #define F_ENA_PER_RDCLK_ALIGN V_ENA_PER_RDCLK_ALIGN(1U)
41292 #define S_ENA_PER_DQS_ALIGN 8
41293 #define V_ENA_PER_DQS_ALIGN(x) ((x) << S_ENA_PER_DQS_ALIGN)
41294 #define F_ENA_PER_DQS_ALIGN V_ENA_PER_DQS_ALIGN(1U)
41296 #define S_ENA_PER_READ_CTR 7
41297 #define V_ENA_PER_READ_CTR(x) ((x) << S_ENA_PER_READ_CTR)
41298 #define F_ENA_PER_READ_CTR V_ENA_PER_READ_CTR(1U)
41300 #define S_PER_NEXT_RANK_PAIR 5
41301 #define M_PER_NEXT_RANK_PAIR 0x3U
41302 #define V_PER_NEXT_RANK_PAIR(x) ((x) << S_PER_NEXT_RANK_PAIR)
41303 #define G_PER_NEXT_RANK_PAIR(x) (((x) >> S_PER_NEXT_RANK_PAIR) & M_PER_NEXT_RANK_PAIR)
41305 #define S_FAST_SIM_PER_CNTR 4
41306 #define V_FAST_SIM_PER_CNTR(x) ((x) << S_FAST_SIM_PER_CNTR)
41307 #define F_FAST_SIM_PER_CNTR V_FAST_SIM_PER_CNTR(1U)
41309 #define S_START_INIT_CAL 3
41310 #define V_START_INIT_CAL(x) ((x) << S_START_INIT_CAL)
41311 #define F_START_INIT_CAL V_START_INIT_CAL(1U)
41313 #define S_START_PER_CAL 2
41314 #define V_START_PER_CAL(x) ((x) << S_START_PER_CAL)
41315 #define F_START_PER_CAL V_START_PER_CAL(1U)
41317 #define A_MC_DDRPHY_PC_CONFIG0 0x47030
41319 #define S_PROTOCOL_DDR 12
41320 #define M_PROTOCOL_DDR 0xfU
41321 #define V_PROTOCOL_DDR(x) ((x) << S_PROTOCOL_DDR)
41322 #define G_PROTOCOL_DDR(x) (((x) >> S_PROTOCOL_DDR) & M_PROTOCOL_DDR)
41324 #define S_DATA_MUX4_1MODE 11
41325 #define V_DATA_MUX4_1MODE(x) ((x) << S_DATA_MUX4_1MODE)
41326 #define F_DATA_MUX4_1MODE V_DATA_MUX4_1MODE(1U)
41328 #define S_DDR4_CMD_SIG_REDUCTION 9
41329 #define V_DDR4_CMD_SIG_REDUCTION(x) ((x) << S_DDR4_CMD_SIG_REDUCTION)
41330 #define F_DDR4_CMD_SIG_REDUCTION V_DDR4_CMD_SIG_REDUCTION(1U)
41332 #define S_SYSCLK_2X_MEMINTCLKO 8
41333 #define V_SYSCLK_2X_MEMINTCLKO(x) ((x) << S_SYSCLK_2X_MEMINTCLKO)
41334 #define F_SYSCLK_2X_MEMINTCLKO V_SYSCLK_2X_MEMINTCLKO(1U)
41336 #define S_RANK_OVERRIDE 7
41337 #define V_RANK_OVERRIDE(x) ((x) << S_RANK_OVERRIDE)
41338 #define F_RANK_OVERRIDE V_RANK_OVERRIDE(1U)
41340 #define S_RANK_OVERRIDE_VALUE 4
41341 #define M_RANK_OVERRIDE_VALUE 0x7U
41342 #define V_RANK_OVERRIDE_VALUE(x) ((x) << S_RANK_OVERRIDE_VALUE)
41343 #define G_RANK_OVERRIDE_VALUE(x) (((x) >> S_RANK_OVERRIDE_VALUE) & M_RANK_OVERRIDE_VALUE)
41345 #define S_LOW_LATENCY 3
41346 #define V_LOW_LATENCY(x) ((x) << S_LOW_LATENCY)
41347 #define F_LOW_LATENCY V_LOW_LATENCY(1U)
41349 #define S_DDR4_BANK_REFRESH 2
41350 #define V_DDR4_BANK_REFRESH(x) ((x) << S_DDR4_BANK_REFRESH)
41351 #define F_DDR4_BANK_REFRESH V_DDR4_BANK_REFRESH(1U)
41353 #define S_DDR4_VLEVEL_BANK_GROUP 1
41354 #define V_DDR4_VLEVEL_BANK_GROUP(x) ((x) << S_DDR4_VLEVEL_BANK_GROUP)
41355 #define F_DDR4_VLEVEL_BANK_GROUP V_DDR4_VLEVEL_BANK_GROUP(1U)
41357 #define A_MC_DDRPHY_PC_CONFIG1 0x47034
41359 #define S_WRITE_LATENCY_OFFSET 12
41360 #define M_WRITE_LATENCY_OFFSET 0xfU
41361 #define V_WRITE_LATENCY_OFFSET(x) ((x) << S_WRITE_LATENCY_OFFSET)
41362 #define G_WRITE_LATENCY_OFFSET(x) (((x) >> S_WRITE_LATENCY_OFFSET) & M_WRITE_LATENCY_OFFSET)
41364 #define S_READ_LATENCY_OFFSET 8
41365 #define M_READ_LATENCY_OFFSET 0xfU
41366 #define V_READ_LATENCY_OFFSET(x) ((x) << S_READ_LATENCY_OFFSET)
41367 #define G_READ_LATENCY_OFFSET(x) (((x) >> S_READ_LATENCY_OFFSET) & M_READ_LATENCY_OFFSET)
41369 #define S_MEMCTL_CIC_FAST 7
41370 #define V_MEMCTL_CIC_FAST(x) ((x) << S_MEMCTL_CIC_FAST)
41371 #define F_MEMCTL_CIC_FAST V_MEMCTL_CIC_FAST(1U)
41373 #define S_MEMCTL_CTRN_IGNORE 6
41374 #define V_MEMCTL_CTRN_IGNORE(x) ((x) << S_MEMCTL_CTRN_IGNORE)
41375 #define F_MEMCTL_CTRN_IGNORE V_MEMCTL_CTRN_IGNORE(1U)
41377 #define S_DISABLE_MEMCTL_CAL 5
41378 #define V_DISABLE_MEMCTL_CAL(x) ((x) << S_DISABLE_MEMCTL_CAL)
41379 #define F_DISABLE_MEMCTL_CAL V_DISABLE_MEMCTL_CAL(1U)
41381 #define A_MC_DDRPHY_PC_RESETS 0x47038
41383 #define S_PLL_RESET 15
41384 #define V_PLL_RESET(x) ((x) << S_PLL_RESET)
41385 #define F_PLL_RESET V_PLL_RESET(1U)
41387 #define S_SYSCLK_RESET 14
41388 #define V_SYSCLK_RESET(x) ((x) << S_SYSCLK_RESET)
41389 #define F_SYSCLK_RESET V_SYSCLK_RESET(1U)
41391 #define A_MC_DDRPHY_PC_PER_ZCAL_CONFIG 0x4703c
41393 #define S_PER_ZCAL_ENA_RANK 8
41394 #define M_PER_ZCAL_ENA_RANK 0xffU
41395 #define V_PER_ZCAL_ENA_RANK(x) ((x) << S_PER_ZCAL_ENA_RANK)
41396 #define G_PER_ZCAL_ENA_RANK(x) (((x) >> S_PER_ZCAL_ENA_RANK) & M_PER_ZCAL_ENA_RANK)
41398 #define S_PER_ZCAL_NEXT_RANK 5
41399 #define M_PER_ZCAL_NEXT_RANK 0x7U
41400 #define V_PER_ZCAL_NEXT_RANK(x) ((x) << S_PER_ZCAL_NEXT_RANK)
41401 #define G_PER_ZCAL_NEXT_RANK(x) (((x) >> S_PER_ZCAL_NEXT_RANK) & M_PER_ZCAL_NEXT_RANK)
41403 #define S_START_PER_ZCAL 4
41404 #define V_START_PER_ZCAL(x) ((x) << S_START_PER_ZCAL)
41405 #define F_START_PER_ZCAL V_START_PER_ZCAL(1U)
41407 #define A_MC_DDRPHY_PC_RANK_GROUP 0x47044
41409 #define S_ADDR_MIRROR_RP0_PRI 15
41410 #define V_ADDR_MIRROR_RP0_PRI(x) ((x) << S_ADDR_MIRROR_RP0_PRI)
41411 #define F_ADDR_MIRROR_RP0_PRI V_ADDR_MIRROR_RP0_PRI(1U)
41413 #define S_ADDR_MIRROR_RP0_SEC 14
41414 #define V_ADDR_MIRROR_RP0_SEC(x) ((x) << S_ADDR_MIRROR_RP0_SEC)
41415 #define F_ADDR_MIRROR_RP0_SEC V_ADDR_MIRROR_RP0_SEC(1U)
41417 #define S_ADDR_MIRROR_RP1_PRI 13
41418 #define V_ADDR_MIRROR_RP1_PRI(x) ((x) << S_ADDR_MIRROR_RP1_PRI)
41419 #define F_ADDR_MIRROR_RP1_PRI V_ADDR_MIRROR_RP1_PRI(1U)
41421 #define S_ADDR_MIRROR_RP1_SEC 12
41422 #define V_ADDR_MIRROR_RP1_SEC(x) ((x) << S_ADDR_MIRROR_RP1_SEC)
41423 #define F_ADDR_MIRROR_RP1_SEC V_ADDR_MIRROR_RP1_SEC(1U)
41425 #define S_ADDR_MIRROR_RP2_PRI 11
41426 #define V_ADDR_MIRROR_RP2_PRI(x) ((x) << S_ADDR_MIRROR_RP2_PRI)
41427 #define F_ADDR_MIRROR_RP2_PRI V_ADDR_MIRROR_RP2_PRI(1U)
41429 #define S_ADDR_MIRROR_RP2_SEC 10
41430 #define V_ADDR_MIRROR_RP2_SEC(x) ((x) << S_ADDR_MIRROR_RP2_SEC)
41431 #define F_ADDR_MIRROR_RP2_SEC V_ADDR_MIRROR_RP2_SEC(1U)
41433 #define S_ADDR_MIRROR_RP3_PRI 9
41434 #define V_ADDR_MIRROR_RP3_PRI(x) ((x) << S_ADDR_MIRROR_RP3_PRI)
41435 #define F_ADDR_MIRROR_RP3_PRI V_ADDR_MIRROR_RP3_PRI(1U)
41437 #define S_ADDR_MIRROR_RP3_SEC 8
41438 #define V_ADDR_MIRROR_RP3_SEC(x) ((x) << S_ADDR_MIRROR_RP3_SEC)
41439 #define F_ADDR_MIRROR_RP3_SEC V_ADDR_MIRROR_RP3_SEC(1U)
41441 #define S_RANK_GROUPING 6
41442 #define M_RANK_GROUPING 0x3U
41443 #define V_RANK_GROUPING(x) ((x) << S_RANK_GROUPING)
41444 #define G_RANK_GROUPING(x) (((x) >> S_RANK_GROUPING) & M_RANK_GROUPING)
41446 #define A_MC_DDRPHY_PC_ERROR_STATUS0 0x47048
41448 #define S_RC_ERROR 15
41449 #define V_RC_ERROR(x) ((x) << S_RC_ERROR)
41450 #define F_RC_ERROR V_RC_ERROR(1U)
41452 #define S_WC_ERROR 14
41453 #define V_WC_ERROR(x) ((x) << S_WC_ERROR)
41454 #define F_WC_ERROR V_WC_ERROR(1U)
41456 #define S_SEQ_ERROR 13
41457 #define V_SEQ_ERROR(x) ((x) << S_SEQ_ERROR)
41458 #define F_SEQ_ERROR V_SEQ_ERROR(1U)
41460 #define S_CC_ERROR 12
41461 #define V_CC_ERROR(x) ((x) << S_CC_ERROR)
41462 #define F_CC_ERROR V_CC_ERROR(1U)
41464 #define S_APB_ERROR 11
41465 #define V_APB_ERROR(x) ((x) << S_APB_ERROR)
41466 #define F_APB_ERROR V_APB_ERROR(1U)
41468 #define S_PC_ERROR 10
41469 #define V_PC_ERROR(x) ((x) << S_PC_ERROR)
41470 #define F_PC_ERROR V_PC_ERROR(1U)
41472 #define A_MC_DDRPHY_PC_ERROR_MASK0 0x4704c
41474 #define S_RC_ERROR_MASK 15
41475 #define V_RC_ERROR_MASK(x) ((x) << S_RC_ERROR_MASK)
41476 #define F_RC_ERROR_MASK V_RC_ERROR_MASK(1U)
41478 #define S_WC_ERROR_MASK 14
41479 #define V_WC_ERROR_MASK(x) ((x) << S_WC_ERROR_MASK)
41480 #define F_WC_ERROR_MASK V_WC_ERROR_MASK(1U)
41482 #define S_SEQ_ERROR_MASK 13
41483 #define V_SEQ_ERROR_MASK(x) ((x) << S_SEQ_ERROR_MASK)
41484 #define F_SEQ_ERROR_MASK V_SEQ_ERROR_MASK(1U)
41486 #define S_CC_ERROR_MASK 12
41487 #define V_CC_ERROR_MASK(x) ((x) << S_CC_ERROR_MASK)
41488 #define F_CC_ERROR_MASK V_CC_ERROR_MASK(1U)
41490 #define S_APB_ERROR_MASK 11
41491 #define V_APB_ERROR_MASK(x) ((x) << S_APB_ERROR_MASK)
41492 #define F_APB_ERROR_MASK V_APB_ERROR_MASK(1U)
41494 #define S_PC_ERROR_MASK 10
41495 #define V_PC_ERROR_MASK(x) ((x) << S_PC_ERROR_MASK)
41496 #define F_PC_ERROR_MASK V_PC_ERROR_MASK(1U)
41498 #define A_MC_DDRPHY_PC_IO_PVT_FET_CONTROL 0x47050
41501 #define M_PVTP 0x1fU
41502 #define V_PVTP(x) ((x) << S_PVTP)
41503 #define G_PVTP(x) (((x) >> S_PVTP) & M_PVTP)
41506 #define M_PVTN 0x1fU
41507 #define V_PVTN(x) ((x) << S_PVTN)
41508 #define G_PVTN(x) (((x) >> S_PVTN) & M_PVTN)
41510 #define S_PVT_OVERRIDE 5
41511 #define V_PVT_OVERRIDE(x) ((x) << S_PVT_OVERRIDE)
41512 #define F_PVT_OVERRIDE V_PVT_OVERRIDE(1U)
41514 #define S_ENABLE_ZCAL 4
41515 #define V_ENABLE_ZCAL(x) ((x) << S_ENABLE_ZCAL)
41516 #define F_ENABLE_ZCAL V_ENABLE_ZCAL(1U)
41518 #define A_MC_DDRPHY_PC_VREF_DRV_CONTROL 0x47054
41520 #define S_VREFDQ0DSGN 15
41521 #define V_VREFDQ0DSGN(x) ((x) << S_VREFDQ0DSGN)
41522 #define F_VREFDQ0DSGN V_VREFDQ0DSGN(1U)
41524 #define S_VREFDQ0D 11
41525 #define M_VREFDQ0D 0xfU
41526 #define V_VREFDQ0D(x) ((x) << S_VREFDQ0D)
41527 #define G_VREFDQ0D(x) (((x) >> S_VREFDQ0D) & M_VREFDQ0D)
41529 #define S_VREFDQ1DSGN 10
41530 #define V_VREFDQ1DSGN(x) ((x) << S_VREFDQ1DSGN)
41531 #define F_VREFDQ1DSGN V_VREFDQ1DSGN(1U)
41533 #define S_VREFDQ1D 6
41534 #define M_VREFDQ1D 0xfU
41535 #define V_VREFDQ1D(x) ((x) << S_VREFDQ1D)
41536 #define G_VREFDQ1D(x) (((x) >> S_VREFDQ1D) & M_VREFDQ1D)
41538 #define A_MC_DDRPHY_PC_INIT_CAL_CONFIG0 0x47058
41540 #define S_ENA_WR_LEVEL 15
41541 #define V_ENA_WR_LEVEL(x) ((x) << S_ENA_WR_LEVEL)
41542 #define F_ENA_WR_LEVEL V_ENA_WR_LEVEL(1U)
41544 #define S_ENA_INITIAL_PAT_WR 14
41545 #define V_ENA_INITIAL_PAT_WR(x) ((x) << S_ENA_INITIAL_PAT_WR)
41546 #define F_ENA_INITIAL_PAT_WR V_ENA_INITIAL_PAT_WR(1U)
41548 #define S_ENA_DQS_ALIGN 13
41549 #define V_ENA_DQS_ALIGN(x) ((x) << S_ENA_DQS_ALIGN)
41550 #define F_ENA_DQS_ALIGN V_ENA_DQS_ALIGN(1U)
41552 #define S_ENA_RDCLK_ALIGN 12
41553 #define V_ENA_RDCLK_ALIGN(x) ((x) << S_ENA_RDCLK_ALIGN)
41554 #define F_ENA_RDCLK_ALIGN V_ENA_RDCLK_ALIGN(1U)
41556 #define S_ENA_READ_CTR 11
41557 #define V_ENA_READ_CTR(x) ((x) << S_ENA_READ_CTR)
41558 #define F_ENA_READ_CTR V_ENA_READ_CTR(1U)
41560 #define S_ENA_WRITE_CTR 10
41561 #define V_ENA_WRITE_CTR(x) ((x) << S_ENA_WRITE_CTR)
41562 #define F_ENA_WRITE_CTR V_ENA_WRITE_CTR(1U)
41564 #define S_ENA_INITIAL_COARSE_WR 9
41565 #define V_ENA_INITIAL_COARSE_WR(x) ((x) << S_ENA_INITIAL_COARSE_WR)
41566 #define F_ENA_INITIAL_COARSE_WR V_ENA_INITIAL_COARSE_WR(1U)
41568 #define S_ENA_COARSE_RD 8
41569 #define V_ENA_COARSE_RD(x) ((x) << S_ENA_COARSE_RD)
41570 #define F_ENA_COARSE_RD V_ENA_COARSE_RD(1U)
41572 #define S_ENA_CUSTOM_RD 7
41573 #define V_ENA_CUSTOM_RD(x) ((x) << S_ENA_CUSTOM_RD)
41574 #define F_ENA_CUSTOM_RD V_ENA_CUSTOM_RD(1U)
41576 #define S_ENA_CUSTOM_WR 6
41577 #define V_ENA_CUSTOM_WR(x) ((x) << S_ENA_CUSTOM_WR)
41578 #define F_ENA_CUSTOM_WR V_ENA_CUSTOM_WR(1U)
41580 #define S_ABORT_ON_CAL_ERROR 5
41581 #define V_ABORT_ON_CAL_ERROR(x) ((x) << S_ABORT_ON_CAL_ERROR)
41582 #define F_ABORT_ON_CAL_ERROR V_ABORT_ON_CAL_ERROR(1U)
41584 #define S_ENA_DIGITAL_EYE 4
41585 #define V_ENA_DIGITAL_EYE(x) ((x) << S_ENA_DIGITAL_EYE)
41586 #define F_ENA_DIGITAL_EYE V_ENA_DIGITAL_EYE(1U)
41588 #define S_ENA_RANK_PAIR 0
41589 #define M_ENA_RANK_PAIR 0xfU
41590 #define V_ENA_RANK_PAIR(x) ((x) << S_ENA_RANK_PAIR)
41591 #define G_ENA_RANK_PAIR(x) (((x) >> S_ENA_RANK_PAIR) & M_ENA_RANK_PAIR)
41593 #define A_MC_DDRPHY_PC_INIT_CAL_CONFIG1 0x4705c
41595 #define S_REFRESH_COUNT 12
41596 #define M_REFRESH_COUNT 0xfU
41597 #define V_REFRESH_COUNT(x) ((x) << S_REFRESH_COUNT)
41598 #define G_REFRESH_COUNT(x) (((x) >> S_REFRESH_COUNT) & M_REFRESH_COUNT)
41600 #define S_REFRESH_CONTROL 10
41601 #define M_REFRESH_CONTROL 0x3U
41602 #define V_REFRESH_CONTROL(x) ((x) << S_REFRESH_CONTROL)
41603 #define G_REFRESH_CONTROL(x) (((x) >> S_REFRESH_CONTROL) & M_REFRESH_CONTROL)
41605 #define S_REFRESH_ALL_RANKS 9
41606 #define V_REFRESH_ALL_RANKS(x) ((x) << S_REFRESH_ALL_RANKS)
41607 #define F_REFRESH_ALL_RANKS V_REFRESH_ALL_RANKS(1U)
41609 #define S_REFRESH_INTERVAL 0
41610 #define M_REFRESH_INTERVAL 0x7fU
41611 #define V_REFRESH_INTERVAL(x) ((x) << S_REFRESH_INTERVAL)
41612 #define G_REFRESH_INTERVAL(x) (((x) >> S_REFRESH_INTERVAL) & M_REFRESH_INTERVAL)
41614 #define A_MC_DDRPHY_PC_INIT_CAL_ERROR 0x47060
41616 #define S_ERROR_WR_LEVEL 15
41617 #define V_ERROR_WR_LEVEL(x) ((x) << S_ERROR_WR_LEVEL)
41618 #define F_ERROR_WR_LEVEL V_ERROR_WR_LEVEL(1U)
41620 #define S_ERROR_INITIAL_PAT_WRITE 14
41621 #define V_ERROR_INITIAL_PAT_WRITE(x) ((x) << S_ERROR_INITIAL_PAT_WRITE)
41622 #define F_ERROR_INITIAL_PAT_WRITE V_ERROR_INITIAL_PAT_WRITE(1U)
41624 #define S_ERROR_DQS_ALIGN 13
41625 #define V_ERROR_DQS_ALIGN(x) ((x) << S_ERROR_DQS_ALIGN)
41626 #define F_ERROR_DQS_ALIGN V_ERROR_DQS_ALIGN(1U)
41628 #define S_ERROR_RDCLK_ALIGN 12
41629 #define V_ERROR_RDCLK_ALIGN(x) ((x) << S_ERROR_RDCLK_ALIGN)
41630 #define F_ERROR_RDCLK_ALIGN V_ERROR_RDCLK_ALIGN(1U)
41632 #define S_ERROR_READ_CTR 11
41633 #define V_ERROR_READ_CTR(x) ((x) << S_ERROR_READ_CTR)
41634 #define F_ERROR_READ_CTR V_ERROR_READ_CTR(1U)
41636 #define S_ERROR_WRITE_CTR 10
41637 #define V_ERROR_WRITE_CTR(x) ((x) << S_ERROR_WRITE_CTR)
41638 #define F_ERROR_WRITE_CTR V_ERROR_WRITE_CTR(1U)
41640 #define S_ERROR_INITIAL_COARSE_WR 9
41641 #define V_ERROR_INITIAL_COARSE_WR(x) ((x) << S_ERROR_INITIAL_COARSE_WR)
41642 #define F_ERROR_INITIAL_COARSE_WR V_ERROR_INITIAL_COARSE_WR(1U)
41644 #define S_ERROR_COARSE_RD 8
41645 #define V_ERROR_COARSE_RD(x) ((x) << S_ERROR_COARSE_RD)
41646 #define F_ERROR_COARSE_RD V_ERROR_COARSE_RD(1U)
41648 #define S_ERROR_CUSTOM_RD 7
41649 #define V_ERROR_CUSTOM_RD(x) ((x) << S_ERROR_CUSTOM_RD)
41650 #define F_ERROR_CUSTOM_RD V_ERROR_CUSTOM_RD(1U)
41652 #define S_ERROR_CUSTOM_WR 6
41653 #define V_ERROR_CUSTOM_WR(x) ((x) << S_ERROR_CUSTOM_WR)
41654 #define F_ERROR_CUSTOM_WR V_ERROR_CUSTOM_WR(1U)
41656 #define S_ERROR_DIGITAL_EYE 5
41657 #define V_ERROR_DIGITAL_EYE(x) ((x) << S_ERROR_DIGITAL_EYE)
41658 #define F_ERROR_DIGITAL_EYE V_ERROR_DIGITAL_EYE(1U)
41660 #define S_ERROR_RANK_PAIR 0
41661 #define M_ERROR_RANK_PAIR 0xfU
41662 #define V_ERROR_RANK_PAIR(x) ((x) << S_ERROR_RANK_PAIR)
41663 #define G_ERROR_RANK_PAIR(x) (((x) >> S_ERROR_RANK_PAIR) & M_ERROR_RANK_PAIR)
41665 #define A_MC_DDRPHY_PC_INIT_CAL_STATUS 0x47064
41667 #define S_INIT_CAL_COMPLETE 12
41668 #define M_INIT_CAL_COMPLETE 0xfU
41669 #define V_INIT_CAL_COMPLETE(x) ((x) << S_INIT_CAL_COMPLETE)
41670 #define G_INIT_CAL_COMPLETE(x) (((x) >> S_INIT_CAL_COMPLETE) & M_INIT_CAL_COMPLETE)
41672 #define A_MC_DDRPHY_PC_INIT_CAL_MASK 0x47068
41674 #define S_ERROR_WR_LEVEL_MASK 15
41675 #define V_ERROR_WR_LEVEL_MASK(x) ((x) << S_ERROR_WR_LEVEL_MASK)
41676 #define F_ERROR_WR_LEVEL_MASK V_ERROR_WR_LEVEL_MASK(1U)
41678 #define S_ERROR_INITIAL_PAT_WRITE_MASK 14
41679 #define V_ERROR_INITIAL_PAT_WRITE_MASK(x) ((x) << S_ERROR_INITIAL_PAT_WRITE_MASK)
41680 #define F_ERROR_INITIAL_PAT_WRITE_MASK V_ERROR_INITIAL_PAT_WRITE_MASK(1U)
41682 #define S_ERROR_DQS_ALIGN_MASK 13
41683 #define V_ERROR_DQS_ALIGN_MASK(x) ((x) << S_ERROR_DQS_ALIGN_MASK)
41684 #define F_ERROR_DQS_ALIGN_MASK V_ERROR_DQS_ALIGN_MASK(1U)
41686 #define S_ERROR_RDCLK_ALIGN_MASK 12
41687 #define V_ERROR_RDCLK_ALIGN_MASK(x) ((x) << S_ERROR_RDCLK_ALIGN_MASK)
41688 #define F_ERROR_RDCLK_ALIGN_MASK V_ERROR_RDCLK_ALIGN_MASK(1U)
41690 #define S_ERROR_READ_CTR_MASK 11
41691 #define V_ERROR_READ_CTR_MASK(x) ((x) << S_ERROR_READ_CTR_MASK)
41692 #define F_ERROR_READ_CTR_MASK V_ERROR_READ_CTR_MASK(1U)
41694 #define S_ERROR_WRITE_CTR_MASK 10
41695 #define V_ERROR_WRITE_CTR_MASK(x) ((x) << S_ERROR_WRITE_CTR_MASK)
41696 #define F_ERROR_WRITE_CTR_MASK V_ERROR_WRITE_CTR_MASK(1U)
41698 #define S_ERROR_INITIAL_COARSE_WR_MASK 9
41699 #define V_ERROR_INITIAL_COARSE_WR_MASK(x) ((x) << S_ERROR_INITIAL_COARSE_WR_MASK)
41700 #define F_ERROR_INITIAL_COARSE_WR_MASK V_ERROR_INITIAL_COARSE_WR_MASK(1U)
41702 #define S_ERROR_COARSE_RD_MASK 8
41703 #define V_ERROR_COARSE_RD_MASK(x) ((x) << S_ERROR_COARSE_RD_MASK)
41704 #define F_ERROR_COARSE_RD_MASK V_ERROR_COARSE_RD_MASK(1U)
41706 #define S_ERROR_CUSTOM_RD_MASK 7
41707 #define V_ERROR_CUSTOM_RD_MASK(x) ((x) << S_ERROR_CUSTOM_RD_MASK)
41708 #define F_ERROR_CUSTOM_RD_MASK V_ERROR_CUSTOM_RD_MASK(1U)
41710 #define S_ERROR_CUSTOM_WR_MASK 6
41711 #define V_ERROR_CUSTOM_WR_MASK(x) ((x) << S_ERROR_CUSTOM_WR_MASK)
41712 #define F_ERROR_CUSTOM_WR_MASK V_ERROR_CUSTOM_WR_MASK(1U)
41714 #define S_ERROR_DIGITAL_EYE_MASK 5
41715 #define V_ERROR_DIGITAL_EYE_MASK(x) ((x) << S_ERROR_DIGITAL_EYE_MASK)
41716 #define F_ERROR_DIGITAL_EYE_MASK V_ERROR_DIGITAL_EYE_MASK(1U)
41718 #define A_MC_DDRPHY_PC_IO_PVT_FET_STATUS 0x4706c
41719 #define A_MC_DDRPHY_PC_MR0_PRI_RP 0x47070
41721 #define S_MODEREGISTER0VALUE 0
41722 #define M_MODEREGISTER0VALUE 0xffffU
41723 #define V_MODEREGISTER0VALUE(x) ((x) << S_MODEREGISTER0VALUE)
41724 #define G_MODEREGISTER0VALUE(x) (((x) >> S_MODEREGISTER0VALUE) & M_MODEREGISTER0VALUE)
41726 #define A_MC_DDRPHY_PC_MR1_PRI_RP 0x47074
41728 #define S_MODEREGISTER1VALUE 0
41729 #define M_MODEREGISTER1VALUE 0xffffU
41730 #define V_MODEREGISTER1VALUE(x) ((x) << S_MODEREGISTER1VALUE)
41731 #define G_MODEREGISTER1VALUE(x) (((x) >> S_MODEREGISTER1VALUE) & M_MODEREGISTER1VALUE)
41733 #define A_MC_DDRPHY_PC_MR2_PRI_RP 0x47078
41735 #define S_MODEREGISTER2VALUE 0
41736 #define M_MODEREGISTER2VALUE 0xffffU
41737 #define V_MODEREGISTER2VALUE(x) ((x) << S_MODEREGISTER2VALUE)
41738 #define G_MODEREGISTER2VALUE(x) (((x) >> S_MODEREGISTER2VALUE) & M_MODEREGISTER2VALUE)
41740 #define A_MC_DDRPHY_PC_MR3_PRI_RP 0x4707c
41742 #define S_MODEREGISTER3VALUE 0
41743 #define M_MODEREGISTER3VALUE 0xffffU
41744 #define V_MODEREGISTER3VALUE(x) ((x) << S_MODEREGISTER3VALUE)
41745 #define G_MODEREGISTER3VALUE(x) (((x) >> S_MODEREGISTER3VALUE) & M_MODEREGISTER3VALUE)
41747 #define A_MC_DDRPHY_PC_MR0_SEC_RP 0x47080
41748 #define A_MC_DDRPHY_PC_MR1_SEC_RP 0x47084
41749 #define A_MC_DDRPHY_PC_MR2_SEC_RP 0x47088
41750 #define A_MC_DDRPHY_PC_MR3_SEC_RP 0x4708c
41752 #define S_MODE_REGISTER_3_VALUE 0
41753 #define M_MODE_REGISTER_3_VALUE 0xffffU
41754 #define V_MODE_REGISTER_3_VALUE(x) ((x) << S_MODE_REGISTER_3_VALUE)
41755 #define G_MODE_REGISTER_3_VALUE(x) (((x) >> S_MODE_REGISTER_3_VALUE) & M_MODE_REGISTER_3_VALUE)
41757 #define A_MC_DDRPHY_SEQ_RD_WR_DATA0 0x47200
41759 #define S_DRD_WR_DATA_REG 0
41760 #define M_DRD_WR_DATA_REG 0xffffU
41761 #define V_DRD_WR_DATA_REG(x) ((x) << S_DRD_WR_DATA_REG)
41762 #define G_DRD_WR_DATA_REG(x) (((x) >> S_DRD_WR_DATA_REG) & M_DRD_WR_DATA_REG)
41764 #define A_MC_DDRPHY_SEQ_RD_WR_DATA1 0x47204
41765 #define A_MC_DDRPHY_SEQ_CONFIG0 0x47208
41767 #define S_MPR_PATTERN_BIT 15
41768 #define V_MPR_PATTERN_BIT(x) ((x) << S_MPR_PATTERN_BIT)
41769 #define F_MPR_PATTERN_BIT V_MPR_PATTERN_BIT(1U)
41771 #define S_TWO_CYCLE_ADDR_EN 14
41772 #define V_TWO_CYCLE_ADDR_EN(x) ((x) << S_TWO_CYCLE_ADDR_EN)
41773 #define F_TWO_CYCLE_ADDR_EN V_TWO_CYCLE_ADDR_EN(1U)
41775 #define S_MR_MASK_EN 10
41776 #define M_MR_MASK_EN 0xfU
41777 #define V_MR_MASK_EN(x) ((x) << S_MR_MASK_EN)
41778 #define G_MR_MASK_EN(x) (((x) >> S_MR_MASK_EN) & M_MR_MASK_EN)
41780 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR0 0x4720c
41781 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR1 0x47210
41782 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR2 0x47214
41783 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR3 0x47218
41784 #define A_MC_DDRPHY_SEQ_RESERVED_ADDR4 0x4721c
41785 #define A_MC_DDRPHY_SEQ_ERROR_STATUS0 0x47220
41787 #define S_MULTIPLE_REQ_ERROR 15
41788 #define V_MULTIPLE_REQ_ERROR(x) ((x) << S_MULTIPLE_REQ_ERROR)
41789 #define F_MULTIPLE_REQ_ERROR V_MULTIPLE_REQ_ERROR(1U)
41791 #define S_INVALID_REQTYPE_ERRO 14
41792 #define V_INVALID_REQTYPE_ERRO(x) ((x) << S_INVALID_REQTYPE_ERRO)
41793 #define F_INVALID_REQTYPE_ERRO V_INVALID_REQTYPE_ERRO(1U)
41795 #define S_EARLY_REQ_ERROR 13
41796 #define V_EARLY_REQ_ERROR(x) ((x) << S_EARLY_REQ_ERROR)
41797 #define F_EARLY_REQ_ERROR V_EARLY_REQ_ERROR(1U)
41799 #define S_MULTIPLE_REQ_SOURCE 10
41800 #define M_MULTIPLE_REQ_SOURCE 0x7U
41801 #define V_MULTIPLE_REQ_SOURCE(x) ((x) << S_MULTIPLE_REQ_SOURCE)
41802 #define G_MULTIPLE_REQ_SOURCE(x) (((x) >> S_MULTIPLE_REQ_SOURCE) & M_MULTIPLE_REQ_SOURCE)
41804 #define S_INVALID_REQTYPE 6
41805 #define M_INVALID_REQTYPE 0xfU
41806 #define V_INVALID_REQTYPE(x) ((x) << S_INVALID_REQTYPE)
41807 #define G_INVALID_REQTYPE(x) (((x) >> S_INVALID_REQTYPE) & M_INVALID_REQTYPE)
41809 #define S_INVALID_REQ_SOURCE 3
41810 #define M_INVALID_REQ_SOURCE 0x7U
41811 #define V_INVALID_REQ_SOURCE(x) ((x) << S_INVALID_REQ_SOURCE)
41812 #define G_INVALID_REQ_SOURCE(x) (((x) >> S_INVALID_REQ_SOURCE) & M_INVALID_REQ_SOURCE)
41814 #define S_EARLY_REQ_SOURCE 0
41815 #define M_EARLY_REQ_SOURCE 0x7U
41816 #define V_EARLY_REQ_SOURCE(x) ((x) << S_EARLY_REQ_SOURCE)
41817 #define G_EARLY_REQ_SOURCE(x) (((x) >> S_EARLY_REQ_SOURCE) & M_EARLY_REQ_SOURCE)
41819 #define A_MC_DDRPHY_SEQ_ERROR_MASK0 0x47224
41821 #define S_MULT_REQ_ERR_MASK 15
41822 #define V_MULT_REQ_ERR_MASK(x) ((x) << S_MULT_REQ_ERR_MASK)
41823 #define F_MULT_REQ_ERR_MASK V_MULT_REQ_ERR_MASK(1U)
41825 #define S_INVALID_REQTYPE_ERR_MASK 14
41826 #define V_INVALID_REQTYPE_ERR_MASK(x) ((x) << S_INVALID_REQTYPE_ERR_MASK)
41827 #define F_INVALID_REQTYPE_ERR_MASK V_INVALID_REQTYPE_ERR_MASK(1U)
41829 #define S_EARLY_REQ_ERR_MASK 13
41830 #define V_EARLY_REQ_ERR_MASK(x) ((x) << S_EARLY_REQ_ERR_MASK)
41831 #define F_EARLY_REQ_ERR_MASK V_EARLY_REQ_ERR_MASK(1U)
41833 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG0 0x47228
41835 #define S_ODT_WR_VALUES_BITS0_7 8
41836 #define M_ODT_WR_VALUES_BITS0_7 0xffU
41837 #define V_ODT_WR_VALUES_BITS0_7(x) ((x) << S_ODT_WR_VALUES_BITS0_7)
41838 #define G_ODT_WR_VALUES_BITS0_7(x) (((x) >> S_ODT_WR_VALUES_BITS0_7) & M_ODT_WR_VALUES_BITS0_7)
41840 #define S_ODT_WR_VALUES_BITS8_15 0
41841 #define M_ODT_WR_VALUES_BITS8_15 0xffU
41842 #define V_ODT_WR_VALUES_BITS8_15(x) ((x) << S_ODT_WR_VALUES_BITS8_15)
41843 #define G_ODT_WR_VALUES_BITS8_15(x) (((x) >> S_ODT_WR_VALUES_BITS8_15) & M_ODT_WR_VALUES_BITS8_15)
41845 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG1 0x4722c
41846 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG2 0x47230
41847 #define A_MC_DDRPHY_SEQ_ODT_WR_CONFIG3 0x47234
41848 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG0 0x47238
41850 #define S_ODT_RD_VALUES_X2 8
41851 #define M_ODT_RD_VALUES_X2 0xffU
41852 #define V_ODT_RD_VALUES_X2(x) ((x) << S_ODT_RD_VALUES_X2)
41853 #define G_ODT_RD_VALUES_X2(x) (((x) >> S_ODT_RD_VALUES_X2) & M_ODT_RD_VALUES_X2)
41855 #define S_ODT_RD_VALUES_X2PLUS1 0
41856 #define M_ODT_RD_VALUES_X2PLUS1 0xffU
41857 #define V_ODT_RD_VALUES_X2PLUS1(x) ((x) << S_ODT_RD_VALUES_X2PLUS1)
41858 #define G_ODT_RD_VALUES_X2PLUS1(x) (((x) >> S_ODT_RD_VALUES_X2PLUS1) & M_ODT_RD_VALUES_X2PLUS1)
41860 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG1 0x4723c
41861 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG2 0x47240
41862 #define A_MC_DDRPHY_SEQ_ODT_RD_CONFIG3 0x47244
41863 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM0 0x47248
41865 #define S_TMOD_CYCLES 12
41866 #define M_TMOD_CYCLES 0xfU
41867 #define V_TMOD_CYCLES(x) ((x) << S_TMOD_CYCLES)
41868 #define G_TMOD_CYCLES(x) (((x) >> S_TMOD_CYCLES) & M_TMOD_CYCLES)
41870 #define S_TRCD_CYCLES 8
41871 #define M_TRCD_CYCLES 0xfU
41872 #define V_TRCD_CYCLES(x) ((x) << S_TRCD_CYCLES)
41873 #define G_TRCD_CYCLES(x) (((x) >> S_TRCD_CYCLES) & M_TRCD_CYCLES)
41875 #define S_TRP_CYCLES 4
41876 #define M_TRP_CYCLES 0xfU
41877 #define V_TRP_CYCLES(x) ((x) << S_TRP_CYCLES)
41878 #define G_TRP_CYCLES(x) (((x) >> S_TRP_CYCLES) & M_TRP_CYCLES)
41880 #define S_TRFC_CYCLES 0
41881 #define M_TRFC_CYCLES 0xfU
41882 #define V_TRFC_CYCLES(x) ((x) << S_TRFC_CYCLES)
41883 #define G_TRFC_CYCLES(x) (((x) >> S_TRFC_CYCLES) & M_TRFC_CYCLES)
41885 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM1 0x4724c
41887 #define S_TZQINIT_CYCLES 12
41888 #define M_TZQINIT_CYCLES 0xfU
41889 #define V_TZQINIT_CYCLES(x) ((x) << S_TZQINIT_CYCLES)
41890 #define G_TZQINIT_CYCLES(x) (((x) >> S_TZQINIT_CYCLES) & M_TZQINIT_CYCLES)
41892 #define S_TZQCS_CYCLES 8
41893 #define M_TZQCS_CYCLES 0xfU
41894 #define V_TZQCS_CYCLES(x) ((x) << S_TZQCS_CYCLES)
41895 #define G_TZQCS_CYCLES(x) (((x) >> S_TZQCS_CYCLES) & M_TZQCS_CYCLES)
41897 #define S_TWLDQSEN_CYCLES 4
41898 #define M_TWLDQSEN_CYCLES 0xfU
41899 #define V_TWLDQSEN_CYCLES(x) ((x) << S_TWLDQSEN_CYCLES)
41900 #define G_TWLDQSEN_CYCLES(x) (((x) >> S_TWLDQSEN_CYCLES) & M_TWLDQSEN_CYCLES)
41902 #define S_TWRMRD_CYCLES 0
41903 #define M_TWRMRD_CYCLES 0xfU
41904 #define V_TWRMRD_CYCLES(x) ((x) << S_TWRMRD_CYCLES)
41905 #define G_TWRMRD_CYCLES(x) (((x) >> S_TWRMRD_CYCLES) & M_TWRMRD_CYCLES)
41907 #define A_MC_DDRPHY_SEQ_MEM_TIMING_PARAM2 0x47250
41909 #define S_TODTLON_OFF_CYCLES 12
41910 #define M_TODTLON_OFF_CYCLES 0xfU
41911 #define V_TODTLON_OFF_CYCLES(x) ((x) << S_TODTLON_OFF_CYCLES)
41912 #define G_TODTLON_OFF_CYCLES(x) (((x) >> S_TODTLON_OFF_CYCLES) & M_TODTLON_OFF_CYCLES)
41914 #define S_TRC_CYCLES 8
41915 #define M_TRC_CYCLES 0xfU
41916 #define V_TRC_CYCLES(x) ((x) << S_TRC_CYCLES)
41917 #define G_TRC_CYCLES(x) (((x) >> S_TRC_CYCLES) & M_TRC_CYCLES)
41919 #define S_TMRSC_CYCLES 4
41920 #define M_TMRSC_CYCLES 0xfU
41921 #define V_TMRSC_CYCLES(x) ((x) << S_TMRSC_CYCLES)
41922 #define G_TMRSC_CYCLES(x) (((x) >> S_TMRSC_CYCLES) & M_TMRSC_CYCLES)
41924 #define A_MC_DDRPHY_RC_CONFIG0 0x47400
41926 #define S_GLOBAL_PHY_OFFSET 12
41927 #define M_GLOBAL_PHY_OFFSET 0xfU
41928 #define V_GLOBAL_PHY_OFFSET(x) ((x) << S_GLOBAL_PHY_OFFSET)
41929 #define G_GLOBAL_PHY_OFFSET(x) (((x) >> S_GLOBAL_PHY_OFFSET) & M_GLOBAL_PHY_OFFSET)
41931 #define S_ADVANCE_RD_VALID 11
41932 #define V_ADVANCE_RD_VALID(x) ((x) << S_ADVANCE_RD_VALID)
41933 #define F_ADVANCE_RD_VALID V_ADVANCE_RD_VALID(1U)
41935 #define S_SINGLE_BIT_MPR_RP0 6
41936 #define V_SINGLE_BIT_MPR_RP0(x) ((x) << S_SINGLE_BIT_MPR_RP0)
41937 #define F_SINGLE_BIT_MPR_RP0 V_SINGLE_BIT_MPR_RP0(1U)
41939 #define S_SINGLE_BIT_MPR_RP1 5
41940 #define V_SINGLE_BIT_MPR_RP1(x) ((x) << S_SINGLE_BIT_MPR_RP1)
41941 #define F_SINGLE_BIT_MPR_RP1 V_SINGLE_BIT_MPR_RP1(1U)
41943 #define S_SINGLE_BIT_MPR_RP2 4
41944 #define V_SINGLE_BIT_MPR_RP2(x) ((x) << S_SINGLE_BIT_MPR_RP2)
41945 #define F_SINGLE_BIT_MPR_RP2 V_SINGLE_BIT_MPR_RP2(1U)
41947 #define S_SINGLE_BIT_MPR_RP3 3
41948 #define V_SINGLE_BIT_MPR_RP3(x) ((x) << S_SINGLE_BIT_MPR_RP3)
41949 #define F_SINGLE_BIT_MPR_RP3 V_SINGLE_BIT_MPR_RP3(1U)
41951 #define S_ALIGN_ON_EVEN_CYCLES 2
41952 #define V_ALIGN_ON_EVEN_CYCLES(x) ((x) << S_ALIGN_ON_EVEN_CYCLES)
41953 #define F_ALIGN_ON_EVEN_CYCLES V_ALIGN_ON_EVEN_CYCLES(1U)
41955 #define S_PERFORM_RDCLK_ALIGN 1
41956 #define V_PERFORM_RDCLK_ALIGN(x) ((x) << S_PERFORM_RDCLK_ALIGN)
41957 #define F_PERFORM_RDCLK_ALIGN V_PERFORM_RDCLK_ALIGN(1U)
41959 #define S_STAGGERED_PATTERN 0
41960 #define V_STAGGERED_PATTERN(x) ((x) << S_STAGGERED_PATTERN)
41961 #define F_STAGGERED_PATTERN V_STAGGERED_PATTERN(1U)
41963 #define A_MC_DDRPHY_RC_CONFIG1 0x47404
41965 #define S_OUTER_LOOP_CNT 2
41966 #define M_OUTER_LOOP_CNT 0x3fffU
41967 #define V_OUTER_LOOP_CNT(x) ((x) << S_OUTER_LOOP_CNT)
41968 #define G_OUTER_LOOP_CNT(x) (((x) >> S_OUTER_LOOP_CNT) & M_OUTER_LOOP_CNT)
41970 #define A_MC_DDRPHY_RC_CONFIG2 0x47408
41972 #define S_CONSEQ_PASS 11
41973 #define M_CONSEQ_PASS 0x1fU
41974 #define V_CONSEQ_PASS(x) ((x) << S_CONSEQ_PASS)
41975 #define G_CONSEQ_PASS(x) (((x) >> S_CONSEQ_PASS) & M_CONSEQ_PASS)
41977 #define S_BURST_WINDOW 5
41978 #define M_BURST_WINDOW 0x3U
41979 #define V_BURST_WINDOW(x) ((x) << S_BURST_WINDOW)
41980 #define G_BURST_WINDOW(x) (((x) >> S_BURST_WINDOW) & M_BURST_WINDOW)
41982 #define S_ALLOW_RD_FIFO_AUTO_R_ESET 4
41983 #define V_ALLOW_RD_FIFO_AUTO_R_ESET(x) ((x) << S_ALLOW_RD_FIFO_AUTO_R_ESET)
41984 #define F_ALLOW_RD_FIFO_AUTO_R_ESET V_ALLOW_RD_FIFO_AUTO_R_ESET(1U)
41986 #define A_MC_DDRPHY_RC_ERROR_STATUS0 0x47414
41988 #define S_RD_CNTL_ERROR 15
41989 #define V_RD_CNTL_ERROR(x) ((x) << S_RD_CNTL_ERROR)
41990 #define F_RD_CNTL_ERROR V_RD_CNTL_ERROR(1U)
41992 #define A_MC_DDRPHY_RC_ERROR_MASK0 0x47418
41994 #define S_RD_CNTL_ERROR_MASK 15
41995 #define V_RD_CNTL_ERROR_MASK(x) ((x) << S_RD_CNTL_ERROR_MASK)
41996 #define F_RD_CNTL_ERROR_MASK V_RD_CNTL_ERROR_MASK(1U)
41998 #define A_MC_DDRPHY_RC_CONFIG3 0x4741c
42000 #define S_FINE_CAL_STEP_SIZE 13
42001 #define M_FINE_CAL_STEP_SIZE 0x7U
42002 #define V_FINE_CAL_STEP_SIZE(x) ((x) << S_FINE_CAL_STEP_SIZE)
42003 #define G_FINE_CAL_STEP_SIZE(x) (((x) >> S_FINE_CAL_STEP_SIZE) & M_FINE_CAL_STEP_SIZE)
42005 #define S_COARSE_CAL_STEP_SIZE 9
42006 #define M_COARSE_CAL_STEP_SIZE 0xfU
42007 #define V_COARSE_CAL_STEP_SIZE(x) ((x) << S_COARSE_CAL_STEP_SIZE)
42008 #define G_COARSE_CAL_STEP_SIZE(x) (((x) >> S_COARSE_CAL_STEP_SIZE) & M_COARSE_CAL_STEP_SIZE)
42010 #define S_DQ_SEL_QUAD 7
42011 #define M_DQ_SEL_QUAD 0x3U
42012 #define V_DQ_SEL_QUAD(x) ((x) << S_DQ_SEL_QUAD)
42013 #define G_DQ_SEL_QUAD(x) (((x) >> S_DQ_SEL_QUAD) & M_DQ_SEL_QUAD)
42015 #define S_DQ_SEL_LANE 4
42016 #define M_DQ_SEL_LANE 0x7U
42017 #define V_DQ_SEL_LANE(x) ((x) << S_DQ_SEL_LANE)
42018 #define G_DQ_SEL_LANE(x) (((x) >> S_DQ_SEL_LANE) & M_DQ_SEL_LANE)
42020 #define A_MC_DDRPHY_RC_PERIODIC 0x47420
42021 #define A_MC_DDRPHY_WC_CONFIG0 0x47600
42023 #define S_TWLO_TWLOE 8
42024 #define M_TWLO_TWLOE 0xffU
42025 #define V_TWLO_TWLOE(x) ((x) << S_TWLO_TWLOE)
42026 #define G_TWLO_TWLOE(x) (((x) >> S_TWLO_TWLOE) & M_TWLO_TWLOE)
42028 #define S_WL_ONE_DQS_PULSE 7
42029 #define V_WL_ONE_DQS_PULSE(x) ((x) << S_WL_ONE_DQS_PULSE)
42030 #define F_WL_ONE_DQS_PULSE V_WL_ONE_DQS_PULSE(1U)
42032 #define S_FW_WR_RD 1
42033 #define M_FW_WR_RD 0x3fU
42034 #define V_FW_WR_RD(x) ((x) << S_FW_WR_RD)
42035 #define G_FW_WR_RD(x) (((x) >> S_FW_WR_RD) & M_FW_WR_RD)
42037 #define S_CUSTOM_INIT_WRITE 0
42038 #define V_CUSTOM_INIT_WRITE(x) ((x) << S_CUSTOM_INIT_WRITE)
42039 #define F_CUSTOM_INIT_WRITE V_CUSTOM_INIT_WRITE(1U)
42041 #define A_MC_DDRPHY_WC_CONFIG1 0x47604
42043 #define S_BIG_STEP 12
42044 #define M_BIG_STEP 0xfU
42045 #define V_BIG_STEP(x) ((x) << S_BIG_STEP)
42046 #define G_BIG_STEP(x) (((x) >> S_BIG_STEP) & M_BIG_STEP)
42048 #define S_SMALL_STEP 9
42049 #define M_SMALL_STEP 0x7U
42050 #define V_SMALL_STEP(x) ((x) << S_SMALL_STEP)
42051 #define G_SMALL_STEP(x) (((x) >> S_SMALL_STEP) & M_SMALL_STEP)
42053 #define S_WR_PRE_DLY 3
42054 #define M_WR_PRE_DLY 0x3fU
42055 #define V_WR_PRE_DLY(x) ((x) << S_WR_PRE_DLY)
42056 #define G_WR_PRE_DLY(x) (((x) >> S_WR_PRE_DLY) & M_WR_PRE_DLY)
42058 #define A_MC_DDRPHY_WC_CONFIG2 0x47608
42060 #define S_NUM_VALID_SAMPLES 12
42061 #define M_NUM_VALID_SAMPLES 0xfU
42062 #define V_NUM_VALID_SAMPLES(x) ((x) << S_NUM_VALID_SAMPLES)
42063 #define G_NUM_VALID_SAMPLES(x) (((x) >> S_NUM_VALID_SAMPLES) & M_NUM_VALID_SAMPLES)
42065 #define S_FW_RD_WR 6
42066 #define M_FW_RD_WR 0x3fU
42067 #define V_FW_RD_WR(x) ((x) << S_FW_RD_WR)
42068 #define G_FW_RD_WR(x) (((x) >> S_FW_RD_WR) & M_FW_RD_WR)
42070 #define A_MC_DDRPHY_WC_ERROR_STATUS0 0x4760c
42072 #define S_WR_CNTL_ERROR 15
42073 #define V_WR_CNTL_ERROR(x) ((x) << S_WR_CNTL_ERROR)
42074 #define F_WR_CNTL_ERROR V_WR_CNTL_ERROR(1U)
42076 #define A_MC_DDRPHY_WC_ERROR_MASK0 0x47610
42078 #define S_WR_CNTL_ERROR_MASK 15
42079 #define V_WR_CNTL_ERROR_MASK(x) ((x) << S_WR_CNTL_ERROR_MASK)
42080 #define F_WR_CNTL_ERROR_MASK V_WR_CNTL_ERROR_MASK(1U)
42082 #define A_MC_DDRPHY_WC_CONFIG3 0x47614
42084 #define S_DDR4_MRS_CMD_DQ_EN 15
42085 #define V_DDR4_MRS_CMD_DQ_EN(x) ((x) << S_DDR4_MRS_CMD_DQ_EN)
42086 #define F_DDR4_MRS_CMD_DQ_EN V_DDR4_MRS_CMD_DQ_EN(1U)
42088 #define S_MRS_CMD_DQ_ON 9
42089 #define M_MRS_CMD_DQ_ON 0x3fU
42090 #define V_MRS_CMD_DQ_ON(x) ((x) << S_MRS_CMD_DQ_ON)
42091 #define G_MRS_CMD_DQ_ON(x) (((x) >> S_MRS_CMD_DQ_ON) & M_MRS_CMD_DQ_ON)
42093 #define S_MRS_CMD_DQ_OFF 3
42094 #define M_MRS_CMD_DQ_OFF 0x3fU
42095 #define V_MRS_CMD_DQ_OFF(x) ((x) << S_MRS_CMD_DQ_OFF)
42096 #define G_MRS_CMD_DQ_OFF(x) (((x) >> S_MRS_CMD_DQ_OFF) & M_MRS_CMD_DQ_OFF)
42098 #define A_MC_DDRPHY_WC_WRCLK_CNTL 0x47618
42100 #define S_WRCLK_CAL_START 15
42101 #define V_WRCLK_CAL_START(x) ((x) << S_WRCLK_CAL_START)
42102 #define F_WRCLK_CAL_START V_WRCLK_CAL_START(1U)
42104 #define S_WRCLK_CAL_DONE 14
42105 #define V_WRCLK_CAL_DONE(x) ((x) << S_WRCLK_CAL_DONE)
42106 #define F_WRCLK_CAL_DONE V_WRCLK_CAL_DONE(1U)
42108 #define A_MC_DDRPHY_APB_CONFIG0 0x47800
42110 #define S_DISABLE_PARITY_CHECKER 15
42111 #define V_DISABLE_PARITY_CHECKER(x) ((x) << S_DISABLE_PARITY_CHECKER)
42112 #define F_DISABLE_PARITY_CHECKER V_DISABLE_PARITY_CHECKER(1U)
42114 #define S_GENERATE_EVEN_PARITY 14
42115 #define V_GENERATE_EVEN_PARITY(x) ((x) << S_GENERATE_EVEN_PARITY)
42116 #define F_GENERATE_EVEN_PARITY V_GENERATE_EVEN_PARITY(1U)
42118 #define S_FORCE_ON_CLK_GATE 13
42119 #define V_FORCE_ON_CLK_GATE(x) ((x) << S_FORCE_ON_CLK_GATE)
42120 #define F_FORCE_ON_CLK_GATE V_FORCE_ON_CLK_GATE(1U)
42122 #define S_DEBUG_BUS_SEL_LO 12
42123 #define V_DEBUG_BUS_SEL_LO(x) ((x) << S_DEBUG_BUS_SEL_LO)
42124 #define F_DEBUG_BUS_SEL_LO V_DEBUG_BUS_SEL_LO(1U)
42126 #define S_DEBUG_BUS_SEL_HI 8
42127 #define M_DEBUG_BUS_SEL_HI 0xfU
42128 #define V_DEBUG_BUS_SEL_HI(x) ((x) << S_DEBUG_BUS_SEL_HI)
42129 #define G_DEBUG_BUS_SEL_HI(x) (((x) >> S_DEBUG_BUS_SEL_HI) & M_DEBUG_BUS_SEL_HI)
42131 #define A_MC_DDRPHY_APB_ERROR_STATUS0 0x47804
42133 #define S_INVALID_ADDRESS 15
42134 #define V_INVALID_ADDRESS(x) ((x) << S_INVALID_ADDRESS)
42135 #define F_INVALID_ADDRESS V_INVALID_ADDRESS(1U)
42137 #define S_WR_PAR_ERR 14
42138 #define V_WR_PAR_ERR(x) ((x) << S_WR_PAR_ERR)
42139 #define F_WR_PAR_ERR V_WR_PAR_ERR(1U)
42141 #define A_MC_DDRPHY_APB_ERROR_MASK0 0x47808
42143 #define S_INVALID_ADDRESS_MASK 15
42144 #define V_INVALID_ADDRESS_MASK(x) ((x) << S_INVALID_ADDRESS_MASK)
42145 #define F_INVALID_ADDRESS_MASK V_INVALID_ADDRESS_MASK(1U)
42147 #define S_WR_PAR_ERR_MASK 14
42148 #define V_WR_PAR_ERR_MASK(x) ((x) << S_WR_PAR_ERR_MASK)
42149 #define F_WR_PAR_ERR_MASK V_WR_PAR_ERR_MASK(1U)
42151 #define A_MC_DDRPHY_APB_DP18_POPULATION 0x4780c
42153 #define S_DP18_0_POPULATED 15
42154 #define V_DP18_0_POPULATED(x) ((x) << S_DP18_0_POPULATED)
42155 #define F_DP18_0_POPULATED V_DP18_0_POPULATED(1U)
42157 #define S_DP18_1_POPULATED 14
42158 #define V_DP18_1_POPULATED(x) ((x) << S_DP18_1_POPULATED)
42159 #define F_DP18_1_POPULATED V_DP18_1_POPULATED(1U)
42161 #define S_DP18_2_POPULATED 13
42162 #define V_DP18_2_POPULATED(x) ((x) << S_DP18_2_POPULATED)
42163 #define F_DP18_2_POPULATED V_DP18_2_POPULATED(1U)
42165 #define S_DP18_3_POPULATED 12
42166 #define V_DP18_3_POPULATED(x) ((x) << S_DP18_3_POPULATED)
42167 #define F_DP18_3_POPULATED V_DP18_3_POPULATED(1U)
42169 #define S_DP18_4_POPULATED 11
42170 #define V_DP18_4_POPULATED(x) ((x) << S_DP18_4_POPULATED)
42171 #define F_DP18_4_POPULATED V_DP18_4_POPULATED(1U)
42173 #define S_DP18_5_POPULATED 10
42174 #define V_DP18_5_POPULATED(x) ((x) << S_DP18_5_POPULATED)
42175 #define F_DP18_5_POPULATED V_DP18_5_POPULATED(1U)
42177 #define S_DP18_6_POPULATED 9
42178 #define V_DP18_6_POPULATED(x) ((x) << S_DP18_6_POPULATED)
42179 #define F_DP18_6_POPULATED V_DP18_6_POPULATED(1U)
42181 #define S_DP18_7_POPULATED 8
42182 #define V_DP18_7_POPULATED(x) ((x) << S_DP18_7_POPULATED)
42183 #define F_DP18_7_POPULATED V_DP18_7_POPULATED(1U)
42185 #define S_DP18_8_POPULATED 7
42186 #define V_DP18_8_POPULATED(x) ((x) << S_DP18_8_POPULATED)
42187 #define F_DP18_8_POPULATED V_DP18_8_POPULATED(1U)
42189 #define S_DP18_9_POPULATED 6
42190 #define V_DP18_9_POPULATED(x) ((x) << S_DP18_9_POPULATED)
42191 #define F_DP18_9_POPULATED V_DP18_9_POPULATED(1U)
42193 #define S_DP18_10_POPULATED 5
42194 #define V_DP18_10_POPULATED(x) ((x) << S_DP18_10_POPULATED)
42195 #define F_DP18_10_POPULATED V_DP18_10_POPULATED(1U)
42197 #define S_DP18_11_POPULATED 4
42198 #define V_DP18_11_POPULATED(x) ((x) << S_DP18_11_POPULATED)
42199 #define F_DP18_11_POPULATED V_DP18_11_POPULATED(1U)
42201 #define S_DP18_12_POPULATED 3
42202 #define V_DP18_12_POPULATED(x) ((x) << S_DP18_12_POPULATED)
42203 #define F_DP18_12_POPULATED V_DP18_12_POPULATED(1U)
42205 #define S_DP18_13_POPULATED 2
42206 #define V_DP18_13_POPULATED(x) ((x) << S_DP18_13_POPULATED)
42207 #define F_DP18_13_POPULATED V_DP18_13_POPULATED(1U)
42209 #define S_DP18_14_POPULATED 1
42210 #define V_DP18_14_POPULATED(x) ((x) << S_DP18_14_POPULATED)
42211 #define F_DP18_14_POPULATED V_DP18_14_POPULATED(1U)
42213 #define A_MC_DDRPHY_APB_ADR_POPULATION 0x47810
42215 #define S_ADR16_0_POPULATED 15
42216 #define V_ADR16_0_POPULATED(x) ((x) << S_ADR16_0_POPULATED)
42217 #define F_ADR16_0_POPULATED V_ADR16_0_POPULATED(1U)
42219 #define S_ADR16_1_POPULATED 14
42220 #define V_ADR16_1_POPULATED(x) ((x) << S_ADR16_1_POPULATED)
42221 #define F_ADR16_1_POPULATED V_ADR16_1_POPULATED(1U)
42223 #define S_ADR16_2_POPULATED 13
42224 #define V_ADR16_2_POPULATED(x) ((x) << S_ADR16_2_POPULATED)
42225 #define F_ADR16_2_POPULATED V_ADR16_2_POPULATED(1U)
42227 #define S_ADR16_3_POPULATED 12
42228 #define V_ADR16_3_POPULATED(x) ((x) << S_ADR16_3_POPULATED)
42229 #define F_ADR16_3_POPULATED V_ADR16_3_POPULATED(1U)
42231 #define S_ADR12_0_POPULATED 7
42232 #define V_ADR12_0_POPULATED(x) ((x) << S_ADR12_0_POPULATED)
42233 #define F_ADR12_0_POPULATED V_ADR12_0_POPULATED(1U)
42235 #define S_ADR12_1_POPULATED 6
42236 #define V_ADR12_1_POPULATED(x) ((x) << S_ADR12_1_POPULATED)
42237 #define F_ADR12_1_POPULATED V_ADR12_1_POPULATED(1U)
42239 #define S_ADR12_2_POPULATED 5
42240 #define V_ADR12_2_POPULATED(x) ((x) << S_ADR12_2_POPULATED)
42241 #define F_ADR12_2_POPULATED V_ADR12_2_POPULATED(1U)
42243 #define S_ADR12_3_POPULATED 4
42244 #define V_ADR12_3_POPULATED(x) ((x) << S_ADR12_3_POPULATED)
42245 #define F_ADR12_3_POPULATED V_ADR12_3_POPULATED(1U)
42247 #define A_MC_DDRPHY_APB_ATEST_MUX_SEL 0x47814
42249 #define S_ATEST_CNTL 10
42250 #define M_ATEST_CNTL 0x3fU
42251 #define V_ATEST_CNTL(x) ((x) << S_ATEST_CNTL)
42252 #define G_ATEST_CNTL(x) (((x) >> S_ATEST_CNTL) & M_ATEST_CNTL)
42254 /* registers for module MC_1 */
42255 #define MC_1_BASE_ADDR 0x48000
42257 /* registers for module EDC_T50 */
42258 #define EDC_T50_BASE_ADDR 0x50000
42260 #define A_EDC_H_REF 0x50000
42262 #define S_EDC_SLEEPSTATUS 31
42263 #define V_EDC_SLEEPSTATUS(x) ((x) << S_EDC_SLEEPSTATUS)
42264 #define F_EDC_SLEEPSTATUS V_EDC_SLEEPSTATUS(1U)
42266 #define S_EDC_SLEEPREQ 30
42267 #define V_EDC_SLEEPREQ(x) ((x) << S_EDC_SLEEPREQ)
42268 #define F_EDC_SLEEPREQ V_EDC_SLEEPREQ(1U)
42270 #define S_PING_PONG 29
42271 #define V_PING_PONG(x) ((x) << S_PING_PONG)
42272 #define F_PING_PONG V_PING_PONG(1U)
42274 #define A_EDC_H_BIST_CMD 0x50004
42275 #define A_EDC_H_BIST_CMD_ADDR 0x50008
42276 #define A_EDC_H_BIST_CMD_LEN 0x5000c
42277 #define A_EDC_H_BIST_DATA_PATTERN 0x50010
42278 #define A_EDC_H_BIST_USER_WDATA0 0x50014
42279 #define A_EDC_H_BIST_USER_WDATA1 0x50018
42280 #define A_EDC_H_BIST_USER_WDATA2 0x5001c
42281 #define A_EDC_H_BIST_NUM_ERR 0x50020
42282 #define A_EDC_H_BIST_ERR_FIRST_ADDR 0x50024
42283 #define A_EDC_H_BIST_STATUS_RDATA 0x50028
42284 #define A_EDC_H_PAR_ENABLE 0x50070
42286 #define S_PERR_PAR_ENABLE 0
42287 #define V_PERR_PAR_ENABLE(x) ((x) << S_PERR_PAR_ENABLE)
42288 #define F_PERR_PAR_ENABLE V_PERR_PAR_ENABLE(1U)
42290 #define A_EDC_H_INT_ENABLE 0x50074
42291 #define A_EDC_H_INT_CAUSE 0x50078
42292 #define A_EDC_H_ECC_STATUS 0x5007c
42293 #define A_EDC_H_ECC_ERR_SEL 0x50080
42297 #define V_CFG(x) ((x) << S_CFG)
42298 #define G_CFG(x) (((x) >> S_CFG) & M_CFG)
42300 #define A_EDC_H_ECC_ERR_ADDR 0x50084
42302 #define S_ECC_ADDR 0
42303 #define M_ECC_ADDR 0x7fffffU
42304 #define V_ECC_ADDR(x) ((x) << S_ECC_ADDR)
42305 #define G_ECC_ADDR(x) (((x) >> S_ECC_ADDR) & M_ECC_ADDR)
42307 #define A_EDC_H_ECC_ERR_DATA_RDATA 0x50090
42308 #define A_EDC_H_BIST_CRC_SEED 0x50400
42310 /* registers for module EDC_T51 */
42311 #define EDC_T51_BASE_ADDR 0x50800
42313 /* registers for module HMA_T5 */
42314 #define HMA_T5_BASE_ADDR 0x51000
42316 #define A_HMA_TABLE_ACCESS 0x51000
42319 #define V_TRIG(x) ((x) << S_TRIG)
42320 #define F_TRIG V_TRIG(1U)
42323 #define V_RW(x) ((x) << S_RW)
42324 #define F_RW V_RW(1U)
42327 #define M_L_SEL 0xfU
42328 #define V_L_SEL(x) ((x) << S_L_SEL)
42329 #define G_L_SEL(x) (((x) >> S_L_SEL) & M_L_SEL)
42331 #define A_HMA_TABLE_LINE0 0x51004
42333 #define S_CLIENT_EN 0
42334 #define M_CLIENT_EN 0x1fffU
42335 #define V_CLIENT_EN(x) ((x) << S_CLIENT_EN)
42336 #define G_CLIENT_EN(x) (((x) >> S_CLIENT_EN) & M_CLIENT_EN)
42338 #define A_HMA_TABLE_LINE1 0x51008
42339 #define A_HMA_TABLE_LINE2 0x5100c
42340 #define A_HMA_TABLE_LINE3 0x51010
42341 #define A_HMA_TABLE_LINE4 0x51014
42342 #define A_HMA_TABLE_LINE5 0x51018
42345 #define M_FID 0x7ffU
42346 #define V_FID(x) ((x) << S_FID)
42347 #define G_FID(x) (((x) >> S_FID) & M_FID)
42350 #define V_NOS(x) ((x) << S_NOS)
42351 #define F_NOS V_NOS(1U)
42354 #define V_RO(x) ((x) << S_RO)
42355 #define F_RO V_RO(1U)
42357 #define A_HMA_COOKIE 0x5101c
42360 #define V_C_REQ(x) ((x) << S_C_REQ)
42361 #define F_C_REQ V_C_REQ(1U)
42364 #define M_C_FID 0x7ffU
42365 #define V_C_FID(x) ((x) << S_C_FID)
42366 #define G_C_FID(x) (((x) >> S_C_FID) & M_C_FID)
42369 #define M_C_VAL 0x3ffU
42370 #define V_C_VAL(x) ((x) << S_C_VAL)
42371 #define G_C_VAL(x) (((x) >> S_C_VAL) & M_C_VAL)
42374 #define M_C_SEL 0xfU
42375 #define V_C_SEL(x) ((x) << S_C_SEL)
42376 #define G_C_SEL(x) (((x) >> S_C_SEL) & M_C_SEL)
42378 #define A_HMA_PAR_ENABLE 0x51300
42379 #define A_HMA_INT_ENABLE 0x51304
42380 #define A_HMA_INT_CAUSE 0x51308