2 * Copyright (c) 2009-2013, 2016 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __IW_CXGB4_H__
34 #define __IW_CXGB4_H__
36 #include <linux/list.h>
37 #include <linux/spinlock.h>
38 #include <linux/idr.h>
39 #include <linux/completion.h>
40 #include <linux/netdevice.h>
41 #include <linux/sched.h>
42 #include <linux/pci.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/wait.h>
45 #include <linux/kref.h>
46 #include <linux/timer.h>
50 #include <asm/byteorder.h>
52 #include <netinet/in.h>
53 #include <netinet/toecore.h>
55 #include <rdma/ib_verbs.h>
56 #include <rdma/iw_cm.h>
60 #include "common/common.h"
61 #include "common/t4_msg.h"
62 #include "common/t4_regs.h"
63 #include "common/t4_tcb.h"
66 #define DRV_NAME "iw_cxgbe"
67 #define MOD DRV_NAME ":"
68 #define KTR_IW_CXGBE KTR_SPARE3
70 extern int c4iw_debug;
71 #define PDBG(fmt, args...) \
74 printf(MOD fmt, ## args); \
79 static inline void *cplhdr(struct mbuf *m)
81 return mtod(m, void*);
84 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.pbl.start)
85 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start)
87 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
88 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
90 struct c4iw_id_table {
92 u32 start; /* logical minimal id */
93 u32 last; /* hint for find */
99 struct c4iw_resource {
100 struct c4iw_id_table tpt_table;
101 struct c4iw_id_table qid_table;
102 struct c4iw_id_table pdid_table;
105 struct c4iw_qid_list {
106 struct list_head entry;
110 struct c4iw_dev_ucontext {
111 struct list_head qpids;
112 struct list_head cqids;
116 enum c4iw_rdev_flags {
117 T4_FATAL_ERROR = (1<<0),
129 struct c4iw_stat qid;
131 struct c4iw_stat stag;
132 struct c4iw_stat pbl;
133 struct c4iw_stat rqt;
137 struct adapter *adap;
138 struct c4iw_resource resource;
139 unsigned long qpshift;
141 unsigned long cqshift;
143 struct c4iw_dev_ucontext uctx;
147 struct c4iw_stats stats;
150 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
152 return rdev->flags & T4_FATAL_ERROR;
155 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
157 return (int)(rdev->adap->vres.stag.size >> 5);
160 #define C4IW_WR_TO (10*HZ)
162 struct c4iw_wr_wait {
167 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
170 atomic_set(&wr_waitp->completion, 0);
173 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
176 atomic_set(&wr_waitp->completion, 1);
181 c4iw_wait_for_reply(struct c4iw_rdev *rdev, struct c4iw_wr_wait *wr_waitp,
182 u32 hwtid, u32 qpid, const char *func)
184 struct adapter *sc = rdev->adap;
185 unsigned to = C4IW_WR_TO;
187 while (!atomic_read(&wr_waitp->completion)) {
188 tsleep(wr_waitp, 0, "c4iw_wait", to);
189 if (SIGPENDING(curthread)) {
190 printf("%s - Device %s not responding - "
191 "tid %u qpid %u\n", func,
192 device_get_nameunit(sc->dev), hwtid, qpid);
193 if (c4iw_fatal_error(rdev)) {
194 wr_waitp->ret = -EIO;
201 CTR4(KTR_IW_CXGBE, "%s: FW reply %d tid %u qpid %u",
202 device_get_nameunit(sc->dev), wr_waitp->ret, hwtid, qpid);
203 return (wr_waitp->ret);
207 struct ib_device ibdev;
208 struct c4iw_rdev rdev;
209 u32 device_cap_flags;
214 struct dentry *debugfs_root;
217 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
219 return container_of(ibdev, struct c4iw_dev, ibdev);
222 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
224 return container_of(rdev, struct c4iw_dev, rdev);
227 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
229 return idr_find(&rhp->cqidr, cqid);
232 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
234 return idr_find(&rhp->qpidr, qpid);
237 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
239 return idr_find(&rhp->mmidr, mmid);
242 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
243 void *handle, u32 id, int lock)
249 if (!idr_pre_get(idr, lock ? GFP_KERNEL : GFP_ATOMIC))
252 spin_lock_irq(&rhp->lock);
253 ret = idr_get_new_above(idr, handle, id, &newid);
254 BUG_ON(!ret && newid != id);
256 spin_unlock_irq(&rhp->lock);
257 } while (ret == -EAGAIN);
262 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
263 void *handle, u32 id)
265 return _insert_handle(rhp, idr, handle, id, 1);
268 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
269 void *handle, u32 id)
271 return _insert_handle(rhp, idr, handle, id, 0);
274 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
278 spin_lock_irq(&rhp->lock);
281 spin_unlock_irq(&rhp->lock);
284 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
286 _remove_handle(rhp, idr, id, 1);
289 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
290 struct idr *idr, u32 id)
292 _remove_handle(rhp, idr, id, 0);
298 struct c4iw_dev *rhp;
301 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
303 return container_of(ibpd, struct c4iw_pd, ibpd);
306 struct tpt_attributes {
309 enum fw_ri_mem_perms perms;
318 u32 remote_invaliate_disable:1;
320 u32 mw_bind_enable:1;
326 struct ib_umem *umem;
327 struct c4iw_dev *rhp;
329 struct tpt_attributes attr;
332 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
334 return container_of(ibmr, struct c4iw_mr, ibmr);
339 struct c4iw_dev *rhp;
341 struct tpt_attributes attr;
344 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
346 return container_of(ibmw, struct c4iw_mw, ibmw);
349 struct c4iw_fr_page_list {
350 struct ib_fast_reg_page_list ibpl;
351 DECLARE_PCI_UNMAP_ADDR(mapping);
353 struct c4iw_dev *dev;
357 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
358 struct ib_fast_reg_page_list *ibpl)
360 return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
365 struct c4iw_dev *rhp;
368 spinlock_t comp_handler_lock;
370 wait_queue_head_t wait;
373 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
375 return container_of(ibcq, struct c4iw_cq, ibcq);
378 struct c4iw_mpa_attributes {
380 u8 recv_marker_enabled;
381 u8 xmit_marker_enabled;
383 u8 enhanced_rdma_conn;
388 struct c4iw_qp_attributes {
394 u32 sq_max_sges_rdma_write;
398 u8 enable_rdma_write;
400 u8 enable_mmid0_fastreg;
405 char terminate_buffer[52];
406 u32 terminate_msg_len;
407 u8 is_terminate_local;
408 struct c4iw_mpa_attributes mpa_attr;
409 struct c4iw_ep *llp_stream_handle;
418 struct c4iw_dev *rhp;
420 struct c4iw_qp_attributes attr;
425 wait_queue_head_t wait;
426 struct timer_list timer;
430 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
432 return container_of(ibqp, struct c4iw_qp, ibqp);
435 struct c4iw_ucontext {
436 struct ib_ucontext ibucontext;
437 struct c4iw_dev_ucontext uctx;
439 spinlock_t mmap_lock;
440 struct list_head mmaps;
443 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
445 return container_of(c, struct c4iw_ucontext, ibucontext);
448 struct c4iw_mm_entry {
449 struct list_head entry;
455 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
456 u32 key, unsigned len)
458 struct list_head *pos, *nxt;
459 struct c4iw_mm_entry *mm;
461 spin_lock(&ucontext->mmap_lock);
462 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
464 mm = list_entry(pos, struct c4iw_mm_entry, entry);
465 if (mm->key == key && mm->len == len) {
466 list_del_init(&mm->entry);
467 spin_unlock(&ucontext->mmap_lock);
468 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d",
469 __func__, key, (unsigned long long) mm->addr,
474 spin_unlock(&ucontext->mmap_lock);
478 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
479 struct c4iw_mm_entry *mm)
481 spin_lock(&ucontext->mmap_lock);
482 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", __func__, mm->key,
483 (unsigned long long) mm->addr, mm->len);
484 list_add_tail(&mm->entry, &ucontext->mmaps);
485 spin_unlock(&ucontext->mmap_lock);
488 enum c4iw_qp_attr_mask {
489 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
490 C4IW_QP_ATTR_SQ_DB = 1<<1,
491 C4IW_QP_ATTR_RQ_DB = 1<<2,
492 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
493 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
494 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
495 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
496 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
497 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
498 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
499 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
500 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
501 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
502 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
503 C4IW_QP_ATTR_MAX_ORD |
504 C4IW_QP_ATTR_MAX_IRD |
505 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
506 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
507 C4IW_QP_ATTR_MPA_ATTR |
508 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
511 int c4iw_modify_qp(struct c4iw_dev *rhp,
513 enum c4iw_qp_attr_mask mask,
514 struct c4iw_qp_attributes *attrs,
521 C4IW_QP_STATE_TERMINATE,
522 C4IW_QP_STATE_CLOSING,
526 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
531 return C4IW_QP_STATE_IDLE;
533 return C4IW_QP_STATE_RTS;
535 return C4IW_QP_STATE_CLOSING;
537 return C4IW_QP_STATE_TERMINATE;
539 return C4IW_QP_STATE_ERROR;
545 static inline int to_ib_qp_state(int c4iw_qp_state)
547 switch (c4iw_qp_state) {
548 case C4IW_QP_STATE_IDLE:
550 case C4IW_QP_STATE_RTS:
552 case C4IW_QP_STATE_CLOSING:
554 case C4IW_QP_STATE_TERMINATE:
556 case C4IW_QP_STATE_ERROR:
562 static inline u32 c4iw_ib_to_tpt_access(int a)
564 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
565 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
566 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
567 FW_RI_MEM_ACCESS_LOCAL_READ;
570 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
572 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
573 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
576 enum c4iw_mmid_state {
577 C4IW_STAG_STATE_VALID,
578 C4IW_STAG_STATE_INVALID
581 #define C4IW_NODE_DESC "iw_cxgbe Chelsio Communications"
583 #define MPA_KEY_REQ "MPA ID Req Frame"
584 #define MPA_KEY_REP "MPA ID Rep Frame"
586 #define MPA_MAX_PRIVATE_DATA 256
587 #define MPA_ENHANCED_RDMA_CONN 0x10
588 #define MPA_REJECT 0x20
590 #define MPA_MARKERS 0x80
591 #define MPA_FLAGS_MASK 0xE0
593 #define MPA_V2_PEER2PEER_MODEL 0x8000
594 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
595 #define MPA_V2_RDMA_WRITE_RTR 0x8000
596 #define MPA_V2_RDMA_READ_RTR 0x4000
597 #define MPA_V2_IRD_ORD_MASK 0x3FFF
599 #define c4iw_put_ep(ep) { \
600 CTR4(KTR_IW_CXGBE, "put_ep (%s:%u) ep %p, refcnt %d", \
601 __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
602 WARN_ON(atomic_read(&(ep)->kref.refcount) < 1); \
603 kref_put(&((ep)->kref), _c4iw_free_ep); \
606 #define c4iw_get_ep(ep) { \
607 CTR4(KTR_IW_CXGBE, "get_ep (%s:%u) ep %p, refcnt %d", \
608 __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
609 kref_get(&((ep)->kref)); \
612 void _c4iw_free_ep(struct kref *kref);
618 __be16 private_data_size;
622 struct mpa_v2_conn_params {
627 struct terminate_message {
634 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
636 enum c4iw_layers_types {
640 RDMAP_LOCAL_CATA = 0x00,
641 RDMAP_REMOTE_PROT = 0x01,
642 RDMAP_REMOTE_OP = 0x02,
643 DDP_LOCAL_CATA = 0x00,
644 DDP_TAGGED_ERR = 0x01,
645 DDP_UNTAGGED_ERR = 0x02,
649 enum c4iw_rdma_ecodes {
650 RDMAP_INV_STAG = 0x00,
651 RDMAP_BASE_BOUNDS = 0x01,
652 RDMAP_ACC_VIOL = 0x02,
653 RDMAP_STAG_NOT_ASSOC = 0x03,
654 RDMAP_TO_WRAP = 0x04,
655 RDMAP_INV_VERS = 0x05,
656 RDMAP_INV_OPCODE = 0x06,
657 RDMAP_STREAM_CATA = 0x07,
658 RDMAP_GLOBAL_CATA = 0x08,
659 RDMAP_CANT_INV_STAG = 0x09,
660 RDMAP_UNSPECIFIED = 0xff
663 enum c4iw_ddp_ecodes {
664 DDPT_INV_STAG = 0x00,
665 DDPT_BASE_BOUNDS = 0x01,
666 DDPT_STAG_NOT_ASSOC = 0x02,
668 DDPT_INV_VERS = 0x04,
670 DDPU_INV_MSN_NOBUF = 0x02,
671 DDPU_INV_MSN_RANGE = 0x03,
673 DDPU_MSG_TOOBIG = 0x05,
677 enum c4iw_mpa_ecodes {
679 MPA_MARKER_ERR = 0x03,
680 MPA_LOCAL_CATA = 0x05,
681 MPA_INSUFF_IRD = 0x06,
682 MPA_NOMATCH_RTR = 0x07,
701 PEER_ABORT_IN_PROGRESS = 0,
702 ABORT_REQ_IN_PROGRESS = 1,
703 RELEASE_RESOURCES = 2,
709 enum c4iw_ep_history {
729 CONN_RPL_UPCALL = 19,
730 ACT_RETRY_NOMEM = 20,
731 ACT_RETRY_INUSE = 21,
740 struct c4iw_ep_common {
741 TAILQ_ENTRY(c4iw_ep_common) entry; /* Work queue attachment */
742 struct iw_cm_id *cm_id;
744 struct c4iw_dev *dev;
745 enum c4iw_ep_state state;
748 struct sockaddr_in local_addr;
749 struct sockaddr_in remote_addr;
750 struct c4iw_wr_wait wr_wait;
752 unsigned long history;
755 struct thread *thread;
757 struct mutex so_mutex;
760 struct c4iw_listen_ep {
761 struct c4iw_ep_common com;
767 struct c4iw_ep_common com;
768 struct c4iw_ep *parent_ep;
769 struct timer_list timer;
770 struct list_head entry;
775 struct l2t_entry *l2t;
776 struct dst_entry *dst;
777 struct c4iw_mpa_attributes mpa_attr;
778 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
779 unsigned int mpa_pkt_len;
792 u8 retry_with_mpa_v1;
793 u8 tried_with_mpa_v1;
796 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
798 return cm_id->provider_data;
801 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
803 return cm_id->provider_data;
806 static inline int compute_wscale(int win)
810 while (wscale < 14 && (65535<<wscale) < win)
815 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
816 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
817 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
818 u32 reserved, u32 flags);
819 void c4iw_id_table_free(struct c4iw_id_table *alloc);
821 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct mbuf *m);
823 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
824 struct l2t_entry *l2t);
825 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
826 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
827 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
828 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
829 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
830 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
831 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
832 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
833 void c4iw_destroy_resource(struct c4iw_resource *rscp);
834 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
835 int c4iw_register_device(struct c4iw_dev *dev);
836 void c4iw_unregister_device(struct c4iw_dev *dev);
837 int __init c4iw_cm_init(void);
838 void __exit c4iw_cm_term(void);
839 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
840 struct c4iw_dev_ucontext *uctx);
841 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
842 struct c4iw_dev_ucontext *uctx);
843 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
844 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
845 struct ib_send_wr **bad_wr);
846 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
847 struct ib_recv_wr **bad_wr);
848 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
849 struct ib_mw_bind *mw_bind);
850 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
851 int c4iw_create_listen_ep(struct iw_cm_id *cm_id, int backlog);
852 void c4iw_destroy_listen_ep(struct iw_cm_id *cm_id);
853 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
854 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
855 void c4iw_qp_add_ref(struct ib_qp *qp);
856 void c4iw_qp_rem_ref(struct ib_qp *qp);
857 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
858 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
859 struct ib_device *device,
861 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
862 int c4iw_dealloc_mw(struct ib_mw *mw);
863 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd);
864 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, u64
865 virt, int acc, struct ib_udata *udata, int mr_id);
866 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
867 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
868 struct ib_phys_buf *buffer_list,
872 int c4iw_reregister_phys_mem(struct ib_mr *mr,
875 struct ib_phys_buf *buffer_list,
877 int acc, u64 *iova_start);
878 int c4iw_dereg_mr(struct ib_mr *ib_mr);
879 int c4iw_destroy_cq(struct ib_cq *ib_cq);
880 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
882 struct ib_ucontext *ib_context,
883 struct ib_udata *udata);
884 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
885 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
886 int c4iw_destroy_qp(struct ib_qp *ib_qp);
887 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
888 struct ib_qp_init_attr *attrs,
889 struct ib_udata *udata);
890 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
891 int attr_mask, struct ib_udata *udata);
892 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
893 int attr_mask, struct ib_qp_init_attr *init_attr);
894 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
895 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
896 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
897 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
898 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
899 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct mbuf *m);
900 void c4iw_flush_hw_cq(struct t4_cq *cq);
901 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
902 void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
903 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
904 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
905 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
906 int c4iw_ev_handler(struct sge_iq *, const struct rsp_ctrl *);
907 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
908 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
909 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
910 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
911 struct c4iw_dev_ucontext *uctx);
912 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
913 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
914 struct c4iw_dev_ucontext *uctx);
915 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
916 void process_newconn(struct iw_cm_id *parent_cm_id,
917 struct socket *child_so);
919 extern struct cxgb4_client t4c_client;
920 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
921 extern int c4iw_max_read_depth;
923 #if defined(__i386__) || defined(__amd64__)
924 #define L1_CACHE_BYTES 128
926 #define L1_CACHE_BYTES 32
930 int idr_for_each(struct idr *idp,
931 int (*fn)(int id, void *p, void *data), void *data)
933 int n, id, max, error = 0;
935 struct idr_layer *pa[MAX_LEVEL];
936 struct idr_layer **paa = &pa[0];
938 n = idp->layers * IDR_BITS;
947 p = p->ary[(id >> n) & IDR_MASK];
951 error = fn(id, (void *)p, data);
957 while (n < fls(id)) {
966 void your_reg_device(struct c4iw_dev *dev);
968 #define SGE_CTRLQ_NUM 0