2 * Copyright (c) 2009-2013, 2016 Chelsio, Inc. All rights reserved.
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
17 * - Redistributions in binary form must reproduce the above
18 * copyright notice, this list of conditions and the following
19 * disclaimer in the documentation and/or other materials
20 * provided with the distribution.
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
23 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
25 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
26 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
27 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
28 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
33 #ifndef __IW_CXGB4_H__
34 #define __IW_CXGB4_H__
36 #include <linux/list.h>
37 #include <linux/spinlock.h>
38 #include <linux/idr.h>
39 #include <linux/completion.h>
40 #include <linux/netdevice.h>
41 #include <linux/sched.h>
42 #include <linux/pci.h>
43 #include <linux/dma-mapping.h>
44 #include <linux/wait.h>
45 #include <linux/kref.h>
46 #include <linux/timer.h>
50 #include <asm/byteorder.h>
52 #include <netinet/in.h>
53 #include <netinet/toecore.h>
55 #include <rdma/ib_verbs.h>
56 #include <rdma/iw_cm.h>
60 #include "common/common.h"
61 #include "common/t4_msg.h"
62 #include "common/t4_regs.h"
63 #include "common/t4_tcb.h"
66 #define DRV_NAME "iw_cxgbe"
67 #define MOD DRV_NAME ":"
68 #define KTR_IW_CXGBE KTR_SPARE3
70 extern int c4iw_debug;
71 #define PDBG(fmt, args...) \
74 printf(MOD fmt, ## args); \
79 static inline void *cplhdr(struct mbuf *m)
81 return mtod(m, void*);
84 #define PBL_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.pbl.start)
85 #define RQT_OFF(rdev_p, a) ((a) - (rdev_p)->adap->vres.rq.start)
87 #define C4IW_ID_TABLE_F_RANDOM 1 /* Pseudo-randomize the id's returned */
88 #define C4IW_ID_TABLE_F_EMPTY 2 /* Table is initially empty */
90 struct c4iw_id_table {
92 u32 start; /* logical minimal id */
93 u32 last; /* hint for find */
99 struct c4iw_resource {
100 struct c4iw_id_table tpt_table;
101 struct c4iw_id_table qid_table;
102 struct c4iw_id_table pdid_table;
105 struct c4iw_qid_list {
106 struct list_head entry;
110 struct c4iw_dev_ucontext {
111 struct list_head qpids;
112 struct list_head cqids;
116 enum c4iw_rdev_flags {
117 T4_FATAL_ERROR = (1<<0),
129 struct c4iw_stat qid;
131 struct c4iw_stat stag;
132 struct c4iw_stat pbl;
133 struct c4iw_stat rqt;
137 struct adapter *adap;
138 struct c4iw_resource resource;
139 unsigned long qpshift;
141 unsigned long cqshift;
143 struct c4iw_dev_ucontext uctx;
147 struct c4iw_stats stats;
150 static inline int c4iw_fatal_error(struct c4iw_rdev *rdev)
152 return rdev->flags & T4_FATAL_ERROR;
155 static inline int c4iw_num_stags(struct c4iw_rdev *rdev)
157 return (int)(rdev->adap->vres.stag.size >> 5);
160 #define C4IW_WR_TO (60*HZ)
162 struct c4iw_wr_wait {
164 struct completion completion;
167 static inline void c4iw_init_wr_wait(struct c4iw_wr_wait *wr_waitp)
170 init_completion(&wr_waitp->completion);
173 static inline void c4iw_wake_up(struct c4iw_wr_wait *wr_waitp, int ret)
176 complete(&wr_waitp->completion);
180 c4iw_wait_for_reply(struct c4iw_rdev *rdev, struct c4iw_wr_wait *wr_waitp,
181 u32 hwtid, u32 qpid, const char *func)
183 struct adapter *sc = rdev->adap;
184 unsigned to = C4IW_WR_TO;
187 struct timeval t1, t2;
189 if (c4iw_fatal_error(rdev)) {
190 wr_waitp->ret = -EIO;
196 ret = wait_for_completion_timeout(&wr_waitp->completion, to);
199 timevalsub(&t2, &t1);
200 printf("%s - Device %s not responding after %ld.%06ld "
201 "seconds - tid %u qpid %u\n", func,
202 device_get_nameunit(sc->dev), t2.tv_sec, t2.tv_usec,
204 if (c4iw_fatal_error(rdev)) {
205 wr_waitp->ret = -EIO;
216 timevalsub(&t2, &t1);
217 printf("%s - Device %s reply after %ld.%06ld seconds - "
218 "tid %u qpid %u\n", func, device_get_nameunit(sc->dev),
219 t2.tv_sec, t2.tv_usec, hwtid, qpid);
222 CTR4(KTR_IW_CXGBE, "%p: FW reply %d tid %u qpid %u", sc,
223 wr_waitp->ret, hwtid, qpid);
224 return (wr_waitp->ret);
228 struct ib_device ibdev;
229 struct c4iw_rdev rdev;
230 u32 device_cap_flags;
235 struct dentry *debugfs_root;
238 static inline struct c4iw_dev *to_c4iw_dev(struct ib_device *ibdev)
240 return container_of(ibdev, struct c4iw_dev, ibdev);
243 static inline struct c4iw_dev *rdev_to_c4iw_dev(struct c4iw_rdev *rdev)
245 return container_of(rdev, struct c4iw_dev, rdev);
248 static inline struct c4iw_cq *get_chp(struct c4iw_dev *rhp, u32 cqid)
250 return idr_find(&rhp->cqidr, cqid);
253 static inline struct c4iw_qp *get_qhp(struct c4iw_dev *rhp, u32 qpid)
255 return idr_find(&rhp->qpidr, qpid);
258 static inline struct c4iw_mr *get_mhp(struct c4iw_dev *rhp, u32 mmid)
260 return idr_find(&rhp->mmidr, mmid);
263 static inline int _insert_handle(struct c4iw_dev *rhp, struct idr *idr,
264 void *handle, u32 id, int lock)
270 if (!idr_pre_get(idr, lock ? GFP_KERNEL : GFP_ATOMIC))
273 spin_lock_irq(&rhp->lock);
274 ret = idr_get_new_above(idr, handle, id, &newid);
275 BUG_ON(!ret && newid != id);
277 spin_unlock_irq(&rhp->lock);
278 } while (ret == -EAGAIN);
283 static inline int insert_handle(struct c4iw_dev *rhp, struct idr *idr,
284 void *handle, u32 id)
286 return _insert_handle(rhp, idr, handle, id, 1);
289 static inline int insert_handle_nolock(struct c4iw_dev *rhp, struct idr *idr,
290 void *handle, u32 id)
292 return _insert_handle(rhp, idr, handle, id, 0);
295 static inline void _remove_handle(struct c4iw_dev *rhp, struct idr *idr,
299 spin_lock_irq(&rhp->lock);
302 spin_unlock_irq(&rhp->lock);
305 static inline void remove_handle(struct c4iw_dev *rhp, struct idr *idr, u32 id)
307 _remove_handle(rhp, idr, id, 1);
310 static inline void remove_handle_nolock(struct c4iw_dev *rhp,
311 struct idr *idr, u32 id)
313 _remove_handle(rhp, idr, id, 0);
319 struct c4iw_dev *rhp;
322 static inline struct c4iw_pd *to_c4iw_pd(struct ib_pd *ibpd)
324 return container_of(ibpd, struct c4iw_pd, ibpd);
327 struct tpt_attributes {
330 enum fw_ri_mem_perms perms;
339 u32 remote_invaliate_disable:1;
341 u32 mw_bind_enable:1;
347 struct ib_umem *umem;
348 struct c4iw_dev *rhp;
350 struct tpt_attributes attr;
353 static inline struct c4iw_mr *to_c4iw_mr(struct ib_mr *ibmr)
355 return container_of(ibmr, struct c4iw_mr, ibmr);
360 struct c4iw_dev *rhp;
362 struct tpt_attributes attr;
365 static inline struct c4iw_mw *to_c4iw_mw(struct ib_mw *ibmw)
367 return container_of(ibmw, struct c4iw_mw, ibmw);
370 struct c4iw_fr_page_list {
371 struct ib_fast_reg_page_list ibpl;
372 DECLARE_PCI_UNMAP_ADDR(mapping);
374 struct c4iw_dev *dev;
378 static inline struct c4iw_fr_page_list *to_c4iw_fr_page_list(
379 struct ib_fast_reg_page_list *ibpl)
381 return container_of(ibpl, struct c4iw_fr_page_list, ibpl);
386 struct c4iw_dev *rhp;
389 spinlock_t comp_handler_lock;
391 wait_queue_head_t wait;
394 static inline struct c4iw_cq *to_c4iw_cq(struct ib_cq *ibcq)
396 return container_of(ibcq, struct c4iw_cq, ibcq);
399 struct c4iw_mpa_attributes {
401 u8 recv_marker_enabled;
402 u8 xmit_marker_enabled;
404 u8 enhanced_rdma_conn;
409 struct c4iw_qp_attributes {
415 u32 sq_max_sges_rdma_write;
419 u8 enable_rdma_write;
421 u8 enable_mmid0_fastreg;
426 char terminate_buffer[52];
427 u32 terminate_msg_len;
428 u8 is_terminate_local;
429 struct c4iw_mpa_attributes mpa_attr;
430 struct c4iw_ep *llp_stream_handle;
439 struct c4iw_dev *rhp;
441 struct c4iw_qp_attributes attr;
446 wait_queue_head_t wait;
447 struct timer_list timer;
451 static inline struct c4iw_qp *to_c4iw_qp(struct ib_qp *ibqp)
453 return container_of(ibqp, struct c4iw_qp, ibqp);
456 struct c4iw_ucontext {
457 struct ib_ucontext ibucontext;
458 struct c4iw_dev_ucontext uctx;
460 spinlock_t mmap_lock;
461 struct list_head mmaps;
464 static inline struct c4iw_ucontext *to_c4iw_ucontext(struct ib_ucontext *c)
466 return container_of(c, struct c4iw_ucontext, ibucontext);
469 struct c4iw_mm_entry {
470 struct list_head entry;
476 static inline struct c4iw_mm_entry *remove_mmap(struct c4iw_ucontext *ucontext,
477 u32 key, unsigned len)
479 struct list_head *pos, *nxt;
480 struct c4iw_mm_entry *mm;
482 spin_lock(&ucontext->mmap_lock);
483 list_for_each_safe(pos, nxt, &ucontext->mmaps) {
485 mm = list_entry(pos, struct c4iw_mm_entry, entry);
486 if (mm->key == key && mm->len == len) {
487 list_del_init(&mm->entry);
488 spin_unlock(&ucontext->mmap_lock);
489 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d",
490 __func__, key, (unsigned long long) mm->addr,
495 spin_unlock(&ucontext->mmap_lock);
499 static inline void insert_mmap(struct c4iw_ucontext *ucontext,
500 struct c4iw_mm_entry *mm)
502 spin_lock(&ucontext->mmap_lock);
503 CTR4(KTR_IW_CXGBE, "%s key 0x%x addr 0x%llx len %d", __func__, mm->key,
504 (unsigned long long) mm->addr, mm->len);
505 list_add_tail(&mm->entry, &ucontext->mmaps);
506 spin_unlock(&ucontext->mmap_lock);
509 enum c4iw_qp_attr_mask {
510 C4IW_QP_ATTR_NEXT_STATE = 1 << 0,
511 C4IW_QP_ATTR_SQ_DB = 1<<1,
512 C4IW_QP_ATTR_RQ_DB = 1<<2,
513 C4IW_QP_ATTR_ENABLE_RDMA_READ = 1 << 7,
514 C4IW_QP_ATTR_ENABLE_RDMA_WRITE = 1 << 8,
515 C4IW_QP_ATTR_ENABLE_RDMA_BIND = 1 << 9,
516 C4IW_QP_ATTR_MAX_ORD = 1 << 11,
517 C4IW_QP_ATTR_MAX_IRD = 1 << 12,
518 C4IW_QP_ATTR_LLP_STREAM_HANDLE = 1 << 22,
519 C4IW_QP_ATTR_STREAM_MSG_BUFFER = 1 << 23,
520 C4IW_QP_ATTR_MPA_ATTR = 1 << 24,
521 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE = 1 << 25,
522 C4IW_QP_ATTR_VALID_MODIFY = (C4IW_QP_ATTR_ENABLE_RDMA_READ |
523 C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
524 C4IW_QP_ATTR_MAX_ORD |
525 C4IW_QP_ATTR_MAX_IRD |
526 C4IW_QP_ATTR_LLP_STREAM_HANDLE |
527 C4IW_QP_ATTR_STREAM_MSG_BUFFER |
528 C4IW_QP_ATTR_MPA_ATTR |
529 C4IW_QP_ATTR_QP_CONTEXT_ACTIVATE)
532 int c4iw_modify_qp(struct c4iw_dev *rhp,
534 enum c4iw_qp_attr_mask mask,
535 struct c4iw_qp_attributes *attrs,
542 C4IW_QP_STATE_TERMINATE,
543 C4IW_QP_STATE_CLOSING,
548 * IW_CXGBE event bits.
549 * These bits are used for handling all events for a particular 'ep' serially.
551 #define C4IW_EVENT_SOCKET 0x0001
552 #define C4IW_EVENT_TIMEOUT 0x0002
553 #define C4IW_EVENT_TERM 0x0004
555 static inline int c4iw_convert_state(enum ib_qp_state ib_state)
560 return C4IW_QP_STATE_IDLE;
562 return C4IW_QP_STATE_RTS;
564 return C4IW_QP_STATE_CLOSING;
566 return C4IW_QP_STATE_TERMINATE;
568 return C4IW_QP_STATE_ERROR;
574 static inline int to_ib_qp_state(int c4iw_qp_state)
576 switch (c4iw_qp_state) {
577 case C4IW_QP_STATE_IDLE:
579 case C4IW_QP_STATE_RTS:
581 case C4IW_QP_STATE_CLOSING:
583 case C4IW_QP_STATE_TERMINATE:
585 case C4IW_QP_STATE_ERROR:
591 #define C4IW_DRAIN_OPCODE FW_RI_SGE_EC_CR_RETURN
593 static inline u32 c4iw_ib_to_tpt_access(int a)
595 return (a & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
596 (a & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0) |
597 (a & IB_ACCESS_LOCAL_WRITE ? FW_RI_MEM_ACCESS_LOCAL_WRITE : 0) |
598 FW_RI_MEM_ACCESS_LOCAL_READ;
601 static inline u32 c4iw_ib_to_tpt_bind_access(int acc)
603 return (acc & IB_ACCESS_REMOTE_WRITE ? FW_RI_MEM_ACCESS_REM_WRITE : 0) |
604 (acc & IB_ACCESS_REMOTE_READ ? FW_RI_MEM_ACCESS_REM_READ : 0);
607 enum c4iw_mmid_state {
608 C4IW_STAG_STATE_VALID,
609 C4IW_STAG_STATE_INVALID
612 #define C4IW_NODE_DESC "iw_cxgbe Chelsio Communications"
614 #define MPA_KEY_REQ "MPA ID Req Frame"
615 #define MPA_KEY_REP "MPA ID Rep Frame"
617 #define MPA_MAX_PRIVATE_DATA 256
618 #define MPA_ENHANCED_RDMA_CONN 0x10
619 #define MPA_REJECT 0x20
621 #define MPA_MARKERS 0x80
622 #define MPA_FLAGS_MASK 0xE0
624 #define MPA_V2_PEER2PEER_MODEL 0x8000
625 #define MPA_V2_ZERO_LEN_FPDU_RTR 0x4000
626 #define MPA_V2_RDMA_WRITE_RTR 0x8000
627 #define MPA_V2_RDMA_READ_RTR 0x4000
628 #define MPA_V2_IRD_ORD_MASK 0x3FFF
630 #define c4iw_put_ep(ep) { \
631 CTR4(KTR_IW_CXGBE, "put_ep (%s:%u) ep %p, refcnt %d", \
632 __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
633 WARN_ON(atomic_read(&(ep)->kref.refcount) < 1); \
634 kref_put(&((ep)->kref), _c4iw_free_ep); \
637 #define c4iw_get_ep(ep) { \
638 CTR4(KTR_IW_CXGBE, "get_ep (%s:%u) ep %p, refcnt %d", \
639 __func__, __LINE__, ep, atomic_read(&(ep)->kref.refcount)); \
640 kref_get(&((ep)->kref)); \
643 void _c4iw_free_ep(struct kref *kref);
649 __be16 private_data_size;
653 struct mpa_v2_conn_params {
658 struct terminate_message {
665 #define TERM_MAX_LENGTH (sizeof(struct terminate_message) + 2 + 18 + 28)
667 enum c4iw_layers_types {
671 RDMAP_LOCAL_CATA = 0x00,
672 RDMAP_REMOTE_PROT = 0x01,
673 RDMAP_REMOTE_OP = 0x02,
674 DDP_LOCAL_CATA = 0x00,
675 DDP_TAGGED_ERR = 0x01,
676 DDP_UNTAGGED_ERR = 0x02,
680 enum c4iw_rdma_ecodes {
681 RDMAP_INV_STAG = 0x00,
682 RDMAP_BASE_BOUNDS = 0x01,
683 RDMAP_ACC_VIOL = 0x02,
684 RDMAP_STAG_NOT_ASSOC = 0x03,
685 RDMAP_TO_WRAP = 0x04,
686 RDMAP_INV_VERS = 0x05,
687 RDMAP_INV_OPCODE = 0x06,
688 RDMAP_STREAM_CATA = 0x07,
689 RDMAP_GLOBAL_CATA = 0x08,
690 RDMAP_CANT_INV_STAG = 0x09,
691 RDMAP_UNSPECIFIED = 0xff
694 enum c4iw_ddp_ecodes {
695 DDPT_INV_STAG = 0x00,
696 DDPT_BASE_BOUNDS = 0x01,
697 DDPT_STAG_NOT_ASSOC = 0x02,
699 DDPT_INV_VERS = 0x04,
701 DDPU_INV_MSN_NOBUF = 0x02,
702 DDPU_INV_MSN_RANGE = 0x03,
704 DDPU_MSG_TOOBIG = 0x05,
708 enum c4iw_mpa_ecodes {
710 MPA_MARKER_ERR = 0x03,
711 MPA_LOCAL_CATA = 0x05,
712 MPA_INSUFF_IRD = 0x06,
713 MPA_NOMATCH_RTR = 0x07,
732 PEER_ABORT_IN_PROGRESS = 0,
733 ABORT_REQ_IN_PROGRESS = 1,
734 RELEASE_RESOURCES = 2,
740 enum c4iw_ep_history {
760 CONN_RPL_UPCALL = 19,
761 ACT_RETRY_NOMEM = 20,
762 ACT_RETRY_INUSE = 21,
771 struct c4iw_ep_common {
772 TAILQ_ENTRY(c4iw_ep_common) entry; /* Work queue attachment */
773 struct iw_cm_id *cm_id;
775 struct c4iw_dev *dev;
776 enum c4iw_ep_state state;
779 struct sockaddr_in local_addr;
780 struct sockaddr_in remote_addr;
781 struct c4iw_wr_wait wr_wait;
783 unsigned long history;
786 struct thread *thread;
791 struct c4iw_listen_ep {
792 struct c4iw_ep_common com;
798 struct c4iw_ep_common com;
799 struct c4iw_ep *parent_ep;
800 struct timer_list timer;
805 struct l2t_entry *l2t;
806 struct dst_entry *dst;
807 struct c4iw_mpa_attributes mpa_attr;
808 u8 mpa_pkt[sizeof(struct mpa_message) + MPA_MAX_PRIVATE_DATA];
809 unsigned int mpa_pkt_len;
822 u8 retry_with_mpa_v1;
823 u8 tried_with_mpa_v1;
826 static inline struct c4iw_ep *to_ep(struct iw_cm_id *cm_id)
828 return cm_id->provider_data;
831 static inline struct c4iw_listen_ep *to_listen_ep(struct iw_cm_id *cm_id)
833 return cm_id->provider_data;
836 static inline int compute_wscale(int win)
840 while (wscale < 14 && (65535<<wscale) < win)
845 u32 c4iw_id_alloc(struct c4iw_id_table *alloc);
846 void c4iw_id_free(struct c4iw_id_table *alloc, u32 obj);
847 int c4iw_id_table_alloc(struct c4iw_id_table *alloc, u32 start, u32 num,
848 u32 reserved, u32 flags);
849 void c4iw_id_table_free(struct c4iw_id_table *alloc);
851 typedef int (*c4iw_handler_func)(struct c4iw_dev *dev, struct mbuf *m);
853 int c4iw_ep_redirect(void *ctx, struct dst_entry *old, struct dst_entry *new,
854 struct l2t_entry *l2t);
855 u32 c4iw_get_resource(struct c4iw_id_table *id_table);
856 void c4iw_put_resource(struct c4iw_id_table *id_table, u32 entry);
857 int c4iw_init_resource(struct c4iw_rdev *rdev, u32 nr_tpt, u32 nr_pdid);
858 int c4iw_init_ctrl_qp(struct c4iw_rdev *rdev);
859 int c4iw_pblpool_create(struct c4iw_rdev *rdev);
860 int c4iw_rqtpool_create(struct c4iw_rdev *rdev);
861 void c4iw_pblpool_destroy(struct c4iw_rdev *rdev);
862 void c4iw_rqtpool_destroy(struct c4iw_rdev *rdev);
863 void c4iw_destroy_resource(struct c4iw_resource *rscp);
864 int c4iw_destroy_ctrl_qp(struct c4iw_rdev *rdev);
865 int c4iw_register_device(struct c4iw_dev *dev);
866 void c4iw_unregister_device(struct c4iw_dev *dev);
867 int __init c4iw_cm_init(void);
868 void __exit c4iw_cm_term(void);
869 void c4iw_release_dev_ucontext(struct c4iw_rdev *rdev,
870 struct c4iw_dev_ucontext *uctx);
871 void c4iw_init_dev_ucontext(struct c4iw_rdev *rdev,
872 struct c4iw_dev_ucontext *uctx);
873 int c4iw_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
874 int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
875 struct ib_send_wr **bad_wr);
876 int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
877 struct ib_recv_wr **bad_wr);
878 int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw,
879 struct ib_mw_bind *mw_bind);
880 int c4iw_connect(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
881 int c4iw_create_listen_ep(struct iw_cm_id *cm_id, int backlog);
882 void c4iw_destroy_listen_ep(struct iw_cm_id *cm_id);
883 int c4iw_accept_cr(struct iw_cm_id *cm_id, struct iw_cm_conn_param *conn_param);
884 int c4iw_reject_cr(struct iw_cm_id *cm_id, const void *pdata, u8 pdata_len);
885 void c4iw_qp_add_ref(struct ib_qp *qp);
886 void c4iw_qp_rem_ref(struct ib_qp *qp);
887 void c4iw_free_fastreg_pbl(struct ib_fast_reg_page_list *page_list);
888 struct ib_fast_reg_page_list *c4iw_alloc_fastreg_pbl(
889 struct ib_device *device,
891 struct ib_mr *c4iw_alloc_fast_reg_mr(struct ib_pd *pd, int pbl_depth);
892 int c4iw_dealloc_mw(struct ib_mw *mw);
893 struct ib_mw *c4iw_alloc_mw(struct ib_pd *pd);
894 struct ib_mr *c4iw_reg_user_mr(struct ib_pd *pd, u64 start, u64 length, u64
895 virt, int acc, struct ib_udata *udata, int mr_id);
896 struct ib_mr *c4iw_get_dma_mr(struct ib_pd *pd, int acc);
897 struct ib_mr *c4iw_register_phys_mem(struct ib_pd *pd,
898 struct ib_phys_buf *buffer_list,
902 int c4iw_reregister_phys_mem(struct ib_mr *mr,
905 struct ib_phys_buf *buffer_list,
907 int acc, u64 *iova_start);
908 int c4iw_dereg_mr(struct ib_mr *ib_mr);
909 int c4iw_destroy_cq(struct ib_cq *ib_cq);
910 struct ib_cq *c4iw_create_cq(struct ib_device *ibdev, int entries,
912 struct ib_ucontext *ib_context,
913 struct ib_udata *udata);
914 int c4iw_resize_cq(struct ib_cq *cq, int cqe, struct ib_udata *udata);
915 int c4iw_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
916 int c4iw_destroy_qp(struct ib_qp *ib_qp);
917 struct ib_qp *c4iw_create_qp(struct ib_pd *pd,
918 struct ib_qp_init_attr *attrs,
919 struct ib_udata *udata);
920 int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
921 int attr_mask, struct ib_udata *udata);
922 int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
923 int attr_mask, struct ib_qp_init_attr *init_attr);
924 struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn);
925 u32 c4iw_rqtpool_alloc(struct c4iw_rdev *rdev, int size);
926 void c4iw_rqtpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
927 u32 c4iw_pblpool_alloc(struct c4iw_rdev *rdev, int size);
928 void c4iw_pblpool_free(struct c4iw_rdev *rdev, u32 addr, int size);
929 int c4iw_ofld_send(struct c4iw_rdev *rdev, struct mbuf *m);
930 void c4iw_flush_hw_cq(struct t4_cq *cq);
931 void c4iw_count_rcqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
932 void c4iw_count_scqes(struct t4_cq *cq, struct t4_wq *wq, int *count);
933 int c4iw_ep_disconnect(struct c4iw_ep *ep, int abrupt, gfp_t gfp);
934 int c4iw_flush_rq(struct t4_wq *wq, struct t4_cq *cq, int count);
935 int c4iw_flush_sq(struct t4_wq *wq, struct t4_cq *cq, int count);
936 int c4iw_ev_handler(struct sge_iq *, const struct rsp_ctrl *);
937 u16 c4iw_rqes_posted(struct c4iw_qp *qhp);
938 int c4iw_post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe);
939 u32 c4iw_get_cqid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
940 void c4iw_put_cqid(struct c4iw_rdev *rdev, u32 qid,
941 struct c4iw_dev_ucontext *uctx);
942 u32 c4iw_get_qpid(struct c4iw_rdev *rdev, struct c4iw_dev_ucontext *uctx);
943 void c4iw_put_qpid(struct c4iw_rdev *rdev, u32 qid,
944 struct c4iw_dev_ucontext *uctx);
945 void c4iw_ev_dispatch(struct c4iw_dev *dev, struct t4_cqe *err_cqe);
946 void process_newconn(struct iw_cm_id *parent_cm_id,
947 struct socket *child_so);
949 extern struct cxgb4_client t4c_client;
950 extern c4iw_handler_func c4iw_handlers[NUM_CPL_CMDS];
951 extern int c4iw_max_read_depth;
953 #if defined(__i386__) || defined(__amd64__)
954 #define L1_CACHE_BYTES 128
956 #define L1_CACHE_BYTES 32
960 int idr_for_each(struct idr *idp,
961 int (*fn)(int id, void *p, void *data), void *data)
963 int n, id, max, error = 0;
965 struct idr_layer *pa[MAX_LEVEL];
966 struct idr_layer **paa = &pa[0];
968 n = idp->layers * IDR_BITS;
977 p = p->ary[(id >> n) & IDR_MASK];
981 error = fn(id, (void *)p, data);
987 while (n < fls(id)) {
996 void your_reg_device(struct c4iw_dev *dev);
998 #define SGE_CTRLQ_NUM 0