2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include "opt_inet6.h"
35 #include <sys/param.h>
38 #include <sys/kernel.h>
40 #include <sys/systm.h>
41 #include <sys/counter.h>
42 #include <sys/module.h>
43 #include <sys/malloc.h>
44 #include <sys/queue.h>
45 #include <sys/taskqueue.h>
46 #include <sys/pciio.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pci_private.h>
50 #include <sys/firmware.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
55 #include <sys/sysctl.h>
56 #include <net/ethernet.h>
58 #include <net/if_types.h>
59 #include <net/if_dl.h>
60 #include <net/if_vlan_var.h>
62 #include <net/rss_config.h>
64 #if defined(__i386__) || defined(__amd64__)
70 #include <ddb/db_lex.h>
73 #include "common/common.h"
74 #include "common/t4_msg.h"
75 #include "common/t4_regs.h"
76 #include "common/t4_regs_values.h"
79 #include "t4_mp_ring.h"
81 /* T4 bus driver interface */
82 static int t4_probe(device_t);
83 static int t4_attach(device_t);
84 static int t4_detach(device_t);
85 static device_method_t t4_methods[] = {
86 DEVMETHOD(device_probe, t4_probe),
87 DEVMETHOD(device_attach, t4_attach),
88 DEVMETHOD(device_detach, t4_detach),
92 static driver_t t4_driver = {
95 sizeof(struct adapter)
99 /* T4 port (cxgbe) interface */
100 static int cxgbe_probe(device_t);
101 static int cxgbe_attach(device_t);
102 static int cxgbe_detach(device_t);
103 device_method_t cxgbe_methods[] = {
104 DEVMETHOD(device_probe, cxgbe_probe),
105 DEVMETHOD(device_attach, cxgbe_attach),
106 DEVMETHOD(device_detach, cxgbe_detach),
109 static driver_t cxgbe_driver = {
112 sizeof(struct port_info)
115 /* T4 VI (vcxgbe) interface */
116 static int vcxgbe_probe(device_t);
117 static int vcxgbe_attach(device_t);
118 static int vcxgbe_detach(device_t);
119 static device_method_t vcxgbe_methods[] = {
120 DEVMETHOD(device_probe, vcxgbe_probe),
121 DEVMETHOD(device_attach, vcxgbe_attach),
122 DEVMETHOD(device_detach, vcxgbe_detach),
125 static driver_t vcxgbe_driver = {
128 sizeof(struct vi_info)
131 static d_ioctl_t t4_ioctl;
133 static struct cdevsw t4_cdevsw = {
134 .d_version = D_VERSION,
139 /* T5 bus driver interface */
140 static int t5_probe(device_t);
141 static device_method_t t5_methods[] = {
142 DEVMETHOD(device_probe, t5_probe),
143 DEVMETHOD(device_attach, t4_attach),
144 DEVMETHOD(device_detach, t4_detach),
148 static driver_t t5_driver = {
151 sizeof(struct adapter)
155 /* T5 port (cxl) interface */
156 static driver_t cxl_driver = {
159 sizeof(struct port_info)
162 /* T5 VI (vcxl) interface */
163 static driver_t vcxl_driver = {
166 sizeof(struct vi_info)
169 /* T6 bus driver interface */
170 static int t6_probe(device_t);
171 static device_method_t t6_methods[] = {
172 DEVMETHOD(device_probe, t6_probe),
173 DEVMETHOD(device_attach, t4_attach),
174 DEVMETHOD(device_detach, t4_detach),
178 static driver_t t6_driver = {
181 sizeof(struct adapter)
185 /* T6 port (cc) interface */
186 static driver_t cc_driver = {
189 sizeof(struct port_info)
192 /* T6 VI (vcc) interface */
193 static driver_t vcc_driver = {
196 sizeof(struct vi_info)
199 /* ifnet + media interface */
200 static void cxgbe_init(void *);
201 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
202 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
203 static void cxgbe_qflush(struct ifnet *);
204 static int cxgbe_media_change(struct ifnet *);
205 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
207 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
210 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
211 * then ADAPTER_LOCK, then t4_uld_list_lock.
213 static struct sx t4_list_lock;
214 SLIST_HEAD(, adapter) t4_list;
216 static struct sx t4_uld_list_lock;
217 SLIST_HEAD(, uld_info) t4_uld_list;
221 * Tunables. See tweak_tunables() too.
223 * Each tunable is set to a default value here if it's known at compile-time.
224 * Otherwise it is set to -n as an indication to tweak_tunables() that it should
225 * provide a reasonable default (upto n) when the driver is loaded.
227 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
228 * T5 are under hw.cxl.
232 * Number of queues for tx and rx, 10G and 1G, NIC and offload.
235 int t4_ntxq10g = -NTXQ_10G;
236 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g);
239 int t4_nrxq10g = -NRXQ_10G;
240 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g);
243 int t4_ntxq1g = -NTXQ_1G;
244 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g);
247 int t4_nrxq1g = -NRXQ_1G;
248 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g);
251 static int t4_ntxq_vi = -NTXQ_VI;
252 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi);
255 static int t4_nrxq_vi = -NRXQ_VI;
256 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi);
258 static int t4_rsrv_noflowq = 0;
259 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq);
262 #define NOFLDTXQ_10G 8
263 static int t4_nofldtxq10g = -NOFLDTXQ_10G;
264 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g);
266 #define NOFLDRXQ_10G 2
267 static int t4_nofldrxq10g = -NOFLDRXQ_10G;
268 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g);
270 #define NOFLDTXQ_1G 2
271 static int t4_nofldtxq1g = -NOFLDTXQ_1G;
272 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g);
274 #define NOFLDRXQ_1G 1
275 static int t4_nofldrxq1g = -NOFLDRXQ_1G;
276 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g);
278 #define NOFLDTXQ_VI 1
279 static int t4_nofldtxq_vi = -NOFLDTXQ_VI;
280 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi);
282 #define NOFLDRXQ_VI 1
283 static int t4_nofldrxq_vi = -NOFLDRXQ_VI;
284 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi);
289 static int t4_nnmtxq_vi = -NNMTXQ_VI;
290 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi);
293 static int t4_nnmrxq_vi = -NNMRXQ_VI;
294 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi);
298 * Holdoff parameters for 10G and 1G ports.
300 #define TMR_IDX_10G 1
301 int t4_tmr_idx_10g = TMR_IDX_10G;
302 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g);
304 #define PKTC_IDX_10G (-1)
305 int t4_pktc_idx_10g = PKTC_IDX_10G;
306 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g);
309 int t4_tmr_idx_1g = TMR_IDX_1G;
310 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g);
312 #define PKTC_IDX_1G (-1)
313 int t4_pktc_idx_1g = PKTC_IDX_1G;
314 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g);
317 * Size (# of entries) of each tx and rx queue.
319 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
320 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
322 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
323 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
326 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
328 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
329 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
332 * Configuration file.
334 #define DEFAULT_CF "default"
335 #define FLASH_CF "flash"
336 #define UWIRE_CF "uwire"
337 #define FPGA_CF "fpga"
338 static char t4_cfg_file[32] = DEFAULT_CF;
339 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
342 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively).
343 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
344 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
345 * mark or when signalled to do so, 0 to never emit PAUSE.
347 static int t4_pause_settings = PAUSE_TX | PAUSE_RX;
348 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings);
351 * Forward Error Correction settings (bit 0, 1, 2 = FEC_RS, FEC_BASER_RS,
352 * FEC_RESERVED respectively).
353 * -1 to run with the firmware default.
356 static int t4_fec = -1;
357 TUNABLE_INT("hw.cxgbe.fec", &t4_fec);
360 * Link autonegotiation.
361 * -1 to run with the firmware default.
365 static int t4_autoneg = -1;
366 TUNABLE_INT("hw.cxgbe.autoneg", &t4_autoneg);
369 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
370 * encouraged respectively).
372 static unsigned int t4_fw_install = 1;
373 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install);
376 * ASIC features that will be used. Disable the ones you don't want so that the
377 * chip resources aren't wasted on features that will not be used.
379 static int t4_nbmcaps_allowed = 0;
380 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed);
382 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
383 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
385 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
386 FW_CAPS_CONFIG_SWITCH_EGRESS;
387 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed);
389 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
390 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
392 static int t4_toecaps_allowed = -1;
393 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
395 static int t4_rdmacaps_allowed = -1;
396 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
398 static int t4_cryptocaps_allowed = 0;
399 TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed);
401 static int t4_iscsicaps_allowed = -1;
402 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
404 static int t4_fcoecaps_allowed = 0;
405 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
407 static int t5_write_combine = 0;
408 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
410 static int t4_num_vis = 1;
411 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis);
413 /* Functions used by extra VIs to obtain unique MAC addresses for each VI. */
414 static int vi_mac_funcs[] = {
417 FW_VI_FUNC_OPENISCSI,
423 struct intrs_and_queues {
424 uint16_t intr_type; /* INTx, MSI, or MSI-X */
425 uint16_t nirq; /* Total # of vectors */
426 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */
427 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */
428 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */
429 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */
430 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */
431 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */
432 uint16_t rsrv_noflowq; /* Flag whether to reserve queue 0 */
433 uint16_t nofldtxq10g; /* # of TOE txq's for each 10G port */
434 uint16_t nofldrxq10g; /* # of TOE rxq's for each 10G port */
435 uint16_t nofldtxq1g; /* # of TOE txq's for each 1G port */
436 uint16_t nofldrxq1g; /* # of TOE rxq's for each 1G port */
438 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
439 uint16_t ntxq_vi; /* # of NIC txq's */
440 uint16_t nrxq_vi; /* # of NIC rxq's */
441 uint16_t nofldtxq_vi; /* # of TOE txq's */
442 uint16_t nofldrxq_vi; /* # of TOE rxq's */
443 uint16_t nnmtxq_vi; /* # of netmap txq's */
444 uint16_t nnmrxq_vi; /* # of netmap rxq's */
447 struct filter_entry {
448 uint32_t valid:1; /* filter allocated and valid */
449 uint32_t locked:1; /* filter is administratively locked */
450 uint32_t pending:1; /* filter action is pending firmware reply */
451 uint32_t smtidx:8; /* Source MAC Table index for smac */
452 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
454 struct t4_filter_specification fs;
457 static void setup_memwin(struct adapter *);
458 static void position_memwin(struct adapter *, int, uint32_t);
459 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
460 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *,
462 static inline int write_via_memwin(struct adapter *, int, uint32_t,
463 const uint32_t *, int);
464 static int validate_mem_range(struct adapter *, uint32_t, int);
465 static int fwmtype_to_hwmtype(int);
466 static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
468 static int fixup_devlog_params(struct adapter *);
469 static int cfg_itype_and_nqueues(struct adapter *, int, int, int,
470 struct intrs_and_queues *);
471 static int prep_firmware(struct adapter *);
472 static int partition_resources(struct adapter *, const struct firmware *,
474 static int get_params__pre_init(struct adapter *);
475 static int get_params__post_init(struct adapter *);
476 static int set_params__post_init(struct adapter *);
477 static void t4_set_desc(struct adapter *);
478 static void build_medialist(struct port_info *, struct ifmedia *);
479 static void init_l1cfg(struct port_info *);
480 static int apply_l1cfg(struct port_info *);
481 static int cxgbe_init_synchronized(struct vi_info *);
482 static int cxgbe_uninit_synchronized(struct vi_info *);
483 static void quiesce_txq(struct adapter *, struct sge_txq *);
484 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
485 static void quiesce_iq(struct adapter *, struct sge_iq *);
486 static void quiesce_fl(struct adapter *, struct sge_fl *);
487 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
488 driver_intr_t *, void *, char *);
489 static int t4_free_irq(struct adapter *, struct irq *);
490 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
491 static void vi_refresh_stats(struct adapter *, struct vi_info *);
492 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
493 static void cxgbe_tick(void *);
494 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
495 static void cxgbe_sysctls(struct port_info *);
496 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
497 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
498 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
499 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
500 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
501 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
502 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
503 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
504 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
505 static int sysctl_fec(SYSCTL_HANDLER_ARGS);
506 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
507 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
508 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
510 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
511 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
512 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
513 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
514 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
515 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
516 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
517 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
518 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
519 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
520 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
521 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
522 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
523 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
524 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
525 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
526 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
527 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
528 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
529 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
530 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
531 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
532 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
533 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
534 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
535 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
536 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
537 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
538 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
541 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
542 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
543 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
545 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t);
546 static uint32_t mode_to_fconf(uint32_t);
547 static uint32_t mode_to_iconf(uint32_t);
548 static int check_fspec_against_fconf_iconf(struct adapter *,
549 struct t4_filter_specification *);
550 static int get_filter_mode(struct adapter *, uint32_t *);
551 static int set_filter_mode(struct adapter *, uint32_t);
552 static inline uint64_t get_filter_hits(struct adapter *, uint32_t);
553 static int get_filter(struct adapter *, struct t4_filter *);
554 static int set_filter(struct adapter *, struct t4_filter *);
555 static int del_filter(struct adapter *, struct t4_filter *);
556 static void clear_filter(struct filter_entry *);
557 static int set_filter_wr(struct adapter *, int);
558 static int del_filter_wr(struct adapter *, int);
559 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *,
561 static int get_sge_context(struct adapter *, struct t4_sge_context *);
562 static int load_fw(struct adapter *, struct t4_data *);
563 static int load_cfg(struct adapter *, struct t4_data *);
564 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
565 static int read_i2c(struct adapter *, struct t4_i2c_data *);
567 static int toe_capability(struct vi_info *, int);
569 static int mod_event(module_t, int, void *);
575 {0xa000, "Chelsio Terminator 4 FPGA"},
576 {0x4400, "Chelsio T440-dbg"},
577 {0x4401, "Chelsio T420-CR"},
578 {0x4402, "Chelsio T422-CR"},
579 {0x4403, "Chelsio T440-CR"},
580 {0x4404, "Chelsio T420-BCH"},
581 {0x4405, "Chelsio T440-BCH"},
582 {0x4406, "Chelsio T440-CH"},
583 {0x4407, "Chelsio T420-SO"},
584 {0x4408, "Chelsio T420-CX"},
585 {0x4409, "Chelsio T420-BT"},
586 {0x440a, "Chelsio T404-BT"},
587 {0x440e, "Chelsio T440-LP-CR"},
589 {0xb000, "Chelsio Terminator 5 FPGA"},
590 {0x5400, "Chelsio T580-dbg"},
591 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
592 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
593 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
594 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
595 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
596 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
597 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
598 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
599 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
600 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
601 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
602 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
603 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
604 {0x5418, "Chelsio T540-BT"}, /* 4 x 10GBaseT */
605 {0x5419, "Chelsio T540-LP-BT"}, /* 4 x 10GBaseT */
606 {0x541a, "Chelsio T540-SO-BT"}, /* 4 x 10GBaseT, nomem */
607 {0x541b, "Chelsio T540-SO-CR"}, /* 4 x 10G, nomem */
610 {0x5483, "Custom T540-CR"},
611 {0x5484, "Custom T540-BT"},
613 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
614 {0x6400, "Chelsio T6-DBG-25"}, /* 2 x 10/25G, debug */
615 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
616 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
617 {0x6403, "Chelsio T6425-CR"}, /* 4 x 10/25G */
618 {0x6404, "Chelsio T6425-SO-CR"}, /* 4 x 10/25G, nomem */
619 {0x6405, "Chelsio T6225-OCP-SO"}, /* 2 x 10/25G, nomem */
620 {0x6406, "Chelsio T62100-OCP-SO"}, /* 2 x 40/50/100G, nomem */
621 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
622 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
623 {0x6409, "Chelsio T6210-BT"}, /* 2 x 10GBASE-T */
624 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
625 {0x6410, "Chelsio T6-DBG-100"}, /* 2 x 40/50/100G, debug */
626 {0x6411, "Chelsio T6225-LL-CR"}, /* 2 x 10/25G */
627 {0x6414, "Chelsio T61100-OCP-SO"}, /* 1 x 40/50/100G, nomem */
628 {0x6415, "Chelsio T6201-BT"}, /* 2 x 1000BASE-T */
631 {0x6480, "Custom T6225-CR"},
632 {0x6481, "Custom T62100-CR"},
633 {0x6482, "Custom T6225-CR"},
634 {0x6483, "Custom T62100-CR"},
635 {0x6484, "Custom T64100-CR"},
636 {0x6485, "Custom T6240-SO"},
637 {0x6486, "Custom T6225-SO-CR"},
638 {0x6487, "Custom T6225-CR"},
643 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be
644 * exactly the same for both rxq and ofld_rxq.
646 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
647 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
649 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
652 t4_probe(device_t dev)
655 uint16_t v = pci_get_vendor(dev);
656 uint16_t d = pci_get_device(dev);
657 uint8_t f = pci_get_function(dev);
659 if (v != PCI_VENDOR_ID_CHELSIO)
662 /* Attach only to PF0 of the FPGA */
663 if (d == 0xa000 && f != 0)
666 for (i = 0; i < nitems(t4_pciids); i++) {
667 if (d == t4_pciids[i].device) {
668 device_set_desc(dev, t4_pciids[i].desc);
669 return (BUS_PROBE_DEFAULT);
677 t5_probe(device_t dev)
680 uint16_t v = pci_get_vendor(dev);
681 uint16_t d = pci_get_device(dev);
682 uint8_t f = pci_get_function(dev);
684 if (v != PCI_VENDOR_ID_CHELSIO)
687 /* Attach only to PF0 of the FPGA */
688 if (d == 0xb000 && f != 0)
691 for (i = 0; i < nitems(t5_pciids); i++) {
692 if (d == t5_pciids[i].device) {
693 device_set_desc(dev, t5_pciids[i].desc);
694 return (BUS_PROBE_DEFAULT);
702 t6_probe(device_t dev)
705 uint16_t v = pci_get_vendor(dev);
706 uint16_t d = pci_get_device(dev);
708 if (v != PCI_VENDOR_ID_CHELSIO)
711 for (i = 0; i < nitems(t6_pciids); i++) {
712 if (d == t6_pciids[i].device) {
713 device_set_desc(dev, t6_pciids[i].desc);
714 return (BUS_PROBE_DEFAULT);
722 t5_attribute_workaround(device_t dev)
728 * The T5 chips do not properly echo the No Snoop and Relaxed
729 * Ordering attributes when replying to a TLP from a Root
730 * Port. As a workaround, find the parent Root Port and
731 * disable No Snoop and Relaxed Ordering. Note that this
732 * affects all devices under this root port.
734 root_port = pci_find_pcie_root_port(dev);
735 if (root_port == NULL) {
736 device_printf(dev, "Unable to find parent root port\n");
740 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
741 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
742 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
744 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
745 device_get_nameunit(root_port));
748 static const struct devnames devnames[] = {
750 .nexus_name = "t4nex",
751 .ifnet_name = "cxgbe",
752 .vi_ifnet_name = "vcxgbe",
753 .pf03_drv_name = "t4iov",
754 .vf_nexus_name = "t4vf",
755 .vf_ifnet_name = "cxgbev"
757 .nexus_name = "t5nex",
759 .vi_ifnet_name = "vcxl",
760 .pf03_drv_name = "t5iov",
761 .vf_nexus_name = "t5vf",
762 .vf_ifnet_name = "cxlv"
764 .nexus_name = "t6nex",
766 .vi_ifnet_name = "vcc",
767 .pf03_drv_name = "t6iov",
768 .vf_nexus_name = "t6vf",
769 .vf_ifnet_name = "ccv"
774 t4_init_devnames(struct adapter *sc)
779 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
780 sc->names = &devnames[id - CHELSIO_T4];
782 device_printf(sc->dev, "chip id %d is not supported.\n", id);
788 t4_attach(device_t dev)
791 int rc = 0, i, j, n10g, n1g, rqidx, tqidx;
792 struct make_dev_args mda;
793 struct intrs_and_queues iaq;
797 int ofld_rqidx, ofld_tqidx;
800 int nm_rqidx, nm_tqidx;
804 sc = device_get_softc(dev);
806 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
808 if ((pci_get_device(dev) & 0xff00) == 0x5400)
809 t5_attribute_workaround(dev);
810 pci_enable_busmaster(dev);
811 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
814 pci_set_max_read_req(dev, 4096);
815 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
816 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
817 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
819 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
822 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
823 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
825 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
826 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
827 device_get_nameunit(dev));
829 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
830 device_get_nameunit(dev));
831 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
834 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
835 TAILQ_INIT(&sc->sfl);
836 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
838 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
840 rc = t4_map_bars_0_and_4(sc);
842 goto done; /* error message displayed already */
844 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
846 /* Prepare the adapter for operation. */
847 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
848 rc = -t4_prep_adapter(sc, buf);
851 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
856 * This is the real PF# to which we're attaching. Works from within PCI
857 * passthrough environments too, where pci_get_function() could return a
858 * different PF# depending on the passthrough configuration. We need to
859 * use the real PF# in all our communication with the firmware.
861 j = t4_read_reg(sc, A_PL_WHOAMI);
862 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
865 t4_init_devnames(sc);
866 if (sc->names == NULL) {
868 goto done; /* error message displayed already */
872 * Do this really early, with the memory windows set up even before the
873 * character device. The userland tool's register i/o and mem read
874 * will work even in "recovery mode".
877 if (t4_init_devlog_params(sc, 0) == 0)
878 fixup_devlog_params(sc);
879 make_dev_args_init(&mda);
880 mda.mda_devsw = &t4_cdevsw;
881 mda.mda_uid = UID_ROOT;
882 mda.mda_gid = GID_WHEEL;
884 mda.mda_si_drv1 = sc;
885 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
887 device_printf(dev, "failed to create nexus char device: %d.\n",
890 /* Go no further if recovery mode has been requested. */
891 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
892 device_printf(dev, "recovery mode.\n");
896 #if defined(__i386__)
897 if ((cpu_feature & CPUID_CX8) == 0) {
898 device_printf(dev, "64 bit atomics not available.\n");
904 /* Prepare the firmware for operation */
905 rc = prep_firmware(sc);
907 goto done; /* error message displayed already */
909 rc = get_params__post_init(sc);
911 goto done; /* error message displayed already */
913 rc = set_params__post_init(sc);
915 goto done; /* error message displayed already */
917 rc = t4_map_bar_2(sc);
919 goto done; /* error message displayed already */
921 rc = t4_create_dma_tag(sc);
923 goto done; /* error message displayed already */
926 * Number of VIs to create per-port. The first VI is the "main" regular
927 * VI for the port. The rest are additional virtual interfaces on the
928 * same physical port. Note that the main VI does not have native
929 * netmap support but the extra VIs do.
931 * Limit the number of VIs per port to the number of available
932 * MAC addresses per port.
935 num_vis = t4_num_vis;
938 if (num_vis > nitems(vi_mac_funcs)) {
939 num_vis = nitems(vi_mac_funcs);
940 device_printf(dev, "Number of VIs limited to %d\n", num_vis);
944 * First pass over all the ports - allocate VIs and initialize some
945 * basic parameters like mac address, port type, etc. We also figure
946 * out whether a port is 10G or 1G and use that information when
947 * calculating how many interrupts to attempt to allocate.
950 for_each_port(sc, i) {
951 struct port_info *pi;
953 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
956 /* These must be set before t4_port_init */
960 * XXX: vi[0] is special so we can't delay this allocation until
961 * pi->nvi's final value is known.
963 pi->vi = malloc(sizeof(struct vi_info) * num_vis, M_CXGBE,
967 * Allocate the "main" VI and initialize parameters
970 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
972 device_printf(dev, "unable to initialize port %d: %d\n",
974 free(pi->vi, M_CXGBE);
980 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
981 device_get_nameunit(dev), i);
982 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
983 sc->chan_map[pi->tx_chan] = i;
985 if (port_top_speed(pi) >= 10) {
991 /* All VIs on this port share this media. */
992 ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
995 pi->dev = device_add_child(dev, sc->names->ifnet_name, -1);
996 if (pi->dev == NULL) {
998 "failed to add device for port %d.\n", i);
1002 pi->vi[0].dev = pi->dev;
1003 device_set_softc(pi->dev, pi);
1007 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1009 rc = cfg_itype_and_nqueues(sc, n10g, n1g, num_vis, &iaq);
1011 goto done; /* error message displayed already */
1012 if (iaq.nrxq_vi + iaq.nofldrxq_vi + iaq.nnmrxq_vi == 0)
1015 sc->intr_type = iaq.intr_type;
1016 sc->intr_count = iaq.nirq;
1019 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
1020 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
1022 s->nrxq += (n10g + n1g) * (num_vis - 1) * iaq.nrxq_vi;
1023 s->ntxq += (n10g + n1g) * (num_vis - 1) * iaq.ntxq_vi;
1025 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
1026 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
1027 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
1029 if (is_offload(sc)) {
1030 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g;
1031 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g;
1033 s->nofldrxq += (n10g + n1g) * (num_vis - 1) *
1035 s->nofldtxq += (n10g + n1g) * (num_vis - 1) *
1038 s->neq += s->nofldtxq + s->nofldrxq;
1039 s->niq += s->nofldrxq;
1041 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1042 M_CXGBE, M_ZERO | M_WAITOK);
1043 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
1044 M_CXGBE, M_ZERO | M_WAITOK);
1049 s->nnmrxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmrxq_vi;
1050 s->nnmtxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmtxq_vi;
1052 s->neq += s->nnmtxq + s->nnmrxq;
1053 s->niq += s->nnmrxq;
1055 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1056 M_CXGBE, M_ZERO | M_WAITOK);
1057 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1058 M_CXGBE, M_ZERO | M_WAITOK);
1061 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE,
1063 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1065 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1067 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
1069 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
1072 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1075 t4_init_l2t(sc, M_WAITOK);
1076 t4_init_tx_sched(sc);
1079 * Second pass over the ports. This time we know the number of rx and
1080 * tx queues that each port should get.
1084 ofld_rqidx = ofld_tqidx = 0;
1087 nm_rqidx = nm_tqidx = 0;
1089 for_each_port(sc, i) {
1090 struct port_info *pi = sc->port[i];
1097 for_each_vi(pi, j, vi) {
1099 vi->qsize_rxq = t4_qsize_rxq;
1100 vi->qsize_txq = t4_qsize_txq;
1102 vi->first_rxq = rqidx;
1103 vi->first_txq = tqidx;
1104 if (port_top_speed(pi) >= 10) {
1105 vi->tmr_idx = t4_tmr_idx_10g;
1106 vi->pktc_idx = t4_pktc_idx_10g;
1107 vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
1108 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi;
1109 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi;
1111 vi->tmr_idx = t4_tmr_idx_1g;
1112 vi->pktc_idx = t4_pktc_idx_1g;
1113 vi->flags |= iaq.intr_flags_1g & INTR_RXQ;
1114 vi->nrxq = j == 0 ? iaq.nrxq1g : iaq.nrxq_vi;
1115 vi->ntxq = j == 0 ? iaq.ntxq1g : iaq.ntxq_vi;
1120 if (j == 0 && vi->ntxq > 1)
1121 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0;
1123 vi->rsrv_noflowq = 0;
1126 vi->first_ofld_rxq = ofld_rqidx;
1127 vi->first_ofld_txq = ofld_tqidx;
1128 if (port_top_speed(pi) >= 10) {
1129 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ;
1130 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g :
1132 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g :
1135 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ;
1136 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g :
1138 vi->nofldtxq = j == 0 ? iaq.nofldtxq1g :
1141 ofld_rqidx += vi->nofldrxq;
1142 ofld_tqidx += vi->nofldtxq;
1146 vi->first_nm_rxq = nm_rqidx;
1147 vi->first_nm_txq = nm_tqidx;
1148 vi->nnmrxq = iaq.nnmrxq_vi;
1149 vi->nnmtxq = iaq.nnmtxq_vi;
1150 nm_rqidx += vi->nnmrxq;
1151 nm_tqidx += vi->nnmtxq;
1157 rc = t4_setup_intr_handlers(sc);
1160 "failed to setup interrupt handlers: %d\n", rc);
1164 rc = bus_generic_probe(dev);
1166 device_printf(dev, "failed to probe child drivers: %d\n", rc);
1170 rc = bus_generic_attach(dev);
1173 "failed to attach all child ports: %d\n", rc);
1178 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1179 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1180 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1181 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1182 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1187 if (rc != 0 && sc->cdev) {
1188 /* cdev was created and so cxgbetool works; recover that way. */
1190 "error during attach, adapter is now in recovery mode.\n");
1195 t4_detach_common(dev);
1206 t4_detach(device_t dev)
1210 sc = device_get_softc(dev);
1212 return (t4_detach_common(dev));
1216 t4_detach_common(device_t dev)
1219 struct port_info *pi;
1222 sc = device_get_softc(dev);
1224 if (sc->flags & FULL_INIT_DONE) {
1225 if (!(sc->flags & IS_VF))
1226 t4_intr_disable(sc);
1230 destroy_dev(sc->cdev);
1234 if (device_is_attached(dev)) {
1235 rc = bus_generic_detach(dev);
1238 "failed to detach child devices: %d\n", rc);
1243 for (i = 0; i < sc->intr_count; i++)
1244 t4_free_irq(sc, &sc->irq[i]);
1246 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1247 t4_free_tx_sched(sc);
1249 for (i = 0; i < MAX_NPORTS; i++) {
1252 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1254 device_delete_child(dev, pi->dev);
1256 mtx_destroy(&pi->pi_lock);
1257 free(pi->vi, M_CXGBE);
1262 device_delete_children(dev);
1264 if (sc->flags & FULL_INIT_DONE)
1265 adapter_full_uninit(sc);
1267 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1268 t4_fw_bye(sc, sc->mbox);
1270 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1271 pci_release_msi(dev);
1274 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1278 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1282 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1286 t4_free_l2t(sc->l2t);
1289 free(sc->sge.ofld_rxq, M_CXGBE);
1290 free(sc->sge.ofld_txq, M_CXGBE);
1293 free(sc->sge.nm_rxq, M_CXGBE);
1294 free(sc->sge.nm_txq, M_CXGBE);
1296 free(sc->irq, M_CXGBE);
1297 free(sc->sge.rxq, M_CXGBE);
1298 free(sc->sge.txq, M_CXGBE);
1299 free(sc->sge.ctrlq, M_CXGBE);
1300 free(sc->sge.iqmap, M_CXGBE);
1301 free(sc->sge.eqmap, M_CXGBE);
1302 free(sc->tids.ftid_tab, M_CXGBE);
1303 t4_destroy_dma_tag(sc);
1304 if (mtx_initialized(&sc->sc_lock)) {
1305 sx_xlock(&t4_list_lock);
1306 SLIST_REMOVE(&t4_list, sc, adapter, link);
1307 sx_xunlock(&t4_list_lock);
1308 mtx_destroy(&sc->sc_lock);
1311 callout_drain(&sc->sfl_callout);
1312 if (mtx_initialized(&sc->tids.ftid_lock))
1313 mtx_destroy(&sc->tids.ftid_lock);
1314 if (mtx_initialized(&sc->sfl_lock))
1315 mtx_destroy(&sc->sfl_lock);
1316 if (mtx_initialized(&sc->ifp_lock))
1317 mtx_destroy(&sc->ifp_lock);
1318 if (mtx_initialized(&sc->reg_lock))
1319 mtx_destroy(&sc->reg_lock);
1321 for (i = 0; i < NUM_MEMWIN; i++) {
1322 struct memwin *mw = &sc->memwin[i];
1324 if (rw_initialized(&mw->mw_lock))
1325 rw_destroy(&mw->mw_lock);
1328 bzero(sc, sizeof(*sc));
1334 cxgbe_probe(device_t dev)
1337 struct port_info *pi = device_get_softc(dev);
1339 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1340 device_set_desc_copy(dev, buf);
1342 return (BUS_PROBE_DEFAULT);
1345 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1346 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1347 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1348 #define T4_CAP_ENABLE (T4_CAP)
1351 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1356 vi->xact_addr_filt = -1;
1357 callout_init(&vi->tick, 1);
1359 /* Allocate an ifnet and set it up */
1360 ifp = if_alloc(IFT_ETHER);
1362 device_printf(dev, "Cannot allocate ifnet\n");
1368 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1369 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1371 ifp->if_init = cxgbe_init;
1372 ifp->if_ioctl = cxgbe_ioctl;
1373 ifp->if_transmit = cxgbe_transmit;
1374 ifp->if_qflush = cxgbe_qflush;
1376 ifp->if_capabilities = T4_CAP;
1378 if (vi->nofldrxq != 0)
1379 ifp->if_capabilities |= IFCAP_TOE;
1382 if (vi->nnmrxq != 0)
1383 ifp->if_capabilities |= IFCAP_NETMAP;
1385 ifp->if_capenable = T4_CAP_ENABLE;
1386 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1387 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1389 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1390 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS;
1391 ifp->if_hw_tsomaxsegsize = 65536;
1393 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1394 EVENTHANDLER_PRI_ANY);
1396 ether_ifattach(ifp, vi->hw_addr);
1398 if (ifp->if_capabilities & IFCAP_NETMAP)
1399 cxgbe_nm_attach(vi);
1401 sb = sbuf_new_auto();
1402 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1404 if (ifp->if_capabilities & IFCAP_TOE)
1405 sbuf_printf(sb, "; %d txq, %d rxq (TOE)",
1406 vi->nofldtxq, vi->nofldrxq);
1409 if (ifp->if_capabilities & IFCAP_NETMAP)
1410 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1411 vi->nnmtxq, vi->nnmrxq);
1414 device_printf(dev, "%s\n", sbuf_data(sb));
1423 cxgbe_attach(device_t dev)
1425 struct port_info *pi = device_get_softc(dev);
1426 struct adapter *sc = pi->adapter;
1430 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1432 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1436 for_each_vi(pi, i, vi) {
1439 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1440 if (vi->dev == NULL) {
1441 device_printf(dev, "failed to add VI %d\n", i);
1444 device_set_softc(vi->dev, vi);
1449 bus_generic_attach(dev);
1455 cxgbe_vi_detach(struct vi_info *vi)
1457 struct ifnet *ifp = vi->ifp;
1459 ether_ifdetach(ifp);
1462 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c);
1464 /* Let detach proceed even if these fail. */
1466 if (ifp->if_capabilities & IFCAP_NETMAP)
1467 cxgbe_nm_detach(vi);
1469 cxgbe_uninit_synchronized(vi);
1470 callout_drain(&vi->tick);
1478 cxgbe_detach(device_t dev)
1480 struct port_info *pi = device_get_softc(dev);
1481 struct adapter *sc = pi->adapter;
1484 /* Detach the extra VIs first. */
1485 rc = bus_generic_detach(dev);
1488 device_delete_children(dev);
1490 doom_vi(sc, &pi->vi[0]);
1492 if (pi->flags & HAS_TRACEQ) {
1493 sc->traceq = -1; /* cloner should not create ifnet */
1494 t4_tracer_port_detach(sc);
1497 cxgbe_vi_detach(&pi->vi[0]);
1498 callout_drain(&pi->tick);
1499 ifmedia_removeall(&pi->media);
1501 end_synchronized_op(sc, 0);
1507 cxgbe_init(void *arg)
1509 struct vi_info *vi = arg;
1510 struct adapter *sc = vi->pi->adapter;
1512 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1514 cxgbe_init_synchronized(vi);
1515 end_synchronized_op(sc, 0);
1519 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1521 int rc = 0, mtu, flags, can_sleep;
1522 struct vi_info *vi = ifp->if_softc;
1523 struct port_info *pi = vi->pi;
1524 struct adapter *sc = pi->adapter;
1525 struct ifreq *ifr = (struct ifreq *)data;
1531 if (mtu < ETHERMIN || mtu > MAX_MTU)
1534 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1538 if (vi->flags & VI_INIT_DONE) {
1539 t4_update_fl_bufsize(ifp);
1540 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1541 rc = update_mac_settings(ifp, XGMAC_MTU);
1543 end_synchronized_op(sc, 0);
1549 rc = begin_synchronized_op(sc, vi,
1550 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg");
1554 if (ifp->if_flags & IFF_UP) {
1555 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1556 flags = vi->if_flags;
1557 if ((ifp->if_flags ^ flags) &
1558 (IFF_PROMISC | IFF_ALLMULTI)) {
1559 if (can_sleep == 1) {
1560 end_synchronized_op(sc, 0);
1564 rc = update_mac_settings(ifp,
1565 XGMAC_PROMISC | XGMAC_ALLMULTI);
1568 if (can_sleep == 0) {
1569 end_synchronized_op(sc, LOCK_HELD);
1573 rc = cxgbe_init_synchronized(vi);
1575 vi->if_flags = ifp->if_flags;
1576 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1577 if (can_sleep == 0) {
1578 end_synchronized_op(sc, LOCK_HELD);
1582 rc = cxgbe_uninit_synchronized(vi);
1584 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD);
1588 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1589 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi");
1592 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1593 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1594 end_synchronized_op(sc, LOCK_HELD);
1598 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1602 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1603 if (mask & IFCAP_TXCSUM) {
1604 ifp->if_capenable ^= IFCAP_TXCSUM;
1605 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1607 if (IFCAP_TSO4 & ifp->if_capenable &&
1608 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1609 ifp->if_capenable &= ~IFCAP_TSO4;
1611 "tso4 disabled due to -txcsum.\n");
1614 if (mask & IFCAP_TXCSUM_IPV6) {
1615 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1616 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1618 if (IFCAP_TSO6 & ifp->if_capenable &&
1619 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1620 ifp->if_capenable &= ~IFCAP_TSO6;
1622 "tso6 disabled due to -txcsum6.\n");
1625 if (mask & IFCAP_RXCSUM)
1626 ifp->if_capenable ^= IFCAP_RXCSUM;
1627 if (mask & IFCAP_RXCSUM_IPV6)
1628 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1631 * Note that we leave CSUM_TSO alone (it is always set). The
1632 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1633 * sending a TSO request our way, so it's sufficient to toggle
1636 if (mask & IFCAP_TSO4) {
1637 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1638 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1639 if_printf(ifp, "enable txcsum first.\n");
1643 ifp->if_capenable ^= IFCAP_TSO4;
1645 if (mask & IFCAP_TSO6) {
1646 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1647 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1648 if_printf(ifp, "enable txcsum6 first.\n");
1652 ifp->if_capenable ^= IFCAP_TSO6;
1654 if (mask & IFCAP_LRO) {
1655 #if defined(INET) || defined(INET6)
1657 struct sge_rxq *rxq;
1659 ifp->if_capenable ^= IFCAP_LRO;
1660 for_each_rxq(vi, i, rxq) {
1661 if (ifp->if_capenable & IFCAP_LRO)
1662 rxq->iq.flags |= IQ_LRO_ENABLED;
1664 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1669 if (mask & IFCAP_TOE) {
1670 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1672 rc = toe_capability(vi, enable);
1676 ifp->if_capenable ^= mask;
1679 if (mask & IFCAP_VLAN_HWTAGGING) {
1680 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1681 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1682 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1684 if (mask & IFCAP_VLAN_MTU) {
1685 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1687 /* Need to find out how to disable auto-mtu-inflation */
1689 if (mask & IFCAP_VLAN_HWTSO)
1690 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1691 if (mask & IFCAP_VLAN_HWCSUM)
1692 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1694 #ifdef VLAN_CAPABILITIES
1695 VLAN_CAPABILITIES(ifp);
1698 end_synchronized_op(sc, 0);
1704 ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
1708 struct ifi2creq i2c;
1710 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
1713 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
1717 if (i2c.len > sizeof(i2c.data)) {
1721 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
1724 rc = -t4_i2c_rd(sc, sc->mbox, pi->port_id, i2c.dev_addr,
1725 i2c.offset, i2c.len, &i2c.data[0]);
1726 end_synchronized_op(sc, 0);
1728 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
1733 rc = ether_ioctl(ifp, cmd, data);
1740 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1742 struct vi_info *vi = ifp->if_softc;
1743 struct port_info *pi = vi->pi;
1744 struct adapter *sc = pi->adapter;
1745 struct sge_txq *txq;
1750 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
1752 if (__predict_false(pi->link_cfg.link_ok == 0)) {
1757 rc = parse_pkt(sc, &m);
1758 if (__predict_false(rc != 0)) {
1759 MPASS(m == NULL); /* was freed already */
1760 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
1765 txq = &sc->sge.txq[vi->first_txq];
1766 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
1767 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
1771 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
1772 if (__predict_false(rc != 0))
1779 cxgbe_qflush(struct ifnet *ifp)
1781 struct vi_info *vi = ifp->if_softc;
1782 struct sge_txq *txq;
1785 /* queues do not exist if !VI_INIT_DONE. */
1786 if (vi->flags & VI_INIT_DONE) {
1787 for_each_txq(vi, i, txq) {
1789 txq->eq.flags |= EQ_QFLUSH;
1791 while (!mp_ring_is_idle(txq->r)) {
1792 mp_ring_check_drainage(txq->r, 0);
1796 txq->eq.flags &= ~EQ_QFLUSH;
1804 * The kernel picks a media from the list we had provided so we do not have to
1805 * validate the request.
1808 cxgbe_media_change(struct ifnet *ifp)
1810 struct vi_info *vi = ifp->if_softc;
1811 struct port_info *pi = vi->pi;
1812 struct ifmedia *ifm = &pi->media;
1813 struct link_config *lc = &pi->link_cfg;
1814 struct adapter *sc = pi->adapter;
1817 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4mec");
1821 if (IFM_SUBTYPE(ifm->ifm_media) == IFM_AUTO) {
1822 MPASS(lc->supported & FW_PORT_CAP_ANEG);
1823 lc->requested_aneg = AUTONEG_ENABLE;
1825 lc->requested_aneg = AUTONEG_DISABLE;
1826 lc->requested_speed =
1827 ifmedia_baudrate(ifm->ifm_media) / 1000000;
1828 lc->requested_fc = 0;
1829 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_RXPAUSE)
1830 lc->requested_fc |= PAUSE_RX;
1831 if (IFM_OPTIONS(ifm->ifm_media) & IFM_ETH_TXPAUSE)
1832 lc->requested_fc |= PAUSE_TX;
1835 rc = apply_l1cfg(pi);
1837 end_synchronized_op(sc, 0);
1842 * Mbps to FW_PORT_CAP_SPEED_* bit.
1845 speed_to_fwspeed(int speed)
1850 return (FW_PORT_CAP_SPEED_100G);
1852 return (FW_PORT_CAP_SPEED_40G);
1854 return (FW_PORT_CAP_SPEED_25G);
1856 return (FW_PORT_CAP_SPEED_10G);
1858 return (FW_PORT_CAP_SPEED_1G);
1860 return (FW_PORT_CAP_SPEED_100M);
1867 * Base media word (without ETHER, pause, link active, etc.) for the port at the
1871 port_mword(struct port_info *pi, uint16_t speed)
1874 MPASS(speed & M_FW_PORT_CAP_SPEED);
1875 MPASS(powerof2(speed));
1877 switch(pi->port_type) {
1878 case FW_PORT_TYPE_BT_SGMII:
1879 case FW_PORT_TYPE_BT_XFI:
1880 case FW_PORT_TYPE_BT_XAUI:
1883 case FW_PORT_CAP_SPEED_100M:
1885 case FW_PORT_CAP_SPEED_1G:
1886 return (IFM_1000_T);
1887 case FW_PORT_CAP_SPEED_10G:
1891 case FW_PORT_TYPE_KX4:
1892 if (speed == FW_PORT_CAP_SPEED_10G)
1893 return (IFM_10G_KX4);
1895 case FW_PORT_TYPE_CX4:
1896 if (speed == FW_PORT_CAP_SPEED_10G)
1897 return (IFM_10G_CX4);
1899 case FW_PORT_TYPE_KX:
1900 if (speed == FW_PORT_CAP_SPEED_1G)
1901 return (IFM_1000_KX);
1903 case FW_PORT_TYPE_KR:
1904 case FW_PORT_TYPE_BP_AP:
1905 case FW_PORT_TYPE_BP4_AP:
1906 case FW_PORT_TYPE_BP40_BA:
1907 case FW_PORT_TYPE_KR4_100G:
1908 case FW_PORT_TYPE_KR_SFP28:
1909 case FW_PORT_TYPE_KR_XLAUI:
1911 case FW_PORT_CAP_SPEED_1G:
1912 return (IFM_1000_KX);
1913 case FW_PORT_CAP_SPEED_10G:
1914 return (IFM_10G_KR);
1915 case FW_PORT_CAP_SPEED_25G:
1916 return (IFM_25G_KR);
1917 case FW_PORT_CAP_SPEED_40G:
1918 return (IFM_40G_KR4);
1919 case FW_PORT_CAP_SPEED_100G:
1920 return (IFM_100G_KR4);
1923 case FW_PORT_TYPE_FIBER_XFI:
1924 case FW_PORT_TYPE_FIBER_XAUI:
1925 case FW_PORT_TYPE_SFP:
1926 case FW_PORT_TYPE_QSFP_10G:
1927 case FW_PORT_TYPE_QSA:
1928 case FW_PORT_TYPE_QSFP:
1929 case FW_PORT_TYPE_CR4_QSFP:
1930 case FW_PORT_TYPE_CR_QSFP:
1931 case FW_PORT_TYPE_CR2_QSFP:
1932 case FW_PORT_TYPE_SFP28:
1933 /* Pluggable transceiver */
1934 switch (pi->mod_type) {
1935 case FW_PORT_MOD_TYPE_LR:
1937 case FW_PORT_CAP_SPEED_1G:
1938 return (IFM_1000_LX);
1939 case FW_PORT_CAP_SPEED_10G:
1940 return (IFM_10G_LR);
1941 case FW_PORT_CAP_SPEED_25G:
1942 return (IFM_25G_LR);
1943 case FW_PORT_CAP_SPEED_40G:
1944 return (IFM_40G_LR4);
1945 case FW_PORT_CAP_SPEED_100G:
1946 return (IFM_100G_LR4);
1949 case FW_PORT_MOD_TYPE_SR:
1951 case FW_PORT_CAP_SPEED_1G:
1952 return (IFM_1000_SX);
1953 case FW_PORT_CAP_SPEED_10G:
1954 return (IFM_10G_SR);
1955 case FW_PORT_CAP_SPEED_25G:
1956 return (IFM_25G_SR);
1957 case FW_PORT_CAP_SPEED_40G:
1958 return (IFM_40G_SR4);
1959 case FW_PORT_CAP_SPEED_100G:
1960 return (IFM_100G_SR4);
1963 case FW_PORT_MOD_TYPE_ER:
1964 if (speed == FW_PORT_CAP_SPEED_10G)
1965 return (IFM_10G_ER);
1967 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
1968 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
1970 case FW_PORT_CAP_SPEED_1G:
1971 return (IFM_1000_CX);
1972 case FW_PORT_CAP_SPEED_10G:
1973 return (IFM_10G_TWINAX);
1974 case FW_PORT_CAP_SPEED_25G:
1975 return (IFM_25G_CR);
1976 case FW_PORT_CAP_SPEED_40G:
1977 return (IFM_40G_CR4);
1978 case FW_PORT_CAP_SPEED_100G:
1979 return (IFM_100G_CR4);
1982 case FW_PORT_MOD_TYPE_LRM:
1983 if (speed == FW_PORT_CAP_SPEED_10G)
1984 return (IFM_10G_LRM);
1986 case FW_PORT_MOD_TYPE_NA:
1987 MPASS(0); /* Not pluggable? */
1989 case FW_PORT_MOD_TYPE_ERROR:
1990 case FW_PORT_MOD_TYPE_UNKNOWN:
1991 case FW_PORT_MOD_TYPE_NOTSUPPORTED:
1993 case FW_PORT_MOD_TYPE_NONE:
1997 case FW_PORT_TYPE_NONE:
2001 return (IFM_UNKNOWN);
2005 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
2007 struct vi_info *vi = ifp->if_softc;
2008 struct port_info *pi = vi->pi;
2009 struct adapter *sc = pi->adapter;
2010 struct link_config *lc = &pi->link_cfg;
2012 if (begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4med") != 0)
2016 if (pi->up_vis == 0) {
2018 * If all the interfaces are administratively down the firmware
2019 * does not report transceiver changes. Refresh port info here
2020 * so that ifconfig displays accurate ifmedia at all times.
2021 * This is the only reason we have a synchronized op in this
2022 * function. Just PORT_LOCK would have been enough otherwise.
2024 t4_update_port_info(pi);
2025 build_medialist(pi, &pi->media);
2029 ifmr->ifm_status = IFM_AVALID;
2030 if (lc->link_ok == 0)
2032 ifmr->ifm_status |= IFM_ACTIVE;
2035 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
2036 ifmr->ifm_active &= ~(IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE);
2037 if (lc->fc & PAUSE_RX)
2038 ifmr->ifm_active |= IFM_ETH_RXPAUSE;
2039 if (lc->fc & PAUSE_TX)
2040 ifmr->ifm_active |= IFM_ETH_TXPAUSE;
2041 ifmr->ifm_active |= port_mword(pi, speed_to_fwspeed(lc->speed));
2044 end_synchronized_op(sc, 0);
2048 vcxgbe_probe(device_t dev)
2051 struct vi_info *vi = device_get_softc(dev);
2053 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
2055 device_set_desc_copy(dev, buf);
2057 return (BUS_PROBE_DEFAULT);
2061 vcxgbe_attach(device_t dev)
2064 struct port_info *pi;
2066 int func, index, rc;
2069 vi = device_get_softc(dev);
2073 index = vi - pi->vi;
2074 KASSERT(index < nitems(vi_mac_funcs),
2075 ("%s: VI %s doesn't have a MAC func", __func__,
2076 device_get_nameunit(dev)));
2077 func = vi_mac_funcs[index];
2078 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
2079 vi->hw_addr, &vi->rss_size, func, 0);
2081 device_printf(dev, "Failed to allocate virtual interface "
2082 "for port %d: %d\n", pi->port_id, -rc);
2086 if (chip_id(sc) <= CHELSIO_T5)
2087 vi->smt_idx = (rc & 0x7f) << 1;
2089 vi->smt_idx = (rc & 0x7f);
2091 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
2092 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
2093 V_FW_PARAMS_PARAM_YZ(vi->viid);
2094 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2096 vi->rss_base = 0xffff;
2098 /* MPASS((val >> 16) == rss_size); */
2099 vi->rss_base = val & 0xffff;
2102 rc = cxgbe_vi_attach(dev, vi);
2104 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2111 vcxgbe_detach(device_t dev)
2116 vi = device_get_softc(dev);
2117 sc = vi->pi->adapter;
2121 cxgbe_vi_detach(vi);
2122 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
2124 end_synchronized_op(sc, 0);
2130 t4_fatal_err(struct adapter *sc)
2132 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
2133 t4_intr_disable(sc);
2134 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
2135 device_get_nameunit(sc->dev));
2139 t4_add_adapter(struct adapter *sc)
2141 sx_xlock(&t4_list_lock);
2142 SLIST_INSERT_HEAD(&t4_list, sc, link);
2143 sx_xunlock(&t4_list_lock);
2147 t4_map_bars_0_and_4(struct adapter *sc)
2149 sc->regs_rid = PCIR_BAR(0);
2150 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2151 &sc->regs_rid, RF_ACTIVE);
2152 if (sc->regs_res == NULL) {
2153 device_printf(sc->dev, "cannot map registers.\n");
2156 sc->bt = rman_get_bustag(sc->regs_res);
2157 sc->bh = rman_get_bushandle(sc->regs_res);
2158 sc->mmio_len = rman_get_size(sc->regs_res);
2159 setbit(&sc->doorbells, DOORBELL_KDB);
2161 sc->msix_rid = PCIR_BAR(4);
2162 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2163 &sc->msix_rid, RF_ACTIVE);
2164 if (sc->msix_res == NULL) {
2165 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
2173 t4_map_bar_2(struct adapter *sc)
2177 * T4: only iWARP driver uses the userspace doorbells. There is no need
2178 * to map it if RDMA is disabled.
2180 if (is_t4(sc) && sc->rdmacaps == 0)
2183 sc->udbs_rid = PCIR_BAR(2);
2184 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
2185 &sc->udbs_rid, RF_ACTIVE);
2186 if (sc->udbs_res == NULL) {
2187 device_printf(sc->dev, "cannot map doorbell BAR.\n");
2190 sc->udbs_base = rman_get_virtual(sc->udbs_res);
2192 if (chip_id(sc) >= CHELSIO_T5) {
2193 setbit(&sc->doorbells, DOORBELL_UDB);
2194 #if defined(__i386__) || defined(__amd64__)
2195 if (t5_write_combine) {
2199 * Enable write combining on BAR2. This is the
2200 * userspace doorbell BAR and is split into 128B
2201 * (UDBS_SEG_SIZE) doorbell regions, each associated
2202 * with an egress queue. The first 64B has the doorbell
2203 * and the second 64B can be used to submit a tx work
2204 * request with an implicit doorbell.
2207 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
2208 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
2210 clrbit(&sc->doorbells, DOORBELL_UDB);
2211 setbit(&sc->doorbells, DOORBELL_WCWR);
2212 setbit(&sc->doorbells, DOORBELL_UDBWC);
2214 device_printf(sc->dev,
2215 "couldn't enable write combining: %d\n",
2219 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
2220 t4_write_reg(sc, A_SGE_STAT_CFG,
2221 V_STATSOURCE_T5(7) | mode);
2229 struct memwin_init {
2234 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2235 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2236 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2237 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2240 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2241 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2242 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2243 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2247 setup_memwin(struct adapter *sc)
2249 const struct memwin_init *mw_init;
2256 * Read low 32b of bar0 indirectly via the hardware backdoor
2257 * mechanism. Works from within PCI passthrough environments
2258 * too, where rman_get_start() can return a different value. We
2259 * need to program the T4 memory window decoders with the actual
2260 * addresses that will be coming across the PCIe link.
2262 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2263 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2265 mw_init = &t4_memwin[0];
2267 /* T5+ use the relative offset inside the PCIe BAR */
2270 mw_init = &t5_memwin[0];
2273 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2274 rw_init(&mw->mw_lock, "memory window access");
2275 mw->mw_base = mw_init->base;
2276 mw->mw_aperture = mw_init->aperture;
2279 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2280 (mw->mw_base + bar0) | V_BIR(0) |
2281 V_WINDOW(ilog2(mw->mw_aperture) - 10));
2282 rw_wlock(&mw->mw_lock);
2283 position_memwin(sc, i, 0);
2284 rw_wunlock(&mw->mw_lock);
2288 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2292 * Positions the memory window at the given address in the card's address space.
2293 * There are some alignment requirements and the actual position may be at an
2294 * address prior to the requested address. mw->mw_curpos always has the actual
2295 * position of the window.
2298 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2304 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2305 mw = &sc->memwin[idx];
2306 rw_assert(&mw->mw_lock, RA_WLOCKED);
2310 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
2312 pf = V_PFNUM(sc->pf);
2313 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
2315 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2316 t4_write_reg(sc, reg, mw->mw_curpos | pf);
2317 t4_read_reg(sc, reg); /* flush */
2321 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2327 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2329 /* Memory can only be accessed in naturally aligned 4 byte units */
2330 if (addr & 3 || len & 3 || len <= 0)
2333 mw = &sc->memwin[idx];
2335 rw_rlock(&mw->mw_lock);
2336 mw_end = mw->mw_curpos + mw->mw_aperture;
2337 if (addr >= mw_end || addr < mw->mw_curpos) {
2338 /* Will need to reposition the window */
2339 if (!rw_try_upgrade(&mw->mw_lock)) {
2340 rw_runlock(&mw->mw_lock);
2341 rw_wlock(&mw->mw_lock);
2343 rw_assert(&mw->mw_lock, RA_WLOCKED);
2344 position_memwin(sc, idx, addr);
2345 rw_downgrade(&mw->mw_lock);
2346 mw_end = mw->mw_curpos + mw->mw_aperture;
2348 rw_assert(&mw->mw_lock, RA_RLOCKED);
2349 while (addr < mw_end && len > 0) {
2351 v = t4_read_reg(sc, mw->mw_base + addr -
2353 *val++ = le32toh(v);
2356 t4_write_reg(sc, mw->mw_base + addr -
2357 mw->mw_curpos, htole32(v));;
2362 rw_runlock(&mw->mw_lock);
2369 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2373 return (rw_via_memwin(sc, idx, addr, val, len, 0));
2377 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
2378 const uint32_t *val, int len)
2381 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
2385 t4_range_cmp(const void *a, const void *b)
2387 return ((const struct t4_range *)a)->start -
2388 ((const struct t4_range *)b)->start;
2392 * Verify that the memory range specified by the addr/len pair is valid within
2393 * the card's address space.
2396 validate_mem_range(struct adapter *sc, uint32_t addr, int len)
2398 struct t4_range mem_ranges[4], *r, *next;
2399 uint32_t em, addr_len;
2400 int i, n, remaining;
2402 /* Memory can only be accessed in naturally aligned 4 byte units */
2403 if (addr & 3 || len & 3 || len <= 0)
2406 /* Enabled memories */
2407 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2411 bzero(r, sizeof(mem_ranges));
2412 if (em & F_EDRAM0_ENABLE) {
2413 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2414 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2416 r->start = G_EDRAM0_BASE(addr_len) << 20;
2417 if (addr >= r->start &&
2418 addr + len <= r->start + r->size)
2424 if (em & F_EDRAM1_ENABLE) {
2425 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2426 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2428 r->start = G_EDRAM1_BASE(addr_len) << 20;
2429 if (addr >= r->start &&
2430 addr + len <= r->start + r->size)
2436 if (em & F_EXT_MEM_ENABLE) {
2437 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2438 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2440 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2441 if (addr >= r->start &&
2442 addr + len <= r->start + r->size)
2448 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2449 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2450 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2452 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2453 if (addr >= r->start &&
2454 addr + len <= r->start + r->size)
2460 MPASS(n <= nitems(mem_ranges));
2463 /* Sort and merge the ranges. */
2464 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2466 /* Start from index 0 and examine the next n - 1 entries. */
2468 for (remaining = n - 1; remaining > 0; remaining--, r++) {
2470 MPASS(r->size > 0); /* r is a valid entry. */
2472 MPASS(next->size > 0); /* and so is the next one. */
2474 while (r->start + r->size >= next->start) {
2475 /* Merge the next one into the current entry. */
2476 r->size = max(r->start + r->size,
2477 next->start + next->size) - r->start;
2478 n--; /* One fewer entry in total. */
2479 if (--remaining == 0)
2480 goto done; /* short circuit */
2483 if (next != r + 1) {
2485 * Some entries were merged into r and next
2486 * points to the first valid entry that couldn't
2489 MPASS(next->size > 0); /* must be valid */
2490 memcpy(r + 1, next, remaining * sizeof(*r));
2493 * This so that the foo->size assertion in the
2494 * next iteration of the loop do the right
2495 * thing for entries that were pulled up and are
2498 MPASS(n < nitems(mem_ranges));
2499 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
2500 sizeof(struct t4_range));
2505 /* Done merging the ranges. */
2508 for (i = 0; i < n; i++, r++) {
2509 if (addr >= r->start &&
2510 addr + len <= r->start + r->size)
2519 fwmtype_to_hwmtype(int mtype)
2523 case FW_MEMTYPE_EDC0:
2525 case FW_MEMTYPE_EDC1:
2527 case FW_MEMTYPE_EXTMEM:
2529 case FW_MEMTYPE_EXTMEM1:
2532 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
2537 * Verify that the memory range specified by the memtype/offset/len pair is
2538 * valid and lies entirely within the memtype specified. The global address of
2539 * the start of the range is returned in addr.
2542 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len,
2545 uint32_t em, addr_len, maddr;
2547 /* Memory can only be accessed in naturally aligned 4 byte units */
2548 if (off & 3 || len & 3 || len == 0)
2551 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2552 switch (fwmtype_to_hwmtype(mtype)) {
2554 if (!(em & F_EDRAM0_ENABLE))
2556 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2557 maddr = G_EDRAM0_BASE(addr_len) << 20;
2560 if (!(em & F_EDRAM1_ENABLE))
2562 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2563 maddr = G_EDRAM1_BASE(addr_len) << 20;
2566 if (!(em & F_EXT_MEM_ENABLE))
2568 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2569 maddr = G_EXT_MEM_BASE(addr_len) << 20;
2572 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
2574 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2575 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
2581 *addr = maddr + off; /* global address */
2582 return (validate_mem_range(sc, *addr, len));
2586 fixup_devlog_params(struct adapter *sc)
2588 struct devlog_params *dparams = &sc->params.devlog;
2591 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
2592 dparams->size, &dparams->addr);
2598 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, int num_vis,
2599 struct intrs_and_queues *iaq)
2601 int rc, itype, navail, nrxq10g, nrxq1g, n;
2602 int nofldrxq10g = 0, nofldrxq1g = 0;
2604 bzero(iaq, sizeof(*iaq));
2606 iaq->ntxq10g = t4_ntxq10g;
2607 iaq->ntxq1g = t4_ntxq1g;
2608 iaq->ntxq_vi = t4_ntxq_vi;
2609 iaq->nrxq10g = nrxq10g = t4_nrxq10g;
2610 iaq->nrxq1g = nrxq1g = t4_nrxq1g;
2611 iaq->nrxq_vi = t4_nrxq_vi;
2612 iaq->rsrv_noflowq = t4_rsrv_noflowq;
2614 if (is_offload(sc)) {
2615 iaq->nofldtxq10g = t4_nofldtxq10g;
2616 iaq->nofldtxq1g = t4_nofldtxq1g;
2617 iaq->nofldtxq_vi = t4_nofldtxq_vi;
2618 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g;
2619 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g;
2620 iaq->nofldrxq_vi = t4_nofldrxq_vi;
2624 iaq->nnmtxq_vi = t4_nnmtxq_vi;
2625 iaq->nnmrxq_vi = t4_nnmrxq_vi;
2628 for (itype = INTR_MSIX; itype; itype >>= 1) {
2630 if ((itype & t4_intr_types) == 0)
2631 continue; /* not allowed */
2633 if (itype == INTR_MSIX)
2634 navail = pci_msix_count(sc->dev);
2635 else if (itype == INTR_MSI)
2636 navail = pci_msi_count(sc->dev);
2643 iaq->intr_type = itype;
2644 iaq->intr_flags_10g = 0;
2645 iaq->intr_flags_1g = 0;
2648 * Best option: an interrupt vector for errors, one for the
2649 * firmware event queue, and one for every rxq (NIC and TOE) of
2650 * every VI. The VIs that support netmap use the same
2651 * interrupts for the NIC rx queues and the netmap rx queues
2652 * because only one set of queues is active at a time.
2654 iaq->nirq = T4_EXTRA_INTR;
2655 iaq->nirq += n10g * (nrxq10g + nofldrxq10g);
2656 iaq->nirq += n1g * (nrxq1g + nofldrxq1g);
2657 iaq->nirq += (n10g + n1g) * (num_vis - 1) *
2658 max(iaq->nrxq_vi, iaq->nnmrxq_vi); /* See comment above. */
2659 iaq->nirq += (n10g + n1g) * (num_vis - 1) * iaq->nofldrxq_vi;
2660 if (iaq->nirq <= navail &&
2661 (itype != INTR_MSI || powerof2(iaq->nirq))) {
2662 iaq->intr_flags_10g = INTR_ALL;
2663 iaq->intr_flags_1g = INTR_ALL;
2667 /* Disable the VIs (and netmap) if there aren't enough intrs */
2669 device_printf(sc->dev, "virtual interfaces disabled "
2670 "because num_vis=%u with current settings "
2671 "(nrxq10g=%u, nrxq1g=%u, nofldrxq10g=%u, "
2672 "nofldrxq1g=%u, nrxq_vi=%u nofldrxq_vi=%u, "
2673 "nnmrxq_vi=%u) would need %u interrupts but "
2674 "only %u are available.\n", num_vis, nrxq10g,
2675 nrxq1g, nofldrxq10g, nofldrxq1g, iaq->nrxq_vi,
2676 iaq->nofldrxq_vi, iaq->nnmrxq_vi, iaq->nirq,
2679 iaq->ntxq_vi = iaq->nrxq_vi = 0;
2680 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
2681 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
2686 * Second best option: a vector for errors, one for the firmware
2687 * event queue, and vectors for either all the NIC rx queues or
2688 * all the TOE rx queues. The queues that don't get vectors
2689 * will forward their interrupts to those that do.
2691 iaq->nirq = T4_EXTRA_INTR;
2692 if (nrxq10g >= nofldrxq10g) {
2693 iaq->intr_flags_10g = INTR_RXQ;
2694 iaq->nirq += n10g * nrxq10g;
2696 iaq->intr_flags_10g = INTR_OFLD_RXQ;
2697 iaq->nirq += n10g * nofldrxq10g;
2699 if (nrxq1g >= nofldrxq1g) {
2700 iaq->intr_flags_1g = INTR_RXQ;
2701 iaq->nirq += n1g * nrxq1g;
2703 iaq->intr_flags_1g = INTR_OFLD_RXQ;
2704 iaq->nirq += n1g * nofldrxq1g;
2706 if (iaq->nirq <= navail &&
2707 (itype != INTR_MSI || powerof2(iaq->nirq)))
2711 * Next best option: an interrupt vector for errors, one for the
2712 * firmware event queue, and at least one per main-VI. At this
2713 * point we know we'll have to downsize nrxq and/or nofldrxq to
2714 * fit what's available to us.
2716 iaq->nirq = T4_EXTRA_INTR;
2717 iaq->nirq += n10g + n1g;
2718 if (iaq->nirq <= navail) {
2719 int leftover = navail - iaq->nirq;
2722 int target = max(nrxq10g, nofldrxq10g);
2724 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ?
2725 INTR_RXQ : INTR_OFLD_RXQ;
2728 while (n < target && leftover >= n10g) {
2733 iaq->nrxq10g = min(n, nrxq10g);
2735 iaq->nofldrxq10g = min(n, nofldrxq10g);
2740 int target = max(nrxq1g, nofldrxq1g);
2742 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ?
2743 INTR_RXQ : INTR_OFLD_RXQ;
2746 while (n < target && leftover >= n1g) {
2751 iaq->nrxq1g = min(n, nrxq1g);
2753 iaq->nofldrxq1g = min(n, nofldrxq1g);
2757 if (itype != INTR_MSI || powerof2(iaq->nirq))
2762 * Least desirable option: one interrupt vector for everything.
2764 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1;
2765 iaq->intr_flags_10g = iaq->intr_flags_1g = 0;
2768 iaq->nofldrxq10g = iaq->nofldrxq1g = 1;
2773 if (itype == INTR_MSIX)
2774 rc = pci_alloc_msix(sc->dev, &navail);
2775 else if (itype == INTR_MSI)
2776 rc = pci_alloc_msi(sc->dev, &navail);
2779 if (navail == iaq->nirq)
2783 * Didn't get the number requested. Use whatever number
2784 * the kernel is willing to allocate (it's in navail).
2786 device_printf(sc->dev, "fewer vectors than requested, "
2787 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
2788 itype, iaq->nirq, navail);
2789 pci_release_msi(sc->dev);
2793 device_printf(sc->dev,
2794 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
2795 itype, rc, iaq->nirq, navail);
2798 device_printf(sc->dev,
2799 "failed to find a usable interrupt type. "
2800 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
2801 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
2806 #define FW_VERSION(chip) ( \
2807 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
2808 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
2809 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
2810 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
2811 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
2817 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */
2821 .kld_name = "t4fw_cfg",
2822 .fw_mod_name = "t4fw",
2824 .chip = FW_HDR_CHIP_T4,
2825 .fw_ver = htobe32_const(FW_VERSION(T4)),
2826 .intfver_nic = FW_INTFVER(T4, NIC),
2827 .intfver_vnic = FW_INTFVER(T4, VNIC),
2828 .intfver_ofld = FW_INTFVER(T4, OFLD),
2829 .intfver_ri = FW_INTFVER(T4, RI),
2830 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
2831 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
2832 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
2833 .intfver_fcoe = FW_INTFVER(T4, FCOE),
2837 .kld_name = "t5fw_cfg",
2838 .fw_mod_name = "t5fw",
2840 .chip = FW_HDR_CHIP_T5,
2841 .fw_ver = htobe32_const(FW_VERSION(T5)),
2842 .intfver_nic = FW_INTFVER(T5, NIC),
2843 .intfver_vnic = FW_INTFVER(T5, VNIC),
2844 .intfver_ofld = FW_INTFVER(T5, OFLD),
2845 .intfver_ri = FW_INTFVER(T5, RI),
2846 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
2847 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2848 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
2849 .intfver_fcoe = FW_INTFVER(T5, FCOE),
2853 .kld_name = "t6fw_cfg",
2854 .fw_mod_name = "t6fw",
2856 .chip = FW_HDR_CHIP_T6,
2857 .fw_ver = htobe32_const(FW_VERSION(T6)),
2858 .intfver_nic = FW_INTFVER(T6, NIC),
2859 .intfver_vnic = FW_INTFVER(T6, VNIC),
2860 .intfver_ofld = FW_INTFVER(T6, OFLD),
2861 .intfver_ri = FW_INTFVER(T6, RI),
2862 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
2863 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
2864 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
2865 .intfver_fcoe = FW_INTFVER(T6, FCOE),
2870 static struct fw_info *
2871 find_fw_info(int chip)
2875 for (i = 0; i < nitems(fw_info); i++) {
2876 if (fw_info[i].chip == chip)
2877 return (&fw_info[i]);
2883 * Is the given firmware API compatible with the one the driver was compiled
2887 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
2890 /* short circuit if it's the exact same firmware version */
2891 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
2895 * XXX: Is this too conservative? Perhaps I should limit this to the
2896 * features that are supported in the driver.
2898 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
2899 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
2900 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
2901 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
2909 * The firmware in the KLD is usable, but should it be installed? This routine
2910 * explains itself in detail if it indicates the KLD firmware should be
2914 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
2918 if (!card_fw_usable) {
2919 reason = "incompatible or unusable";
2924 reason = "older than the version bundled with this driver";
2928 if (t4_fw_install == 2 && k != c) {
2929 reason = "different than the version bundled with this driver";
2936 if (t4_fw_install == 0) {
2937 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2938 "but the driver is prohibited from installing a different "
2939 "firmware on the card.\n",
2940 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2941 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
2946 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2947 "installing firmware %u.%u.%u.%u on card.\n",
2948 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2949 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
2950 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2951 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2956 * Establish contact with the firmware and determine if we are the master driver
2957 * or not, and whether we are responsible for chip initialization.
2960 prep_firmware(struct adapter *sc)
2962 const struct firmware *fw = NULL, *default_cfg;
2963 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
2964 enum dev_state state;
2965 struct fw_info *fw_info;
2966 struct fw_hdr *card_fw; /* fw on the card */
2967 const struct fw_hdr *kld_fw; /* fw in the KLD */
2968 const struct fw_hdr *drv_fw; /* fw header the driver was compiled
2971 /* Contact firmware. */
2972 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
2973 if (rc < 0 || state == DEV_STATE_ERR) {
2975 device_printf(sc->dev,
2976 "failed to connect to the firmware: %d, %d.\n", rc, state);
2981 sc->flags |= MASTER_PF;
2982 else if (state == DEV_STATE_UNINIT) {
2984 * We didn't get to be the master so we definitely won't be
2985 * configuring the chip. It's a bug if someone else hasn't
2986 * configured it already.
2988 device_printf(sc->dev, "couldn't be master(%d), "
2989 "device not already initialized either(%d).\n", rc, state);
2993 /* This is the firmware whose headers the driver was compiled against */
2994 fw_info = find_fw_info(chip_id(sc));
2995 if (fw_info == NULL) {
2996 device_printf(sc->dev,
2997 "unable to look up firmware information for chip %d.\n",
3001 drv_fw = &fw_info->fw_hdr;
3004 * The firmware KLD contains many modules. The KLD name is also the
3005 * name of the module that contains the default config file.
3007 default_cfg = firmware_get(fw_info->kld_name);
3009 /* Read the header of the firmware on the card */
3010 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
3011 rc = -t4_read_flash(sc, FLASH_FW_START,
3012 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
3014 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
3016 device_printf(sc->dev,
3017 "Unable to read card's firmware header: %d\n", rc);
3021 /* This is the firmware in the KLD */
3022 fw = firmware_get(fw_info->fw_mod_name);
3024 kld_fw = (const void *)fw->data;
3025 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
3031 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
3032 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
3034 * Common case: the firmware on the card is an exact match and
3035 * the KLD is an exact match too, or the KLD is
3036 * absent/incompatible. Note that t4_fw_install = 2 is ignored
3037 * here -- use cxgbetool loadfw if you want to reinstall the
3038 * same firmware as the one on the card.
3040 } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
3041 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
3042 be32toh(card_fw->fw_ver))) {
3044 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
3046 device_printf(sc->dev,
3047 "failed to install firmware: %d\n", rc);
3051 /* Installed successfully, update the cached header too. */
3052 memcpy(card_fw, kld_fw, sizeof(*card_fw));
3054 need_fw_reset = 0; /* already reset as part of load_fw */
3057 if (!card_fw_usable) {
3060 d = ntohl(drv_fw->fw_ver);
3061 c = ntohl(card_fw->fw_ver);
3062 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
3064 device_printf(sc->dev, "Cannot find a usable firmware: "
3065 "fw_install %d, chip state %d, "
3066 "driver compiled with %d.%d.%d.%d, "
3067 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
3068 t4_fw_install, state,
3069 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
3070 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
3071 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
3072 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
3073 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
3074 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
3080 if (need_fw_reset &&
3081 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
3082 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
3083 if (rc != ETIMEDOUT && rc != EIO)
3084 t4_fw_bye(sc, sc->mbox);
3089 rc = get_params__pre_init(sc);
3091 goto done; /* error message displayed already */
3093 /* Partition adapter resources as specified in the config file. */
3094 if (state == DEV_STATE_UNINIT) {
3096 KASSERT(sc->flags & MASTER_PF,
3097 ("%s: trying to change chip settings when not master.",
3100 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
3102 goto done; /* error message displayed already */
3104 t4_tweak_chip_settings(sc);
3106 /* get basic stuff going */
3107 rc = -t4_fw_initialize(sc, sc->mbox);
3109 device_printf(sc->dev, "fw init failed: %d.\n", rc);
3113 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
3118 free(card_fw, M_CXGBE);
3120 firmware_put(fw, FIRMWARE_UNLOAD);
3121 if (default_cfg != NULL)
3122 firmware_put(default_cfg, FIRMWARE_UNLOAD);
3127 #define FW_PARAM_DEV(param) \
3128 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
3129 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
3130 #define FW_PARAM_PFVF(param) \
3131 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
3132 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
3135 * Partition chip resources for use between various PFs, VFs, etc.
3138 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
3139 const char *name_prefix)
3141 const struct firmware *cfg = NULL;
3143 struct fw_caps_config_cmd caps;
3144 uint32_t mtype, moff, finicsum, cfcsum;
3147 * Figure out what configuration file to use. Pick the default config
3148 * file for the card if the user hasn't specified one explicitly.
3150 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
3151 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
3152 /* Card specific overrides go here. */
3153 if (pci_get_device(sc->dev) == 0x440a)
3154 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
3156 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
3160 * We need to load another module if the profile is anything except
3161 * "default" or "flash".
3163 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
3164 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
3167 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
3168 cfg = firmware_get(s);
3170 if (default_cfg != NULL) {
3171 device_printf(sc->dev,
3172 "unable to load module \"%s\" for "
3173 "configuration profile \"%s\", will use "
3174 "the default config file instead.\n",
3176 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
3179 device_printf(sc->dev,
3180 "unable to load module \"%s\" for "
3181 "configuration profile \"%s\", will use "
3182 "the config file on the card's flash "
3183 "instead.\n", s, sc->cfg_file);
3184 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
3190 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
3191 default_cfg == NULL) {
3192 device_printf(sc->dev,
3193 "default config file not available, will use the config "
3194 "file on the card's flash instead.\n");
3195 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
3198 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
3200 const uint32_t *cfdata;
3201 uint32_t param, val, addr;
3203 KASSERT(cfg != NULL || default_cfg != NULL,
3204 ("%s: no config to upload", __func__));
3207 * Ask the firmware where it wants us to upload the config file.
3209 param = FW_PARAM_DEV(CF);
3210 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3212 /* No support for config file? Shouldn't happen. */
3213 device_printf(sc->dev,
3214 "failed to query config file location: %d.\n", rc);
3217 mtype = G_FW_PARAMS_PARAM_Y(val);
3218 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
3221 * XXX: sheer laziness. We deliberately added 4 bytes of
3222 * useless stuffing/comments at the end of the config file so
3223 * it's ok to simply throw away the last remaining bytes when
3224 * the config file is not an exact multiple of 4. This also
3225 * helps with the validate_mt_off_len check.
3228 cflen = cfg->datasize & ~3;
3231 cflen = default_cfg->datasize & ~3;
3232 cfdata = default_cfg->data;
3235 if (cflen > FLASH_CFG_MAX_SIZE) {
3236 device_printf(sc->dev,
3237 "config file too long (%d, max allowed is %d). "
3238 "Will try to use the config on the card, if any.\n",
3239 cflen, FLASH_CFG_MAX_SIZE);
3240 goto use_config_on_flash;
3243 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
3245 device_printf(sc->dev,
3246 "%s: addr (%d/0x%x) or len %d is not valid: %d. "
3247 "Will try to use the config on the card, if any.\n",
3248 __func__, mtype, moff, cflen, rc);
3249 goto use_config_on_flash;
3251 write_via_memwin(sc, 2, addr, cfdata, cflen);
3253 use_config_on_flash:
3254 mtype = FW_MEMTYPE_FLASH;
3255 moff = t4_flash_cfg_addr(sc);
3258 bzero(&caps, sizeof(caps));
3259 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3260 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3261 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3262 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3263 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
3264 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3266 device_printf(sc->dev,
3267 "failed to pre-process config file: %d "
3268 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
3272 finicsum = be32toh(caps.finicsum);
3273 cfcsum = be32toh(caps.cfcsum);
3274 if (finicsum != cfcsum) {
3275 device_printf(sc->dev,
3276 "WARNING: config file checksum mismatch: %08x %08x\n",
3279 sc->cfcsum = cfcsum;
3281 #define LIMIT_CAPS(x) do { \
3282 caps.x &= htobe16(t4_##x##_allowed); \
3286 * Let the firmware know what features will (not) be used so it can tune
3287 * things accordingly.
3289 LIMIT_CAPS(nbmcaps);
3290 LIMIT_CAPS(linkcaps);
3291 LIMIT_CAPS(switchcaps);
3292 LIMIT_CAPS(niccaps);
3293 LIMIT_CAPS(toecaps);
3294 LIMIT_CAPS(rdmacaps);
3295 LIMIT_CAPS(cryptocaps);
3296 LIMIT_CAPS(iscsicaps);
3297 LIMIT_CAPS(fcoecaps);
3300 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3301 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3302 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3303 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
3305 device_printf(sc->dev,
3306 "failed to process config file: %d.\n", rc);
3310 firmware_put(cfg, FIRMWARE_UNLOAD);
3315 * Retrieve parameters that are needed (or nice to have) very early.
3318 get_params__pre_init(struct adapter *sc)
3321 uint32_t param[2], val[2];
3323 t4_get_version_info(sc);
3325 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
3326 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
3327 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
3328 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
3329 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
3331 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
3332 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
3333 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
3334 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
3335 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
3337 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
3338 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
3339 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
3340 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
3341 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
3343 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
3344 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
3345 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
3346 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
3347 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
3349 param[0] = FW_PARAM_DEV(PORTVEC);
3350 param[1] = FW_PARAM_DEV(CCLK);
3351 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3353 device_printf(sc->dev,
3354 "failed to query parameters (pre_init): %d.\n", rc);
3358 sc->params.portvec = val[0];
3359 sc->params.nports = bitcount32(val[0]);
3360 sc->params.vpd.cclk = val[1];
3362 /* Read device log parameters. */
3363 rc = -t4_init_devlog_params(sc, 1);
3365 fixup_devlog_params(sc);
3367 device_printf(sc->dev,
3368 "failed to get devlog parameters: %d.\n", rc);
3369 rc = 0; /* devlog isn't critical for device operation */
3376 * Retrieve various parameters that are of interest to the driver. The device
3377 * has been initialized by the firmware at this point.
3380 get_params__post_init(struct adapter *sc)
3383 uint32_t param[7], val[7];
3384 struct fw_caps_config_cmd caps;
3386 param[0] = FW_PARAM_PFVF(IQFLINT_START);
3387 param[1] = FW_PARAM_PFVF(EQ_START);
3388 param[2] = FW_PARAM_PFVF(FILTER_START);
3389 param[3] = FW_PARAM_PFVF(FILTER_END);
3390 param[4] = FW_PARAM_PFVF(L2T_START);
3391 param[5] = FW_PARAM_PFVF(L2T_END);
3392 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3394 device_printf(sc->dev,
3395 "failed to query parameters (post_init): %d.\n", rc);
3399 sc->sge.iq_start = val[0];
3400 sc->sge.eq_start = val[1];
3401 sc->tids.ftid_base = val[2];
3402 sc->tids.nftids = val[3] - val[2] + 1;
3403 sc->params.ftid_min = val[2];
3404 sc->params.ftid_max = val[3];
3405 sc->vres.l2t.start = val[4];
3406 sc->vres.l2t.size = val[5] - val[4] + 1;
3407 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
3408 ("%s: L2 table size (%u) larger than expected (%u)",
3409 __func__, sc->vres.l2t.size, L2T_SIZE));
3411 /* get capabilites */
3412 bzero(&caps, sizeof(caps));
3413 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3414 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3415 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3416 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3418 device_printf(sc->dev,
3419 "failed to get card capabilities: %d.\n", rc);
3423 #define READ_CAPS(x) do { \
3424 sc->x = htobe16(caps.x); \
3427 READ_CAPS(linkcaps);
3428 READ_CAPS(switchcaps);
3431 READ_CAPS(rdmacaps);
3432 READ_CAPS(cryptocaps);
3433 READ_CAPS(iscsicaps);
3434 READ_CAPS(fcoecaps);
3436 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3437 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3438 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3439 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3440 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
3442 device_printf(sc->dev,
3443 "failed to query NIC parameters: %d.\n", rc);
3446 sc->tids.etid_base = val[0];
3447 sc->params.etid_min = val[0];
3448 sc->tids.netids = val[1] - val[0] + 1;
3449 sc->params.netids = sc->tids.netids;
3450 sc->params.eo_wr_cred = val[2];
3451 sc->params.ethoffload = 1;
3455 /* query offload-related parameters */
3456 param[0] = FW_PARAM_DEV(NTID);
3457 param[1] = FW_PARAM_PFVF(SERVER_START);
3458 param[2] = FW_PARAM_PFVF(SERVER_END);
3459 param[3] = FW_PARAM_PFVF(TDDP_START);
3460 param[4] = FW_PARAM_PFVF(TDDP_END);
3461 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3462 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3464 device_printf(sc->dev,
3465 "failed to query TOE parameters: %d.\n", rc);
3468 sc->tids.ntids = val[0];
3469 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
3470 sc->tids.stid_base = val[1];
3471 sc->tids.nstids = val[2] - val[1] + 1;
3472 sc->vres.ddp.start = val[3];
3473 sc->vres.ddp.size = val[4] - val[3] + 1;
3474 sc->params.ofldq_wr_cred = val[5];
3475 sc->params.offload = 1;
3478 param[0] = FW_PARAM_PFVF(STAG_START);
3479 param[1] = FW_PARAM_PFVF(STAG_END);
3480 param[2] = FW_PARAM_PFVF(RQ_START);
3481 param[3] = FW_PARAM_PFVF(RQ_END);
3482 param[4] = FW_PARAM_PFVF(PBL_START);
3483 param[5] = FW_PARAM_PFVF(PBL_END);
3484 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3486 device_printf(sc->dev,
3487 "failed to query RDMA parameters(1): %d.\n", rc);
3490 sc->vres.stag.start = val[0];
3491 sc->vres.stag.size = val[1] - val[0] + 1;
3492 sc->vres.rq.start = val[2];
3493 sc->vres.rq.size = val[3] - val[2] + 1;
3494 sc->vres.pbl.start = val[4];
3495 sc->vres.pbl.size = val[5] - val[4] + 1;
3497 param[0] = FW_PARAM_PFVF(SQRQ_START);
3498 param[1] = FW_PARAM_PFVF(SQRQ_END);
3499 param[2] = FW_PARAM_PFVF(CQ_START);
3500 param[3] = FW_PARAM_PFVF(CQ_END);
3501 param[4] = FW_PARAM_PFVF(OCQ_START);
3502 param[5] = FW_PARAM_PFVF(OCQ_END);
3503 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3505 device_printf(sc->dev,
3506 "failed to query RDMA parameters(2): %d.\n", rc);
3509 sc->vres.qp.start = val[0];
3510 sc->vres.qp.size = val[1] - val[0] + 1;
3511 sc->vres.cq.start = val[2];
3512 sc->vres.cq.size = val[3] - val[2] + 1;
3513 sc->vres.ocq.start = val[4];
3514 sc->vres.ocq.size = val[5] - val[4] + 1;
3516 param[0] = FW_PARAM_PFVF(SRQ_START);
3517 param[1] = FW_PARAM_PFVF(SRQ_END);
3518 param[2] = FW_PARAM_DEV(MAXORDIRD_QP);
3519 param[3] = FW_PARAM_DEV(MAXIRD_ADAPTER);
3520 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 4, param, val);
3522 device_printf(sc->dev,
3523 "failed to query RDMA parameters(3): %d.\n", rc);
3526 sc->vres.srq.start = val[0];
3527 sc->vres.srq.size = val[1] - val[0] + 1;
3528 sc->params.max_ordird_qp = val[2];
3529 sc->params.max_ird_adapter = val[3];
3531 if (sc->iscsicaps) {
3532 param[0] = FW_PARAM_PFVF(ISCSI_START);
3533 param[1] = FW_PARAM_PFVF(ISCSI_END);
3534 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3536 device_printf(sc->dev,
3537 "failed to query iSCSI parameters: %d.\n", rc);
3540 sc->vres.iscsi.start = val[0];
3541 sc->vres.iscsi.size = val[1] - val[0] + 1;
3544 t4_init_sge_params(sc);
3547 * We've got the params we wanted to query via the firmware. Now grab
3548 * some others directly from the chip.
3550 rc = t4_read_chip_settings(sc);
3556 set_params__post_init(struct adapter *sc)
3558 uint32_t param, val;
3560 /* ask for encapsulated CPLs */
3561 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3563 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3568 #undef FW_PARAM_PFVF
3572 t4_set_desc(struct adapter *sc)
3575 struct adapter_params *p = &sc->params;
3577 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
3579 device_set_desc_copy(sc->dev, buf);
3583 ifmedia_add4(struct ifmedia *ifm, int m)
3586 ifmedia_add(ifm, m, 0, NULL);
3587 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE, 0, NULL);
3588 ifmedia_add(ifm, m | IFM_ETH_RXPAUSE, 0, NULL);
3589 ifmedia_add(ifm, m | IFM_ETH_TXPAUSE | IFM_ETH_RXPAUSE, 0, NULL);
3593 set_current_media(struct port_info *pi, struct ifmedia *ifm)
3595 struct link_config *lc;
3598 PORT_LOCK_ASSERT_OWNED(pi);
3600 /* Leave current media alone if it's already set to IFM_NONE. */
3601 if (ifm->ifm_cur != NULL &&
3602 IFM_SUBTYPE(ifm->ifm_cur->ifm_media) == IFM_NONE)
3606 if (lc->requested_aneg == AUTONEG_ENABLE &&
3607 lc->supported & FW_PORT_CAP_ANEG) {
3608 ifmedia_set(ifm, IFM_ETHER | IFM_AUTO);
3611 mword = IFM_ETHER | IFM_FDX;
3612 if (lc->requested_fc & PAUSE_TX)
3613 mword |= IFM_ETH_TXPAUSE;
3614 if (lc->requested_fc & PAUSE_RX)
3615 mword |= IFM_ETH_RXPAUSE;
3616 mword |= port_mword(pi, speed_to_fwspeed(lc->requested_speed));
3617 ifmedia_set(ifm, mword);
3621 build_medialist(struct port_info *pi, struct ifmedia *ifm)
3624 int unknown, mword, bit;
3625 struct link_config *lc;
3627 PORT_LOCK_ASSERT_OWNED(pi);
3629 if (pi->flags & FIXED_IFMEDIA)
3633 * First setup all the requested_ fields so that they comply with what's
3634 * supported by the port + transceiver. Note that this clobbers any
3635 * user preferences set via sysctl_pause_settings or sysctl_autoneg.
3640 * Now (re)build the ifmedia list.
3642 ifmedia_removeall(ifm);
3644 ss = G_FW_PORT_CAP_SPEED(lc->supported); /* Supported Speeds */
3645 if (__predict_false(ss == 0)) { /* not supposed to happen. */
3648 MPASS(LIST_EMPTY(&ifm->ifm_list));
3649 ifmedia_add(ifm, IFM_ETHER | IFM_NONE, 0, NULL);
3650 ifmedia_set(ifm, IFM_ETHER | IFM_NONE);
3655 for (bit = 0; bit < fls(ss); bit++) {
3657 MPASS(speed & M_FW_PORT_CAP_SPEED);
3659 mword = port_mword(pi, speed);
3660 if (mword == IFM_NONE) {
3662 } else if (mword == IFM_UNKNOWN)
3665 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | mword);
3668 if (unknown > 0) /* Add one unknown for all unknown media types. */
3669 ifmedia_add4(ifm, IFM_ETHER | IFM_FDX | IFM_UNKNOWN);
3670 if (lc->supported & FW_PORT_CAP_ANEG)
3671 ifmedia_add(ifm, IFM_ETHER | IFM_AUTO, 0, NULL);
3673 set_current_media(pi, ifm);
3677 * Update all the requested_* fields in the link config to something valid (and
3681 init_l1cfg(struct port_info *pi)
3683 struct link_config *lc = &pi->link_cfg;
3685 PORT_LOCK_ASSERT_OWNED(pi);
3688 lc->requested_speed = port_top_speed(pi) * 1000;
3690 if (t4_autoneg != 0 && lc->supported & FW_PORT_CAP_ANEG) {
3691 lc->requested_aneg = AUTONEG_ENABLE;
3693 lc->requested_aneg = AUTONEG_DISABLE;
3696 lc->requested_fc = t4_pause_settings & (PAUSE_TX | PAUSE_RX);
3699 if (t4_fec & FEC_RS && lc->supported & FW_PORT_CAP_FEC_RS) {
3700 lc->requested_fec = FEC_RS;
3701 } else if (t4_fec & FEC_BASER_RS &&
3702 lc->supported & FW_PORT_CAP_FEC_BASER_RS) {
3703 lc->requested_fec = FEC_BASER_RS;
3705 lc->requested_fec = 0;
3708 /* Use the suggested value provided by the firmware in acaps */
3709 if (lc->advertising & FW_PORT_CAP_FEC_RS &&
3710 lc->supported & FW_PORT_CAP_FEC_RS) {
3711 lc->requested_fec = FEC_RS;
3712 } else if (lc->advertising & FW_PORT_CAP_FEC_BASER_RS &&
3713 lc->supported & FW_PORT_CAP_FEC_BASER_RS) {
3714 lc->requested_fec = FEC_BASER_RS;
3716 lc->requested_fec = 0;
3722 * Apply the settings in requested_* to the hardware. The parameters are
3723 * expected to be sane.
3726 apply_l1cfg(struct port_info *pi)
3728 struct adapter *sc = pi->adapter;
3729 struct link_config *lc = &pi->link_cfg;
3734 ASSERT_SYNCHRONIZED_OP(sc);
3735 PORT_LOCK_ASSERT_OWNED(pi);
3737 if (lc->requested_aneg == AUTONEG_ENABLE)
3738 MPASS(lc->supported & FW_PORT_CAP_ANEG);
3739 if (lc->requested_fc & PAUSE_TX)
3740 MPASS(lc->supported & FW_PORT_CAP_FC_TX);
3741 if (lc->requested_fc & PAUSE_RX)
3742 MPASS(lc->supported & FW_PORT_CAP_FC_RX);
3743 if (lc->requested_fec == FEC_RS)
3744 MPASS(lc->supported & FW_PORT_CAP_FEC_RS);
3745 if (lc->requested_fec == FEC_BASER_RS)
3746 MPASS(lc->supported & FW_PORT_CAP_FEC_BASER_RS);
3747 fwspeed = speed_to_fwspeed(lc->requested_speed);
3748 MPASS(fwspeed != 0);
3749 MPASS(lc->supported & fwspeed);
3751 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
3753 device_printf(pi->dev, "l1cfg failed: %d\n", rc);
3755 lc->fc = lc->requested_fc;
3756 lc->fec = lc->requested_fec;
3761 #define FW_MAC_EXACT_CHUNK 7
3764 * Program the port's XGMAC based on parameters in ifnet. The caller also
3765 * indicates which parameters should be programmed (the rest are left alone).
3768 update_mac_settings(struct ifnet *ifp, int flags)
3771 struct vi_info *vi = ifp->if_softc;
3772 struct port_info *pi = vi->pi;
3773 struct adapter *sc = pi->adapter;
3774 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
3776 ASSERT_SYNCHRONIZED_OP(sc);
3777 KASSERT(flags, ("%s: not told what to update.", __func__));
3779 if (flags & XGMAC_MTU)
3782 if (flags & XGMAC_PROMISC)
3783 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
3785 if (flags & XGMAC_ALLMULTI)
3786 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
3788 if (flags & XGMAC_VLANEX)
3789 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
3791 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
3792 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
3793 allmulti, 1, vlanex, false);
3795 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
3801 if (flags & XGMAC_UCADDR) {
3802 uint8_t ucaddr[ETHER_ADDR_LEN];
3804 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
3805 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
3806 ucaddr, true, true);
3809 if_printf(ifp, "change_mac failed: %d\n", rc);
3812 vi->xact_addr_filt = rc;
3817 if (flags & XGMAC_MCADDRS) {
3818 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
3821 struct ifmultiaddr *ifma;
3824 if_maddr_rlock(ifp);
3825 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3826 if (ifma->ifma_addr->sa_family != AF_LINK)
3829 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
3830 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
3833 if (i == FW_MAC_EXACT_CHUNK) {
3834 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
3835 del, i, mcaddr, NULL, &hash, 0);
3838 for (j = 0; j < i; j++) {
3840 "failed to add mc address"
3842 "%02x:%02x:%02x rc=%d\n",
3843 mcaddr[j][0], mcaddr[j][1],
3844 mcaddr[j][2], mcaddr[j][3],
3845 mcaddr[j][4], mcaddr[j][5],
3855 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
3856 mcaddr, NULL, &hash, 0);
3859 for (j = 0; j < i; j++) {
3861 "failed to add mc address"
3863 "%02x:%02x:%02x rc=%d\n",
3864 mcaddr[j][0], mcaddr[j][1],
3865 mcaddr[j][2], mcaddr[j][3],
3866 mcaddr[j][4], mcaddr[j][5],
3873 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
3875 if_printf(ifp, "failed to set mc address hash: %d", rc);
3877 if_maddr_runlock(ifp);
3884 * {begin|end}_synchronized_op must be called from the same thread.
3887 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
3893 /* the caller thinks it's ok to sleep, but is it really? */
3894 if (flags & SLEEP_OK)
3895 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
3896 "begin_synchronized_op");
3907 if (vi && IS_DOOMED(vi)) {
3917 if (!(flags & SLEEP_OK)) {
3922 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
3928 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
3931 sc->last_op = wmesg;
3932 sc->last_op_thr = curthread;
3933 sc->last_op_flags = flags;
3937 if (!(flags & HOLD_LOCK) || rc)
3944 * Tell if_ioctl and if_init that the VI is going away. This is
3945 * special variant of begin_synchronized_op and must be paired with a
3946 * call to end_synchronized_op.
3949 doom_vi(struct adapter *sc, struct vi_info *vi)
3956 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
3959 sc->last_op = "t4detach";
3960 sc->last_op_thr = curthread;
3961 sc->last_op_flags = 0;
3967 * {begin|end}_synchronized_op must be called from the same thread.
3970 end_synchronized_op(struct adapter *sc, int flags)
3973 if (flags & LOCK_HELD)
3974 ADAPTER_LOCK_ASSERT_OWNED(sc);
3978 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
3985 cxgbe_init_synchronized(struct vi_info *vi)
3987 struct port_info *pi = vi->pi;
3988 struct adapter *sc = pi->adapter;
3989 struct ifnet *ifp = vi->ifp;
3991 struct sge_txq *txq;
3993 ASSERT_SYNCHRONIZED_OP(sc);
3995 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3996 return (0); /* already running */
3998 if (!(sc->flags & FULL_INIT_DONE) &&
3999 ((rc = adapter_full_init(sc)) != 0))
4000 return (rc); /* error message displayed already */
4002 if (!(vi->flags & VI_INIT_DONE) &&
4003 ((rc = vi_full_init(vi)) != 0))
4004 return (rc); /* error message displayed already */
4006 rc = update_mac_settings(ifp, XGMAC_ALL);
4008 goto done; /* error message displayed already */
4010 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
4012 if_printf(ifp, "enable_vi failed: %d\n", rc);
4017 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
4021 for_each_txq(vi, i, txq) {
4023 txq->eq.flags |= EQ_ENABLED;
4028 * The first iq of the first port to come up is used for tracing.
4030 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
4031 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
4032 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
4033 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
4034 V_QUEUENUMBER(sc->traceq));
4035 pi->flags |= HAS_TRACEQ;
4040 if (pi->up_vis++ == 0) {
4041 t4_update_port_info(pi);
4042 build_medialist(pi, &pi->media);
4045 ifp->if_drv_flags |= IFF_DRV_RUNNING;
4047 if (pi->nvi > 1 || sc->flags & IS_VF)
4048 callout_reset(&vi->tick, hz, vi_tick, vi);
4050 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
4054 cxgbe_uninit_synchronized(vi);
4063 cxgbe_uninit_synchronized(struct vi_info *vi)
4065 struct port_info *pi = vi->pi;
4066 struct adapter *sc = pi->adapter;
4067 struct ifnet *ifp = vi->ifp;
4069 struct sge_txq *txq;
4071 ASSERT_SYNCHRONIZED_OP(sc);
4073 if (!(vi->flags & VI_INIT_DONE)) {
4074 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING),
4075 ("uninited VI is running"));
4080 * Disable the VI so that all its data in either direction is discarded
4081 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
4082 * tick) intact as the TP can deliver negative advice or data that it's
4083 * holding in its RAM (for an offloaded connection) even after the VI is
4086 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
4088 if_printf(ifp, "disable_vi failed: %d\n", rc);
4092 for_each_txq(vi, i, txq) {
4094 txq->eq.flags &= ~EQ_ENABLED;
4099 if (pi->nvi > 1 || sc->flags & IS_VF)
4100 callout_stop(&vi->tick);
4102 callout_stop(&pi->tick);
4103 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4107 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
4109 if (pi->up_vis > 0) {
4114 pi->link_cfg.link_ok = 0;
4115 pi->link_cfg.speed = 0;
4116 pi->link_cfg.link_down_rc = 255;
4117 t4_os_link_changed(pi);
4118 pi->old_link_cfg = pi->link_cfg;
4125 * It is ok for this function to fail midway and return right away. t4_detach
4126 * will walk the entire sc->irq list and clean up whatever is valid.
4129 t4_setup_intr_handlers(struct adapter *sc)
4131 int rc, rid, p, q, v;
4134 struct port_info *pi;
4136 struct sge *sge = &sc->sge;
4137 struct sge_rxq *rxq;
4139 struct sge_ofld_rxq *ofld_rxq;
4142 struct sge_nm_rxq *nm_rxq;
4149 rid = sc->intr_type == INTR_INTX ? 0 : 1;
4150 if (sc->intr_count == 1)
4151 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
4153 /* Multiple interrupts. */
4154 if (sc->flags & IS_VF)
4155 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
4156 ("%s: too few intr.", __func__));
4158 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
4159 ("%s: too few intr.", __func__));
4161 /* The first one is always error intr on PFs */
4162 if (!(sc->flags & IS_VF)) {
4163 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
4170 /* The second one is always the firmware event queue (first on VFs) */
4171 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
4177 for_each_port(sc, p) {
4179 for_each_vi(pi, v, vi) {
4180 vi->first_intr = rid - 1;
4182 if (vi->nnmrxq > 0) {
4183 int n = max(vi->nrxq, vi->nnmrxq);
4185 MPASS(vi->flags & INTR_RXQ);
4187 rxq = &sge->rxq[vi->first_rxq];
4189 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
4191 for (q = 0; q < n; q++) {
4192 snprintf(s, sizeof(s), "%x%c%x", p,
4198 irq->nm_rxq = nm_rxq++;
4200 rc = t4_alloc_irq(sc, irq, rid,
4201 t4_vi_intr, irq, s);
4208 } else if (vi->flags & INTR_RXQ) {
4209 for_each_rxq(vi, q, rxq) {
4210 snprintf(s, sizeof(s), "%x%c%x", p,
4212 rc = t4_alloc_irq(sc, irq, rid,
4222 if (vi->flags & INTR_OFLD_RXQ) {
4223 for_each_ofld_rxq(vi, q, ofld_rxq) {
4224 snprintf(s, sizeof(s), "%x%c%x", p,
4226 rc = t4_alloc_irq(sc, irq, rid,
4227 t4_intr, ofld_rxq, s);
4238 MPASS(irq == &sc->irq[sc->intr_count]);
4244 adapter_full_init(struct adapter *sc)
4248 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4249 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4252 ASSERT_SYNCHRONIZED_OP(sc);
4253 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4254 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
4255 ("%s: FULL_INIT_DONE already", __func__));
4258 * queues that belong to the adapter (not any particular port).
4260 rc = t4_setup_adapter_queues(sc);
4264 for (i = 0; i < nitems(sc->tq); i++) {
4265 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
4266 taskqueue_thread_enqueue, &sc->tq[i]);
4267 if (sc->tq[i] == NULL) {
4268 device_printf(sc->dev,
4269 "failed to allocate task queue %d\n", i);
4273 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
4274 device_get_nameunit(sc->dev), i);
4277 MPASS(RSS_KEYSIZE == 40);
4278 rss_getkey((void *)&raw_rss_key[0]);
4279 for (i = 0; i < nitems(rss_key); i++) {
4280 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
4282 t4_write_rss_key(sc, &rss_key[0], -1, 1);
4285 if (!(sc->flags & IS_VF))
4287 sc->flags |= FULL_INIT_DONE;
4290 adapter_full_uninit(sc);
4296 adapter_full_uninit(struct adapter *sc)
4300 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4302 t4_teardown_adapter_queues(sc);
4304 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
4305 taskqueue_free(sc->tq[i]);
4309 sc->flags &= ~FULL_INIT_DONE;
4315 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
4316 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
4317 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
4318 RSS_HASHTYPE_RSS_UDP_IPV6)
4320 /* Translates kernel hash types to hardware. */
4322 hashconfig_to_hashen(int hashconfig)
4326 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
4327 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
4328 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
4329 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
4330 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
4331 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4332 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4334 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
4335 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4336 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4338 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
4339 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4340 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
4341 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4346 /* Translates hardware hash types to kernel. */
4348 hashen_to_hashconfig(int hashen)
4352 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
4354 * If UDP hashing was enabled it must have been enabled for
4355 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
4356 * enabling any 4-tuple hash is nonsense configuration.
4358 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4359 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
4361 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4362 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
4363 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4364 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
4366 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4367 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
4368 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4369 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
4370 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
4371 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
4372 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
4373 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
4375 return (hashconfig);
4380 vi_full_init(struct vi_info *vi)
4382 struct adapter *sc = vi->pi->adapter;
4383 struct ifnet *ifp = vi->ifp;
4385 struct sge_rxq *rxq;
4386 int rc, i, j, hashen;
4388 int nbuckets = rss_getnumbuckets();
4389 int hashconfig = rss_gethashconfig();
4393 ASSERT_SYNCHRONIZED_OP(sc);
4394 KASSERT((vi->flags & VI_INIT_DONE) == 0,
4395 ("%s: VI_INIT_DONE already", __func__));
4397 sysctl_ctx_init(&vi->ctx);
4398 vi->flags |= VI_SYSCTL_CTX;
4401 * Allocate tx/rx/fl queues for this VI.
4403 rc = t4_setup_vi_queues(vi);
4405 goto done; /* error message displayed already */
4408 * Setup RSS for this VI. Save a copy of the RSS table for later use.
4410 if (vi->nrxq > vi->rss_size) {
4411 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
4412 "some queues will never receive traffic.\n", vi->nrxq,
4414 } else if (vi->rss_size % vi->nrxq) {
4415 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
4416 "expect uneven traffic distribution.\n", vi->nrxq,
4420 if (vi->nrxq != nbuckets) {
4421 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
4422 "performance will be impacted.\n", vi->nrxq, nbuckets);
4425 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
4426 for (i = 0; i < vi->rss_size;) {
4428 j = rss_get_indirection_to_bucket(i);
4430 rxq = &sc->sge.rxq[vi->first_rxq + j];
4431 rss[i++] = rxq->iq.abs_id;
4433 for_each_rxq(vi, j, rxq) {
4434 rss[i++] = rxq->iq.abs_id;
4435 if (i == vi->rss_size)
4441 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
4444 if_printf(ifp, "rss_config failed: %d\n", rc);
4449 hashen = hashconfig_to_hashen(hashconfig);
4452 * We may have had to enable some hashes even though the global config
4453 * wants them disabled. This is a potential problem that must be
4454 * reported to the user.
4456 extra = hashen_to_hashconfig(hashen) ^ hashconfig;
4459 * If we consider only the supported hash types, then the enabled hashes
4460 * are a superset of the requested hashes. In other words, there cannot
4461 * be any supported hash that was requested but not enabled, but there
4462 * can be hashes that were not requested but had to be enabled.
4464 extra &= SUPPORTED_RSS_HASHTYPES;
4465 MPASS((extra & hashconfig) == 0);
4469 "global RSS config (0x%x) cannot be accomodated.\n",
4472 if (extra & RSS_HASHTYPE_RSS_IPV4)
4473 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
4474 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
4475 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
4476 if (extra & RSS_HASHTYPE_RSS_IPV6)
4477 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
4478 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
4479 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
4480 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
4481 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
4482 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
4483 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
4485 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
4486 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
4487 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4488 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
4490 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0);
4492 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
4497 vi->flags |= VI_INIT_DONE;
4509 vi_full_uninit(struct vi_info *vi)
4511 struct port_info *pi = vi->pi;
4512 struct adapter *sc = pi->adapter;
4514 struct sge_rxq *rxq;
4515 struct sge_txq *txq;
4517 struct sge_ofld_rxq *ofld_rxq;
4518 struct sge_wrq *ofld_txq;
4521 if (vi->flags & VI_INIT_DONE) {
4523 /* Need to quiesce queues. */
4525 /* XXX: Only for the first VI? */
4526 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
4527 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
4529 for_each_txq(vi, i, txq) {
4530 quiesce_txq(sc, txq);
4534 for_each_ofld_txq(vi, i, ofld_txq) {
4535 quiesce_wrq(sc, ofld_txq);
4539 for_each_rxq(vi, i, rxq) {
4540 quiesce_iq(sc, &rxq->iq);
4541 quiesce_fl(sc, &rxq->fl);
4545 for_each_ofld_rxq(vi, i, ofld_rxq) {
4546 quiesce_iq(sc, &ofld_rxq->iq);
4547 quiesce_fl(sc, &ofld_rxq->fl);
4550 free(vi->rss, M_CXGBE);
4551 free(vi->nm_rss, M_CXGBE);
4554 t4_teardown_vi_queues(vi);
4555 vi->flags &= ~VI_INIT_DONE;
4561 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
4563 struct sge_eq *eq = &txq->eq;
4564 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4566 (void) sc; /* unused */
4570 MPASS((eq->flags & EQ_ENABLED) == 0);
4574 /* Wait for the mp_ring to empty. */
4575 while (!mp_ring_is_idle(txq->r)) {
4576 mp_ring_check_drainage(txq->r, 0);
4577 pause("rquiesce", 1);
4580 /* Then wait for the hardware to finish. */
4581 while (spg->cidx != htobe16(eq->pidx))
4582 pause("equiesce", 1);
4584 /* Finally, wait for the driver to reclaim all descriptors. */
4585 while (eq->cidx != eq->pidx)
4586 pause("dquiesce", 1);
4590 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
4597 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
4599 (void) sc; /* unused */
4601 /* Synchronize with the interrupt handler */
4602 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
4607 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
4609 mtx_lock(&sc->sfl_lock);
4611 fl->flags |= FL_DOOMED;
4613 callout_stop(&sc->sfl_callout);
4614 mtx_unlock(&sc->sfl_lock);
4616 KASSERT((fl->flags & FL_STARVING) == 0,
4617 ("%s: still starving", __func__));
4621 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
4622 driver_intr_t *handler, void *arg, char *name)
4627 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
4628 RF_SHAREABLE | RF_ACTIVE);
4629 if (irq->res == NULL) {
4630 device_printf(sc->dev,
4631 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
4635 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
4636 NULL, handler, arg, &irq->tag);
4638 device_printf(sc->dev,
4639 "failed to setup interrupt for rid %d, name %s: %d\n",
4642 bus_describe_intr(sc->dev, irq->res, irq->tag, name);
4648 t4_free_irq(struct adapter *sc, struct irq *irq)
4651 bus_teardown_intr(sc->dev, irq->res, irq->tag);
4653 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
4655 bzero(irq, sizeof(*irq));
4661 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
4664 regs->version = chip_id(sc) | chip_rev(sc) << 10;
4665 t4_get_regs(sc, buf, regs->len);
4668 #define A_PL_INDIR_CMD 0x1f8
4670 #define S_PL_AUTOINC 31
4671 #define M_PL_AUTOINC 0x1U
4672 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
4673 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
4675 #define S_PL_VFID 20
4676 #define M_PL_VFID 0xffU
4677 #define V_PL_VFID(x) ((x) << S_PL_VFID)
4678 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
4681 #define M_PL_ADDR 0xfffffU
4682 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
4683 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
4685 #define A_PL_INDIR_DATA 0x1fc
4688 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
4692 mtx_assert(&sc->reg_lock, MA_OWNED);
4693 if (sc->flags & IS_VF) {
4694 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
4695 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
4697 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4698 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4699 V_PL_ADDR(VF_MPS_REG(reg)));
4700 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
4701 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
4703 return (((uint64_t)stats[1]) << 32 | stats[0]);
4707 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
4708 struct fw_vi_stats_vf *stats)
4711 #define GET_STAT(name) \
4712 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
4714 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
4715 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
4716 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
4717 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
4718 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
4719 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
4720 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
4721 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
4722 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
4723 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
4724 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
4725 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
4726 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
4727 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
4728 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
4729 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
4735 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
4739 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4740 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4741 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
4742 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
4743 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
4744 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
4748 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
4750 struct ifnet *ifp = vi->ifp;
4751 struct sge_txq *txq;
4753 struct fw_vi_stats_vf *s = &vi->stats;
4755 const struct timeval interval = {0, 250000}; /* 250ms */
4757 if (!(vi->flags & VI_INIT_DONE))
4761 timevalsub(&tv, &interval);
4762 if (timevalcmp(&tv, &vi->last_refreshed, <))
4765 mtx_lock(&sc->reg_lock);
4766 t4_get_vi_stats(sc, vi->viid, &vi->stats);
4768 ifp->if_ipackets = s->rx_bcast_frames + s->rx_mcast_frames +
4770 ifp->if_ierrors = s->rx_err_frames;
4771 ifp->if_opackets = s->tx_bcast_frames + s->tx_mcast_frames +
4772 s->tx_ucast_frames + s->tx_offload_frames;
4773 ifp->if_oerrors = s->tx_drop_frames;
4774 ifp->if_ibytes = s->rx_bcast_bytes + s->rx_mcast_bytes +
4776 ifp->if_obytes = s->tx_bcast_bytes + s->tx_mcast_bytes +
4777 s->tx_ucast_bytes + s->tx_offload_bytes;
4778 ifp->if_imcasts = s->rx_mcast_frames;
4779 ifp->if_omcasts = s->tx_mcast_frames;
4782 for_each_txq(vi, i, txq)
4783 drops += counter_u64_fetch(txq->r->drops);
4784 ifp->if_snd.ifq_drops = drops;
4786 getmicrotime(&vi->last_refreshed);
4787 mtx_unlock(&sc->reg_lock);
4791 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
4793 struct vi_info *vi = &pi->vi[0];
4794 struct ifnet *ifp = vi->ifp;
4795 struct sge_txq *txq;
4797 struct port_stats *s = &pi->stats;
4799 const struct timeval interval = {0, 250000}; /* 250ms */
4802 timevalsub(&tv, &interval);
4803 if (timevalcmp(&tv, &pi->last_refreshed, <))
4806 t4_get_port_stats(sc, pi->tx_chan, s);
4808 ifp->if_opackets = s->tx_frames;
4809 ifp->if_ipackets = s->rx_frames;
4810 ifp->if_obytes = s->tx_octets;
4811 ifp->if_ibytes = s->rx_octets;
4812 ifp->if_omcasts = s->tx_mcast_frames;
4813 ifp->if_imcasts = s->rx_mcast_frames;
4814 ifp->if_iqdrops = s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
4815 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
4817 for (i = 0; i < sc->chip_params->nchan; i++) {
4818 if (pi->rx_chan_map & (1 << i)) {
4821 mtx_lock(&sc->reg_lock);
4822 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
4823 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
4824 mtx_unlock(&sc->reg_lock);
4825 ifp->if_iqdrops += v;
4830 for_each_txq(vi, i, txq)
4831 drops += counter_u64_fetch(txq->r->drops);
4832 ifp->if_snd.ifq_drops = drops;
4834 ifp->if_oerrors = s->tx_error_frames;
4835 ifp->if_ierrors = s->rx_jabber + s->rx_runt + s->rx_too_long +
4836 s->rx_fcs_err + s->rx_len_err;
4838 getmicrotime(&pi->last_refreshed);
4842 cxgbe_tick(void *arg)
4844 struct port_info *pi = arg;
4845 struct adapter *sc = pi->adapter;
4847 PORT_LOCK_ASSERT_OWNED(pi);
4848 cxgbe_refresh_stats(sc, pi);
4850 callout_schedule(&pi->tick, hz);
4856 struct vi_info *vi = arg;
4857 struct adapter *sc = vi->pi->adapter;
4859 vi_refresh_stats(sc, vi);
4861 callout_schedule(&vi->tick, hz);
4865 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
4869 if (arg != ifp || ifp->if_type != IFT_ETHER)
4872 vlan = VLAN_DEVAT(ifp, vid);
4873 VLAN_SETCOOKIE(vlan, ifp);
4877 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
4879 static char *caps_decoder[] = {
4880 "\20\001IPMI\002NCSI", /* 0: NBM */
4881 "\20\001PPP\002QFC\003DCBX", /* 1: link */
4882 "\20\001INGRESS\002EGRESS", /* 2: switch */
4883 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
4884 "\006HASHFILTER\007ETHOFLD",
4885 "\20\001TOE", /* 4: TOE */
4886 "\20\001RDDP\002RDMAC", /* 5: RDMA */
4887 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
4888 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
4889 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
4891 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
4892 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */
4893 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
4894 "\004PO_INITIATOR\005PO_TARGET",
4898 t4_sysctls(struct adapter *sc)
4900 struct sysctl_ctx_list *ctx;
4901 struct sysctl_oid *oid;
4902 struct sysctl_oid_list *children, *c0;
4903 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
4905 ctx = device_get_sysctl_ctx(sc->dev);
4910 oid = device_get_sysctl_tree(sc->dev);
4911 c0 = children = SYSCTL_CHILDREN(oid);
4913 sc->sc_do_rxcopy = 1;
4914 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
4915 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
4917 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
4918 sc->params.nports, "# of ports");
4920 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
4921 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells,
4922 sysctl_bitfield, "A", "available doorbells");
4924 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
4925 sc->params.vpd.cclk, "core clock frequency (in KHz)");
4927 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
4928 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
4929 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
4930 "interrupt holdoff timer values (us)");
4932 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
4933 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
4934 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
4935 "interrupt holdoff packet counter values");
4937 t4_sge_sysctls(sc, ctx, children);
4939 sc->lro_timeout = 100;
4940 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
4941 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
4943 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
4944 &sc->debug_flags, 0, "flags to enable runtime debugging");
4946 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
4947 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
4949 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
4950 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
4952 if (sc->flags & IS_VF)
4955 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
4956 NULL, chip_rev(sc), "chip hardware revision");
4958 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
4959 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
4961 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
4962 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
4964 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
4965 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
4967 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
4968 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
4970 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
4971 sc->er_version, 0, "expansion ROM version");
4973 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
4974 sc->bs_version, 0, "bootstrap firmware version");
4976 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
4977 NULL, sc->params.scfg_vers, "serial config version");
4979 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
4980 NULL, sc->params.vpd_vers, "VPD version");
4982 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
4983 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
4985 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
4986 sc->cfcsum, "config file checksum");
4988 #define SYSCTL_CAP(name, n, text) \
4989 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
4990 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \
4991 sysctl_bitfield, "A", "available " text " capabilities")
4993 SYSCTL_CAP(nbmcaps, 0, "NBM");
4994 SYSCTL_CAP(linkcaps, 1, "link");
4995 SYSCTL_CAP(switchcaps, 2, "switch");
4996 SYSCTL_CAP(niccaps, 3, "NIC");
4997 SYSCTL_CAP(toecaps, 4, "TCP offload");
4998 SYSCTL_CAP(rdmacaps, 5, "RDMA");
4999 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
5000 SYSCTL_CAP(cryptocaps, 7, "crypto");
5001 SYSCTL_CAP(fcoecaps, 8, "FCoE");
5004 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
5005 NULL, sc->tids.nftids, "number of filters");
5007 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
5008 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
5009 "chip temperature (in Celsius)");
5013 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
5015 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
5016 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
5017 "logs and miscellaneous information");
5018 children = SYSCTL_CHILDREN(oid);
5020 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
5021 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5022 sysctl_cctrl, "A", "congestion control");
5024 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
5025 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5026 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
5028 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
5029 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
5030 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
5032 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
5033 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
5034 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
5036 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
5037 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
5038 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
5040 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
5041 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
5042 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
5044 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
5045 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
5046 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
5048 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
5049 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5050 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
5051 "A", "CIM logic analyzer");
5053 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
5054 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5055 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
5057 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
5058 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
5059 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
5061 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
5062 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
5063 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
5065 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
5066 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
5067 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
5069 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
5070 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
5071 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
5073 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
5074 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
5075 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
5077 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
5078 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
5079 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
5081 if (chip_id(sc) > CHELSIO_T4) {
5082 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
5083 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
5084 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
5086 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
5087 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
5088 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
5091 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
5092 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5093 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
5095 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
5096 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5097 sysctl_cim_qcfg, "A", "CIM queue configuration");
5099 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
5100 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5101 sysctl_cpl_stats, "A", "CPL statistics");
5103 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
5104 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5105 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
5107 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
5108 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5109 sysctl_devlog, "A", "firmware's device log");
5111 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
5112 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5113 sysctl_fcoe_stats, "A", "FCoE statistics");
5115 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
5116 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5117 sysctl_hw_sched, "A", "hardware scheduler ");
5119 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
5120 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5121 sysctl_l2t, "A", "hardware L2 table");
5123 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
5124 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5125 sysctl_lb_stats, "A", "loopback statistics");
5127 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
5128 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5129 sysctl_meminfo, "A", "memory regions");
5131 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
5132 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5133 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
5134 "A", "MPS TCAM entries");
5136 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
5137 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5138 sysctl_path_mtus, "A", "path MTUs");
5140 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
5141 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5142 sysctl_pm_stats, "A", "PM statistics");
5144 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
5145 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5146 sysctl_rdma_stats, "A", "RDMA statistics");
5148 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
5149 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5150 sysctl_tcp_stats, "A", "TCP statistics");
5152 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
5153 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5154 sysctl_tids, "A", "TID information");
5156 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
5157 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5158 sysctl_tp_err_stats, "A", "TP error statistics");
5160 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
5161 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
5162 "TP logic analyzer event capture mask");
5164 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
5165 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5166 sysctl_tp_la, "A", "TP logic analyzer");
5168 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
5169 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5170 sysctl_tx_rate, "A", "Tx rate");
5172 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
5173 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5174 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
5176 if (chip_id(sc) >= CHELSIO_T5) {
5177 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
5178 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
5179 sysctl_wcwr_stats, "A", "write combined work requests");
5184 if (is_offload(sc)) {
5188 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
5189 NULL, "TOE parameters");
5190 children = SYSCTL_CHILDREN(oid);
5192 sc->tt.sndbuf = 256 * 1024;
5193 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
5194 &sc->tt.sndbuf, 0, "max hardware send buffer size");
5197 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
5198 &sc->tt.ddp, 0, "DDP allowed");
5200 sc->tt.indsz = G_INDICATESIZE(t4_read_reg(sc, A_TP_PARA_REG5));
5201 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "indsz", CTLFLAG_RW,
5202 &sc->tt.indsz, 0, "DDP max indicate size allowed");
5205 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2));
5206 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp_thres", CTLFLAG_RW,
5207 &sc->tt.ddp_thres, 0, "DDP threshold");
5209 sc->tt.rx_coalesce = 1;
5210 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
5211 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
5213 sc->tt.tx_align = 1;
5214 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
5215 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
5217 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
5218 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
5219 "TP timer tick (us)");
5221 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
5222 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
5223 "TCP timestamp tick (us)");
5225 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
5226 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
5229 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
5230 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
5231 "IU", "DACK timer (us)");
5233 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
5234 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
5235 sysctl_tp_timer, "LU", "Retransmit min (us)");
5237 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
5238 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
5239 sysctl_tp_timer, "LU", "Retransmit max (us)");
5241 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
5242 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
5243 sysctl_tp_timer, "LU", "Persist timer min (us)");
5245 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
5246 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
5247 sysctl_tp_timer, "LU", "Persist timer max (us)");
5249 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
5250 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
5251 sysctl_tp_timer, "LU", "Keepidle idle timer (us)");
5253 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_intvl",
5254 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
5255 sysctl_tp_timer, "LU", "Keepidle interval (us)");
5257 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
5258 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
5259 sysctl_tp_timer, "LU", "Initial SRTT (us)");
5261 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
5262 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
5263 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
5269 vi_sysctls(struct vi_info *vi)
5271 struct sysctl_ctx_list *ctx;
5272 struct sysctl_oid *oid;
5273 struct sysctl_oid_list *children;
5275 ctx = device_get_sysctl_ctx(vi->dev);
5278 * dev.v?(cxgbe|cxl).X.
5280 oid = device_get_sysctl_tree(vi->dev);
5281 children = SYSCTL_CHILDREN(oid);
5283 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
5284 vi->viid, "VI identifer");
5285 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
5286 &vi->nrxq, 0, "# of rx queues");
5287 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
5288 &vi->ntxq, 0, "# of tx queues");
5289 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
5290 &vi->first_rxq, 0, "index of first rx queue");
5291 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
5292 &vi->first_txq, 0, "index of first tx queue");
5293 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
5294 vi->rss_size, "size of RSS indirection table");
5296 if (IS_MAIN_VI(vi)) {
5297 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
5298 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
5299 "Reserve queue 0 for non-flowid packets");
5303 if (vi->nofldrxq != 0) {
5304 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
5306 "# of rx queues for offloaded TCP connections");
5307 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
5309 "# of tx queues for offloaded TCP connections");
5310 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
5311 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
5312 "index of first TOE rx queue");
5313 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
5314 CTLFLAG_RD, &vi->first_ofld_txq, 0,
5315 "index of first TOE tx queue");
5319 if (vi->nnmrxq != 0) {
5320 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
5321 &vi->nnmrxq, 0, "# of netmap rx queues");
5322 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
5323 &vi->nnmtxq, 0, "# of netmap tx queues");
5324 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
5325 CTLFLAG_RD, &vi->first_nm_rxq, 0,
5326 "index of first netmap rx queue");
5327 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
5328 CTLFLAG_RD, &vi->first_nm_txq, 0,
5329 "index of first netmap tx queue");
5333 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
5334 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
5335 "holdoff timer index");
5336 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
5337 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
5338 "holdoff packet counter index");
5340 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
5341 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
5343 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
5344 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
5349 cxgbe_sysctls(struct port_info *pi)
5351 struct sysctl_ctx_list *ctx;
5352 struct sysctl_oid *oid;
5353 struct sysctl_oid_list *children, *children2;
5354 struct adapter *sc = pi->adapter;
5358 ctx = device_get_sysctl_ctx(pi->dev);
5363 oid = device_get_sysctl_tree(pi->dev);
5364 children = SYSCTL_CHILDREN(oid);
5366 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
5367 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
5368 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
5369 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
5370 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
5371 "PHY temperature (in Celsius)");
5372 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
5373 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
5374 "PHY firmware version");
5377 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
5378 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A",
5379 "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)");
5380 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec",
5381 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A",
5382 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
5383 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
5384 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I",
5385 "autonegotiation (-1 = not supported)");
5387 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
5388 port_top_speed(pi), "max speed (in Gbps)");
5390 if (sc->flags & IS_VF)
5394 * dev.(cxgbe|cxl).X.tc.
5396 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
5397 "Tx scheduler traffic classes (cl_rl)");
5398 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
5399 struct tx_cl_rl_params *tc = &pi->sched_params->cl_rl[i];
5401 snprintf(name, sizeof(name), "%d", i);
5402 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
5403 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
5405 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD,
5406 &tc->flags, 0, "flags");
5407 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
5408 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
5410 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
5411 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
5412 sysctl_tc_params, "A", "traffic class parameters");
5417 * dev.cxgbe.X.stats.
5419 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
5420 NULL, "port statistics");
5421 children = SYSCTL_CHILDREN(oid);
5422 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
5423 &pi->tx_parse_error, 0,
5424 "# of tx packets with invalid length or # of segments");
5426 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
5427 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
5428 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
5429 sysctl_handle_t4_reg64, "QU", desc)
5431 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
5432 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
5433 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
5434 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
5435 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
5436 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
5437 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
5438 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
5439 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
5440 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
5441 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
5442 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
5443 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
5444 "# of tx frames in this range",
5445 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
5446 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
5447 "# of tx frames in this range",
5448 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
5449 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
5450 "# of tx frames in this range",
5451 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
5452 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
5453 "# of tx frames in this range",
5454 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
5455 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
5456 "# of tx frames in this range",
5457 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
5458 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
5459 "# of tx frames in this range",
5460 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
5461 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
5462 "# of tx frames in this range",
5463 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
5464 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
5465 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
5466 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
5467 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
5468 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
5469 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
5470 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
5471 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
5472 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
5473 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
5474 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
5475 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
5476 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
5477 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
5478 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
5479 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
5480 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
5481 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
5482 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
5483 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
5485 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
5486 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
5487 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
5488 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
5489 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
5490 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
5491 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
5492 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
5493 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
5494 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
5495 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
5496 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
5497 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
5498 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
5499 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
5500 "# of frames received with bad FCS",
5501 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
5502 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
5503 "# of frames received with length error",
5504 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
5505 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
5506 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
5507 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
5508 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
5509 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
5510 "# of rx frames in this range",
5511 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
5512 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
5513 "# of rx frames in this range",
5514 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
5515 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
5516 "# of rx frames in this range",
5517 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
5518 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
5519 "# of rx frames in this range",
5520 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
5521 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
5522 "# of rx frames in this range",
5523 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
5524 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
5525 "# of rx frames in this range",
5526 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
5527 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
5528 "# of rx frames in this range",
5529 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
5530 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
5531 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
5532 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
5533 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
5534 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
5535 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
5536 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
5537 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
5538 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
5539 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
5540 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
5541 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
5542 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
5543 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
5544 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
5545 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
5546 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
5547 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
5549 #undef SYSCTL_ADD_T4_REG64
5551 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
5552 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
5553 &pi->stats.name, desc)
5555 /* We get these from port_stats and they may be stale by upto 1s */
5556 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
5557 "# drops due to buffer-group 0 overflows");
5558 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
5559 "# drops due to buffer-group 1 overflows");
5560 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
5561 "# drops due to buffer-group 2 overflows");
5562 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
5563 "# drops due to buffer-group 3 overflows");
5564 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
5565 "# of buffer-group 0 truncated packets");
5566 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
5567 "# of buffer-group 1 truncated packets");
5568 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
5569 "# of buffer-group 2 truncated packets");
5570 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
5571 "# of buffer-group 3 truncated packets");
5573 #undef SYSCTL_ADD_T4_PORTSTAT
5577 sysctl_int_array(SYSCTL_HANDLER_ARGS)
5579 int rc, *i, space = 0;
5582 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5583 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
5585 sbuf_printf(&sb, " ");
5586 sbuf_printf(&sb, "%d", *i);
5590 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5596 sysctl_bitfield(SYSCTL_HANDLER_ARGS)
5601 rc = sysctl_wire_old_buffer(req, 0);
5605 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5609 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
5610 rc = sbuf_finish(sb);
5617 sysctl_btphy(SYSCTL_HANDLER_ARGS)
5619 struct port_info *pi = arg1;
5621 struct adapter *sc = pi->adapter;
5625 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
5628 /* XXX: magic numbers */
5629 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
5631 end_synchronized_op(sc, 0);
5637 rc = sysctl_handle_int(oidp, &v, 0, req);
5642 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
5644 struct vi_info *vi = arg1;
5647 val = vi->rsrv_noflowq;
5648 rc = sysctl_handle_int(oidp, &val, 0, req);
5649 if (rc != 0 || req->newptr == NULL)
5652 if ((val >= 1) && (vi->ntxq > 1))
5653 vi->rsrv_noflowq = 1;
5655 vi->rsrv_noflowq = 0;
5661 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
5663 struct vi_info *vi = arg1;
5664 struct adapter *sc = vi->pi->adapter;
5666 struct sge_rxq *rxq;
5668 struct sge_ofld_rxq *ofld_rxq;
5674 rc = sysctl_handle_int(oidp, &idx, 0, req);
5675 if (rc != 0 || req->newptr == NULL)
5678 if (idx < 0 || idx >= SGE_NTIMERS)
5681 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5686 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
5687 for_each_rxq(vi, i, rxq) {
5688 #ifdef atomic_store_rel_8
5689 atomic_store_rel_8(&rxq->iq.intr_params, v);
5691 rxq->iq.intr_params = v;
5695 for_each_ofld_rxq(vi, i, ofld_rxq) {
5696 #ifdef atomic_store_rel_8
5697 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
5699 ofld_rxq->iq.intr_params = v;
5705 end_synchronized_op(sc, LOCK_HELD);
5710 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
5712 struct vi_info *vi = arg1;
5713 struct adapter *sc = vi->pi->adapter;
5718 rc = sysctl_handle_int(oidp, &idx, 0, req);
5719 if (rc != 0 || req->newptr == NULL)
5722 if (idx < -1 || idx >= SGE_NCOUNTERS)
5725 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5730 if (vi->flags & VI_INIT_DONE)
5731 rc = EBUSY; /* cannot be changed once the queues are created */
5735 end_synchronized_op(sc, LOCK_HELD);
5740 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
5742 struct vi_info *vi = arg1;
5743 struct adapter *sc = vi->pi->adapter;
5746 qsize = vi->qsize_rxq;
5748 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5749 if (rc != 0 || req->newptr == NULL)
5752 if (qsize < 128 || (qsize & 7))
5755 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5760 if (vi->flags & VI_INIT_DONE)
5761 rc = EBUSY; /* cannot be changed once the queues are created */
5763 vi->qsize_rxq = qsize;
5765 end_synchronized_op(sc, LOCK_HELD);
5770 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
5772 struct vi_info *vi = arg1;
5773 struct adapter *sc = vi->pi->adapter;
5776 qsize = vi->qsize_txq;
5778 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5779 if (rc != 0 || req->newptr == NULL)
5782 if (qsize < 128 || qsize > 65536)
5785 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5790 if (vi->flags & VI_INIT_DONE)
5791 rc = EBUSY; /* cannot be changed once the queues are created */
5793 vi->qsize_txq = qsize;
5795 end_synchronized_op(sc, LOCK_HELD);
5800 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
5802 struct port_info *pi = arg1;
5803 struct adapter *sc = pi->adapter;
5804 struct link_config *lc = &pi->link_cfg;
5807 if (req->newptr == NULL) {
5809 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX";
5811 rc = sysctl_wire_old_buffer(req, 0);
5815 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5819 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits);
5820 rc = sbuf_finish(sb);
5826 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX));
5829 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
5835 if (s[0] < '0' || s[0] > '9')
5836 return (EINVAL); /* not a number */
5838 if (n & ~(PAUSE_TX | PAUSE_RX))
5839 return (EINVAL); /* some other bit is set too */
5841 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
5846 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) {
5847 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX);
5848 lc->requested_fc |= n;
5849 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5851 lc->fc = lc->requested_fc;
5852 set_current_media(pi, &pi->media);
5856 end_synchronized_op(sc, 0);
5863 sysctl_fec(SYSCTL_HANDLER_ARGS)
5865 struct port_info *pi = arg1;
5866 struct adapter *sc = pi->adapter;
5867 struct link_config *lc = &pi->link_cfg;
5870 if (req->newptr == NULL) {
5872 static char *bits = "\20\1RS\2BASER_RS\3RESERVED";
5874 rc = sysctl_wire_old_buffer(req, 0);
5878 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5882 sbuf_printf(sb, "%b", lc->fec & M_FW_PORT_CAP_FEC, bits);
5883 rc = sbuf_finish(sb);
5889 s[0] = '0' + (lc->requested_fec & M_FW_PORT_CAP_FEC);
5892 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
5898 if (s[0] < '0' || s[0] > '9')
5899 return (EINVAL); /* not a number */
5901 if (n & ~M_FW_PORT_CAP_FEC)
5902 return (EINVAL); /* some other bit is set too */
5904 return (EINVAL); /* one bit can be set at most */
5906 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
5911 if ((lc->requested_fec & M_FW_PORT_CAP_FEC) != n) {
5912 lc->requested_fec = n &
5913 G_FW_PORT_CAP_FEC(lc->supported);
5914 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5916 lc->fec = lc->requested_fec;
5920 end_synchronized_op(sc, 0);
5927 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
5929 struct port_info *pi = arg1;
5930 struct adapter *sc = pi->adapter;
5931 struct link_config *lc = &pi->link_cfg;
5934 if (lc->supported & FW_PORT_CAP_ANEG)
5935 val = lc->requested_aneg == AUTONEG_ENABLE ? 1 : 0;
5938 rc = sysctl_handle_int(oidp, &val, 0, req);
5939 if (rc != 0 || req->newptr == NULL)
5942 val = AUTONEG_DISABLE;
5944 val = AUTONEG_ENABLE;
5948 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
5953 if ((lc->supported & FW_PORT_CAP_ANEG) == 0) {
5957 if (lc->requested_aneg == val) {
5958 rc = 0; /* no change, do nothing. */
5961 old = lc->requested_aneg;
5962 lc->requested_aneg = val;
5963 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5965 lc->requested_aneg = old;
5967 set_current_media(pi, &pi->media);
5970 end_synchronized_op(sc, 0);
5975 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
5977 struct adapter *sc = arg1;
5981 val = t4_read_reg64(sc, reg);
5983 return (sysctl_handle_64(oidp, &val, 0, req));
5987 sysctl_temperature(SYSCTL_HANDLER_ARGS)
5989 struct adapter *sc = arg1;
5991 uint32_t param, val;
5993 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
5996 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5997 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5998 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
5999 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
6000 end_synchronized_op(sc, 0);
6004 /* unknown is returned as 0 but we display -1 in that case */
6005 t = val == 0 ? -1 : val;
6007 rc = sysctl_handle_int(oidp, &t, 0, req);
6013 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
6015 struct adapter *sc = arg1;
6018 uint16_t incr[NMTUS][NCCTRL_WIN];
6019 static const char *dec_fac[] = {
6020 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
6024 rc = sysctl_wire_old_buffer(req, 0);
6028 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6032 t4_read_cong_tbl(sc, incr);
6034 for (i = 0; i < NCCTRL_WIN; ++i) {
6035 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
6036 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
6037 incr[5][i], incr[6][i], incr[7][i]);
6038 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
6039 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
6040 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
6041 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
6044 rc = sbuf_finish(sb);
6050 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
6051 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
6052 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
6053 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
6057 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
6059 struct adapter *sc = arg1;
6061 int rc, i, n, qid = arg2;
6064 u_int cim_num_obq = sc->chip_params->cim_num_obq;
6066 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
6067 ("%s: bad qid %d\n", __func__, qid));
6069 if (qid < CIM_NUM_IBQ) {
6072 n = 4 * CIM_IBQ_SIZE;
6073 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
6074 rc = t4_read_cim_ibq(sc, qid, buf, n);
6076 /* outbound queue */
6079 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
6080 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
6081 rc = t4_read_cim_obq(sc, qid, buf, n);
6088 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
6090 rc = sysctl_wire_old_buffer(req, 0);
6094 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
6100 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
6101 for (i = 0, p = buf; i < n; i += 16, p += 4)
6102 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
6105 rc = sbuf_finish(sb);
6113 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
6115 struct adapter *sc = arg1;
6121 MPASS(chip_id(sc) <= CHELSIO_T5);
6123 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
6127 rc = sysctl_wire_old_buffer(req, 0);
6131 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6135 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
6138 rc = -t4_cim_read_la(sc, buf, NULL);
6142 sbuf_printf(sb, "Status Data PC%s",
6143 cfg & F_UPDBGLACAPTPCONLY ? "" :
6144 " LS0Stat LS0Addr LS0Data");
6146 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
6147 if (cfg & F_UPDBGLACAPTPCONLY) {
6148 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
6150 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
6151 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
6152 p[4] & 0xff, p[5] >> 8);
6153 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
6154 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
6155 p[1] & 0xf, p[2] >> 4);
6158 "\n %02x %x%07x %x%07x %08x %08x "
6160 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
6161 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
6166 rc = sbuf_finish(sb);
6174 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
6176 struct adapter *sc = arg1;
6182 MPASS(chip_id(sc) > CHELSIO_T5);
6184 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
6188 rc = sysctl_wire_old_buffer(req, 0);
6192 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6196 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
6199 rc = -t4_cim_read_la(sc, buf, NULL);
6203 sbuf_printf(sb, "Status Inst Data PC%s",
6204 cfg & F_UPDBGLACAPTPCONLY ? "" :
6205 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
6207 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
6208 if (cfg & F_UPDBGLACAPTPCONLY) {
6209 sbuf_printf(sb, "\n %02x %08x %08x %08x",
6210 p[3] & 0xff, p[2], p[1], p[0]);
6211 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
6212 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
6213 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
6214 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
6215 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
6216 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
6219 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
6220 "%08x %08x %08x %08x %08x %08x",
6221 (p[9] >> 16) & 0xff,
6222 p[9] & 0xffff, p[8] >> 16,
6223 p[8] & 0xffff, p[7] >> 16,
6224 p[7] & 0xffff, p[6] >> 16,
6225 p[2], p[1], p[0], p[5], p[4], p[3]);
6229 rc = sbuf_finish(sb);
6237 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
6239 struct adapter *sc = arg1;
6245 rc = sysctl_wire_old_buffer(req, 0);
6249 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6253 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
6256 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
6259 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
6260 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
6264 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
6265 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
6266 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
6267 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
6268 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
6269 (p[1] >> 2) | ((p[2] & 3) << 30),
6270 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
6274 rc = sbuf_finish(sb);
6281 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
6283 struct adapter *sc = arg1;
6289 rc = sysctl_wire_old_buffer(req, 0);
6293 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6297 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
6300 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
6303 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
6304 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
6305 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
6306 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
6307 p[4], p[3], p[2], p[1], p[0]);
6310 sbuf_printf(sb, "\n\nCntl ID Data");
6311 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
6312 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
6313 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
6316 rc = sbuf_finish(sb);
6323 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
6325 struct adapter *sc = arg1;
6328 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
6329 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
6330 uint16_t thres[CIM_NUM_IBQ];
6331 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
6332 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
6333 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
6335 cim_num_obq = sc->chip_params->cim_num_obq;
6337 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
6338 obq_rdaddr = A_UP_OBQ_0_REALADDR;
6340 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
6341 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
6343 nq = CIM_NUM_IBQ + cim_num_obq;
6345 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
6347 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
6351 t4_read_cimq_cfg(sc, base, size, thres);
6353 rc = sysctl_wire_old_buffer(req, 0);
6357 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
6362 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
6364 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
6365 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
6366 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
6367 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
6368 G_QUEREMFLITS(p[2]) * 16);
6369 for ( ; i < nq; i++, p += 4, wr += 2)
6370 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
6371 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
6372 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
6373 G_QUEREMFLITS(p[2]) * 16);
6375 rc = sbuf_finish(sb);
6382 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
6384 struct adapter *sc = arg1;
6387 struct tp_cpl_stats stats;
6389 rc = sysctl_wire_old_buffer(req, 0);
6393 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6397 mtx_lock(&sc->reg_lock);
6398 t4_tp_get_cpl_stats(sc, &stats, 0);
6399 mtx_unlock(&sc->reg_lock);
6401 if (sc->chip_params->nchan > 2) {
6402 sbuf_printf(sb, " channel 0 channel 1"
6403 " channel 2 channel 3");
6404 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
6405 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
6406 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
6407 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
6409 sbuf_printf(sb, " channel 0 channel 1");
6410 sbuf_printf(sb, "\nCPL requests: %10u %10u",
6411 stats.req[0], stats.req[1]);
6412 sbuf_printf(sb, "\nCPL responses: %10u %10u",
6413 stats.rsp[0], stats.rsp[1]);
6416 rc = sbuf_finish(sb);
6423 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
6425 struct adapter *sc = arg1;
6428 struct tp_usm_stats stats;
6430 rc = sysctl_wire_old_buffer(req, 0);
6434 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6438 t4_get_usm_stats(sc, &stats, 1);
6440 sbuf_printf(sb, "Frames: %u\n", stats.frames);
6441 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
6442 sbuf_printf(sb, "Drops: %u", stats.drops);
6444 rc = sbuf_finish(sb);
6450 static const char * const devlog_level_strings[] = {
6451 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
6452 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
6453 [FW_DEVLOG_LEVEL_ERR] = "ERR",
6454 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
6455 [FW_DEVLOG_LEVEL_INFO] = "INFO",
6456 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
6459 static const char * const devlog_facility_strings[] = {
6460 [FW_DEVLOG_FACILITY_CORE] = "CORE",
6461 [FW_DEVLOG_FACILITY_CF] = "CF",
6462 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
6463 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
6464 [FW_DEVLOG_FACILITY_RES] = "RES",
6465 [FW_DEVLOG_FACILITY_HW] = "HW",
6466 [FW_DEVLOG_FACILITY_FLR] = "FLR",
6467 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
6468 [FW_DEVLOG_FACILITY_PHY] = "PHY",
6469 [FW_DEVLOG_FACILITY_MAC] = "MAC",
6470 [FW_DEVLOG_FACILITY_PORT] = "PORT",
6471 [FW_DEVLOG_FACILITY_VI] = "VI",
6472 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
6473 [FW_DEVLOG_FACILITY_ACL] = "ACL",
6474 [FW_DEVLOG_FACILITY_TM] = "TM",
6475 [FW_DEVLOG_FACILITY_QFC] = "QFC",
6476 [FW_DEVLOG_FACILITY_DCB] = "DCB",
6477 [FW_DEVLOG_FACILITY_ETH] = "ETH",
6478 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
6479 [FW_DEVLOG_FACILITY_RI] = "RI",
6480 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
6481 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
6482 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
6483 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
6484 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
6488 sysctl_devlog(SYSCTL_HANDLER_ARGS)
6490 struct adapter *sc = arg1;
6491 struct devlog_params *dparams = &sc->params.devlog;
6492 struct fw_devlog_e *buf, *e;
6493 int i, j, rc, nentries, first = 0;
6495 uint64_t ftstamp = UINT64_MAX;
6497 if (dparams->addr == 0)
6500 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
6504 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
6508 nentries = dparams->size / sizeof(struct fw_devlog_e);
6509 for (i = 0; i < nentries; i++) {
6512 if (e->timestamp == 0)
6515 e->timestamp = be64toh(e->timestamp);
6516 e->seqno = be32toh(e->seqno);
6517 for (j = 0; j < 8; j++)
6518 e->params[j] = be32toh(e->params[j]);
6520 if (e->timestamp < ftstamp) {
6521 ftstamp = e->timestamp;
6526 if (buf[first].timestamp == 0)
6527 goto done; /* nothing in the log */
6529 rc = sysctl_wire_old_buffer(req, 0);
6533 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6538 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
6539 "Seq#", "Tstamp", "Level", "Facility", "Message");
6544 if (e->timestamp == 0)
6547 sbuf_printf(sb, "%10d %15ju %8s %8s ",
6548 e->seqno, e->timestamp,
6549 (e->level < nitems(devlog_level_strings) ?
6550 devlog_level_strings[e->level] : "UNKNOWN"),
6551 (e->facility < nitems(devlog_facility_strings) ?
6552 devlog_facility_strings[e->facility] : "UNKNOWN"));
6553 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
6554 e->params[2], e->params[3], e->params[4],
6555 e->params[5], e->params[6], e->params[7]);
6557 if (++i == nentries)
6559 } while (i != first);
6561 rc = sbuf_finish(sb);
6569 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
6571 struct adapter *sc = arg1;
6574 struct tp_fcoe_stats stats[MAX_NCHAN];
6575 int i, nchan = sc->chip_params->nchan;
6577 rc = sysctl_wire_old_buffer(req, 0);
6581 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6585 for (i = 0; i < nchan; i++)
6586 t4_get_fcoe_stats(sc, i, &stats[i], 1);
6589 sbuf_printf(sb, " channel 0 channel 1"
6590 " channel 2 channel 3");
6591 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
6592 stats[0].octets_ddp, stats[1].octets_ddp,
6593 stats[2].octets_ddp, stats[3].octets_ddp);
6594 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
6595 stats[0].frames_ddp, stats[1].frames_ddp,
6596 stats[2].frames_ddp, stats[3].frames_ddp);
6597 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
6598 stats[0].frames_drop, stats[1].frames_drop,
6599 stats[2].frames_drop, stats[3].frames_drop);
6601 sbuf_printf(sb, " channel 0 channel 1");
6602 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
6603 stats[0].octets_ddp, stats[1].octets_ddp);
6604 sbuf_printf(sb, "\nframesDDP: %16u %16u",
6605 stats[0].frames_ddp, stats[1].frames_ddp);
6606 sbuf_printf(sb, "\nframesDrop: %16u %16u",
6607 stats[0].frames_drop, stats[1].frames_drop);
6610 rc = sbuf_finish(sb);
6617 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
6619 struct adapter *sc = arg1;
6622 unsigned int map, kbps, ipg, mode;
6623 unsigned int pace_tab[NTX_SCHED];
6625 rc = sysctl_wire_old_buffer(req, 0);
6629 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6633 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
6634 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
6635 t4_read_pace_tbl(sc, pace_tab);
6637 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
6638 "Class IPG (0.1 ns) Flow IPG (us)");
6640 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
6641 t4_get_tx_sched(sc, i, &kbps, &ipg, 1);
6642 sbuf_printf(sb, "\n %u %-5s %u ", i,
6643 (mode & (1 << i)) ? "flow" : "class", map & 3);
6645 sbuf_printf(sb, "%9u ", kbps);
6647 sbuf_printf(sb, " disabled ");
6650 sbuf_printf(sb, "%13u ", ipg);
6652 sbuf_printf(sb, " disabled ");
6655 sbuf_printf(sb, "%10u", pace_tab[i]);
6657 sbuf_printf(sb, " disabled");
6660 rc = sbuf_finish(sb);
6667 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
6669 struct adapter *sc = arg1;
6673 struct lb_port_stats s[2];
6674 static const char *stat_name[] = {
6675 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
6676 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
6677 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
6678 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
6679 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
6680 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
6681 "BG2FramesTrunc:", "BG3FramesTrunc:"
6684 rc = sysctl_wire_old_buffer(req, 0);
6688 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6692 memset(s, 0, sizeof(s));
6694 for (i = 0; i < sc->chip_params->nchan; i += 2) {
6695 t4_get_lb_stats(sc, i, &s[0]);
6696 t4_get_lb_stats(sc, i + 1, &s[1]);
6700 sbuf_printf(sb, "%s Loopback %u"
6701 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
6703 for (j = 0; j < nitems(stat_name); j++)
6704 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
6708 rc = sbuf_finish(sb);
6715 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
6718 struct port_info *pi = arg1;
6719 struct link_config *lc = &pi->link_cfg;
6722 rc = sysctl_wire_old_buffer(req, 0);
6725 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
6729 if (lc->link_ok || lc->link_down_rc == 255)
6730 sbuf_printf(sb, "n/a");
6732 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
6734 rc = sbuf_finish(sb);
6747 mem_desc_cmp(const void *a, const void *b)
6749 return ((const struct mem_desc *)a)->base -
6750 ((const struct mem_desc *)b)->base;
6754 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
6762 size = to - from + 1;
6766 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
6767 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
6771 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
6773 struct adapter *sc = arg1;
6776 uint32_t lo, hi, used, alloc;
6777 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
6778 static const char *region[] = {
6779 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
6780 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
6781 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
6782 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
6783 "RQUDP region:", "PBL region:", "TXPBL region:",
6784 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
6787 struct mem_desc avail[4];
6788 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
6789 struct mem_desc *md = mem;
6791 rc = sysctl_wire_old_buffer(req, 0);
6795 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6799 for (i = 0; i < nitems(mem); i++) {
6804 /* Find and sort the populated memory ranges */
6806 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
6807 if (lo & F_EDRAM0_ENABLE) {
6808 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
6809 avail[i].base = G_EDRAM0_BASE(hi) << 20;
6810 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
6814 if (lo & F_EDRAM1_ENABLE) {
6815 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
6816 avail[i].base = G_EDRAM1_BASE(hi) << 20;
6817 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
6821 if (lo & F_EXT_MEM_ENABLE) {
6822 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
6823 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
6824 avail[i].limit = avail[i].base +
6825 (G_EXT_MEM_SIZE(hi) << 20);
6826 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
6829 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
6830 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
6831 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
6832 avail[i].limit = avail[i].base +
6833 (G_EXT_MEM1_SIZE(hi) << 20);
6837 if (!i) /* no memory available */
6839 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
6841 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
6842 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
6843 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
6844 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
6845 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
6846 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
6847 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
6848 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
6849 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
6851 /* the next few have explicit upper bounds */
6852 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
6853 md->limit = md->base - 1 +
6854 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
6855 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
6858 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
6859 md->limit = md->base - 1 +
6860 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
6861 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
6864 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6865 if (chip_id(sc) <= CHELSIO_T5)
6866 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
6868 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
6872 md->idx = nitems(region); /* hide it */
6876 #define ulp_region(reg) \
6877 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
6878 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
6880 ulp_region(RX_ISCSI);
6881 ulp_region(RX_TDDP);
6883 ulp_region(RX_STAG);
6885 ulp_region(RX_RQUDP);
6891 md->idx = nitems(region);
6894 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
6895 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
6898 if (sge_ctrl & F_VFIFO_ENABLE)
6899 size = G_DBVFIFO_SIZE(fifo_size);
6901 size = G_T6_DBVFIFO_SIZE(fifo_size);
6904 md->base = G_BASEADDR(t4_read_reg(sc,
6905 A_SGE_DBVFIFO_BADDR));
6906 md->limit = md->base + (size << 2) - 1;
6911 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
6914 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
6918 md->base = sc->vres.ocq.start;
6919 if (sc->vres.ocq.size)
6920 md->limit = md->base + sc->vres.ocq.size - 1;
6922 md->idx = nitems(region); /* hide it */
6925 /* add any address-space holes, there can be up to 3 */
6926 for (n = 0; n < i - 1; n++)
6927 if (avail[n].limit < avail[n + 1].base)
6928 (md++)->base = avail[n].limit;
6930 (md++)->base = avail[n].limit;
6933 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
6935 for (lo = 0; lo < i; lo++)
6936 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
6937 avail[lo].limit - 1);
6939 sbuf_printf(sb, "\n");
6940 for (i = 0; i < n; i++) {
6941 if (mem[i].idx >= nitems(region))
6942 continue; /* skip holes */
6944 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
6945 mem_region_show(sb, region[mem[i].idx], mem[i].base,
6949 sbuf_printf(sb, "\n");
6950 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
6951 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
6952 mem_region_show(sb, "uP RAM:", lo, hi);
6954 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
6955 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
6956 mem_region_show(sb, "uP Extmem2:", lo, hi);
6958 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
6959 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
6961 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
6962 (lo & F_PMRXNUMCHN) ? 2 : 1);
6964 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
6965 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
6966 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
6968 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
6969 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
6970 sbuf_printf(sb, "%u p-structs\n",
6971 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
6973 for (i = 0; i < 4; i++) {
6974 if (chip_id(sc) > CHELSIO_T5)
6975 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
6977 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
6979 used = G_T5_USED(lo);
6980 alloc = G_T5_ALLOC(lo);
6983 alloc = G_ALLOC(lo);
6985 /* For T6 these are MAC buffer groups */
6986 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
6989 for (i = 0; i < sc->chip_params->nchan; i++) {
6990 if (chip_id(sc) > CHELSIO_T5)
6991 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
6993 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
6995 used = G_T5_USED(lo);
6996 alloc = G_T5_ALLOC(lo);
6999 alloc = G_ALLOC(lo);
7001 /* For T6 these are MAC buffer groups */
7003 "\nLoopback %d using %u pages out of %u allocated",
7007 rc = sbuf_finish(sb);
7014 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
7018 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
7022 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
7024 struct adapter *sc = arg1;
7028 MPASS(chip_id(sc) <= CHELSIO_T5);
7030 rc = sysctl_wire_old_buffer(req, 0);
7034 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7039 "Idx Ethernet address Mask Vld Ports PF"
7040 " VF Replication P0 P1 P2 P3 ML");
7041 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
7042 uint64_t tcamx, tcamy, mask;
7043 uint32_t cls_lo, cls_hi;
7044 uint8_t addr[ETHER_ADDR_LEN];
7046 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
7047 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
7050 tcamxy2valmask(tcamx, tcamy, addr, &mask);
7051 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
7052 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
7053 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
7054 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
7055 addr[3], addr[4], addr[5], (uintmax_t)mask,
7056 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
7057 G_PORTMAP(cls_hi), G_PF(cls_lo),
7058 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
7060 if (cls_lo & F_REPLICATE) {
7061 struct fw_ldst_cmd ldst_cmd;
7063 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
7064 ldst_cmd.op_to_addrspace =
7065 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
7066 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7067 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
7068 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
7069 ldst_cmd.u.mps.rplc.fid_idx =
7070 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
7071 V_FW_LDST_CMD_IDX(i));
7073 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
7077 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
7078 sizeof(ldst_cmd), &ldst_cmd);
7079 end_synchronized_op(sc, 0);
7082 sbuf_printf(sb, "%36d", rc);
7085 sbuf_printf(sb, " %08x %08x %08x %08x",
7086 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
7087 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
7088 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
7089 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
7092 sbuf_printf(sb, "%36s", "");
7094 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
7095 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
7096 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
7100 (void) sbuf_finish(sb);
7102 rc = sbuf_finish(sb);
7109 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
7111 struct adapter *sc = arg1;
7115 MPASS(chip_id(sc) > CHELSIO_T5);
7117 rc = sysctl_wire_old_buffer(req, 0);
7121 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7125 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
7126 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
7128 " P0 P1 P2 P3 ML\n");
7130 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
7131 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
7133 uint64_t tcamx, tcamy, val, mask;
7134 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
7135 uint8_t addr[ETHER_ADDR_LEN];
7137 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
7139 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
7141 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
7142 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
7143 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
7144 tcamy = G_DMACH(val) << 32;
7145 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
7146 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
7147 lookup_type = G_DATALKPTYPE(data2);
7148 port_num = G_DATAPORTNUM(data2);
7149 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7150 /* Inner header VNI */
7151 vniy = ((data2 & F_DATAVIDH2) << 23) |
7152 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
7153 dip_hit = data2 & F_DATADIPHIT;
7158 vlan_vld = data2 & F_DATAVIDH2;
7159 ivlan = G_VIDL(val);
7162 ctl |= V_CTLXYBITSEL(1);
7163 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
7164 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
7165 tcamx = G_DMACH(val) << 32;
7166 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
7167 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
7168 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7169 /* Inner header VNI mask */
7170 vnix = ((data2 & F_DATAVIDH2) << 23) |
7171 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
7177 tcamxy2valmask(tcamx, tcamy, addr, &mask);
7179 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
7180 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
7182 if (lookup_type && lookup_type != M_DATALKPTYPE) {
7183 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
7184 "%012jx %06x %06x - - %3c"
7185 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
7186 addr[1], addr[2], addr[3], addr[4], addr[5],
7187 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
7188 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
7189 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
7190 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
7192 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
7193 "%012jx - - ", i, addr[0], addr[1],
7194 addr[2], addr[3], addr[4], addr[5],
7198 sbuf_printf(sb, "%4u Y ", ivlan);
7200 sbuf_printf(sb, " - N ");
7202 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
7203 lookup_type ? 'I' : 'O', port_num,
7204 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
7205 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
7206 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
7210 if (cls_lo & F_T6_REPLICATE) {
7211 struct fw_ldst_cmd ldst_cmd;
7213 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
7214 ldst_cmd.op_to_addrspace =
7215 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
7216 F_FW_CMD_REQUEST | F_FW_CMD_READ |
7217 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
7218 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
7219 ldst_cmd.u.mps.rplc.fid_idx =
7220 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
7221 V_FW_LDST_CMD_IDX(i));
7223 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
7227 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
7228 sizeof(ldst_cmd), &ldst_cmd);
7229 end_synchronized_op(sc, 0);
7232 sbuf_printf(sb, "%72d", rc);
7235 sbuf_printf(sb, " %08x %08x %08x %08x"
7236 " %08x %08x %08x %08x",
7237 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
7238 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
7239 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
7240 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
7241 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
7242 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
7243 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
7244 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
7247 sbuf_printf(sb, "%72s", "");
7249 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
7250 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
7251 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
7252 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
7256 (void) sbuf_finish(sb);
7258 rc = sbuf_finish(sb);
7265 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
7267 struct adapter *sc = arg1;
7270 uint16_t mtus[NMTUS];
7272 rc = sysctl_wire_old_buffer(req, 0);
7276 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7280 t4_read_mtu_tbl(sc, mtus, NULL);
7282 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
7283 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
7284 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
7285 mtus[14], mtus[15]);
7287 rc = sbuf_finish(sb);
7294 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
7296 struct adapter *sc = arg1;
7299 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
7300 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
7301 static const char *tx_stats[MAX_PM_NSTATS] = {
7302 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
7303 "Tx FIFO wait", NULL, "Tx latency"
7305 static const char *rx_stats[MAX_PM_NSTATS] = {
7306 "Read:", "Write bypass:", "Write mem:", "Flush:",
7307 "Rx FIFO wait", NULL, "Rx latency"
7310 rc = sysctl_wire_old_buffer(req, 0);
7314 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7318 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
7319 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
7321 sbuf_printf(sb, " Tx pcmds Tx bytes");
7322 for (i = 0; i < 4; i++) {
7323 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
7327 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
7328 for (i = 0; i < 4; i++) {
7329 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
7333 if (chip_id(sc) > CHELSIO_T5) {
7335 "\n Total wait Total occupancy");
7336 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
7338 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
7342 MPASS(i < nitems(tx_stats));
7345 "\n Reads Total wait");
7346 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
7348 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
7352 rc = sbuf_finish(sb);
7359 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
7361 struct adapter *sc = arg1;
7364 struct tp_rdma_stats stats;
7366 rc = sysctl_wire_old_buffer(req, 0);
7370 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7374 mtx_lock(&sc->reg_lock);
7375 t4_tp_get_rdma_stats(sc, &stats, 0);
7376 mtx_unlock(&sc->reg_lock);
7378 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
7379 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
7381 rc = sbuf_finish(sb);
7388 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
7390 struct adapter *sc = arg1;
7393 struct tp_tcp_stats v4, v6;
7395 rc = sysctl_wire_old_buffer(req, 0);
7399 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7403 mtx_lock(&sc->reg_lock);
7404 t4_tp_get_tcp_stats(sc, &v4, &v6, 0);
7405 mtx_unlock(&sc->reg_lock);
7409 sbuf_printf(sb, "OutRsts: %20u %20u\n",
7410 v4.tcp_out_rsts, v6.tcp_out_rsts);
7411 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
7412 v4.tcp_in_segs, v6.tcp_in_segs);
7413 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
7414 v4.tcp_out_segs, v6.tcp_out_segs);
7415 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
7416 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
7418 rc = sbuf_finish(sb);
7425 sysctl_tids(SYSCTL_HANDLER_ARGS)
7427 struct adapter *sc = arg1;
7430 struct tid_info *t = &sc->tids;
7432 rc = sysctl_wire_old_buffer(req, 0);
7436 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7441 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
7446 sbuf_printf(sb, "TID range: ");
7447 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
7450 if (chip_id(sc) <= CHELSIO_T5) {
7451 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
7452 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
7454 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
7455 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
7459 sbuf_printf(sb, "0-%u, ", b - 1);
7460 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1);
7462 sbuf_printf(sb, "0-%u", t->ntids - 1);
7463 sbuf_printf(sb, ", in use: %u\n",
7464 atomic_load_acq_int(&t->tids_in_use));
7468 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
7469 t->stid_base + t->nstids - 1, t->stids_in_use);
7473 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
7474 t->ftid_base + t->nftids - 1);
7478 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base,
7479 t->etid_base + t->netids - 1);
7482 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
7483 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
7484 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
7486 rc = sbuf_finish(sb);
7493 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
7495 struct adapter *sc = arg1;
7498 struct tp_err_stats stats;
7500 rc = sysctl_wire_old_buffer(req, 0);
7504 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7508 mtx_lock(&sc->reg_lock);
7509 t4_tp_get_err_stats(sc, &stats, 0);
7510 mtx_unlock(&sc->reg_lock);
7512 if (sc->chip_params->nchan > 2) {
7513 sbuf_printf(sb, " channel 0 channel 1"
7514 " channel 2 channel 3\n");
7515 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
7516 stats.mac_in_errs[0], stats.mac_in_errs[1],
7517 stats.mac_in_errs[2], stats.mac_in_errs[3]);
7518 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
7519 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
7520 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
7521 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
7522 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
7523 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
7524 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
7525 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
7526 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
7527 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
7528 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
7529 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
7530 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
7531 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
7532 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
7533 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
7534 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
7535 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
7536 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
7537 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
7538 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
7540 sbuf_printf(sb, " channel 0 channel 1\n");
7541 sbuf_printf(sb, "macInErrs: %10u %10u\n",
7542 stats.mac_in_errs[0], stats.mac_in_errs[1]);
7543 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
7544 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
7545 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
7546 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
7547 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
7548 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
7549 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
7550 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
7551 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
7552 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
7553 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
7554 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
7555 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
7556 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
7559 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
7560 stats.ofld_no_neigh, stats.ofld_cong_defer);
7562 rc = sbuf_finish(sb);
7569 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
7571 struct adapter *sc = arg1;
7572 struct tp_params *tpp = &sc->params.tp;
7576 mask = tpp->la_mask >> 16;
7577 rc = sysctl_handle_int(oidp, &mask, 0, req);
7578 if (rc != 0 || req->newptr == NULL)
7582 tpp->la_mask = mask << 16;
7583 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
7595 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
7601 uint64_t mask = (1ULL << f->width) - 1;
7602 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
7603 ((uintmax_t)v >> f->start) & mask);
7605 if (line_size + len >= 79) {
7607 sbuf_printf(sb, "\n ");
7609 sbuf_printf(sb, "%s ", buf);
7610 line_size += len + 1;
7613 sbuf_printf(sb, "\n");
7616 static const struct field_desc tp_la0[] = {
7617 { "RcfOpCodeOut", 60, 4 },
7619 { "WcfState", 52, 4 },
7620 { "RcfOpcSrcOut", 50, 2 },
7621 { "CRxError", 49, 1 },
7622 { "ERxError", 48, 1 },
7623 { "SanityFailed", 47, 1 },
7624 { "SpuriousMsg", 46, 1 },
7625 { "FlushInputMsg", 45, 1 },
7626 { "FlushInputCpl", 44, 1 },
7627 { "RssUpBit", 43, 1 },
7628 { "RssFilterHit", 42, 1 },
7630 { "InitTcb", 31, 1 },
7631 { "LineNumber", 24, 7 },
7633 { "EdataOut", 22, 1 },
7635 { "CdataOut", 20, 1 },
7636 { "EreadPdu", 19, 1 },
7637 { "CreadPdu", 18, 1 },
7638 { "TunnelPkt", 17, 1 },
7639 { "RcfPeerFin", 16, 1 },
7640 { "RcfReasonOut", 12, 4 },
7641 { "TxCchannel", 10, 2 },
7642 { "RcfTxChannel", 8, 2 },
7643 { "RxEchannel", 6, 2 },
7644 { "RcfRxChannel", 5, 1 },
7645 { "RcfDataOutSrdy", 4, 1 },
7647 { "RxOoDvld", 2, 1 },
7648 { "RxCongestion", 1, 1 },
7649 { "TxCongestion", 0, 1 },
7653 static const struct field_desc tp_la1[] = {
7654 { "CplCmdIn", 56, 8 },
7655 { "CplCmdOut", 48, 8 },
7656 { "ESynOut", 47, 1 },
7657 { "EAckOut", 46, 1 },
7658 { "EFinOut", 45, 1 },
7659 { "ERstOut", 44, 1 },
7664 { "DataIn", 39, 1 },
7665 { "DataInVld", 38, 1 },
7667 { "RxBufEmpty", 36, 1 },
7669 { "RxFbCongestion", 34, 1 },
7670 { "TxFbCongestion", 33, 1 },
7671 { "TxPktSumSrdy", 32, 1 },
7672 { "RcfUlpType", 28, 4 },
7674 { "Ebypass", 26, 1 },
7676 { "Static0", 24, 1 },
7678 { "Cbypass", 22, 1 },
7680 { "CPktOut", 20, 1 },
7681 { "RxPagePoolFull", 18, 2 },
7682 { "RxLpbkPkt", 17, 1 },
7683 { "TxLpbkPkt", 16, 1 },
7684 { "RxVfValid", 15, 1 },
7685 { "SynLearned", 14, 1 },
7686 { "SetDelEntry", 13, 1 },
7687 { "SetInvEntry", 12, 1 },
7688 { "CpcmdDvld", 11, 1 },
7689 { "CpcmdSave", 10, 1 },
7690 { "RxPstructsFull", 8, 2 },
7691 { "EpcmdDvld", 7, 1 },
7692 { "EpcmdFlush", 6, 1 },
7693 { "EpcmdTrimPrefix", 5, 1 },
7694 { "EpcmdTrimPostfix", 4, 1 },
7695 { "ERssIp4Pkt", 3, 1 },
7696 { "ERssIp6Pkt", 2, 1 },
7697 { "ERssTcpUdpPkt", 1, 1 },
7698 { "ERssFceFipPkt", 0, 1 },
7702 static const struct field_desc tp_la2[] = {
7703 { "CplCmdIn", 56, 8 },
7704 { "MpsVfVld", 55, 1 },
7711 { "DataIn", 39, 1 },
7712 { "DataInVld", 38, 1 },
7714 { "RxBufEmpty", 36, 1 },
7716 { "RxFbCongestion", 34, 1 },
7717 { "TxFbCongestion", 33, 1 },
7718 { "TxPktSumSrdy", 32, 1 },
7719 { "RcfUlpType", 28, 4 },
7721 { "Ebypass", 26, 1 },
7723 { "Static0", 24, 1 },
7725 { "Cbypass", 22, 1 },
7727 { "CPktOut", 20, 1 },
7728 { "RxPagePoolFull", 18, 2 },
7729 { "RxLpbkPkt", 17, 1 },
7730 { "TxLpbkPkt", 16, 1 },
7731 { "RxVfValid", 15, 1 },
7732 { "SynLearned", 14, 1 },
7733 { "SetDelEntry", 13, 1 },
7734 { "SetInvEntry", 12, 1 },
7735 { "CpcmdDvld", 11, 1 },
7736 { "CpcmdSave", 10, 1 },
7737 { "RxPstructsFull", 8, 2 },
7738 { "EpcmdDvld", 7, 1 },
7739 { "EpcmdFlush", 6, 1 },
7740 { "EpcmdTrimPrefix", 5, 1 },
7741 { "EpcmdTrimPostfix", 4, 1 },
7742 { "ERssIp4Pkt", 3, 1 },
7743 { "ERssIp6Pkt", 2, 1 },
7744 { "ERssTcpUdpPkt", 1, 1 },
7745 { "ERssFceFipPkt", 0, 1 },
7750 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
7753 field_desc_show(sb, *p, tp_la0);
7757 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
7761 sbuf_printf(sb, "\n");
7762 field_desc_show(sb, p[0], tp_la0);
7763 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7764 field_desc_show(sb, p[1], tp_la0);
7768 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
7772 sbuf_printf(sb, "\n");
7773 field_desc_show(sb, p[0], tp_la0);
7774 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7775 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
7779 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
7781 struct adapter *sc = arg1;
7786 void (*show_func)(struct sbuf *, uint64_t *, int);
7788 rc = sysctl_wire_old_buffer(req, 0);
7792 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7796 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
7798 t4_tp_read_la(sc, buf, NULL);
7801 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
7804 show_func = tp_la_show2;
7808 show_func = tp_la_show3;
7812 show_func = tp_la_show;
7815 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
7816 (*show_func)(sb, p, i);
7818 rc = sbuf_finish(sb);
7825 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
7827 struct adapter *sc = arg1;
7830 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
7832 rc = sysctl_wire_old_buffer(req, 0);
7836 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7840 t4_get_chan_txrate(sc, nrate, orate);
7842 if (sc->chip_params->nchan > 2) {
7843 sbuf_printf(sb, " channel 0 channel 1"
7844 " channel 2 channel 3\n");
7845 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
7846 nrate[0], nrate[1], nrate[2], nrate[3]);
7847 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
7848 orate[0], orate[1], orate[2], orate[3]);
7850 sbuf_printf(sb, " channel 0 channel 1\n");
7851 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
7852 nrate[0], nrate[1]);
7853 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
7854 orate[0], orate[1]);
7857 rc = sbuf_finish(sb);
7864 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
7866 struct adapter *sc = arg1;
7871 rc = sysctl_wire_old_buffer(req, 0);
7875 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7879 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
7882 t4_ulprx_read_la(sc, buf);
7885 sbuf_printf(sb, " Pcmd Type Message"
7887 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
7888 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
7889 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
7892 rc = sbuf_finish(sb);
7899 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
7901 struct adapter *sc = arg1;
7905 MPASS(chip_id(sc) >= CHELSIO_T5);
7907 rc = sysctl_wire_old_buffer(req, 0);
7911 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7915 v = t4_read_reg(sc, A_SGE_STAT_CFG);
7916 if (G_STATSOURCE_T5(v) == 7) {
7919 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
7921 sbuf_printf(sb, "total %d, incomplete %d",
7922 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7923 t4_read_reg(sc, A_SGE_STAT_MATCH));
7924 } else if (mode == 1) {
7925 sbuf_printf(sb, "total %d, data overflow %d",
7926 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7927 t4_read_reg(sc, A_SGE_STAT_MATCH));
7929 sbuf_printf(sb, "unknown mode %d", mode);
7932 rc = sbuf_finish(sb);
7939 sysctl_tc_params(SYSCTL_HANDLER_ARGS)
7941 struct adapter *sc = arg1;
7942 struct tx_cl_rl_params tc;
7944 int i, rc, port_id, mbps, gbps;
7946 rc = sysctl_wire_old_buffer(req, 0);
7950 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7954 port_id = arg2 >> 16;
7955 MPASS(port_id < sc->params.nports);
7956 MPASS(sc->port[port_id] != NULL);
7958 MPASS(i < sc->chip_params->nsched_cls);
7960 mtx_lock(&sc->tc_lock);
7961 tc = sc->port[port_id]->sched_params->cl_rl[i];
7962 mtx_unlock(&sc->tc_lock);
7964 if (tc.flags & TX_CLRL_ERROR) {
7965 sbuf_printf(sb, "error");
7969 if (tc.ratemode == SCHED_CLASS_RATEMODE_REL) {
7970 /* XXX: top speed or actual link speed? */
7971 gbps = port_top_speed(sc->port[port_id]);
7972 sbuf_printf(sb, " %u%% of %uGbps", tc.maxrate, gbps);
7973 } else if (tc.ratemode == SCHED_CLASS_RATEMODE_ABS) {
7974 switch (tc.rateunit) {
7975 case SCHED_CLASS_RATEUNIT_BITS:
7976 mbps = tc.maxrate / 1000;
7977 gbps = tc.maxrate / 1000000;
7978 if (tc.maxrate == gbps * 1000000)
7979 sbuf_printf(sb, " %uGbps", gbps);
7980 else if (tc.maxrate == mbps * 1000)
7981 sbuf_printf(sb, " %uMbps", mbps);
7983 sbuf_printf(sb, " %uKbps", tc.maxrate);
7985 case SCHED_CLASS_RATEUNIT_PKTS:
7986 sbuf_printf(sb, " %upps", tc.maxrate);
7995 case SCHED_CLASS_MODE_CLASS:
7996 sbuf_printf(sb, " aggregate");
7998 case SCHED_CLASS_MODE_FLOW:
7999 sbuf_printf(sb, " per-flow");
8008 rc = sbuf_finish(sb);
8017 unit_conv(char *buf, size_t len, u_int val, u_int factor)
8019 u_int rem = val % factor;
8022 snprintf(buf, len, "%u", val / factor);
8024 while (rem % 10 == 0)
8026 snprintf(buf, len, "%u.%u", val / factor, rem);
8031 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
8033 struct adapter *sc = arg1;
8036 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8038 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
8042 re = G_TIMERRESOLUTION(res);
8045 /* TCP timestamp tick */
8046 re = G_TIMESTAMPRESOLUTION(res);
8050 re = G_DELAYEDACKRESOLUTION(res);
8056 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
8058 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
8062 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
8064 struct adapter *sc = arg1;
8065 u_int res, dack_re, v;
8066 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8068 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
8069 dack_re = G_DELAYEDACKRESOLUTION(res);
8070 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
8072 return (sysctl_handle_int(oidp, &v, 0, req));
8076 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
8078 struct adapter *sc = arg1;
8081 u_long tp_tick_us, v;
8082 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
8084 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
8085 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
8086 reg == A_TP_KEEP_IDLE || reg == A_TP_KEEP_INTVL ||
8087 reg == A_TP_INIT_SRTT || reg == A_TP_FINWAIT2_TIMER);
8089 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
8090 tp_tick_us = (cclk_ps << tre) / 1000000;
8092 if (reg == A_TP_INIT_SRTT)
8093 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
8095 v = tp_tick_us * t4_read_reg(sc, reg);
8097 return (sysctl_handle_long(oidp, &v, 0, req));
8102 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf)
8106 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
8107 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
8109 if (fconf & F_FRAGMENTATION)
8110 mode |= T4_FILTER_IP_FRAGMENT;
8112 if (fconf & F_MPSHITTYPE)
8113 mode |= T4_FILTER_MPS_HIT_TYPE;
8115 if (fconf & F_MACMATCH)
8116 mode |= T4_FILTER_MAC_IDX;
8118 if (fconf & F_ETHERTYPE)
8119 mode |= T4_FILTER_ETH_TYPE;
8121 if (fconf & F_PROTOCOL)
8122 mode |= T4_FILTER_IP_PROTO;
8125 mode |= T4_FILTER_IP_TOS;
8128 mode |= T4_FILTER_VLAN;
8130 if (fconf & F_VNIC_ID) {
8131 mode |= T4_FILTER_VNIC;
8133 mode |= T4_FILTER_IC_VNIC;
8137 mode |= T4_FILTER_PORT;
8140 mode |= T4_FILTER_FCoE;
8146 mode_to_fconf(uint32_t mode)
8150 if (mode & T4_FILTER_IP_FRAGMENT)
8151 fconf |= F_FRAGMENTATION;
8153 if (mode & T4_FILTER_MPS_HIT_TYPE)
8154 fconf |= F_MPSHITTYPE;
8156 if (mode & T4_FILTER_MAC_IDX)
8157 fconf |= F_MACMATCH;
8159 if (mode & T4_FILTER_ETH_TYPE)
8160 fconf |= F_ETHERTYPE;
8162 if (mode & T4_FILTER_IP_PROTO)
8163 fconf |= F_PROTOCOL;
8165 if (mode & T4_FILTER_IP_TOS)
8168 if (mode & T4_FILTER_VLAN)
8171 if (mode & T4_FILTER_VNIC)
8174 if (mode & T4_FILTER_PORT)
8177 if (mode & T4_FILTER_FCoE)
8184 mode_to_iconf(uint32_t mode)
8187 if (mode & T4_FILTER_IC_VNIC)
8192 static int check_fspec_against_fconf_iconf(struct adapter *sc,
8193 struct t4_filter_specification *fs)
8195 struct tp_params *tpp = &sc->params.tp;
8198 if (fs->val.frag || fs->mask.frag)
8199 fconf |= F_FRAGMENTATION;
8201 if (fs->val.matchtype || fs->mask.matchtype)
8202 fconf |= F_MPSHITTYPE;
8204 if (fs->val.macidx || fs->mask.macidx)
8205 fconf |= F_MACMATCH;
8207 if (fs->val.ethtype || fs->mask.ethtype)
8208 fconf |= F_ETHERTYPE;
8210 if (fs->val.proto || fs->mask.proto)
8211 fconf |= F_PROTOCOL;
8213 if (fs->val.tos || fs->mask.tos)
8216 if (fs->val.vlan_vld || fs->mask.vlan_vld)
8219 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
8221 if (tpp->ingress_config & F_VNIC)
8225 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
8227 if ((tpp->ingress_config & F_VNIC) == 0)
8231 if (fs->val.iport || fs->mask.iport)
8234 if (fs->val.fcoe || fs->mask.fcoe)
8237 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map)
8244 get_filter_mode(struct adapter *sc, uint32_t *mode)
8246 struct tp_params *tpp = &sc->params.tp;
8249 * We trust the cached values of the relevant TP registers. This means
8250 * things work reliably only if writes to those registers are always via
8251 * t4_set_filter_mode.
8253 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config);
8259 set_filter_mode(struct adapter *sc, uint32_t mode)
8261 struct tp_params *tpp = &sc->params.tp;
8262 uint32_t fconf, iconf;
8265 iconf = mode_to_iconf(mode);
8266 if ((iconf ^ tpp->ingress_config) & F_VNIC) {
8268 * For now we just complain if A_TP_INGRESS_CONFIG is not
8269 * already set to the correct value for the requested filter
8270 * mode. It's not clear if it's safe to write to this register
8271 * on the fly. (And we trust the cached value of the register).
8276 fconf = mode_to_fconf(mode);
8278 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
8283 if (sc->tids.ftids_in_use > 0) {
8289 if (uld_active(sc, ULD_TOM)) {
8295 rc = -t4_set_filter_mode(sc, fconf, true);
8297 end_synchronized_op(sc, LOCK_HELD);
8301 static inline uint64_t
8302 get_filter_hits(struct adapter *sc, uint32_t fid)
8306 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) +
8307 (fid + sc->tids.ftid_base) * TCB_SIZE;
8312 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8);
8313 return (be64toh(hits));
8317 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4);
8318 return (be32toh(hits));
8323 get_filter(struct adapter *sc, struct t4_filter *t)
8325 int i, rc, nfilters = sc->tids.nftids;
8326 struct filter_entry *f;
8328 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
8333 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL ||
8334 t->idx >= nfilters) {
8335 t->idx = 0xffffffff;
8339 f = &sc->tids.ftid_tab[t->idx];
8340 for (i = t->idx; i < nfilters; i++, f++) {
8343 t->l2tidx = f->l2t ? f->l2t->idx : 0;
8344 t->smtidx = f->smtidx;
8346 t->hits = get_filter_hits(sc, t->idx);
8348 t->hits = UINT64_MAX;
8355 t->idx = 0xffffffff;
8357 end_synchronized_op(sc, LOCK_HELD);
8362 set_filter(struct adapter *sc, struct t4_filter *t)
8364 unsigned int nfilters, nports;
8365 struct filter_entry *f;
8368 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf");
8372 nfilters = sc->tids.nftids;
8373 nports = sc->params.nports;
8375 if (nfilters == 0) {
8380 if (t->idx >= nfilters) {
8385 /* Validate against the global filter mode and ingress config */
8386 rc = check_fspec_against_fconf_iconf(sc, &t->fs);
8390 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) {
8395 if (t->fs.val.iport >= nports) {
8400 /* Can't specify an iq if not steering to it */
8401 if (!t->fs.dirsteer && t->fs.iq) {
8406 /* IPv6 filter idx must be 4 aligned */
8407 if (t->fs.type == 1 &&
8408 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) {
8413 if (!(sc->flags & FULL_INIT_DONE) &&
8414 ((rc = adapter_full_init(sc)) != 0))
8417 if (sc->tids.ftid_tab == NULL) {
8418 KASSERT(sc->tids.ftids_in_use == 0,
8419 ("%s: no memory allocated but filters_in_use > 0",
8422 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) *
8423 nfilters, M_CXGBE, M_NOWAIT | M_ZERO);
8424 if (sc->tids.ftid_tab == NULL) {
8428 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF);
8431 for (i = 0; i < 4; i++) {
8432 f = &sc->tids.ftid_tab[t->idx + i];
8434 if (f->pending || f->valid) {
8443 if (t->fs.type == 0)
8447 f = &sc->tids.ftid_tab[t->idx];
8450 rc = set_filter_wr(sc, t->idx);
8452 end_synchronized_op(sc, 0);
8455 mtx_lock(&sc->tids.ftid_lock);
8457 if (f->pending == 0) {
8458 rc = f->valid ? 0 : EIO;
8462 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
8463 PCATCH, "t4setfw", 0)) {
8468 mtx_unlock(&sc->tids.ftid_lock);
8474 del_filter(struct adapter *sc, struct t4_filter *t)
8476 unsigned int nfilters;
8477 struct filter_entry *f;
8480 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf");
8484 nfilters = sc->tids.nftids;
8486 if (nfilters == 0) {
8491 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 ||
8492 t->idx >= nfilters) {
8497 if (!(sc->flags & FULL_INIT_DONE)) {
8502 f = &sc->tids.ftid_tab[t->idx];
8514 t->fs = f->fs; /* extra info for the caller */
8515 rc = del_filter_wr(sc, t->idx);
8519 end_synchronized_op(sc, 0);
8522 mtx_lock(&sc->tids.ftid_lock);
8524 if (f->pending == 0) {
8525 rc = f->valid ? EIO : 0;
8529 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
8530 PCATCH, "t4delfw", 0)) {
8535 mtx_unlock(&sc->tids.ftid_lock);
8542 clear_filter(struct filter_entry *f)
8545 t4_l2t_release(f->l2t);
8547 bzero(f, sizeof (*f));
8551 set_filter_wr(struct adapter *sc, int fidx)
8553 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8554 struct fw_filter_wr *fwr;
8555 unsigned int ftid, vnic_vld, vnic_vld_mask;
8556 struct wrq_cookie cookie;
8558 ASSERT_SYNCHRONIZED_OP(sc);
8560 if (f->fs.newdmac || f->fs.newvlan) {
8561 /* This filter needs an L2T entry; allocate one. */
8562 f->l2t = t4_l2t_alloc_switching(sc->l2t);
8565 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport,
8567 t4_l2t_release(f->l2t);
8573 /* Already validated against fconf, iconf */
8574 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0);
8575 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0);
8576 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld)
8580 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld)
8585 ftid = sc->tids.ftid_base + fidx;
8587 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8590 bzero(fwr, sizeof(*fwr));
8592 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR));
8593 fwr->len16_pkd = htobe32(FW_LEN16(*fwr));
8595 htobe32(V_FW_FILTER_WR_TID(ftid) |
8596 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
8597 V_FW_FILTER_WR_NOREPLY(0) |
8598 V_FW_FILTER_WR_IQ(f->fs.iq));
8599 fwr->del_filter_to_l2tix =
8600 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
8601 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
8602 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
8603 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
8604 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
8605 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
8606 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
8607 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
8608 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
8609 f->fs.newvlan == VLAN_REWRITE) |
8610 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
8611 f->fs.newvlan == VLAN_REWRITE) |
8612 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
8613 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
8614 V_FW_FILTER_WR_PRIO(f->fs.prio) |
8615 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
8616 fwr->ethtype = htobe16(f->fs.val.ethtype);
8617 fwr->ethtypem = htobe16(f->fs.mask.ethtype);
8618 fwr->frag_to_ovlan_vldm =
8619 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
8620 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
8621 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
8622 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) |
8623 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
8624 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask));
8626 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
8627 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
8628 fwr->maci_to_matchtypem =
8629 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
8630 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
8631 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
8632 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
8633 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
8634 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
8635 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
8636 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
8637 fwr->ptcl = f->fs.val.proto;
8638 fwr->ptclm = f->fs.mask.proto;
8639 fwr->ttyp = f->fs.val.tos;
8640 fwr->ttypm = f->fs.mask.tos;
8641 fwr->ivlan = htobe16(f->fs.val.vlan);
8642 fwr->ivlanm = htobe16(f->fs.mask.vlan);
8643 fwr->ovlan = htobe16(f->fs.val.vnic);
8644 fwr->ovlanm = htobe16(f->fs.mask.vnic);
8645 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
8646 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
8647 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
8648 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm));
8649 fwr->lp = htobe16(f->fs.val.dport);
8650 fwr->lpm = htobe16(f->fs.mask.dport);
8651 fwr->fp = htobe16(f->fs.val.sport);
8652 fwr->fpm = htobe16(f->fs.mask.sport);
8654 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma));
8657 sc->tids.ftids_in_use++;
8659 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8664 del_filter_wr(struct adapter *sc, int fidx)
8666 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8667 struct fw_filter_wr *fwr;
8669 struct wrq_cookie cookie;
8671 ftid = sc->tids.ftid_base + fidx;
8673 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8676 bzero(fwr, sizeof (*fwr));
8678 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
8681 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8686 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8688 struct adapter *sc = iq->adapter;
8689 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
8690 unsigned int idx = GET_TID(rpl);
8692 struct filter_entry *f;
8694 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
8696 MPASS(iq == &sc->sge.fwq);
8697 MPASS(is_ftid(sc, idx));
8699 idx -= sc->tids.ftid_base;
8700 f = &sc->tids.ftid_tab[idx];
8701 rc = G_COOKIE(rpl->cookie);
8703 mtx_lock(&sc->tids.ftid_lock);
8704 if (rc == FW_FILTER_WR_FLT_ADDED) {
8705 KASSERT(f->pending, ("%s: filter[%u] isn't pending.",
8707 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
8708 f->pending = 0; /* asynchronous setup completed */
8711 if (rc != FW_FILTER_WR_FLT_DELETED) {
8712 /* Add or delete failed, display an error */
8714 "filter %u setup failed with error %u\n",
8719 sc->tids.ftids_in_use--;
8721 wakeup(&sc->tids.ftid_tab);
8722 mtx_unlock(&sc->tids.ftid_lock);
8728 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8731 MPASS(iq->set_tcb_rpl != NULL);
8732 return (iq->set_tcb_rpl(iq, rss, m));
8736 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8739 MPASS(iq->l2t_write_rpl != NULL);
8740 return (iq->l2t_write_rpl(iq, rss, m));
8744 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
8748 if (cntxt->cid > M_CTXTQID)
8751 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
8752 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
8755 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
8759 if (sc->flags & FW_OK) {
8760 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
8767 * Read via firmware failed or wasn't even attempted. Read directly via
8770 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
8772 end_synchronized_op(sc, 0);
8777 load_fw(struct adapter *sc, struct t4_data *fw)
8782 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
8786 if (sc->flags & FULL_INIT_DONE) {
8791 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
8792 if (fw_data == NULL) {
8797 rc = copyin(fw->data, fw_data, fw->len);
8799 rc = -t4_load_fw(sc, fw_data, fw->len);
8801 free(fw_data, M_CXGBE);
8803 end_synchronized_op(sc, 0);
8808 load_cfg(struct adapter *sc, struct t4_data *cfg)
8811 uint8_t *cfg_data = NULL;
8813 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
8817 if (cfg->len == 0) {
8819 rc = -t4_load_cfg(sc, NULL, 0);
8823 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
8824 if (cfg_data == NULL) {
8829 rc = copyin(cfg->data, cfg_data, cfg->len);
8831 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
8833 free(cfg_data, M_CXGBE);
8835 end_synchronized_op(sc, 0);
8839 #define MAX_READ_BUF_SIZE (128 * 1024)
8841 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
8843 uint32_t addr, remaining, n;
8848 rc = validate_mem_range(sc, mr->addr, mr->len);
8852 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
8854 remaining = mr->len;
8855 dst = (void *)mr->data;
8858 n = min(remaining, MAX_READ_BUF_SIZE);
8859 read_via_memwin(sc, 2, addr, buf, n);
8861 rc = copyout(buf, dst, n);
8873 #undef MAX_READ_BUF_SIZE
8876 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
8880 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
8883 if (i2cd->len > sizeof(i2cd->data))
8886 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
8889 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
8890 i2cd->offset, i2cd->len, &i2cd->data[0]);
8891 end_synchronized_op(sc, 0);
8897 t4_os_find_pci_capability(struct adapter *sc, int cap)
8901 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
8905 t4_os_pci_save_state(struct adapter *sc)
8908 struct pci_devinfo *dinfo;
8911 dinfo = device_get_ivars(dev);
8913 pci_cfg_save(dev, dinfo, 0);
8918 t4_os_pci_restore_state(struct adapter *sc)
8921 struct pci_devinfo *dinfo;
8924 dinfo = device_get_ivars(dev);
8926 pci_cfg_restore(dev, dinfo);
8931 t4_os_portmod_changed(struct port_info *pi)
8933 struct adapter *sc = pi->adapter;
8936 static const char *mod_str[] = {
8937 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
8940 MPASS((pi->flags & FIXED_IFMEDIA) == 0);
8943 if (begin_synchronized_op(sc, vi, HOLD_LOCK, "t4mod") == 0) {
8945 build_medialist(pi, &pi->media);
8948 end_synchronized_op(sc, LOCK_HELD);
8952 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
8953 if_printf(ifp, "transceiver unplugged.\n");
8954 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
8955 if_printf(ifp, "unknown transceiver inserted.\n");
8956 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
8957 if_printf(ifp, "unsupported transceiver inserted.\n");
8958 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
8959 if_printf(ifp, "%dGbps %s transceiver inserted.\n",
8960 port_top_speed(pi), mod_str[pi->mod_type]);
8962 if_printf(ifp, "transceiver (type %d) inserted.\n",
8968 t4_os_link_changed(struct port_info *pi)
8972 struct link_config *lc;
8975 PORT_LOCK_ASSERT_OWNED(pi);
8977 for_each_vi(pi, v, vi) {
8984 ifp->if_baudrate = IF_Mbps(lc->speed);
8985 if_link_state_change(ifp, LINK_STATE_UP);
8987 if_link_state_change(ifp, LINK_STATE_DOWN);
8993 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
8997 sx_slock(&t4_list_lock);
8998 SLIST_FOREACH(sc, &t4_list, link) {
9000 * func should not make any assumptions about what state sc is
9001 * in - the only guarantee is that sc->sc_lock is a valid lock.
9005 sx_sunlock(&t4_list_lock);
9009 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
9013 struct adapter *sc = dev->si_drv1;
9015 rc = priv_check(td, PRIV_DRIVER);
9020 case CHELSIO_T4_GETREG: {
9021 struct t4_reg *edata = (struct t4_reg *)data;
9023 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9026 if (edata->size == 4)
9027 edata->val = t4_read_reg(sc, edata->addr);
9028 else if (edata->size == 8)
9029 edata->val = t4_read_reg64(sc, edata->addr);
9035 case CHELSIO_T4_SETREG: {
9036 struct t4_reg *edata = (struct t4_reg *)data;
9038 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9041 if (edata->size == 4) {
9042 if (edata->val & 0xffffffff00000000)
9044 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
9045 } else if (edata->size == 8)
9046 t4_write_reg64(sc, edata->addr, edata->val);
9051 case CHELSIO_T4_REGDUMP: {
9052 struct t4_regdump *regs = (struct t4_regdump *)data;
9053 int reglen = t4_get_regs_len(sc);
9056 if (regs->len < reglen) {
9057 regs->len = reglen; /* hint to the caller */
9062 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
9063 get_regs(sc, regs, buf);
9064 rc = copyout(buf, regs->data, reglen);
9068 case CHELSIO_T4_GET_FILTER_MODE:
9069 rc = get_filter_mode(sc, (uint32_t *)data);
9071 case CHELSIO_T4_SET_FILTER_MODE:
9072 rc = set_filter_mode(sc, *(uint32_t *)data);
9074 case CHELSIO_T4_GET_FILTER:
9075 rc = get_filter(sc, (struct t4_filter *)data);
9077 case CHELSIO_T4_SET_FILTER:
9078 rc = set_filter(sc, (struct t4_filter *)data);
9080 case CHELSIO_T4_DEL_FILTER:
9081 rc = del_filter(sc, (struct t4_filter *)data);
9083 case CHELSIO_T4_GET_SGE_CONTEXT:
9084 rc = get_sge_context(sc, (struct t4_sge_context *)data);
9086 case CHELSIO_T4_LOAD_FW:
9087 rc = load_fw(sc, (struct t4_data *)data);
9089 case CHELSIO_T4_GET_MEM:
9090 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
9092 case CHELSIO_T4_GET_I2C:
9093 rc = read_i2c(sc, (struct t4_i2c_data *)data);
9095 case CHELSIO_T4_CLEAR_STATS: {
9097 u_int port_id = *(uint32_t *)data;
9098 struct port_info *pi;
9101 if (port_id >= sc->params.nports)
9103 pi = sc->port[port_id];
9108 t4_clr_port_stats(sc, pi->tx_chan);
9109 pi->tx_parse_error = 0;
9110 mtx_lock(&sc->reg_lock);
9111 for_each_vi(pi, v, vi) {
9112 if (vi->flags & VI_INIT_DONE)
9113 t4_clr_vi_stats(sc, vi->viid);
9115 mtx_unlock(&sc->reg_lock);
9118 * Since this command accepts a port, clear stats for
9119 * all VIs on this port.
9121 for_each_vi(pi, v, vi) {
9122 if (vi->flags & VI_INIT_DONE) {
9123 struct sge_rxq *rxq;
9124 struct sge_txq *txq;
9125 struct sge_wrq *wrq;
9127 for_each_rxq(vi, i, rxq) {
9128 #if defined(INET) || defined(INET6)
9129 rxq->lro.lro_queued = 0;
9130 rxq->lro.lro_flushed = 0;
9133 rxq->vlan_extraction = 0;
9136 for_each_txq(vi, i, txq) {
9139 txq->vlan_insertion = 0;
9143 txq->txpkts0_wrs = 0;
9144 txq->txpkts1_wrs = 0;
9145 txq->txpkts0_pkts = 0;
9146 txq->txpkts1_pkts = 0;
9147 mp_ring_reset_stats(txq->r);
9151 /* nothing to clear for each ofld_rxq */
9153 for_each_ofld_txq(vi, i, wrq) {
9154 wrq->tx_wrs_direct = 0;
9155 wrq->tx_wrs_copied = 0;
9159 if (IS_MAIN_VI(vi)) {
9160 wrq = &sc->sge.ctrlq[pi->port_id];
9161 wrq->tx_wrs_direct = 0;
9162 wrq->tx_wrs_copied = 0;
9168 case CHELSIO_T4_SCHED_CLASS:
9169 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
9171 case CHELSIO_T4_SCHED_QUEUE:
9172 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
9174 case CHELSIO_T4_GET_TRACER:
9175 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
9177 case CHELSIO_T4_SET_TRACER:
9178 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
9180 case CHELSIO_T4_LOAD_CFG:
9181 rc = load_cfg(sc, (struct t4_data *)data);
9191 t4_db_full(struct adapter *sc)
9194 CXGBE_UNIMPLEMENTED(__func__);
9198 t4_db_dropped(struct adapter *sc)
9201 CXGBE_UNIMPLEMENTED(__func__);
9206 t4_iscsi_init(struct adapter *sc, u_int tag_mask, const u_int *pgsz_order)
9209 t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask);
9210 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) |
9211 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) |
9212 V_HPZ3(pgsz_order[3]));
9216 toe_capability(struct vi_info *vi, int enable)
9219 struct port_info *pi = vi->pi;
9220 struct adapter *sc = pi->adapter;
9222 ASSERT_SYNCHRONIZED_OP(sc);
9224 if (!is_offload(sc))
9228 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
9229 /* TOE is already enabled. */
9234 * We need the port's queues around so that we're able to send
9235 * and receive CPLs to/from the TOE even if the ifnet for this
9236 * port has never been UP'd administratively.
9238 if (!(vi->flags & VI_INIT_DONE)) {
9239 rc = vi_full_init(vi);
9243 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
9244 rc = vi_full_init(&pi->vi[0]);
9249 if (isset(&sc->offload_map, pi->port_id)) {
9250 /* TOE is enabled on another VI of this port. */
9255 if (!uld_active(sc, ULD_TOM)) {
9256 rc = t4_activate_uld(sc, ULD_TOM);
9259 "You must kldload t4_tom.ko before trying "
9260 "to enable TOE on a cxgbe interface.\n");
9264 KASSERT(sc->tom_softc != NULL,
9265 ("%s: TOM activated but softc NULL", __func__));
9266 KASSERT(uld_active(sc, ULD_TOM),
9267 ("%s: TOM activated but flag not set", __func__));
9270 /* Activate iWARP and iSCSI too, if the modules are loaded. */
9271 if (!uld_active(sc, ULD_IWARP))
9272 (void) t4_activate_uld(sc, ULD_IWARP);
9273 if (!uld_active(sc, ULD_ISCSI))
9274 (void) t4_activate_uld(sc, ULD_ISCSI);
9277 setbit(&sc->offload_map, pi->port_id);
9281 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
9284 KASSERT(uld_active(sc, ULD_TOM),
9285 ("%s: TOM never initialized?", __func__));
9286 clrbit(&sc->offload_map, pi->port_id);
9293 * Add an upper layer driver to the global list.
9296 t4_register_uld(struct uld_info *ui)
9301 sx_xlock(&t4_uld_list_lock);
9302 SLIST_FOREACH(u, &t4_uld_list, link) {
9303 if (u->uld_id == ui->uld_id) {
9309 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
9312 sx_xunlock(&t4_uld_list_lock);
9317 t4_unregister_uld(struct uld_info *ui)
9322 sx_xlock(&t4_uld_list_lock);
9324 SLIST_FOREACH(u, &t4_uld_list, link) {
9326 if (ui->refcount > 0) {
9331 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
9337 sx_xunlock(&t4_uld_list_lock);
9342 t4_activate_uld(struct adapter *sc, int id)
9345 struct uld_info *ui;
9347 ASSERT_SYNCHRONIZED_OP(sc);
9349 if (id < 0 || id > ULD_MAX)
9351 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
9353 sx_slock(&t4_uld_list_lock);
9355 SLIST_FOREACH(ui, &t4_uld_list, link) {
9356 if (ui->uld_id == id) {
9357 if (!(sc->flags & FULL_INIT_DONE)) {
9358 rc = adapter_full_init(sc);
9363 rc = ui->activate(sc);
9365 setbit(&sc->active_ulds, id);
9372 sx_sunlock(&t4_uld_list_lock);
9378 t4_deactivate_uld(struct adapter *sc, int id)
9381 struct uld_info *ui;
9383 ASSERT_SYNCHRONIZED_OP(sc);
9385 if (id < 0 || id > ULD_MAX)
9389 sx_slock(&t4_uld_list_lock);
9391 SLIST_FOREACH(ui, &t4_uld_list, link) {
9392 if (ui->uld_id == id) {
9393 rc = ui->deactivate(sc);
9395 clrbit(&sc->active_ulds, id);
9402 sx_sunlock(&t4_uld_list_lock);
9408 uld_active(struct adapter *sc, int uld_id)
9411 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
9413 return (isset(&sc->active_ulds, uld_id));
9418 * t = ptr to tunable.
9419 * nc = number of CPUs.
9420 * c = compiled in default for that tunable.
9423 calculate_nqueues(int *t, int nc, const int c)
9429 nq = *t < 0 ? -*t : c;
9434 * Come up with reasonable defaults for some of the tunables, provided they're
9435 * not set by the user (in which case we'll use the values as is).
9438 tweak_tunables(void)
9440 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
9442 if (t4_ntxq10g < 1) {
9444 t4_ntxq10g = rss_getnumbuckets();
9446 calculate_nqueues(&t4_ntxq10g, nc, NTXQ_10G);
9450 if (t4_ntxq1g < 1) {
9452 /* XXX: way too many for 1GbE? */
9453 t4_ntxq1g = rss_getnumbuckets();
9455 calculate_nqueues(&t4_ntxq1g, nc, NTXQ_1G);
9459 calculate_nqueues(&t4_ntxq_vi, nc, NTXQ_VI);
9461 if (t4_nrxq10g < 1) {
9463 t4_nrxq10g = rss_getnumbuckets();
9465 calculate_nqueues(&t4_nrxq10g, nc, NRXQ_10G);
9469 if (t4_nrxq1g < 1) {
9471 /* XXX: way too many for 1GbE? */
9472 t4_nrxq1g = rss_getnumbuckets();
9474 calculate_nqueues(&t4_nrxq1g, nc, NRXQ_1G);
9478 calculate_nqueues(&t4_nrxq_vi, nc, NRXQ_VI);
9481 calculate_nqueues(&t4_nofldtxq10g, nc, NOFLDTXQ_10G);
9482 calculate_nqueues(&t4_nofldtxq1g, nc, NOFLDTXQ_1G);
9483 calculate_nqueues(&t4_nofldtxq_vi, nc, NOFLDTXQ_VI);
9484 calculate_nqueues(&t4_nofldrxq10g, nc, NOFLDRXQ_10G);
9485 calculate_nqueues(&t4_nofldrxq1g, nc, NOFLDRXQ_1G);
9486 calculate_nqueues(&t4_nofldrxq_vi, nc, NOFLDRXQ_VI);
9488 if (t4_toecaps_allowed == -1)
9489 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
9491 if (t4_rdmacaps_allowed == -1) {
9492 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
9493 FW_CAPS_CONFIG_RDMA_RDMAC;
9496 if (t4_iscsicaps_allowed == -1) {
9497 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
9498 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
9499 FW_CAPS_CONFIG_ISCSI_T10DIF;
9502 if (t4_toecaps_allowed == -1)
9503 t4_toecaps_allowed = 0;
9505 if (t4_rdmacaps_allowed == -1)
9506 t4_rdmacaps_allowed = 0;
9508 if (t4_iscsicaps_allowed == -1)
9509 t4_iscsicaps_allowed = 0;
9513 calculate_nqueues(&t4_nnmtxq_vi, nc, NNMTXQ_VI);
9514 calculate_nqueues(&t4_nnmrxq_vi, nc, NNMRXQ_VI);
9517 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS)
9518 t4_tmr_idx_10g = TMR_IDX_10G;
9520 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS)
9521 t4_pktc_idx_10g = PKTC_IDX_10G;
9523 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS)
9524 t4_tmr_idx_1g = TMR_IDX_1G;
9526 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS)
9527 t4_pktc_idx_1g = PKTC_IDX_1G;
9529 if (t4_qsize_txq < 128)
9532 if (t4_qsize_rxq < 128)
9534 while (t4_qsize_rxq & 7)
9537 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
9542 t4_dump_tcb(struct adapter *sc, int tid)
9544 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
9546 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
9547 save = t4_read_reg(sc, reg);
9548 base = sc->memwin[2].mw_base;
9550 /* Dump TCB for the tid */
9551 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
9552 tcb_addr += tid * TCB_SIZE;
9556 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
9558 pf = V_PFNUM(sc->pf);
9559 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
9561 t4_write_reg(sc, reg, win_pos | pf);
9562 t4_read_reg(sc, reg);
9564 off = tcb_addr - win_pos;
9565 for (i = 0; i < 4; i++) {
9567 for (j = 0; j < 8; j++, off += 4)
9568 buf[j] = htonl(t4_read_reg(sc, base + off));
9570 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
9571 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
9575 t4_write_reg(sc, reg, save);
9576 t4_read_reg(sc, reg);
9580 t4_dump_devlog(struct adapter *sc)
9582 struct devlog_params *dparams = &sc->params.devlog;
9583 struct fw_devlog_e e;
9584 int i, first, j, m, nentries, rc;
9585 uint64_t ftstamp = UINT64_MAX;
9587 if (dparams->start == 0) {
9588 db_printf("devlog params not valid\n");
9592 nentries = dparams->size / sizeof(struct fw_devlog_e);
9593 m = fwmtype_to_hwmtype(dparams->memtype);
9595 /* Find the first entry. */
9597 for (i = 0; i < nentries && !db_pager_quit; i++) {
9598 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9599 sizeof(e), (void *)&e);
9603 if (e.timestamp == 0)
9606 e.timestamp = be64toh(e.timestamp);
9607 if (e.timestamp < ftstamp) {
9608 ftstamp = e.timestamp;
9618 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9619 sizeof(e), (void *)&e);
9623 if (e.timestamp == 0)
9626 e.timestamp = be64toh(e.timestamp);
9627 e.seqno = be32toh(e.seqno);
9628 for (j = 0; j < 8; j++)
9629 e.params[j] = be32toh(e.params[j]);
9631 db_printf("%10d %15ju %8s %8s ",
9632 e.seqno, e.timestamp,
9633 (e.level < nitems(devlog_level_strings) ?
9634 devlog_level_strings[e.level] : "UNKNOWN"),
9635 (e.facility < nitems(devlog_facility_strings) ?
9636 devlog_facility_strings[e.facility] : "UNKNOWN"));
9637 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
9638 e.params[3], e.params[4], e.params[5], e.params[6],
9641 if (++i == nentries)
9643 } while (i != first && !db_pager_quit);
9646 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
9647 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
9649 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
9656 t = db_read_token();
9658 dev = device_lookup_by_name(db_tok_string);
9663 db_printf("usage: show t4 devlog <nexus>\n");
9668 db_printf("device not found\n");
9672 t4_dump_devlog(device_get_softc(dev));
9675 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
9684 t = db_read_token();
9686 dev = device_lookup_by_name(db_tok_string);
9687 t = db_read_token();
9689 tid = db_tok_number;
9696 db_printf("usage: show t4 tcb <nexus> <tid>\n");
9701 db_printf("device not found\n");
9705 db_printf("invalid tid\n");
9709 t4_dump_tcb(device_get_softc(dev), tid);
9713 static struct sx mlu; /* mod load unload */
9714 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
9717 mod_event(module_t mod, int cmd, void *arg)
9720 static int loaded = 0;
9725 if (loaded++ == 0) {
9727 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl);
9728 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl);
9729 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
9730 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
9731 sx_init(&t4_list_lock, "T4/T5 adapters");
9732 SLIST_INIT(&t4_list);
9734 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
9735 SLIST_INIT(&t4_uld_list);
9737 t4_tracer_modload();
9745 if (--loaded == 0) {
9748 sx_slock(&t4_list_lock);
9749 if (!SLIST_EMPTY(&t4_list)) {
9751 sx_sunlock(&t4_list_lock);
9755 sx_slock(&t4_uld_list_lock);
9756 if (!SLIST_EMPTY(&t4_uld_list)) {
9758 sx_sunlock(&t4_uld_list_lock);
9759 sx_sunlock(&t4_list_lock);
9764 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
9765 uprintf("%ju clusters with custom free routine "
9766 "still is use.\n", t4_sge_extfree_refs());
9767 pause("t4unload", 2 * hz);
9770 sx_sunlock(&t4_uld_list_lock);
9772 sx_sunlock(&t4_list_lock);
9774 if (t4_sge_extfree_refs() == 0) {
9775 t4_tracer_modunload();
9777 sx_destroy(&t4_uld_list_lock);
9779 sx_destroy(&t4_list_lock);
9784 loaded++; /* undo earlier decrement */
9795 static devclass_t t4_devclass, t5_devclass, t6_devclass;
9796 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
9797 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
9799 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
9800 MODULE_VERSION(t4nex, 1);
9801 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
9803 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
9804 MODULE_VERSION(t5nex, 1);
9805 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
9807 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
9808 MODULE_VERSION(t6nex, 1);
9809 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
9811 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
9812 #endif /* DEV_NETMAP */
9814 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
9815 MODULE_VERSION(cxgbe, 1);
9817 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
9818 MODULE_VERSION(cxl, 1);
9820 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
9821 MODULE_VERSION(cc, 1);
9823 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
9824 MODULE_VERSION(vcxgbe, 1);
9826 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
9827 MODULE_VERSION(vcxl, 1);
9829 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
9830 MODULE_VERSION(vcc, 1);