sys/dev/cxgbe/t4_main.c

   1 /*-
   2  * Copyright (c) 2011 Chelsio Communications, Inc.
   3  * All rights reserved.
   4  * Written by: Navdeep Parhar <np@FreeBSD.org>
   5  *
   6  * Redistribution and use in source and binary forms, with or without
   7  * modification, are permitted provided that the following conditions
   8  * are met:
   9  * 1. Redistributions of source code must retain the above copyright
  10  *    notice, this list of conditions and the following disclaimer.
  11  * 2. Redistributions in binary form must reproduce the above copyright
  12  *    notice, this list of conditions and the following disclaimer in the
  13  *    documentation and/or other materials provided with the distribution.
  14  *
  15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  16  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  19  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  20  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  21  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  23  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  24  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  25  * SUCH DAMAGE.
  26  */
  27
  28 #include <sys/cdefs.h>
  29 __FBSDID("$FreeBSD$");
  30
  31 #include "opt_inet.h"
  32 #include "opt_inet6.h"
  33
  34 #include <sys/param.h>
  35 #include <sys/conf.h>
  36 #include <sys/priv.h>
  37 #include <sys/kernel.h>
  38 #include <sys/bus.h>
  39 #include <sys/module.h>
  40 #include <sys/malloc.h>
  41 #include <sys/queue.h>
  42 #include <sys/taskqueue.h>
  43 #include <sys/pciio.h>
  44 #include <dev/pci/pcireg.h>
  45 #include <dev/pci/pcivar.h>
  46 #include <dev/pci/pci_private.h>
  47 #include <sys/firmware.h>
  48 #include <sys/sbuf.h>
  49 #include <sys/smp.h>
  50 #include <sys/socket.h>
  51 #include <sys/sockio.h>
  52 #include <sys/sysctl.h>
  53 #include <net/ethernet.h>
  54 #include <net/if.h>
  55 #include <net/if_types.h>
  56 #include <net/if_dl.h>
  57 #include <net/if_vlan_var.h>
  58 #if defined(__i386__) || defined(__amd64__)
  59 #include <vm/vm.h>
  60 #include <vm/pmap.h>
  61 #endif
  62
  63 #include "common/common.h"
  64 #include "common/t4_msg.h"
  65 #include "common/t4_regs.h"
  66 #include "common/t4_regs_values.h"
  67 #include "t4_ioctl.h"
  68 #include "t4_l2t.h"
  69
  70 /* T4 bus driver interface */
  71 static int t4_probe(device_t);
  72 static int t4_attach(device_t);
  73 static int t4_detach(device_t);
  74 static device_method_t t4_methods[] = {
  75         DEVMETHOD(device_probe,         t4_probe),
  76         DEVMETHOD(device_attach,        t4_attach),
  77         DEVMETHOD(device_detach,        t4_detach),
  78
  79         DEVMETHOD_END
  80 };
  81 static driver_t t4_driver = {
  82         "t4nex",
  83         t4_methods,
  84         sizeof(struct adapter)
  85 };
  86
  87
  88 /* T4 port (cxgbe) interface */
  89 static int cxgbe_probe(device_t);
  90 static int cxgbe_attach(device_t);
  91 static int cxgbe_detach(device_t);
  92 static device_method_t cxgbe_methods[] = {
  93         DEVMETHOD(device_probe,         cxgbe_probe),
  94         DEVMETHOD(device_attach,        cxgbe_attach),
  95         DEVMETHOD(device_detach,        cxgbe_detach),
  96         { 0, 0 }
  97 };
  98 static driver_t cxgbe_driver = {
  99         "cxgbe",
 100         cxgbe_methods,
 101         sizeof(struct port_info)
 102 };
 103
 104 static d_ioctl_t t4_ioctl;
 105 static d_open_t t4_open;
 106 static d_close_t t4_close;
 107
 108 static struct cdevsw t4_cdevsw = {
 109        .d_version = D_VERSION,
 110        .d_flags = 0,
 111        .d_open = t4_open,
 112        .d_close = t4_close,
 113        .d_ioctl = t4_ioctl,
 114        .d_name = "t4nex",
 115 };
 116
 117 /* T5 bus driver interface */
 118 static int t5_probe(device_t);
 119 static device_method_t t5_methods[] = {
 120         DEVMETHOD(device_probe,         t5_probe),
 121         DEVMETHOD(device_attach,        t4_attach),
 122         DEVMETHOD(device_detach,        t4_detach),
 123
 124         DEVMETHOD_END
 125 };
 126 static driver_t t5_driver = {
 127         "t5nex",
 128         t5_methods,
 129         sizeof(struct adapter)
 130 };
 131
 132
 133 /* T5 port (cxl) interface */
 134 static driver_t cxl_driver = {
 135         "cxl",
 136         cxgbe_methods,
 137         sizeof(struct port_info)
 138 };
 139
 140 static struct cdevsw t5_cdevsw = {
 141        .d_version = D_VERSION,
 142        .d_flags = 0,
 143        .d_open = t4_open,
 144        .d_close = t4_close,
 145        .d_ioctl = t4_ioctl,
 146        .d_name = "t5nex",
 147 };
 148
 149 /* ifnet + media interface */
 150 static void cxgbe_init(void *);
 151 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
 152 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
 153 static void cxgbe_qflush(struct ifnet *);
 154 static int cxgbe_media_change(struct ifnet *);
 155 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
 156
 157 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
 158
 159 /*
 160  * Correct lock order when you need to acquire multiple locks is t4_list_lock,
 161  * then ADAPTER_LOCK, then t4_uld_list_lock.
 162  */
 163 static struct sx t4_list_lock;
 164 SLIST_HEAD(, adapter) t4_list;
 165 #ifdef TCP_OFFLOAD
 166 static struct sx t4_uld_list_lock;
 167 SLIST_HEAD(, uld_info) t4_uld_list;
 168 #endif
 169
 170 /*
 171  * Tunables.  See tweak_tunables() too.
 172  *
 173  * Each tunable is set to a default value here if it's known at compile-time.
 174  * Otherwise it is set to -1 as an indication to tweak_tunables() that it should
 175  * provide a reasonable default when the driver is loaded.
 176  *
 177  * Tunables applicable to both T4 and T5 are under hw.cxgbe.  Those specific to
 178  * T5 are under hw.cxl.
 179  */
 180
 181 /*
 182  * Number of queues for tx and rx, 10G and 1G, NIC and offload.
 183  */
 184 #define NTXQ_10G 16
 185 static int t4_ntxq10g = -1;
 186 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g);
 187
 188 #define NRXQ_10G 8
 189 static int t4_nrxq10g = -1;
 190 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g);
 191
 192 #define NTXQ_1G 4
 193 static int t4_ntxq1g = -1;
 194 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g);
 195
 196 #define NRXQ_1G 2
 197 static int t4_nrxq1g = -1;
 198 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g);
 199
 200 static int t4_rsrv_noflowq = 0;
 201 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq);
 202
 203 #ifdef TCP_OFFLOAD
 204 #define NOFLDTXQ_10G 8
 205 static int t4_nofldtxq10g = -1;
 206 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g);
 207
 208 #define NOFLDRXQ_10G 2
 209 static int t4_nofldrxq10g = -1;
 210 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g);
 211
 212 #define NOFLDTXQ_1G 2
 213 static int t4_nofldtxq1g = -1;
 214 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g);
 215
 216 #define NOFLDRXQ_1G 1
 217 static int t4_nofldrxq1g = -1;
 218 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g);
 219 #endif
 220
 221 #ifdef DEV_NETMAP
 222 #define NNMTXQ_10G 2
 223 static int t4_nnmtxq10g = -1;
 224 TUNABLE_INT("hw.cxgbe.nnmtxq10g", &t4_nnmtxq10g);
 225
 226 #define NNMRXQ_10G 2
 227 static int t4_nnmrxq10g = -1;
 228 TUNABLE_INT("hw.cxgbe.nnmrxq10g", &t4_nnmrxq10g);
 229
 230 #define NNMTXQ_1G 1
 231 static int t4_nnmtxq1g = -1;
 232 TUNABLE_INT("hw.cxgbe.nnmtxq1g", &t4_nnmtxq1g);
 233
 234 #define NNMRXQ_1G 1
 235 static int t4_nnmrxq1g = -1;
 236 TUNABLE_INT("hw.cxgbe.nnmrxq1g", &t4_nnmrxq1g);
 237 #endif
 238
 239 /*
 240  * Holdoff parameters for 10G and 1G ports.
 241  */
 242 #define TMR_IDX_10G 1
 243 static int t4_tmr_idx_10g = TMR_IDX_10G;
 244 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g);
 245
 246 #define PKTC_IDX_10G (-1)
 247 static int t4_pktc_idx_10g = PKTC_IDX_10G;
 248 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g);
 249
 250 #define TMR_IDX_1G 1
 251 static int t4_tmr_idx_1g = TMR_IDX_1G;
 252 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g);
 253
 254 #define PKTC_IDX_1G (-1)
 255 static int t4_pktc_idx_1g = PKTC_IDX_1G;
 256 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g);
 257
 258 /*
 259  * Size (# of entries) of each tx and rx queue.
 260  */
 261 static unsigned int t4_qsize_txq = TX_EQ_QSIZE;
 262 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
 263
 264 static unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
 265 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
 266
 267 /*
 268  * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
 269  */
 270 static int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
 271 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
 272
 273 /*
 274  * Configuration file.
 275  */
 276 #define DEFAULT_CF      "default"
 277 #define FLASH_CF        "flash"
 278 #define UWIRE_CF        "uwire"
 279 #define FPGA_CF         "fpga"
 280 static char t4_cfg_file[32] = DEFAULT_CF;
 281 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
 282
 283 /*
 284  * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively).
 285  * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
 286  * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
 287  *            mark or when signalled to do so, 0 to never emit PAUSE.
 288  */
 289 static int t4_pause_settings = PAUSE_TX | PAUSE_RX;
 290 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings);
 291
 292 /*
 293  * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
 294  * encouraged respectively).
 295  */
 296 static unsigned int t4_fw_install = 1;
 297 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install);
 298
 299 /*
 300  * ASIC features that will be used.  Disable the ones you don't want so that the
 301  * chip resources aren't wasted on features that will not be used.
 302  */
 303 static int t4_linkcaps_allowed = 0;     /* No DCBX, PPP, etc. by default */
 304 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
 305
 306 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
 307 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
 308
 309 static int t4_toecaps_allowed = -1;
 310 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
 311
 312 static int t4_rdmacaps_allowed = 0;
 313 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
 314
 315 static int t4_iscsicaps_allowed = 0;
 316 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
 317
 318 static int t4_fcoecaps_allowed = 0;
 319 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
 320
 321 static int t5_write_combine = 0;
 322 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
 323
 324 struct intrs_and_queues {
 325         uint16_t intr_type;     /* INTx, MSI, or MSI-X */
 326         uint16_t nirq;          /* Total # of vectors */
 327         uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */
 328         uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */
 329         uint16_t ntxq10g;       /* # of NIC txq's for each 10G port */
 330         uint16_t nrxq10g;       /* # of NIC rxq's for each 10G port */
 331         uint16_t ntxq1g;        /* # of NIC txq's for each 1G port */
 332         uint16_t nrxq1g;        /* # of NIC rxq's for each 1G port */
 333         uint16_t rsrv_noflowq;  /* Flag whether to reserve queue 0 */
 334 #ifdef TCP_OFFLOAD
 335         uint16_t nofldtxq10g;   /* # of TOE txq's for each 10G port */
 336         uint16_t nofldrxq10g;   /* # of TOE rxq's for each 10G port */
 337         uint16_t nofldtxq1g;    /* # of TOE txq's for each 1G port */
 338         uint16_t nofldrxq1g;    /* # of TOE rxq's for each 1G port */
 339 #endif
 340 #ifdef DEV_NETMAP
 341         uint16_t nnmtxq10g;     /* # of netmap txq's for each 10G port */
 342         uint16_t nnmrxq10g;     /* # of netmap rxq's for each 10G port */
 343         uint16_t nnmtxq1g;      /* # of netmap txq's for each 1G port */
 344         uint16_t nnmrxq1g;      /* # of netmap rxq's for each 1G port */
 345 #endif
 346 };
 347
 348 struct filter_entry {
 349         uint32_t valid:1;       /* filter allocated and valid */
 350         uint32_t locked:1;      /* filter is administratively locked */
 351         uint32_t pending:1;     /* filter action is pending firmware reply */
 352         uint32_t smtidx:8;      /* Source MAC Table index for smac */
 353         struct l2t_entry *l2t;  /* Layer Two Table entry for dmac */
 354
 355         struct t4_filter_specification fs;
 356 };
 357
 358 static int map_bars_0_and_4(struct adapter *);
 359 static int map_bar_2(struct adapter *);
 360 static void setup_memwin(struct adapter *);
 361 static int validate_mem_range(struct adapter *, uint32_t, int);
 362 static int fwmtype_to_hwmtype(int);
 363 static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
 364     uint32_t *);
 365 static void memwin_info(struct adapter *, int, uint32_t *, uint32_t *);
 366 static uint32_t position_memwin(struct adapter *, int, uint32_t);
 367 static int cfg_itype_and_nqueues(struct adapter *, int, int,
 368     struct intrs_and_queues *);
 369 static int prep_firmware(struct adapter *);
 370 static int partition_resources(struct adapter *, const struct firmware *,
 371     const char *);
 372 static int get_params__pre_init(struct adapter *);
 373 static int get_params__post_init(struct adapter *);
 374 static int set_params__post_init(struct adapter *);
 375 static void t4_set_desc(struct adapter *);
 376 static void build_medialist(struct port_info *, struct ifmedia *);
 377 static int cxgbe_init_synchronized(struct port_info *);
 378 static int cxgbe_uninit_synchronized(struct port_info *);
 379 static int setup_intr_handlers(struct adapter *);
 380 static void quiesce_eq(struct adapter *, struct sge_eq *);
 381 static void quiesce_iq(struct adapter *, struct sge_iq *);
 382 static void quiesce_fl(struct adapter *, struct sge_fl *);
 383 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
 384     driver_intr_t *, void *, char *);
 385 static int t4_free_irq(struct adapter *, struct irq *);
 386 static void reg_block_dump(struct adapter *, uint8_t *, unsigned int,
 387     unsigned int);
 388 static void t4_get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
 389 static void cxgbe_tick(void *);
 390 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
 391 static int cpl_not_handled(struct sge_iq *, const struct rss_header *,
 392     struct mbuf *);
 393 static int an_not_handled(struct sge_iq *, const struct rsp_ctrl *);
 394 static int fw_msg_not_handled(struct adapter *, const __be64 *);
 395 static int t4_sysctls(struct adapter *);
 396 static int cxgbe_sysctls(struct port_info *);
 397 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
 398 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
 399 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
 400 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
 401 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
 402 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
 403 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
 404 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
 405 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
 406 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
 407 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
 408 #ifdef SBUF_DRAIN
 409 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
 410 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
 411 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
 412 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
 413 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
 414 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
 415 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
 416 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
 417 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
 418 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
 419 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
 420 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
 421 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
 422 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
 423 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
 424 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
 425 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
 426 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
 427 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
 428 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
 429 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
 430 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
 431 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
 432 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
 433 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
 434 #endif
 435 static inline void txq_start(struct ifnet *, struct sge_txq *);
 436 static uint32_t fconf_to_mode(uint32_t);
 437 static uint32_t mode_to_fconf(uint32_t);
 438 static uint32_t fspec_to_fconf(struct t4_filter_specification *);
 439 static int get_filter_mode(struct adapter *, uint32_t *);
 440 static int set_filter_mode(struct adapter *, uint32_t);
 441 static inline uint64_t get_filter_hits(struct adapter *, uint32_t);
 442 static int get_filter(struct adapter *, struct t4_filter *);
 443 static int set_filter(struct adapter *, struct t4_filter *);
 444 static int del_filter(struct adapter *, struct t4_filter *);
 445 static void clear_filter(struct filter_entry *);
 446 static int set_filter_wr(struct adapter *, int);
 447 static int del_filter_wr(struct adapter *, int);
 448 static int get_sge_context(struct adapter *, struct t4_sge_context *);
 449 static int load_fw(struct adapter *, struct t4_data *);
 450 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
 451 static int read_i2c(struct adapter *, struct t4_i2c_data *);
 452 static int set_sched_class(struct adapter *, struct t4_sched_params *);
 453 static int set_sched_queue(struct adapter *, struct t4_sched_queue *);
 454 #ifdef TCP_OFFLOAD
 455 static int toe_capability(struct port_info *, int);
 456 #endif
 457 static int mod_event(module_t, int, void *);
 458
 459 struct {
 460         uint16_t device;
 461         char *desc;
 462 } t4_pciids[] = {
 463         {0xa000, "Chelsio Terminator 4 FPGA"},
 464         {0x4400, "Chelsio T440-dbg"},
 465         {0x4401, "Chelsio T420-CR"},
 466         {0x4402, "Chelsio T422-CR"},
 467         {0x4403, "Chelsio T440-CR"},
 468         {0x4404, "Chelsio T420-BCH"},
 469         {0x4405, "Chelsio T440-BCH"},
 470         {0x4406, "Chelsio T440-CH"},
 471         {0x4407, "Chelsio T420-SO"},
 472         {0x4408, "Chelsio T420-CX"},
 473         {0x4409, "Chelsio T420-BT"},
 474         {0x440a, "Chelsio T404-BT"},
 475         {0x440e, "Chelsio T440-LP-CR"},
 476 }, t5_pciids[] = {
 477         {0xb000, "Chelsio Terminator 5 FPGA"},
 478         {0x5400, "Chelsio T580-dbg"},
 479         {0x5401,  "Chelsio T520-CR"},           /* 2 x 10G */
 480         {0x5402,  "Chelsio T522-CR"},           /* 2 x 10G, 2 X 1G */
 481         {0x5403,  "Chelsio T540-CR"},           /* 4 x 10G */
 482         {0x5407,  "Chelsio T520-SO"},           /* 2 x 10G, nomem */
 483         {0x5409,  "Chelsio T520-BT"},           /* 2 x 10GBaseT */
 484         {0x540a,  "Chelsio T504-BT"},           /* 4 x 1G */
 485         {0x540d,  "Chelsio T580-CR"},           /* 2 x 40G */
 486         {0x540e,  "Chelsio T540-LP-CR"},        /* 4 x 10G */
 487         {0x5410,  "Chelsio T580-LP-CR"},        /* 2 x 40G */
 488         {0x5411,  "Chelsio T520-LL-CR"},        /* 2 x 10G */
 489         {0x5412,  "Chelsio T560-CR"},           /* 1 x 40G, 2 x 10G */
 490         {0x5414,  "Chelsio T580-LP-SO-CR"},     /* 2 x 40G, nomem */
 491         {0x5415,  "Chelsio T502-BT"},           /* 2 x 1G */
 492 #ifdef notyet
 493         {0x5404,  "Chelsio T520-BCH"},
 494         {0x5405,  "Chelsio T540-BCH"},
 495         {0x5406,  "Chelsio T540-CH"},
 496         {0x5408,  "Chelsio T520-CX"},
 497         {0x540b,  "Chelsio B520-SR"},
 498         {0x540c,  "Chelsio B504-BT"},
 499         {0x540f,  "Chelsio Amsterdam"},
 500         {0x5413,  "Chelsio T580-CHR"},
 501 #endif
 502 };
 503
 504 #ifdef TCP_OFFLOAD
 505 /*
 506  * service_iq() has an iq and needs the fl.  Offset of fl from the iq should be
 507  * exactly the same for both rxq and ofld_rxq.
 508  */
 509 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
 510 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
 511 #endif
 512
 513 /* No easy way to include t4_msg.h before adapter.h so we check this way */
 514 CTASSERT(nitems(((struct adapter *)0)->cpl_handler) == NUM_CPL_CMDS);
 515 CTASSERT(nitems(((struct adapter *)0)->fw_msg_handler) == NUM_FW6_TYPES);
 516
 517 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
 518
 519 static int
 520 t4_probe(device_t dev)
 521 {
 522         int i;
 523         uint16_t v = pci_get_vendor(dev);
 524         uint16_t d = pci_get_device(dev);
 525         uint8_t f = pci_get_function(dev);
 526
 527         if (v != PCI_VENDOR_ID_CHELSIO)
 528                 return (ENXIO);
 529
 530         /* Attach only to PF0 of the FPGA */
 531         if (d == 0xa000 && f != 0)
 532                 return (ENXIO);
 533
 534         for (i = 0; i < nitems(t4_pciids); i++) {
 535                 if (d == t4_pciids[i].device) {
 536                         device_set_desc(dev, t4_pciids[i].desc);
 537                         return (BUS_PROBE_DEFAULT);
 538                 }
 539         }
 540
 541         return (ENXIO);
 542 }
 543
 544 static int
 545 t5_probe(device_t dev)
 546 {
 547         int i;
 548         uint16_t v = pci_get_vendor(dev);
 549         uint16_t d = pci_get_device(dev);
 550         uint8_t f = pci_get_function(dev);
 551
 552         if (v != PCI_VENDOR_ID_CHELSIO)
 553                 return (ENXIO);
 554
 555         /* Attach only to PF0 of the FPGA */
 556         if (d == 0xb000 && f != 0)
 557                 return (ENXIO);
 558
 559         for (i = 0; i < nitems(t5_pciids); i++) {
 560                 if (d == t5_pciids[i].device) {
 561                         device_set_desc(dev, t5_pciids[i].desc);
 562                         return (BUS_PROBE_DEFAULT);
 563                 }
 564         }
 565
 566         return (ENXIO);
 567 }
 568
 569 static int
 570 t4_attach(device_t dev)
 571 {
 572         struct adapter *sc;
 573         int rc = 0, i, n10g, n1g, rqidx, tqidx;
 574         struct intrs_and_queues iaq;
 575         struct sge *s;
 576 #ifdef TCP_OFFLOAD
 577         int ofld_rqidx, ofld_tqidx;
 578 #endif
 579 #ifdef DEV_NETMAP
 580         int nm_rqidx, nm_tqidx;
 581 #endif
 582
 583         sc = device_get_softc(dev);
 584         sc->dev = dev;
 585
 586         pci_enable_busmaster(dev);
 587         if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
 588                 uint32_t v;
 589
 590                 pci_set_max_read_req(dev, 4096);
 591                 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
 592                 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
 593                 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
 594
 595                 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
 596         }
 597
 598         sc->traceq = -1;
 599         mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
 600         snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
 601             device_get_nameunit(dev));
 602
 603         snprintf(sc->lockname, sizeof(sc->lockname), "%s",
 604             device_get_nameunit(dev));
 605         mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
 606         sx_xlock(&t4_list_lock);
 607         SLIST_INSERT_HEAD(&t4_list, sc, link);
 608         sx_xunlock(&t4_list_lock);
 609
 610         mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
 611         TAILQ_INIT(&sc->sfl);
 612         callout_init(&sc->sfl_callout, CALLOUT_MPSAFE);
 613
 614         rc = map_bars_0_and_4(sc);
 615         if (rc != 0)
 616                 goto done; /* error message displayed already */
 617
 618         /*
 619          * This is the real PF# to which we're attaching.  Works from within PCI
 620          * passthrough environments too, where pci_get_function() could return a
 621          * different PF# depending on the passthrough configuration.  We need to
 622          * use the real PF# in all our communication with the firmware.
 623          */
 624         sc->pf = G_SOURCEPF(t4_read_reg(sc, A_PL_WHOAMI));
 625         sc->mbox = sc->pf;
 626
 627         memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
 628         sc->an_handler = an_not_handled;
 629         for (i = 0; i < nitems(sc->cpl_handler); i++)
 630                 sc->cpl_handler[i] = cpl_not_handled;
 631         for (i = 0; i < nitems(sc->fw_msg_handler); i++)
 632                 sc->fw_msg_handler[i] = fw_msg_not_handled;
 633         t4_register_cpl_handler(sc, CPL_SET_TCB_RPL, t4_filter_rpl);
 634         t4_register_cpl_handler(sc, CPL_TRACE_PKT, t4_trace_pkt);
 635         t4_register_cpl_handler(sc, CPL_TRACE_PKT_T5, t5_trace_pkt);
 636         t4_init_sge_cpl_handlers(sc);
 637
 638         /* Prepare the adapter for operation */
 639         rc = -t4_prep_adapter(sc);
 640         if (rc != 0) {
 641                 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
 642                 goto done;
 643         }
 644
 645         /*
 646          * Do this really early, with the memory windows set up even before the
 647          * character device.  The userland tool's register i/o and mem read
 648          * will work even in "recovery mode".
 649          */
 650         setup_memwin(sc);
 651         sc->cdev = make_dev(is_t4(sc) ? &t4_cdevsw : &t5_cdevsw,
 652             device_get_unit(dev), UID_ROOT, GID_WHEEL, 0600, "%s",
 653             device_get_nameunit(dev));
 654         if (sc->cdev == NULL)
 655                 device_printf(dev, "failed to create nexus char device.\n");
 656         else
 657                 sc->cdev->si_drv1 = sc;
 658
 659         /* Go no further if recovery mode has been requested. */
 660         if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
 661                 device_printf(dev, "recovery mode.\n");
 662                 goto done;
 663         }
 664
 665         /* Prepare the firmware for operation */
 666         rc = prep_firmware(sc);
 667         if (rc != 0)
 668                 goto done; /* error message displayed already */
 669
 670         rc = get_params__post_init(sc);
 671         if (rc != 0)
 672                 goto done; /* error message displayed already */
 673
 674         rc = set_params__post_init(sc);
 675         if (rc != 0)
 676                 goto done; /* error message displayed already */
 677
 678         rc = map_bar_2(sc);
 679         if (rc != 0)
 680                 goto done; /* error message displayed already */
 681
 682         rc = t4_create_dma_tag(sc);
 683         if (rc != 0)
 684                 goto done; /* error message displayed already */
 685
 686         /*
 687          * First pass over all the ports - allocate VIs and initialize some
 688          * basic parameters like mac address, port type, etc.  We also figure
 689          * out whether a port is 10G or 1G and use that information when
 690          * calculating how many interrupts to attempt to allocate.
 691          */
 692         n10g = n1g = 0;
 693         for_each_port(sc, i) {
 694                 struct port_info *pi;
 695
 696                 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
 697                 sc->port[i] = pi;
 698
 699                 /* These must be set before t4_port_init */
 700                 pi->adapter = sc;
 701                 pi->port_id = i;
 702
 703                 /* Allocate the vi and initialize parameters like mac addr */
 704                 rc = -t4_port_init(pi, sc->mbox, sc->pf, 0);
 705                 if (rc != 0) {
 706                         device_printf(dev, "unable to initialize port %d: %d\n",
 707                             i, rc);
 708                         free(pi, M_CXGBE);
 709                         sc->port[i] = NULL;
 710                         goto done;
 711                 }
 712
 713                 pi->link_cfg.requested_fc &= ~(PAUSE_TX | PAUSE_RX);
 714                 pi->link_cfg.requested_fc |= t4_pause_settings;
 715                 pi->link_cfg.fc &= ~(PAUSE_TX | PAUSE_RX);
 716                 pi->link_cfg.fc |= t4_pause_settings;
 717
 718                 rc = -t4_link_start(sc, sc->mbox, pi->tx_chan, &pi->link_cfg);
 719                 if (rc != 0) {
 720                         device_printf(dev, "port %d l1cfg failed: %d\n", i, rc);
 721                         free(pi, M_CXGBE);
 722                         sc->port[i] = NULL;
 723                         goto done;
 724                 }
 725
 726                 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
 727                     device_get_nameunit(dev), i);
 728                 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
 729                 sc->chan_map[pi->tx_chan] = i;
 730
 731                 if (is_10G_port(pi) || is_40G_port(pi)) {
 732                         n10g++;
 733                         pi->tmr_idx = t4_tmr_idx_10g;
 734                         pi->pktc_idx = t4_pktc_idx_10g;
 735                 } else {
 736                         n1g++;
 737                         pi->tmr_idx = t4_tmr_idx_1g;
 738                         pi->pktc_idx = t4_pktc_idx_1g;
 739                 }
 740
 741                 pi->xact_addr_filt = -1;
 742                 pi->linkdnrc = -1;
 743
 744                 pi->qsize_rxq = t4_qsize_rxq;
 745                 pi->qsize_txq = t4_qsize_txq;
 746
 747                 pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbe" : "cxl", -1);
 748                 if (pi->dev == NULL) {
 749                         device_printf(dev,
 750                             "failed to add device for port %d.\n", i);
 751                         rc = ENXIO;
 752                         goto done;
 753                 }
 754                 device_set_softc(pi->dev, pi);
 755         }
 756
 757         /*
 758          * Interrupt type, # of interrupts, # of rx/tx queues, etc.
 759          */
 760         rc = cfg_itype_and_nqueues(sc, n10g, n1g, &iaq);
 761         if (rc != 0)
 762                 goto done; /* error message displayed already */
 763
 764         sc->intr_type = iaq.intr_type;
 765         sc->intr_count = iaq.nirq;
 766
 767         s = &sc->sge;
 768         s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
 769         s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
 770         s->neq = s->ntxq + s->nrxq;     /* the free list in an rxq is an eq */
 771         s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
 772         s->niq = s->nrxq + 1;           /* 1 extra for firmware event queue */
 773 #ifdef TCP_OFFLOAD
 774         if (is_offload(sc)) {
 775                 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g;
 776                 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g;
 777                 s->neq += s->nofldtxq + s->nofldrxq;
 778                 s->niq += s->nofldrxq;
 779
 780                 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
 781                     M_CXGBE, M_ZERO | M_WAITOK);
 782                 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
 783                     M_CXGBE, M_ZERO | M_WAITOK);
 784         }
 785 #endif
 786 #ifdef DEV_NETMAP
 787         s->nnmrxq = n10g * iaq.nnmrxq10g + n1g * iaq.nnmrxq1g;
 788         s->nnmtxq = n10g * iaq.nnmtxq10g + n1g * iaq.nnmtxq1g;
 789         s->neq += s->nnmtxq + s->nnmrxq;
 790         s->niq += s->nnmrxq;
 791
 792         s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
 793             M_CXGBE, M_ZERO | M_WAITOK);
 794         s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
 795             M_CXGBE, M_ZERO | M_WAITOK);
 796 #endif
 797
 798         s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE,
 799             M_ZERO | M_WAITOK);
 800         s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
 801             M_ZERO | M_WAITOK);
 802         s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
 803             M_ZERO | M_WAITOK);
 804         s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
 805             M_ZERO | M_WAITOK);
 806         s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
 807             M_ZERO | M_WAITOK);
 808
 809         sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
 810             M_ZERO | M_WAITOK);
 811
 812         t4_init_l2t(sc, M_WAITOK);
 813
 814         /*
 815          * Second pass over the ports.  This time we know the number of rx and
 816          * tx queues that each port should get.
 817          */
 818         rqidx = tqidx = 0;
 819 #ifdef TCP_OFFLOAD
 820         ofld_rqidx = ofld_tqidx = 0;
 821 #endif
 822 #ifdef DEV_NETMAP
 823         nm_rqidx = nm_tqidx = 0;
 824 #endif
 825         for_each_port(sc, i) {
 826                 struct port_info *pi = sc->port[i];
 827
 828                 if (pi == NULL)
 829                         continue;
 830
 831                 pi->first_rxq = rqidx;
 832                 pi->first_txq = tqidx;
 833                 if (is_10G_port(pi) || is_40G_port(pi)) {
 834                         pi->flags |= iaq.intr_flags_10g;
 835                         pi->nrxq = iaq.nrxq10g;
 836                         pi->ntxq = iaq.ntxq10g;
 837                 } else {
 838                         pi->flags |= iaq.intr_flags_1g;
 839                         pi->nrxq = iaq.nrxq1g;
 840                         pi->ntxq = iaq.ntxq1g;
 841                 }
 842
 843                 if (pi->ntxq > 1)
 844                         pi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0;
 845                 else
 846                         pi->rsrv_noflowq = 0;
 847
 848                 rqidx += pi->nrxq;
 849                 tqidx += pi->ntxq;
 850 #ifdef TCP_OFFLOAD
 851                 if (is_offload(sc)) {
 852                         pi->first_ofld_rxq = ofld_rqidx;
 853                         pi->first_ofld_txq = ofld_tqidx;
 854                         if (is_10G_port(pi) || is_40G_port(pi)) {
 855                                 pi->nofldrxq = iaq.nofldrxq10g;
 856                                 pi->nofldtxq = iaq.nofldtxq10g;
 857                         } else {
 858                                 pi->nofldrxq = iaq.nofldrxq1g;
 859                                 pi->nofldtxq = iaq.nofldtxq1g;
 860                         }
 861                         ofld_rqidx += pi->nofldrxq;
 862                         ofld_tqidx += pi->nofldtxq;
 863                 }
 864 #endif
 865 #ifdef DEV_NETMAP
 866                 pi->first_nm_rxq = nm_rqidx;
 867                 pi->first_nm_txq = nm_tqidx;
 868                 if (is_10G_port(pi) || is_40G_port(pi)) {
 869                         pi->nnmrxq = iaq.nnmrxq10g;
 870                         pi->nnmtxq = iaq.nnmtxq10g;
 871                 } else {
 872                         pi->nnmrxq = iaq.nnmrxq1g;
 873                         pi->nnmtxq = iaq.nnmtxq1g;
 874                 }
 875                 nm_rqidx += pi->nnmrxq;
 876                 nm_tqidx += pi->nnmtxq;
 877 #endif
 878         }
 879
 880         rc = setup_intr_handlers(sc);
 881         if (rc != 0) {
 882                 device_printf(dev,
 883                     "failed to setup interrupt handlers: %d\n", rc);
 884                 goto done;
 885         }
 886
 887         rc = bus_generic_attach(dev);
 888         if (rc != 0) {
 889                 device_printf(dev,
 890                     "failed to attach all child ports: %d\n", rc);
 891                 goto done;
 892         }
 893
 894         device_printf(dev,
 895             "PCIe x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
 896             sc->params.pci.width, sc->params.nports, sc->intr_count,
 897             sc->intr_type == INTR_MSIX ? "MSI-X" :
 898             (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
 899             sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
 900
 901         t4_set_desc(sc);
 902
 903 done:
 904         if (rc != 0 && sc->cdev) {
 905                 /* cdev was created and so cxgbetool works; recover that way. */
 906                 device_printf(dev,
 907                     "error during attach, adapter is now in recovery mode.\n");
 908                 rc = 0;
 909         }
 910
 911         if (rc != 0)
 912                 t4_detach(dev);
 913         else
 914                 t4_sysctls(sc);
 915
 916         return (rc);
 917 }
 918
 919 /*
 920  * Idempotent
 921  */
 922 static int
 923 t4_detach(device_t dev)
 924 {
 925         struct adapter *sc;
 926         struct port_info *pi;
 927         int i, rc;
 928
 929         sc = device_get_softc(dev);
 930
 931         if (sc->flags & FULL_INIT_DONE)
 932                 t4_intr_disable(sc);
 933
 934         if (sc->cdev) {
 935                 destroy_dev(sc->cdev);
 936                 sc->cdev = NULL;
 937         }
 938
 939         rc = bus_generic_detach(dev);
 940         if (rc) {
 941                 device_printf(dev,
 942                     "failed to detach child devices: %d\n", rc);
 943                 return (rc);
 944         }
 945
 946         for (i = 0; i < sc->intr_count; i++)
 947                 t4_free_irq(sc, &sc->irq[i]);
 948
 949         for (i = 0; i < MAX_NPORTS; i++) {
 950                 pi = sc->port[i];
 951                 if (pi) {
 952                         t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->viid);
 953                         if (pi->dev)
 954                                 device_delete_child(dev, pi->dev);
 955
 956                         mtx_destroy(&pi->pi_lock);
 957                         free(pi, M_CXGBE);
 958                 }
 959         }
 960
 961         if (sc->flags & FULL_INIT_DONE)
 962                 adapter_full_uninit(sc);
 963
 964         if (sc->flags & FW_OK)
 965                 t4_fw_bye(sc, sc->mbox);
 966
 967         if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
 968                 pci_release_msi(dev);
 969
 970         if (sc->regs_res)
 971                 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
 972                     sc->regs_res);
 973
 974         if (sc->udbs_res)
 975                 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
 976                     sc->udbs_res);
 977
 978         if (sc->msix_res)
 979                 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
 980                     sc->msix_res);
 981
 982         if (sc->l2t)
 983                 t4_free_l2t(sc->l2t);
 984
 985 #ifdef TCP_OFFLOAD
 986         free(sc->sge.ofld_rxq, M_CXGBE);
 987         free(sc->sge.ofld_txq, M_CXGBE);
 988 #endif
 989 #ifdef DEV_NETMAP
 990         free(sc->sge.nm_rxq, M_CXGBE);
 991         free(sc->sge.nm_txq, M_CXGBE);
 992 #endif
 993         free(sc->irq, M_CXGBE);
 994         free(sc->sge.rxq, M_CXGBE);
 995         free(sc->sge.txq, M_CXGBE);
 996         free(sc->sge.ctrlq, M_CXGBE);
 997         free(sc->sge.iqmap, M_CXGBE);
 998         free(sc->sge.eqmap, M_CXGBE);
 999         free(sc->tids.ftid_tab, M_CXGBE);
1000         t4_destroy_dma_tag(sc);
1001         if (mtx_initialized(&sc->sc_lock)) {
1002                 sx_xlock(&t4_list_lock);
1003                 SLIST_REMOVE(&t4_list, sc, adapter, link);
1004                 sx_xunlock(&t4_list_lock);
1005                 mtx_destroy(&sc->sc_lock);
1006         }
1007
1008         if (mtx_initialized(&sc->tids.ftid_lock))
1009                 mtx_destroy(&sc->tids.ftid_lock);
1010         if (mtx_initialized(&sc->sfl_lock))
1011                 mtx_destroy(&sc->sfl_lock);
1012         if (mtx_initialized(&sc->ifp_lock))
1013                 mtx_destroy(&sc->ifp_lock);
1014
1015         bzero(sc, sizeof(*sc));
1016
1017         return (0);
1018 }
1019
1020 static int
1021 cxgbe_probe(device_t dev)
1022 {
1023         char buf[128];
1024         struct port_info *pi = device_get_softc(dev);
1025
1026         snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1027         device_set_desc_copy(dev, buf);
1028
1029         return (BUS_PROBE_DEFAULT);
1030 }
1031
1032 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1033     IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1034     IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1035 #define T4_CAP_ENABLE (T4_CAP)
1036
1037 static int
1038 cxgbe_attach(device_t dev)
1039 {
1040         struct port_info *pi = device_get_softc(dev);
1041         struct ifnet *ifp;
1042         char *s;
1043         int n, o;
1044
1045         /* Allocate an ifnet and set it up */
1046         ifp = if_alloc(IFT_ETHER);
1047         if (ifp == NULL) {
1048                 device_printf(dev, "Cannot allocate ifnet\n");
1049                 return (ENOMEM);
1050         }
1051         pi->ifp = ifp;
1052         ifp->if_softc = pi;
1053
1054         callout_init(&pi->tick, CALLOUT_MPSAFE);
1055
1056         if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1057         ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1058
1059         ifp->if_init = cxgbe_init;
1060         ifp->if_ioctl = cxgbe_ioctl;
1061         ifp->if_transmit = cxgbe_transmit;
1062         ifp->if_qflush = cxgbe_qflush;
1063
1064         ifp->if_capabilities = T4_CAP;
1065 #ifdef TCP_OFFLOAD
1066         if (is_offload(pi->adapter))
1067                 ifp->if_capabilities |= IFCAP_TOE;
1068 #endif
1069         ifp->if_capenable = T4_CAP_ENABLE;
1070         ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1071             CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1072
1073         ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1074         ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS;
1075         ifp->if_hw_tsomaxsegsize = 65536;
1076
1077         /* Initialize ifmedia for this port */
1078         ifmedia_init(&pi->media, IFM_IMASK, cxgbe_media_change,
1079             cxgbe_media_status);
1080         build_medialist(pi, &pi->media);
1081
1082         pi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1083             EVENTHANDLER_PRI_ANY);
1084
1085         ether_ifattach(ifp, pi->hw_addr);
1086
1087         n = 128;
1088         s = malloc(n, M_CXGBE, M_WAITOK);
1089         o = snprintf(s, n, "%d txq, %d rxq (NIC)", pi->ntxq, pi->nrxq);
1090         MPASS(n > o);
1091 #ifdef TCP_OFFLOAD
1092         if (is_offload(pi->adapter)) {
1093                 o += snprintf(s + o, n - o, "; %d txq, %d rxq (TOE)",
1094                     pi->nofldtxq, pi->nofldrxq);
1095                 MPASS(n > o);
1096         }
1097 #endif
1098 #ifdef DEV_NETMAP
1099         o += snprintf(s + o, n - o, "; %d txq, %d rxq (netmap)", pi->nnmtxq,
1100             pi->nnmrxq);
1101         MPASS(n > o);
1102 #endif
1103         device_printf(dev, "%s\n", s);
1104         free(s, M_CXGBE);
1105
1106 #ifdef DEV_NETMAP
1107         /* nm_media handled here to keep implementation private to this file */
1108         ifmedia_init(&pi->nm_media, IFM_IMASK, cxgbe_media_change,
1109             cxgbe_media_status);
1110         build_medialist(pi, &pi->nm_media);
1111         create_netmap_ifnet(pi);        /* logs errors it something fails */
1112 #endif
1113         cxgbe_sysctls(pi);
1114
1115         return (0);
1116 }
1117
1118 static int
1119 cxgbe_detach(device_t dev)
1120 {
1121         struct port_info *pi = device_get_softc(dev);
1122         struct adapter *sc = pi->adapter;
1123         struct ifnet *ifp = pi->ifp;
1124
1125         /* Tell if_ioctl and if_init that the port is going away */
1126         ADAPTER_LOCK(sc);
1127         SET_DOOMED(pi);
1128         wakeup(&sc->flags);
1129         while (IS_BUSY(sc))
1130                 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
1131         SET_BUSY(sc);
1132 #ifdef INVARIANTS
1133         sc->last_op = "t4detach";
1134         sc->last_op_thr = curthread;
1135 #endif
1136         ADAPTER_UNLOCK(sc);
1137
1138         if (pi->flags & HAS_TRACEQ) {
1139                 sc->traceq = -1;        /* cloner should not create ifnet */
1140                 t4_tracer_port_detach(sc);
1141         }
1142
1143         if (pi->vlan_c)
1144                 EVENTHANDLER_DEREGISTER(vlan_config, pi->vlan_c);
1145
1146         PORT_LOCK(pi);
1147         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1148         callout_stop(&pi->tick);
1149         PORT_UNLOCK(pi);
1150         callout_drain(&pi->tick);
1151
1152         /* Let detach proceed even if these fail. */
1153         cxgbe_uninit_synchronized(pi);
1154         port_full_uninit(pi);
1155
1156         ifmedia_removeall(&pi->media);
1157         ether_ifdetach(pi->ifp);
1158         if_free(pi->ifp);
1159
1160 #ifdef DEV_NETMAP
1161         /* XXXNM: equivalent of cxgbe_uninit_synchronized to ifdown nm_ifp */
1162         destroy_netmap_ifnet(pi);
1163 #endif
1164
1165         ADAPTER_LOCK(sc);
1166         CLR_BUSY(sc);
1167         wakeup(&sc->flags);
1168         ADAPTER_UNLOCK(sc);
1169
1170         return (0);
1171 }
1172
1173 static void
1174 cxgbe_init(void *arg)
1175 {
1176         struct port_info *pi = arg;
1177         struct adapter *sc = pi->adapter;
1178
1179         if (begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4init") != 0)
1180                 return;
1181         cxgbe_init_synchronized(pi);
1182         end_synchronized_op(sc, 0);
1183 }
1184
1185 static int
1186 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1187 {
1188         int rc = 0, mtu, flags, can_sleep;
1189         struct port_info *pi = ifp->if_softc;
1190         struct adapter *sc = pi->adapter;
1191         struct ifreq *ifr = (struct ifreq *)data;
1192         uint32_t mask;
1193
1194         switch (cmd) {
1195         case SIOCSIFMTU:
1196                 mtu = ifr->ifr_mtu;
1197                 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO))
1198                         return (EINVAL);
1199
1200                 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4mtu");
1201                 if (rc)
1202                         return (rc);
1203                 ifp->if_mtu = mtu;
1204                 if (pi->flags & PORT_INIT_DONE) {
1205                         t4_update_fl_bufsize(ifp);
1206                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1207                                 rc = update_mac_settings(ifp, XGMAC_MTU);
1208                 }
1209                 end_synchronized_op(sc, 0);
1210                 break;
1211
1212         case SIOCSIFFLAGS:
1213                 can_sleep = 0;
1214 redo_sifflags:
1215                 rc = begin_synchronized_op(sc, pi,
1216                     can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg");
1217                 if (rc)
1218                         return (rc);
1219
1220                 if (ifp->if_flags & IFF_UP) {
1221                         if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1222                                 flags = pi->if_flags;
1223                                 if ((ifp->if_flags ^ flags) &
1224                                     (IFF_PROMISC | IFF_ALLMULTI)) {
1225                                         if (can_sleep == 1) {
1226                                                 end_synchronized_op(sc, 0);
1227                                                 can_sleep = 0;
1228                                                 goto redo_sifflags;
1229                                         }
1230                                         rc = update_mac_settings(ifp,
1231                                             XGMAC_PROMISC | XGMAC_ALLMULTI);
1232                                 }
1233                         } else {
1234                                 if (can_sleep == 0) {
1235                                         end_synchronized_op(sc, LOCK_HELD);
1236                                         can_sleep = 1;
1237                                         goto redo_sifflags;
1238                                 }
1239                                 rc = cxgbe_init_synchronized(pi);
1240                         }
1241                         pi->if_flags = ifp->if_flags;
1242                 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1243                         if (can_sleep == 0) {
1244                                 end_synchronized_op(sc, LOCK_HELD);
1245                                 can_sleep = 1;
1246                                 goto redo_sifflags;
1247                         }
1248                         rc = cxgbe_uninit_synchronized(pi);
1249                 }
1250                 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD);
1251                 break;
1252
1253         case SIOCADDMULTI:
1254         case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1255                 rc = begin_synchronized_op(sc, pi, HOLD_LOCK, "t4multi");
1256                 if (rc)
1257                         return (rc);
1258                 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1259                         rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1260                 end_synchronized_op(sc, LOCK_HELD);
1261                 break;
1262
1263         case SIOCSIFCAP:
1264                 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4cap");
1265                 if (rc)
1266                         return (rc);
1267
1268                 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1269                 if (mask & IFCAP_TXCSUM) {
1270                         ifp->if_capenable ^= IFCAP_TXCSUM;
1271                         ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1272
1273                         if (IFCAP_TSO4 & ifp->if_capenable &&
1274                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
1275                                 ifp->if_capenable &= ~IFCAP_TSO4;
1276                                 if_printf(ifp,
1277                                     "tso4 disabled due to -txcsum.\n");
1278                         }
1279                 }
1280                 if (mask & IFCAP_TXCSUM_IPV6) {
1281                         ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1282                         ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1283
1284                         if (IFCAP_TSO6 & ifp->if_capenable &&
1285                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1286                                 ifp->if_capenable &= ~IFCAP_TSO6;
1287                                 if_printf(ifp,
1288                                     "tso6 disabled due to -txcsum6.\n");
1289                         }
1290                 }
1291                 if (mask & IFCAP_RXCSUM)
1292                         ifp->if_capenable ^= IFCAP_RXCSUM;
1293                 if (mask & IFCAP_RXCSUM_IPV6)
1294                         ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1295
1296                 /*
1297                  * Note that we leave CSUM_TSO alone (it is always set).  The
1298                  * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1299                  * sending a TSO request our way, so it's sufficient to toggle
1300                  * IFCAP_TSOx only.
1301                  */
1302                 if (mask & IFCAP_TSO4) {
1303                         if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1304                             !(IFCAP_TXCSUM & ifp->if_capenable)) {
1305                                 if_printf(ifp, "enable txcsum first.\n");
1306                                 rc = EAGAIN;
1307                                 goto fail;
1308                         }
1309                         ifp->if_capenable ^= IFCAP_TSO4;
1310                 }
1311                 if (mask & IFCAP_TSO6) {
1312                         if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1313                             !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1314                                 if_printf(ifp, "enable txcsum6 first.\n");
1315                                 rc = EAGAIN;
1316                                 goto fail;
1317                         }
1318                         ifp->if_capenable ^= IFCAP_TSO6;
1319                 }
1320                 if (mask & IFCAP_LRO) {
1321 #if defined(INET) || defined(INET6)
1322                         int i;
1323                         struct sge_rxq *rxq;
1324
1325                         ifp->if_capenable ^= IFCAP_LRO;
1326                         for_each_rxq(pi, i, rxq) {
1327                                 if (ifp->if_capenable & IFCAP_LRO)
1328                                         rxq->iq.flags |= IQ_LRO_ENABLED;
1329                                 else
1330                                         rxq->iq.flags &= ~IQ_LRO_ENABLED;
1331                         }
1332 #endif
1333                 }
1334 #ifdef TCP_OFFLOAD
1335                 if (mask & IFCAP_TOE) {
1336                         int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1337
1338                         rc = toe_capability(pi, enable);
1339                         if (rc != 0)
1340                                 goto fail;
1341
1342                         ifp->if_capenable ^= mask;
1343                 }
1344 #endif
1345                 if (mask & IFCAP_VLAN_HWTAGGING) {
1346                         ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1347                         if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1348                                 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1349                 }
1350                 if (mask & IFCAP_VLAN_MTU) {
1351                         ifp->if_capenable ^= IFCAP_VLAN_MTU;
1352
1353                         /* Need to find out how to disable auto-mtu-inflation */
1354                 }
1355                 if (mask & IFCAP_VLAN_HWTSO)
1356                         ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1357                 if (mask & IFCAP_VLAN_HWCSUM)
1358                         ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1359
1360 #ifdef VLAN_CAPABILITIES
1361                 VLAN_CAPABILITIES(ifp);
1362 #endif
1363 fail:
1364                 end_synchronized_op(sc, 0);
1365                 break;
1366
1367         case SIOCSIFMEDIA:
1368         case SIOCGIFMEDIA:
1369                 ifmedia_ioctl(ifp, ifr, &pi->media, cmd);
1370                 break;
1371
1372         default:
1373                 rc = ether_ioctl(ifp, cmd, data);
1374         }
1375
1376         return (rc);
1377 }
1378
1379 static int
1380 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1381 {
1382         struct port_info *pi = ifp->if_softc;
1383         struct adapter *sc = pi->adapter;
1384         struct sge_txq *txq = &sc->sge.txq[pi->first_txq];
1385         struct buf_ring *br;
1386         int rc;
1387
1388         M_ASSERTPKTHDR(m);
1389
1390         if (__predict_false(pi->link_cfg.link_ok == 0)) {
1391                 m_freem(m);
1392                 return (ENETDOWN);
1393         }
1394
1395         /* check if flowid is set */
1396         if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
1397                 txq += ((m->m_pkthdr.flowid % (pi->ntxq - pi->rsrv_noflowq))
1398                     + pi->rsrv_noflowq);
1399         br = txq->br;
1400
1401         if (TXQ_TRYLOCK(txq) == 0) {
1402                 struct sge_eq *eq = &txq->eq;
1403
1404                 /*
1405                  * It is possible that t4_eth_tx finishes up and releases the
1406                  * lock between the TRYLOCK above and the drbr_enqueue here.  We
1407                  * need to make sure that this mbuf doesn't just sit there in
1408                  * the drbr.
1409                  */
1410
1411                 rc = drbr_enqueue(ifp, br, m);
1412                 if (rc == 0 && callout_pending(&eq->tx_callout) == 0 &&
1413                     !(eq->flags & EQ_DOOMED))
1414                         callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq);
1415                 return (rc);
1416         }
1417
1418         /*
1419          * txq->m is the mbuf that is held up due to a temporary shortage of
1420          * resources and it should be put on the wire first.  Then what's in
1421          * drbr and finally the mbuf that was just passed in to us.
1422          *
1423          * Return code should indicate the fate of the mbuf that was passed in
1424          * this time.
1425          */
1426
1427         TXQ_LOCK_ASSERT_OWNED(txq);
1428         if (drbr_needs_enqueue(ifp, br) || txq->m) {
1429
1430                 /* Queued for transmission. */
1431
1432                 rc = drbr_enqueue(ifp, br, m);
1433                 m = txq->m ? txq->m : drbr_dequeue(ifp, br);
1434                 (void) t4_eth_tx(ifp, txq, m);
1435                 TXQ_UNLOCK(txq);
1436                 return (rc);
1437         }
1438
1439         /* Direct transmission. */
1440         rc = t4_eth_tx(ifp, txq, m);
1441         if (rc != 0 && txq->m)
1442                 rc = 0; /* held, will be transmitted soon (hopefully) */
1443
1444         TXQ_UNLOCK(txq);
1445         return (rc);
1446 }
1447
1448 static void
1449 cxgbe_qflush(struct ifnet *ifp)
1450 {
1451         struct port_info *pi = ifp->if_softc;
1452         struct sge_txq *txq;
1453         int i;
1454         struct mbuf *m;
1455
1456         /* queues do not exist if !PORT_INIT_DONE. */
1457         if (pi->flags & PORT_INIT_DONE) {
1458                 for_each_txq(pi, i, txq) {
1459                         TXQ_LOCK(txq);
1460                         m_freem(txq->m);
1461                         txq->m = NULL;
1462                         while ((m = buf_ring_dequeue_sc(txq->br)) != NULL)
1463                                 m_freem(m);
1464                         TXQ_UNLOCK(txq);
1465                 }
1466         }
1467         if_qflush(ifp);
1468 }
1469
1470 static int
1471 cxgbe_media_change(struct ifnet *ifp)
1472 {
1473         struct port_info *pi = ifp->if_softc;
1474
1475         device_printf(pi->dev, "%s unimplemented.\n", __func__);
1476
1477         return (EOPNOTSUPP);
1478 }
1479
1480 static void
1481 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1482 {
1483         struct port_info *pi = ifp->if_softc;
1484         struct ifmedia *media = NULL;
1485         struct ifmedia_entry *cur;
1486         int speed = pi->link_cfg.speed;
1487 #ifdef INVARIANTS
1488         int data = (pi->port_type << 8) | pi->mod_type;
1489 #endif
1490
1491         if (ifp == pi->ifp)
1492                 media = &pi->media;
1493 #ifdef DEV_NETMAP
1494         else if (ifp == pi->nm_ifp)
1495                 media = &pi->nm_media;
1496 #endif
1497         MPASS(media != NULL);
1498
1499         cur = media->ifm_cur;
1500         MPASS(cur->ifm_data == data);
1501
1502         ifmr->ifm_status = IFM_AVALID;
1503         if (!pi->link_cfg.link_ok)
1504                 return;
1505
1506         ifmr->ifm_status |= IFM_ACTIVE;
1507
1508         /* active and current will differ iff current media is autoselect. */
1509         if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO)
1510                 return;
1511
1512         ifmr->ifm_active = IFM_ETHER | IFM_FDX;
1513         if (speed == SPEED_10000)
1514                 ifmr->ifm_active |= IFM_10G_T;
1515         else if (speed == SPEED_1000)
1516                 ifmr->ifm_active |= IFM_1000_T;
1517         else if (speed == SPEED_100)
1518                 ifmr->ifm_active |= IFM_100_TX;
1519         else if (speed == SPEED_10)
1520                 ifmr->ifm_active |= IFM_10_T;
1521         else
1522                 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__,
1523                             speed));
1524 }
1525
1526 void
1527 t4_fatal_err(struct adapter *sc)
1528 {
1529         t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
1530         t4_intr_disable(sc);
1531         log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
1532             device_get_nameunit(sc->dev));
1533 }
1534
1535 static int
1536 map_bars_0_and_4(struct adapter *sc)
1537 {
1538         sc->regs_rid = PCIR_BAR(0);
1539         sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1540             &sc->regs_rid, RF_ACTIVE);
1541         if (sc->regs_res == NULL) {
1542                 device_printf(sc->dev, "cannot map registers.\n");
1543                 return (ENXIO);
1544         }
1545         sc->bt = rman_get_bustag(sc->regs_res);
1546         sc->bh = rman_get_bushandle(sc->regs_res);
1547         sc->mmio_len = rman_get_size(sc->regs_res);
1548         setbit(&sc->doorbells, DOORBELL_KDB);
1549
1550         sc->msix_rid = PCIR_BAR(4);
1551         sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1552             &sc->msix_rid, RF_ACTIVE);
1553         if (sc->msix_res == NULL) {
1554                 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
1555                 return (ENXIO);
1556         }
1557
1558         return (0);
1559 }
1560
1561 static int
1562 map_bar_2(struct adapter *sc)
1563 {
1564
1565         /*
1566          * T4: only iWARP driver uses the userspace doorbells.  There is no need
1567          * to map it if RDMA is disabled.
1568          */
1569         if (is_t4(sc) && sc->rdmacaps == 0)
1570                 return (0);
1571
1572         sc->udbs_rid = PCIR_BAR(2);
1573         sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1574             &sc->udbs_rid, RF_ACTIVE);
1575         if (sc->udbs_res == NULL) {
1576                 device_printf(sc->dev, "cannot map doorbell BAR.\n");
1577                 return (ENXIO);
1578         }
1579         sc->udbs_base = rman_get_virtual(sc->udbs_res);
1580
1581         if (is_t5(sc)) {
1582                 setbit(&sc->doorbells, DOORBELL_UDB);
1583 #if defined(__i386__) || defined(__amd64__)
1584                 if (t5_write_combine) {
1585                         int rc;
1586
1587                         /*
1588                          * Enable write combining on BAR2.  This is the
1589                          * userspace doorbell BAR and is split into 128B
1590                          * (UDBS_SEG_SIZE) doorbell regions, each associated
1591                          * with an egress queue.  The first 64B has the doorbell
1592                          * and the second 64B can be used to submit a tx work
1593                          * request with an implicit doorbell.
1594                          */
1595
1596                         rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
1597                             rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
1598                         if (rc == 0) {
1599                                 clrbit(&sc->doorbells, DOORBELL_UDB);
1600                                 setbit(&sc->doorbells, DOORBELL_WCWR);
1601                                 setbit(&sc->doorbells, DOORBELL_UDBWC);
1602                         } else {
1603                                 device_printf(sc->dev,
1604                                     "couldn't enable write combining: %d\n",
1605                                     rc);
1606                         }
1607
1608                         t4_write_reg(sc, A_SGE_STAT_CFG,
1609                             V_STATSOURCE_T5(7) | V_STATMODE(0));
1610                 }
1611 #endif
1612         }
1613
1614         return (0);
1615 }
1616
1617 static const struct memwin t4_memwin[] = {
1618         { MEMWIN0_BASE, MEMWIN0_APERTURE },
1619         { MEMWIN1_BASE, MEMWIN1_APERTURE },
1620         { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
1621 };
1622
1623 static const struct memwin t5_memwin[] = {
1624         { MEMWIN0_BASE, MEMWIN0_APERTURE },
1625         { MEMWIN1_BASE, MEMWIN1_APERTURE },
1626         { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
1627 };
1628
1629 static void
1630 setup_memwin(struct adapter *sc)
1631 {
1632         const struct memwin *mw;
1633         int i, n;
1634         uint32_t bar0;
1635
1636         if (is_t4(sc)) {
1637                 /*
1638                  * Read low 32b of bar0 indirectly via the hardware backdoor
1639                  * mechanism.  Works from within PCI passthrough environments
1640                  * too, where rman_get_start() can return a different value.  We
1641                  * need to program the T4 memory window decoders with the actual
1642                  * addresses that will be coming across the PCIe link.
1643                  */
1644                 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
1645                 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
1646
1647                 mw = &t4_memwin[0];
1648                 n = nitems(t4_memwin);
1649         } else {
1650                 /* T5 uses the relative offset inside the PCIe BAR */
1651                 bar0 = 0;
1652
1653                 mw = &t5_memwin[0];
1654                 n = nitems(t5_memwin);
1655         }
1656
1657         for (i = 0; i < n; i++, mw++) {
1658                 t4_write_reg(sc,
1659                     PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
1660                     (mw->base + bar0) | V_BIR(0) |
1661                     V_WINDOW(ilog2(mw->aperture) - 10));
1662         }
1663
1664         /* flush */
1665         t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
1666 }
1667
1668 /*
1669  * Verify that the memory range specified by the addr/len pair is valid and lies
1670  * entirely within a single region (EDCx or MCx).
1671  */
1672 static int
1673 validate_mem_range(struct adapter *sc, uint32_t addr, int len)
1674 {
1675         uint32_t em, addr_len, maddr, mlen;
1676
1677         /* Memory can only be accessed in naturally aligned 4 byte units */
1678         if (addr & 3 || len & 3 || len == 0)
1679                 return (EINVAL);
1680
1681         /* Enabled memories */
1682         em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
1683         if (em & F_EDRAM0_ENABLE) {
1684                 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
1685                 maddr = G_EDRAM0_BASE(addr_len) << 20;
1686                 mlen = G_EDRAM0_SIZE(addr_len) << 20;
1687                 if (mlen > 0 && addr >= maddr && addr < maddr + mlen &&
1688                     addr + len <= maddr + mlen)
1689                         return (0);
1690         }
1691         if (em & F_EDRAM1_ENABLE) {
1692                 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
1693                 maddr = G_EDRAM1_BASE(addr_len) << 20;
1694                 mlen = G_EDRAM1_SIZE(addr_len) << 20;
1695                 if (mlen > 0 && addr >= maddr && addr < maddr + mlen &&
1696                     addr + len <= maddr + mlen)
1697                         return (0);
1698         }
1699         if (em & F_EXT_MEM_ENABLE) {
1700                 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
1701                 maddr = G_EXT_MEM_BASE(addr_len) << 20;
1702                 mlen = G_EXT_MEM_SIZE(addr_len) << 20;
1703                 if (mlen > 0 && addr >= maddr && addr < maddr + mlen &&
1704                     addr + len <= maddr + mlen)
1705                         return (0);
1706         }
1707         if (!is_t4(sc) && em & F_EXT_MEM1_ENABLE) {
1708                 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
1709                 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
1710                 mlen = G_EXT_MEM1_SIZE(addr_len) << 20;
1711                 if (mlen > 0 && addr >= maddr && addr < maddr + mlen &&
1712                     addr + len <= maddr + mlen)
1713                         return (0);
1714         }
1715
1716         return (EFAULT);
1717 }
1718
1719 static int
1720 fwmtype_to_hwmtype(int mtype)
1721 {
1722
1723         switch (mtype) {
1724         case FW_MEMTYPE_EDC0:
1725                 return (MEM_EDC0);
1726         case FW_MEMTYPE_EDC1:
1727                 return (MEM_EDC1);
1728         case FW_MEMTYPE_EXTMEM:
1729                 return (MEM_MC0);
1730         case FW_MEMTYPE_EXTMEM1:
1731                 return (MEM_MC1);
1732         default:
1733                 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
1734         }
1735 }
1736
1737 /*
1738  * Verify that the memory range specified by the memtype/offset/len pair is
1739  * valid and lies entirely within the memtype specified.  The global address of
1740  * the start of the range is returned in addr.
1741  */
1742 static int
1743 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len,
1744     uint32_t *addr)
1745 {
1746         uint32_t em, addr_len, maddr, mlen;
1747
1748         /* Memory can only be accessed in naturally aligned 4 byte units */
1749         if (off & 3 || len & 3 || len == 0)
1750                 return (EINVAL);
1751
1752         em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
1753         switch (fwmtype_to_hwmtype(mtype)) {
1754         case MEM_EDC0:
1755                 if (!(em & F_EDRAM0_ENABLE))
1756                         return (EINVAL);
1757                 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
1758                 maddr = G_EDRAM0_BASE(addr_len) << 20;
1759                 mlen = G_EDRAM0_SIZE(addr_len) << 20;
1760                 break;
1761         case MEM_EDC1:
1762                 if (!(em & F_EDRAM1_ENABLE))
1763                         return (EINVAL);
1764                 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
1765                 maddr = G_EDRAM1_BASE(addr_len) << 20;
1766                 mlen = G_EDRAM1_SIZE(addr_len) << 20;
1767                 break;
1768         case MEM_MC:
1769                 if (!(em & F_EXT_MEM_ENABLE))
1770                         return (EINVAL);
1771                 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
1772                 maddr = G_EXT_MEM_BASE(addr_len) << 20;
1773                 mlen = G_EXT_MEM_SIZE(addr_len) << 20;
1774                 break;
1775         case MEM_MC1:
1776                 if (is_t4(sc) || !(em & F_EXT_MEM1_ENABLE))
1777                         return (EINVAL);
1778                 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
1779                 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
1780                 mlen = G_EXT_MEM1_SIZE(addr_len) << 20;
1781                 break;
1782         default:
1783                 return (EINVAL);
1784         }
1785
1786         if (mlen > 0 && off < mlen && off + len <= mlen) {
1787                 *addr = maddr + off;    /* global address */
1788                 return (0);
1789         }
1790
1791         return (EFAULT);
1792 }
1793
1794 static void
1795 memwin_info(struct adapter *sc, int win, uint32_t *base, uint32_t *aperture)
1796 {
1797         const struct memwin *mw;
1798
1799         if (is_t4(sc)) {
1800                 KASSERT(win >= 0 && win < nitems(t4_memwin),
1801                     ("%s: incorrect memwin# (%d)", __func__, win));
1802                 mw = &t4_memwin[win];
1803         } else {
1804                 KASSERT(win >= 0 && win < nitems(t5_memwin),
1805                     ("%s: incorrect memwin# (%d)", __func__, win));
1806                 mw = &t5_memwin[win];
1807         }
1808
1809         if (base != NULL)
1810                 *base = mw->base;
1811         if (aperture != NULL)
1812                 *aperture = mw->aperture;
1813 }
1814
1815 /*
1816  * Positions the memory window such that it can be used to access the specified
1817  * address in the chip's address space.  The return value is the offset of addr
1818  * from the start of the window.
1819  */
1820 static uint32_t
1821 position_memwin(struct adapter *sc, int n, uint32_t addr)
1822 {
1823         uint32_t start, pf;
1824         uint32_t reg;
1825
1826         KASSERT(n >= 0 && n <= 3,
1827             ("%s: invalid window %d.", __func__, n));
1828         KASSERT((addr & 3) == 0,
1829             ("%s: addr (0x%x) is not at a 4B boundary.", __func__, addr));
1830
1831         if (is_t4(sc)) {
1832                 pf = 0;
1833                 start = addr & ~0xf;    /* start must be 16B aligned */
1834         } else {
1835                 pf = V_PFNUM(sc->pf);
1836                 start = addr & ~0x7f;   /* start must be 128B aligned */
1837         }
1838         reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, n);
1839
1840         t4_write_reg(sc, reg, start | pf);
1841         t4_read_reg(sc, reg);
1842
1843         return (addr - start);
1844 }
1845
1846 static int
1847 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g,
1848     struct intrs_and_queues *iaq)
1849 {
1850         int rc, itype, navail, nrxq10g, nrxq1g, n;
1851         int nofldrxq10g = 0, nofldrxq1g = 0;
1852         int nnmrxq10g = 0, nnmrxq1g = 0;
1853
1854         bzero(iaq, sizeof(*iaq));
1855
1856         iaq->ntxq10g = t4_ntxq10g;
1857         iaq->ntxq1g = t4_ntxq1g;
1858         iaq->nrxq10g = nrxq10g = t4_nrxq10g;
1859         iaq->nrxq1g = nrxq1g = t4_nrxq1g;
1860         iaq->rsrv_noflowq = t4_rsrv_noflowq;
1861 #ifdef TCP_OFFLOAD
1862         if (is_offload(sc)) {
1863                 iaq->nofldtxq10g = t4_nofldtxq10g;
1864                 iaq->nofldtxq1g = t4_nofldtxq1g;
1865                 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g;
1866                 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g;
1867         }
1868 #endif
1869 #ifdef DEV_NETMAP
1870         iaq->nnmtxq10g = t4_nnmtxq10g;
1871         iaq->nnmtxq1g = t4_nnmtxq1g;
1872         iaq->nnmrxq10g = nnmrxq10g = t4_nnmrxq10g;
1873         iaq->nnmrxq1g = nnmrxq1g = t4_nnmrxq1g;
1874 #endif
1875
1876         for (itype = INTR_MSIX; itype; itype >>= 1) {
1877
1878                 if ((itype & t4_intr_types) == 0)
1879                         continue;       /* not allowed */
1880
1881                 if (itype == INTR_MSIX)
1882                         navail = pci_msix_count(sc->dev);
1883                 else if (itype == INTR_MSI)
1884                         navail = pci_msi_count(sc->dev);
1885                 else
1886                         navail = 1;
1887 restart:
1888                 if (navail == 0)
1889                         continue;
1890
1891                 iaq->intr_type = itype;
1892                 iaq->intr_flags_10g = 0;
1893                 iaq->intr_flags_1g = 0;
1894
1895                 /*
1896                  * Best option: an interrupt vector for errors, one for the
1897                  * firmware event queue, and one for every rxq (NIC, TOE, and
1898                  * netmap).
1899                  */
1900                 iaq->nirq = T4_EXTRA_INTR;
1901                 iaq->nirq += n10g * (nrxq10g + nofldrxq10g + nnmrxq10g);
1902                 iaq->nirq += n1g * (nrxq1g + nofldrxq1g + nnmrxq1g);
1903                 if (iaq->nirq <= navail &&
1904                     (itype != INTR_MSI || powerof2(iaq->nirq))) {
1905                         iaq->intr_flags_10g = INTR_ALL;
1906                         iaq->intr_flags_1g = INTR_ALL;
1907                         goto allocate;
1908                 }
1909
1910                 /*
1911                  * Second best option: a vector for errors, one for the firmware
1912                  * event queue, and vectors for either all the NIC rx queues or
1913                  * all the TOE rx queues.  The queues that don't get vectors
1914                  * will forward their interrupts to those that do.
1915                  *
1916                  * Note: netmap rx queues cannot be created early and so they
1917                  * can't be setup to receive forwarded interrupts for others.
1918                  */
1919                 iaq->nirq = T4_EXTRA_INTR;
1920                 if (nrxq10g >= nofldrxq10g) {
1921                         iaq->intr_flags_10g = INTR_RXQ;
1922                         iaq->nirq += n10g * nrxq10g;
1923 #ifdef DEV_NETMAP
1924                         iaq->nnmrxq10g = min(nnmrxq10g, nrxq10g);
1925 #endif
1926                 } else {
1927                         iaq->intr_flags_10g = INTR_OFLD_RXQ;
1928                         iaq->nirq += n10g * nofldrxq10g;
1929 #ifdef DEV_NETMAP
1930                         iaq->nnmrxq10g = min(nnmrxq10g, nofldrxq10g);
1931 #endif
1932                 }
1933                 if (nrxq1g >= nofldrxq1g) {
1934                         iaq->intr_flags_1g = INTR_RXQ;
1935                         iaq->nirq += n1g * nrxq1g;
1936 #ifdef DEV_NETMAP
1937                         iaq->nnmrxq1g = min(nnmrxq1g, nrxq1g);
1938 #endif
1939                 } else {
1940                         iaq->intr_flags_1g = INTR_OFLD_RXQ;
1941                         iaq->nirq += n1g * nofldrxq1g;
1942 #ifdef DEV_NETMAP
1943                         iaq->nnmrxq1g = min(nnmrxq1g, nofldrxq1g);
1944 #endif
1945                 }
1946                 if (iaq->nirq <= navail &&
1947                     (itype != INTR_MSI || powerof2(iaq->nirq)))
1948                         goto allocate;
1949
1950                 /*
1951                  * Next best option: an interrupt vector for errors, one for the
1952                  * firmware event queue, and at least one per port.  At this
1953                  * point we know we'll have to downsize nrxq and/or nofldrxq
1954                  * and/or nnmrxq to fit what's available to us.
1955                  */
1956                 iaq->nirq = T4_EXTRA_INTR;
1957                 iaq->nirq += n10g + n1g;
1958                 if (iaq->nirq <= navail) {
1959                         int leftover = navail - iaq->nirq;
1960
1961                         if (n10g > 0) {
1962                                 int target = max(nrxq10g, nofldrxq10g);
1963
1964                                 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ?
1965                                     INTR_RXQ : INTR_OFLD_RXQ;
1966
1967                                 n = 1;
1968                                 while (n < target && leftover >= n10g) {
1969                                         leftover -= n10g;
1970                                         iaq->nirq += n10g;
1971                                         n++;
1972                                 }
1973                                 iaq->nrxq10g = min(n, nrxq10g);
1974 #ifdef TCP_OFFLOAD
1975                                 iaq->nofldrxq10g = min(n, nofldrxq10g);
1976 #endif
1977 #ifdef DEV_NETMAP
1978                                 iaq->nnmrxq10g = min(n, nnmrxq10g);
1979 #endif
1980                         }
1981
1982                         if (n1g > 0) {
1983                                 int target = max(nrxq1g, nofldrxq1g);
1984
1985                                 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ?
1986                                     INTR_RXQ : INTR_OFLD_RXQ;
1987
1988                                 n = 1;
1989                                 while (n < target && leftover >= n1g) {
1990                                         leftover -= n1g;
1991                                         iaq->nirq += n1g;
1992                                         n++;
1993                                 }
1994                                 iaq->nrxq1g = min(n, nrxq1g);
1995 #ifdef TCP_OFFLOAD
1996                                 iaq->nofldrxq1g = min(n, nofldrxq1g);
1997 #endif
1998 #ifdef DEV_NETMAP
1999                                 iaq->nnmrxq1g = min(n, nnmrxq1g);
2000 #endif
2001                         }
2002
2003                         if (itype != INTR_MSI || powerof2(iaq->nirq))
2004                                 goto allocate;
2005                 }
2006
2007                 /*
2008                  * Least desirable option: one interrupt vector for everything.
2009                  */
2010                 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1;
2011                 iaq->intr_flags_10g = iaq->intr_flags_1g = 0;
2012 #ifdef TCP_OFFLOAD
2013                 if (is_offload(sc))
2014                         iaq->nofldrxq10g = iaq->nofldrxq1g = 1;
2015 #endif
2016 #ifdef DEV_NETMAP
2017                 iaq->nnmrxq10g = iaq->nnmrxq1g = 1;
2018 #endif
2019
2020 allocate:
2021                 navail = iaq->nirq;
2022                 rc = 0;
2023                 if (itype == INTR_MSIX)
2024                         rc = pci_alloc_msix(sc->dev, &navail);
2025                 else if (itype == INTR_MSI)
2026                         rc = pci_alloc_msi(sc->dev, &navail);
2027
2028                 if (rc == 0) {
2029                         if (navail == iaq->nirq)
2030                                 return (0);
2031
2032                         /*
2033                          * Didn't get the number requested.  Use whatever number
2034                          * the kernel is willing to allocate (it's in navail).
2035                          */
2036                         device_printf(sc->dev, "fewer vectors than requested, "
2037                             "type=%d, req=%d, rcvd=%d; will downshift req.\n",
2038                             itype, iaq->nirq, navail);
2039                         pci_release_msi(sc->dev);
2040                         goto restart;
2041                 }
2042
2043                 device_printf(sc->dev,
2044                     "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
2045                     itype, rc, iaq->nirq, navail);
2046         }
2047
2048         device_printf(sc->dev,
2049             "failed to find a usable interrupt type.  "
2050             "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
2051             pci_msix_count(sc->dev), pci_msi_count(sc->dev));
2052
2053         return (ENXIO);
2054 }
2055
2056 #define FW_VERSION(chip) ( \
2057     V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
2058     V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
2059     V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
2060     V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
2061 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
2062
2063 struct fw_info {
2064         uint8_t chip;
2065         char *kld_name;
2066         char *fw_mod_name;
2067         struct fw_hdr fw_hdr;   /* XXX: waste of space, need a sparse struct */
2068 } fw_info[] = {
2069         {
2070                 .chip = CHELSIO_T4,
2071                 .kld_name = "t4fw_cfg",
2072                 .fw_mod_name = "t4fw",
2073                 .fw_hdr = {
2074                         .chip = FW_HDR_CHIP_T4,
2075                         .fw_ver = htobe32_const(FW_VERSION(T4)),
2076                         .intfver_nic = FW_INTFVER(T4, NIC),
2077                         .intfver_vnic = FW_INTFVER(T4, VNIC),
2078                         .intfver_ofld = FW_INTFVER(T4, OFLD),
2079                         .intfver_ri = FW_INTFVER(T4, RI),
2080                         .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
2081                         .intfver_iscsi = FW_INTFVER(T4, ISCSI),
2082                         .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
2083                         .intfver_fcoe = FW_INTFVER(T4, FCOE),
2084                 },
2085         }, {
2086                 .chip = CHELSIO_T5,
2087                 .kld_name = "t5fw_cfg",
2088                 .fw_mod_name = "t5fw",
2089                 .fw_hdr = {
2090                         .chip = FW_HDR_CHIP_T5,
2091                         .fw_ver = htobe32_const(FW_VERSION(T5)),
2092                         .intfver_nic = FW_INTFVER(T5, NIC),
2093                         .intfver_vnic = FW_INTFVER(T5, VNIC),
2094                         .intfver_ofld = FW_INTFVER(T5, OFLD),
2095                         .intfver_ri = FW_INTFVER(T5, RI),
2096                         .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
2097                         .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2098                         .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
2099                         .intfver_fcoe = FW_INTFVER(T5, FCOE),
2100                 },
2101         }
2102 };
2103
2104 static struct fw_info *
2105 find_fw_info(int chip)
2106 {
2107         int i;
2108
2109         for (i = 0; i < nitems(fw_info); i++) {
2110                 if (fw_info[i].chip == chip)
2111                         return (&fw_info[i]);
2112         }
2113         return (NULL);
2114 }
2115
2116 /*
2117  * Is the given firmware API compatible with the one the driver was compiled
2118  * with?
2119  */
2120 static int
2121 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
2122 {
2123
2124         /* short circuit if it's the exact same firmware version */
2125         if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
2126                 return (1);
2127
2128         /*
2129          * XXX: Is this too conservative?  Perhaps I should limit this to the
2130          * features that are supported in the driver.
2131          */
2132 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
2133         if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
2134             SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
2135             SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
2136                 return (1);
2137 #undef SAME_INTF
2138
2139         return (0);
2140 }
2141
2142 /*
2143  * The firmware in the KLD is usable, but should it be installed?  This routine
2144  * explains itself in detail if it indicates the KLD firmware should be
2145  * installed.
2146  */
2147 static int
2148 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
2149 {
2150         const char *reason;
2151
2152         if (!card_fw_usable) {
2153                 reason = "incompatible or unusable";
2154                 goto install;
2155         }
2156
2157         if (k > c) {
2158                 reason = "older than the version bundled with this driver";
2159                 goto install;
2160         }
2161
2162         if (t4_fw_install == 2 && k != c) {
2163                 reason = "different than the version bundled with this driver";
2164                 goto install;
2165         }
2166
2167         return (0);
2168
2169 install:
2170         if (t4_fw_install == 0) {
2171                 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2172                     "but the driver is prohibited from installing a different "
2173                     "firmware on the card.\n",
2174                     G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2175                     G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
2176
2177                 return (0);
2178         }
2179
2180         device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2181             "installing firmware %u.%u.%u.%u on card.\n",
2182             G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2183             G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
2184             G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2185             G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2186
2187         return (1);
2188 }
2189 /*
2190  * Establish contact with the firmware and determine if we are the master driver
2191  * or not, and whether we are responsible for chip initialization.
2192  */
2193 static int
2194 prep_firmware(struct adapter *sc)
2195 {
2196         const struct firmware *fw = NULL, *default_cfg;
2197         int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
2198         enum dev_state state;
2199         struct fw_info *fw_info;
2200         struct fw_hdr *card_fw;         /* fw on the card */
2201         const struct fw_hdr *kld_fw;    /* fw in the KLD */
2202         const struct fw_hdr *drv_fw;    /* fw header the driver was compiled
2203                                            against */
2204
2205         /* Contact firmware. */
2206         rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
2207         if (rc < 0 || state == DEV_STATE_ERR) {
2208                 rc = -rc;
2209                 device_printf(sc->dev,
2210                     "failed to connect to the firmware: %d, %d.\n", rc, state);
2211                 return (rc);
2212         }
2213         pf = rc;
2214         if (pf == sc->mbox)
2215                 sc->flags |= MASTER_PF;
2216         else if (state == DEV_STATE_UNINIT) {
2217                 /*
2218                  * We didn't get to be the master so we definitely won't be
2219                  * configuring the chip.  It's a bug if someone else hasn't
2220                  * configured it already.
2221                  */
2222                 device_printf(sc->dev, "couldn't be master(%d), "
2223                     "device not already initialized either(%d).\n", rc, state);
2224                 return (EDOOFUS);
2225         }
2226
2227         /* This is the firmware whose headers the driver was compiled against */
2228         fw_info = find_fw_info(chip_id(sc));
2229         if (fw_info == NULL) {
2230                 device_printf(sc->dev,
2231                     "unable to look up firmware information for chip %d.\n",
2232                     chip_id(sc));
2233                 return (EINVAL);
2234         }
2235         drv_fw = &fw_info->fw_hdr;
2236
2237         /*
2238          * The firmware KLD contains many modules.  The KLD name is also the
2239          * name of the module that contains the default config file.
2240          */
2241         default_cfg = firmware_get(fw_info->kld_name);
2242
2243         /* Read the header of the firmware on the card */
2244         card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
2245         rc = -t4_read_flash(sc, FLASH_FW_START,
2246             sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
2247         if (rc == 0)
2248                 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
2249         else {
2250                 device_printf(sc->dev,
2251                     "Unable to read card's firmware header: %d\n", rc);
2252                 card_fw_usable = 0;
2253         }
2254
2255         /* This is the firmware in the KLD */
2256         fw = firmware_get(fw_info->fw_mod_name);
2257         if (fw != NULL) {
2258                 kld_fw = (const void *)fw->data;
2259                 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
2260         } else {
2261                 kld_fw = NULL;
2262                 kld_fw_usable = 0;
2263         }
2264
2265         if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
2266             (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
2267                 /*
2268                  * Common case: the firmware on the card is an exact match and
2269                  * the KLD is an exact match too, or the KLD is
2270                  * absent/incompatible.  Note that t4_fw_install = 2 is ignored
2271                  * here -- use cxgbetool loadfw if you want to reinstall the
2272                  * same firmware as the one on the card.
2273                  */
2274         } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
2275             should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
2276             be32toh(card_fw->fw_ver))) {
2277
2278                 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
2279                 if (rc != 0) {
2280                         device_printf(sc->dev,
2281                             "failed to install firmware: %d\n", rc);
2282                         goto done;
2283                 }
2284
2285                 /* Installed successfully, update the cached header too. */
2286                 memcpy(card_fw, kld_fw, sizeof(*card_fw));
2287                 card_fw_usable = 1;
2288                 need_fw_reset = 0;      /* already reset as part of load_fw */
2289         }
2290
2291         if (!card_fw_usable) {
2292                 uint32_t d, c, k;
2293
2294                 d = ntohl(drv_fw->fw_ver);
2295                 c = ntohl(card_fw->fw_ver);
2296                 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
2297
2298                 device_printf(sc->dev, "Cannot find a usable firmware: "
2299                     "fw_install %d, chip state %d, "
2300                     "driver compiled with %d.%d.%d.%d, "
2301                     "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
2302                     t4_fw_install, state,
2303                     G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
2304                     G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
2305                     G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2306                     G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
2307                     G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2308                     G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2309                 rc = EINVAL;
2310                 goto done;
2311         }
2312
2313         /* We're using whatever's on the card and it's known to be good. */
2314         sc->params.fw_vers = ntohl(card_fw->fw_ver);
2315         snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
2316             G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
2317             G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
2318             G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
2319             G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
2320         t4_get_tp_version(sc, &sc->params.tp_vers);
2321
2322         /* Reset device */
2323         if (need_fw_reset &&
2324             (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
2325                 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
2326                 if (rc != ETIMEDOUT && rc != EIO)
2327                         t4_fw_bye(sc, sc->mbox);
2328                 goto done;
2329         }
2330         sc->flags |= FW_OK;
2331
2332         rc = get_params__pre_init(sc);
2333         if (rc != 0)
2334                 goto done; /* error message displayed already */
2335
2336         /* Partition adapter resources as specified in the config file. */
2337         if (state == DEV_STATE_UNINIT) {
2338
2339                 KASSERT(sc->flags & MASTER_PF,
2340                     ("%s: trying to change chip settings when not master.",
2341                     __func__));
2342
2343                 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
2344                 if (rc != 0)
2345                         goto done;      /* error message displayed already */
2346
2347                 t4_tweak_chip_settings(sc);
2348
2349                 /* get basic stuff going */
2350                 rc = -t4_fw_initialize(sc, sc->mbox);
2351                 if (rc != 0) {
2352                         device_printf(sc->dev, "fw init failed: %d.\n", rc);
2353                         goto done;
2354                 }
2355         } else {
2356                 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
2357                 sc->cfcsum = 0;
2358         }
2359
2360 done:
2361         free(card_fw, M_CXGBE);
2362         if (fw != NULL)
2363                 firmware_put(fw, FIRMWARE_UNLOAD);
2364         if (default_cfg != NULL)
2365                 firmware_put(default_cfg, FIRMWARE_UNLOAD);
2366
2367         return (rc);
2368 }
2369
2370 #define FW_PARAM_DEV(param) \
2371         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
2372          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
2373 #define FW_PARAM_PFVF(param) \
2374         (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
2375          V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
2376
2377 /*
2378  * Partition chip resources for use between various PFs, VFs, etc.
2379  */
2380 static int
2381 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
2382     const char *name_prefix)
2383 {
2384         const struct firmware *cfg = NULL;
2385         int rc = 0;
2386         struct fw_caps_config_cmd caps;
2387         uint32_t mtype, moff, finicsum, cfcsum;
2388
2389         /*
2390          * Figure out what configuration file to use.  Pick the default config
2391          * file for the card if the user hasn't specified one explicitly.
2392          */
2393         snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
2394         if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
2395                 /* Card specific overrides go here. */
2396                 if (pci_get_device(sc->dev) == 0x440a)
2397                         snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
2398                 if (is_fpga(sc))
2399                         snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
2400         }
2401
2402         /*
2403          * We need to load another module if the profile is anything except
2404          * "default" or "flash".
2405          */
2406         if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
2407             strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2408                 char s[32];
2409
2410                 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
2411                 cfg = firmware_get(s);
2412                 if (cfg == NULL) {
2413                         if (default_cfg != NULL) {
2414                                 device_printf(sc->dev,
2415                                     "unable to load module \"%s\" for "
2416                                     "configuration profile \"%s\", will use "
2417                                     "the default config file instead.\n",
2418                                     s, sc->cfg_file);
2419                                 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2420                                     "%s", DEFAULT_CF);
2421                         } else {
2422                                 device_printf(sc->dev,
2423                                     "unable to load module \"%s\" for "
2424                                     "configuration profile \"%s\", will use "
2425                                     "the config file on the card's flash "
2426                                     "instead.\n", s, sc->cfg_file);
2427                                 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2428                                     "%s", FLASH_CF);
2429                         }
2430                 }
2431         }
2432
2433         if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
2434             default_cfg == NULL) {
2435                 device_printf(sc->dev,
2436                     "default config file not available, will use the config "
2437                     "file on the card's flash instead.\n");
2438                 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
2439         }
2440
2441         if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2442                 u_int cflen, i, n;
2443                 const uint32_t *cfdata;
2444                 uint32_t param, val, addr, off, mw_base, mw_aperture;
2445
2446                 KASSERT(cfg != NULL || default_cfg != NULL,
2447                     ("%s: no config to upload", __func__));
2448
2449                 /*
2450                  * Ask the firmware where it wants us to upload the config file.
2451                  */
2452                 param = FW_PARAM_DEV(CF);
2453                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
2454                 if (rc != 0) {
2455                         /* No support for config file?  Shouldn't happen. */
2456                         device_printf(sc->dev,
2457                             "failed to query config file location: %d.\n", rc);
2458                         goto done;
2459                 }
2460                 mtype = G_FW_PARAMS_PARAM_Y(val);
2461                 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
2462
2463                 /*
2464                  * XXX: sheer laziness.  We deliberately added 4 bytes of
2465                  * useless stuffing/comments at the end of the config file so
2466                  * it's ok to simply throw away the last remaining bytes when
2467                  * the config file is not an exact multiple of 4.  This also
2468                  * helps with the validate_mt_off_len check.
2469                  */
2470                 if (cfg != NULL) {
2471                         cflen = cfg->datasize & ~3;
2472                         cfdata = cfg->data;
2473                 } else {
2474                         cflen = default_cfg->datasize & ~3;
2475                         cfdata = default_cfg->data;
2476                 }
2477
2478                 if (cflen > FLASH_CFG_MAX_SIZE) {
2479                         device_printf(sc->dev,
2480                             "config file too long (%d, max allowed is %d).  "
2481                             "Will try to use the config on the card, if any.\n",
2482                             cflen, FLASH_CFG_MAX_SIZE);
2483                         goto use_config_on_flash;
2484                 }
2485
2486                 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
2487                 if (rc != 0) {
2488                         device_printf(sc->dev,
2489                             "%s: addr (%d/0x%x) or len %d is not valid: %d.  "
2490                             "Will try to use the config on the card, if any.\n",
2491                             __func__, mtype, moff, cflen, rc);
2492                         goto use_config_on_flash;
2493                 }
2494
2495                 memwin_info(sc, 2, &mw_base, &mw_aperture);
2496                 while (cflen) {
2497                         off = position_memwin(sc, 2, addr);
2498                         n = min(cflen, mw_aperture - off);
2499                         for (i = 0; i < n; i += 4)
2500                                 t4_write_reg(sc, mw_base + off + i, *cfdata++);
2501                         cflen -= n;
2502                         addr += n;
2503                 }
2504         } else {
2505 use_config_on_flash:
2506                 mtype = FW_MEMTYPE_FLASH;
2507                 moff = t4_flash_cfg_addr(sc);
2508         }
2509
2510         bzero(&caps, sizeof(caps));
2511         caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2512             F_FW_CMD_REQUEST | F_FW_CMD_READ);
2513         caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
2514             V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
2515             V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
2516         rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
2517         if (rc != 0) {
2518                 device_printf(sc->dev,
2519                     "failed to pre-process config file: %d "
2520                     "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
2521                 goto done;
2522         }
2523
2524         finicsum = be32toh(caps.finicsum);
2525         cfcsum = be32toh(caps.cfcsum);
2526         if (finicsum != cfcsum) {
2527                 device_printf(sc->dev,
2528                     "WARNING: config file checksum mismatch: %08x %08x\n",
2529                     finicsum, cfcsum);
2530         }
2531         sc->cfcsum = cfcsum;
2532
2533 #define LIMIT_CAPS(x) do { \
2534         caps.x &= htobe16(t4_##x##_allowed); \
2535 } while (0)
2536
2537         /*
2538          * Let the firmware know what features will (not) be used so it can tune
2539          * things accordingly.
2540          */
2541         LIMIT_CAPS(linkcaps);
2542         LIMIT_CAPS(niccaps);
2543         LIMIT_CAPS(toecaps);
2544         LIMIT_CAPS(rdmacaps);
2545         LIMIT_CAPS(iscsicaps);
2546         LIMIT_CAPS(fcoecaps);
2547 #undef LIMIT_CAPS
2548
2549         caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2550             F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
2551         caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
2552         rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
2553         if (rc != 0) {
2554                 device_printf(sc->dev,
2555                     "failed to process config file: %d.\n", rc);
2556         }
2557 done:
2558         if (cfg != NULL)
2559                 firmware_put(cfg, FIRMWARE_UNLOAD);
2560         return (rc);
2561 }
2562
2563 /*
2564  * Retrieve parameters that are needed (or nice to have) very early.
2565  */
2566 static int
2567 get_params__pre_init(struct adapter *sc)
2568 {
2569         int rc;
2570         uint32_t param[2], val[2];
2571         struct fw_devlog_cmd cmd;
2572         struct devlog_params *dlog = &sc->params.devlog;
2573
2574         param[0] = FW_PARAM_DEV(PORTVEC);
2575         param[1] = FW_PARAM_DEV(CCLK);
2576         rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
2577         if (rc != 0) {
2578                 device_printf(sc->dev,
2579                     "failed to query parameters (pre_init): %d.\n", rc);
2580                 return (rc);
2581         }
2582
2583         sc->params.portvec = val[0];
2584         sc->params.nports = bitcount32(val[0]);
2585         sc->params.vpd.cclk = val[1];
2586
2587         /* Read device log parameters. */
2588         bzero(&cmd, sizeof(cmd));
2589         cmd.op_to_write = htobe32(V_FW_CMD_OP(FW_DEVLOG_CMD) |
2590             F_FW_CMD_REQUEST | F_FW_CMD_READ);
2591         cmd.retval_len16 = htobe32(FW_LEN16(cmd));
2592         rc = -t4_wr_mbox(sc, sc->mbox, &cmd, sizeof(cmd), &cmd);
2593         if (rc != 0) {
2594                 device_printf(sc->dev,
2595                     "failed to get devlog parameters: %d.\n", rc);
2596                 bzero(dlog, sizeof (*dlog));
2597                 rc = 0; /* devlog isn't critical for device operation */
2598         } else {
2599                 val[0] = be32toh(cmd.memtype_devlog_memaddr16_devlog);
2600                 dlog->memtype = G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(val[0]);
2601                 dlog->start = G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(val[0]) << 4;
2602                 dlog->size = be32toh(cmd.memsize_devlog);
2603         }
2604
2605         return (rc);
2606 }
2607
2608 /*
2609  * Retrieve various parameters that are of interest to the driver.  The device
2610  * has been initialized by the firmware at this point.
2611  */
2612 static int
2613 get_params__post_init(struct adapter *sc)
2614 {
2615         int rc;
2616         uint32_t param[7], val[7];
2617         struct fw_caps_config_cmd caps;
2618
2619         param[0] = FW_PARAM_PFVF(IQFLINT_START);
2620         param[1] = FW_PARAM_PFVF(EQ_START);
2621         param[2] = FW_PARAM_PFVF(FILTER_START);
2622         param[3] = FW_PARAM_PFVF(FILTER_END);
2623         param[4] = FW_PARAM_PFVF(L2T_START);
2624         param[5] = FW_PARAM_PFVF(L2T_END);
2625         rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
2626         if (rc != 0) {
2627                 device_printf(sc->dev,
2628                     "failed to query parameters (post_init): %d.\n", rc);
2629                 return (rc);
2630         }
2631
2632         sc->sge.iq_start = val[0];
2633         sc->sge.eq_start = val[1];
2634         sc->tids.ftid_base = val[2];
2635         sc->tids.nftids = val[3] - val[2] + 1;
2636         sc->params.ftid_min = val[2];
2637         sc->params.ftid_max = val[3];
2638         sc->vres.l2t.start = val[4];
2639         sc->vres.l2t.size = val[5] - val[4] + 1;
2640         KASSERT(sc->vres.l2t.size <= L2T_SIZE,
2641             ("%s: L2 table size (%u) larger than expected (%u)",
2642             __func__, sc->vres.l2t.size, L2T_SIZE));
2643
2644         /* get capabilites */
2645         bzero(&caps, sizeof(caps));
2646         caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2647             F_FW_CMD_REQUEST | F_FW_CMD_READ);
2648         caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
2649         rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
2650         if (rc != 0) {
2651                 device_printf(sc->dev,
2652                     "failed to get card capabilities: %d.\n", rc);
2653                 return (rc);
2654         }
2655
2656 #define READ_CAPS(x) do { \
2657         sc->x = htobe16(caps.x); \
2658 } while (0)
2659         READ_CAPS(linkcaps);
2660         READ_CAPS(niccaps);
2661         READ_CAPS(toecaps);
2662         READ_CAPS(rdmacaps);
2663         READ_CAPS(iscsicaps);
2664         READ_CAPS(fcoecaps);
2665
2666         if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
2667                 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
2668                 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
2669                 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
2670                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
2671                 if (rc != 0) {
2672                         device_printf(sc->dev,
2673                             "failed to query NIC parameters: %d.\n", rc);
2674                         return (rc);
2675                 }
2676                 sc->tids.etid_base = val[0];
2677                 sc->params.etid_min = val[0];
2678                 sc->tids.netids = val[1] - val[0] + 1;
2679                 sc->params.netids = sc->tids.netids;
2680                 sc->params.eo_wr_cred = val[2];
2681                 sc->params.ethoffload = 1;
2682         }
2683
2684         if (sc->toecaps) {
2685                 /* query offload-related parameters */
2686                 param[0] = FW_PARAM_DEV(NTID);
2687                 param[1] = FW_PARAM_PFVF(SERVER_START);
2688                 param[2] = FW_PARAM_PFVF(SERVER_END);
2689                 param[3] = FW_PARAM_PFVF(TDDP_START);
2690                 param[4] = FW_PARAM_PFVF(TDDP_END);
2691                 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
2692                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
2693                 if (rc != 0) {
2694                         device_printf(sc->dev,
2695                             "failed to query TOE parameters: %d.\n", rc);
2696                         return (rc);
2697                 }
2698                 sc->tids.ntids = val[0];
2699                 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
2700                 sc->tids.stid_base = val[1];
2701                 sc->tids.nstids = val[2] - val[1] + 1;
2702                 sc->vres.ddp.start = val[3];
2703                 sc->vres.ddp.size = val[4] - val[3] + 1;
2704                 sc->params.ofldq_wr_cred = val[5];
2705                 sc->params.offload = 1;
2706         }
2707         if (sc->rdmacaps) {
2708                 param[0] = FW_PARAM_PFVF(STAG_START);
2709                 param[1] = FW_PARAM_PFVF(STAG_END);
2710                 param[2] = FW_PARAM_PFVF(RQ_START);
2711                 param[3] = FW_PARAM_PFVF(RQ_END);
2712                 param[4] = FW_PARAM_PFVF(PBL_START);
2713                 param[5] = FW_PARAM_PFVF(PBL_END);
2714                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
2715                 if (rc != 0) {
2716                         device_printf(sc->dev,
2717                             "failed to query RDMA parameters(1): %d.\n", rc);
2718                         return (rc);
2719                 }
2720                 sc->vres.stag.start = val[0];
2721                 sc->vres.stag.size = val[1] - val[0] + 1;
2722                 sc->vres.rq.start = val[2];
2723                 sc->vres.rq.size = val[3] - val[2] + 1;
2724                 sc->vres.pbl.start = val[4];
2725                 sc->vres.pbl.size = val[5] - val[4] + 1;
2726
2727                 param[0] = FW_PARAM_PFVF(SQRQ_START);
2728                 param[1] = FW_PARAM_PFVF(SQRQ_END);
2729                 param[2] = FW_PARAM_PFVF(CQ_START);
2730                 param[3] = FW_PARAM_PFVF(CQ_END);
2731                 param[4] = FW_PARAM_PFVF(OCQ_START);
2732                 param[5] = FW_PARAM_PFVF(OCQ_END);
2733                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
2734                 if (rc != 0) {
2735                         device_printf(sc->dev,
2736                             "failed to query RDMA parameters(2): %d.\n", rc);
2737                         return (rc);
2738                 }
2739                 sc->vres.qp.start = val[0];
2740                 sc->vres.qp.size = val[1] - val[0] + 1;
2741                 sc->vres.cq.start = val[2];
2742                 sc->vres.cq.size = val[3] - val[2] + 1;
2743                 sc->vres.ocq.start = val[4];
2744                 sc->vres.ocq.size = val[5] - val[4] + 1;
2745         }
2746         if (sc->iscsicaps) {
2747                 param[0] = FW_PARAM_PFVF(ISCSI_START);
2748                 param[1] = FW_PARAM_PFVF(ISCSI_END);
2749                 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
2750                 if (rc != 0) {
2751                         device_printf(sc->dev,
2752                             "failed to query iSCSI parameters: %d.\n", rc);
2753                         return (rc);
2754                 }
2755                 sc->vres.iscsi.start = val[0];
2756                 sc->vres.iscsi.size = val[1] - val[0] + 1;
2757         }
2758
2759         /*
2760          * We've got the params we wanted to query via the firmware.  Now grab
2761          * some others directly from the chip.
2762          */
2763         rc = t4_read_chip_settings(sc);
2764
2765         return (rc);
2766 }
2767
2768 static int
2769 set_params__post_init(struct adapter *sc)
2770 {
2771         uint32_t param, val;
2772
2773         /* ask for encapsulated CPLs */
2774         param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
2775         val = 1;
2776         (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
2777
2778         return (0);
2779 }
2780
2781 #undef FW_PARAM_PFVF
2782 #undef FW_PARAM_DEV
2783
2784 static void
2785 t4_set_desc(struct adapter *sc)
2786 {
2787         char buf[128];
2788         struct adapter_params *p = &sc->params;
2789
2790         snprintf(buf, sizeof(buf), "Chelsio %s %sNIC (rev %d), S/N:%s, "
2791             "P/N:%s, E/C:%s", p->vpd.id, is_offload(sc) ? "R" : "",
2792             chip_rev(sc), p->vpd.sn, p->vpd.pn, p->vpd.ec);
2793
2794         device_set_desc_copy(sc->dev, buf);
2795 }
2796
2797 static void
2798 build_medialist(struct port_info *pi, struct ifmedia *media)
2799 {
2800         int data, m;
2801
2802         PORT_LOCK(pi);
2803
2804         ifmedia_removeall(media);
2805
2806         m = IFM_ETHER | IFM_FDX;
2807         data = (pi->port_type << 8) | pi->mod_type;
2808
2809         switch(pi->port_type) {
2810         case FW_PORT_TYPE_BT_XFI:
2811         case FW_PORT_TYPE_BT_XAUI:
2812                 ifmedia_add(media, m | IFM_10G_T, data, NULL);
2813                 /* fall through */
2814
2815         case FW_PORT_TYPE_BT_SGMII:
2816                 ifmedia_add(media, m | IFM_1000_T, data, NULL);
2817                 ifmedia_add(media, m | IFM_100_TX, data, NULL);
2818                 ifmedia_add(media, IFM_ETHER | IFM_AUTO, data, NULL);
2819                 ifmedia_set(media, IFM_ETHER | IFM_AUTO);
2820                 break;
2821
2822         case FW_PORT_TYPE_CX4:
2823                 ifmedia_add(media, m | IFM_10G_CX4, data, NULL);
2824                 ifmedia_set(media, m | IFM_10G_CX4);
2825                 break;
2826
2827         case FW_PORT_TYPE_QSFP_10G:
2828         case FW_PORT_TYPE_SFP:
2829         case FW_PORT_TYPE_FIBER_XFI:
2830         case FW_PORT_TYPE_FIBER_XAUI:
2831                 switch (pi->mod_type) {
2832
2833                 case FW_PORT_MOD_TYPE_LR:
2834                         ifmedia_add(media, m | IFM_10G_LR, data, NULL);
2835                         ifmedia_set(media, m | IFM_10G_LR);
2836                         break;
2837
2838                 case FW_PORT_MOD_TYPE_SR:
2839                         ifmedia_add(media, m | IFM_10G_SR, data, NULL);
2840                         ifmedia_set(media, m | IFM_10G_SR);
2841                         break;
2842
2843                 case FW_PORT_MOD_TYPE_LRM:
2844                         ifmedia_add(media, m | IFM_10G_LRM, data, NULL);
2845                         ifmedia_set(media, m | IFM_10G_LRM);
2846                         break;
2847
2848                 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
2849                 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
2850                         ifmedia_add(media, m | IFM_10G_TWINAX, data, NULL);
2851                         ifmedia_set(media, m | IFM_10G_TWINAX);
2852                         break;
2853
2854                 case FW_PORT_MOD_TYPE_NONE:
2855                         m &= ~IFM_FDX;
2856                         ifmedia_add(media, m | IFM_NONE, data, NULL);
2857                         ifmedia_set(media, m | IFM_NONE);
2858                         break;
2859
2860                 case FW_PORT_MOD_TYPE_NA:
2861                 case FW_PORT_MOD_TYPE_ER:
2862                 default:
2863                         device_printf(pi->dev,
2864                             "unknown port_type (%d), mod_type (%d)\n",
2865                             pi->port_type, pi->mod_type);
2866                         ifmedia_add(media, m | IFM_UNKNOWN, data, NULL);
2867                         ifmedia_set(media, m | IFM_UNKNOWN);
2868                         break;
2869                 }
2870                 break;
2871
2872         case FW_PORT_TYPE_QSFP:
2873                 switch (pi->mod_type) {
2874
2875                 case FW_PORT_MOD_TYPE_LR:
2876                         ifmedia_add(media, m | IFM_40G_LR4, data, NULL);
2877                         ifmedia_set(media, m | IFM_40G_LR4);
2878                         break;
2879
2880                 case FW_PORT_MOD_TYPE_SR:
2881                         ifmedia_add(media, m | IFM_40G_SR4, data, NULL);
2882                         ifmedia_set(media, m | IFM_40G_SR4);
2883                         break;
2884
2885                 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
2886                 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
2887                         ifmedia_add(media, m | IFM_40G_CR4, data, NULL);
2888                         ifmedia_set(media, m | IFM_40G_CR4);
2889                         break;
2890
2891                 case FW_PORT_MOD_TYPE_NONE:
2892                         m &= ~IFM_FDX;
2893                         ifmedia_add(media, m | IFM_NONE, data, NULL);
2894                         ifmedia_set(media, m | IFM_NONE);
2895                         break;
2896
2897                 default:
2898                         device_printf(pi->dev,
2899                             "unknown port_type (%d), mod_type (%d)\n",
2900                             pi->port_type, pi->mod_type);
2901                         ifmedia_add(media, m | IFM_UNKNOWN, data, NULL);
2902                         ifmedia_set(media, m | IFM_UNKNOWN);
2903                         break;
2904                 }
2905                 break;
2906
2907         default:
2908                 device_printf(pi->dev,
2909                     "unknown port_type (%d), mod_type (%d)\n", pi->port_type,
2910                     pi->mod_type);
2911                 ifmedia_add(media, m | IFM_UNKNOWN, data, NULL);
2912                 ifmedia_set(media, m | IFM_UNKNOWN);
2913                 break;
2914         }
2915
2916         PORT_UNLOCK(pi);
2917 }
2918
2919 #define FW_MAC_EXACT_CHUNK      7
2920
2921 /*
2922  * Program the port's XGMAC based on parameters in ifnet.  The caller also
2923  * indicates which parameters should be programmed (the rest are left alone).
2924  */
2925 int
2926 update_mac_settings(struct ifnet *ifp, int flags)
2927 {
2928         int rc = 0;
2929         struct port_info *pi = ifp->if_softc;
2930         struct adapter *sc = pi->adapter;
2931         int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
2932         uint16_t viid = 0xffff;
2933         int16_t *xact_addr_filt = NULL;
2934
2935         ASSERT_SYNCHRONIZED_OP(sc);
2936         KASSERT(flags, ("%s: not told what to update.", __func__));
2937
2938         if (ifp == pi->ifp) {
2939                 viid = pi->viid;
2940                 xact_addr_filt = &pi->xact_addr_filt;
2941         }
2942 #ifdef DEV_NETMAP
2943         else if (ifp == pi->nm_ifp) {
2944                 viid = pi->nm_viid;
2945                 xact_addr_filt = &pi->nm_xact_addr_filt;
2946         }
2947 #endif
2948         if (flags & XGMAC_MTU)
2949                 mtu = ifp->if_mtu;
2950
2951         if (flags & XGMAC_PROMISC)
2952                 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
2953
2954         if (flags & XGMAC_ALLMULTI)
2955                 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
2956
2957         if (flags & XGMAC_VLANEX)
2958                 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
2959
2960         if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
2961                 rc = -t4_set_rxmode(sc, sc->mbox, viid, mtu, promisc, allmulti,
2962                     1, vlanex, false);
2963                 if (rc) {
2964                         if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
2965                             rc);
2966                         return (rc);
2967                 }
2968         }
2969
2970         if (flags & XGMAC_UCADDR) {
2971                 uint8_t ucaddr[ETHER_ADDR_LEN];
2972
2973                 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
2974                 rc = t4_change_mac(sc, sc->mbox, viid, *xact_addr_filt, ucaddr,
2975                     true, true);
2976                 if (rc < 0) {
2977                         rc = -rc;
2978                         if_printf(ifp, "change_mac failed: %d\n", rc);
2979                         return (rc);
2980                 } else {
2981                         *xact_addr_filt = rc;
2982                         rc = 0;
2983                 }
2984         }
2985
2986         if (flags & XGMAC_MCADDRS) {
2987                 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
2988                 int del = 1;
2989                 uint64_t hash = 0;
2990                 struct ifmultiaddr *ifma;
2991                 int i = 0, j;
2992
2993                 if_maddr_rlock(ifp);
2994                 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
2995                         if (ifma->ifma_addr->sa_family != AF_LINK)
2996                                 continue;
2997                         mcaddr[i] =
2998                             LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
2999                         MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
3000                         i++;
3001
3002                         if (i == FW_MAC_EXACT_CHUNK) {
3003                                 rc = t4_alloc_mac_filt(sc, sc->mbox, viid, del,
3004                                     i, mcaddr, NULL, &hash, 0);
3005                                 if (rc < 0) {
3006                                         rc = -rc;
3007                                         for (j = 0; j < i; j++) {
3008                                                 if_printf(ifp,
3009                                                     "failed to add mc address"
3010                                                     " %02x:%02x:%02x:"
3011                                                     "%02x:%02x:%02x rc=%d\n",
3012                                                     mcaddr[j][0], mcaddr[j][1],
3013                                                     mcaddr[j][2], mcaddr[j][3],
3014                                                     mcaddr[j][4], mcaddr[j][5],
3015                                                     rc);
3016                                         }
3017                                         goto mcfail;
3018                                 }
3019                                 del = 0;
3020                                 i = 0;
3021                         }
3022                 }
3023                 if (i > 0) {
3024                         rc = t4_alloc_mac_filt(sc, sc->mbox, viid, del, i,
3025                             mcaddr, NULL, &hash, 0);
3026                         if (rc < 0) {
3027                                 rc = -rc;
3028                                 for (j = 0; j < i; j++) {
3029                                         if_printf(ifp,
3030                                             "failed to add mc address"
3031                                             " %02x:%02x:%02x:"
3032                                             "%02x:%02x:%02x rc=%d\n",
3033                                             mcaddr[j][0], mcaddr[j][1],
3034                                             mcaddr[j][2], mcaddr[j][3],
3035                                             mcaddr[j][4], mcaddr[j][5],
3036                                             rc);
3037                                 }
3038                                 goto mcfail;
3039                         }
3040                 }
3041
3042                 rc = -t4_set_addr_hash(sc, sc->mbox, viid, 0, hash, 0);
3043                 if (rc != 0)
3044                         if_printf(ifp, "failed to set mc address hash: %d", rc);
3045 mcfail:
3046                 if_maddr_runlock(ifp);
3047         }
3048
3049         return (rc);
3050 }
3051
3052 /*
3053  * {begin|end}_synchronized_op must be called from the same thread.
3054  */
3055 int
3056 begin_synchronized_op(struct adapter *sc, struct port_info *pi, int flags,
3057     char *wmesg)
3058 {
3059         int rc, pri;
3060
3061 #ifdef WITNESS
3062         /* the caller thinks it's ok to sleep, but is it really? */
3063         if (flags & SLEEP_OK)
3064                 pause("t4slptst", 1);
3065 #endif
3066
3067         if (INTR_OK)
3068                 pri = PCATCH;
3069         else
3070                 pri = 0;
3071
3072         ADAPTER_LOCK(sc);
3073         for (;;) {
3074
3075                 if (pi && IS_DOOMED(pi)) {
3076                         rc = ENXIO;
3077                         goto done;
3078                 }
3079
3080                 if (!IS_BUSY(sc)) {
3081                         rc = 0;
3082                         break;
3083                 }
3084
3085                 if (!(flags & SLEEP_OK)) {
3086                         rc = EBUSY;
3087                         goto done;
3088                 }
3089
3090                 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
3091                         rc = EINTR;
3092                         goto done;
3093                 }
3094         }
3095
3096         KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
3097         SET_BUSY(sc);
3098 #ifdef INVARIANTS
3099         sc->last_op = wmesg;
3100         sc->last_op_thr = curthread;
3101 #endif
3102
3103 done:
3104         if (!(flags & HOLD_LOCK) || rc)
3105                 ADAPTER_UNLOCK(sc);
3106
3107         return (rc);
3108 }
3109
3110 /*
3111  * {begin|end}_synchronized_op must be called from the same thread.
3112  */
3113 void
3114 end_synchronized_op(struct adapter *sc, int flags)
3115 {
3116
3117         if (flags & LOCK_HELD)
3118                 ADAPTER_LOCK_ASSERT_OWNED(sc);
3119         else
3120                 ADAPTER_LOCK(sc);
3121
3122         KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
3123         CLR_BUSY(sc);
3124         wakeup(&sc->flags);
3125         ADAPTER_UNLOCK(sc);
3126 }
3127
3128 static int
3129 cxgbe_init_synchronized(struct port_info *pi)
3130 {
3131         struct adapter *sc = pi->adapter;
3132         struct ifnet *ifp = pi->ifp;
3133         int rc = 0;
3134
3135         ASSERT_SYNCHRONIZED_OP(sc);
3136
3137         if (isset(&sc->open_device_map, pi->port_id)) {
3138                 KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING,
3139                     ("mismatch between open_device_map and if_drv_flags"));
3140                 return (0);     /* already running */
3141         }
3142
3143         if (!(sc->flags & FULL_INIT_DONE) &&
3144             ((rc = adapter_full_init(sc)) != 0))
3145                 return (rc);    /* error message displayed already */
3146
3147         if (!(pi->flags & PORT_INIT_DONE) &&
3148             ((rc = port_full_init(pi)) != 0))
3149                 return (rc); /* error message displayed already */
3150
3151         rc = update_mac_settings(ifp, XGMAC_ALL);
3152         if (rc)
3153                 goto done;      /* error message displayed already */
3154
3155         rc = -t4_enable_vi(sc, sc->mbox, pi->viid, true, true);
3156         if (rc != 0) {
3157                 if_printf(ifp, "enable_vi failed: %d\n", rc);
3158                 goto done;
3159         }
3160
3161         /*
3162          * The first iq of the first port to come up is used for tracing.
3163          */
3164         if (sc->traceq < 0) {
3165                 sc->traceq = sc->sge.rxq[pi->first_rxq].iq.abs_id;
3166                 t4_write_reg(sc, is_t4(sc) ?  A_MPS_TRC_RSS_CONTROL :
3167                     A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
3168                     V_QUEUENUMBER(sc->traceq));
3169                 pi->flags |= HAS_TRACEQ;
3170         }
3171
3172         /* all ok */
3173         setbit(&sc->open_device_map, pi->port_id);
3174         PORT_LOCK(pi);
3175         ifp->if_drv_flags |= IFF_DRV_RUNNING;
3176         PORT_UNLOCK(pi);
3177
3178         callout_reset(&pi->tick, hz, cxgbe_tick, pi);
3179 done:
3180         if (rc != 0)
3181                 cxgbe_uninit_synchronized(pi);
3182
3183         return (rc);
3184 }
3185
3186 /*
3187  * Idempotent.
3188  */
3189 static int
3190 cxgbe_uninit_synchronized(struct port_info *pi)
3191 {
3192         struct adapter *sc = pi->adapter;
3193         struct ifnet *ifp = pi->ifp;
3194         int rc;
3195
3196         ASSERT_SYNCHRONIZED_OP(sc);
3197
3198         /*
3199          * Disable the VI so that all its data in either direction is discarded
3200          * by the MPS.  Leave everything else (the queues, interrupts, and 1Hz
3201          * tick) intact as the TP can deliver negative advice or data that it's
3202          * holding in its RAM (for an offloaded connection) even after the VI is
3203          * disabled.
3204          */
3205         rc = -t4_enable_vi(sc, sc->mbox, pi->viid, false, false);
3206         if (rc) {
3207                 if_printf(ifp, "disable_vi failed: %d\n", rc);
3208                 return (rc);
3209         }
3210
3211         clrbit(&sc->open_device_map, pi->port_id);
3212         PORT_LOCK(pi);
3213         ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3214         PORT_UNLOCK(pi);
3215
3216         pi->link_cfg.link_ok = 0;
3217         pi->link_cfg.speed = 0;
3218         pi->linkdnrc = -1;
3219         t4_os_link_changed(sc, pi->port_id, 0, -1);
3220
3221         return (0);
3222 }
3223
3224 /*
3225  * It is ok for this function to fail midway and return right away.  t4_detach
3226  * will walk the entire sc->irq list and clean up whatever is valid.
3227  */
3228 static int
3229 setup_intr_handlers(struct adapter *sc)
3230 {
3231         int rc, rid, p, q;
3232         char s[8];
3233         struct irq *irq;
3234         struct port_info *pi;
3235         struct sge_rxq *rxq;
3236 #ifdef TCP_OFFLOAD
3237         struct sge_ofld_rxq *ofld_rxq;
3238 #endif
3239 #ifdef DEV_NETMAP
3240         struct sge_nm_rxq *nm_rxq;
3241 #endif
3242
3243         /*
3244          * Setup interrupts.
3245          */
3246         irq = &sc->irq[0];
3247         rid = sc->intr_type == INTR_INTX ? 0 : 1;
3248         if (sc->intr_count == 1)
3249                 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
3250
3251         /* Multiple interrupts. */
3252         KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
3253             ("%s: too few intr.", __func__));
3254
3255         /* The first one is always error intr */
3256         rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
3257         if (rc != 0)
3258                 return (rc);
3259         irq++;
3260         rid++;
3261
3262         /* The second one is always the firmware event queue */
3263         rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sc->sge.fwq, "evt");
3264         if (rc != 0)
3265                 return (rc);
3266         irq++;
3267         rid++;
3268
3269         for_each_port(sc, p) {
3270                 pi = sc->port[p];
3271
3272                 if (pi->flags & INTR_RXQ) {
3273                         for_each_rxq(pi, q, rxq) {
3274                                 snprintf(s, sizeof(s), "%d.%d", p, q);
3275                                 rc = t4_alloc_irq(sc, irq, rid, t4_intr, rxq,
3276                                     s);
3277                                 if (rc != 0)
3278                                         return (rc);
3279                                 irq++;
3280                                 rid++;
3281                         }
3282                 }
3283 #ifdef TCP_OFFLOAD
3284                 if (pi->flags & INTR_OFLD_RXQ) {
3285                         for_each_ofld_rxq(pi, q, ofld_rxq) {
3286                                 snprintf(s, sizeof(s), "%d,%d", p, q);
3287                                 rc = t4_alloc_irq(sc, irq, rid, t4_intr,
3288                                     ofld_rxq, s);
3289                                 if (rc != 0)
3290                                         return (rc);
3291                                 irq++;
3292                                 rid++;
3293                         }
3294                 }
3295 #endif
3296 #ifdef DEV_NETMAP
3297                 if (pi->flags & INTR_NM_RXQ) {
3298                         for_each_nm_rxq(pi, q, nm_rxq) {
3299                                 snprintf(s, sizeof(s), "%d-%d", p, q);
3300                                 rc = t4_alloc_irq(sc, irq, rid, t4_nm_intr,
3301                                     nm_rxq, s);
3302                                 if (rc != 0)
3303                                         return (rc);
3304                                 irq++;
3305                                 rid++;
3306                         }
3307                 }
3308 #endif
3309         }
3310         MPASS(irq == &sc->irq[sc->intr_count]);
3311
3312         return (0);
3313 }
3314
3315 int
3316 adapter_full_init(struct adapter *sc)
3317 {
3318         int rc, i;
3319
3320         ASSERT_SYNCHRONIZED_OP(sc);
3321         ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3322         KASSERT((sc->flags & FULL_INIT_DONE) == 0,
3323             ("%s: FULL_INIT_DONE already", __func__));
3324
3325         /*
3326          * queues that belong to the adapter (not any particular port).
3327          */
3328         rc = t4_setup_adapter_queues(sc);
3329         if (rc != 0)
3330                 goto done;
3331
3332         for (i = 0; i < nitems(sc->tq); i++) {
3333                 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
3334                     taskqueue_thread_enqueue, &sc->tq[i]);
3335                 if (sc->tq[i] == NULL) {
3336                         device_printf(sc->dev,
3337                             "failed to allocate task queue %d\n", i);
3338                         rc = ENOMEM;
3339                         goto done;
3340                 }
3341                 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
3342                     device_get_nameunit(sc->dev), i);
3343         }
3344
3345         t4_intr_enable(sc);
3346         sc->flags |= FULL_INIT_DONE;
3347 done:
3348         if (rc != 0)
3349                 adapter_full_uninit(sc);
3350
3351         return (rc);
3352 }
3353
3354 int
3355 adapter_full_uninit(struct adapter *sc)
3356 {
3357         int i;
3358
3359         ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3360
3361         t4_teardown_adapter_queues(sc);
3362
3363         for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
3364                 taskqueue_free(sc->tq[i]);
3365                 sc->tq[i] = NULL;
3366         }
3367
3368         sc->flags &= ~FULL_INIT_DONE;
3369
3370         return (0);
3371 }
3372
3373 int
3374 port_full_init(struct port_info *pi)
3375 {
3376         struct adapter *sc = pi->adapter;
3377         struct ifnet *ifp = pi->ifp;
3378         uint16_t *rss;
3379         struct sge_rxq *rxq;
3380         int rc, i, j;
3381
3382         ASSERT_SYNCHRONIZED_OP(sc);
3383         KASSERT((pi->flags & PORT_INIT_DONE) == 0,
3384             ("%s: PORT_INIT_DONE already", __func__));
3385
3386         sysctl_ctx_init(&pi->ctx);
3387         pi->flags |= PORT_SYSCTL_CTX;
3388
3389         /*
3390          * Allocate tx/rx/fl queues for this port.
3391          */
3392         rc = t4_setup_port_queues(pi);
3393         if (rc != 0)
3394                 goto done;      /* error message displayed already */
3395
3396         /*
3397          * Setup RSS for this port.  Save a copy of the RSS table for later use.
3398          */
3399         rss = malloc(pi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
3400         for (i = 0; i < pi->rss_size;) {
3401                 for_each_rxq(pi, j, rxq) {
3402                         rss[i++] = rxq->iq.abs_id;
3403                         if (i == pi->rss_size)
3404                                 break;
3405                 }
3406         }
3407
3408         rc = -t4_config_rss_range(sc, sc->mbox, pi->viid, 0, pi->rss_size, rss,
3409             pi->rss_size);
3410         if (rc != 0) {
3411                 if_printf(ifp, "rss_config failed: %d\n", rc);
3412                 goto done;
3413         }
3414
3415         pi->rss = rss;
3416         pi->flags |= PORT_INIT_DONE;
3417 done:
3418         if (rc != 0)
3419                 port_full_uninit(pi);
3420
3421         return (rc);
3422 }
3423
3424 /*
3425  * Idempotent.
3426  */
3427 int
3428 port_full_uninit(struct port_info *pi)
3429 {
3430         struct adapter *sc = pi->adapter;
3431         int i;
3432         struct sge_rxq *rxq;
3433         struct sge_txq *txq;
3434 #ifdef TCP_OFFLOAD
3435         struct sge_ofld_rxq *ofld_rxq;
3436         struct sge_wrq *ofld_txq;
3437 #endif
3438
3439         if (pi->flags & PORT_INIT_DONE) {
3440
3441                 /* Need to quiesce queues.  XXX: ctrl queues? */
3442
3443                 for_each_txq(pi, i, txq) {
3444                         quiesce_eq(sc, &txq->eq);
3445                 }
3446
3447 #ifdef TCP_OFFLOAD
3448                 for_each_ofld_txq(pi, i, ofld_txq) {
3449                         quiesce_eq(sc, &ofld_txq->eq);
3450                 }
3451 #endif
3452
3453                 for_each_rxq(pi, i, rxq) {
3454                         quiesce_iq(sc, &rxq->iq);
3455                         quiesce_fl(sc, &rxq->fl);
3456                 }
3457
3458 #ifdef TCP_OFFLOAD
3459                 for_each_ofld_rxq(pi, i, ofld_rxq) {
3460                         quiesce_iq(sc, &ofld_rxq->iq);
3461                         quiesce_fl(sc, &ofld_rxq->fl);
3462                 }
3463 #endif
3464                 free(pi->rss, M_CXGBE);
3465         }
3466
3467         t4_teardown_port_queues(pi);
3468         pi->flags &= ~PORT_INIT_DONE;
3469
3470         return (0);
3471 }
3472
3473 static void
3474 quiesce_eq(struct adapter *sc, struct sge_eq *eq)
3475 {
3476         EQ_LOCK(eq);
3477         eq->flags |= EQ_DOOMED;
3478
3479         /*
3480          * Wait for the response to a credit flush if one's
3481          * pending.
3482          */
3483         while (eq->flags & EQ_CRFLUSHED)
3484                 mtx_sleep(eq, &eq->eq_lock, 0, "crflush", 0);
3485         EQ_UNLOCK(eq);
3486
3487         callout_drain(&eq->tx_callout); /* XXX: iffy */
3488         pause("callout", 10);           /* Still iffy */
3489
3490         taskqueue_drain(sc->tq[eq->tx_chan], &eq->tx_task);
3491 }
3492
3493 static void
3494 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
3495 {
3496         (void) sc;      /* unused */
3497
3498         /* Synchronize with the interrupt handler */
3499         while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
3500                 pause("iqfree", 1);
3501 }
3502
3503 static void
3504 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
3505 {
3506         mtx_lock(&sc->sfl_lock);
3507         FL_LOCK(fl);
3508         fl->flags |= FL_DOOMED;
3509         FL_UNLOCK(fl);
3510         mtx_unlock(&sc->sfl_lock);
3511
3512         callout_drain(&sc->sfl_callout);
3513         KASSERT((fl->flags & FL_STARVING) == 0,
3514             ("%s: still starving", __func__));
3515 }
3516
3517 static int
3518 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
3519     driver_intr_t *handler, void *arg, char *name)
3520 {
3521         int rc;
3522
3523         irq->rid = rid;
3524         irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
3525             RF_SHAREABLE | RF_ACTIVE);
3526         if (irq->res == NULL) {
3527                 device_printf(sc->dev,
3528                     "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
3529                 return (ENOMEM);
3530         }
3531
3532         rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
3533             NULL, handler, arg, &irq->tag);
3534         if (rc != 0) {
3535                 device_printf(sc->dev,
3536                     "failed to setup interrupt for rid %d, name %s: %d\n",
3537                     rid, name, rc);
3538         } else if (name)
3539                 bus_describe_intr(sc->dev, irq->res, irq->tag, name);
3540
3541         return (rc);
3542 }
3543
3544 static int
3545 t4_free_irq(struct adapter *sc, struct irq *irq)
3546 {
3547         if (irq->tag)
3548                 bus_teardown_intr(sc->dev, irq->res, irq->tag);
3549         if (irq->res)
3550                 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
3551
3552         bzero(irq, sizeof(*irq));
3553
3554         return (0);
3555 }
3556
3557 static void
3558 reg_block_dump(struct adapter *sc, uint8_t *buf, unsigned int start,
3559     unsigned int end)
3560 {
3561         uint32_t *p = (uint32_t *)(buf + start);
3562
3563         for ( ; start <= end; start += sizeof(uint32_t))
3564                 *p++ = t4_read_reg(sc, start);
3565 }
3566
3567 static void
3568 t4_get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
3569 {
3570         int i, n;
3571         const unsigned int *reg_ranges;
3572         static const unsigned int t4_reg_ranges[] = {
3573                 0x1008, 0x1108,
3574                 0x1180, 0x11b4,
3575                 0x11fc, 0x123c,
3576                 0x1300, 0x173c,
3577                 0x1800, 0x18fc,
3578                 0x3000, 0x30d8,
3579                 0x30e0, 0x5924,
3580                 0x5960, 0x59d4,
3581                 0x5a00, 0x5af8,
3582                 0x6000, 0x6098,
3583                 0x6100, 0x6150,
3584                 0x6200, 0x6208,
3585                 0x6240, 0x6248,
3586                 0x6280, 0x6338,
3587                 0x6370, 0x638c,
3588                 0x6400, 0x643c,
3589                 0x6500, 0x6524,
3590                 0x6a00, 0x6a38,
3591                 0x6a60, 0x6a78,
3592                 0x6b00, 0x6b84,
3593                 0x6bf0, 0x6c84,
3594                 0x6cf0, 0x6d84,
3595                 0x6df0, 0x6e84,
3596                 0x6ef0, 0x6f84,
3597                 0x6ff0, 0x7084,
3598                 0x70f0, 0x7184,
3599                 0x71f0, 0x7284,
3600                 0x72f0, 0x7384,
3601                 0x73f0, 0x7450,
3602                 0x7500, 0x7530,
3603                 0x7600, 0x761c,
3604                 0x7680, 0x76cc,
3605                 0x7700, 0x7798,
3606                 0x77c0, 0x77fc,
3607                 0x7900, 0x79fc,
3608                 0x7b00, 0x7c38,
3609                 0x7d00, 0x7efc,
3610                 0x8dc0, 0x8e1c,
3611                 0x8e30, 0x8e78,
3612                 0x8ea0, 0x8f6c,
3613                 0x8fc0, 0x9074,
3614                 0x90fc, 0x90fc,
3615                 0x9400, 0x9458,
3616                 0x9600, 0x96bc,
3617                 0x9800, 0x9808,
3618                 0x9820, 0x983c,
3619                 0x9850, 0x9864,
3620                 0x9c00, 0x9c6c,
3621                 0x9c80, 0x9cec,
3622                 0x9d00, 0x9d6c,
3623                 0x9d80, 0x9dec,
3624                 0x9e00, 0x9e6c,
3625                 0x9e80, 0x9eec,
3626                 0x9f00, 0x9f6c,
3627                 0x9f80, 0x9fec,
3628                 0xd004, 0xd03c,
3629                 0xdfc0, 0xdfe0,
3630                 0xe000, 0xea7c,
3631                 0xf000, 0x11110,
3632                 0x11118, 0x11190,
3633                 0x19040, 0x1906c,
3634                 0x19078, 0x19080,
3635                 0x1908c, 0x19124,
3636                 0x19150, 0x191b0,
3637                 0x191d0, 0x191e8,
3638                 0x19238, 0x1924c,
3639                 0x193f8, 0x19474,
3640                 0x19490, 0x194f8,
3641                 0x19800, 0x19f30,
3642                 0x1a000, 0x1a06c,
3643                 0x1a0b0, 0x1a120,
3644                 0x1a128, 0x1a138,
3645                 0x1a190, 0x1a1c4,
3646                 0x1a1fc, 0x1a1fc,
3647                 0x1e040, 0x1e04c,
3648                 0x1e284, 0x1e28c,
3649                 0x1e2c0, 0x1e2c0,
3650                 0x1e2e0, 0x1e2e0,
3651                 0x1e300, 0x1e384,
3652                 0x1e3c0, 0x1e3c8,
3653                 0x1e440, 0x1e44c,
3654                 0x1e684, 0x1e68c,
3655                 0x1e6c0, 0x1e6c0,
3656                 0x1e6e0, 0x1e6e0,
3657                 0x1e700, 0x1e784,
3658                 0x1e7c0, 0x1e7c8,
3659                 0x1e840, 0x1e84c,
3660                 0x1ea84, 0x1ea8c,
3661                 0x1eac0, 0x1eac0,
3662                 0x1eae0, 0x1eae0,
3663                 0x1eb00, 0x1eb84,
3664                 0x1ebc0, 0x1ebc8,
3665                 0x1ec40, 0x1ec4c,
3666                 0x1ee84, 0x1ee8c,
3667                 0x1eec0, 0x1eec0,
3668                 0x1eee0, 0x1eee0,
3669                 0x1ef00, 0x1ef84,
3670                 0x1efc0, 0x1efc8,
3671                 0x1f040, 0x1f04c,
3672                 0x1f284, 0x1f28c,
3673                 0x1f2c0, 0x1f2c0,
3674                 0x1f2e0, 0x1f2e0,
3675                 0x1f300, 0x1f384,
3676                 0x1f3c0, 0x1f3c8,
3677                 0x1f440, 0x1f44c,
3678                 0x1f684, 0x1f68c,
3679                 0x1f6c0, 0x1f6c0,
3680                 0x1f6e0, 0x1f6e0,
3681                 0x1f700, 0x1f784,
3682                 0x1f7c0, 0x1f7c8,
3683                 0x1f840, 0x1f84c,
3684                 0x1fa84, 0x1fa8c,
3685                 0x1fac0, 0x1fac0,
3686                 0x1fae0, 0x1fae0,
3687                 0x1fb00, 0x1fb84,
3688                 0x1fbc0, 0x1fbc8,
3689                 0x1fc40, 0x1fc4c,
3690                 0x1fe84, 0x1fe8c,
3691                 0x1fec0, 0x1fec0,
3692                 0x1fee0, 0x1fee0,
3693                 0x1ff00, 0x1ff84,
3694                 0x1ffc0, 0x1ffc8,
3695                 0x20000, 0x2002c,
3696                 0x20100, 0x2013c,
3697                 0x20190, 0x201c8,
3698                 0x20200, 0x20318,
3699                 0x20400, 0x20528,
3700                 0x20540, 0x20614,
3701                 0x21000, 0x21040,
3702                 0x2104c, 0x21060,
3703                 0x210c0, 0x210ec,
3704                 0x21200, 0x21268,
3705                 0x21270, 0x21284,
3706                 0x212fc, 0x21388,
3707                 0x21400, 0x21404,
3708                 0x21500, 0x21518,
3709                 0x2152c, 0x2153c,
3710                 0x21550, 0x21554,
3711                 0x21600, 0x21600,
3712                 0x21608, 0x21628,
3713                 0x21630, 0x2163c,
3714                 0x21700, 0x2171c,
3715                 0x21780, 0x2178c,
3716                 0x21800, 0x21c38,
3717                 0x21c80, 0x21d7c,
3718                 0x21e00, 0x21e04,
3719                 0x22000, 0x2202c,
3720                 0x22100, 0x2213c,
3721                 0x22190, 0x221c8,
3722                 0x22200, 0x22318,
3723                 0x22400, 0x22528,
3724                 0x22540, 0x22614,
3725                 0x23000, 0x23040,
3726                 0x2304c, 0x23060,
3727                 0x230c0, 0x230ec,
3728                 0x23200, 0x23268,
3729                 0x23270, 0x23284,
3730                 0x232fc, 0x23388,
3731                 0x23400, 0x23404,
3732                 0x23500, 0x23518,
3733                 0x2352c, 0x2353c,
3734                 0x23550, 0x23554,
3735                 0x23600, 0x23600,
3736                 0x23608, 0x23628,
3737                 0x23630, 0x2363c,
3738                 0x23700, 0x2371c,
3739                 0x23780, 0x2378c,
3740                 0x23800, 0x23c38,
3741                 0x23c80, 0x23d7c,
3742                 0x23e00, 0x23e04,
3743                 0x24000, 0x2402c,
3744                 0x24100, 0x2413c,
3745                 0x24190, 0x241c8,
3746                 0x24200, 0x24318,
3747                 0x24400, 0x24528,
3748                 0x24540, 0x24614,
3749                 0x25000, 0x25040,
3750                 0x2504c, 0x25060,
3751                 0x250c0, 0x250ec,
3752                 0x25200, 0x25268,
3753                 0x25270, 0x25284,
3754                 0x252fc, 0x25388,
3755                 0x25400, 0x25404,
3756                 0x25500, 0x25518,
3757                 0x2552c, 0x2553c,
3758                 0x25550, 0x25554,
3759                 0x25600, 0x25600,
3760                 0x25608, 0x25628,
3761                 0x25630, 0x2563c,
3762                 0x25700, 0x2571c,
3763                 0x25780, 0x2578c,
3764                 0x25800, 0x25c38,
3765                 0x25c80, 0x25d7c,
3766                 0x25e00, 0x25e04,
3767                 0x26000, 0x2602c,
3768                 0x26100, 0x2613c,
3769                 0x26190, 0x261c8,
3770                 0x26200, 0x26318,
3771                 0x26400, 0x26528,
3772                 0x26540, 0x26614,
3773                 0x27000, 0x27040,
3774                 0x2704c, 0x27060,
3775                 0x270c0, 0x270ec,
3776                 0x27200, 0x27268,
3777                 0x27270, 0x27284,
3778                 0x272fc, 0x27388,
3779                 0x27400, 0x27404,
3780                 0x27500, 0x27518,
3781                 0x2752c, 0x2753c,
3782                 0x27550, 0x27554,
3783                 0x27600, 0x27600,
3784                 0x27608, 0x27628,
3785                 0x27630, 0x2763c,
3786                 0x27700, 0x2771c,
3787                 0x27780, 0x2778c,
3788                 0x27800, 0x27c38,
3789                 0x27c80, 0x27d7c,
3790                 0x27e00, 0x27e04
3791         };
3792         static const unsigned int t5_reg_ranges[] = {
3793                 0x1008, 0x1148,
3794                 0x1180, 0x11b4,
3795                 0x11fc, 0x123c,
3796                 0x1280, 0x173c,
3797                 0x1800, 0x18fc,
3798                 0x3000, 0x3028,
3799                 0x3060, 0x30d8,
3800                 0x30e0, 0x30fc,
3801                 0x3140, 0x357c,
3802                 0x35a8, 0x35cc,
3803                 0x35ec, 0x35ec,
3804                 0x3600, 0x5624,
3805                 0x56cc, 0x575c,
3806                 0x580c, 0x5814,
3807                 0x5890, 0x58bc,
3808                 0x5940, 0x59dc,
3809                 0x59fc, 0x5a18,
3810                 0x5a60, 0x5a9c,
3811                 0x5b94, 0x5bfc,
3812                 0x6000, 0x6040,
3813                 0x6058, 0x614c,
3814                 0x7700, 0x7798,
3815                 0x77c0, 0x78fc,
3816                 0x7b00, 0x7c54,
3817                 0x7d00, 0x7efc,
3818                 0x8dc0, 0x8de0,
3819                 0x8df8, 0x8e84,
3820                 0x8ea0, 0x8f84,
3821                 0x8fc0, 0x90f8,
3822                 0x9400, 0x9470,
3823                 0x9600, 0x96f4,
3824                 0x9800, 0x9808,
3825                 0x9820, 0x983c,
3826                 0x9850, 0x9864,
3827                 0x9c00, 0x9c6c,
3828                 0x9c80, 0x9cec,
3829                 0x9d00, 0x9d6c,
3830                 0x9d80, 0x9dec,
3831                 0x9e00, 0x9e6c,
3832                 0x9e80, 0x9eec,
3833                 0x9f00, 0x9f6c,
3834                 0x9f80, 0xa020,
3835                 0xd004, 0xd03c,
3836                 0xdfc0, 0xdfe0,
3837                 0xe000, 0x11088,
3838                 0x1109c, 0x11110,
3839                 0x11118, 0x1117c,
3840                 0x11190, 0x11204,
3841                 0x19040, 0x1906c,
3842                 0x19078, 0x19080,
3843                 0x1908c, 0x19124,
3844                 0x19150, 0x191b0,
3845                 0x191d0, 0x191e8,
3846                 0x19238, 0x19290,
3847                 0x193f8, 0x19474,
3848                 0x19490, 0x194cc,
3849                 0x194f0, 0x194f8,
3850                 0x19c00, 0x19c60,
3851                 0x19c94, 0x19e10,
3852                 0x19e50, 0x19f34,
3853                 0x19f40, 0x19f50,
3854                 0x19f90, 0x19fe4,
3855                 0x1a000, 0x1a06c,
3856                 0x1a0b0, 0x1a120,
3857                 0x1a128, 0x1a138,
3858                 0x1a190, 0x1a1c4,
3859                 0x1a1fc, 0x1a1fc,
3860                 0x1e008, 0x1e00c,
3861                 0x1e040, 0x1e04c,
3862                 0x1e284, 0x1e290,
3863                 0x1e2c0, 0x1e2c0,
3864                 0x1e2e0, 0x1e2e0,
3865                 0x1e300, 0x1e384,
3866                 0x1e3c0, 0x1e3c8,
3867                 0x1e408, 0x1e40c,
3868                 0x1e440, 0x1e44c,
3869                 0x1e684, 0x1e690,
3870                 0x1e6c0, 0x1e6c0,
3871                 0x1e6e0, 0x1e6e0,
3872                 0x1e700, 0x1e784,
3873                 0x1e7c0, 0x1e7c8,
3874                 0x1e808, 0x1e80c,
3875                 0x1e840, 0x1e84c,
3876                 0x1ea84, 0x1ea90,
3877                 0x1eac0, 0x1eac0,
3878                 0x1eae0, 0x1eae0,
3879                 0x1eb00, 0x1eb84,
3880                 0x1ebc0, 0x1ebc8,
3881                 0x1ec08, 0x1ec0c,
3882                 0x1ec40, 0x1ec4c,
3883                 0x1ee84, 0x1ee90,
3884                 0x1eec0, 0x1eec0,
3885                 0x1eee0, 0x1eee0,
3886                 0x1ef00, 0x1ef84,
3887                 0x1efc0, 0x1efc8,
3888                 0x1f008, 0x1f00c,
3889                 0x1f040, 0x1f04c,
3890                 0x1f284, 0x1f290,
3891                 0x1f2c0, 0x1f2c0,
3892                 0x1f2e0, 0x1f2e0,
3893                 0x1f300, 0x1f384,
3894                 0x1f3c0, 0x1f3c8,
3895                 0x1f408, 0x1f40c,
3896                 0x1f440, 0x1f44c,
3897                 0x1f684, 0x1f690,
3898                 0x1f6c0, 0x1f6c0,
3899                 0x1f6e0, 0x1f6e0,
3900                 0x1f700, 0x1f784,
3901                 0x1f7c0, 0x1f7c8,
3902                 0x1f808, 0x1f80c,
3903                 0x1f840, 0x1f84c,
3904                 0x1fa84, 0x1fa90,
3905                 0x1fac0, 0x1fac0,
3906                 0x1fae0, 0x1fae0,
3907                 0x1fb00, 0x1fb84,
3908                 0x1fbc0, 0x1fbc8,
3909                 0x1fc08, 0x1fc0c,
3910                 0x1fc40, 0x1fc4c,
3911                 0x1fe84, 0x1fe90,
3912                 0x1fec0, 0x1fec0,
3913                 0x1fee0, 0x1fee0,
3914                 0x1ff00, 0x1ff84,
3915                 0x1ffc0, 0x1ffc8,
3916                 0x30000, 0x30030,
3917                 0x30100, 0x30144,
3918                 0x30190, 0x301d0,
3919                 0x30200, 0x30318,
3920                 0x30400, 0x3052c,
3921                 0x30540, 0x3061c,
3922                 0x30800, 0x30834,
3923                 0x308c0, 0x30908,
3924                 0x30910, 0x309ac,
3925                 0x30a00, 0x30a2c,
3926                 0x30a44, 0x30a50,
3927                 0x30a74, 0x30c24,
3928                 0x30d00, 0x30d00,
3929                 0x30d08, 0x30d14,
3930                 0x30d1c, 0x30d20,
3931                 0x30d3c, 0x30d50,
3932                 0x31200, 0x3120c,
3933                 0x31220, 0x31220,
3934                 0x31240, 0x31240,
3935                 0x31600, 0x3160c,
3936                 0x31a00, 0x31a1c,
3937                 0x31e00, 0x31e20,
3938                 0x31e38, 0x31e3c,
3939                 0x31e80, 0x31e80,
3940                 0x31e88, 0x31ea8,
3941                 0x31eb0, 0x31eb4,
3942                 0x31ec8, 0x31ed4,
3943                 0x31fb8, 0x32004,
3944                 0x32200, 0x32200,
3945                 0x32208, 0x32240,
3946                 0x32248, 0x32280,
3947                 0x32288, 0x322c0,
3948                 0x322c8, 0x322fc,
3949                 0x32600, 0x32630,
3950                 0x32a00, 0x32abc,
3951                 0x32b00, 0x32b70,
3952                 0x33000, 0x33048,
3953                 0x33060, 0x3309c,
3954                 0x330f0, 0x33148,
3955                 0x33160, 0x3319c,
3956                 0x331f0, 0x332e4,
3957                 0x332f8, 0x333e4,
3958                 0x333f8, 0x33448,
3959                 0x33460, 0x3349c,
3960                 0x334f0, 0x33548,
3961                 0x33560, 0x3359c,
3962                 0x335f0, 0x336e4,
3963                 0x336f8, 0x337e4,
3964                 0x337f8, 0x337fc,
3965                 0x33814, 0x33814,
3966                 0x3382c, 0x3382c,
3967                 0x33880, 0x3388c,
3968                 0x338e8, 0x338ec,
3969                 0x33900, 0x33948,
3970                 0x33960, 0x3399c,
3971                 0x339f0, 0x33ae4,
3972                 0x33af8, 0x33b10,
3973                 0x33b28, 0x33b28,
3974                 0x33b3c, 0x33b50,
3975                 0x33bf0, 0x33c10,
3976                 0x33c28, 0x33c28,
3977                 0x33c3c, 0x33c50,
3978                 0x33cf0, 0x33cfc,
3979                 0x34000, 0x34030,
3980                 0x34100, 0x34144,
3981                 0x34190, 0x341d0,
3982                 0x34200, 0x34318,
3983                 0x34400, 0x3452c,
3984                 0x34540, 0x3461c,
3985                 0x34800, 0x34834,
3986                 0x348c0, 0x34908,
3987                 0x34910, 0x349ac,
3988                 0x34a00, 0x34a2c,
3989                 0x34a44, 0x34a50,
3990                 0x34a74, 0x34c24,
3991                 0x34d00, 0x34d00,
3992                 0x34d08, 0x34d14,
3993                 0x34d1c, 0x34d20,
3994                 0x34d3c, 0x34d50,
3995                 0x35200, 0x3520c,
3996                 0x35220, 0x35220,
3997                 0x35240, 0x35240,
3998                 0x35600, 0x3560c,
3999                 0x35a00, 0x35a1c,
4000                 0x35e00, 0x35e20,
4001                 0x35e38, 0x35e3c,
4002                 0x35e80, 0x35e80,
4003                 0x35e88, 0x35ea8,
4004                 0x35eb0, 0x35eb4,
4005                 0x35ec8, 0x35ed4,
4006                 0x35fb8, 0x36004,
4007                 0x36200, 0x36200,
4008                 0x36208, 0x36240,
4009                 0x36248, 0x36280,
4010                 0x36288, 0x362c0,
4011                 0x362c8, 0x362fc,
4012                 0x36600, 0x36630,
4013                 0x36a00, 0x36abc,
4014                 0x36b00, 0x36b70,
4015                 0x37000, 0x37048,
4016                 0x37060, 0x3709c,
4017                 0x370f0, 0x37148,
4018                 0x37160, 0x3719c,
4019                 0x371f0, 0x372e4,
4020                 0x372f8, 0x373e4,
4021                 0x373f8, 0x37448,
4022                 0x37460, 0x3749c,
4023                 0x374f0, 0x37548,
4024                 0x37560, 0x3759c,
4025                 0x375f0, 0x376e4,
4026                 0x376f8, 0x377e4,
4027                 0x377f8, 0x377fc,
4028                 0x37814, 0x37814,
4029                 0x3782c, 0x3782c,
4030                 0x37880, 0x3788c,
4031                 0x378e8, 0x378ec,
4032                 0x37900, 0x37948,
4033                 0x37960, 0x3799c,
4034                 0x379f0, 0x37ae4,
4035                 0x37af8, 0x37b10,
4036                 0x37b28, 0x37b28,
4037                 0x37b3c, 0x37b50,
4038                 0x37bf0, 0x37c10,
4039                 0x37c28, 0x37c28,
4040                 0x37c3c, 0x37c50,
4041                 0x37cf0, 0x37cfc,
4042                 0x38000, 0x38030,
4043                 0x38100, 0x38144,
4044                 0x38190, 0x381d0,
4045                 0x38200, 0x38318,
4046                 0x38400, 0x3852c,
4047                 0x38540, 0x3861c,
4048                 0x38800, 0x38834,
4049                 0x388c0, 0x38908,
4050                 0x38910, 0x389ac,
4051                 0x38a00, 0x38a2c,
4052                 0x38a44, 0x38a50,
4053                 0x38a74, 0x38c24,
4054                 0x38d00, 0x38d00,
4055                 0x38d08, 0x38d14,
4056                 0x38d1c, 0x38d20,
4057                 0x38d3c, 0x38d50,
4058                 0x39200, 0x3920c,
4059                 0x39220, 0x39220,
4060                 0x39240, 0x39240,
4061                 0x39600, 0x3960c,
4062                 0x39a00, 0x39a1c,
4063                 0x39e00, 0x39e20,
4064                 0x39e38, 0x39e3c,
4065                 0x39e80, 0x39e80,
4066                 0x39e88, 0x39ea8,
4067                 0x39eb0, 0x39eb4,
4068                 0x39ec8, 0x39ed4,
4069                 0x39fb8, 0x3a004,
4070                 0x3a200, 0x3a200,
4071                 0x3a208, 0x3a240,
4072                 0x3a248, 0x3a280,
4073                 0x3a288, 0x3a2c0,
4074                 0x3a2c8, 0x3a2fc,
4075                 0x3a600, 0x3a630,
4076                 0x3aa00, 0x3aabc,
4077                 0x3ab00, 0x3ab70,
4078                 0x3b000, 0x3b048,
4079                 0x3b060, 0x3b09c,
4080                 0x3b0f0, 0x3b148,
4081                 0x3b160, 0x3b19c,
4082                 0x3b1f0, 0x3b2e4,
4083                 0x3b2f8, 0x3b3e4,
4084                 0x3b3f8, 0x3b448,
4085                 0x3b460, 0x3b49c,
4086                 0x3b4f0, 0x3b548,
4087                 0x3b560, 0x3b59c,
4088                 0x3b5f0, 0x3b6e4,
4089                 0x3b6f8, 0x3b7e4,
4090                 0x3b7f8, 0x3b7fc,
4091                 0x3b814, 0x3b814,
4092                 0x3b82c, 0x3b82c,
4093                 0x3b880, 0x3b88c,
4094                 0x3b8e8, 0x3b8ec,
4095                 0x3b900, 0x3b948,
4096                 0x3b960, 0x3b99c,
4097                 0x3b9f0, 0x3bae4,
4098                 0x3baf8, 0x3bb10,
4099                 0x3bb28, 0x3bb28,
4100                 0x3bb3c, 0x3bb50,
4101                 0x3bbf0, 0x3bc10,
4102                 0x3bc28, 0x3bc28,
4103                 0x3bc3c, 0x3bc50,
4104                 0x3bcf0, 0x3bcfc,
4105                 0x3c000, 0x3c030,
4106                 0x3c100, 0x3c144,
4107                 0x3c190, 0x3c1d0,
4108                 0x3c200, 0x3c318,
4109                 0x3c400, 0x3c52c,
4110                 0x3c540, 0x3c61c,
4111                 0x3c800, 0x3c834,
4112                 0x3c8c0, 0x3c908,
4113                 0x3c910, 0x3c9ac,
4114                 0x3ca00, 0x3ca2c,
4115                 0x3ca44, 0x3ca50,
4116                 0x3ca74, 0x3cc24,
4117                 0x3cd00, 0x3cd00,
4118                 0x3cd08, 0x3cd14,
4119                 0x3cd1c, 0x3cd20,
4120                 0x3cd3c, 0x3cd50,
4121                 0x3d200, 0x3d20c,
4122                 0x3d220, 0x3d220,
4123                 0x3d240, 0x3d240,
4124                 0x3d600, 0x3d60c,
4125                 0x3da00, 0x3da1c,
4126                 0x3de00, 0x3de20,
4127                 0x3de38, 0x3de3c,
4128                 0x3de80, 0x3de80,
4129                 0x3de88, 0x3dea8,
4130                 0x3deb0, 0x3deb4,
4131                 0x3dec8, 0x3ded4,
4132                 0x3dfb8, 0x3e004,
4133                 0x3e200, 0x3e200,
4134                 0x3e208, 0x3e240,
4135                 0x3e248, 0x3e280,
4136                 0x3e288, 0x3e2c0,
4137                 0x3e2c8, 0x3e2fc,
4138                 0x3e600, 0x3e630,
4139                 0x3ea00, 0x3eabc,
4140                 0x3eb00, 0x3eb70,
4141                 0x3f000, 0x3f048,
4142                 0x3f060, 0x3f09c,
4143                 0x3f0f0, 0x3f148,
4144                 0x3f160, 0x3f19c,
4145                 0x3f1f0, 0x3f2e4,
4146                 0x3f2f8, 0x3f3e4,
4147                 0x3f3f8, 0x3f448,
4148                 0x3f460, 0x3f49c,
4149                 0x3f4f0, 0x3f548,
4150                 0x3f560, 0x3f59c,
4151                 0x3f5f0, 0x3f6e4,
4152                 0x3f6f8, 0x3f7e4,
4153                 0x3f7f8, 0x3f7fc,
4154                 0x3f814, 0x3f814,
4155                 0x3f82c, 0x3f82c,
4156                 0x3f880, 0x3f88c,
4157                 0x3f8e8, 0x3f8ec,
4158                 0x3f900, 0x3f948,
4159                 0x3f960, 0x3f99c,
4160                 0x3f9f0, 0x3fae4,
4161                 0x3faf8, 0x3fb10,
4162                 0x3fb28, 0x3fb28,
4163                 0x3fb3c, 0x3fb50,
4164                 0x3fbf0, 0x3fc10,
4165                 0x3fc28, 0x3fc28,
4166                 0x3fc3c, 0x3fc50,
4167                 0x3fcf0, 0x3fcfc,
4168                 0x40000, 0x4000c,
4169                 0x40040, 0x40068,
4170                 0x4007c, 0x40144,
4171                 0x40180, 0x4018c,
4172                 0x40200, 0x40298,
4173                 0x402ac, 0x4033c,
4174                 0x403f8, 0x403fc,
4175                 0x41304, 0x413c4,
4176                 0x41400, 0x4141c,
4177                 0x41480, 0x414d0,
4178                 0x44000, 0x44078,
4179                 0x440c0, 0x44278,
4180                 0x442c0, 0x44478,
4181                 0x444c0, 0x44678,
4182                 0x446c0, 0x44878,
4183                 0x448c0, 0x449fc,
4184                 0x45000, 0x45068,
4185                 0x45080, 0x45084,
4186                 0x450a0, 0x450b0,
4187                 0x45200, 0x45268,
4188                 0x45280, 0x45284,
4189                 0x452a0, 0x452b0,
4190                 0x460c0, 0x460e4,
4191                 0x47000, 0x4708c,
4192                 0x47200, 0x47250,
4193                 0x47400, 0x47420,
4194                 0x47600, 0x47618,
4195                 0x47800, 0x47814,
4196                 0x48000, 0x4800c,
4197                 0x48040, 0x48068,
4198                 0x4807c, 0x48144,
4199                 0x48180, 0x4818c,
4200                 0x48200, 0x48298,
4201                 0x482ac, 0x4833c,
4202                 0x483f8, 0x483fc,
4203                 0x49304, 0x493c4,
4204                 0x49400, 0x4941c,
4205                 0x49480, 0x494d0,
4206                 0x4c000, 0x4c078,
4207                 0x4c0c0, 0x4c278,
4208                 0x4c2c0, 0x4c478,
4209                 0x4c4c0, 0x4c678,
4210                 0x4c6c0, 0x4c878,
4211                 0x4c8c0, 0x4c9fc,
4212                 0x4d000, 0x4d068,
4213                 0x4d080, 0x4d084,
4214                 0x4d0a0, 0x4d0b0,
4215                 0x4d200, 0x4d268,
4216                 0x4d280, 0x4d284,
4217                 0x4d2a0, 0x4d2b0,
4218                 0x4e0c0, 0x4e0e4,
4219                 0x4f000, 0x4f08c,
4220                 0x4f200, 0x4f250,
4221                 0x4f400, 0x4f420,
4222                 0x4f600, 0x4f618,
4223                 0x4f800, 0x4f814,
4224                 0x50000, 0x500cc,
4225                 0x50400, 0x50400,
4226                 0x50800, 0x508cc,
4227                 0x50c00, 0x50c00,
4228                 0x51000, 0x5101c,
4229                 0x51300, 0x51308,
4230         };
4231
4232         if (is_t4(sc)) {
4233                 reg_ranges = &t4_reg_ranges[0];
4234                 n = nitems(t4_reg_ranges);
4235         } else {
4236                 reg_ranges = &t5_reg_ranges[0];
4237                 n = nitems(t5_reg_ranges);
4238         }
4239
4240         regs->version = chip_id(sc) | chip_rev(sc) << 10;
4241         for (i = 0; i < n; i += 2)
4242                 reg_block_dump(sc, buf, reg_ranges[i], reg_ranges[i + 1]);
4243 }
4244
4245 static void
4246 cxgbe_tick(void *arg)
4247 {
4248         struct port_info *pi = arg;
4249         struct adapter *sc = pi->adapter;
4250         struct ifnet *ifp = pi->ifp;
4251         struct sge_txq *txq;
4252         int i, drops;
4253         struct port_stats *s = &pi->stats;
4254
4255         PORT_LOCK(pi);
4256         if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
4257                 PORT_UNLOCK(pi);
4258                 return; /* without scheduling another callout */
4259         }
4260
4261         t4_get_port_stats(sc, pi->tx_chan, s);
4262
4263         ifp->if_opackets = s->tx_frames - s->tx_pause;
4264         ifp->if_ipackets = s->rx_frames - s->rx_pause;
4265         ifp->if_obytes = s->tx_octets - s->tx_pause * 64;
4266         ifp->if_ibytes = s->rx_octets - s->rx_pause * 64;
4267         ifp->if_omcasts = s->tx_mcast_frames - s->tx_pause;
4268         ifp->if_imcasts = s->rx_mcast_frames - s->rx_pause;
4269         ifp->if_iqdrops = s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
4270             s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
4271             s->rx_trunc3;
4272         for (i = 0; i < 4; i++) {
4273                 if (pi->rx_chan_map & (1 << i)) {
4274                         uint32_t v;
4275
4276                         /*
4277                          * XXX: indirect reads from the same ADDR/DATA pair can
4278                          * race with each other.
4279                          */
4280                         t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
4281                             1, A_TP_MIB_TNL_CNG_DROP_0 + i);
4282                         ifp->if_iqdrops += v;
4283                 }
4284         }
4285
4286         drops = s->tx_drop;
4287         for_each_txq(pi, i, txq)
4288                 drops += txq->br->br_drops;
4289         ifp->if_snd.ifq_drops = drops;
4290
4291         ifp->if_oerrors = s->tx_error_frames;
4292         ifp->if_ierrors = s->rx_jabber + s->rx_runt + s->rx_too_long +
4293             s->rx_fcs_err + s->rx_len_err;
4294
4295         callout_schedule(&pi->tick, hz);
4296         PORT_UNLOCK(pi);
4297 }
4298
4299 static void
4300 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
4301 {
4302         struct ifnet *vlan;
4303
4304         if (arg != ifp || ifp->if_type != IFT_ETHER)
4305                 return;
4306
4307         vlan = VLAN_DEVAT(ifp, vid);
4308         VLAN_SETCOOKIE(vlan, ifp);
4309 }
4310
4311 static int
4312 cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
4313 {
4314
4315 #ifdef INVARIANTS
4316         panic("%s: opcode 0x%02x on iq %p with payload %p",
4317             __func__, rss->opcode, iq, m);
4318 #else
4319         log(LOG_ERR, "%s: opcode 0x%02x on iq %p with payload %p\n",
4320             __func__, rss->opcode, iq, m);
4321         m_freem(m);
4322 #endif
4323         return (EDOOFUS);
4324 }
4325
4326 int
4327 t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h)
4328 {
4329         uintptr_t *loc, new;
4330
4331         if (opcode >= nitems(sc->cpl_handler))
4332                 return (EINVAL);
4333
4334         new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled;
4335         loc = (uintptr_t *) &sc->cpl_handler[opcode];
4336         atomic_store_rel_ptr(loc, new);
4337
4338         return (0);
4339 }
4340
4341 static int
4342 an_not_handled(struct sge_iq *iq, const struct rsp_ctrl *ctrl)
4343 {
4344
4345 #ifdef INVARIANTS
4346         panic("%s: async notification on iq %p (ctrl %p)", __func__, iq, ctrl);
4347 #else
4348         log(LOG_ERR, "%s: async notification on iq %p (ctrl %p)\n",
4349             __func__, iq, ctrl);
4350 #endif
4351         return (EDOOFUS);
4352 }
4353
4354 int
4355 t4_register_an_handler(struct adapter *sc, an_handler_t h)
4356 {
4357         uintptr_t *loc, new;
4358
4359         new = h ? (uintptr_t)h : (uintptr_t)an_not_handled;
4360         loc = (uintptr_t *) &sc->an_handler;
4361         atomic_store_rel_ptr(loc, new);
4362
4363         return (0);
4364 }
4365
4366 static int
4367 fw_msg_not_handled(struct adapter *sc, const __be64 *rpl)
4368 {
4369         const struct cpl_fw6_msg *cpl =
4370             __containerof(rpl, struct cpl_fw6_msg, data[0]);
4371
4372 #ifdef INVARIANTS
4373         panic("%s: fw_msg type %d", __func__, cpl->type);
4374 #else
4375         log(LOG_ERR, "%s: fw_msg type %d\n", __func__, cpl->type);
4376 #endif
4377         return (EDOOFUS);
4378 }
4379
4380 int
4381 t4_register_fw_msg_handler(struct adapter *sc, int type, fw_msg_handler_t h)
4382 {
4383         uintptr_t *loc, new;
4384
4385         if (type >= nitems(sc->fw_msg_handler))
4386                 return (EINVAL);
4387
4388         /*
4389          * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
4390          * handler dispatch table.  Reject any attempt to install a handler for
4391          * this subtype.
4392          */
4393         if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL)
4394                 return (EINVAL);
4395
4396         new = h ? (uintptr_t)h : (uintptr_t)fw_msg_not_handled;
4397         loc = (uintptr_t *) &sc->fw_msg_handler[type];
4398         atomic_store_rel_ptr(loc, new);
4399
4400         return (0);
4401 }
4402
4403 static int
4404 t4_sysctls(struct adapter *sc)
4405 {
4406         struct sysctl_ctx_list *ctx;
4407         struct sysctl_oid *oid;
4408         struct sysctl_oid_list *children, *c0;
4409         static char *caps[] = {
4410                 "\20\1PPP\2QFC\3DCBX",                  /* caps[0] linkcaps */
4411                 "\20\1NIC\2VM\3IDS\4UM\5UM_ISGL"        /* caps[1] niccaps */
4412                     "\6HASHFILTER\7ETHOFLD",
4413                 "\20\1TOE",                             /* caps[2] toecaps */
4414                 "\20\1RDDP\2RDMAC",                     /* caps[3] rdmacaps */
4415                 "\20\1INITIATOR_PDU\2TARGET_PDU"        /* caps[4] iscsicaps */
4416                     "\3INITIATOR_CNXOFLD\4TARGET_CNXOFLD"
4417                     "\5INITIATOR_SSNOFLD\6TARGET_SSNOFLD",
4418                 "\20\1INITIATOR\2TARGET\3CTRL_OFLD"     /* caps[5] fcoecaps */
4419                     "\4PO_INITIAOR\5PO_TARGET"
4420         };
4421         static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
4422
4423         ctx = device_get_sysctl_ctx(sc->dev);
4424
4425         /*
4426          * dev.t4nex.X.
4427          */
4428         oid = device_get_sysctl_tree(sc->dev);
4429         c0 = children = SYSCTL_CHILDREN(oid);
4430
4431         sc->sc_do_rxcopy = 1;
4432         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
4433             &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
4434
4435         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
4436             sc->params.nports, "# of ports");
4437
4438         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
4439             NULL, chip_rev(sc), "chip hardware revision");
4440
4441         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
4442             CTLFLAG_RD, sc->fw_version, 0, "firmware version");
4443
4444         SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
4445             CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
4446
4447         SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
4448             sc->cfcsum, "config file checksum");
4449
4450         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
4451             CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells,
4452             sysctl_bitfield, "A", "available doorbells");
4453
4454         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkcaps",
4455             CTLTYPE_STRING | CTLFLAG_RD, caps[0], sc->linkcaps,
4456             sysctl_bitfield, "A", "available link capabilities");
4457
4458         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "niccaps",
4459             CTLTYPE_STRING | CTLFLAG_RD, caps[1], sc->niccaps,
4460             sysctl_bitfield, "A", "available NIC capabilities");
4461
4462         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "toecaps",
4463             CTLTYPE_STRING | CTLFLAG_RD, caps[2], sc->toecaps,
4464             sysctl_bitfield, "A", "available TCP offload capabilities");
4465
4466         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdmacaps",
4467             CTLTYPE_STRING | CTLFLAG_RD, caps[3], sc->rdmacaps,
4468             sysctl_bitfield, "A", "available RDMA capabilities");
4469
4470         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "iscsicaps",
4471             CTLTYPE_STRING | CTLFLAG_RD, caps[4], sc->iscsicaps,
4472             sysctl_bitfield, "A", "available iSCSI capabilities");
4473
4474         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoecaps",
4475             CTLTYPE_STRING | CTLFLAG_RD, caps[5], sc->fcoecaps,
4476             sysctl_bitfield, "A", "available FCoE capabilities");
4477
4478         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
4479             sc->params.vpd.cclk, "core clock frequency (in KHz)");
4480
4481         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
4482             CTLTYPE_STRING | CTLFLAG_RD, sc->sge.timer_val,
4483             sizeof(sc->sge.timer_val), sysctl_int_array, "A",
4484             "interrupt holdoff timer values (us)");
4485
4486         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
4487             CTLTYPE_STRING | CTLFLAG_RD, sc->sge.counter_val,
4488             sizeof(sc->sge.counter_val), sysctl_int_array, "A",
4489             "interrupt holdoff packet counter values");
4490
4491         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
4492             NULL, sc->tids.nftids, "number of filters");
4493
4494         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
4495             CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
4496             "chip temperature (in Celsius)");
4497
4498         t4_sge_sysctls(sc, ctx, children);
4499
4500         sc->lro_timeout = 100;
4501         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
4502             &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
4503
4504 #ifdef SBUF_DRAIN
4505         /*
4506          * dev.t4nex.X.misc.  Marked CTLFLAG_SKIP to avoid information overload.
4507          */
4508         oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
4509             CTLFLAG_RD | CTLFLAG_SKIP, NULL,
4510             "logs and miscellaneous information");
4511         children = SYSCTL_CHILDREN(oid);
4512
4513         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
4514             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4515             sysctl_cctrl, "A", "congestion control");
4516
4517         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
4518             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4519             sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
4520
4521         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
4522             CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
4523             sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
4524
4525         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
4526             CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
4527             sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
4528
4529         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
4530             CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
4531             sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
4532
4533         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
4534             CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
4535             sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
4536
4537         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
4538             CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
4539             sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
4540
4541         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
4542             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4543             sysctl_cim_la, "A", "CIM logic analyzer");
4544
4545         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
4546             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4547             sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
4548
4549         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
4550             CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
4551             sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
4552
4553         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
4554             CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
4555             sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
4556
4557         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
4558             CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
4559             sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
4560
4561         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
4562             CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
4563             sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
4564
4565         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
4566             CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
4567             sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
4568
4569         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
4570             CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
4571             sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
4572
4573         if (is_t5(sc)) {
4574                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
4575                     CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
4576                     sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
4577
4578                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
4579                     CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
4580                     sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
4581         }
4582
4583         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
4584             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4585             sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
4586
4587         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
4588             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4589             sysctl_cim_qcfg, "A", "CIM queue configuration");
4590
4591         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
4592             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4593             sysctl_cpl_stats, "A", "CPL statistics");
4594
4595         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
4596             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4597             sysctl_ddp_stats, "A", "non-TCP DDP statistics");
4598
4599         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
4600             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4601             sysctl_devlog, "A", "firmware's device log");
4602
4603         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
4604             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4605             sysctl_fcoe_stats, "A", "FCoE statistics");
4606
4607         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
4608             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4609             sysctl_hw_sched, "A", "hardware scheduler ");
4610
4611         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
4612             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4613             sysctl_l2t, "A", "hardware L2 table");
4614
4615         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
4616             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4617             sysctl_lb_stats, "A", "loopback statistics");
4618
4619         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
4620             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4621             sysctl_meminfo, "A", "memory regions");
4622
4623         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
4624             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4625             sysctl_mps_tcam, "A", "MPS TCAM entries");
4626
4627         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
4628             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4629             sysctl_path_mtus, "A", "path MTUs");
4630
4631         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
4632             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4633             sysctl_pm_stats, "A", "PM statistics");
4634
4635         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
4636             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4637             sysctl_rdma_stats, "A", "RDMA statistics");
4638
4639         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
4640             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4641             sysctl_tcp_stats, "A", "TCP statistics");
4642
4643         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
4644             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4645             sysctl_tids, "A", "TID information");
4646
4647         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
4648             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4649             sysctl_tp_err_stats, "A", "TP error statistics");
4650
4651         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
4652             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4653             sysctl_tp_la, "A", "TP logic analyzer");
4654
4655         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
4656             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4657             sysctl_tx_rate, "A", "Tx rate");
4658
4659         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
4660             CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4661             sysctl_ulprx_la, "A", "ULPRX logic analyzer");
4662
4663         if (is_t5(sc)) {
4664                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
4665                     CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4666                     sysctl_wcwr_stats, "A", "write combined work requests");
4667         }
4668 #endif
4669
4670 #ifdef TCP_OFFLOAD
4671         if (is_offload(sc)) {
4672                 /*
4673                  * dev.t4nex.X.toe.
4674                  */
4675                 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
4676                     NULL, "TOE parameters");
4677                 children = SYSCTL_CHILDREN(oid);
4678
4679                 sc->tt.sndbuf = 256 * 1024;
4680                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
4681                     &sc->tt.sndbuf, 0, "max hardware send buffer size");
4682
4683                 sc->tt.ddp = 0;
4684                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
4685                     &sc->tt.ddp, 0, "DDP allowed");
4686
4687                 sc->tt.indsz = G_INDICATESIZE(t4_read_reg(sc, A_TP_PARA_REG5));
4688                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "indsz", CTLFLAG_RW,
4689                     &sc->tt.indsz, 0, "DDP max indicate size allowed");
4690
4691                 sc->tt.ddp_thres =
4692                     G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2));
4693                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp_thres", CTLFLAG_RW,
4694                     &sc->tt.ddp_thres, 0, "DDP threshold");
4695
4696                 sc->tt.rx_coalesce = 1;
4697                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
4698                     CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
4699
4700                 sc->tt.tx_align = 1;
4701                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
4702                     CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
4703         }
4704 #endif
4705
4706
4707         return (0);
4708 }
4709
4710 static int
4711 cxgbe_sysctls(struct port_info *pi)
4712 {
4713         struct sysctl_ctx_list *ctx;
4714         struct sysctl_oid *oid;
4715         struct sysctl_oid_list *children;
4716         struct adapter *sc = pi->adapter;
4717
4718         ctx = device_get_sysctl_ctx(pi->dev);
4719
4720         /*
4721          * dev.cxgbe.X.
4722          */
4723         oid = device_get_sysctl_tree(pi->dev);
4724         children = SYSCTL_CHILDREN(oid);
4725
4726         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
4727            CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
4728         if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
4729                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
4730                     CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
4731                     "PHY temperature (in Celsius)");
4732                 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
4733                     CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
4734                     "PHY firmware version");
4735         }
4736         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
4737             &pi->nrxq, 0, "# of rx queues");
4738         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
4739             &pi->ntxq, 0, "# of tx queues");
4740         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
4741             &pi->first_rxq, 0, "index of first rx queue");
4742         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
4743             &pi->first_txq, 0, "index of first tx queue");
4744         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq", CTLTYPE_INT |
4745             CTLFLAG_RW, pi, 0, sysctl_noflowq, "IU",
4746             "Reserve queue 0 for non-flowid packets");
4747
4748 #ifdef TCP_OFFLOAD
4749         if (is_offload(sc)) {
4750                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
4751                     &pi->nofldrxq, 0,
4752                     "# of rx queues for offloaded TCP connections");
4753                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
4754                     &pi->nofldtxq, 0,
4755                     "# of tx queues for offloaded TCP connections");
4756                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
4757                     CTLFLAG_RD, &pi->first_ofld_rxq, 0,
4758                     "index of first TOE rx queue");
4759                 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
4760                     CTLFLAG_RD, &pi->first_ofld_txq, 0,
4761                     "index of first TOE tx queue");
4762         }
4763 #endif
4764 #ifdef DEV_NETMAP
4765         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
4766             &pi->nnmrxq, 0, "# of rx queues for netmap");
4767         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
4768             &pi->nnmtxq, 0, "# of tx queues for netmap");
4769         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
4770             CTLFLAG_RD, &pi->first_nm_rxq, 0,
4771             "index of first netmap rx queue");
4772         SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
4773             CTLFLAG_RD, &pi->first_nm_txq, 0,
4774             "index of first netmap tx queue");
4775 #endif
4776
4777         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
4778             CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_tmr_idx, "I",
4779             "holdoff timer index");
4780         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
4781             CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_holdoff_pktc_idx, "I",
4782             "holdoff packet counter index");
4783
4784         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
4785             CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_qsize_rxq, "I",
4786             "rx queue size");
4787         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
4788             CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_qsize_txq, "I",
4789             "tx queue size");
4790
4791         SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
4792             CTLTYPE_STRING | CTLFLAG_RW, pi, PAUSE_TX, sysctl_pause_settings,
4793             "A", "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)");
4794
4795         /*
4796          * dev.cxgbe.X.stats.
4797          */
4798         oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4799             NULL, "port statistics");
4800         children = SYSCTL_CHILDREN(oid);
4801
4802 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
4803         SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
4804             CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
4805             sysctl_handle_t4_reg64, "QU", desc)
4806
4807         SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
4808             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
4809         SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
4810             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
4811         SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
4812             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
4813         SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
4814             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
4815         SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
4816             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
4817         SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
4818             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
4819         SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
4820             "# of tx frames in this range",
4821             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
4822         SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
4823             "# of tx frames in this range",
4824             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
4825         SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
4826             "# of tx frames in this range",
4827             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
4828         SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
4829             "# of tx frames in this range",
4830             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
4831         SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
4832             "# of tx frames in this range",
4833             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
4834         SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
4835             "# of tx frames in this range",
4836             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
4837         SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
4838             "# of tx frames in this range",
4839             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
4840         SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
4841             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
4842         SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
4843             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
4844         SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
4845             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
4846         SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
4847             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
4848         SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
4849             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
4850         SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
4851             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
4852         SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
4853             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
4854         SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
4855             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
4856         SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
4857             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
4858         SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
4859             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
4860
4861         SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
4862             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
4863         SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
4864             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
4865         SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
4866             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
4867         SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
4868             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
4869         SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
4870             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
4871         SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
4872             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
4873         SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
4874             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
4875         SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
4876             "# of frames received with bad FCS",
4877             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
4878         SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
4879             "# of frames received with length error",
4880             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
4881         SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
4882             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
4883         SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
4884             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
4885         SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
4886             "# of rx frames in this range",
4887             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
4888         SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
4889             "# of rx frames in this range",
4890             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
4891         SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
4892             "# of rx frames in this range",
4893             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
4894         SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
4895             "# of rx frames in this range",
4896             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
4897         SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
4898             "# of rx frames in this range",
4899             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
4900         SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
4901             "# of rx frames in this range",
4902             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
4903         SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
4904             "# of rx frames in this range",
4905             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
4906         SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
4907             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
4908         SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
4909             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
4910         SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
4911             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
4912         SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
4913             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
4914         SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
4915             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
4916         SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
4917             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
4918         SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
4919             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
4920         SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
4921             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
4922         SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
4923             PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
4924
4925 #undef SYSCTL_ADD_T4_REG64
4926
4927 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
4928         SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
4929             &pi->stats.name, desc)
4930
4931         /* We get these from port_stats and they may be stale by upto 1s */
4932         SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
4933             "# drops due to buffer-group 0 overflows");
4934         SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
4935             "# drops due to buffer-group 1 overflows");
4936         SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
4937             "# drops due to buffer-group 2 overflows");
4938         SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
4939             "# drops due to buffer-group 3 overflows");
4940         SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
4941             "# of buffer-group 0 truncated packets");
4942         SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
4943             "# of buffer-group 1 truncated packets");
4944         SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
4945             "# of buffer-group 2 truncated packets");
4946         SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
4947             "# of buffer-group 3 truncated packets");
4948
4949 #undef SYSCTL_ADD_T4_PORTSTAT
4950
4951         return (0);
4952 }
4953
4954 static int
4955 sysctl_int_array(SYSCTL_HANDLER_ARGS)
4956 {
4957         int rc, *i, space = 0;
4958         struct sbuf sb;
4959
4960         sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
4961         for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
4962                 if (space)
4963                         sbuf_printf(&sb, " ");
4964                 sbuf_printf(&sb, "%d", *i);
4965                 space = 1;
4966         }
4967         sbuf_finish(&sb);
4968         rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
4969         sbuf_delete(&sb);
4970         return (rc);
4971 }
4972
4973 static int
4974 sysctl_bitfield(SYSCTL_HANDLER_ARGS)
4975 {
4976         int rc;
4977         struct sbuf *sb;
4978
4979         rc = sysctl_wire_old_buffer(req, 0);
4980         if (rc != 0)
4981                 return(rc);
4982
4983         sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
4984         if (sb == NULL)
4985                 return (ENOMEM);
4986
4987         sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
4988         rc = sbuf_finish(sb);
4989         sbuf_delete(sb);
4990
4991         return (rc);
4992 }
4993
4994 static int
4995 sysctl_btphy(SYSCTL_HANDLER_ARGS)
4996 {
4997         struct port_info *pi = arg1;
4998         int op = arg2;
4999         struct adapter *sc = pi->adapter;
5000         u_int v;
5001         int rc;
5002
5003         rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4btt");
5004         if (rc)
5005                 return (rc);
5006         /* XXX: magic numbers */
5007         rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
5008             &v);
5009         end_synchronized_op(sc, 0);
5010         if (rc)
5011                 return (rc);
5012         if (op == 0)
5013                 v /= 256;
5014
5015         rc = sysctl_handle_int(oidp, &v, 0, req);
5016         return (rc);
5017 }
5018
5019 static int
5020 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
5021 {
5022         struct port_info *pi = arg1;
5023         int rc, val;
5024
5025         val = pi->rsrv_noflowq;
5026         rc = sysctl_handle_int(oidp, &val, 0, req);
5027         if (rc != 0 || req->newptr == NULL)
5028                 return (rc);
5029
5030         if ((val >= 1) && (pi->ntxq > 1))
5031                 pi->rsrv_noflowq = 1;
5032         else
5033                 pi->rsrv_noflowq = 0;
5034
5035         return (rc);
5036 }
5037
5038 static int
5039 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
5040 {
5041         struct port_info *pi = arg1;
5042         struct adapter *sc = pi->adapter;
5043         int idx, rc, i;
5044         struct sge_rxq *rxq;
5045 #ifdef TCP_OFFLOAD
5046         struct sge_ofld_rxq *ofld_rxq;
5047 #endif
5048         uint8_t v;
5049
5050         idx = pi->tmr_idx;
5051
5052         rc = sysctl_handle_int(oidp, &idx, 0, req);
5053         if (rc != 0 || req->newptr == NULL)
5054                 return (rc);
5055
5056         if (idx < 0 || idx >= SGE_NTIMERS)
5057                 return (EINVAL);
5058
5059         rc = begin_synchronized_op(sc, pi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5060             "t4tmr");
5061         if (rc)
5062                 return (rc);
5063
5064         v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(pi->pktc_idx != -1);
5065         for_each_rxq(pi, i, rxq) {
5066 #ifdef atomic_store_rel_8
5067                 atomic_store_rel_8(&rxq->iq.intr_params, v);
5068 #else
5069                 rxq->iq.intr_params = v;
5070 #endif
5071         }
5072 #ifdef TCP_OFFLOAD
5073         for_each_ofld_rxq(pi, i, ofld_rxq) {
5074 #ifdef atomic_store_rel_8
5075                 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
5076 #else
5077                 ofld_rxq->iq.intr_params = v;
5078 #endif
5079         }
5080 #endif
5081         pi->tmr_idx = idx;
5082
5083         end_synchronized_op(sc, LOCK_HELD);
5084         return (0);
5085 }
5086
5087 static int
5088 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
5089 {
5090         struct port_info *pi = arg1;
5091         struct adapter *sc = pi->adapter;
5092         int idx, rc;
5093
5094         idx = pi->pktc_idx;
5095
5096         rc = sysctl_handle_int(oidp, &idx, 0, req);
5097         if (rc != 0 || req->newptr == NULL)
5098                 return (rc);
5099
5100         if (idx < -1 || idx >= SGE_NCOUNTERS)
5101                 return (EINVAL);
5102
5103         rc = begin_synchronized_op(sc, pi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5104             "t4pktc");
5105         if (rc)
5106                 return (rc);
5107
5108         if (pi->flags & PORT_INIT_DONE)
5109                 rc = EBUSY; /* cannot be changed once the queues are created */
5110         else
5111                 pi->pktc_idx = idx;
5112
5113         end_synchronized_op(sc, LOCK_HELD);
5114         return (rc);
5115 }
5116
5117 static int
5118 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
5119 {
5120         struct port_info *pi = arg1;
5121         struct adapter *sc = pi->adapter;
5122         int qsize, rc;
5123
5124         qsize = pi->qsize_rxq;
5125
5126         rc = sysctl_handle_int(oidp, &qsize, 0, req);
5127         if (rc != 0 || req->newptr == NULL)
5128                 return (rc);
5129
5130         if (qsize < 128 || (qsize & 7))
5131                 return (EINVAL);
5132
5133         rc = begin_synchronized_op(sc, pi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5134             "t4rxqs");
5135         if (rc)
5136                 return (rc);
5137
5138         if (pi->flags & PORT_INIT_DONE)
5139                 rc = EBUSY; /* cannot be changed once the queues are created */
5140         else
5141                 pi->qsize_rxq = qsize;
5142
5143         end_synchronized_op(sc, LOCK_HELD);
5144         return (rc);
5145 }
5146
5147 static int
5148 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
5149 {
5150         struct port_info *pi = arg1;
5151         struct adapter *sc = pi->adapter;
5152         int qsize, rc;
5153
5154         qsize = pi->qsize_txq;
5155
5156         rc = sysctl_handle_int(oidp, &qsize, 0, req);
5157         if (rc != 0 || req->newptr == NULL)
5158                 return (rc);
5159
5160         /* bufring size must be powerof2 */
5161         if (qsize < 128 || !powerof2(qsize))
5162                 return (EINVAL);
5163
5164         rc = begin_synchronized_op(sc, pi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5165             "t4txqs");
5166         if (rc)
5167                 return (rc);
5168
5169         if (pi->flags & PORT_INIT_DONE)
5170                 rc = EBUSY; /* cannot be changed once the queues are created */
5171         else
5172                 pi->qsize_txq = qsize;
5173
5174         end_synchronized_op(sc, LOCK_HELD);
5175         return (rc);
5176 }
5177
5178 static int
5179 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
5180 {
5181         struct port_info *pi = arg1;
5182         struct adapter *sc = pi->adapter;
5183         struct link_config *lc = &pi->link_cfg;
5184         int rc;
5185
5186         if (req->newptr == NULL) {
5187                 struct sbuf *sb;
5188                 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX";
5189
5190                 rc = sysctl_wire_old_buffer(req, 0);
5191                 if (rc != 0)
5192                         return(rc);
5193
5194                 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5195                 if (sb == NULL)
5196                         return (ENOMEM);
5197
5198                 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits);
5199                 rc = sbuf_finish(sb);
5200                 sbuf_delete(sb);
5201         } else {
5202                 char s[2];
5203                 int n;
5204
5205                 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX));
5206                 s[1] = 0;
5207
5208                 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
5209                 if (rc != 0)
5210                         return(rc);
5211
5212                 if (s[1] != 0)
5213                         return (EINVAL);
5214                 if (s[0] < '0' || s[0] > '9')
5215                         return (EINVAL);        /* not a number */
5216                 n = s[0] - '0';
5217                 if (n & ~(PAUSE_TX | PAUSE_RX))
5218                         return (EINVAL);        /* some other bit is set too */
5219
5220                 rc = begin_synchronized_op(sc, pi, SLEEP_OK | INTR_OK, "t4PAUSE");
5221                 if (rc)
5222                         return (rc);
5223                 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) {
5224                         int link_ok = lc->link_ok;
5225
5226                         lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX);
5227                         lc->requested_fc |= n;
5228                         rc = -t4_link_start(sc, sc->mbox, pi->tx_chan, lc);
5229                         lc->link_ok = link_ok;  /* restore */
5230                 }
5231                 end_synchronized_op(sc, 0);
5232         }
5233
5234         return (rc);
5235 }
5236
5237 static int
5238 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
5239 {
5240         struct adapter *sc = arg1;
5241         int reg = arg2;
5242         uint64_t val;
5243
5244         val = t4_read_reg64(sc, reg);
5245
5246         return (sysctl_handle_64(oidp, &val, 0, req));
5247 }
5248
5249 static int
5250 sysctl_temperature(SYSCTL_HANDLER_ARGS)
5251 {
5252         struct adapter *sc = arg1;
5253         int rc, t;
5254         uint32_t param, val;
5255
5256         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
5257         if (rc)
5258                 return (rc);
5259         param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5260             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5261             V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
5262         rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, &param, &val);
5263         end_synchronized_op(sc, 0);
5264         if (rc)
5265                 return (rc);
5266
5267         /* unknown is returned as 0 but we display -1 in that case */
5268         t = val == 0 ? -1 : val;
5269
5270         rc = sysctl_handle_int(oidp, &t, 0, req);
5271         return (rc);
5272 }
5273
5274 #ifdef SBUF_DRAIN
5275 static int
5276 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
5277 {
5278         struct adapter *sc = arg1;
5279         struct sbuf *sb;
5280         int rc, i;
5281         uint16_t incr[NMTUS][NCCTRL_WIN];
5282         static const char *dec_fac[] = {
5283                 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
5284                 "0.9375"
5285         };
5286
5287         rc = sysctl_wire_old_buffer(req, 0);
5288         if (rc != 0)
5289                 return (rc);
5290
5291         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5292         if (sb == NULL)
5293                 return (ENOMEM);
5294
5295         t4_read_cong_tbl(sc, incr);
5296
5297         for (i = 0; i < NCCTRL_WIN; ++i) {
5298                 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
5299                     incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
5300                     incr[5][i], incr[6][i], incr[7][i]);
5301                 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
5302                     incr[8][i], incr[9][i], incr[10][i], incr[11][i],
5303                     incr[12][i], incr[13][i], incr[14][i], incr[15][i],
5304                     sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
5305         }
5306
5307         rc = sbuf_finish(sb);
5308         sbuf_delete(sb);
5309
5310         return (rc);
5311 }
5312
5313 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
5314         "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI",   /* ibq's */
5315         "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
5316         "SGE0-RX", "SGE1-RX"    /* additional obq's (T5 onwards) */
5317 };
5318
5319 static int
5320 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
5321 {
5322         struct adapter *sc = arg1;
5323         struct sbuf *sb;
5324         int rc, i, n, qid = arg2;
5325         uint32_t *buf, *p;
5326         char *qtype;
5327         u_int cim_num_obq = is_t4(sc) ? CIM_NUM_OBQ : CIM_NUM_OBQ_T5;
5328
5329         KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
5330             ("%s: bad qid %d\n", __func__, qid));
5331
5332         if (qid < CIM_NUM_IBQ) {
5333                 /* inbound queue */
5334                 qtype = "IBQ";
5335                 n = 4 * CIM_IBQ_SIZE;
5336                 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5337                 rc = t4_read_cim_ibq(sc, qid, buf, n);
5338         } else {
5339                 /* outbound queue */
5340                 qtype = "OBQ";
5341                 qid -= CIM_NUM_IBQ;
5342                 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
5343                 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5344                 rc = t4_read_cim_obq(sc, qid, buf, n);
5345         }
5346
5347         if (rc < 0) {
5348                 rc = -rc;
5349                 goto done;
5350         }
5351         n = rc * sizeof(uint32_t);      /* rc has # of words actually read */
5352
5353         rc = sysctl_wire_old_buffer(req, 0);
5354         if (rc != 0)
5355                 goto done;
5356
5357         sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5358         if (sb == NULL) {
5359                 rc = ENOMEM;
5360                 goto done;
5361         }
5362
5363         sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
5364         for (i = 0, p = buf; i < n; i += 16, p += 4)
5365                 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
5366                     p[2], p[3]);
5367
5368         rc = sbuf_finish(sb);
5369         sbuf_delete(sb);
5370 done:
5371         free(buf, M_CXGBE);
5372         return (rc);
5373 }
5374
5375 static int
5376 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
5377 {
5378         struct adapter *sc = arg1;
5379         u_int cfg;
5380         struct sbuf *sb;
5381         uint32_t *buf, *p;
5382         int rc;
5383
5384         rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5385         if (rc != 0)
5386                 return (rc);
5387
5388         rc = sysctl_wire_old_buffer(req, 0);
5389         if (rc != 0)
5390                 return (rc);
5391
5392         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5393         if (sb == NULL)
5394                 return (ENOMEM);
5395
5396         buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5397             M_ZERO | M_WAITOK);
5398
5399         rc = -t4_cim_read_la(sc, buf, NULL);
5400         if (rc != 0)
5401                 goto done;
5402
5403         sbuf_printf(sb, "Status   Data      PC%s",
5404             cfg & F_UPDBGLACAPTPCONLY ? "" :
5405             "     LS0Stat  LS0Addr             LS0Data");
5406
5407         KASSERT((sc->params.cim_la_size & 7) == 0,
5408             ("%s: p will walk off the end of buf", __func__));
5409
5410         for (p = buf; p < &buf[sc->params.cim_la_size]; p += 8) {
5411                 if (cfg & F_UPDBGLACAPTPCONLY) {
5412                         sbuf_printf(sb, "\n  %02x   %08x %08x", p[5] & 0xff,
5413                             p[6], p[7]);
5414                         sbuf_printf(sb, "\n  %02x   %02x%06x %02x%06x",
5415                             (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
5416                             p[4] & 0xff, p[5] >> 8);
5417                         sbuf_printf(sb, "\n  %02x   %x%07x %x%07x",
5418                             (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5419                             p[1] & 0xf, p[2] >> 4);
5420                 } else {
5421                         sbuf_printf(sb,
5422                             "\n  %02x   %x%07x %x%07x %08x %08x "
5423                             "%08x%08x%08x%08x",
5424                             (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5425                             p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
5426                             p[6], p[7]);
5427                 }
5428         }
5429
5430         rc = sbuf_finish(sb);
5431         sbuf_delete(sb);
5432 done:
5433         free(buf, M_CXGBE);
5434         return (rc);
5435 }
5436
5437 static int
5438 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
5439 {
5440         struct adapter *sc = arg1;
5441         u_int i;
5442         struct sbuf *sb;
5443         uint32_t *buf, *p;
5444         int rc;
5445
5446         rc = sysctl_wire_old_buffer(req, 0);
5447         if (rc != 0)
5448                 return (rc);
5449
5450         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5451         if (sb == NULL)
5452                 return (ENOMEM);
5453
5454         buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
5455             M_ZERO | M_WAITOK);
5456
5457         t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
5458         p = buf;
5459
5460         for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5461                 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
5462                     p[1], p[0]);
5463         }
5464
5465         sbuf_printf(sb, "\n\nCnt ID Tag UE       Data       RDY VLD");
5466         for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5467                 sbuf_printf(sb, "\n%3u %2u  %x   %u %08x%08x  %u   %u",
5468                     (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
5469                     (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
5470                     (p[1] >> 2) | ((p[2] & 3) << 30),
5471                     (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
5472                     p[0] & 1);
5473         }
5474
5475         rc = sbuf_finish(sb);
5476         sbuf_delete(sb);
5477         free(buf, M_CXGBE);
5478         return (rc);
5479 }
5480
5481 static int
5482 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
5483 {
5484         struct adapter *sc = arg1;
5485         u_int i;
5486         struct sbuf *sb;
5487         uint32_t *buf, *p;
5488         int rc;
5489
5490         rc = sysctl_wire_old_buffer(req, 0);
5491         if (rc != 0)
5492                 return (rc);
5493
5494         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5495         if (sb == NULL)
5496                 return (ENOMEM);
5497
5498         buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
5499             M_ZERO | M_WAITOK);
5500
5501         t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
5502         p = buf;
5503
5504         sbuf_printf(sb, "Cntl ID DataBE   Addr                 Data");
5505         for (i = 0; i < CIM_MALA_SIZE; i++, p += 6) {
5506                 sbuf_printf(sb, "\n %02x  %02x  %04x  %08x %08x%08x%08x%08x",
5507                     (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
5508                     p[4], p[3], p[2], p[1], p[0]);
5509         }
5510
5511         sbuf_printf(sb, "\n\nCntl ID               Data");
5512         for (i = 0; i < CIM_MALA_SIZE; i++, p += 6) {
5513                 sbuf_printf(sb, "\n %02x  %02x %08x%08x%08x%08x",
5514                     (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
5515         }
5516
5517         rc = sbuf_finish(sb);
5518         sbuf_delete(sb);
5519         free(buf, M_CXGBE);
5520         return (rc);
5521 }
5522
5523 static int
5524 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
5525 {
5526         struct adapter *sc = arg1;
5527         struct sbuf *sb;
5528         int rc, i;
5529         uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5530         uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5531         uint16_t thres[CIM_NUM_IBQ];
5532         uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
5533         uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
5534         u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
5535
5536         if (is_t4(sc)) {
5537                 cim_num_obq = CIM_NUM_OBQ;
5538                 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
5539                 obq_rdaddr = A_UP_OBQ_0_REALADDR;
5540         } else {
5541                 cim_num_obq = CIM_NUM_OBQ_T5;
5542                 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
5543                 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
5544         }
5545         nq = CIM_NUM_IBQ + cim_num_obq;
5546
5547         rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
5548         if (rc == 0)
5549                 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
5550         if (rc != 0)
5551                 return (rc);
5552
5553         t4_read_cimq_cfg(sc, base, size, thres);
5554
5555         rc = sysctl_wire_old_buffer(req, 0);
5556         if (rc != 0)
5557                 return (rc);
5558
5559         sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5560         if (sb == NULL)
5561                 return (ENOMEM);
5562
5563         sbuf_printf(sb, "Queue  Base  Size Thres RdPtr WrPtr  SOP  EOP Avail");
5564
5565         for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
5566                 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x  %4x %4u %4u %5u",
5567                     qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
5568                     G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5569                     G_QUEREMFLITS(p[2]) * 16);
5570         for ( ; i < nq; i++, p += 4, wr += 2)
5571                 sbuf_printf(sb, "\n%7s %5x %5u %12x  %4x %4u %4u %5u", qname[i],
5572                     base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
5573                     wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5574                     G_QUEREMFLITS(p[2]) * 16);
5575
5576         rc = sbuf_finish(sb);
5577         sbuf_delete(sb);
5578
5579         return (rc);
5580 }
5581
5582 static int
5583 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
5584 {
5585         struct adapter *sc = arg1;
5586         struct sbuf *sb;
5587         int rc;
5588         struct tp_cpl_stats stats;
5589
5590         rc = sysctl_wire_old_buffer(req, 0);
5591         if (rc != 0)
5592                 return (rc);
5593
5594         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5595         if (sb == NULL)
5596                 return (ENOMEM);
5597
5598         t4_tp_get_cpl_stats(sc, &stats);
5599
5600         sbuf_printf(sb, "                 channel 0  channel 1  channel 2  "
5601             "channel 3\n");
5602         sbuf_printf(sb, "CPL requests:   %10u %10u %10u %10u\n",
5603                    stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
5604         sbuf_printf(sb, "CPL responses:  %10u %10u %10u %10u",
5605                    stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
5606
5607         rc = sbuf_finish(sb);
5608         sbuf_delete(sb);
5609
5610         return (rc);
5611 }
5612
5613 static int
5614 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
5615 {
5616         struct adapter *sc = arg1;
5617         struct sbuf *sb;
5618         int rc;
5619         struct tp_usm_stats stats;
5620
5621         rc = sysctl_wire_old_buffer(req, 0);
5622         if (rc != 0)
5623                 return(rc);
5624
5625         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5626         if (sb == NULL)
5627                 return (ENOMEM);
5628
5629         t4_get_usm_stats(sc, &stats);
5630
5631         sbuf_printf(sb, "Frames: %u\n", stats.frames);
5632         sbuf_printf(sb, "Octets: %ju\n", stats.octets);
5633         sbuf_printf(sb, "Drops:  %u", stats.drops);
5634
5635         rc = sbuf_finish(sb);
5636         sbuf_delete(sb);
5637
5638         return (rc);
5639 }
5640
5641 const char *devlog_level_strings[] = {
5642         [FW_DEVLOG_LEVEL_EMERG]         = "EMERG",
5643         [FW_DEVLOG_LEVEL_CRIT]          = "CRIT",
5644         [FW_DEVLOG_LEVEL_ERR]           = "ERR",
5645         [FW_DEVLOG_LEVEL_NOTICE]        = "NOTICE",
5646         [FW_DEVLOG_LEVEL_INFO]          = "INFO",
5647         [FW_DEVLOG_LEVEL_DEBUG]         = "DEBUG"
5648 };
5649
5650 const char *devlog_facility_strings[] = {
5651         [FW_DEVLOG_FACILITY_CORE]       = "CORE",
5652         [FW_DEVLOG_FACILITY_CF]         = "CF",
5653         [FW_DEVLOG_FACILITY_SCHED]      = "SCHED",
5654         [FW_DEVLOG_FACILITY_TIMER]      = "TIMER",
5655         [FW_DEVLOG_FACILITY_RES]        = "RES",
5656         [FW_DEVLOG_FACILITY_HW]         = "HW",
5657         [FW_DEVLOG_FACILITY_FLR]        = "FLR",
5658         [FW_DEVLOG_FACILITY_DMAQ]       = "DMAQ",
5659         [FW_DEVLOG_FACILITY_PHY]        = "PHY",
5660         [FW_DEVLOG_FACILITY_MAC]        = "MAC",
5661         [FW_DEVLOG_FACILITY_PORT]       = "PORT",
5662         [FW_DEVLOG_FACILITY_VI]         = "VI",
5663         [FW_DEVLOG_FACILITY_FILTER]     = "FILTER",
5664         [FW_DEVLOG_FACILITY_ACL]        = "ACL",
5665         [FW_DEVLOG_FACILITY_TM]         = "TM",
5666         [FW_DEVLOG_FACILITY_QFC]        = "QFC",
5667         [FW_DEVLOG_FACILITY_DCB]        = "DCB",
5668         [FW_DEVLOG_FACILITY_ETH]        = "ETH",
5669         [FW_DEVLOG_FACILITY_OFLD]       = "OFLD",
5670         [FW_DEVLOG_FACILITY_RI]         = "RI",
5671         [FW_DEVLOG_FACILITY_ISCSI]      = "ISCSI",
5672         [FW_DEVLOG_FACILITY_FCOE]       = "FCOE",
5673         [FW_DEVLOG_FACILITY_FOISCSI]    = "FOISCSI",
5674         [FW_DEVLOG_FACILITY_FOFCOE]     = "FOFCOE"
5675 };
5676
5677 static int
5678 sysctl_devlog(SYSCTL_HANDLER_ARGS)
5679 {
5680         struct adapter *sc = arg1;
5681         struct devlog_params *dparams = &sc->params.devlog;
5682         struct fw_devlog_e *buf, *e;
5683         int i, j, rc, nentries, first = 0, m;
5684         struct sbuf *sb;
5685         uint64_t ftstamp = UINT64_MAX;
5686
5687         if (dparams->start == 0) {
5688                 dparams->memtype = FW_MEMTYPE_EDC0;
5689                 dparams->start = 0x84000;
5690                 dparams->size = 32768;
5691         }
5692
5693         nentries = dparams->size / sizeof(struct fw_devlog_e);
5694
5695         buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
5696         if (buf == NULL)
5697                 return (ENOMEM);
5698
5699         m = fwmtype_to_hwmtype(dparams->memtype);
5700         rc = -t4_mem_read(sc, m, dparams->start, dparams->size, (void *)buf);
5701         if (rc != 0)
5702                 goto done;
5703
5704         for (i = 0; i < nentries; i++) {
5705                 e = &buf[i];
5706
5707                 if (e->timestamp == 0)
5708                         break;  /* end */
5709
5710                 e->timestamp = be64toh(e->timestamp);
5711                 e->seqno = be32toh(e->seqno);
5712                 for (j = 0; j < 8; j++)
5713                         e->params[j] = be32toh(e->params[j]);
5714
5715                 if (e->timestamp < ftstamp) {
5716                         ftstamp = e->timestamp;
5717                         first = i;
5718                 }
5719         }
5720
5721         if (buf[first].timestamp == 0)
5722                 goto done;      /* nothing in the log */
5723
5724         rc = sysctl_wire_old_buffer(req, 0);
5725         if (rc != 0)
5726                 goto done;
5727
5728         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5729         if (sb == NULL) {
5730                 rc = ENOMEM;
5731                 goto done;
5732         }
5733         sbuf_printf(sb, "%10s  %15s  %8s  %8s  %s\n",
5734             "Seq#", "Tstamp", "Level", "Facility", "Message");
5735
5736         i = first;
5737         do {
5738                 e = &buf[i];
5739                 if (e->timestamp == 0)
5740                         break;  /* end */
5741
5742                 sbuf_printf(sb, "%10d  %15ju  %8s  %8s  ",
5743                     e->seqno, e->timestamp,
5744                     (e->level < nitems(devlog_level_strings) ?
5745                         devlog_level_strings[e->level] : "UNKNOWN"),
5746                     (e->facility < nitems(devlog_facility_strings) ?
5747                         devlog_facility_strings[e->facility] : "UNKNOWN"));
5748                 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
5749                     e->params[2], e->params[3], e->params[4],
5750                     e->params[5], e->params[6], e->params[7]);
5751
5752                 if (++i == nentries)
5753                         i = 0;
5754         } while (i != first);
5755
5756         rc = sbuf_finish(sb);
5757         sbuf_delete(sb);
5758 done:
5759         free(buf, M_CXGBE);
5760         return (rc);
5761 }
5762
5763 static int
5764 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
5765 {
5766         struct adapter *sc = arg1;
5767         struct sbuf *sb;
5768         int rc;
5769         struct tp_fcoe_stats stats[4];
5770
5771         rc = sysctl_wire_old_buffer(req, 0);
5772         if (rc != 0)
5773                 return (rc);
5774
5775         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5776         if (sb == NULL)
5777                 return (ENOMEM);
5778
5779         t4_get_fcoe_stats(sc, 0, &stats[0]);
5780         t4_get_fcoe_stats(sc, 1, &stats[1]);
5781         t4_get_fcoe_stats(sc, 2, &stats[2]);
5782         t4_get_fcoe_stats(sc, 3, &stats[3]);
5783
5784         sbuf_printf(sb, "                   channel 0        channel 1        "
5785             "channel 2        channel 3\n");
5786         sbuf_printf(sb, "octetsDDP:  %16ju %16ju %16ju %16ju\n",
5787             stats[0].octetsDDP, stats[1].octetsDDP, stats[2].octetsDDP,
5788             stats[3].octetsDDP);
5789         sbuf_printf(sb, "framesDDP:  %16u %16u %16u %16u\n", stats[0].framesDDP,
5790             stats[1].framesDDP, stats[2].framesDDP, stats[3].framesDDP);
5791         sbuf_printf(sb, "framesDrop: %16u %16u %16u %16u",
5792             stats[0].framesDrop, stats[1].framesDrop, stats[2].framesDrop,
5793             stats[3].framesDrop);
5794
5795         rc = sbuf_finish(sb);
5796         sbuf_delete(sb);
5797
5798         return (rc);
5799 }
5800
5801 static int
5802 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
5803 {
5804         struct adapter *sc = arg1;
5805         struct sbuf *sb;
5806         int rc, i;
5807         unsigned int map, kbps, ipg, mode;
5808         unsigned int pace_tab[NTX_SCHED];
5809
5810         rc = sysctl_wire_old_buffer(req, 0);
5811         if (rc != 0)
5812                 return (rc);
5813
5814         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5815         if (sb == NULL)
5816                 return (ENOMEM);
5817
5818         map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
5819         mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
5820         t4_read_pace_tbl(sc, pace_tab);
5821
5822         sbuf_printf(sb, "Scheduler  Mode   Channel  Rate (Kbps)   "
5823             "Class IPG (0.1 ns)   Flow IPG (us)");
5824
5825         for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
5826                 t4_get_tx_sched(sc, i, &kbps, &ipg);
5827                 sbuf_printf(sb, "\n    %u      %-5s     %u     ", i,
5828                     (mode & (1 << i)) ? "flow" : "class", map & 3);
5829                 if (kbps)
5830                         sbuf_printf(sb, "%9u     ", kbps);
5831                 else
5832                         sbuf_printf(sb, " disabled     ");
5833
5834                 if (ipg)
5835                         sbuf_printf(sb, "%13u        ", ipg);
5836                 else
5837                         sbuf_printf(sb, "     disabled        ");
5838
5839                 if (pace_tab[i])
5840                         sbuf_printf(sb, "%10u", pace_tab[i]);
5841                 else
5842                         sbuf_printf(sb, "  disabled");
5843         }
5844
5845         rc = sbuf_finish(sb);
5846         sbuf_delete(sb);
5847
5848         return (rc);
5849 }
5850
5851 static int
5852 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
5853 {
5854         struct adapter *sc = arg1;
5855         struct sbuf *sb;
5856         int rc, i, j;
5857         uint64_t *p0, *p1;
5858         struct lb_port_stats s[2];
5859         static const char *stat_name[] = {
5860                 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
5861                 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
5862                 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
5863                 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
5864                 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
5865                 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
5866                 "BG2FramesTrunc:", "BG3FramesTrunc:"
5867         };
5868
5869         rc = sysctl_wire_old_buffer(req, 0);
5870         if (rc != 0)
5871                 return (rc);
5872
5873         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5874         if (sb == NULL)
5875                 return (ENOMEM);
5876
5877         memset(s, 0, sizeof(s));
5878
5879         for (i = 0; i < 4; i += 2) {
5880                 t4_get_lb_stats(sc, i, &s[0]);
5881                 t4_get_lb_stats(sc, i + 1, &s[1]);
5882
5883                 p0 = &s[0].octets;
5884                 p1 = &s[1].octets;
5885                 sbuf_printf(sb, "%s                       Loopback %u"
5886                     "           Loopback %u", i == 0 ? "" : "\n", i, i + 1);
5887
5888                 for (j = 0; j < nitems(stat_name); j++)
5889                         sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
5890                                    *p0++, *p1++);
5891         }
5892
5893         rc = sbuf_finish(sb);
5894         sbuf_delete(sb);
5895
5896         return (rc);
5897 }
5898
5899 static int
5900 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
5901 {
5902         int rc = 0;
5903         struct port_info *pi = arg1;
5904         struct sbuf *sb;
5905         static const char *linkdnreasons[] = {
5906                 "non-specific", "remote fault", "autoneg failed", "reserved3",
5907                 "PHY overheated", "unknown", "rx los", "reserved7"
5908         };
5909
5910         rc = sysctl_wire_old_buffer(req, 0);
5911         if (rc != 0)
5912                 return(rc);
5913         sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
5914         if (sb == NULL)
5915                 return (ENOMEM);
5916
5917         if (pi->linkdnrc < 0)
5918                 sbuf_printf(sb, "n/a");
5919         else if (pi->linkdnrc < nitems(linkdnreasons))
5920                 sbuf_printf(sb, "%s", linkdnreasons[pi->linkdnrc]);
5921         else
5922                 sbuf_printf(sb, "%d", pi->linkdnrc);
5923
5924         rc = sbuf_finish(sb);
5925         sbuf_delete(sb);
5926
5927         return (rc);
5928 }
5929
5930 struct mem_desc {
5931         unsigned int base;
5932         unsigned int limit;
5933         unsigned int idx;
5934 };
5935
5936 static int
5937 mem_desc_cmp(const void *a, const void *b)
5938 {
5939         return ((const struct mem_desc *)a)->base -
5940                ((const struct mem_desc *)b)->base;
5941 }
5942
5943 static void
5944 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
5945     unsigned int to)
5946 {
5947         unsigned int size;
5948
5949         size = to - from + 1;
5950         if (size == 0)
5951                 return;
5952
5953         /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
5954         sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
5955 }
5956
5957 static int
5958 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
5959 {
5960         struct adapter *sc = arg1;
5961         struct sbuf *sb;
5962         int rc, i, n;
5963         uint32_t lo, hi, used, alloc;
5964         static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
5965         static const char *region[] = {
5966                 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
5967                 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
5968                 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
5969                 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
5970                 "RQUDP region:", "PBL region:", "TXPBL region:",
5971                 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
5972                 "On-chip queues:"
5973         };
5974         struct mem_desc avail[4];
5975         struct mem_desc mem[nitems(region) + 3];        /* up to 3 holes */
5976         struct mem_desc *md = mem;
5977
5978         rc = sysctl_wire_old_buffer(req, 0);
5979         if (rc != 0)
5980                 return (rc);
5981
5982         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5983         if (sb == NULL)
5984                 return (ENOMEM);
5985
5986         for (i = 0; i < nitems(mem); i++) {
5987                 mem[i].limit = 0;
5988                 mem[i].idx = i;
5989         }
5990
5991         /* Find and sort the populated memory ranges */
5992         i = 0;
5993         lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
5994         if (lo & F_EDRAM0_ENABLE) {
5995                 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
5996                 avail[i].base = G_EDRAM0_BASE(hi) << 20;
5997                 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
5998                 avail[i].idx = 0;
5999                 i++;
6000         }
6001         if (lo & F_EDRAM1_ENABLE) {
6002                 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
6003                 avail[i].base = G_EDRAM1_BASE(hi) << 20;
6004                 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
6005                 avail[i].idx = 1;
6006                 i++;
6007         }
6008         if (lo & F_EXT_MEM_ENABLE) {
6009                 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
6010                 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
6011                 avail[i].limit = avail[i].base +
6012                     (G_EXT_MEM_SIZE(hi) << 20);
6013                 avail[i].idx = is_t4(sc) ? 2 : 3;       /* Call it MC for T4 */
6014                 i++;
6015         }
6016         if (!is_t4(sc) && lo & F_EXT_MEM1_ENABLE) {
6017                 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
6018                 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
6019                 avail[i].limit = avail[i].base +
6020                     (G_EXT_MEM1_SIZE(hi) << 20);
6021                 avail[i].idx = 4;
6022                 i++;
6023         }
6024         if (!i)                                    /* no memory available */
6025                 return 0;
6026         qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
6027
6028         (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
6029         (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
6030         (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
6031         (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
6032         (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
6033         (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
6034         (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
6035         (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
6036         (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
6037
6038         /* the next few have explicit upper bounds */
6039         md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
6040         md->limit = md->base - 1 +
6041                     t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
6042                     G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
6043         md++;
6044
6045         md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
6046         md->limit = md->base - 1 +
6047                     t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
6048                     G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
6049         md++;
6050
6051         if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6052                 hi = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
6053                 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
6054                 md->limit = (sc->tids.ntids - hi) * 16 + md->base - 1;
6055         } else {
6056                 md->base = 0;
6057                 md->idx = nitems(region);  /* hide it */
6058         }
6059         md++;
6060
6061 #define ulp_region(reg) \
6062         md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
6063         (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
6064
6065         ulp_region(RX_ISCSI);
6066         ulp_region(RX_TDDP);
6067         ulp_region(TX_TPT);
6068         ulp_region(RX_STAG);
6069         ulp_region(RX_RQ);
6070         ulp_region(RX_RQUDP);
6071         ulp_region(RX_PBL);
6072         ulp_region(TX_PBL);
6073 #undef ulp_region
6074
6075         md->base = 0;
6076         md->idx = nitems(region);
6077         if (!is_t4(sc) && t4_read_reg(sc, A_SGE_CONTROL2) & F_VFIFO_ENABLE) {
6078                 md->base = G_BASEADDR(t4_read_reg(sc, A_SGE_DBVFIFO_BADDR));
6079                 md->limit = md->base + (G_DBVFIFO_SIZE((t4_read_reg(sc,
6080                     A_SGE_DBVFIFO_SIZE))) << 2) - 1;
6081         }
6082         md++;
6083
6084         md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
6085         md->limit = md->base + sc->tids.ntids - 1;
6086         md++;
6087         md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
6088         md->limit = md->base + sc->tids.ntids - 1;
6089         md++;
6090
6091         md->base = sc->vres.ocq.start;
6092         if (sc->vres.ocq.size)
6093                 md->limit = md->base + sc->vres.ocq.size - 1;
6094         else
6095                 md->idx = nitems(region);  /* hide it */
6096         md++;
6097
6098         /* add any address-space holes, there can be up to 3 */
6099         for (n = 0; n < i - 1; n++)
6100                 if (avail[n].limit < avail[n + 1].base)
6101                         (md++)->base = avail[n].limit;
6102         if (avail[n].limit)
6103                 (md++)->base = avail[n].limit;
6104
6105         n = md - mem;
6106         qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
6107
6108         for (lo = 0; lo < i; lo++)
6109                 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
6110                                 avail[lo].limit - 1);
6111
6112         sbuf_printf(sb, "\n");
6113         for (i = 0; i < n; i++) {
6114                 if (mem[i].idx >= nitems(region))
6115                         continue;                        /* skip holes */
6116                 if (!mem[i].limit)
6117                         mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
6118                 mem_region_show(sb, region[mem[i].idx], mem[i].base,
6119                                 mem[i].limit);
6120         }
6121
6122         sbuf_printf(sb, "\n");
6123         lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
6124         hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
6125         mem_region_show(sb, "uP RAM:", lo, hi);
6126
6127         lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
6128         hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
6129         mem_region_show(sb, "uP Extmem2:", lo, hi);
6130
6131         lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
6132         sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
6133                    G_PMRXMAXPAGE(lo),
6134                    t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
6135                    (lo & F_PMRXNUMCHN) ? 2 : 1);
6136
6137         lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
6138         hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
6139         sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
6140                    G_PMTXMAXPAGE(lo),
6141                    hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
6142                    hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
6143         sbuf_printf(sb, "%u p-structs\n",
6144                    t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
6145
6146         for (i = 0; i < 4; i++) {
6147                 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
6148                 if (is_t4(sc)) {
6149                         used = G_USED(lo);
6150                         alloc = G_ALLOC(lo);
6151                 } else {
6152                         used = G_T5_USED(lo);
6153                         alloc = G_T5_ALLOC(lo);
6154                 }
6155                 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
6156                            i, used, alloc);
6157         }
6158         for (i = 0; i < 4; i++) {
6159                 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
6160                 if (is_t4(sc)) {
6161                         used = G_USED(lo);
6162                         alloc = G_ALLOC(lo);
6163                 } else {
6164                         used = G_T5_USED(lo);
6165                         alloc = G_T5_ALLOC(lo);
6166                 }
6167                 sbuf_printf(sb,
6168                            "\nLoopback %d using %u pages out of %u allocated",
6169                            i, used, alloc);
6170         }
6171
6172         rc = sbuf_finish(sb);
6173         sbuf_delete(sb);
6174
6175         return (rc);
6176 }
6177
6178 static inline void
6179 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
6180 {
6181         *mask = x | y;
6182         y = htobe64(y);
6183         memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
6184 }
6185
6186 static int
6187 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
6188 {
6189         struct adapter *sc = arg1;
6190         struct sbuf *sb;
6191         int rc, i, n;
6192
6193         rc = sysctl_wire_old_buffer(req, 0);
6194         if (rc != 0)
6195                 return (rc);
6196
6197         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6198         if (sb == NULL)
6199                 return (ENOMEM);
6200
6201         sbuf_printf(sb,
6202             "Idx  Ethernet address     Mask     Vld Ports PF"
6203             "  VF              Replication             P0 P1 P2 P3  ML");
6204         n = is_t4(sc) ? NUM_MPS_CLS_SRAM_L_INSTANCES :
6205             NUM_MPS_T5_CLS_SRAM_L_INSTANCES;
6206         for (i = 0; i < n; i++) {
6207                 uint64_t tcamx, tcamy, mask;
6208                 uint32_t cls_lo, cls_hi;
6209                 uint8_t addr[ETHER_ADDR_LEN];
6210
6211                 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
6212                 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
6213                 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6214                 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6215
6216                 if (tcamx & tcamy)
6217                         continue;
6218
6219                 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6220                 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
6221                            "  %c   %#x%4u%4d", i, addr[0], addr[1], addr[2],
6222                            addr[3], addr[4], addr[5], (uintmax_t)mask,
6223                            (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
6224                            G_PORTMAP(cls_hi), G_PF(cls_lo),
6225                            (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
6226
6227                 if (cls_lo & F_REPLICATE) {
6228                         struct fw_ldst_cmd ldst_cmd;
6229
6230                         memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6231                         ldst_cmd.op_to_addrspace =
6232                             htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6233                                 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6234                                 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6235                         ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6236                         ldst_cmd.u.mps.fid_ctl =
6237                             htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6238                                 V_FW_LDST_CMD_CTL(i));
6239
6240                         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6241                             "t4mps");
6242                         if (rc)
6243                                 break;
6244                         rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6245                             sizeof(ldst_cmd), &ldst_cmd);
6246                         end_synchronized_op(sc, 0);
6247
6248                         if (rc != 0) {
6249                                 sbuf_printf(sb,
6250                                     " ------------ error %3u ------------", rc);
6251                                 rc = 0;
6252                         } else {
6253                                 sbuf_printf(sb, " %08x %08x %08x %08x",
6254                                     be32toh(ldst_cmd.u.mps.rplc127_96),
6255                                     be32toh(ldst_cmd.u.mps.rplc95_64),
6256                                     be32toh(ldst_cmd.u.mps.rplc63_32),
6257                                     be32toh(ldst_cmd.u.mps.rplc31_0));
6258                         }
6259                 } else
6260                         sbuf_printf(sb, "%36s", "");
6261
6262                 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
6263                     G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
6264                     G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
6265         }
6266
6267         if (rc)
6268                 (void) sbuf_finish(sb);
6269         else
6270                 rc = sbuf_finish(sb);
6271         sbuf_delete(sb);
6272
6273         return (rc);
6274 }
6275
6276 static int
6277 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
6278 {
6279         struct adapter *sc = arg1;
6280         struct sbuf *sb;
6281         int rc;
6282         uint16_t mtus[NMTUS];
6283
6284         rc = sysctl_wire_old_buffer(req, 0);
6285         if (rc != 0)
6286                 return (rc);
6287
6288         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6289         if (sb == NULL)
6290                 return (ENOMEM);
6291
6292         t4_read_mtu_tbl(sc, mtus, NULL);
6293
6294         sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
6295             mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
6296             mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
6297             mtus[14], mtus[15]);
6298
6299         rc = sbuf_finish(sb);
6300         sbuf_delete(sb);
6301
6302         return (rc);
6303 }
6304
6305 static int
6306 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
6307 {
6308         struct adapter *sc = arg1;
6309         struct sbuf *sb;
6310         int rc, i;
6311         uint32_t cnt[PM_NSTATS];
6312         uint64_t cyc[PM_NSTATS];
6313         static const char *rx_stats[] = {
6314                 "Read:", "Write bypass:", "Write mem:", "Flush:"
6315         };
6316         static const char *tx_stats[] = {
6317                 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:"
6318         };
6319
6320         rc = sysctl_wire_old_buffer(req, 0);
6321         if (rc != 0)
6322                 return (rc);
6323
6324         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6325         if (sb == NULL)
6326                 return (ENOMEM);
6327
6328         t4_pmtx_get_stats(sc, cnt, cyc);
6329         sbuf_printf(sb, "                Tx pcmds             Tx bytes");
6330         for (i = 0; i < ARRAY_SIZE(tx_stats); i++)
6331                 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], cnt[i],
6332                     cyc[i]);
6333
6334         t4_pmrx_get_stats(sc, cnt, cyc);
6335         sbuf_printf(sb, "\n                Rx pcmds             Rx bytes");
6336         for (i = 0; i < ARRAY_SIZE(rx_stats); i++)
6337                 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], cnt[i],
6338                     cyc[i]);
6339
6340         rc = sbuf_finish(sb);
6341         sbuf_delete(sb);
6342
6343         return (rc);
6344 }
6345
6346 static int
6347 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
6348 {
6349         struct adapter *sc = arg1;
6350         struct sbuf *sb;
6351         int rc;
6352         struct tp_rdma_stats stats;
6353
6354         rc = sysctl_wire_old_buffer(req, 0);
6355         if (rc != 0)
6356                 return (rc);
6357
6358         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6359         if (sb == NULL)
6360                 return (ENOMEM);
6361
6362         t4_tp_get_rdma_stats(sc, &stats);
6363         sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
6364         sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
6365
6366         rc = sbuf_finish(sb);
6367         sbuf_delete(sb);
6368
6369         return (rc);
6370 }
6371
6372 static int
6373 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
6374 {
6375         struct adapter *sc = arg1;
6376         struct sbuf *sb;
6377         int rc;
6378         struct tp_tcp_stats v4, v6;
6379
6380         rc = sysctl_wire_old_buffer(req, 0);
6381         if (rc != 0)
6382                 return (rc);
6383
6384         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6385         if (sb == NULL)
6386                 return (ENOMEM);
6387
6388         t4_tp_get_tcp_stats(sc, &v4, &v6);
6389         sbuf_printf(sb,
6390             "                                IP                 IPv6\n");
6391         sbuf_printf(sb, "OutRsts:      %20u %20u\n",
6392             v4.tcpOutRsts, v6.tcpOutRsts);
6393         sbuf_printf(sb, "InSegs:       %20ju %20ju\n",
6394             v4.tcpInSegs, v6.tcpInSegs);
6395         sbuf_printf(sb, "OutSegs:      %20ju %20ju\n",
6396             v4.tcpOutSegs, v6.tcpOutSegs);
6397         sbuf_printf(sb, "RetransSegs:  %20ju %20ju",
6398             v4.tcpRetransSegs, v6.tcpRetransSegs);
6399
6400         rc = sbuf_finish(sb);
6401         sbuf_delete(sb);
6402
6403         return (rc);
6404 }
6405
6406 static int
6407 sysctl_tids(SYSCTL_HANDLER_ARGS)
6408 {
6409         struct adapter *sc = arg1;
6410         struct sbuf *sb;
6411         int rc;
6412         struct tid_info *t = &sc->tids;
6413
6414         rc = sysctl_wire_old_buffer(req, 0);
6415         if (rc != 0)
6416                 return (rc);
6417
6418         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6419         if (sb == NULL)
6420                 return (ENOMEM);
6421
6422         if (t->natids) {
6423                 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
6424                     t->atids_in_use);
6425         }
6426
6427         if (t->ntids) {
6428                 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6429                         uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
6430
6431                         if (b) {
6432                                 sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1,
6433                                     t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6434                                     t->ntids - 1);
6435                         } else {
6436                                 sbuf_printf(sb, "TID range: %u-%u",
6437                                     t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6438                                     t->ntids - 1);
6439                         }
6440                 } else
6441                         sbuf_printf(sb, "TID range: 0-%u", t->ntids - 1);
6442                 sbuf_printf(sb, ", in use: %u\n",
6443                     atomic_load_acq_int(&t->tids_in_use));
6444         }
6445
6446         if (t->nstids) {
6447                 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
6448                     t->stid_base + t->nstids - 1, t->stids_in_use);
6449         }
6450
6451         if (t->nftids) {
6452                 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
6453                     t->ftid_base + t->nftids - 1);
6454         }
6455
6456         if (t->netids) {
6457                 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base,
6458                     t->etid_base + t->netids - 1);
6459         }
6460
6461         sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
6462             t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
6463             t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
6464
6465         rc = sbuf_finish(sb);
6466         sbuf_delete(sb);
6467
6468         return (rc);
6469 }
6470
6471 static int
6472 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
6473 {
6474         struct adapter *sc = arg1;
6475         struct sbuf *sb;
6476         int rc;
6477         struct tp_err_stats stats;
6478
6479         rc = sysctl_wire_old_buffer(req, 0);
6480         if (rc != 0)
6481                 return (rc);
6482
6483         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6484         if (sb == NULL)
6485                 return (ENOMEM);
6486
6487         t4_tp_get_err_stats(sc, &stats);
6488
6489         sbuf_printf(sb, "                 channel 0  channel 1  channel 2  "
6490                       "channel 3\n");
6491         sbuf_printf(sb, "macInErrs:      %10u %10u %10u %10u\n",
6492             stats.macInErrs[0], stats.macInErrs[1], stats.macInErrs[2],
6493             stats.macInErrs[3]);
6494         sbuf_printf(sb, "hdrInErrs:      %10u %10u %10u %10u\n",
6495             stats.hdrInErrs[0], stats.hdrInErrs[1], stats.hdrInErrs[2],
6496             stats.hdrInErrs[3]);
6497         sbuf_printf(sb, "tcpInErrs:      %10u %10u %10u %10u\n",
6498             stats.tcpInErrs[0], stats.tcpInErrs[1], stats.tcpInErrs[2],
6499             stats.tcpInErrs[3]);
6500         sbuf_printf(sb, "tcp6InErrs:     %10u %10u %10u %10u\n",
6501             stats.tcp6InErrs[0], stats.tcp6InErrs[1], stats.tcp6InErrs[2],
6502             stats.tcp6InErrs[3]);
6503         sbuf_printf(sb, "tnlCongDrops:   %10u %10u %10u %10u\n",
6504             stats.tnlCongDrops[0], stats.tnlCongDrops[1], stats.tnlCongDrops[2],
6505             stats.tnlCongDrops[3]);
6506         sbuf_printf(sb, "tnlTxDrops:     %10u %10u %10u %10u\n",
6507             stats.tnlTxDrops[0], stats.tnlTxDrops[1], stats.tnlTxDrops[2],
6508             stats.tnlTxDrops[3]);
6509         sbuf_printf(sb, "ofldVlanDrops:  %10u %10u %10u %10u\n",
6510             stats.ofldVlanDrops[0], stats.ofldVlanDrops[1],
6511             stats.ofldVlanDrops[2], stats.ofldVlanDrops[3]);
6512         sbuf_printf(sb, "ofldChanDrops:  %10u %10u %10u %10u\n\n",
6513             stats.ofldChanDrops[0], stats.ofldChanDrops[1],
6514             stats.ofldChanDrops[2], stats.ofldChanDrops[3]);
6515         sbuf_printf(sb, "ofldNoNeigh:    %u\nofldCongDefer:  %u",
6516             stats.ofldNoNeigh, stats.ofldCongDefer);
6517
6518         rc = sbuf_finish(sb);
6519         sbuf_delete(sb);
6520
6521         return (rc);
6522 }
6523
6524 struct field_desc {
6525         const char *name;
6526         u_int start;
6527         u_int width;
6528 };
6529
6530 static void
6531 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
6532 {
6533         char buf[32];
6534         int line_size = 0;
6535
6536         while (f->name) {
6537                 uint64_t mask = (1ULL << f->width) - 1;
6538                 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
6539                     ((uintmax_t)v >> f->start) & mask);
6540
6541                 if (line_size + len >= 79) {
6542                         line_size = 8;
6543                         sbuf_printf(sb, "\n        ");
6544                 }
6545                 sbuf_printf(sb, "%s ", buf);
6546                 line_size += len + 1;
6547                 f++;
6548         }
6549         sbuf_printf(sb, "\n");
6550 }
6551
6552 static struct field_desc tp_la0[] = {
6553         { "RcfOpCodeOut", 60, 4 },
6554         { "State", 56, 4 },
6555         { "WcfState", 52, 4 },
6556         { "RcfOpcSrcOut", 50, 2 },
6557         { "CRxError", 49, 1 },
6558         { "ERxError", 48, 1 },
6559         { "SanityFailed", 47, 1 },
6560         { "SpuriousMsg", 46, 1 },
6561         { "FlushInputMsg", 45, 1 },
6562         { "FlushInputCpl", 44, 1 },
6563         { "RssUpBit", 43, 1 },
6564         { "RssFilterHit", 42, 1 },
6565         { "Tid", 32, 10 },
6566         { "InitTcb", 31, 1 },
6567         { "LineNumber", 24, 7 },
6568         { "Emsg", 23, 1 },
6569         { "EdataOut", 22, 1 },
6570         { "Cmsg", 21, 1 },
6571         { "CdataOut", 20, 1 },
6572         { "EreadPdu", 19, 1 },
6573         { "CreadPdu", 18, 1 },
6574         { "TunnelPkt", 17, 1 },
6575         { "RcfPeerFin", 16, 1 },
6576         { "RcfReasonOut", 12, 4 },
6577         { "TxCchannel", 10, 2 },
6578         { "RcfTxChannel", 8, 2 },
6579         { "RxEchannel", 6, 2 },
6580         { "RcfRxChannel", 5, 1 },
6581         { "RcfDataOutSrdy", 4, 1 },
6582         { "RxDvld", 3, 1 },
6583         { "RxOoDvld", 2, 1 },
6584         { "RxCongestion", 1, 1 },
6585         { "TxCongestion", 0, 1 },
6586         { NULL }
6587 };
6588
6589 static struct field_desc tp_la1[] = {
6590         { "CplCmdIn", 56, 8 },
6591         { "CplCmdOut", 48, 8 },
6592         { "ESynOut", 47, 1 },
6593         { "EAckOut", 46, 1 },
6594         { "EFinOut", 45, 1 },
6595         { "ERstOut", 44, 1 },
6596         { "SynIn", 43, 1 },
6597         { "AckIn", 42, 1 },
6598         { "FinIn", 41, 1 },
6599         { "RstIn", 40, 1 },
6600         { "DataIn", 39, 1 },
6601         { "DataInVld", 38, 1 },
6602         { "PadIn", 37, 1 },
6603         { "RxBufEmpty", 36, 1 },
6604         { "RxDdp", 35, 1 },
6605         { "RxFbCongestion", 34, 1 },
6606         { "TxFbCongestion", 33, 1 },
6607         { "TxPktSumSrdy", 32, 1 },
6608         { "RcfUlpType", 28, 4 },
6609         { "Eread", 27, 1 },
6610         { "Ebypass", 26, 1 },
6611         { "Esave", 25, 1 },
6612         { "Static0", 24, 1 },
6613         { "Cread", 23, 1 },
6614         { "Cbypass", 22, 1 },
6615         { "Csave", 21, 1 },
6616         { "CPktOut", 20, 1 },
6617         { "RxPagePoolFull", 18, 2 },
6618         { "RxLpbkPkt", 17, 1 },
6619         { "TxLpbkPkt", 16, 1 },
6620         { "RxVfValid", 15, 1 },
6621         { "SynLearned", 14, 1 },
6622         { "SetDelEntry", 13, 1 },
6623         { "SetInvEntry", 12, 1 },
6624         { "CpcmdDvld", 11, 1 },
6625         { "CpcmdSave", 10, 1 },
6626         { "RxPstructsFull", 8, 2 },
6627         { "EpcmdDvld", 7, 1 },
6628         { "EpcmdFlush", 6, 1 },
6629         { "EpcmdTrimPrefix", 5, 1 },
6630         { "EpcmdTrimPostfix", 4, 1 },
6631         { "ERssIp4Pkt", 3, 1 },
6632         { "ERssIp6Pkt", 2, 1 },
6633         { "ERssTcpUdpPkt", 1, 1 },
6634         { "ERssFceFipPkt", 0, 1 },
6635         { NULL }
6636 };
6637
6638 static struct field_desc tp_la2[] = {
6639         { "CplCmdIn", 56, 8 },
6640         { "MpsVfVld", 55, 1 },
6641         { "MpsPf", 52, 3 },
6642         { "MpsVf", 44, 8 },
6643         { "SynIn", 43, 1 },
6644         { "AckIn", 42, 1 },
6645         { "FinIn", 41, 1 },
6646         { "RstIn", 40, 1 },
6647         { "DataIn", 39, 1 },
6648         { "DataInVld", 38, 1 },
6649         { "PadIn", 37, 1 },
6650         { "RxBufEmpty", 36, 1 },
6651         { "RxDdp", 35, 1 },
6652         { "RxFbCongestion", 34, 1 },
6653         { "TxFbCongestion", 33, 1 },
6654         { "TxPktSumSrdy", 32, 1 },
6655         { "RcfUlpType", 28, 4 },
6656         { "Eread", 27, 1 },
6657         { "Ebypass", 26, 1 },
6658         { "Esave", 25, 1 },
6659         { "Static0", 24, 1 },
6660         { "Cread", 23, 1 },
6661         { "Cbypass", 22, 1 },
6662         { "Csave", 21, 1 },
6663         { "CPktOut", 20, 1 },
6664         { "RxPagePoolFull", 18, 2 },
6665         { "RxLpbkPkt", 17, 1 },
6666         { "TxLpbkPkt", 16, 1 },
6667         { "RxVfValid", 15, 1 },
6668         { "SynLearned", 14, 1 },
6669         { "SetDelEntry", 13, 1 },
6670         { "SetInvEntry", 12, 1 },
6671         { "CpcmdDvld", 11, 1 },
6672         { "CpcmdSave", 10, 1 },
6673         { "RxPstructsFull", 8, 2 },
6674         { "EpcmdDvld", 7, 1 },
6675         { "EpcmdFlush", 6, 1 },
6676         { "EpcmdTrimPrefix", 5, 1 },
6677         { "EpcmdTrimPostfix", 4, 1 },
6678         { "ERssIp4Pkt", 3, 1 },
6679         { "ERssIp6Pkt", 2, 1 },
6680         { "ERssTcpUdpPkt", 1, 1 },
6681         { "ERssFceFipPkt", 0, 1 },
6682         { NULL }
6683 };
6684
6685 static void
6686 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
6687 {
6688
6689         field_desc_show(sb, *p, tp_la0);
6690 }
6691
6692 static void
6693 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
6694 {
6695
6696         if (idx)
6697                 sbuf_printf(sb, "\n");
6698         field_desc_show(sb, p[0], tp_la0);
6699         if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
6700                 field_desc_show(sb, p[1], tp_la0);
6701 }
6702
6703 static void
6704 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
6705 {
6706
6707         if (idx)
6708                 sbuf_printf(sb, "\n");
6709         field_desc_show(sb, p[0], tp_la0);
6710         if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
6711                 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
6712 }
6713
6714 static int
6715 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
6716 {
6717         struct adapter *sc = arg1;
6718         struct sbuf *sb;
6719         uint64_t *buf, *p;
6720         int rc;
6721         u_int i, inc;
6722         void (*show_func)(struct sbuf *, uint64_t *, int);
6723
6724         rc = sysctl_wire_old_buffer(req, 0);
6725         if (rc != 0)
6726                 return (rc);
6727
6728         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6729         if (sb == NULL)
6730                 return (ENOMEM);
6731
6732         buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
6733
6734         t4_tp_read_la(sc, buf, NULL);
6735         p = buf;
6736
6737         switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
6738         case 2:
6739                 inc = 2;
6740                 show_func = tp_la_show2;
6741                 break;
6742         case 3:
6743                 inc = 2;
6744                 show_func = tp_la_show3;
6745                 break;
6746         default:
6747                 inc = 1;
6748                 show_func = tp_la_show;
6749         }
6750
6751         for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
6752                 (*show_func)(sb, p, i);
6753
6754         rc = sbuf_finish(sb);
6755         sbuf_delete(sb);
6756         free(buf, M_CXGBE);
6757         return (rc);
6758 }
6759
6760 static int
6761 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
6762 {
6763         struct adapter *sc = arg1;
6764         struct sbuf *sb;
6765         int rc;
6766         u64 nrate[NCHAN], orate[NCHAN];
6767
6768         rc = sysctl_wire_old_buffer(req, 0);
6769         if (rc != 0)
6770                 return (rc);
6771
6772         sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6773         if (sb == NULL)
6774                 return (ENOMEM);
6775
6776         t4_get_chan_txrate(sc, nrate, orate);
6777         sbuf_printf(sb, "              channel 0   channel 1   channel 2   "
6778                  "channel 3\n");
6779         sbuf_printf(sb, "NIC B/s:     %10ju  %10ju  %10ju  %10ju\n",
6780             nrate[0], nrate[1], nrate[2], nrate[3]);
6781         sbuf_printf(sb, "Offload B/s: %10ju  %10ju  %10ju  %10ju",
6782             orate[0], orate[1], orate[2], orate[3]);
6783
6784         rc = sbuf_finish(sb);
6785         sbuf_delete(sb);
6786
6787         return (rc);
6788 }
6789
6790 static int
6791 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
6792 {
6793         struct adapter *sc = arg1;
6794         struct sbuf *sb;
6795         uint32_t *buf, *p;
6796         int rc, i;
6797
6798         rc = sysctl_wire_old_buffer(req, 0);
6799         if (rc != 0)
6800                 return (rc);
6801
6802         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6803         if (sb == NULL)
6804                 return (ENOMEM);
6805
6806         buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
6807             M_ZERO | M_WAITOK);
6808
6809         t4_ulprx_read_la(sc, buf);
6810         p = buf;
6811
6812         sbuf_printf(sb, "      Pcmd        Type   Message"
6813             "                Data");
6814         for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
6815                 sbuf_printf(sb, "\n%08x%08x  %4x  %08x  %08x%08x%08x%08x",
6816                     p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
6817         }
6818
6819         rc = sbuf_finish(sb);
6820         sbuf_delete(sb);
6821         free(buf, M_CXGBE);
6822         return (rc);
6823 }
6824
6825 static int
6826 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
6827 {
6828         struct adapter *sc = arg1;
6829         struct sbuf *sb;
6830         int rc, v;
6831
6832         rc = sysctl_wire_old_buffer(req, 0);
6833         if (rc != 0)
6834                 return (rc);
6835
6836         sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6837         if (sb == NULL)
6838                 return (ENOMEM);
6839
6840         v = t4_read_reg(sc, A_SGE_STAT_CFG);
6841         if (G_STATSOURCE_T5(v) == 7) {
6842                 if (G_STATMODE(v) == 0) {
6843                         sbuf_printf(sb, "total %d, incomplete %d",
6844                             t4_read_reg(sc, A_SGE_STAT_TOTAL),
6845                             t4_read_reg(sc, A_SGE_STAT_MATCH));
6846                 } else if (G_STATMODE(v) == 1) {
6847                         sbuf_printf(sb, "total %d, data overflow %d",
6848                             t4_read_reg(sc, A_SGE_STAT_TOTAL),
6849                             t4_read_reg(sc, A_SGE_STAT_MATCH));
6850                 }
6851         }
6852         rc = sbuf_finish(sb);
6853         sbuf_delete(sb);
6854
6855         return (rc);
6856 }
6857 #endif
6858
6859 static inline void
6860 txq_start(struct ifnet *ifp, struct sge_txq *txq)
6861 {
6862         struct buf_ring *br;
6863         struct mbuf *m;
6864
6865         TXQ_LOCK_ASSERT_OWNED(txq);
6866
6867         br = txq->br;
6868         m = txq->m ? txq->m : drbr_dequeue(ifp, br);
6869         if (m)
6870                 t4_eth_tx(ifp, txq, m);
6871 }
6872
6873 void
6874 t4_tx_callout(void *arg)
6875 {
6876         struct sge_eq *eq = arg;
6877         struct adapter *sc;
6878
6879         if (EQ_TRYLOCK(eq) == 0)
6880                 goto reschedule;
6881
6882         if (eq->flags & EQ_STALLED && !can_resume_tx(eq)) {
6883                 EQ_UNLOCK(eq);
6884 reschedule:
6885                 if (__predict_true(!(eq->flags && EQ_DOOMED)))
6886                         callout_schedule(&eq->tx_callout, 1);
6887                 return;
6888         }
6889
6890         EQ_LOCK_ASSERT_OWNED(eq);
6891
6892         if (__predict_true((eq->flags & EQ_DOOMED) == 0)) {
6893
6894                 if ((eq->flags & EQ_TYPEMASK) == EQ_ETH) {
6895                         struct sge_txq *txq = arg;
6896                         struct port_info *pi = txq->ifp->if_softc;
6897
6898                         sc = pi->adapter;
6899                 } else {
6900                         struct sge_wrq *wrq = arg;
6901
6902                         sc = wrq->adapter;
6903                 }
6904
6905                 taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task);
6906         }
6907
6908         EQ_UNLOCK(eq);
6909 }
6910
6911 void
6912 t4_tx_task(void *arg, int count)
6913 {
6914         struct sge_eq *eq = arg;
6915
6916         EQ_LOCK(eq);
6917         if ((eq->flags & EQ_TYPEMASK) == EQ_ETH) {
6918                 struct sge_txq *txq = arg;
6919                 txq_start(txq->ifp, txq);
6920         } else {
6921                 struct sge_wrq *wrq = arg;
6922                 t4_wrq_tx_locked(wrq->adapter, wrq, NULL);
6923         }
6924         EQ_UNLOCK(eq);
6925 }
6926
6927 static uint32_t
6928 fconf_to_mode(uint32_t fconf)
6929 {
6930         uint32_t mode;
6931
6932         mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
6933             T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
6934
6935         if (fconf & F_FRAGMENTATION)
6936                 mode |= T4_FILTER_IP_FRAGMENT;
6937
6938         if (fconf & F_MPSHITTYPE)
6939                 mode |= T4_FILTER_MPS_HIT_TYPE;
6940
6941         if (fconf & F_MACMATCH)
6942                 mode |= T4_FILTER_MAC_IDX;
6943
6944         if (fconf & F_ETHERTYPE)
6945                 mode |= T4_FILTER_ETH_TYPE;
6946
6947         if (fconf & F_PROTOCOL)
6948                 mode |= T4_FILTER_IP_PROTO;
6949
6950         if (fconf & F_TOS)
6951                 mode |= T4_FILTER_IP_TOS;
6952
6953         if (fconf & F_VLAN)
6954                 mode |= T4_FILTER_VLAN;
6955
6956         if (fconf & F_VNIC_ID)
6957                 mode |= T4_FILTER_VNIC;
6958
6959         if (fconf & F_PORT)
6960                 mode |= T4_FILTER_PORT;
6961
6962         if (fconf & F_FCOE)
6963                 mode |= T4_FILTER_FCoE;
6964
6965         return (mode);
6966 }
6967
6968 static uint32_t
6969 mode_to_fconf(uint32_t mode)
6970 {
6971         uint32_t fconf = 0;
6972
6973         if (mode & T4_FILTER_IP_FRAGMENT)
6974                 fconf |= F_FRAGMENTATION;
6975
6976         if (mode & T4_FILTER_MPS_HIT_TYPE)
6977                 fconf |= F_MPSHITTYPE;
6978
6979         if (mode & T4_FILTER_MAC_IDX)
6980                 fconf |= F_MACMATCH;
6981
6982         if (mode & T4_FILTER_ETH_TYPE)
6983                 fconf |= F_ETHERTYPE;
6984
6985         if (mode & T4_FILTER_IP_PROTO)
6986                 fconf |= F_PROTOCOL;
6987
6988         if (mode & T4_FILTER_IP_TOS)
6989                 fconf |= F_TOS;
6990
6991         if (mode & T4_FILTER_VLAN)
6992                 fconf |= F_VLAN;
6993
6994         if (mode & T4_FILTER_VNIC)
6995                 fconf |= F_VNIC_ID;
6996
6997         if (mode & T4_FILTER_PORT)
6998                 fconf |= F_PORT;
6999
7000         if (mode & T4_FILTER_FCoE)
7001                 fconf |= F_FCOE;
7002
7003         return (fconf);
7004 }
7005
7006 static uint32_t
7007 fspec_to_fconf(struct t4_filter_specification *fs)
7008 {
7009         uint32_t fconf = 0;
7010
7011         if (fs->val.frag || fs->mask.frag)
7012                 fconf |= F_FRAGMENTATION;
7013
7014         if (fs->val.matchtype || fs->mask.matchtype)
7015                 fconf |= F_MPSHITTYPE;
7016
7017         if (fs->val.macidx || fs->mask.macidx)
7018                 fconf |= F_MACMATCH;
7019
7020         if (fs->val.ethtype || fs->mask.ethtype)
7021                 fconf |= F_ETHERTYPE;
7022
7023         if (fs->val.proto || fs->mask.proto)
7024                 fconf |= F_PROTOCOL;
7025
7026         if (fs->val.tos || fs->mask.tos)
7027                 fconf |= F_TOS;
7028
7029         if (fs->val.vlan_vld || fs->mask.vlan_vld)
7030                 fconf |= F_VLAN;
7031
7032         if (fs->val.vnic_vld || fs->mask.vnic_vld)
7033                 fconf |= F_VNIC_ID;
7034
7035         if (fs->val.iport || fs->mask.iport)
7036                 fconf |= F_PORT;
7037
7038         if (fs->val.fcoe || fs->mask.fcoe)
7039                 fconf |= F_FCOE;
7040
7041         return (fconf);
7042 }
7043
7044 static int
7045 get_filter_mode(struct adapter *sc, uint32_t *mode)
7046 {
7047         int rc;
7048         uint32_t fconf;
7049
7050         rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7051             "t4getfm");
7052         if (rc)
7053                 return (rc);
7054
7055         t4_read_indirect(sc, A_TP_PIO_ADDR, A_TP_PIO_DATA, &fconf, 1,
7056             A_TP_VLAN_PRI_MAP);
7057
7058         if (sc->params.tp.vlan_pri_map != fconf) {
7059                 log(LOG_WARNING, "%s: cached filter mode out of sync %x %x.\n",
7060                     device_get_nameunit(sc->dev), sc->params.tp.vlan_pri_map,
7061                     fconf);
7062         }
7063
7064         *mode = fconf_to_mode(fconf);
7065
7066         end_synchronized_op(sc, LOCK_HELD);
7067         return (0);
7068 }
7069
7070 static int
7071 set_filter_mode(struct adapter *sc, uint32_t mode)
7072 {
7073         uint32_t fconf;
7074         int rc;
7075
7076         fconf = mode_to_fconf(mode);
7077
7078         rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7079             "t4setfm");
7080         if (rc)
7081                 return (rc);
7082
7083         if (sc->tids.ftids_in_use > 0) {
7084                 rc = EBUSY;
7085                 goto done;
7086         }
7087
7088 #ifdef TCP_OFFLOAD
7089         if (sc->offload_map) {
7090                 rc = EBUSY;
7091                 goto done;
7092         }
7093 #endif
7094
7095         rc = -t4_set_filter_mode(sc, fconf);
7096 done:
7097         end_synchronized_op(sc, LOCK_HELD);
7098         return (rc);
7099 }
7100
7101 static inline uint64_t
7102 get_filter_hits(struct adapter *sc, uint32_t fid)
7103 {
7104         uint32_t mw_base, off, tcb_base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
7105         uint64_t hits;
7106
7107         memwin_info(sc, 0, &mw_base, NULL);
7108         off = position_memwin(sc, 0,
7109             tcb_base + (fid + sc->tids.ftid_base) * TCB_SIZE);
7110         if (is_t4(sc)) {
7111                 hits = t4_read_reg64(sc, mw_base + off + 16);
7112                 hits = be64toh(hits);
7113         } else {
7114                 hits = t4_read_reg(sc, mw_base + off + 24);
7115                 hits = be32toh(hits);
7116         }
7117
7118         return (hits);
7119 }
7120
7121 static int
7122 get_filter(struct adapter *sc, struct t4_filter *t)
7123 {
7124         int i, rc, nfilters = sc->tids.nftids;
7125         struct filter_entry *f;
7126
7127         rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7128             "t4getf");
7129         if (rc)
7130                 return (rc);
7131
7132         if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL ||
7133             t->idx >= nfilters) {
7134                 t->idx = 0xffffffff;
7135                 goto done;
7136         }
7137
7138         f = &sc->tids.ftid_tab[t->idx];
7139         for (i = t->idx; i < nfilters; i++, f++) {
7140                 if (f->valid) {
7141                         t->idx = i;
7142                         t->l2tidx = f->l2t ? f->l2t->idx : 0;
7143                         t->smtidx = f->smtidx;
7144                         if (f->fs.hitcnts)
7145                                 t->hits = get_filter_hits(sc, t->idx);
7146                         else
7147                                 t->hits = UINT64_MAX;
7148                         t->fs = f->fs;
7149
7150                         goto done;
7151                 }
7152         }
7153
7154         t->idx = 0xffffffff;
7155 done:
7156         end_synchronized_op(sc, LOCK_HELD);
7157         return (0);
7158 }
7159
7160 static int
7161 set_filter(struct adapter *sc, struct t4_filter *t)
7162 {
7163         unsigned int nfilters, nports;
7164         struct filter_entry *f;
7165         int i, rc;
7166
7167         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf");
7168         if (rc)
7169                 return (rc);
7170
7171         nfilters = sc->tids.nftids;
7172         nports = sc->params.nports;
7173
7174         if (nfilters == 0) {
7175                 rc = ENOTSUP;
7176                 goto done;
7177         }
7178
7179         if (!(sc->flags & FULL_INIT_DONE)) {
7180                 rc = EAGAIN;
7181                 goto done;
7182         }
7183
7184         if (t->idx >= nfilters) {
7185                 rc = EINVAL;
7186                 goto done;
7187         }
7188
7189         /* Validate against the global filter mode */
7190         if ((sc->params.tp.vlan_pri_map | fspec_to_fconf(&t->fs)) !=
7191             sc->params.tp.vlan_pri_map) {
7192                 rc = E2BIG;
7193                 goto done;
7194         }
7195
7196         if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) {
7197                 rc = EINVAL;
7198                 goto done;
7199         }
7200
7201         if (t->fs.val.iport >= nports) {
7202                 rc = EINVAL;
7203                 goto done;
7204         }
7205
7206         /* Can't specify an iq if not steering to it */
7207         if (!t->fs.dirsteer && t->fs.iq) {
7208                 rc = EINVAL;
7209                 goto done;
7210         }
7211
7212         /* IPv6 filter idx must be 4 aligned */
7213         if (t->fs.type == 1 &&
7214             ((t->idx & 0x3) || t->idx + 4 >= nfilters)) {
7215                 rc = EINVAL;
7216                 goto done;
7217         }
7218
7219         if (sc->tids.ftid_tab == NULL) {
7220                 KASSERT(sc->tids.ftids_in_use == 0,
7221                     ("%s: no memory allocated but filters_in_use > 0",
7222                     __func__));
7223
7224                 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) *
7225                     nfilters, M_CXGBE, M_NOWAIT | M_ZERO);
7226                 if (sc->tids.ftid_tab == NULL) {
7227                         rc = ENOMEM;
7228                         goto done;
7229                 }
7230                 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF);
7231         }
7232
7233         for (i = 0; i < 4; i++) {
7234                 f = &sc->tids.ftid_tab[t->idx + i];
7235
7236                 if (f->pending || f->valid) {
7237                         rc = EBUSY;
7238                         goto done;
7239                 }
7240                 if (f->locked) {
7241                         rc = EPERM;
7242                         goto done;
7243                 }
7244
7245                 if (t->fs.type == 0)
7246                         break;
7247         }
7248
7249         f = &sc->tids.ftid_tab[t->idx];
7250         f->fs = t->fs;
7251
7252         rc = set_filter_wr(sc, t->idx);
7253 done:
7254         end_synchronized_op(sc, 0);
7255
7256         if (rc == 0) {
7257                 mtx_lock(&sc->tids.ftid_lock);
7258                 for (;;) {
7259                         if (f->pending == 0) {
7260                                 rc = f->valid ? 0 : EIO;
7261                                 break;
7262                         }
7263
7264                         if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
7265                             PCATCH, "t4setfw", 0)) {
7266                                 rc = EINPROGRESS;
7267                                 break;
7268                         }
7269                 }
7270                 mtx_unlock(&sc->tids.ftid_lock);
7271         }
7272         return (rc);
7273 }
7274
7275 static int
7276 del_filter(struct adapter *sc, struct t4_filter *t)
7277 {
7278         unsigned int nfilters;
7279         struct filter_entry *f;
7280         int rc;
7281
7282         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf");
7283         if (rc)
7284                 return (rc);
7285
7286         nfilters = sc->tids.nftids;
7287
7288         if (nfilters == 0) {
7289                 rc = ENOTSUP;
7290                 goto done;
7291         }
7292
7293         if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 ||
7294             t->idx >= nfilters) {
7295                 rc = EINVAL;
7296                 goto done;
7297         }
7298
7299         if (!(sc->flags & FULL_INIT_DONE)) {
7300                 rc = EAGAIN;
7301                 goto done;
7302         }
7303
7304         f = &sc->tids.ftid_tab[t->idx];
7305
7306         if (f->pending) {
7307                 rc = EBUSY;
7308                 goto done;
7309         }
7310         if (f->locked) {
7311                 rc = EPERM;
7312                 goto done;
7313         }
7314
7315         if (f->valid) {
7316                 t->fs = f->fs;  /* extra info for the caller */
7317                 rc = del_filter_wr(sc, t->idx);
7318         }
7319
7320 done:
7321         end_synchronized_op(sc, 0);
7322
7323         if (rc == 0) {
7324                 mtx_lock(&sc->tids.ftid_lock);
7325                 for (;;) {
7326                         if (f->pending == 0) {
7327                                 rc = f->valid ? EIO : 0;
7328                                 break;
7329                         }
7330
7331                         if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
7332                             PCATCH, "t4delfw", 0)) {
7333                                 rc = EINPROGRESS;
7334                                 break;
7335                         }
7336                 }
7337                 mtx_unlock(&sc->tids.ftid_lock);
7338         }
7339
7340         return (rc);
7341 }
7342
7343 static void
7344 clear_filter(struct filter_entry *f)
7345 {
7346         if (f->l2t)
7347                 t4_l2t_release(f->l2t);
7348
7349         bzero(f, sizeof (*f));
7350 }
7351
7352 static int
7353 set_filter_wr(struct adapter *sc, int fidx)
7354 {
7355         struct filter_entry *f = &sc->tids.ftid_tab[fidx];
7356         struct wrqe *wr;
7357         struct fw_filter_wr *fwr;
7358         unsigned int ftid;
7359
7360         ASSERT_SYNCHRONIZED_OP(sc);
7361
7362         if (f->fs.newdmac || f->fs.newvlan) {
7363                 /* This filter needs an L2T entry; allocate one. */
7364                 f->l2t = t4_l2t_alloc_switching(sc->l2t);
7365                 if (f->l2t == NULL)
7366                         return (EAGAIN);
7367                 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport,
7368                     f->fs.dmac)) {
7369                         t4_l2t_release(f->l2t);
7370                         f->l2t = NULL;
7371                         return (ENOMEM);
7372                 }
7373         }
7374
7375         ftid = sc->tids.ftid_base + fidx;
7376
7377         wr = alloc_wrqe(sizeof(*fwr), &sc->sge.mgmtq);
7378         if (wr == NULL)
7379                 return (ENOMEM);
7380
7381         fwr = wrtod(wr);
7382         bzero(fwr, sizeof (*fwr));
7383
7384         fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR));
7385         fwr->len16_pkd = htobe32(FW_LEN16(*fwr));
7386         fwr->tid_to_iq =
7387             htobe32(V_FW_FILTER_WR_TID(ftid) |
7388                 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
7389                 V_FW_FILTER_WR_NOREPLY(0) |
7390                 V_FW_FILTER_WR_IQ(f->fs.iq));
7391         fwr->del_filter_to_l2tix =
7392             htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
7393                 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
7394                 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
7395                 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
7396                 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
7397                 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
7398                 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
7399                 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
7400                 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
7401                     f->fs.newvlan == VLAN_REWRITE) |
7402                 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
7403                     f->fs.newvlan == VLAN_REWRITE) |
7404                 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
7405                 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
7406                 V_FW_FILTER_WR_PRIO(f->fs.prio) |
7407                 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
7408         fwr->ethtype = htobe16(f->fs.val.ethtype);
7409         fwr->ethtypem = htobe16(f->fs.mask.ethtype);
7410         fwr->frag_to_ovlan_vldm =
7411             (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
7412                 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
7413                 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
7414                 V_FW_FILTER_WR_OVLAN_VLD(f->fs.val.vnic_vld) |
7415                 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
7416                 V_FW_FILTER_WR_OVLAN_VLDM(f->fs.mask.vnic_vld));
7417         fwr->smac_sel = 0;
7418         fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
7419             V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
7420         fwr->maci_to_matchtypem =
7421             htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
7422                 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
7423                 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
7424                 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
7425                 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
7426                 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
7427                 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
7428                 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
7429         fwr->ptcl = f->fs.val.proto;
7430         fwr->ptclm = f->fs.mask.proto;
7431         fwr->ttyp = f->fs.val.tos;
7432         fwr->ttypm = f->fs.mask.tos;
7433         fwr->ivlan = htobe16(f->fs.val.vlan);
7434         fwr->ivlanm = htobe16(f->fs.mask.vlan);
7435         fwr->ovlan = htobe16(f->fs.val.vnic);
7436         fwr->ovlanm = htobe16(f->fs.mask.vnic);
7437         bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
7438         bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
7439         bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
7440         bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm));
7441         fwr->lp = htobe16(f->fs.val.dport);
7442         fwr->lpm = htobe16(f->fs.mask.dport);
7443         fwr->fp = htobe16(f->fs.val.sport);
7444         fwr->fpm = htobe16(f->fs.mask.sport);
7445         if (f->fs.newsmac)
7446                 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma));
7447
7448         f->pending = 1;
7449         sc->tids.ftids_in_use++;
7450
7451         t4_wrq_tx(sc, wr);
7452         return (0);
7453 }
7454
7455 static int
7456 del_filter_wr(struct adapter *sc, int fidx)
7457 {
7458         struct filter_entry *f = &sc->tids.ftid_tab[fidx];
7459         struct wrqe *wr;
7460         struct fw_filter_wr *fwr;
7461         unsigned int ftid;
7462
7463         ftid = sc->tids.ftid_base + fidx;
7464
7465         wr = alloc_wrqe(sizeof(*fwr), &sc->sge.mgmtq);
7466         if (wr == NULL)
7467                 return (ENOMEM);
7468         fwr = wrtod(wr);
7469         bzero(fwr, sizeof (*fwr));
7470
7471         t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
7472
7473         f->pending = 1;
7474         t4_wrq_tx(sc, wr);
7475         return (0);
7476 }
7477
7478 int
7479 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
7480 {
7481         struct adapter *sc = iq->adapter;
7482         const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
7483         unsigned int idx = GET_TID(rpl);
7484         unsigned int rc;
7485         struct filter_entry *f;
7486
7487         KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
7488             rss->opcode));
7489
7490         if (is_ftid(sc, idx)) {
7491
7492                 idx -= sc->tids.ftid_base;
7493                 f = &sc->tids.ftid_tab[idx];
7494                 rc = G_COOKIE(rpl->cookie);
7495
7496                 mtx_lock(&sc->tids.ftid_lock);
7497                 if (rc == FW_FILTER_WR_FLT_ADDED) {
7498                         KASSERT(f->pending, ("%s: filter[%u] isn't pending.",
7499                             __func__, idx));
7500                         f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
7501                         f->pending = 0;  /* asynchronous setup completed */
7502                         f->valid = 1;
7503                 } else {
7504                         if (rc != FW_FILTER_WR_FLT_DELETED) {
7505                                 /* Add or delete failed, display an error */
7506                                 log(LOG_ERR,
7507                                     "filter %u setup failed with error %u\n",
7508                                     idx, rc);
7509                         }
7510
7511                         clear_filter(f);
7512                         sc->tids.ftids_in_use--;
7513                 }
7514                 wakeup(&sc->tids.ftid_tab);
7515                 mtx_unlock(&sc->tids.ftid_lock);
7516         }
7517
7518         return (0);
7519 }
7520
7521 static int
7522 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
7523 {
7524         int rc;
7525
7526         if (cntxt->cid > M_CTXTQID)
7527                 return (EINVAL);
7528
7529         if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
7530             cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
7531                 return (EINVAL);
7532
7533         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
7534         if (rc)
7535                 return (rc);
7536
7537         if (sc->flags & FW_OK) {
7538                 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
7539                     &cntxt->data[0]);
7540                 if (rc == 0)
7541                         goto done;
7542         }
7543
7544         /*
7545          * Read via firmware failed or wasn't even attempted.  Read directly via
7546          * the backdoor.
7547          */
7548         rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
7549 done:
7550         end_synchronized_op(sc, 0);
7551         return (rc);
7552 }
7553
7554 static int
7555 load_fw(struct adapter *sc, struct t4_data *fw)
7556 {
7557         int rc;
7558         uint8_t *fw_data;
7559
7560         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
7561         if (rc)
7562                 return (rc);
7563
7564         if (sc->flags & FULL_INIT_DONE) {
7565                 rc = EBUSY;
7566                 goto done;
7567         }
7568
7569         fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
7570         if (fw_data == NULL) {
7571                 rc = ENOMEM;
7572                 goto done;
7573         }
7574
7575         rc = copyin(fw->data, fw_data, fw->len);
7576         if (rc == 0)
7577                 rc = -t4_load_fw(sc, fw_data, fw->len);
7578
7579         free(fw_data, M_CXGBE);
7580 done:
7581         end_synchronized_op(sc, 0);
7582         return (rc);
7583 }
7584
7585 static int
7586 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
7587 {
7588         uint32_t addr, off, remaining, i, n;
7589         uint32_t *buf, *b;
7590         uint32_t mw_base, mw_aperture;
7591         int rc;
7592         uint8_t *dst;
7593
7594         rc = validate_mem_range(sc, mr->addr, mr->len);
7595         if (rc != 0)
7596                 return (rc);
7597
7598         memwin_info(sc, win, &mw_base, &mw_aperture);
7599         buf = b = malloc(min(mr->len, mw_aperture), M_CXGBE, M_WAITOK);
7600         addr = mr->addr;
7601         remaining = mr->len;
7602         dst = (void *)mr->data;
7603
7604         while (remaining) {
7605                 off = position_memwin(sc, win, addr);
7606
7607                 /* number of bytes that we'll copy in the inner loop */
7608                 n = min(remaining, mw_aperture - off);
7609                 for (i = 0; i < n; i += 4)
7610                         *b++ = t4_read_reg(sc, mw_base + off + i);
7611
7612                 rc = copyout(buf, dst, n);
7613                 if (rc != 0)
7614                         break;
7615
7616                 b = buf;
7617                 dst += n;
7618                 remaining -= n;
7619                 addr += n;
7620         }
7621
7622         free(buf, M_CXGBE);
7623         return (rc);
7624 }
7625
7626 static int
7627 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
7628 {
7629         int rc;
7630
7631         if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
7632                 return (EINVAL);
7633
7634         if (i2cd->len > sizeof(i2cd->data))
7635                 return (EFBIG);
7636
7637         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
7638         if (rc)
7639                 return (rc);
7640         rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
7641             i2cd->offset, i2cd->len, &i2cd->data[0]);
7642         end_synchronized_op(sc, 0);
7643
7644         return (rc);
7645 }
7646
7647 static int
7648 in_range(int val, int lo, int hi)
7649 {
7650
7651         return (val < 0 || (val <= hi && val >= lo));
7652 }
7653
7654 static int
7655 set_sched_class(struct adapter *sc, struct t4_sched_params *p)
7656 {
7657         int fw_subcmd, fw_type, rc;
7658
7659         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsc");
7660         if (rc)
7661                 return (rc);
7662
7663         if (!(sc->flags & FULL_INIT_DONE)) {
7664                 rc = EAGAIN;
7665                 goto done;
7666         }
7667
7668         /*
7669          * Translate the cxgbetool parameters into T4 firmware parameters.  (The
7670          * sub-command and type are in common locations.)
7671          */
7672         if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG)
7673                 fw_subcmd = FW_SCHED_SC_CONFIG;
7674         else if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS)
7675                 fw_subcmd = FW_SCHED_SC_PARAMS;
7676         else {
7677                 rc = EINVAL;
7678                 goto done;
7679         }
7680         if (p->type == SCHED_CLASS_TYPE_PACKET)
7681                 fw_type = FW_SCHED_TYPE_PKTSCHED;
7682         else {
7683                 rc = EINVAL;
7684                 goto done;
7685         }
7686
7687         if (fw_subcmd == FW_SCHED_SC_CONFIG) {
7688                 /* Vet our parameters ..*/
7689                 if (p->u.config.minmax < 0) {
7690                         rc = EINVAL;
7691                         goto done;
7692                 }
7693
7694                 /* And pass the request to the firmware ...*/
7695                 rc = -t4_sched_config(sc, fw_type, p->u.config.minmax, 1);
7696                 goto done;
7697         }
7698
7699         if (fw_subcmd == FW_SCHED_SC_PARAMS) {
7700                 int fw_level;
7701                 int fw_mode;
7702                 int fw_rateunit;
7703                 int fw_ratemode;
7704
7705                 if (p->u.params.level == SCHED_CLASS_LEVEL_CL_RL)
7706                         fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL;
7707                 else if (p->u.params.level == SCHED_CLASS_LEVEL_CL_WRR)
7708                         fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
7709                 else if (p->u.params.level == SCHED_CLASS_LEVEL_CH_RL)
7710                         fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL;
7711                 else {
7712                         rc = EINVAL;
7713                         goto done;
7714                 }
7715
7716                 if (p->u.params.mode == SCHED_CLASS_MODE_CLASS)
7717                         fw_mode = FW_SCHED_PARAMS_MODE_CLASS;
7718                 else if (p->u.params.mode == SCHED_CLASS_MODE_FLOW)
7719                         fw_mode = FW_SCHED_PARAMS_MODE_FLOW;
7720                 else {
7721                         rc = EINVAL;
7722                         goto done;
7723                 }
7724
7725                 if (p->u.params.rateunit == SCHED_CLASS_RATEUNIT_BITS)
7726                         fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE;
7727                 else if (p->u.params.rateunit == SCHED_CLASS_RATEUNIT_PKTS)
7728                         fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE;
7729                 else {
7730                         rc = EINVAL;
7731                         goto done;
7732                 }
7733
7734                 if (p->u.params.ratemode == SCHED_CLASS_RATEMODE_REL)
7735                         fw_ratemode = FW_SCHED_PARAMS_RATE_REL;
7736                 else if (p->u.params.ratemode == SCHED_CLASS_RATEMODE_ABS)
7737                         fw_ratemode = FW_SCHED_PARAMS_RATE_ABS;
7738                 else {
7739                         rc = EINVAL;
7740                         goto done;
7741                 }
7742
7743                 /* Vet our parameters ... */
7744                 if (!in_range(p->u.params.channel, 0, 3) ||
7745                     !in_range(p->u.params.cl, 0, is_t4(sc) ? 15 : 16) ||
7746                     !in_range(p->u.params.minrate, 0, 10000000) ||
7747                     !in_range(p->u.params.maxrate, 0, 10000000) ||
7748                     !in_range(p->u.params.weight, 0, 100)) {
7749                         rc = ERANGE;
7750                         goto done;
7751                 }
7752
7753                 /*
7754                  * Translate any unset parameters into the firmware's
7755                  * nomenclature and/or fail the call if the parameters
7756                  * are required ...
7757                  */
7758                 if (p->u.params.rateunit < 0 || p->u.params.ratemode < 0 ||
7759                     p->u.params.channel < 0 || p->u.params.cl < 0) {
7760                         rc = EINVAL;
7761                         goto done;
7762                 }
7763                 if (p->u.params.minrate < 0)
7764                         p->u.params.minrate = 0;
7765                 if (p->u.params.maxrate < 0) {
7766                         if (p->u.params.level == SCHED_CLASS_LEVEL_CL_RL ||
7767                             p->u.params.level == SCHED_CLASS_LEVEL_CH_RL) {
7768                                 rc = EINVAL;
7769                                 goto done;
7770                         } else
7771                                 p->u.params.maxrate = 0;
7772                 }
7773                 if (p->u.params.weight < 0) {
7774                         if (p->u.params.level == SCHED_CLASS_LEVEL_CL_WRR) {
7775                                 rc = EINVAL;
7776                                 goto done;
7777                         } else
7778                                 p->u.params.weight = 0;
7779                 }
7780                 if (p->u.params.pktsize < 0) {
7781                         if (p->u.params.level == SCHED_CLASS_LEVEL_CL_RL ||
7782                             p->u.params.level == SCHED_CLASS_LEVEL_CH_RL) {
7783                                 rc = EINVAL;
7784                                 goto done;
7785                         } else
7786                                 p->u.params.pktsize = 0;
7787                 }
7788
7789                 /* See what the firmware thinks of the request ... */
7790                 rc = -t4_sched_params(sc, fw_type, fw_level, fw_mode,
7791                     fw_rateunit, fw_ratemode, p->u.params.channel,
7792                     p->u.params.cl, p->u.params.minrate, p->u.params.maxrate,
7793                     p->u.params.weight, p->u.params.pktsize, 1);
7794                 goto done;
7795         }
7796
7797         rc = EINVAL;
7798 done:
7799         end_synchronized_op(sc, 0);
7800         return (rc);
7801 }
7802
7803 static int
7804 set_sched_queue(struct adapter *sc, struct t4_sched_queue *p)
7805 {
7806         struct port_info *pi = NULL;
7807         struct sge_txq *txq;
7808         uint32_t fw_mnem, fw_queue, fw_class;
7809         int i, rc;
7810
7811         rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq");
7812         if (rc)
7813                 return (rc);
7814
7815         if (!(sc->flags & FULL_INIT_DONE)) {
7816                 rc = EAGAIN;
7817                 goto done;
7818         }
7819
7820         if (p->port >= sc->params.nports) {
7821                 rc = EINVAL;
7822                 goto done;
7823         }
7824
7825         pi = sc->port[p->port];
7826         if (!in_range(p->queue, 0, pi->ntxq - 1) || !in_range(p->cl, 0, 7)) {
7827                 rc = EINVAL;
7828                 goto done;
7829         }
7830
7831         /*
7832          * Create a template for the FW_PARAMS_CMD mnemonic and value (TX
7833          * Scheduling Class in this case).
7834          */
7835         fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
7836             V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH));
7837         fw_class = p->cl < 0 ? 0xffffffff : p->cl;
7838
7839         /*
7840          * If op.queue is non-negative, then we're only changing the scheduling
7841          * on a single specified TX queue.
7842          */
7843         if (p->queue >= 0) {
7844                 txq = &sc->sge.txq[pi->first_txq + p->queue];
7845                 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
7846                 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
7847                     &fw_class);
7848                 goto done;
7849         }
7850
7851         /*
7852          * Change the scheduling on all the TX queues for the
7853          * interface.
7854          */
7855         for_each_txq(pi, i, txq) {
7856                 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
7857                 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
7858                     &fw_class);
7859                 if (rc)
7860                         goto done;
7861         }
7862
7863         rc = 0;
7864 done:
7865         end_synchronized_op(sc, 0);
7866         return (rc);
7867 }
7868
7869 int
7870 t4_os_find_pci_capability(struct adapter *sc, int cap)
7871 {
7872         int i;
7873
7874         return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
7875 }
7876
7877 int
7878 t4_os_pci_save_state(struct adapter *sc)
7879 {
7880         device_t dev;
7881         struct pci_devinfo *dinfo;
7882
7883         dev = sc->dev;
7884         dinfo = device_get_ivars(dev);
7885
7886         pci_cfg_save(dev, dinfo, 0);
7887         return (0);
7888 }
7889
7890 int
7891 t4_os_pci_restore_state(struct adapter *sc)
7892 {
7893         device_t dev;
7894         struct pci_devinfo *dinfo;
7895
7896         dev = sc->dev;
7897         dinfo = device_get_ivars(dev);
7898
7899         pci_cfg_restore(dev, dinfo);
7900         return (0);
7901 }
7902
7903 void
7904 t4_os_portmod_changed(const struct adapter *sc, int idx)
7905 {
7906         struct port_info *pi = sc->port[idx];
7907         static const char *mod_str[] = {
7908                 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
7909         };
7910
7911         build_medialist(pi, &pi->media);
7912 #ifdef DEV_NETMAP
7913         build_medialist(pi, &pi->nm_media);
7914 #endif
7915
7916         if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
7917                 if_printf(pi->ifp, "transceiver unplugged.\n");
7918         else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
7919                 if_printf(pi->ifp, "unknown transceiver inserted.\n");
7920         else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
7921                 if_printf(pi->ifp, "unsupported transceiver inserted.\n");
7922         else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
7923                 if_printf(pi->ifp, "%s transceiver inserted.\n",
7924                     mod_str[pi->mod_type]);
7925         } else {
7926                 if_printf(pi->ifp, "transceiver (type %d) inserted.\n",
7927                     pi->mod_type);
7928         }
7929 }
7930
7931 void
7932 t4_os_link_changed(struct adapter *sc, int idx, int link_stat, int reason)
7933 {
7934         struct port_info *pi = sc->port[idx];
7935         struct ifnet *ifp = pi->ifp;
7936
7937         if (link_stat) {
7938                 pi->linkdnrc = -1;
7939                 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed);
7940                 if_link_state_change(ifp, LINK_STATE_UP);
7941         } else {
7942                 if (reason >= 0)
7943                         pi->linkdnrc = reason;
7944                 if_link_state_change(ifp, LINK_STATE_DOWN);
7945         }
7946 }
7947
7948 void
7949 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
7950 {
7951         struct adapter *sc;
7952
7953         sx_slock(&t4_list_lock);
7954         SLIST_FOREACH(sc, &t4_list, link) {
7955                 /*
7956                  * func should not make any assumptions about what state sc is
7957                  * in - the only guarantee is that sc->sc_lock is a valid lock.
7958                  */
7959                 func(sc, arg);
7960         }
7961         sx_sunlock(&t4_list_lock);
7962 }
7963
7964 static int
7965 t4_open(struct cdev *dev, int flags, int type, struct thread *td)
7966 {
7967        return (0);
7968 }
7969
7970 static int
7971 t4_close(struct cdev *dev, int flags, int type, struct thread *td)
7972 {
7973        return (0);
7974 }
7975
7976 static int
7977 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
7978     struct thread *td)
7979 {
7980         int rc;
7981         struct adapter *sc = dev->si_drv1;
7982
7983         rc = priv_check(td, PRIV_DRIVER);
7984         if (rc != 0)
7985                 return (rc);
7986
7987         switch (cmd) {
7988         case CHELSIO_T4_GETREG: {
7989                 struct t4_reg *edata = (struct t4_reg *)data;
7990
7991                 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
7992                         return (EFAULT);
7993
7994                 if (edata->size == 4)
7995                         edata->val = t4_read_reg(sc, edata->addr);
7996                 else if (edata->size == 8)
7997                         edata->val = t4_read_reg64(sc, edata->addr);
7998                 else
7999                         return (EINVAL);
8000
8001                 break;
8002         }
8003         case CHELSIO_T4_SETREG: {
8004                 struct t4_reg *edata = (struct t4_reg *)data;
8005
8006                 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8007                         return (EFAULT);
8008
8009                 if (edata->size == 4) {
8010                         if (edata->val & 0xffffffff00000000)
8011                                 return (EINVAL);
8012                         t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
8013                 } else if (edata->size == 8)
8014                         t4_write_reg64(sc, edata->addr, edata->val);
8015                 else
8016                         return (EINVAL);
8017                 break;
8018         }
8019         case CHELSIO_T4_REGDUMP: {
8020                 struct t4_regdump *regs = (struct t4_regdump *)data;
8021                 int reglen = is_t4(sc) ? T4_REGDUMP_SIZE : T5_REGDUMP_SIZE;
8022                 uint8_t *buf;
8023
8024                 if (regs->len < reglen) {
8025                         regs->len = reglen; /* hint to the caller */
8026                         return (ENOBUFS);
8027                 }
8028
8029                 regs->len = reglen;
8030                 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
8031                 t4_get_regs(sc, regs, buf);
8032                 rc = copyout(buf, regs->data, reglen);
8033                 free(buf, M_CXGBE);
8034                 break;
8035         }
8036         case CHELSIO_T4_GET_FILTER_MODE:
8037                 rc = get_filter_mode(sc, (uint32_t *)data);
8038                 break;
8039         case CHELSIO_T4_SET_FILTER_MODE:
8040                 rc = set_filter_mode(sc, *(uint32_t *)data);
8041                 break;
8042         case CHELSIO_T4_GET_FILTER:
8043                 rc = get_filter(sc, (struct t4_filter *)data);
8044                 break;
8045         case CHELSIO_T4_SET_FILTER:
8046                 rc = set_filter(sc, (struct t4_filter *)data);
8047                 break;
8048         case CHELSIO_T4_DEL_FILTER:
8049                 rc = del_filter(sc, (struct t4_filter *)data);
8050                 break;
8051         case CHELSIO_T4_GET_SGE_CONTEXT:
8052                 rc = get_sge_context(sc, (struct t4_sge_context *)data);
8053                 break;
8054         case CHELSIO_T4_LOAD_FW:
8055                 rc = load_fw(sc, (struct t4_data *)data);
8056                 break;
8057         case CHELSIO_T4_GET_MEM:
8058                 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
8059                 break;
8060         case CHELSIO_T4_GET_I2C:
8061                 rc = read_i2c(sc, (struct t4_i2c_data *)data);
8062                 break;
8063         case CHELSIO_T4_CLEAR_STATS: {
8064                 int i;
8065                 u_int port_id = *(uint32_t *)data;
8066                 struct port_info *pi;
8067
8068                 if (port_id >= sc->params.nports)
8069                         return (EINVAL);
8070                 pi = sc->port[port_id];
8071
8072                 /* MAC stats */
8073                 t4_clr_port_stats(sc, pi->tx_chan);
8074
8075                 if (pi->flags & PORT_INIT_DONE) {
8076                         struct sge_rxq *rxq;
8077                         struct sge_txq *txq;
8078                         struct sge_wrq *wrq;
8079
8080                         for_each_rxq(pi, i, rxq) {
8081 #if defined(INET) || defined(INET6)
8082                                 rxq->lro.lro_queued = 0;
8083                                 rxq->lro.lro_flushed = 0;
8084 #endif
8085                                 rxq->rxcsum = 0;
8086                                 rxq->vlan_extraction = 0;
8087                         }
8088
8089                         for_each_txq(pi, i, txq) {
8090                                 txq->txcsum = 0;
8091                                 txq->tso_wrs = 0;
8092                                 txq->vlan_insertion = 0;
8093                                 txq->imm_wrs = 0;
8094                                 txq->sgl_wrs = 0;
8095                                 txq->txpkt_wrs = 0;
8096                                 txq->txpkts_wrs = 0;
8097                                 txq->txpkts_pkts = 0;
8098                                 txq->br->br_drops = 0;
8099                                 txq->no_dmamap = 0;
8100                                 txq->no_desc = 0;
8101                         }
8102
8103 #ifdef TCP_OFFLOAD
8104                         /* nothing to clear for each ofld_rxq */
8105
8106                         for_each_ofld_txq(pi, i, wrq) {
8107                                 wrq->tx_wrs = 0;
8108                                 wrq->no_desc = 0;
8109                         }
8110 #endif
8111                         wrq = &sc->sge.ctrlq[pi->port_id];
8112                         wrq->tx_wrs = 0;
8113                         wrq->no_desc = 0;
8114                 }
8115                 break;
8116         }
8117         case CHELSIO_T4_SCHED_CLASS:
8118                 rc = set_sched_class(sc, (struct t4_sched_params *)data);
8119                 break;
8120         case CHELSIO_T4_SCHED_QUEUE:
8121                 rc = set_sched_queue(sc, (struct t4_sched_queue *)data);
8122                 break;
8123         case CHELSIO_T4_GET_TRACER:
8124                 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
8125                 break;
8126         case CHELSIO_T4_SET_TRACER:
8127                 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
8128                 break;
8129         default:
8130                 rc = EINVAL;
8131         }
8132
8133         return (rc);
8134 }
8135
8136 #ifdef TCP_OFFLOAD
8137 void
8138 t4_iscsi_init(struct ifnet *ifp, unsigned int tag_mask,
8139     const unsigned int *pgsz_order)
8140 {
8141         struct port_info *pi = ifp->if_softc;
8142         struct adapter *sc = pi->adapter;
8143
8144         t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask);
8145         t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) |
8146                 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) |
8147                 V_HPZ3(pgsz_order[3]));
8148 }
8149
8150 static int
8151 toe_capability(struct port_info *pi, int enable)
8152 {
8153         int rc;
8154         struct adapter *sc = pi->adapter;
8155
8156         ASSERT_SYNCHRONIZED_OP(sc);
8157
8158         if (!is_offload(sc))
8159                 return (ENODEV);
8160
8161         if (enable) {
8162                 /*
8163                  * We need the port's queues around so that we're able to send
8164                  * and receive CPLs to/from the TOE even if the ifnet for this
8165                  * port has never been UP'd administratively.
8166                  */
8167                 if (!(pi->flags & PORT_INIT_DONE)) {
8168                         rc = cxgbe_init_synchronized(pi);
8169                         if (rc)
8170                                 return (rc);
8171                 }
8172
8173                 if (isset(&sc->offload_map, pi->port_id))
8174                         return (0);
8175
8176                 if (!(sc->flags & TOM_INIT_DONE)) {
8177                         rc = t4_activate_uld(sc, ULD_TOM);
8178                         if (rc == EAGAIN) {
8179                                 log(LOG_WARNING,
8180                                     "You must kldload t4_tom.ko before trying "
8181                                     "to enable TOE on a cxgbe interface.\n");
8182                         }
8183                         if (rc != 0)
8184                                 return (rc);
8185                         KASSERT(sc->tom_softc != NULL,
8186                             ("%s: TOM activated but softc NULL", __func__));
8187                         KASSERT(sc->flags & TOM_INIT_DONE,
8188                             ("%s: TOM activated but flag not set", __func__));
8189                 }
8190
8191                 setbit(&sc->offload_map, pi->port_id);
8192         } else {
8193                 if (!isset(&sc->offload_map, pi->port_id))
8194                         return (0);
8195
8196                 KASSERT(sc->flags & TOM_INIT_DONE,
8197                     ("%s: TOM never initialized?", __func__));
8198                 clrbit(&sc->offload_map, pi->port_id);
8199         }
8200
8201         return (0);
8202 }
8203
8204 /*
8205  * Add an upper layer driver to the global list.
8206  */
8207 int
8208 t4_register_uld(struct uld_info *ui)
8209 {
8210         int rc = 0;
8211         struct uld_info *u;
8212
8213         sx_xlock(&t4_uld_list_lock);
8214         SLIST_FOREACH(u, &t4_uld_list, link) {
8215             if (u->uld_id == ui->uld_id) {
8216                     rc = EEXIST;
8217                     goto done;
8218             }
8219         }
8220
8221         SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
8222         ui->refcount = 0;
8223 done:
8224         sx_xunlock(&t4_uld_list_lock);
8225         return (rc);
8226 }
8227
8228 int
8229 t4_unregister_uld(struct uld_info *ui)
8230 {
8231         int rc = EINVAL;
8232         struct uld_info *u;
8233
8234         sx_xlock(&t4_uld_list_lock);
8235
8236         SLIST_FOREACH(u, &t4_uld_list, link) {
8237             if (u == ui) {
8238                     if (ui->refcount > 0) {
8239                             rc = EBUSY;
8240                             goto done;
8241                     }
8242
8243                     SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
8244                     rc = 0;
8245                     goto done;
8246             }
8247         }
8248 done:
8249         sx_xunlock(&t4_uld_list_lock);
8250         return (rc);
8251 }
8252
8253 int
8254 t4_activate_uld(struct adapter *sc, int id)
8255 {
8256         int rc = EAGAIN;
8257         struct uld_info *ui;
8258
8259         ASSERT_SYNCHRONIZED_OP(sc);
8260
8261         sx_slock(&t4_uld_list_lock);
8262
8263         SLIST_FOREACH(ui, &t4_uld_list, link) {
8264                 if (ui->uld_id == id) {
8265                         if (!(sc->flags & FULL_INIT_DONE)) {
8266                                 rc = adapter_full_init(sc);
8267                                 if (rc != 0)
8268                                         goto done;
8269                         }
8270
8271                         rc = ui->activate(sc);
8272                         if (rc == 0)
8273                                 ui->refcount++;
8274                         goto done;
8275                 }
8276         }
8277 done:
8278         sx_sunlock(&t4_uld_list_lock);
8279
8280         return (rc);
8281 }
8282
8283 int
8284 t4_deactivate_uld(struct adapter *sc, int id)
8285 {
8286         int rc = EINVAL;
8287         struct uld_info *ui;
8288
8289         ASSERT_SYNCHRONIZED_OP(sc);
8290
8291         sx_slock(&t4_uld_list_lock);
8292
8293         SLIST_FOREACH(ui, &t4_uld_list, link) {
8294                 if (ui->uld_id == id) {
8295                         rc = ui->deactivate(sc);
8296                         if (rc == 0)
8297                                 ui->refcount--;
8298                         goto done;
8299                 }
8300         }
8301 done:
8302         sx_sunlock(&t4_uld_list_lock);
8303
8304         return (rc);
8305 }
8306 #endif
8307
8308 /*
8309  * Come up with reasonable defaults for some of the tunables, provided they're
8310  * not set by the user (in which case we'll use the values as is).
8311  */
8312 static void
8313 tweak_tunables(void)
8314 {
8315         int nc = mp_ncpus;      /* our snapshot of the number of CPUs */
8316
8317         if (t4_ntxq10g < 1)
8318                 t4_ntxq10g = min(nc, NTXQ_10G);
8319
8320         if (t4_ntxq1g < 1)
8321                 t4_ntxq1g = min(nc, NTXQ_1G);
8322
8323         if (t4_nrxq10g < 1)
8324                 t4_nrxq10g = min(nc, NRXQ_10G);
8325
8326         if (t4_nrxq1g < 1)
8327                 t4_nrxq1g = min(nc, NRXQ_1G);
8328
8329 #ifdef TCP_OFFLOAD
8330         if (t4_nofldtxq10g < 1)
8331                 t4_nofldtxq10g = min(nc, NOFLDTXQ_10G);
8332
8333         if (t4_nofldtxq1g < 1)
8334                 t4_nofldtxq1g = min(nc, NOFLDTXQ_1G);
8335
8336         if (t4_nofldrxq10g < 1)
8337                 t4_nofldrxq10g = min(nc, NOFLDRXQ_10G);
8338
8339         if (t4_nofldrxq1g < 1)
8340                 t4_nofldrxq1g = min(nc, NOFLDRXQ_1G);
8341
8342         if (t4_toecaps_allowed == -1)
8343                 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
8344 #else
8345         if (t4_toecaps_allowed == -1)
8346                 t4_toecaps_allowed = 0;
8347 #endif
8348
8349 #ifdef DEV_NETMAP
8350         if (t4_nnmtxq10g < 1)
8351                 t4_nnmtxq10g = min(nc, NNMTXQ_10G);
8352
8353         if (t4_nnmtxq1g < 1)
8354                 t4_nnmtxq1g = min(nc, NNMTXQ_1G);
8355
8356         if (t4_nnmrxq10g < 1)
8357                 t4_nnmrxq10g = min(nc, NNMRXQ_10G);
8358
8359         if (t4_nnmrxq1g < 1)
8360                 t4_nnmrxq1g = min(nc, NNMRXQ_1G);
8361 #endif
8362
8363         if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS)
8364                 t4_tmr_idx_10g = TMR_IDX_10G;
8365
8366         if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS)
8367                 t4_pktc_idx_10g = PKTC_IDX_10G;
8368
8369         if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS)
8370                 t4_tmr_idx_1g = TMR_IDX_1G;
8371
8372         if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS)
8373                 t4_pktc_idx_1g = PKTC_IDX_1G;
8374
8375         if (t4_qsize_txq < 128)
8376                 t4_qsize_txq = 128;
8377
8378         if (t4_qsize_rxq < 128)
8379                 t4_qsize_rxq = 128;
8380         while (t4_qsize_rxq & 7)
8381                 t4_qsize_rxq++;
8382
8383         t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
8384 }
8385
8386 static struct sx mlu;   /* mod load unload */
8387 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
8388
8389 static int
8390 mod_event(module_t mod, int cmd, void *arg)
8391 {
8392         int rc = 0;
8393         static int loaded = 0;
8394
8395         switch (cmd) {
8396         case MOD_LOAD:
8397                 sx_xlock(&mlu);
8398                 if (loaded++ == 0) {
8399                         t4_sge_modload();
8400                         sx_init(&t4_list_lock, "T4/T5 adapters");
8401                         SLIST_INIT(&t4_list);
8402 #ifdef TCP_OFFLOAD
8403                         sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
8404                         SLIST_INIT(&t4_uld_list);
8405 #endif
8406                         t4_tracer_modload();
8407                         tweak_tunables();
8408                 }
8409                 sx_xunlock(&mlu);
8410                 break;
8411
8412         case MOD_UNLOAD:
8413                 sx_xlock(&mlu);
8414                 if (--loaded == 0) {
8415                         int tries;
8416
8417                         sx_slock(&t4_list_lock);
8418                         if (!SLIST_EMPTY(&t4_list)) {
8419                                 rc = EBUSY;
8420                                 sx_sunlock(&t4_list_lock);
8421                                 goto done_unload;
8422                         }
8423 #ifdef TCP_OFFLOAD
8424                         sx_slock(&t4_uld_list_lock);
8425                         if (!SLIST_EMPTY(&t4_uld_list)) {
8426                                 rc = EBUSY;
8427                                 sx_sunlock(&t4_uld_list_lock);
8428                                 sx_sunlock(&t4_list_lock);
8429                                 goto done_unload;
8430                         }
8431 #endif
8432                         tries = 0;
8433                         while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
8434                                 uprintf("%ju clusters with custom free routine "
8435                                     "still is use.\n", t4_sge_extfree_refs());
8436                                 pause("t4unload", 2 * hz);
8437                         }
8438 #ifdef TCP_OFFLOAD
8439                         sx_sunlock(&t4_uld_list_lock);
8440 #endif
8441                         sx_sunlock(&t4_list_lock);
8442
8443                         if (t4_sge_extfree_refs() == 0) {
8444                                 t4_tracer_modunload();
8445 #ifdef TCP_OFFLOAD
8446                                 sx_destroy(&t4_uld_list_lock);
8447 #endif
8448                                 sx_destroy(&t4_list_lock);
8449                                 t4_sge_modunload();
8450                                 loaded = 0;
8451                         } else {
8452                                 rc = EBUSY;
8453                                 loaded++;       /* undo earlier decrement */
8454                         }
8455                 }
8456 done_unload:
8457                 sx_xunlock(&mlu);
8458                 break;
8459         }
8460
8461         return (rc);
8462 }
8463
8464 static devclass_t t4_devclass, t5_devclass;
8465 static devclass_t cxgbe_devclass, cxl_devclass;
8466
8467 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
8468 MODULE_VERSION(t4nex, 1);
8469 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
8470
8471 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
8472 MODULE_VERSION(t5nex, 1);
8473 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
8474
8475 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
8476 MODULE_VERSION(cxgbe, 1);
8477
8478 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
8479 MODULE_VERSION(cxl, 1);