2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include "opt_inet6.h"
35 #include <sys/param.h>
38 #include <sys/kernel.h>
40 #include <sys/systm.h>
41 #include <sys/counter.h>
42 #include <sys/module.h>
43 #include <sys/malloc.h>
44 #include <sys/queue.h>
45 #include <sys/taskqueue.h>
46 #include <sys/pciio.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pci_private.h>
50 #include <sys/firmware.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
55 #include <sys/sysctl.h>
56 #include <net/ethernet.h>
58 #include <net/if_types.h>
59 #include <net/if_dl.h>
60 #include <net/if_vlan_var.h>
62 #include <net/rss_config.h>
64 #if defined(__i386__) || defined(__amd64__)
70 #include <ddb/db_lex.h>
73 #include "common/common.h"
74 #include "common/t4_msg.h"
75 #include "common/t4_regs.h"
76 #include "common/t4_regs_values.h"
79 #include "t4_mp_ring.h"
81 /* T4 bus driver interface */
82 static int t4_probe(device_t);
83 static int t4_attach(device_t);
84 static int t4_detach(device_t);
85 static device_method_t t4_methods[] = {
86 DEVMETHOD(device_probe, t4_probe),
87 DEVMETHOD(device_attach, t4_attach),
88 DEVMETHOD(device_detach, t4_detach),
92 static driver_t t4_driver = {
95 sizeof(struct adapter)
99 /* T4 port (cxgbe) interface */
100 static int cxgbe_probe(device_t);
101 static int cxgbe_attach(device_t);
102 static int cxgbe_detach(device_t);
103 device_method_t cxgbe_methods[] = {
104 DEVMETHOD(device_probe, cxgbe_probe),
105 DEVMETHOD(device_attach, cxgbe_attach),
106 DEVMETHOD(device_detach, cxgbe_detach),
109 static driver_t cxgbe_driver = {
112 sizeof(struct port_info)
115 /* T4 VI (vcxgbe) interface */
116 static int vcxgbe_probe(device_t);
117 static int vcxgbe_attach(device_t);
118 static int vcxgbe_detach(device_t);
119 static device_method_t vcxgbe_methods[] = {
120 DEVMETHOD(device_probe, vcxgbe_probe),
121 DEVMETHOD(device_attach, vcxgbe_attach),
122 DEVMETHOD(device_detach, vcxgbe_detach),
125 static driver_t vcxgbe_driver = {
128 sizeof(struct vi_info)
131 static d_ioctl_t t4_ioctl;
133 static struct cdevsw t4_cdevsw = {
134 .d_version = D_VERSION,
139 /* T5 bus driver interface */
140 static int t5_probe(device_t);
141 static device_method_t t5_methods[] = {
142 DEVMETHOD(device_probe, t5_probe),
143 DEVMETHOD(device_attach, t4_attach),
144 DEVMETHOD(device_detach, t4_detach),
148 static driver_t t5_driver = {
151 sizeof(struct adapter)
155 /* T5 port (cxl) interface */
156 static driver_t cxl_driver = {
159 sizeof(struct port_info)
162 /* T5 VI (vcxl) interface */
163 static driver_t vcxl_driver = {
166 sizeof(struct vi_info)
169 /* T6 bus driver interface */
170 static int t6_probe(device_t);
171 static device_method_t t6_methods[] = {
172 DEVMETHOD(device_probe, t6_probe),
173 DEVMETHOD(device_attach, t4_attach),
174 DEVMETHOD(device_detach, t4_detach),
178 static driver_t t6_driver = {
181 sizeof(struct adapter)
185 /* T6 port (cc) interface */
186 static driver_t cc_driver = {
189 sizeof(struct port_info)
192 /* T6 VI (vcc) interface */
193 static driver_t vcc_driver = {
196 sizeof(struct vi_info)
199 /* ifnet + media interface */
200 static void cxgbe_init(void *);
201 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
202 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
203 static void cxgbe_qflush(struct ifnet *);
204 static int cxgbe_media_change(struct ifnet *);
205 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
207 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
210 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
211 * then ADAPTER_LOCK, then t4_uld_list_lock.
213 static struct sx t4_list_lock;
214 SLIST_HEAD(, adapter) t4_list;
216 static struct sx t4_uld_list_lock;
217 SLIST_HEAD(, uld_info) t4_uld_list;
221 * Tunables. See tweak_tunables() too.
223 * Each tunable is set to a default value here if it's known at compile-time.
224 * Otherwise it is set to -1 as an indication to tweak_tunables() that it should
225 * provide a reasonable default when the driver is loaded.
227 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
228 * T5 are under hw.cxl.
232 * Number of queues for tx and rx, 10G and 1G, NIC and offload.
236 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g);
240 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g);
244 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g);
248 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g);
251 static int t4_ntxq_vi = -1;
252 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi);
255 static int t4_nrxq_vi = -1;
256 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi);
258 static int t4_rsrv_noflowq = 0;
259 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq);
262 #define NOFLDTXQ_10G 8
263 static int t4_nofldtxq10g = -1;
264 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g);
266 #define NOFLDRXQ_10G 2
267 static int t4_nofldrxq10g = -1;
268 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g);
270 #define NOFLDTXQ_1G 2
271 static int t4_nofldtxq1g = -1;
272 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g);
274 #define NOFLDRXQ_1G 1
275 static int t4_nofldrxq1g = -1;
276 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g);
278 #define NOFLDTXQ_VI 1
279 static int t4_nofldtxq_vi = -1;
280 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi);
282 #define NOFLDRXQ_VI 1
283 static int t4_nofldrxq_vi = -1;
284 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi);
289 static int t4_nnmtxq_vi = -1;
290 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi);
293 static int t4_nnmrxq_vi = -1;
294 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi);
298 * Holdoff parameters for 10G and 1G ports.
300 #define TMR_IDX_10G 1
301 int t4_tmr_idx_10g = TMR_IDX_10G;
302 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g);
304 #define PKTC_IDX_10G (-1)
305 int t4_pktc_idx_10g = PKTC_IDX_10G;
306 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g);
309 int t4_tmr_idx_1g = TMR_IDX_1G;
310 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g);
312 #define PKTC_IDX_1G (-1)
313 int t4_pktc_idx_1g = PKTC_IDX_1G;
314 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g);
317 * Size (# of entries) of each tx and rx queue.
319 unsigned int t4_qsize_txq = TX_EQ_QSIZE;
320 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
322 unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
323 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
326 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
328 int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
329 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
332 * Configuration file.
334 #define DEFAULT_CF "default"
335 #define FLASH_CF "flash"
336 #define UWIRE_CF "uwire"
337 #define FPGA_CF "fpga"
338 static char t4_cfg_file[32] = DEFAULT_CF;
339 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
342 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively).
343 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
344 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
345 * mark or when signalled to do so, 0 to never emit PAUSE.
347 static int t4_pause_settings = PAUSE_TX | PAUSE_RX;
348 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings);
351 * Forward Error Correction settings (bit 0, 1, 2 = FEC_RS, FEC_BASER_RS,
352 * FEC_RESERVED respectively).
353 * -1 to run with the firmware default.
356 static int t4_fec = -1;
357 TUNABLE_INT("hw.cxgbe.fec", &t4_fec);
360 * Link autonegotiation.
361 * -1 to run with the firmware default.
365 static int t4_autoneg = -1;
366 TUNABLE_INT("hw.cxgbe.autoneg", &t4_autoneg);
369 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
370 * encouraged respectively).
372 static unsigned int t4_fw_install = 1;
373 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install);
376 * ASIC features that will be used. Disable the ones you don't want so that the
377 * chip resources aren't wasted on features that will not be used.
379 static int t4_nbmcaps_allowed = 0;
380 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed);
382 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
383 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
385 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
386 FW_CAPS_CONFIG_SWITCH_EGRESS;
387 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed);
389 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
390 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
392 static int t4_toecaps_allowed = -1;
393 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
395 static int t4_rdmacaps_allowed = -1;
396 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
398 static int t4_cryptocaps_allowed = 0;
399 TUNABLE_INT("hw.cxgbe.cryptocaps_allowed", &t4_cryptocaps_allowed);
401 static int t4_iscsicaps_allowed = -1;
402 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
404 static int t4_fcoecaps_allowed = 0;
405 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
407 static int t5_write_combine = 0;
408 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
410 static int t4_num_vis = 1;
411 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis);
413 /* Functions used by extra VIs to obtain unique MAC addresses for each VI. */
414 static int vi_mac_funcs[] = {
417 FW_VI_FUNC_OPENISCSI,
423 struct intrs_and_queues {
424 uint16_t intr_type; /* INTx, MSI, or MSI-X */
425 uint16_t nirq; /* Total # of vectors */
426 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */
427 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */
428 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */
429 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */
430 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */
431 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */
432 uint16_t rsrv_noflowq; /* Flag whether to reserve queue 0 */
433 uint16_t nofldtxq10g; /* # of TOE txq's for each 10G port */
434 uint16_t nofldrxq10g; /* # of TOE rxq's for each 10G port */
435 uint16_t nofldtxq1g; /* # of TOE txq's for each 1G port */
436 uint16_t nofldrxq1g; /* # of TOE rxq's for each 1G port */
438 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
439 uint16_t ntxq_vi; /* # of NIC txq's */
440 uint16_t nrxq_vi; /* # of NIC rxq's */
441 uint16_t nofldtxq_vi; /* # of TOE txq's */
442 uint16_t nofldrxq_vi; /* # of TOE rxq's */
443 uint16_t nnmtxq_vi; /* # of netmap txq's */
444 uint16_t nnmrxq_vi; /* # of netmap rxq's */
447 struct filter_entry {
448 uint32_t valid:1; /* filter allocated and valid */
449 uint32_t locked:1; /* filter is administratively locked */
450 uint32_t pending:1; /* filter action is pending firmware reply */
451 uint32_t smtidx:8; /* Source MAC Table index for smac */
452 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
454 struct t4_filter_specification fs;
457 static void setup_memwin(struct adapter *);
458 static void position_memwin(struct adapter *, int, uint32_t);
459 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
460 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *,
462 static inline int write_via_memwin(struct adapter *, int, uint32_t,
463 const uint32_t *, int);
464 static int validate_mem_range(struct adapter *, uint32_t, int);
465 static int fwmtype_to_hwmtype(int);
466 static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
468 static int fixup_devlog_params(struct adapter *);
469 static int cfg_itype_and_nqueues(struct adapter *, int, int, int,
470 struct intrs_and_queues *);
471 static int prep_firmware(struct adapter *);
472 static int partition_resources(struct adapter *, const struct firmware *,
474 static int get_params__pre_init(struct adapter *);
475 static int get_params__post_init(struct adapter *);
476 static int set_params__post_init(struct adapter *);
477 static void t4_set_desc(struct adapter *);
478 static void build_medialist(struct port_info *, struct ifmedia *);
479 static int cxgbe_init_synchronized(struct vi_info *);
480 static int cxgbe_uninit_synchronized(struct vi_info *);
481 static void quiesce_txq(struct adapter *, struct sge_txq *);
482 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
483 static void quiesce_iq(struct adapter *, struct sge_iq *);
484 static void quiesce_fl(struct adapter *, struct sge_fl *);
485 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
486 driver_intr_t *, void *, char *);
487 static int t4_free_irq(struct adapter *, struct irq *);
488 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
489 static void vi_refresh_stats(struct adapter *, struct vi_info *);
490 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
491 static void cxgbe_tick(void *);
492 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
493 static void cxgbe_sysctls(struct port_info *);
494 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
495 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
496 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
497 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
498 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
499 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
500 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
501 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
502 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
503 static int sysctl_fec(SYSCTL_HANDLER_ARGS);
504 static int sysctl_autoneg(SYSCTL_HANDLER_ARGS);
505 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
506 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
508 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
509 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
510 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
511 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
512 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
513 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
514 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
515 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
516 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
517 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
518 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
519 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
520 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
521 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
522 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
523 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
524 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
525 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
526 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
527 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
528 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
529 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
530 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
531 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
532 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
533 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
534 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
535 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
536 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
539 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
540 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
541 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
543 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t);
544 static uint32_t mode_to_fconf(uint32_t);
545 static uint32_t mode_to_iconf(uint32_t);
546 static int check_fspec_against_fconf_iconf(struct adapter *,
547 struct t4_filter_specification *);
548 static int get_filter_mode(struct adapter *, uint32_t *);
549 static int set_filter_mode(struct adapter *, uint32_t);
550 static inline uint64_t get_filter_hits(struct adapter *, uint32_t);
551 static int get_filter(struct adapter *, struct t4_filter *);
552 static int set_filter(struct adapter *, struct t4_filter *);
553 static int del_filter(struct adapter *, struct t4_filter *);
554 static void clear_filter(struct filter_entry *);
555 static int set_filter_wr(struct adapter *, int);
556 static int del_filter_wr(struct adapter *, int);
557 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *,
559 static int get_sge_context(struct adapter *, struct t4_sge_context *);
560 static int load_fw(struct adapter *, struct t4_data *);
561 static int load_cfg(struct adapter *, struct t4_data *);
562 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
563 static int read_i2c(struct adapter *, struct t4_i2c_data *);
565 static int toe_capability(struct vi_info *, int);
567 static int mod_event(module_t, int, void *);
573 {0xa000, "Chelsio Terminator 4 FPGA"},
574 {0x4400, "Chelsio T440-dbg"},
575 {0x4401, "Chelsio T420-CR"},
576 {0x4402, "Chelsio T422-CR"},
577 {0x4403, "Chelsio T440-CR"},
578 {0x4404, "Chelsio T420-BCH"},
579 {0x4405, "Chelsio T440-BCH"},
580 {0x4406, "Chelsio T440-CH"},
581 {0x4407, "Chelsio T420-SO"},
582 {0x4408, "Chelsio T420-CX"},
583 {0x4409, "Chelsio T420-BT"},
584 {0x440a, "Chelsio T404-BT"},
585 {0x440e, "Chelsio T440-LP-CR"},
587 {0xb000, "Chelsio Terminator 5 FPGA"},
588 {0x5400, "Chelsio T580-dbg"},
589 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
590 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
591 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
592 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
593 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
594 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
595 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
596 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
597 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
598 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
599 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
600 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
601 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
603 {0x5404, "Chelsio T520-BCH"},
604 {0x5405, "Chelsio T540-BCH"},
605 {0x5406, "Chelsio T540-CH"},
606 {0x5408, "Chelsio T520-CX"},
607 {0x540b, "Chelsio B520-SR"},
608 {0x540c, "Chelsio B504-BT"},
609 {0x540f, "Chelsio Amsterdam"},
610 {0x5413, "Chelsio T580-CHR"},
613 {0xc006, "Chelsio Terminator 6 FPGA"}, /* T6 PE10K6 FPGA (PF0) */
614 {0x6401, "Chelsio T6225-CR"}, /* 2 x 10/25G */
615 {0x6402, "Chelsio T6225-SO-CR"}, /* 2 x 10/25G, nomem */
616 {0x6407, "Chelsio T62100-LP-CR"}, /* 2 x 40/50/100G */
617 {0x6408, "Chelsio T62100-SO-CR"}, /* 2 x 40/50/100G, nomem */
618 {0x640d, "Chelsio T62100-CR"}, /* 2 x 40/50/100G */
619 {0x6410, "Chelsio T62100-DBG"}, /* 2 x 40/50/100G, debug */
624 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be
625 * exactly the same for both rxq and ofld_rxq.
627 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
628 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
630 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
633 t4_probe(device_t dev)
636 uint16_t v = pci_get_vendor(dev);
637 uint16_t d = pci_get_device(dev);
638 uint8_t f = pci_get_function(dev);
640 if (v != PCI_VENDOR_ID_CHELSIO)
643 /* Attach only to PF0 of the FPGA */
644 if (d == 0xa000 && f != 0)
647 for (i = 0; i < nitems(t4_pciids); i++) {
648 if (d == t4_pciids[i].device) {
649 device_set_desc(dev, t4_pciids[i].desc);
650 return (BUS_PROBE_DEFAULT);
658 t5_probe(device_t dev)
661 uint16_t v = pci_get_vendor(dev);
662 uint16_t d = pci_get_device(dev);
663 uint8_t f = pci_get_function(dev);
665 if (v != PCI_VENDOR_ID_CHELSIO)
668 /* Attach only to PF0 of the FPGA */
669 if (d == 0xb000 && f != 0)
672 for (i = 0; i < nitems(t5_pciids); i++) {
673 if (d == t5_pciids[i].device) {
674 device_set_desc(dev, t5_pciids[i].desc);
675 return (BUS_PROBE_DEFAULT);
683 t6_probe(device_t dev)
686 uint16_t v = pci_get_vendor(dev);
687 uint16_t d = pci_get_device(dev);
689 if (v != PCI_VENDOR_ID_CHELSIO)
692 for (i = 0; i < nitems(t6_pciids); i++) {
693 if (d == t6_pciids[i].device) {
694 device_set_desc(dev, t6_pciids[i].desc);
695 return (BUS_PROBE_DEFAULT);
703 t5_attribute_workaround(device_t dev)
709 * The T5 chips do not properly echo the No Snoop and Relaxed
710 * Ordering attributes when replying to a TLP from a Root
711 * Port. As a workaround, find the parent Root Port and
712 * disable No Snoop and Relaxed Ordering. Note that this
713 * affects all devices under this root port.
715 root_port = pci_find_pcie_root_port(dev);
716 if (root_port == NULL) {
717 device_printf(dev, "Unable to find parent root port\n");
721 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
722 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
723 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
725 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
726 device_get_nameunit(root_port));
729 static const struct devnames devnames[] = {
731 .nexus_name = "t4nex",
732 .ifnet_name = "cxgbe",
733 .vi_ifnet_name = "vcxgbe",
734 .pf03_drv_name = "t4iov",
735 .vf_nexus_name = "t4vf",
736 .vf_ifnet_name = "cxgbev"
738 .nexus_name = "t5nex",
740 .vi_ifnet_name = "vcxl",
741 .pf03_drv_name = "t5iov",
742 .vf_nexus_name = "t5vf",
743 .vf_ifnet_name = "cxlv"
745 .nexus_name = "t6nex",
747 .vi_ifnet_name = "vcc",
748 .pf03_drv_name = "t6iov",
749 .vf_nexus_name = "t6vf",
750 .vf_ifnet_name = "ccv"
755 t4_init_devnames(struct adapter *sc)
760 if (id >= CHELSIO_T4 && id - CHELSIO_T4 < nitems(devnames))
761 sc->names = &devnames[id - CHELSIO_T4];
763 device_printf(sc->dev, "chip id %d is not supported.\n", id);
769 t4_attach(device_t dev)
772 int rc = 0, i, j, n10g, n1g, rqidx, tqidx;
773 struct make_dev_args mda;
774 struct intrs_and_queues iaq;
778 int ofld_rqidx, ofld_tqidx;
781 int nm_rqidx, nm_tqidx;
785 sc = device_get_softc(dev);
787 TUNABLE_INT_FETCH("hw.cxgbe.dflags", &sc->debug_flags);
789 if ((pci_get_device(dev) & 0xff00) == 0x5400)
790 t5_attribute_workaround(dev);
791 pci_enable_busmaster(dev);
792 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
795 pci_set_max_read_req(dev, 4096);
796 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
797 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
798 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
800 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
803 sc->sge_gts_reg = MYPF_REG(A_SGE_PF_GTS);
804 sc->sge_kdoorbell_reg = MYPF_REG(A_SGE_PF_KDOORBELL);
806 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
807 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
808 device_get_nameunit(dev));
810 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
811 device_get_nameunit(dev));
812 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
815 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
816 TAILQ_INIT(&sc->sfl);
817 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
819 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
821 rc = t4_map_bars_0_and_4(sc);
823 goto done; /* error message displayed already */
825 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
827 /* Prepare the adapter for operation. */
828 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
829 rc = -t4_prep_adapter(sc, buf);
832 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
837 * This is the real PF# to which we're attaching. Works from within PCI
838 * passthrough environments too, where pci_get_function() could return a
839 * different PF# depending on the passthrough configuration. We need to
840 * use the real PF# in all our communication with the firmware.
842 j = t4_read_reg(sc, A_PL_WHOAMI);
843 sc->pf = chip_id(sc) <= CHELSIO_T5 ? G_SOURCEPF(j) : G_T6_SOURCEPF(j);
846 t4_init_devnames(sc);
847 if (sc->names == NULL) {
849 goto done; /* error message displayed already */
853 * Do this really early, with the memory windows set up even before the
854 * character device. The userland tool's register i/o and mem read
855 * will work even in "recovery mode".
858 if (t4_init_devlog_params(sc, 0) == 0)
859 fixup_devlog_params(sc);
860 make_dev_args_init(&mda);
861 mda.mda_devsw = &t4_cdevsw;
862 mda.mda_uid = UID_ROOT;
863 mda.mda_gid = GID_WHEEL;
865 mda.mda_si_drv1 = sc;
866 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
868 device_printf(dev, "failed to create nexus char device: %d.\n",
871 /* Go no further if recovery mode has been requested. */
872 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
873 device_printf(dev, "recovery mode.\n");
877 #if defined(__i386__)
878 if ((cpu_feature & CPUID_CX8) == 0) {
879 device_printf(dev, "64 bit atomics not available.\n");
885 /* Prepare the firmware for operation */
886 rc = prep_firmware(sc);
888 goto done; /* error message displayed already */
890 rc = get_params__post_init(sc);
892 goto done; /* error message displayed already */
894 rc = set_params__post_init(sc);
896 goto done; /* error message displayed already */
898 rc = t4_map_bar_2(sc);
900 goto done; /* error message displayed already */
902 rc = t4_create_dma_tag(sc);
904 goto done; /* error message displayed already */
907 * Number of VIs to create per-port. The first VI is the "main" regular
908 * VI for the port. The rest are additional virtual interfaces on the
909 * same physical port. Note that the main VI does not have native
910 * netmap support but the extra VIs do.
912 * Limit the number of VIs per port to the number of available
913 * MAC addresses per port.
916 num_vis = t4_num_vis;
919 if (num_vis > nitems(vi_mac_funcs)) {
920 num_vis = nitems(vi_mac_funcs);
921 device_printf(dev, "Number of VIs limited to %d\n", num_vis);
925 * First pass over all the ports - allocate VIs and initialize some
926 * basic parameters like mac address, port type, etc. We also figure
927 * out whether a port is 10G or 1G and use that information when
928 * calculating how many interrupts to attempt to allocate.
931 for_each_port(sc, i) {
932 struct port_info *pi;
933 struct link_config *lc;
935 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
938 /* These must be set before t4_port_init */
942 * XXX: vi[0] is special so we can't delay this allocation until
943 * pi->nvi's final value is known.
945 pi->vi = malloc(sizeof(struct vi_info) * num_vis, M_CXGBE,
949 * Allocate the "main" VI and initialize parameters
952 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
954 device_printf(dev, "unable to initialize port %d: %d\n",
956 free(pi->vi, M_CXGBE);
963 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX);
964 lc->requested_fc |= t4_pause_settings;
966 lc->requested_fec = t4_fec &
967 G_FW_PORT_CAP_FEC(lc->supported);
969 if (lc->supported & FW_PORT_CAP_ANEG && t4_autoneg != -1) {
970 lc->autoneg = t4_autoneg ? AUTONEG_ENABLE :
974 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
976 device_printf(dev, "port %d l1cfg failed: %d\n", i, rc);
977 free(pi->vi, M_CXGBE);
983 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
984 device_get_nameunit(dev), i);
985 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
986 sc->chan_map[pi->tx_chan] = i;
988 pi->tc = malloc(sizeof(struct tx_sched_class) *
989 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
991 if (port_top_speed(pi) >= 10) {
997 pi->dev = device_add_child(dev, sc->names->ifnet_name, -1);
998 if (pi->dev == NULL) {
1000 "failed to add device for port %d.\n", i);
1004 pi->vi[0].dev = pi->dev;
1005 device_set_softc(pi->dev, pi);
1009 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
1011 rc = cfg_itype_and_nqueues(sc, n10g, n1g, num_vis, &iaq);
1013 goto done; /* error message displayed already */
1014 if (iaq.nrxq_vi + iaq.nofldrxq_vi + iaq.nnmrxq_vi == 0)
1017 sc->intr_type = iaq.intr_type;
1018 sc->intr_count = iaq.nirq;
1021 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
1022 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
1024 s->nrxq += (n10g + n1g) * (num_vis - 1) * iaq.nrxq_vi;
1025 s->ntxq += (n10g + n1g) * (num_vis - 1) * iaq.ntxq_vi;
1027 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
1028 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
1029 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
1031 if (is_offload(sc)) {
1032 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g;
1033 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g;
1035 s->nofldrxq += (n10g + n1g) * (num_vis - 1) *
1037 s->nofldtxq += (n10g + n1g) * (num_vis - 1) *
1040 s->neq += s->nofldtxq + s->nofldrxq;
1041 s->niq += s->nofldrxq;
1043 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
1044 M_CXGBE, M_ZERO | M_WAITOK);
1045 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
1046 M_CXGBE, M_ZERO | M_WAITOK);
1051 s->nnmrxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmrxq_vi;
1052 s->nnmtxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmtxq_vi;
1054 s->neq += s->nnmtxq + s->nnmrxq;
1055 s->niq += s->nnmrxq;
1057 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
1058 M_CXGBE, M_ZERO | M_WAITOK);
1059 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
1060 M_CXGBE, M_ZERO | M_WAITOK);
1063 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE,
1065 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
1067 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
1069 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
1071 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
1074 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
1077 t4_init_l2t(sc, M_WAITOK);
1080 * Second pass over the ports. This time we know the number of rx and
1081 * tx queues that each port should get.
1085 ofld_rqidx = ofld_tqidx = 0;
1088 nm_rqidx = nm_tqidx = 0;
1090 for_each_port(sc, i) {
1091 struct port_info *pi = sc->port[i];
1098 for_each_vi(pi, j, vi) {
1100 vi->qsize_rxq = t4_qsize_rxq;
1101 vi->qsize_txq = t4_qsize_txq;
1103 vi->first_rxq = rqidx;
1104 vi->first_txq = tqidx;
1105 if (port_top_speed(pi) >= 10) {
1106 vi->tmr_idx = t4_tmr_idx_10g;
1107 vi->pktc_idx = t4_pktc_idx_10g;
1108 vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
1109 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi;
1110 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi;
1112 vi->tmr_idx = t4_tmr_idx_1g;
1113 vi->pktc_idx = t4_pktc_idx_1g;
1114 vi->flags |= iaq.intr_flags_1g & INTR_RXQ;
1115 vi->nrxq = j == 0 ? iaq.nrxq1g : iaq.nrxq_vi;
1116 vi->ntxq = j == 0 ? iaq.ntxq1g : iaq.ntxq_vi;
1121 if (j == 0 && vi->ntxq > 1)
1122 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0;
1124 vi->rsrv_noflowq = 0;
1127 vi->first_ofld_rxq = ofld_rqidx;
1128 vi->first_ofld_txq = ofld_tqidx;
1129 if (port_top_speed(pi) >= 10) {
1130 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ;
1131 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g :
1133 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g :
1136 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ;
1137 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g :
1139 vi->nofldtxq = j == 0 ? iaq.nofldtxq1g :
1142 ofld_rqidx += vi->nofldrxq;
1143 ofld_tqidx += vi->nofldtxq;
1147 vi->first_nm_rxq = nm_rqidx;
1148 vi->first_nm_txq = nm_tqidx;
1149 vi->nnmrxq = iaq.nnmrxq_vi;
1150 vi->nnmtxq = iaq.nnmtxq_vi;
1151 nm_rqidx += vi->nnmrxq;
1152 nm_tqidx += vi->nnmtxq;
1158 rc = t4_setup_intr_handlers(sc);
1161 "failed to setup interrupt handlers: %d\n", rc);
1165 rc = bus_generic_attach(dev);
1168 "failed to attach all child ports: %d\n", rc);
1173 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1174 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1175 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1176 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1177 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1182 if (rc != 0 && sc->cdev) {
1183 /* cdev was created and so cxgbetool works; recover that way. */
1185 "error during attach, adapter is now in recovery mode.\n");
1190 t4_detach_common(dev);
1201 t4_detach(device_t dev)
1205 sc = device_get_softc(dev);
1207 return (t4_detach_common(dev));
1211 t4_detach_common(device_t dev)
1214 struct port_info *pi;
1217 sc = device_get_softc(dev);
1219 if (sc->flags & FULL_INIT_DONE) {
1220 if (!(sc->flags & IS_VF))
1221 t4_intr_disable(sc);
1225 destroy_dev(sc->cdev);
1229 if (device_is_attached(dev)) {
1230 rc = bus_generic_detach(dev);
1233 "failed to detach child devices: %d\n", rc);
1238 for (i = 0; i < sc->intr_count; i++)
1239 t4_free_irq(sc, &sc->irq[i]);
1241 for (i = 0; i < MAX_NPORTS; i++) {
1244 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1246 device_delete_child(dev, pi->dev);
1248 mtx_destroy(&pi->pi_lock);
1249 free(pi->vi, M_CXGBE);
1250 free(pi->tc, M_CXGBE);
1255 if (sc->flags & FULL_INIT_DONE)
1256 adapter_full_uninit(sc);
1258 if ((sc->flags & (IS_VF | FW_OK)) == FW_OK)
1259 t4_fw_bye(sc, sc->mbox);
1261 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1262 pci_release_msi(dev);
1265 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1269 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1273 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1277 t4_free_l2t(sc->l2t);
1280 free(sc->sge.ofld_rxq, M_CXGBE);
1281 free(sc->sge.ofld_txq, M_CXGBE);
1284 free(sc->sge.nm_rxq, M_CXGBE);
1285 free(sc->sge.nm_txq, M_CXGBE);
1287 free(sc->irq, M_CXGBE);
1288 free(sc->sge.rxq, M_CXGBE);
1289 free(sc->sge.txq, M_CXGBE);
1290 free(sc->sge.ctrlq, M_CXGBE);
1291 free(sc->sge.iqmap, M_CXGBE);
1292 free(sc->sge.eqmap, M_CXGBE);
1293 free(sc->tids.ftid_tab, M_CXGBE);
1294 t4_destroy_dma_tag(sc);
1295 if (mtx_initialized(&sc->sc_lock)) {
1296 sx_xlock(&t4_list_lock);
1297 SLIST_REMOVE(&t4_list, sc, adapter, link);
1298 sx_xunlock(&t4_list_lock);
1299 mtx_destroy(&sc->sc_lock);
1302 callout_drain(&sc->sfl_callout);
1303 if (mtx_initialized(&sc->tids.ftid_lock))
1304 mtx_destroy(&sc->tids.ftid_lock);
1305 if (mtx_initialized(&sc->sfl_lock))
1306 mtx_destroy(&sc->sfl_lock);
1307 if (mtx_initialized(&sc->ifp_lock))
1308 mtx_destroy(&sc->ifp_lock);
1309 if (mtx_initialized(&sc->reg_lock))
1310 mtx_destroy(&sc->reg_lock);
1312 for (i = 0; i < NUM_MEMWIN; i++) {
1313 struct memwin *mw = &sc->memwin[i];
1315 if (rw_initialized(&mw->mw_lock))
1316 rw_destroy(&mw->mw_lock);
1319 bzero(sc, sizeof(*sc));
1325 cxgbe_probe(device_t dev)
1328 struct port_info *pi = device_get_softc(dev);
1330 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1331 device_set_desc_copy(dev, buf);
1333 return (BUS_PROBE_DEFAULT);
1336 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1337 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1338 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1339 #define T4_CAP_ENABLE (T4_CAP)
1342 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1347 vi->xact_addr_filt = -1;
1348 callout_init(&vi->tick, 1);
1350 /* Allocate an ifnet and set it up */
1351 ifp = if_alloc(IFT_ETHER);
1353 device_printf(dev, "Cannot allocate ifnet\n");
1359 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1360 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1362 ifp->if_init = cxgbe_init;
1363 ifp->if_ioctl = cxgbe_ioctl;
1364 ifp->if_transmit = cxgbe_transmit;
1365 ifp->if_qflush = cxgbe_qflush;
1367 ifp->if_capabilities = T4_CAP;
1369 if (vi->nofldrxq != 0)
1370 ifp->if_capabilities |= IFCAP_TOE;
1372 ifp->if_capenable = T4_CAP_ENABLE;
1373 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1374 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1376 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1377 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS;
1378 ifp->if_hw_tsomaxsegsize = 65536;
1380 /* Initialize ifmedia for this VI */
1381 ifmedia_init(&vi->media, IFM_IMASK, cxgbe_media_change,
1382 cxgbe_media_status);
1383 build_medialist(vi->pi, &vi->media);
1385 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1386 EVENTHANDLER_PRI_ANY);
1388 ether_ifattach(ifp, vi->hw_addr);
1390 if (vi->nnmrxq != 0)
1391 cxgbe_nm_attach(vi);
1393 sb = sbuf_new_auto();
1394 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1396 if (ifp->if_capabilities & IFCAP_TOE)
1397 sbuf_printf(sb, "; %d txq, %d rxq (TOE)",
1398 vi->nofldtxq, vi->nofldrxq);
1401 if (ifp->if_capabilities & IFCAP_NETMAP)
1402 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1403 vi->nnmtxq, vi->nnmrxq);
1406 device_printf(dev, "%s\n", sbuf_data(sb));
1415 cxgbe_attach(device_t dev)
1417 struct port_info *pi = device_get_softc(dev);
1418 struct adapter *sc = pi->adapter;
1422 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1424 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1428 for_each_vi(pi, i, vi) {
1431 vi->dev = device_add_child(dev, sc->names->vi_ifnet_name, -1);
1432 if (vi->dev == NULL) {
1433 device_printf(dev, "failed to add VI %d\n", i);
1436 device_set_softc(vi->dev, vi);
1441 bus_generic_attach(dev);
1447 cxgbe_vi_detach(struct vi_info *vi)
1449 struct ifnet *ifp = vi->ifp;
1451 ether_ifdetach(ifp);
1454 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c);
1456 /* Let detach proceed even if these fail. */
1458 if (ifp->if_capabilities & IFCAP_NETMAP)
1459 cxgbe_nm_detach(vi);
1461 cxgbe_uninit_synchronized(vi);
1462 callout_drain(&vi->tick);
1465 ifmedia_removeall(&vi->media);
1471 cxgbe_detach(device_t dev)
1473 struct port_info *pi = device_get_softc(dev);
1474 struct adapter *sc = pi->adapter;
1477 /* Detach the extra VIs first. */
1478 rc = bus_generic_detach(dev);
1481 device_delete_children(dev);
1483 doom_vi(sc, &pi->vi[0]);
1485 if (pi->flags & HAS_TRACEQ) {
1486 sc->traceq = -1; /* cloner should not create ifnet */
1487 t4_tracer_port_detach(sc);
1490 cxgbe_vi_detach(&pi->vi[0]);
1491 callout_drain(&pi->tick);
1493 end_synchronized_op(sc, 0);
1499 cxgbe_init(void *arg)
1501 struct vi_info *vi = arg;
1502 struct adapter *sc = vi->pi->adapter;
1504 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1506 cxgbe_init_synchronized(vi);
1507 end_synchronized_op(sc, 0);
1511 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1513 int rc = 0, mtu, flags, can_sleep;
1514 struct vi_info *vi = ifp->if_softc;
1515 struct adapter *sc = vi->pi->adapter;
1516 struct ifreq *ifr = (struct ifreq *)data;
1522 if (mtu < ETHERMIN || mtu > MAX_MTU)
1525 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1529 if (vi->flags & VI_INIT_DONE) {
1530 t4_update_fl_bufsize(ifp);
1531 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1532 rc = update_mac_settings(ifp, XGMAC_MTU);
1534 end_synchronized_op(sc, 0);
1540 rc = begin_synchronized_op(sc, vi,
1541 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg");
1545 if (ifp->if_flags & IFF_UP) {
1546 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1547 flags = vi->if_flags;
1548 if ((ifp->if_flags ^ flags) &
1549 (IFF_PROMISC | IFF_ALLMULTI)) {
1550 if (can_sleep == 1) {
1551 end_synchronized_op(sc, 0);
1555 rc = update_mac_settings(ifp,
1556 XGMAC_PROMISC | XGMAC_ALLMULTI);
1559 if (can_sleep == 0) {
1560 end_synchronized_op(sc, LOCK_HELD);
1564 rc = cxgbe_init_synchronized(vi);
1566 vi->if_flags = ifp->if_flags;
1567 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1568 if (can_sleep == 0) {
1569 end_synchronized_op(sc, LOCK_HELD);
1573 rc = cxgbe_uninit_synchronized(vi);
1575 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD);
1579 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1580 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi");
1583 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1584 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1585 end_synchronized_op(sc, LOCK_HELD);
1589 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1593 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1594 if (mask & IFCAP_TXCSUM) {
1595 ifp->if_capenable ^= IFCAP_TXCSUM;
1596 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1598 if (IFCAP_TSO4 & ifp->if_capenable &&
1599 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1600 ifp->if_capenable &= ~IFCAP_TSO4;
1602 "tso4 disabled due to -txcsum.\n");
1605 if (mask & IFCAP_TXCSUM_IPV6) {
1606 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1607 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1609 if (IFCAP_TSO6 & ifp->if_capenable &&
1610 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1611 ifp->if_capenable &= ~IFCAP_TSO6;
1613 "tso6 disabled due to -txcsum6.\n");
1616 if (mask & IFCAP_RXCSUM)
1617 ifp->if_capenable ^= IFCAP_RXCSUM;
1618 if (mask & IFCAP_RXCSUM_IPV6)
1619 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1622 * Note that we leave CSUM_TSO alone (it is always set). The
1623 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1624 * sending a TSO request our way, so it's sufficient to toggle
1627 if (mask & IFCAP_TSO4) {
1628 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1629 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1630 if_printf(ifp, "enable txcsum first.\n");
1634 ifp->if_capenable ^= IFCAP_TSO4;
1636 if (mask & IFCAP_TSO6) {
1637 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1638 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1639 if_printf(ifp, "enable txcsum6 first.\n");
1643 ifp->if_capenable ^= IFCAP_TSO6;
1645 if (mask & IFCAP_LRO) {
1646 #if defined(INET) || defined(INET6)
1648 struct sge_rxq *rxq;
1650 ifp->if_capenable ^= IFCAP_LRO;
1651 for_each_rxq(vi, i, rxq) {
1652 if (ifp->if_capenable & IFCAP_LRO)
1653 rxq->iq.flags |= IQ_LRO_ENABLED;
1655 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1660 if (mask & IFCAP_TOE) {
1661 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1663 rc = toe_capability(vi, enable);
1667 ifp->if_capenable ^= mask;
1670 if (mask & IFCAP_VLAN_HWTAGGING) {
1671 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1672 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1673 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1675 if (mask & IFCAP_VLAN_MTU) {
1676 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1678 /* Need to find out how to disable auto-mtu-inflation */
1680 if (mask & IFCAP_VLAN_HWTSO)
1681 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1682 if (mask & IFCAP_VLAN_HWCSUM)
1683 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1685 #ifdef VLAN_CAPABILITIES
1686 VLAN_CAPABILITIES(ifp);
1689 end_synchronized_op(sc, 0);
1695 ifmedia_ioctl(ifp, ifr, &vi->media, cmd);
1699 struct ifi2creq i2c;
1701 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
1704 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
1708 if (i2c.len > sizeof(i2c.data)) {
1712 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
1715 rc = -t4_i2c_rd(sc, sc->mbox, vi->pi->port_id, i2c.dev_addr,
1716 i2c.offset, i2c.len, &i2c.data[0]);
1717 end_synchronized_op(sc, 0);
1719 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
1724 rc = ether_ioctl(ifp, cmd, data);
1731 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1733 struct vi_info *vi = ifp->if_softc;
1734 struct port_info *pi = vi->pi;
1735 struct adapter *sc = pi->adapter;
1736 struct sge_txq *txq;
1741 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
1743 if (__predict_false(pi->link_cfg.link_ok == 0)) {
1748 rc = parse_pkt(sc, &m);
1749 if (__predict_false(rc != 0)) {
1750 MPASS(m == NULL); /* was freed already */
1751 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
1756 txq = &sc->sge.txq[vi->first_txq];
1757 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
1758 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
1762 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
1763 if (__predict_false(rc != 0))
1770 cxgbe_qflush(struct ifnet *ifp)
1772 struct vi_info *vi = ifp->if_softc;
1773 struct sge_txq *txq;
1776 /* queues do not exist if !VI_INIT_DONE. */
1777 if (vi->flags & VI_INIT_DONE) {
1778 for_each_txq(vi, i, txq) {
1780 txq->eq.flags &= ~EQ_ENABLED;
1782 while (!mp_ring_is_idle(txq->r)) {
1783 mp_ring_check_drainage(txq->r, 0);
1792 cxgbe_media_change(struct ifnet *ifp)
1794 struct vi_info *vi = ifp->if_softc;
1796 device_printf(vi->dev, "%s unimplemented.\n", __func__);
1798 return (EOPNOTSUPP);
1802 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1804 struct vi_info *vi = ifp->if_softc;
1805 struct port_info *pi = vi->pi;
1806 struct ifmedia_entry *cur;
1807 int speed = pi->link_cfg.speed;
1809 cur = vi->media.ifm_cur;
1811 ifmr->ifm_status = IFM_AVALID;
1812 if (!pi->link_cfg.link_ok)
1815 ifmr->ifm_status |= IFM_ACTIVE;
1817 /* active and current will differ iff current media is autoselect. */
1818 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO)
1821 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
1823 ifmr->ifm_active |= IFM_10G_T;
1824 else if (speed == 1000)
1825 ifmr->ifm_active |= IFM_1000_T;
1826 else if (speed == 100)
1827 ifmr->ifm_active |= IFM_100_TX;
1828 else if (speed == 10)
1829 ifmr->ifm_active |= IFM_10_T;
1831 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__,
1836 vcxgbe_probe(device_t dev)
1839 struct vi_info *vi = device_get_softc(dev);
1841 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
1843 device_set_desc_copy(dev, buf);
1845 return (BUS_PROBE_DEFAULT);
1849 vcxgbe_attach(device_t dev)
1852 struct port_info *pi;
1854 int func, index, rc;
1857 vi = device_get_softc(dev);
1861 index = vi - pi->vi;
1862 KASSERT(index < nitems(vi_mac_funcs),
1863 ("%s: VI %s doesn't have a MAC func", __func__,
1864 device_get_nameunit(dev)));
1865 func = vi_mac_funcs[index];
1866 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
1867 vi->hw_addr, &vi->rss_size, func, 0);
1869 device_printf(dev, "Failed to allocate virtual interface "
1870 "for port %d: %d\n", pi->port_id, -rc);
1874 if (chip_id(sc) <= CHELSIO_T5)
1875 vi->smt_idx = (rc & 0x7f) << 1;
1877 vi->smt_idx = (rc & 0x7f);
1879 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1880 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
1881 V_FW_PARAMS_PARAM_YZ(vi->viid);
1882 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
1884 vi->rss_base = 0xffff;
1886 /* MPASS((val >> 16) == rss_size); */
1887 vi->rss_base = val & 0xffff;
1890 rc = cxgbe_vi_attach(dev, vi);
1892 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1899 vcxgbe_detach(device_t dev)
1904 vi = device_get_softc(dev);
1905 sc = vi->pi->adapter;
1909 cxgbe_vi_detach(vi);
1910 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1912 end_synchronized_op(sc, 0);
1918 t4_fatal_err(struct adapter *sc)
1920 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
1921 t4_intr_disable(sc);
1922 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
1923 device_get_nameunit(sc->dev));
1927 t4_add_adapter(struct adapter *sc)
1929 sx_xlock(&t4_list_lock);
1930 SLIST_INSERT_HEAD(&t4_list, sc, link);
1931 sx_xunlock(&t4_list_lock);
1935 t4_map_bars_0_and_4(struct adapter *sc)
1937 sc->regs_rid = PCIR_BAR(0);
1938 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1939 &sc->regs_rid, RF_ACTIVE);
1940 if (sc->regs_res == NULL) {
1941 device_printf(sc->dev, "cannot map registers.\n");
1944 sc->bt = rman_get_bustag(sc->regs_res);
1945 sc->bh = rman_get_bushandle(sc->regs_res);
1946 sc->mmio_len = rman_get_size(sc->regs_res);
1947 setbit(&sc->doorbells, DOORBELL_KDB);
1949 sc->msix_rid = PCIR_BAR(4);
1950 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1951 &sc->msix_rid, RF_ACTIVE);
1952 if (sc->msix_res == NULL) {
1953 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
1961 t4_map_bar_2(struct adapter *sc)
1965 * T4: only iWARP driver uses the userspace doorbells. There is no need
1966 * to map it if RDMA is disabled.
1968 if (is_t4(sc) && sc->rdmacaps == 0)
1971 sc->udbs_rid = PCIR_BAR(2);
1972 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1973 &sc->udbs_rid, RF_ACTIVE);
1974 if (sc->udbs_res == NULL) {
1975 device_printf(sc->dev, "cannot map doorbell BAR.\n");
1978 sc->udbs_base = rman_get_virtual(sc->udbs_res);
1980 if (chip_id(sc) >= CHELSIO_T5) {
1981 setbit(&sc->doorbells, DOORBELL_UDB);
1982 #if defined(__i386__) || defined(__amd64__)
1983 if (t5_write_combine) {
1987 * Enable write combining on BAR2. This is the
1988 * userspace doorbell BAR and is split into 128B
1989 * (UDBS_SEG_SIZE) doorbell regions, each associated
1990 * with an egress queue. The first 64B has the doorbell
1991 * and the second 64B can be used to submit a tx work
1992 * request with an implicit doorbell.
1995 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
1996 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
1998 clrbit(&sc->doorbells, DOORBELL_UDB);
1999 setbit(&sc->doorbells, DOORBELL_WCWR);
2000 setbit(&sc->doorbells, DOORBELL_UDBWC);
2002 device_printf(sc->dev,
2003 "couldn't enable write combining: %d\n",
2007 mode = is_t5(sc) ? V_STATMODE(0) : V_T6_STATMODE(0);
2008 t4_write_reg(sc, A_SGE_STAT_CFG,
2009 V_STATSOURCE_T5(7) | mode);
2017 struct memwin_init {
2022 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
2023 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2024 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2025 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
2028 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
2029 { MEMWIN0_BASE, MEMWIN0_APERTURE },
2030 { MEMWIN1_BASE, MEMWIN1_APERTURE },
2031 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
2035 setup_memwin(struct adapter *sc)
2037 const struct memwin_init *mw_init;
2044 * Read low 32b of bar0 indirectly via the hardware backdoor
2045 * mechanism. Works from within PCI passthrough environments
2046 * too, where rman_get_start() can return a different value. We
2047 * need to program the T4 memory window decoders with the actual
2048 * addresses that will be coming across the PCIe link.
2050 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
2051 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
2053 mw_init = &t4_memwin[0];
2055 /* T5+ use the relative offset inside the PCIe BAR */
2058 mw_init = &t5_memwin[0];
2061 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
2062 rw_init(&mw->mw_lock, "memory window access");
2063 mw->mw_base = mw_init->base;
2064 mw->mw_aperture = mw_init->aperture;
2067 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
2068 (mw->mw_base + bar0) | V_BIR(0) |
2069 V_WINDOW(ilog2(mw->mw_aperture) - 10));
2070 rw_wlock(&mw->mw_lock);
2071 position_memwin(sc, i, 0);
2072 rw_wunlock(&mw->mw_lock);
2076 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
2080 * Positions the memory window at the given address in the card's address space.
2081 * There are some alignment requirements and the actual position may be at an
2082 * address prior to the requested address. mw->mw_curpos always has the actual
2083 * position of the window.
2086 position_memwin(struct adapter *sc, int idx, uint32_t addr)
2092 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2093 mw = &sc->memwin[idx];
2094 rw_assert(&mw->mw_lock, RA_WLOCKED);
2098 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
2100 pf = V_PFNUM(sc->pf);
2101 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
2103 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
2104 t4_write_reg(sc, reg, mw->mw_curpos | pf);
2105 t4_read_reg(sc, reg); /* flush */
2109 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2115 MPASS(idx >= 0 && idx < NUM_MEMWIN);
2117 /* Memory can only be accessed in naturally aligned 4 byte units */
2118 if (addr & 3 || len & 3 || len <= 0)
2121 mw = &sc->memwin[idx];
2123 rw_rlock(&mw->mw_lock);
2124 mw_end = mw->mw_curpos + mw->mw_aperture;
2125 if (addr >= mw_end || addr < mw->mw_curpos) {
2126 /* Will need to reposition the window */
2127 if (!rw_try_upgrade(&mw->mw_lock)) {
2128 rw_runlock(&mw->mw_lock);
2129 rw_wlock(&mw->mw_lock);
2131 rw_assert(&mw->mw_lock, RA_WLOCKED);
2132 position_memwin(sc, idx, addr);
2133 rw_downgrade(&mw->mw_lock);
2134 mw_end = mw->mw_curpos + mw->mw_aperture;
2136 rw_assert(&mw->mw_lock, RA_RLOCKED);
2137 while (addr < mw_end && len > 0) {
2139 v = t4_read_reg(sc, mw->mw_base + addr -
2141 *val++ = le32toh(v);
2144 t4_write_reg(sc, mw->mw_base + addr -
2145 mw->mw_curpos, htole32(v));;
2150 rw_runlock(&mw->mw_lock);
2157 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2161 return (rw_via_memwin(sc, idx, addr, val, len, 0));
2165 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
2166 const uint32_t *val, int len)
2169 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
2173 t4_range_cmp(const void *a, const void *b)
2175 return ((const struct t4_range *)a)->start -
2176 ((const struct t4_range *)b)->start;
2180 * Verify that the memory range specified by the addr/len pair is valid within
2181 * the card's address space.
2184 validate_mem_range(struct adapter *sc, uint32_t addr, int len)
2186 struct t4_range mem_ranges[4], *r, *next;
2187 uint32_t em, addr_len;
2188 int i, n, remaining;
2190 /* Memory can only be accessed in naturally aligned 4 byte units */
2191 if (addr & 3 || len & 3 || len <= 0)
2194 /* Enabled memories */
2195 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2199 bzero(r, sizeof(mem_ranges));
2200 if (em & F_EDRAM0_ENABLE) {
2201 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2202 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2204 r->start = G_EDRAM0_BASE(addr_len) << 20;
2205 if (addr >= r->start &&
2206 addr + len <= r->start + r->size)
2212 if (em & F_EDRAM1_ENABLE) {
2213 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2214 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2216 r->start = G_EDRAM1_BASE(addr_len) << 20;
2217 if (addr >= r->start &&
2218 addr + len <= r->start + r->size)
2224 if (em & F_EXT_MEM_ENABLE) {
2225 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2226 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2228 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2229 if (addr >= r->start &&
2230 addr + len <= r->start + r->size)
2236 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2237 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2238 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2240 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2241 if (addr >= r->start &&
2242 addr + len <= r->start + r->size)
2248 MPASS(n <= nitems(mem_ranges));
2251 /* Sort and merge the ranges. */
2252 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2254 /* Start from index 0 and examine the next n - 1 entries. */
2256 for (remaining = n - 1; remaining > 0; remaining--, r++) {
2258 MPASS(r->size > 0); /* r is a valid entry. */
2260 MPASS(next->size > 0); /* and so is the next one. */
2262 while (r->start + r->size >= next->start) {
2263 /* Merge the next one into the current entry. */
2264 r->size = max(r->start + r->size,
2265 next->start + next->size) - r->start;
2266 n--; /* One fewer entry in total. */
2267 if (--remaining == 0)
2268 goto done; /* short circuit */
2271 if (next != r + 1) {
2273 * Some entries were merged into r and next
2274 * points to the first valid entry that couldn't
2277 MPASS(next->size > 0); /* must be valid */
2278 memcpy(r + 1, next, remaining * sizeof(*r));
2281 * This so that the foo->size assertion in the
2282 * next iteration of the loop do the right
2283 * thing for entries that were pulled up and are
2286 MPASS(n < nitems(mem_ranges));
2287 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
2288 sizeof(struct t4_range));
2293 /* Done merging the ranges. */
2296 for (i = 0; i < n; i++, r++) {
2297 if (addr >= r->start &&
2298 addr + len <= r->start + r->size)
2307 fwmtype_to_hwmtype(int mtype)
2311 case FW_MEMTYPE_EDC0:
2313 case FW_MEMTYPE_EDC1:
2315 case FW_MEMTYPE_EXTMEM:
2317 case FW_MEMTYPE_EXTMEM1:
2320 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
2325 * Verify that the memory range specified by the memtype/offset/len pair is
2326 * valid and lies entirely within the memtype specified. The global address of
2327 * the start of the range is returned in addr.
2330 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len,
2333 uint32_t em, addr_len, maddr;
2335 /* Memory can only be accessed in naturally aligned 4 byte units */
2336 if (off & 3 || len & 3 || len == 0)
2339 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2340 switch (fwmtype_to_hwmtype(mtype)) {
2342 if (!(em & F_EDRAM0_ENABLE))
2344 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2345 maddr = G_EDRAM0_BASE(addr_len) << 20;
2348 if (!(em & F_EDRAM1_ENABLE))
2350 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2351 maddr = G_EDRAM1_BASE(addr_len) << 20;
2354 if (!(em & F_EXT_MEM_ENABLE))
2356 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2357 maddr = G_EXT_MEM_BASE(addr_len) << 20;
2360 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
2362 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2363 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
2369 *addr = maddr + off; /* global address */
2370 return (validate_mem_range(sc, *addr, len));
2374 fixup_devlog_params(struct adapter *sc)
2376 struct devlog_params *dparams = &sc->params.devlog;
2379 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
2380 dparams->size, &dparams->addr);
2386 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, int num_vis,
2387 struct intrs_and_queues *iaq)
2389 int rc, itype, navail, nrxq10g, nrxq1g, n;
2390 int nofldrxq10g = 0, nofldrxq1g = 0;
2392 bzero(iaq, sizeof(*iaq));
2394 iaq->ntxq10g = t4_ntxq10g;
2395 iaq->ntxq1g = t4_ntxq1g;
2396 iaq->ntxq_vi = t4_ntxq_vi;
2397 iaq->nrxq10g = nrxq10g = t4_nrxq10g;
2398 iaq->nrxq1g = nrxq1g = t4_nrxq1g;
2399 iaq->nrxq_vi = t4_nrxq_vi;
2400 iaq->rsrv_noflowq = t4_rsrv_noflowq;
2402 if (is_offload(sc)) {
2403 iaq->nofldtxq10g = t4_nofldtxq10g;
2404 iaq->nofldtxq1g = t4_nofldtxq1g;
2405 iaq->nofldtxq_vi = t4_nofldtxq_vi;
2406 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g;
2407 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g;
2408 iaq->nofldrxq_vi = t4_nofldrxq_vi;
2412 iaq->nnmtxq_vi = t4_nnmtxq_vi;
2413 iaq->nnmrxq_vi = t4_nnmrxq_vi;
2416 for (itype = INTR_MSIX; itype; itype >>= 1) {
2418 if ((itype & t4_intr_types) == 0)
2419 continue; /* not allowed */
2421 if (itype == INTR_MSIX)
2422 navail = pci_msix_count(sc->dev);
2423 else if (itype == INTR_MSI)
2424 navail = pci_msi_count(sc->dev);
2431 iaq->intr_type = itype;
2432 iaq->intr_flags_10g = 0;
2433 iaq->intr_flags_1g = 0;
2436 * Best option: an interrupt vector for errors, one for the
2437 * firmware event queue, and one for every rxq (NIC and TOE) of
2438 * every VI. The VIs that support netmap use the same
2439 * interrupts for the NIC rx queues and the netmap rx queues
2440 * because only one set of queues is active at a time.
2442 iaq->nirq = T4_EXTRA_INTR;
2443 iaq->nirq += n10g * (nrxq10g + nofldrxq10g);
2444 iaq->nirq += n1g * (nrxq1g + nofldrxq1g);
2445 iaq->nirq += (n10g + n1g) * (num_vis - 1) *
2446 max(iaq->nrxq_vi, iaq->nnmrxq_vi); /* See comment above. */
2447 iaq->nirq += (n10g + n1g) * (num_vis - 1) * iaq->nofldrxq_vi;
2448 if (iaq->nirq <= navail &&
2449 (itype != INTR_MSI || powerof2(iaq->nirq))) {
2450 iaq->intr_flags_10g = INTR_ALL;
2451 iaq->intr_flags_1g = INTR_ALL;
2455 /* Disable the VIs (and netmap) if there aren't enough intrs */
2457 device_printf(sc->dev, "virtual interfaces disabled "
2458 "because num_vis=%u with current settings "
2459 "(nrxq10g=%u, nrxq1g=%u, nofldrxq10g=%u, "
2460 "nofldrxq1g=%u, nrxq_vi=%u nofldrxq_vi=%u, "
2461 "nnmrxq_vi=%u) would need %u interrupts but "
2462 "only %u are available.\n", num_vis, nrxq10g,
2463 nrxq1g, nofldrxq10g, nofldrxq1g, iaq->nrxq_vi,
2464 iaq->nofldrxq_vi, iaq->nnmrxq_vi, iaq->nirq,
2467 iaq->ntxq_vi = iaq->nrxq_vi = 0;
2468 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
2469 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
2474 * Second best option: a vector for errors, one for the firmware
2475 * event queue, and vectors for either all the NIC rx queues or
2476 * all the TOE rx queues. The queues that don't get vectors
2477 * will forward their interrupts to those that do.
2479 iaq->nirq = T4_EXTRA_INTR;
2480 if (nrxq10g >= nofldrxq10g) {
2481 iaq->intr_flags_10g = INTR_RXQ;
2482 iaq->nirq += n10g * nrxq10g;
2484 iaq->intr_flags_10g = INTR_OFLD_RXQ;
2485 iaq->nirq += n10g * nofldrxq10g;
2487 if (nrxq1g >= nofldrxq1g) {
2488 iaq->intr_flags_1g = INTR_RXQ;
2489 iaq->nirq += n1g * nrxq1g;
2491 iaq->intr_flags_1g = INTR_OFLD_RXQ;
2492 iaq->nirq += n1g * nofldrxq1g;
2494 if (iaq->nirq <= navail &&
2495 (itype != INTR_MSI || powerof2(iaq->nirq)))
2499 * Next best option: an interrupt vector for errors, one for the
2500 * firmware event queue, and at least one per main-VI. At this
2501 * point we know we'll have to downsize nrxq and/or nofldrxq to
2502 * fit what's available to us.
2504 iaq->nirq = T4_EXTRA_INTR;
2505 iaq->nirq += n10g + n1g;
2506 if (iaq->nirq <= navail) {
2507 int leftover = navail - iaq->nirq;
2510 int target = max(nrxq10g, nofldrxq10g);
2512 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ?
2513 INTR_RXQ : INTR_OFLD_RXQ;
2516 while (n < target && leftover >= n10g) {
2521 iaq->nrxq10g = min(n, nrxq10g);
2523 iaq->nofldrxq10g = min(n, nofldrxq10g);
2528 int target = max(nrxq1g, nofldrxq1g);
2530 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ?
2531 INTR_RXQ : INTR_OFLD_RXQ;
2534 while (n < target && leftover >= n1g) {
2539 iaq->nrxq1g = min(n, nrxq1g);
2541 iaq->nofldrxq1g = min(n, nofldrxq1g);
2545 if (itype != INTR_MSI || powerof2(iaq->nirq))
2550 * Least desirable option: one interrupt vector for everything.
2552 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1;
2553 iaq->intr_flags_10g = iaq->intr_flags_1g = 0;
2556 iaq->nofldrxq10g = iaq->nofldrxq1g = 1;
2561 if (itype == INTR_MSIX)
2562 rc = pci_alloc_msix(sc->dev, &navail);
2563 else if (itype == INTR_MSI)
2564 rc = pci_alloc_msi(sc->dev, &navail);
2567 if (navail == iaq->nirq)
2571 * Didn't get the number requested. Use whatever number
2572 * the kernel is willing to allocate (it's in navail).
2574 device_printf(sc->dev, "fewer vectors than requested, "
2575 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
2576 itype, iaq->nirq, navail);
2577 pci_release_msi(sc->dev);
2581 device_printf(sc->dev,
2582 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
2583 itype, rc, iaq->nirq, navail);
2586 device_printf(sc->dev,
2587 "failed to find a usable interrupt type. "
2588 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
2589 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
2594 #define FW_VERSION(chip) ( \
2595 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
2596 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
2597 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
2598 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
2599 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
2605 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */
2609 .kld_name = "t4fw_cfg",
2610 .fw_mod_name = "t4fw",
2612 .chip = FW_HDR_CHIP_T4,
2613 .fw_ver = htobe32_const(FW_VERSION(T4)),
2614 .intfver_nic = FW_INTFVER(T4, NIC),
2615 .intfver_vnic = FW_INTFVER(T4, VNIC),
2616 .intfver_ofld = FW_INTFVER(T4, OFLD),
2617 .intfver_ri = FW_INTFVER(T4, RI),
2618 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
2619 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
2620 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
2621 .intfver_fcoe = FW_INTFVER(T4, FCOE),
2625 .kld_name = "t5fw_cfg",
2626 .fw_mod_name = "t5fw",
2628 .chip = FW_HDR_CHIP_T5,
2629 .fw_ver = htobe32_const(FW_VERSION(T5)),
2630 .intfver_nic = FW_INTFVER(T5, NIC),
2631 .intfver_vnic = FW_INTFVER(T5, VNIC),
2632 .intfver_ofld = FW_INTFVER(T5, OFLD),
2633 .intfver_ri = FW_INTFVER(T5, RI),
2634 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
2635 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2636 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
2637 .intfver_fcoe = FW_INTFVER(T5, FCOE),
2641 .kld_name = "t6fw_cfg",
2642 .fw_mod_name = "t6fw",
2644 .chip = FW_HDR_CHIP_T6,
2645 .fw_ver = htobe32_const(FW_VERSION(T6)),
2646 .intfver_nic = FW_INTFVER(T6, NIC),
2647 .intfver_vnic = FW_INTFVER(T6, VNIC),
2648 .intfver_ofld = FW_INTFVER(T6, OFLD),
2649 .intfver_ri = FW_INTFVER(T6, RI),
2650 .intfver_iscsipdu = FW_INTFVER(T6, ISCSIPDU),
2651 .intfver_iscsi = FW_INTFVER(T6, ISCSI),
2652 .intfver_fcoepdu = FW_INTFVER(T6, FCOEPDU),
2653 .intfver_fcoe = FW_INTFVER(T6, FCOE),
2658 static struct fw_info *
2659 find_fw_info(int chip)
2663 for (i = 0; i < nitems(fw_info); i++) {
2664 if (fw_info[i].chip == chip)
2665 return (&fw_info[i]);
2671 * Is the given firmware API compatible with the one the driver was compiled
2675 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
2678 /* short circuit if it's the exact same firmware version */
2679 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
2683 * XXX: Is this too conservative? Perhaps I should limit this to the
2684 * features that are supported in the driver.
2686 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
2687 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
2688 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
2689 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
2697 * The firmware in the KLD is usable, but should it be installed? This routine
2698 * explains itself in detail if it indicates the KLD firmware should be
2702 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
2706 if (!card_fw_usable) {
2707 reason = "incompatible or unusable";
2712 reason = "older than the version bundled with this driver";
2716 if (t4_fw_install == 2 && k != c) {
2717 reason = "different than the version bundled with this driver";
2724 if (t4_fw_install == 0) {
2725 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2726 "but the driver is prohibited from installing a different "
2727 "firmware on the card.\n",
2728 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2729 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
2734 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2735 "installing firmware %u.%u.%u.%u on card.\n",
2736 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2737 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
2738 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2739 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2744 * Establish contact with the firmware and determine if we are the master driver
2745 * or not, and whether we are responsible for chip initialization.
2748 prep_firmware(struct adapter *sc)
2750 const struct firmware *fw = NULL, *default_cfg;
2751 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
2752 enum dev_state state;
2753 struct fw_info *fw_info;
2754 struct fw_hdr *card_fw; /* fw on the card */
2755 const struct fw_hdr *kld_fw; /* fw in the KLD */
2756 const struct fw_hdr *drv_fw; /* fw header the driver was compiled
2759 /* Contact firmware. */
2760 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
2761 if (rc < 0 || state == DEV_STATE_ERR) {
2763 device_printf(sc->dev,
2764 "failed to connect to the firmware: %d, %d.\n", rc, state);
2769 sc->flags |= MASTER_PF;
2770 else if (state == DEV_STATE_UNINIT) {
2772 * We didn't get to be the master so we definitely won't be
2773 * configuring the chip. It's a bug if someone else hasn't
2774 * configured it already.
2776 device_printf(sc->dev, "couldn't be master(%d), "
2777 "device not already initialized either(%d).\n", rc, state);
2781 /* This is the firmware whose headers the driver was compiled against */
2782 fw_info = find_fw_info(chip_id(sc));
2783 if (fw_info == NULL) {
2784 device_printf(sc->dev,
2785 "unable to look up firmware information for chip %d.\n",
2789 drv_fw = &fw_info->fw_hdr;
2792 * The firmware KLD contains many modules. The KLD name is also the
2793 * name of the module that contains the default config file.
2795 default_cfg = firmware_get(fw_info->kld_name);
2797 /* Read the header of the firmware on the card */
2798 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
2799 rc = -t4_read_flash(sc, FLASH_FW_START,
2800 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
2802 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
2804 device_printf(sc->dev,
2805 "Unable to read card's firmware header: %d\n", rc);
2809 /* This is the firmware in the KLD */
2810 fw = firmware_get(fw_info->fw_mod_name);
2812 kld_fw = (const void *)fw->data;
2813 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
2819 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
2820 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
2822 * Common case: the firmware on the card is an exact match and
2823 * the KLD is an exact match too, or the KLD is
2824 * absent/incompatible. Note that t4_fw_install = 2 is ignored
2825 * here -- use cxgbetool loadfw if you want to reinstall the
2826 * same firmware as the one on the card.
2828 } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
2829 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
2830 be32toh(card_fw->fw_ver))) {
2832 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
2834 device_printf(sc->dev,
2835 "failed to install firmware: %d\n", rc);
2839 /* Installed successfully, update the cached header too. */
2840 memcpy(card_fw, kld_fw, sizeof(*card_fw));
2842 need_fw_reset = 0; /* already reset as part of load_fw */
2845 if (!card_fw_usable) {
2848 d = ntohl(drv_fw->fw_ver);
2849 c = ntohl(card_fw->fw_ver);
2850 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
2852 device_printf(sc->dev, "Cannot find a usable firmware: "
2853 "fw_install %d, chip state %d, "
2854 "driver compiled with %d.%d.%d.%d, "
2855 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
2856 t4_fw_install, state,
2857 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
2858 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
2859 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2860 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
2861 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2862 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2868 if (need_fw_reset &&
2869 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
2870 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
2871 if (rc != ETIMEDOUT && rc != EIO)
2872 t4_fw_bye(sc, sc->mbox);
2877 rc = get_params__pre_init(sc);
2879 goto done; /* error message displayed already */
2881 /* Partition adapter resources as specified in the config file. */
2882 if (state == DEV_STATE_UNINIT) {
2884 KASSERT(sc->flags & MASTER_PF,
2885 ("%s: trying to change chip settings when not master.",
2888 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
2890 goto done; /* error message displayed already */
2892 t4_tweak_chip_settings(sc);
2894 /* get basic stuff going */
2895 rc = -t4_fw_initialize(sc, sc->mbox);
2897 device_printf(sc->dev, "fw init failed: %d.\n", rc);
2901 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
2906 free(card_fw, M_CXGBE);
2908 firmware_put(fw, FIRMWARE_UNLOAD);
2909 if (default_cfg != NULL)
2910 firmware_put(default_cfg, FIRMWARE_UNLOAD);
2915 #define FW_PARAM_DEV(param) \
2916 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
2917 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
2918 #define FW_PARAM_PFVF(param) \
2919 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
2920 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
2923 * Partition chip resources for use between various PFs, VFs, etc.
2926 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
2927 const char *name_prefix)
2929 const struct firmware *cfg = NULL;
2931 struct fw_caps_config_cmd caps;
2932 uint32_t mtype, moff, finicsum, cfcsum;
2935 * Figure out what configuration file to use. Pick the default config
2936 * file for the card if the user hasn't specified one explicitly.
2938 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
2939 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
2940 /* Card specific overrides go here. */
2941 if (pci_get_device(sc->dev) == 0x440a)
2942 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
2944 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
2948 * We need to load another module if the profile is anything except
2949 * "default" or "flash".
2951 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
2952 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2955 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
2956 cfg = firmware_get(s);
2958 if (default_cfg != NULL) {
2959 device_printf(sc->dev,
2960 "unable to load module \"%s\" for "
2961 "configuration profile \"%s\", will use "
2962 "the default config file instead.\n",
2964 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2967 device_printf(sc->dev,
2968 "unable to load module \"%s\" for "
2969 "configuration profile \"%s\", will use "
2970 "the config file on the card's flash "
2971 "instead.\n", s, sc->cfg_file);
2972 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2978 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
2979 default_cfg == NULL) {
2980 device_printf(sc->dev,
2981 "default config file not available, will use the config "
2982 "file on the card's flash instead.\n");
2983 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
2986 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2988 const uint32_t *cfdata;
2989 uint32_t param, val, addr;
2991 KASSERT(cfg != NULL || default_cfg != NULL,
2992 ("%s: no config to upload", __func__));
2995 * Ask the firmware where it wants us to upload the config file.
2997 param = FW_PARAM_DEV(CF);
2998 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3000 /* No support for config file? Shouldn't happen. */
3001 device_printf(sc->dev,
3002 "failed to query config file location: %d.\n", rc);
3005 mtype = G_FW_PARAMS_PARAM_Y(val);
3006 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
3009 * XXX: sheer laziness. We deliberately added 4 bytes of
3010 * useless stuffing/comments at the end of the config file so
3011 * it's ok to simply throw away the last remaining bytes when
3012 * the config file is not an exact multiple of 4. This also
3013 * helps with the validate_mt_off_len check.
3016 cflen = cfg->datasize & ~3;
3019 cflen = default_cfg->datasize & ~3;
3020 cfdata = default_cfg->data;
3023 if (cflen > FLASH_CFG_MAX_SIZE) {
3024 device_printf(sc->dev,
3025 "config file too long (%d, max allowed is %d). "
3026 "Will try to use the config on the card, if any.\n",
3027 cflen, FLASH_CFG_MAX_SIZE);
3028 goto use_config_on_flash;
3031 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
3033 device_printf(sc->dev,
3034 "%s: addr (%d/0x%x) or len %d is not valid: %d. "
3035 "Will try to use the config on the card, if any.\n",
3036 __func__, mtype, moff, cflen, rc);
3037 goto use_config_on_flash;
3039 write_via_memwin(sc, 2, addr, cfdata, cflen);
3041 use_config_on_flash:
3042 mtype = FW_MEMTYPE_FLASH;
3043 moff = t4_flash_cfg_addr(sc);
3046 bzero(&caps, sizeof(caps));
3047 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3048 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3049 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
3050 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
3051 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
3052 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3054 device_printf(sc->dev,
3055 "failed to pre-process config file: %d "
3056 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
3060 finicsum = be32toh(caps.finicsum);
3061 cfcsum = be32toh(caps.cfcsum);
3062 if (finicsum != cfcsum) {
3063 device_printf(sc->dev,
3064 "WARNING: config file checksum mismatch: %08x %08x\n",
3067 sc->cfcsum = cfcsum;
3069 #define LIMIT_CAPS(x) do { \
3070 caps.x &= htobe16(t4_##x##_allowed); \
3074 * Let the firmware know what features will (not) be used so it can tune
3075 * things accordingly.
3077 LIMIT_CAPS(nbmcaps);
3078 LIMIT_CAPS(linkcaps);
3079 LIMIT_CAPS(switchcaps);
3080 LIMIT_CAPS(niccaps);
3081 LIMIT_CAPS(toecaps);
3082 LIMIT_CAPS(rdmacaps);
3083 LIMIT_CAPS(cryptocaps);
3084 LIMIT_CAPS(iscsicaps);
3085 LIMIT_CAPS(fcoecaps);
3088 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3089 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
3090 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3091 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
3093 device_printf(sc->dev,
3094 "failed to process config file: %d.\n", rc);
3098 firmware_put(cfg, FIRMWARE_UNLOAD);
3103 * Retrieve parameters that are needed (or nice to have) very early.
3106 get_params__pre_init(struct adapter *sc)
3109 uint32_t param[2], val[2];
3111 t4_get_version_info(sc);
3113 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
3114 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
3115 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
3116 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
3117 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
3119 snprintf(sc->bs_version, sizeof(sc->bs_version), "%u.%u.%u.%u",
3120 G_FW_HDR_FW_VER_MAJOR(sc->params.bs_vers),
3121 G_FW_HDR_FW_VER_MINOR(sc->params.bs_vers),
3122 G_FW_HDR_FW_VER_MICRO(sc->params.bs_vers),
3123 G_FW_HDR_FW_VER_BUILD(sc->params.bs_vers));
3125 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
3126 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
3127 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
3128 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
3129 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
3131 snprintf(sc->er_version, sizeof(sc->er_version), "%u.%u.%u.%u",
3132 G_FW_HDR_FW_VER_MAJOR(sc->params.er_vers),
3133 G_FW_HDR_FW_VER_MINOR(sc->params.er_vers),
3134 G_FW_HDR_FW_VER_MICRO(sc->params.er_vers),
3135 G_FW_HDR_FW_VER_BUILD(sc->params.er_vers));
3137 param[0] = FW_PARAM_DEV(PORTVEC);
3138 param[1] = FW_PARAM_DEV(CCLK);
3139 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3141 device_printf(sc->dev,
3142 "failed to query parameters (pre_init): %d.\n", rc);
3146 sc->params.portvec = val[0];
3147 sc->params.nports = bitcount32(val[0]);
3148 sc->params.vpd.cclk = val[1];
3150 /* Read device log parameters. */
3151 rc = -t4_init_devlog_params(sc, 1);
3153 fixup_devlog_params(sc);
3155 device_printf(sc->dev,
3156 "failed to get devlog parameters: %d.\n", rc);
3157 rc = 0; /* devlog isn't critical for device operation */
3164 * Retrieve various parameters that are of interest to the driver. The device
3165 * has been initialized by the firmware at this point.
3168 get_params__post_init(struct adapter *sc)
3171 uint32_t param[7], val[7];
3172 struct fw_caps_config_cmd caps;
3174 param[0] = FW_PARAM_PFVF(IQFLINT_START);
3175 param[1] = FW_PARAM_PFVF(EQ_START);
3176 param[2] = FW_PARAM_PFVF(FILTER_START);
3177 param[3] = FW_PARAM_PFVF(FILTER_END);
3178 param[4] = FW_PARAM_PFVF(L2T_START);
3179 param[5] = FW_PARAM_PFVF(L2T_END);
3180 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3182 device_printf(sc->dev,
3183 "failed to query parameters (post_init): %d.\n", rc);
3187 sc->sge.iq_start = val[0];
3188 sc->sge.eq_start = val[1];
3189 sc->tids.ftid_base = val[2];
3190 sc->tids.nftids = val[3] - val[2] + 1;
3191 sc->params.ftid_min = val[2];
3192 sc->params.ftid_max = val[3];
3193 sc->vres.l2t.start = val[4];
3194 sc->vres.l2t.size = val[5] - val[4] + 1;
3195 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
3196 ("%s: L2 table size (%u) larger than expected (%u)",
3197 __func__, sc->vres.l2t.size, L2T_SIZE));
3199 /* get capabilites */
3200 bzero(&caps, sizeof(caps));
3201 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3202 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3203 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3204 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3206 device_printf(sc->dev,
3207 "failed to get card capabilities: %d.\n", rc);
3211 #define READ_CAPS(x) do { \
3212 sc->x = htobe16(caps.x); \
3215 READ_CAPS(linkcaps);
3216 READ_CAPS(switchcaps);
3219 READ_CAPS(rdmacaps);
3220 READ_CAPS(cryptocaps);
3221 READ_CAPS(iscsicaps);
3222 READ_CAPS(fcoecaps);
3224 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3225 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3226 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3227 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3228 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
3230 device_printf(sc->dev,
3231 "failed to query NIC parameters: %d.\n", rc);
3234 sc->tids.etid_base = val[0];
3235 sc->params.etid_min = val[0];
3236 sc->tids.netids = val[1] - val[0] + 1;
3237 sc->params.netids = sc->tids.netids;
3238 sc->params.eo_wr_cred = val[2];
3239 sc->params.ethoffload = 1;
3243 /* query offload-related parameters */
3244 param[0] = FW_PARAM_DEV(NTID);
3245 param[1] = FW_PARAM_PFVF(SERVER_START);
3246 param[2] = FW_PARAM_PFVF(SERVER_END);
3247 param[3] = FW_PARAM_PFVF(TDDP_START);
3248 param[4] = FW_PARAM_PFVF(TDDP_END);
3249 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3250 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3252 device_printf(sc->dev,
3253 "failed to query TOE parameters: %d.\n", rc);
3256 sc->tids.ntids = val[0];
3257 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
3258 sc->tids.stid_base = val[1];
3259 sc->tids.nstids = val[2] - val[1] + 1;
3260 sc->vres.ddp.start = val[3];
3261 sc->vres.ddp.size = val[4] - val[3] + 1;
3262 sc->params.ofldq_wr_cred = val[5];
3263 sc->params.offload = 1;
3266 param[0] = FW_PARAM_PFVF(STAG_START);
3267 param[1] = FW_PARAM_PFVF(STAG_END);
3268 param[2] = FW_PARAM_PFVF(RQ_START);
3269 param[3] = FW_PARAM_PFVF(RQ_END);
3270 param[4] = FW_PARAM_PFVF(PBL_START);
3271 param[5] = FW_PARAM_PFVF(PBL_END);
3272 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3274 device_printf(sc->dev,
3275 "failed to query RDMA parameters(1): %d.\n", rc);
3278 sc->vres.stag.start = val[0];
3279 sc->vres.stag.size = val[1] - val[0] + 1;
3280 sc->vres.rq.start = val[2];
3281 sc->vres.rq.size = val[3] - val[2] + 1;
3282 sc->vres.pbl.start = val[4];
3283 sc->vres.pbl.size = val[5] - val[4] + 1;
3285 param[0] = FW_PARAM_PFVF(SQRQ_START);
3286 param[1] = FW_PARAM_PFVF(SQRQ_END);
3287 param[2] = FW_PARAM_PFVF(CQ_START);
3288 param[3] = FW_PARAM_PFVF(CQ_END);
3289 param[4] = FW_PARAM_PFVF(OCQ_START);
3290 param[5] = FW_PARAM_PFVF(OCQ_END);
3291 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3293 device_printf(sc->dev,
3294 "failed to query RDMA parameters(2): %d.\n", rc);
3297 sc->vres.qp.start = val[0];
3298 sc->vres.qp.size = val[1] - val[0] + 1;
3299 sc->vres.cq.start = val[2];
3300 sc->vres.cq.size = val[3] - val[2] + 1;
3301 sc->vres.ocq.start = val[4];
3302 sc->vres.ocq.size = val[5] - val[4] + 1;
3304 if (sc->iscsicaps) {
3305 param[0] = FW_PARAM_PFVF(ISCSI_START);
3306 param[1] = FW_PARAM_PFVF(ISCSI_END);
3307 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3309 device_printf(sc->dev,
3310 "failed to query iSCSI parameters: %d.\n", rc);
3313 sc->vres.iscsi.start = val[0];
3314 sc->vres.iscsi.size = val[1] - val[0] + 1;
3317 t4_init_sge_params(sc);
3320 * We've got the params we wanted to query via the firmware. Now grab
3321 * some others directly from the chip.
3323 rc = t4_read_chip_settings(sc);
3329 set_params__post_init(struct adapter *sc)
3331 uint32_t param, val;
3333 /* ask for encapsulated CPLs */
3334 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3336 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3341 #undef FW_PARAM_PFVF
3345 t4_set_desc(struct adapter *sc)
3348 struct adapter_params *p = &sc->params;
3350 snprintf(buf, sizeof(buf), "Chelsio %s", p->vpd.id);
3352 device_set_desc_copy(sc->dev, buf);
3356 build_medialist(struct port_info *pi, struct ifmedia *media)
3362 ifmedia_removeall(media);
3364 m = IFM_ETHER | IFM_FDX;
3366 switch(pi->port_type) {
3367 case FW_PORT_TYPE_BT_XFI:
3368 case FW_PORT_TYPE_BT_XAUI:
3369 ifmedia_add(media, m | IFM_10G_T, 0, NULL);
3372 case FW_PORT_TYPE_BT_SGMII:
3373 ifmedia_add(media, m | IFM_1000_T, 0, NULL);
3374 ifmedia_add(media, m | IFM_100_TX, 0, NULL);
3375 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL);
3376 ifmedia_set(media, IFM_ETHER | IFM_AUTO);
3379 case FW_PORT_TYPE_CX4:
3380 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL);
3381 ifmedia_set(media, m | IFM_10G_CX4);
3384 case FW_PORT_TYPE_QSFP_10G:
3385 case FW_PORT_TYPE_SFP:
3386 case FW_PORT_TYPE_FIBER_XFI:
3387 case FW_PORT_TYPE_FIBER_XAUI:
3388 switch (pi->mod_type) {
3390 case FW_PORT_MOD_TYPE_LR:
3391 ifmedia_add(media, m | IFM_10G_LR, 0, NULL);
3392 ifmedia_set(media, m | IFM_10G_LR);
3395 case FW_PORT_MOD_TYPE_SR:
3396 ifmedia_add(media, m | IFM_10G_SR, 0, NULL);
3397 ifmedia_set(media, m | IFM_10G_SR);
3400 case FW_PORT_MOD_TYPE_LRM:
3401 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL);
3402 ifmedia_set(media, m | IFM_10G_LRM);
3405 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3406 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3407 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL);
3408 ifmedia_set(media, m | IFM_10G_TWINAX);
3411 case FW_PORT_MOD_TYPE_NONE:
3413 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3414 ifmedia_set(media, m | IFM_NONE);
3417 case FW_PORT_MOD_TYPE_NA:
3418 case FW_PORT_MOD_TYPE_ER:
3420 device_printf(pi->dev,
3421 "unknown port_type (%d), mod_type (%d)\n",
3422 pi->port_type, pi->mod_type);
3423 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3424 ifmedia_set(media, m | IFM_UNKNOWN);
3429 case FW_PORT_TYPE_CR_QSFP:
3430 case FW_PORT_TYPE_SFP28:
3431 case FW_PORT_TYPE_KR_SFP28:
3432 switch (pi->mod_type) {
3434 case FW_PORT_MOD_TYPE_SR:
3435 ifmedia_add(media, m | IFM_25G_SR, 0, NULL);
3436 ifmedia_set(media, m | IFM_25G_SR);
3439 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3440 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3441 ifmedia_add(media, m | IFM_25G_CR, 0, NULL);
3442 ifmedia_set(media, m | IFM_25G_CR);
3445 case FW_PORT_MOD_TYPE_NONE:
3447 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3448 ifmedia_set(media, m | IFM_NONE);
3452 device_printf(pi->dev,
3453 "unknown port_type (%d), mod_type (%d)\n",
3454 pi->port_type, pi->mod_type);
3455 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3456 ifmedia_set(media, m | IFM_UNKNOWN);
3461 case FW_PORT_TYPE_QSFP:
3462 switch (pi->mod_type) {
3464 case FW_PORT_MOD_TYPE_LR:
3465 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL);
3466 ifmedia_set(media, m | IFM_40G_LR4);
3469 case FW_PORT_MOD_TYPE_SR:
3470 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL);
3471 ifmedia_set(media, m | IFM_40G_SR4);
3474 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3475 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3476 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL);
3477 ifmedia_set(media, m | IFM_40G_CR4);
3480 case FW_PORT_MOD_TYPE_NONE:
3482 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3483 ifmedia_set(media, m | IFM_NONE);
3487 device_printf(pi->dev,
3488 "unknown port_type (%d), mod_type (%d)\n",
3489 pi->port_type, pi->mod_type);
3490 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3491 ifmedia_set(media, m | IFM_UNKNOWN);
3496 case FW_PORT_TYPE_KR4_100G:
3497 case FW_PORT_TYPE_CR4_QSFP:
3498 switch (pi->mod_type) {
3500 case FW_PORT_MOD_TYPE_LR:
3501 ifmedia_add(media, m | IFM_100G_LR4, 0, NULL);
3502 ifmedia_set(media, m | IFM_100G_LR4);
3505 case FW_PORT_MOD_TYPE_SR:
3506 ifmedia_add(media, m | IFM_100G_SR4, 0, NULL);
3507 ifmedia_set(media, m | IFM_100G_SR4);
3510 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3511 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3512 ifmedia_add(media, m | IFM_100G_CR4, 0, NULL);
3513 ifmedia_set(media, m | IFM_100G_CR4);
3516 case FW_PORT_MOD_TYPE_NONE:
3518 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3519 ifmedia_set(media, m | IFM_NONE);
3523 device_printf(pi->dev,
3524 "unknown port_type (%d), mod_type (%d)\n",
3525 pi->port_type, pi->mod_type);
3526 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3527 ifmedia_set(media, m | IFM_UNKNOWN);
3533 device_printf(pi->dev,
3534 "unknown port_type (%d), mod_type (%d)\n", pi->port_type,
3536 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3537 ifmedia_set(media, m | IFM_UNKNOWN);
3544 #define FW_MAC_EXACT_CHUNK 7
3547 * Program the port's XGMAC based on parameters in ifnet. The caller also
3548 * indicates which parameters should be programmed (the rest are left alone).
3551 update_mac_settings(struct ifnet *ifp, int flags)
3554 struct vi_info *vi = ifp->if_softc;
3555 struct port_info *pi = vi->pi;
3556 struct adapter *sc = pi->adapter;
3557 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
3559 ASSERT_SYNCHRONIZED_OP(sc);
3560 KASSERT(flags, ("%s: not told what to update.", __func__));
3562 if (flags & XGMAC_MTU)
3565 if (flags & XGMAC_PROMISC)
3566 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
3568 if (flags & XGMAC_ALLMULTI)
3569 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
3571 if (flags & XGMAC_VLANEX)
3572 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
3574 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
3575 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
3576 allmulti, 1, vlanex, false);
3578 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
3584 if (flags & XGMAC_UCADDR) {
3585 uint8_t ucaddr[ETHER_ADDR_LEN];
3587 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
3588 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
3589 ucaddr, true, true);
3592 if_printf(ifp, "change_mac failed: %d\n", rc);
3595 vi->xact_addr_filt = rc;
3600 if (flags & XGMAC_MCADDRS) {
3601 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
3604 struct ifmultiaddr *ifma;
3607 if_maddr_rlock(ifp);
3608 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3609 if (ifma->ifma_addr->sa_family != AF_LINK)
3612 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
3613 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
3616 if (i == FW_MAC_EXACT_CHUNK) {
3617 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
3618 del, i, mcaddr, NULL, &hash, 0);
3621 for (j = 0; j < i; j++) {
3623 "failed to add mc address"
3625 "%02x:%02x:%02x rc=%d\n",
3626 mcaddr[j][0], mcaddr[j][1],
3627 mcaddr[j][2], mcaddr[j][3],
3628 mcaddr[j][4], mcaddr[j][5],
3638 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
3639 mcaddr, NULL, &hash, 0);
3642 for (j = 0; j < i; j++) {
3644 "failed to add mc address"
3646 "%02x:%02x:%02x rc=%d\n",
3647 mcaddr[j][0], mcaddr[j][1],
3648 mcaddr[j][2], mcaddr[j][3],
3649 mcaddr[j][4], mcaddr[j][5],
3656 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
3658 if_printf(ifp, "failed to set mc address hash: %d", rc);
3660 if_maddr_runlock(ifp);
3667 * {begin|end}_synchronized_op must be called from the same thread.
3670 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
3676 /* the caller thinks it's ok to sleep, but is it really? */
3677 if (flags & SLEEP_OK)
3678 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
3679 "begin_synchronized_op");
3690 if (vi && IS_DOOMED(vi)) {
3700 if (!(flags & SLEEP_OK)) {
3705 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
3711 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
3714 sc->last_op = wmesg;
3715 sc->last_op_thr = curthread;
3716 sc->last_op_flags = flags;
3720 if (!(flags & HOLD_LOCK) || rc)
3727 * Tell if_ioctl and if_init that the VI is going away. This is
3728 * special variant of begin_synchronized_op and must be paired with a
3729 * call to end_synchronized_op.
3732 doom_vi(struct adapter *sc, struct vi_info *vi)
3739 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
3742 sc->last_op = "t4detach";
3743 sc->last_op_thr = curthread;
3744 sc->last_op_flags = 0;
3750 * {begin|end}_synchronized_op must be called from the same thread.
3753 end_synchronized_op(struct adapter *sc, int flags)
3756 if (flags & LOCK_HELD)
3757 ADAPTER_LOCK_ASSERT_OWNED(sc);
3761 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
3768 cxgbe_init_synchronized(struct vi_info *vi)
3770 struct port_info *pi = vi->pi;
3771 struct adapter *sc = pi->adapter;
3772 struct ifnet *ifp = vi->ifp;
3774 struct sge_txq *txq;
3776 ASSERT_SYNCHRONIZED_OP(sc);
3778 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3779 return (0); /* already running */
3781 if (!(sc->flags & FULL_INIT_DONE) &&
3782 ((rc = adapter_full_init(sc)) != 0))
3783 return (rc); /* error message displayed already */
3785 if (!(vi->flags & VI_INIT_DONE) &&
3786 ((rc = vi_full_init(vi)) != 0))
3787 return (rc); /* error message displayed already */
3789 rc = update_mac_settings(ifp, XGMAC_ALL);
3791 goto done; /* error message displayed already */
3793 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
3795 if_printf(ifp, "enable_vi failed: %d\n", rc);
3800 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
3804 for_each_txq(vi, i, txq) {
3806 txq->eq.flags |= EQ_ENABLED;
3811 * The first iq of the first port to come up is used for tracing.
3813 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
3814 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
3815 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
3816 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
3817 V_QUEUENUMBER(sc->traceq));
3818 pi->flags |= HAS_TRACEQ;
3823 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3826 if (pi->nvi > 1 || sc->flags & IS_VF)
3827 callout_reset(&vi->tick, hz, vi_tick, vi);
3829 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
3833 cxgbe_uninit_synchronized(vi);
3842 cxgbe_uninit_synchronized(struct vi_info *vi)
3844 struct port_info *pi = vi->pi;
3845 struct adapter *sc = pi->adapter;
3846 struct ifnet *ifp = vi->ifp;
3848 struct sge_txq *txq;
3850 ASSERT_SYNCHRONIZED_OP(sc);
3852 if (!(vi->flags & VI_INIT_DONE)) {
3853 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING),
3854 ("uninited VI is running"));
3859 * Disable the VI so that all its data in either direction is discarded
3860 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
3861 * tick) intact as the TP can deliver negative advice or data that it's
3862 * holding in its RAM (for an offloaded connection) even after the VI is
3865 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
3867 if_printf(ifp, "disable_vi failed: %d\n", rc);
3871 for_each_txq(vi, i, txq) {
3873 txq->eq.flags &= ~EQ_ENABLED;
3878 if (pi->nvi > 1 || sc->flags & IS_VF)
3879 callout_stop(&vi->tick);
3881 callout_stop(&pi->tick);
3882 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3886 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3888 if (pi->up_vis > 0) {
3894 pi->link_cfg.link_ok = 0;
3895 pi->link_cfg.speed = 0;
3896 pi->link_cfg.link_down_rc = 255;
3897 t4_os_link_changed(sc, pi->port_id, 0);
3903 * It is ok for this function to fail midway and return right away. t4_detach
3904 * will walk the entire sc->irq list and clean up whatever is valid.
3907 t4_setup_intr_handlers(struct adapter *sc)
3909 int rc, rid, p, q, v;
3912 struct port_info *pi;
3914 struct sge *sge = &sc->sge;
3915 struct sge_rxq *rxq;
3917 struct sge_ofld_rxq *ofld_rxq;
3920 struct sge_nm_rxq *nm_rxq;
3927 rid = sc->intr_type == INTR_INTX ? 0 : 1;
3928 if (sc->intr_count == 1)
3929 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
3931 /* Multiple interrupts. */
3932 if (sc->flags & IS_VF)
3933 KASSERT(sc->intr_count >= T4VF_EXTRA_INTR + sc->params.nports,
3934 ("%s: too few intr.", __func__));
3936 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
3937 ("%s: too few intr.", __func__));
3939 /* The first one is always error intr on PFs */
3940 if (!(sc->flags & IS_VF)) {
3941 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
3948 /* The second one is always the firmware event queue (first on VFs) */
3949 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
3955 for_each_port(sc, p) {
3957 for_each_vi(pi, v, vi) {
3958 vi->first_intr = rid - 1;
3960 if (vi->nnmrxq > 0) {
3961 int n = max(vi->nrxq, vi->nnmrxq);
3963 MPASS(vi->flags & INTR_RXQ);
3965 rxq = &sge->rxq[vi->first_rxq];
3967 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
3969 for (q = 0; q < n; q++) {
3970 snprintf(s, sizeof(s), "%x%c%x", p,
3976 irq->nm_rxq = nm_rxq++;
3978 rc = t4_alloc_irq(sc, irq, rid,
3979 t4_vi_intr, irq, s);
3986 } else if (vi->flags & INTR_RXQ) {
3987 for_each_rxq(vi, q, rxq) {
3988 snprintf(s, sizeof(s), "%x%c%x", p,
3990 rc = t4_alloc_irq(sc, irq, rid,
4000 if (vi->flags & INTR_OFLD_RXQ) {
4001 for_each_ofld_rxq(vi, q, ofld_rxq) {
4002 snprintf(s, sizeof(s), "%x%c%x", p,
4004 rc = t4_alloc_irq(sc, irq, rid,
4005 t4_intr, ofld_rxq, s);
4016 MPASS(irq == &sc->irq[sc->intr_count]);
4022 adapter_full_init(struct adapter *sc)
4026 ASSERT_SYNCHRONIZED_OP(sc);
4027 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4028 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
4029 ("%s: FULL_INIT_DONE already", __func__));
4032 * queues that belong to the adapter (not any particular port).
4034 rc = t4_setup_adapter_queues(sc);
4038 for (i = 0; i < nitems(sc->tq); i++) {
4039 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
4040 taskqueue_thread_enqueue, &sc->tq[i]);
4041 if (sc->tq[i] == NULL) {
4042 device_printf(sc->dev,
4043 "failed to allocate task queue %d\n", i);
4047 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
4048 device_get_nameunit(sc->dev), i);
4051 if (!(sc->flags & IS_VF))
4053 sc->flags |= FULL_INIT_DONE;
4056 adapter_full_uninit(sc);
4062 adapter_full_uninit(struct adapter *sc)
4066 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
4068 t4_teardown_adapter_queues(sc);
4070 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
4071 taskqueue_free(sc->tq[i]);
4075 sc->flags &= ~FULL_INIT_DONE;
4081 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
4082 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
4083 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
4084 RSS_HASHTYPE_RSS_UDP_IPV6)
4086 /* Translates kernel hash types to hardware. */
4088 hashconfig_to_hashen(int hashconfig)
4092 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
4093 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
4094 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
4095 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
4096 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
4097 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4098 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4100 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
4101 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
4102 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4104 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
4105 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
4106 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
4107 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
4112 /* Translates hardware hash types to kernel. */
4114 hashen_to_hashconfig(int hashen)
4118 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
4120 * If UDP hashing was enabled it must have been enabled for
4121 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
4122 * enabling any 4-tuple hash is nonsense configuration.
4124 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4125 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
4127 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4128 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
4129 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4130 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
4132 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
4133 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
4134 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
4135 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
4136 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
4137 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
4138 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
4139 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
4141 return (hashconfig);
4146 vi_full_init(struct vi_info *vi)
4148 struct adapter *sc = vi->pi->adapter;
4149 struct ifnet *ifp = vi->ifp;
4151 struct sge_rxq *rxq;
4152 int rc, i, j, hashen;
4154 int nbuckets = rss_getnumbuckets();
4155 int hashconfig = rss_gethashconfig();
4157 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4158 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
4161 ASSERT_SYNCHRONIZED_OP(sc);
4162 KASSERT((vi->flags & VI_INIT_DONE) == 0,
4163 ("%s: VI_INIT_DONE already", __func__));
4165 sysctl_ctx_init(&vi->ctx);
4166 vi->flags |= VI_SYSCTL_CTX;
4169 * Allocate tx/rx/fl queues for this VI.
4171 rc = t4_setup_vi_queues(vi);
4173 goto done; /* error message displayed already */
4176 * Setup RSS for this VI. Save a copy of the RSS table for later use.
4178 if (vi->nrxq > vi->rss_size) {
4179 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
4180 "some queues will never receive traffic.\n", vi->nrxq,
4182 } else if (vi->rss_size % vi->nrxq) {
4183 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
4184 "expect uneven traffic distribution.\n", vi->nrxq,
4188 MPASS(RSS_KEYSIZE == 40);
4189 if (vi->nrxq != nbuckets) {
4190 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
4191 "performance will be impacted.\n", vi->nrxq, nbuckets);
4194 rss_getkey((void *)&raw_rss_key[0]);
4195 for (i = 0; i < nitems(rss_key); i++) {
4196 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
4198 t4_write_rss_key(sc, &rss_key[0], -1);
4200 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
4201 for (i = 0; i < vi->rss_size;) {
4203 j = rss_get_indirection_to_bucket(i);
4205 rxq = &sc->sge.rxq[vi->first_rxq + j];
4206 rss[i++] = rxq->iq.abs_id;
4208 for_each_rxq(vi, j, rxq) {
4209 rss[i++] = rxq->iq.abs_id;
4210 if (i == vi->rss_size)
4216 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
4219 if_printf(ifp, "rss_config failed: %d\n", rc);
4224 hashen = hashconfig_to_hashen(hashconfig);
4227 * We may have had to enable some hashes even though the global config
4228 * wants them disabled. This is a potential problem that must be
4229 * reported to the user.
4231 extra = hashen_to_hashconfig(hashen) ^ hashconfig;
4234 * If we consider only the supported hash types, then the enabled hashes
4235 * are a superset of the requested hashes. In other words, there cannot
4236 * be any supported hash that was requested but not enabled, but there
4237 * can be hashes that were not requested but had to be enabled.
4239 extra &= SUPPORTED_RSS_HASHTYPES;
4240 MPASS((extra & hashconfig) == 0);
4244 "global RSS config (0x%x) cannot be accomodated.\n",
4247 if (extra & RSS_HASHTYPE_RSS_IPV4)
4248 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
4249 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
4250 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
4251 if (extra & RSS_HASHTYPE_RSS_IPV6)
4252 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
4253 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
4254 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
4255 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
4256 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
4257 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
4258 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
4260 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
4261 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
4262 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4263 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
4265 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0], 0, 0);
4267 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
4272 vi->flags |= VI_INIT_DONE;
4284 vi_full_uninit(struct vi_info *vi)
4286 struct port_info *pi = vi->pi;
4287 struct adapter *sc = pi->adapter;
4289 struct sge_rxq *rxq;
4290 struct sge_txq *txq;
4292 struct sge_ofld_rxq *ofld_rxq;
4293 struct sge_wrq *ofld_txq;
4296 if (vi->flags & VI_INIT_DONE) {
4298 /* Need to quiesce queues. */
4300 /* XXX: Only for the first VI? */
4301 if (IS_MAIN_VI(vi) && !(sc->flags & IS_VF))
4302 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
4304 for_each_txq(vi, i, txq) {
4305 quiesce_txq(sc, txq);
4309 for_each_ofld_txq(vi, i, ofld_txq) {
4310 quiesce_wrq(sc, ofld_txq);
4314 for_each_rxq(vi, i, rxq) {
4315 quiesce_iq(sc, &rxq->iq);
4316 quiesce_fl(sc, &rxq->fl);
4320 for_each_ofld_rxq(vi, i, ofld_rxq) {
4321 quiesce_iq(sc, &ofld_rxq->iq);
4322 quiesce_fl(sc, &ofld_rxq->fl);
4325 free(vi->rss, M_CXGBE);
4326 free(vi->nm_rss, M_CXGBE);
4329 t4_teardown_vi_queues(vi);
4330 vi->flags &= ~VI_INIT_DONE;
4336 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
4338 struct sge_eq *eq = &txq->eq;
4339 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4341 (void) sc; /* unused */
4345 MPASS((eq->flags & EQ_ENABLED) == 0);
4349 /* Wait for the mp_ring to empty. */
4350 while (!mp_ring_is_idle(txq->r)) {
4351 mp_ring_check_drainage(txq->r, 0);
4352 pause("rquiesce", 1);
4355 /* Then wait for the hardware to finish. */
4356 while (spg->cidx != htobe16(eq->pidx))
4357 pause("equiesce", 1);
4359 /* Finally, wait for the driver to reclaim all descriptors. */
4360 while (eq->cidx != eq->pidx)
4361 pause("dquiesce", 1);
4365 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
4372 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
4374 (void) sc; /* unused */
4376 /* Synchronize with the interrupt handler */
4377 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
4382 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
4384 mtx_lock(&sc->sfl_lock);
4386 fl->flags |= FL_DOOMED;
4388 callout_stop(&sc->sfl_callout);
4389 mtx_unlock(&sc->sfl_lock);
4391 KASSERT((fl->flags & FL_STARVING) == 0,
4392 ("%s: still starving", __func__));
4396 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
4397 driver_intr_t *handler, void *arg, char *name)
4402 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
4403 RF_SHAREABLE | RF_ACTIVE);
4404 if (irq->res == NULL) {
4405 device_printf(sc->dev,
4406 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
4410 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
4411 NULL, handler, arg, &irq->tag);
4413 device_printf(sc->dev,
4414 "failed to setup interrupt for rid %d, name %s: %d\n",
4417 bus_describe_intr(sc->dev, irq->res, irq->tag, name);
4423 t4_free_irq(struct adapter *sc, struct irq *irq)
4426 bus_teardown_intr(sc->dev, irq->res, irq->tag);
4428 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
4430 bzero(irq, sizeof(*irq));
4436 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
4439 regs->version = chip_id(sc) | chip_rev(sc) << 10;
4440 t4_get_regs(sc, buf, regs->len);
4443 #define A_PL_INDIR_CMD 0x1f8
4445 #define S_PL_AUTOINC 31
4446 #define M_PL_AUTOINC 0x1U
4447 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
4448 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
4450 #define S_PL_VFID 20
4451 #define M_PL_VFID 0xffU
4452 #define V_PL_VFID(x) ((x) << S_PL_VFID)
4453 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
4456 #define M_PL_ADDR 0xfffffU
4457 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
4458 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
4460 #define A_PL_INDIR_DATA 0x1fc
4463 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
4467 mtx_assert(&sc->reg_lock, MA_OWNED);
4468 if (sc->flags & IS_VF) {
4469 stats[0] = t4_read_reg(sc, VF_MPS_REG(reg));
4470 stats[1] = t4_read_reg(sc, VF_MPS_REG(reg + 4));
4472 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4473 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4474 V_PL_ADDR(VF_MPS_REG(reg)));
4475 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
4476 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
4478 return (((uint64_t)stats[1]) << 32 | stats[0]);
4482 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
4483 struct fw_vi_stats_vf *stats)
4486 #define GET_STAT(name) \
4487 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
4489 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
4490 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
4491 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
4492 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
4493 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
4494 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
4495 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
4496 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
4497 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
4498 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
4499 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
4500 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
4501 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
4502 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
4503 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
4504 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
4510 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
4514 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4515 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4516 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
4517 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
4518 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
4519 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
4523 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
4525 struct ifnet *ifp = vi->ifp;
4526 struct sge_txq *txq;
4528 struct fw_vi_stats_vf *s = &vi->stats;
4530 const struct timeval interval = {0, 250000}; /* 250ms */
4532 if (!(vi->flags & VI_INIT_DONE))
4536 timevalsub(&tv, &interval);
4537 if (timevalcmp(&tv, &vi->last_refreshed, <))
4540 mtx_lock(&sc->reg_lock);
4541 t4_get_vi_stats(sc, vi->viid, &vi->stats);
4543 ifp->if_ipackets = s->rx_bcast_frames + s->rx_mcast_frames +
4545 ifp->if_ierrors = s->rx_err_frames;
4546 ifp->if_opackets = s->tx_bcast_frames + s->tx_mcast_frames +
4547 s->tx_ucast_frames + s->tx_offload_frames;
4548 ifp->if_oerrors = s->tx_drop_frames;
4549 ifp->if_ibytes = s->rx_bcast_bytes + s->rx_mcast_bytes +
4551 ifp->if_obytes = s->tx_bcast_bytes + s->tx_mcast_bytes +
4552 s->tx_ucast_bytes + s->tx_offload_bytes;
4553 ifp->if_imcasts = s->rx_mcast_frames;
4554 ifp->if_omcasts = s->tx_mcast_frames;
4557 for_each_txq(vi, i, txq)
4558 drops += counter_u64_fetch(txq->r->drops);
4559 ifp->if_snd.ifq_drops = drops;
4561 getmicrotime(&vi->last_refreshed);
4562 mtx_unlock(&sc->reg_lock);
4566 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
4568 struct vi_info *vi = &pi->vi[0];
4569 struct ifnet *ifp = vi->ifp;
4570 struct sge_txq *txq;
4572 struct port_stats *s = &pi->stats;
4574 const struct timeval interval = {0, 250000}; /* 250ms */
4577 timevalsub(&tv, &interval);
4578 if (timevalcmp(&tv, &pi->last_refreshed, <))
4581 t4_get_port_stats(sc, pi->tx_chan, s);
4583 ifp->if_opackets = s->tx_frames;
4584 ifp->if_ipackets = s->rx_frames;
4585 ifp->if_obytes = s->tx_octets;
4586 ifp->if_ibytes = s->rx_octets;
4587 ifp->if_omcasts = s->tx_mcast_frames;
4588 ifp->if_imcasts = s->rx_mcast_frames;
4589 ifp->if_iqdrops = s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
4590 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
4592 for (i = 0; i < sc->chip_params->nchan; i++) {
4593 if (pi->rx_chan_map & (1 << i)) {
4596 mtx_lock(&sc->reg_lock);
4597 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
4598 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
4599 mtx_unlock(&sc->reg_lock);
4600 ifp->if_iqdrops += v;
4605 for_each_txq(vi, i, txq)
4606 drops += counter_u64_fetch(txq->r->drops);
4607 ifp->if_snd.ifq_drops = drops;
4609 ifp->if_oerrors = s->tx_error_frames;
4610 ifp->if_ierrors = s->rx_jabber + s->rx_runt + s->rx_too_long +
4611 s->rx_fcs_err + s->rx_len_err;
4613 getmicrotime(&pi->last_refreshed);
4617 cxgbe_tick(void *arg)
4619 struct port_info *pi = arg;
4620 struct adapter *sc = pi->adapter;
4622 PORT_LOCK_ASSERT_OWNED(pi);
4623 cxgbe_refresh_stats(sc, pi);
4625 callout_schedule(&pi->tick, hz);
4631 struct vi_info *vi = arg;
4632 struct adapter *sc = vi->pi->adapter;
4634 vi_refresh_stats(sc, vi);
4636 callout_schedule(&vi->tick, hz);
4640 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
4644 if (arg != ifp || ifp->if_type != IFT_ETHER)
4647 vlan = VLAN_DEVAT(ifp, vid);
4648 VLAN_SETCOOKIE(vlan, ifp);
4652 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
4654 static char *caps_decoder[] = {
4655 "\20\001IPMI\002NCSI", /* 0: NBM */
4656 "\20\001PPP\002QFC\003DCBX", /* 1: link */
4657 "\20\001INGRESS\002EGRESS", /* 2: switch */
4658 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
4659 "\006HASHFILTER\007ETHOFLD",
4660 "\20\001TOE", /* 4: TOE */
4661 "\20\001RDDP\002RDMAC", /* 5: RDMA */
4662 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
4663 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
4664 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
4666 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
4667 "\20\001LOOKASIDE\002TLSKEYS", /* 7: Crypto */
4668 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
4669 "\004PO_INITIATOR\005PO_TARGET",
4673 t4_sysctls(struct adapter *sc)
4675 struct sysctl_ctx_list *ctx;
4676 struct sysctl_oid *oid;
4677 struct sysctl_oid_list *children, *c0;
4678 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
4680 ctx = device_get_sysctl_ctx(sc->dev);
4685 oid = device_get_sysctl_tree(sc->dev);
4686 c0 = children = SYSCTL_CHILDREN(oid);
4688 sc->sc_do_rxcopy = 1;
4689 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
4690 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
4692 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
4693 sc->params.nports, "# of ports");
4695 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
4696 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells,
4697 sysctl_bitfield, "A", "available doorbells");
4699 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
4700 sc->params.vpd.cclk, "core clock frequency (in KHz)");
4702 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
4703 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
4704 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
4705 "interrupt holdoff timer values (us)");
4707 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
4708 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
4709 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
4710 "interrupt holdoff packet counter values");
4712 t4_sge_sysctls(sc, ctx, children);
4714 sc->lro_timeout = 100;
4715 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
4716 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
4718 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "dflags", CTLFLAG_RW,
4719 &sc->debug_flags, 0, "flags to enable runtime debugging");
4721 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
4722 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
4724 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
4725 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
4727 if (sc->flags & IS_VF)
4730 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
4731 NULL, chip_rev(sc), "chip hardware revision");
4733 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "sn",
4734 CTLFLAG_RD, sc->params.vpd.sn, 0, "serial number");
4736 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "pn",
4737 CTLFLAG_RD, sc->params.vpd.pn, 0, "part number");
4739 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "ec",
4740 CTLFLAG_RD, sc->params.vpd.ec, 0, "engineering change");
4742 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "na",
4743 CTLFLAG_RD, sc->params.vpd.na, 0, "network address");
4745 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "er_version", CTLFLAG_RD,
4746 sc->er_version, 0, "expansion ROM version");
4748 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "bs_version", CTLFLAG_RD,
4749 sc->bs_version, 0, "bootstrap firmware version");
4751 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "scfg_version", CTLFLAG_RD,
4752 NULL, sc->params.scfg_vers, "serial config version");
4754 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "vpd_version", CTLFLAG_RD,
4755 NULL, sc->params.vpd_vers, "VPD version");
4757 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
4758 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
4760 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
4761 sc->cfcsum, "config file checksum");
4763 #define SYSCTL_CAP(name, n, text) \
4764 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
4765 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \
4766 sysctl_bitfield, "A", "available " text " capabilities")
4768 SYSCTL_CAP(nbmcaps, 0, "NBM");
4769 SYSCTL_CAP(linkcaps, 1, "link");
4770 SYSCTL_CAP(switchcaps, 2, "switch");
4771 SYSCTL_CAP(niccaps, 3, "NIC");
4772 SYSCTL_CAP(toecaps, 4, "TCP offload");
4773 SYSCTL_CAP(rdmacaps, 5, "RDMA");
4774 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
4775 SYSCTL_CAP(cryptocaps, 7, "crypto");
4776 SYSCTL_CAP(fcoecaps, 8, "FCoE");
4779 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
4780 NULL, sc->tids.nftids, "number of filters");
4782 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
4783 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
4784 "chip temperature (in Celsius)");
4788 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
4790 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
4791 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
4792 "logs and miscellaneous information");
4793 children = SYSCTL_CHILDREN(oid);
4795 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
4796 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4797 sysctl_cctrl, "A", "congestion control");
4799 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
4800 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4801 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
4803 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
4804 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
4805 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
4807 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
4808 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
4809 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
4811 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
4812 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
4813 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
4815 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
4816 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
4817 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
4819 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
4820 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
4821 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
4823 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
4824 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4825 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
4826 "A", "CIM logic analyzer");
4828 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
4829 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4830 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
4832 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
4833 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
4834 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
4836 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
4837 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
4838 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
4840 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
4841 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
4842 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
4844 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
4845 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
4846 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
4848 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
4849 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
4850 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
4852 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
4853 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
4854 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
4856 if (chip_id(sc) > CHELSIO_T4) {
4857 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
4858 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
4859 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
4861 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
4862 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
4863 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
4866 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
4867 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4868 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
4870 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
4871 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4872 sysctl_cim_qcfg, "A", "CIM queue configuration");
4874 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
4875 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4876 sysctl_cpl_stats, "A", "CPL statistics");
4878 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
4879 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4880 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
4882 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
4883 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4884 sysctl_devlog, "A", "firmware's device log");
4886 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
4887 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4888 sysctl_fcoe_stats, "A", "FCoE statistics");
4890 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
4891 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4892 sysctl_hw_sched, "A", "hardware scheduler ");
4894 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
4895 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4896 sysctl_l2t, "A", "hardware L2 table");
4898 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
4899 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4900 sysctl_lb_stats, "A", "loopback statistics");
4902 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
4903 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4904 sysctl_meminfo, "A", "memory regions");
4906 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
4907 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4908 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
4909 "A", "MPS TCAM entries");
4911 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
4912 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4913 sysctl_path_mtus, "A", "path MTUs");
4915 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
4916 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4917 sysctl_pm_stats, "A", "PM statistics");
4919 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
4920 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4921 sysctl_rdma_stats, "A", "RDMA statistics");
4923 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
4924 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4925 sysctl_tcp_stats, "A", "TCP statistics");
4927 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
4928 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4929 sysctl_tids, "A", "TID information");
4931 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
4932 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4933 sysctl_tp_err_stats, "A", "TP error statistics");
4935 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
4936 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
4937 "TP logic analyzer event capture mask");
4939 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
4940 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4941 sysctl_tp_la, "A", "TP logic analyzer");
4943 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
4944 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4945 sysctl_tx_rate, "A", "Tx rate");
4947 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
4948 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4949 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
4951 if (chip_id(sc) >= CHELSIO_T5) {
4952 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
4953 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4954 sysctl_wcwr_stats, "A", "write combined work requests");
4959 if (is_offload(sc)) {
4963 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
4964 NULL, "TOE parameters");
4965 children = SYSCTL_CHILDREN(oid);
4967 sc->tt.sndbuf = 256 * 1024;
4968 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
4969 &sc->tt.sndbuf, 0, "max hardware send buffer size");
4972 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
4973 &sc->tt.ddp, 0, "DDP allowed");
4975 sc->tt.indsz = G_INDICATESIZE(t4_read_reg(sc, A_TP_PARA_REG5));
4976 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "indsz", CTLFLAG_RW,
4977 &sc->tt.indsz, 0, "DDP max indicate size allowed");
4980 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2));
4981 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp_thres", CTLFLAG_RW,
4982 &sc->tt.ddp_thres, 0, "DDP threshold");
4984 sc->tt.rx_coalesce = 1;
4985 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
4986 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
4988 sc->tt.tx_align = 1;
4989 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
4990 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
4992 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
4993 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
4994 "TP timer tick (us)");
4996 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
4997 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
4998 "TCP timestamp tick (us)");
5000 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
5001 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
5004 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
5005 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
5006 "IU", "DACK timer (us)");
5008 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
5009 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
5010 sysctl_tp_timer, "LU", "Retransmit min (us)");
5012 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
5013 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
5014 sysctl_tp_timer, "LU", "Retransmit max (us)");
5016 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
5017 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
5018 sysctl_tp_timer, "LU", "Persist timer min (us)");
5020 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
5021 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
5022 sysctl_tp_timer, "LU", "Persist timer max (us)");
5024 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
5025 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
5026 sysctl_tp_timer, "LU", "Keepidle idle timer (us)");
5028 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_intvl",
5029 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
5030 sysctl_tp_timer, "LU", "Keepidle interval (us)");
5032 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
5033 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
5034 sysctl_tp_timer, "LU", "Initial SRTT (us)");
5036 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
5037 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
5038 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
5044 vi_sysctls(struct vi_info *vi)
5046 struct sysctl_ctx_list *ctx;
5047 struct sysctl_oid *oid;
5048 struct sysctl_oid_list *children;
5050 ctx = device_get_sysctl_ctx(vi->dev);
5053 * dev.v?(cxgbe|cxl).X.
5055 oid = device_get_sysctl_tree(vi->dev);
5056 children = SYSCTL_CHILDREN(oid);
5058 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
5059 vi->viid, "VI identifer");
5060 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
5061 &vi->nrxq, 0, "# of rx queues");
5062 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
5063 &vi->ntxq, 0, "# of tx queues");
5064 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
5065 &vi->first_rxq, 0, "index of first rx queue");
5066 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
5067 &vi->first_txq, 0, "index of first tx queue");
5068 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rss_size", CTLFLAG_RD, NULL,
5069 vi->rss_size, "size of RSS indirection table");
5071 if (IS_MAIN_VI(vi)) {
5072 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
5073 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
5074 "Reserve queue 0 for non-flowid packets");
5078 if (vi->nofldrxq != 0) {
5079 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
5081 "# of rx queues for offloaded TCP connections");
5082 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
5084 "# of tx queues for offloaded TCP connections");
5085 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
5086 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
5087 "index of first TOE rx queue");
5088 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
5089 CTLFLAG_RD, &vi->first_ofld_txq, 0,
5090 "index of first TOE tx queue");
5094 if (vi->nnmrxq != 0) {
5095 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
5096 &vi->nnmrxq, 0, "# of netmap rx queues");
5097 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
5098 &vi->nnmtxq, 0, "# of netmap tx queues");
5099 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
5100 CTLFLAG_RD, &vi->first_nm_rxq, 0,
5101 "index of first netmap rx queue");
5102 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
5103 CTLFLAG_RD, &vi->first_nm_txq, 0,
5104 "index of first netmap tx queue");
5108 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
5109 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
5110 "holdoff timer index");
5111 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
5112 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
5113 "holdoff packet counter index");
5115 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
5116 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
5118 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
5119 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
5124 cxgbe_sysctls(struct port_info *pi)
5126 struct sysctl_ctx_list *ctx;
5127 struct sysctl_oid *oid;
5128 struct sysctl_oid_list *children, *children2;
5129 struct adapter *sc = pi->adapter;
5133 ctx = device_get_sysctl_ctx(pi->dev);
5138 oid = device_get_sysctl_tree(pi->dev);
5139 children = SYSCTL_CHILDREN(oid);
5141 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
5142 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
5143 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
5144 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
5145 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
5146 "PHY temperature (in Celsius)");
5147 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
5148 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
5149 "PHY firmware version");
5152 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
5153 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_pause_settings, "A",
5154 "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)");
5155 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fec",
5156 CTLTYPE_STRING | CTLFLAG_RW, pi, 0, sysctl_fec, "A",
5157 "Forward Error Correction (bit 0 = RS, bit 1 = BASER_RS)");
5158 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "autoneg",
5159 CTLTYPE_INT | CTLFLAG_RW, pi, 0, sysctl_autoneg, "I",
5160 "autonegotiation (-1 = not supported)");
5162 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
5163 port_top_speed(pi), "max speed (in Gbps)");
5165 if (sc->flags & IS_VF)
5169 * dev.(cxgbe|cxl).X.tc.
5171 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
5172 "Tx scheduler traffic classes");
5173 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
5174 struct tx_sched_class *tc = &pi->tc[i];
5176 snprintf(name, sizeof(name), "%d", i);
5177 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
5178 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
5180 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD,
5181 &tc->flags, 0, "flags");
5182 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
5183 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
5185 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
5186 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
5187 sysctl_tc_params, "A", "traffic class parameters");
5192 * dev.cxgbe.X.stats.
5194 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
5195 NULL, "port statistics");
5196 children = SYSCTL_CHILDREN(oid);
5197 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
5198 &pi->tx_parse_error, 0,
5199 "# of tx packets with invalid length or # of segments");
5201 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
5202 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
5203 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
5204 sysctl_handle_t4_reg64, "QU", desc)
5206 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
5207 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
5208 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
5209 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
5210 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
5211 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
5212 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
5213 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
5214 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
5215 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
5216 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
5217 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
5218 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
5219 "# of tx frames in this range",
5220 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
5221 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
5222 "# of tx frames in this range",
5223 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
5224 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
5225 "# of tx frames in this range",
5226 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
5227 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
5228 "# of tx frames in this range",
5229 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
5230 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
5231 "# of tx frames in this range",
5232 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
5233 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
5234 "# of tx frames in this range",
5235 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
5236 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
5237 "# of tx frames in this range",
5238 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
5239 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
5240 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
5241 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
5242 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
5243 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
5244 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
5245 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
5246 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
5247 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
5248 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
5249 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
5250 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
5251 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
5252 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
5253 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
5254 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
5255 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
5256 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
5257 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
5258 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
5260 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
5261 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
5262 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
5263 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
5264 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
5265 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
5266 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
5267 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
5268 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
5269 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
5270 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
5271 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
5272 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
5273 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
5274 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
5275 "# of frames received with bad FCS",
5276 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
5277 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
5278 "# of frames received with length error",
5279 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
5280 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
5281 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
5282 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
5283 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
5284 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
5285 "# of rx frames in this range",
5286 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
5287 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
5288 "# of rx frames in this range",
5289 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
5290 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
5291 "# of rx frames in this range",
5292 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
5293 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
5294 "# of rx frames in this range",
5295 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
5296 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
5297 "# of rx frames in this range",
5298 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
5299 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
5300 "# of rx frames in this range",
5301 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
5302 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
5303 "# of rx frames in this range",
5304 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
5305 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
5306 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
5307 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
5308 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
5309 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
5310 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
5311 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
5312 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
5313 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
5314 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
5315 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
5316 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
5317 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
5318 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
5319 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
5320 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
5321 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
5322 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
5324 #undef SYSCTL_ADD_T4_REG64
5326 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
5327 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
5328 &pi->stats.name, desc)
5330 /* We get these from port_stats and they may be stale by upto 1s */
5331 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
5332 "# drops due to buffer-group 0 overflows");
5333 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
5334 "# drops due to buffer-group 1 overflows");
5335 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
5336 "# drops due to buffer-group 2 overflows");
5337 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
5338 "# drops due to buffer-group 3 overflows");
5339 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
5340 "# of buffer-group 0 truncated packets");
5341 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
5342 "# of buffer-group 1 truncated packets");
5343 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
5344 "# of buffer-group 2 truncated packets");
5345 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
5346 "# of buffer-group 3 truncated packets");
5348 #undef SYSCTL_ADD_T4_PORTSTAT
5352 sysctl_int_array(SYSCTL_HANDLER_ARGS)
5354 int rc, *i, space = 0;
5357 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5358 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
5360 sbuf_printf(&sb, " ");
5361 sbuf_printf(&sb, "%d", *i);
5365 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5371 sysctl_bitfield(SYSCTL_HANDLER_ARGS)
5376 rc = sysctl_wire_old_buffer(req, 0);
5380 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5384 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
5385 rc = sbuf_finish(sb);
5392 sysctl_btphy(SYSCTL_HANDLER_ARGS)
5394 struct port_info *pi = arg1;
5396 struct adapter *sc = pi->adapter;
5400 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
5403 /* XXX: magic numbers */
5404 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
5406 end_synchronized_op(sc, 0);
5412 rc = sysctl_handle_int(oidp, &v, 0, req);
5417 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
5419 struct vi_info *vi = arg1;
5422 val = vi->rsrv_noflowq;
5423 rc = sysctl_handle_int(oidp, &val, 0, req);
5424 if (rc != 0 || req->newptr == NULL)
5427 if ((val >= 1) && (vi->ntxq > 1))
5428 vi->rsrv_noflowq = 1;
5430 vi->rsrv_noflowq = 0;
5436 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
5438 struct vi_info *vi = arg1;
5439 struct adapter *sc = vi->pi->adapter;
5441 struct sge_rxq *rxq;
5443 struct sge_ofld_rxq *ofld_rxq;
5449 rc = sysctl_handle_int(oidp, &idx, 0, req);
5450 if (rc != 0 || req->newptr == NULL)
5453 if (idx < 0 || idx >= SGE_NTIMERS)
5456 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5461 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
5462 for_each_rxq(vi, i, rxq) {
5463 #ifdef atomic_store_rel_8
5464 atomic_store_rel_8(&rxq->iq.intr_params, v);
5466 rxq->iq.intr_params = v;
5470 for_each_ofld_rxq(vi, i, ofld_rxq) {
5471 #ifdef atomic_store_rel_8
5472 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
5474 ofld_rxq->iq.intr_params = v;
5480 end_synchronized_op(sc, LOCK_HELD);
5485 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
5487 struct vi_info *vi = arg1;
5488 struct adapter *sc = vi->pi->adapter;
5493 rc = sysctl_handle_int(oidp, &idx, 0, req);
5494 if (rc != 0 || req->newptr == NULL)
5497 if (idx < -1 || idx >= SGE_NCOUNTERS)
5500 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5505 if (vi->flags & VI_INIT_DONE)
5506 rc = EBUSY; /* cannot be changed once the queues are created */
5510 end_synchronized_op(sc, LOCK_HELD);
5515 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
5517 struct vi_info *vi = arg1;
5518 struct adapter *sc = vi->pi->adapter;
5521 qsize = vi->qsize_rxq;
5523 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5524 if (rc != 0 || req->newptr == NULL)
5527 if (qsize < 128 || (qsize & 7))
5530 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5535 if (vi->flags & VI_INIT_DONE)
5536 rc = EBUSY; /* cannot be changed once the queues are created */
5538 vi->qsize_rxq = qsize;
5540 end_synchronized_op(sc, LOCK_HELD);
5545 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
5547 struct vi_info *vi = arg1;
5548 struct adapter *sc = vi->pi->adapter;
5551 qsize = vi->qsize_txq;
5553 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5554 if (rc != 0 || req->newptr == NULL)
5557 if (qsize < 128 || qsize > 65536)
5560 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5565 if (vi->flags & VI_INIT_DONE)
5566 rc = EBUSY; /* cannot be changed once the queues are created */
5568 vi->qsize_txq = qsize;
5570 end_synchronized_op(sc, LOCK_HELD);
5575 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
5577 struct port_info *pi = arg1;
5578 struct adapter *sc = pi->adapter;
5579 struct link_config *lc = &pi->link_cfg;
5582 if (req->newptr == NULL) {
5584 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX";
5586 rc = sysctl_wire_old_buffer(req, 0);
5590 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5594 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits);
5595 rc = sbuf_finish(sb);
5601 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX));
5604 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
5610 if (s[0] < '0' || s[0] > '9')
5611 return (EINVAL); /* not a number */
5613 if (n & ~(PAUSE_TX | PAUSE_RX))
5614 return (EINVAL); /* some other bit is set too */
5616 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
5620 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) {
5621 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX);
5622 lc->requested_fc |= n;
5623 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5625 end_synchronized_op(sc, 0);
5632 sysctl_fec(SYSCTL_HANDLER_ARGS)
5634 struct port_info *pi = arg1;
5635 struct adapter *sc = pi->adapter;
5636 struct link_config *lc = &pi->link_cfg;
5639 if (req->newptr == NULL) {
5641 static char *bits = "\20\1RS\2BASER_RS\3RESERVED";
5643 rc = sysctl_wire_old_buffer(req, 0);
5647 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5651 sbuf_printf(sb, "%b", lc->fec & M_FW_PORT_CAP_FEC, bits);
5652 rc = sbuf_finish(sb);
5658 s[0] = '0' + (lc->requested_fec & M_FW_PORT_CAP_FEC);
5661 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
5667 if (s[0] < '0' || s[0] > '9')
5668 return (EINVAL); /* not a number */
5670 if (n & ~M_FW_PORT_CAP_FEC)
5671 return (EINVAL); /* some other bit is set too */
5673 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
5677 if ((lc->requested_fec & M_FW_PORT_CAP_FEC) != n) {
5678 lc->requested_fec = n &
5679 G_FW_PORT_CAP_FEC(lc->supported);
5680 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5682 end_synchronized_op(sc, 0);
5689 sysctl_autoneg(SYSCTL_HANDLER_ARGS)
5691 struct port_info *pi = arg1;
5692 struct adapter *sc = pi->adapter;
5693 struct link_config *lc = &pi->link_cfg;
5696 if (lc->supported & FW_PORT_CAP_ANEG)
5697 val = lc->autoneg == AUTONEG_ENABLE ? 1 : 0;
5700 rc = sysctl_handle_int(oidp, &val, 0, req);
5701 if (rc != 0 || req->newptr == NULL)
5703 if ((lc->supported & FW_PORT_CAP_ANEG) == 0)
5706 val = val ? AUTONEG_ENABLE : AUTONEG_DISABLE;
5707 if (lc->autoneg == val)
5708 return (0); /* no change */
5710 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
5716 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5723 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
5725 struct adapter *sc = arg1;
5729 val = t4_read_reg64(sc, reg);
5731 return (sysctl_handle_64(oidp, &val, 0, req));
5735 sysctl_temperature(SYSCTL_HANDLER_ARGS)
5737 struct adapter *sc = arg1;
5739 uint32_t param, val;
5741 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
5744 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5745 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5746 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
5747 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5748 end_synchronized_op(sc, 0);
5752 /* unknown is returned as 0 but we display -1 in that case */
5753 t = val == 0 ? -1 : val;
5755 rc = sysctl_handle_int(oidp, &t, 0, req);
5761 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
5763 struct adapter *sc = arg1;
5766 uint16_t incr[NMTUS][NCCTRL_WIN];
5767 static const char *dec_fac[] = {
5768 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
5772 rc = sysctl_wire_old_buffer(req, 0);
5776 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5780 t4_read_cong_tbl(sc, incr);
5782 for (i = 0; i < NCCTRL_WIN; ++i) {
5783 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
5784 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
5785 incr[5][i], incr[6][i], incr[7][i]);
5786 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
5787 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
5788 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
5789 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
5792 rc = sbuf_finish(sb);
5798 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
5799 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
5800 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
5801 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
5805 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
5807 struct adapter *sc = arg1;
5809 int rc, i, n, qid = arg2;
5812 u_int cim_num_obq = sc->chip_params->cim_num_obq;
5814 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
5815 ("%s: bad qid %d\n", __func__, qid));
5817 if (qid < CIM_NUM_IBQ) {
5820 n = 4 * CIM_IBQ_SIZE;
5821 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5822 rc = t4_read_cim_ibq(sc, qid, buf, n);
5824 /* outbound queue */
5827 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
5828 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5829 rc = t4_read_cim_obq(sc, qid, buf, n);
5836 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
5838 rc = sysctl_wire_old_buffer(req, 0);
5842 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5848 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
5849 for (i = 0, p = buf; i < n; i += 16, p += 4)
5850 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
5853 rc = sbuf_finish(sb);
5861 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
5863 struct adapter *sc = arg1;
5869 MPASS(chip_id(sc) <= CHELSIO_T5);
5871 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5875 rc = sysctl_wire_old_buffer(req, 0);
5879 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5883 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5886 rc = -t4_cim_read_la(sc, buf, NULL);
5890 sbuf_printf(sb, "Status Data PC%s",
5891 cfg & F_UPDBGLACAPTPCONLY ? "" :
5892 " LS0Stat LS0Addr LS0Data");
5894 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
5895 if (cfg & F_UPDBGLACAPTPCONLY) {
5896 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
5898 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
5899 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
5900 p[4] & 0xff, p[5] >> 8);
5901 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
5902 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5903 p[1] & 0xf, p[2] >> 4);
5906 "\n %02x %x%07x %x%07x %08x %08x "
5908 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5909 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
5914 rc = sbuf_finish(sb);
5922 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
5924 struct adapter *sc = arg1;
5930 MPASS(chip_id(sc) > CHELSIO_T5);
5932 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5936 rc = sysctl_wire_old_buffer(req, 0);
5940 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5944 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5947 rc = -t4_cim_read_la(sc, buf, NULL);
5951 sbuf_printf(sb, "Status Inst Data PC%s",
5952 cfg & F_UPDBGLACAPTPCONLY ? "" :
5953 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
5955 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
5956 if (cfg & F_UPDBGLACAPTPCONLY) {
5957 sbuf_printf(sb, "\n %02x %08x %08x %08x",
5958 p[3] & 0xff, p[2], p[1], p[0]);
5959 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
5960 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
5961 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
5962 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
5963 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
5964 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
5967 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
5968 "%08x %08x %08x %08x %08x %08x",
5969 (p[9] >> 16) & 0xff,
5970 p[9] & 0xffff, p[8] >> 16,
5971 p[8] & 0xffff, p[7] >> 16,
5972 p[7] & 0xffff, p[6] >> 16,
5973 p[2], p[1], p[0], p[5], p[4], p[3]);
5977 rc = sbuf_finish(sb);
5985 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
5987 struct adapter *sc = arg1;
5993 rc = sysctl_wire_old_buffer(req, 0);
5997 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6001 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
6004 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
6007 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
6008 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
6012 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
6013 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
6014 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
6015 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
6016 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
6017 (p[1] >> 2) | ((p[2] & 3) << 30),
6018 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
6022 rc = sbuf_finish(sb);
6029 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
6031 struct adapter *sc = arg1;
6037 rc = sysctl_wire_old_buffer(req, 0);
6041 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6045 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
6048 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
6051 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
6052 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
6053 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
6054 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
6055 p[4], p[3], p[2], p[1], p[0]);
6058 sbuf_printf(sb, "\n\nCntl ID Data");
6059 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
6060 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
6061 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
6064 rc = sbuf_finish(sb);
6071 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
6073 struct adapter *sc = arg1;
6076 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
6077 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
6078 uint16_t thres[CIM_NUM_IBQ];
6079 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
6080 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
6081 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
6083 cim_num_obq = sc->chip_params->cim_num_obq;
6085 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
6086 obq_rdaddr = A_UP_OBQ_0_REALADDR;
6088 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
6089 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
6091 nq = CIM_NUM_IBQ + cim_num_obq;
6093 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
6095 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
6099 t4_read_cimq_cfg(sc, base, size, thres);
6101 rc = sysctl_wire_old_buffer(req, 0);
6105 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
6110 " Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
6112 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
6113 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
6114 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
6115 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
6116 G_QUEREMFLITS(p[2]) * 16);
6117 for ( ; i < nq; i++, p += 4, wr += 2)
6118 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
6119 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
6120 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
6121 G_QUEREMFLITS(p[2]) * 16);
6123 rc = sbuf_finish(sb);
6130 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
6132 struct adapter *sc = arg1;
6135 struct tp_cpl_stats stats;
6137 rc = sysctl_wire_old_buffer(req, 0);
6141 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6145 mtx_lock(&sc->reg_lock);
6146 t4_tp_get_cpl_stats(sc, &stats);
6147 mtx_unlock(&sc->reg_lock);
6149 if (sc->chip_params->nchan > 2) {
6150 sbuf_printf(sb, " channel 0 channel 1"
6151 " channel 2 channel 3");
6152 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
6153 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
6154 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
6155 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
6157 sbuf_printf(sb, " channel 0 channel 1");
6158 sbuf_printf(sb, "\nCPL requests: %10u %10u",
6159 stats.req[0], stats.req[1]);
6160 sbuf_printf(sb, "\nCPL responses: %10u %10u",
6161 stats.rsp[0], stats.rsp[1]);
6164 rc = sbuf_finish(sb);
6171 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
6173 struct adapter *sc = arg1;
6176 struct tp_usm_stats stats;
6178 rc = sysctl_wire_old_buffer(req, 0);
6182 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6186 t4_get_usm_stats(sc, &stats);
6188 sbuf_printf(sb, "Frames: %u\n", stats.frames);
6189 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
6190 sbuf_printf(sb, "Drops: %u", stats.drops);
6192 rc = sbuf_finish(sb);
6198 static const char * const devlog_level_strings[] = {
6199 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
6200 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
6201 [FW_DEVLOG_LEVEL_ERR] = "ERR",
6202 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
6203 [FW_DEVLOG_LEVEL_INFO] = "INFO",
6204 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
6207 static const char * const devlog_facility_strings[] = {
6208 [FW_DEVLOG_FACILITY_CORE] = "CORE",
6209 [FW_DEVLOG_FACILITY_CF] = "CF",
6210 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
6211 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
6212 [FW_DEVLOG_FACILITY_RES] = "RES",
6213 [FW_DEVLOG_FACILITY_HW] = "HW",
6214 [FW_DEVLOG_FACILITY_FLR] = "FLR",
6215 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
6216 [FW_DEVLOG_FACILITY_PHY] = "PHY",
6217 [FW_DEVLOG_FACILITY_MAC] = "MAC",
6218 [FW_DEVLOG_FACILITY_PORT] = "PORT",
6219 [FW_DEVLOG_FACILITY_VI] = "VI",
6220 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
6221 [FW_DEVLOG_FACILITY_ACL] = "ACL",
6222 [FW_DEVLOG_FACILITY_TM] = "TM",
6223 [FW_DEVLOG_FACILITY_QFC] = "QFC",
6224 [FW_DEVLOG_FACILITY_DCB] = "DCB",
6225 [FW_DEVLOG_FACILITY_ETH] = "ETH",
6226 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
6227 [FW_DEVLOG_FACILITY_RI] = "RI",
6228 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
6229 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
6230 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
6231 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
6232 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
6236 sysctl_devlog(SYSCTL_HANDLER_ARGS)
6238 struct adapter *sc = arg1;
6239 struct devlog_params *dparams = &sc->params.devlog;
6240 struct fw_devlog_e *buf, *e;
6241 int i, j, rc, nentries, first = 0;
6243 uint64_t ftstamp = UINT64_MAX;
6245 if (dparams->addr == 0)
6248 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
6252 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
6256 nentries = dparams->size / sizeof(struct fw_devlog_e);
6257 for (i = 0; i < nentries; i++) {
6260 if (e->timestamp == 0)
6263 e->timestamp = be64toh(e->timestamp);
6264 e->seqno = be32toh(e->seqno);
6265 for (j = 0; j < 8; j++)
6266 e->params[j] = be32toh(e->params[j]);
6268 if (e->timestamp < ftstamp) {
6269 ftstamp = e->timestamp;
6274 if (buf[first].timestamp == 0)
6275 goto done; /* nothing in the log */
6277 rc = sysctl_wire_old_buffer(req, 0);
6281 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6286 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
6287 "Seq#", "Tstamp", "Level", "Facility", "Message");
6292 if (e->timestamp == 0)
6295 sbuf_printf(sb, "%10d %15ju %8s %8s ",
6296 e->seqno, e->timestamp,
6297 (e->level < nitems(devlog_level_strings) ?
6298 devlog_level_strings[e->level] : "UNKNOWN"),
6299 (e->facility < nitems(devlog_facility_strings) ?
6300 devlog_facility_strings[e->facility] : "UNKNOWN"));
6301 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
6302 e->params[2], e->params[3], e->params[4],
6303 e->params[5], e->params[6], e->params[7]);
6305 if (++i == nentries)
6307 } while (i != first);
6309 rc = sbuf_finish(sb);
6317 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
6319 struct adapter *sc = arg1;
6322 struct tp_fcoe_stats stats[MAX_NCHAN];
6323 int i, nchan = sc->chip_params->nchan;
6325 rc = sysctl_wire_old_buffer(req, 0);
6329 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6333 for (i = 0; i < nchan; i++)
6334 t4_get_fcoe_stats(sc, i, &stats[i]);
6337 sbuf_printf(sb, " channel 0 channel 1"
6338 " channel 2 channel 3");
6339 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
6340 stats[0].octets_ddp, stats[1].octets_ddp,
6341 stats[2].octets_ddp, stats[3].octets_ddp);
6342 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
6343 stats[0].frames_ddp, stats[1].frames_ddp,
6344 stats[2].frames_ddp, stats[3].frames_ddp);
6345 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
6346 stats[0].frames_drop, stats[1].frames_drop,
6347 stats[2].frames_drop, stats[3].frames_drop);
6349 sbuf_printf(sb, " channel 0 channel 1");
6350 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
6351 stats[0].octets_ddp, stats[1].octets_ddp);
6352 sbuf_printf(sb, "\nframesDDP: %16u %16u",
6353 stats[0].frames_ddp, stats[1].frames_ddp);
6354 sbuf_printf(sb, "\nframesDrop: %16u %16u",
6355 stats[0].frames_drop, stats[1].frames_drop);
6358 rc = sbuf_finish(sb);
6365 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
6367 struct adapter *sc = arg1;
6370 unsigned int map, kbps, ipg, mode;
6371 unsigned int pace_tab[NTX_SCHED];
6373 rc = sysctl_wire_old_buffer(req, 0);
6377 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6381 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
6382 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
6383 t4_read_pace_tbl(sc, pace_tab);
6385 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
6386 "Class IPG (0.1 ns) Flow IPG (us)");
6388 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
6389 t4_get_tx_sched(sc, i, &kbps, &ipg);
6390 sbuf_printf(sb, "\n %u %-5s %u ", i,
6391 (mode & (1 << i)) ? "flow" : "class", map & 3);
6393 sbuf_printf(sb, "%9u ", kbps);
6395 sbuf_printf(sb, " disabled ");
6398 sbuf_printf(sb, "%13u ", ipg);
6400 sbuf_printf(sb, " disabled ");
6403 sbuf_printf(sb, "%10u", pace_tab[i]);
6405 sbuf_printf(sb, " disabled");
6408 rc = sbuf_finish(sb);
6415 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
6417 struct adapter *sc = arg1;
6421 struct lb_port_stats s[2];
6422 static const char *stat_name[] = {
6423 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
6424 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
6425 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
6426 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
6427 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
6428 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
6429 "BG2FramesTrunc:", "BG3FramesTrunc:"
6432 rc = sysctl_wire_old_buffer(req, 0);
6436 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6440 memset(s, 0, sizeof(s));
6442 for (i = 0; i < sc->chip_params->nchan; i += 2) {
6443 t4_get_lb_stats(sc, i, &s[0]);
6444 t4_get_lb_stats(sc, i + 1, &s[1]);
6448 sbuf_printf(sb, "%s Loopback %u"
6449 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
6451 for (j = 0; j < nitems(stat_name); j++)
6452 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
6456 rc = sbuf_finish(sb);
6463 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
6466 struct port_info *pi = arg1;
6467 struct link_config *lc = &pi->link_cfg;
6470 rc = sysctl_wire_old_buffer(req, 0);
6473 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
6477 if (lc->link_ok || lc->link_down_rc == 255)
6478 sbuf_printf(sb, "n/a");
6480 sbuf_printf(sb, "%s", t4_link_down_rc_str(lc->link_down_rc));
6482 rc = sbuf_finish(sb);
6495 mem_desc_cmp(const void *a, const void *b)
6497 return ((const struct mem_desc *)a)->base -
6498 ((const struct mem_desc *)b)->base;
6502 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
6510 size = to - from + 1;
6514 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
6515 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
6519 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
6521 struct adapter *sc = arg1;
6524 uint32_t lo, hi, used, alloc;
6525 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
6526 static const char *region[] = {
6527 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
6528 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
6529 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
6530 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
6531 "RQUDP region:", "PBL region:", "TXPBL region:",
6532 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
6535 struct mem_desc avail[4];
6536 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
6537 struct mem_desc *md = mem;
6539 rc = sysctl_wire_old_buffer(req, 0);
6543 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6547 for (i = 0; i < nitems(mem); i++) {
6552 /* Find and sort the populated memory ranges */
6554 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
6555 if (lo & F_EDRAM0_ENABLE) {
6556 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
6557 avail[i].base = G_EDRAM0_BASE(hi) << 20;
6558 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
6562 if (lo & F_EDRAM1_ENABLE) {
6563 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
6564 avail[i].base = G_EDRAM1_BASE(hi) << 20;
6565 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
6569 if (lo & F_EXT_MEM_ENABLE) {
6570 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
6571 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
6572 avail[i].limit = avail[i].base +
6573 (G_EXT_MEM_SIZE(hi) << 20);
6574 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
6577 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
6578 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
6579 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
6580 avail[i].limit = avail[i].base +
6581 (G_EXT_MEM1_SIZE(hi) << 20);
6585 if (!i) /* no memory available */
6587 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
6589 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
6590 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
6591 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
6592 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
6593 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
6594 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
6595 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
6596 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
6597 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
6599 /* the next few have explicit upper bounds */
6600 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
6601 md->limit = md->base - 1 +
6602 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
6603 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
6606 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
6607 md->limit = md->base - 1 +
6608 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
6609 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
6612 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6613 if (chip_id(sc) <= CHELSIO_T5)
6614 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
6616 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
6620 md->idx = nitems(region); /* hide it */
6624 #define ulp_region(reg) \
6625 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
6626 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
6628 ulp_region(RX_ISCSI);
6629 ulp_region(RX_TDDP);
6631 ulp_region(RX_STAG);
6633 ulp_region(RX_RQUDP);
6639 md->idx = nitems(region);
6642 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
6643 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
6646 if (sge_ctrl & F_VFIFO_ENABLE)
6647 size = G_DBVFIFO_SIZE(fifo_size);
6649 size = G_T6_DBVFIFO_SIZE(fifo_size);
6652 md->base = G_BASEADDR(t4_read_reg(sc,
6653 A_SGE_DBVFIFO_BADDR));
6654 md->limit = md->base + (size << 2) - 1;
6659 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
6662 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
6666 md->base = sc->vres.ocq.start;
6667 if (sc->vres.ocq.size)
6668 md->limit = md->base + sc->vres.ocq.size - 1;
6670 md->idx = nitems(region); /* hide it */
6673 /* add any address-space holes, there can be up to 3 */
6674 for (n = 0; n < i - 1; n++)
6675 if (avail[n].limit < avail[n + 1].base)
6676 (md++)->base = avail[n].limit;
6678 (md++)->base = avail[n].limit;
6681 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
6683 for (lo = 0; lo < i; lo++)
6684 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
6685 avail[lo].limit - 1);
6687 sbuf_printf(sb, "\n");
6688 for (i = 0; i < n; i++) {
6689 if (mem[i].idx >= nitems(region))
6690 continue; /* skip holes */
6692 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
6693 mem_region_show(sb, region[mem[i].idx], mem[i].base,
6697 sbuf_printf(sb, "\n");
6698 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
6699 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
6700 mem_region_show(sb, "uP RAM:", lo, hi);
6702 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
6703 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
6704 mem_region_show(sb, "uP Extmem2:", lo, hi);
6706 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
6707 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
6709 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
6710 (lo & F_PMRXNUMCHN) ? 2 : 1);
6712 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
6713 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
6714 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
6716 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
6717 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
6718 sbuf_printf(sb, "%u p-structs\n",
6719 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
6721 for (i = 0; i < 4; i++) {
6722 if (chip_id(sc) > CHELSIO_T5)
6723 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
6725 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
6727 used = G_T5_USED(lo);
6728 alloc = G_T5_ALLOC(lo);
6731 alloc = G_ALLOC(lo);
6733 /* For T6 these are MAC buffer groups */
6734 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
6737 for (i = 0; i < sc->chip_params->nchan; i++) {
6738 if (chip_id(sc) > CHELSIO_T5)
6739 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
6741 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
6743 used = G_T5_USED(lo);
6744 alloc = G_T5_ALLOC(lo);
6747 alloc = G_ALLOC(lo);
6749 /* For T6 these are MAC buffer groups */
6751 "\nLoopback %d using %u pages out of %u allocated",
6755 rc = sbuf_finish(sb);
6762 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
6766 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
6770 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
6772 struct adapter *sc = arg1;
6776 MPASS(chip_id(sc) <= CHELSIO_T5);
6778 rc = sysctl_wire_old_buffer(req, 0);
6782 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6787 "Idx Ethernet address Mask Vld Ports PF"
6788 " VF Replication P0 P1 P2 P3 ML");
6789 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6790 uint64_t tcamx, tcamy, mask;
6791 uint32_t cls_lo, cls_hi;
6792 uint8_t addr[ETHER_ADDR_LEN];
6794 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
6795 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
6798 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6799 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6800 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6801 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
6802 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
6803 addr[3], addr[4], addr[5], (uintmax_t)mask,
6804 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
6805 G_PORTMAP(cls_hi), G_PF(cls_lo),
6806 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
6808 if (cls_lo & F_REPLICATE) {
6809 struct fw_ldst_cmd ldst_cmd;
6811 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6812 ldst_cmd.op_to_addrspace =
6813 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6814 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6815 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6816 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6817 ldst_cmd.u.mps.rplc.fid_idx =
6818 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6819 V_FW_LDST_CMD_IDX(i));
6821 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6825 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6826 sizeof(ldst_cmd), &ldst_cmd);
6827 end_synchronized_op(sc, 0);
6830 sbuf_printf(sb, "%36d", rc);
6833 sbuf_printf(sb, " %08x %08x %08x %08x",
6834 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6835 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6836 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6837 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6840 sbuf_printf(sb, "%36s", "");
6842 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
6843 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
6844 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
6848 (void) sbuf_finish(sb);
6850 rc = sbuf_finish(sb);
6857 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
6859 struct adapter *sc = arg1;
6863 MPASS(chip_id(sc) > CHELSIO_T5);
6865 rc = sysctl_wire_old_buffer(req, 0);
6869 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6873 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
6874 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
6876 " P0 P1 P2 P3 ML\n");
6878 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6879 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
6881 uint64_t tcamx, tcamy, val, mask;
6882 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
6883 uint8_t addr[ETHER_ADDR_LEN];
6885 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
6887 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
6889 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
6890 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6891 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6892 tcamy = G_DMACH(val) << 32;
6893 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6894 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6895 lookup_type = G_DATALKPTYPE(data2);
6896 port_num = G_DATAPORTNUM(data2);
6897 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6898 /* Inner header VNI */
6899 vniy = ((data2 & F_DATAVIDH2) << 23) |
6900 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6901 dip_hit = data2 & F_DATADIPHIT;
6906 vlan_vld = data2 & F_DATAVIDH2;
6907 ivlan = G_VIDL(val);
6910 ctl |= V_CTLXYBITSEL(1);
6911 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6912 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6913 tcamx = G_DMACH(val) << 32;
6914 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6915 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6916 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6917 /* Inner header VNI mask */
6918 vnix = ((data2 & F_DATAVIDH2) << 23) |
6919 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6925 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6927 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6928 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6930 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6931 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6932 "%012jx %06x %06x - - %3c"
6933 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
6934 addr[1], addr[2], addr[3], addr[4], addr[5],
6935 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
6936 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6937 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6938 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6940 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6941 "%012jx - - ", i, addr[0], addr[1],
6942 addr[2], addr[3], addr[4], addr[5],
6946 sbuf_printf(sb, "%4u Y ", ivlan);
6948 sbuf_printf(sb, " - N ");
6950 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
6951 lookup_type ? 'I' : 'O', port_num,
6952 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6953 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6954 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6958 if (cls_lo & F_T6_REPLICATE) {
6959 struct fw_ldst_cmd ldst_cmd;
6961 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6962 ldst_cmd.op_to_addrspace =
6963 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6964 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6965 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6966 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6967 ldst_cmd.u.mps.rplc.fid_idx =
6968 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6969 V_FW_LDST_CMD_IDX(i));
6971 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6975 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6976 sizeof(ldst_cmd), &ldst_cmd);
6977 end_synchronized_op(sc, 0);
6980 sbuf_printf(sb, "%72d", rc);
6983 sbuf_printf(sb, " %08x %08x %08x %08x"
6984 " %08x %08x %08x %08x",
6985 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
6986 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
6987 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
6988 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
6989 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6990 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6991 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6992 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6995 sbuf_printf(sb, "%72s", "");
6997 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
6998 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
6999 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
7000 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
7004 (void) sbuf_finish(sb);
7006 rc = sbuf_finish(sb);
7013 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
7015 struct adapter *sc = arg1;
7018 uint16_t mtus[NMTUS];
7020 rc = sysctl_wire_old_buffer(req, 0);
7024 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7028 t4_read_mtu_tbl(sc, mtus, NULL);
7030 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
7031 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
7032 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
7033 mtus[14], mtus[15]);
7035 rc = sbuf_finish(sb);
7042 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
7044 struct adapter *sc = arg1;
7047 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
7048 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
7049 static const char *tx_stats[MAX_PM_NSTATS] = {
7050 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
7051 "Tx FIFO wait", NULL, "Tx latency"
7053 static const char *rx_stats[MAX_PM_NSTATS] = {
7054 "Read:", "Write bypass:", "Write mem:", "Flush:",
7055 "Rx FIFO wait", NULL, "Rx latency"
7058 rc = sysctl_wire_old_buffer(req, 0);
7062 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7066 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
7067 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
7069 sbuf_printf(sb, " Tx pcmds Tx bytes");
7070 for (i = 0; i < 4; i++) {
7071 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
7075 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
7076 for (i = 0; i < 4; i++) {
7077 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
7081 if (chip_id(sc) > CHELSIO_T5) {
7083 "\n Total wait Total occupancy");
7084 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
7086 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
7090 MPASS(i < nitems(tx_stats));
7093 "\n Reads Total wait");
7094 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
7096 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
7100 rc = sbuf_finish(sb);
7107 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
7109 struct adapter *sc = arg1;
7112 struct tp_rdma_stats stats;
7114 rc = sysctl_wire_old_buffer(req, 0);
7118 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7122 mtx_lock(&sc->reg_lock);
7123 t4_tp_get_rdma_stats(sc, &stats);
7124 mtx_unlock(&sc->reg_lock);
7126 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
7127 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
7129 rc = sbuf_finish(sb);
7136 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
7138 struct adapter *sc = arg1;
7141 struct tp_tcp_stats v4, v6;
7143 rc = sysctl_wire_old_buffer(req, 0);
7147 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7151 mtx_lock(&sc->reg_lock);
7152 t4_tp_get_tcp_stats(sc, &v4, &v6);
7153 mtx_unlock(&sc->reg_lock);
7157 sbuf_printf(sb, "OutRsts: %20u %20u\n",
7158 v4.tcp_out_rsts, v6.tcp_out_rsts);
7159 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
7160 v4.tcp_in_segs, v6.tcp_in_segs);
7161 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
7162 v4.tcp_out_segs, v6.tcp_out_segs);
7163 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
7164 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
7166 rc = sbuf_finish(sb);
7173 sysctl_tids(SYSCTL_HANDLER_ARGS)
7175 struct adapter *sc = arg1;
7178 struct tid_info *t = &sc->tids;
7180 rc = sysctl_wire_old_buffer(req, 0);
7184 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7189 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
7194 sbuf_printf(sb, "TID range: ");
7195 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
7198 if (chip_id(sc) <= CHELSIO_T5) {
7199 b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
7200 hb = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
7202 b = t4_read_reg(sc, A_LE_DB_SRVR_START_INDEX);
7203 hb = t4_read_reg(sc, A_T6_LE_DB_HASH_TID_BASE);
7207 sbuf_printf(sb, "0-%u, ", b - 1);
7208 sbuf_printf(sb, "%u-%u", hb, t->ntids - 1);
7210 sbuf_printf(sb, "0-%u", t->ntids - 1);
7211 sbuf_printf(sb, ", in use: %u\n",
7212 atomic_load_acq_int(&t->tids_in_use));
7216 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
7217 t->stid_base + t->nstids - 1, t->stids_in_use);
7221 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
7222 t->ftid_base + t->nftids - 1);
7226 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base,
7227 t->etid_base + t->netids - 1);
7230 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
7231 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
7232 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
7234 rc = sbuf_finish(sb);
7241 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
7243 struct adapter *sc = arg1;
7246 struct tp_err_stats stats;
7248 rc = sysctl_wire_old_buffer(req, 0);
7252 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7256 mtx_lock(&sc->reg_lock);
7257 t4_tp_get_err_stats(sc, &stats);
7258 mtx_unlock(&sc->reg_lock);
7260 if (sc->chip_params->nchan > 2) {
7261 sbuf_printf(sb, " channel 0 channel 1"
7262 " channel 2 channel 3\n");
7263 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
7264 stats.mac_in_errs[0], stats.mac_in_errs[1],
7265 stats.mac_in_errs[2], stats.mac_in_errs[3]);
7266 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
7267 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
7268 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
7269 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
7270 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
7271 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
7272 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
7273 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
7274 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
7275 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
7276 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
7277 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
7278 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
7279 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
7280 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
7281 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
7282 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
7283 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
7284 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
7285 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
7286 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
7288 sbuf_printf(sb, " channel 0 channel 1\n");
7289 sbuf_printf(sb, "macInErrs: %10u %10u\n",
7290 stats.mac_in_errs[0], stats.mac_in_errs[1]);
7291 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
7292 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
7293 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
7294 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
7295 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
7296 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
7297 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
7298 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
7299 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
7300 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
7301 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
7302 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
7303 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
7304 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
7307 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
7308 stats.ofld_no_neigh, stats.ofld_cong_defer);
7310 rc = sbuf_finish(sb);
7317 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
7319 struct adapter *sc = arg1;
7320 struct tp_params *tpp = &sc->params.tp;
7324 mask = tpp->la_mask >> 16;
7325 rc = sysctl_handle_int(oidp, &mask, 0, req);
7326 if (rc != 0 || req->newptr == NULL)
7330 tpp->la_mask = mask << 16;
7331 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
7343 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
7349 uint64_t mask = (1ULL << f->width) - 1;
7350 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
7351 ((uintmax_t)v >> f->start) & mask);
7353 if (line_size + len >= 79) {
7355 sbuf_printf(sb, "\n ");
7357 sbuf_printf(sb, "%s ", buf);
7358 line_size += len + 1;
7361 sbuf_printf(sb, "\n");
7364 static const struct field_desc tp_la0[] = {
7365 { "RcfOpCodeOut", 60, 4 },
7367 { "WcfState", 52, 4 },
7368 { "RcfOpcSrcOut", 50, 2 },
7369 { "CRxError", 49, 1 },
7370 { "ERxError", 48, 1 },
7371 { "SanityFailed", 47, 1 },
7372 { "SpuriousMsg", 46, 1 },
7373 { "FlushInputMsg", 45, 1 },
7374 { "FlushInputCpl", 44, 1 },
7375 { "RssUpBit", 43, 1 },
7376 { "RssFilterHit", 42, 1 },
7378 { "InitTcb", 31, 1 },
7379 { "LineNumber", 24, 7 },
7381 { "EdataOut", 22, 1 },
7383 { "CdataOut", 20, 1 },
7384 { "EreadPdu", 19, 1 },
7385 { "CreadPdu", 18, 1 },
7386 { "TunnelPkt", 17, 1 },
7387 { "RcfPeerFin", 16, 1 },
7388 { "RcfReasonOut", 12, 4 },
7389 { "TxCchannel", 10, 2 },
7390 { "RcfTxChannel", 8, 2 },
7391 { "RxEchannel", 6, 2 },
7392 { "RcfRxChannel", 5, 1 },
7393 { "RcfDataOutSrdy", 4, 1 },
7395 { "RxOoDvld", 2, 1 },
7396 { "RxCongestion", 1, 1 },
7397 { "TxCongestion", 0, 1 },
7401 static const struct field_desc tp_la1[] = {
7402 { "CplCmdIn", 56, 8 },
7403 { "CplCmdOut", 48, 8 },
7404 { "ESynOut", 47, 1 },
7405 { "EAckOut", 46, 1 },
7406 { "EFinOut", 45, 1 },
7407 { "ERstOut", 44, 1 },
7412 { "DataIn", 39, 1 },
7413 { "DataInVld", 38, 1 },
7415 { "RxBufEmpty", 36, 1 },
7417 { "RxFbCongestion", 34, 1 },
7418 { "TxFbCongestion", 33, 1 },
7419 { "TxPktSumSrdy", 32, 1 },
7420 { "RcfUlpType", 28, 4 },
7422 { "Ebypass", 26, 1 },
7424 { "Static0", 24, 1 },
7426 { "Cbypass", 22, 1 },
7428 { "CPktOut", 20, 1 },
7429 { "RxPagePoolFull", 18, 2 },
7430 { "RxLpbkPkt", 17, 1 },
7431 { "TxLpbkPkt", 16, 1 },
7432 { "RxVfValid", 15, 1 },
7433 { "SynLearned", 14, 1 },
7434 { "SetDelEntry", 13, 1 },
7435 { "SetInvEntry", 12, 1 },
7436 { "CpcmdDvld", 11, 1 },
7437 { "CpcmdSave", 10, 1 },
7438 { "RxPstructsFull", 8, 2 },
7439 { "EpcmdDvld", 7, 1 },
7440 { "EpcmdFlush", 6, 1 },
7441 { "EpcmdTrimPrefix", 5, 1 },
7442 { "EpcmdTrimPostfix", 4, 1 },
7443 { "ERssIp4Pkt", 3, 1 },
7444 { "ERssIp6Pkt", 2, 1 },
7445 { "ERssTcpUdpPkt", 1, 1 },
7446 { "ERssFceFipPkt", 0, 1 },
7450 static const struct field_desc tp_la2[] = {
7451 { "CplCmdIn", 56, 8 },
7452 { "MpsVfVld", 55, 1 },
7459 { "DataIn", 39, 1 },
7460 { "DataInVld", 38, 1 },
7462 { "RxBufEmpty", 36, 1 },
7464 { "RxFbCongestion", 34, 1 },
7465 { "TxFbCongestion", 33, 1 },
7466 { "TxPktSumSrdy", 32, 1 },
7467 { "RcfUlpType", 28, 4 },
7469 { "Ebypass", 26, 1 },
7471 { "Static0", 24, 1 },
7473 { "Cbypass", 22, 1 },
7475 { "CPktOut", 20, 1 },
7476 { "RxPagePoolFull", 18, 2 },
7477 { "RxLpbkPkt", 17, 1 },
7478 { "TxLpbkPkt", 16, 1 },
7479 { "RxVfValid", 15, 1 },
7480 { "SynLearned", 14, 1 },
7481 { "SetDelEntry", 13, 1 },
7482 { "SetInvEntry", 12, 1 },
7483 { "CpcmdDvld", 11, 1 },
7484 { "CpcmdSave", 10, 1 },
7485 { "RxPstructsFull", 8, 2 },
7486 { "EpcmdDvld", 7, 1 },
7487 { "EpcmdFlush", 6, 1 },
7488 { "EpcmdTrimPrefix", 5, 1 },
7489 { "EpcmdTrimPostfix", 4, 1 },
7490 { "ERssIp4Pkt", 3, 1 },
7491 { "ERssIp6Pkt", 2, 1 },
7492 { "ERssTcpUdpPkt", 1, 1 },
7493 { "ERssFceFipPkt", 0, 1 },
7498 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
7501 field_desc_show(sb, *p, tp_la0);
7505 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
7509 sbuf_printf(sb, "\n");
7510 field_desc_show(sb, p[0], tp_la0);
7511 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7512 field_desc_show(sb, p[1], tp_la0);
7516 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
7520 sbuf_printf(sb, "\n");
7521 field_desc_show(sb, p[0], tp_la0);
7522 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7523 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
7527 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
7529 struct adapter *sc = arg1;
7534 void (*show_func)(struct sbuf *, uint64_t *, int);
7536 rc = sysctl_wire_old_buffer(req, 0);
7540 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7544 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
7546 t4_tp_read_la(sc, buf, NULL);
7549 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
7552 show_func = tp_la_show2;
7556 show_func = tp_la_show3;
7560 show_func = tp_la_show;
7563 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
7564 (*show_func)(sb, p, i);
7566 rc = sbuf_finish(sb);
7573 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
7575 struct adapter *sc = arg1;
7578 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
7580 rc = sysctl_wire_old_buffer(req, 0);
7584 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7588 t4_get_chan_txrate(sc, nrate, orate);
7590 if (sc->chip_params->nchan > 2) {
7591 sbuf_printf(sb, " channel 0 channel 1"
7592 " channel 2 channel 3\n");
7593 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
7594 nrate[0], nrate[1], nrate[2], nrate[3]);
7595 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
7596 orate[0], orate[1], orate[2], orate[3]);
7598 sbuf_printf(sb, " channel 0 channel 1\n");
7599 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
7600 nrate[0], nrate[1]);
7601 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
7602 orate[0], orate[1]);
7605 rc = sbuf_finish(sb);
7612 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
7614 struct adapter *sc = arg1;
7619 rc = sysctl_wire_old_buffer(req, 0);
7623 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7627 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
7630 t4_ulprx_read_la(sc, buf);
7633 sbuf_printf(sb, " Pcmd Type Message"
7635 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
7636 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
7637 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
7640 rc = sbuf_finish(sb);
7647 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
7649 struct adapter *sc = arg1;
7653 MPASS(chip_id(sc) >= CHELSIO_T5);
7655 rc = sysctl_wire_old_buffer(req, 0);
7659 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7663 v = t4_read_reg(sc, A_SGE_STAT_CFG);
7664 if (G_STATSOURCE_T5(v) == 7) {
7667 mode = is_t5(sc) ? G_STATMODE(v) : G_T6_STATMODE(v);
7669 sbuf_printf(sb, "total %d, incomplete %d",
7670 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7671 t4_read_reg(sc, A_SGE_STAT_MATCH));
7672 } else if (mode == 1) {
7673 sbuf_printf(sb, "total %d, data overflow %d",
7674 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7675 t4_read_reg(sc, A_SGE_STAT_MATCH));
7677 sbuf_printf(sb, "unknown mode %d", mode);
7680 rc = sbuf_finish(sb);
7687 sysctl_tc_params(SYSCTL_HANDLER_ARGS)
7689 struct adapter *sc = arg1;
7690 struct tx_sched_class *tc;
7691 struct t4_sched_class_params p;
7693 int i, rc, port_id, flags, mbps, gbps;
7695 rc = sysctl_wire_old_buffer(req, 0);
7699 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7703 port_id = arg2 >> 16;
7704 MPASS(port_id < sc->params.nports);
7705 MPASS(sc->port[port_id] != NULL);
7707 MPASS(i < sc->chip_params->nsched_cls);
7708 tc = &sc->port[port_id]->tc[i];
7710 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7716 end_synchronized_op(sc, LOCK_HELD);
7718 if ((flags & TX_SC_OK) == 0) {
7719 sbuf_printf(sb, "none");
7723 if (p.level == SCHED_CLASS_LEVEL_CL_WRR) {
7724 sbuf_printf(sb, "cl-wrr weight %u", p.weight);
7726 } else if (p.level == SCHED_CLASS_LEVEL_CL_RL)
7727 sbuf_printf(sb, "cl-rl");
7728 else if (p.level == SCHED_CLASS_LEVEL_CH_RL)
7729 sbuf_printf(sb, "ch-rl");
7735 if (p.ratemode == SCHED_CLASS_RATEMODE_REL) {
7736 /* XXX: top speed or actual link speed? */
7737 gbps = port_top_speed(sc->port[port_id]);
7738 sbuf_printf(sb, " %u%% of %uGbps", p.maxrate, gbps);
7740 else if (p.ratemode == SCHED_CLASS_RATEMODE_ABS) {
7741 switch (p.rateunit) {
7742 case SCHED_CLASS_RATEUNIT_BITS:
7743 mbps = p.maxrate / 1000;
7744 gbps = p.maxrate / 1000000;
7745 if (p.maxrate == gbps * 1000000)
7746 sbuf_printf(sb, " %uGbps", gbps);
7747 else if (p.maxrate == mbps * 1000)
7748 sbuf_printf(sb, " %uMbps", mbps);
7750 sbuf_printf(sb, " %uKbps", p.maxrate);
7752 case SCHED_CLASS_RATEUNIT_PKTS:
7753 sbuf_printf(sb, " %upps", p.maxrate);
7762 case SCHED_CLASS_MODE_CLASS:
7763 sbuf_printf(sb, " aggregate");
7765 case SCHED_CLASS_MODE_FLOW:
7766 sbuf_printf(sb, " per-flow");
7775 rc = sbuf_finish(sb);
7784 unit_conv(char *buf, size_t len, u_int val, u_int factor)
7786 u_int rem = val % factor;
7789 snprintf(buf, len, "%u", val / factor);
7791 while (rem % 10 == 0)
7793 snprintf(buf, len, "%u.%u", val / factor, rem);
7798 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
7800 struct adapter *sc = arg1;
7803 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7805 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
7809 re = G_TIMERRESOLUTION(res);
7812 /* TCP timestamp tick */
7813 re = G_TIMESTAMPRESOLUTION(res);
7817 re = G_DELAYEDACKRESOLUTION(res);
7823 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
7825 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
7829 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
7831 struct adapter *sc = arg1;
7832 u_int res, dack_re, v;
7833 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7835 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
7836 dack_re = G_DELAYEDACKRESOLUTION(res);
7837 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
7839 return (sysctl_handle_int(oidp, &v, 0, req));
7843 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
7845 struct adapter *sc = arg1;
7848 u_long tp_tick_us, v;
7849 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7851 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
7852 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
7853 reg == A_TP_KEEP_IDLE || A_TP_KEEP_INTVL || reg == A_TP_INIT_SRTT ||
7854 reg == A_TP_FINWAIT2_TIMER);
7856 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
7857 tp_tick_us = (cclk_ps << tre) / 1000000;
7859 if (reg == A_TP_INIT_SRTT)
7860 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
7862 v = tp_tick_us * t4_read_reg(sc, reg);
7864 return (sysctl_handle_long(oidp, &v, 0, req));
7869 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf)
7873 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
7874 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
7876 if (fconf & F_FRAGMENTATION)
7877 mode |= T4_FILTER_IP_FRAGMENT;
7879 if (fconf & F_MPSHITTYPE)
7880 mode |= T4_FILTER_MPS_HIT_TYPE;
7882 if (fconf & F_MACMATCH)
7883 mode |= T4_FILTER_MAC_IDX;
7885 if (fconf & F_ETHERTYPE)
7886 mode |= T4_FILTER_ETH_TYPE;
7888 if (fconf & F_PROTOCOL)
7889 mode |= T4_FILTER_IP_PROTO;
7892 mode |= T4_FILTER_IP_TOS;
7895 mode |= T4_FILTER_VLAN;
7897 if (fconf & F_VNIC_ID) {
7898 mode |= T4_FILTER_VNIC;
7900 mode |= T4_FILTER_IC_VNIC;
7904 mode |= T4_FILTER_PORT;
7907 mode |= T4_FILTER_FCoE;
7913 mode_to_fconf(uint32_t mode)
7917 if (mode & T4_FILTER_IP_FRAGMENT)
7918 fconf |= F_FRAGMENTATION;
7920 if (mode & T4_FILTER_MPS_HIT_TYPE)
7921 fconf |= F_MPSHITTYPE;
7923 if (mode & T4_FILTER_MAC_IDX)
7924 fconf |= F_MACMATCH;
7926 if (mode & T4_FILTER_ETH_TYPE)
7927 fconf |= F_ETHERTYPE;
7929 if (mode & T4_FILTER_IP_PROTO)
7930 fconf |= F_PROTOCOL;
7932 if (mode & T4_FILTER_IP_TOS)
7935 if (mode & T4_FILTER_VLAN)
7938 if (mode & T4_FILTER_VNIC)
7941 if (mode & T4_FILTER_PORT)
7944 if (mode & T4_FILTER_FCoE)
7951 mode_to_iconf(uint32_t mode)
7954 if (mode & T4_FILTER_IC_VNIC)
7959 static int check_fspec_against_fconf_iconf(struct adapter *sc,
7960 struct t4_filter_specification *fs)
7962 struct tp_params *tpp = &sc->params.tp;
7965 if (fs->val.frag || fs->mask.frag)
7966 fconf |= F_FRAGMENTATION;
7968 if (fs->val.matchtype || fs->mask.matchtype)
7969 fconf |= F_MPSHITTYPE;
7971 if (fs->val.macidx || fs->mask.macidx)
7972 fconf |= F_MACMATCH;
7974 if (fs->val.ethtype || fs->mask.ethtype)
7975 fconf |= F_ETHERTYPE;
7977 if (fs->val.proto || fs->mask.proto)
7978 fconf |= F_PROTOCOL;
7980 if (fs->val.tos || fs->mask.tos)
7983 if (fs->val.vlan_vld || fs->mask.vlan_vld)
7986 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
7988 if (tpp->ingress_config & F_VNIC)
7992 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
7994 if ((tpp->ingress_config & F_VNIC) == 0)
7998 if (fs->val.iport || fs->mask.iport)
8001 if (fs->val.fcoe || fs->mask.fcoe)
8004 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map)
8011 get_filter_mode(struct adapter *sc, uint32_t *mode)
8013 struct tp_params *tpp = &sc->params.tp;
8016 * We trust the cached values of the relevant TP registers. This means
8017 * things work reliably only if writes to those registers are always via
8018 * t4_set_filter_mode.
8020 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config);
8026 set_filter_mode(struct adapter *sc, uint32_t mode)
8028 struct tp_params *tpp = &sc->params.tp;
8029 uint32_t fconf, iconf;
8032 iconf = mode_to_iconf(mode);
8033 if ((iconf ^ tpp->ingress_config) & F_VNIC) {
8035 * For now we just complain if A_TP_INGRESS_CONFIG is not
8036 * already set to the correct value for the requested filter
8037 * mode. It's not clear if it's safe to write to this register
8038 * on the fly. (And we trust the cached value of the register).
8043 fconf = mode_to_fconf(mode);
8045 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
8050 if (sc->tids.ftids_in_use > 0) {
8056 if (uld_active(sc, ULD_TOM)) {
8062 rc = -t4_set_filter_mode(sc, fconf);
8064 end_synchronized_op(sc, LOCK_HELD);
8068 static inline uint64_t
8069 get_filter_hits(struct adapter *sc, uint32_t fid)
8073 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) +
8074 (fid + sc->tids.ftid_base) * TCB_SIZE;
8079 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8);
8080 return (be64toh(hits));
8084 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4);
8085 return (be32toh(hits));
8090 get_filter(struct adapter *sc, struct t4_filter *t)
8092 int i, rc, nfilters = sc->tids.nftids;
8093 struct filter_entry *f;
8095 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
8100 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL ||
8101 t->idx >= nfilters) {
8102 t->idx = 0xffffffff;
8106 f = &sc->tids.ftid_tab[t->idx];
8107 for (i = t->idx; i < nfilters; i++, f++) {
8110 t->l2tidx = f->l2t ? f->l2t->idx : 0;
8111 t->smtidx = f->smtidx;
8113 t->hits = get_filter_hits(sc, t->idx);
8115 t->hits = UINT64_MAX;
8122 t->idx = 0xffffffff;
8124 end_synchronized_op(sc, LOCK_HELD);
8129 set_filter(struct adapter *sc, struct t4_filter *t)
8131 unsigned int nfilters, nports;
8132 struct filter_entry *f;
8135 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf");
8139 nfilters = sc->tids.nftids;
8140 nports = sc->params.nports;
8142 if (nfilters == 0) {
8147 if (t->idx >= nfilters) {
8152 /* Validate against the global filter mode and ingress config */
8153 rc = check_fspec_against_fconf_iconf(sc, &t->fs);
8157 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) {
8162 if (t->fs.val.iport >= nports) {
8167 /* Can't specify an iq if not steering to it */
8168 if (!t->fs.dirsteer && t->fs.iq) {
8173 /* IPv6 filter idx must be 4 aligned */
8174 if (t->fs.type == 1 &&
8175 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) {
8180 if (!(sc->flags & FULL_INIT_DONE) &&
8181 ((rc = adapter_full_init(sc)) != 0))
8184 if (sc->tids.ftid_tab == NULL) {
8185 KASSERT(sc->tids.ftids_in_use == 0,
8186 ("%s: no memory allocated but filters_in_use > 0",
8189 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) *
8190 nfilters, M_CXGBE, M_NOWAIT | M_ZERO);
8191 if (sc->tids.ftid_tab == NULL) {
8195 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF);
8198 for (i = 0; i < 4; i++) {
8199 f = &sc->tids.ftid_tab[t->idx + i];
8201 if (f->pending || f->valid) {
8210 if (t->fs.type == 0)
8214 f = &sc->tids.ftid_tab[t->idx];
8217 rc = set_filter_wr(sc, t->idx);
8219 end_synchronized_op(sc, 0);
8222 mtx_lock(&sc->tids.ftid_lock);
8224 if (f->pending == 0) {
8225 rc = f->valid ? 0 : EIO;
8229 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
8230 PCATCH, "t4setfw", 0)) {
8235 mtx_unlock(&sc->tids.ftid_lock);
8241 del_filter(struct adapter *sc, struct t4_filter *t)
8243 unsigned int nfilters;
8244 struct filter_entry *f;
8247 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf");
8251 nfilters = sc->tids.nftids;
8253 if (nfilters == 0) {
8258 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 ||
8259 t->idx >= nfilters) {
8264 if (!(sc->flags & FULL_INIT_DONE)) {
8269 f = &sc->tids.ftid_tab[t->idx];
8281 t->fs = f->fs; /* extra info for the caller */
8282 rc = del_filter_wr(sc, t->idx);
8286 end_synchronized_op(sc, 0);
8289 mtx_lock(&sc->tids.ftid_lock);
8291 if (f->pending == 0) {
8292 rc = f->valid ? EIO : 0;
8296 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
8297 PCATCH, "t4delfw", 0)) {
8302 mtx_unlock(&sc->tids.ftid_lock);
8309 clear_filter(struct filter_entry *f)
8312 t4_l2t_release(f->l2t);
8314 bzero(f, sizeof (*f));
8318 set_filter_wr(struct adapter *sc, int fidx)
8320 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8321 struct fw_filter_wr *fwr;
8322 unsigned int ftid, vnic_vld, vnic_vld_mask;
8323 struct wrq_cookie cookie;
8325 ASSERT_SYNCHRONIZED_OP(sc);
8327 if (f->fs.newdmac || f->fs.newvlan) {
8328 /* This filter needs an L2T entry; allocate one. */
8329 f->l2t = t4_l2t_alloc_switching(sc->l2t);
8332 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport,
8334 t4_l2t_release(f->l2t);
8340 /* Already validated against fconf, iconf */
8341 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0);
8342 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0);
8343 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld)
8347 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld)
8352 ftid = sc->tids.ftid_base + fidx;
8354 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8357 bzero(fwr, sizeof(*fwr));
8359 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR));
8360 fwr->len16_pkd = htobe32(FW_LEN16(*fwr));
8362 htobe32(V_FW_FILTER_WR_TID(ftid) |
8363 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
8364 V_FW_FILTER_WR_NOREPLY(0) |
8365 V_FW_FILTER_WR_IQ(f->fs.iq));
8366 fwr->del_filter_to_l2tix =
8367 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
8368 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
8369 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
8370 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
8371 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
8372 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
8373 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
8374 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
8375 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
8376 f->fs.newvlan == VLAN_REWRITE) |
8377 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
8378 f->fs.newvlan == VLAN_REWRITE) |
8379 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
8380 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
8381 V_FW_FILTER_WR_PRIO(f->fs.prio) |
8382 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
8383 fwr->ethtype = htobe16(f->fs.val.ethtype);
8384 fwr->ethtypem = htobe16(f->fs.mask.ethtype);
8385 fwr->frag_to_ovlan_vldm =
8386 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
8387 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
8388 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
8389 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) |
8390 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
8391 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask));
8393 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
8394 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
8395 fwr->maci_to_matchtypem =
8396 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
8397 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
8398 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
8399 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
8400 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
8401 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
8402 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
8403 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
8404 fwr->ptcl = f->fs.val.proto;
8405 fwr->ptclm = f->fs.mask.proto;
8406 fwr->ttyp = f->fs.val.tos;
8407 fwr->ttypm = f->fs.mask.tos;
8408 fwr->ivlan = htobe16(f->fs.val.vlan);
8409 fwr->ivlanm = htobe16(f->fs.mask.vlan);
8410 fwr->ovlan = htobe16(f->fs.val.vnic);
8411 fwr->ovlanm = htobe16(f->fs.mask.vnic);
8412 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
8413 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
8414 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
8415 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm));
8416 fwr->lp = htobe16(f->fs.val.dport);
8417 fwr->lpm = htobe16(f->fs.mask.dport);
8418 fwr->fp = htobe16(f->fs.val.sport);
8419 fwr->fpm = htobe16(f->fs.mask.sport);
8421 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma));
8424 sc->tids.ftids_in_use++;
8426 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8431 del_filter_wr(struct adapter *sc, int fidx)
8433 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8434 struct fw_filter_wr *fwr;
8436 struct wrq_cookie cookie;
8438 ftid = sc->tids.ftid_base + fidx;
8440 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8443 bzero(fwr, sizeof (*fwr));
8445 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
8448 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8453 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8455 struct adapter *sc = iq->adapter;
8456 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
8457 unsigned int idx = GET_TID(rpl);
8459 struct filter_entry *f;
8461 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
8463 MPASS(iq == &sc->sge.fwq);
8464 MPASS(is_ftid(sc, idx));
8466 idx -= sc->tids.ftid_base;
8467 f = &sc->tids.ftid_tab[idx];
8468 rc = G_COOKIE(rpl->cookie);
8470 mtx_lock(&sc->tids.ftid_lock);
8471 if (rc == FW_FILTER_WR_FLT_ADDED) {
8472 KASSERT(f->pending, ("%s: filter[%u] isn't pending.",
8474 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
8475 f->pending = 0; /* asynchronous setup completed */
8478 if (rc != FW_FILTER_WR_FLT_DELETED) {
8479 /* Add or delete failed, display an error */
8481 "filter %u setup failed with error %u\n",
8486 sc->tids.ftids_in_use--;
8488 wakeup(&sc->tids.ftid_tab);
8489 mtx_unlock(&sc->tids.ftid_lock);
8495 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8498 MPASS(iq->set_tcb_rpl != NULL);
8499 return (iq->set_tcb_rpl(iq, rss, m));
8503 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8506 MPASS(iq->l2t_write_rpl != NULL);
8507 return (iq->l2t_write_rpl(iq, rss, m));
8511 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
8515 if (cntxt->cid > M_CTXTQID)
8518 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
8519 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
8522 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
8526 if (sc->flags & FW_OK) {
8527 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
8534 * Read via firmware failed or wasn't even attempted. Read directly via
8537 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
8539 end_synchronized_op(sc, 0);
8544 load_fw(struct adapter *sc, struct t4_data *fw)
8549 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
8553 if (sc->flags & FULL_INIT_DONE) {
8558 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
8559 if (fw_data == NULL) {
8564 rc = copyin(fw->data, fw_data, fw->len);
8566 rc = -t4_load_fw(sc, fw_data, fw->len);
8568 free(fw_data, M_CXGBE);
8570 end_synchronized_op(sc, 0);
8575 load_cfg(struct adapter *sc, struct t4_data *cfg)
8578 uint8_t *cfg_data = NULL;
8580 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldcf");
8584 if (cfg->len == 0) {
8586 rc = -t4_load_cfg(sc, NULL, 0);
8590 cfg_data = malloc(cfg->len, M_CXGBE, M_WAITOK);
8591 if (cfg_data == NULL) {
8596 rc = copyin(cfg->data, cfg_data, cfg->len);
8598 rc = -t4_load_cfg(sc, cfg_data, cfg->len);
8600 free(cfg_data, M_CXGBE);
8602 end_synchronized_op(sc, 0);
8606 #define MAX_READ_BUF_SIZE (128 * 1024)
8608 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
8610 uint32_t addr, remaining, n;
8615 rc = validate_mem_range(sc, mr->addr, mr->len);
8619 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
8621 remaining = mr->len;
8622 dst = (void *)mr->data;
8625 n = min(remaining, MAX_READ_BUF_SIZE);
8626 read_via_memwin(sc, 2, addr, buf, n);
8628 rc = copyout(buf, dst, n);
8640 #undef MAX_READ_BUF_SIZE
8643 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
8647 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
8650 if (i2cd->len > sizeof(i2cd->data))
8653 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
8656 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
8657 i2cd->offset, i2cd->len, &i2cd->data[0]);
8658 end_synchronized_op(sc, 0);
8664 in_range(int val, int lo, int hi)
8667 return (val < 0 || (val <= hi && val >= lo));
8671 set_sched_class_config(struct adapter *sc, int minmax)
8678 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4sscc");
8681 rc = -t4_sched_config(sc, FW_SCHED_TYPE_PKTSCHED, minmax, 1);
8682 end_synchronized_op(sc, 0);
8688 set_sched_class_params(struct adapter *sc, struct t4_sched_class_params *p,
8691 int rc, top_speed, fw_level, fw_mode, fw_rateunit, fw_ratemode;
8692 struct port_info *pi;
8693 struct tx_sched_class *tc;
8695 if (p->level == SCHED_CLASS_LEVEL_CL_RL)
8696 fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL;
8697 else if (p->level == SCHED_CLASS_LEVEL_CL_WRR)
8698 fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
8699 else if (p->level == SCHED_CLASS_LEVEL_CH_RL)
8700 fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL;
8704 if (p->mode == SCHED_CLASS_MODE_CLASS)
8705 fw_mode = FW_SCHED_PARAMS_MODE_CLASS;
8706 else if (p->mode == SCHED_CLASS_MODE_FLOW)
8707 fw_mode = FW_SCHED_PARAMS_MODE_FLOW;
8711 if (p->rateunit == SCHED_CLASS_RATEUNIT_BITS)
8712 fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE;
8713 else if (p->rateunit == SCHED_CLASS_RATEUNIT_PKTS)
8714 fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE;
8718 if (p->ratemode == SCHED_CLASS_RATEMODE_REL)
8719 fw_ratemode = FW_SCHED_PARAMS_RATE_REL;
8720 else if (p->ratemode == SCHED_CLASS_RATEMODE_ABS)
8721 fw_ratemode = FW_SCHED_PARAMS_RATE_ABS;
8725 /* Vet our parameters ... */
8726 if (!in_range(p->channel, 0, sc->chip_params->nchan - 1))
8729 pi = sc->port[sc->chan_map[p->channel]];
8732 MPASS(pi->tx_chan == p->channel);
8733 top_speed = port_top_speed(pi) * 1000000; /* Gbps -> Kbps */
8735 if (!in_range(p->cl, 0, sc->chip_params->nsched_cls) ||
8736 !in_range(p->minrate, 0, top_speed) ||
8737 !in_range(p->maxrate, 0, top_speed) ||
8738 !in_range(p->weight, 0, 100))
8742 * Translate any unset parameters into the firmware's
8743 * nomenclature and/or fail the call if the parameters
8746 if (p->rateunit < 0 || p->ratemode < 0 || p->channel < 0 || p->cl < 0)
8751 if (p->maxrate < 0) {
8752 if (p->level == SCHED_CLASS_LEVEL_CL_RL ||
8753 p->level == SCHED_CLASS_LEVEL_CH_RL)
8758 if (p->weight < 0) {
8759 if (p->level == SCHED_CLASS_LEVEL_CL_WRR)
8764 if (p->pktsize < 0) {
8765 if (p->level == SCHED_CLASS_LEVEL_CL_RL ||
8766 p->level == SCHED_CLASS_LEVEL_CH_RL)
8772 rc = begin_synchronized_op(sc, NULL,
8773 sleep_ok ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4sscp");
8776 tc = &pi->tc[p->cl];
8778 rc = -t4_sched_params(sc, FW_SCHED_TYPE_PKTSCHED, fw_level, fw_mode,
8779 fw_rateunit, fw_ratemode, p->channel, p->cl, p->minrate, p->maxrate,
8780 p->weight, p->pktsize, sleep_ok);
8782 tc->flags |= TX_SC_OK;
8785 * Unknown state at this point, see tc->params for what was
8788 tc->flags &= ~TX_SC_OK;
8790 end_synchronized_op(sc, sleep_ok ? 0 : LOCK_HELD);
8796 t4_set_sched_class(struct adapter *sc, struct t4_sched_params *p)
8799 if (p->type != SCHED_CLASS_TYPE_PACKET)
8802 if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG)
8803 return (set_sched_class_config(sc, p->u.config.minmax));
8805 if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS)
8806 return (set_sched_class_params(sc, &p->u.params, 1));
8812 t4_set_sched_queue(struct adapter *sc, struct t4_sched_queue *p)
8814 struct port_info *pi = NULL;
8816 struct sge_txq *txq;
8817 uint32_t fw_mnem, fw_queue, fw_class;
8820 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq");
8824 if (p->port >= sc->params.nports) {
8829 /* XXX: Only supported for the main VI. */
8830 pi = sc->port[p->port];
8832 if (!(vi->flags & VI_INIT_DONE)) {
8833 /* tx queues not set up yet */
8838 if (!in_range(p->queue, 0, vi->ntxq - 1) ||
8839 !in_range(p->cl, 0, sc->chip_params->nsched_cls - 1)) {
8845 * Create a template for the FW_PARAMS_CMD mnemonic and value (TX
8846 * Scheduling Class in this case).
8848 fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
8849 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH));
8850 fw_class = p->cl < 0 ? 0xffffffff : p->cl;
8853 * If op.queue is non-negative, then we're only changing the scheduling
8854 * on a single specified TX queue.
8856 if (p->queue >= 0) {
8857 txq = &sc->sge.txq[vi->first_txq + p->queue];
8858 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8859 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8865 * Change the scheduling on all the TX queues for the
8868 for_each_txq(vi, i, txq) {
8869 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8870 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8878 end_synchronized_op(sc, 0);
8883 t4_os_find_pci_capability(struct adapter *sc, int cap)
8887 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
8891 t4_os_pci_save_state(struct adapter *sc)
8894 struct pci_devinfo *dinfo;
8897 dinfo = device_get_ivars(dev);
8899 pci_cfg_save(dev, dinfo, 0);
8904 t4_os_pci_restore_state(struct adapter *sc)
8907 struct pci_devinfo *dinfo;
8910 dinfo = device_get_ivars(dev);
8912 pci_cfg_restore(dev, dinfo);
8917 t4_os_portmod_changed(const struct adapter *sc, int idx)
8919 struct port_info *pi = sc->port[idx];
8923 static const char *mod_str[] = {
8924 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
8927 for_each_vi(pi, v, vi) {
8928 build_medialist(pi, &vi->media);
8931 ifp = pi->vi[0].ifp;
8932 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
8933 if_printf(ifp, "transceiver unplugged.\n");
8934 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
8935 if_printf(ifp, "unknown transceiver inserted.\n");
8936 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
8937 if_printf(ifp, "unsupported transceiver inserted.\n");
8938 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
8939 if_printf(ifp, "%s transceiver inserted.\n",
8940 mod_str[pi->mod_type]);
8942 if_printf(ifp, "transceiver (type %d) inserted.\n",
8948 t4_os_link_changed(struct adapter *sc, int idx, int link_stat)
8950 struct port_info *pi = sc->port[idx];
8955 for_each_vi(pi, v, vi) {
8961 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed);
8962 if_link_state_change(ifp, LINK_STATE_UP);
8964 if_link_state_change(ifp, LINK_STATE_DOWN);
8970 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
8974 sx_slock(&t4_list_lock);
8975 SLIST_FOREACH(sc, &t4_list, link) {
8977 * func should not make any assumptions about what state sc is
8978 * in - the only guarantee is that sc->sc_lock is a valid lock.
8982 sx_sunlock(&t4_list_lock);
8986 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
8990 struct adapter *sc = dev->si_drv1;
8992 rc = priv_check(td, PRIV_DRIVER);
8997 case CHELSIO_T4_GETREG: {
8998 struct t4_reg *edata = (struct t4_reg *)data;
9000 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9003 if (edata->size == 4)
9004 edata->val = t4_read_reg(sc, edata->addr);
9005 else if (edata->size == 8)
9006 edata->val = t4_read_reg64(sc, edata->addr);
9012 case CHELSIO_T4_SETREG: {
9013 struct t4_reg *edata = (struct t4_reg *)data;
9015 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
9018 if (edata->size == 4) {
9019 if (edata->val & 0xffffffff00000000)
9021 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
9022 } else if (edata->size == 8)
9023 t4_write_reg64(sc, edata->addr, edata->val);
9028 case CHELSIO_T4_REGDUMP: {
9029 struct t4_regdump *regs = (struct t4_regdump *)data;
9030 int reglen = t4_get_regs_len(sc);
9033 if (regs->len < reglen) {
9034 regs->len = reglen; /* hint to the caller */
9039 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
9040 get_regs(sc, regs, buf);
9041 rc = copyout(buf, regs->data, reglen);
9045 case CHELSIO_T4_GET_FILTER_MODE:
9046 rc = get_filter_mode(sc, (uint32_t *)data);
9048 case CHELSIO_T4_SET_FILTER_MODE:
9049 rc = set_filter_mode(sc, *(uint32_t *)data);
9051 case CHELSIO_T4_GET_FILTER:
9052 rc = get_filter(sc, (struct t4_filter *)data);
9054 case CHELSIO_T4_SET_FILTER:
9055 rc = set_filter(sc, (struct t4_filter *)data);
9057 case CHELSIO_T4_DEL_FILTER:
9058 rc = del_filter(sc, (struct t4_filter *)data);
9060 case CHELSIO_T4_GET_SGE_CONTEXT:
9061 rc = get_sge_context(sc, (struct t4_sge_context *)data);
9063 case CHELSIO_T4_LOAD_FW:
9064 rc = load_fw(sc, (struct t4_data *)data);
9066 case CHELSIO_T4_GET_MEM:
9067 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
9069 case CHELSIO_T4_GET_I2C:
9070 rc = read_i2c(sc, (struct t4_i2c_data *)data);
9072 case CHELSIO_T4_CLEAR_STATS: {
9074 u_int port_id = *(uint32_t *)data;
9075 struct port_info *pi;
9078 if (port_id >= sc->params.nports)
9080 pi = sc->port[port_id];
9085 t4_clr_port_stats(sc, pi->tx_chan);
9086 pi->tx_parse_error = 0;
9087 mtx_lock(&sc->reg_lock);
9088 for_each_vi(pi, v, vi) {
9089 if (vi->flags & VI_INIT_DONE)
9090 t4_clr_vi_stats(sc, vi->viid);
9092 mtx_unlock(&sc->reg_lock);
9095 * Since this command accepts a port, clear stats for
9096 * all VIs on this port.
9098 for_each_vi(pi, v, vi) {
9099 if (vi->flags & VI_INIT_DONE) {
9100 struct sge_rxq *rxq;
9101 struct sge_txq *txq;
9102 struct sge_wrq *wrq;
9104 for_each_rxq(vi, i, rxq) {
9105 #if defined(INET) || defined(INET6)
9106 rxq->lro.lro_queued = 0;
9107 rxq->lro.lro_flushed = 0;
9110 rxq->vlan_extraction = 0;
9113 for_each_txq(vi, i, txq) {
9116 txq->vlan_insertion = 0;
9120 txq->txpkts0_wrs = 0;
9121 txq->txpkts1_wrs = 0;
9122 txq->txpkts0_pkts = 0;
9123 txq->txpkts1_pkts = 0;
9124 mp_ring_reset_stats(txq->r);
9128 /* nothing to clear for each ofld_rxq */
9130 for_each_ofld_txq(vi, i, wrq) {
9131 wrq->tx_wrs_direct = 0;
9132 wrq->tx_wrs_copied = 0;
9136 if (IS_MAIN_VI(vi)) {
9137 wrq = &sc->sge.ctrlq[pi->port_id];
9138 wrq->tx_wrs_direct = 0;
9139 wrq->tx_wrs_copied = 0;
9145 case CHELSIO_T4_SCHED_CLASS:
9146 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
9148 case CHELSIO_T4_SCHED_QUEUE:
9149 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
9151 case CHELSIO_T4_GET_TRACER:
9152 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
9154 case CHELSIO_T4_SET_TRACER:
9155 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
9157 case CHELSIO_T4_LOAD_CFG:
9158 rc = load_cfg(sc, (struct t4_data *)data);
9168 t4_db_full(struct adapter *sc)
9171 CXGBE_UNIMPLEMENTED(__func__);
9175 t4_db_dropped(struct adapter *sc)
9178 CXGBE_UNIMPLEMENTED(__func__);
9183 t4_iscsi_init(struct adapter *sc, u_int tag_mask, const u_int *pgsz_order)
9186 t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask);
9187 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) |
9188 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) |
9189 V_HPZ3(pgsz_order[3]));
9193 toe_capability(struct vi_info *vi, int enable)
9196 struct port_info *pi = vi->pi;
9197 struct adapter *sc = pi->adapter;
9199 ASSERT_SYNCHRONIZED_OP(sc);
9201 if (!is_offload(sc))
9205 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
9206 /* TOE is already enabled. */
9211 * We need the port's queues around so that we're able to send
9212 * and receive CPLs to/from the TOE even if the ifnet for this
9213 * port has never been UP'd administratively.
9215 if (!(vi->flags & VI_INIT_DONE)) {
9216 rc = vi_full_init(vi);
9220 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
9221 rc = vi_full_init(&pi->vi[0]);
9226 if (isset(&sc->offload_map, pi->port_id)) {
9227 /* TOE is enabled on another VI of this port. */
9232 if (!uld_active(sc, ULD_TOM)) {
9233 rc = t4_activate_uld(sc, ULD_TOM);
9236 "You must kldload t4_tom.ko before trying "
9237 "to enable TOE on a cxgbe interface.\n");
9241 KASSERT(sc->tom_softc != NULL,
9242 ("%s: TOM activated but softc NULL", __func__));
9243 KASSERT(uld_active(sc, ULD_TOM),
9244 ("%s: TOM activated but flag not set", __func__));
9247 /* Activate iWARP and iSCSI too, if the modules are loaded. */
9248 if (!uld_active(sc, ULD_IWARP))
9249 (void) t4_activate_uld(sc, ULD_IWARP);
9250 if (!uld_active(sc, ULD_ISCSI))
9251 (void) t4_activate_uld(sc, ULD_ISCSI);
9254 setbit(&sc->offload_map, pi->port_id);
9258 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
9261 KASSERT(uld_active(sc, ULD_TOM),
9262 ("%s: TOM never initialized?", __func__));
9263 clrbit(&sc->offload_map, pi->port_id);
9270 * Add an upper layer driver to the global list.
9273 t4_register_uld(struct uld_info *ui)
9278 sx_xlock(&t4_uld_list_lock);
9279 SLIST_FOREACH(u, &t4_uld_list, link) {
9280 if (u->uld_id == ui->uld_id) {
9286 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
9289 sx_xunlock(&t4_uld_list_lock);
9294 t4_unregister_uld(struct uld_info *ui)
9299 sx_xlock(&t4_uld_list_lock);
9301 SLIST_FOREACH(u, &t4_uld_list, link) {
9303 if (ui->refcount > 0) {
9308 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
9314 sx_xunlock(&t4_uld_list_lock);
9319 t4_activate_uld(struct adapter *sc, int id)
9322 struct uld_info *ui;
9324 ASSERT_SYNCHRONIZED_OP(sc);
9326 if (id < 0 || id > ULD_MAX)
9328 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
9330 sx_slock(&t4_uld_list_lock);
9332 SLIST_FOREACH(ui, &t4_uld_list, link) {
9333 if (ui->uld_id == id) {
9334 if (!(sc->flags & FULL_INIT_DONE)) {
9335 rc = adapter_full_init(sc);
9340 rc = ui->activate(sc);
9342 setbit(&sc->active_ulds, id);
9349 sx_sunlock(&t4_uld_list_lock);
9355 t4_deactivate_uld(struct adapter *sc, int id)
9358 struct uld_info *ui;
9360 ASSERT_SYNCHRONIZED_OP(sc);
9362 if (id < 0 || id > ULD_MAX)
9366 sx_slock(&t4_uld_list_lock);
9368 SLIST_FOREACH(ui, &t4_uld_list, link) {
9369 if (ui->uld_id == id) {
9370 rc = ui->deactivate(sc);
9372 clrbit(&sc->active_ulds, id);
9379 sx_sunlock(&t4_uld_list_lock);
9385 uld_active(struct adapter *sc, int uld_id)
9388 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
9390 return (isset(&sc->active_ulds, uld_id));
9395 * Come up with reasonable defaults for some of the tunables, provided they're
9396 * not set by the user (in which case we'll use the values as is).
9399 tweak_tunables(void)
9401 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
9403 if (t4_ntxq10g < 1) {
9405 t4_ntxq10g = rss_getnumbuckets();
9407 t4_ntxq10g = min(nc, NTXQ_10G);
9411 if (t4_ntxq1g < 1) {
9413 /* XXX: way too many for 1GbE? */
9414 t4_ntxq1g = rss_getnumbuckets();
9416 t4_ntxq1g = min(nc, NTXQ_1G);
9421 t4_ntxq_vi = min(nc, NTXQ_VI);
9423 if (t4_nrxq10g < 1) {
9425 t4_nrxq10g = rss_getnumbuckets();
9427 t4_nrxq10g = min(nc, NRXQ_10G);
9431 if (t4_nrxq1g < 1) {
9433 /* XXX: way too many for 1GbE? */
9434 t4_nrxq1g = rss_getnumbuckets();
9436 t4_nrxq1g = min(nc, NRXQ_1G);
9441 t4_nrxq_vi = min(nc, NRXQ_VI);
9444 if (t4_nofldtxq10g < 1)
9445 t4_nofldtxq10g = min(nc, NOFLDTXQ_10G);
9447 if (t4_nofldtxq1g < 1)
9448 t4_nofldtxq1g = min(nc, NOFLDTXQ_1G);
9450 if (t4_nofldtxq_vi < 1)
9451 t4_nofldtxq_vi = min(nc, NOFLDTXQ_VI);
9453 if (t4_nofldrxq10g < 1)
9454 t4_nofldrxq10g = min(nc, NOFLDRXQ_10G);
9456 if (t4_nofldrxq1g < 1)
9457 t4_nofldrxq1g = min(nc, NOFLDRXQ_1G);
9459 if (t4_nofldrxq_vi < 1)
9460 t4_nofldrxq_vi = min(nc, NOFLDRXQ_VI);
9462 if (t4_toecaps_allowed == -1)
9463 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
9465 if (t4_rdmacaps_allowed == -1) {
9466 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
9467 FW_CAPS_CONFIG_RDMA_RDMAC;
9470 if (t4_iscsicaps_allowed == -1) {
9471 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
9472 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
9473 FW_CAPS_CONFIG_ISCSI_T10DIF;
9476 if (t4_toecaps_allowed == -1)
9477 t4_toecaps_allowed = 0;
9479 if (t4_rdmacaps_allowed == -1)
9480 t4_rdmacaps_allowed = 0;
9482 if (t4_iscsicaps_allowed == -1)
9483 t4_iscsicaps_allowed = 0;
9487 if (t4_nnmtxq_vi < 1)
9488 t4_nnmtxq_vi = min(nc, NNMTXQ_VI);
9490 if (t4_nnmrxq_vi < 1)
9491 t4_nnmrxq_vi = min(nc, NNMRXQ_VI);
9494 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS)
9495 t4_tmr_idx_10g = TMR_IDX_10G;
9497 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS)
9498 t4_pktc_idx_10g = PKTC_IDX_10G;
9500 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS)
9501 t4_tmr_idx_1g = TMR_IDX_1G;
9503 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS)
9504 t4_pktc_idx_1g = PKTC_IDX_1G;
9506 if (t4_qsize_txq < 128)
9509 if (t4_qsize_rxq < 128)
9511 while (t4_qsize_rxq & 7)
9514 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
9519 t4_dump_tcb(struct adapter *sc, int tid)
9521 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
9523 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
9524 save = t4_read_reg(sc, reg);
9525 base = sc->memwin[2].mw_base;
9527 /* Dump TCB for the tid */
9528 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
9529 tcb_addr += tid * TCB_SIZE;
9533 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
9535 pf = V_PFNUM(sc->pf);
9536 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
9538 t4_write_reg(sc, reg, win_pos | pf);
9539 t4_read_reg(sc, reg);
9541 off = tcb_addr - win_pos;
9542 for (i = 0; i < 4; i++) {
9544 for (j = 0; j < 8; j++, off += 4)
9545 buf[j] = htonl(t4_read_reg(sc, base + off));
9547 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
9548 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
9552 t4_write_reg(sc, reg, save);
9553 t4_read_reg(sc, reg);
9557 t4_dump_devlog(struct adapter *sc)
9559 struct devlog_params *dparams = &sc->params.devlog;
9560 struct fw_devlog_e e;
9561 int i, first, j, m, nentries, rc;
9562 uint64_t ftstamp = UINT64_MAX;
9564 if (dparams->start == 0) {
9565 db_printf("devlog params not valid\n");
9569 nentries = dparams->size / sizeof(struct fw_devlog_e);
9570 m = fwmtype_to_hwmtype(dparams->memtype);
9572 /* Find the first entry. */
9574 for (i = 0; i < nentries && !db_pager_quit; i++) {
9575 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9576 sizeof(e), (void *)&e);
9580 if (e.timestamp == 0)
9583 e.timestamp = be64toh(e.timestamp);
9584 if (e.timestamp < ftstamp) {
9585 ftstamp = e.timestamp;
9595 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9596 sizeof(e), (void *)&e);
9600 if (e.timestamp == 0)
9603 e.timestamp = be64toh(e.timestamp);
9604 e.seqno = be32toh(e.seqno);
9605 for (j = 0; j < 8; j++)
9606 e.params[j] = be32toh(e.params[j]);
9608 db_printf("%10d %15ju %8s %8s ",
9609 e.seqno, e.timestamp,
9610 (e.level < nitems(devlog_level_strings) ?
9611 devlog_level_strings[e.level] : "UNKNOWN"),
9612 (e.facility < nitems(devlog_facility_strings) ?
9613 devlog_facility_strings[e.facility] : "UNKNOWN"));
9614 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
9615 e.params[3], e.params[4], e.params[5], e.params[6],
9618 if (++i == nentries)
9620 } while (i != first && !db_pager_quit);
9623 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
9624 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
9626 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
9633 t = db_read_token();
9635 dev = device_lookup_by_name(db_tok_string);
9640 db_printf("usage: show t4 devlog <nexus>\n");
9645 db_printf("device not found\n");
9649 t4_dump_devlog(device_get_softc(dev));
9652 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
9661 t = db_read_token();
9663 dev = device_lookup_by_name(db_tok_string);
9664 t = db_read_token();
9666 tid = db_tok_number;
9673 db_printf("usage: show t4 tcb <nexus> <tid>\n");
9678 db_printf("device not found\n");
9682 db_printf("invalid tid\n");
9686 t4_dump_tcb(device_get_softc(dev), tid);
9690 static struct sx mlu; /* mod load unload */
9691 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
9694 mod_event(module_t mod, int cmd, void *arg)
9697 static int loaded = 0;
9702 if (loaded++ == 0) {
9704 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl);
9705 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl);
9706 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
9707 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
9708 sx_init(&t4_list_lock, "T4/T5 adapters");
9709 SLIST_INIT(&t4_list);
9711 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
9712 SLIST_INIT(&t4_uld_list);
9714 t4_tracer_modload();
9722 if (--loaded == 0) {
9725 sx_slock(&t4_list_lock);
9726 if (!SLIST_EMPTY(&t4_list)) {
9728 sx_sunlock(&t4_list_lock);
9732 sx_slock(&t4_uld_list_lock);
9733 if (!SLIST_EMPTY(&t4_uld_list)) {
9735 sx_sunlock(&t4_uld_list_lock);
9736 sx_sunlock(&t4_list_lock);
9741 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
9742 uprintf("%ju clusters with custom free routine "
9743 "still is use.\n", t4_sge_extfree_refs());
9744 pause("t4unload", 2 * hz);
9747 sx_sunlock(&t4_uld_list_lock);
9749 sx_sunlock(&t4_list_lock);
9751 if (t4_sge_extfree_refs() == 0) {
9752 t4_tracer_modunload();
9754 sx_destroy(&t4_uld_list_lock);
9756 sx_destroy(&t4_list_lock);
9761 loaded++; /* undo earlier decrement */
9772 static devclass_t t4_devclass, t5_devclass, t6_devclass;
9773 static devclass_t cxgbe_devclass, cxl_devclass, cc_devclass;
9774 static devclass_t vcxgbe_devclass, vcxl_devclass, vcc_devclass;
9776 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
9777 MODULE_VERSION(t4nex, 1);
9778 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
9780 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
9781 MODULE_VERSION(t5nex, 1);
9782 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
9784 DRIVER_MODULE(t6nex, pci, t6_driver, t6_devclass, mod_event, 0);
9785 MODULE_VERSION(t6nex, 1);
9786 MODULE_DEPEND(t6nex, firmware, 1, 1, 1);
9788 MODULE_DEPEND(t6nex, netmap, 1, 1, 1);
9789 #endif /* DEV_NETMAP */
9791 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
9792 MODULE_VERSION(cxgbe, 1);
9794 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
9795 MODULE_VERSION(cxl, 1);
9797 DRIVER_MODULE(cc, t6nex, cc_driver, cc_devclass, 0, 0);
9798 MODULE_VERSION(cc, 1);
9800 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
9801 MODULE_VERSION(vcxgbe, 1);
9803 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
9804 MODULE_VERSION(vcxl, 1);
9806 DRIVER_MODULE(vcc, cc, vcc_driver, vcc_devclass, 0, 0);
9807 MODULE_VERSION(vcc, 1);