2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/param.h>
37 #include <sys/kernel.h>
39 #include <sys/systm.h>
40 #include <sys/counter.h>
41 #include <sys/module.h>
42 #include <sys/malloc.h>
43 #include <sys/queue.h>
44 #include <sys/taskqueue.h>
45 #include <sys/pciio.h>
46 #include <dev/pci/pcireg.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pci_private.h>
49 #include <sys/firmware.h>
52 #include <sys/socket.h>
53 #include <sys/sockio.h>
54 #include <sys/sysctl.h>
55 #include <net/ethernet.h>
57 #include <net/if_types.h>
58 #include <net/if_dl.h>
59 #include <net/if_vlan_var.h>
61 #include <net/rss_config.h>
63 #if defined(__i386__) || defined(__amd64__)
68 #include "common/common.h"
69 #include "common/t4_msg.h"
70 #include "common/t4_regs.h"
71 #include "common/t4_regs_values.h"
74 #include "t4_mp_ring.h"
76 /* T4 bus driver interface */
77 static int t4_probe(device_t);
78 static int t4_attach(device_t);
79 static int t4_detach(device_t);
80 static device_method_t t4_methods[] = {
81 DEVMETHOD(device_probe, t4_probe),
82 DEVMETHOD(device_attach, t4_attach),
83 DEVMETHOD(device_detach, t4_detach),
87 static driver_t t4_driver = {
90 sizeof(struct adapter)
94 /* T4 port (cxgbe) interface */
95 static int cxgbe_probe(device_t);
96 static int cxgbe_attach(device_t);
97 static int cxgbe_detach(device_t);
98 static device_method_t cxgbe_methods[] = {
99 DEVMETHOD(device_probe, cxgbe_probe),
100 DEVMETHOD(device_attach, cxgbe_attach),
101 DEVMETHOD(device_detach, cxgbe_detach),
104 static driver_t cxgbe_driver = {
107 sizeof(struct port_info)
110 /* T4 VI (vcxgbe) interface */
111 static int vcxgbe_probe(device_t);
112 static int vcxgbe_attach(device_t);
113 static int vcxgbe_detach(device_t);
114 static device_method_t vcxgbe_methods[] = {
115 DEVMETHOD(device_probe, vcxgbe_probe),
116 DEVMETHOD(device_attach, vcxgbe_attach),
117 DEVMETHOD(device_detach, vcxgbe_detach),
120 static driver_t vcxgbe_driver = {
123 sizeof(struct vi_info)
126 static d_ioctl_t t4_ioctl;
127 static d_open_t t4_open;
128 static d_close_t t4_close;
130 static struct cdevsw t4_cdevsw = {
131 .d_version = D_VERSION,
139 /* T5 bus driver interface */
140 static int t5_probe(device_t);
141 static device_method_t t5_methods[] = {
142 DEVMETHOD(device_probe, t5_probe),
143 DEVMETHOD(device_attach, t4_attach),
144 DEVMETHOD(device_detach, t4_detach),
148 static driver_t t5_driver = {
151 sizeof(struct adapter)
155 /* T5 port (cxl) interface */
156 static driver_t cxl_driver = {
159 sizeof(struct port_info)
162 /* T5 VI (vcxl) interface */
163 static driver_t vcxl_driver = {
166 sizeof(struct vi_info)
169 static struct cdevsw t5_cdevsw = {
170 .d_version = D_VERSION,
178 /* ifnet + media interface */
179 static void cxgbe_init(void *);
180 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
181 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
182 static void cxgbe_qflush(struct ifnet *);
183 static int cxgbe_media_change(struct ifnet *);
184 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
186 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
189 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
190 * then ADAPTER_LOCK, then t4_uld_list_lock.
192 static struct sx t4_list_lock;
193 SLIST_HEAD(, adapter) t4_list;
195 static struct sx t4_uld_list_lock;
196 SLIST_HEAD(, uld_info) t4_uld_list;
200 * Tunables. See tweak_tunables() too.
202 * Each tunable is set to a default value here if it's known at compile-time.
203 * Otherwise it is set to -1 as an indication to tweak_tunables() that it should
204 * provide a reasonable default when the driver is loaded.
206 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
207 * T5 are under hw.cxl.
211 * Number of queues for tx and rx, 10G and 1G, NIC and offload.
214 static int t4_ntxq10g = -1;
215 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g);
218 static int t4_nrxq10g = -1;
219 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g);
222 static int t4_ntxq1g = -1;
223 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g);
226 static int t4_nrxq1g = -1;
227 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g);
230 static int t4_ntxq_vi = -1;
231 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi);
234 static int t4_nrxq_vi = -1;
235 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi);
237 static int t4_rsrv_noflowq = 0;
238 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq);
241 #define NOFLDTXQ_10G 8
242 static int t4_nofldtxq10g = -1;
243 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g);
245 #define NOFLDRXQ_10G 2
246 static int t4_nofldrxq10g = -1;
247 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g);
249 #define NOFLDTXQ_1G 2
250 static int t4_nofldtxq1g = -1;
251 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g);
253 #define NOFLDRXQ_1G 1
254 static int t4_nofldrxq1g = -1;
255 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g);
257 #define NOFLDTXQ_VI 1
258 static int t4_nofldtxq_vi = -1;
259 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi);
261 #define NOFLDRXQ_VI 1
262 static int t4_nofldrxq_vi = -1;
263 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi);
268 static int t4_nnmtxq_vi = -1;
269 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi);
272 static int t4_nnmrxq_vi = -1;
273 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi);
277 * Holdoff parameters for 10G and 1G ports.
279 #define TMR_IDX_10G 1
280 static int t4_tmr_idx_10g = TMR_IDX_10G;
281 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g);
283 #define PKTC_IDX_10G (-1)
284 static int t4_pktc_idx_10g = PKTC_IDX_10G;
285 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g);
288 static int t4_tmr_idx_1g = TMR_IDX_1G;
289 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g);
291 #define PKTC_IDX_1G (-1)
292 static int t4_pktc_idx_1g = PKTC_IDX_1G;
293 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g);
296 * Size (# of entries) of each tx and rx queue.
298 static unsigned int t4_qsize_txq = TX_EQ_QSIZE;
299 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
301 static unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
302 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
305 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
307 static int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
308 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
311 * Configuration file.
313 #define DEFAULT_CF "default"
314 #define FLASH_CF "flash"
315 #define UWIRE_CF "uwire"
316 #define FPGA_CF "fpga"
317 static char t4_cfg_file[32] = DEFAULT_CF;
318 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
321 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively).
322 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
323 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
324 * mark or when signalled to do so, 0 to never emit PAUSE.
326 static int t4_pause_settings = PAUSE_TX | PAUSE_RX;
327 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings);
330 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
331 * encouraged respectively).
333 static unsigned int t4_fw_install = 1;
334 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install);
337 * ASIC features that will be used. Disable the ones you don't want so that the
338 * chip resources aren't wasted on features that will not be used.
340 static int t4_nbmcaps_allowed = 0;
341 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed);
343 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
344 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
346 static int t4_switchcaps_allowed = 0;
347 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed);
349 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
350 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
352 static int t4_toecaps_allowed = -1;
353 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
355 static int t4_rdmacaps_allowed = 0;
356 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
358 static int t4_tlscaps_allowed = 0;
359 TUNABLE_INT("hw.cxgbe.tlscaps_allowed", &t4_tlscaps_allowed);
361 static int t4_iscsicaps_allowed = 0;
362 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
364 static int t4_fcoecaps_allowed = 0;
365 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
367 static int t5_write_combine = 0;
368 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
370 static int t4_num_vis = 1;
371 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis);
373 /* Functions used by extra VIs to obtain unique MAC addresses for each VI. */
374 static int vi_mac_funcs[] = {
377 FW_VI_FUNC_OPENISCSI,
383 struct intrs_and_queues {
384 uint16_t intr_type; /* INTx, MSI, or MSI-X */
385 uint16_t nirq; /* Total # of vectors */
386 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */
387 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */
388 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */
389 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */
390 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */
391 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */
392 uint16_t rsrv_noflowq; /* Flag whether to reserve queue 0 */
393 uint16_t nofldtxq10g; /* # of TOE txq's for each 10G port */
394 uint16_t nofldrxq10g; /* # of TOE rxq's for each 10G port */
395 uint16_t nofldtxq1g; /* # of TOE txq's for each 1G port */
396 uint16_t nofldrxq1g; /* # of TOE rxq's for each 1G port */
398 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
399 uint16_t ntxq_vi; /* # of NIC txq's */
400 uint16_t nrxq_vi; /* # of NIC rxq's */
401 uint16_t nofldtxq_vi; /* # of TOE txq's */
402 uint16_t nofldrxq_vi; /* # of TOE rxq's */
403 uint16_t nnmtxq_vi; /* # of netmap txq's */
404 uint16_t nnmrxq_vi; /* # of netmap rxq's */
407 struct filter_entry {
408 uint32_t valid:1; /* filter allocated and valid */
409 uint32_t locked:1; /* filter is administratively locked */
410 uint32_t pending:1; /* filter action is pending firmware reply */
411 uint32_t smtidx:8; /* Source MAC Table index for smac */
412 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
414 struct t4_filter_specification fs;
417 static int map_bars_0_and_4(struct adapter *);
418 static int map_bar_2(struct adapter *);
419 static void setup_memwin(struct adapter *);
420 static void position_memwin(struct adapter *, int, uint32_t);
421 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
422 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *,
424 static inline int write_via_memwin(struct adapter *, int, uint32_t,
425 const uint32_t *, int);
426 static int validate_mem_range(struct adapter *, uint32_t, int);
427 static int fwmtype_to_hwmtype(int);
428 static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
430 static int fixup_devlog_params(struct adapter *);
431 static int cfg_itype_and_nqueues(struct adapter *, int, int, int,
432 struct intrs_and_queues *);
433 static int prep_firmware(struct adapter *);
434 static int partition_resources(struct adapter *, const struct firmware *,
436 static int get_params__pre_init(struct adapter *);
437 static int get_params__post_init(struct adapter *);
438 static int set_params__post_init(struct adapter *);
439 static void t4_set_desc(struct adapter *);
440 static void build_medialist(struct port_info *, struct ifmedia *);
441 static int cxgbe_init_synchronized(struct vi_info *);
442 static int cxgbe_uninit_synchronized(struct vi_info *);
443 static int setup_intr_handlers(struct adapter *);
444 static void quiesce_txq(struct adapter *, struct sge_txq *);
445 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
446 static void quiesce_iq(struct adapter *, struct sge_iq *);
447 static void quiesce_fl(struct adapter *, struct sge_fl *);
448 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
449 driver_intr_t *, void *, char *);
450 static int t4_free_irq(struct adapter *, struct irq *);
451 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
452 static void vi_refresh_stats(struct adapter *, struct vi_info *);
453 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
454 static void cxgbe_tick(void *);
455 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
456 static int cpl_not_handled(struct sge_iq *, const struct rss_header *,
458 static int an_not_handled(struct sge_iq *, const struct rsp_ctrl *);
459 static int fw_msg_not_handled(struct adapter *, const __be64 *);
460 static void t4_sysctls(struct adapter *);
461 static void cxgbe_sysctls(struct port_info *);
462 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
463 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
464 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
465 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
466 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
467 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
468 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
469 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
470 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
471 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
472 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
474 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
475 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
476 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
477 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
478 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
479 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
480 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
481 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
482 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
483 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
484 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
485 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
486 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
487 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
488 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
489 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
490 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
491 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
492 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
493 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
494 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
495 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
496 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
497 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
498 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
499 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
500 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
502 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t);
503 static uint32_t mode_to_fconf(uint32_t);
504 static uint32_t mode_to_iconf(uint32_t);
505 static int check_fspec_against_fconf_iconf(struct adapter *,
506 struct t4_filter_specification *);
507 static int get_filter_mode(struct adapter *, uint32_t *);
508 static int set_filter_mode(struct adapter *, uint32_t);
509 static inline uint64_t get_filter_hits(struct adapter *, uint32_t);
510 static int get_filter(struct adapter *, struct t4_filter *);
511 static int set_filter(struct adapter *, struct t4_filter *);
512 static int del_filter(struct adapter *, struct t4_filter *);
513 static void clear_filter(struct filter_entry *);
514 static int set_filter_wr(struct adapter *, int);
515 static int del_filter_wr(struct adapter *, int);
516 static int get_sge_context(struct adapter *, struct t4_sge_context *);
517 static int load_fw(struct adapter *, struct t4_data *);
518 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
519 static int read_i2c(struct adapter *, struct t4_i2c_data *);
520 static int set_sched_class(struct adapter *, struct t4_sched_params *);
521 static int set_sched_queue(struct adapter *, struct t4_sched_queue *);
523 static int toe_capability(struct vi_info *, int);
525 static int mod_event(module_t, int, void *);
531 {0xa000, "Chelsio Terminator 4 FPGA"},
532 {0x4400, "Chelsio T440-dbg"},
533 {0x4401, "Chelsio T420-CR"},
534 {0x4402, "Chelsio T422-CR"},
535 {0x4403, "Chelsio T440-CR"},
536 {0x4404, "Chelsio T420-BCH"},
537 {0x4405, "Chelsio T440-BCH"},
538 {0x4406, "Chelsio T440-CH"},
539 {0x4407, "Chelsio T420-SO"},
540 {0x4408, "Chelsio T420-CX"},
541 {0x4409, "Chelsio T420-BT"},
542 {0x440a, "Chelsio T404-BT"},
543 {0x440e, "Chelsio T440-LP-CR"},
545 {0xb000, "Chelsio Terminator 5 FPGA"},
546 {0x5400, "Chelsio T580-dbg"},
547 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
548 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
549 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
550 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
551 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
552 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
553 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
554 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
555 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
556 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
557 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
558 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
559 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
561 {0x5404, "Chelsio T520-BCH"},
562 {0x5405, "Chelsio T540-BCH"},
563 {0x5406, "Chelsio T540-CH"},
564 {0x5408, "Chelsio T520-CX"},
565 {0x540b, "Chelsio B520-SR"},
566 {0x540c, "Chelsio B504-BT"},
567 {0x540f, "Chelsio Amsterdam"},
568 {0x5413, "Chelsio T580-CHR"},
574 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be
575 * exactly the same for both rxq and ofld_rxq.
577 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
578 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
581 /* No easy way to include t4_msg.h before adapter.h so we check this way */
582 CTASSERT(nitems(((struct adapter *)0)->cpl_handler) == NUM_CPL_CMDS);
583 CTASSERT(nitems(((struct adapter *)0)->fw_msg_handler) == NUM_FW6_TYPES);
585 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
588 t4_probe(device_t dev)
591 uint16_t v = pci_get_vendor(dev);
592 uint16_t d = pci_get_device(dev);
593 uint8_t f = pci_get_function(dev);
595 if (v != PCI_VENDOR_ID_CHELSIO)
598 /* Attach only to PF0 of the FPGA */
599 if (d == 0xa000 && f != 0)
602 for (i = 0; i < nitems(t4_pciids); i++) {
603 if (d == t4_pciids[i].device) {
604 device_set_desc(dev, t4_pciids[i].desc);
605 return (BUS_PROBE_DEFAULT);
613 t5_probe(device_t dev)
616 uint16_t v = pci_get_vendor(dev);
617 uint16_t d = pci_get_device(dev);
618 uint8_t f = pci_get_function(dev);
620 if (v != PCI_VENDOR_ID_CHELSIO)
623 /* Attach only to PF0 of the FPGA */
624 if (d == 0xb000 && f != 0)
627 for (i = 0; i < nitems(t5_pciids); i++) {
628 if (d == t5_pciids[i].device) {
629 device_set_desc(dev, t5_pciids[i].desc);
630 return (BUS_PROBE_DEFAULT);
638 t5_attribute_workaround(device_t dev)
644 * The T5 chips do not properly echo the No Snoop and Relaxed
645 * Ordering attributes when replying to a TLP from a Root
646 * Port. As a workaround, find the parent Root Port and
647 * disable No Snoop and Relaxed Ordering. Note that this
648 * affects all devices under this root port.
650 root_port = pci_find_pcie_root_port(dev);
651 if (root_port == NULL) {
652 device_printf(dev, "Unable to find parent root port\n");
656 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
657 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
658 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
660 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
661 device_get_nameunit(root_port));
665 t4_attach(device_t dev)
668 int rc = 0, i, j, n10g, n1g, rqidx, tqidx;
669 struct intrs_and_queues iaq;
673 int ofld_rqidx, ofld_tqidx;
676 int nm_rqidx, nm_tqidx;
680 sc = device_get_softc(dev);
682 TUNABLE_INT_FETCH("hw.cxgbe.debug_flags", &sc->debug_flags);
684 if ((pci_get_device(dev) & 0xff00) == 0x5400)
685 t5_attribute_workaround(dev);
686 pci_enable_busmaster(dev);
687 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
690 pci_set_max_read_req(dev, 4096);
691 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
692 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
693 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
695 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
699 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
700 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
701 device_get_nameunit(dev));
703 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
704 device_get_nameunit(dev));
705 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
706 sx_xlock(&t4_list_lock);
707 SLIST_INSERT_HEAD(&t4_list, sc, link);
708 sx_xunlock(&t4_list_lock);
710 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
711 TAILQ_INIT(&sc->sfl);
712 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
714 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
716 rc = map_bars_0_and_4(sc);
718 goto done; /* error message displayed already */
721 * This is the real PF# to which we're attaching. Works from within PCI
722 * passthrough environments too, where pci_get_function() could return a
723 * different PF# depending on the passthrough configuration. We need to
724 * use the real PF# in all our communication with the firmware.
726 sc->pf = G_SOURCEPF(t4_read_reg(sc, A_PL_WHOAMI));
729 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
730 sc->an_handler = an_not_handled;
731 for (i = 0; i < nitems(sc->cpl_handler); i++)
732 sc->cpl_handler[i] = cpl_not_handled;
733 for (i = 0; i < nitems(sc->fw_msg_handler); i++)
734 sc->fw_msg_handler[i] = fw_msg_not_handled;
735 t4_register_cpl_handler(sc, CPL_SET_TCB_RPL, t4_filter_rpl);
736 t4_register_cpl_handler(sc, CPL_TRACE_PKT, t4_trace_pkt);
737 t4_register_cpl_handler(sc, CPL_T5_TRACE_PKT, t5_trace_pkt);
738 t4_init_sge_cpl_handlers(sc);
740 /* Prepare the adapter for operation. */
741 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
742 rc = -t4_prep_adapter(sc, buf);
745 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
750 * Do this really early, with the memory windows set up even before the
751 * character device. The userland tool's register i/o and mem read
752 * will work even in "recovery mode".
755 if (t4_init_devlog_params(sc, 0) == 0)
756 fixup_devlog_params(sc);
757 sc->cdev = make_dev(is_t4(sc) ? &t4_cdevsw : &t5_cdevsw,
758 device_get_unit(dev), UID_ROOT, GID_WHEEL, 0600, "%s",
759 device_get_nameunit(dev));
760 if (sc->cdev == NULL)
761 device_printf(dev, "failed to create nexus char device.\n");
763 sc->cdev->si_drv1 = sc;
765 /* Go no further if recovery mode has been requested. */
766 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
767 device_printf(dev, "recovery mode.\n");
771 #if defined(__i386__)
772 if ((cpu_feature & CPUID_CX8) == 0) {
773 device_printf(dev, "64 bit atomics not available.\n");
779 /* Prepare the firmware for operation */
780 rc = prep_firmware(sc);
782 goto done; /* error message displayed already */
784 rc = get_params__post_init(sc);
786 goto done; /* error message displayed already */
788 rc = set_params__post_init(sc);
790 goto done; /* error message displayed already */
794 goto done; /* error message displayed already */
796 rc = t4_create_dma_tag(sc);
798 goto done; /* error message displayed already */
801 * Number of VIs to create per-port. The first VI is the "main" regular
802 * VI for the port. The rest are additional virtual interfaces on the
803 * same physical port. Note that the main VI does not have native
804 * netmap support but the extra VIs do.
806 * Limit the number of VIs per port to the number of available
807 * MAC addresses per port.
810 num_vis = t4_num_vis;
813 if (num_vis > nitems(vi_mac_funcs)) {
814 num_vis = nitems(vi_mac_funcs);
815 device_printf(dev, "Number of VIs limited to %d\n", num_vis);
819 * First pass over all the ports - allocate VIs and initialize some
820 * basic parameters like mac address, port type, etc. We also figure
821 * out whether a port is 10G or 1G and use that information when
822 * calculating how many interrupts to attempt to allocate.
825 for_each_port(sc, i) {
826 struct port_info *pi;
828 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
831 /* These must be set before t4_port_init */
835 * XXX: vi[0] is special so we can't delay this allocation until
836 * pi->nvi's final value is known.
838 pi->vi = malloc(sizeof(struct vi_info) * num_vis, M_CXGBE,
842 * Allocate the "main" VI and initialize parameters
845 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
847 device_printf(dev, "unable to initialize port %d: %d\n",
849 free(pi->vi, M_CXGBE);
855 pi->link_cfg.requested_fc &= ~(PAUSE_TX | PAUSE_RX);
856 pi->link_cfg.requested_fc |= t4_pause_settings;
857 pi->link_cfg.fc &= ~(PAUSE_TX | PAUSE_RX);
858 pi->link_cfg.fc |= t4_pause_settings;
860 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, &pi->link_cfg);
862 device_printf(dev, "port %d l1cfg failed: %d\n", i, rc);
863 free(pi->vi, M_CXGBE);
869 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
870 device_get_nameunit(dev), i);
871 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
872 sc->chan_map[pi->tx_chan] = i;
874 if (is_10G_port(pi) || is_40G_port(pi)) {
882 pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbe" : "cxl", -1);
883 if (pi->dev == NULL) {
885 "failed to add device for port %d.\n", i);
889 pi->vi[0].dev = pi->dev;
890 device_set_softc(pi->dev, pi);
894 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
896 rc = cfg_itype_and_nqueues(sc, n10g, n1g, num_vis, &iaq);
898 goto done; /* error message displayed already */
899 if (iaq.nrxq_vi + iaq.nofldrxq_vi + iaq.nnmrxq_vi == 0)
902 sc->intr_type = iaq.intr_type;
903 sc->intr_count = iaq.nirq;
906 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
907 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
909 s->nrxq += (n10g + n1g) * (num_vis - 1) * iaq.nrxq_vi;
910 s->ntxq += (n10g + n1g) * (num_vis - 1) * iaq.ntxq_vi;
912 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
913 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
914 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
916 if (is_offload(sc)) {
917 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g;
918 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g;
920 s->nofldrxq += (n10g + n1g) * (num_vis - 1) *
922 s->nofldtxq += (n10g + n1g) * (num_vis - 1) *
925 s->neq += s->nofldtxq + s->nofldrxq;
926 s->niq += s->nofldrxq;
928 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
929 M_CXGBE, M_ZERO | M_WAITOK);
930 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
931 M_CXGBE, M_ZERO | M_WAITOK);
936 s->nnmrxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmrxq_vi;
937 s->nnmtxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmtxq_vi;
939 s->neq += s->nnmtxq + s->nnmrxq;
942 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
943 M_CXGBE, M_ZERO | M_WAITOK);
944 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
945 M_CXGBE, M_ZERO | M_WAITOK);
948 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE,
950 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
952 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
954 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
956 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
959 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
962 t4_init_l2t(sc, M_WAITOK);
965 * Second pass over the ports. This time we know the number of rx and
966 * tx queues that each port should get.
970 ofld_rqidx = ofld_tqidx = 0;
973 nm_rqidx = nm_tqidx = 0;
975 for_each_port(sc, i) {
976 struct port_info *pi = sc->port[i];
983 for_each_vi(pi, j, vi) {
985 vi->qsize_rxq = t4_qsize_rxq;
986 vi->qsize_txq = t4_qsize_txq;
988 vi->first_rxq = rqidx;
989 vi->first_txq = tqidx;
990 if (is_10G_port(pi) || is_40G_port(pi)) {
991 vi->tmr_idx = t4_tmr_idx_10g;
992 vi->pktc_idx = t4_pktc_idx_10g;
993 vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
994 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi;
995 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi;
997 vi->tmr_idx = t4_tmr_idx_1g;
998 vi->pktc_idx = t4_pktc_idx_1g;
999 vi->flags |= iaq.intr_flags_1g & INTR_RXQ;
1000 vi->nrxq = j == 0 ? iaq.nrxq1g : iaq.nrxq_vi;
1001 vi->ntxq = j == 0 ? iaq.ntxq1g : iaq.ntxq_vi;
1006 if (j == 0 && vi->ntxq > 1)
1007 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0;
1009 vi->rsrv_noflowq = 0;
1012 vi->first_ofld_rxq = ofld_rqidx;
1013 vi->first_ofld_txq = ofld_tqidx;
1014 if (is_10G_port(pi) || is_40G_port(pi)) {
1015 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ;
1016 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g :
1018 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g :
1021 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ;
1022 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g :
1024 vi->nofldtxq = j == 0 ? iaq.nofldtxq1g :
1027 ofld_rqidx += vi->nofldrxq;
1028 ofld_tqidx += vi->nofldtxq;
1032 vi->first_nm_rxq = nm_rqidx;
1033 vi->first_nm_txq = nm_tqidx;
1034 vi->nnmrxq = iaq.nnmrxq_vi;
1035 vi->nnmtxq = iaq.nnmtxq_vi;
1036 nm_rqidx += vi->nnmrxq;
1037 nm_tqidx += vi->nnmtxq;
1043 rc = setup_intr_handlers(sc);
1046 "failed to setup interrupt handlers: %d\n", rc);
1050 rc = bus_generic_attach(dev);
1053 "failed to attach all child ports: %d\n", rc);
1058 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1059 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1060 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1061 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1062 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1067 if (rc != 0 && sc->cdev) {
1068 /* cdev was created and so cxgbetool works; recover that way. */
1070 "error during attach, adapter is now in recovery mode.\n");
1086 t4_detach(device_t dev)
1089 struct port_info *pi;
1092 sc = device_get_softc(dev);
1094 if (sc->flags & FULL_INIT_DONE)
1095 t4_intr_disable(sc);
1098 destroy_dev(sc->cdev);
1102 rc = bus_generic_detach(dev);
1105 "failed to detach child devices: %d\n", rc);
1109 for (i = 0; i < sc->intr_count; i++)
1110 t4_free_irq(sc, &sc->irq[i]);
1112 for (i = 0; i < MAX_NPORTS; i++) {
1115 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1117 device_delete_child(dev, pi->dev);
1119 mtx_destroy(&pi->pi_lock);
1120 free(pi->vi, M_CXGBE);
1125 if (sc->flags & FULL_INIT_DONE)
1126 adapter_full_uninit(sc);
1128 if (sc->flags & FW_OK)
1129 t4_fw_bye(sc, sc->mbox);
1131 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1132 pci_release_msi(dev);
1135 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1139 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1143 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1147 t4_free_l2t(sc->l2t);
1150 free(sc->sge.ofld_rxq, M_CXGBE);
1151 free(sc->sge.ofld_txq, M_CXGBE);
1154 free(sc->sge.nm_rxq, M_CXGBE);
1155 free(sc->sge.nm_txq, M_CXGBE);
1157 free(sc->irq, M_CXGBE);
1158 free(sc->sge.rxq, M_CXGBE);
1159 free(sc->sge.txq, M_CXGBE);
1160 free(sc->sge.ctrlq, M_CXGBE);
1161 free(sc->sge.iqmap, M_CXGBE);
1162 free(sc->sge.eqmap, M_CXGBE);
1163 free(sc->tids.ftid_tab, M_CXGBE);
1164 t4_destroy_dma_tag(sc);
1165 if (mtx_initialized(&sc->sc_lock)) {
1166 sx_xlock(&t4_list_lock);
1167 SLIST_REMOVE(&t4_list, sc, adapter, link);
1168 sx_xunlock(&t4_list_lock);
1169 mtx_destroy(&sc->sc_lock);
1172 callout_drain(&sc->sfl_callout);
1173 if (mtx_initialized(&sc->tids.ftid_lock))
1174 mtx_destroy(&sc->tids.ftid_lock);
1175 if (mtx_initialized(&sc->sfl_lock))
1176 mtx_destroy(&sc->sfl_lock);
1177 if (mtx_initialized(&sc->ifp_lock))
1178 mtx_destroy(&sc->ifp_lock);
1179 if (mtx_initialized(&sc->reg_lock))
1180 mtx_destroy(&sc->reg_lock);
1182 for (i = 0; i < NUM_MEMWIN; i++) {
1183 struct memwin *mw = &sc->memwin[i];
1185 if (rw_initialized(&mw->mw_lock))
1186 rw_destroy(&mw->mw_lock);
1189 bzero(sc, sizeof(*sc));
1195 cxgbe_probe(device_t dev)
1198 struct port_info *pi = device_get_softc(dev);
1200 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1201 device_set_desc_copy(dev, buf);
1203 return (BUS_PROBE_DEFAULT);
1206 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1207 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1208 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1209 #define T4_CAP_ENABLE (T4_CAP)
1212 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1217 vi->xact_addr_filt = -1;
1218 callout_init(&vi->tick, 1);
1220 /* Allocate an ifnet and set it up */
1221 ifp = if_alloc(IFT_ETHER);
1223 device_printf(dev, "Cannot allocate ifnet\n");
1229 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1230 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1232 ifp->if_init = cxgbe_init;
1233 ifp->if_ioctl = cxgbe_ioctl;
1234 ifp->if_transmit = cxgbe_transmit;
1235 ifp->if_qflush = cxgbe_qflush;
1237 ifp->if_capabilities = T4_CAP;
1239 if (vi->nofldrxq != 0)
1240 ifp->if_capabilities |= IFCAP_TOE;
1242 ifp->if_capenable = T4_CAP_ENABLE;
1243 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1244 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1246 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1247 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS;
1248 ifp->if_hw_tsomaxsegsize = 65536;
1250 /* Initialize ifmedia for this VI */
1251 ifmedia_init(&vi->media, IFM_IMASK, cxgbe_media_change,
1252 cxgbe_media_status);
1253 build_medialist(vi->pi, &vi->media);
1255 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1256 EVENTHANDLER_PRI_ANY);
1258 ether_ifattach(ifp, vi->hw_addr);
1260 if (vi->nnmrxq != 0)
1261 cxgbe_nm_attach(vi);
1263 sb = sbuf_new_auto();
1264 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1266 if (ifp->if_capabilities & IFCAP_TOE)
1267 sbuf_printf(sb, "; %d txq, %d rxq (TOE)",
1268 vi->nofldtxq, vi->nofldrxq);
1271 if (ifp->if_capabilities & IFCAP_NETMAP)
1272 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1273 vi->nnmtxq, vi->nnmrxq);
1276 device_printf(dev, "%s\n", sbuf_data(sb));
1285 cxgbe_attach(device_t dev)
1287 struct port_info *pi = device_get_softc(dev);
1291 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1293 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1297 for_each_vi(pi, i, vi) {
1300 vi->dev = device_add_child(dev, is_t4(pi->adapter) ?
1301 "vcxgbe" : "vcxl", -1);
1302 if (vi->dev == NULL) {
1303 device_printf(dev, "failed to add VI %d\n", i);
1306 device_set_softc(vi->dev, vi);
1311 bus_generic_attach(dev);
1317 cxgbe_vi_detach(struct vi_info *vi)
1319 struct ifnet *ifp = vi->ifp;
1321 ether_ifdetach(ifp);
1324 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c);
1326 /* Let detach proceed even if these fail. */
1328 if (ifp->if_capabilities & IFCAP_NETMAP)
1329 cxgbe_nm_detach(vi);
1331 cxgbe_uninit_synchronized(vi);
1332 callout_drain(&vi->tick);
1335 ifmedia_removeall(&vi->media);
1341 cxgbe_detach(device_t dev)
1343 struct port_info *pi = device_get_softc(dev);
1344 struct adapter *sc = pi->adapter;
1347 /* Detach the extra VIs first. */
1348 rc = bus_generic_detach(dev);
1351 device_delete_children(dev);
1353 doom_vi(sc, &pi->vi[0]);
1355 if (pi->flags & HAS_TRACEQ) {
1356 sc->traceq = -1; /* cloner should not create ifnet */
1357 t4_tracer_port_detach(sc);
1360 cxgbe_vi_detach(&pi->vi[0]);
1361 callout_drain(&pi->tick);
1363 end_synchronized_op(sc, 0);
1369 cxgbe_init(void *arg)
1371 struct vi_info *vi = arg;
1372 struct adapter *sc = vi->pi->adapter;
1374 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1376 cxgbe_init_synchronized(vi);
1377 end_synchronized_op(sc, 0);
1381 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1383 int rc = 0, mtu, flags, can_sleep;
1384 struct vi_info *vi = ifp->if_softc;
1385 struct adapter *sc = vi->pi->adapter;
1386 struct ifreq *ifr = (struct ifreq *)data;
1392 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO))
1395 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1399 if (vi->flags & VI_INIT_DONE) {
1400 t4_update_fl_bufsize(ifp);
1401 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1402 rc = update_mac_settings(ifp, XGMAC_MTU);
1404 end_synchronized_op(sc, 0);
1410 rc = begin_synchronized_op(sc, vi,
1411 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg");
1415 if (ifp->if_flags & IFF_UP) {
1416 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1417 flags = vi->if_flags;
1418 if ((ifp->if_flags ^ flags) &
1419 (IFF_PROMISC | IFF_ALLMULTI)) {
1420 if (can_sleep == 1) {
1421 end_synchronized_op(sc, 0);
1425 rc = update_mac_settings(ifp,
1426 XGMAC_PROMISC | XGMAC_ALLMULTI);
1429 if (can_sleep == 0) {
1430 end_synchronized_op(sc, LOCK_HELD);
1434 rc = cxgbe_init_synchronized(vi);
1436 vi->if_flags = ifp->if_flags;
1437 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1438 if (can_sleep == 0) {
1439 end_synchronized_op(sc, LOCK_HELD);
1443 rc = cxgbe_uninit_synchronized(vi);
1445 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD);
1449 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1450 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi");
1453 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1454 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1455 end_synchronized_op(sc, LOCK_HELD);
1459 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1463 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1464 if (mask & IFCAP_TXCSUM) {
1465 ifp->if_capenable ^= IFCAP_TXCSUM;
1466 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1468 if (IFCAP_TSO4 & ifp->if_capenable &&
1469 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1470 ifp->if_capenable &= ~IFCAP_TSO4;
1472 "tso4 disabled due to -txcsum.\n");
1475 if (mask & IFCAP_TXCSUM_IPV6) {
1476 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1477 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1479 if (IFCAP_TSO6 & ifp->if_capenable &&
1480 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1481 ifp->if_capenable &= ~IFCAP_TSO6;
1483 "tso6 disabled due to -txcsum6.\n");
1486 if (mask & IFCAP_RXCSUM)
1487 ifp->if_capenable ^= IFCAP_RXCSUM;
1488 if (mask & IFCAP_RXCSUM_IPV6)
1489 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1492 * Note that we leave CSUM_TSO alone (it is always set). The
1493 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1494 * sending a TSO request our way, so it's sufficient to toggle
1497 if (mask & IFCAP_TSO4) {
1498 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1499 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1500 if_printf(ifp, "enable txcsum first.\n");
1504 ifp->if_capenable ^= IFCAP_TSO4;
1506 if (mask & IFCAP_TSO6) {
1507 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1508 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1509 if_printf(ifp, "enable txcsum6 first.\n");
1513 ifp->if_capenable ^= IFCAP_TSO6;
1515 if (mask & IFCAP_LRO) {
1516 #if defined(INET) || defined(INET6)
1518 struct sge_rxq *rxq;
1520 ifp->if_capenable ^= IFCAP_LRO;
1521 for_each_rxq(vi, i, rxq) {
1522 if (ifp->if_capenable & IFCAP_LRO)
1523 rxq->iq.flags |= IQ_LRO_ENABLED;
1525 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1530 if (mask & IFCAP_TOE) {
1531 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1533 rc = toe_capability(vi, enable);
1537 ifp->if_capenable ^= mask;
1540 if (mask & IFCAP_VLAN_HWTAGGING) {
1541 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1542 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1543 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1545 if (mask & IFCAP_VLAN_MTU) {
1546 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1548 /* Need to find out how to disable auto-mtu-inflation */
1550 if (mask & IFCAP_VLAN_HWTSO)
1551 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1552 if (mask & IFCAP_VLAN_HWCSUM)
1553 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1555 #ifdef VLAN_CAPABILITIES
1556 VLAN_CAPABILITIES(ifp);
1559 end_synchronized_op(sc, 0);
1564 ifmedia_ioctl(ifp, ifr, &vi->media, cmd);
1568 struct ifi2creq i2c;
1570 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
1573 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
1577 if (i2c.len > sizeof(i2c.data)) {
1581 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
1584 rc = -t4_i2c_rd(sc, sc->mbox, vi->pi->port_id, i2c.dev_addr,
1585 i2c.offset, i2c.len, &i2c.data[0]);
1586 end_synchronized_op(sc, 0);
1588 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
1593 rc = ether_ioctl(ifp, cmd, data);
1600 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1602 struct vi_info *vi = ifp->if_softc;
1603 struct port_info *pi = vi->pi;
1604 struct adapter *sc = pi->adapter;
1605 struct sge_txq *txq;
1610 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
1612 if (__predict_false(pi->link_cfg.link_ok == 0)) {
1618 if (__predict_false(rc != 0)) {
1619 MPASS(m == NULL); /* was freed already */
1620 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
1625 txq = &sc->sge.txq[vi->first_txq];
1626 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
1627 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
1631 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
1632 if (__predict_false(rc != 0))
1639 cxgbe_qflush(struct ifnet *ifp)
1641 struct vi_info *vi = ifp->if_softc;
1642 struct sge_txq *txq;
1645 /* queues do not exist if !VI_INIT_DONE. */
1646 if (vi->flags & VI_INIT_DONE) {
1647 for_each_txq(vi, i, txq) {
1649 txq->eq.flags &= ~EQ_ENABLED;
1651 while (!mp_ring_is_idle(txq->r)) {
1652 mp_ring_check_drainage(txq->r, 0);
1661 cxgbe_media_change(struct ifnet *ifp)
1663 struct vi_info *vi = ifp->if_softc;
1665 device_printf(vi->dev, "%s unimplemented.\n", __func__);
1667 return (EOPNOTSUPP);
1671 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1673 struct vi_info *vi = ifp->if_softc;
1674 struct port_info *pi = vi->pi;
1675 struct ifmedia_entry *cur;
1676 int speed = pi->link_cfg.speed;
1678 cur = vi->media.ifm_cur;
1680 ifmr->ifm_status = IFM_AVALID;
1681 if (!pi->link_cfg.link_ok)
1684 ifmr->ifm_status |= IFM_ACTIVE;
1686 /* active and current will differ iff current media is autoselect. */
1687 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO)
1690 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
1692 ifmr->ifm_active |= IFM_10G_T;
1693 else if (speed == 1000)
1694 ifmr->ifm_active |= IFM_1000_T;
1695 else if (speed == 100)
1696 ifmr->ifm_active |= IFM_100_TX;
1697 else if (speed == 10)
1698 ifmr->ifm_active |= IFM_10_T;
1700 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__,
1705 vcxgbe_probe(device_t dev)
1708 struct vi_info *vi = device_get_softc(dev);
1710 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
1712 device_set_desc_copy(dev, buf);
1714 return (BUS_PROBE_DEFAULT);
1718 vcxgbe_attach(device_t dev)
1721 struct port_info *pi;
1723 int func, index, rc;
1726 vi = device_get_softc(dev);
1730 index = vi - pi->vi;
1731 KASSERT(index < nitems(vi_mac_funcs),
1732 ("%s: VI %s doesn't have a MAC func", __func__,
1733 device_get_nameunit(dev)));
1734 func = vi_mac_funcs[index];
1735 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
1736 vi->hw_addr, &vi->rss_size, func, 0);
1738 device_printf(dev, "Failed to allocate virtual interface "
1739 "for port %d: %d\n", pi->port_id, -rc);
1744 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1745 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
1746 V_FW_PARAMS_PARAM_YZ(vi->viid);
1747 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
1749 vi->rss_base = 0xffff;
1751 /* MPASS((val >> 16) == rss_size); */
1752 vi->rss_base = val & 0xffff;
1755 rc = cxgbe_vi_attach(dev, vi);
1757 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1764 vcxgbe_detach(device_t dev)
1769 vi = device_get_softc(dev);
1770 sc = vi->pi->adapter;
1774 cxgbe_vi_detach(vi);
1775 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1777 end_synchronized_op(sc, 0);
1783 t4_fatal_err(struct adapter *sc)
1785 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
1786 t4_intr_disable(sc);
1787 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
1788 device_get_nameunit(sc->dev));
1792 map_bars_0_and_4(struct adapter *sc)
1794 sc->regs_rid = PCIR_BAR(0);
1795 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1796 &sc->regs_rid, RF_ACTIVE);
1797 if (sc->regs_res == NULL) {
1798 device_printf(sc->dev, "cannot map registers.\n");
1801 sc->bt = rman_get_bustag(sc->regs_res);
1802 sc->bh = rman_get_bushandle(sc->regs_res);
1803 sc->mmio_len = rman_get_size(sc->regs_res);
1804 setbit(&sc->doorbells, DOORBELL_KDB);
1806 sc->msix_rid = PCIR_BAR(4);
1807 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1808 &sc->msix_rid, RF_ACTIVE);
1809 if (sc->msix_res == NULL) {
1810 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
1818 map_bar_2(struct adapter *sc)
1822 * T4: only iWARP driver uses the userspace doorbells. There is no need
1823 * to map it if RDMA is disabled.
1825 if (is_t4(sc) && sc->rdmacaps == 0)
1828 sc->udbs_rid = PCIR_BAR(2);
1829 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1830 &sc->udbs_rid, RF_ACTIVE);
1831 if (sc->udbs_res == NULL) {
1832 device_printf(sc->dev, "cannot map doorbell BAR.\n");
1835 sc->udbs_base = rman_get_virtual(sc->udbs_res);
1838 setbit(&sc->doorbells, DOORBELL_UDB);
1839 #if defined(__i386__) || defined(__amd64__)
1840 if (t5_write_combine) {
1844 * Enable write combining on BAR2. This is the
1845 * userspace doorbell BAR and is split into 128B
1846 * (UDBS_SEG_SIZE) doorbell regions, each associated
1847 * with an egress queue. The first 64B has the doorbell
1848 * and the second 64B can be used to submit a tx work
1849 * request with an implicit doorbell.
1852 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
1853 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
1855 clrbit(&sc->doorbells, DOORBELL_UDB);
1856 setbit(&sc->doorbells, DOORBELL_WCWR);
1857 setbit(&sc->doorbells, DOORBELL_UDBWC);
1859 device_printf(sc->dev,
1860 "couldn't enable write combining: %d\n",
1864 t4_write_reg(sc, A_SGE_STAT_CFG,
1865 V_STATSOURCE_T5(7) | V_STATMODE(0));
1873 struct memwin_init {
1878 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
1879 { MEMWIN0_BASE, MEMWIN0_APERTURE },
1880 { MEMWIN1_BASE, MEMWIN1_APERTURE },
1881 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
1884 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
1885 { MEMWIN0_BASE, MEMWIN0_APERTURE },
1886 { MEMWIN1_BASE, MEMWIN1_APERTURE },
1887 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
1891 setup_memwin(struct adapter *sc)
1893 const struct memwin_init *mw_init;
1900 * Read low 32b of bar0 indirectly via the hardware backdoor
1901 * mechanism. Works from within PCI passthrough environments
1902 * too, where rman_get_start() can return a different value. We
1903 * need to program the T4 memory window decoders with the actual
1904 * addresses that will be coming across the PCIe link.
1906 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
1907 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
1909 mw_init = &t4_memwin[0];
1911 /* T5+ use the relative offset inside the PCIe BAR */
1914 mw_init = &t5_memwin[0];
1917 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
1918 rw_init(&mw->mw_lock, "memory window access");
1919 mw->mw_base = mw_init->base;
1920 mw->mw_aperture = mw_init->aperture;
1923 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
1924 (mw->mw_base + bar0) | V_BIR(0) |
1925 V_WINDOW(ilog2(mw->mw_aperture) - 10));
1926 rw_wlock(&mw->mw_lock);
1927 position_memwin(sc, i, 0);
1928 rw_wunlock(&mw->mw_lock);
1932 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
1936 * Positions the memory window at the given address in the card's address space.
1937 * There are some alignment requirements and the actual position may be at an
1938 * address prior to the requested address. mw->mw_curpos always has the actual
1939 * position of the window.
1942 position_memwin(struct adapter *sc, int idx, uint32_t addr)
1948 MPASS(idx >= 0 && idx < NUM_MEMWIN);
1949 mw = &sc->memwin[idx];
1950 rw_assert(&mw->mw_lock, RA_WLOCKED);
1954 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
1956 pf = V_PFNUM(sc->pf);
1957 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
1959 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
1960 t4_write_reg(sc, reg, mw->mw_curpos | pf);
1961 t4_read_reg(sc, reg); /* flush */
1965 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1971 MPASS(idx >= 0 && idx < NUM_MEMWIN);
1973 /* Memory can only be accessed in naturally aligned 4 byte units */
1974 if (addr & 3 || len & 3 || len <= 0)
1977 mw = &sc->memwin[idx];
1979 rw_rlock(&mw->mw_lock);
1980 mw_end = mw->mw_curpos + mw->mw_aperture;
1981 if (addr >= mw_end || addr < mw->mw_curpos) {
1982 /* Will need to reposition the window */
1983 if (!rw_try_upgrade(&mw->mw_lock)) {
1984 rw_runlock(&mw->mw_lock);
1985 rw_wlock(&mw->mw_lock);
1987 rw_assert(&mw->mw_lock, RA_WLOCKED);
1988 position_memwin(sc, idx, addr);
1989 rw_downgrade(&mw->mw_lock);
1990 mw_end = mw->mw_curpos + mw->mw_aperture;
1992 rw_assert(&mw->mw_lock, RA_RLOCKED);
1993 while (addr < mw_end && len > 0) {
1995 v = t4_read_reg(sc, mw->mw_base + addr -
1997 *val++ = le32toh(v);
2000 t4_write_reg(sc, mw->mw_base + addr -
2001 mw->mw_curpos, htole32(v));;
2006 rw_runlock(&mw->mw_lock);
2013 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2017 return (rw_via_memwin(sc, idx, addr, val, len, 0));
2021 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
2022 const uint32_t *val, int len)
2025 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
2029 t4_range_cmp(const void *a, const void *b)
2031 return ((const struct t4_range *)a)->start -
2032 ((const struct t4_range *)b)->start;
2036 * Verify that the memory range specified by the addr/len pair is valid within
2037 * the card's address space.
2040 validate_mem_range(struct adapter *sc, uint32_t addr, int len)
2042 struct t4_range mem_ranges[4], *r, *next;
2043 uint32_t em, addr_len;
2044 int i, n, remaining;
2046 /* Memory can only be accessed in naturally aligned 4 byte units */
2047 if (addr & 3 || len & 3 || len <= 0)
2050 /* Enabled memories */
2051 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2055 bzero(r, sizeof(mem_ranges));
2056 if (em & F_EDRAM0_ENABLE) {
2057 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2058 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2060 r->start = G_EDRAM0_BASE(addr_len) << 20;
2061 if (addr >= r->start &&
2062 addr + len <= r->start + r->size)
2068 if (em & F_EDRAM1_ENABLE) {
2069 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2070 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2072 r->start = G_EDRAM1_BASE(addr_len) << 20;
2073 if (addr >= r->start &&
2074 addr + len <= r->start + r->size)
2080 if (em & F_EXT_MEM_ENABLE) {
2081 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2082 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2084 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2085 if (addr >= r->start &&
2086 addr + len <= r->start + r->size)
2092 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2093 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2094 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2096 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2097 if (addr >= r->start &&
2098 addr + len <= r->start + r->size)
2104 MPASS(n <= nitems(mem_ranges));
2107 /* Sort and merge the ranges. */
2108 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2110 /* Start from index 0 and examine the next n - 1 entries. */
2112 for (remaining = n - 1; remaining > 0; remaining--, r++) {
2114 MPASS(r->size > 0); /* r is a valid entry. */
2116 MPASS(next->size > 0); /* and so is the next one. */
2118 while (r->start + r->size >= next->start) {
2119 /* Merge the next one into the current entry. */
2120 r->size = max(r->start + r->size,
2121 next->start + next->size) - r->start;
2122 n--; /* One fewer entry in total. */
2123 if (--remaining == 0)
2124 goto done; /* short circuit */
2127 if (next != r + 1) {
2129 * Some entries were merged into r and next
2130 * points to the first valid entry that couldn't
2133 MPASS(next->size > 0); /* must be valid */
2134 memcpy(r + 1, next, remaining * sizeof(*r));
2137 * This so that the foo->size assertion in the
2138 * next iteration of the loop do the right
2139 * thing for entries that were pulled up and are
2142 MPASS(n < nitems(mem_ranges));
2143 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
2144 sizeof(struct t4_range));
2149 /* Done merging the ranges. */
2152 for (i = 0; i < n; i++, r++) {
2153 if (addr >= r->start &&
2154 addr + len <= r->start + r->size)
2163 fwmtype_to_hwmtype(int mtype)
2167 case FW_MEMTYPE_EDC0:
2169 case FW_MEMTYPE_EDC1:
2171 case FW_MEMTYPE_EXTMEM:
2173 case FW_MEMTYPE_EXTMEM1:
2176 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
2181 * Verify that the memory range specified by the memtype/offset/len pair is
2182 * valid and lies entirely within the memtype specified. The global address of
2183 * the start of the range is returned in addr.
2186 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len,
2189 uint32_t em, addr_len, maddr;
2191 /* Memory can only be accessed in naturally aligned 4 byte units */
2192 if (off & 3 || len & 3 || len == 0)
2195 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2196 switch (fwmtype_to_hwmtype(mtype)) {
2198 if (!(em & F_EDRAM0_ENABLE))
2200 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2201 maddr = G_EDRAM0_BASE(addr_len) << 20;
2204 if (!(em & F_EDRAM1_ENABLE))
2206 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2207 maddr = G_EDRAM1_BASE(addr_len) << 20;
2210 if (!(em & F_EXT_MEM_ENABLE))
2212 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2213 maddr = G_EXT_MEM_BASE(addr_len) << 20;
2216 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
2218 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2219 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
2225 *addr = maddr + off; /* global address */
2226 return (validate_mem_range(sc, *addr, len));
2230 fixup_devlog_params(struct adapter *sc)
2232 struct devlog_params *dparams = &sc->params.devlog;
2235 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
2236 dparams->size, &dparams->addr);
2242 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, int num_vis,
2243 struct intrs_and_queues *iaq)
2245 int rc, itype, navail, nrxq10g, nrxq1g, n;
2246 int nofldrxq10g = 0, nofldrxq1g = 0;
2248 bzero(iaq, sizeof(*iaq));
2250 iaq->ntxq10g = t4_ntxq10g;
2251 iaq->ntxq1g = t4_ntxq1g;
2252 iaq->ntxq_vi = t4_ntxq_vi;
2253 iaq->nrxq10g = nrxq10g = t4_nrxq10g;
2254 iaq->nrxq1g = nrxq1g = t4_nrxq1g;
2255 iaq->nrxq_vi = t4_nrxq_vi;
2256 iaq->rsrv_noflowq = t4_rsrv_noflowq;
2258 if (is_offload(sc)) {
2259 iaq->nofldtxq10g = t4_nofldtxq10g;
2260 iaq->nofldtxq1g = t4_nofldtxq1g;
2261 iaq->nofldtxq_vi = t4_nofldtxq_vi;
2262 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g;
2263 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g;
2264 iaq->nofldrxq_vi = t4_nofldrxq_vi;
2268 iaq->nnmtxq_vi = t4_nnmtxq_vi;
2269 iaq->nnmrxq_vi = t4_nnmrxq_vi;
2272 for (itype = INTR_MSIX; itype; itype >>= 1) {
2274 if ((itype & t4_intr_types) == 0)
2275 continue; /* not allowed */
2277 if (itype == INTR_MSIX)
2278 navail = pci_msix_count(sc->dev);
2279 else if (itype == INTR_MSI)
2280 navail = pci_msi_count(sc->dev);
2287 iaq->intr_type = itype;
2288 iaq->intr_flags_10g = 0;
2289 iaq->intr_flags_1g = 0;
2292 * Best option: an interrupt vector for errors, one for the
2293 * firmware event queue, and one for every rxq (NIC and TOE) of
2294 * every VI. The VIs that support netmap use the same
2295 * interrupts for the NIC rx queues and the netmap rx queues
2296 * because only one set of queues is active at a time.
2298 iaq->nirq = T4_EXTRA_INTR;
2299 iaq->nirq += n10g * (nrxq10g + nofldrxq10g);
2300 iaq->nirq += n1g * (nrxq1g + nofldrxq1g);
2301 iaq->nirq += (n10g + n1g) * (num_vis - 1) *
2302 max(iaq->nrxq_vi, iaq->nnmrxq_vi); /* See comment above. */
2303 iaq->nirq += (n10g + n1g) * (num_vis - 1) * iaq->nofldrxq_vi;
2304 if (iaq->nirq <= navail &&
2305 (itype != INTR_MSI || powerof2(iaq->nirq))) {
2306 iaq->intr_flags_10g = INTR_ALL;
2307 iaq->intr_flags_1g = INTR_ALL;
2311 /* Disable the VIs (and netmap) if there aren't enough intrs */
2313 device_printf(sc->dev, "virtual interfaces disabled "
2314 "because num_vis=%u with current settings "
2315 "(nrxq10g=%u, nrxq1g=%u, nofldrxq10g=%u, "
2316 "nofldrxq1g=%u, nrxq_vi=%u nofldrxq_vi=%u, "
2317 "nnmrxq_vi=%u) would need %u interrupts but "
2318 "only %u are available.\n", num_vis, nrxq10g,
2319 nrxq1g, nofldrxq10g, nofldrxq1g, iaq->nrxq_vi,
2320 iaq->nofldrxq_vi, iaq->nnmrxq_vi, iaq->nirq,
2323 iaq->ntxq_vi = iaq->nrxq_vi = 0;
2324 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
2325 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
2330 * Second best option: a vector for errors, one for the firmware
2331 * event queue, and vectors for either all the NIC rx queues or
2332 * all the TOE rx queues. The queues that don't get vectors
2333 * will forward their interrupts to those that do.
2335 iaq->nirq = T4_EXTRA_INTR;
2336 if (nrxq10g >= nofldrxq10g) {
2337 iaq->intr_flags_10g = INTR_RXQ;
2338 iaq->nirq += n10g * nrxq10g;
2340 iaq->intr_flags_10g = INTR_OFLD_RXQ;
2341 iaq->nirq += n10g * nofldrxq10g;
2343 if (nrxq1g >= nofldrxq1g) {
2344 iaq->intr_flags_1g = INTR_RXQ;
2345 iaq->nirq += n1g * nrxq1g;
2347 iaq->intr_flags_1g = INTR_OFLD_RXQ;
2348 iaq->nirq += n1g * nofldrxq1g;
2350 if (iaq->nirq <= navail &&
2351 (itype != INTR_MSI || powerof2(iaq->nirq)))
2355 * Next best option: an interrupt vector for errors, one for the
2356 * firmware event queue, and at least one per main-VI. At this
2357 * point we know we'll have to downsize nrxq and/or nofldrxq to
2358 * fit what's available to us.
2360 iaq->nirq = T4_EXTRA_INTR;
2361 iaq->nirq += n10g + n1g;
2362 if (iaq->nirq <= navail) {
2363 int leftover = navail - iaq->nirq;
2366 int target = max(nrxq10g, nofldrxq10g);
2368 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ?
2369 INTR_RXQ : INTR_OFLD_RXQ;
2372 while (n < target && leftover >= n10g) {
2377 iaq->nrxq10g = min(n, nrxq10g);
2379 iaq->nofldrxq10g = min(n, nofldrxq10g);
2384 int target = max(nrxq1g, nofldrxq1g);
2386 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ?
2387 INTR_RXQ : INTR_OFLD_RXQ;
2390 while (n < target && leftover >= n1g) {
2395 iaq->nrxq1g = min(n, nrxq1g);
2397 iaq->nofldrxq1g = min(n, nofldrxq1g);
2401 if (itype != INTR_MSI || powerof2(iaq->nirq))
2406 * Least desirable option: one interrupt vector for everything.
2408 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1;
2409 iaq->intr_flags_10g = iaq->intr_flags_1g = 0;
2412 iaq->nofldrxq10g = iaq->nofldrxq1g = 1;
2417 if (itype == INTR_MSIX)
2418 rc = pci_alloc_msix(sc->dev, &navail);
2419 else if (itype == INTR_MSI)
2420 rc = pci_alloc_msi(sc->dev, &navail);
2423 if (navail == iaq->nirq)
2427 * Didn't get the number requested. Use whatever number
2428 * the kernel is willing to allocate (it's in navail).
2430 device_printf(sc->dev, "fewer vectors than requested, "
2431 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
2432 itype, iaq->nirq, navail);
2433 pci_release_msi(sc->dev);
2437 device_printf(sc->dev,
2438 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
2439 itype, rc, iaq->nirq, navail);
2442 device_printf(sc->dev,
2443 "failed to find a usable interrupt type. "
2444 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
2445 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
2450 #define FW_VERSION(chip) ( \
2451 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
2452 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
2453 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
2454 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
2455 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
2461 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */
2465 .kld_name = "t4fw_cfg",
2466 .fw_mod_name = "t4fw",
2468 .chip = FW_HDR_CHIP_T4,
2469 .fw_ver = htobe32_const(FW_VERSION(T4)),
2470 .intfver_nic = FW_INTFVER(T4, NIC),
2471 .intfver_vnic = FW_INTFVER(T4, VNIC),
2472 .intfver_ofld = FW_INTFVER(T4, OFLD),
2473 .intfver_ri = FW_INTFVER(T4, RI),
2474 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
2475 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
2476 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
2477 .intfver_fcoe = FW_INTFVER(T4, FCOE),
2481 .kld_name = "t5fw_cfg",
2482 .fw_mod_name = "t5fw",
2484 .chip = FW_HDR_CHIP_T5,
2485 .fw_ver = htobe32_const(FW_VERSION(T5)),
2486 .intfver_nic = FW_INTFVER(T5, NIC),
2487 .intfver_vnic = FW_INTFVER(T5, VNIC),
2488 .intfver_ofld = FW_INTFVER(T5, OFLD),
2489 .intfver_ri = FW_INTFVER(T5, RI),
2490 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
2491 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2492 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
2493 .intfver_fcoe = FW_INTFVER(T5, FCOE),
2498 static struct fw_info *
2499 find_fw_info(int chip)
2503 for (i = 0; i < nitems(fw_info); i++) {
2504 if (fw_info[i].chip == chip)
2505 return (&fw_info[i]);
2511 * Is the given firmware API compatible with the one the driver was compiled
2515 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
2518 /* short circuit if it's the exact same firmware version */
2519 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
2523 * XXX: Is this too conservative? Perhaps I should limit this to the
2524 * features that are supported in the driver.
2526 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
2527 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
2528 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
2529 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
2537 * The firmware in the KLD is usable, but should it be installed? This routine
2538 * explains itself in detail if it indicates the KLD firmware should be
2542 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
2546 if (!card_fw_usable) {
2547 reason = "incompatible or unusable";
2552 reason = "older than the version bundled with this driver";
2556 if (t4_fw_install == 2 && k != c) {
2557 reason = "different than the version bundled with this driver";
2564 if (t4_fw_install == 0) {
2565 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2566 "but the driver is prohibited from installing a different "
2567 "firmware on the card.\n",
2568 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2569 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
2574 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2575 "installing firmware %u.%u.%u.%u on card.\n",
2576 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2577 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
2578 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2579 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2584 * Establish contact with the firmware and determine if we are the master driver
2585 * or not, and whether we are responsible for chip initialization.
2588 prep_firmware(struct adapter *sc)
2590 const struct firmware *fw = NULL, *default_cfg;
2591 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
2592 enum dev_state state;
2593 struct fw_info *fw_info;
2594 struct fw_hdr *card_fw; /* fw on the card */
2595 const struct fw_hdr *kld_fw; /* fw in the KLD */
2596 const struct fw_hdr *drv_fw; /* fw header the driver was compiled
2599 /* Contact firmware. */
2600 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
2601 if (rc < 0 || state == DEV_STATE_ERR) {
2603 device_printf(sc->dev,
2604 "failed to connect to the firmware: %d, %d.\n", rc, state);
2609 sc->flags |= MASTER_PF;
2610 else if (state == DEV_STATE_UNINIT) {
2612 * We didn't get to be the master so we definitely won't be
2613 * configuring the chip. It's a bug if someone else hasn't
2614 * configured it already.
2616 device_printf(sc->dev, "couldn't be master(%d), "
2617 "device not already initialized either(%d).\n", rc, state);
2621 /* This is the firmware whose headers the driver was compiled against */
2622 fw_info = find_fw_info(chip_id(sc));
2623 if (fw_info == NULL) {
2624 device_printf(sc->dev,
2625 "unable to look up firmware information for chip %d.\n",
2629 drv_fw = &fw_info->fw_hdr;
2632 * The firmware KLD contains many modules. The KLD name is also the
2633 * name of the module that contains the default config file.
2635 default_cfg = firmware_get(fw_info->kld_name);
2637 /* Read the header of the firmware on the card */
2638 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
2639 rc = -t4_read_flash(sc, FLASH_FW_START,
2640 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
2642 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
2644 device_printf(sc->dev,
2645 "Unable to read card's firmware header: %d\n", rc);
2649 /* This is the firmware in the KLD */
2650 fw = firmware_get(fw_info->fw_mod_name);
2652 kld_fw = (const void *)fw->data;
2653 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
2659 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
2660 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
2662 * Common case: the firmware on the card is an exact match and
2663 * the KLD is an exact match too, or the KLD is
2664 * absent/incompatible. Note that t4_fw_install = 2 is ignored
2665 * here -- use cxgbetool loadfw if you want to reinstall the
2666 * same firmware as the one on the card.
2668 } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
2669 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
2670 be32toh(card_fw->fw_ver))) {
2672 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
2674 device_printf(sc->dev,
2675 "failed to install firmware: %d\n", rc);
2679 /* Installed successfully, update the cached header too. */
2680 memcpy(card_fw, kld_fw, sizeof(*card_fw));
2682 need_fw_reset = 0; /* already reset as part of load_fw */
2685 if (!card_fw_usable) {
2688 d = ntohl(drv_fw->fw_ver);
2689 c = ntohl(card_fw->fw_ver);
2690 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
2692 device_printf(sc->dev, "Cannot find a usable firmware: "
2693 "fw_install %d, chip state %d, "
2694 "driver compiled with %d.%d.%d.%d, "
2695 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
2696 t4_fw_install, state,
2697 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
2698 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
2699 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2700 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
2701 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2702 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2707 /* We're using whatever's on the card and it's known to be good. */
2708 sc->params.fw_vers = ntohl(card_fw->fw_ver);
2709 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
2710 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
2711 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
2712 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
2713 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
2714 t4_get_tp_version(sc, &sc->params.tp_vers);
2717 if (need_fw_reset &&
2718 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
2719 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
2720 if (rc != ETIMEDOUT && rc != EIO)
2721 t4_fw_bye(sc, sc->mbox);
2726 rc = get_params__pre_init(sc);
2728 goto done; /* error message displayed already */
2730 /* Partition adapter resources as specified in the config file. */
2731 if (state == DEV_STATE_UNINIT) {
2733 KASSERT(sc->flags & MASTER_PF,
2734 ("%s: trying to change chip settings when not master.",
2737 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
2739 goto done; /* error message displayed already */
2741 t4_tweak_chip_settings(sc);
2743 /* get basic stuff going */
2744 rc = -t4_fw_initialize(sc, sc->mbox);
2746 device_printf(sc->dev, "fw init failed: %d.\n", rc);
2750 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
2755 free(card_fw, M_CXGBE);
2757 firmware_put(fw, FIRMWARE_UNLOAD);
2758 if (default_cfg != NULL)
2759 firmware_put(default_cfg, FIRMWARE_UNLOAD);
2764 #define FW_PARAM_DEV(param) \
2765 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
2766 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
2767 #define FW_PARAM_PFVF(param) \
2768 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
2769 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
2772 * Partition chip resources for use between various PFs, VFs, etc.
2775 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
2776 const char *name_prefix)
2778 const struct firmware *cfg = NULL;
2780 struct fw_caps_config_cmd caps;
2781 uint32_t mtype, moff, finicsum, cfcsum;
2784 * Figure out what configuration file to use. Pick the default config
2785 * file for the card if the user hasn't specified one explicitly.
2787 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
2788 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
2789 /* Card specific overrides go here. */
2790 if (pci_get_device(sc->dev) == 0x440a)
2791 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
2793 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
2797 * We need to load another module if the profile is anything except
2798 * "default" or "flash".
2800 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
2801 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2804 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
2805 cfg = firmware_get(s);
2807 if (default_cfg != NULL) {
2808 device_printf(sc->dev,
2809 "unable to load module \"%s\" for "
2810 "configuration profile \"%s\", will use "
2811 "the default config file instead.\n",
2813 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2816 device_printf(sc->dev,
2817 "unable to load module \"%s\" for "
2818 "configuration profile \"%s\", will use "
2819 "the config file on the card's flash "
2820 "instead.\n", s, sc->cfg_file);
2821 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2827 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
2828 default_cfg == NULL) {
2829 device_printf(sc->dev,
2830 "default config file not available, will use the config "
2831 "file on the card's flash instead.\n");
2832 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
2835 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2837 const uint32_t *cfdata;
2838 uint32_t param, val, addr;
2840 KASSERT(cfg != NULL || default_cfg != NULL,
2841 ("%s: no config to upload", __func__));
2844 * Ask the firmware where it wants us to upload the config file.
2846 param = FW_PARAM_DEV(CF);
2847 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2849 /* No support for config file? Shouldn't happen. */
2850 device_printf(sc->dev,
2851 "failed to query config file location: %d.\n", rc);
2854 mtype = G_FW_PARAMS_PARAM_Y(val);
2855 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
2858 * XXX: sheer laziness. We deliberately added 4 bytes of
2859 * useless stuffing/comments at the end of the config file so
2860 * it's ok to simply throw away the last remaining bytes when
2861 * the config file is not an exact multiple of 4. This also
2862 * helps with the validate_mt_off_len check.
2865 cflen = cfg->datasize & ~3;
2868 cflen = default_cfg->datasize & ~3;
2869 cfdata = default_cfg->data;
2872 if (cflen > FLASH_CFG_MAX_SIZE) {
2873 device_printf(sc->dev,
2874 "config file too long (%d, max allowed is %d). "
2875 "Will try to use the config on the card, if any.\n",
2876 cflen, FLASH_CFG_MAX_SIZE);
2877 goto use_config_on_flash;
2880 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
2882 device_printf(sc->dev,
2883 "%s: addr (%d/0x%x) or len %d is not valid: %d. "
2884 "Will try to use the config on the card, if any.\n",
2885 __func__, mtype, moff, cflen, rc);
2886 goto use_config_on_flash;
2888 write_via_memwin(sc, 2, addr, cfdata, cflen);
2890 use_config_on_flash:
2891 mtype = FW_MEMTYPE_FLASH;
2892 moff = t4_flash_cfg_addr(sc);
2895 bzero(&caps, sizeof(caps));
2896 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2897 F_FW_CMD_REQUEST | F_FW_CMD_READ);
2898 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
2899 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
2900 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
2901 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
2903 device_printf(sc->dev,
2904 "failed to pre-process config file: %d "
2905 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
2909 finicsum = be32toh(caps.finicsum);
2910 cfcsum = be32toh(caps.cfcsum);
2911 if (finicsum != cfcsum) {
2912 device_printf(sc->dev,
2913 "WARNING: config file checksum mismatch: %08x %08x\n",
2916 sc->cfcsum = cfcsum;
2918 #define LIMIT_CAPS(x) do { \
2919 caps.x &= htobe16(t4_##x##_allowed); \
2923 * Let the firmware know what features will (not) be used so it can tune
2924 * things accordingly.
2926 LIMIT_CAPS(nbmcaps);
2927 LIMIT_CAPS(linkcaps);
2928 LIMIT_CAPS(switchcaps);
2929 LIMIT_CAPS(niccaps);
2930 LIMIT_CAPS(toecaps);
2931 LIMIT_CAPS(rdmacaps);
2932 LIMIT_CAPS(tlscaps);
2933 LIMIT_CAPS(iscsicaps);
2934 LIMIT_CAPS(fcoecaps);
2937 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2938 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
2939 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
2940 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
2942 device_printf(sc->dev,
2943 "failed to process config file: %d.\n", rc);
2947 firmware_put(cfg, FIRMWARE_UNLOAD);
2952 * Retrieve parameters that are needed (or nice to have) very early.
2955 get_params__pre_init(struct adapter *sc)
2958 uint32_t param[2], val[2];
2960 param[0] = FW_PARAM_DEV(PORTVEC);
2961 param[1] = FW_PARAM_DEV(CCLK);
2962 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
2964 device_printf(sc->dev,
2965 "failed to query parameters (pre_init): %d.\n", rc);
2969 sc->params.portvec = val[0];
2970 sc->params.nports = bitcount32(val[0]);
2971 sc->params.vpd.cclk = val[1];
2973 /* Read device log parameters. */
2974 rc = -t4_init_devlog_params(sc, 1);
2976 fixup_devlog_params(sc);
2978 device_printf(sc->dev,
2979 "failed to get devlog parameters: %d.\n", rc);
2980 rc = 0; /* devlog isn't critical for device operation */
2987 * Retrieve various parameters that are of interest to the driver. The device
2988 * has been initialized by the firmware at this point.
2991 get_params__post_init(struct adapter *sc)
2994 uint32_t param[7], val[7];
2995 struct fw_caps_config_cmd caps;
2997 param[0] = FW_PARAM_PFVF(IQFLINT_START);
2998 param[1] = FW_PARAM_PFVF(EQ_START);
2999 param[2] = FW_PARAM_PFVF(FILTER_START);
3000 param[3] = FW_PARAM_PFVF(FILTER_END);
3001 param[4] = FW_PARAM_PFVF(L2T_START);
3002 param[5] = FW_PARAM_PFVF(L2T_END);
3003 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3005 device_printf(sc->dev,
3006 "failed to query parameters (post_init): %d.\n", rc);
3010 sc->sge.iq_start = val[0];
3011 sc->sge.eq_start = val[1];
3012 sc->tids.ftid_base = val[2];
3013 sc->tids.nftids = val[3] - val[2] + 1;
3014 sc->params.ftid_min = val[2];
3015 sc->params.ftid_max = val[3];
3016 sc->vres.l2t.start = val[4];
3017 sc->vres.l2t.size = val[5] - val[4] + 1;
3018 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
3019 ("%s: L2 table size (%u) larger than expected (%u)",
3020 __func__, sc->vres.l2t.size, L2T_SIZE));
3022 /* get capabilites */
3023 bzero(&caps, sizeof(caps));
3024 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3025 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3026 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3027 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3029 device_printf(sc->dev,
3030 "failed to get card capabilities: %d.\n", rc);
3034 #define READ_CAPS(x) do { \
3035 sc->x = htobe16(caps.x); \
3038 READ_CAPS(linkcaps);
3039 READ_CAPS(switchcaps);
3042 READ_CAPS(rdmacaps);
3044 READ_CAPS(iscsicaps);
3045 READ_CAPS(fcoecaps);
3047 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3048 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3049 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3050 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3051 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
3053 device_printf(sc->dev,
3054 "failed to query NIC parameters: %d.\n", rc);
3057 sc->tids.etid_base = val[0];
3058 sc->params.etid_min = val[0];
3059 sc->tids.netids = val[1] - val[0] + 1;
3060 sc->params.netids = sc->tids.netids;
3061 sc->params.eo_wr_cred = val[2];
3062 sc->params.ethoffload = 1;
3066 /* query offload-related parameters */
3067 param[0] = FW_PARAM_DEV(NTID);
3068 param[1] = FW_PARAM_PFVF(SERVER_START);
3069 param[2] = FW_PARAM_PFVF(SERVER_END);
3070 param[3] = FW_PARAM_PFVF(TDDP_START);
3071 param[4] = FW_PARAM_PFVF(TDDP_END);
3072 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3073 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3075 device_printf(sc->dev,
3076 "failed to query TOE parameters: %d.\n", rc);
3079 sc->tids.ntids = val[0];
3080 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
3081 sc->tids.stid_base = val[1];
3082 sc->tids.nstids = val[2] - val[1] + 1;
3083 sc->vres.ddp.start = val[3];
3084 sc->vres.ddp.size = val[4] - val[3] + 1;
3085 sc->params.ofldq_wr_cred = val[5];
3086 sc->params.offload = 1;
3089 param[0] = FW_PARAM_PFVF(STAG_START);
3090 param[1] = FW_PARAM_PFVF(STAG_END);
3091 param[2] = FW_PARAM_PFVF(RQ_START);
3092 param[3] = FW_PARAM_PFVF(RQ_END);
3093 param[4] = FW_PARAM_PFVF(PBL_START);
3094 param[5] = FW_PARAM_PFVF(PBL_END);
3095 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3097 device_printf(sc->dev,
3098 "failed to query RDMA parameters(1): %d.\n", rc);
3101 sc->vres.stag.start = val[0];
3102 sc->vres.stag.size = val[1] - val[0] + 1;
3103 sc->vres.rq.start = val[2];
3104 sc->vres.rq.size = val[3] - val[2] + 1;
3105 sc->vres.pbl.start = val[4];
3106 sc->vres.pbl.size = val[5] - val[4] + 1;
3108 param[0] = FW_PARAM_PFVF(SQRQ_START);
3109 param[1] = FW_PARAM_PFVF(SQRQ_END);
3110 param[2] = FW_PARAM_PFVF(CQ_START);
3111 param[3] = FW_PARAM_PFVF(CQ_END);
3112 param[4] = FW_PARAM_PFVF(OCQ_START);
3113 param[5] = FW_PARAM_PFVF(OCQ_END);
3114 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3116 device_printf(sc->dev,
3117 "failed to query RDMA parameters(2): %d.\n", rc);
3120 sc->vres.qp.start = val[0];
3121 sc->vres.qp.size = val[1] - val[0] + 1;
3122 sc->vres.cq.start = val[2];
3123 sc->vres.cq.size = val[3] - val[2] + 1;
3124 sc->vres.ocq.start = val[4];
3125 sc->vres.ocq.size = val[5] - val[4] + 1;
3127 if (sc->iscsicaps) {
3128 param[0] = FW_PARAM_PFVF(ISCSI_START);
3129 param[1] = FW_PARAM_PFVF(ISCSI_END);
3130 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3132 device_printf(sc->dev,
3133 "failed to query iSCSI parameters: %d.\n", rc);
3136 sc->vres.iscsi.start = val[0];
3137 sc->vres.iscsi.size = val[1] - val[0] + 1;
3141 * We've got the params we wanted to query via the firmware. Now grab
3142 * some others directly from the chip.
3144 rc = t4_read_chip_settings(sc);
3150 set_params__post_init(struct adapter *sc)
3152 uint32_t param, val;
3154 /* ask for encapsulated CPLs */
3155 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3157 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3162 #undef FW_PARAM_PFVF
3166 t4_set_desc(struct adapter *sc)
3169 struct adapter_params *p = &sc->params;
3171 snprintf(buf, sizeof(buf), "Chelsio %s %sNIC (rev %d), S/N:%s, "
3172 "P/N:%s, E/C:%s", p->vpd.id, is_offload(sc) ? "R" : "",
3173 chip_rev(sc), p->vpd.sn, p->vpd.pn, p->vpd.ec);
3175 device_set_desc_copy(sc->dev, buf);
3179 build_medialist(struct port_info *pi, struct ifmedia *media)
3185 ifmedia_removeall(media);
3187 m = IFM_ETHER | IFM_FDX;
3189 switch(pi->port_type) {
3190 case FW_PORT_TYPE_BT_XFI:
3191 case FW_PORT_TYPE_BT_XAUI:
3192 ifmedia_add(media, m | IFM_10G_T, 0, NULL);
3195 case FW_PORT_TYPE_BT_SGMII:
3196 ifmedia_add(media, m | IFM_1000_T, 0, NULL);
3197 ifmedia_add(media, m | IFM_100_TX, 0, NULL);
3198 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL);
3199 ifmedia_set(media, IFM_ETHER | IFM_AUTO);
3202 case FW_PORT_TYPE_CX4:
3203 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL);
3204 ifmedia_set(media, m | IFM_10G_CX4);
3207 case FW_PORT_TYPE_QSFP_10G:
3208 case FW_PORT_TYPE_SFP:
3209 case FW_PORT_TYPE_FIBER_XFI:
3210 case FW_PORT_TYPE_FIBER_XAUI:
3211 switch (pi->mod_type) {
3213 case FW_PORT_MOD_TYPE_LR:
3214 ifmedia_add(media, m | IFM_10G_LR, 0, NULL);
3215 ifmedia_set(media, m | IFM_10G_LR);
3218 case FW_PORT_MOD_TYPE_SR:
3219 ifmedia_add(media, m | IFM_10G_SR, 0, NULL);
3220 ifmedia_set(media, m | IFM_10G_SR);
3223 case FW_PORT_MOD_TYPE_LRM:
3224 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL);
3225 ifmedia_set(media, m | IFM_10G_LRM);
3228 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3229 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3230 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL);
3231 ifmedia_set(media, m | IFM_10G_TWINAX);
3234 case FW_PORT_MOD_TYPE_NONE:
3236 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3237 ifmedia_set(media, m | IFM_NONE);
3240 case FW_PORT_MOD_TYPE_NA:
3241 case FW_PORT_MOD_TYPE_ER:
3243 device_printf(pi->dev,
3244 "unknown port_type (%d), mod_type (%d)\n",
3245 pi->port_type, pi->mod_type);
3246 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3247 ifmedia_set(media, m | IFM_UNKNOWN);
3252 case FW_PORT_TYPE_QSFP:
3253 switch (pi->mod_type) {
3255 case FW_PORT_MOD_TYPE_LR:
3256 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL);
3257 ifmedia_set(media, m | IFM_40G_LR4);
3260 case FW_PORT_MOD_TYPE_SR:
3261 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL);
3262 ifmedia_set(media, m | IFM_40G_SR4);
3265 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3266 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3267 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL);
3268 ifmedia_set(media, m | IFM_40G_CR4);
3271 case FW_PORT_MOD_TYPE_NONE:
3273 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3274 ifmedia_set(media, m | IFM_NONE);
3278 device_printf(pi->dev,
3279 "unknown port_type (%d), mod_type (%d)\n",
3280 pi->port_type, pi->mod_type);
3281 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3282 ifmedia_set(media, m | IFM_UNKNOWN);
3288 device_printf(pi->dev,
3289 "unknown port_type (%d), mod_type (%d)\n", pi->port_type,
3291 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3292 ifmedia_set(media, m | IFM_UNKNOWN);
3299 #define FW_MAC_EXACT_CHUNK 7
3302 * Program the port's XGMAC based on parameters in ifnet. The caller also
3303 * indicates which parameters should be programmed (the rest are left alone).
3306 update_mac_settings(struct ifnet *ifp, int flags)
3309 struct vi_info *vi = ifp->if_softc;
3310 struct port_info *pi = vi->pi;
3311 struct adapter *sc = pi->adapter;
3312 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
3314 ASSERT_SYNCHRONIZED_OP(sc);
3315 KASSERT(flags, ("%s: not told what to update.", __func__));
3317 if (flags & XGMAC_MTU)
3320 if (flags & XGMAC_PROMISC)
3321 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
3323 if (flags & XGMAC_ALLMULTI)
3324 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
3326 if (flags & XGMAC_VLANEX)
3327 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
3329 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
3330 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
3331 allmulti, 1, vlanex, false);
3333 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
3339 if (flags & XGMAC_UCADDR) {
3340 uint8_t ucaddr[ETHER_ADDR_LEN];
3342 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
3343 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
3344 ucaddr, true, true);
3347 if_printf(ifp, "change_mac failed: %d\n", rc);
3350 vi->xact_addr_filt = rc;
3355 if (flags & XGMAC_MCADDRS) {
3356 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
3359 struct ifmultiaddr *ifma;
3362 if_maddr_rlock(ifp);
3363 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3364 if (ifma->ifma_addr->sa_family != AF_LINK)
3367 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
3368 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
3371 if (i == FW_MAC_EXACT_CHUNK) {
3372 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
3373 del, i, mcaddr, NULL, &hash, 0);
3376 for (j = 0; j < i; j++) {
3378 "failed to add mc address"
3380 "%02x:%02x:%02x rc=%d\n",
3381 mcaddr[j][0], mcaddr[j][1],
3382 mcaddr[j][2], mcaddr[j][3],
3383 mcaddr[j][4], mcaddr[j][5],
3393 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
3394 mcaddr, NULL, &hash, 0);
3397 for (j = 0; j < i; j++) {
3399 "failed to add mc address"
3401 "%02x:%02x:%02x rc=%d\n",
3402 mcaddr[j][0], mcaddr[j][1],
3403 mcaddr[j][2], mcaddr[j][3],
3404 mcaddr[j][4], mcaddr[j][5],
3411 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
3413 if_printf(ifp, "failed to set mc address hash: %d", rc);
3415 if_maddr_runlock(ifp);
3422 * {begin|end}_synchronized_op must be called from the same thread.
3425 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
3431 /* the caller thinks it's ok to sleep, but is it really? */
3432 if (flags & SLEEP_OK)
3433 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
3434 "begin_synchronized_op");
3445 if (vi && IS_DOOMED(vi)) {
3455 if (!(flags & SLEEP_OK)) {
3460 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
3466 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
3469 sc->last_op = wmesg;
3470 sc->last_op_thr = curthread;
3471 sc->last_op_flags = flags;
3475 if (!(flags & HOLD_LOCK) || rc)
3482 * Tell if_ioctl and if_init that the VI is going away. This is
3483 * special variant of begin_synchronized_op and must be paired with a
3484 * call to end_synchronized_op.
3487 doom_vi(struct adapter *sc, struct vi_info *vi)
3494 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
3497 sc->last_op = "t4detach";
3498 sc->last_op_thr = curthread;
3499 sc->last_op_flags = 0;
3505 * {begin|end}_synchronized_op must be called from the same thread.
3508 end_synchronized_op(struct adapter *sc, int flags)
3511 if (flags & LOCK_HELD)
3512 ADAPTER_LOCK_ASSERT_OWNED(sc);
3516 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
3523 cxgbe_init_synchronized(struct vi_info *vi)
3525 struct port_info *pi = vi->pi;
3526 struct adapter *sc = pi->adapter;
3527 struct ifnet *ifp = vi->ifp;
3529 struct sge_txq *txq;
3531 ASSERT_SYNCHRONIZED_OP(sc);
3533 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3534 return (0); /* already running */
3536 if (!(sc->flags & FULL_INIT_DONE) &&
3537 ((rc = adapter_full_init(sc)) != 0))
3538 return (rc); /* error message displayed already */
3540 if (!(vi->flags & VI_INIT_DONE) &&
3541 ((rc = vi_full_init(vi)) != 0))
3542 return (rc); /* error message displayed already */
3544 rc = update_mac_settings(ifp, XGMAC_ALL);
3546 goto done; /* error message displayed already */
3548 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
3550 if_printf(ifp, "enable_vi failed: %d\n", rc);
3555 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
3559 for_each_txq(vi, i, txq) {
3561 txq->eq.flags |= EQ_ENABLED;
3566 * The first iq of the first port to come up is used for tracing.
3568 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
3569 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
3570 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
3571 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
3572 V_QUEUENUMBER(sc->traceq));
3573 pi->flags |= HAS_TRACEQ;
3578 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3582 callout_reset(&vi->tick, hz, vi_tick, vi);
3584 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
3588 cxgbe_uninit_synchronized(vi);
3597 cxgbe_uninit_synchronized(struct vi_info *vi)
3599 struct port_info *pi = vi->pi;
3600 struct adapter *sc = pi->adapter;
3601 struct ifnet *ifp = vi->ifp;
3603 struct sge_txq *txq;
3605 ASSERT_SYNCHRONIZED_OP(sc);
3607 if (!(vi->flags & VI_INIT_DONE)) {
3608 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING),
3609 ("uninited VI is running"));
3614 * Disable the VI so that all its data in either direction is discarded
3615 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
3616 * tick) intact as the TP can deliver negative advice or data that it's
3617 * holding in its RAM (for an offloaded connection) even after the VI is
3620 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
3622 if_printf(ifp, "disable_vi failed: %d\n", rc);
3626 for_each_txq(vi, i, txq) {
3628 txq->eq.flags &= ~EQ_ENABLED;
3634 callout_stop(&pi->tick);
3636 callout_stop(&vi->tick);
3637 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3641 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3643 if (pi->up_vis > 0) {
3649 pi->link_cfg.link_ok = 0;
3650 pi->link_cfg.speed = 0;
3652 t4_os_link_changed(sc, pi->port_id, 0, -1);
3658 * It is ok for this function to fail midway and return right away. t4_detach
3659 * will walk the entire sc->irq list and clean up whatever is valid.
3662 setup_intr_handlers(struct adapter *sc)
3664 int rc, rid, p, q, v;
3667 struct port_info *pi;
3669 struct sge *sge = &sc->sge;
3670 struct sge_rxq *rxq;
3672 struct sge_ofld_rxq *ofld_rxq;
3675 struct sge_nm_rxq *nm_rxq;
3682 rid = sc->intr_type == INTR_INTX ? 0 : 1;
3683 if (sc->intr_count == 1)
3684 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
3686 /* Multiple interrupts. */
3687 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
3688 ("%s: too few intr.", __func__));
3690 /* The first one is always error intr */
3691 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
3697 /* The second one is always the firmware event queue */
3698 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
3704 for_each_port(sc, p) {
3706 for_each_vi(pi, v, vi) {
3707 vi->first_intr = rid - 1;
3709 if (vi->nnmrxq > 0) {
3710 int n = max(vi->nrxq, vi->nnmrxq);
3712 MPASS(vi->flags & INTR_RXQ);
3714 rxq = &sge->rxq[vi->first_rxq];
3716 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
3718 for (q = 0; q < n; q++) {
3719 snprintf(s, sizeof(s), "%x%c%x", p,
3725 irq->nm_rxq = nm_rxq++;
3727 rc = t4_alloc_irq(sc, irq, rid,
3728 t4_vi_intr, irq, s);
3735 } else if (vi->flags & INTR_RXQ) {
3736 for_each_rxq(vi, q, rxq) {
3737 snprintf(s, sizeof(s), "%x%c%x", p,
3739 rc = t4_alloc_irq(sc, irq, rid,
3749 if (vi->flags & INTR_OFLD_RXQ) {
3750 for_each_ofld_rxq(vi, q, ofld_rxq) {
3751 snprintf(s, sizeof(s), "%x%c%x", p,
3753 rc = t4_alloc_irq(sc, irq, rid,
3754 t4_intr, ofld_rxq, s);
3765 MPASS(irq == &sc->irq[sc->intr_count]);
3771 adapter_full_init(struct adapter *sc)
3775 ASSERT_SYNCHRONIZED_OP(sc);
3776 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3777 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
3778 ("%s: FULL_INIT_DONE already", __func__));
3781 * queues that belong to the adapter (not any particular port).
3783 rc = t4_setup_adapter_queues(sc);
3787 for (i = 0; i < nitems(sc->tq); i++) {
3788 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
3789 taskqueue_thread_enqueue, &sc->tq[i]);
3790 if (sc->tq[i] == NULL) {
3791 device_printf(sc->dev,
3792 "failed to allocate task queue %d\n", i);
3796 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
3797 device_get_nameunit(sc->dev), i);
3801 sc->flags |= FULL_INIT_DONE;
3804 adapter_full_uninit(sc);
3810 adapter_full_uninit(struct adapter *sc)
3814 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3816 t4_teardown_adapter_queues(sc);
3818 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
3819 taskqueue_free(sc->tq[i]);
3823 sc->flags &= ~FULL_INIT_DONE;
3829 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
3830 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
3831 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
3832 RSS_HASHTYPE_RSS_UDP_IPV6)
3834 /* Translates kernel hash types to hardware. */
3836 hashconfig_to_hashen(int hashconfig)
3840 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
3841 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
3842 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
3843 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
3844 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
3845 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
3846 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
3848 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
3849 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
3850 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
3852 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
3853 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
3854 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
3855 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
3860 /* Translates hardware hash types to kernel. */
3862 hashen_to_hashconfig(int hashen)
3866 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
3868 * If UDP hashing was enabled it must have been enabled for
3869 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
3870 * enabling any 4-tuple hash is nonsense configuration.
3872 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
3873 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
3875 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
3876 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
3877 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
3878 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
3880 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
3881 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
3882 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
3883 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
3884 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3885 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
3886 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3887 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
3889 return (hashconfig);
3894 vi_full_init(struct vi_info *vi)
3896 struct adapter *sc = vi->pi->adapter;
3897 struct ifnet *ifp = vi->ifp;
3899 struct sge_rxq *rxq;
3900 int rc, i, j, hashen;
3902 int nbuckets = rss_getnumbuckets();
3903 int hashconfig = rss_gethashconfig();
3905 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
3906 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
3909 ASSERT_SYNCHRONIZED_OP(sc);
3910 KASSERT((vi->flags & VI_INIT_DONE) == 0,
3911 ("%s: VI_INIT_DONE already", __func__));
3913 sysctl_ctx_init(&vi->ctx);
3914 vi->flags |= VI_SYSCTL_CTX;
3917 * Allocate tx/rx/fl queues for this VI.
3919 rc = t4_setup_vi_queues(vi);
3921 goto done; /* error message displayed already */
3924 * Setup RSS for this VI. Save a copy of the RSS table for later use.
3926 if (vi->nrxq > vi->rss_size) {
3927 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
3928 "some queues will never receive traffic.\n", vi->nrxq,
3930 } else if (vi->rss_size % vi->nrxq) {
3931 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
3932 "expect uneven traffic distribution.\n", vi->nrxq,
3936 MPASS(RSS_KEYSIZE == 40);
3937 if (vi->nrxq != nbuckets) {
3938 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
3939 "performance will be impacted.\n", vi->nrxq, nbuckets);
3942 rss_getkey((void *)&raw_rss_key[0]);
3943 for (i = 0; i < nitems(rss_key); i++) {
3944 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
3946 t4_write_rss_key(sc, &rss_key[0], -1);
3948 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
3949 for (i = 0; i < vi->rss_size;) {
3951 j = rss_get_indirection_to_bucket(i);
3953 rxq = &sc->sge.rxq[vi->first_rxq + j];
3954 rss[i++] = rxq->iq.abs_id;
3956 for_each_rxq(vi, j, rxq) {
3957 rss[i++] = rxq->iq.abs_id;
3958 if (i == vi->rss_size)
3964 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
3967 if_printf(ifp, "rss_config failed: %d\n", rc);
3972 hashen = hashconfig_to_hashen(hashconfig);
3975 * We may have had to enable some hashes even though the global config
3976 * wants them disabled. This is a potential problem that must be
3977 * reported to the user.
3979 extra = hashen_to_hashconfig(hashen) ^ hashconfig;
3982 * If we consider only the supported hash types, then the enabled hashes
3983 * are a superset of the requested hashes. In other words, there cannot
3984 * be any supported hash that was requested but not enabled, but there
3985 * can be hashes that were not requested but had to be enabled.
3987 extra &= SUPPORTED_RSS_HASHTYPES;
3988 MPASS((extra & hashconfig) == 0);
3992 "global RSS config (0x%x) cannot be accomodated.\n",
3995 if (extra & RSS_HASHTYPE_RSS_IPV4)
3996 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
3997 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
3998 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
3999 if (extra & RSS_HASHTYPE_RSS_IPV6)
4000 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
4001 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
4002 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
4003 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
4004 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
4005 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
4006 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
4008 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
4009 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
4010 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4011 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
4013 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0]);
4015 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
4020 vi->flags |= VI_INIT_DONE;
4032 vi_full_uninit(struct vi_info *vi)
4034 struct port_info *pi = vi->pi;
4035 struct adapter *sc = pi->adapter;
4037 struct sge_rxq *rxq;
4038 struct sge_txq *txq;
4040 struct sge_ofld_rxq *ofld_rxq;
4041 struct sge_wrq *ofld_txq;
4044 if (vi->flags & VI_INIT_DONE) {
4046 /* Need to quiesce queues. */
4048 /* XXX: Only for the first VI? */
4050 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
4052 for_each_txq(vi, i, txq) {
4053 quiesce_txq(sc, txq);
4057 for_each_ofld_txq(vi, i, ofld_txq) {
4058 quiesce_wrq(sc, ofld_txq);
4062 for_each_rxq(vi, i, rxq) {
4063 quiesce_iq(sc, &rxq->iq);
4064 quiesce_fl(sc, &rxq->fl);
4068 for_each_ofld_rxq(vi, i, ofld_rxq) {
4069 quiesce_iq(sc, &ofld_rxq->iq);
4070 quiesce_fl(sc, &ofld_rxq->fl);
4073 free(vi->rss, M_CXGBE);
4074 free(vi->nm_rss, M_CXGBE);
4077 t4_teardown_vi_queues(vi);
4078 vi->flags &= ~VI_INIT_DONE;
4084 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
4086 struct sge_eq *eq = &txq->eq;
4087 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4089 (void) sc; /* unused */
4093 MPASS((eq->flags & EQ_ENABLED) == 0);
4097 /* Wait for the mp_ring to empty. */
4098 while (!mp_ring_is_idle(txq->r)) {
4099 mp_ring_check_drainage(txq->r, 0);
4100 pause("rquiesce", 1);
4103 /* Then wait for the hardware to finish. */
4104 while (spg->cidx != htobe16(eq->pidx))
4105 pause("equiesce", 1);
4107 /* Finally, wait for the driver to reclaim all descriptors. */
4108 while (eq->cidx != eq->pidx)
4109 pause("dquiesce", 1);
4113 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
4120 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
4122 (void) sc; /* unused */
4124 /* Synchronize with the interrupt handler */
4125 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
4130 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
4132 mtx_lock(&sc->sfl_lock);
4134 fl->flags |= FL_DOOMED;
4136 callout_stop(&sc->sfl_callout);
4137 mtx_unlock(&sc->sfl_lock);
4139 KASSERT((fl->flags & FL_STARVING) == 0,
4140 ("%s: still starving", __func__));
4144 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
4145 driver_intr_t *handler, void *arg, char *name)
4150 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
4151 RF_SHAREABLE | RF_ACTIVE);
4152 if (irq->res == NULL) {
4153 device_printf(sc->dev,
4154 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
4158 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
4159 NULL, handler, arg, &irq->tag);
4161 device_printf(sc->dev,
4162 "failed to setup interrupt for rid %d, name %s: %d\n",
4165 bus_describe_intr(sc->dev, irq->res, irq->tag, name);
4171 t4_free_irq(struct adapter *sc, struct irq *irq)
4174 bus_teardown_intr(sc->dev, irq->res, irq->tag);
4176 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
4178 bzero(irq, sizeof(*irq));
4184 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
4187 regs->version = chip_id(sc) | chip_rev(sc) << 10;
4188 t4_get_regs(sc, buf, regs->len);
4191 #define A_PL_INDIR_CMD 0x1f8
4193 #define S_PL_AUTOINC 31
4194 #define M_PL_AUTOINC 0x1U
4195 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
4196 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
4198 #define S_PL_VFID 20
4199 #define M_PL_VFID 0xffU
4200 #define V_PL_VFID(x) ((x) << S_PL_VFID)
4201 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
4204 #define M_PL_ADDR 0xfffffU
4205 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
4206 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
4208 #define A_PL_INDIR_DATA 0x1fc
4211 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
4215 mtx_assert(&sc->reg_lock, MA_OWNED);
4216 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4217 V_PL_VFID(G_FW_VIID_VIN(viid)) | V_PL_ADDR(VF_MPS_REG(reg)));
4218 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
4219 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
4220 return (((uint64_t)stats[1]) << 32 | stats[0]);
4224 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
4225 struct fw_vi_stats_vf *stats)
4228 #define GET_STAT(name) \
4229 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
4231 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
4232 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
4233 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
4234 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
4235 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
4236 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
4237 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
4238 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
4239 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
4240 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
4241 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
4242 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
4243 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
4244 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
4245 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
4246 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
4252 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
4256 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4257 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4258 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
4259 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
4260 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
4261 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
4265 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
4267 struct ifnet *ifp = vi->ifp;
4268 struct sge_txq *txq;
4270 struct fw_vi_stats_vf *s = &vi->stats;
4272 const struct timeval interval = {0, 250000}; /* 250ms */
4274 if (!(vi->flags & VI_INIT_DONE))
4278 timevalsub(&tv, &interval);
4279 if (timevalcmp(&tv, &vi->last_refreshed, <))
4282 mtx_lock(&sc->reg_lock);
4283 t4_get_vi_stats(sc, vi->viid, &vi->stats);
4285 ifp->if_ipackets = s->rx_bcast_frames + s->rx_mcast_frames +
4287 ifp->if_ierrors = s->rx_err_frames;
4288 ifp->if_opackets = s->tx_bcast_frames + s->tx_mcast_frames +
4289 s->tx_ucast_frames + s->tx_offload_frames;
4290 ifp->if_oerrors = s->tx_drop_frames;
4291 ifp->if_ibytes = s->rx_bcast_bytes + s->rx_mcast_bytes +
4293 ifp->if_obytes = s->tx_bcast_bytes + s->tx_mcast_bytes +
4294 s->tx_ucast_bytes + s->tx_offload_bytes;
4295 ifp->if_imcasts = s->rx_mcast_frames;
4296 ifp->if_omcasts = s->tx_mcast_frames;
4299 for_each_txq(vi, i, txq)
4300 drops += counter_u64_fetch(txq->r->drops);
4301 ifp->if_snd.ifq_drops = drops;
4303 getmicrotime(&vi->last_refreshed);
4304 mtx_unlock(&sc->reg_lock);
4308 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
4310 struct vi_info *vi = &pi->vi[0];
4311 struct ifnet *ifp = vi->ifp;
4312 struct sge_txq *txq;
4314 struct port_stats *s = &pi->stats;
4316 const struct timeval interval = {0, 250000}; /* 250ms */
4319 timevalsub(&tv, &interval);
4320 if (timevalcmp(&tv, &pi->last_refreshed, <))
4323 t4_get_port_stats(sc, pi->tx_chan, s);
4325 ifp->if_opackets = s->tx_frames - s->tx_pause;
4326 ifp->if_ipackets = s->rx_frames - s->rx_pause;
4327 ifp->if_obytes = s->tx_octets - s->tx_pause * 64;
4328 ifp->if_ibytes = s->rx_octets - s->rx_pause * 64;
4329 ifp->if_omcasts = s->tx_mcast_frames - s->tx_pause;
4330 ifp->if_imcasts = s->rx_mcast_frames - s->rx_pause;
4331 ifp->if_iqdrops = s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
4332 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
4334 for (i = 0; i < sc->chip_params->nchan; i++) {
4335 if (pi->rx_chan_map & (1 << i)) {
4338 mtx_lock(&sc->reg_lock);
4339 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
4340 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
4341 mtx_unlock(&sc->reg_lock);
4342 ifp->if_iqdrops += v;
4347 for_each_txq(vi, i, txq)
4348 drops += counter_u64_fetch(txq->r->drops);
4349 ifp->if_snd.ifq_drops = drops;
4351 ifp->if_oerrors = s->tx_error_frames;
4352 ifp->if_ierrors = s->rx_jabber + s->rx_runt + s->rx_too_long +
4353 s->rx_fcs_err + s->rx_len_err;
4355 getmicrotime(&pi->last_refreshed);
4359 cxgbe_tick(void *arg)
4361 struct port_info *pi = arg;
4362 struct adapter *sc = pi->adapter;
4364 PORT_LOCK_ASSERT_OWNED(pi);
4365 cxgbe_refresh_stats(sc, pi);
4367 callout_schedule(&pi->tick, hz);
4373 struct vi_info *vi = arg;
4374 struct adapter *sc = vi->pi->adapter;
4376 vi_refresh_stats(sc, vi);
4378 callout_schedule(&vi->tick, hz);
4382 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
4386 if (arg != ifp || ifp->if_type != IFT_ETHER)
4389 vlan = VLAN_DEVAT(ifp, vid);
4390 VLAN_SETCOOKIE(vlan, ifp);
4394 cpl_not_handled(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
4398 panic("%s: opcode 0x%02x on iq %p with payload %p",
4399 __func__, rss->opcode, iq, m);
4401 log(LOG_ERR, "%s: opcode 0x%02x on iq %p with payload %p\n",
4402 __func__, rss->opcode, iq, m);
4409 t4_register_cpl_handler(struct adapter *sc, int opcode, cpl_handler_t h)
4411 uintptr_t *loc, new;
4413 if (opcode >= nitems(sc->cpl_handler))
4416 new = h ? (uintptr_t)h : (uintptr_t)cpl_not_handled;
4417 loc = (uintptr_t *) &sc->cpl_handler[opcode];
4418 atomic_store_rel_ptr(loc, new);
4424 an_not_handled(struct sge_iq *iq, const struct rsp_ctrl *ctrl)
4428 panic("%s: async notification on iq %p (ctrl %p)", __func__, iq, ctrl);
4430 log(LOG_ERR, "%s: async notification on iq %p (ctrl %p)\n",
4431 __func__, iq, ctrl);
4437 t4_register_an_handler(struct adapter *sc, an_handler_t h)
4439 uintptr_t *loc, new;
4441 new = h ? (uintptr_t)h : (uintptr_t)an_not_handled;
4442 loc = (uintptr_t *) &sc->an_handler;
4443 atomic_store_rel_ptr(loc, new);
4449 fw_msg_not_handled(struct adapter *sc, const __be64 *rpl)
4451 const struct cpl_fw6_msg *cpl =
4452 __containerof(rpl, struct cpl_fw6_msg, data[0]);
4455 panic("%s: fw_msg type %d", __func__, cpl->type);
4457 log(LOG_ERR, "%s: fw_msg type %d\n", __func__, cpl->type);
4463 t4_register_fw_msg_handler(struct adapter *sc, int type, fw_msg_handler_t h)
4465 uintptr_t *loc, new;
4467 if (type >= nitems(sc->fw_msg_handler))
4471 * These are dispatched by the handler for FW{4|6}_CPL_MSG using the CPL
4472 * handler dispatch table. Reject any attempt to install a handler for
4475 if (type == FW_TYPE_RSSCPL || type == FW6_TYPE_RSSCPL)
4478 new = h ? (uintptr_t)h : (uintptr_t)fw_msg_not_handled;
4479 loc = (uintptr_t *) &sc->fw_msg_handler[type];
4480 atomic_store_rel_ptr(loc, new);
4486 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
4488 static char *caps_decoder[] = {
4489 "\20\001IPMI\002NCSI", /* 0: NBM */
4490 "\20\001PPP\002QFC\003DCBX", /* 1: link */
4491 "\20\001INGRESS\002EGRESS", /* 2: switch */
4492 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
4493 "\006HASHFILTER\007ETHOFLD",
4494 "\20\001TOE", /* 4: TOE */
4495 "\20\001RDDP\002RDMAC", /* 5: RDMA */
4496 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
4497 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
4498 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
4500 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
4501 "\20\00KEYS", /* 7: TLS */
4502 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
4503 "\004PO_INITIATOR\005PO_TARGET",
4507 t4_sysctls(struct adapter *sc)
4509 struct sysctl_ctx_list *ctx;
4510 struct sysctl_oid *oid;
4511 struct sysctl_oid_list *children, *c0;
4512 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
4514 ctx = device_get_sysctl_ctx(sc->dev);
4519 oid = device_get_sysctl_tree(sc->dev);
4520 c0 = children = SYSCTL_CHILDREN(oid);
4522 sc->sc_do_rxcopy = 1;
4523 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
4524 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
4526 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
4527 sc->params.nports, "# of ports");
4529 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
4530 NULL, chip_rev(sc), "chip hardware revision");
4532 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
4533 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
4535 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
4536 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
4538 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
4539 sc->cfcsum, "config file checksum");
4541 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
4542 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells,
4543 sysctl_bitfield, "A", "available doorbells");
4545 #define SYSCTL_CAP(name, n, text) \
4546 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
4547 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \
4548 sysctl_bitfield, "A", "available " text "capabilities")
4550 SYSCTL_CAP(nbmcaps, 0, "NBM");
4551 SYSCTL_CAP(linkcaps, 1, "link");
4552 SYSCTL_CAP(switchcaps, 2, "switch");
4553 SYSCTL_CAP(niccaps, 3, "NIC");
4554 SYSCTL_CAP(toecaps, 4, "TCP offload");
4555 SYSCTL_CAP(rdmacaps, 5, "RDMA");
4556 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
4557 SYSCTL_CAP(tlscaps, 7, "TLS");
4558 SYSCTL_CAP(fcoecaps, 8, "FCoE");
4561 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
4562 sc->params.vpd.cclk, "core clock frequency (in KHz)");
4564 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
4565 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
4566 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
4567 "interrupt holdoff timer values (us)");
4569 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
4570 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
4571 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
4572 "interrupt holdoff packet counter values");
4574 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
4575 NULL, sc->tids.nftids, "number of filters");
4577 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
4578 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
4579 "chip temperature (in Celsius)");
4581 t4_sge_sysctls(sc, ctx, children);
4583 sc->lro_timeout = 100;
4584 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
4585 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
4587 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "debug_flags", CTLFLAG_RW,
4588 &sc->debug_flags, 0, "flags to enable runtime debugging");
4592 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
4594 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
4595 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
4596 "logs and miscellaneous information");
4597 children = SYSCTL_CHILDREN(oid);
4599 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
4600 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4601 sysctl_cctrl, "A", "congestion control");
4603 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
4604 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4605 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
4607 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
4608 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
4609 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
4611 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
4612 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
4613 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
4615 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
4616 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
4617 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
4619 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
4620 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
4621 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
4623 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
4624 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
4625 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
4627 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
4628 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4629 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
4630 "A", "CIM logic analyzer");
4632 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
4633 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4634 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
4636 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
4637 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
4638 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
4640 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
4641 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
4642 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
4644 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
4645 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
4646 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
4648 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
4649 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
4650 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
4652 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
4653 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
4654 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
4656 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
4657 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
4658 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
4660 if (chip_id(sc) > CHELSIO_T4) {
4661 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
4662 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
4663 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
4665 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
4666 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
4667 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
4670 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
4671 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4672 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
4674 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
4675 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4676 sysctl_cim_qcfg, "A", "CIM queue configuration");
4678 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
4679 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4680 sysctl_cpl_stats, "A", "CPL statistics");
4682 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
4683 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4684 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
4686 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
4687 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4688 sysctl_devlog, "A", "firmware's device log");
4690 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
4691 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4692 sysctl_fcoe_stats, "A", "FCoE statistics");
4694 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
4695 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4696 sysctl_hw_sched, "A", "hardware scheduler ");
4698 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
4699 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4700 sysctl_l2t, "A", "hardware L2 table");
4702 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
4703 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4704 sysctl_lb_stats, "A", "loopback statistics");
4706 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
4707 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4708 sysctl_meminfo, "A", "memory regions");
4710 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
4711 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4712 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
4713 "A", "MPS TCAM entries");
4715 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
4716 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4717 sysctl_path_mtus, "A", "path MTUs");
4719 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
4720 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4721 sysctl_pm_stats, "A", "PM statistics");
4723 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
4724 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4725 sysctl_rdma_stats, "A", "RDMA statistics");
4727 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
4728 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4729 sysctl_tcp_stats, "A", "TCP statistics");
4731 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
4732 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4733 sysctl_tids, "A", "TID information");
4735 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
4736 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4737 sysctl_tp_err_stats, "A", "TP error statistics");
4739 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
4740 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4741 sysctl_tp_la, "A", "TP logic analyzer");
4743 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
4744 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4745 sysctl_tx_rate, "A", "Tx rate");
4747 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
4748 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4749 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
4752 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
4753 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4754 sysctl_wcwr_stats, "A", "write combined work requests");
4759 if (is_offload(sc)) {
4763 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
4764 NULL, "TOE parameters");
4765 children = SYSCTL_CHILDREN(oid);
4767 sc->tt.sndbuf = 256 * 1024;
4768 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
4769 &sc->tt.sndbuf, 0, "max hardware send buffer size");
4772 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
4773 &sc->tt.ddp, 0, "DDP allowed");
4775 sc->tt.indsz = G_INDICATESIZE(t4_read_reg(sc, A_TP_PARA_REG5));
4776 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "indsz", CTLFLAG_RW,
4777 &sc->tt.indsz, 0, "DDP max indicate size allowed");
4780 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2));
4781 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp_thres", CTLFLAG_RW,
4782 &sc->tt.ddp_thres, 0, "DDP threshold");
4784 sc->tt.rx_coalesce = 1;
4785 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
4786 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
4788 sc->tt.tx_align = 1;
4789 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
4790 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
4796 vi_sysctls(struct vi_info *vi)
4798 struct sysctl_ctx_list *ctx;
4799 struct sysctl_oid *oid;
4800 struct sysctl_oid_list *children;
4802 ctx = device_get_sysctl_ctx(vi->dev);
4805 * dev.v?(cxgbe|cxl).X.
4807 oid = device_get_sysctl_tree(vi->dev);
4808 children = SYSCTL_CHILDREN(oid);
4810 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
4811 vi->viid, "VI identifer");
4812 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
4813 &vi->nrxq, 0, "# of rx queues");
4814 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
4815 &vi->ntxq, 0, "# of tx queues");
4816 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
4817 &vi->first_rxq, 0, "index of first rx queue");
4818 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
4819 &vi->first_txq, 0, "index of first tx queue");
4821 if (IS_MAIN_VI(vi)) {
4822 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
4823 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
4824 "Reserve queue 0 for non-flowid packets");
4828 if (vi->nofldrxq != 0) {
4829 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
4831 "# of rx queues for offloaded TCP connections");
4832 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
4834 "# of tx queues for offloaded TCP connections");
4835 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
4836 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
4837 "index of first TOE rx queue");
4838 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
4839 CTLFLAG_RD, &vi->first_ofld_txq, 0,
4840 "index of first TOE tx queue");
4844 if (vi->nnmrxq != 0) {
4845 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
4846 &vi->nnmrxq, 0, "# of netmap rx queues");
4847 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
4848 &vi->nnmtxq, 0, "# of netmap tx queues");
4849 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
4850 CTLFLAG_RD, &vi->first_nm_rxq, 0,
4851 "index of first netmap rx queue");
4852 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
4853 CTLFLAG_RD, &vi->first_nm_txq, 0,
4854 "index of first netmap tx queue");
4858 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
4859 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
4860 "holdoff timer index");
4861 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
4862 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
4863 "holdoff packet counter index");
4865 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
4866 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
4868 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
4869 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
4874 cxgbe_sysctls(struct port_info *pi)
4876 struct sysctl_ctx_list *ctx;
4877 struct sysctl_oid *oid;
4878 struct sysctl_oid_list *children;
4879 struct adapter *sc = pi->adapter;
4881 ctx = device_get_sysctl_ctx(pi->dev);
4886 oid = device_get_sysctl_tree(pi->dev);
4887 children = SYSCTL_CHILDREN(oid);
4889 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
4890 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
4891 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
4892 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
4893 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
4894 "PHY temperature (in Celsius)");
4895 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
4896 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
4897 "PHY firmware version");
4900 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
4901 CTLTYPE_STRING | CTLFLAG_RW, pi, PAUSE_TX, sysctl_pause_settings,
4902 "A", "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)");
4905 * dev.cxgbe.X.stats.
4907 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4908 NULL, "port statistics");
4909 children = SYSCTL_CHILDREN(oid);
4910 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
4911 &pi->tx_parse_error, 0,
4912 "# of tx packets with invalid length or # of segments");
4914 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
4915 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
4916 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
4917 sysctl_handle_t4_reg64, "QU", desc)
4919 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
4920 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
4921 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
4922 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
4923 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
4924 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
4925 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
4926 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
4927 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
4928 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
4929 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
4930 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
4931 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
4932 "# of tx frames in this range",
4933 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
4934 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
4935 "# of tx frames in this range",
4936 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
4937 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
4938 "# of tx frames in this range",
4939 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
4940 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
4941 "# of tx frames in this range",
4942 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
4943 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
4944 "# of tx frames in this range",
4945 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
4946 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
4947 "# of tx frames in this range",
4948 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
4949 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
4950 "# of tx frames in this range",
4951 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
4952 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
4953 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
4954 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
4955 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
4956 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
4957 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
4958 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
4959 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
4960 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
4961 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
4962 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
4963 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
4964 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
4965 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
4966 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
4967 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
4968 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
4969 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
4970 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
4971 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
4973 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
4974 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
4975 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
4976 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
4977 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
4978 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
4979 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
4980 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
4981 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
4982 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
4983 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
4984 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
4985 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
4986 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
4987 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
4988 "# of frames received with bad FCS",
4989 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
4990 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
4991 "# of frames received with length error",
4992 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
4993 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
4994 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
4995 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
4996 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
4997 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
4998 "# of rx frames in this range",
4999 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
5000 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
5001 "# of rx frames in this range",
5002 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
5003 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
5004 "# of rx frames in this range",
5005 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
5006 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
5007 "# of rx frames in this range",
5008 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
5009 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
5010 "# of rx frames in this range",
5011 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
5012 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
5013 "# of rx frames in this range",
5014 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
5015 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
5016 "# of rx frames in this range",
5017 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
5018 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
5019 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
5020 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
5021 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
5022 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
5023 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
5024 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
5025 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
5026 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
5027 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
5028 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
5029 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
5030 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
5031 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
5032 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
5033 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
5034 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
5035 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
5037 #undef SYSCTL_ADD_T4_REG64
5039 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
5040 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
5041 &pi->stats.name, desc)
5043 /* We get these from port_stats and they may be stale by upto 1s */
5044 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
5045 "# drops due to buffer-group 0 overflows");
5046 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
5047 "# drops due to buffer-group 1 overflows");
5048 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
5049 "# drops due to buffer-group 2 overflows");
5050 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
5051 "# drops due to buffer-group 3 overflows");
5052 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
5053 "# of buffer-group 0 truncated packets");
5054 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
5055 "# of buffer-group 1 truncated packets");
5056 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
5057 "# of buffer-group 2 truncated packets");
5058 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
5059 "# of buffer-group 3 truncated packets");
5061 #undef SYSCTL_ADD_T4_PORTSTAT
5065 sysctl_int_array(SYSCTL_HANDLER_ARGS)
5067 int rc, *i, space = 0;
5070 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5071 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
5073 sbuf_printf(&sb, " ");
5074 sbuf_printf(&sb, "%d", *i);
5078 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5084 sysctl_bitfield(SYSCTL_HANDLER_ARGS)
5089 rc = sysctl_wire_old_buffer(req, 0);
5093 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5097 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
5098 rc = sbuf_finish(sb);
5105 sysctl_btphy(SYSCTL_HANDLER_ARGS)
5107 struct port_info *pi = arg1;
5109 struct adapter *sc = pi->adapter;
5113 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
5116 /* XXX: magic numbers */
5117 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
5119 end_synchronized_op(sc, 0);
5125 rc = sysctl_handle_int(oidp, &v, 0, req);
5130 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
5132 struct vi_info *vi = arg1;
5135 val = vi->rsrv_noflowq;
5136 rc = sysctl_handle_int(oidp, &val, 0, req);
5137 if (rc != 0 || req->newptr == NULL)
5140 if ((val >= 1) && (vi->ntxq > 1))
5141 vi->rsrv_noflowq = 1;
5143 vi->rsrv_noflowq = 0;
5149 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
5151 struct vi_info *vi = arg1;
5152 struct adapter *sc = vi->pi->adapter;
5154 struct sge_rxq *rxq;
5156 struct sge_ofld_rxq *ofld_rxq;
5162 rc = sysctl_handle_int(oidp, &idx, 0, req);
5163 if (rc != 0 || req->newptr == NULL)
5166 if (idx < 0 || idx >= SGE_NTIMERS)
5169 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5174 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
5175 for_each_rxq(vi, i, rxq) {
5176 #ifdef atomic_store_rel_8
5177 atomic_store_rel_8(&rxq->iq.intr_params, v);
5179 rxq->iq.intr_params = v;
5183 for_each_ofld_rxq(vi, i, ofld_rxq) {
5184 #ifdef atomic_store_rel_8
5185 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
5187 ofld_rxq->iq.intr_params = v;
5193 end_synchronized_op(sc, LOCK_HELD);
5198 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
5200 struct vi_info *vi = arg1;
5201 struct adapter *sc = vi->pi->adapter;
5206 rc = sysctl_handle_int(oidp, &idx, 0, req);
5207 if (rc != 0 || req->newptr == NULL)
5210 if (idx < -1 || idx >= SGE_NCOUNTERS)
5213 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5218 if (vi->flags & VI_INIT_DONE)
5219 rc = EBUSY; /* cannot be changed once the queues are created */
5223 end_synchronized_op(sc, LOCK_HELD);
5228 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
5230 struct vi_info *vi = arg1;
5231 struct adapter *sc = vi->pi->adapter;
5234 qsize = vi->qsize_rxq;
5236 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5237 if (rc != 0 || req->newptr == NULL)
5240 if (qsize < 128 || (qsize & 7))
5243 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5248 if (vi->flags & VI_INIT_DONE)
5249 rc = EBUSY; /* cannot be changed once the queues are created */
5251 vi->qsize_rxq = qsize;
5253 end_synchronized_op(sc, LOCK_HELD);
5258 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
5260 struct vi_info *vi = arg1;
5261 struct adapter *sc = vi->pi->adapter;
5264 qsize = vi->qsize_txq;
5266 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5267 if (rc != 0 || req->newptr == NULL)
5270 if (qsize < 128 || qsize > 65536)
5273 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5278 if (vi->flags & VI_INIT_DONE)
5279 rc = EBUSY; /* cannot be changed once the queues are created */
5281 vi->qsize_txq = qsize;
5283 end_synchronized_op(sc, LOCK_HELD);
5288 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
5290 struct port_info *pi = arg1;
5291 struct adapter *sc = pi->adapter;
5292 struct link_config *lc = &pi->link_cfg;
5295 if (req->newptr == NULL) {
5297 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX";
5299 rc = sysctl_wire_old_buffer(req, 0);
5303 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5307 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits);
5308 rc = sbuf_finish(sb);
5314 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX));
5317 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
5323 if (s[0] < '0' || s[0] > '9')
5324 return (EINVAL); /* not a number */
5326 if (n & ~(PAUSE_TX | PAUSE_RX))
5327 return (EINVAL); /* some other bit is set too */
5329 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
5333 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) {
5334 int link_ok = lc->link_ok;
5336 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX);
5337 lc->requested_fc |= n;
5338 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5339 lc->link_ok = link_ok; /* restore */
5341 end_synchronized_op(sc, 0);
5348 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
5350 struct adapter *sc = arg1;
5354 val = t4_read_reg64(sc, reg);
5356 return (sysctl_handle_64(oidp, &val, 0, req));
5360 sysctl_temperature(SYSCTL_HANDLER_ARGS)
5362 struct adapter *sc = arg1;
5364 uint32_t param, val;
5366 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
5369 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5370 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5371 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
5372 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5373 end_synchronized_op(sc, 0);
5377 /* unknown is returned as 0 but we display -1 in that case */
5378 t = val == 0 ? -1 : val;
5380 rc = sysctl_handle_int(oidp, &t, 0, req);
5386 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
5388 struct adapter *sc = arg1;
5391 uint16_t incr[NMTUS][NCCTRL_WIN];
5392 static const char *dec_fac[] = {
5393 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
5397 rc = sysctl_wire_old_buffer(req, 0);
5401 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5405 t4_read_cong_tbl(sc, incr);
5407 for (i = 0; i < NCCTRL_WIN; ++i) {
5408 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
5409 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
5410 incr[5][i], incr[6][i], incr[7][i]);
5411 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
5412 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
5413 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
5414 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
5417 rc = sbuf_finish(sb);
5423 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
5424 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
5425 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
5426 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
5430 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
5432 struct adapter *sc = arg1;
5434 int rc, i, n, qid = arg2;
5437 u_int cim_num_obq = sc->chip_params->cim_num_obq;
5439 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
5440 ("%s: bad qid %d\n", __func__, qid));
5442 if (qid < CIM_NUM_IBQ) {
5445 n = 4 * CIM_IBQ_SIZE;
5446 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5447 rc = t4_read_cim_ibq(sc, qid, buf, n);
5449 /* outbound queue */
5452 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
5453 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5454 rc = t4_read_cim_obq(sc, qid, buf, n);
5461 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
5463 rc = sysctl_wire_old_buffer(req, 0);
5467 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5473 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
5474 for (i = 0, p = buf; i < n; i += 16, p += 4)
5475 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
5478 rc = sbuf_finish(sb);
5486 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
5488 struct adapter *sc = arg1;
5494 MPASS(chip_id(sc) <= CHELSIO_T5);
5496 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5500 rc = sysctl_wire_old_buffer(req, 0);
5504 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5508 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5511 rc = -t4_cim_read_la(sc, buf, NULL);
5515 sbuf_printf(sb, "Status Data PC%s",
5516 cfg & F_UPDBGLACAPTPCONLY ? "" :
5517 " LS0Stat LS0Addr LS0Data");
5519 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
5520 if (cfg & F_UPDBGLACAPTPCONLY) {
5521 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
5523 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
5524 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
5525 p[4] & 0xff, p[5] >> 8);
5526 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
5527 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5528 p[1] & 0xf, p[2] >> 4);
5531 "\n %02x %x%07x %x%07x %08x %08x "
5533 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5534 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
5539 rc = sbuf_finish(sb);
5547 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
5549 struct adapter *sc = arg1;
5555 MPASS(chip_id(sc) > CHELSIO_T5);
5557 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5561 rc = sysctl_wire_old_buffer(req, 0);
5565 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5569 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5572 rc = -t4_cim_read_la(sc, buf, NULL);
5576 sbuf_printf(sb, "Status Inst Data PC%s",
5577 cfg & F_UPDBGLACAPTPCONLY ? "" :
5578 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
5580 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
5581 if (cfg & F_UPDBGLACAPTPCONLY) {
5582 sbuf_printf(sb, "\n %02x %08x %08x %08x",
5583 p[3] & 0xff, p[2], p[1], p[0]);
5584 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
5585 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
5586 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
5587 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
5588 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
5589 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
5592 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
5593 "%08x %08x %08x %08x %08x %08x",
5594 (p[9] >> 16) & 0xff,
5595 p[9] & 0xffff, p[8] >> 16,
5596 p[8] & 0xffff, p[7] >> 16,
5597 p[7] & 0xffff, p[6] >> 16,
5598 p[2], p[1], p[0], p[5], p[4], p[3]);
5602 rc = sbuf_finish(sb);
5610 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
5612 struct adapter *sc = arg1;
5618 rc = sysctl_wire_old_buffer(req, 0);
5622 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5626 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
5629 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
5632 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5633 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
5637 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
5638 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5639 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
5640 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
5641 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
5642 (p[1] >> 2) | ((p[2] & 3) << 30),
5643 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
5647 rc = sbuf_finish(sb);
5654 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
5656 struct adapter *sc = arg1;
5662 rc = sysctl_wire_old_buffer(req, 0);
5666 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5670 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
5673 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
5676 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
5677 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
5678 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
5679 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
5680 p[4], p[3], p[2], p[1], p[0]);
5683 sbuf_printf(sb, "\n\nCntl ID Data");
5684 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
5685 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
5686 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
5689 rc = sbuf_finish(sb);
5696 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
5698 struct adapter *sc = arg1;
5701 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5702 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5703 uint16_t thres[CIM_NUM_IBQ];
5704 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
5705 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
5706 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
5708 cim_num_obq = sc->chip_params->cim_num_obq;
5710 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
5711 obq_rdaddr = A_UP_OBQ_0_REALADDR;
5713 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
5714 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
5716 nq = CIM_NUM_IBQ + cim_num_obq;
5718 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
5720 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
5724 t4_read_cimq_cfg(sc, base, size, thres);
5726 rc = sysctl_wire_old_buffer(req, 0);
5730 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5734 sbuf_printf(sb, "Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
5736 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
5737 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
5738 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
5739 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5740 G_QUEREMFLITS(p[2]) * 16);
5741 for ( ; i < nq; i++, p += 4, wr += 2)
5742 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
5743 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
5744 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5745 G_QUEREMFLITS(p[2]) * 16);
5747 rc = sbuf_finish(sb);
5754 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
5756 struct adapter *sc = arg1;
5759 struct tp_cpl_stats stats;
5761 rc = sysctl_wire_old_buffer(req, 0);
5765 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5769 mtx_lock(&sc->reg_lock);
5770 t4_tp_get_cpl_stats(sc, &stats);
5771 mtx_unlock(&sc->reg_lock);
5773 if (sc->chip_params->nchan > 2) {
5774 sbuf_printf(sb, " channel 0 channel 1"
5775 " channel 2 channel 3");
5776 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
5777 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
5778 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
5779 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
5781 sbuf_printf(sb, " channel 0 channel 1");
5782 sbuf_printf(sb, "\nCPL requests: %10u %10u",
5783 stats.req[0], stats.req[1]);
5784 sbuf_printf(sb, "\nCPL responses: %10u %10u",
5785 stats.rsp[0], stats.rsp[1]);
5788 rc = sbuf_finish(sb);
5795 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
5797 struct adapter *sc = arg1;
5800 struct tp_usm_stats stats;
5802 rc = sysctl_wire_old_buffer(req, 0);
5806 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5810 t4_get_usm_stats(sc, &stats);
5812 sbuf_printf(sb, "Frames: %u\n", stats.frames);
5813 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
5814 sbuf_printf(sb, "Drops: %u", stats.drops);
5816 rc = sbuf_finish(sb);
5822 static const char * const devlog_level_strings[] = {
5823 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
5824 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
5825 [FW_DEVLOG_LEVEL_ERR] = "ERR",
5826 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
5827 [FW_DEVLOG_LEVEL_INFO] = "INFO",
5828 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
5831 static const char * const devlog_facility_strings[] = {
5832 [FW_DEVLOG_FACILITY_CORE] = "CORE",
5833 [FW_DEVLOG_FACILITY_CF] = "CF",
5834 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
5835 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
5836 [FW_DEVLOG_FACILITY_RES] = "RES",
5837 [FW_DEVLOG_FACILITY_HW] = "HW",
5838 [FW_DEVLOG_FACILITY_FLR] = "FLR",
5839 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
5840 [FW_DEVLOG_FACILITY_PHY] = "PHY",
5841 [FW_DEVLOG_FACILITY_MAC] = "MAC",
5842 [FW_DEVLOG_FACILITY_PORT] = "PORT",
5843 [FW_DEVLOG_FACILITY_VI] = "VI",
5844 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
5845 [FW_DEVLOG_FACILITY_ACL] = "ACL",
5846 [FW_DEVLOG_FACILITY_TM] = "TM",
5847 [FW_DEVLOG_FACILITY_QFC] = "QFC",
5848 [FW_DEVLOG_FACILITY_DCB] = "DCB",
5849 [FW_DEVLOG_FACILITY_ETH] = "ETH",
5850 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
5851 [FW_DEVLOG_FACILITY_RI] = "RI",
5852 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
5853 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
5854 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
5855 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
5856 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
5860 sysctl_devlog(SYSCTL_HANDLER_ARGS)
5862 struct adapter *sc = arg1;
5863 struct devlog_params *dparams = &sc->params.devlog;
5864 struct fw_devlog_e *buf, *e;
5865 int i, j, rc, nentries, first = 0;
5867 uint64_t ftstamp = UINT64_MAX;
5869 if (dparams->addr == 0)
5872 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
5876 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
5880 nentries = dparams->size / sizeof(struct fw_devlog_e);
5881 for (i = 0; i < nentries; i++) {
5884 if (e->timestamp == 0)
5887 e->timestamp = be64toh(e->timestamp);
5888 e->seqno = be32toh(e->seqno);
5889 for (j = 0; j < 8; j++)
5890 e->params[j] = be32toh(e->params[j]);
5892 if (e->timestamp < ftstamp) {
5893 ftstamp = e->timestamp;
5898 if (buf[first].timestamp == 0)
5899 goto done; /* nothing in the log */
5901 rc = sysctl_wire_old_buffer(req, 0);
5905 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5910 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
5911 "Seq#", "Tstamp", "Level", "Facility", "Message");
5916 if (e->timestamp == 0)
5919 sbuf_printf(sb, "%10d %15ju %8s %8s ",
5920 e->seqno, e->timestamp,
5921 (e->level < nitems(devlog_level_strings) ?
5922 devlog_level_strings[e->level] : "UNKNOWN"),
5923 (e->facility < nitems(devlog_facility_strings) ?
5924 devlog_facility_strings[e->facility] : "UNKNOWN"));
5925 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
5926 e->params[2], e->params[3], e->params[4],
5927 e->params[5], e->params[6], e->params[7]);
5929 if (++i == nentries)
5931 } while (i != first);
5933 rc = sbuf_finish(sb);
5941 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
5943 struct adapter *sc = arg1;
5946 struct tp_fcoe_stats stats[MAX_NCHAN];
5947 int i, nchan = sc->chip_params->nchan;
5949 rc = sysctl_wire_old_buffer(req, 0);
5953 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5957 for (i = 0; i < nchan; i++)
5958 t4_get_fcoe_stats(sc, i, &stats[i]);
5961 sbuf_printf(sb, " channel 0 channel 1"
5962 " channel 2 channel 3");
5963 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
5964 stats[0].octets_ddp, stats[1].octets_ddp,
5965 stats[2].octets_ddp, stats[3].octets_ddp);
5966 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
5967 stats[0].frames_ddp, stats[1].frames_ddp,
5968 stats[2].frames_ddp, stats[3].frames_ddp);
5969 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
5970 stats[0].frames_drop, stats[1].frames_drop,
5971 stats[2].frames_drop, stats[3].frames_drop);
5973 sbuf_printf(sb, " channel 0 channel 1");
5974 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
5975 stats[0].octets_ddp, stats[1].octets_ddp);
5976 sbuf_printf(sb, "\nframesDDP: %16u %16u",
5977 stats[0].frames_ddp, stats[1].frames_ddp);
5978 sbuf_printf(sb, "\nframesDrop: %16u %16u",
5979 stats[0].frames_drop, stats[1].frames_drop);
5982 rc = sbuf_finish(sb);
5989 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
5991 struct adapter *sc = arg1;
5994 unsigned int map, kbps, ipg, mode;
5995 unsigned int pace_tab[NTX_SCHED];
5997 rc = sysctl_wire_old_buffer(req, 0);
6001 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6005 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
6006 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
6007 t4_read_pace_tbl(sc, pace_tab);
6009 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
6010 "Class IPG (0.1 ns) Flow IPG (us)");
6012 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
6013 t4_get_tx_sched(sc, i, &kbps, &ipg);
6014 sbuf_printf(sb, "\n %u %-5s %u ", i,
6015 (mode & (1 << i)) ? "flow" : "class", map & 3);
6017 sbuf_printf(sb, "%9u ", kbps);
6019 sbuf_printf(sb, " disabled ");
6022 sbuf_printf(sb, "%13u ", ipg);
6024 sbuf_printf(sb, " disabled ");
6027 sbuf_printf(sb, "%10u", pace_tab[i]);
6029 sbuf_printf(sb, " disabled");
6032 rc = sbuf_finish(sb);
6039 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
6041 struct adapter *sc = arg1;
6045 struct lb_port_stats s[2];
6046 static const char *stat_name[] = {
6047 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
6048 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
6049 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
6050 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
6051 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
6052 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
6053 "BG2FramesTrunc:", "BG3FramesTrunc:"
6056 rc = sysctl_wire_old_buffer(req, 0);
6060 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6064 memset(s, 0, sizeof(s));
6066 for (i = 0; i < sc->chip_params->nchan; i += 2) {
6067 t4_get_lb_stats(sc, i, &s[0]);
6068 t4_get_lb_stats(sc, i + 1, &s[1]);
6072 sbuf_printf(sb, "%s Loopback %u"
6073 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
6075 for (j = 0; j < nitems(stat_name); j++)
6076 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
6080 rc = sbuf_finish(sb);
6087 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
6090 struct port_info *pi = arg1;
6093 rc = sysctl_wire_old_buffer(req, 0);
6096 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
6100 if (pi->linkdnrc < 0)
6101 sbuf_printf(sb, "n/a");
6103 sbuf_printf(sb, "%s", t4_link_down_rc_str(pi->linkdnrc));
6105 rc = sbuf_finish(sb);
6118 mem_desc_cmp(const void *a, const void *b)
6120 return ((const struct mem_desc *)a)->base -
6121 ((const struct mem_desc *)b)->base;
6125 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
6130 size = to - from + 1;
6134 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
6135 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
6139 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
6141 struct adapter *sc = arg1;
6144 uint32_t lo, hi, used, alloc;
6145 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
6146 static const char *region[] = {
6147 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
6148 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
6149 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
6150 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
6151 "RQUDP region:", "PBL region:", "TXPBL region:",
6152 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
6155 struct mem_desc avail[4];
6156 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
6157 struct mem_desc *md = mem;
6159 rc = sysctl_wire_old_buffer(req, 0);
6163 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6167 for (i = 0; i < nitems(mem); i++) {
6172 /* Find and sort the populated memory ranges */
6174 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
6175 if (lo & F_EDRAM0_ENABLE) {
6176 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
6177 avail[i].base = G_EDRAM0_BASE(hi) << 20;
6178 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
6182 if (lo & F_EDRAM1_ENABLE) {
6183 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
6184 avail[i].base = G_EDRAM1_BASE(hi) << 20;
6185 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
6189 if (lo & F_EXT_MEM_ENABLE) {
6190 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
6191 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
6192 avail[i].limit = avail[i].base +
6193 (G_EXT_MEM_SIZE(hi) << 20);
6194 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
6197 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
6198 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
6199 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
6200 avail[i].limit = avail[i].base +
6201 (G_EXT_MEM1_SIZE(hi) << 20);
6205 if (!i) /* no memory available */
6207 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
6209 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
6210 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
6211 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
6212 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
6213 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
6214 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
6215 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
6216 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
6217 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
6219 /* the next few have explicit upper bounds */
6220 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
6221 md->limit = md->base - 1 +
6222 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
6223 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
6226 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
6227 md->limit = md->base - 1 +
6228 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
6229 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
6232 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6233 if (chip_id(sc) <= CHELSIO_T5) {
6234 hi = t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4;
6235 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
6237 hi = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
6238 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
6243 md->idx = nitems(region); /* hide it */
6247 #define ulp_region(reg) \
6248 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
6249 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
6251 ulp_region(RX_ISCSI);
6252 ulp_region(RX_TDDP);
6254 ulp_region(RX_STAG);
6256 ulp_region(RX_RQUDP);
6262 md->idx = nitems(region);
6265 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
6266 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
6269 if (sge_ctrl & F_VFIFO_ENABLE)
6270 size = G_DBVFIFO_SIZE(fifo_size);
6272 size = G_T6_DBVFIFO_SIZE(fifo_size);
6275 md->base = G_BASEADDR(t4_read_reg(sc,
6276 A_SGE_DBVFIFO_BADDR));
6277 md->limit = md->base + (size << 2) - 1;
6282 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
6285 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
6289 md->base = sc->vres.ocq.start;
6290 if (sc->vres.ocq.size)
6291 md->limit = md->base + sc->vres.ocq.size - 1;
6293 md->idx = nitems(region); /* hide it */
6296 /* add any address-space holes, there can be up to 3 */
6297 for (n = 0; n < i - 1; n++)
6298 if (avail[n].limit < avail[n + 1].base)
6299 (md++)->base = avail[n].limit;
6301 (md++)->base = avail[n].limit;
6304 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
6306 for (lo = 0; lo < i; lo++)
6307 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
6308 avail[lo].limit - 1);
6310 sbuf_printf(sb, "\n");
6311 for (i = 0; i < n; i++) {
6312 if (mem[i].idx >= nitems(region))
6313 continue; /* skip holes */
6315 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
6316 mem_region_show(sb, region[mem[i].idx], mem[i].base,
6320 sbuf_printf(sb, "\n");
6321 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
6322 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
6323 mem_region_show(sb, "uP RAM:", lo, hi);
6325 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
6326 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
6327 mem_region_show(sb, "uP Extmem2:", lo, hi);
6329 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
6330 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
6332 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
6333 (lo & F_PMRXNUMCHN) ? 2 : 1);
6335 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
6336 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
6337 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
6339 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
6340 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
6341 sbuf_printf(sb, "%u p-structs\n",
6342 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
6344 for (i = 0; i < 4; i++) {
6345 if (chip_id(sc) > CHELSIO_T5)
6346 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
6348 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
6350 used = G_T5_USED(lo);
6351 alloc = G_T5_ALLOC(lo);
6354 alloc = G_ALLOC(lo);
6356 /* For T6 these are MAC buffer groups */
6357 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
6360 for (i = 0; i < sc->chip_params->nchan; i++) {
6361 if (chip_id(sc) > CHELSIO_T5)
6362 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
6364 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
6366 used = G_T5_USED(lo);
6367 alloc = G_T5_ALLOC(lo);
6370 alloc = G_ALLOC(lo);
6372 /* For T6 these are MAC buffer groups */
6374 "\nLoopback %d using %u pages out of %u allocated",
6378 rc = sbuf_finish(sb);
6385 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
6389 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
6393 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
6395 struct adapter *sc = arg1;
6399 MPASS(chip_id(sc) <= CHELSIO_T5);
6401 rc = sysctl_wire_old_buffer(req, 0);
6405 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6410 "Idx Ethernet address Mask Vld Ports PF"
6411 " VF Replication P0 P1 P2 P3 ML");
6412 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6413 uint64_t tcamx, tcamy, mask;
6414 uint32_t cls_lo, cls_hi;
6415 uint8_t addr[ETHER_ADDR_LEN];
6417 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
6418 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
6421 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6422 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6423 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6424 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
6425 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
6426 addr[3], addr[4], addr[5], (uintmax_t)mask,
6427 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
6428 G_PORTMAP(cls_hi), G_PF(cls_lo),
6429 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
6431 if (cls_lo & F_REPLICATE) {
6432 struct fw_ldst_cmd ldst_cmd;
6434 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6435 ldst_cmd.op_to_addrspace =
6436 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6437 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6438 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6439 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6440 ldst_cmd.u.mps.rplc.fid_idx =
6441 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6442 V_FW_LDST_CMD_IDX(i));
6444 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6448 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6449 sizeof(ldst_cmd), &ldst_cmd);
6450 end_synchronized_op(sc, 0);
6453 sbuf_printf(sb, "%36d", rc);
6456 sbuf_printf(sb, " %08x %08x %08x %08x",
6457 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6458 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6459 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6460 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6463 sbuf_printf(sb, "%36s", "");
6465 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
6466 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
6467 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
6471 (void) sbuf_finish(sb);
6473 rc = sbuf_finish(sb);
6480 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
6482 struct adapter *sc = arg1;
6486 MPASS(chip_id(sc) > CHELSIO_T5);
6488 rc = sysctl_wire_old_buffer(req, 0);
6492 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6496 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
6497 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
6499 " P0 P1 P2 P3 ML\n");
6501 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6502 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
6504 uint64_t tcamx, tcamy, val, mask;
6505 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
6506 uint8_t addr[ETHER_ADDR_LEN];
6508 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
6510 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
6512 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
6513 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6514 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6515 tcamy = G_DMACH(val) << 32;
6516 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6517 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6518 lookup_type = G_DATALKPTYPE(data2);
6519 port_num = G_DATAPORTNUM(data2);
6520 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6521 /* Inner header VNI */
6522 vniy = ((data2 & F_DATAVIDH2) << 23) |
6523 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6524 dip_hit = data2 & F_DATADIPHIT;
6529 vlan_vld = data2 & F_DATAVIDH2;
6530 ivlan = G_VIDL(val);
6533 ctl |= V_CTLXYBITSEL(1);
6534 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6535 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6536 tcamx = G_DMACH(val) << 32;
6537 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6538 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6539 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6540 /* Inner header VNI mask */
6541 vnix = ((data2 & F_DATAVIDH2) << 23) |
6542 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6548 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6550 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6551 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6553 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6554 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6555 "%012jx %06x %06x - - %3c"
6556 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
6557 addr[1], addr[2], addr[3], addr[4], addr[5],
6558 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
6559 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6560 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6561 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6563 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6564 "%012jx - - ", i, addr[0], addr[1],
6565 addr[2], addr[3], addr[4], addr[5],
6569 sbuf_printf(sb, "%4u Y ", ivlan);
6571 sbuf_printf(sb, " - N ");
6573 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
6574 lookup_type ? 'I' : 'O', port_num,
6575 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6576 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6577 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6581 if (cls_lo & F_T6_REPLICATE) {
6582 struct fw_ldst_cmd ldst_cmd;
6584 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6585 ldst_cmd.op_to_addrspace =
6586 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6587 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6588 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6589 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6590 ldst_cmd.u.mps.rplc.fid_idx =
6591 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6592 V_FW_LDST_CMD_IDX(i));
6594 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6598 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6599 sizeof(ldst_cmd), &ldst_cmd);
6600 end_synchronized_op(sc, 0);
6603 sbuf_printf(sb, "%72d", rc);
6606 sbuf_printf(sb, " %08x %08x %08x %08x"
6607 " %08x %08x %08x %08x",
6608 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
6609 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
6610 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
6611 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
6612 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6613 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6614 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6615 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6618 sbuf_printf(sb, "%72s", "");
6620 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
6621 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
6622 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
6623 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
6627 (void) sbuf_finish(sb);
6629 rc = sbuf_finish(sb);
6636 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
6638 struct adapter *sc = arg1;
6641 uint16_t mtus[NMTUS];
6643 rc = sysctl_wire_old_buffer(req, 0);
6647 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6651 t4_read_mtu_tbl(sc, mtus, NULL);
6653 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
6654 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
6655 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
6656 mtus[14], mtus[15]);
6658 rc = sbuf_finish(sb);
6665 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
6667 struct adapter *sc = arg1;
6670 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
6671 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
6672 static const char *tx_stats[MAX_PM_NSTATS] = {
6673 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
6674 "Tx FIFO wait", NULL, "Tx latency"
6676 static const char *rx_stats[MAX_PM_NSTATS] = {
6677 "Read:", "Write bypass:", "Write mem:", "Flush:",
6678 " Rx FIFO wait", NULL, "Rx latency"
6681 rc = sysctl_wire_old_buffer(req, 0);
6685 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6689 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
6690 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
6692 sbuf_printf(sb, " Tx pcmds Tx bytes");
6693 for (i = 0; i < 4; i++) {
6694 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6698 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
6699 for (i = 0; i < 4; i++) {
6700 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6704 if (chip_id(sc) > CHELSIO_T5) {
6706 "\n Total wait Total occupancy");
6707 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6709 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6713 MPASS(i < nitems(tx_stats));
6716 "\n Reads Total wait");
6717 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6719 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6723 rc = sbuf_finish(sb);
6730 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
6732 struct adapter *sc = arg1;
6735 struct tp_rdma_stats stats;
6737 rc = sysctl_wire_old_buffer(req, 0);
6741 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6745 mtx_lock(&sc->reg_lock);
6746 t4_tp_get_rdma_stats(sc, &stats);
6747 mtx_unlock(&sc->reg_lock);
6749 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
6750 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
6752 rc = sbuf_finish(sb);
6759 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
6761 struct adapter *sc = arg1;
6764 struct tp_tcp_stats v4, v6;
6766 rc = sysctl_wire_old_buffer(req, 0);
6770 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6774 mtx_lock(&sc->reg_lock);
6775 t4_tp_get_tcp_stats(sc, &v4, &v6);
6776 mtx_unlock(&sc->reg_lock);
6780 sbuf_printf(sb, "OutRsts: %20u %20u\n",
6781 v4.tcp_out_rsts, v6.tcp_out_rsts);
6782 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
6783 v4.tcp_in_segs, v6.tcp_in_segs);
6784 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
6785 v4.tcp_out_segs, v6.tcp_out_segs);
6786 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
6787 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
6789 rc = sbuf_finish(sb);
6796 sysctl_tids(SYSCTL_HANDLER_ARGS)
6798 struct adapter *sc = arg1;
6801 struct tid_info *t = &sc->tids;
6803 rc = sysctl_wire_old_buffer(req, 0);
6807 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6812 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
6817 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6818 uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
6821 sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1,
6822 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6825 sbuf_printf(sb, "TID range: %u-%u",
6826 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6830 sbuf_printf(sb, "TID range: 0-%u", t->ntids - 1);
6831 sbuf_printf(sb, ", in use: %u\n",
6832 atomic_load_acq_int(&t->tids_in_use));
6836 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
6837 t->stid_base + t->nstids - 1, t->stids_in_use);
6841 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
6842 t->ftid_base + t->nftids - 1);
6846 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base,
6847 t->etid_base + t->netids - 1);
6850 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
6851 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
6852 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
6854 rc = sbuf_finish(sb);
6861 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
6863 struct adapter *sc = arg1;
6866 struct tp_err_stats stats;
6868 rc = sysctl_wire_old_buffer(req, 0);
6872 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6876 mtx_lock(&sc->reg_lock);
6877 t4_tp_get_err_stats(sc, &stats);
6878 mtx_unlock(&sc->reg_lock);
6880 if (sc->chip_params->nchan > 2) {
6881 sbuf_printf(sb, " channel 0 channel 1"
6882 " channel 2 channel 3\n");
6883 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
6884 stats.mac_in_errs[0], stats.mac_in_errs[1],
6885 stats.mac_in_errs[2], stats.mac_in_errs[3]);
6886 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
6887 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
6888 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
6889 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
6890 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
6891 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
6892 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
6893 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
6894 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
6895 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
6896 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
6897 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
6898 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
6899 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
6900 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
6901 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
6902 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
6903 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
6904 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
6905 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
6906 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
6908 sbuf_printf(sb, " channel 0 channel 1\n");
6909 sbuf_printf(sb, "macInErrs: %10u %10u\n",
6910 stats.mac_in_errs[0], stats.mac_in_errs[1]);
6911 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
6912 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
6913 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
6914 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
6915 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
6916 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
6917 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
6918 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
6919 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
6920 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
6921 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
6922 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
6923 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
6924 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
6927 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
6928 stats.ofld_no_neigh, stats.ofld_cong_defer);
6930 rc = sbuf_finish(sb);
6943 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
6949 uint64_t mask = (1ULL << f->width) - 1;
6950 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
6951 ((uintmax_t)v >> f->start) & mask);
6953 if (line_size + len >= 79) {
6955 sbuf_printf(sb, "\n ");
6957 sbuf_printf(sb, "%s ", buf);
6958 line_size += len + 1;
6961 sbuf_printf(sb, "\n");
6964 static const struct field_desc tp_la0[] = {
6965 { "RcfOpCodeOut", 60, 4 },
6967 { "WcfState", 52, 4 },
6968 { "RcfOpcSrcOut", 50, 2 },
6969 { "CRxError", 49, 1 },
6970 { "ERxError", 48, 1 },
6971 { "SanityFailed", 47, 1 },
6972 { "SpuriousMsg", 46, 1 },
6973 { "FlushInputMsg", 45, 1 },
6974 { "FlushInputCpl", 44, 1 },
6975 { "RssUpBit", 43, 1 },
6976 { "RssFilterHit", 42, 1 },
6978 { "InitTcb", 31, 1 },
6979 { "LineNumber", 24, 7 },
6981 { "EdataOut", 22, 1 },
6983 { "CdataOut", 20, 1 },
6984 { "EreadPdu", 19, 1 },
6985 { "CreadPdu", 18, 1 },
6986 { "TunnelPkt", 17, 1 },
6987 { "RcfPeerFin", 16, 1 },
6988 { "RcfReasonOut", 12, 4 },
6989 { "TxCchannel", 10, 2 },
6990 { "RcfTxChannel", 8, 2 },
6991 { "RxEchannel", 6, 2 },
6992 { "RcfRxChannel", 5, 1 },
6993 { "RcfDataOutSrdy", 4, 1 },
6995 { "RxOoDvld", 2, 1 },
6996 { "RxCongestion", 1, 1 },
6997 { "TxCongestion", 0, 1 },
7001 static const struct field_desc tp_la1[] = {
7002 { "CplCmdIn", 56, 8 },
7003 { "CplCmdOut", 48, 8 },
7004 { "ESynOut", 47, 1 },
7005 { "EAckOut", 46, 1 },
7006 { "EFinOut", 45, 1 },
7007 { "ERstOut", 44, 1 },
7012 { "DataIn", 39, 1 },
7013 { "DataInVld", 38, 1 },
7015 { "RxBufEmpty", 36, 1 },
7017 { "RxFbCongestion", 34, 1 },
7018 { "TxFbCongestion", 33, 1 },
7019 { "TxPktSumSrdy", 32, 1 },
7020 { "RcfUlpType", 28, 4 },
7022 { "Ebypass", 26, 1 },
7024 { "Static0", 24, 1 },
7026 { "Cbypass", 22, 1 },
7028 { "CPktOut", 20, 1 },
7029 { "RxPagePoolFull", 18, 2 },
7030 { "RxLpbkPkt", 17, 1 },
7031 { "TxLpbkPkt", 16, 1 },
7032 { "RxVfValid", 15, 1 },
7033 { "SynLearned", 14, 1 },
7034 { "SetDelEntry", 13, 1 },
7035 { "SetInvEntry", 12, 1 },
7036 { "CpcmdDvld", 11, 1 },
7037 { "CpcmdSave", 10, 1 },
7038 { "RxPstructsFull", 8, 2 },
7039 { "EpcmdDvld", 7, 1 },
7040 { "EpcmdFlush", 6, 1 },
7041 { "EpcmdTrimPrefix", 5, 1 },
7042 { "EpcmdTrimPostfix", 4, 1 },
7043 { "ERssIp4Pkt", 3, 1 },
7044 { "ERssIp6Pkt", 2, 1 },
7045 { "ERssTcpUdpPkt", 1, 1 },
7046 { "ERssFceFipPkt", 0, 1 },
7050 static const struct field_desc tp_la2[] = {
7051 { "CplCmdIn", 56, 8 },
7052 { "MpsVfVld", 55, 1 },
7059 { "DataIn", 39, 1 },
7060 { "DataInVld", 38, 1 },
7062 { "RxBufEmpty", 36, 1 },
7064 { "RxFbCongestion", 34, 1 },
7065 { "TxFbCongestion", 33, 1 },
7066 { "TxPktSumSrdy", 32, 1 },
7067 { "RcfUlpType", 28, 4 },
7069 { "Ebypass", 26, 1 },
7071 { "Static0", 24, 1 },
7073 { "Cbypass", 22, 1 },
7075 { "CPktOut", 20, 1 },
7076 { "RxPagePoolFull", 18, 2 },
7077 { "RxLpbkPkt", 17, 1 },
7078 { "TxLpbkPkt", 16, 1 },
7079 { "RxVfValid", 15, 1 },
7080 { "SynLearned", 14, 1 },
7081 { "SetDelEntry", 13, 1 },
7082 { "SetInvEntry", 12, 1 },
7083 { "CpcmdDvld", 11, 1 },
7084 { "CpcmdSave", 10, 1 },
7085 { "RxPstructsFull", 8, 2 },
7086 { "EpcmdDvld", 7, 1 },
7087 { "EpcmdFlush", 6, 1 },
7088 { "EpcmdTrimPrefix", 5, 1 },
7089 { "EpcmdTrimPostfix", 4, 1 },
7090 { "ERssIp4Pkt", 3, 1 },
7091 { "ERssIp6Pkt", 2, 1 },
7092 { "ERssTcpUdpPkt", 1, 1 },
7093 { "ERssFceFipPkt", 0, 1 },
7098 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
7101 field_desc_show(sb, *p, tp_la0);
7105 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
7109 sbuf_printf(sb, "\n");
7110 field_desc_show(sb, p[0], tp_la0);
7111 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7112 field_desc_show(sb, p[1], tp_la0);
7116 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
7120 sbuf_printf(sb, "\n");
7121 field_desc_show(sb, p[0], tp_la0);
7122 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7123 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
7127 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
7129 struct adapter *sc = arg1;
7134 void (*show_func)(struct sbuf *, uint64_t *, int);
7136 rc = sysctl_wire_old_buffer(req, 0);
7140 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7144 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
7146 t4_tp_read_la(sc, buf, NULL);
7149 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
7152 show_func = tp_la_show2;
7156 show_func = tp_la_show3;
7160 show_func = tp_la_show;
7163 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
7164 (*show_func)(sb, p, i);
7166 rc = sbuf_finish(sb);
7173 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
7175 struct adapter *sc = arg1;
7178 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
7180 rc = sysctl_wire_old_buffer(req, 0);
7184 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7188 t4_get_chan_txrate(sc, nrate, orate);
7190 if (sc->chip_params->nchan > 2) {
7191 sbuf_printf(sb, " channel 0 channel 1"
7192 " channel 2 channel 3\n");
7193 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
7194 nrate[0], nrate[1], nrate[2], nrate[3]);
7195 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
7196 orate[0], orate[1], orate[2], orate[3]);
7198 sbuf_printf(sb, " channel 0 channel 1\n");
7199 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
7200 nrate[0], nrate[1]);
7201 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
7202 orate[0], orate[1]);
7205 rc = sbuf_finish(sb);
7212 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
7214 struct adapter *sc = arg1;
7219 rc = sysctl_wire_old_buffer(req, 0);
7223 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7227 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
7230 t4_ulprx_read_la(sc, buf);
7233 sbuf_printf(sb, " Pcmd Type Message"
7235 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
7236 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
7237 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
7240 rc = sbuf_finish(sb);
7247 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
7249 struct adapter *sc = arg1;
7253 rc = sysctl_wire_old_buffer(req, 0);
7257 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7261 v = t4_read_reg(sc, A_SGE_STAT_CFG);
7262 if (G_STATSOURCE_T5(v) == 7) {
7263 if (G_STATMODE(v) == 0) {
7264 sbuf_printf(sb, "total %d, incomplete %d",
7265 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7266 t4_read_reg(sc, A_SGE_STAT_MATCH));
7267 } else if (G_STATMODE(v) == 1) {
7268 sbuf_printf(sb, "total %d, data overflow %d",
7269 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7270 t4_read_reg(sc, A_SGE_STAT_MATCH));
7273 rc = sbuf_finish(sb);
7281 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf)
7285 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
7286 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
7288 if (fconf & F_FRAGMENTATION)
7289 mode |= T4_FILTER_IP_FRAGMENT;
7291 if (fconf & F_MPSHITTYPE)
7292 mode |= T4_FILTER_MPS_HIT_TYPE;
7294 if (fconf & F_MACMATCH)
7295 mode |= T4_FILTER_MAC_IDX;
7297 if (fconf & F_ETHERTYPE)
7298 mode |= T4_FILTER_ETH_TYPE;
7300 if (fconf & F_PROTOCOL)
7301 mode |= T4_FILTER_IP_PROTO;
7304 mode |= T4_FILTER_IP_TOS;
7307 mode |= T4_FILTER_VLAN;
7309 if (fconf & F_VNIC_ID) {
7310 mode |= T4_FILTER_VNIC;
7312 mode |= T4_FILTER_IC_VNIC;
7316 mode |= T4_FILTER_PORT;
7319 mode |= T4_FILTER_FCoE;
7325 mode_to_fconf(uint32_t mode)
7329 if (mode & T4_FILTER_IP_FRAGMENT)
7330 fconf |= F_FRAGMENTATION;
7332 if (mode & T4_FILTER_MPS_HIT_TYPE)
7333 fconf |= F_MPSHITTYPE;
7335 if (mode & T4_FILTER_MAC_IDX)
7336 fconf |= F_MACMATCH;
7338 if (mode & T4_FILTER_ETH_TYPE)
7339 fconf |= F_ETHERTYPE;
7341 if (mode & T4_FILTER_IP_PROTO)
7342 fconf |= F_PROTOCOL;
7344 if (mode & T4_FILTER_IP_TOS)
7347 if (mode & T4_FILTER_VLAN)
7350 if (mode & T4_FILTER_VNIC)
7353 if (mode & T4_FILTER_PORT)
7356 if (mode & T4_FILTER_FCoE)
7363 mode_to_iconf(uint32_t mode)
7366 if (mode & T4_FILTER_IC_VNIC)
7371 static int check_fspec_against_fconf_iconf(struct adapter *sc,
7372 struct t4_filter_specification *fs)
7374 struct tp_params *tpp = &sc->params.tp;
7377 if (fs->val.frag || fs->mask.frag)
7378 fconf |= F_FRAGMENTATION;
7380 if (fs->val.matchtype || fs->mask.matchtype)
7381 fconf |= F_MPSHITTYPE;
7383 if (fs->val.macidx || fs->mask.macidx)
7384 fconf |= F_MACMATCH;
7386 if (fs->val.ethtype || fs->mask.ethtype)
7387 fconf |= F_ETHERTYPE;
7389 if (fs->val.proto || fs->mask.proto)
7390 fconf |= F_PROTOCOL;
7392 if (fs->val.tos || fs->mask.tos)
7395 if (fs->val.vlan_vld || fs->mask.vlan_vld)
7398 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
7400 if (tpp->ingress_config & F_VNIC)
7404 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
7406 if ((tpp->ingress_config & F_VNIC) == 0)
7410 if (fs->val.iport || fs->mask.iport)
7413 if (fs->val.fcoe || fs->mask.fcoe)
7416 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map)
7423 get_filter_mode(struct adapter *sc, uint32_t *mode)
7425 struct tp_params *tpp = &sc->params.tp;
7428 * We trust the cached values of the relevant TP registers. This means
7429 * things work reliably only if writes to those registers are always via
7430 * t4_set_filter_mode.
7432 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config);
7438 set_filter_mode(struct adapter *sc, uint32_t mode)
7440 struct tp_params *tpp = &sc->params.tp;
7441 uint32_t fconf, iconf;
7444 iconf = mode_to_iconf(mode);
7445 if ((iconf ^ tpp->ingress_config) & F_VNIC) {
7447 * For now we just complain if A_TP_INGRESS_CONFIG is not
7448 * already set to the correct value for the requested filter
7449 * mode. It's not clear if it's safe to write to this register
7450 * on the fly. (And we trust the cached value of the register).
7455 fconf = mode_to_fconf(mode);
7457 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7462 if (sc->tids.ftids_in_use > 0) {
7468 if (uld_active(sc, ULD_TOM)) {
7474 rc = -t4_set_filter_mode(sc, fconf);
7476 end_synchronized_op(sc, LOCK_HELD);
7480 static inline uint64_t
7481 get_filter_hits(struct adapter *sc, uint32_t fid)
7485 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) +
7486 (fid + sc->tids.ftid_base) * TCB_SIZE;
7491 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8);
7492 return (be64toh(hits));
7496 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4);
7497 return (be32toh(hits));
7502 get_filter(struct adapter *sc, struct t4_filter *t)
7504 int i, rc, nfilters = sc->tids.nftids;
7505 struct filter_entry *f;
7507 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7512 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL ||
7513 t->idx >= nfilters) {
7514 t->idx = 0xffffffff;
7518 f = &sc->tids.ftid_tab[t->idx];
7519 for (i = t->idx; i < nfilters; i++, f++) {
7522 t->l2tidx = f->l2t ? f->l2t->idx : 0;
7523 t->smtidx = f->smtidx;
7525 t->hits = get_filter_hits(sc, t->idx);
7527 t->hits = UINT64_MAX;
7534 t->idx = 0xffffffff;
7536 end_synchronized_op(sc, LOCK_HELD);
7541 set_filter(struct adapter *sc, struct t4_filter *t)
7543 unsigned int nfilters, nports;
7544 struct filter_entry *f;
7547 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf");
7551 nfilters = sc->tids.nftids;
7552 nports = sc->params.nports;
7554 if (nfilters == 0) {
7559 if (!(sc->flags & FULL_INIT_DONE)) {
7564 if (t->idx >= nfilters) {
7569 /* Validate against the global filter mode and ingress config */
7570 rc = check_fspec_against_fconf_iconf(sc, &t->fs);
7574 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) {
7579 if (t->fs.val.iport >= nports) {
7584 /* Can't specify an iq if not steering to it */
7585 if (!t->fs.dirsteer && t->fs.iq) {
7590 /* IPv6 filter idx must be 4 aligned */
7591 if (t->fs.type == 1 &&
7592 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) {
7597 if (sc->tids.ftid_tab == NULL) {
7598 KASSERT(sc->tids.ftids_in_use == 0,
7599 ("%s: no memory allocated but filters_in_use > 0",
7602 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) *
7603 nfilters, M_CXGBE, M_NOWAIT | M_ZERO);
7604 if (sc->tids.ftid_tab == NULL) {
7608 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF);
7611 for (i = 0; i < 4; i++) {
7612 f = &sc->tids.ftid_tab[t->idx + i];
7614 if (f->pending || f->valid) {
7623 if (t->fs.type == 0)
7627 f = &sc->tids.ftid_tab[t->idx];
7630 rc = set_filter_wr(sc, t->idx);
7632 end_synchronized_op(sc, 0);
7635 mtx_lock(&sc->tids.ftid_lock);
7637 if (f->pending == 0) {
7638 rc = f->valid ? 0 : EIO;
7642 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
7643 PCATCH, "t4setfw", 0)) {
7648 mtx_unlock(&sc->tids.ftid_lock);
7654 del_filter(struct adapter *sc, struct t4_filter *t)
7656 unsigned int nfilters;
7657 struct filter_entry *f;
7660 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf");
7664 nfilters = sc->tids.nftids;
7666 if (nfilters == 0) {
7671 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 ||
7672 t->idx >= nfilters) {
7677 if (!(sc->flags & FULL_INIT_DONE)) {
7682 f = &sc->tids.ftid_tab[t->idx];
7694 t->fs = f->fs; /* extra info for the caller */
7695 rc = del_filter_wr(sc, t->idx);
7699 end_synchronized_op(sc, 0);
7702 mtx_lock(&sc->tids.ftid_lock);
7704 if (f->pending == 0) {
7705 rc = f->valid ? EIO : 0;
7709 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
7710 PCATCH, "t4delfw", 0)) {
7715 mtx_unlock(&sc->tids.ftid_lock);
7722 clear_filter(struct filter_entry *f)
7725 t4_l2t_release(f->l2t);
7727 bzero(f, sizeof (*f));
7731 set_filter_wr(struct adapter *sc, int fidx)
7733 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
7734 struct fw_filter_wr *fwr;
7735 unsigned int ftid, vnic_vld, vnic_vld_mask;
7736 struct wrq_cookie cookie;
7738 ASSERT_SYNCHRONIZED_OP(sc);
7740 if (f->fs.newdmac || f->fs.newvlan) {
7741 /* This filter needs an L2T entry; allocate one. */
7742 f->l2t = t4_l2t_alloc_switching(sc->l2t);
7745 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport,
7747 t4_l2t_release(f->l2t);
7753 /* Already validated against fconf, iconf */
7754 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0);
7755 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0);
7756 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld)
7760 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld)
7765 ftid = sc->tids.ftid_base + fidx;
7767 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
7770 bzero(fwr, sizeof(*fwr));
7772 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR));
7773 fwr->len16_pkd = htobe32(FW_LEN16(*fwr));
7775 htobe32(V_FW_FILTER_WR_TID(ftid) |
7776 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
7777 V_FW_FILTER_WR_NOREPLY(0) |
7778 V_FW_FILTER_WR_IQ(f->fs.iq));
7779 fwr->del_filter_to_l2tix =
7780 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
7781 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
7782 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
7783 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
7784 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
7785 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
7786 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
7787 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
7788 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
7789 f->fs.newvlan == VLAN_REWRITE) |
7790 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
7791 f->fs.newvlan == VLAN_REWRITE) |
7792 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
7793 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
7794 V_FW_FILTER_WR_PRIO(f->fs.prio) |
7795 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
7796 fwr->ethtype = htobe16(f->fs.val.ethtype);
7797 fwr->ethtypem = htobe16(f->fs.mask.ethtype);
7798 fwr->frag_to_ovlan_vldm =
7799 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
7800 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
7801 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
7802 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) |
7803 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
7804 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask));
7806 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
7807 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
7808 fwr->maci_to_matchtypem =
7809 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
7810 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
7811 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
7812 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
7813 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
7814 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
7815 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
7816 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
7817 fwr->ptcl = f->fs.val.proto;
7818 fwr->ptclm = f->fs.mask.proto;
7819 fwr->ttyp = f->fs.val.tos;
7820 fwr->ttypm = f->fs.mask.tos;
7821 fwr->ivlan = htobe16(f->fs.val.vlan);
7822 fwr->ivlanm = htobe16(f->fs.mask.vlan);
7823 fwr->ovlan = htobe16(f->fs.val.vnic);
7824 fwr->ovlanm = htobe16(f->fs.mask.vnic);
7825 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
7826 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
7827 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
7828 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm));
7829 fwr->lp = htobe16(f->fs.val.dport);
7830 fwr->lpm = htobe16(f->fs.mask.dport);
7831 fwr->fp = htobe16(f->fs.val.sport);
7832 fwr->fpm = htobe16(f->fs.mask.sport);
7834 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma));
7837 sc->tids.ftids_in_use++;
7839 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
7844 del_filter_wr(struct adapter *sc, int fidx)
7846 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
7847 struct fw_filter_wr *fwr;
7849 struct wrq_cookie cookie;
7851 ftid = sc->tids.ftid_base + fidx;
7853 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
7856 bzero(fwr, sizeof (*fwr));
7858 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
7861 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
7866 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
7868 struct adapter *sc = iq->adapter;
7869 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
7870 unsigned int idx = GET_TID(rpl);
7872 struct filter_entry *f;
7874 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
7877 if (is_ftid(sc, idx)) {
7879 idx -= sc->tids.ftid_base;
7880 f = &sc->tids.ftid_tab[idx];
7881 rc = G_COOKIE(rpl->cookie);
7883 mtx_lock(&sc->tids.ftid_lock);
7884 if (rc == FW_FILTER_WR_FLT_ADDED) {
7885 KASSERT(f->pending, ("%s: filter[%u] isn't pending.",
7887 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
7888 f->pending = 0; /* asynchronous setup completed */
7891 if (rc != FW_FILTER_WR_FLT_DELETED) {
7892 /* Add or delete failed, display an error */
7894 "filter %u setup failed with error %u\n",
7899 sc->tids.ftids_in_use--;
7901 wakeup(&sc->tids.ftid_tab);
7902 mtx_unlock(&sc->tids.ftid_lock);
7909 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
7913 if (cntxt->cid > M_CTXTQID)
7916 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
7917 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
7920 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
7924 if (sc->flags & FW_OK) {
7925 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
7932 * Read via firmware failed or wasn't even attempted. Read directly via
7935 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
7937 end_synchronized_op(sc, 0);
7942 load_fw(struct adapter *sc, struct t4_data *fw)
7947 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
7951 if (sc->flags & FULL_INIT_DONE) {
7956 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
7957 if (fw_data == NULL) {
7962 rc = copyin(fw->data, fw_data, fw->len);
7964 rc = -t4_load_fw(sc, fw_data, fw->len);
7966 free(fw_data, M_CXGBE);
7968 end_synchronized_op(sc, 0);
7972 #define MAX_READ_BUF_SIZE (128 * 1024)
7974 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
7976 uint32_t addr, remaining, n;
7981 rc = validate_mem_range(sc, mr->addr, mr->len);
7985 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
7987 remaining = mr->len;
7988 dst = (void *)mr->data;
7991 n = min(remaining, MAX_READ_BUF_SIZE);
7992 read_via_memwin(sc, 2, addr, buf, n);
7994 rc = copyout(buf, dst, n);
8006 #undef MAX_READ_BUF_SIZE
8009 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
8013 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
8016 if (i2cd->len > sizeof(i2cd->data))
8019 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
8022 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
8023 i2cd->offset, i2cd->len, &i2cd->data[0]);
8024 end_synchronized_op(sc, 0);
8030 in_range(int val, int lo, int hi)
8033 return (val < 0 || (val <= hi && val >= lo));
8037 set_sched_class(struct adapter *sc, struct t4_sched_params *p)
8039 int fw_subcmd, fw_type, rc;
8041 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsc");
8045 if (!(sc->flags & FULL_INIT_DONE)) {
8051 * Translate the cxgbetool parameters into T4 firmware parameters. (The
8052 * sub-command and type are in common locations.)
8054 if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG)
8055 fw_subcmd = FW_SCHED_SC_CONFIG;
8056 else if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS)
8057 fw_subcmd = FW_SCHED_SC_PARAMS;
8062 if (p->type == SCHED_CLASS_TYPE_PACKET)
8063 fw_type = FW_SCHED_TYPE_PKTSCHED;
8069 if (fw_subcmd == FW_SCHED_SC_CONFIG) {
8070 /* Vet our parameters ..*/
8071 if (p->u.config.minmax < 0) {
8076 /* And pass the request to the firmware ...*/
8077 rc = -t4_sched_config(sc, fw_type, p->u.config.minmax, 1);
8081 if (fw_subcmd == FW_SCHED_SC_PARAMS) {
8087 if (p->u.params.level == SCHED_CLASS_LEVEL_CL_RL)
8088 fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL;
8089 else if (p->u.params.level == SCHED_CLASS_LEVEL_CL_WRR)
8090 fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
8091 else if (p->u.params.level == SCHED_CLASS_LEVEL_CH_RL)
8092 fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL;
8098 if (p->u.params.mode == SCHED_CLASS_MODE_CLASS)
8099 fw_mode = FW_SCHED_PARAMS_MODE_CLASS;
8100 else if (p->u.params.mode == SCHED_CLASS_MODE_FLOW)
8101 fw_mode = FW_SCHED_PARAMS_MODE_FLOW;
8107 if (p->u.params.rateunit == SCHED_CLASS_RATEUNIT_BITS)
8108 fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE;
8109 else if (p->u.params.rateunit == SCHED_CLASS_RATEUNIT_PKTS)
8110 fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE;
8116 if (p->u.params.ratemode == SCHED_CLASS_RATEMODE_REL)
8117 fw_ratemode = FW_SCHED_PARAMS_RATE_REL;
8118 else if (p->u.params.ratemode == SCHED_CLASS_RATEMODE_ABS)
8119 fw_ratemode = FW_SCHED_PARAMS_RATE_ABS;
8125 /* Vet our parameters ... */
8126 if (!in_range(p->u.params.channel, 0, 3) ||
8127 !in_range(p->u.params.cl, 0, sc->chip_params->nsched_cls) ||
8128 !in_range(p->u.params.minrate, 0, 10000000) ||
8129 !in_range(p->u.params.maxrate, 0, 10000000) ||
8130 !in_range(p->u.params.weight, 0, 100)) {
8136 * Translate any unset parameters into the firmware's
8137 * nomenclature and/or fail the call if the parameters
8140 if (p->u.params.rateunit < 0 || p->u.params.ratemode < 0 ||
8141 p->u.params.channel < 0 || p->u.params.cl < 0) {
8145 if (p->u.params.minrate < 0)
8146 p->u.params.minrate = 0;
8147 if (p->u.params.maxrate < 0) {
8148 if (p->u.params.level == SCHED_CLASS_LEVEL_CL_RL ||
8149 p->u.params.level == SCHED_CLASS_LEVEL_CH_RL) {
8153 p->u.params.maxrate = 0;
8155 if (p->u.params.weight < 0) {
8156 if (p->u.params.level == SCHED_CLASS_LEVEL_CL_WRR) {
8160 p->u.params.weight = 0;
8162 if (p->u.params.pktsize < 0) {
8163 if (p->u.params.level == SCHED_CLASS_LEVEL_CL_RL ||
8164 p->u.params.level == SCHED_CLASS_LEVEL_CH_RL) {
8168 p->u.params.pktsize = 0;
8171 /* See what the firmware thinks of the request ... */
8172 rc = -t4_sched_params(sc, fw_type, fw_level, fw_mode,
8173 fw_rateunit, fw_ratemode, p->u.params.channel,
8174 p->u.params.cl, p->u.params.minrate, p->u.params.maxrate,
8175 p->u.params.weight, p->u.params.pktsize, 1);
8181 end_synchronized_op(sc, 0);
8186 set_sched_queue(struct adapter *sc, struct t4_sched_queue *p)
8188 struct port_info *pi = NULL;
8190 struct sge_txq *txq;
8191 uint32_t fw_mnem, fw_queue, fw_class;
8194 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq");
8198 if (!(sc->flags & FULL_INIT_DONE)) {
8203 if (p->port >= sc->params.nports) {
8208 /* XXX: Only supported for the main VI. */
8209 pi = sc->port[p->port];
8211 if (!in_range(p->queue, 0, vi->ntxq - 1) || !in_range(p->cl, 0, 7)) {
8217 * Create a template for the FW_PARAMS_CMD mnemonic and value (TX
8218 * Scheduling Class in this case).
8220 fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
8221 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH));
8222 fw_class = p->cl < 0 ? 0xffffffff : p->cl;
8225 * If op.queue is non-negative, then we're only changing the scheduling
8226 * on a single specified TX queue.
8228 if (p->queue >= 0) {
8229 txq = &sc->sge.txq[vi->first_txq + p->queue];
8230 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8231 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8237 * Change the scheduling on all the TX queues for the
8240 for_each_txq(vi, i, txq) {
8241 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8242 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8250 end_synchronized_op(sc, 0);
8255 t4_os_find_pci_capability(struct adapter *sc, int cap)
8259 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
8263 t4_os_pci_save_state(struct adapter *sc)
8266 struct pci_devinfo *dinfo;
8269 dinfo = device_get_ivars(dev);
8271 pci_cfg_save(dev, dinfo, 0);
8276 t4_os_pci_restore_state(struct adapter *sc)
8279 struct pci_devinfo *dinfo;
8282 dinfo = device_get_ivars(dev);
8284 pci_cfg_restore(dev, dinfo);
8289 t4_os_portmod_changed(const struct adapter *sc, int idx)
8291 struct port_info *pi = sc->port[idx];
8295 static const char *mod_str[] = {
8296 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
8299 for_each_vi(pi, v, vi) {
8300 build_medialist(pi, &vi->media);
8303 ifp = pi->vi[0].ifp;
8304 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
8305 if_printf(ifp, "transceiver unplugged.\n");
8306 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
8307 if_printf(ifp, "unknown transceiver inserted.\n");
8308 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
8309 if_printf(ifp, "unsupported transceiver inserted.\n");
8310 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
8311 if_printf(ifp, "%s transceiver inserted.\n",
8312 mod_str[pi->mod_type]);
8314 if_printf(ifp, "transceiver (type %d) inserted.\n",
8320 t4_os_link_changed(struct adapter *sc, int idx, int link_stat, int reason)
8322 struct port_info *pi = sc->port[idx];
8331 pi->linkdnrc = reason;
8333 for_each_vi(pi, v, vi) {
8339 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed);
8340 if_link_state_change(ifp, LINK_STATE_UP);
8342 if_link_state_change(ifp, LINK_STATE_DOWN);
8348 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
8352 sx_slock(&t4_list_lock);
8353 SLIST_FOREACH(sc, &t4_list, link) {
8355 * func should not make any assumptions about what state sc is
8356 * in - the only guarantee is that sc->sc_lock is a valid lock.
8360 sx_sunlock(&t4_list_lock);
8364 t4_open(struct cdev *dev, int flags, int type, struct thread *td)
8370 t4_close(struct cdev *dev, int flags, int type, struct thread *td)
8376 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
8380 struct adapter *sc = dev->si_drv1;
8382 rc = priv_check(td, PRIV_DRIVER);
8387 case CHELSIO_T4_GETREG: {
8388 struct t4_reg *edata = (struct t4_reg *)data;
8390 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8393 if (edata->size == 4)
8394 edata->val = t4_read_reg(sc, edata->addr);
8395 else if (edata->size == 8)
8396 edata->val = t4_read_reg64(sc, edata->addr);
8402 case CHELSIO_T4_SETREG: {
8403 struct t4_reg *edata = (struct t4_reg *)data;
8405 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8408 if (edata->size == 4) {
8409 if (edata->val & 0xffffffff00000000)
8411 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
8412 } else if (edata->size == 8)
8413 t4_write_reg64(sc, edata->addr, edata->val);
8418 case CHELSIO_T4_REGDUMP: {
8419 struct t4_regdump *regs = (struct t4_regdump *)data;
8420 int reglen = is_t4(sc) ? T4_REGDUMP_SIZE : T5_REGDUMP_SIZE;
8423 if (regs->len < reglen) {
8424 regs->len = reglen; /* hint to the caller */
8429 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
8430 get_regs(sc, regs, buf);
8431 rc = copyout(buf, regs->data, reglen);
8435 case CHELSIO_T4_GET_FILTER_MODE:
8436 rc = get_filter_mode(sc, (uint32_t *)data);
8438 case CHELSIO_T4_SET_FILTER_MODE:
8439 rc = set_filter_mode(sc, *(uint32_t *)data);
8441 case CHELSIO_T4_GET_FILTER:
8442 rc = get_filter(sc, (struct t4_filter *)data);
8444 case CHELSIO_T4_SET_FILTER:
8445 rc = set_filter(sc, (struct t4_filter *)data);
8447 case CHELSIO_T4_DEL_FILTER:
8448 rc = del_filter(sc, (struct t4_filter *)data);
8450 case CHELSIO_T4_GET_SGE_CONTEXT:
8451 rc = get_sge_context(sc, (struct t4_sge_context *)data);
8453 case CHELSIO_T4_LOAD_FW:
8454 rc = load_fw(sc, (struct t4_data *)data);
8456 case CHELSIO_T4_GET_MEM:
8457 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
8459 case CHELSIO_T4_GET_I2C:
8460 rc = read_i2c(sc, (struct t4_i2c_data *)data);
8462 case CHELSIO_T4_CLEAR_STATS: {
8464 u_int port_id = *(uint32_t *)data;
8465 struct port_info *pi;
8468 if (port_id >= sc->params.nports)
8470 pi = sc->port[port_id];
8473 t4_clr_port_stats(sc, pi->tx_chan);
8474 pi->tx_parse_error = 0;
8475 mtx_lock(&sc->reg_lock);
8476 for_each_vi(pi, v, vi) {
8477 if (vi->flags & VI_INIT_DONE)
8478 t4_clr_vi_stats(sc, vi->viid);
8480 mtx_unlock(&sc->reg_lock);
8483 * Since this command accepts a port, clear stats for
8484 * all VIs on this port.
8486 for_each_vi(pi, v, vi) {
8487 if (vi->flags & VI_INIT_DONE) {
8488 struct sge_rxq *rxq;
8489 struct sge_txq *txq;
8490 struct sge_wrq *wrq;
8492 for_each_rxq(vi, i, rxq) {
8493 #if defined(INET) || defined(INET6)
8494 rxq->lro.lro_queued = 0;
8495 rxq->lro.lro_flushed = 0;
8498 rxq->vlan_extraction = 0;
8501 for_each_txq(vi, i, txq) {
8504 txq->vlan_insertion = 0;
8508 txq->txpkts0_wrs = 0;
8509 txq->txpkts1_wrs = 0;
8510 txq->txpkts0_pkts = 0;
8511 txq->txpkts1_pkts = 0;
8512 mp_ring_reset_stats(txq->r);
8516 /* nothing to clear for each ofld_rxq */
8518 for_each_ofld_txq(vi, i, wrq) {
8519 wrq->tx_wrs_direct = 0;
8520 wrq->tx_wrs_copied = 0;
8524 if (IS_MAIN_VI(vi)) {
8525 wrq = &sc->sge.ctrlq[pi->port_id];
8526 wrq->tx_wrs_direct = 0;
8527 wrq->tx_wrs_copied = 0;
8533 case CHELSIO_T4_SCHED_CLASS:
8534 rc = set_sched_class(sc, (struct t4_sched_params *)data);
8536 case CHELSIO_T4_SCHED_QUEUE:
8537 rc = set_sched_queue(sc, (struct t4_sched_queue *)data);
8539 case CHELSIO_T4_GET_TRACER:
8540 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
8542 case CHELSIO_T4_SET_TRACER:
8543 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
8553 t4_db_full(struct adapter *sc)
8556 CXGBE_UNIMPLEMENTED(__func__);
8560 t4_db_dropped(struct adapter *sc)
8563 CXGBE_UNIMPLEMENTED(__func__);
8568 t4_iscsi_init(struct ifnet *ifp, unsigned int tag_mask,
8569 const unsigned int *pgsz_order)
8571 struct vi_info *vi = ifp->if_softc;
8572 struct adapter *sc = vi->pi->adapter;
8574 t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask);
8575 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) |
8576 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) |
8577 V_HPZ3(pgsz_order[3]));
8581 toe_capability(struct vi_info *vi, int enable)
8584 struct port_info *pi = vi->pi;
8585 struct adapter *sc = pi->adapter;
8587 ASSERT_SYNCHRONIZED_OP(sc);
8589 if (!is_offload(sc))
8593 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
8594 /* TOE is already enabled. */
8599 * We need the port's queues around so that we're able to send
8600 * and receive CPLs to/from the TOE even if the ifnet for this
8601 * port has never been UP'd administratively.
8603 if (!(vi->flags & VI_INIT_DONE)) {
8604 rc = vi_full_init(vi);
8608 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
8609 rc = vi_full_init(&pi->vi[0]);
8614 if (isset(&sc->offload_map, pi->port_id)) {
8615 /* TOE is enabled on another VI of this port. */
8620 if (!uld_active(sc, ULD_TOM)) {
8621 rc = t4_activate_uld(sc, ULD_TOM);
8624 "You must kldload t4_tom.ko before trying "
8625 "to enable TOE on a cxgbe interface.\n");
8629 KASSERT(sc->tom_softc != NULL,
8630 ("%s: TOM activated but softc NULL", __func__));
8631 KASSERT(uld_active(sc, ULD_TOM),
8632 ("%s: TOM activated but flag not set", __func__));
8635 /* Activate iWARP and iSCSI too, if the modules are loaded. */
8636 if (!uld_active(sc, ULD_IWARP))
8637 (void) t4_activate_uld(sc, ULD_IWARP);
8638 if (!uld_active(sc, ULD_ISCSI))
8639 (void) t4_activate_uld(sc, ULD_ISCSI);
8642 setbit(&sc->offload_map, pi->port_id);
8646 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
8649 KASSERT(uld_active(sc, ULD_TOM),
8650 ("%s: TOM never initialized?", __func__));
8651 clrbit(&sc->offload_map, pi->port_id);
8658 * Add an upper layer driver to the global list.
8661 t4_register_uld(struct uld_info *ui)
8666 sx_xlock(&t4_uld_list_lock);
8667 SLIST_FOREACH(u, &t4_uld_list, link) {
8668 if (u->uld_id == ui->uld_id) {
8674 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
8677 sx_xunlock(&t4_uld_list_lock);
8682 t4_unregister_uld(struct uld_info *ui)
8687 sx_xlock(&t4_uld_list_lock);
8689 SLIST_FOREACH(u, &t4_uld_list, link) {
8691 if (ui->refcount > 0) {
8696 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
8702 sx_xunlock(&t4_uld_list_lock);
8707 t4_activate_uld(struct adapter *sc, int id)
8710 struct uld_info *ui;
8712 ASSERT_SYNCHRONIZED_OP(sc);
8714 if (id < 0 || id > ULD_MAX)
8716 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
8718 sx_slock(&t4_uld_list_lock);
8720 SLIST_FOREACH(ui, &t4_uld_list, link) {
8721 if (ui->uld_id == id) {
8722 if (!(sc->flags & FULL_INIT_DONE)) {
8723 rc = adapter_full_init(sc);
8728 rc = ui->activate(sc);
8730 setbit(&sc->active_ulds, id);
8737 sx_sunlock(&t4_uld_list_lock);
8743 t4_deactivate_uld(struct adapter *sc, int id)
8746 struct uld_info *ui;
8748 ASSERT_SYNCHRONIZED_OP(sc);
8750 if (id < 0 || id > ULD_MAX)
8754 sx_slock(&t4_uld_list_lock);
8756 SLIST_FOREACH(ui, &t4_uld_list, link) {
8757 if (ui->uld_id == id) {
8758 rc = ui->deactivate(sc);
8760 clrbit(&sc->active_ulds, id);
8767 sx_sunlock(&t4_uld_list_lock);
8773 uld_active(struct adapter *sc, int uld_id)
8776 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
8778 return (isset(&sc->active_ulds, uld_id));
8783 * Come up with reasonable defaults for some of the tunables, provided they're
8784 * not set by the user (in which case we'll use the values as is).
8787 tweak_tunables(void)
8789 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
8791 if (t4_ntxq10g < 1) {
8793 t4_ntxq10g = rss_getnumbuckets();
8795 t4_ntxq10g = min(nc, NTXQ_10G);
8799 if (t4_ntxq1g < 1) {
8801 /* XXX: way too many for 1GbE? */
8802 t4_ntxq1g = rss_getnumbuckets();
8804 t4_ntxq1g = min(nc, NTXQ_1G);
8809 t4_ntxq_vi = min(nc, NTXQ_VI);
8811 if (t4_nrxq10g < 1) {
8813 t4_nrxq10g = rss_getnumbuckets();
8815 t4_nrxq10g = min(nc, NRXQ_10G);
8819 if (t4_nrxq1g < 1) {
8821 /* XXX: way too many for 1GbE? */
8822 t4_nrxq1g = rss_getnumbuckets();
8824 t4_nrxq1g = min(nc, NRXQ_1G);
8829 t4_nrxq_vi = min(nc, NRXQ_VI);
8832 if (t4_nofldtxq10g < 1)
8833 t4_nofldtxq10g = min(nc, NOFLDTXQ_10G);
8835 if (t4_nofldtxq1g < 1)
8836 t4_nofldtxq1g = min(nc, NOFLDTXQ_1G);
8838 if (t4_nofldtxq_vi < 1)
8839 t4_nofldtxq_vi = min(nc, NOFLDTXQ_VI);
8841 if (t4_nofldrxq10g < 1)
8842 t4_nofldrxq10g = min(nc, NOFLDRXQ_10G);
8844 if (t4_nofldrxq1g < 1)
8845 t4_nofldrxq1g = min(nc, NOFLDRXQ_1G);
8847 if (t4_nofldrxq_vi < 1)
8848 t4_nofldrxq_vi = min(nc, NOFLDRXQ_VI);
8850 if (t4_toecaps_allowed == -1)
8851 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
8853 if (t4_toecaps_allowed == -1)
8854 t4_toecaps_allowed = 0;
8858 if (t4_nnmtxq_vi < 1)
8859 t4_nnmtxq_vi = min(nc, NNMTXQ_VI);
8861 if (t4_nnmrxq_vi < 1)
8862 t4_nnmrxq_vi = min(nc, NNMRXQ_VI);
8865 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS)
8866 t4_tmr_idx_10g = TMR_IDX_10G;
8868 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS)
8869 t4_pktc_idx_10g = PKTC_IDX_10G;
8871 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS)
8872 t4_tmr_idx_1g = TMR_IDX_1G;
8874 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS)
8875 t4_pktc_idx_1g = PKTC_IDX_1G;
8877 if (t4_qsize_txq < 128)
8880 if (t4_qsize_rxq < 128)
8882 while (t4_qsize_rxq & 7)
8885 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
8888 static struct sx mlu; /* mod load unload */
8889 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
8892 mod_event(module_t mod, int cmd, void *arg)
8895 static int loaded = 0;
8900 if (loaded++ == 0) {
8902 sx_init(&t4_list_lock, "T4/T5 adapters");
8903 SLIST_INIT(&t4_list);
8905 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
8906 SLIST_INIT(&t4_uld_list);
8908 t4_tracer_modload();
8916 if (--loaded == 0) {
8919 sx_slock(&t4_list_lock);
8920 if (!SLIST_EMPTY(&t4_list)) {
8922 sx_sunlock(&t4_list_lock);
8926 sx_slock(&t4_uld_list_lock);
8927 if (!SLIST_EMPTY(&t4_uld_list)) {
8929 sx_sunlock(&t4_uld_list_lock);
8930 sx_sunlock(&t4_list_lock);
8935 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
8936 uprintf("%ju clusters with custom free routine "
8937 "still is use.\n", t4_sge_extfree_refs());
8938 pause("t4unload", 2 * hz);
8941 sx_sunlock(&t4_uld_list_lock);
8943 sx_sunlock(&t4_list_lock);
8945 if (t4_sge_extfree_refs() == 0) {
8946 t4_tracer_modunload();
8948 sx_destroy(&t4_uld_list_lock);
8950 sx_destroy(&t4_list_lock);
8955 loaded++; /* undo earlier decrement */
8966 static devclass_t t4_devclass, t5_devclass;
8967 static devclass_t cxgbe_devclass, cxl_devclass;
8968 static devclass_t vcxgbe_devclass, vcxl_devclass;
8970 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
8971 MODULE_VERSION(t4nex, 1);
8972 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
8974 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
8975 MODULE_VERSION(t5nex, 1);
8976 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
8978 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
8979 MODULE_VERSION(cxgbe, 1);
8981 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
8982 MODULE_VERSION(cxl, 1);
8984 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
8985 MODULE_VERSION(vcxgbe, 1);
8987 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
8988 MODULE_VERSION(vcxl, 1);