2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
33 #include "opt_inet6.h"
35 #include <sys/param.h>
38 #include <sys/kernel.h>
40 #include <sys/systm.h>
41 #include <sys/counter.h>
42 #include <sys/module.h>
43 #include <sys/malloc.h>
44 #include <sys/queue.h>
45 #include <sys/taskqueue.h>
46 #include <sys/pciio.h>
47 #include <dev/pci/pcireg.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pci_private.h>
50 #include <sys/firmware.h>
53 #include <sys/socket.h>
54 #include <sys/sockio.h>
55 #include <sys/sysctl.h>
56 #include <net/ethernet.h>
58 #include <net/if_types.h>
59 #include <net/if_dl.h>
60 #include <net/if_vlan_var.h>
62 #include <net/rss_config.h>
64 #if defined(__i386__) || defined(__amd64__)
70 #include <ddb/db_lex.h>
73 #include "common/common.h"
74 #include "common/t4_msg.h"
75 #include "common/t4_regs.h"
76 #include "common/t4_regs_values.h"
79 #include "t4_mp_ring.h"
81 /* T4 bus driver interface */
82 static int t4_probe(device_t);
83 static int t4_attach(device_t);
84 static int t4_detach(device_t);
85 static device_method_t t4_methods[] = {
86 DEVMETHOD(device_probe, t4_probe),
87 DEVMETHOD(device_attach, t4_attach),
88 DEVMETHOD(device_detach, t4_detach),
92 static driver_t t4_driver = {
95 sizeof(struct adapter)
99 /* T4 port (cxgbe) interface */
100 static int cxgbe_probe(device_t);
101 static int cxgbe_attach(device_t);
102 static int cxgbe_detach(device_t);
103 static device_method_t cxgbe_methods[] = {
104 DEVMETHOD(device_probe, cxgbe_probe),
105 DEVMETHOD(device_attach, cxgbe_attach),
106 DEVMETHOD(device_detach, cxgbe_detach),
109 static driver_t cxgbe_driver = {
112 sizeof(struct port_info)
115 /* T4 VI (vcxgbe) interface */
116 static int vcxgbe_probe(device_t);
117 static int vcxgbe_attach(device_t);
118 static int vcxgbe_detach(device_t);
119 static device_method_t vcxgbe_methods[] = {
120 DEVMETHOD(device_probe, vcxgbe_probe),
121 DEVMETHOD(device_attach, vcxgbe_attach),
122 DEVMETHOD(device_detach, vcxgbe_detach),
125 static driver_t vcxgbe_driver = {
128 sizeof(struct vi_info)
131 static d_ioctl_t t4_ioctl;
132 static d_open_t t4_open;
133 static d_close_t t4_close;
135 static struct cdevsw t4_cdevsw = {
136 .d_version = D_VERSION,
144 /* T5 bus driver interface */
145 static int t5_probe(device_t);
146 static device_method_t t5_methods[] = {
147 DEVMETHOD(device_probe, t5_probe),
148 DEVMETHOD(device_attach, t4_attach),
149 DEVMETHOD(device_detach, t4_detach),
153 static driver_t t5_driver = {
156 sizeof(struct adapter)
160 /* T5 port (cxl) interface */
161 static driver_t cxl_driver = {
164 sizeof(struct port_info)
167 /* T5 VI (vcxl) interface */
168 static driver_t vcxl_driver = {
171 sizeof(struct vi_info)
174 static struct cdevsw t5_cdevsw = {
175 .d_version = D_VERSION,
183 /* ifnet + media interface */
184 static void cxgbe_init(void *);
185 static int cxgbe_ioctl(struct ifnet *, unsigned long, caddr_t);
186 static int cxgbe_transmit(struct ifnet *, struct mbuf *);
187 static void cxgbe_qflush(struct ifnet *);
188 static int cxgbe_media_change(struct ifnet *);
189 static void cxgbe_media_status(struct ifnet *, struct ifmediareq *);
191 MALLOC_DEFINE(M_CXGBE, "cxgbe", "Chelsio T4/T5 Ethernet driver and services");
194 * Correct lock order when you need to acquire multiple locks is t4_list_lock,
195 * then ADAPTER_LOCK, then t4_uld_list_lock.
197 static struct sx t4_list_lock;
198 SLIST_HEAD(, adapter) t4_list;
200 static struct sx t4_uld_list_lock;
201 SLIST_HEAD(, uld_info) t4_uld_list;
205 * Tunables. See tweak_tunables() too.
207 * Each tunable is set to a default value here if it's known at compile-time.
208 * Otherwise it is set to -1 as an indication to tweak_tunables() that it should
209 * provide a reasonable default when the driver is loaded.
211 * Tunables applicable to both T4 and T5 are under hw.cxgbe. Those specific to
212 * T5 are under hw.cxl.
216 * Number of queues for tx and rx, 10G and 1G, NIC and offload.
219 static int t4_ntxq10g = -1;
220 TUNABLE_INT("hw.cxgbe.ntxq10g", &t4_ntxq10g);
223 static int t4_nrxq10g = -1;
224 TUNABLE_INT("hw.cxgbe.nrxq10g", &t4_nrxq10g);
227 static int t4_ntxq1g = -1;
228 TUNABLE_INT("hw.cxgbe.ntxq1g", &t4_ntxq1g);
231 static int t4_nrxq1g = -1;
232 TUNABLE_INT("hw.cxgbe.nrxq1g", &t4_nrxq1g);
235 static int t4_ntxq_vi = -1;
236 TUNABLE_INT("hw.cxgbe.ntxq_vi", &t4_ntxq_vi);
239 static int t4_nrxq_vi = -1;
240 TUNABLE_INT("hw.cxgbe.nrxq_vi", &t4_nrxq_vi);
242 static int t4_rsrv_noflowq = 0;
243 TUNABLE_INT("hw.cxgbe.rsrv_noflowq", &t4_rsrv_noflowq);
246 #define NOFLDTXQ_10G 8
247 static int t4_nofldtxq10g = -1;
248 TUNABLE_INT("hw.cxgbe.nofldtxq10g", &t4_nofldtxq10g);
250 #define NOFLDRXQ_10G 2
251 static int t4_nofldrxq10g = -1;
252 TUNABLE_INT("hw.cxgbe.nofldrxq10g", &t4_nofldrxq10g);
254 #define NOFLDTXQ_1G 2
255 static int t4_nofldtxq1g = -1;
256 TUNABLE_INT("hw.cxgbe.nofldtxq1g", &t4_nofldtxq1g);
258 #define NOFLDRXQ_1G 1
259 static int t4_nofldrxq1g = -1;
260 TUNABLE_INT("hw.cxgbe.nofldrxq1g", &t4_nofldrxq1g);
262 #define NOFLDTXQ_VI 1
263 static int t4_nofldtxq_vi = -1;
264 TUNABLE_INT("hw.cxgbe.nofldtxq_vi", &t4_nofldtxq_vi);
266 #define NOFLDRXQ_VI 1
267 static int t4_nofldrxq_vi = -1;
268 TUNABLE_INT("hw.cxgbe.nofldrxq_vi", &t4_nofldrxq_vi);
273 static int t4_nnmtxq_vi = -1;
274 TUNABLE_INT("hw.cxgbe.nnmtxq_vi", &t4_nnmtxq_vi);
277 static int t4_nnmrxq_vi = -1;
278 TUNABLE_INT("hw.cxgbe.nnmrxq_vi", &t4_nnmrxq_vi);
282 * Holdoff parameters for 10G and 1G ports.
284 #define TMR_IDX_10G 1
285 static int t4_tmr_idx_10g = TMR_IDX_10G;
286 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_10G", &t4_tmr_idx_10g);
288 #define PKTC_IDX_10G (-1)
289 static int t4_pktc_idx_10g = PKTC_IDX_10G;
290 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_10G", &t4_pktc_idx_10g);
293 static int t4_tmr_idx_1g = TMR_IDX_1G;
294 TUNABLE_INT("hw.cxgbe.holdoff_timer_idx_1G", &t4_tmr_idx_1g);
296 #define PKTC_IDX_1G (-1)
297 static int t4_pktc_idx_1g = PKTC_IDX_1G;
298 TUNABLE_INT("hw.cxgbe.holdoff_pktc_idx_1G", &t4_pktc_idx_1g);
301 * Size (# of entries) of each tx and rx queue.
303 static unsigned int t4_qsize_txq = TX_EQ_QSIZE;
304 TUNABLE_INT("hw.cxgbe.qsize_txq", &t4_qsize_txq);
306 static unsigned int t4_qsize_rxq = RX_IQ_QSIZE;
307 TUNABLE_INT("hw.cxgbe.qsize_rxq", &t4_qsize_rxq);
310 * Interrupt types allowed (bits 0, 1, 2 = INTx, MSI, MSI-X respectively).
312 static int t4_intr_types = INTR_MSIX | INTR_MSI | INTR_INTX;
313 TUNABLE_INT("hw.cxgbe.interrupt_types", &t4_intr_types);
316 * Configuration file.
318 #define DEFAULT_CF "default"
319 #define FLASH_CF "flash"
320 #define UWIRE_CF "uwire"
321 #define FPGA_CF "fpga"
322 static char t4_cfg_file[32] = DEFAULT_CF;
323 TUNABLE_STR("hw.cxgbe.config_file", t4_cfg_file, sizeof(t4_cfg_file));
326 * PAUSE settings (bit 0, 1 = rx_pause, tx_pause respectively).
327 * rx_pause = 1 to heed incoming PAUSE frames, 0 to ignore them.
328 * tx_pause = 1 to emit PAUSE frames when the rx FIFO reaches its high water
329 * mark or when signalled to do so, 0 to never emit PAUSE.
331 static int t4_pause_settings = PAUSE_TX | PAUSE_RX;
332 TUNABLE_INT("hw.cxgbe.pause_settings", &t4_pause_settings);
335 * Firmware auto-install by driver during attach (0, 1, 2 = prohibited, allowed,
336 * encouraged respectively).
338 static unsigned int t4_fw_install = 1;
339 TUNABLE_INT("hw.cxgbe.fw_install", &t4_fw_install);
342 * ASIC features that will be used. Disable the ones you don't want so that the
343 * chip resources aren't wasted on features that will not be used.
345 static int t4_nbmcaps_allowed = 0;
346 TUNABLE_INT("hw.cxgbe.nbmcaps_allowed", &t4_nbmcaps_allowed);
348 static int t4_linkcaps_allowed = 0; /* No DCBX, PPP, etc. by default */
349 TUNABLE_INT("hw.cxgbe.linkcaps_allowed", &t4_linkcaps_allowed);
351 static int t4_switchcaps_allowed = FW_CAPS_CONFIG_SWITCH_INGRESS |
352 FW_CAPS_CONFIG_SWITCH_EGRESS;
353 TUNABLE_INT("hw.cxgbe.switchcaps_allowed", &t4_switchcaps_allowed);
355 static int t4_niccaps_allowed = FW_CAPS_CONFIG_NIC;
356 TUNABLE_INT("hw.cxgbe.niccaps_allowed", &t4_niccaps_allowed);
358 static int t4_toecaps_allowed = -1;
359 TUNABLE_INT("hw.cxgbe.toecaps_allowed", &t4_toecaps_allowed);
361 static int t4_rdmacaps_allowed = -1;
362 TUNABLE_INT("hw.cxgbe.rdmacaps_allowed", &t4_rdmacaps_allowed);
364 static int t4_tlscaps_allowed = 0;
365 TUNABLE_INT("hw.cxgbe.tlscaps_allowed", &t4_tlscaps_allowed);
367 static int t4_iscsicaps_allowed = -1;
368 TUNABLE_INT("hw.cxgbe.iscsicaps_allowed", &t4_iscsicaps_allowed);
370 static int t4_fcoecaps_allowed = 0;
371 TUNABLE_INT("hw.cxgbe.fcoecaps_allowed", &t4_fcoecaps_allowed);
373 static int t5_write_combine = 0;
374 TUNABLE_INT("hw.cxl.write_combine", &t5_write_combine);
376 static int t4_num_vis = 1;
377 TUNABLE_INT("hw.cxgbe.num_vis", &t4_num_vis);
379 /* Functions used by extra VIs to obtain unique MAC addresses for each VI. */
380 static int vi_mac_funcs[] = {
383 FW_VI_FUNC_OPENISCSI,
389 struct intrs_and_queues {
390 uint16_t intr_type; /* INTx, MSI, or MSI-X */
391 uint16_t nirq; /* Total # of vectors */
392 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */
393 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */
394 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */
395 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */
396 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */
397 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */
398 uint16_t rsrv_noflowq; /* Flag whether to reserve queue 0 */
399 uint16_t nofldtxq10g; /* # of TOE txq's for each 10G port */
400 uint16_t nofldrxq10g; /* # of TOE rxq's for each 10G port */
401 uint16_t nofldtxq1g; /* # of TOE txq's for each 1G port */
402 uint16_t nofldrxq1g; /* # of TOE rxq's for each 1G port */
404 /* The vcxgbe/vcxl interfaces use these and not the ones above. */
405 uint16_t ntxq_vi; /* # of NIC txq's */
406 uint16_t nrxq_vi; /* # of NIC rxq's */
407 uint16_t nofldtxq_vi; /* # of TOE txq's */
408 uint16_t nofldrxq_vi; /* # of TOE rxq's */
409 uint16_t nnmtxq_vi; /* # of netmap txq's */
410 uint16_t nnmrxq_vi; /* # of netmap rxq's */
413 struct filter_entry {
414 uint32_t valid:1; /* filter allocated and valid */
415 uint32_t locked:1; /* filter is administratively locked */
416 uint32_t pending:1; /* filter action is pending firmware reply */
417 uint32_t smtidx:8; /* Source MAC Table index for smac */
418 struct l2t_entry *l2t; /* Layer Two Table entry for dmac */
420 struct t4_filter_specification fs;
423 static int map_bars_0_and_4(struct adapter *);
424 static int map_bar_2(struct adapter *);
425 static void setup_memwin(struct adapter *);
426 static void position_memwin(struct adapter *, int, uint32_t);
427 static int rw_via_memwin(struct adapter *, int, uint32_t, uint32_t *, int, int);
428 static inline int read_via_memwin(struct adapter *, int, uint32_t, uint32_t *,
430 static inline int write_via_memwin(struct adapter *, int, uint32_t,
431 const uint32_t *, int);
432 static int validate_mem_range(struct adapter *, uint32_t, int);
433 static int fwmtype_to_hwmtype(int);
434 static int validate_mt_off_len(struct adapter *, int, uint32_t, int,
436 static int fixup_devlog_params(struct adapter *);
437 static int cfg_itype_and_nqueues(struct adapter *, int, int, int,
438 struct intrs_and_queues *);
439 static int prep_firmware(struct adapter *);
440 static int partition_resources(struct adapter *, const struct firmware *,
442 static int get_params__pre_init(struct adapter *);
443 static int get_params__post_init(struct adapter *);
444 static int set_params__post_init(struct adapter *);
445 static void t4_set_desc(struct adapter *);
446 static void build_medialist(struct port_info *, struct ifmedia *);
447 static int cxgbe_init_synchronized(struct vi_info *);
448 static int cxgbe_uninit_synchronized(struct vi_info *);
449 static int setup_intr_handlers(struct adapter *);
450 static void quiesce_txq(struct adapter *, struct sge_txq *);
451 static void quiesce_wrq(struct adapter *, struct sge_wrq *);
452 static void quiesce_iq(struct adapter *, struct sge_iq *);
453 static void quiesce_fl(struct adapter *, struct sge_fl *);
454 static int t4_alloc_irq(struct adapter *, struct irq *, int rid,
455 driver_intr_t *, void *, char *);
456 static int t4_free_irq(struct adapter *, struct irq *);
457 static void get_regs(struct adapter *, struct t4_regdump *, uint8_t *);
458 static void vi_refresh_stats(struct adapter *, struct vi_info *);
459 static void cxgbe_refresh_stats(struct adapter *, struct port_info *);
460 static void cxgbe_tick(void *);
461 static void cxgbe_vlan_config(void *, struct ifnet *, uint16_t);
462 static void t4_sysctls(struct adapter *);
463 static void cxgbe_sysctls(struct port_info *);
464 static int sysctl_int_array(SYSCTL_HANDLER_ARGS);
465 static int sysctl_bitfield(SYSCTL_HANDLER_ARGS);
466 static int sysctl_btphy(SYSCTL_HANDLER_ARGS);
467 static int sysctl_noflowq(SYSCTL_HANDLER_ARGS);
468 static int sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS);
469 static int sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS);
470 static int sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS);
471 static int sysctl_qsize_txq(SYSCTL_HANDLER_ARGS);
472 static int sysctl_pause_settings(SYSCTL_HANDLER_ARGS);
473 static int sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS);
474 static int sysctl_temperature(SYSCTL_HANDLER_ARGS);
476 static int sysctl_cctrl(SYSCTL_HANDLER_ARGS);
477 static int sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS);
478 static int sysctl_cim_la(SYSCTL_HANDLER_ARGS);
479 static int sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS);
480 static int sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS);
481 static int sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS);
482 static int sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS);
483 static int sysctl_cpl_stats(SYSCTL_HANDLER_ARGS);
484 static int sysctl_ddp_stats(SYSCTL_HANDLER_ARGS);
485 static int sysctl_devlog(SYSCTL_HANDLER_ARGS);
486 static int sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS);
487 static int sysctl_hw_sched(SYSCTL_HANDLER_ARGS);
488 static int sysctl_lb_stats(SYSCTL_HANDLER_ARGS);
489 static int sysctl_linkdnrc(SYSCTL_HANDLER_ARGS);
490 static int sysctl_meminfo(SYSCTL_HANDLER_ARGS);
491 static int sysctl_mps_tcam(SYSCTL_HANDLER_ARGS);
492 static int sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS);
493 static int sysctl_path_mtus(SYSCTL_HANDLER_ARGS);
494 static int sysctl_pm_stats(SYSCTL_HANDLER_ARGS);
495 static int sysctl_rdma_stats(SYSCTL_HANDLER_ARGS);
496 static int sysctl_tcp_stats(SYSCTL_HANDLER_ARGS);
497 static int sysctl_tids(SYSCTL_HANDLER_ARGS);
498 static int sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS);
499 static int sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS);
500 static int sysctl_tp_la(SYSCTL_HANDLER_ARGS);
501 static int sysctl_tx_rate(SYSCTL_HANDLER_ARGS);
502 static int sysctl_ulprx_la(SYSCTL_HANDLER_ARGS);
503 static int sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS);
504 static int sysctl_tc_params(SYSCTL_HANDLER_ARGS);
507 static int sysctl_tp_tick(SYSCTL_HANDLER_ARGS);
508 static int sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS);
509 static int sysctl_tp_timer(SYSCTL_HANDLER_ARGS);
511 static uint32_t fconf_iconf_to_mode(uint32_t, uint32_t);
512 static uint32_t mode_to_fconf(uint32_t);
513 static uint32_t mode_to_iconf(uint32_t);
514 static int check_fspec_against_fconf_iconf(struct adapter *,
515 struct t4_filter_specification *);
516 static int get_filter_mode(struct adapter *, uint32_t *);
517 static int set_filter_mode(struct adapter *, uint32_t);
518 static inline uint64_t get_filter_hits(struct adapter *, uint32_t);
519 static int get_filter(struct adapter *, struct t4_filter *);
520 static int set_filter(struct adapter *, struct t4_filter *);
521 static int del_filter(struct adapter *, struct t4_filter *);
522 static void clear_filter(struct filter_entry *);
523 static int set_filter_wr(struct adapter *, int);
524 static int del_filter_wr(struct adapter *, int);
525 static int set_tcb_rpl(struct sge_iq *, const struct rss_header *,
527 static int get_sge_context(struct adapter *, struct t4_sge_context *);
528 static int load_fw(struct adapter *, struct t4_data *);
529 static int read_card_mem(struct adapter *, int, struct t4_mem_range *);
530 static int read_i2c(struct adapter *, struct t4_i2c_data *);
531 static int set_sched_class(struct adapter *, struct t4_sched_params *);
532 static int set_sched_queue(struct adapter *, struct t4_sched_queue *);
534 static int toe_capability(struct vi_info *, int);
536 static int mod_event(module_t, int, void *);
542 {0xa000, "Chelsio Terminator 4 FPGA"},
543 {0x4400, "Chelsio T440-dbg"},
544 {0x4401, "Chelsio T420-CR"},
545 {0x4402, "Chelsio T422-CR"},
546 {0x4403, "Chelsio T440-CR"},
547 {0x4404, "Chelsio T420-BCH"},
548 {0x4405, "Chelsio T440-BCH"},
549 {0x4406, "Chelsio T440-CH"},
550 {0x4407, "Chelsio T420-SO"},
551 {0x4408, "Chelsio T420-CX"},
552 {0x4409, "Chelsio T420-BT"},
553 {0x440a, "Chelsio T404-BT"},
554 {0x440e, "Chelsio T440-LP-CR"},
556 {0xb000, "Chelsio Terminator 5 FPGA"},
557 {0x5400, "Chelsio T580-dbg"},
558 {0x5401, "Chelsio T520-CR"}, /* 2 x 10G */
559 {0x5402, "Chelsio T522-CR"}, /* 2 x 10G, 2 X 1G */
560 {0x5403, "Chelsio T540-CR"}, /* 4 x 10G */
561 {0x5407, "Chelsio T520-SO"}, /* 2 x 10G, nomem */
562 {0x5409, "Chelsio T520-BT"}, /* 2 x 10GBaseT */
563 {0x540a, "Chelsio T504-BT"}, /* 4 x 1G */
564 {0x540d, "Chelsio T580-CR"}, /* 2 x 40G */
565 {0x540e, "Chelsio T540-LP-CR"}, /* 4 x 10G */
566 {0x5410, "Chelsio T580-LP-CR"}, /* 2 x 40G */
567 {0x5411, "Chelsio T520-LL-CR"}, /* 2 x 10G */
568 {0x5412, "Chelsio T560-CR"}, /* 1 x 40G, 2 x 10G */
569 {0x5414, "Chelsio T580-LP-SO-CR"}, /* 2 x 40G, nomem */
570 {0x5415, "Chelsio T502-BT"}, /* 2 x 1G */
572 {0x5404, "Chelsio T520-BCH"},
573 {0x5405, "Chelsio T540-BCH"},
574 {0x5406, "Chelsio T540-CH"},
575 {0x5408, "Chelsio T520-CX"},
576 {0x540b, "Chelsio B520-SR"},
577 {0x540c, "Chelsio B504-BT"},
578 {0x540f, "Chelsio Amsterdam"},
579 {0x5413, "Chelsio T580-CHR"},
585 * service_iq() has an iq and needs the fl. Offset of fl from the iq should be
586 * exactly the same for both rxq and ofld_rxq.
588 CTASSERT(offsetof(struct sge_ofld_rxq, iq) == offsetof(struct sge_rxq, iq));
589 CTASSERT(offsetof(struct sge_ofld_rxq, fl) == offsetof(struct sge_rxq, fl));
591 CTASSERT(sizeof(struct cluster_metadata) <= CL_METADATA_SIZE);
594 t4_probe(device_t dev)
597 uint16_t v = pci_get_vendor(dev);
598 uint16_t d = pci_get_device(dev);
599 uint8_t f = pci_get_function(dev);
601 if (v != PCI_VENDOR_ID_CHELSIO)
604 /* Attach only to PF0 of the FPGA */
605 if (d == 0xa000 && f != 0)
608 for (i = 0; i < nitems(t4_pciids); i++) {
609 if (d == t4_pciids[i].device) {
610 device_set_desc(dev, t4_pciids[i].desc);
611 return (BUS_PROBE_DEFAULT);
619 t5_probe(device_t dev)
622 uint16_t v = pci_get_vendor(dev);
623 uint16_t d = pci_get_device(dev);
624 uint8_t f = pci_get_function(dev);
626 if (v != PCI_VENDOR_ID_CHELSIO)
629 /* Attach only to PF0 of the FPGA */
630 if (d == 0xb000 && f != 0)
633 for (i = 0; i < nitems(t5_pciids); i++) {
634 if (d == t5_pciids[i].device) {
635 device_set_desc(dev, t5_pciids[i].desc);
636 return (BUS_PROBE_DEFAULT);
644 t5_attribute_workaround(device_t dev)
650 * The T5 chips do not properly echo the No Snoop and Relaxed
651 * Ordering attributes when replying to a TLP from a Root
652 * Port. As a workaround, find the parent Root Port and
653 * disable No Snoop and Relaxed Ordering. Note that this
654 * affects all devices under this root port.
656 root_port = pci_find_pcie_root_port(dev);
657 if (root_port == NULL) {
658 device_printf(dev, "Unable to find parent root port\n");
662 v = pcie_adjust_config(root_port, PCIER_DEVICE_CTL,
663 PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE, 0, 2);
664 if ((v & (PCIEM_CTL_RELAXED_ORD_ENABLE | PCIEM_CTL_NOSNOOP_ENABLE)) !=
666 device_printf(dev, "Disabled No Snoop/Relaxed Ordering on %s\n",
667 device_get_nameunit(root_port));
671 t4_attach(device_t dev)
674 int rc = 0, i, j, n10g, n1g, rqidx, tqidx;
675 struct intrs_and_queues iaq;
679 int ofld_rqidx, ofld_tqidx;
682 int nm_rqidx, nm_tqidx;
686 sc = device_get_softc(dev);
688 TUNABLE_INT_FETCH("hw.cxgbe.debug_flags", &sc->debug_flags);
690 if ((pci_get_device(dev) & 0xff00) == 0x5400)
691 t5_attribute_workaround(dev);
692 pci_enable_busmaster(dev);
693 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
696 pci_set_max_read_req(dev, 4096);
697 v = pci_read_config(dev, i + PCIER_DEVICE_CTL, 2);
698 v |= PCIEM_CTL_RELAXED_ORD_ENABLE;
699 pci_write_config(dev, i + PCIER_DEVICE_CTL, v, 2);
701 sc->params.pci.mps = 128 << ((v & PCIEM_CTL_MAX_PAYLOAD) >> 5);
705 mtx_init(&sc->ifp_lock, sc->ifp_lockname, 0, MTX_DEF);
706 snprintf(sc->ifp_lockname, sizeof(sc->ifp_lockname), "%s tracer",
707 device_get_nameunit(dev));
709 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
710 device_get_nameunit(dev));
711 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
712 sx_xlock(&t4_list_lock);
713 SLIST_INSERT_HEAD(&t4_list, sc, link);
714 sx_xunlock(&t4_list_lock);
716 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
717 TAILQ_INIT(&sc->sfl);
718 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
720 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
722 rc = map_bars_0_and_4(sc);
724 goto done; /* error message displayed already */
727 * This is the real PF# to which we're attaching. Works from within PCI
728 * passthrough environments too, where pci_get_function() could return a
729 * different PF# depending on the passthrough configuration. We need to
730 * use the real PF# in all our communication with the firmware.
732 sc->pf = G_SOURCEPF(t4_read_reg(sc, A_PL_WHOAMI));
735 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
737 /* Prepare the adapter for operation. */
738 buf = malloc(PAGE_SIZE, M_CXGBE, M_ZERO | M_WAITOK);
739 rc = -t4_prep_adapter(sc, buf);
742 device_printf(dev, "failed to prepare adapter: %d.\n", rc);
747 * Do this really early, with the memory windows set up even before the
748 * character device. The userland tool's register i/o and mem read
749 * will work even in "recovery mode".
752 if (t4_init_devlog_params(sc, 0) == 0)
753 fixup_devlog_params(sc);
754 sc->cdev = make_dev(is_t4(sc) ? &t4_cdevsw : &t5_cdevsw,
755 device_get_unit(dev), UID_ROOT, GID_WHEEL, 0600, "%s",
756 device_get_nameunit(dev));
757 if (sc->cdev == NULL)
758 device_printf(dev, "failed to create nexus char device.\n");
760 sc->cdev->si_drv1 = sc;
762 /* Go no further if recovery mode has been requested. */
763 if (TUNABLE_INT_FETCH("hw.cxgbe.sos", &i) && i != 0) {
764 device_printf(dev, "recovery mode.\n");
768 #if defined(__i386__)
769 if ((cpu_feature & CPUID_CX8) == 0) {
770 device_printf(dev, "64 bit atomics not available.\n");
776 /* Prepare the firmware for operation */
777 rc = prep_firmware(sc);
779 goto done; /* error message displayed already */
781 rc = get_params__post_init(sc);
783 goto done; /* error message displayed already */
785 rc = set_params__post_init(sc);
787 goto done; /* error message displayed already */
791 goto done; /* error message displayed already */
793 rc = t4_create_dma_tag(sc);
795 goto done; /* error message displayed already */
798 * Number of VIs to create per-port. The first VI is the "main" regular
799 * VI for the port. The rest are additional virtual interfaces on the
800 * same physical port. Note that the main VI does not have native
801 * netmap support but the extra VIs do.
803 * Limit the number of VIs per port to the number of available
804 * MAC addresses per port.
807 num_vis = t4_num_vis;
810 if (num_vis > nitems(vi_mac_funcs)) {
811 num_vis = nitems(vi_mac_funcs);
812 device_printf(dev, "Number of VIs limited to %d\n", num_vis);
816 * First pass over all the ports - allocate VIs and initialize some
817 * basic parameters like mac address, port type, etc. We also figure
818 * out whether a port is 10G or 1G and use that information when
819 * calculating how many interrupts to attempt to allocate.
822 for_each_port(sc, i) {
823 struct port_info *pi;
825 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
828 /* These must be set before t4_port_init */
832 * XXX: vi[0] is special so we can't delay this allocation until
833 * pi->nvi's final value is known.
835 pi->vi = malloc(sizeof(struct vi_info) * num_vis, M_CXGBE,
839 * Allocate the "main" VI and initialize parameters
842 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
844 device_printf(dev, "unable to initialize port %d: %d\n",
846 free(pi->vi, M_CXGBE);
852 pi->link_cfg.requested_fc &= ~(PAUSE_TX | PAUSE_RX);
853 pi->link_cfg.requested_fc |= t4_pause_settings;
854 pi->link_cfg.fc &= ~(PAUSE_TX | PAUSE_RX);
855 pi->link_cfg.fc |= t4_pause_settings;
857 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, &pi->link_cfg);
859 device_printf(dev, "port %d l1cfg failed: %d\n", i, rc);
860 free(pi->vi, M_CXGBE);
866 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
867 device_get_nameunit(dev), i);
868 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
869 sc->chan_map[pi->tx_chan] = i;
871 pi->tc = malloc(sizeof(struct tx_sched_class) *
872 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
874 if (is_10G_port(pi) || is_40G_port(pi)) {
882 pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbe" : "cxl", -1);
883 if (pi->dev == NULL) {
885 "failed to add device for port %d.\n", i);
889 pi->vi[0].dev = pi->dev;
890 device_set_softc(pi->dev, pi);
894 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
896 rc = cfg_itype_and_nqueues(sc, n10g, n1g, num_vis, &iaq);
898 goto done; /* error message displayed already */
899 if (iaq.nrxq_vi + iaq.nofldrxq_vi + iaq.nnmrxq_vi == 0)
902 sc->intr_type = iaq.intr_type;
903 sc->intr_count = iaq.nirq;
906 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
907 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
909 s->nrxq += (n10g + n1g) * (num_vis - 1) * iaq.nrxq_vi;
910 s->ntxq += (n10g + n1g) * (num_vis - 1) * iaq.ntxq_vi;
912 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
913 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
914 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
916 if (is_offload(sc)) {
917 s->nofldrxq = n10g * iaq.nofldrxq10g + n1g * iaq.nofldrxq1g;
918 s->nofldtxq = n10g * iaq.nofldtxq10g + n1g * iaq.nofldtxq1g;
920 s->nofldrxq += (n10g + n1g) * (num_vis - 1) *
922 s->nofldtxq += (n10g + n1g) * (num_vis - 1) *
925 s->neq += s->nofldtxq + s->nofldrxq;
926 s->niq += s->nofldrxq;
928 s->ofld_rxq = malloc(s->nofldrxq * sizeof(struct sge_ofld_rxq),
929 M_CXGBE, M_ZERO | M_WAITOK);
930 s->ofld_txq = malloc(s->nofldtxq * sizeof(struct sge_wrq),
931 M_CXGBE, M_ZERO | M_WAITOK);
936 s->nnmrxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmrxq_vi;
937 s->nnmtxq = (n10g + n1g) * (num_vis - 1) * iaq.nnmtxq_vi;
939 s->neq += s->nnmtxq + s->nnmrxq;
942 s->nm_rxq = malloc(s->nnmrxq * sizeof(struct sge_nm_rxq),
943 M_CXGBE, M_ZERO | M_WAITOK);
944 s->nm_txq = malloc(s->nnmtxq * sizeof(struct sge_nm_txq),
945 M_CXGBE, M_ZERO | M_WAITOK);
948 s->ctrlq = malloc(sc->params.nports * sizeof(struct sge_wrq), M_CXGBE,
950 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
952 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
954 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
956 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
959 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
962 t4_init_l2t(sc, M_WAITOK);
965 * Second pass over the ports. This time we know the number of rx and
966 * tx queues that each port should get.
970 ofld_rqidx = ofld_tqidx = 0;
973 nm_rqidx = nm_tqidx = 0;
975 for_each_port(sc, i) {
976 struct port_info *pi = sc->port[i];
983 for_each_vi(pi, j, vi) {
985 vi->qsize_rxq = t4_qsize_rxq;
986 vi->qsize_txq = t4_qsize_txq;
988 vi->first_rxq = rqidx;
989 vi->first_txq = tqidx;
990 if (is_10G_port(pi) || is_40G_port(pi)) {
991 vi->tmr_idx = t4_tmr_idx_10g;
992 vi->pktc_idx = t4_pktc_idx_10g;
993 vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
994 vi->nrxq = j == 0 ? iaq.nrxq10g : iaq.nrxq_vi;
995 vi->ntxq = j == 0 ? iaq.ntxq10g : iaq.ntxq_vi;
997 vi->tmr_idx = t4_tmr_idx_1g;
998 vi->pktc_idx = t4_pktc_idx_1g;
999 vi->flags |= iaq.intr_flags_1g & INTR_RXQ;
1000 vi->nrxq = j == 0 ? iaq.nrxq1g : iaq.nrxq_vi;
1001 vi->ntxq = j == 0 ? iaq.ntxq1g : iaq.ntxq_vi;
1006 if (j == 0 && vi->ntxq > 1)
1007 vi->rsrv_noflowq = iaq.rsrv_noflowq ? 1 : 0;
1009 vi->rsrv_noflowq = 0;
1012 vi->first_ofld_rxq = ofld_rqidx;
1013 vi->first_ofld_txq = ofld_tqidx;
1014 if (is_10G_port(pi) || is_40G_port(pi)) {
1015 vi->flags |= iaq.intr_flags_10g & INTR_OFLD_RXQ;
1016 vi->nofldrxq = j == 0 ? iaq.nofldrxq10g :
1018 vi->nofldtxq = j == 0 ? iaq.nofldtxq10g :
1021 vi->flags |= iaq.intr_flags_1g & INTR_OFLD_RXQ;
1022 vi->nofldrxq = j == 0 ? iaq.nofldrxq1g :
1024 vi->nofldtxq = j == 0 ? iaq.nofldtxq1g :
1027 ofld_rqidx += vi->nofldrxq;
1028 ofld_tqidx += vi->nofldtxq;
1032 vi->first_nm_rxq = nm_rqidx;
1033 vi->first_nm_txq = nm_tqidx;
1034 vi->nnmrxq = iaq.nnmrxq_vi;
1035 vi->nnmtxq = iaq.nnmtxq_vi;
1036 nm_rqidx += vi->nnmrxq;
1037 nm_tqidx += vi->nnmtxq;
1043 rc = setup_intr_handlers(sc);
1046 "failed to setup interrupt handlers: %d\n", rc);
1050 rc = bus_generic_attach(dev);
1053 "failed to attach all child ports: %d\n", rc);
1058 "PCIe gen%d x%d, %d ports, %d %s interrupt%s, %d eq, %d iq\n",
1059 sc->params.pci.speed, sc->params.pci.width, sc->params.nports,
1060 sc->intr_count, sc->intr_type == INTR_MSIX ? "MSI-X" :
1061 (sc->intr_type == INTR_MSI ? "MSI" : "INTx"),
1062 sc->intr_count > 1 ? "s" : "", sc->sge.neq, sc->sge.niq);
1067 if (rc != 0 && sc->cdev) {
1068 /* cdev was created and so cxgbetool works; recover that way. */
1070 "error during attach, adapter is now in recovery mode.\n");
1086 t4_detach(device_t dev)
1089 struct port_info *pi;
1092 sc = device_get_softc(dev);
1094 if (sc->flags & FULL_INIT_DONE)
1095 t4_intr_disable(sc);
1098 destroy_dev(sc->cdev);
1102 rc = bus_generic_detach(dev);
1105 "failed to detach child devices: %d\n", rc);
1109 for (i = 0; i < sc->intr_count; i++)
1110 t4_free_irq(sc, &sc->irq[i]);
1112 for (i = 0; i < MAX_NPORTS; i++) {
1115 t4_free_vi(sc, sc->mbox, sc->pf, 0, pi->vi[0].viid);
1117 device_delete_child(dev, pi->dev);
1119 mtx_destroy(&pi->pi_lock);
1120 free(pi->vi, M_CXGBE);
1121 free(pi->tc, M_CXGBE);
1126 if (sc->flags & FULL_INIT_DONE)
1127 adapter_full_uninit(sc);
1129 if (sc->flags & FW_OK)
1130 t4_fw_bye(sc, sc->mbox);
1132 if (sc->intr_type == INTR_MSI || sc->intr_type == INTR_MSIX)
1133 pci_release_msi(dev);
1136 bus_release_resource(dev, SYS_RES_MEMORY, sc->regs_rid,
1140 bus_release_resource(dev, SYS_RES_MEMORY, sc->udbs_rid,
1144 bus_release_resource(dev, SYS_RES_MEMORY, sc->msix_rid,
1148 t4_free_l2t(sc->l2t);
1151 free(sc->sge.ofld_rxq, M_CXGBE);
1152 free(sc->sge.ofld_txq, M_CXGBE);
1155 free(sc->sge.nm_rxq, M_CXGBE);
1156 free(sc->sge.nm_txq, M_CXGBE);
1158 free(sc->irq, M_CXGBE);
1159 free(sc->sge.rxq, M_CXGBE);
1160 free(sc->sge.txq, M_CXGBE);
1161 free(sc->sge.ctrlq, M_CXGBE);
1162 free(sc->sge.iqmap, M_CXGBE);
1163 free(sc->sge.eqmap, M_CXGBE);
1164 free(sc->tids.ftid_tab, M_CXGBE);
1165 t4_destroy_dma_tag(sc);
1166 if (mtx_initialized(&sc->sc_lock)) {
1167 sx_xlock(&t4_list_lock);
1168 SLIST_REMOVE(&t4_list, sc, adapter, link);
1169 sx_xunlock(&t4_list_lock);
1170 mtx_destroy(&sc->sc_lock);
1173 callout_drain(&sc->sfl_callout);
1174 if (mtx_initialized(&sc->tids.ftid_lock))
1175 mtx_destroy(&sc->tids.ftid_lock);
1176 if (mtx_initialized(&sc->sfl_lock))
1177 mtx_destroy(&sc->sfl_lock);
1178 if (mtx_initialized(&sc->ifp_lock))
1179 mtx_destroy(&sc->ifp_lock);
1180 if (mtx_initialized(&sc->reg_lock))
1181 mtx_destroy(&sc->reg_lock);
1183 for (i = 0; i < NUM_MEMWIN; i++) {
1184 struct memwin *mw = &sc->memwin[i];
1186 if (rw_initialized(&mw->mw_lock))
1187 rw_destroy(&mw->mw_lock);
1190 bzero(sc, sizeof(*sc));
1196 cxgbe_probe(device_t dev)
1199 struct port_info *pi = device_get_softc(dev);
1201 snprintf(buf, sizeof(buf), "port %d", pi->port_id);
1202 device_set_desc_copy(dev, buf);
1204 return (BUS_PROBE_DEFAULT);
1207 #define T4_CAP (IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_MTU | IFCAP_HWCSUM | \
1208 IFCAP_VLAN_HWCSUM | IFCAP_TSO | IFCAP_JUMBO_MTU | IFCAP_LRO | \
1209 IFCAP_VLAN_HWTSO | IFCAP_LINKSTATE | IFCAP_HWCSUM_IPV6 | IFCAP_HWSTATS)
1210 #define T4_CAP_ENABLE (T4_CAP)
1213 cxgbe_vi_attach(device_t dev, struct vi_info *vi)
1218 vi->xact_addr_filt = -1;
1219 callout_init(&vi->tick, 1);
1221 /* Allocate an ifnet and set it up */
1222 ifp = if_alloc(IFT_ETHER);
1224 device_printf(dev, "Cannot allocate ifnet\n");
1230 if_initname(ifp, device_get_name(dev), device_get_unit(dev));
1231 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
1233 ifp->if_init = cxgbe_init;
1234 ifp->if_ioctl = cxgbe_ioctl;
1235 ifp->if_transmit = cxgbe_transmit;
1236 ifp->if_qflush = cxgbe_qflush;
1238 ifp->if_capabilities = T4_CAP;
1240 if (vi->nofldrxq != 0)
1241 ifp->if_capabilities |= IFCAP_TOE;
1243 ifp->if_capenable = T4_CAP_ENABLE;
1244 ifp->if_hwassist = CSUM_TCP | CSUM_UDP | CSUM_IP | CSUM_TSO |
1245 CSUM_UDP_IPV6 | CSUM_TCP_IPV6;
1247 ifp->if_hw_tsomax = 65536 - (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN);
1248 ifp->if_hw_tsomaxsegcount = TX_SGL_SEGS;
1249 ifp->if_hw_tsomaxsegsize = 65536;
1251 /* Initialize ifmedia for this VI */
1252 ifmedia_init(&vi->media, IFM_IMASK, cxgbe_media_change,
1253 cxgbe_media_status);
1254 build_medialist(vi->pi, &vi->media);
1256 vi->vlan_c = EVENTHANDLER_REGISTER(vlan_config, cxgbe_vlan_config, ifp,
1257 EVENTHANDLER_PRI_ANY);
1259 ether_ifattach(ifp, vi->hw_addr);
1261 if (vi->nnmrxq != 0)
1262 cxgbe_nm_attach(vi);
1264 sb = sbuf_new_auto();
1265 sbuf_printf(sb, "%d txq, %d rxq (NIC)", vi->ntxq, vi->nrxq);
1267 if (ifp->if_capabilities & IFCAP_TOE)
1268 sbuf_printf(sb, "; %d txq, %d rxq (TOE)",
1269 vi->nofldtxq, vi->nofldrxq);
1272 if (ifp->if_capabilities & IFCAP_NETMAP)
1273 sbuf_printf(sb, "; %d txq, %d rxq (netmap)",
1274 vi->nnmtxq, vi->nnmrxq);
1277 device_printf(dev, "%s\n", sbuf_data(sb));
1286 cxgbe_attach(device_t dev)
1288 struct port_info *pi = device_get_softc(dev);
1292 callout_init_mtx(&pi->tick, &pi->pi_lock, 0);
1294 rc = cxgbe_vi_attach(dev, &pi->vi[0]);
1298 for_each_vi(pi, i, vi) {
1301 vi->dev = device_add_child(dev, is_t4(pi->adapter) ?
1302 "vcxgbe" : "vcxl", -1);
1303 if (vi->dev == NULL) {
1304 device_printf(dev, "failed to add VI %d\n", i);
1307 device_set_softc(vi->dev, vi);
1312 bus_generic_attach(dev);
1318 cxgbe_vi_detach(struct vi_info *vi)
1320 struct ifnet *ifp = vi->ifp;
1322 ether_ifdetach(ifp);
1325 EVENTHANDLER_DEREGISTER(vlan_config, vi->vlan_c);
1327 /* Let detach proceed even if these fail. */
1329 if (ifp->if_capabilities & IFCAP_NETMAP)
1330 cxgbe_nm_detach(vi);
1332 cxgbe_uninit_synchronized(vi);
1333 callout_drain(&vi->tick);
1336 ifmedia_removeall(&vi->media);
1342 cxgbe_detach(device_t dev)
1344 struct port_info *pi = device_get_softc(dev);
1345 struct adapter *sc = pi->adapter;
1348 /* Detach the extra VIs first. */
1349 rc = bus_generic_detach(dev);
1352 device_delete_children(dev);
1354 doom_vi(sc, &pi->vi[0]);
1356 if (pi->flags & HAS_TRACEQ) {
1357 sc->traceq = -1; /* cloner should not create ifnet */
1358 t4_tracer_port_detach(sc);
1361 cxgbe_vi_detach(&pi->vi[0]);
1362 callout_drain(&pi->tick);
1364 end_synchronized_op(sc, 0);
1370 cxgbe_init(void *arg)
1372 struct vi_info *vi = arg;
1373 struct adapter *sc = vi->pi->adapter;
1375 if (begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4init") != 0)
1377 cxgbe_init_synchronized(vi);
1378 end_synchronized_op(sc, 0);
1382 cxgbe_ioctl(struct ifnet *ifp, unsigned long cmd, caddr_t data)
1384 int rc = 0, mtu, flags, can_sleep;
1385 struct vi_info *vi = ifp->if_softc;
1386 struct adapter *sc = vi->pi->adapter;
1387 struct ifreq *ifr = (struct ifreq *)data;
1393 if ((mtu < ETHERMIN) || (mtu > ETHERMTU_JUMBO))
1396 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4mtu");
1400 if (vi->flags & VI_INIT_DONE) {
1401 t4_update_fl_bufsize(ifp);
1402 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1403 rc = update_mac_settings(ifp, XGMAC_MTU);
1405 end_synchronized_op(sc, 0);
1411 rc = begin_synchronized_op(sc, vi,
1412 can_sleep ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4flg");
1416 if (ifp->if_flags & IFF_UP) {
1417 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1418 flags = vi->if_flags;
1419 if ((ifp->if_flags ^ flags) &
1420 (IFF_PROMISC | IFF_ALLMULTI)) {
1421 if (can_sleep == 1) {
1422 end_synchronized_op(sc, 0);
1426 rc = update_mac_settings(ifp,
1427 XGMAC_PROMISC | XGMAC_ALLMULTI);
1430 if (can_sleep == 0) {
1431 end_synchronized_op(sc, LOCK_HELD);
1435 rc = cxgbe_init_synchronized(vi);
1437 vi->if_flags = ifp->if_flags;
1438 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1439 if (can_sleep == 0) {
1440 end_synchronized_op(sc, LOCK_HELD);
1444 rc = cxgbe_uninit_synchronized(vi);
1446 end_synchronized_op(sc, can_sleep ? 0 : LOCK_HELD);
1450 case SIOCDELMULTI: /* these two are called with a mutex held :-( */
1451 rc = begin_synchronized_op(sc, vi, HOLD_LOCK, "t4multi");
1454 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1455 rc = update_mac_settings(ifp, XGMAC_MCADDRS);
1456 end_synchronized_op(sc, LOCK_HELD);
1460 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4cap");
1464 mask = ifr->ifr_reqcap ^ ifp->if_capenable;
1465 if (mask & IFCAP_TXCSUM) {
1466 ifp->if_capenable ^= IFCAP_TXCSUM;
1467 ifp->if_hwassist ^= (CSUM_TCP | CSUM_UDP | CSUM_IP);
1469 if (IFCAP_TSO4 & ifp->if_capenable &&
1470 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1471 ifp->if_capenable &= ~IFCAP_TSO4;
1473 "tso4 disabled due to -txcsum.\n");
1476 if (mask & IFCAP_TXCSUM_IPV6) {
1477 ifp->if_capenable ^= IFCAP_TXCSUM_IPV6;
1478 ifp->if_hwassist ^= (CSUM_UDP_IPV6 | CSUM_TCP_IPV6);
1480 if (IFCAP_TSO6 & ifp->if_capenable &&
1481 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1482 ifp->if_capenable &= ~IFCAP_TSO6;
1484 "tso6 disabled due to -txcsum6.\n");
1487 if (mask & IFCAP_RXCSUM)
1488 ifp->if_capenable ^= IFCAP_RXCSUM;
1489 if (mask & IFCAP_RXCSUM_IPV6)
1490 ifp->if_capenable ^= IFCAP_RXCSUM_IPV6;
1493 * Note that we leave CSUM_TSO alone (it is always set). The
1494 * kernel takes both IFCAP_TSOx and CSUM_TSO into account before
1495 * sending a TSO request our way, so it's sufficient to toggle
1498 if (mask & IFCAP_TSO4) {
1499 if (!(IFCAP_TSO4 & ifp->if_capenable) &&
1500 !(IFCAP_TXCSUM & ifp->if_capenable)) {
1501 if_printf(ifp, "enable txcsum first.\n");
1505 ifp->if_capenable ^= IFCAP_TSO4;
1507 if (mask & IFCAP_TSO6) {
1508 if (!(IFCAP_TSO6 & ifp->if_capenable) &&
1509 !(IFCAP_TXCSUM_IPV6 & ifp->if_capenable)) {
1510 if_printf(ifp, "enable txcsum6 first.\n");
1514 ifp->if_capenable ^= IFCAP_TSO6;
1516 if (mask & IFCAP_LRO) {
1517 #if defined(INET) || defined(INET6)
1519 struct sge_rxq *rxq;
1521 ifp->if_capenable ^= IFCAP_LRO;
1522 for_each_rxq(vi, i, rxq) {
1523 if (ifp->if_capenable & IFCAP_LRO)
1524 rxq->iq.flags |= IQ_LRO_ENABLED;
1526 rxq->iq.flags &= ~IQ_LRO_ENABLED;
1531 if (mask & IFCAP_TOE) {
1532 int enable = (ifp->if_capenable ^ mask) & IFCAP_TOE;
1534 rc = toe_capability(vi, enable);
1538 ifp->if_capenable ^= mask;
1541 if (mask & IFCAP_VLAN_HWTAGGING) {
1542 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
1543 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1544 rc = update_mac_settings(ifp, XGMAC_VLANEX);
1546 if (mask & IFCAP_VLAN_MTU) {
1547 ifp->if_capenable ^= IFCAP_VLAN_MTU;
1549 /* Need to find out how to disable auto-mtu-inflation */
1551 if (mask & IFCAP_VLAN_HWTSO)
1552 ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
1553 if (mask & IFCAP_VLAN_HWCSUM)
1554 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
1556 #ifdef VLAN_CAPABILITIES
1557 VLAN_CAPABILITIES(ifp);
1560 end_synchronized_op(sc, 0);
1565 ifmedia_ioctl(ifp, ifr, &vi->media, cmd);
1569 struct ifi2creq i2c;
1571 rc = copyin(ifr->ifr_data, &i2c, sizeof(i2c));
1574 if (i2c.dev_addr != 0xA0 && i2c.dev_addr != 0xA2) {
1578 if (i2c.len > sizeof(i2c.data)) {
1582 rc = begin_synchronized_op(sc, vi, SLEEP_OK | INTR_OK, "t4i2c");
1585 rc = -t4_i2c_rd(sc, sc->mbox, vi->pi->port_id, i2c.dev_addr,
1586 i2c.offset, i2c.len, &i2c.data[0]);
1587 end_synchronized_op(sc, 0);
1589 rc = copyout(&i2c, ifr->ifr_data, sizeof(i2c));
1594 rc = ether_ioctl(ifp, cmd, data);
1601 cxgbe_transmit(struct ifnet *ifp, struct mbuf *m)
1603 struct vi_info *vi = ifp->if_softc;
1604 struct port_info *pi = vi->pi;
1605 struct adapter *sc = pi->adapter;
1606 struct sge_txq *txq;
1611 MPASS(m->m_nextpkt == NULL); /* not quite ready for this yet */
1613 if (__predict_false(pi->link_cfg.link_ok == 0)) {
1619 if (__predict_false(rc != 0)) {
1620 MPASS(m == NULL); /* was freed already */
1621 atomic_add_int(&pi->tx_parse_error, 1); /* rare, atomic is ok */
1626 txq = &sc->sge.txq[vi->first_txq];
1627 if (M_HASHTYPE_GET(m) != M_HASHTYPE_NONE)
1628 txq += ((m->m_pkthdr.flowid % (vi->ntxq - vi->rsrv_noflowq)) +
1632 rc = mp_ring_enqueue(txq->r, items, 1, 4096);
1633 if (__predict_false(rc != 0))
1640 cxgbe_qflush(struct ifnet *ifp)
1642 struct vi_info *vi = ifp->if_softc;
1643 struct sge_txq *txq;
1646 /* queues do not exist if !VI_INIT_DONE. */
1647 if (vi->flags & VI_INIT_DONE) {
1648 for_each_txq(vi, i, txq) {
1650 txq->eq.flags &= ~EQ_ENABLED;
1652 while (!mp_ring_is_idle(txq->r)) {
1653 mp_ring_check_drainage(txq->r, 0);
1662 cxgbe_media_change(struct ifnet *ifp)
1664 struct vi_info *vi = ifp->if_softc;
1666 device_printf(vi->dev, "%s unimplemented.\n", __func__);
1668 return (EOPNOTSUPP);
1672 cxgbe_media_status(struct ifnet *ifp, struct ifmediareq *ifmr)
1674 struct vi_info *vi = ifp->if_softc;
1675 struct port_info *pi = vi->pi;
1676 struct ifmedia_entry *cur;
1677 int speed = pi->link_cfg.speed;
1679 cur = vi->media.ifm_cur;
1681 ifmr->ifm_status = IFM_AVALID;
1682 if (!pi->link_cfg.link_ok)
1685 ifmr->ifm_status |= IFM_ACTIVE;
1687 /* active and current will differ iff current media is autoselect. */
1688 if (IFM_SUBTYPE(cur->ifm_media) != IFM_AUTO)
1691 ifmr->ifm_active = IFM_ETHER | IFM_FDX;
1693 ifmr->ifm_active |= IFM_10G_T;
1694 else if (speed == 1000)
1695 ifmr->ifm_active |= IFM_1000_T;
1696 else if (speed == 100)
1697 ifmr->ifm_active |= IFM_100_TX;
1698 else if (speed == 10)
1699 ifmr->ifm_active |= IFM_10_T;
1701 KASSERT(0, ("%s: link up but speed unknown (%u)", __func__,
1706 vcxgbe_probe(device_t dev)
1709 struct vi_info *vi = device_get_softc(dev);
1711 snprintf(buf, sizeof(buf), "port %d vi %td", vi->pi->port_id,
1713 device_set_desc_copy(dev, buf);
1715 return (BUS_PROBE_DEFAULT);
1719 vcxgbe_attach(device_t dev)
1722 struct port_info *pi;
1724 int func, index, rc;
1727 vi = device_get_softc(dev);
1731 index = vi - pi->vi;
1732 KASSERT(index < nitems(vi_mac_funcs),
1733 ("%s: VI %s doesn't have a MAC func", __func__,
1734 device_get_nameunit(dev)));
1735 func = vi_mac_funcs[index];
1736 rc = t4_alloc_vi_func(sc, sc->mbox, pi->tx_chan, sc->pf, 0, 1,
1737 vi->hw_addr, &vi->rss_size, func, 0);
1739 device_printf(dev, "Failed to allocate virtual interface "
1740 "for port %d: %d\n", pi->port_id, -rc);
1745 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
1746 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_RSSINFO) |
1747 V_FW_PARAMS_PARAM_YZ(vi->viid);
1748 rc = t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
1750 vi->rss_base = 0xffff;
1752 /* MPASS((val >> 16) == rss_size); */
1753 vi->rss_base = val & 0xffff;
1756 rc = cxgbe_vi_attach(dev, vi);
1758 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1765 vcxgbe_detach(device_t dev)
1770 vi = device_get_softc(dev);
1771 sc = vi->pi->adapter;
1775 cxgbe_vi_detach(vi);
1776 t4_free_vi(sc, sc->mbox, sc->pf, 0, vi->viid);
1778 end_synchronized_op(sc, 0);
1784 t4_fatal_err(struct adapter *sc)
1786 t4_set_reg_field(sc, A_SGE_CONTROL, F_GLOBALENABLE, 0);
1787 t4_intr_disable(sc);
1788 log(LOG_EMERG, "%s: encountered fatal error, adapter stopped.\n",
1789 device_get_nameunit(sc->dev));
1793 map_bars_0_and_4(struct adapter *sc)
1795 sc->regs_rid = PCIR_BAR(0);
1796 sc->regs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1797 &sc->regs_rid, RF_ACTIVE);
1798 if (sc->regs_res == NULL) {
1799 device_printf(sc->dev, "cannot map registers.\n");
1802 sc->bt = rman_get_bustag(sc->regs_res);
1803 sc->bh = rman_get_bushandle(sc->regs_res);
1804 sc->mmio_len = rman_get_size(sc->regs_res);
1805 setbit(&sc->doorbells, DOORBELL_KDB);
1807 sc->msix_rid = PCIR_BAR(4);
1808 sc->msix_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1809 &sc->msix_rid, RF_ACTIVE);
1810 if (sc->msix_res == NULL) {
1811 device_printf(sc->dev, "cannot map MSI-X BAR.\n");
1819 map_bar_2(struct adapter *sc)
1823 * T4: only iWARP driver uses the userspace doorbells. There is no need
1824 * to map it if RDMA is disabled.
1826 if (is_t4(sc) && sc->rdmacaps == 0)
1829 sc->udbs_rid = PCIR_BAR(2);
1830 sc->udbs_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
1831 &sc->udbs_rid, RF_ACTIVE);
1832 if (sc->udbs_res == NULL) {
1833 device_printf(sc->dev, "cannot map doorbell BAR.\n");
1836 sc->udbs_base = rman_get_virtual(sc->udbs_res);
1839 setbit(&sc->doorbells, DOORBELL_UDB);
1840 #if defined(__i386__) || defined(__amd64__)
1841 if (t5_write_combine) {
1845 * Enable write combining on BAR2. This is the
1846 * userspace doorbell BAR and is split into 128B
1847 * (UDBS_SEG_SIZE) doorbell regions, each associated
1848 * with an egress queue. The first 64B has the doorbell
1849 * and the second 64B can be used to submit a tx work
1850 * request with an implicit doorbell.
1853 rc = pmap_change_attr((vm_offset_t)sc->udbs_base,
1854 rman_get_size(sc->udbs_res), PAT_WRITE_COMBINING);
1856 clrbit(&sc->doorbells, DOORBELL_UDB);
1857 setbit(&sc->doorbells, DOORBELL_WCWR);
1858 setbit(&sc->doorbells, DOORBELL_UDBWC);
1860 device_printf(sc->dev,
1861 "couldn't enable write combining: %d\n",
1865 t4_write_reg(sc, A_SGE_STAT_CFG,
1866 V_STATSOURCE_T5(7) | V_STATMODE(0));
1874 struct memwin_init {
1879 static const struct memwin_init t4_memwin[NUM_MEMWIN] = {
1880 { MEMWIN0_BASE, MEMWIN0_APERTURE },
1881 { MEMWIN1_BASE, MEMWIN1_APERTURE },
1882 { MEMWIN2_BASE_T4, MEMWIN2_APERTURE_T4 }
1885 static const struct memwin_init t5_memwin[NUM_MEMWIN] = {
1886 { MEMWIN0_BASE, MEMWIN0_APERTURE },
1887 { MEMWIN1_BASE, MEMWIN1_APERTURE },
1888 { MEMWIN2_BASE_T5, MEMWIN2_APERTURE_T5 },
1892 setup_memwin(struct adapter *sc)
1894 const struct memwin_init *mw_init;
1901 * Read low 32b of bar0 indirectly via the hardware backdoor
1902 * mechanism. Works from within PCI passthrough environments
1903 * too, where rman_get_start() can return a different value. We
1904 * need to program the T4 memory window decoders with the actual
1905 * addresses that will be coming across the PCIe link.
1907 bar0 = t4_hw_pci_read_cfg4(sc, PCIR_BAR(0));
1908 bar0 &= (uint32_t) PCIM_BAR_MEM_BASE;
1910 mw_init = &t4_memwin[0];
1912 /* T5+ use the relative offset inside the PCIe BAR */
1915 mw_init = &t5_memwin[0];
1918 for (i = 0, mw = &sc->memwin[0]; i < NUM_MEMWIN; i++, mw_init++, mw++) {
1919 rw_init(&mw->mw_lock, "memory window access");
1920 mw->mw_base = mw_init->base;
1921 mw->mw_aperture = mw_init->aperture;
1924 PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, i),
1925 (mw->mw_base + bar0) | V_BIR(0) |
1926 V_WINDOW(ilog2(mw->mw_aperture) - 10));
1927 rw_wlock(&mw->mw_lock);
1928 position_memwin(sc, i, 0);
1929 rw_wunlock(&mw->mw_lock);
1933 t4_read_reg(sc, PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_BASE_WIN, 2));
1937 * Positions the memory window at the given address in the card's address space.
1938 * There are some alignment requirements and the actual position may be at an
1939 * address prior to the requested address. mw->mw_curpos always has the actual
1940 * position of the window.
1943 position_memwin(struct adapter *sc, int idx, uint32_t addr)
1949 MPASS(idx >= 0 && idx < NUM_MEMWIN);
1950 mw = &sc->memwin[idx];
1951 rw_assert(&mw->mw_lock, RA_WLOCKED);
1955 mw->mw_curpos = addr & ~0xf; /* start must be 16B aligned */
1957 pf = V_PFNUM(sc->pf);
1958 mw->mw_curpos = addr & ~0x7f; /* start must be 128B aligned */
1960 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, idx);
1961 t4_write_reg(sc, reg, mw->mw_curpos | pf);
1962 t4_read_reg(sc, reg); /* flush */
1966 rw_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
1972 MPASS(idx >= 0 && idx < NUM_MEMWIN);
1974 /* Memory can only be accessed in naturally aligned 4 byte units */
1975 if (addr & 3 || len & 3 || len <= 0)
1978 mw = &sc->memwin[idx];
1980 rw_rlock(&mw->mw_lock);
1981 mw_end = mw->mw_curpos + mw->mw_aperture;
1982 if (addr >= mw_end || addr < mw->mw_curpos) {
1983 /* Will need to reposition the window */
1984 if (!rw_try_upgrade(&mw->mw_lock)) {
1985 rw_runlock(&mw->mw_lock);
1986 rw_wlock(&mw->mw_lock);
1988 rw_assert(&mw->mw_lock, RA_WLOCKED);
1989 position_memwin(sc, idx, addr);
1990 rw_downgrade(&mw->mw_lock);
1991 mw_end = mw->mw_curpos + mw->mw_aperture;
1993 rw_assert(&mw->mw_lock, RA_RLOCKED);
1994 while (addr < mw_end && len > 0) {
1996 v = t4_read_reg(sc, mw->mw_base + addr -
1998 *val++ = le32toh(v);
2001 t4_write_reg(sc, mw->mw_base + addr -
2002 mw->mw_curpos, htole32(v));;
2007 rw_runlock(&mw->mw_lock);
2014 read_via_memwin(struct adapter *sc, int idx, uint32_t addr, uint32_t *val,
2018 return (rw_via_memwin(sc, idx, addr, val, len, 0));
2022 write_via_memwin(struct adapter *sc, int idx, uint32_t addr,
2023 const uint32_t *val, int len)
2026 return (rw_via_memwin(sc, idx, addr, (void *)(uintptr_t)val, len, 1));
2030 t4_range_cmp(const void *a, const void *b)
2032 return ((const struct t4_range *)a)->start -
2033 ((const struct t4_range *)b)->start;
2037 * Verify that the memory range specified by the addr/len pair is valid within
2038 * the card's address space.
2041 validate_mem_range(struct adapter *sc, uint32_t addr, int len)
2043 struct t4_range mem_ranges[4], *r, *next;
2044 uint32_t em, addr_len;
2045 int i, n, remaining;
2047 /* Memory can only be accessed in naturally aligned 4 byte units */
2048 if (addr & 3 || len & 3 || len <= 0)
2051 /* Enabled memories */
2052 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2056 bzero(r, sizeof(mem_ranges));
2057 if (em & F_EDRAM0_ENABLE) {
2058 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2059 r->size = G_EDRAM0_SIZE(addr_len) << 20;
2061 r->start = G_EDRAM0_BASE(addr_len) << 20;
2062 if (addr >= r->start &&
2063 addr + len <= r->start + r->size)
2069 if (em & F_EDRAM1_ENABLE) {
2070 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2071 r->size = G_EDRAM1_SIZE(addr_len) << 20;
2073 r->start = G_EDRAM1_BASE(addr_len) << 20;
2074 if (addr >= r->start &&
2075 addr + len <= r->start + r->size)
2081 if (em & F_EXT_MEM_ENABLE) {
2082 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2083 r->size = G_EXT_MEM_SIZE(addr_len) << 20;
2085 r->start = G_EXT_MEM_BASE(addr_len) << 20;
2086 if (addr >= r->start &&
2087 addr + len <= r->start + r->size)
2093 if (is_t5(sc) && em & F_EXT_MEM1_ENABLE) {
2094 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2095 r->size = G_EXT_MEM1_SIZE(addr_len) << 20;
2097 r->start = G_EXT_MEM1_BASE(addr_len) << 20;
2098 if (addr >= r->start &&
2099 addr + len <= r->start + r->size)
2105 MPASS(n <= nitems(mem_ranges));
2108 /* Sort and merge the ranges. */
2109 qsort(mem_ranges, n, sizeof(struct t4_range), t4_range_cmp);
2111 /* Start from index 0 and examine the next n - 1 entries. */
2113 for (remaining = n - 1; remaining > 0; remaining--, r++) {
2115 MPASS(r->size > 0); /* r is a valid entry. */
2117 MPASS(next->size > 0); /* and so is the next one. */
2119 while (r->start + r->size >= next->start) {
2120 /* Merge the next one into the current entry. */
2121 r->size = max(r->start + r->size,
2122 next->start + next->size) - r->start;
2123 n--; /* One fewer entry in total. */
2124 if (--remaining == 0)
2125 goto done; /* short circuit */
2128 if (next != r + 1) {
2130 * Some entries were merged into r and next
2131 * points to the first valid entry that couldn't
2134 MPASS(next->size > 0); /* must be valid */
2135 memcpy(r + 1, next, remaining * sizeof(*r));
2138 * This so that the foo->size assertion in the
2139 * next iteration of the loop do the right
2140 * thing for entries that were pulled up and are
2143 MPASS(n < nitems(mem_ranges));
2144 bzero(&mem_ranges[n], (nitems(mem_ranges) - n) *
2145 sizeof(struct t4_range));
2150 /* Done merging the ranges. */
2153 for (i = 0; i < n; i++, r++) {
2154 if (addr >= r->start &&
2155 addr + len <= r->start + r->size)
2164 fwmtype_to_hwmtype(int mtype)
2168 case FW_MEMTYPE_EDC0:
2170 case FW_MEMTYPE_EDC1:
2172 case FW_MEMTYPE_EXTMEM:
2174 case FW_MEMTYPE_EXTMEM1:
2177 panic("%s: cannot translate fw mtype %d.", __func__, mtype);
2182 * Verify that the memory range specified by the memtype/offset/len pair is
2183 * valid and lies entirely within the memtype specified. The global address of
2184 * the start of the range is returned in addr.
2187 validate_mt_off_len(struct adapter *sc, int mtype, uint32_t off, int len,
2190 uint32_t em, addr_len, maddr;
2192 /* Memory can only be accessed in naturally aligned 4 byte units */
2193 if (off & 3 || len & 3 || len == 0)
2196 em = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
2197 switch (fwmtype_to_hwmtype(mtype)) {
2199 if (!(em & F_EDRAM0_ENABLE))
2201 addr_len = t4_read_reg(sc, A_MA_EDRAM0_BAR);
2202 maddr = G_EDRAM0_BASE(addr_len) << 20;
2205 if (!(em & F_EDRAM1_ENABLE))
2207 addr_len = t4_read_reg(sc, A_MA_EDRAM1_BAR);
2208 maddr = G_EDRAM1_BASE(addr_len) << 20;
2211 if (!(em & F_EXT_MEM_ENABLE))
2213 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
2214 maddr = G_EXT_MEM_BASE(addr_len) << 20;
2217 if (!is_t5(sc) || !(em & F_EXT_MEM1_ENABLE))
2219 addr_len = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
2220 maddr = G_EXT_MEM1_BASE(addr_len) << 20;
2226 *addr = maddr + off; /* global address */
2227 return (validate_mem_range(sc, *addr, len));
2231 fixup_devlog_params(struct adapter *sc)
2233 struct devlog_params *dparams = &sc->params.devlog;
2236 rc = validate_mt_off_len(sc, dparams->memtype, dparams->start,
2237 dparams->size, &dparams->addr);
2243 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g, int num_vis,
2244 struct intrs_and_queues *iaq)
2246 int rc, itype, navail, nrxq10g, nrxq1g, n;
2247 int nofldrxq10g = 0, nofldrxq1g = 0;
2249 bzero(iaq, sizeof(*iaq));
2251 iaq->ntxq10g = t4_ntxq10g;
2252 iaq->ntxq1g = t4_ntxq1g;
2253 iaq->ntxq_vi = t4_ntxq_vi;
2254 iaq->nrxq10g = nrxq10g = t4_nrxq10g;
2255 iaq->nrxq1g = nrxq1g = t4_nrxq1g;
2256 iaq->nrxq_vi = t4_nrxq_vi;
2257 iaq->rsrv_noflowq = t4_rsrv_noflowq;
2259 if (is_offload(sc)) {
2260 iaq->nofldtxq10g = t4_nofldtxq10g;
2261 iaq->nofldtxq1g = t4_nofldtxq1g;
2262 iaq->nofldtxq_vi = t4_nofldtxq_vi;
2263 iaq->nofldrxq10g = nofldrxq10g = t4_nofldrxq10g;
2264 iaq->nofldrxq1g = nofldrxq1g = t4_nofldrxq1g;
2265 iaq->nofldrxq_vi = t4_nofldrxq_vi;
2269 iaq->nnmtxq_vi = t4_nnmtxq_vi;
2270 iaq->nnmrxq_vi = t4_nnmrxq_vi;
2273 for (itype = INTR_MSIX; itype; itype >>= 1) {
2275 if ((itype & t4_intr_types) == 0)
2276 continue; /* not allowed */
2278 if (itype == INTR_MSIX)
2279 navail = pci_msix_count(sc->dev);
2280 else if (itype == INTR_MSI)
2281 navail = pci_msi_count(sc->dev);
2288 iaq->intr_type = itype;
2289 iaq->intr_flags_10g = 0;
2290 iaq->intr_flags_1g = 0;
2293 * Best option: an interrupt vector for errors, one for the
2294 * firmware event queue, and one for every rxq (NIC and TOE) of
2295 * every VI. The VIs that support netmap use the same
2296 * interrupts for the NIC rx queues and the netmap rx queues
2297 * because only one set of queues is active at a time.
2299 iaq->nirq = T4_EXTRA_INTR;
2300 iaq->nirq += n10g * (nrxq10g + nofldrxq10g);
2301 iaq->nirq += n1g * (nrxq1g + nofldrxq1g);
2302 iaq->nirq += (n10g + n1g) * (num_vis - 1) *
2303 max(iaq->nrxq_vi, iaq->nnmrxq_vi); /* See comment above. */
2304 iaq->nirq += (n10g + n1g) * (num_vis - 1) * iaq->nofldrxq_vi;
2305 if (iaq->nirq <= navail &&
2306 (itype != INTR_MSI || powerof2(iaq->nirq))) {
2307 iaq->intr_flags_10g = INTR_ALL;
2308 iaq->intr_flags_1g = INTR_ALL;
2312 /* Disable the VIs (and netmap) if there aren't enough intrs */
2314 device_printf(sc->dev, "virtual interfaces disabled "
2315 "because num_vis=%u with current settings "
2316 "(nrxq10g=%u, nrxq1g=%u, nofldrxq10g=%u, "
2317 "nofldrxq1g=%u, nrxq_vi=%u nofldrxq_vi=%u, "
2318 "nnmrxq_vi=%u) would need %u interrupts but "
2319 "only %u are available.\n", num_vis, nrxq10g,
2320 nrxq1g, nofldrxq10g, nofldrxq1g, iaq->nrxq_vi,
2321 iaq->nofldrxq_vi, iaq->nnmrxq_vi, iaq->nirq,
2324 iaq->ntxq_vi = iaq->nrxq_vi = 0;
2325 iaq->nofldtxq_vi = iaq->nofldrxq_vi = 0;
2326 iaq->nnmtxq_vi = iaq->nnmrxq_vi = 0;
2331 * Second best option: a vector for errors, one for the firmware
2332 * event queue, and vectors for either all the NIC rx queues or
2333 * all the TOE rx queues. The queues that don't get vectors
2334 * will forward their interrupts to those that do.
2336 iaq->nirq = T4_EXTRA_INTR;
2337 if (nrxq10g >= nofldrxq10g) {
2338 iaq->intr_flags_10g = INTR_RXQ;
2339 iaq->nirq += n10g * nrxq10g;
2341 iaq->intr_flags_10g = INTR_OFLD_RXQ;
2342 iaq->nirq += n10g * nofldrxq10g;
2344 if (nrxq1g >= nofldrxq1g) {
2345 iaq->intr_flags_1g = INTR_RXQ;
2346 iaq->nirq += n1g * nrxq1g;
2348 iaq->intr_flags_1g = INTR_OFLD_RXQ;
2349 iaq->nirq += n1g * nofldrxq1g;
2351 if (iaq->nirq <= navail &&
2352 (itype != INTR_MSI || powerof2(iaq->nirq)))
2356 * Next best option: an interrupt vector for errors, one for the
2357 * firmware event queue, and at least one per main-VI. At this
2358 * point we know we'll have to downsize nrxq and/or nofldrxq to
2359 * fit what's available to us.
2361 iaq->nirq = T4_EXTRA_INTR;
2362 iaq->nirq += n10g + n1g;
2363 if (iaq->nirq <= navail) {
2364 int leftover = navail - iaq->nirq;
2367 int target = max(nrxq10g, nofldrxq10g);
2369 iaq->intr_flags_10g = nrxq10g >= nofldrxq10g ?
2370 INTR_RXQ : INTR_OFLD_RXQ;
2373 while (n < target && leftover >= n10g) {
2378 iaq->nrxq10g = min(n, nrxq10g);
2380 iaq->nofldrxq10g = min(n, nofldrxq10g);
2385 int target = max(nrxq1g, nofldrxq1g);
2387 iaq->intr_flags_1g = nrxq1g >= nofldrxq1g ?
2388 INTR_RXQ : INTR_OFLD_RXQ;
2391 while (n < target && leftover >= n1g) {
2396 iaq->nrxq1g = min(n, nrxq1g);
2398 iaq->nofldrxq1g = min(n, nofldrxq1g);
2402 if (itype != INTR_MSI || powerof2(iaq->nirq))
2407 * Least desirable option: one interrupt vector for everything.
2409 iaq->nirq = iaq->nrxq10g = iaq->nrxq1g = 1;
2410 iaq->intr_flags_10g = iaq->intr_flags_1g = 0;
2413 iaq->nofldrxq10g = iaq->nofldrxq1g = 1;
2418 if (itype == INTR_MSIX)
2419 rc = pci_alloc_msix(sc->dev, &navail);
2420 else if (itype == INTR_MSI)
2421 rc = pci_alloc_msi(sc->dev, &navail);
2424 if (navail == iaq->nirq)
2428 * Didn't get the number requested. Use whatever number
2429 * the kernel is willing to allocate (it's in navail).
2431 device_printf(sc->dev, "fewer vectors than requested, "
2432 "type=%d, req=%d, rcvd=%d; will downshift req.\n",
2433 itype, iaq->nirq, navail);
2434 pci_release_msi(sc->dev);
2438 device_printf(sc->dev,
2439 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
2440 itype, rc, iaq->nirq, navail);
2443 device_printf(sc->dev,
2444 "failed to find a usable interrupt type. "
2445 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
2446 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
2451 #define FW_VERSION(chip) ( \
2452 V_FW_HDR_FW_VER_MAJOR(chip##FW_VERSION_MAJOR) | \
2453 V_FW_HDR_FW_VER_MINOR(chip##FW_VERSION_MINOR) | \
2454 V_FW_HDR_FW_VER_MICRO(chip##FW_VERSION_MICRO) | \
2455 V_FW_HDR_FW_VER_BUILD(chip##FW_VERSION_BUILD))
2456 #define FW_INTFVER(chip, intf) (chip##FW_HDR_INTFVER_##intf)
2462 struct fw_hdr fw_hdr; /* XXX: waste of space, need a sparse struct */
2466 .kld_name = "t4fw_cfg",
2467 .fw_mod_name = "t4fw",
2469 .chip = FW_HDR_CHIP_T4,
2470 .fw_ver = htobe32_const(FW_VERSION(T4)),
2471 .intfver_nic = FW_INTFVER(T4, NIC),
2472 .intfver_vnic = FW_INTFVER(T4, VNIC),
2473 .intfver_ofld = FW_INTFVER(T4, OFLD),
2474 .intfver_ri = FW_INTFVER(T4, RI),
2475 .intfver_iscsipdu = FW_INTFVER(T4, ISCSIPDU),
2476 .intfver_iscsi = FW_INTFVER(T4, ISCSI),
2477 .intfver_fcoepdu = FW_INTFVER(T4, FCOEPDU),
2478 .intfver_fcoe = FW_INTFVER(T4, FCOE),
2482 .kld_name = "t5fw_cfg",
2483 .fw_mod_name = "t5fw",
2485 .chip = FW_HDR_CHIP_T5,
2486 .fw_ver = htobe32_const(FW_VERSION(T5)),
2487 .intfver_nic = FW_INTFVER(T5, NIC),
2488 .intfver_vnic = FW_INTFVER(T5, VNIC),
2489 .intfver_ofld = FW_INTFVER(T5, OFLD),
2490 .intfver_ri = FW_INTFVER(T5, RI),
2491 .intfver_iscsipdu = FW_INTFVER(T5, ISCSIPDU),
2492 .intfver_iscsi = FW_INTFVER(T5, ISCSI),
2493 .intfver_fcoepdu = FW_INTFVER(T5, FCOEPDU),
2494 .intfver_fcoe = FW_INTFVER(T5, FCOE),
2499 static struct fw_info *
2500 find_fw_info(int chip)
2504 for (i = 0; i < nitems(fw_info); i++) {
2505 if (fw_info[i].chip == chip)
2506 return (&fw_info[i]);
2512 * Is the given firmware API compatible with the one the driver was compiled
2516 fw_compatible(const struct fw_hdr *hdr1, const struct fw_hdr *hdr2)
2519 /* short circuit if it's the exact same firmware version */
2520 if (hdr1->chip == hdr2->chip && hdr1->fw_ver == hdr2->fw_ver)
2524 * XXX: Is this too conservative? Perhaps I should limit this to the
2525 * features that are supported in the driver.
2527 #define SAME_INTF(x) (hdr1->intfver_##x == hdr2->intfver_##x)
2528 if (hdr1->chip == hdr2->chip && SAME_INTF(nic) && SAME_INTF(vnic) &&
2529 SAME_INTF(ofld) && SAME_INTF(ri) && SAME_INTF(iscsipdu) &&
2530 SAME_INTF(iscsi) && SAME_INTF(fcoepdu) && SAME_INTF(fcoe))
2538 * The firmware in the KLD is usable, but should it be installed? This routine
2539 * explains itself in detail if it indicates the KLD firmware should be
2543 should_install_kld_fw(struct adapter *sc, int card_fw_usable, int k, int c)
2547 if (!card_fw_usable) {
2548 reason = "incompatible or unusable";
2553 reason = "older than the version bundled with this driver";
2557 if (t4_fw_install == 2 && k != c) {
2558 reason = "different than the version bundled with this driver";
2565 if (t4_fw_install == 0) {
2566 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2567 "but the driver is prohibited from installing a different "
2568 "firmware on the card.\n",
2569 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2570 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason);
2575 device_printf(sc->dev, "firmware on card (%u.%u.%u.%u) is %s, "
2576 "installing firmware %u.%u.%u.%u on card.\n",
2577 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2578 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c), reason,
2579 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2580 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2585 * Establish contact with the firmware and determine if we are the master driver
2586 * or not, and whether we are responsible for chip initialization.
2589 prep_firmware(struct adapter *sc)
2591 const struct firmware *fw = NULL, *default_cfg;
2592 int rc, pf, card_fw_usable, kld_fw_usable, need_fw_reset = 1;
2593 enum dev_state state;
2594 struct fw_info *fw_info;
2595 struct fw_hdr *card_fw; /* fw on the card */
2596 const struct fw_hdr *kld_fw; /* fw in the KLD */
2597 const struct fw_hdr *drv_fw; /* fw header the driver was compiled
2600 /* Contact firmware. */
2601 rc = t4_fw_hello(sc, sc->mbox, sc->mbox, MASTER_MAY, &state);
2602 if (rc < 0 || state == DEV_STATE_ERR) {
2604 device_printf(sc->dev,
2605 "failed to connect to the firmware: %d, %d.\n", rc, state);
2610 sc->flags |= MASTER_PF;
2611 else if (state == DEV_STATE_UNINIT) {
2613 * We didn't get to be the master so we definitely won't be
2614 * configuring the chip. It's a bug if someone else hasn't
2615 * configured it already.
2617 device_printf(sc->dev, "couldn't be master(%d), "
2618 "device not already initialized either(%d).\n", rc, state);
2622 /* This is the firmware whose headers the driver was compiled against */
2623 fw_info = find_fw_info(chip_id(sc));
2624 if (fw_info == NULL) {
2625 device_printf(sc->dev,
2626 "unable to look up firmware information for chip %d.\n",
2630 drv_fw = &fw_info->fw_hdr;
2633 * The firmware KLD contains many modules. The KLD name is also the
2634 * name of the module that contains the default config file.
2636 default_cfg = firmware_get(fw_info->kld_name);
2638 /* Read the header of the firmware on the card */
2639 card_fw = malloc(sizeof(*card_fw), M_CXGBE, M_ZERO | M_WAITOK);
2640 rc = -t4_read_flash(sc, FLASH_FW_START,
2641 sizeof (*card_fw) / sizeof (uint32_t), (uint32_t *)card_fw, 1);
2643 card_fw_usable = fw_compatible(drv_fw, (const void*)card_fw);
2645 device_printf(sc->dev,
2646 "Unable to read card's firmware header: %d\n", rc);
2650 /* This is the firmware in the KLD */
2651 fw = firmware_get(fw_info->fw_mod_name);
2653 kld_fw = (const void *)fw->data;
2654 kld_fw_usable = fw_compatible(drv_fw, kld_fw);
2660 if (card_fw_usable && card_fw->fw_ver == drv_fw->fw_ver &&
2661 (!kld_fw_usable || kld_fw->fw_ver == drv_fw->fw_ver)) {
2663 * Common case: the firmware on the card is an exact match and
2664 * the KLD is an exact match too, or the KLD is
2665 * absent/incompatible. Note that t4_fw_install = 2 is ignored
2666 * here -- use cxgbetool loadfw if you want to reinstall the
2667 * same firmware as the one on the card.
2669 } else if (kld_fw_usable && state == DEV_STATE_UNINIT &&
2670 should_install_kld_fw(sc, card_fw_usable, be32toh(kld_fw->fw_ver),
2671 be32toh(card_fw->fw_ver))) {
2673 rc = -t4_fw_upgrade(sc, sc->mbox, fw->data, fw->datasize, 0);
2675 device_printf(sc->dev,
2676 "failed to install firmware: %d\n", rc);
2680 /* Installed successfully, update the cached header too. */
2681 memcpy(card_fw, kld_fw, sizeof(*card_fw));
2683 need_fw_reset = 0; /* already reset as part of load_fw */
2686 if (!card_fw_usable) {
2689 d = ntohl(drv_fw->fw_ver);
2690 c = ntohl(card_fw->fw_ver);
2691 k = kld_fw ? ntohl(kld_fw->fw_ver) : 0;
2693 device_printf(sc->dev, "Cannot find a usable firmware: "
2694 "fw_install %d, chip state %d, "
2695 "driver compiled with %d.%d.%d.%d, "
2696 "card has %d.%d.%d.%d, KLD has %d.%d.%d.%d\n",
2697 t4_fw_install, state,
2698 G_FW_HDR_FW_VER_MAJOR(d), G_FW_HDR_FW_VER_MINOR(d),
2699 G_FW_HDR_FW_VER_MICRO(d), G_FW_HDR_FW_VER_BUILD(d),
2700 G_FW_HDR_FW_VER_MAJOR(c), G_FW_HDR_FW_VER_MINOR(c),
2701 G_FW_HDR_FW_VER_MICRO(c), G_FW_HDR_FW_VER_BUILD(c),
2702 G_FW_HDR_FW_VER_MAJOR(k), G_FW_HDR_FW_VER_MINOR(k),
2703 G_FW_HDR_FW_VER_MICRO(k), G_FW_HDR_FW_VER_BUILD(k));
2708 /* We're using whatever's on the card and it's known to be good. */
2709 sc->params.fw_vers = ntohl(card_fw->fw_ver);
2710 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
2711 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
2712 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
2713 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
2714 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
2716 t4_get_tp_version(sc, &sc->params.tp_vers);
2717 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
2718 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
2719 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
2720 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
2721 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
2723 if (t4_get_exprom_version(sc, &sc->params.exprom_vers) != 0)
2724 sc->params.exprom_vers = 0;
2726 snprintf(sc->exprom_version, sizeof(sc->exprom_version),
2728 G_FW_HDR_FW_VER_MAJOR(sc->params.exprom_vers),
2729 G_FW_HDR_FW_VER_MINOR(sc->params.exprom_vers),
2730 G_FW_HDR_FW_VER_MICRO(sc->params.exprom_vers),
2731 G_FW_HDR_FW_VER_BUILD(sc->params.exprom_vers));
2735 if (need_fw_reset &&
2736 (rc = -t4_fw_reset(sc, sc->mbox, F_PIORSTMODE | F_PIORST)) != 0) {
2737 device_printf(sc->dev, "firmware reset failed: %d.\n", rc);
2738 if (rc != ETIMEDOUT && rc != EIO)
2739 t4_fw_bye(sc, sc->mbox);
2744 rc = get_params__pre_init(sc);
2746 goto done; /* error message displayed already */
2748 /* Partition adapter resources as specified in the config file. */
2749 if (state == DEV_STATE_UNINIT) {
2751 KASSERT(sc->flags & MASTER_PF,
2752 ("%s: trying to change chip settings when not master.",
2755 rc = partition_resources(sc, default_cfg, fw_info->kld_name);
2757 goto done; /* error message displayed already */
2759 t4_tweak_chip_settings(sc);
2761 /* get basic stuff going */
2762 rc = -t4_fw_initialize(sc, sc->mbox);
2764 device_printf(sc->dev, "fw init failed: %d.\n", rc);
2768 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "pf%d", pf);
2773 free(card_fw, M_CXGBE);
2775 firmware_put(fw, FIRMWARE_UNLOAD);
2776 if (default_cfg != NULL)
2777 firmware_put(default_cfg, FIRMWARE_UNLOAD);
2782 #define FW_PARAM_DEV(param) \
2783 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
2784 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
2785 #define FW_PARAM_PFVF(param) \
2786 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
2787 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
2790 * Partition chip resources for use between various PFs, VFs, etc.
2793 partition_resources(struct adapter *sc, const struct firmware *default_cfg,
2794 const char *name_prefix)
2796 const struct firmware *cfg = NULL;
2798 struct fw_caps_config_cmd caps;
2799 uint32_t mtype, moff, finicsum, cfcsum;
2802 * Figure out what configuration file to use. Pick the default config
2803 * file for the card if the user hasn't specified one explicitly.
2805 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", t4_cfg_file);
2806 if (strncmp(t4_cfg_file, DEFAULT_CF, sizeof(t4_cfg_file)) == 0) {
2807 /* Card specific overrides go here. */
2808 if (pci_get_device(sc->dev) == 0x440a)
2809 snprintf(sc->cfg_file, sizeof(sc->cfg_file), UWIRE_CF);
2811 snprintf(sc->cfg_file, sizeof(sc->cfg_file), FPGA_CF);
2815 * We need to load another module if the profile is anything except
2816 * "default" or "flash".
2818 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) != 0 &&
2819 strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2822 snprintf(s, sizeof(s), "%s_%s", name_prefix, sc->cfg_file);
2823 cfg = firmware_get(s);
2825 if (default_cfg != NULL) {
2826 device_printf(sc->dev,
2827 "unable to load module \"%s\" for "
2828 "configuration profile \"%s\", will use "
2829 "the default config file instead.\n",
2831 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2834 device_printf(sc->dev,
2835 "unable to load module \"%s\" for "
2836 "configuration profile \"%s\", will use "
2837 "the config file on the card's flash "
2838 "instead.\n", s, sc->cfg_file);
2839 snprintf(sc->cfg_file, sizeof(sc->cfg_file),
2845 if (strncmp(sc->cfg_file, DEFAULT_CF, sizeof(sc->cfg_file)) == 0 &&
2846 default_cfg == NULL) {
2847 device_printf(sc->dev,
2848 "default config file not available, will use the config "
2849 "file on the card's flash instead.\n");
2850 snprintf(sc->cfg_file, sizeof(sc->cfg_file), "%s", FLASH_CF);
2853 if (strncmp(sc->cfg_file, FLASH_CF, sizeof(sc->cfg_file)) != 0) {
2855 const uint32_t *cfdata;
2856 uint32_t param, val, addr;
2858 KASSERT(cfg != NULL || default_cfg != NULL,
2859 ("%s: no config to upload", __func__));
2862 * Ask the firmware where it wants us to upload the config file.
2864 param = FW_PARAM_DEV(CF);
2865 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2867 /* No support for config file? Shouldn't happen. */
2868 device_printf(sc->dev,
2869 "failed to query config file location: %d.\n", rc);
2872 mtype = G_FW_PARAMS_PARAM_Y(val);
2873 moff = G_FW_PARAMS_PARAM_Z(val) << 16;
2876 * XXX: sheer laziness. We deliberately added 4 bytes of
2877 * useless stuffing/comments at the end of the config file so
2878 * it's ok to simply throw away the last remaining bytes when
2879 * the config file is not an exact multiple of 4. This also
2880 * helps with the validate_mt_off_len check.
2883 cflen = cfg->datasize & ~3;
2886 cflen = default_cfg->datasize & ~3;
2887 cfdata = default_cfg->data;
2890 if (cflen > FLASH_CFG_MAX_SIZE) {
2891 device_printf(sc->dev,
2892 "config file too long (%d, max allowed is %d). "
2893 "Will try to use the config on the card, if any.\n",
2894 cflen, FLASH_CFG_MAX_SIZE);
2895 goto use_config_on_flash;
2898 rc = validate_mt_off_len(sc, mtype, moff, cflen, &addr);
2900 device_printf(sc->dev,
2901 "%s: addr (%d/0x%x) or len %d is not valid: %d. "
2902 "Will try to use the config on the card, if any.\n",
2903 __func__, mtype, moff, cflen, rc);
2904 goto use_config_on_flash;
2906 write_via_memwin(sc, 2, addr, cfdata, cflen);
2908 use_config_on_flash:
2909 mtype = FW_MEMTYPE_FLASH;
2910 moff = t4_flash_cfg_addr(sc);
2913 bzero(&caps, sizeof(caps));
2914 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2915 F_FW_CMD_REQUEST | F_FW_CMD_READ);
2916 caps.cfvalid_to_len16 = htobe32(F_FW_CAPS_CONFIG_CMD_CFVALID |
2917 V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(mtype) |
2918 V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(moff >> 16) | FW_LEN16(caps));
2919 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
2921 device_printf(sc->dev,
2922 "failed to pre-process config file: %d "
2923 "(mtype %d, moff 0x%x).\n", rc, mtype, moff);
2927 finicsum = be32toh(caps.finicsum);
2928 cfcsum = be32toh(caps.cfcsum);
2929 if (finicsum != cfcsum) {
2930 device_printf(sc->dev,
2931 "WARNING: config file checksum mismatch: %08x %08x\n",
2934 sc->cfcsum = cfcsum;
2936 #define LIMIT_CAPS(x) do { \
2937 caps.x &= htobe16(t4_##x##_allowed); \
2941 * Let the firmware know what features will (not) be used so it can tune
2942 * things accordingly.
2944 LIMIT_CAPS(nbmcaps);
2945 LIMIT_CAPS(linkcaps);
2946 LIMIT_CAPS(switchcaps);
2947 LIMIT_CAPS(niccaps);
2948 LIMIT_CAPS(toecaps);
2949 LIMIT_CAPS(rdmacaps);
2950 LIMIT_CAPS(tlscaps);
2951 LIMIT_CAPS(iscsicaps);
2952 LIMIT_CAPS(fcoecaps);
2955 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
2956 F_FW_CMD_REQUEST | F_FW_CMD_WRITE);
2957 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
2958 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), NULL);
2960 device_printf(sc->dev,
2961 "failed to process config file: %d.\n", rc);
2965 firmware_put(cfg, FIRMWARE_UNLOAD);
2970 * Retrieve parameters that are needed (or nice to have) very early.
2973 get_params__pre_init(struct adapter *sc)
2976 uint32_t param[2], val[2];
2978 param[0] = FW_PARAM_DEV(PORTVEC);
2979 param[1] = FW_PARAM_DEV(CCLK);
2980 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
2982 device_printf(sc->dev,
2983 "failed to query parameters (pre_init): %d.\n", rc);
2987 sc->params.portvec = val[0];
2988 sc->params.nports = bitcount32(val[0]);
2989 sc->params.vpd.cclk = val[1];
2991 /* Read device log parameters. */
2992 rc = -t4_init_devlog_params(sc, 1);
2994 fixup_devlog_params(sc);
2996 device_printf(sc->dev,
2997 "failed to get devlog parameters: %d.\n", rc);
2998 rc = 0; /* devlog isn't critical for device operation */
3005 * Retrieve various parameters that are of interest to the driver. The device
3006 * has been initialized by the firmware at this point.
3009 get_params__post_init(struct adapter *sc)
3012 uint32_t param[7], val[7];
3013 struct fw_caps_config_cmd caps;
3015 param[0] = FW_PARAM_PFVF(IQFLINT_START);
3016 param[1] = FW_PARAM_PFVF(EQ_START);
3017 param[2] = FW_PARAM_PFVF(FILTER_START);
3018 param[3] = FW_PARAM_PFVF(FILTER_END);
3019 param[4] = FW_PARAM_PFVF(L2T_START);
3020 param[5] = FW_PARAM_PFVF(L2T_END);
3021 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3023 device_printf(sc->dev,
3024 "failed to query parameters (post_init): %d.\n", rc);
3028 sc->sge.iq_start = val[0];
3029 sc->sge.eq_start = val[1];
3030 sc->tids.ftid_base = val[2];
3031 sc->tids.nftids = val[3] - val[2] + 1;
3032 sc->params.ftid_min = val[2];
3033 sc->params.ftid_max = val[3];
3034 sc->vres.l2t.start = val[4];
3035 sc->vres.l2t.size = val[5] - val[4] + 1;
3036 KASSERT(sc->vres.l2t.size <= L2T_SIZE,
3037 ("%s: L2 table size (%u) larger than expected (%u)",
3038 __func__, sc->vres.l2t.size, L2T_SIZE));
3040 /* get capabilites */
3041 bzero(&caps, sizeof(caps));
3042 caps.op_to_write = htobe32(V_FW_CMD_OP(FW_CAPS_CONFIG_CMD) |
3043 F_FW_CMD_REQUEST | F_FW_CMD_READ);
3044 caps.cfvalid_to_len16 = htobe32(FW_LEN16(caps));
3045 rc = -t4_wr_mbox(sc, sc->mbox, &caps, sizeof(caps), &caps);
3047 device_printf(sc->dev,
3048 "failed to get card capabilities: %d.\n", rc);
3052 #define READ_CAPS(x) do { \
3053 sc->x = htobe16(caps.x); \
3056 READ_CAPS(linkcaps);
3057 READ_CAPS(switchcaps);
3060 READ_CAPS(rdmacaps);
3062 READ_CAPS(iscsicaps);
3063 READ_CAPS(fcoecaps);
3065 if (sc->niccaps & FW_CAPS_CONFIG_NIC_ETHOFLD) {
3066 param[0] = FW_PARAM_PFVF(ETHOFLD_START);
3067 param[1] = FW_PARAM_PFVF(ETHOFLD_END);
3068 param[2] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3069 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 3, param, val);
3071 device_printf(sc->dev,
3072 "failed to query NIC parameters: %d.\n", rc);
3075 sc->tids.etid_base = val[0];
3076 sc->params.etid_min = val[0];
3077 sc->tids.netids = val[1] - val[0] + 1;
3078 sc->params.netids = sc->tids.netids;
3079 sc->params.eo_wr_cred = val[2];
3080 sc->params.ethoffload = 1;
3084 /* query offload-related parameters */
3085 param[0] = FW_PARAM_DEV(NTID);
3086 param[1] = FW_PARAM_PFVF(SERVER_START);
3087 param[2] = FW_PARAM_PFVF(SERVER_END);
3088 param[3] = FW_PARAM_PFVF(TDDP_START);
3089 param[4] = FW_PARAM_PFVF(TDDP_END);
3090 param[5] = FW_PARAM_DEV(FLOWC_BUFFIFO_SZ);
3091 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3093 device_printf(sc->dev,
3094 "failed to query TOE parameters: %d.\n", rc);
3097 sc->tids.ntids = val[0];
3098 sc->tids.natids = min(sc->tids.ntids / 2, MAX_ATIDS);
3099 sc->tids.stid_base = val[1];
3100 sc->tids.nstids = val[2] - val[1] + 1;
3101 sc->vres.ddp.start = val[3];
3102 sc->vres.ddp.size = val[4] - val[3] + 1;
3103 sc->params.ofldq_wr_cred = val[5];
3104 sc->params.offload = 1;
3107 param[0] = FW_PARAM_PFVF(STAG_START);
3108 param[1] = FW_PARAM_PFVF(STAG_END);
3109 param[2] = FW_PARAM_PFVF(RQ_START);
3110 param[3] = FW_PARAM_PFVF(RQ_END);
3111 param[4] = FW_PARAM_PFVF(PBL_START);
3112 param[5] = FW_PARAM_PFVF(PBL_END);
3113 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3115 device_printf(sc->dev,
3116 "failed to query RDMA parameters(1): %d.\n", rc);
3119 sc->vres.stag.start = val[0];
3120 sc->vres.stag.size = val[1] - val[0] + 1;
3121 sc->vres.rq.start = val[2];
3122 sc->vres.rq.size = val[3] - val[2] + 1;
3123 sc->vres.pbl.start = val[4];
3124 sc->vres.pbl.size = val[5] - val[4] + 1;
3126 param[0] = FW_PARAM_PFVF(SQRQ_START);
3127 param[1] = FW_PARAM_PFVF(SQRQ_END);
3128 param[2] = FW_PARAM_PFVF(CQ_START);
3129 param[3] = FW_PARAM_PFVF(CQ_END);
3130 param[4] = FW_PARAM_PFVF(OCQ_START);
3131 param[5] = FW_PARAM_PFVF(OCQ_END);
3132 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 6, param, val);
3134 device_printf(sc->dev,
3135 "failed to query RDMA parameters(2): %d.\n", rc);
3138 sc->vres.qp.start = val[0];
3139 sc->vres.qp.size = val[1] - val[0] + 1;
3140 sc->vres.cq.start = val[2];
3141 sc->vres.cq.size = val[3] - val[2] + 1;
3142 sc->vres.ocq.start = val[4];
3143 sc->vres.ocq.size = val[5] - val[4] + 1;
3145 if (sc->iscsicaps) {
3146 param[0] = FW_PARAM_PFVF(ISCSI_START);
3147 param[1] = FW_PARAM_PFVF(ISCSI_END);
3148 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 2, param, val);
3150 device_printf(sc->dev,
3151 "failed to query iSCSI parameters: %d.\n", rc);
3154 sc->vres.iscsi.start = val[0];
3155 sc->vres.iscsi.size = val[1] - val[0] + 1;
3159 * We've got the params we wanted to query via the firmware. Now grab
3160 * some others directly from the chip.
3162 rc = t4_read_chip_settings(sc);
3168 set_params__post_init(struct adapter *sc)
3170 uint32_t param, val;
3172 /* ask for encapsulated CPLs */
3173 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
3175 (void)t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
3180 #undef FW_PARAM_PFVF
3184 t4_set_desc(struct adapter *sc)
3187 struct adapter_params *p = &sc->params;
3189 snprintf(buf, sizeof(buf), "Chelsio %s %sNIC (rev %d), S/N:%s, "
3190 "P/N:%s, E/C:%s", p->vpd.id, is_offload(sc) ? "R" : "",
3191 chip_rev(sc), p->vpd.sn, p->vpd.pn, p->vpd.ec);
3193 device_set_desc_copy(sc->dev, buf);
3197 build_medialist(struct port_info *pi, struct ifmedia *media)
3203 ifmedia_removeall(media);
3205 m = IFM_ETHER | IFM_FDX;
3207 switch(pi->port_type) {
3208 case FW_PORT_TYPE_BT_XFI:
3209 case FW_PORT_TYPE_BT_XAUI:
3210 ifmedia_add(media, m | IFM_10G_T, 0, NULL);
3213 case FW_PORT_TYPE_BT_SGMII:
3214 ifmedia_add(media, m | IFM_1000_T, 0, NULL);
3215 ifmedia_add(media, m | IFM_100_TX, 0, NULL);
3216 ifmedia_add(media, IFM_ETHER | IFM_AUTO, 0, NULL);
3217 ifmedia_set(media, IFM_ETHER | IFM_AUTO);
3220 case FW_PORT_TYPE_CX4:
3221 ifmedia_add(media, m | IFM_10G_CX4, 0, NULL);
3222 ifmedia_set(media, m | IFM_10G_CX4);
3225 case FW_PORT_TYPE_QSFP_10G:
3226 case FW_PORT_TYPE_SFP:
3227 case FW_PORT_TYPE_FIBER_XFI:
3228 case FW_PORT_TYPE_FIBER_XAUI:
3229 switch (pi->mod_type) {
3231 case FW_PORT_MOD_TYPE_LR:
3232 ifmedia_add(media, m | IFM_10G_LR, 0, NULL);
3233 ifmedia_set(media, m | IFM_10G_LR);
3236 case FW_PORT_MOD_TYPE_SR:
3237 ifmedia_add(media, m | IFM_10G_SR, 0, NULL);
3238 ifmedia_set(media, m | IFM_10G_SR);
3241 case FW_PORT_MOD_TYPE_LRM:
3242 ifmedia_add(media, m | IFM_10G_LRM, 0, NULL);
3243 ifmedia_set(media, m | IFM_10G_LRM);
3246 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3247 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3248 ifmedia_add(media, m | IFM_10G_TWINAX, 0, NULL);
3249 ifmedia_set(media, m | IFM_10G_TWINAX);
3252 case FW_PORT_MOD_TYPE_NONE:
3254 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3255 ifmedia_set(media, m | IFM_NONE);
3258 case FW_PORT_MOD_TYPE_NA:
3259 case FW_PORT_MOD_TYPE_ER:
3261 device_printf(pi->dev,
3262 "unknown port_type (%d), mod_type (%d)\n",
3263 pi->port_type, pi->mod_type);
3264 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3265 ifmedia_set(media, m | IFM_UNKNOWN);
3270 case FW_PORT_TYPE_QSFP:
3271 switch (pi->mod_type) {
3273 case FW_PORT_MOD_TYPE_LR:
3274 ifmedia_add(media, m | IFM_40G_LR4, 0, NULL);
3275 ifmedia_set(media, m | IFM_40G_LR4);
3278 case FW_PORT_MOD_TYPE_SR:
3279 ifmedia_add(media, m | IFM_40G_SR4, 0, NULL);
3280 ifmedia_set(media, m | IFM_40G_SR4);
3283 case FW_PORT_MOD_TYPE_TWINAX_PASSIVE:
3284 case FW_PORT_MOD_TYPE_TWINAX_ACTIVE:
3285 ifmedia_add(media, m | IFM_40G_CR4, 0, NULL);
3286 ifmedia_set(media, m | IFM_40G_CR4);
3289 case FW_PORT_MOD_TYPE_NONE:
3291 ifmedia_add(media, m | IFM_NONE, 0, NULL);
3292 ifmedia_set(media, m | IFM_NONE);
3296 device_printf(pi->dev,
3297 "unknown port_type (%d), mod_type (%d)\n",
3298 pi->port_type, pi->mod_type);
3299 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3300 ifmedia_set(media, m | IFM_UNKNOWN);
3306 device_printf(pi->dev,
3307 "unknown port_type (%d), mod_type (%d)\n", pi->port_type,
3309 ifmedia_add(media, m | IFM_UNKNOWN, 0, NULL);
3310 ifmedia_set(media, m | IFM_UNKNOWN);
3317 #define FW_MAC_EXACT_CHUNK 7
3320 * Program the port's XGMAC based on parameters in ifnet. The caller also
3321 * indicates which parameters should be programmed (the rest are left alone).
3324 update_mac_settings(struct ifnet *ifp, int flags)
3327 struct vi_info *vi = ifp->if_softc;
3328 struct port_info *pi = vi->pi;
3329 struct adapter *sc = pi->adapter;
3330 int mtu = -1, promisc = -1, allmulti = -1, vlanex = -1;
3332 ASSERT_SYNCHRONIZED_OP(sc);
3333 KASSERT(flags, ("%s: not told what to update.", __func__));
3335 if (flags & XGMAC_MTU)
3338 if (flags & XGMAC_PROMISC)
3339 promisc = ifp->if_flags & IFF_PROMISC ? 1 : 0;
3341 if (flags & XGMAC_ALLMULTI)
3342 allmulti = ifp->if_flags & IFF_ALLMULTI ? 1 : 0;
3344 if (flags & XGMAC_VLANEX)
3345 vlanex = ifp->if_capenable & IFCAP_VLAN_HWTAGGING ? 1 : 0;
3347 if (flags & (XGMAC_MTU|XGMAC_PROMISC|XGMAC_ALLMULTI|XGMAC_VLANEX)) {
3348 rc = -t4_set_rxmode(sc, sc->mbox, vi->viid, mtu, promisc,
3349 allmulti, 1, vlanex, false);
3351 if_printf(ifp, "set_rxmode (%x) failed: %d\n", flags,
3357 if (flags & XGMAC_UCADDR) {
3358 uint8_t ucaddr[ETHER_ADDR_LEN];
3360 bcopy(IF_LLADDR(ifp), ucaddr, sizeof(ucaddr));
3361 rc = t4_change_mac(sc, sc->mbox, vi->viid, vi->xact_addr_filt,
3362 ucaddr, true, true);
3365 if_printf(ifp, "change_mac failed: %d\n", rc);
3368 vi->xact_addr_filt = rc;
3373 if (flags & XGMAC_MCADDRS) {
3374 const uint8_t *mcaddr[FW_MAC_EXACT_CHUNK];
3377 struct ifmultiaddr *ifma;
3380 if_maddr_rlock(ifp);
3381 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
3382 if (ifma->ifma_addr->sa_family != AF_LINK)
3385 LLADDR((struct sockaddr_dl *)ifma->ifma_addr);
3386 MPASS(ETHER_IS_MULTICAST(mcaddr[i]));
3389 if (i == FW_MAC_EXACT_CHUNK) {
3390 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid,
3391 del, i, mcaddr, NULL, &hash, 0);
3394 for (j = 0; j < i; j++) {
3396 "failed to add mc address"
3398 "%02x:%02x:%02x rc=%d\n",
3399 mcaddr[j][0], mcaddr[j][1],
3400 mcaddr[j][2], mcaddr[j][3],
3401 mcaddr[j][4], mcaddr[j][5],
3411 rc = t4_alloc_mac_filt(sc, sc->mbox, vi->viid, del, i,
3412 mcaddr, NULL, &hash, 0);
3415 for (j = 0; j < i; j++) {
3417 "failed to add mc address"
3419 "%02x:%02x:%02x rc=%d\n",
3420 mcaddr[j][0], mcaddr[j][1],
3421 mcaddr[j][2], mcaddr[j][3],
3422 mcaddr[j][4], mcaddr[j][5],
3429 rc = -t4_set_addr_hash(sc, sc->mbox, vi->viid, 0, hash, 0);
3431 if_printf(ifp, "failed to set mc address hash: %d", rc);
3433 if_maddr_runlock(ifp);
3440 * {begin|end}_synchronized_op must be called from the same thread.
3443 begin_synchronized_op(struct adapter *sc, struct vi_info *vi, int flags,
3449 /* the caller thinks it's ok to sleep, but is it really? */
3450 if (flags & SLEEP_OK)
3451 WITNESS_WARN(WARN_GIANTOK | WARN_SLEEPOK, NULL,
3452 "begin_synchronized_op");
3463 if (vi && IS_DOOMED(vi)) {
3473 if (!(flags & SLEEP_OK)) {
3478 if (mtx_sleep(&sc->flags, &sc->sc_lock, pri, wmesg, 0)) {
3484 KASSERT(!IS_BUSY(sc), ("%s: controller busy.", __func__));
3487 sc->last_op = wmesg;
3488 sc->last_op_thr = curthread;
3489 sc->last_op_flags = flags;
3493 if (!(flags & HOLD_LOCK) || rc)
3500 * Tell if_ioctl and if_init that the VI is going away. This is
3501 * special variant of begin_synchronized_op and must be paired with a
3502 * call to end_synchronized_op.
3505 doom_vi(struct adapter *sc, struct vi_info *vi)
3512 mtx_sleep(&sc->flags, &sc->sc_lock, 0, "t4detach", 0);
3515 sc->last_op = "t4detach";
3516 sc->last_op_thr = curthread;
3517 sc->last_op_flags = 0;
3523 * {begin|end}_synchronized_op must be called from the same thread.
3526 end_synchronized_op(struct adapter *sc, int flags)
3529 if (flags & LOCK_HELD)
3530 ADAPTER_LOCK_ASSERT_OWNED(sc);
3534 KASSERT(IS_BUSY(sc), ("%s: controller not busy.", __func__));
3541 cxgbe_init_synchronized(struct vi_info *vi)
3543 struct port_info *pi = vi->pi;
3544 struct adapter *sc = pi->adapter;
3545 struct ifnet *ifp = vi->ifp;
3547 struct sge_txq *txq;
3549 ASSERT_SYNCHRONIZED_OP(sc);
3551 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
3552 return (0); /* already running */
3554 if (!(sc->flags & FULL_INIT_DONE) &&
3555 ((rc = adapter_full_init(sc)) != 0))
3556 return (rc); /* error message displayed already */
3558 if (!(vi->flags & VI_INIT_DONE) &&
3559 ((rc = vi_full_init(vi)) != 0))
3560 return (rc); /* error message displayed already */
3562 rc = update_mac_settings(ifp, XGMAC_ALL);
3564 goto done; /* error message displayed already */
3566 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, true, true);
3568 if_printf(ifp, "enable_vi failed: %d\n", rc);
3573 * Can't fail from this point onwards. Review cxgbe_uninit_synchronized
3577 for_each_txq(vi, i, txq) {
3579 txq->eq.flags |= EQ_ENABLED;
3584 * The first iq of the first port to come up is used for tracing.
3586 if (sc->traceq < 0 && IS_MAIN_VI(vi)) {
3587 sc->traceq = sc->sge.rxq[vi->first_rxq].iq.abs_id;
3588 t4_write_reg(sc, is_t4(sc) ? A_MPS_TRC_RSS_CONTROL :
3589 A_MPS_T5_TRC_RSS_CONTROL, V_RSSCONTROL(pi->tx_chan) |
3590 V_QUEUENUMBER(sc->traceq));
3591 pi->flags |= HAS_TRACEQ;
3596 ifp->if_drv_flags |= IFF_DRV_RUNNING;
3600 callout_reset(&vi->tick, hz, vi_tick, vi);
3602 callout_reset(&pi->tick, hz, cxgbe_tick, pi);
3606 cxgbe_uninit_synchronized(vi);
3615 cxgbe_uninit_synchronized(struct vi_info *vi)
3617 struct port_info *pi = vi->pi;
3618 struct adapter *sc = pi->adapter;
3619 struct ifnet *ifp = vi->ifp;
3621 struct sge_txq *txq;
3623 ASSERT_SYNCHRONIZED_OP(sc);
3625 if (!(vi->flags & VI_INIT_DONE)) {
3626 KASSERT(!(ifp->if_drv_flags & IFF_DRV_RUNNING),
3627 ("uninited VI is running"));
3632 * Disable the VI so that all its data in either direction is discarded
3633 * by the MPS. Leave everything else (the queues, interrupts, and 1Hz
3634 * tick) intact as the TP can deliver negative advice or data that it's
3635 * holding in its RAM (for an offloaded connection) even after the VI is
3638 rc = -t4_enable_vi(sc, sc->mbox, vi->viid, false, false);
3640 if_printf(ifp, "disable_vi failed: %d\n", rc);
3644 for_each_txq(vi, i, txq) {
3646 txq->eq.flags &= ~EQ_ENABLED;
3652 callout_stop(&pi->tick);
3654 callout_stop(&vi->tick);
3655 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
3659 ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
3661 if (pi->up_vis > 0) {
3667 pi->link_cfg.link_ok = 0;
3668 pi->link_cfg.speed = 0;
3670 t4_os_link_changed(sc, pi->port_id, 0, -1);
3676 * It is ok for this function to fail midway and return right away. t4_detach
3677 * will walk the entire sc->irq list and clean up whatever is valid.
3680 setup_intr_handlers(struct adapter *sc)
3682 int rc, rid, p, q, v;
3685 struct port_info *pi;
3687 struct sge *sge = &sc->sge;
3688 struct sge_rxq *rxq;
3690 struct sge_ofld_rxq *ofld_rxq;
3693 struct sge_nm_rxq *nm_rxq;
3700 rid = sc->intr_type == INTR_INTX ? 0 : 1;
3701 if (sc->intr_count == 1)
3702 return (t4_alloc_irq(sc, irq, rid, t4_intr_all, sc, "all"));
3704 /* Multiple interrupts. */
3705 KASSERT(sc->intr_count >= T4_EXTRA_INTR + sc->params.nports,
3706 ("%s: too few intr.", __func__));
3708 /* The first one is always error intr */
3709 rc = t4_alloc_irq(sc, irq, rid, t4_intr_err, sc, "err");
3715 /* The second one is always the firmware event queue */
3716 rc = t4_alloc_irq(sc, irq, rid, t4_intr_evt, &sge->fwq, "evt");
3722 for_each_port(sc, p) {
3724 for_each_vi(pi, v, vi) {
3725 vi->first_intr = rid - 1;
3727 if (vi->nnmrxq > 0) {
3728 int n = max(vi->nrxq, vi->nnmrxq);
3730 MPASS(vi->flags & INTR_RXQ);
3732 rxq = &sge->rxq[vi->first_rxq];
3734 nm_rxq = &sge->nm_rxq[vi->first_nm_rxq];
3736 for (q = 0; q < n; q++) {
3737 snprintf(s, sizeof(s), "%x%c%x", p,
3743 irq->nm_rxq = nm_rxq++;
3745 rc = t4_alloc_irq(sc, irq, rid,
3746 t4_vi_intr, irq, s);
3753 } else if (vi->flags & INTR_RXQ) {
3754 for_each_rxq(vi, q, rxq) {
3755 snprintf(s, sizeof(s), "%x%c%x", p,
3757 rc = t4_alloc_irq(sc, irq, rid,
3767 if (vi->flags & INTR_OFLD_RXQ) {
3768 for_each_ofld_rxq(vi, q, ofld_rxq) {
3769 snprintf(s, sizeof(s), "%x%c%x", p,
3771 rc = t4_alloc_irq(sc, irq, rid,
3772 t4_intr, ofld_rxq, s);
3783 MPASS(irq == &sc->irq[sc->intr_count]);
3789 adapter_full_init(struct adapter *sc)
3793 ASSERT_SYNCHRONIZED_OP(sc);
3794 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3795 KASSERT((sc->flags & FULL_INIT_DONE) == 0,
3796 ("%s: FULL_INIT_DONE already", __func__));
3799 * queues that belong to the adapter (not any particular port).
3801 rc = t4_setup_adapter_queues(sc);
3805 for (i = 0; i < nitems(sc->tq); i++) {
3806 sc->tq[i] = taskqueue_create("t4 taskq", M_NOWAIT,
3807 taskqueue_thread_enqueue, &sc->tq[i]);
3808 if (sc->tq[i] == NULL) {
3809 device_printf(sc->dev,
3810 "failed to allocate task queue %d\n", i);
3814 taskqueue_start_threads(&sc->tq[i], 1, PI_NET, "%s tq%d",
3815 device_get_nameunit(sc->dev), i);
3819 sc->flags |= FULL_INIT_DONE;
3822 adapter_full_uninit(sc);
3828 adapter_full_uninit(struct adapter *sc)
3832 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
3834 t4_teardown_adapter_queues(sc);
3836 for (i = 0; i < nitems(sc->tq) && sc->tq[i]; i++) {
3837 taskqueue_free(sc->tq[i]);
3841 sc->flags &= ~FULL_INIT_DONE;
3847 #define SUPPORTED_RSS_HASHTYPES (RSS_HASHTYPE_RSS_IPV4 | \
3848 RSS_HASHTYPE_RSS_TCP_IPV4 | RSS_HASHTYPE_RSS_IPV6 | \
3849 RSS_HASHTYPE_RSS_TCP_IPV6 | RSS_HASHTYPE_RSS_UDP_IPV4 | \
3850 RSS_HASHTYPE_RSS_UDP_IPV6)
3852 /* Translates kernel hash types to hardware. */
3854 hashconfig_to_hashen(int hashconfig)
3858 if (hashconfig & RSS_HASHTYPE_RSS_IPV4)
3859 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN;
3860 if (hashconfig & RSS_HASHTYPE_RSS_IPV6)
3861 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN;
3862 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV4) {
3863 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
3864 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
3866 if (hashconfig & RSS_HASHTYPE_RSS_UDP_IPV6) {
3867 hashen |= F_FW_RSS_VI_CONFIG_CMD_UDPEN |
3868 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
3870 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV4)
3871 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN;
3872 if (hashconfig & RSS_HASHTYPE_RSS_TCP_IPV6)
3873 hashen |= F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN;
3878 /* Translates hardware hash types to kernel. */
3880 hashen_to_hashconfig(int hashen)
3884 if (hashen & F_FW_RSS_VI_CONFIG_CMD_UDPEN) {
3886 * If UDP hashing was enabled it must have been enabled for
3887 * either IPv4 or IPv6 (inclusive or). Enabling UDP without
3888 * enabling any 4-tuple hash is nonsense configuration.
3890 MPASS(hashen & (F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
3891 F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN));
3893 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
3894 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV4;
3895 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
3896 hashconfig |= RSS_HASHTYPE_RSS_UDP_IPV6;
3898 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN)
3899 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV4;
3900 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN)
3901 hashconfig |= RSS_HASHTYPE_RSS_TCP_IPV6;
3902 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN)
3903 hashconfig |= RSS_HASHTYPE_RSS_IPV4;
3904 if (hashen & F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN)
3905 hashconfig |= RSS_HASHTYPE_RSS_IPV6;
3907 return (hashconfig);
3912 vi_full_init(struct vi_info *vi)
3914 struct adapter *sc = vi->pi->adapter;
3915 struct ifnet *ifp = vi->ifp;
3917 struct sge_rxq *rxq;
3918 int rc, i, j, hashen;
3920 int nbuckets = rss_getnumbuckets();
3921 int hashconfig = rss_gethashconfig();
3923 uint32_t raw_rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
3924 uint32_t rss_key[RSS_KEYSIZE / sizeof(uint32_t)];
3927 ASSERT_SYNCHRONIZED_OP(sc);
3928 KASSERT((vi->flags & VI_INIT_DONE) == 0,
3929 ("%s: VI_INIT_DONE already", __func__));
3931 sysctl_ctx_init(&vi->ctx);
3932 vi->flags |= VI_SYSCTL_CTX;
3935 * Allocate tx/rx/fl queues for this VI.
3937 rc = t4_setup_vi_queues(vi);
3939 goto done; /* error message displayed already */
3942 * Setup RSS for this VI. Save a copy of the RSS table for later use.
3944 if (vi->nrxq > vi->rss_size) {
3945 if_printf(ifp, "nrxq (%d) > hw RSS table size (%d); "
3946 "some queues will never receive traffic.\n", vi->nrxq,
3948 } else if (vi->rss_size % vi->nrxq) {
3949 if_printf(ifp, "nrxq (%d), hw RSS table size (%d); "
3950 "expect uneven traffic distribution.\n", vi->nrxq,
3954 MPASS(RSS_KEYSIZE == 40);
3955 if (vi->nrxq != nbuckets) {
3956 if_printf(ifp, "nrxq (%d) != kernel RSS buckets (%d);"
3957 "performance will be impacted.\n", vi->nrxq, nbuckets);
3960 rss_getkey((void *)&raw_rss_key[0]);
3961 for (i = 0; i < nitems(rss_key); i++) {
3962 rss_key[i] = htobe32(raw_rss_key[nitems(rss_key) - 1 - i]);
3964 t4_write_rss_key(sc, &rss_key[0], -1);
3966 rss = malloc(vi->rss_size * sizeof (*rss), M_CXGBE, M_ZERO | M_WAITOK);
3967 for (i = 0; i < vi->rss_size;) {
3969 j = rss_get_indirection_to_bucket(i);
3971 rxq = &sc->sge.rxq[vi->first_rxq + j];
3972 rss[i++] = rxq->iq.abs_id;
3974 for_each_rxq(vi, j, rxq) {
3975 rss[i++] = rxq->iq.abs_id;
3976 if (i == vi->rss_size)
3982 rc = -t4_config_rss_range(sc, sc->mbox, vi->viid, 0, vi->rss_size, rss,
3985 if_printf(ifp, "rss_config failed: %d\n", rc);
3990 hashen = hashconfig_to_hashen(hashconfig);
3993 * We may have had to enable some hashes even though the global config
3994 * wants them disabled. This is a potential problem that must be
3995 * reported to the user.
3997 extra = hashen_to_hashconfig(hashen) ^ hashconfig;
4000 * If we consider only the supported hash types, then the enabled hashes
4001 * are a superset of the requested hashes. In other words, there cannot
4002 * be any supported hash that was requested but not enabled, but there
4003 * can be hashes that were not requested but had to be enabled.
4005 extra &= SUPPORTED_RSS_HASHTYPES;
4006 MPASS((extra & hashconfig) == 0);
4010 "global RSS config (0x%x) cannot be accomodated.\n",
4013 if (extra & RSS_HASHTYPE_RSS_IPV4)
4014 if_printf(ifp, "IPv4 2-tuple hashing forced on.\n");
4015 if (extra & RSS_HASHTYPE_RSS_TCP_IPV4)
4016 if_printf(ifp, "TCP/IPv4 4-tuple hashing forced on.\n");
4017 if (extra & RSS_HASHTYPE_RSS_IPV6)
4018 if_printf(ifp, "IPv6 2-tuple hashing forced on.\n");
4019 if (extra & RSS_HASHTYPE_RSS_TCP_IPV6)
4020 if_printf(ifp, "TCP/IPv6 4-tuple hashing forced on.\n");
4021 if (extra & RSS_HASHTYPE_RSS_UDP_IPV4)
4022 if_printf(ifp, "UDP/IPv4 4-tuple hashing forced on.\n");
4023 if (extra & RSS_HASHTYPE_RSS_UDP_IPV6)
4024 if_printf(ifp, "UDP/IPv6 4-tuple hashing forced on.\n");
4026 hashen = F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN |
4027 F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN |
4028 F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN |
4029 F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN | F_FW_RSS_VI_CONFIG_CMD_UDPEN;
4031 rc = -t4_config_vi_rss(sc, sc->mbox, vi->viid, hashen, rss[0]);
4033 if_printf(ifp, "rss hash/defaultq config failed: %d\n", rc);
4038 vi->flags |= VI_INIT_DONE;
4050 vi_full_uninit(struct vi_info *vi)
4052 struct port_info *pi = vi->pi;
4053 struct adapter *sc = pi->adapter;
4055 struct sge_rxq *rxq;
4056 struct sge_txq *txq;
4058 struct sge_ofld_rxq *ofld_rxq;
4059 struct sge_wrq *ofld_txq;
4062 if (vi->flags & VI_INIT_DONE) {
4064 /* Need to quiesce queues. */
4066 /* XXX: Only for the first VI? */
4068 quiesce_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
4070 for_each_txq(vi, i, txq) {
4071 quiesce_txq(sc, txq);
4075 for_each_ofld_txq(vi, i, ofld_txq) {
4076 quiesce_wrq(sc, ofld_txq);
4080 for_each_rxq(vi, i, rxq) {
4081 quiesce_iq(sc, &rxq->iq);
4082 quiesce_fl(sc, &rxq->fl);
4086 for_each_ofld_rxq(vi, i, ofld_rxq) {
4087 quiesce_iq(sc, &ofld_rxq->iq);
4088 quiesce_fl(sc, &ofld_rxq->fl);
4091 free(vi->rss, M_CXGBE);
4092 free(vi->nm_rss, M_CXGBE);
4095 t4_teardown_vi_queues(vi);
4096 vi->flags &= ~VI_INIT_DONE;
4102 quiesce_txq(struct adapter *sc, struct sge_txq *txq)
4104 struct sge_eq *eq = &txq->eq;
4105 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4107 (void) sc; /* unused */
4111 MPASS((eq->flags & EQ_ENABLED) == 0);
4115 /* Wait for the mp_ring to empty. */
4116 while (!mp_ring_is_idle(txq->r)) {
4117 mp_ring_check_drainage(txq->r, 0);
4118 pause("rquiesce", 1);
4121 /* Then wait for the hardware to finish. */
4122 while (spg->cidx != htobe16(eq->pidx))
4123 pause("equiesce", 1);
4125 /* Finally, wait for the driver to reclaim all descriptors. */
4126 while (eq->cidx != eq->pidx)
4127 pause("dquiesce", 1);
4131 quiesce_wrq(struct adapter *sc, struct sge_wrq *wrq)
4138 quiesce_iq(struct adapter *sc, struct sge_iq *iq)
4140 (void) sc; /* unused */
4142 /* Synchronize with the interrupt handler */
4143 while (!atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_DISABLED))
4148 quiesce_fl(struct adapter *sc, struct sge_fl *fl)
4150 mtx_lock(&sc->sfl_lock);
4152 fl->flags |= FL_DOOMED;
4154 callout_stop(&sc->sfl_callout);
4155 mtx_unlock(&sc->sfl_lock);
4157 KASSERT((fl->flags & FL_STARVING) == 0,
4158 ("%s: still starving", __func__));
4162 t4_alloc_irq(struct adapter *sc, struct irq *irq, int rid,
4163 driver_intr_t *handler, void *arg, char *name)
4168 irq->res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ, &irq->rid,
4169 RF_SHAREABLE | RF_ACTIVE);
4170 if (irq->res == NULL) {
4171 device_printf(sc->dev,
4172 "failed to allocate IRQ for rid %d, name %s.\n", rid, name);
4176 rc = bus_setup_intr(sc->dev, irq->res, INTR_MPSAFE | INTR_TYPE_NET,
4177 NULL, handler, arg, &irq->tag);
4179 device_printf(sc->dev,
4180 "failed to setup interrupt for rid %d, name %s: %d\n",
4183 bus_describe_intr(sc->dev, irq->res, irq->tag, name);
4189 t4_free_irq(struct adapter *sc, struct irq *irq)
4192 bus_teardown_intr(sc->dev, irq->res, irq->tag);
4194 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->rid, irq->res);
4196 bzero(irq, sizeof(*irq));
4202 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
4205 regs->version = chip_id(sc) | chip_rev(sc) << 10;
4206 t4_get_regs(sc, buf, regs->len);
4209 #define A_PL_INDIR_CMD 0x1f8
4211 #define S_PL_AUTOINC 31
4212 #define M_PL_AUTOINC 0x1U
4213 #define V_PL_AUTOINC(x) ((x) << S_PL_AUTOINC)
4214 #define G_PL_AUTOINC(x) (((x) >> S_PL_AUTOINC) & M_PL_AUTOINC)
4216 #define S_PL_VFID 20
4217 #define M_PL_VFID 0xffU
4218 #define V_PL_VFID(x) ((x) << S_PL_VFID)
4219 #define G_PL_VFID(x) (((x) >> S_PL_VFID) & M_PL_VFID)
4222 #define M_PL_ADDR 0xfffffU
4223 #define V_PL_ADDR(x) ((x) << S_PL_ADDR)
4224 #define G_PL_ADDR(x) (((x) >> S_PL_ADDR) & M_PL_ADDR)
4226 #define A_PL_INDIR_DATA 0x1fc
4229 read_vf_stat(struct adapter *sc, unsigned int viid, int reg)
4233 mtx_assert(&sc->reg_lock, MA_OWNED);
4234 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4235 V_PL_VFID(G_FW_VIID_VIN(viid)) | V_PL_ADDR(VF_MPS_REG(reg)));
4236 stats[0] = t4_read_reg(sc, A_PL_INDIR_DATA);
4237 stats[1] = t4_read_reg(sc, A_PL_INDIR_DATA);
4238 return (((uint64_t)stats[1]) << 32 | stats[0]);
4242 t4_get_vi_stats(struct adapter *sc, unsigned int viid,
4243 struct fw_vi_stats_vf *stats)
4246 #define GET_STAT(name) \
4247 read_vf_stat(sc, viid, A_MPS_VF_STAT_##name##_L)
4249 stats->tx_bcast_bytes = GET_STAT(TX_VF_BCAST_BYTES);
4250 stats->tx_bcast_frames = GET_STAT(TX_VF_BCAST_FRAMES);
4251 stats->tx_mcast_bytes = GET_STAT(TX_VF_MCAST_BYTES);
4252 stats->tx_mcast_frames = GET_STAT(TX_VF_MCAST_FRAMES);
4253 stats->tx_ucast_bytes = GET_STAT(TX_VF_UCAST_BYTES);
4254 stats->tx_ucast_frames = GET_STAT(TX_VF_UCAST_FRAMES);
4255 stats->tx_drop_frames = GET_STAT(TX_VF_DROP_FRAMES);
4256 stats->tx_offload_bytes = GET_STAT(TX_VF_OFFLOAD_BYTES);
4257 stats->tx_offload_frames = GET_STAT(TX_VF_OFFLOAD_FRAMES);
4258 stats->rx_bcast_bytes = GET_STAT(RX_VF_BCAST_BYTES);
4259 stats->rx_bcast_frames = GET_STAT(RX_VF_BCAST_FRAMES);
4260 stats->rx_mcast_bytes = GET_STAT(RX_VF_MCAST_BYTES);
4261 stats->rx_mcast_frames = GET_STAT(RX_VF_MCAST_FRAMES);
4262 stats->rx_ucast_bytes = GET_STAT(RX_VF_UCAST_BYTES);
4263 stats->rx_ucast_frames = GET_STAT(RX_VF_UCAST_FRAMES);
4264 stats->rx_err_frames = GET_STAT(RX_VF_ERR_FRAMES);
4270 t4_clr_vi_stats(struct adapter *sc, unsigned int viid)
4274 t4_write_reg(sc, A_PL_INDIR_CMD, V_PL_AUTOINC(1) |
4275 V_PL_VFID(G_FW_VIID_VIN(viid)) |
4276 V_PL_ADDR(VF_MPS_REG(A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L)));
4277 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
4278 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
4279 t4_write_reg(sc, A_PL_INDIR_DATA, 0);
4283 vi_refresh_stats(struct adapter *sc, struct vi_info *vi)
4285 struct ifnet *ifp = vi->ifp;
4286 struct sge_txq *txq;
4288 struct fw_vi_stats_vf *s = &vi->stats;
4290 const struct timeval interval = {0, 250000}; /* 250ms */
4292 if (!(vi->flags & VI_INIT_DONE))
4296 timevalsub(&tv, &interval);
4297 if (timevalcmp(&tv, &vi->last_refreshed, <))
4300 mtx_lock(&sc->reg_lock);
4301 t4_get_vi_stats(sc, vi->viid, &vi->stats);
4303 ifp->if_ipackets = s->rx_bcast_frames + s->rx_mcast_frames +
4305 ifp->if_ierrors = s->rx_err_frames;
4306 ifp->if_opackets = s->tx_bcast_frames + s->tx_mcast_frames +
4307 s->tx_ucast_frames + s->tx_offload_frames;
4308 ifp->if_oerrors = s->tx_drop_frames;
4309 ifp->if_ibytes = s->rx_bcast_bytes + s->rx_mcast_bytes +
4311 ifp->if_obytes = s->tx_bcast_bytes + s->tx_mcast_bytes +
4312 s->tx_ucast_bytes + s->tx_offload_bytes;
4313 ifp->if_imcasts = s->rx_mcast_frames;
4314 ifp->if_omcasts = s->tx_mcast_frames;
4317 for_each_txq(vi, i, txq)
4318 drops += counter_u64_fetch(txq->r->drops);
4319 ifp->if_snd.ifq_drops = drops;
4321 getmicrotime(&vi->last_refreshed);
4322 mtx_unlock(&sc->reg_lock);
4326 cxgbe_refresh_stats(struct adapter *sc, struct port_info *pi)
4328 struct vi_info *vi = &pi->vi[0];
4329 struct ifnet *ifp = vi->ifp;
4330 struct sge_txq *txq;
4332 struct port_stats *s = &pi->stats;
4334 const struct timeval interval = {0, 250000}; /* 250ms */
4337 timevalsub(&tv, &interval);
4338 if (timevalcmp(&tv, &pi->last_refreshed, <))
4341 t4_get_port_stats(sc, pi->tx_chan, s);
4343 ifp->if_opackets = s->tx_frames;
4344 ifp->if_ipackets = s->rx_frames;
4345 ifp->if_obytes = s->tx_octets;
4346 ifp->if_ibytes = s->rx_octets;
4347 ifp->if_omcasts = s->tx_mcast_frames;
4348 ifp->if_imcasts = s->rx_mcast_frames;
4349 ifp->if_iqdrops = s->rx_ovflow0 + s->rx_ovflow1 + s->rx_ovflow2 +
4350 s->rx_ovflow3 + s->rx_trunc0 + s->rx_trunc1 + s->rx_trunc2 +
4352 for (i = 0; i < sc->chip_params->nchan; i++) {
4353 if (pi->rx_chan_map & (1 << i)) {
4356 mtx_lock(&sc->reg_lock);
4357 t4_read_indirect(sc, A_TP_MIB_INDEX, A_TP_MIB_DATA, &v,
4358 1, A_TP_MIB_TNL_CNG_DROP_0 + i);
4359 mtx_unlock(&sc->reg_lock);
4360 ifp->if_iqdrops += v;
4365 for_each_txq(vi, i, txq)
4366 drops += counter_u64_fetch(txq->r->drops);
4367 ifp->if_snd.ifq_drops = drops;
4369 ifp->if_oerrors = s->tx_error_frames;
4370 ifp->if_ierrors = s->rx_jabber + s->rx_runt + s->rx_too_long +
4371 s->rx_fcs_err + s->rx_len_err;
4373 getmicrotime(&pi->last_refreshed);
4377 cxgbe_tick(void *arg)
4379 struct port_info *pi = arg;
4380 struct adapter *sc = pi->adapter;
4382 PORT_LOCK_ASSERT_OWNED(pi);
4383 cxgbe_refresh_stats(sc, pi);
4385 callout_schedule(&pi->tick, hz);
4391 struct vi_info *vi = arg;
4392 struct adapter *sc = vi->pi->adapter;
4394 vi_refresh_stats(sc, vi);
4396 callout_schedule(&vi->tick, hz);
4400 cxgbe_vlan_config(void *arg, struct ifnet *ifp, uint16_t vid)
4404 if (arg != ifp || ifp->if_type != IFT_ETHER)
4407 vlan = VLAN_DEVAT(ifp, vid);
4408 VLAN_SETCOOKIE(vlan, ifp);
4412 * Should match fw_caps_config_<foo> enums in t4fw_interface.h
4414 static char *caps_decoder[] = {
4415 "\20\001IPMI\002NCSI", /* 0: NBM */
4416 "\20\001PPP\002QFC\003DCBX", /* 1: link */
4417 "\20\001INGRESS\002EGRESS", /* 2: switch */
4418 "\20\001NIC\002VM\003IDS\004UM\005UM_ISGL" /* 3: NIC */
4419 "\006HASHFILTER\007ETHOFLD",
4420 "\20\001TOE", /* 4: TOE */
4421 "\20\001RDDP\002RDMAC", /* 5: RDMA */
4422 "\20\001INITIATOR_PDU\002TARGET_PDU" /* 6: iSCSI */
4423 "\003INITIATOR_CNXOFLD\004TARGET_CNXOFLD"
4424 "\005INITIATOR_SSNOFLD\006TARGET_SSNOFLD"
4426 "\010INITIATOR_CMDOFLD\011TARGET_CMDOFLD",
4427 "\20\00KEYS", /* 7: TLS */
4428 "\20\001INITIATOR\002TARGET\003CTRL_OFLD" /* 8: FCoE */
4429 "\004PO_INITIATOR\005PO_TARGET",
4433 t4_sysctls(struct adapter *sc)
4435 struct sysctl_ctx_list *ctx;
4436 struct sysctl_oid *oid;
4437 struct sysctl_oid_list *children, *c0;
4438 static char *doorbells = {"\20\1UDB\2WCWR\3UDBWC\4KDB"};
4440 ctx = device_get_sysctl_ctx(sc->dev);
4445 oid = device_get_sysctl_tree(sc->dev);
4446 c0 = children = SYSCTL_CHILDREN(oid);
4448 sc->sc_do_rxcopy = 1;
4449 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "do_rx_copy", CTLFLAG_RW,
4450 &sc->sc_do_rxcopy, 1, "Do RX copy of small frames");
4452 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nports", CTLFLAG_RD, NULL,
4453 sc->params.nports, "# of ports");
4455 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "hw_revision", CTLFLAG_RD,
4456 NULL, chip_rev(sc), "chip hardware revision");
4458 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "tp_version",
4459 CTLFLAG_RD, sc->tp_version, 0, "TP microcode version");
4461 if (sc->params.exprom_vers != 0) {
4462 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "exprom_version",
4463 CTLFLAG_RD, sc->exprom_version, 0, "expansion ROM version");
4466 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "firmware_version",
4467 CTLFLAG_RD, sc->fw_version, 0, "firmware version");
4469 SYSCTL_ADD_STRING(ctx, children, OID_AUTO, "cf",
4470 CTLFLAG_RD, sc->cfg_file, 0, "configuration file");
4472 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cfcsum", CTLFLAG_RD, NULL,
4473 sc->cfcsum, "config file checksum");
4475 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "doorbells",
4476 CTLTYPE_STRING | CTLFLAG_RD, doorbells, sc->doorbells,
4477 sysctl_bitfield, "A", "available doorbells");
4479 #define SYSCTL_CAP(name, n, text) \
4480 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, #name, \
4481 CTLTYPE_STRING | CTLFLAG_RD, caps_decoder[n], sc->name, \
4482 sysctl_bitfield, "A", "available " text "capabilities")
4484 SYSCTL_CAP(nbmcaps, 0, "NBM");
4485 SYSCTL_CAP(linkcaps, 1, "link");
4486 SYSCTL_CAP(switchcaps, 2, "switch");
4487 SYSCTL_CAP(niccaps, 3, "NIC");
4488 SYSCTL_CAP(toecaps, 4, "TCP offload");
4489 SYSCTL_CAP(rdmacaps, 5, "RDMA");
4490 SYSCTL_CAP(iscsicaps, 6, "iSCSI");
4491 SYSCTL_CAP(tlscaps, 7, "TLS");
4492 SYSCTL_CAP(fcoecaps, 8, "FCoE");
4495 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "core_clock", CTLFLAG_RD, NULL,
4496 sc->params.vpd.cclk, "core clock frequency (in KHz)");
4498 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_timers",
4499 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.timer_val,
4500 sizeof(sc->params.sge.timer_val), sysctl_int_array, "A",
4501 "interrupt holdoff timer values (us)");
4503 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pkt_counts",
4504 CTLTYPE_STRING | CTLFLAG_RD, sc->params.sge.counter_val,
4505 sizeof(sc->params.sge.counter_val), sysctl_int_array, "A",
4506 "interrupt holdoff packet counter values");
4508 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nfilters", CTLFLAG_RD,
4509 NULL, sc->tids.nftids, "number of filters");
4511 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature", CTLTYPE_INT |
4512 CTLFLAG_RD, sc, 0, sysctl_temperature, "I",
4513 "chip temperature (in Celsius)");
4515 t4_sge_sysctls(sc, ctx, children);
4517 sc->lro_timeout = 100;
4518 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "lro_timeout", CTLFLAG_RW,
4519 &sc->lro_timeout, 0, "lro inactive-flush timeout (in us)");
4521 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "debug_flags", CTLFLAG_RW,
4522 &sc->debug_flags, 0, "flags to enable runtime debugging");
4526 * dev.t4nex.X.misc. Marked CTLFLAG_SKIP to avoid information overload.
4528 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "misc",
4529 CTLFLAG_RD | CTLFLAG_SKIP, NULL,
4530 "logs and miscellaneous information");
4531 children = SYSCTL_CHILDREN(oid);
4533 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cctrl",
4534 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4535 sysctl_cctrl, "A", "congestion control");
4537 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp0",
4538 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4539 sysctl_cim_ibq_obq, "A", "CIM IBQ 0 (TP0)");
4541 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_tp1",
4542 CTLTYPE_STRING | CTLFLAG_RD, sc, 1,
4543 sysctl_cim_ibq_obq, "A", "CIM IBQ 1 (TP1)");
4545 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ulp",
4546 CTLTYPE_STRING | CTLFLAG_RD, sc, 2,
4547 sysctl_cim_ibq_obq, "A", "CIM IBQ 2 (ULP)");
4549 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge0",
4550 CTLTYPE_STRING | CTLFLAG_RD, sc, 3,
4551 sysctl_cim_ibq_obq, "A", "CIM IBQ 3 (SGE0)");
4553 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_sge1",
4554 CTLTYPE_STRING | CTLFLAG_RD, sc, 4,
4555 sysctl_cim_ibq_obq, "A", "CIM IBQ 4 (SGE1)");
4557 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ibq_ncsi",
4558 CTLTYPE_STRING | CTLFLAG_RD, sc, 5,
4559 sysctl_cim_ibq_obq, "A", "CIM IBQ 5 (NCSI)");
4561 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_la",
4562 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4563 chip_id(sc) <= CHELSIO_T5 ? sysctl_cim_la : sysctl_cim_la_t6,
4564 "A", "CIM logic analyzer");
4566 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_ma_la",
4567 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4568 sysctl_cim_ma_la, "A", "CIM MA logic analyzer");
4570 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp0",
4571 CTLTYPE_STRING | CTLFLAG_RD, sc, 0 + CIM_NUM_IBQ,
4572 sysctl_cim_ibq_obq, "A", "CIM OBQ 0 (ULP0)");
4574 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp1",
4575 CTLTYPE_STRING | CTLFLAG_RD, sc, 1 + CIM_NUM_IBQ,
4576 sysctl_cim_ibq_obq, "A", "CIM OBQ 1 (ULP1)");
4578 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp2",
4579 CTLTYPE_STRING | CTLFLAG_RD, sc, 2 + CIM_NUM_IBQ,
4580 sysctl_cim_ibq_obq, "A", "CIM OBQ 2 (ULP2)");
4582 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ulp3",
4583 CTLTYPE_STRING | CTLFLAG_RD, sc, 3 + CIM_NUM_IBQ,
4584 sysctl_cim_ibq_obq, "A", "CIM OBQ 3 (ULP3)");
4586 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge",
4587 CTLTYPE_STRING | CTLFLAG_RD, sc, 4 + CIM_NUM_IBQ,
4588 sysctl_cim_ibq_obq, "A", "CIM OBQ 4 (SGE)");
4590 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_ncsi",
4591 CTLTYPE_STRING | CTLFLAG_RD, sc, 5 + CIM_NUM_IBQ,
4592 sysctl_cim_ibq_obq, "A", "CIM OBQ 5 (NCSI)");
4594 if (chip_id(sc) > CHELSIO_T4) {
4595 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge0_rx",
4596 CTLTYPE_STRING | CTLFLAG_RD, sc, 6 + CIM_NUM_IBQ,
4597 sysctl_cim_ibq_obq, "A", "CIM OBQ 6 (SGE0-RX)");
4599 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_obq_sge1_rx",
4600 CTLTYPE_STRING | CTLFLAG_RD, sc, 7 + CIM_NUM_IBQ,
4601 sysctl_cim_ibq_obq, "A", "CIM OBQ 7 (SGE1-RX)");
4604 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_pif_la",
4605 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4606 sysctl_cim_pif_la, "A", "CIM PIF logic analyzer");
4608 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cim_qcfg",
4609 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4610 sysctl_cim_qcfg, "A", "CIM queue configuration");
4612 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cpl_stats",
4613 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4614 sysctl_cpl_stats, "A", "CPL statistics");
4616 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ddp_stats",
4617 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4618 sysctl_ddp_stats, "A", "non-TCP DDP statistics");
4620 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "devlog",
4621 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4622 sysctl_devlog, "A", "firmware's device log");
4624 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fcoe_stats",
4625 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4626 sysctl_fcoe_stats, "A", "FCoE statistics");
4628 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "hw_sched",
4629 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4630 sysctl_hw_sched, "A", "hardware scheduler ");
4632 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "l2t",
4633 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4634 sysctl_l2t, "A", "hardware L2 table");
4636 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "lb_stats",
4637 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4638 sysctl_lb_stats, "A", "loopback statistics");
4640 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "meminfo",
4641 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4642 sysctl_meminfo, "A", "memory regions");
4644 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "mps_tcam",
4645 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4646 chip_id(sc) <= CHELSIO_T5 ? sysctl_mps_tcam : sysctl_mps_tcam_t6,
4647 "A", "MPS TCAM entries");
4649 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "path_mtus",
4650 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4651 sysctl_path_mtus, "A", "path MTUs");
4653 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pm_stats",
4654 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4655 sysctl_pm_stats, "A", "PM statistics");
4657 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rdma_stats",
4658 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4659 sysctl_rdma_stats, "A", "RDMA statistics");
4661 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tcp_stats",
4662 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4663 sysctl_tcp_stats, "A", "TCP statistics");
4665 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tids",
4666 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4667 sysctl_tids, "A", "TID information");
4669 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_err_stats",
4670 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4671 sysctl_tp_err_stats, "A", "TP error statistics");
4673 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la_mask",
4674 CTLTYPE_INT | CTLFLAG_RW, sc, 0, sysctl_tp_la_mask, "I",
4675 "TP logic analyzer event capture mask");
4677 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tp_la",
4678 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4679 sysctl_tp_la, "A", "TP logic analyzer");
4681 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_rate",
4682 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4683 sysctl_tx_rate, "A", "Tx rate");
4685 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "ulprx_la",
4686 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4687 sysctl_ulprx_la, "A", "ULPRX logic analyzer");
4690 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "wcwr_stats",
4691 CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
4692 sysctl_wcwr_stats, "A", "write combined work requests");
4697 if (is_offload(sc)) {
4701 oid = SYSCTL_ADD_NODE(ctx, c0, OID_AUTO, "toe", CTLFLAG_RD,
4702 NULL, "TOE parameters");
4703 children = SYSCTL_CHILDREN(oid);
4705 sc->tt.sndbuf = 256 * 1024;
4706 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "sndbuf", CTLFLAG_RW,
4707 &sc->tt.sndbuf, 0, "max hardware send buffer size");
4710 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp", CTLFLAG_RW,
4711 &sc->tt.ddp, 0, "DDP allowed");
4713 sc->tt.indsz = G_INDICATESIZE(t4_read_reg(sc, A_TP_PARA_REG5));
4714 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "indsz", CTLFLAG_RW,
4715 &sc->tt.indsz, 0, "DDP max indicate size allowed");
4718 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2));
4719 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ddp_thres", CTLFLAG_RW,
4720 &sc->tt.ddp_thres, 0, "DDP threshold");
4722 sc->tt.rx_coalesce = 1;
4723 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "rx_coalesce",
4724 CTLFLAG_RW, &sc->tt.rx_coalesce, 0, "receive coalescing");
4726 sc->tt.tx_align = 1;
4727 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "tx_align",
4728 CTLFLAG_RW, &sc->tt.tx_align, 0, "chop and align payload");
4730 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timer_tick",
4731 CTLTYPE_STRING | CTLFLAG_RD, sc, 0, sysctl_tp_tick, "A",
4732 "TP timer tick (us)");
4734 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "timestamp_tick",
4735 CTLTYPE_STRING | CTLFLAG_RD, sc, 1, sysctl_tp_tick, "A",
4736 "TCP timestamp tick (us)");
4738 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_tick",
4739 CTLTYPE_STRING | CTLFLAG_RD, sc, 2, sysctl_tp_tick, "A",
4742 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "dack_timer",
4743 CTLTYPE_UINT | CTLFLAG_RD, sc, 0, sysctl_tp_dack_timer,
4744 "IU", "DACK timer (us)");
4746 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_min",
4747 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MIN,
4748 sysctl_tp_timer, "LU", "Retransmit min (us)");
4750 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rexmt_max",
4751 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_RXT_MAX,
4752 sysctl_tp_timer, "LU", "Retransmit max (us)");
4754 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_min",
4755 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MIN,
4756 sysctl_tp_timer, "LU", "Persist timer min (us)");
4758 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "persist_max",
4759 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_PERS_MAX,
4760 sysctl_tp_timer, "LU", "Persist timer max (us)");
4762 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_idle",
4763 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_IDLE,
4764 sysctl_tp_timer, "LU", "Keepidle idle timer (us)");
4766 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "keepalive_intvl",
4767 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_KEEP_INTVL,
4768 sysctl_tp_timer, "LU", "Keepidle interval (us)");
4770 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "initial_srtt",
4771 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_INIT_SRTT,
4772 sysctl_tp_timer, "LU", "Initial SRTT (us)");
4774 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "finwait2_timer",
4775 CTLTYPE_ULONG | CTLFLAG_RD, sc, A_TP_FINWAIT2_TIMER,
4776 sysctl_tp_timer, "LU", "FINWAIT2 timer (us)");
4782 vi_sysctls(struct vi_info *vi)
4784 struct sysctl_ctx_list *ctx;
4785 struct sysctl_oid *oid;
4786 struct sysctl_oid_list *children;
4788 ctx = device_get_sysctl_ctx(vi->dev);
4791 * dev.v?(cxgbe|cxl).X.
4793 oid = device_get_sysctl_tree(vi->dev);
4794 children = SYSCTL_CHILDREN(oid);
4796 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "viid", CTLFLAG_RD, NULL,
4797 vi->viid, "VI identifer");
4798 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nrxq", CTLFLAG_RD,
4799 &vi->nrxq, 0, "# of rx queues");
4800 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "ntxq", CTLFLAG_RD,
4801 &vi->ntxq, 0, "# of tx queues");
4802 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_rxq", CTLFLAG_RD,
4803 &vi->first_rxq, 0, "index of first rx queue");
4804 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_txq", CTLFLAG_RD,
4805 &vi->first_txq, 0, "index of first tx queue");
4807 if (IS_MAIN_VI(vi)) {
4808 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rsrv_noflowq",
4809 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_noflowq, "IU",
4810 "Reserve queue 0 for non-flowid packets");
4814 if (vi->nofldrxq != 0) {
4815 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldrxq", CTLFLAG_RD,
4817 "# of rx queues for offloaded TCP connections");
4818 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nofldtxq", CTLFLAG_RD,
4820 "# of tx queues for offloaded TCP connections");
4821 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_rxq",
4822 CTLFLAG_RD, &vi->first_ofld_rxq, 0,
4823 "index of first TOE rx queue");
4824 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_ofld_txq",
4825 CTLFLAG_RD, &vi->first_ofld_txq, 0,
4826 "index of first TOE tx queue");
4830 if (vi->nnmrxq != 0) {
4831 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmrxq", CTLFLAG_RD,
4832 &vi->nnmrxq, 0, "# of netmap rx queues");
4833 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "nnmtxq", CTLFLAG_RD,
4834 &vi->nnmtxq, 0, "# of netmap tx queues");
4835 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_rxq",
4836 CTLFLAG_RD, &vi->first_nm_rxq, 0,
4837 "index of first netmap rx queue");
4838 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "first_nm_txq",
4839 CTLFLAG_RD, &vi->first_nm_txq, 0,
4840 "index of first netmap tx queue");
4844 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_tmr_idx",
4845 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_tmr_idx, "I",
4846 "holdoff timer index");
4847 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "holdoff_pktc_idx",
4848 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_holdoff_pktc_idx, "I",
4849 "holdoff packet counter index");
4851 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_rxq",
4852 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_rxq, "I",
4854 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "qsize_txq",
4855 CTLTYPE_INT | CTLFLAG_RW, vi, 0, sysctl_qsize_txq, "I",
4860 cxgbe_sysctls(struct port_info *pi)
4862 struct sysctl_ctx_list *ctx;
4863 struct sysctl_oid *oid;
4864 struct sysctl_oid_list *children, *children2;
4865 struct adapter *sc = pi->adapter;
4869 ctx = device_get_sysctl_ctx(pi->dev);
4874 oid = device_get_sysctl_tree(pi->dev);
4875 children = SYSCTL_CHILDREN(oid);
4877 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "linkdnrc", CTLTYPE_STRING |
4878 CTLFLAG_RD, pi, 0, sysctl_linkdnrc, "A", "reason why link is down");
4879 if (pi->port_type == FW_PORT_TYPE_BT_XAUI) {
4880 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "temperature",
4881 CTLTYPE_INT | CTLFLAG_RD, pi, 0, sysctl_btphy, "I",
4882 "PHY temperature (in Celsius)");
4883 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "fw_version",
4884 CTLTYPE_INT | CTLFLAG_RD, pi, 1, sysctl_btphy, "I",
4885 "PHY firmware version");
4888 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pause_settings",
4889 CTLTYPE_STRING | CTLFLAG_RW, pi, PAUSE_TX, sysctl_pause_settings,
4890 "A", "PAUSE settings (bit 0 = rx_pause, bit 1 = tx_pause)");
4892 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "max_speed", CTLFLAG_RD, NULL,
4893 port_top_speed(pi), "max speed (in Gbps)");
4896 * dev.(cxgbe|cxl).X.tc.
4898 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "tc", CTLFLAG_RD, NULL,
4899 "Tx scheduler traffic classes");
4900 for (i = 0; i < sc->chip_params->nsched_cls; i++) {
4901 struct tx_sched_class *tc = &pi->tc[i];
4903 snprintf(name, sizeof(name), "%d", i);
4904 children2 = SYSCTL_CHILDREN(SYSCTL_ADD_NODE(ctx,
4905 SYSCTL_CHILDREN(oid), OID_AUTO, name, CTLFLAG_RD, NULL,
4907 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "flags", CTLFLAG_RD,
4908 &tc->flags, 0, "flags");
4909 SYSCTL_ADD_UINT(ctx, children2, OID_AUTO, "refcount",
4910 CTLFLAG_RD, &tc->refcount, 0, "references to this class");
4912 SYSCTL_ADD_PROC(ctx, children2, OID_AUTO, "params",
4913 CTLTYPE_STRING | CTLFLAG_RD, sc, (pi->port_id << 16) | i,
4914 sysctl_tc_params, "A", "traffic class parameters");
4919 * dev.cxgbe.X.stats.
4921 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "stats", CTLFLAG_RD,
4922 NULL, "port statistics");
4923 children = SYSCTL_CHILDREN(oid);
4924 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "tx_parse_error", CTLFLAG_RD,
4925 &pi->tx_parse_error, 0,
4926 "# of tx packets with invalid length or # of segments");
4928 #define SYSCTL_ADD_T4_REG64(pi, name, desc, reg) \
4929 SYSCTL_ADD_OID(ctx, children, OID_AUTO, name, \
4930 CTLTYPE_U64 | CTLFLAG_RD, sc, reg, \
4931 sysctl_handle_t4_reg64, "QU", desc)
4933 SYSCTL_ADD_T4_REG64(pi, "tx_octets", "# of octets in good frames",
4934 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BYTES_L));
4935 SYSCTL_ADD_T4_REG64(pi, "tx_frames", "total # of good frames",
4936 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_FRAMES_L));
4937 SYSCTL_ADD_T4_REG64(pi, "tx_bcast_frames", "# of broadcast frames",
4938 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_BCAST_L));
4939 SYSCTL_ADD_T4_REG64(pi, "tx_mcast_frames", "# of multicast frames",
4940 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_MCAST_L));
4941 SYSCTL_ADD_T4_REG64(pi, "tx_ucast_frames", "# of unicast frames",
4942 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_UCAST_L));
4943 SYSCTL_ADD_T4_REG64(pi, "tx_error_frames", "# of error frames",
4944 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_ERROR_L));
4945 SYSCTL_ADD_T4_REG64(pi, "tx_frames_64",
4946 "# of tx frames in this range",
4947 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_64B_L));
4948 SYSCTL_ADD_T4_REG64(pi, "tx_frames_65_127",
4949 "# of tx frames in this range",
4950 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_65B_127B_L));
4951 SYSCTL_ADD_T4_REG64(pi, "tx_frames_128_255",
4952 "# of tx frames in this range",
4953 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_128B_255B_L));
4954 SYSCTL_ADD_T4_REG64(pi, "tx_frames_256_511",
4955 "# of tx frames in this range",
4956 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_256B_511B_L));
4957 SYSCTL_ADD_T4_REG64(pi, "tx_frames_512_1023",
4958 "# of tx frames in this range",
4959 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_512B_1023B_L));
4960 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1024_1518",
4961 "# of tx frames in this range",
4962 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1024B_1518B_L));
4963 SYSCTL_ADD_T4_REG64(pi, "tx_frames_1519_max",
4964 "# of tx frames in this range",
4965 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_1519B_MAX_L));
4966 SYSCTL_ADD_T4_REG64(pi, "tx_drop", "# of dropped tx frames",
4967 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_DROP_L));
4968 SYSCTL_ADD_T4_REG64(pi, "tx_pause", "# of pause frames transmitted",
4969 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PAUSE_L));
4970 SYSCTL_ADD_T4_REG64(pi, "tx_ppp0", "# of PPP prio 0 frames transmitted",
4971 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP0_L));
4972 SYSCTL_ADD_T4_REG64(pi, "tx_ppp1", "# of PPP prio 1 frames transmitted",
4973 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP1_L));
4974 SYSCTL_ADD_T4_REG64(pi, "tx_ppp2", "# of PPP prio 2 frames transmitted",
4975 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP2_L));
4976 SYSCTL_ADD_T4_REG64(pi, "tx_ppp3", "# of PPP prio 3 frames transmitted",
4977 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP3_L));
4978 SYSCTL_ADD_T4_REG64(pi, "tx_ppp4", "# of PPP prio 4 frames transmitted",
4979 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP4_L));
4980 SYSCTL_ADD_T4_REG64(pi, "tx_ppp5", "# of PPP prio 5 frames transmitted",
4981 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP5_L));
4982 SYSCTL_ADD_T4_REG64(pi, "tx_ppp6", "# of PPP prio 6 frames transmitted",
4983 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP6_L));
4984 SYSCTL_ADD_T4_REG64(pi, "tx_ppp7", "# of PPP prio 7 frames transmitted",
4985 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_TX_PORT_PPP7_L));
4987 SYSCTL_ADD_T4_REG64(pi, "rx_octets", "# of octets in good frames",
4988 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BYTES_L));
4989 SYSCTL_ADD_T4_REG64(pi, "rx_frames", "total # of good frames",
4990 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_FRAMES_L));
4991 SYSCTL_ADD_T4_REG64(pi, "rx_bcast_frames", "# of broadcast frames",
4992 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_BCAST_L));
4993 SYSCTL_ADD_T4_REG64(pi, "rx_mcast_frames", "# of multicast frames",
4994 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MCAST_L));
4995 SYSCTL_ADD_T4_REG64(pi, "rx_ucast_frames", "# of unicast frames",
4996 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_UCAST_L));
4997 SYSCTL_ADD_T4_REG64(pi, "rx_too_long", "# of frames exceeding MTU",
4998 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L));
4999 SYSCTL_ADD_T4_REG64(pi, "rx_jabber", "# of jabber frames",
5000 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L));
5001 SYSCTL_ADD_T4_REG64(pi, "rx_fcs_err",
5002 "# of frames received with bad FCS",
5003 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L));
5004 SYSCTL_ADD_T4_REG64(pi, "rx_len_err",
5005 "# of frames received with length error",
5006 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L));
5007 SYSCTL_ADD_T4_REG64(pi, "rx_symbol_err", "symbol errors",
5008 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L));
5009 SYSCTL_ADD_T4_REG64(pi, "rx_runt", "# of short frames received",
5010 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_LESS_64B_L));
5011 SYSCTL_ADD_T4_REG64(pi, "rx_frames_64",
5012 "# of rx frames in this range",
5013 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_64B_L));
5014 SYSCTL_ADD_T4_REG64(pi, "rx_frames_65_127",
5015 "# of rx frames in this range",
5016 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_65B_127B_L));
5017 SYSCTL_ADD_T4_REG64(pi, "rx_frames_128_255",
5018 "# of rx frames in this range",
5019 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_128B_255B_L));
5020 SYSCTL_ADD_T4_REG64(pi, "rx_frames_256_511",
5021 "# of rx frames in this range",
5022 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_256B_511B_L));
5023 SYSCTL_ADD_T4_REG64(pi, "rx_frames_512_1023",
5024 "# of rx frames in this range",
5025 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_512B_1023B_L));
5026 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1024_1518",
5027 "# of rx frames in this range",
5028 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1024B_1518B_L));
5029 SYSCTL_ADD_T4_REG64(pi, "rx_frames_1519_max",
5030 "# of rx frames in this range",
5031 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_1519B_MAX_L));
5032 SYSCTL_ADD_T4_REG64(pi, "rx_pause", "# of pause frames received",
5033 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PAUSE_L));
5034 SYSCTL_ADD_T4_REG64(pi, "rx_ppp0", "# of PPP prio 0 frames received",
5035 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP0_L));
5036 SYSCTL_ADD_T4_REG64(pi, "rx_ppp1", "# of PPP prio 1 frames received",
5037 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP1_L));
5038 SYSCTL_ADD_T4_REG64(pi, "rx_ppp2", "# of PPP prio 2 frames received",
5039 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP2_L));
5040 SYSCTL_ADD_T4_REG64(pi, "rx_ppp3", "# of PPP prio 3 frames received",
5041 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP3_L));
5042 SYSCTL_ADD_T4_REG64(pi, "rx_ppp4", "# of PPP prio 4 frames received",
5043 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP4_L));
5044 SYSCTL_ADD_T4_REG64(pi, "rx_ppp5", "# of PPP prio 5 frames received",
5045 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP5_L));
5046 SYSCTL_ADD_T4_REG64(pi, "rx_ppp6", "# of PPP prio 6 frames received",
5047 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP6_L));
5048 SYSCTL_ADD_T4_REG64(pi, "rx_ppp7", "# of PPP prio 7 frames received",
5049 PORT_REG(pi->tx_chan, A_MPS_PORT_STAT_RX_PORT_PPP7_L));
5051 #undef SYSCTL_ADD_T4_REG64
5053 #define SYSCTL_ADD_T4_PORTSTAT(name, desc) \
5054 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, #name, CTLFLAG_RD, \
5055 &pi->stats.name, desc)
5057 /* We get these from port_stats and they may be stale by upto 1s */
5058 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow0,
5059 "# drops due to buffer-group 0 overflows");
5060 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow1,
5061 "# drops due to buffer-group 1 overflows");
5062 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow2,
5063 "# drops due to buffer-group 2 overflows");
5064 SYSCTL_ADD_T4_PORTSTAT(rx_ovflow3,
5065 "# drops due to buffer-group 3 overflows");
5066 SYSCTL_ADD_T4_PORTSTAT(rx_trunc0,
5067 "# of buffer-group 0 truncated packets");
5068 SYSCTL_ADD_T4_PORTSTAT(rx_trunc1,
5069 "# of buffer-group 1 truncated packets");
5070 SYSCTL_ADD_T4_PORTSTAT(rx_trunc2,
5071 "# of buffer-group 2 truncated packets");
5072 SYSCTL_ADD_T4_PORTSTAT(rx_trunc3,
5073 "# of buffer-group 3 truncated packets");
5075 #undef SYSCTL_ADD_T4_PORTSTAT
5079 sysctl_int_array(SYSCTL_HANDLER_ARGS)
5081 int rc, *i, space = 0;
5084 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
5085 for (i = arg1; arg2; arg2 -= sizeof(int), i++) {
5087 sbuf_printf(&sb, " ");
5088 sbuf_printf(&sb, "%d", *i);
5092 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);
5098 sysctl_bitfield(SYSCTL_HANDLER_ARGS)
5103 rc = sysctl_wire_old_buffer(req, 0);
5107 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5111 sbuf_printf(sb, "%b", (int)arg2, (char *)arg1);
5112 rc = sbuf_finish(sb);
5119 sysctl_btphy(SYSCTL_HANDLER_ARGS)
5121 struct port_info *pi = arg1;
5123 struct adapter *sc = pi->adapter;
5127 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK, "t4btt");
5130 /* XXX: magic numbers */
5131 rc = -t4_mdio_rd(sc, sc->mbox, pi->mdio_addr, 0x1e, op ? 0x20 : 0xc820,
5133 end_synchronized_op(sc, 0);
5139 rc = sysctl_handle_int(oidp, &v, 0, req);
5144 sysctl_noflowq(SYSCTL_HANDLER_ARGS)
5146 struct vi_info *vi = arg1;
5149 val = vi->rsrv_noflowq;
5150 rc = sysctl_handle_int(oidp, &val, 0, req);
5151 if (rc != 0 || req->newptr == NULL)
5154 if ((val >= 1) && (vi->ntxq > 1))
5155 vi->rsrv_noflowq = 1;
5157 vi->rsrv_noflowq = 0;
5163 sysctl_holdoff_tmr_idx(SYSCTL_HANDLER_ARGS)
5165 struct vi_info *vi = arg1;
5166 struct adapter *sc = vi->pi->adapter;
5168 struct sge_rxq *rxq;
5170 struct sge_ofld_rxq *ofld_rxq;
5176 rc = sysctl_handle_int(oidp, &idx, 0, req);
5177 if (rc != 0 || req->newptr == NULL)
5180 if (idx < 0 || idx >= SGE_NTIMERS)
5183 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5188 v = V_QINTR_TIMER_IDX(idx) | V_QINTR_CNT_EN(vi->pktc_idx != -1);
5189 for_each_rxq(vi, i, rxq) {
5190 #ifdef atomic_store_rel_8
5191 atomic_store_rel_8(&rxq->iq.intr_params, v);
5193 rxq->iq.intr_params = v;
5197 for_each_ofld_rxq(vi, i, ofld_rxq) {
5198 #ifdef atomic_store_rel_8
5199 atomic_store_rel_8(&ofld_rxq->iq.intr_params, v);
5201 ofld_rxq->iq.intr_params = v;
5207 end_synchronized_op(sc, LOCK_HELD);
5212 sysctl_holdoff_pktc_idx(SYSCTL_HANDLER_ARGS)
5214 struct vi_info *vi = arg1;
5215 struct adapter *sc = vi->pi->adapter;
5220 rc = sysctl_handle_int(oidp, &idx, 0, req);
5221 if (rc != 0 || req->newptr == NULL)
5224 if (idx < -1 || idx >= SGE_NCOUNTERS)
5227 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5232 if (vi->flags & VI_INIT_DONE)
5233 rc = EBUSY; /* cannot be changed once the queues are created */
5237 end_synchronized_op(sc, LOCK_HELD);
5242 sysctl_qsize_rxq(SYSCTL_HANDLER_ARGS)
5244 struct vi_info *vi = arg1;
5245 struct adapter *sc = vi->pi->adapter;
5248 qsize = vi->qsize_rxq;
5250 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5251 if (rc != 0 || req->newptr == NULL)
5254 if (qsize < 128 || (qsize & 7))
5257 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5262 if (vi->flags & VI_INIT_DONE)
5263 rc = EBUSY; /* cannot be changed once the queues are created */
5265 vi->qsize_rxq = qsize;
5267 end_synchronized_op(sc, LOCK_HELD);
5272 sysctl_qsize_txq(SYSCTL_HANDLER_ARGS)
5274 struct vi_info *vi = arg1;
5275 struct adapter *sc = vi->pi->adapter;
5278 qsize = vi->qsize_txq;
5280 rc = sysctl_handle_int(oidp, &qsize, 0, req);
5281 if (rc != 0 || req->newptr == NULL)
5284 if (qsize < 128 || qsize > 65536)
5287 rc = begin_synchronized_op(sc, vi, HOLD_LOCK | SLEEP_OK | INTR_OK,
5292 if (vi->flags & VI_INIT_DONE)
5293 rc = EBUSY; /* cannot be changed once the queues are created */
5295 vi->qsize_txq = qsize;
5297 end_synchronized_op(sc, LOCK_HELD);
5302 sysctl_pause_settings(SYSCTL_HANDLER_ARGS)
5304 struct port_info *pi = arg1;
5305 struct adapter *sc = pi->adapter;
5306 struct link_config *lc = &pi->link_cfg;
5309 if (req->newptr == NULL) {
5311 static char *bits = "\20\1PAUSE_RX\2PAUSE_TX";
5313 rc = sysctl_wire_old_buffer(req, 0);
5317 sb = sbuf_new_for_sysctl(NULL, NULL, 128, req);
5321 sbuf_printf(sb, "%b", lc->fc & (PAUSE_TX | PAUSE_RX), bits);
5322 rc = sbuf_finish(sb);
5328 s[0] = '0' + (lc->requested_fc & (PAUSE_TX | PAUSE_RX));
5331 rc = sysctl_handle_string(oidp, s, sizeof(s), req);
5337 if (s[0] < '0' || s[0] > '9')
5338 return (EINVAL); /* not a number */
5340 if (n & ~(PAUSE_TX | PAUSE_RX))
5341 return (EINVAL); /* some other bit is set too */
5343 rc = begin_synchronized_op(sc, &pi->vi[0], SLEEP_OK | INTR_OK,
5347 if ((lc->requested_fc & (PAUSE_TX | PAUSE_RX)) != n) {
5348 int link_ok = lc->link_ok;
5350 lc->requested_fc &= ~(PAUSE_TX | PAUSE_RX);
5351 lc->requested_fc |= n;
5352 rc = -t4_link_l1cfg(sc, sc->mbox, pi->tx_chan, lc);
5353 lc->link_ok = link_ok; /* restore */
5355 end_synchronized_op(sc, 0);
5362 sysctl_handle_t4_reg64(SYSCTL_HANDLER_ARGS)
5364 struct adapter *sc = arg1;
5368 val = t4_read_reg64(sc, reg);
5370 return (sysctl_handle_64(oidp, &val, 0, req));
5374 sysctl_temperature(SYSCTL_HANDLER_ARGS)
5376 struct adapter *sc = arg1;
5378 uint32_t param, val;
5380 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4temp");
5383 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) |
5384 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_DIAG) |
5385 V_FW_PARAMS_PARAM_Y(FW_PARAM_DEV_DIAG_TMP);
5386 rc = -t4_query_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
5387 end_synchronized_op(sc, 0);
5391 /* unknown is returned as 0 but we display -1 in that case */
5392 t = val == 0 ? -1 : val;
5394 rc = sysctl_handle_int(oidp, &t, 0, req);
5400 sysctl_cctrl(SYSCTL_HANDLER_ARGS)
5402 struct adapter *sc = arg1;
5405 uint16_t incr[NMTUS][NCCTRL_WIN];
5406 static const char *dec_fac[] = {
5407 "0.5", "0.5625", "0.625", "0.6875", "0.75", "0.8125", "0.875",
5411 rc = sysctl_wire_old_buffer(req, 0);
5415 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5419 t4_read_cong_tbl(sc, incr);
5421 for (i = 0; i < NCCTRL_WIN; ++i) {
5422 sbuf_printf(sb, "%2d: %4u %4u %4u %4u %4u %4u %4u %4u\n", i,
5423 incr[0][i], incr[1][i], incr[2][i], incr[3][i], incr[4][i],
5424 incr[5][i], incr[6][i], incr[7][i]);
5425 sbuf_printf(sb, "%8u %4u %4u %4u %4u %4u %4u %4u %5u %s\n",
5426 incr[8][i], incr[9][i], incr[10][i], incr[11][i],
5427 incr[12][i], incr[13][i], incr[14][i], incr[15][i],
5428 sc->params.a_wnd[i], dec_fac[sc->params.b_wnd[i]]);
5431 rc = sbuf_finish(sb);
5437 static const char *qname[CIM_NUM_IBQ + CIM_NUM_OBQ_T5] = {
5438 "TP0", "TP1", "ULP", "SGE0", "SGE1", "NC-SI", /* ibq's */
5439 "ULP0", "ULP1", "ULP2", "ULP3", "SGE", "NC-SI", /* obq's */
5440 "SGE0-RX", "SGE1-RX" /* additional obq's (T5 onwards) */
5444 sysctl_cim_ibq_obq(SYSCTL_HANDLER_ARGS)
5446 struct adapter *sc = arg1;
5448 int rc, i, n, qid = arg2;
5451 u_int cim_num_obq = sc->chip_params->cim_num_obq;
5453 KASSERT(qid >= 0 && qid < CIM_NUM_IBQ + cim_num_obq,
5454 ("%s: bad qid %d\n", __func__, qid));
5456 if (qid < CIM_NUM_IBQ) {
5459 n = 4 * CIM_IBQ_SIZE;
5460 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5461 rc = t4_read_cim_ibq(sc, qid, buf, n);
5463 /* outbound queue */
5466 n = 4 * cim_num_obq * CIM_OBQ_SIZE;
5467 buf = malloc(n * sizeof(uint32_t), M_CXGBE, M_ZERO | M_WAITOK);
5468 rc = t4_read_cim_obq(sc, qid, buf, n);
5475 n = rc * sizeof(uint32_t); /* rc has # of words actually read */
5477 rc = sysctl_wire_old_buffer(req, 0);
5481 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5487 sbuf_printf(sb, "%s%d %s", qtype , qid, qname[arg2]);
5488 for (i = 0, p = buf; i < n; i += 16, p += 4)
5489 sbuf_printf(sb, "\n%#06x: %08x %08x %08x %08x", i, p[0], p[1],
5492 rc = sbuf_finish(sb);
5500 sysctl_cim_la(SYSCTL_HANDLER_ARGS)
5502 struct adapter *sc = arg1;
5508 MPASS(chip_id(sc) <= CHELSIO_T5);
5510 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5514 rc = sysctl_wire_old_buffer(req, 0);
5518 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5522 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5525 rc = -t4_cim_read_la(sc, buf, NULL);
5529 sbuf_printf(sb, "Status Data PC%s",
5530 cfg & F_UPDBGLACAPTPCONLY ? "" :
5531 " LS0Stat LS0Addr LS0Data");
5533 for (p = buf; p <= &buf[sc->params.cim_la_size - 8]; p += 8) {
5534 if (cfg & F_UPDBGLACAPTPCONLY) {
5535 sbuf_printf(sb, "\n %02x %08x %08x", p[5] & 0xff,
5537 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x",
5538 (p[3] >> 8) & 0xff, p[3] & 0xff, p[4] >> 8,
5539 p[4] & 0xff, p[5] >> 8);
5540 sbuf_printf(sb, "\n %02x %x%07x %x%07x",
5541 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5542 p[1] & 0xf, p[2] >> 4);
5545 "\n %02x %x%07x %x%07x %08x %08x "
5547 (p[0] >> 4) & 0xff, p[0] & 0xf, p[1] >> 4,
5548 p[1] & 0xf, p[2] >> 4, p[2] & 0xf, p[3], p[4], p[5],
5553 rc = sbuf_finish(sb);
5561 sysctl_cim_la_t6(SYSCTL_HANDLER_ARGS)
5563 struct adapter *sc = arg1;
5569 MPASS(chip_id(sc) > CHELSIO_T5);
5571 rc = -t4_cim_read(sc, A_UP_UP_DBG_LA_CFG, 1, &cfg);
5575 rc = sysctl_wire_old_buffer(req, 0);
5579 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5583 buf = malloc(sc->params.cim_la_size * sizeof(uint32_t), M_CXGBE,
5586 rc = -t4_cim_read_la(sc, buf, NULL);
5590 sbuf_printf(sb, "Status Inst Data PC%s",
5591 cfg & F_UPDBGLACAPTPCONLY ? "" :
5592 " LS0Stat LS0Addr LS0Data LS1Stat LS1Addr LS1Data");
5594 for (p = buf; p <= &buf[sc->params.cim_la_size - 10]; p += 10) {
5595 if (cfg & F_UPDBGLACAPTPCONLY) {
5596 sbuf_printf(sb, "\n %02x %08x %08x %08x",
5597 p[3] & 0xff, p[2], p[1], p[0]);
5598 sbuf_printf(sb, "\n %02x %02x%06x %02x%06x %02x%06x",
5599 (p[6] >> 8) & 0xff, p[6] & 0xff, p[5] >> 8,
5600 p[5] & 0xff, p[4] >> 8, p[4] & 0xff, p[3] >> 8);
5601 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x",
5602 (p[9] >> 16) & 0xff, p[9] & 0xffff, p[8] >> 16,
5603 p[8] & 0xffff, p[7] >> 16, p[7] & 0xffff,
5606 sbuf_printf(sb, "\n %02x %04x%04x %04x%04x %04x%04x "
5607 "%08x %08x %08x %08x %08x %08x",
5608 (p[9] >> 16) & 0xff,
5609 p[9] & 0xffff, p[8] >> 16,
5610 p[8] & 0xffff, p[7] >> 16,
5611 p[7] & 0xffff, p[6] >> 16,
5612 p[2], p[1], p[0], p[5], p[4], p[3]);
5616 rc = sbuf_finish(sb);
5624 sysctl_cim_ma_la(SYSCTL_HANDLER_ARGS)
5626 struct adapter *sc = arg1;
5632 rc = sysctl_wire_old_buffer(req, 0);
5636 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5640 buf = malloc(2 * CIM_MALA_SIZE * 5 * sizeof(uint32_t), M_CXGBE,
5643 t4_cim_read_ma_la(sc, buf, buf + 5 * CIM_MALA_SIZE);
5646 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5647 sbuf_printf(sb, "\n%02x%08x%08x%08x%08x", p[4], p[3], p[2],
5651 sbuf_printf(sb, "\n\nCnt ID Tag UE Data RDY VLD");
5652 for (i = 0; i < CIM_MALA_SIZE; i++, p += 5) {
5653 sbuf_printf(sb, "\n%3u %2u %x %u %08x%08x %u %u",
5654 (p[2] >> 10) & 0xff, (p[2] >> 7) & 7,
5655 (p[2] >> 3) & 0xf, (p[2] >> 2) & 1,
5656 (p[1] >> 2) | ((p[2] & 3) << 30),
5657 (p[0] >> 2) | ((p[1] & 3) << 30), (p[0] >> 1) & 1,
5661 rc = sbuf_finish(sb);
5668 sysctl_cim_pif_la(SYSCTL_HANDLER_ARGS)
5670 struct adapter *sc = arg1;
5676 rc = sysctl_wire_old_buffer(req, 0);
5680 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5684 buf = malloc(2 * CIM_PIFLA_SIZE * 6 * sizeof(uint32_t), M_CXGBE,
5687 t4_cim_read_pif_la(sc, buf, buf + 6 * CIM_PIFLA_SIZE, NULL, NULL);
5690 sbuf_printf(sb, "Cntl ID DataBE Addr Data");
5691 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
5692 sbuf_printf(sb, "\n %02x %02x %04x %08x %08x%08x%08x%08x",
5693 (p[5] >> 22) & 0xff, (p[5] >> 16) & 0x3f, p[5] & 0xffff,
5694 p[4], p[3], p[2], p[1], p[0]);
5697 sbuf_printf(sb, "\n\nCntl ID Data");
5698 for (i = 0; i < CIM_PIFLA_SIZE; i++, p += 6) {
5699 sbuf_printf(sb, "\n %02x %02x %08x%08x%08x%08x",
5700 (p[4] >> 6) & 0xff, p[4] & 0x3f, p[3], p[2], p[1], p[0]);
5703 rc = sbuf_finish(sb);
5710 sysctl_cim_qcfg(SYSCTL_HANDLER_ARGS)
5712 struct adapter *sc = arg1;
5715 uint16_t base[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5716 uint16_t size[CIM_NUM_IBQ + CIM_NUM_OBQ_T5];
5717 uint16_t thres[CIM_NUM_IBQ];
5718 uint32_t obq_wr[2 * CIM_NUM_OBQ_T5], *wr = obq_wr;
5719 uint32_t stat[4 * (CIM_NUM_IBQ + CIM_NUM_OBQ_T5)], *p = stat;
5720 u_int cim_num_obq, ibq_rdaddr, obq_rdaddr, nq;
5722 cim_num_obq = sc->chip_params->cim_num_obq;
5724 ibq_rdaddr = A_UP_IBQ_0_RDADDR;
5725 obq_rdaddr = A_UP_OBQ_0_REALADDR;
5727 ibq_rdaddr = A_UP_IBQ_0_SHADOW_RDADDR;
5728 obq_rdaddr = A_UP_OBQ_0_SHADOW_REALADDR;
5730 nq = CIM_NUM_IBQ + cim_num_obq;
5732 rc = -t4_cim_read(sc, ibq_rdaddr, 4 * nq, stat);
5734 rc = -t4_cim_read(sc, obq_rdaddr, 2 * cim_num_obq, obq_wr);
5738 t4_read_cimq_cfg(sc, base, size, thres);
5740 rc = sysctl_wire_old_buffer(req, 0);
5744 sb = sbuf_new_for_sysctl(NULL, NULL, PAGE_SIZE, req);
5748 sbuf_printf(sb, "Queue Base Size Thres RdPtr WrPtr SOP EOP Avail");
5750 for (i = 0; i < CIM_NUM_IBQ; i++, p += 4)
5751 sbuf_printf(sb, "\n%7s %5x %5u %5u %6x %4x %4u %4u %5u",
5752 qname[i], base[i], size[i], thres[i], G_IBQRDADDR(p[0]),
5753 G_IBQWRADDR(p[1]), G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5754 G_QUEREMFLITS(p[2]) * 16);
5755 for ( ; i < nq; i++, p += 4, wr += 2)
5756 sbuf_printf(sb, "\n%7s %5x %5u %12x %4x %4u %4u %5u", qname[i],
5757 base[i], size[i], G_QUERDADDR(p[0]) & 0x3fff,
5758 wr[0] - base[i], G_QUESOPCNT(p[3]), G_QUEEOPCNT(p[3]),
5759 G_QUEREMFLITS(p[2]) * 16);
5761 rc = sbuf_finish(sb);
5768 sysctl_cpl_stats(SYSCTL_HANDLER_ARGS)
5770 struct adapter *sc = arg1;
5773 struct tp_cpl_stats stats;
5775 rc = sysctl_wire_old_buffer(req, 0);
5779 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5783 mtx_lock(&sc->reg_lock);
5784 t4_tp_get_cpl_stats(sc, &stats);
5785 mtx_unlock(&sc->reg_lock);
5787 if (sc->chip_params->nchan > 2) {
5788 sbuf_printf(sb, " channel 0 channel 1"
5789 " channel 2 channel 3");
5790 sbuf_printf(sb, "\nCPL requests: %10u %10u %10u %10u",
5791 stats.req[0], stats.req[1], stats.req[2], stats.req[3]);
5792 sbuf_printf(sb, "\nCPL responses: %10u %10u %10u %10u",
5793 stats.rsp[0], stats.rsp[1], stats.rsp[2], stats.rsp[3]);
5795 sbuf_printf(sb, " channel 0 channel 1");
5796 sbuf_printf(sb, "\nCPL requests: %10u %10u",
5797 stats.req[0], stats.req[1]);
5798 sbuf_printf(sb, "\nCPL responses: %10u %10u",
5799 stats.rsp[0], stats.rsp[1]);
5802 rc = sbuf_finish(sb);
5809 sysctl_ddp_stats(SYSCTL_HANDLER_ARGS)
5811 struct adapter *sc = arg1;
5814 struct tp_usm_stats stats;
5816 rc = sysctl_wire_old_buffer(req, 0);
5820 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5824 t4_get_usm_stats(sc, &stats);
5826 sbuf_printf(sb, "Frames: %u\n", stats.frames);
5827 sbuf_printf(sb, "Octets: %ju\n", stats.octets);
5828 sbuf_printf(sb, "Drops: %u", stats.drops);
5830 rc = sbuf_finish(sb);
5836 static const char * const devlog_level_strings[] = {
5837 [FW_DEVLOG_LEVEL_EMERG] = "EMERG",
5838 [FW_DEVLOG_LEVEL_CRIT] = "CRIT",
5839 [FW_DEVLOG_LEVEL_ERR] = "ERR",
5840 [FW_DEVLOG_LEVEL_NOTICE] = "NOTICE",
5841 [FW_DEVLOG_LEVEL_INFO] = "INFO",
5842 [FW_DEVLOG_LEVEL_DEBUG] = "DEBUG"
5845 static const char * const devlog_facility_strings[] = {
5846 [FW_DEVLOG_FACILITY_CORE] = "CORE",
5847 [FW_DEVLOG_FACILITY_CF] = "CF",
5848 [FW_DEVLOG_FACILITY_SCHED] = "SCHED",
5849 [FW_DEVLOG_FACILITY_TIMER] = "TIMER",
5850 [FW_DEVLOG_FACILITY_RES] = "RES",
5851 [FW_DEVLOG_FACILITY_HW] = "HW",
5852 [FW_DEVLOG_FACILITY_FLR] = "FLR",
5853 [FW_DEVLOG_FACILITY_DMAQ] = "DMAQ",
5854 [FW_DEVLOG_FACILITY_PHY] = "PHY",
5855 [FW_DEVLOG_FACILITY_MAC] = "MAC",
5856 [FW_DEVLOG_FACILITY_PORT] = "PORT",
5857 [FW_DEVLOG_FACILITY_VI] = "VI",
5858 [FW_DEVLOG_FACILITY_FILTER] = "FILTER",
5859 [FW_DEVLOG_FACILITY_ACL] = "ACL",
5860 [FW_DEVLOG_FACILITY_TM] = "TM",
5861 [FW_DEVLOG_FACILITY_QFC] = "QFC",
5862 [FW_DEVLOG_FACILITY_DCB] = "DCB",
5863 [FW_DEVLOG_FACILITY_ETH] = "ETH",
5864 [FW_DEVLOG_FACILITY_OFLD] = "OFLD",
5865 [FW_DEVLOG_FACILITY_RI] = "RI",
5866 [FW_DEVLOG_FACILITY_ISCSI] = "ISCSI",
5867 [FW_DEVLOG_FACILITY_FCOE] = "FCOE",
5868 [FW_DEVLOG_FACILITY_FOISCSI] = "FOISCSI",
5869 [FW_DEVLOG_FACILITY_FOFCOE] = "FOFCOE",
5870 [FW_DEVLOG_FACILITY_CHNET] = "CHNET",
5874 sysctl_devlog(SYSCTL_HANDLER_ARGS)
5876 struct adapter *sc = arg1;
5877 struct devlog_params *dparams = &sc->params.devlog;
5878 struct fw_devlog_e *buf, *e;
5879 int i, j, rc, nentries, first = 0;
5881 uint64_t ftstamp = UINT64_MAX;
5883 if (dparams->addr == 0)
5886 buf = malloc(dparams->size, M_CXGBE, M_NOWAIT);
5890 rc = read_via_memwin(sc, 1, dparams->addr, (void *)buf, dparams->size);
5894 nentries = dparams->size / sizeof(struct fw_devlog_e);
5895 for (i = 0; i < nentries; i++) {
5898 if (e->timestamp == 0)
5901 e->timestamp = be64toh(e->timestamp);
5902 e->seqno = be32toh(e->seqno);
5903 for (j = 0; j < 8; j++)
5904 e->params[j] = be32toh(e->params[j]);
5906 if (e->timestamp < ftstamp) {
5907 ftstamp = e->timestamp;
5912 if (buf[first].timestamp == 0)
5913 goto done; /* nothing in the log */
5915 rc = sysctl_wire_old_buffer(req, 0);
5919 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
5924 sbuf_printf(sb, "%10s %15s %8s %8s %s\n",
5925 "Seq#", "Tstamp", "Level", "Facility", "Message");
5930 if (e->timestamp == 0)
5933 sbuf_printf(sb, "%10d %15ju %8s %8s ",
5934 e->seqno, e->timestamp,
5935 (e->level < nitems(devlog_level_strings) ?
5936 devlog_level_strings[e->level] : "UNKNOWN"),
5937 (e->facility < nitems(devlog_facility_strings) ?
5938 devlog_facility_strings[e->facility] : "UNKNOWN"));
5939 sbuf_printf(sb, e->fmt, e->params[0], e->params[1],
5940 e->params[2], e->params[3], e->params[4],
5941 e->params[5], e->params[6], e->params[7]);
5943 if (++i == nentries)
5945 } while (i != first);
5947 rc = sbuf_finish(sb);
5955 sysctl_fcoe_stats(SYSCTL_HANDLER_ARGS)
5957 struct adapter *sc = arg1;
5960 struct tp_fcoe_stats stats[MAX_NCHAN];
5961 int i, nchan = sc->chip_params->nchan;
5963 rc = sysctl_wire_old_buffer(req, 0);
5967 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
5971 for (i = 0; i < nchan; i++)
5972 t4_get_fcoe_stats(sc, i, &stats[i]);
5975 sbuf_printf(sb, " channel 0 channel 1"
5976 " channel 2 channel 3");
5977 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju %16ju %16ju",
5978 stats[0].octets_ddp, stats[1].octets_ddp,
5979 stats[2].octets_ddp, stats[3].octets_ddp);
5980 sbuf_printf(sb, "\nframesDDP: %16u %16u %16u %16u",
5981 stats[0].frames_ddp, stats[1].frames_ddp,
5982 stats[2].frames_ddp, stats[3].frames_ddp);
5983 sbuf_printf(sb, "\nframesDrop: %16u %16u %16u %16u",
5984 stats[0].frames_drop, stats[1].frames_drop,
5985 stats[2].frames_drop, stats[3].frames_drop);
5987 sbuf_printf(sb, " channel 0 channel 1");
5988 sbuf_printf(sb, "\noctetsDDP: %16ju %16ju",
5989 stats[0].octets_ddp, stats[1].octets_ddp);
5990 sbuf_printf(sb, "\nframesDDP: %16u %16u",
5991 stats[0].frames_ddp, stats[1].frames_ddp);
5992 sbuf_printf(sb, "\nframesDrop: %16u %16u",
5993 stats[0].frames_drop, stats[1].frames_drop);
5996 rc = sbuf_finish(sb);
6003 sysctl_hw_sched(SYSCTL_HANDLER_ARGS)
6005 struct adapter *sc = arg1;
6008 unsigned int map, kbps, ipg, mode;
6009 unsigned int pace_tab[NTX_SCHED];
6011 rc = sysctl_wire_old_buffer(req, 0);
6015 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6019 map = t4_read_reg(sc, A_TP_TX_MOD_QUEUE_REQ_MAP);
6020 mode = G_TIMERMODE(t4_read_reg(sc, A_TP_MOD_CONFIG));
6021 t4_read_pace_tbl(sc, pace_tab);
6023 sbuf_printf(sb, "Scheduler Mode Channel Rate (Kbps) "
6024 "Class IPG (0.1 ns) Flow IPG (us)");
6026 for (i = 0; i < NTX_SCHED; ++i, map >>= 2) {
6027 t4_get_tx_sched(sc, i, &kbps, &ipg);
6028 sbuf_printf(sb, "\n %u %-5s %u ", i,
6029 (mode & (1 << i)) ? "flow" : "class", map & 3);
6031 sbuf_printf(sb, "%9u ", kbps);
6033 sbuf_printf(sb, " disabled ");
6036 sbuf_printf(sb, "%13u ", ipg);
6038 sbuf_printf(sb, " disabled ");
6041 sbuf_printf(sb, "%10u", pace_tab[i]);
6043 sbuf_printf(sb, " disabled");
6046 rc = sbuf_finish(sb);
6053 sysctl_lb_stats(SYSCTL_HANDLER_ARGS)
6055 struct adapter *sc = arg1;
6059 struct lb_port_stats s[2];
6060 static const char *stat_name[] = {
6061 "OctetsOK:", "FramesOK:", "BcastFrames:", "McastFrames:",
6062 "UcastFrames:", "ErrorFrames:", "Frames64:", "Frames65To127:",
6063 "Frames128To255:", "Frames256To511:", "Frames512To1023:",
6064 "Frames1024To1518:", "Frames1519ToMax:", "FramesDropped:",
6065 "BG0FramesDropped:", "BG1FramesDropped:", "BG2FramesDropped:",
6066 "BG3FramesDropped:", "BG0FramesTrunc:", "BG1FramesTrunc:",
6067 "BG2FramesTrunc:", "BG3FramesTrunc:"
6070 rc = sysctl_wire_old_buffer(req, 0);
6074 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6078 memset(s, 0, sizeof(s));
6080 for (i = 0; i < sc->chip_params->nchan; i += 2) {
6081 t4_get_lb_stats(sc, i, &s[0]);
6082 t4_get_lb_stats(sc, i + 1, &s[1]);
6086 sbuf_printf(sb, "%s Loopback %u"
6087 " Loopback %u", i == 0 ? "" : "\n", i, i + 1);
6089 for (j = 0; j < nitems(stat_name); j++)
6090 sbuf_printf(sb, "\n%-17s %20ju %20ju", stat_name[j],
6094 rc = sbuf_finish(sb);
6101 sysctl_linkdnrc(SYSCTL_HANDLER_ARGS)
6104 struct port_info *pi = arg1;
6107 rc = sysctl_wire_old_buffer(req, 0);
6110 sb = sbuf_new_for_sysctl(NULL, NULL, 64, req);
6114 if (pi->linkdnrc < 0)
6115 sbuf_printf(sb, "n/a");
6117 sbuf_printf(sb, "%s", t4_link_down_rc_str(pi->linkdnrc));
6119 rc = sbuf_finish(sb);
6132 mem_desc_cmp(const void *a, const void *b)
6134 return ((const struct mem_desc *)a)->base -
6135 ((const struct mem_desc *)b)->base;
6139 mem_region_show(struct sbuf *sb, const char *name, unsigned int from,
6147 size = to - from + 1;
6151 /* XXX: need humanize_number(3) in libkern for a more readable 'size' */
6152 sbuf_printf(sb, "%-15s %#x-%#x [%u]\n", name, from, to, size);
6156 sysctl_meminfo(SYSCTL_HANDLER_ARGS)
6158 struct adapter *sc = arg1;
6161 uint32_t lo, hi, used, alloc;
6162 static const char *memory[] = {"EDC0:", "EDC1:", "MC:", "MC0:", "MC1:"};
6163 static const char *region[] = {
6164 "DBQ contexts:", "IMSG contexts:", "FLM cache:", "TCBs:",
6165 "Pstructs:", "Timers:", "Rx FL:", "Tx FL:", "Pstruct FL:",
6166 "Tx payload:", "Rx payload:", "LE hash:", "iSCSI region:",
6167 "TDDP region:", "TPT region:", "STAG region:", "RQ region:",
6168 "RQUDP region:", "PBL region:", "TXPBL region:",
6169 "DBVFIFO region:", "ULPRX state:", "ULPTX state:",
6172 struct mem_desc avail[4];
6173 struct mem_desc mem[nitems(region) + 3]; /* up to 3 holes */
6174 struct mem_desc *md = mem;
6176 rc = sysctl_wire_old_buffer(req, 0);
6180 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6184 for (i = 0; i < nitems(mem); i++) {
6189 /* Find and sort the populated memory ranges */
6191 lo = t4_read_reg(sc, A_MA_TARGET_MEM_ENABLE);
6192 if (lo & F_EDRAM0_ENABLE) {
6193 hi = t4_read_reg(sc, A_MA_EDRAM0_BAR);
6194 avail[i].base = G_EDRAM0_BASE(hi) << 20;
6195 avail[i].limit = avail[i].base + (G_EDRAM0_SIZE(hi) << 20);
6199 if (lo & F_EDRAM1_ENABLE) {
6200 hi = t4_read_reg(sc, A_MA_EDRAM1_BAR);
6201 avail[i].base = G_EDRAM1_BASE(hi) << 20;
6202 avail[i].limit = avail[i].base + (G_EDRAM1_SIZE(hi) << 20);
6206 if (lo & F_EXT_MEM_ENABLE) {
6207 hi = t4_read_reg(sc, A_MA_EXT_MEMORY_BAR);
6208 avail[i].base = G_EXT_MEM_BASE(hi) << 20;
6209 avail[i].limit = avail[i].base +
6210 (G_EXT_MEM_SIZE(hi) << 20);
6211 avail[i].idx = is_t5(sc) ? 3 : 2; /* Call it MC0 for T5 */
6214 if (is_t5(sc) && lo & F_EXT_MEM1_ENABLE) {
6215 hi = t4_read_reg(sc, A_MA_EXT_MEMORY1_BAR);
6216 avail[i].base = G_EXT_MEM1_BASE(hi) << 20;
6217 avail[i].limit = avail[i].base +
6218 (G_EXT_MEM1_SIZE(hi) << 20);
6222 if (!i) /* no memory available */
6224 qsort(avail, i, sizeof(struct mem_desc), mem_desc_cmp);
6226 (md++)->base = t4_read_reg(sc, A_SGE_DBQ_CTXT_BADDR);
6227 (md++)->base = t4_read_reg(sc, A_SGE_IMSG_CTXT_BADDR);
6228 (md++)->base = t4_read_reg(sc, A_SGE_FLM_CACHE_BADDR);
6229 (md++)->base = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
6230 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_BASE);
6231 (md++)->base = t4_read_reg(sc, A_TP_CMM_TIMER_BASE);
6232 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_RX_FLST_BASE);
6233 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_TX_FLST_BASE);
6234 (md++)->base = t4_read_reg(sc, A_TP_CMM_MM_PS_FLST_BASE);
6236 /* the next few have explicit upper bounds */
6237 md->base = t4_read_reg(sc, A_TP_PMM_TX_BASE);
6238 md->limit = md->base - 1 +
6239 t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE) *
6240 G_PMTXMAXPAGE(t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE));
6243 md->base = t4_read_reg(sc, A_TP_PMM_RX_BASE);
6244 md->limit = md->base - 1 +
6245 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) *
6246 G_PMRXMAXPAGE(t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE));
6249 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6250 if (chip_id(sc) <= CHELSIO_T5)
6251 md->base = t4_read_reg(sc, A_LE_DB_HASH_TID_BASE);
6253 md->base = t4_read_reg(sc, A_LE_DB_HASH_TBL_BASE_ADDR);
6257 md->idx = nitems(region); /* hide it */
6261 #define ulp_region(reg) \
6262 md->base = t4_read_reg(sc, A_ULP_ ## reg ## _LLIMIT);\
6263 (md++)->limit = t4_read_reg(sc, A_ULP_ ## reg ## _ULIMIT)
6265 ulp_region(RX_ISCSI);
6266 ulp_region(RX_TDDP);
6268 ulp_region(RX_STAG);
6270 ulp_region(RX_RQUDP);
6276 md->idx = nitems(region);
6279 uint32_t sge_ctrl = t4_read_reg(sc, A_SGE_CONTROL2);
6280 uint32_t fifo_size = t4_read_reg(sc, A_SGE_DBVFIFO_SIZE);
6283 if (sge_ctrl & F_VFIFO_ENABLE)
6284 size = G_DBVFIFO_SIZE(fifo_size);
6286 size = G_T6_DBVFIFO_SIZE(fifo_size);
6289 md->base = G_BASEADDR(t4_read_reg(sc,
6290 A_SGE_DBVFIFO_BADDR));
6291 md->limit = md->base + (size << 2) - 1;
6296 md->base = t4_read_reg(sc, A_ULP_RX_CTX_BASE);
6299 md->base = t4_read_reg(sc, A_ULP_TX_ERR_TABLE_BASE);
6303 md->base = sc->vres.ocq.start;
6304 if (sc->vres.ocq.size)
6305 md->limit = md->base + sc->vres.ocq.size - 1;
6307 md->idx = nitems(region); /* hide it */
6310 /* add any address-space holes, there can be up to 3 */
6311 for (n = 0; n < i - 1; n++)
6312 if (avail[n].limit < avail[n + 1].base)
6313 (md++)->base = avail[n].limit;
6315 (md++)->base = avail[n].limit;
6318 qsort(mem, n, sizeof(struct mem_desc), mem_desc_cmp);
6320 for (lo = 0; lo < i; lo++)
6321 mem_region_show(sb, memory[avail[lo].idx], avail[lo].base,
6322 avail[lo].limit - 1);
6324 sbuf_printf(sb, "\n");
6325 for (i = 0; i < n; i++) {
6326 if (mem[i].idx >= nitems(region))
6327 continue; /* skip holes */
6329 mem[i].limit = i < n - 1 ? mem[i + 1].base - 1 : ~0;
6330 mem_region_show(sb, region[mem[i].idx], mem[i].base,
6334 sbuf_printf(sb, "\n");
6335 lo = t4_read_reg(sc, A_CIM_SDRAM_BASE_ADDR);
6336 hi = t4_read_reg(sc, A_CIM_SDRAM_ADDR_SIZE) + lo - 1;
6337 mem_region_show(sb, "uP RAM:", lo, hi);
6339 lo = t4_read_reg(sc, A_CIM_EXTMEM2_BASE_ADDR);
6340 hi = t4_read_reg(sc, A_CIM_EXTMEM2_ADDR_SIZE) + lo - 1;
6341 mem_region_show(sb, "uP Extmem2:", lo, hi);
6343 lo = t4_read_reg(sc, A_TP_PMM_RX_MAX_PAGE);
6344 sbuf_printf(sb, "\n%u Rx pages of size %uKiB for %u channels\n",
6346 t4_read_reg(sc, A_TP_PMM_RX_PAGE_SIZE) >> 10,
6347 (lo & F_PMRXNUMCHN) ? 2 : 1);
6349 lo = t4_read_reg(sc, A_TP_PMM_TX_MAX_PAGE);
6350 hi = t4_read_reg(sc, A_TP_PMM_TX_PAGE_SIZE);
6351 sbuf_printf(sb, "%u Tx pages of size %u%ciB for %u channels\n",
6353 hi >= (1 << 20) ? (hi >> 20) : (hi >> 10),
6354 hi >= (1 << 20) ? 'M' : 'K', 1 << G_PMTXNUMCHN(lo));
6355 sbuf_printf(sb, "%u p-structs\n",
6356 t4_read_reg(sc, A_TP_CMM_MM_MAX_PSTRUCT));
6358 for (i = 0; i < 4; i++) {
6359 if (chip_id(sc) > CHELSIO_T5)
6360 lo = t4_read_reg(sc, A_MPS_RX_MAC_BG_PG_CNT0 + i * 4);
6362 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV0 + i * 4);
6364 used = G_T5_USED(lo);
6365 alloc = G_T5_ALLOC(lo);
6368 alloc = G_ALLOC(lo);
6370 /* For T6 these are MAC buffer groups */
6371 sbuf_printf(sb, "\nPort %d using %u pages out of %u allocated",
6374 for (i = 0; i < sc->chip_params->nchan; i++) {
6375 if (chip_id(sc) > CHELSIO_T5)
6376 lo = t4_read_reg(sc, A_MPS_RX_LPBK_BG_PG_CNT0 + i * 4);
6378 lo = t4_read_reg(sc, A_MPS_RX_PG_RSV4 + i * 4);
6380 used = G_T5_USED(lo);
6381 alloc = G_T5_ALLOC(lo);
6384 alloc = G_ALLOC(lo);
6386 /* For T6 these are MAC buffer groups */
6388 "\nLoopback %d using %u pages out of %u allocated",
6392 rc = sbuf_finish(sb);
6399 tcamxy2valmask(uint64_t x, uint64_t y, uint8_t *addr, uint64_t *mask)
6403 memcpy(addr, (char *)&y + 2, ETHER_ADDR_LEN);
6407 sysctl_mps_tcam(SYSCTL_HANDLER_ARGS)
6409 struct adapter *sc = arg1;
6413 MPASS(chip_id(sc) <= CHELSIO_T5);
6415 rc = sysctl_wire_old_buffer(req, 0);
6419 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6424 "Idx Ethernet address Mask Vld Ports PF"
6425 " VF Replication P0 P1 P2 P3 ML");
6426 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6427 uint64_t tcamx, tcamy, mask;
6428 uint32_t cls_lo, cls_hi;
6429 uint8_t addr[ETHER_ADDR_LEN];
6431 tcamy = t4_read_reg64(sc, MPS_CLS_TCAM_Y_L(i));
6432 tcamx = t4_read_reg64(sc, MPS_CLS_TCAM_X_L(i));
6435 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6436 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6437 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6438 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x %012jx"
6439 " %c %#x%4u%4d", i, addr[0], addr[1], addr[2],
6440 addr[3], addr[4], addr[5], (uintmax_t)mask,
6441 (cls_lo & F_SRAM_VLD) ? 'Y' : 'N',
6442 G_PORTMAP(cls_hi), G_PF(cls_lo),
6443 (cls_lo & F_VF_VALID) ? G_VF(cls_lo) : -1);
6445 if (cls_lo & F_REPLICATE) {
6446 struct fw_ldst_cmd ldst_cmd;
6448 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6449 ldst_cmd.op_to_addrspace =
6450 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6451 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6452 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6453 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6454 ldst_cmd.u.mps.rplc.fid_idx =
6455 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6456 V_FW_LDST_CMD_IDX(i));
6458 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6462 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6463 sizeof(ldst_cmd), &ldst_cmd);
6464 end_synchronized_op(sc, 0);
6467 sbuf_printf(sb, "%36d", rc);
6470 sbuf_printf(sb, " %08x %08x %08x %08x",
6471 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6472 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6473 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6474 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6477 sbuf_printf(sb, "%36s", "");
6479 sbuf_printf(sb, "%4u%3u%3u%3u %#3x", G_SRAM_PRIO0(cls_lo),
6480 G_SRAM_PRIO1(cls_lo), G_SRAM_PRIO2(cls_lo),
6481 G_SRAM_PRIO3(cls_lo), (cls_lo >> S_MULTILISTEN0) & 0xf);
6485 (void) sbuf_finish(sb);
6487 rc = sbuf_finish(sb);
6494 sysctl_mps_tcam_t6(SYSCTL_HANDLER_ARGS)
6496 struct adapter *sc = arg1;
6500 MPASS(chip_id(sc) > CHELSIO_T5);
6502 rc = sysctl_wire_old_buffer(req, 0);
6506 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
6510 sbuf_printf(sb, "Idx Ethernet address Mask VNI Mask"
6511 " IVLAN Vld DIP_Hit Lookup Port Vld Ports PF VF"
6513 " P0 P1 P2 P3 ML\n");
6515 for (i = 0; i < sc->chip_params->mps_tcam_size; i++) {
6516 uint8_t dip_hit, vlan_vld, lookup_type, port_num;
6518 uint64_t tcamx, tcamy, val, mask;
6519 uint32_t cls_lo, cls_hi, ctl, data2, vnix, vniy;
6520 uint8_t addr[ETHER_ADDR_LEN];
6522 ctl = V_CTLREQID(1) | V_CTLCMDTYPE(0) | V_CTLXYBITSEL(0);
6524 ctl |= V_CTLTCAMINDEX(i) | V_CTLTCAMSEL(0);
6526 ctl |= V_CTLTCAMINDEX(i - 256) | V_CTLTCAMSEL(1);
6527 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6528 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6529 tcamy = G_DMACH(val) << 32;
6530 tcamy |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6531 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6532 lookup_type = G_DATALKPTYPE(data2);
6533 port_num = G_DATAPORTNUM(data2);
6534 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6535 /* Inner header VNI */
6536 vniy = ((data2 & F_DATAVIDH2) << 23) |
6537 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6538 dip_hit = data2 & F_DATADIPHIT;
6543 vlan_vld = data2 & F_DATAVIDH2;
6544 ivlan = G_VIDL(val);
6547 ctl |= V_CTLXYBITSEL(1);
6548 t4_write_reg(sc, A_MPS_CLS_TCAM_DATA2_CTL, ctl);
6549 val = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA1_REQ_ID1);
6550 tcamx = G_DMACH(val) << 32;
6551 tcamx |= t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA0_REQ_ID1);
6552 data2 = t4_read_reg(sc, A_MPS_CLS_TCAM_RDATA2_REQ_ID1);
6553 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6554 /* Inner header VNI mask */
6555 vnix = ((data2 & F_DATAVIDH2) << 23) |
6556 (G_DATAVIDH1(data2) << 16) | G_VIDL(val);
6562 tcamxy2valmask(tcamx, tcamy, addr, &mask);
6564 cls_lo = t4_read_reg(sc, MPS_CLS_SRAM_L(i));
6565 cls_hi = t4_read_reg(sc, MPS_CLS_SRAM_H(i));
6567 if (lookup_type && lookup_type != M_DATALKPTYPE) {
6568 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6569 "%012jx %06x %06x - - %3c"
6570 " 'I' %4x %3c %#x%4u%4d", i, addr[0],
6571 addr[1], addr[2], addr[3], addr[4], addr[5],
6572 (uintmax_t)mask, vniy, vnix, dip_hit ? 'Y' : 'N',
6573 port_num, cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6574 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6575 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6577 sbuf_printf(sb, "\n%3u %02x:%02x:%02x:%02x:%02x:%02x "
6578 "%012jx - - ", i, addr[0], addr[1],
6579 addr[2], addr[3], addr[4], addr[5],
6583 sbuf_printf(sb, "%4u Y ", ivlan);
6585 sbuf_printf(sb, " - N ");
6587 sbuf_printf(sb, "- %3c %4x %3c %#x%4u%4d",
6588 lookup_type ? 'I' : 'O', port_num,
6589 cls_lo & F_T6_SRAM_VLD ? 'Y' : 'N',
6590 G_PORTMAP(cls_hi), G_T6_PF(cls_lo),
6591 cls_lo & F_T6_VF_VALID ? G_T6_VF(cls_lo) : -1);
6595 if (cls_lo & F_T6_REPLICATE) {
6596 struct fw_ldst_cmd ldst_cmd;
6598 memset(&ldst_cmd, 0, sizeof(ldst_cmd));
6599 ldst_cmd.op_to_addrspace =
6600 htobe32(V_FW_CMD_OP(FW_LDST_CMD) |
6601 F_FW_CMD_REQUEST | F_FW_CMD_READ |
6602 V_FW_LDST_CMD_ADDRSPACE(FW_LDST_ADDRSPC_MPS));
6603 ldst_cmd.cycles_to_len16 = htobe32(FW_LEN16(ldst_cmd));
6604 ldst_cmd.u.mps.rplc.fid_idx =
6605 htobe16(V_FW_LDST_CMD_FID(FW_LDST_MPS_RPLC) |
6606 V_FW_LDST_CMD_IDX(i));
6608 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK,
6612 rc = -t4_wr_mbox(sc, sc->mbox, &ldst_cmd,
6613 sizeof(ldst_cmd), &ldst_cmd);
6614 end_synchronized_op(sc, 0);
6617 sbuf_printf(sb, "%72d", rc);
6620 sbuf_printf(sb, " %08x %08x %08x %08x"
6621 " %08x %08x %08x %08x",
6622 be32toh(ldst_cmd.u.mps.rplc.rplc255_224),
6623 be32toh(ldst_cmd.u.mps.rplc.rplc223_192),
6624 be32toh(ldst_cmd.u.mps.rplc.rplc191_160),
6625 be32toh(ldst_cmd.u.mps.rplc.rplc159_128),
6626 be32toh(ldst_cmd.u.mps.rplc.rplc127_96),
6627 be32toh(ldst_cmd.u.mps.rplc.rplc95_64),
6628 be32toh(ldst_cmd.u.mps.rplc.rplc63_32),
6629 be32toh(ldst_cmd.u.mps.rplc.rplc31_0));
6632 sbuf_printf(sb, "%72s", "");
6634 sbuf_printf(sb, "%4u%3u%3u%3u %#x",
6635 G_T6_SRAM_PRIO0(cls_lo), G_T6_SRAM_PRIO1(cls_lo),
6636 G_T6_SRAM_PRIO2(cls_lo), G_T6_SRAM_PRIO3(cls_lo),
6637 (cls_lo >> S_T6_MULTILISTEN0) & 0xf);
6641 (void) sbuf_finish(sb);
6643 rc = sbuf_finish(sb);
6650 sysctl_path_mtus(SYSCTL_HANDLER_ARGS)
6652 struct adapter *sc = arg1;
6655 uint16_t mtus[NMTUS];
6657 rc = sysctl_wire_old_buffer(req, 0);
6661 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6665 t4_read_mtu_tbl(sc, mtus, NULL);
6667 sbuf_printf(sb, "%u %u %u %u %u %u %u %u %u %u %u %u %u %u %u %u",
6668 mtus[0], mtus[1], mtus[2], mtus[3], mtus[4], mtus[5], mtus[6],
6669 mtus[7], mtus[8], mtus[9], mtus[10], mtus[11], mtus[12], mtus[13],
6670 mtus[14], mtus[15]);
6672 rc = sbuf_finish(sb);
6679 sysctl_pm_stats(SYSCTL_HANDLER_ARGS)
6681 struct adapter *sc = arg1;
6684 uint32_t tx_cnt[MAX_PM_NSTATS], rx_cnt[MAX_PM_NSTATS];
6685 uint64_t tx_cyc[MAX_PM_NSTATS], rx_cyc[MAX_PM_NSTATS];
6686 static const char *tx_stats[MAX_PM_NSTATS] = {
6687 "Read:", "Write bypass:", "Write mem:", "Bypass + mem:",
6688 "Tx FIFO wait", NULL, "Tx latency"
6690 static const char *rx_stats[MAX_PM_NSTATS] = {
6691 "Read:", "Write bypass:", "Write mem:", "Flush:",
6692 " Rx FIFO wait", NULL, "Rx latency"
6695 rc = sysctl_wire_old_buffer(req, 0);
6699 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6703 t4_pmtx_get_stats(sc, tx_cnt, tx_cyc);
6704 t4_pmrx_get_stats(sc, rx_cnt, rx_cyc);
6706 sbuf_printf(sb, " Tx pcmds Tx bytes");
6707 for (i = 0; i < 4; i++) {
6708 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6712 sbuf_printf(sb, "\n Rx pcmds Rx bytes");
6713 for (i = 0; i < 4; i++) {
6714 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6718 if (chip_id(sc) > CHELSIO_T5) {
6720 "\n Total wait Total occupancy");
6721 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6723 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6727 MPASS(i < nitems(tx_stats));
6730 "\n Reads Total wait");
6731 sbuf_printf(sb, "\n%-13s %10u %20ju", tx_stats[i], tx_cnt[i],
6733 sbuf_printf(sb, "\n%-13s %10u %20ju", rx_stats[i], rx_cnt[i],
6737 rc = sbuf_finish(sb);
6744 sysctl_rdma_stats(SYSCTL_HANDLER_ARGS)
6746 struct adapter *sc = arg1;
6749 struct tp_rdma_stats stats;
6751 rc = sysctl_wire_old_buffer(req, 0);
6755 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6759 mtx_lock(&sc->reg_lock);
6760 t4_tp_get_rdma_stats(sc, &stats);
6761 mtx_unlock(&sc->reg_lock);
6763 sbuf_printf(sb, "NoRQEModDefferals: %u\n", stats.rqe_dfr_mod);
6764 sbuf_printf(sb, "NoRQEPktDefferals: %u", stats.rqe_dfr_pkt);
6766 rc = sbuf_finish(sb);
6773 sysctl_tcp_stats(SYSCTL_HANDLER_ARGS)
6775 struct adapter *sc = arg1;
6778 struct tp_tcp_stats v4, v6;
6780 rc = sysctl_wire_old_buffer(req, 0);
6784 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6788 mtx_lock(&sc->reg_lock);
6789 t4_tp_get_tcp_stats(sc, &v4, &v6);
6790 mtx_unlock(&sc->reg_lock);
6794 sbuf_printf(sb, "OutRsts: %20u %20u\n",
6795 v4.tcp_out_rsts, v6.tcp_out_rsts);
6796 sbuf_printf(sb, "InSegs: %20ju %20ju\n",
6797 v4.tcp_in_segs, v6.tcp_in_segs);
6798 sbuf_printf(sb, "OutSegs: %20ju %20ju\n",
6799 v4.tcp_out_segs, v6.tcp_out_segs);
6800 sbuf_printf(sb, "RetransSegs: %20ju %20ju",
6801 v4.tcp_retrans_segs, v6.tcp_retrans_segs);
6803 rc = sbuf_finish(sb);
6810 sysctl_tids(SYSCTL_HANDLER_ARGS)
6812 struct adapter *sc = arg1;
6815 struct tid_info *t = &sc->tids;
6817 rc = sysctl_wire_old_buffer(req, 0);
6821 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6826 sbuf_printf(sb, "ATID range: 0-%u, in use: %u\n", t->natids - 1,
6831 if (t4_read_reg(sc, A_LE_DB_CONFIG) & F_HASHEN) {
6832 uint32_t b = t4_read_reg(sc, A_LE_DB_SERVER_INDEX) / 4;
6835 sbuf_printf(sb, "TID range: 0-%u, %u-%u", b - 1,
6836 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6839 sbuf_printf(sb, "TID range: %u-%u",
6840 t4_read_reg(sc, A_LE_DB_TID_HASHBASE) / 4,
6844 sbuf_printf(sb, "TID range: 0-%u", t->ntids - 1);
6845 sbuf_printf(sb, ", in use: %u\n",
6846 atomic_load_acq_int(&t->tids_in_use));
6850 sbuf_printf(sb, "STID range: %u-%u, in use: %u\n", t->stid_base,
6851 t->stid_base + t->nstids - 1, t->stids_in_use);
6855 sbuf_printf(sb, "FTID range: %u-%u\n", t->ftid_base,
6856 t->ftid_base + t->nftids - 1);
6860 sbuf_printf(sb, "ETID range: %u-%u\n", t->etid_base,
6861 t->etid_base + t->netids - 1);
6864 sbuf_printf(sb, "HW TID usage: %u IP users, %u IPv6 users",
6865 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV4),
6866 t4_read_reg(sc, A_LE_DB_ACT_CNT_IPV6));
6868 rc = sbuf_finish(sb);
6875 sysctl_tp_err_stats(SYSCTL_HANDLER_ARGS)
6877 struct adapter *sc = arg1;
6880 struct tp_err_stats stats;
6882 rc = sysctl_wire_old_buffer(req, 0);
6886 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
6890 mtx_lock(&sc->reg_lock);
6891 t4_tp_get_err_stats(sc, &stats);
6892 mtx_unlock(&sc->reg_lock);
6894 if (sc->chip_params->nchan > 2) {
6895 sbuf_printf(sb, " channel 0 channel 1"
6896 " channel 2 channel 3\n");
6897 sbuf_printf(sb, "macInErrs: %10u %10u %10u %10u\n",
6898 stats.mac_in_errs[0], stats.mac_in_errs[1],
6899 stats.mac_in_errs[2], stats.mac_in_errs[3]);
6900 sbuf_printf(sb, "hdrInErrs: %10u %10u %10u %10u\n",
6901 stats.hdr_in_errs[0], stats.hdr_in_errs[1],
6902 stats.hdr_in_errs[2], stats.hdr_in_errs[3]);
6903 sbuf_printf(sb, "tcpInErrs: %10u %10u %10u %10u\n",
6904 stats.tcp_in_errs[0], stats.tcp_in_errs[1],
6905 stats.tcp_in_errs[2], stats.tcp_in_errs[3]);
6906 sbuf_printf(sb, "tcp6InErrs: %10u %10u %10u %10u\n",
6907 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1],
6908 stats.tcp6_in_errs[2], stats.tcp6_in_errs[3]);
6909 sbuf_printf(sb, "tnlCongDrops: %10u %10u %10u %10u\n",
6910 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1],
6911 stats.tnl_cong_drops[2], stats.tnl_cong_drops[3]);
6912 sbuf_printf(sb, "tnlTxDrops: %10u %10u %10u %10u\n",
6913 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1],
6914 stats.tnl_tx_drops[2], stats.tnl_tx_drops[3]);
6915 sbuf_printf(sb, "ofldVlanDrops: %10u %10u %10u %10u\n",
6916 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1],
6917 stats.ofld_vlan_drops[2], stats.ofld_vlan_drops[3]);
6918 sbuf_printf(sb, "ofldChanDrops: %10u %10u %10u %10u\n\n",
6919 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1],
6920 stats.ofld_chan_drops[2], stats.ofld_chan_drops[3]);
6922 sbuf_printf(sb, " channel 0 channel 1\n");
6923 sbuf_printf(sb, "macInErrs: %10u %10u\n",
6924 stats.mac_in_errs[0], stats.mac_in_errs[1]);
6925 sbuf_printf(sb, "hdrInErrs: %10u %10u\n",
6926 stats.hdr_in_errs[0], stats.hdr_in_errs[1]);
6927 sbuf_printf(sb, "tcpInErrs: %10u %10u\n",
6928 stats.tcp_in_errs[0], stats.tcp_in_errs[1]);
6929 sbuf_printf(sb, "tcp6InErrs: %10u %10u\n",
6930 stats.tcp6_in_errs[0], stats.tcp6_in_errs[1]);
6931 sbuf_printf(sb, "tnlCongDrops: %10u %10u\n",
6932 stats.tnl_cong_drops[0], stats.tnl_cong_drops[1]);
6933 sbuf_printf(sb, "tnlTxDrops: %10u %10u\n",
6934 stats.tnl_tx_drops[0], stats.tnl_tx_drops[1]);
6935 sbuf_printf(sb, "ofldVlanDrops: %10u %10u\n",
6936 stats.ofld_vlan_drops[0], stats.ofld_vlan_drops[1]);
6937 sbuf_printf(sb, "ofldChanDrops: %10u %10u\n\n",
6938 stats.ofld_chan_drops[0], stats.ofld_chan_drops[1]);
6941 sbuf_printf(sb, "ofldNoNeigh: %u\nofldCongDefer: %u",
6942 stats.ofld_no_neigh, stats.ofld_cong_defer);
6944 rc = sbuf_finish(sb);
6951 sysctl_tp_la_mask(SYSCTL_HANDLER_ARGS)
6953 struct adapter *sc = arg1;
6954 struct tp_params *tpp = &sc->params.tp;
6958 mask = tpp->la_mask >> 16;
6959 rc = sysctl_handle_int(oidp, &mask, 0, req);
6960 if (rc != 0 || req->newptr == NULL)
6964 tpp->la_mask = mask << 16;
6965 t4_set_reg_field(sc, A_TP_DBG_LA_CONFIG, 0xffff0000U, tpp->la_mask);
6977 field_desc_show(struct sbuf *sb, uint64_t v, const struct field_desc *f)
6983 uint64_t mask = (1ULL << f->width) - 1;
6984 int len = snprintf(buf, sizeof(buf), "%s: %ju", f->name,
6985 ((uintmax_t)v >> f->start) & mask);
6987 if (line_size + len >= 79) {
6989 sbuf_printf(sb, "\n ");
6991 sbuf_printf(sb, "%s ", buf);
6992 line_size += len + 1;
6995 sbuf_printf(sb, "\n");
6998 static const struct field_desc tp_la0[] = {
6999 { "RcfOpCodeOut", 60, 4 },
7001 { "WcfState", 52, 4 },
7002 { "RcfOpcSrcOut", 50, 2 },
7003 { "CRxError", 49, 1 },
7004 { "ERxError", 48, 1 },
7005 { "SanityFailed", 47, 1 },
7006 { "SpuriousMsg", 46, 1 },
7007 { "FlushInputMsg", 45, 1 },
7008 { "FlushInputCpl", 44, 1 },
7009 { "RssUpBit", 43, 1 },
7010 { "RssFilterHit", 42, 1 },
7012 { "InitTcb", 31, 1 },
7013 { "LineNumber", 24, 7 },
7015 { "EdataOut", 22, 1 },
7017 { "CdataOut", 20, 1 },
7018 { "EreadPdu", 19, 1 },
7019 { "CreadPdu", 18, 1 },
7020 { "TunnelPkt", 17, 1 },
7021 { "RcfPeerFin", 16, 1 },
7022 { "RcfReasonOut", 12, 4 },
7023 { "TxCchannel", 10, 2 },
7024 { "RcfTxChannel", 8, 2 },
7025 { "RxEchannel", 6, 2 },
7026 { "RcfRxChannel", 5, 1 },
7027 { "RcfDataOutSrdy", 4, 1 },
7029 { "RxOoDvld", 2, 1 },
7030 { "RxCongestion", 1, 1 },
7031 { "TxCongestion", 0, 1 },
7035 static const struct field_desc tp_la1[] = {
7036 { "CplCmdIn", 56, 8 },
7037 { "CplCmdOut", 48, 8 },
7038 { "ESynOut", 47, 1 },
7039 { "EAckOut", 46, 1 },
7040 { "EFinOut", 45, 1 },
7041 { "ERstOut", 44, 1 },
7046 { "DataIn", 39, 1 },
7047 { "DataInVld", 38, 1 },
7049 { "RxBufEmpty", 36, 1 },
7051 { "RxFbCongestion", 34, 1 },
7052 { "TxFbCongestion", 33, 1 },
7053 { "TxPktSumSrdy", 32, 1 },
7054 { "RcfUlpType", 28, 4 },
7056 { "Ebypass", 26, 1 },
7058 { "Static0", 24, 1 },
7060 { "Cbypass", 22, 1 },
7062 { "CPktOut", 20, 1 },
7063 { "RxPagePoolFull", 18, 2 },
7064 { "RxLpbkPkt", 17, 1 },
7065 { "TxLpbkPkt", 16, 1 },
7066 { "RxVfValid", 15, 1 },
7067 { "SynLearned", 14, 1 },
7068 { "SetDelEntry", 13, 1 },
7069 { "SetInvEntry", 12, 1 },
7070 { "CpcmdDvld", 11, 1 },
7071 { "CpcmdSave", 10, 1 },
7072 { "RxPstructsFull", 8, 2 },
7073 { "EpcmdDvld", 7, 1 },
7074 { "EpcmdFlush", 6, 1 },
7075 { "EpcmdTrimPrefix", 5, 1 },
7076 { "EpcmdTrimPostfix", 4, 1 },
7077 { "ERssIp4Pkt", 3, 1 },
7078 { "ERssIp6Pkt", 2, 1 },
7079 { "ERssTcpUdpPkt", 1, 1 },
7080 { "ERssFceFipPkt", 0, 1 },
7084 static const struct field_desc tp_la2[] = {
7085 { "CplCmdIn", 56, 8 },
7086 { "MpsVfVld", 55, 1 },
7093 { "DataIn", 39, 1 },
7094 { "DataInVld", 38, 1 },
7096 { "RxBufEmpty", 36, 1 },
7098 { "RxFbCongestion", 34, 1 },
7099 { "TxFbCongestion", 33, 1 },
7100 { "TxPktSumSrdy", 32, 1 },
7101 { "RcfUlpType", 28, 4 },
7103 { "Ebypass", 26, 1 },
7105 { "Static0", 24, 1 },
7107 { "Cbypass", 22, 1 },
7109 { "CPktOut", 20, 1 },
7110 { "RxPagePoolFull", 18, 2 },
7111 { "RxLpbkPkt", 17, 1 },
7112 { "TxLpbkPkt", 16, 1 },
7113 { "RxVfValid", 15, 1 },
7114 { "SynLearned", 14, 1 },
7115 { "SetDelEntry", 13, 1 },
7116 { "SetInvEntry", 12, 1 },
7117 { "CpcmdDvld", 11, 1 },
7118 { "CpcmdSave", 10, 1 },
7119 { "RxPstructsFull", 8, 2 },
7120 { "EpcmdDvld", 7, 1 },
7121 { "EpcmdFlush", 6, 1 },
7122 { "EpcmdTrimPrefix", 5, 1 },
7123 { "EpcmdTrimPostfix", 4, 1 },
7124 { "ERssIp4Pkt", 3, 1 },
7125 { "ERssIp6Pkt", 2, 1 },
7126 { "ERssTcpUdpPkt", 1, 1 },
7127 { "ERssFceFipPkt", 0, 1 },
7132 tp_la_show(struct sbuf *sb, uint64_t *p, int idx)
7135 field_desc_show(sb, *p, tp_la0);
7139 tp_la_show2(struct sbuf *sb, uint64_t *p, int idx)
7143 sbuf_printf(sb, "\n");
7144 field_desc_show(sb, p[0], tp_la0);
7145 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7146 field_desc_show(sb, p[1], tp_la0);
7150 tp_la_show3(struct sbuf *sb, uint64_t *p, int idx)
7154 sbuf_printf(sb, "\n");
7155 field_desc_show(sb, p[0], tp_la0);
7156 if (idx < (TPLA_SIZE / 2 - 1) || p[1] != ~0ULL)
7157 field_desc_show(sb, p[1], (p[0] & (1 << 17)) ? tp_la2 : tp_la1);
7161 sysctl_tp_la(SYSCTL_HANDLER_ARGS)
7163 struct adapter *sc = arg1;
7168 void (*show_func)(struct sbuf *, uint64_t *, int);
7170 rc = sysctl_wire_old_buffer(req, 0);
7174 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7178 buf = malloc(TPLA_SIZE * sizeof(uint64_t), M_CXGBE, M_ZERO | M_WAITOK);
7180 t4_tp_read_la(sc, buf, NULL);
7183 switch (G_DBGLAMODE(t4_read_reg(sc, A_TP_DBG_LA_CONFIG))) {
7186 show_func = tp_la_show2;
7190 show_func = tp_la_show3;
7194 show_func = tp_la_show;
7197 for (i = 0; i < TPLA_SIZE / inc; i++, p += inc)
7198 (*show_func)(sb, p, i);
7200 rc = sbuf_finish(sb);
7207 sysctl_tx_rate(SYSCTL_HANDLER_ARGS)
7209 struct adapter *sc = arg1;
7212 u64 nrate[MAX_NCHAN], orate[MAX_NCHAN];
7214 rc = sysctl_wire_old_buffer(req, 0);
7218 sb = sbuf_new_for_sysctl(NULL, NULL, 256, req);
7222 t4_get_chan_txrate(sc, nrate, orate);
7224 if (sc->chip_params->nchan > 2) {
7225 sbuf_printf(sb, " channel 0 channel 1"
7226 " channel 2 channel 3\n");
7227 sbuf_printf(sb, "NIC B/s: %10ju %10ju %10ju %10ju\n",
7228 nrate[0], nrate[1], nrate[2], nrate[3]);
7229 sbuf_printf(sb, "Offload B/s: %10ju %10ju %10ju %10ju",
7230 orate[0], orate[1], orate[2], orate[3]);
7232 sbuf_printf(sb, " channel 0 channel 1\n");
7233 sbuf_printf(sb, "NIC B/s: %10ju %10ju\n",
7234 nrate[0], nrate[1]);
7235 sbuf_printf(sb, "Offload B/s: %10ju %10ju",
7236 orate[0], orate[1]);
7239 rc = sbuf_finish(sb);
7246 sysctl_ulprx_la(SYSCTL_HANDLER_ARGS)
7248 struct adapter *sc = arg1;
7253 rc = sysctl_wire_old_buffer(req, 0);
7257 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7261 buf = malloc(ULPRX_LA_SIZE * 8 * sizeof(uint32_t), M_CXGBE,
7264 t4_ulprx_read_la(sc, buf);
7267 sbuf_printf(sb, " Pcmd Type Message"
7269 for (i = 0; i < ULPRX_LA_SIZE; i++, p += 8) {
7270 sbuf_printf(sb, "\n%08x%08x %4x %08x %08x%08x%08x%08x",
7271 p[1], p[0], p[2], p[3], p[7], p[6], p[5], p[4]);
7274 rc = sbuf_finish(sb);
7281 sysctl_wcwr_stats(SYSCTL_HANDLER_ARGS)
7283 struct adapter *sc = arg1;
7287 rc = sysctl_wire_old_buffer(req, 0);
7291 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7295 v = t4_read_reg(sc, A_SGE_STAT_CFG);
7296 if (G_STATSOURCE_T5(v) == 7) {
7297 if (G_STATMODE(v) == 0) {
7298 sbuf_printf(sb, "total %d, incomplete %d",
7299 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7300 t4_read_reg(sc, A_SGE_STAT_MATCH));
7301 } else if (G_STATMODE(v) == 1) {
7302 sbuf_printf(sb, "total %d, data overflow %d",
7303 t4_read_reg(sc, A_SGE_STAT_TOTAL),
7304 t4_read_reg(sc, A_SGE_STAT_MATCH));
7307 rc = sbuf_finish(sb);
7314 sysctl_tc_params(SYSCTL_HANDLER_ARGS)
7316 struct adapter *sc = arg1;
7317 struct tx_sched_class *tc;
7318 struct t4_sched_class_params p;
7320 int i, rc, port_id, flags, mbps, gbps;
7322 rc = sysctl_wire_old_buffer(req, 0);
7326 sb = sbuf_new_for_sysctl(NULL, NULL, 4096, req);
7330 port_id = arg2 >> 16;
7331 MPASS(port_id < sc->params.nports);
7332 MPASS(sc->port[port_id] != NULL);
7334 MPASS(i < sc->chip_params->nsched_cls);
7335 tc = &sc->port[port_id]->tc[i];
7337 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7343 end_synchronized_op(sc, LOCK_HELD);
7345 if ((flags & TX_SC_OK) == 0) {
7346 sbuf_printf(sb, "none");
7350 if (p.level == SCHED_CLASS_LEVEL_CL_WRR) {
7351 sbuf_printf(sb, "cl-wrr weight %u", p.weight);
7353 } else if (p.level == SCHED_CLASS_LEVEL_CL_RL)
7354 sbuf_printf(sb, "cl-rl");
7355 else if (p.level == SCHED_CLASS_LEVEL_CH_RL)
7356 sbuf_printf(sb, "ch-rl");
7362 if (p.ratemode == SCHED_CLASS_RATEMODE_REL) {
7363 /* XXX: top speed or actual link speed? */
7364 gbps = port_top_speed(sc->port[port_id]);
7365 sbuf_printf(sb, " %u%% of %uGbps", p.maxrate, gbps);
7367 else if (p.ratemode == SCHED_CLASS_RATEMODE_ABS) {
7368 switch (p.rateunit) {
7369 case SCHED_CLASS_RATEUNIT_BITS:
7370 mbps = p.maxrate / 1000;
7371 gbps = p.maxrate / 1000000;
7372 if (p.maxrate == gbps * 1000000)
7373 sbuf_printf(sb, " %uGbps", gbps);
7374 else if (p.maxrate == mbps * 1000)
7375 sbuf_printf(sb, " %uMbps", mbps);
7377 sbuf_printf(sb, " %uKbps", p.maxrate);
7379 case SCHED_CLASS_RATEUNIT_PKTS:
7380 sbuf_printf(sb, " %upps", p.maxrate);
7389 case SCHED_CLASS_MODE_CLASS:
7390 sbuf_printf(sb, " aggregate");
7392 case SCHED_CLASS_MODE_FLOW:
7393 sbuf_printf(sb, " per-flow");
7402 rc = sbuf_finish(sb);
7411 unit_conv(char *buf, size_t len, u_int val, u_int factor)
7413 u_int rem = val % factor;
7416 snprintf(buf, len, "%u", val / factor);
7418 while (rem % 10 == 0)
7420 snprintf(buf, len, "%u.%u", val / factor, rem);
7425 sysctl_tp_tick(SYSCTL_HANDLER_ARGS)
7427 struct adapter *sc = arg1;
7430 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7432 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
7436 re = G_TIMERRESOLUTION(res);
7439 /* TCP timestamp tick */
7440 re = G_TIMESTAMPRESOLUTION(res);
7444 re = G_DELAYEDACKRESOLUTION(res);
7450 unit_conv(buf, sizeof(buf), (cclk_ps << re), 1000000);
7452 return (sysctl_handle_string(oidp, buf, sizeof(buf), req));
7456 sysctl_tp_dack_timer(SYSCTL_HANDLER_ARGS)
7458 struct adapter *sc = arg1;
7459 u_int res, dack_re, v;
7460 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7462 res = t4_read_reg(sc, A_TP_TIMER_RESOLUTION);
7463 dack_re = G_DELAYEDACKRESOLUTION(res);
7464 v = ((cclk_ps << dack_re) / 1000000) * t4_read_reg(sc, A_TP_DACK_TIMER);
7466 return (sysctl_handle_int(oidp, &v, 0, req));
7470 sysctl_tp_timer(SYSCTL_HANDLER_ARGS)
7472 struct adapter *sc = arg1;
7475 u_long tp_tick_us, v;
7476 u_int cclk_ps = 1000000000 / sc->params.vpd.cclk;
7478 MPASS(reg == A_TP_RXT_MIN || reg == A_TP_RXT_MAX ||
7479 reg == A_TP_PERS_MIN || reg == A_TP_PERS_MAX ||
7480 reg == A_TP_KEEP_IDLE || A_TP_KEEP_INTVL || reg == A_TP_INIT_SRTT ||
7481 reg == A_TP_FINWAIT2_TIMER);
7483 tre = G_TIMERRESOLUTION(t4_read_reg(sc, A_TP_TIMER_RESOLUTION));
7484 tp_tick_us = (cclk_ps << tre) / 1000000;
7486 if (reg == A_TP_INIT_SRTT)
7487 v = tp_tick_us * G_INITSRTT(t4_read_reg(sc, reg));
7489 v = tp_tick_us * t4_read_reg(sc, reg);
7491 return (sysctl_handle_long(oidp, &v, 0, req));
7496 fconf_iconf_to_mode(uint32_t fconf, uint32_t iconf)
7500 mode = T4_FILTER_IPv4 | T4_FILTER_IPv6 | T4_FILTER_IP_SADDR |
7501 T4_FILTER_IP_DADDR | T4_FILTER_IP_SPORT | T4_FILTER_IP_DPORT;
7503 if (fconf & F_FRAGMENTATION)
7504 mode |= T4_FILTER_IP_FRAGMENT;
7506 if (fconf & F_MPSHITTYPE)
7507 mode |= T4_FILTER_MPS_HIT_TYPE;
7509 if (fconf & F_MACMATCH)
7510 mode |= T4_FILTER_MAC_IDX;
7512 if (fconf & F_ETHERTYPE)
7513 mode |= T4_FILTER_ETH_TYPE;
7515 if (fconf & F_PROTOCOL)
7516 mode |= T4_FILTER_IP_PROTO;
7519 mode |= T4_FILTER_IP_TOS;
7522 mode |= T4_FILTER_VLAN;
7524 if (fconf & F_VNIC_ID) {
7525 mode |= T4_FILTER_VNIC;
7527 mode |= T4_FILTER_IC_VNIC;
7531 mode |= T4_FILTER_PORT;
7534 mode |= T4_FILTER_FCoE;
7540 mode_to_fconf(uint32_t mode)
7544 if (mode & T4_FILTER_IP_FRAGMENT)
7545 fconf |= F_FRAGMENTATION;
7547 if (mode & T4_FILTER_MPS_HIT_TYPE)
7548 fconf |= F_MPSHITTYPE;
7550 if (mode & T4_FILTER_MAC_IDX)
7551 fconf |= F_MACMATCH;
7553 if (mode & T4_FILTER_ETH_TYPE)
7554 fconf |= F_ETHERTYPE;
7556 if (mode & T4_FILTER_IP_PROTO)
7557 fconf |= F_PROTOCOL;
7559 if (mode & T4_FILTER_IP_TOS)
7562 if (mode & T4_FILTER_VLAN)
7565 if (mode & T4_FILTER_VNIC)
7568 if (mode & T4_FILTER_PORT)
7571 if (mode & T4_FILTER_FCoE)
7578 mode_to_iconf(uint32_t mode)
7581 if (mode & T4_FILTER_IC_VNIC)
7586 static int check_fspec_against_fconf_iconf(struct adapter *sc,
7587 struct t4_filter_specification *fs)
7589 struct tp_params *tpp = &sc->params.tp;
7592 if (fs->val.frag || fs->mask.frag)
7593 fconf |= F_FRAGMENTATION;
7595 if (fs->val.matchtype || fs->mask.matchtype)
7596 fconf |= F_MPSHITTYPE;
7598 if (fs->val.macidx || fs->mask.macidx)
7599 fconf |= F_MACMATCH;
7601 if (fs->val.ethtype || fs->mask.ethtype)
7602 fconf |= F_ETHERTYPE;
7604 if (fs->val.proto || fs->mask.proto)
7605 fconf |= F_PROTOCOL;
7607 if (fs->val.tos || fs->mask.tos)
7610 if (fs->val.vlan_vld || fs->mask.vlan_vld)
7613 if (fs->val.ovlan_vld || fs->mask.ovlan_vld) {
7615 if (tpp->ingress_config & F_VNIC)
7619 if (fs->val.pfvf_vld || fs->mask.pfvf_vld) {
7621 if ((tpp->ingress_config & F_VNIC) == 0)
7625 if (fs->val.iport || fs->mask.iport)
7628 if (fs->val.fcoe || fs->mask.fcoe)
7631 if ((tpp->vlan_pri_map | fconf) != tpp->vlan_pri_map)
7638 get_filter_mode(struct adapter *sc, uint32_t *mode)
7640 struct tp_params *tpp = &sc->params.tp;
7643 * We trust the cached values of the relevant TP registers. This means
7644 * things work reliably only if writes to those registers are always via
7645 * t4_set_filter_mode.
7647 *mode = fconf_iconf_to_mode(tpp->vlan_pri_map, tpp->ingress_config);
7653 set_filter_mode(struct adapter *sc, uint32_t mode)
7655 struct tp_params *tpp = &sc->params.tp;
7656 uint32_t fconf, iconf;
7659 iconf = mode_to_iconf(mode);
7660 if ((iconf ^ tpp->ingress_config) & F_VNIC) {
7662 * For now we just complain if A_TP_INGRESS_CONFIG is not
7663 * already set to the correct value for the requested filter
7664 * mode. It's not clear if it's safe to write to this register
7665 * on the fly. (And we trust the cached value of the register).
7670 fconf = mode_to_fconf(mode);
7672 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7677 if (sc->tids.ftids_in_use > 0) {
7683 if (uld_active(sc, ULD_TOM)) {
7689 rc = -t4_set_filter_mode(sc, fconf);
7691 end_synchronized_op(sc, LOCK_HELD);
7695 static inline uint64_t
7696 get_filter_hits(struct adapter *sc, uint32_t fid)
7700 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE) +
7701 (fid + sc->tids.ftid_base) * TCB_SIZE;
7706 read_via_memwin(sc, 0, tcb_addr + 16, (uint32_t *)&hits, 8);
7707 return (be64toh(hits));
7711 read_via_memwin(sc, 0, tcb_addr + 24, &hits, 4);
7712 return (be32toh(hits));
7717 get_filter(struct adapter *sc, struct t4_filter *t)
7719 int i, rc, nfilters = sc->tids.nftids;
7720 struct filter_entry *f;
7722 rc = begin_synchronized_op(sc, NULL, HOLD_LOCK | SLEEP_OK | INTR_OK,
7727 if (sc->tids.ftids_in_use == 0 || sc->tids.ftid_tab == NULL ||
7728 t->idx >= nfilters) {
7729 t->idx = 0xffffffff;
7733 f = &sc->tids.ftid_tab[t->idx];
7734 for (i = t->idx; i < nfilters; i++, f++) {
7737 t->l2tidx = f->l2t ? f->l2t->idx : 0;
7738 t->smtidx = f->smtidx;
7740 t->hits = get_filter_hits(sc, t->idx);
7742 t->hits = UINT64_MAX;
7749 t->idx = 0xffffffff;
7751 end_synchronized_op(sc, LOCK_HELD);
7756 set_filter(struct adapter *sc, struct t4_filter *t)
7758 unsigned int nfilters, nports;
7759 struct filter_entry *f;
7762 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setf");
7766 nfilters = sc->tids.nftids;
7767 nports = sc->params.nports;
7769 if (nfilters == 0) {
7774 if (!(sc->flags & FULL_INIT_DONE)) {
7779 if (t->idx >= nfilters) {
7784 /* Validate against the global filter mode and ingress config */
7785 rc = check_fspec_against_fconf_iconf(sc, &t->fs);
7789 if (t->fs.action == FILTER_SWITCH && t->fs.eport >= nports) {
7794 if (t->fs.val.iport >= nports) {
7799 /* Can't specify an iq if not steering to it */
7800 if (!t->fs.dirsteer && t->fs.iq) {
7805 /* IPv6 filter idx must be 4 aligned */
7806 if (t->fs.type == 1 &&
7807 ((t->idx & 0x3) || t->idx + 4 >= nfilters)) {
7812 if (sc->tids.ftid_tab == NULL) {
7813 KASSERT(sc->tids.ftids_in_use == 0,
7814 ("%s: no memory allocated but filters_in_use > 0",
7817 sc->tids.ftid_tab = malloc(sizeof (struct filter_entry) *
7818 nfilters, M_CXGBE, M_NOWAIT | M_ZERO);
7819 if (sc->tids.ftid_tab == NULL) {
7823 mtx_init(&sc->tids.ftid_lock, "T4 filters", 0, MTX_DEF);
7826 for (i = 0; i < 4; i++) {
7827 f = &sc->tids.ftid_tab[t->idx + i];
7829 if (f->pending || f->valid) {
7838 if (t->fs.type == 0)
7842 f = &sc->tids.ftid_tab[t->idx];
7845 rc = set_filter_wr(sc, t->idx);
7847 end_synchronized_op(sc, 0);
7850 mtx_lock(&sc->tids.ftid_lock);
7852 if (f->pending == 0) {
7853 rc = f->valid ? 0 : EIO;
7857 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
7858 PCATCH, "t4setfw", 0)) {
7863 mtx_unlock(&sc->tids.ftid_lock);
7869 del_filter(struct adapter *sc, struct t4_filter *t)
7871 unsigned int nfilters;
7872 struct filter_entry *f;
7875 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4delf");
7879 nfilters = sc->tids.nftids;
7881 if (nfilters == 0) {
7886 if (sc->tids.ftid_tab == NULL || sc->tids.ftids_in_use == 0 ||
7887 t->idx >= nfilters) {
7892 if (!(sc->flags & FULL_INIT_DONE)) {
7897 f = &sc->tids.ftid_tab[t->idx];
7909 t->fs = f->fs; /* extra info for the caller */
7910 rc = del_filter_wr(sc, t->idx);
7914 end_synchronized_op(sc, 0);
7917 mtx_lock(&sc->tids.ftid_lock);
7919 if (f->pending == 0) {
7920 rc = f->valid ? EIO : 0;
7924 if (mtx_sleep(&sc->tids.ftid_tab, &sc->tids.ftid_lock,
7925 PCATCH, "t4delfw", 0)) {
7930 mtx_unlock(&sc->tids.ftid_lock);
7937 clear_filter(struct filter_entry *f)
7940 t4_l2t_release(f->l2t);
7942 bzero(f, sizeof (*f));
7946 set_filter_wr(struct adapter *sc, int fidx)
7948 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
7949 struct fw_filter_wr *fwr;
7950 unsigned int ftid, vnic_vld, vnic_vld_mask;
7951 struct wrq_cookie cookie;
7953 ASSERT_SYNCHRONIZED_OP(sc);
7955 if (f->fs.newdmac || f->fs.newvlan) {
7956 /* This filter needs an L2T entry; allocate one. */
7957 f->l2t = t4_l2t_alloc_switching(sc->l2t);
7960 if (t4_l2t_set_switching(sc, f->l2t, f->fs.vlan, f->fs.eport,
7962 t4_l2t_release(f->l2t);
7968 /* Already validated against fconf, iconf */
7969 MPASS((f->fs.val.pfvf_vld & f->fs.val.ovlan_vld) == 0);
7970 MPASS((f->fs.mask.pfvf_vld & f->fs.mask.ovlan_vld) == 0);
7971 if (f->fs.val.pfvf_vld || f->fs.val.ovlan_vld)
7975 if (f->fs.mask.pfvf_vld || f->fs.mask.ovlan_vld)
7980 ftid = sc->tids.ftid_base + fidx;
7982 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
7985 bzero(fwr, sizeof(*fwr));
7987 fwr->op_pkd = htobe32(V_FW_WR_OP(FW_FILTER_WR));
7988 fwr->len16_pkd = htobe32(FW_LEN16(*fwr));
7990 htobe32(V_FW_FILTER_WR_TID(ftid) |
7991 V_FW_FILTER_WR_RQTYPE(f->fs.type) |
7992 V_FW_FILTER_WR_NOREPLY(0) |
7993 V_FW_FILTER_WR_IQ(f->fs.iq));
7994 fwr->del_filter_to_l2tix =
7995 htobe32(V_FW_FILTER_WR_RPTTID(f->fs.rpttid) |
7996 V_FW_FILTER_WR_DROP(f->fs.action == FILTER_DROP) |
7997 V_FW_FILTER_WR_DIRSTEER(f->fs.dirsteer) |
7998 V_FW_FILTER_WR_MASKHASH(f->fs.maskhash) |
7999 V_FW_FILTER_WR_DIRSTEERHASH(f->fs.dirsteerhash) |
8000 V_FW_FILTER_WR_LPBK(f->fs.action == FILTER_SWITCH) |
8001 V_FW_FILTER_WR_DMAC(f->fs.newdmac) |
8002 V_FW_FILTER_WR_SMAC(f->fs.newsmac) |
8003 V_FW_FILTER_WR_INSVLAN(f->fs.newvlan == VLAN_INSERT ||
8004 f->fs.newvlan == VLAN_REWRITE) |
8005 V_FW_FILTER_WR_RMVLAN(f->fs.newvlan == VLAN_REMOVE ||
8006 f->fs.newvlan == VLAN_REWRITE) |
8007 V_FW_FILTER_WR_HITCNTS(f->fs.hitcnts) |
8008 V_FW_FILTER_WR_TXCHAN(f->fs.eport) |
8009 V_FW_FILTER_WR_PRIO(f->fs.prio) |
8010 V_FW_FILTER_WR_L2TIX(f->l2t ? f->l2t->idx : 0));
8011 fwr->ethtype = htobe16(f->fs.val.ethtype);
8012 fwr->ethtypem = htobe16(f->fs.mask.ethtype);
8013 fwr->frag_to_ovlan_vldm =
8014 (V_FW_FILTER_WR_FRAG(f->fs.val.frag) |
8015 V_FW_FILTER_WR_FRAGM(f->fs.mask.frag) |
8016 V_FW_FILTER_WR_IVLAN_VLD(f->fs.val.vlan_vld) |
8017 V_FW_FILTER_WR_OVLAN_VLD(vnic_vld) |
8018 V_FW_FILTER_WR_IVLAN_VLDM(f->fs.mask.vlan_vld) |
8019 V_FW_FILTER_WR_OVLAN_VLDM(vnic_vld_mask));
8021 fwr->rx_chan_rx_rpl_iq = htobe16(V_FW_FILTER_WR_RX_CHAN(0) |
8022 V_FW_FILTER_WR_RX_RPL_IQ(sc->sge.fwq.abs_id));
8023 fwr->maci_to_matchtypem =
8024 htobe32(V_FW_FILTER_WR_MACI(f->fs.val.macidx) |
8025 V_FW_FILTER_WR_MACIM(f->fs.mask.macidx) |
8026 V_FW_FILTER_WR_FCOE(f->fs.val.fcoe) |
8027 V_FW_FILTER_WR_FCOEM(f->fs.mask.fcoe) |
8028 V_FW_FILTER_WR_PORT(f->fs.val.iport) |
8029 V_FW_FILTER_WR_PORTM(f->fs.mask.iport) |
8030 V_FW_FILTER_WR_MATCHTYPE(f->fs.val.matchtype) |
8031 V_FW_FILTER_WR_MATCHTYPEM(f->fs.mask.matchtype));
8032 fwr->ptcl = f->fs.val.proto;
8033 fwr->ptclm = f->fs.mask.proto;
8034 fwr->ttyp = f->fs.val.tos;
8035 fwr->ttypm = f->fs.mask.tos;
8036 fwr->ivlan = htobe16(f->fs.val.vlan);
8037 fwr->ivlanm = htobe16(f->fs.mask.vlan);
8038 fwr->ovlan = htobe16(f->fs.val.vnic);
8039 fwr->ovlanm = htobe16(f->fs.mask.vnic);
8040 bcopy(f->fs.val.dip, fwr->lip, sizeof (fwr->lip));
8041 bcopy(f->fs.mask.dip, fwr->lipm, sizeof (fwr->lipm));
8042 bcopy(f->fs.val.sip, fwr->fip, sizeof (fwr->fip));
8043 bcopy(f->fs.mask.sip, fwr->fipm, sizeof (fwr->fipm));
8044 fwr->lp = htobe16(f->fs.val.dport);
8045 fwr->lpm = htobe16(f->fs.mask.dport);
8046 fwr->fp = htobe16(f->fs.val.sport);
8047 fwr->fpm = htobe16(f->fs.mask.sport);
8049 bcopy(f->fs.smac, fwr->sma, sizeof (fwr->sma));
8052 sc->tids.ftids_in_use++;
8054 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8059 del_filter_wr(struct adapter *sc, int fidx)
8061 struct filter_entry *f = &sc->tids.ftid_tab[fidx];
8062 struct fw_filter_wr *fwr;
8064 struct wrq_cookie cookie;
8066 ftid = sc->tids.ftid_base + fidx;
8068 fwr = start_wrq_wr(&sc->sge.mgmtq, howmany(sizeof(*fwr), 16), &cookie);
8071 bzero(fwr, sizeof (*fwr));
8073 t4_mk_filtdelwr(ftid, fwr, sc->sge.fwq.abs_id);
8076 commit_wrq_wr(&sc->sge.mgmtq, fwr, &cookie);
8081 t4_filter_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8083 struct adapter *sc = iq->adapter;
8084 const struct cpl_set_tcb_rpl *rpl = (const void *)(rss + 1);
8085 unsigned int idx = GET_TID(rpl);
8087 struct filter_entry *f;
8089 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
8091 MPASS(iq == &sc->sge.fwq);
8092 MPASS(is_ftid(sc, idx));
8094 idx -= sc->tids.ftid_base;
8095 f = &sc->tids.ftid_tab[idx];
8096 rc = G_COOKIE(rpl->cookie);
8098 mtx_lock(&sc->tids.ftid_lock);
8099 if (rc == FW_FILTER_WR_FLT_ADDED) {
8100 KASSERT(f->pending, ("%s: filter[%u] isn't pending.",
8102 f->smtidx = (be64toh(rpl->oldval) >> 24) & 0xff;
8103 f->pending = 0; /* asynchronous setup completed */
8106 if (rc != FW_FILTER_WR_FLT_DELETED) {
8107 /* Add or delete failed, display an error */
8109 "filter %u setup failed with error %u\n",
8114 sc->tids.ftids_in_use--;
8116 wakeup(&sc->tids.ftid_tab);
8117 mtx_unlock(&sc->tids.ftid_lock);
8123 set_tcb_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8126 MPASS(iq->set_tcb_rpl != NULL);
8127 return (iq->set_tcb_rpl(iq, rss, m));
8131 l2t_write_rpl(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
8134 MPASS(iq->l2t_write_rpl != NULL);
8135 return (iq->l2t_write_rpl(iq, rss, m));
8139 get_sge_context(struct adapter *sc, struct t4_sge_context *cntxt)
8143 if (cntxt->cid > M_CTXTQID)
8146 if (cntxt->mem_id != CTXT_EGRESS && cntxt->mem_id != CTXT_INGRESS &&
8147 cntxt->mem_id != CTXT_FLM && cntxt->mem_id != CTXT_CNM)
8150 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ctxt");
8154 if (sc->flags & FW_OK) {
8155 rc = -t4_sge_ctxt_rd(sc, sc->mbox, cntxt->cid, cntxt->mem_id,
8162 * Read via firmware failed or wasn't even attempted. Read directly via
8165 rc = -t4_sge_ctxt_rd_bd(sc, cntxt->cid, cntxt->mem_id, &cntxt->data[0]);
8167 end_synchronized_op(sc, 0);
8172 load_fw(struct adapter *sc, struct t4_data *fw)
8177 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4ldfw");
8181 if (sc->flags & FULL_INIT_DONE) {
8186 fw_data = malloc(fw->len, M_CXGBE, M_WAITOK);
8187 if (fw_data == NULL) {
8192 rc = copyin(fw->data, fw_data, fw->len);
8194 rc = -t4_load_fw(sc, fw_data, fw->len);
8196 free(fw_data, M_CXGBE);
8198 end_synchronized_op(sc, 0);
8202 #define MAX_READ_BUF_SIZE (128 * 1024)
8204 read_card_mem(struct adapter *sc, int win, struct t4_mem_range *mr)
8206 uint32_t addr, remaining, n;
8211 rc = validate_mem_range(sc, mr->addr, mr->len);
8215 buf = malloc(min(mr->len, MAX_READ_BUF_SIZE), M_CXGBE, M_WAITOK);
8217 remaining = mr->len;
8218 dst = (void *)mr->data;
8221 n = min(remaining, MAX_READ_BUF_SIZE);
8222 read_via_memwin(sc, 2, addr, buf, n);
8224 rc = copyout(buf, dst, n);
8236 #undef MAX_READ_BUF_SIZE
8239 read_i2c(struct adapter *sc, struct t4_i2c_data *i2cd)
8243 if (i2cd->len == 0 || i2cd->port_id >= sc->params.nports)
8246 if (i2cd->len > sizeof(i2cd->data))
8249 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4i2crd");
8252 rc = -t4_i2c_rd(sc, sc->mbox, i2cd->port_id, i2cd->dev_addr,
8253 i2cd->offset, i2cd->len, &i2cd->data[0]);
8254 end_synchronized_op(sc, 0);
8260 in_range(int val, int lo, int hi)
8263 return (val < 0 || (val <= hi && val >= lo));
8267 set_sched_class_config(struct adapter *sc, int minmax)
8274 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4sscc");
8277 rc = -t4_sched_config(sc, FW_SCHED_TYPE_PKTSCHED, minmax, 1);
8278 end_synchronized_op(sc, 0);
8284 set_sched_class_params(struct adapter *sc, struct t4_sched_class_params *p,
8287 int rc, top_speed, fw_level, fw_mode, fw_rateunit, fw_ratemode;
8288 struct port_info *pi;
8289 struct tx_sched_class *tc;
8291 if (p->level == SCHED_CLASS_LEVEL_CL_RL)
8292 fw_level = FW_SCHED_PARAMS_LEVEL_CL_RL;
8293 else if (p->level == SCHED_CLASS_LEVEL_CL_WRR)
8294 fw_level = FW_SCHED_PARAMS_LEVEL_CL_WRR;
8295 else if (p->level == SCHED_CLASS_LEVEL_CH_RL)
8296 fw_level = FW_SCHED_PARAMS_LEVEL_CH_RL;
8300 if (p->mode == SCHED_CLASS_MODE_CLASS)
8301 fw_mode = FW_SCHED_PARAMS_MODE_CLASS;
8302 else if (p->mode == SCHED_CLASS_MODE_FLOW)
8303 fw_mode = FW_SCHED_PARAMS_MODE_FLOW;
8307 if (p->rateunit == SCHED_CLASS_RATEUNIT_BITS)
8308 fw_rateunit = FW_SCHED_PARAMS_UNIT_BITRATE;
8309 else if (p->rateunit == SCHED_CLASS_RATEUNIT_PKTS)
8310 fw_rateunit = FW_SCHED_PARAMS_UNIT_PKTRATE;
8314 if (p->ratemode == SCHED_CLASS_RATEMODE_REL)
8315 fw_ratemode = FW_SCHED_PARAMS_RATE_REL;
8316 else if (p->ratemode == SCHED_CLASS_RATEMODE_ABS)
8317 fw_ratemode = FW_SCHED_PARAMS_RATE_ABS;
8321 /* Vet our parameters ... */
8322 if (!in_range(p->channel, 0, sc->chip_params->nchan - 1))
8325 pi = sc->port[sc->chan_map[p->channel]];
8328 MPASS(pi->tx_chan == p->channel);
8329 top_speed = port_top_speed(pi) * 1000000; /* Gbps -> Kbps */
8331 if (!in_range(p->cl, 0, sc->chip_params->nsched_cls) ||
8332 !in_range(p->minrate, 0, top_speed) ||
8333 !in_range(p->maxrate, 0, top_speed) ||
8334 !in_range(p->weight, 0, 100))
8338 * Translate any unset parameters into the firmware's
8339 * nomenclature and/or fail the call if the parameters
8342 if (p->rateunit < 0 || p->ratemode < 0 || p->channel < 0 || p->cl < 0)
8347 if (p->maxrate < 0) {
8348 if (p->level == SCHED_CLASS_LEVEL_CL_RL ||
8349 p->level == SCHED_CLASS_LEVEL_CH_RL)
8354 if (p->weight < 0) {
8355 if (p->level == SCHED_CLASS_LEVEL_CL_WRR)
8360 if (p->pktsize < 0) {
8361 if (p->level == SCHED_CLASS_LEVEL_CL_RL ||
8362 p->level == SCHED_CLASS_LEVEL_CH_RL)
8368 rc = begin_synchronized_op(sc, NULL,
8369 sleep_ok ? (SLEEP_OK | INTR_OK) : HOLD_LOCK, "t4sscp");
8372 tc = &pi->tc[p->cl];
8374 rc = -t4_sched_params(sc, FW_SCHED_TYPE_PKTSCHED, fw_level, fw_mode,
8375 fw_rateunit, fw_ratemode, p->channel, p->cl, p->minrate, p->maxrate,
8376 p->weight, p->pktsize, sleep_ok);
8378 tc->flags |= TX_SC_OK;
8381 * Unknown state at this point, see tc->params for what was
8384 tc->flags &= ~TX_SC_OK;
8386 end_synchronized_op(sc, sleep_ok ? 0 : LOCK_HELD);
8392 set_sched_class(struct adapter *sc, struct t4_sched_params *p)
8395 if (p->type != SCHED_CLASS_TYPE_PACKET)
8398 if (p->subcmd == SCHED_CLASS_SUBCMD_CONFIG)
8399 return (set_sched_class_config(sc, p->u.config.minmax));
8401 if (p->subcmd == SCHED_CLASS_SUBCMD_PARAMS)
8402 return (set_sched_class_params(sc, &p->u.params, 1));
8408 set_sched_queue(struct adapter *sc, struct t4_sched_queue *p)
8410 struct port_info *pi = NULL;
8412 struct sge_txq *txq;
8413 uint32_t fw_mnem, fw_queue, fw_class;
8416 rc = begin_synchronized_op(sc, NULL, SLEEP_OK | INTR_OK, "t4setsq");
8420 if (p->port >= sc->params.nports) {
8425 /* XXX: Only supported for the main VI. */
8426 pi = sc->port[p->port];
8428 if (!(vi->flags & VI_INIT_DONE)) {
8429 /* tx queues not set up yet */
8434 if (!in_range(p->queue, 0, vi->ntxq - 1) ||
8435 !in_range(p->cl, 0, sc->chip_params->nsched_cls - 1)) {
8441 * Create a template for the FW_PARAMS_CMD mnemonic and value (TX
8442 * Scheduling Class in this case).
8444 fw_mnem = (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
8445 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH));
8446 fw_class = p->cl < 0 ? 0xffffffff : p->cl;
8449 * If op.queue is non-negative, then we're only changing the scheduling
8450 * on a single specified TX queue.
8452 if (p->queue >= 0) {
8453 txq = &sc->sge.txq[vi->first_txq + p->queue];
8454 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8455 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8461 * Change the scheduling on all the TX queues for the
8464 for_each_txq(vi, i, txq) {
8465 fw_queue = (fw_mnem | V_FW_PARAMS_PARAM_YZ(txq->eq.cntxt_id));
8466 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, &fw_queue,
8474 end_synchronized_op(sc, 0);
8479 t4_os_find_pci_capability(struct adapter *sc, int cap)
8483 return (pci_find_cap(sc->dev, cap, &i) == 0 ? i : 0);
8487 t4_os_pci_save_state(struct adapter *sc)
8490 struct pci_devinfo *dinfo;
8493 dinfo = device_get_ivars(dev);
8495 pci_cfg_save(dev, dinfo, 0);
8500 t4_os_pci_restore_state(struct adapter *sc)
8503 struct pci_devinfo *dinfo;
8506 dinfo = device_get_ivars(dev);
8508 pci_cfg_restore(dev, dinfo);
8513 t4_os_portmod_changed(const struct adapter *sc, int idx)
8515 struct port_info *pi = sc->port[idx];
8519 static const char *mod_str[] = {
8520 NULL, "LR", "SR", "ER", "TWINAX", "active TWINAX", "LRM"
8523 for_each_vi(pi, v, vi) {
8524 build_medialist(pi, &vi->media);
8527 ifp = pi->vi[0].ifp;
8528 if (pi->mod_type == FW_PORT_MOD_TYPE_NONE)
8529 if_printf(ifp, "transceiver unplugged.\n");
8530 else if (pi->mod_type == FW_PORT_MOD_TYPE_UNKNOWN)
8531 if_printf(ifp, "unknown transceiver inserted.\n");
8532 else if (pi->mod_type == FW_PORT_MOD_TYPE_NOTSUPPORTED)
8533 if_printf(ifp, "unsupported transceiver inserted.\n");
8534 else if (pi->mod_type > 0 && pi->mod_type < nitems(mod_str)) {
8535 if_printf(ifp, "%s transceiver inserted.\n",
8536 mod_str[pi->mod_type]);
8538 if_printf(ifp, "transceiver (type %d) inserted.\n",
8544 t4_os_link_changed(struct adapter *sc, int idx, int link_stat, int reason)
8546 struct port_info *pi = sc->port[idx];
8555 pi->linkdnrc = reason;
8557 for_each_vi(pi, v, vi) {
8563 ifp->if_baudrate = IF_Mbps(pi->link_cfg.speed);
8564 if_link_state_change(ifp, LINK_STATE_UP);
8566 if_link_state_change(ifp, LINK_STATE_DOWN);
8572 t4_iterate(void (*func)(struct adapter *, void *), void *arg)
8576 sx_slock(&t4_list_lock);
8577 SLIST_FOREACH(sc, &t4_list, link) {
8579 * func should not make any assumptions about what state sc is
8580 * in - the only guarantee is that sc->sc_lock is a valid lock.
8584 sx_sunlock(&t4_list_lock);
8588 t4_open(struct cdev *dev, int flags, int type, struct thread *td)
8594 t4_close(struct cdev *dev, int flags, int type, struct thread *td)
8600 t4_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
8604 struct adapter *sc = dev->si_drv1;
8606 rc = priv_check(td, PRIV_DRIVER);
8611 case CHELSIO_T4_GETREG: {
8612 struct t4_reg *edata = (struct t4_reg *)data;
8614 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8617 if (edata->size == 4)
8618 edata->val = t4_read_reg(sc, edata->addr);
8619 else if (edata->size == 8)
8620 edata->val = t4_read_reg64(sc, edata->addr);
8626 case CHELSIO_T4_SETREG: {
8627 struct t4_reg *edata = (struct t4_reg *)data;
8629 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
8632 if (edata->size == 4) {
8633 if (edata->val & 0xffffffff00000000)
8635 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
8636 } else if (edata->size == 8)
8637 t4_write_reg64(sc, edata->addr, edata->val);
8642 case CHELSIO_T4_REGDUMP: {
8643 struct t4_regdump *regs = (struct t4_regdump *)data;
8644 int reglen = is_t4(sc) ? T4_REGDUMP_SIZE : T5_REGDUMP_SIZE;
8647 if (regs->len < reglen) {
8648 regs->len = reglen; /* hint to the caller */
8653 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
8654 get_regs(sc, regs, buf);
8655 rc = copyout(buf, regs->data, reglen);
8659 case CHELSIO_T4_GET_FILTER_MODE:
8660 rc = get_filter_mode(sc, (uint32_t *)data);
8662 case CHELSIO_T4_SET_FILTER_MODE:
8663 rc = set_filter_mode(sc, *(uint32_t *)data);
8665 case CHELSIO_T4_GET_FILTER:
8666 rc = get_filter(sc, (struct t4_filter *)data);
8668 case CHELSIO_T4_SET_FILTER:
8669 rc = set_filter(sc, (struct t4_filter *)data);
8671 case CHELSIO_T4_DEL_FILTER:
8672 rc = del_filter(sc, (struct t4_filter *)data);
8674 case CHELSIO_T4_GET_SGE_CONTEXT:
8675 rc = get_sge_context(sc, (struct t4_sge_context *)data);
8677 case CHELSIO_T4_LOAD_FW:
8678 rc = load_fw(sc, (struct t4_data *)data);
8680 case CHELSIO_T4_GET_MEM:
8681 rc = read_card_mem(sc, 2, (struct t4_mem_range *)data);
8683 case CHELSIO_T4_GET_I2C:
8684 rc = read_i2c(sc, (struct t4_i2c_data *)data);
8686 case CHELSIO_T4_CLEAR_STATS: {
8688 u_int port_id = *(uint32_t *)data;
8689 struct port_info *pi;
8692 if (port_id >= sc->params.nports)
8694 pi = sc->port[port_id];
8697 t4_clr_port_stats(sc, pi->tx_chan);
8698 pi->tx_parse_error = 0;
8699 mtx_lock(&sc->reg_lock);
8700 for_each_vi(pi, v, vi) {
8701 if (vi->flags & VI_INIT_DONE)
8702 t4_clr_vi_stats(sc, vi->viid);
8704 mtx_unlock(&sc->reg_lock);
8707 * Since this command accepts a port, clear stats for
8708 * all VIs on this port.
8710 for_each_vi(pi, v, vi) {
8711 if (vi->flags & VI_INIT_DONE) {
8712 struct sge_rxq *rxq;
8713 struct sge_txq *txq;
8714 struct sge_wrq *wrq;
8716 for_each_rxq(vi, i, rxq) {
8717 #if defined(INET) || defined(INET6)
8718 rxq->lro.lro_queued = 0;
8719 rxq->lro.lro_flushed = 0;
8722 rxq->vlan_extraction = 0;
8725 for_each_txq(vi, i, txq) {
8728 txq->vlan_insertion = 0;
8732 txq->txpkts0_wrs = 0;
8733 txq->txpkts1_wrs = 0;
8734 txq->txpkts0_pkts = 0;
8735 txq->txpkts1_pkts = 0;
8736 mp_ring_reset_stats(txq->r);
8740 /* nothing to clear for each ofld_rxq */
8742 for_each_ofld_txq(vi, i, wrq) {
8743 wrq->tx_wrs_direct = 0;
8744 wrq->tx_wrs_copied = 0;
8748 if (IS_MAIN_VI(vi)) {
8749 wrq = &sc->sge.ctrlq[pi->port_id];
8750 wrq->tx_wrs_direct = 0;
8751 wrq->tx_wrs_copied = 0;
8757 case CHELSIO_T4_SCHED_CLASS:
8758 rc = set_sched_class(sc, (struct t4_sched_params *)data);
8760 case CHELSIO_T4_SCHED_QUEUE:
8761 rc = set_sched_queue(sc, (struct t4_sched_queue *)data);
8763 case CHELSIO_T4_GET_TRACER:
8764 rc = t4_get_tracer(sc, (struct t4_tracer *)data);
8766 case CHELSIO_T4_SET_TRACER:
8767 rc = t4_set_tracer(sc, (struct t4_tracer *)data);
8777 t4_db_full(struct adapter *sc)
8780 CXGBE_UNIMPLEMENTED(__func__);
8784 t4_db_dropped(struct adapter *sc)
8787 CXGBE_UNIMPLEMENTED(__func__);
8792 t4_iscsi_init(struct adapter *sc, u_int tag_mask, const u_int *pgsz_order)
8795 t4_write_reg(sc, A_ULP_RX_ISCSI_TAGMASK, tag_mask);
8796 t4_write_reg(sc, A_ULP_RX_ISCSI_PSZ, V_HPZ0(pgsz_order[0]) |
8797 V_HPZ1(pgsz_order[1]) | V_HPZ2(pgsz_order[2]) |
8798 V_HPZ3(pgsz_order[3]));
8802 toe_capability(struct vi_info *vi, int enable)
8805 struct port_info *pi = vi->pi;
8806 struct adapter *sc = pi->adapter;
8808 ASSERT_SYNCHRONIZED_OP(sc);
8810 if (!is_offload(sc))
8814 if ((vi->ifp->if_capenable & IFCAP_TOE) != 0) {
8815 /* TOE is already enabled. */
8820 * We need the port's queues around so that we're able to send
8821 * and receive CPLs to/from the TOE even if the ifnet for this
8822 * port has never been UP'd administratively.
8824 if (!(vi->flags & VI_INIT_DONE)) {
8825 rc = vi_full_init(vi);
8829 if (!(pi->vi[0].flags & VI_INIT_DONE)) {
8830 rc = vi_full_init(&pi->vi[0]);
8835 if (isset(&sc->offload_map, pi->port_id)) {
8836 /* TOE is enabled on another VI of this port. */
8841 if (!uld_active(sc, ULD_TOM)) {
8842 rc = t4_activate_uld(sc, ULD_TOM);
8845 "You must kldload t4_tom.ko before trying "
8846 "to enable TOE on a cxgbe interface.\n");
8850 KASSERT(sc->tom_softc != NULL,
8851 ("%s: TOM activated but softc NULL", __func__));
8852 KASSERT(uld_active(sc, ULD_TOM),
8853 ("%s: TOM activated but flag not set", __func__));
8856 /* Activate iWARP and iSCSI too, if the modules are loaded. */
8857 if (!uld_active(sc, ULD_IWARP))
8858 (void) t4_activate_uld(sc, ULD_IWARP);
8859 if (!uld_active(sc, ULD_ISCSI))
8860 (void) t4_activate_uld(sc, ULD_ISCSI);
8863 setbit(&sc->offload_map, pi->port_id);
8867 if (!isset(&sc->offload_map, pi->port_id) || pi->uld_vis > 0)
8870 KASSERT(uld_active(sc, ULD_TOM),
8871 ("%s: TOM never initialized?", __func__));
8872 clrbit(&sc->offload_map, pi->port_id);
8879 * Add an upper layer driver to the global list.
8882 t4_register_uld(struct uld_info *ui)
8887 sx_xlock(&t4_uld_list_lock);
8888 SLIST_FOREACH(u, &t4_uld_list, link) {
8889 if (u->uld_id == ui->uld_id) {
8895 SLIST_INSERT_HEAD(&t4_uld_list, ui, link);
8898 sx_xunlock(&t4_uld_list_lock);
8903 t4_unregister_uld(struct uld_info *ui)
8908 sx_xlock(&t4_uld_list_lock);
8910 SLIST_FOREACH(u, &t4_uld_list, link) {
8912 if (ui->refcount > 0) {
8917 SLIST_REMOVE(&t4_uld_list, ui, uld_info, link);
8923 sx_xunlock(&t4_uld_list_lock);
8928 t4_activate_uld(struct adapter *sc, int id)
8931 struct uld_info *ui;
8933 ASSERT_SYNCHRONIZED_OP(sc);
8935 if (id < 0 || id > ULD_MAX)
8937 rc = EAGAIN; /* kldoad the module with this ULD and try again. */
8939 sx_slock(&t4_uld_list_lock);
8941 SLIST_FOREACH(ui, &t4_uld_list, link) {
8942 if (ui->uld_id == id) {
8943 if (!(sc->flags & FULL_INIT_DONE)) {
8944 rc = adapter_full_init(sc);
8949 rc = ui->activate(sc);
8951 setbit(&sc->active_ulds, id);
8958 sx_sunlock(&t4_uld_list_lock);
8964 t4_deactivate_uld(struct adapter *sc, int id)
8967 struct uld_info *ui;
8969 ASSERT_SYNCHRONIZED_OP(sc);
8971 if (id < 0 || id > ULD_MAX)
8975 sx_slock(&t4_uld_list_lock);
8977 SLIST_FOREACH(ui, &t4_uld_list, link) {
8978 if (ui->uld_id == id) {
8979 rc = ui->deactivate(sc);
8981 clrbit(&sc->active_ulds, id);
8988 sx_sunlock(&t4_uld_list_lock);
8994 uld_active(struct adapter *sc, int uld_id)
8997 MPASS(uld_id >= 0 && uld_id <= ULD_MAX);
8999 return (isset(&sc->active_ulds, uld_id));
9004 * Come up with reasonable defaults for some of the tunables, provided they're
9005 * not set by the user (in which case we'll use the values as is).
9008 tweak_tunables(void)
9010 int nc = mp_ncpus; /* our snapshot of the number of CPUs */
9012 if (t4_ntxq10g < 1) {
9014 t4_ntxq10g = rss_getnumbuckets();
9016 t4_ntxq10g = min(nc, NTXQ_10G);
9020 if (t4_ntxq1g < 1) {
9022 /* XXX: way too many for 1GbE? */
9023 t4_ntxq1g = rss_getnumbuckets();
9025 t4_ntxq1g = min(nc, NTXQ_1G);
9030 t4_ntxq_vi = min(nc, NTXQ_VI);
9032 if (t4_nrxq10g < 1) {
9034 t4_nrxq10g = rss_getnumbuckets();
9036 t4_nrxq10g = min(nc, NRXQ_10G);
9040 if (t4_nrxq1g < 1) {
9042 /* XXX: way too many for 1GbE? */
9043 t4_nrxq1g = rss_getnumbuckets();
9045 t4_nrxq1g = min(nc, NRXQ_1G);
9050 t4_nrxq_vi = min(nc, NRXQ_VI);
9053 if (t4_nofldtxq10g < 1)
9054 t4_nofldtxq10g = min(nc, NOFLDTXQ_10G);
9056 if (t4_nofldtxq1g < 1)
9057 t4_nofldtxq1g = min(nc, NOFLDTXQ_1G);
9059 if (t4_nofldtxq_vi < 1)
9060 t4_nofldtxq_vi = min(nc, NOFLDTXQ_VI);
9062 if (t4_nofldrxq10g < 1)
9063 t4_nofldrxq10g = min(nc, NOFLDRXQ_10G);
9065 if (t4_nofldrxq1g < 1)
9066 t4_nofldrxq1g = min(nc, NOFLDRXQ_1G);
9068 if (t4_nofldrxq_vi < 1)
9069 t4_nofldrxq_vi = min(nc, NOFLDRXQ_VI);
9071 if (t4_toecaps_allowed == -1)
9072 t4_toecaps_allowed = FW_CAPS_CONFIG_TOE;
9074 if (t4_rdmacaps_allowed == -1) {
9075 t4_rdmacaps_allowed = FW_CAPS_CONFIG_RDMA_RDDP |
9076 FW_CAPS_CONFIG_RDMA_RDMAC;
9079 if (t4_iscsicaps_allowed == -1) {
9080 t4_iscsicaps_allowed = FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU |
9081 FW_CAPS_CONFIG_ISCSI_TARGET_PDU |
9082 FW_CAPS_CONFIG_ISCSI_T10DIF;
9085 if (t4_toecaps_allowed == -1)
9086 t4_toecaps_allowed = 0;
9088 if (t4_rdmacaps_allowed == -1)
9089 t4_rdmacaps_allowed = 0;
9091 if (t4_iscsicaps_allowed == -1)
9092 t4_iscsicaps_allowed = 0;
9096 if (t4_nnmtxq_vi < 1)
9097 t4_nnmtxq_vi = min(nc, NNMTXQ_VI);
9099 if (t4_nnmrxq_vi < 1)
9100 t4_nnmrxq_vi = min(nc, NNMRXQ_VI);
9103 if (t4_tmr_idx_10g < 0 || t4_tmr_idx_10g >= SGE_NTIMERS)
9104 t4_tmr_idx_10g = TMR_IDX_10G;
9106 if (t4_pktc_idx_10g < -1 || t4_pktc_idx_10g >= SGE_NCOUNTERS)
9107 t4_pktc_idx_10g = PKTC_IDX_10G;
9109 if (t4_tmr_idx_1g < 0 || t4_tmr_idx_1g >= SGE_NTIMERS)
9110 t4_tmr_idx_1g = TMR_IDX_1G;
9112 if (t4_pktc_idx_1g < -1 || t4_pktc_idx_1g >= SGE_NCOUNTERS)
9113 t4_pktc_idx_1g = PKTC_IDX_1G;
9115 if (t4_qsize_txq < 128)
9118 if (t4_qsize_rxq < 128)
9120 while (t4_qsize_rxq & 7)
9123 t4_intr_types &= INTR_MSIX | INTR_MSI | INTR_INTX;
9128 t4_dump_tcb(struct adapter *sc, int tid)
9130 uint32_t base, i, j, off, pf, reg, save, tcb_addr, win_pos;
9132 reg = PCIE_MEM_ACCESS_REG(A_PCIE_MEM_ACCESS_OFFSET, 2);
9133 save = t4_read_reg(sc, reg);
9134 base = sc->memwin[2].mw_base;
9136 /* Dump TCB for the tid */
9137 tcb_addr = t4_read_reg(sc, A_TP_CMM_TCB_BASE);
9138 tcb_addr += tid * TCB_SIZE;
9142 win_pos = tcb_addr & ~0xf; /* start must be 16B aligned */
9144 pf = V_PFNUM(sc->pf);
9145 win_pos = tcb_addr & ~0x7f; /* start must be 128B aligned */
9147 t4_write_reg(sc, reg, win_pos | pf);
9148 t4_read_reg(sc, reg);
9150 off = tcb_addr - win_pos;
9151 for (i = 0; i < 4; i++) {
9153 for (j = 0; j < 8; j++, off += 4)
9154 buf[j] = htonl(t4_read_reg(sc, base + off));
9156 db_printf("%08x %08x %08x %08x %08x %08x %08x %08x\n",
9157 buf[0], buf[1], buf[2], buf[3], buf[4], buf[5], buf[6],
9161 t4_write_reg(sc, reg, save);
9162 t4_read_reg(sc, reg);
9166 t4_dump_devlog(struct adapter *sc)
9168 struct devlog_params *dparams = &sc->params.devlog;
9169 struct fw_devlog_e e;
9170 int i, first, j, m, nentries, rc;
9171 uint64_t ftstamp = UINT64_MAX;
9173 if (dparams->start == 0) {
9174 db_printf("devlog params not valid\n");
9178 nentries = dparams->size / sizeof(struct fw_devlog_e);
9179 m = fwmtype_to_hwmtype(dparams->memtype);
9181 /* Find the first entry. */
9183 for (i = 0; i < nentries && !db_pager_quit; i++) {
9184 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9185 sizeof(e), (void *)&e);
9189 if (e.timestamp == 0)
9192 e.timestamp = be64toh(e.timestamp);
9193 if (e.timestamp < ftstamp) {
9194 ftstamp = e.timestamp;
9204 rc = -t4_mem_read(sc, m, dparams->start + i * sizeof(e),
9205 sizeof(e), (void *)&e);
9209 if (e.timestamp == 0)
9212 e.timestamp = be64toh(e.timestamp);
9213 e.seqno = be32toh(e.seqno);
9214 for (j = 0; j < 8; j++)
9215 e.params[j] = be32toh(e.params[j]);
9217 db_printf("%10d %15ju %8s %8s ",
9218 e.seqno, e.timestamp,
9219 (e.level < nitems(devlog_level_strings) ?
9220 devlog_level_strings[e.level] : "UNKNOWN"),
9221 (e.facility < nitems(devlog_facility_strings) ?
9222 devlog_facility_strings[e.facility] : "UNKNOWN"));
9223 db_printf(e.fmt, e.params[0], e.params[1], e.params[2],
9224 e.params[3], e.params[4], e.params[5], e.params[6],
9227 if (++i == nentries)
9229 } while (i != first && !db_pager_quit);
9232 static struct command_table db_t4_table = LIST_HEAD_INITIALIZER(db_t4_table);
9233 _DB_SET(_show, t4, NULL, db_show_table, 0, &db_t4_table);
9235 DB_FUNC(devlog, db_show_devlog, db_t4_table, CS_OWN, NULL)
9242 t = db_read_token();
9244 dev = device_lookup_by_name(db_tok_string);
9249 db_printf("usage: show t4 devlog <nexus>\n");
9254 db_printf("device not found\n");
9258 t4_dump_devlog(device_get_softc(dev));
9261 DB_FUNC(tcb, db_show_t4tcb, db_t4_table, CS_OWN, NULL)
9270 t = db_read_token();
9272 dev = device_lookup_by_name(db_tok_string);
9273 t = db_read_token();
9275 tid = db_tok_number;
9282 db_printf("usage: show t4 tcb <nexus> <tid>\n");
9287 db_printf("device not found\n");
9291 db_printf("invalid tid\n");
9295 t4_dump_tcb(device_get_softc(dev), tid);
9299 static struct sx mlu; /* mod load unload */
9300 SX_SYSINIT(cxgbe_mlu, &mlu, "cxgbe mod load/unload");
9303 mod_event(module_t mod, int cmd, void *arg)
9306 static int loaded = 0;
9311 if (loaded++ == 0) {
9313 t4_register_cpl_handler(CPL_SET_TCB_RPL, set_tcb_rpl);
9314 t4_register_cpl_handler(CPL_L2T_WRITE_RPL, l2t_write_rpl);
9315 t4_register_cpl_handler(CPL_TRACE_PKT, t4_trace_pkt);
9316 t4_register_cpl_handler(CPL_T5_TRACE_PKT, t5_trace_pkt);
9317 sx_init(&t4_list_lock, "T4/T5 adapters");
9318 SLIST_INIT(&t4_list);
9320 sx_init(&t4_uld_list_lock, "T4/T5 ULDs");
9321 SLIST_INIT(&t4_uld_list);
9323 t4_tracer_modload();
9331 if (--loaded == 0) {
9334 sx_slock(&t4_list_lock);
9335 if (!SLIST_EMPTY(&t4_list)) {
9337 sx_sunlock(&t4_list_lock);
9341 sx_slock(&t4_uld_list_lock);
9342 if (!SLIST_EMPTY(&t4_uld_list)) {
9344 sx_sunlock(&t4_uld_list_lock);
9345 sx_sunlock(&t4_list_lock);
9350 while (tries++ < 5 && t4_sge_extfree_refs() != 0) {
9351 uprintf("%ju clusters with custom free routine "
9352 "still is use.\n", t4_sge_extfree_refs());
9353 pause("t4unload", 2 * hz);
9356 sx_sunlock(&t4_uld_list_lock);
9358 sx_sunlock(&t4_list_lock);
9360 if (t4_sge_extfree_refs() == 0) {
9361 t4_tracer_modunload();
9363 sx_destroy(&t4_uld_list_lock);
9365 sx_destroy(&t4_list_lock);
9370 loaded++; /* undo earlier decrement */
9381 static devclass_t t4_devclass, t5_devclass;
9382 static devclass_t cxgbe_devclass, cxl_devclass;
9383 static devclass_t vcxgbe_devclass, vcxl_devclass;
9385 DRIVER_MODULE(t4nex, pci, t4_driver, t4_devclass, mod_event, 0);
9386 MODULE_VERSION(t4nex, 1);
9387 MODULE_DEPEND(t4nex, firmware, 1, 1, 1);
9389 DRIVER_MODULE(t5nex, pci, t5_driver, t5_devclass, mod_event, 0);
9390 MODULE_VERSION(t5nex, 1);
9391 MODULE_DEPEND(t5nex, firmware, 1, 1, 1);
9393 DRIVER_MODULE(cxgbe, t4nex, cxgbe_driver, cxgbe_devclass, 0, 0);
9394 MODULE_VERSION(cxgbe, 1);
9396 DRIVER_MODULE(cxl, t5nex, cxl_driver, cxl_devclass, 0, 0);
9397 MODULE_VERSION(cxl, 1);
9399 DRIVER_MODULE(vcxgbe, cxgbe, vcxgbe_driver, vcxgbe_devclass, 0, 0);
9400 MODULE_VERSION(vcxgbe, 1);
9402 DRIVER_MODULE(vcxl, cxl, vcxl_driver, vcxl_devclass, 0, 0);
9403 MODULE_VERSION(vcxl, 1);