2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/types.h>
36 #include <sys/socket.h>
37 #include <sys/kernel.h>
39 #include <sys/malloc.h>
40 #include <sys/queue.h>
42 #include <sys/taskqueue.h>
44 #include <sys/sysctl.h>
46 #include <sys/counter.h>
48 #include <net/ethernet.h>
50 #include <net/if_vlan_var.h>
51 #include <netinet/in.h>
52 #include <netinet/ip.h>
53 #include <netinet/ip6.h>
54 #include <netinet/tcp.h>
55 #include <machine/md_var.h>
59 #include <machine/bus.h>
60 #include <sys/selinfo.h>
61 #include <net/if_var.h>
62 #include <net/netmap.h>
63 #include <dev/netmap/netmap_kern.h>
66 #include "common/common.h"
67 #include "common/t4_regs.h"
68 #include "common/t4_regs_values.h"
69 #include "common/t4_msg.h"
71 #ifdef T4_PKT_TIMESTAMP
72 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
74 #define RX_COPY_THRESHOLD MINCLSIZE
78 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
79 * 0-7 are valid values.
82 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
85 * Pad ethernet payload up to this boundary.
86 * -1: driver should figure out a good value.
88 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
91 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
95 * -1: driver should figure out a good value.
96 * 64 or 128 are the only other valid values.
99 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
103 * -1: no congestion feedback (not recommended).
104 * 0: backpressure the channel instead of dropping packets right away.
105 * 1: no backpressure, drop packets for the congested queue immediately.
107 static int cong_drop = 0;
108 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
111 * Deliver multiple frames in the same free list buffer if they fit.
112 * -1: let the driver decide whether to enable buffer packing or not.
113 * 0: disable buffer packing.
114 * 1: enable buffer packing.
116 static int buffer_packing = -1;
117 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
120 * Start next frame in a packed buffer at this boundary.
121 * -1: driver should figure out a good value.
122 * T4: driver will ignore this and use the same value as fl_pad above.
123 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
125 static int fl_pack = -1;
126 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
129 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
130 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
131 * 1: ok to create mbuf(s) within a cluster if there is room.
133 static int allow_mbufs_in_cluster = 1;
134 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster);
137 * Largest rx cluster size that the driver is allowed to allocate.
139 static int largest_rx_cluster = MJUM16BYTES;
140 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster);
143 * Size of cluster allocation that's most likely to succeed. The driver will
144 * fall back to this size if it fails to allocate clusters larger than this.
146 static int safest_rx_cluster = PAGE_SIZE;
147 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster);
149 /* Used to track coalesced tx work request */
151 uint64_t *flitp; /* ptr to flit where next pkt should start */
152 uint8_t npkt; /* # of packets in this work request */
153 uint8_t nflits; /* # of flits used by this work request */
154 uint16_t plen; /* total payload (sum of all packets) */
157 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
159 int nsegs; /* # of segments in the SGL, 0 means imm. tx */
160 int nflits; /* # of flits needed for the SGL */
161 bus_dma_segment_t seg[TX_SGL_SEGS];
164 static int service_iq(struct sge_iq *, int);
165 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
166 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
167 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
168 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
169 static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t,
171 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
172 bus_addr_t *, void **);
173 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
175 static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *,
177 static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *);
178 static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
180 static int alloc_fwq(struct adapter *);
181 static int free_fwq(struct adapter *);
182 static int alloc_mgmtq(struct adapter *);
183 static int free_mgmtq(struct adapter *);
184 static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int,
185 struct sysctl_oid *);
186 static int free_rxq(struct port_info *, struct sge_rxq *);
188 static int alloc_ofld_rxq(struct port_info *, struct sge_ofld_rxq *, int, int,
189 struct sysctl_oid *);
190 static int free_ofld_rxq(struct port_info *, struct sge_ofld_rxq *);
193 static int alloc_nm_rxq(struct port_info *, struct sge_nm_rxq *, int, int,
194 struct sysctl_oid *);
195 static int free_nm_rxq(struct port_info *, struct sge_nm_rxq *);
196 static int alloc_nm_txq(struct port_info *, struct sge_nm_txq *, int, int,
197 struct sysctl_oid *);
198 static int free_nm_txq(struct port_info *, struct sge_nm_txq *);
200 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
201 static int eth_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *);
203 static int ofld_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *);
205 static int alloc_eq(struct adapter *, struct port_info *, struct sge_eq *);
206 static int free_eq(struct adapter *, struct sge_eq *);
207 static int alloc_wrq(struct adapter *, struct port_info *, struct sge_wrq *,
208 struct sysctl_oid *);
209 static int free_wrq(struct adapter *, struct sge_wrq *);
210 static int alloc_txq(struct port_info *, struct sge_txq *, int,
211 struct sysctl_oid *);
212 static int free_txq(struct port_info *, struct sge_txq *);
213 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
214 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
215 static int refill_fl(struct adapter *, struct sge_fl *, int);
216 static void refill_sfl(void *);
217 static int alloc_fl_sdesc(struct sge_fl *);
218 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
219 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
220 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
221 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
223 static int get_pkt_sgl(struct sge_txq *, struct mbuf **, struct sgl *, int);
224 static int free_pkt_sgl(struct sge_txq *, struct sgl *);
225 static int write_txpkt_wr(struct port_info *, struct sge_txq *, struct mbuf *,
227 static int add_to_txpkts(struct port_info *, struct sge_txq *, struct txpkts *,
228 struct mbuf *, struct sgl *);
229 static void write_txpkts_wr(struct sge_txq *, struct txpkts *);
230 static inline void write_ulp_cpl_sgl(struct port_info *, struct sge_txq *,
231 struct txpkts *, struct mbuf *, struct sgl *);
232 static int write_sgl_to_txd(struct sge_eq *, struct sgl *, caddr_t *);
233 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
234 static inline void ring_eq_db(struct adapter *, struct sge_eq *);
235 static inline int reclaimable(struct sge_eq *);
236 static int reclaim_tx_descs(struct sge_txq *, int, int);
237 static void write_eqflush_wr(struct sge_eq *);
238 static __be64 get_flit(bus_dma_segment_t *, int, int);
239 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
241 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
244 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
245 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
247 static counter_u64_t extfree_refs;
248 static counter_u64_t extfree_rels;
251 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
257 if (fl_pktshift < 0 || fl_pktshift > 7) {
258 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
259 " using 2 instead.\n", fl_pktshift);
263 if (spg_len != 64 && spg_len != 128) {
266 #if defined(__i386__) || defined(__amd64__)
267 len = cpu_clflush_line_size > 64 ? 128 : 64;
272 printf("Invalid hw.cxgbe.spg_len value (%d),"
273 " using %d instead.\n", spg_len, len);
278 if (cong_drop < -1 || cong_drop > 1) {
279 printf("Invalid hw.cxgbe.cong_drop value (%d),"
280 " using 0 instead.\n", cong_drop);
284 extfree_refs = counter_u64_alloc(M_WAITOK);
285 extfree_rels = counter_u64_alloc(M_WAITOK);
286 counter_u64_zero(extfree_refs);
287 counter_u64_zero(extfree_rels);
291 t4_sge_modunload(void)
294 counter_u64_free(extfree_refs);
295 counter_u64_free(extfree_rels);
299 t4_sge_extfree_refs(void)
303 rels = counter_u64_fetch(extfree_rels);
304 refs = counter_u64_fetch(extfree_refs);
306 return (refs - rels);
310 t4_init_sge_cpl_handlers(struct adapter *sc)
313 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg);
314 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg);
315 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
316 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx);
317 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
321 setup_pad_and_pack_boundaries(struct adapter *sc)
327 if (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad)) {
329 * If there is any chance that we might use buffer packing and
330 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
331 * it to 32 in all other cases.
333 pad = is_t4(sc) && buffer_packing ? 64 : 32;
336 * For fl_pad = 0 we'll still write a reasonable value to the
337 * register but all the freelists will opt out of padding.
338 * We'll complain here only if the user tried to set it to a
339 * value greater than 0 that was invalid.
342 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
343 " (%d), using %d instead.\n", fl_pad, pad);
346 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
347 v = V_INGPADBOUNDARY(ilog2(pad) - 5);
348 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
351 if (fl_pack != -1 && fl_pack != pad) {
352 /* Complain but carry on. */
353 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
354 " using %d instead.\n", fl_pack, pad);
360 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
361 !powerof2(fl_pack)) {
362 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
363 MPASS(powerof2(pack));
371 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
372 " (%d), using %d instead.\n", fl_pack, pack);
375 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
377 v = V_INGPACKBOUNDARY(0);
379 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
381 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
382 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
386 * adap->params.vpd.cclk must be set up before this is called.
389 t4_tweak_chip_settings(struct adapter *sc)
393 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
394 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
395 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
396 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
397 static int sge_flbuf_sizes[] = {
399 #if MJUMPAGESIZE != MCLBYTES
401 MJUMPAGESIZE - CL_METADATA_SIZE,
402 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
406 MCLBYTES - MSIZE - CL_METADATA_SIZE,
407 MJUM9BYTES - CL_METADATA_SIZE,
408 MJUM16BYTES - CL_METADATA_SIZE,
411 KASSERT(sc->flags & MASTER_PF,
412 ("%s: trying to change chip settings when not master.", __func__));
414 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
415 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
416 V_EGRSTATUSPAGESIZE(spg_len == 128);
417 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
419 setup_pad_and_pack_boundaries(sc);
421 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
422 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
423 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
424 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
425 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
426 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
427 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
428 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
429 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
431 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
432 ("%s: hw buffer size table too big", __func__));
433 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
434 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
438 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
439 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
440 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
442 KASSERT(intr_timer[0] <= timer_max,
443 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
445 for (i = 1; i < nitems(intr_timer); i++) {
446 KASSERT(intr_timer[i] >= intr_timer[i - 1],
447 ("%s: timers not listed in increasing order (%d)",
450 while (intr_timer[i] > timer_max) {
451 if (i == nitems(intr_timer) - 1) {
452 intr_timer[i] = timer_max;
455 intr_timer[i] += intr_timer[i - 1];
460 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
461 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
462 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
463 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
464 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
465 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
466 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
467 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
468 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
470 if (cong_drop == 0) {
471 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 |
473 t4_set_reg_field(sc, A_TP_PARA_REG3, m, 0);
476 /* 4K, 16K, 64K, 256K DDP "page sizes" */
477 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
478 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
480 m = v = F_TDDPTAGTCB;
481 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
483 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
485 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
486 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
490 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
491 * padding is is use the buffer's start and end need to be aligned to the pad
492 * boundary as well. We'll just make sure that the size is a multiple of the
493 * boundary here, it is up to the buffer allocation code to make sure the start
494 * of the buffer is aligned as well.
497 hwsz_ok(struct adapter *sc, int hwsz)
499 int mask = fl_pad ? sc->sge.pad_boundary - 1 : 16 - 1;
501 return (hwsz >= 64 && (hwsz & mask) == 0);
505 * XXX: driver really should be able to deal with unexpected settings.
508 t4_read_chip_settings(struct adapter *sc)
510 struct sge *s = &sc->sge;
513 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
514 static int sw_buf_sizes[] = { /* Sorted by size */
516 #if MJUMPAGESIZE != MCLBYTES
522 struct sw_zone_info *swz, *safe_swz;
523 struct hw_buf_info *hwb;
525 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
526 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
527 V_EGRSTATUSPAGESIZE(spg_len == 128);
528 r = t4_read_reg(sc, A_SGE_CONTROL);
530 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
533 s->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 5);
536 s->pack_boundary = s->pad_boundary;
538 r = t4_read_reg(sc, A_SGE_CONTROL2);
539 if (G_INGPACKBOUNDARY(r) == 0)
540 s->pack_boundary = 16;
542 s->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
545 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
546 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
547 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
548 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
549 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
550 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
551 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
552 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
553 r = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE);
555 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
559 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
560 hwb = &s->hw_buf_info[0];
561 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
562 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i));
564 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
569 * Create a sorted list in decreasing order of hw buffer sizes (and so
570 * increasing order of spare area) for each software zone.
572 * If padding is enabled then the start and end of the buffer must align
573 * to the pad boundary; if packing is enabled then they must align with
574 * the pack boundary as well. Allocations from the cluster zones are
575 * aligned to min(size, 4K), so the buffer starts at that alignment and
576 * ends at hwb->size alignment. If mbuf inlining is allowed the
577 * starting alignment will be reduced to MSIZE and the driver will
578 * exercise appropriate caution when deciding on the best buffer layout
581 n = 0; /* no usable buffer size to begin with */
582 swz = &s->sw_zone_info[0];
584 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
585 int8_t head = -1, tail = -1;
587 swz->size = sw_buf_sizes[i];
588 swz->zone = m_getzone(swz->size);
589 swz->type = m_gettype(swz->size);
591 if (swz->size < PAGE_SIZE) {
592 MPASS(powerof2(swz->size));
593 if (fl_pad && (swz->size % sc->sge.pad_boundary != 0))
597 if (swz->size == safest_rx_cluster)
600 hwb = &s->hw_buf_info[0];
601 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
602 if (hwb->zidx != -1 || hwb->size > swz->size)
606 MPASS(hwb->size % sc->sge.pad_boundary == 0);
611 else if (hwb->size < s->hw_buf_info[tail].size) {
612 s->hw_buf_info[tail].next = j;
616 struct hw_buf_info *t;
618 for (cur = &head; *cur != -1; cur = &t->next) {
619 t = &s->hw_buf_info[*cur];
620 if (hwb->size == t->size) {
624 if (hwb->size > t->size) {
632 swz->head_hwidx = head;
633 swz->tail_hwidx = tail;
637 if (swz->size - s->hw_buf_info[tail].size >=
639 sc->flags |= BUF_PACKING_OK;
643 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
649 if (safe_swz != NULL) {
650 s->safe_hwidx1 = safe_swz->head_hwidx;
651 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
654 hwb = &s->hw_buf_info[i];
657 MPASS(hwb->size % sc->sge.pad_boundary == 0);
659 spare = safe_swz->size - hwb->size;
660 if (spare >= CL_METADATA_SIZE) {
667 r = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD);
668 s->counter_val[0] = G_THRESHOLD_0(r);
669 s->counter_val[1] = G_THRESHOLD_1(r);
670 s->counter_val[2] = G_THRESHOLD_2(r);
671 s->counter_val[3] = G_THRESHOLD_3(r);
673 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1);
674 s->timer_val[0] = G_TIMERVALUE0(r) / core_ticks_per_usec(sc);
675 s->timer_val[1] = G_TIMERVALUE1(r) / core_ticks_per_usec(sc);
676 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3);
677 s->timer_val[2] = G_TIMERVALUE2(r) / core_ticks_per_usec(sc);
678 s->timer_val[3] = G_TIMERVALUE3(r) / core_ticks_per_usec(sc);
679 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5);
680 s->timer_val[4] = G_TIMERVALUE4(r) / core_ticks_per_usec(sc);
681 s->timer_val[5] = G_TIMERVALUE5(r) / core_ticks_per_usec(sc);
683 if (cong_drop == 0) {
684 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 |
686 r = t4_read_reg(sc, A_TP_PARA_REG3);
688 device_printf(sc->dev,
689 "invalid TP_PARA_REG3(0x%x)\n", r);
694 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
695 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
697 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
701 m = v = F_TDDPTAGTCB;
702 r = t4_read_reg(sc, A_ULP_RX_CTL);
704 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
708 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
710 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
711 r = t4_read_reg(sc, A_TP_PARA_REG5);
713 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
717 r = t4_read_reg(sc, A_SGE_CONM_CTRL);
718 s->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
720 s->fl_starve_threshold2 = s->fl_starve_threshold;
722 s->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
724 /* egress queues: log2 of # of doorbells per BAR2 page */
725 r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
726 r >>= S_QUEUESPERPAGEPF0 +
727 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf;
728 s->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
730 /* ingress queues: log2 of # of doorbells per BAR2 page */
731 r = t4_read_reg(sc, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
732 r >>= S_QUEUESPERPAGEPF0 +
733 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf;
734 s->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
736 t4_init_tp_params(sc);
738 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
739 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
745 t4_create_dma_tag(struct adapter *sc)
749 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
750 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
751 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
754 device_printf(sc->dev,
755 "failed to create main DMA tag: %d\n", rc);
762 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
763 struct sysctl_oid_list *children)
766 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
767 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
768 "freelist buffer sizes");
770 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
771 NULL, fl_pktshift, "payload DMA offset in rx buffer (bytes)");
773 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
774 NULL, sc->sge.pad_boundary, "payload pad boundary (bytes)");
776 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
777 NULL, spg_len, "status page size (bytes)");
779 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
780 NULL, cong_drop, "congestion drop setting");
782 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
783 NULL, sc->sge.pack_boundary, "payload pack boundary (bytes)");
787 t4_destroy_dma_tag(struct adapter *sc)
790 bus_dma_tag_destroy(sc->dmat);
796 * Allocate and initialize the firmware event queue and the management queue.
798 * Returns errno on failure. Resources allocated up to that point may still be
799 * allocated. Caller is responsible for cleanup in case this function fails.
802 t4_setup_adapter_queues(struct adapter *sc)
806 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
808 sysctl_ctx_init(&sc->ctx);
809 sc->flags |= ADAP_SYSCTL_CTX;
812 * Firmware event queue
819 * Management queue. This is just a control queue that uses the fwq as
822 rc = alloc_mgmtq(sc);
831 t4_teardown_adapter_queues(struct adapter *sc)
834 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
836 /* Do this before freeing the queue */
837 if (sc->flags & ADAP_SYSCTL_CTX) {
838 sysctl_ctx_free(&sc->ctx);
839 sc->flags &= ~ADAP_SYSCTL_CTX;
849 port_intr_count(struct port_info *pi)
853 if (pi->flags & INTR_RXQ)
856 if (pi->flags & INTR_OFLD_RXQ)
860 if (pi->flags & INTR_NM_RXQ)
867 first_vector(struct port_info *pi)
869 struct adapter *sc = pi->adapter;
870 int rc = T4_EXTRA_INTR, i;
872 if (sc->intr_count == 1)
875 for_each_port(sc, i) {
876 if (i == pi->port_id)
879 rc += port_intr_count(sc->port[i]);
886 * Given an arbitrary "index," come up with an iq that can be used by other
887 * queues (of this port) for interrupt forwarding, SGE egress updates, etc.
888 * The iq returned is guaranteed to be something that takes direct interrupts.
890 static struct sge_iq *
891 port_intr_iq(struct port_info *pi, int idx)
893 struct adapter *sc = pi->adapter;
894 struct sge *s = &sc->sge;
895 struct sge_iq *iq = NULL;
898 if (sc->intr_count == 1)
899 return (&sc->sge.fwq);
901 nintr = port_intr_count(pi);
903 ("%s: pi %p has no exclusive interrupts, total interrupts = %d",
904 __func__, pi, sc->intr_count));
906 /* Exclude netmap queues as they can't take anyone else's interrupts */
907 if (pi->flags & INTR_NM_RXQ)
910 ("%s: pi %p has nintr %d after netmap adjustment of %d", __func__,
911 pi, nintr, pi->nnmrxq));
915 if (pi->flags & INTR_RXQ) {
917 iq = &s->rxq[pi->first_rxq + i].iq;
923 if (pi->flags & INTR_OFLD_RXQ) {
924 if (i < pi->nofldrxq) {
925 iq = &s->ofld_rxq[pi->first_ofld_rxq + i].iq;
931 panic("%s: pi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__,
932 pi, pi->flags & INTR_ALL, idx, nintr);
935 KASSERT(iq->flags & IQ_INTR,
936 ("%s: iq %p (port %p, intr_flags 0x%lx, idx %d)", __func__, iq, pi,
937 pi->flags & INTR_ALL, idx));
941 /* Maximum payload that can be delivered with a single iq descriptor */
943 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
949 payload = sc->tt.rx_coalesce ?
950 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu;
953 /* large enough even when hw VLAN extraction is disabled */
954 payload = fl_pktshift + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
964 t4_setup_port_queues(struct port_info *pi)
966 int rc = 0, i, j, intr_idx, iqid;
969 struct sge_wrq *ctrlq;
971 struct sge_ofld_rxq *ofld_rxq;
972 struct sge_wrq *ofld_txq;
975 struct sge_nm_rxq *nm_rxq;
976 struct sge_nm_txq *nm_txq;
979 struct adapter *sc = pi->adapter;
980 struct ifnet *ifp = pi->ifp;
981 struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev);
982 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
983 int maxp, mtu = ifp->if_mtu;
985 /* Interrupt vector to start from (when using multiple vectors) */
986 intr_idx = first_vector(pi);
989 * First pass over all NIC and TOE rx queues:
990 * a) initialize iq and fl
991 * b) allocate queue iff it will take direct interrupts.
993 maxp = mtu_to_max_payload(sc, mtu, 0);
994 if (pi->flags & INTR_RXQ) {
995 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq",
996 CTLFLAG_RD, NULL, "rx queues");
998 for_each_rxq(pi, i, rxq) {
1000 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, pi->qsize_rxq);
1002 snprintf(name, sizeof(name), "%s rxq%d-fl",
1003 device_get_nameunit(pi->dev), i);
1004 init_fl(sc, &rxq->fl, pi->qsize_rxq / 8, maxp, name);
1006 if (pi->flags & INTR_RXQ) {
1007 rxq->iq.flags |= IQ_INTR;
1008 rc = alloc_rxq(pi, rxq, intr_idx, i, oid);
1015 maxp = mtu_to_max_payload(sc, mtu, 1);
1016 if (is_offload(sc) && pi->flags & INTR_OFLD_RXQ) {
1017 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq",
1019 "rx queues for offloaded TCP connections");
1021 for_each_ofld_rxq(pi, i, ofld_rxq) {
1023 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx,
1026 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1027 device_get_nameunit(pi->dev), i);
1028 init_fl(sc, &ofld_rxq->fl, pi->qsize_rxq / 8, maxp, name);
1030 if (pi->flags & INTR_OFLD_RXQ) {
1031 ofld_rxq->iq.flags |= IQ_INTR;
1032 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid);
1041 * We don't have buffers to back the netmap rx queues right now so we
1042 * create the queues in a way that doesn't set off any congestion signal
1045 if (pi->flags & INTR_NM_RXQ) {
1046 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_rxq",
1047 CTLFLAG_RD, NULL, "rx queues for netmap");
1048 for_each_nm_rxq(pi, i, nm_rxq) {
1049 rc = alloc_nm_rxq(pi, nm_rxq, intr_idx, i, oid);
1058 * Second pass over all NIC and TOE rx queues. The queues forwarding
1059 * their interrupts are allocated now.
1062 if (!(pi->flags & INTR_RXQ)) {
1063 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq",
1064 CTLFLAG_RD, NULL, "rx queues");
1065 for_each_rxq(pi, i, rxq) {
1066 MPASS(!(rxq->iq.flags & IQ_INTR));
1068 intr_idx = port_intr_iq(pi, j)->abs_id;
1070 rc = alloc_rxq(pi, rxq, intr_idx, i, oid);
1077 if (is_offload(sc) && !(pi->flags & INTR_OFLD_RXQ)) {
1078 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq",
1080 "rx queues for offloaded TCP connections");
1081 for_each_ofld_rxq(pi, i, ofld_rxq) {
1082 MPASS(!(ofld_rxq->iq.flags & IQ_INTR));
1084 intr_idx = port_intr_iq(pi, j)->abs_id;
1086 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid);
1094 if (!(pi->flags & INTR_NM_RXQ))
1095 CXGBE_UNIMPLEMENTED(__func__);
1099 * Now the tx queues. Only one pass needed.
1101 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1104 for_each_txq(pi, i, txq) {
1105 iqid = port_intr_iq(pi, j)->cntxt_id;
1106 snprintf(name, sizeof(name), "%s txq%d",
1107 device_get_nameunit(pi->dev), i);
1108 init_eq(&txq->eq, EQ_ETH, pi->qsize_txq, pi->tx_chan, iqid,
1111 rc = alloc_txq(pi, txq, i, oid);
1117 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_txq",
1118 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections");
1119 for_each_ofld_txq(pi, i, ofld_txq) {
1120 struct sysctl_oid *oid2;
1122 iqid = port_intr_iq(pi, j)->cntxt_id;
1123 snprintf(name, sizeof(name), "%s ofld_txq%d",
1124 device_get_nameunit(pi->dev), i);
1125 init_eq(&ofld_txq->eq, EQ_OFLD, pi->qsize_txq, pi->tx_chan,
1128 snprintf(name, sizeof(name), "%d", i);
1129 oid2 = SYSCTL_ADD_NODE(&pi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1130 name, CTLFLAG_RD, NULL, "offload tx queue");
1132 rc = alloc_wrq(sc, pi, ofld_txq, oid2);
1139 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_txq",
1140 CTLFLAG_RD, NULL, "tx queues for netmap use");
1141 for_each_nm_txq(pi, i, nm_txq) {
1142 iqid = pi->first_nm_rxq + (j % pi->nnmrxq);
1143 rc = alloc_nm_txq(pi, nm_txq, iqid, i, oid);
1151 * Finally, the control queue.
1153 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
1154 NULL, "ctrl queue");
1155 ctrlq = &sc->sge.ctrlq[pi->port_id];
1156 iqid = port_intr_iq(pi, 0)->cntxt_id;
1157 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(pi->dev));
1158 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name);
1159 rc = alloc_wrq(sc, pi, ctrlq, oid);
1163 t4_teardown_port_queues(pi);
1172 t4_teardown_port_queues(struct port_info *pi)
1175 struct adapter *sc = pi->adapter;
1176 struct sge_rxq *rxq;
1177 struct sge_txq *txq;
1179 struct sge_ofld_rxq *ofld_rxq;
1180 struct sge_wrq *ofld_txq;
1183 struct sge_nm_rxq *nm_rxq;
1184 struct sge_nm_txq *nm_txq;
1187 /* Do this before freeing the queues */
1188 if (pi->flags & PORT_SYSCTL_CTX) {
1189 sysctl_ctx_free(&pi->ctx);
1190 pi->flags &= ~PORT_SYSCTL_CTX;
1194 * Take down all the tx queues first, as they reference the rx queues
1195 * (for egress updates, etc.).
1198 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
1200 for_each_txq(pi, i, txq) {
1204 for_each_ofld_txq(pi, i, ofld_txq) {
1205 free_wrq(sc, ofld_txq);
1209 for_each_nm_txq(pi, i, nm_txq)
1210 free_nm_txq(pi, nm_txq);
1214 * Then take down the rx queues that forward their interrupts, as they
1215 * reference other rx queues.
1218 for_each_rxq(pi, i, rxq) {
1219 if ((rxq->iq.flags & IQ_INTR) == 0)
1223 for_each_ofld_rxq(pi, i, ofld_rxq) {
1224 if ((ofld_rxq->iq.flags & IQ_INTR) == 0)
1225 free_ofld_rxq(pi, ofld_rxq);
1229 for_each_nm_rxq(pi, i, nm_rxq)
1230 free_nm_rxq(pi, nm_rxq);
1234 * Then take down the rx queues that take direct interrupts.
1237 for_each_rxq(pi, i, rxq) {
1238 if (rxq->iq.flags & IQ_INTR)
1242 for_each_ofld_rxq(pi, i, ofld_rxq) {
1243 if (ofld_rxq->iq.flags & IQ_INTR)
1244 free_ofld_rxq(pi, ofld_rxq);
1248 CXGBE_UNIMPLEMENTED(__func__);
1255 * Deals with errors and the firmware event queue. All data rx queues forward
1256 * their interrupt to the firmware event queue.
1259 t4_intr_all(void *arg)
1261 struct adapter *sc = arg;
1262 struct sge_iq *fwq = &sc->sge.fwq;
1265 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
1267 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
1271 /* Deals with error interrupts */
1273 t4_intr_err(void *arg)
1275 struct adapter *sc = arg;
1277 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1278 t4_slow_intr_handler(sc);
1282 t4_intr_evt(void *arg)
1284 struct sge_iq *iq = arg;
1286 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1288 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1295 struct sge_iq *iq = arg;
1297 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1299 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1304 * Deals with anything and everything on the given ingress queue.
1307 service_iq(struct sge_iq *iq, int budget)
1310 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */
1311 struct sge_fl *fl; /* Use iff IQ_HAS_FL */
1312 struct adapter *sc = iq->adapter;
1313 struct iq_desc *d = &iq->desc[iq->cidx];
1314 int ndescs = 0, limit;
1315 int rsp_type, refill;
1317 uint16_t fl_hw_cidx;
1319 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1320 #if defined(INET) || defined(INET6)
1321 const struct timeval lro_timeout = {0, sc->lro_timeout};
1324 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1326 limit = budget ? budget : iq->qsize / 16;
1328 if (iq->flags & IQ_HAS_FL) {
1330 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1333 fl_hw_cidx = 0; /* to silence gcc warning */
1337 * We always come back and check the descriptor ring for new indirect
1338 * interrupts and other responses after running a single handler.
1341 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1347 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1348 lq = be32toh(d->rsp.pldbuflen_qid);
1351 case X_RSPD_TYPE_FLBUF:
1353 KASSERT(iq->flags & IQ_HAS_FL,
1354 ("%s: data for an iq (%p) with no freelist",
1357 m0 = get_fl_payload(sc, fl, lq);
1358 if (__predict_false(m0 == NULL))
1360 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1361 #ifdef T4_PKT_TIMESTAMP
1363 * 60 bit timestamp for the payload is
1364 * *(uint64_t *)m0->m_pktdat. Note that it is
1365 * in the leading free-space in the mbuf. The
1366 * kernel can clobber it during a pullup,
1367 * m_copymdata, etc. You need to make sure that
1368 * the mbuf reaches you unmolested if you care
1369 * about the timestamp.
1371 *(uint64_t *)m0->m_pktdat =
1372 be64toh(ctrl->u.last_flit) &
1378 case X_RSPD_TYPE_CPL:
1379 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1380 ("%s: bad opcode %02x.", __func__,
1382 sc->cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1385 case X_RSPD_TYPE_INTR:
1388 * Interrupts should be forwarded only to queues
1389 * that are not forwarding their interrupts.
1390 * This means service_iq can recurse but only 1
1393 KASSERT(budget == 0,
1394 ("%s: budget %u, rsp_type %u", __func__,
1398 * There are 1K interrupt-capable queues (qids 0
1399 * through 1023). A response type indicating a
1400 * forwarded interrupt with a qid >= 1K is an
1401 * iWARP async notification.
1404 sc->an_handler(iq, &d->rsp);
1408 q = sc->sge.iqmap[lq - sc->sge.iq_start];
1409 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1411 if (service_iq(q, q->qsize / 16) == 0) {
1412 atomic_cmpset_int(&q->state,
1413 IQS_BUSY, IQS_IDLE);
1415 STAILQ_INSERT_TAIL(&iql, q,
1423 ("%s: illegal response type %d on iq %p",
1424 __func__, rsp_type, iq));
1426 "%s: illegal response type %d on iq %p",
1427 device_get_nameunit(sc->dev), rsp_type, iq);
1432 if (__predict_false(++iq->cidx == iq->sidx)) {
1434 iq->gen ^= F_RSPD_GEN;
1437 if (__predict_false(++ndescs == limit)) {
1438 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
1440 V_INGRESSQID(iq->cntxt_id) |
1441 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1444 #if defined(INET) || defined(INET6)
1445 if (iq->flags & IQ_LRO_ENABLED &&
1446 sc->lro_timeout != 0) {
1447 tcp_lro_flush_inactive(&rxq->lro,
1453 if (iq->flags & IQ_HAS_FL) {
1455 refill_fl(sc, fl, 32);
1458 return (EINPROGRESS);
1463 refill_fl(sc, fl, 32);
1465 fl_hw_cidx = fl->hw_cidx;
1470 if (STAILQ_EMPTY(&iql))
1474 * Process the head only, and send it to the back of the list if
1475 * it's still not done.
1477 q = STAILQ_FIRST(&iql);
1478 STAILQ_REMOVE_HEAD(&iql, link);
1479 if (service_iq(q, q->qsize / 8) == 0)
1480 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1482 STAILQ_INSERT_TAIL(&iql, q, link);
1485 #if defined(INET) || defined(INET6)
1486 if (iq->flags & IQ_LRO_ENABLED) {
1487 struct lro_ctrl *lro = &rxq->lro;
1488 struct lro_entry *l;
1490 while (!SLIST_EMPTY(&lro->lro_active)) {
1491 l = SLIST_FIRST(&lro->lro_active);
1492 SLIST_REMOVE_HEAD(&lro->lro_active, next);
1493 tcp_lro_flush(lro, l);
1498 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) |
1499 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1501 if (iq->flags & IQ_HAS_FL) {
1505 starved = refill_fl(sc, fl, 64);
1507 if (__predict_false(starved != 0))
1508 add_fl_to_sfl(sc, fl);
1515 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1517 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1520 MPASS(cll->region3 >= CL_METADATA_SIZE);
1525 static inline struct cluster_metadata *
1526 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1530 if (cl_has_metadata(fl, cll)) {
1531 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1533 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1539 rxb_free(struct mbuf *m, void *arg1, void *arg2)
1541 uma_zone_t zone = arg1;
1544 uma_zfree(zone, cl);
1545 counter_u64_add(extfree_rels, 1);
1547 return (EXT_FREE_OK);
1551 * The mbuf returned by this function could be allocated from zone_mbuf or
1552 * constructed in spare room in the cluster.
1554 * The mbuf carries the payload in one of these ways
1555 * a) frame inside the mbuf (mbuf from zone_mbuf)
1556 * b) m_cljset (for clusters without metadata) zone_mbuf
1557 * c) m_extaddref (cluster with metadata) inline mbuf
1558 * d) m_extaddref (cluster with metadata) zone_mbuf
1560 static struct mbuf *
1561 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1565 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1566 struct cluster_layout *cll = &sd->cll;
1567 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1568 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1569 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1573 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1574 len = min(remaining, blen);
1575 payload = sd->cl + cll->region1 + fl->rx_offset;
1576 if (fl->flags & FL_BUF_PACKING) {
1577 const u_int l = fr_offset + len;
1578 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1580 if (fl->rx_offset + len + pad < hwb->size)
1582 MPASS(fl->rx_offset + blen <= hwb->size);
1584 MPASS(fl->rx_offset == 0); /* not packing */
1588 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1591 * Copy payload into a freshly allocated mbuf.
1594 m = fr_offset == 0 ?
1595 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1598 fl->mbuf_allocated++;
1599 #ifdef T4_PKT_TIMESTAMP
1600 /* Leave room for a timestamp */
1603 /* copy data to mbuf */
1604 bcopy(payload, mtod(m, caddr_t), len);
1606 } else if (sd->nmbuf * MSIZE < cll->region1) {
1609 * There's spare room in the cluster for an mbuf. Create one
1610 * and associate it with the payload that's in the cluster.
1614 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1615 /* No bzero required */
1616 if (m_init(m, NULL, 0, M_NOWAIT, MT_DATA,
1617 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1620 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1622 if (sd->nmbuf++ == 0)
1623 counter_u64_add(extfree_refs, 1);
1628 * Grab an mbuf from zone_mbuf and associate it with the
1629 * payload in the cluster.
1632 m = fr_offset == 0 ?
1633 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1636 fl->mbuf_allocated++;
1638 m_extaddref(m, payload, blen, &clm->refcount,
1639 rxb_free, swz->zone, sd->cl);
1640 if (sd->nmbuf++ == 0)
1641 counter_u64_add(extfree_refs, 1);
1643 m_cljset(m, sd->cl, swz->type);
1644 sd->cl = NULL; /* consumed, not a recycle candidate */
1648 m->m_pkthdr.len = remaining;
1651 if (fl->flags & FL_BUF_PACKING) {
1652 fl->rx_offset += blen;
1653 MPASS(fl->rx_offset <= hwb->size);
1654 if (fl->rx_offset < hwb->size)
1655 return (m); /* without advancing the cidx */
1658 if (__predict_false(++fl->cidx % 8 == 0)) {
1659 uint16_t cidx = fl->cidx / 8;
1661 if (__predict_false(cidx == fl->sidx))
1662 fl->cidx = cidx = 0;
1670 static struct mbuf *
1671 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1673 struct mbuf *m0, *m, **pnext;
1675 const u_int total = G_RSPD_LEN(len_newbuf);
1677 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1678 M_ASSERTPKTHDR(fl->m0);
1679 MPASS(fl->m0->m_pkthdr.len == total);
1680 MPASS(fl->remaining < total);
1684 remaining = fl->remaining;
1685 fl->flags &= ~FL_BUF_RESUME;
1689 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1691 if (__predict_false(++fl->cidx % 8 == 0)) {
1692 uint16_t cidx = fl->cidx / 8;
1694 if (__predict_false(cidx == fl->sidx))
1695 fl->cidx = cidx = 0;
1701 * Payload starts at rx_offset in the current hw buffer. Its length is
1702 * 'len' and it may span multiple hw buffers.
1705 m0 = get_scatter_segment(sc, fl, 0, total);
1708 remaining = total - m0->m_len;
1709 pnext = &m0->m_next;
1710 while (remaining > 0) {
1712 MPASS(fl->rx_offset == 0);
1713 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1714 if (__predict_false(m == NULL)) {
1717 fl->remaining = remaining;
1718 fl->flags |= FL_BUF_RESUME;
1723 remaining -= m->m_len;
1731 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1733 struct sge_rxq *rxq = iq_to_rxq(iq);
1734 struct ifnet *ifp = rxq->ifp;
1735 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1736 #if defined(INET) || defined(INET6)
1737 struct lro_ctrl *lro = &rxq->lro;
1740 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1743 m0->m_pkthdr.len -= fl_pktshift;
1744 m0->m_len -= fl_pktshift;
1745 m0->m_data += fl_pktshift;
1747 m0->m_pkthdr.rcvif = ifp;
1748 m0->m_flags |= M_FLOWID;
1749 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
1751 if (cpl->csum_calc && !cpl->err_vec) {
1752 if (ifp->if_capenable & IFCAP_RXCSUM &&
1753 cpl->l2info & htobe32(F_RXF_IP)) {
1754 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1755 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1757 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1758 cpl->l2info & htobe32(F_RXF_IP6)) {
1759 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1764 if (__predict_false(cpl->ip_frag))
1765 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1767 m0->m_pkthdr.csum_data = 0xffff;
1771 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1772 m0->m_flags |= M_VLANTAG;
1773 rxq->vlan_extraction++;
1776 #if defined(INET) || defined(INET6)
1777 if (cpl->l2info & htobe32(F_RXF_LRO) &&
1778 iq->flags & IQ_LRO_ENABLED &&
1779 tcp_lro_rx(lro, m0, 0) == 0) {
1780 /* queued for LRO */
1783 ifp->if_input(ifp, m0);
1789 * Doesn't fail. Holds on to work requests it can't send right away.
1792 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
1794 struct sge_eq *eq = &wrq->eq;
1798 TXQ_LOCK_ASSERT_OWNED(wrq);
1800 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_OFLD ||
1801 (eq->flags & EQ_TYPEMASK) == EQ_CTRL,
1802 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK));
1804 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_CTRL,
1805 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK));
1808 if (__predict_true(wr != NULL))
1809 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
1811 can_reclaim = reclaimable(eq);
1812 if (__predict_false(eq->flags & EQ_STALLED)) {
1813 if (eq->avail + can_reclaim < tx_resume_threshold(eq))
1815 eq->flags &= ~EQ_STALLED;
1818 eq->cidx += can_reclaim;
1819 eq->avail += can_reclaim;
1820 if (__predict_false(eq->cidx >= eq->cap))
1821 eq->cidx -= eq->cap;
1823 while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL) {
1826 if (__predict_false(wr->wr_len < 0 ||
1827 wr->wr_len > SGE_MAX_WR_LEN || (wr->wr_len & 0x7))) {
1830 panic("%s: work request with length %d", __func__,
1836 log(LOG_ERR, "%s: %s work request with length %d",
1837 device_get_nameunit(sc->dev), __func__, wr->wr_len);
1838 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1843 ndesc = howmany(wr->wr_len, EQ_ESIZE);
1844 if (eq->avail < ndesc) {
1849 dst = (void *)&eq->desc[eq->pidx];
1850 copy_to_txd(eq, wrtod(wr), &dst, wr->wr_len);
1854 if (__predict_false(eq->pidx >= eq->cap))
1855 eq->pidx -= eq->cap;
1857 eq->pending += ndesc;
1858 if (eq->pending >= 8)
1862 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1865 if (eq->avail < 8) {
1866 can_reclaim = reclaimable(eq);
1867 eq->cidx += can_reclaim;
1868 eq->avail += can_reclaim;
1869 if (__predict_false(eq->cidx >= eq->cap))
1870 eq->cidx -= eq->cap;
1878 eq->flags |= EQ_STALLED;
1879 if (callout_pending(&eq->tx_callout) == 0)
1880 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq);
1884 /* Per-packet header in a coalesced tx WR, before the SGL starts (in flits) */
1885 #define TXPKTS_PKT_HDR ((\
1886 sizeof(struct ulp_txpkt) + \
1887 sizeof(struct ulptx_idata) + \
1888 sizeof(struct cpl_tx_pkt_core) \
1891 /* Header of a coalesced tx WR, before SGL of first packet (in flits) */
1892 #define TXPKTS_WR_HDR (\
1893 sizeof(struct fw_eth_tx_pkts_wr) / 8 + \
1896 /* Header of a tx WR, before SGL of first packet (in flits) */
1897 #define TXPKT_WR_HDR ((\
1898 sizeof(struct fw_eth_tx_pkt_wr) + \
1899 sizeof(struct cpl_tx_pkt_core) \
1902 /* Header of a tx LSO WR, before SGL of first packet (in flits) */
1903 #define TXPKT_LSO_WR_HDR ((\
1904 sizeof(struct fw_eth_tx_pkt_wr) + \
1905 sizeof(struct cpl_tx_pkt_lso_core) + \
1906 sizeof(struct cpl_tx_pkt_core) \
1910 t4_eth_tx(struct ifnet *ifp, struct sge_txq *txq, struct mbuf *m)
1912 struct port_info *pi = (void *)ifp->if_softc;
1913 struct adapter *sc = pi->adapter;
1914 struct sge_eq *eq = &txq->eq;
1915 struct buf_ring *br = txq->br;
1917 int rc, coalescing, can_reclaim;
1918 struct txpkts txpkts;
1921 TXQ_LOCK_ASSERT_OWNED(txq);
1922 KASSERT(m, ("%s: called with nothing to do.", __func__));
1923 KASSERT((eq->flags & EQ_TYPEMASK) == EQ_ETH,
1924 ("%s: eq type %d", __func__, eq->flags & EQ_TYPEMASK));
1926 prefetch(&eq->desc[eq->pidx]);
1927 prefetch(&txq->sdesc[eq->pidx]);
1929 txpkts.npkt = 0;/* indicates there's nothing in txpkts */
1932 can_reclaim = reclaimable(eq);
1933 if (__predict_false(eq->flags & EQ_STALLED)) {
1934 if (eq->avail + can_reclaim < tx_resume_threshold(eq)) {
1938 eq->flags &= ~EQ_STALLED;
1942 if (__predict_false(eq->flags & EQ_DOOMED)) {
1944 while ((m = buf_ring_dequeue_sc(txq->br)) != NULL)
1949 if (eq->avail < 8 && can_reclaim)
1950 reclaim_tx_descs(txq, can_reclaim, 32);
1952 for (; m; m = next ? next : drbr_dequeue(ifp, br)) {
1957 next = m->m_nextpkt;
1958 m->m_nextpkt = NULL;
1960 if (next || buf_ring_peek(br))
1963 rc = get_pkt_sgl(txq, &m, &sgl, coalescing);
1967 /* Short of resources, suspend tx */
1969 m->m_nextpkt = next;
1974 * Unrecoverable error for this packet, throw it away
1975 * and move on to the next. get_pkt_sgl may already
1976 * have freed m (it will be NULL in that case and the
1977 * m_freem here is still safe).
1985 add_to_txpkts(pi, txq, &txpkts, m, &sgl) == 0) {
1987 /* Successfully absorbed into txpkts */
1989 write_ulp_cpl_sgl(pi, txq, &txpkts, m, &sgl);
1994 * We weren't coalescing to begin with, or current frame could
1995 * not be coalesced (add_to_txpkts flushes txpkts if a frame
1996 * given to it can't be coalesced). Either way there should be
1997 * nothing in txpkts.
1999 KASSERT(txpkts.npkt == 0,
2000 ("%s: txpkts not empty: %d", __func__, txpkts.npkt));
2002 /* We're sending out individual packets now */
2006 reclaim_tx_descs(txq, 0, 8);
2007 rc = write_txpkt_wr(pi, txq, m, &sgl);
2010 /* Short of hardware descriptors, suspend tx */
2013 * This is an unlikely but expensive failure. We've
2014 * done all the hard work (DMA mappings etc.) and now we
2015 * can't send out the packet. What's worse, we have to
2016 * spend even more time freeing up everything in sgl.
2019 free_pkt_sgl(txq, &sgl);
2021 m->m_nextpkt = next;
2025 ETHER_BPF_MTAP(ifp, m);
2029 if (eq->pending >= 8)
2032 can_reclaim = reclaimable(eq);
2033 if (can_reclaim >= 32)
2034 reclaim_tx_descs(txq, can_reclaim, 64);
2037 if (txpkts.npkt > 0)
2038 write_txpkts_wr(txq, &txpkts);
2041 * m not NULL means there was an error but we haven't thrown it away.
2042 * This can happen when we're short of tx descriptors (no_desc) or maybe
2043 * even DMA maps (no_dmamap). Either way, a credit flush and reclaim
2044 * will get things going again.
2046 if (m && !(eq->flags & EQ_CRFLUSHED)) {
2047 struct tx_sdesc *txsd = &txq->sdesc[eq->pidx];
2050 * If EQ_CRFLUSHED is not set then we know we have at least one
2051 * available descriptor because any WR that reduces eq->avail to
2052 * 0 also sets EQ_CRFLUSHED.
2054 KASSERT(eq->avail > 0, ("%s: no space for eqflush.", __func__));
2056 txsd->desc_used = 1;
2058 write_eqflush_wr(eq);
2065 reclaim_tx_descs(txq, 0, 128);
2067 if (eq->flags & EQ_STALLED && callout_pending(&eq->tx_callout) == 0)
2068 callout_reset(&eq->tx_callout, 1, t4_tx_callout, eq);
2074 t4_update_fl_bufsize(struct ifnet *ifp)
2076 struct port_info *pi = ifp->if_softc;
2077 struct adapter *sc = pi->adapter;
2078 struct sge_rxq *rxq;
2080 struct sge_ofld_rxq *ofld_rxq;
2083 int i, maxp, mtu = ifp->if_mtu;
2085 maxp = mtu_to_max_payload(sc, mtu, 0);
2086 for_each_rxq(pi, i, rxq) {
2090 find_best_refill_source(sc, fl, maxp);
2094 maxp = mtu_to_max_payload(sc, mtu, 1);
2095 for_each_ofld_rxq(pi, i, ofld_rxq) {
2099 find_best_refill_source(sc, fl, maxp);
2106 can_resume_tx(struct sge_eq *eq)
2109 return (eq->avail + reclaimable(eq) >= tx_resume_threshold(eq));
2113 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2117 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2118 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2119 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2120 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2124 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2125 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2126 if (pktc_idx >= 0) {
2127 iq->intr_params |= F_QINTR_CNT_EN;
2128 iq->intr_pktc_idx = pktc_idx;
2130 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2131 iq->sidx = iq->qsize - spg_len / IQ_ESIZE;
2135 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
2139 fl->sidx = qsize - spg_len / EQ_ESIZE;
2140 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2141 if (sc->flags & BUF_PACKING_OK &&
2142 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
2143 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
2144 fl->flags |= FL_BUF_PACKING;
2145 find_best_refill_source(sc, fl, maxp);
2146 find_safe_refill_source(sc, fl);
2150 init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan,
2151 uint16_t iqid, char *name)
2153 KASSERT(tx_chan < NCHAN, ("%s: bad tx channel %d", __func__, tx_chan));
2154 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2156 eq->flags = eqtype & EQ_TYPEMASK;
2157 eq->tx_chan = tx_chan;
2160 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2162 TASK_INIT(&eq->tx_task, 0, t4_tx_task, eq);
2163 callout_init(&eq->tx_callout, CALLOUT_MPSAFE);
2167 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2168 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2172 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2173 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2175 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2179 rc = bus_dmamem_alloc(*tag, va,
2180 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2182 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2186 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2188 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2193 free_ring(sc, *tag, *map, *pa, *va);
2199 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2200 bus_addr_t pa, void *va)
2203 bus_dmamap_unload(tag, map);
2205 bus_dmamem_free(tag, va, map);
2207 bus_dma_tag_destroy(tag);
2213 * Allocates the ring for an ingress queue and an optional freelist. If the
2214 * freelist is specified it will be allocated and then associated with the
2217 * Returns errno on failure. Resources allocated up to that point may still be
2218 * allocated. Caller is responsible for cleanup in case this function fails.
2220 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then
2221 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies
2222 * the abs_id of the ingress queue to which its interrupts should be forwarded.
2225 alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
2226 int intr_idx, int cong)
2228 int rc, i, cntxt_id;
2231 struct adapter *sc = iq->adapter;
2234 len = iq->qsize * IQ_ESIZE;
2235 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2236 (void **)&iq->desc);
2240 bzero(&c, sizeof(c));
2241 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2242 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2243 V_FW_IQ_CMD_VFN(0));
2245 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2248 /* Special handling for firmware event queue */
2249 if (iq == &sc->sge.fwq)
2250 v |= F_FW_IQ_CMD_IQASYNCH;
2252 if (iq->flags & IQ_INTR) {
2253 KASSERT(intr_idx < sc->intr_count,
2254 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2256 v |= F_FW_IQ_CMD_IQANDST;
2257 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2259 c.type_to_iqandstindex = htobe32(v |
2260 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2261 V_FW_IQ_CMD_VIID(pi->viid) |
2262 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2263 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2264 F_FW_IQ_CMD_IQGTSMODE |
2265 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2266 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
2267 c.iqsize = htobe16(iq->qsize);
2268 c.iqaddr = htobe64(iq->ba);
2270 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2273 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2275 len = fl->qsize * EQ_ESIZE;
2276 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2277 &fl->ba, (void **)&fl->desc);
2281 /* Allocate space for one software descriptor per buffer. */
2282 rc = alloc_fl_sdesc(fl);
2284 device_printf(sc->dev,
2285 "failed to setup fl software descriptors: %d\n",
2290 if (fl->flags & FL_BUF_PACKING) {
2291 fl->lowat = roundup2(sc->sge.fl_starve_threshold2, 8);
2292 fl->buf_boundary = sc->sge.pack_boundary;
2294 fl->lowat = roundup2(sc->sge.fl_starve_threshold, 8);
2295 fl->buf_boundary = 16;
2297 if (fl_pad && fl->buf_boundary < sc->sge.pad_boundary)
2298 fl->buf_boundary = sc->sge.pad_boundary;
2300 c.iqns_to_fl0congen |=
2301 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
2302 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
2303 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
2304 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
2307 c.iqns_to_fl0congen |=
2308 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
2309 F_FW_IQ_CMD_FL0CONGCIF |
2310 F_FW_IQ_CMD_FL0CONGEN);
2312 c.fl0dcaen_to_fl0cidxfthresh =
2313 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_64B) |
2314 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B));
2315 c.fl0size = htobe16(fl->qsize);
2316 c.fl0addr = htobe64(fl->ba);
2319 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2321 device_printf(sc->dev,
2322 "failed to create ingress queue: %d\n", rc);
2327 iq->gen = F_RSPD_GEN;
2328 iq->intr_next = iq->intr_params;
2329 iq->cntxt_id = be16toh(c.iqid);
2330 iq->abs_id = be16toh(c.physiqid);
2331 iq->flags |= IQ_ALLOCATED;
2333 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
2334 if (cntxt_id >= sc->sge.niq) {
2335 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
2336 cntxt_id, sc->sge.niq - 1);
2338 sc->sge.iqmap[cntxt_id] = iq;
2343 iq->flags |= IQ_HAS_FL;
2344 fl->cntxt_id = be16toh(c.fl0id);
2345 fl->pidx = fl->cidx = 0;
2347 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
2348 if (cntxt_id >= sc->sge.neq) {
2349 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
2350 __func__, cntxt_id, sc->sge.neq - 1);
2352 sc->sge.eqmap[cntxt_id] = (void *)fl;
2355 if (isset(&sc->doorbells, DOORBELL_UDB)) {
2356 uint32_t s_qpp = sc->sge.eq_s_qpp;
2357 uint32_t mask = (1 << s_qpp) - 1;
2358 volatile uint8_t *udb;
2360 udb = sc->udbs_base + UDBS_DB_OFFSET;
2361 udb += (qid >> s_qpp) << PAGE_SHIFT;
2363 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
2364 udb += qid << UDBS_SEG_SHIFT;
2367 fl->udb = (volatile void *)udb;
2369 fl->dbval = F_DBPRIO | V_QID(qid);
2371 fl->dbval |= F_DBTYPE;
2374 /* Enough to make sure the SGE doesn't think it's starved */
2375 refill_fl(sc, fl, fl->lowat);
2379 if (is_t5(sc) && cong >= 0) {
2380 uint32_t param, val;
2382 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2383 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2384 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
2389 for (i = 0; i < 4; i++) {
2390 if (cong & (1 << i))
2391 val |= 1 << (i << 2);
2395 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2397 /* report error but carry on */
2398 device_printf(sc->dev,
2399 "failed to set congestion manager context for "
2400 "ingress queue %d: %d\n", iq->cntxt_id, rc);
2404 /* Enable IQ interrupts */
2405 atomic_store_rel_int(&iq->state, IQS_IDLE);
2406 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) |
2407 V_INGRESSQID(iq->cntxt_id));
2413 free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl)
2416 struct adapter *sc = iq->adapter;
2420 return (0); /* nothing to do */
2422 dev = pi ? pi->dev : sc->dev;
2424 if (iq->flags & IQ_ALLOCATED) {
2425 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
2426 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
2427 fl ? fl->cntxt_id : 0xffff, 0xffff);
2430 "failed to free queue %p: %d\n", iq, rc);
2433 iq->flags &= ~IQ_ALLOCATED;
2436 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
2438 bzero(iq, sizeof(*iq));
2441 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
2445 free_fl_sdesc(sc, fl);
2447 if (mtx_initialized(&fl->fl_lock))
2448 mtx_destroy(&fl->fl_lock);
2450 bzero(fl, sizeof(*fl));
2457 add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
2460 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2462 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2464 children = SYSCTL_CHILDREN(oid);
2466 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2467 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
2468 "SGE context id of the freelist");
2469 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
2470 fl_pad ? 1 : 0, "padding enabled");
2471 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
2472 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
2473 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
2474 0, "consumer index");
2475 if (fl->flags & FL_BUF_PACKING) {
2476 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
2477 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
2479 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
2480 0, "producer index");
2481 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
2482 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
2483 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
2484 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
2485 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
2486 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
2487 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
2488 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
2489 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
2490 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
2494 alloc_fwq(struct adapter *sc)
2497 struct sge_iq *fwq = &sc->sge.fwq;
2498 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2499 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2501 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
2502 fwq->flags |= IQ_INTR; /* always */
2503 intr_idx = sc->intr_count > 1 ? 1 : 0;
2504 rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1);
2506 device_printf(sc->dev,
2507 "failed to create firmware event queue: %d\n", rc);
2511 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
2512 NULL, "firmware event queue");
2513 children = SYSCTL_CHILDREN(oid);
2515 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
2516 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
2517 "absolute id of the queue");
2518 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
2519 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
2520 "SGE context id of the queue");
2521 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
2522 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
2529 free_fwq(struct adapter *sc)
2531 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
2535 alloc_mgmtq(struct adapter *sc)
2538 struct sge_wrq *mgmtq = &sc->sge.mgmtq;
2540 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2541 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2543 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
2544 NULL, "management queue");
2546 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
2547 init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
2548 sc->sge.fwq.cntxt_id, name);
2549 rc = alloc_wrq(sc, NULL, mgmtq, oid);
2551 device_printf(sc->dev,
2552 "failed to create management queue: %d\n", rc);
2560 free_mgmtq(struct adapter *sc)
2563 return free_wrq(sc, &sc->sge.mgmtq);
2567 tnl_cong(struct port_info *pi)
2570 if (cong_drop == -1)
2572 else if (cong_drop == 1)
2575 return (pi->rx_chan_map);
2579 alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx,
2580 struct sysctl_oid *oid)
2583 struct sysctl_oid_list *children;
2586 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, tnl_cong(pi));
2591 * The freelist is just barely above the starvation threshold right now,
2592 * fill it up a bit more.
2595 refill_fl(pi->adapter, &rxq->fl, 128);
2596 FL_UNLOCK(&rxq->fl);
2598 #if defined(INET) || defined(INET6)
2599 rc = tcp_lro_init(&rxq->lro);
2602 rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */
2604 if (pi->ifp->if_capenable & IFCAP_LRO)
2605 rxq->iq.flags |= IQ_LRO_ENABLED;
2609 children = SYSCTL_CHILDREN(oid);
2611 snprintf(name, sizeof(name), "%d", idx);
2612 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2614 children = SYSCTL_CHILDREN(oid);
2616 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id",
2617 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I",
2618 "absolute id of the queue");
2619 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id",
2620 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I",
2621 "SGE context id of the queue");
2622 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
2623 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I",
2625 #if defined(INET) || defined(INET6)
2626 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
2627 &rxq->lro.lro_queued, 0, NULL);
2628 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
2629 &rxq->lro.lro_flushed, 0, NULL);
2631 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
2632 &rxq->rxcsum, "# of times hardware assisted with checksum");
2633 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction",
2634 CTLFLAG_RD, &rxq->vlan_extraction,
2635 "# of times hardware extracted 802.1Q tag");
2637 add_fl_sysctls(&pi->ctx, oid, &rxq->fl);
2643 free_rxq(struct port_info *pi, struct sge_rxq *rxq)
2647 #if defined(INET) || defined(INET6)
2649 tcp_lro_free(&rxq->lro);
2650 rxq->lro.ifp = NULL;
2654 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl);
2656 bzero(rxq, sizeof(*rxq));
2663 alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq,
2664 int intr_idx, int idx, struct sysctl_oid *oid)
2667 struct sysctl_oid_list *children;
2670 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
2675 children = SYSCTL_CHILDREN(oid);
2677 snprintf(name, sizeof(name), "%d", idx);
2678 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2680 children = SYSCTL_CHILDREN(oid);
2682 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id",
2683 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
2684 "I", "absolute id of the queue");
2685 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id",
2686 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16,
2687 "I", "SGE context id of the queue");
2688 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
2689 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
2692 add_fl_sysctls(&pi->ctx, oid, &ofld_rxq->fl);
2698 free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq)
2702 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl);
2704 bzero(ofld_rxq, sizeof(*ofld_rxq));
2712 alloc_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq, int intr_idx,
2713 int idx, struct sysctl_oid *oid)
2716 struct sysctl_oid_list *children;
2717 struct sysctl_ctx_list *ctx;
2720 struct adapter *sc = pi->adapter;
2721 struct netmap_adapter *na = NA(pi->nm_ifp);
2725 len = pi->qsize_rxq * IQ_ESIZE;
2726 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
2727 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
2731 len = na->num_rx_desc * EQ_ESIZE + spg_len;
2732 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
2733 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
2739 nm_rxq->iq_cidx = 0;
2740 nm_rxq->iq_sidx = pi->qsize_rxq - spg_len / IQ_ESIZE;
2741 nm_rxq->iq_gen = F_RSPD_GEN;
2742 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
2743 nm_rxq->fl_sidx = na->num_rx_desc;
2744 nm_rxq->intr_idx = intr_idx;
2747 children = SYSCTL_CHILDREN(oid);
2749 snprintf(name, sizeof(name), "%d", idx);
2750 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
2752 children = SYSCTL_CHILDREN(oid);
2754 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
2755 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
2756 "I", "absolute id of the queue");
2757 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2758 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
2759 "I", "SGE context id of the queue");
2760 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
2761 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
2764 children = SYSCTL_CHILDREN(oid);
2765 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2767 children = SYSCTL_CHILDREN(oid);
2769 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2770 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
2771 "I", "SGE context id of the freelist");
2772 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
2773 &nm_rxq->fl_cidx, 0, "consumer index");
2774 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
2775 &nm_rxq->fl_pidx, 0, "producer index");
2782 free_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq)
2784 struct adapter *sc = pi->adapter;
2786 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
2788 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
2795 alloc_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
2796 struct sysctl_oid *oid)
2800 struct adapter *sc = pi->adapter;
2801 struct netmap_adapter *na = NA(pi->nm_ifp);
2803 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2805 len = na->num_tx_desc * EQ_ESIZE + spg_len;
2806 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
2807 &nm_txq->ba, (void **)&nm_txq->desc);
2811 nm_txq->pidx = nm_txq->cidx = 0;
2812 nm_txq->sidx = na->num_tx_desc;
2814 nm_txq->iqidx = iqidx;
2815 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
2816 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf));
2818 snprintf(name, sizeof(name), "%d", idx);
2819 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2820 NULL, "netmap tx queue");
2821 children = SYSCTL_CHILDREN(oid);
2823 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
2824 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
2825 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
2826 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
2828 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx",
2829 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
2836 free_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq)
2838 struct adapter *sc = pi->adapter;
2840 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
2848 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
2851 struct fw_eq_ctrl_cmd c;
2853 bzero(&c, sizeof(c));
2855 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
2856 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
2857 V_FW_EQ_CTRL_CMD_VFN(0));
2858 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
2859 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
2860 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid)); /* XXX */
2861 c.physeqid_pkd = htobe32(0);
2862 c.fetchszm_to_iqid =
2863 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
2864 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
2865 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
2867 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
2868 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
2869 V_FW_EQ_CTRL_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
2870 V_FW_EQ_CTRL_CMD_EQSIZE(eq->qsize));
2871 c.eqaddr = htobe64(eq->ba);
2873 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2875 device_printf(sc->dev,
2876 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
2879 eq->flags |= EQ_ALLOCATED;
2881 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
2882 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
2883 if (cntxt_id >= sc->sge.neq)
2884 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
2885 cntxt_id, sc->sge.neq - 1);
2886 sc->sge.eqmap[cntxt_id] = eq;
2892 eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
2895 struct fw_eq_eth_cmd c;
2897 bzero(&c, sizeof(c));
2899 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
2900 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
2901 V_FW_EQ_ETH_CMD_VFN(0));
2902 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
2903 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
2904 c.autoequiqe_to_viid = htobe32(V_FW_EQ_ETH_CMD_VIID(pi->viid));
2905 c.fetchszm_to_iqid =
2906 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
2907 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
2908 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
2909 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
2910 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
2911 V_FW_EQ_ETH_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
2912 V_FW_EQ_ETH_CMD_EQSIZE(eq->qsize));
2913 c.eqaddr = htobe64(eq->ba);
2915 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2917 device_printf(pi->dev,
2918 "failed to create Ethernet egress queue: %d\n", rc);
2921 eq->flags |= EQ_ALLOCATED;
2923 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
2924 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
2925 if (cntxt_id >= sc->sge.neq)
2926 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
2927 cntxt_id, sc->sge.neq - 1);
2928 sc->sge.eqmap[cntxt_id] = eq;
2935 ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
2938 struct fw_eq_ofld_cmd c;
2940 bzero(&c, sizeof(c));
2942 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
2943 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
2944 V_FW_EQ_OFLD_CMD_VFN(0));
2945 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
2946 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
2947 c.fetchszm_to_iqid =
2948 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_STATUS_PAGE) |
2949 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
2950 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
2952 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
2953 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
2954 V_FW_EQ_OFLD_CMD_CIDXFTHRESH(X_CIDXFLUSHTHRESH_32) |
2955 V_FW_EQ_OFLD_CMD_EQSIZE(eq->qsize));
2956 c.eqaddr = htobe64(eq->ba);
2958 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2960 device_printf(pi->dev,
2961 "failed to create egress queue for TCP offload: %d\n", rc);
2964 eq->flags |= EQ_ALLOCATED;
2966 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
2967 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
2968 if (cntxt_id >= sc->sge.neq)
2969 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
2970 cntxt_id, sc->sge.neq - 1);
2971 sc->sge.eqmap[cntxt_id] = eq;
2978 alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
2983 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
2985 len = eq->qsize * EQ_ESIZE;
2986 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
2987 &eq->ba, (void **)&eq->desc);
2991 eq->cap = eq->qsize - spg_len / EQ_ESIZE;
2992 eq->spg = (void *)&eq->desc[eq->cap];
2993 eq->avail = eq->cap - 1; /* one less to avoid cidx = pidx */
2994 eq->pidx = eq->cidx = 0;
2995 eq->doorbells = sc->doorbells;
2997 switch (eq->flags & EQ_TYPEMASK) {
2999 rc = ctrl_eq_alloc(sc, eq);
3003 rc = eth_eq_alloc(sc, pi, eq);
3008 rc = ofld_eq_alloc(sc, pi, eq);
3013 panic("%s: invalid eq type %d.", __func__,
3014 eq->flags & EQ_TYPEMASK);
3017 device_printf(sc->dev,
3018 "failed to allocate egress queue(%d): %d\n",
3019 eq->flags & EQ_TYPEMASK, rc);
3022 eq->tx_callout.c_cpu = eq->cntxt_id % mp_ncpus;
3024 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3025 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3026 isset(&eq->doorbells, DOORBELL_WCWR)) {
3027 uint32_t s_qpp = sc->sge.eq_s_qpp;
3028 uint32_t mask = (1 << s_qpp) - 1;
3029 volatile uint8_t *udb;
3031 udb = sc->udbs_base + UDBS_DB_OFFSET;
3032 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3033 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3034 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3035 clrbit(&eq->doorbells, DOORBELL_WCWR);
3037 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3040 eq->udb = (volatile void *)udb;
3047 free_eq(struct adapter *sc, struct sge_eq *eq)
3051 if (eq->flags & EQ_ALLOCATED) {
3052 switch (eq->flags & EQ_TYPEMASK) {
3054 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3059 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3065 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3071 panic("%s: invalid eq type %d.", __func__,
3072 eq->flags & EQ_TYPEMASK);
3075 device_printf(sc->dev,
3076 "failed to free egress queue (%d): %d\n",
3077 eq->flags & EQ_TYPEMASK, rc);
3080 eq->flags &= ~EQ_ALLOCATED;
3083 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3085 if (mtx_initialized(&eq->eq_lock))
3086 mtx_destroy(&eq->eq_lock);
3088 bzero(eq, sizeof(*eq));
3093 alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq,
3094 struct sysctl_oid *oid)
3097 struct sysctl_ctx_list *ctx = pi ? &pi->ctx : &sc->ctx;
3098 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3100 rc = alloc_eq(sc, pi, &wrq->eq);
3105 STAILQ_INIT(&wrq->wr_list);
3107 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3108 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3109 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3110 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3112 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3113 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3115 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs", CTLFLAG_RD,
3116 &wrq->tx_wrs, "# of work requests");
3117 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD,
3119 "# of times queue ran out of hardware descriptors");
3120 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD,
3121 &wrq->eq.unstalled, 0, "# of times queue recovered after stall");
3127 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
3131 rc = free_eq(sc, &wrq->eq);
3135 bzero(wrq, sizeof(*wrq));
3140 alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx,
3141 struct sysctl_oid *oid)
3144 struct adapter *sc = pi->adapter;
3145 struct sge_eq *eq = &txq->eq;
3147 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3149 rc = alloc_eq(sc, pi, eq);
3155 txq->sdesc = malloc(eq->cap * sizeof(struct tx_sdesc), M_CXGBE,
3157 txq->br = buf_ring_alloc(eq->qsize, M_CXGBE, M_WAITOK, &eq->eq_lock);
3159 rc = bus_dma_tag_create(sc->dmat, 1, 0, BUS_SPACE_MAXADDR,
3160 BUS_SPACE_MAXADDR, NULL, NULL, 64 * 1024, TX_SGL_SEGS,
3161 BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL, NULL, &txq->tx_tag);
3163 device_printf(sc->dev,
3164 "failed to create tx DMA tag: %d\n", rc);
3169 * We can stuff ~10 frames in an 8-descriptor txpkts WR (8 is the SGE
3170 * limit for any WR). txq->no_dmamap events shouldn't occur if maps is
3171 * sized for the worst case.
3173 rc = t4_alloc_tx_maps(&txq->txmaps, txq->tx_tag, eq->qsize * 10 / 8,
3176 device_printf(sc->dev, "failed to setup tx DMA maps: %d\n", rc);
3180 snprintf(name, sizeof(name), "%d", idx);
3181 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3183 children = SYSCTL_CHILDREN(oid);
3185 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3186 &eq->cntxt_id, 0, "SGE context id of the queue");
3187 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
3188 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3190 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx",
3191 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
3194 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
3195 &txq->txcsum, "# of times hardware assisted with checksum");
3196 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion",
3197 CTLFLAG_RD, &txq->vlan_insertion,
3198 "# of times hardware inserted 802.1Q tag");
3199 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
3200 &txq->tso_wrs, "# of TSO work requests");
3201 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
3202 &txq->imm_wrs, "# of work requests with immediate data");
3203 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
3204 &txq->sgl_wrs, "# of work requests with direct SGL");
3205 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
3206 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
3207 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_wrs", CTLFLAG_RD,
3208 &txq->txpkts_wrs, "# of txpkts work requests (multiple pkts/WR)");
3209 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts_pkts", CTLFLAG_RD,
3210 &txq->txpkts_pkts, "# of frames tx'd using txpkts work requests");
3212 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "br_drops", CTLFLAG_RD,
3213 &txq->br->br_drops, "# of drops in the buf_ring for this queue");
3214 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_dmamap", CTLFLAG_RD,
3215 &txq->no_dmamap, 0, "# of times txq ran out of DMA maps");
3216 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "no_desc", CTLFLAG_RD,
3217 &txq->no_desc, 0, "# of times txq ran out of hardware descriptors");
3218 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "egr_update", CTLFLAG_RD,
3219 &eq->egr_update, 0, "egress update notifications from the SGE");
3220 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "unstalled", CTLFLAG_RD,
3221 &eq->unstalled, 0, "# of times txq recovered after stall");
3227 free_txq(struct port_info *pi, struct sge_txq *txq)
3230 struct adapter *sc = pi->adapter;
3231 struct sge_eq *eq = &txq->eq;
3233 rc = free_eq(sc, eq);
3237 free(txq->sdesc, M_CXGBE);
3239 if (txq->txmaps.maps)
3240 t4_free_tx_maps(&txq->txmaps, txq->tx_tag);
3242 buf_ring_free(txq->br, M_CXGBE);
3245 bus_dma_tag_destroy(txq->tx_tag);
3247 bzero(txq, sizeof(*txq));
3252 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3254 bus_addr_t *ba = arg;
3257 ("%s meant for single segment mappings only.", __func__));
3259 *ba = error ? 0 : segs->ds_addr;
3263 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
3267 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
3271 v = fl->dbval | V_PIDX(n);
3273 *fl->udb = htole32(v);
3275 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v);
3276 IDXINCR(fl->dbidx, n, fl->sidx);
3280 * Fills up the freelist by allocating upto 'n' buffers. Buffers that are
3281 * recycled do not count towards this allocation budget.
3283 * Returns non-zero to indicate that this freelist should be added to the list
3284 * of starving freelists.
3287 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
3290 struct fl_sdesc *sd;
3293 struct cluster_layout *cll;
3294 struct sw_zone_info *swz;
3295 struct cluster_metadata *clm;
3297 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
3299 FL_LOCK_ASSERT_OWNED(fl);
3302 * We always stop at the begining of the hardware descriptor that's just
3303 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
3304 * which would mean an empty freelist to the chip.
3306 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
3307 if (fl->pidx == max_pidx * 8)
3310 d = &fl->desc[fl->pidx];
3311 sd = &fl->sdesc[fl->pidx];
3312 cll = &fl->cll_def; /* default layout */
3313 swz = &sc->sge.sw_zone_info[cll->zidx];
3317 if (sd->cl != NULL) {
3319 if (sd->nmbuf == 0) {
3321 * Fast recycle without involving any atomics on
3322 * the cluster's metadata (if the cluster has
3323 * metadata). This happens when all frames
3324 * received in the cluster were small enough to
3325 * fit within a single mbuf each.
3327 fl->cl_fast_recycled++;
3329 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3331 MPASS(clm->refcount == 1);
3337 * Cluster is guaranteed to have metadata. Clusters
3338 * without metadata always take the fast recycle path
3339 * when they're recycled.
3341 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3344 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3346 counter_u64_add(extfree_rels, 1);
3349 sd->cl = NULL; /* gave up my reference */
3351 MPASS(sd->cl == NULL);
3353 cl = uma_zalloc(swz->zone, M_NOWAIT);
3354 if (__predict_false(cl == NULL)) {
3355 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
3356 fl->cll_def.zidx == fl->cll_alt.zidx)
3359 /* fall back to the safe zone */
3361 swz = &sc->sge.sw_zone_info[cll->zidx];
3367 pa = pmap_kextract((vm_offset_t)cl);
3371 *d = htobe64(pa | cll->hwidx);
3372 clm = cl_metadata(sc, fl, cll, cl);
3384 if (__predict_false(++fl->pidx % 8 == 0)) {
3385 uint16_t pidx = fl->pidx / 8;
3387 if (__predict_false(pidx == fl->sidx)) {
3393 if (pidx == max_pidx)
3396 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
3401 if (fl->pidx / 8 != fl->dbidx)
3404 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
3408 * Attempt to refill all starving freelists.
3411 refill_sfl(void *arg)
3413 struct adapter *sc = arg;
3414 struct sge_fl *fl, *fl_temp;
3416 mtx_lock(&sc->sfl_lock);
3417 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
3419 refill_fl(sc, fl, 64);
3420 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
3421 TAILQ_REMOVE(&sc->sfl, fl, link);
3422 fl->flags &= ~FL_STARVING;
3427 if (!TAILQ_EMPTY(&sc->sfl))
3428 callout_schedule(&sc->sfl_callout, hz / 5);
3429 mtx_unlock(&sc->sfl_lock);
3433 alloc_fl_sdesc(struct sge_fl *fl)
3436 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
3443 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
3445 struct fl_sdesc *sd;
3446 struct cluster_metadata *clm;
3447 struct cluster_layout *cll;
3451 for (i = 0; i < fl->sidx * 8; i++, sd++) {
3456 clm = cl_metadata(sc, fl, cll, sd->cl);
3458 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3459 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3460 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3461 counter_u64_add(extfree_rels, 1);
3466 free(fl->sdesc, M_CXGBE);
3471 t4_alloc_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag, int count,
3477 txmaps->map_total = txmaps->map_avail = count;
3478 txmaps->map_cidx = txmaps->map_pidx = 0;
3480 txmaps->maps = malloc(count * sizeof(struct tx_map), M_CXGBE,
3484 for (i = 0; i < count; i++, txm++) {
3485 rc = bus_dmamap_create(tx_tag, 0, &txm->map);
3494 bus_dmamap_destroy(tx_tag, txm->map);
3496 KASSERT(txm == txmaps->maps, ("%s: EDOOFUS", __func__));
3498 free(txmaps->maps, M_CXGBE);
3499 txmaps->maps = NULL;
3505 t4_free_tx_maps(struct tx_maps *txmaps, bus_dma_tag_t tx_tag)
3511 for (i = 0; i < txmaps->map_total; i++, txm++) {
3514 bus_dmamap_unload(tx_tag, txm->map);
3519 bus_dmamap_destroy(tx_tag, txm->map);
3522 free(txmaps->maps, M_CXGBE);
3523 txmaps->maps = NULL;
3527 * We'll do immediate data tx for non-TSO, but only when not coalescing. We're
3528 * willing to use upto 2 hardware descriptors which means a maximum of 96 bytes
3529 * of immediate data.
3533 - sizeof(struct fw_eth_tx_pkt_wr) \
3534 - sizeof(struct cpl_tx_pkt_core))
3537 * Returns non-zero on failure, no need to cleanup anything in that case.
3539 * Note 1: We always try to defrag the mbuf if required and return EFBIG only
3540 * if the resulting chain still won't fit in a tx descriptor.
3542 * Note 2: We'll pullup the mbuf chain if TSO is requested and the first mbuf
3543 * does not have the TCP header in it.
3546 get_pkt_sgl(struct sge_txq *txq, struct mbuf **fp, struct sgl *sgl,
3549 struct mbuf *m = *fp;
3550 struct tx_maps *txmaps;
3552 int rc, defragged = 0, n;
3554 TXQ_LOCK_ASSERT_OWNED(txq);
3556 if (m->m_pkthdr.tso_segsz)
3557 sgl_only = 1; /* Do not allow immediate data with LSO */
3559 start: sgl->nsegs = 0;
3561 if (m->m_pkthdr.len <= IMM_LEN && !sgl_only)
3562 return (0); /* nsegs = 0 tells caller to use imm. tx */
3564 txmaps = &txq->txmaps;
3565 if (txmaps->map_avail == 0) {
3569 txm = &txmaps->maps[txmaps->map_pidx];
3571 if (m->m_pkthdr.tso_segsz && m->m_len < 50) {
3572 *fp = m_pullup(m, 50);
3578 rc = bus_dmamap_load_mbuf_sg(txq->tx_tag, txm->map, m, sgl->seg,
3579 &sgl->nsegs, BUS_DMA_NOWAIT);
3580 if (rc == EFBIG && defragged == 0) {
3581 m = m_defrag(m, M_NOWAIT);
3593 txmaps->map_avail--;
3594 if (++txmaps->map_pidx == txmaps->map_total)
3595 txmaps->map_pidx = 0;
3597 KASSERT(sgl->nsegs > 0 && sgl->nsegs <= TX_SGL_SEGS,
3598 ("%s: bad DMA mapping (%d segments)", __func__, sgl->nsegs));
3601 * Store the # of flits required to hold this frame's SGL in nflits. An
3602 * SGL has a (ULPTX header + len0, addr0) tuple optionally followed by
3603 * multiple (len0 + len1, addr0, addr1) tuples. If addr1 is not used
3604 * then len1 must be set to 0.
3607 sgl->nflits = (3 * n) / 2 + (n & 1) + 2;
3614 * Releases all the txq resources used up in the specified sgl.
3617 free_pkt_sgl(struct sge_txq *txq, struct sgl *sgl)
3619 struct tx_maps *txmaps;
3622 TXQ_LOCK_ASSERT_OWNED(txq);
3624 if (sgl->nsegs == 0)
3625 return (0); /* didn't use any map */
3627 txmaps = &txq->txmaps;
3629 /* 1 pkt uses exactly 1 map, back it out */
3631 txmaps->map_avail++;
3632 if (txmaps->map_pidx > 0)
3635 txmaps->map_pidx = txmaps->map_total - 1;
3637 txm = &txmaps->maps[txmaps->map_pidx];
3638 bus_dmamap_unload(txq->tx_tag, txm->map);
3645 write_txpkt_wr(struct port_info *pi, struct sge_txq *txq, struct mbuf *m,
3648 struct sge_eq *eq = &txq->eq;
3649 struct fw_eth_tx_pkt_wr *wr;
3650 struct cpl_tx_pkt_core *cpl;
3651 uint32_t ctrl; /* used in many unrelated places */
3653 int nflits, ndesc, pktlen;
3654 struct tx_sdesc *txsd;
3657 TXQ_LOCK_ASSERT_OWNED(txq);
3659 pktlen = m->m_pkthdr.len;
3662 * Do we have enough flits to send this frame out?
3664 ctrl = sizeof(struct cpl_tx_pkt_core);
3665 if (m->m_pkthdr.tso_segsz) {
3666 nflits = TXPKT_LSO_WR_HDR;
3667 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
3669 nflits = TXPKT_WR_HDR;
3671 nflits += sgl->nflits;
3673 nflits += howmany(pktlen, 8);
3676 ndesc = howmany(nflits, 8);
3677 if (ndesc > eq->avail)
3680 /* Firmware work request header */
3681 wr = (void *)&eq->desc[eq->pidx];
3682 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
3683 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
3684 ctrl = V_FW_WR_LEN16(howmany(nflits, 2));
3685 if (eq->avail == ndesc) {
3686 if (!(eq->flags & EQ_CRFLUSHED)) {
3687 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ;
3688 eq->flags |= EQ_CRFLUSHED;
3690 eq->flags |= EQ_STALLED;
3693 wr->equiq_to_len16 = htobe32(ctrl);
3696 if (m->m_pkthdr.tso_segsz) {
3697 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
3698 struct ether_header *eh;
3700 #if defined(INET) || defined(INET6)
3705 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
3708 eh = mtod(m, struct ether_header *);
3709 eh_type = ntohs(eh->ether_type);
3710 if (eh_type == ETHERTYPE_VLAN) {
3711 struct ether_vlan_header *evh = (void *)eh;
3713 ctrl |= V_LSO_ETHHDR_LEN(1);
3715 eh_type = ntohs(evh->evl_proto);
3721 case ETHERTYPE_IPV6:
3723 struct ip6_hdr *ip6 = l3hdr;
3726 * XXX-BZ For now we do not pretend to support
3727 * IPv6 extension headers.
3729 KASSERT(ip6->ip6_nxt == IPPROTO_TCP, ("%s: CSUM_TSO "
3730 "with ip6_nxt != TCP: %u", __func__, ip6->ip6_nxt));
3731 tcp = (struct tcphdr *)(ip6 + 1);
3733 ctrl |= V_LSO_IPHDR_LEN(sizeof(*ip6) >> 2) |
3734 V_LSO_TCPHDR_LEN(tcp->th_off);
3741 struct ip *ip = l3hdr;
3743 tcp = (void *)((uintptr_t)ip + ip->ip_hl * 4);
3744 ctrl |= V_LSO_IPHDR_LEN(ip->ip_hl) |
3745 V_LSO_TCPHDR_LEN(tcp->th_off);
3750 panic("%s: CSUM_TSO but no supported IP version "
3751 "(0x%04x)", __func__, eh_type);
3754 lso->lso_ctrl = htobe32(ctrl);
3755 lso->ipid_ofst = htobe16(0);
3756 lso->mss = htobe16(m->m_pkthdr.tso_segsz);
3757 lso->seqno_offset = htobe32(0);
3758 lso->len = htobe32(pktlen);
3760 cpl = (void *)(lso + 1);
3764 cpl = (void *)(wr + 1);
3766 /* Checksum offload */
3768 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)))
3769 ctrl1 |= F_TXPKT_IPCSUM_DIS;
3770 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
3771 CSUM_TCP_IPV6 | CSUM_TSO)))
3772 ctrl1 |= F_TXPKT_L4CSUM_DIS;
3773 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
3774 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
3775 txq->txcsum++; /* some hardware assistance provided */
3777 /* VLAN tag insertion */
3778 if (m->m_flags & M_VLANTAG) {
3779 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
3780 txq->vlan_insertion++;
3784 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3785 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf));
3787 cpl->len = htobe16(pktlen);
3788 cpl->ctrl1 = htobe64(ctrl1);
3790 /* Software descriptor */
3791 txsd = &txq->sdesc[eq->pidx];
3792 txsd->desc_used = ndesc;
3794 eq->pending += ndesc;
3797 if (eq->pidx >= eq->cap)
3798 eq->pidx -= eq->cap;
3801 dst = (void *)(cpl + 1);
3802 if (sgl->nsegs > 0) {
3805 write_sgl_to_txd(eq, sgl, &dst);
3809 for (; m; m = m->m_next) {
3810 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
3816 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
3826 * Returns 0 to indicate that m has been accepted into a coalesced tx work
3827 * request. It has either been folded into txpkts or txpkts was flushed and m
3828 * has started a new coalesced work request (as the first frame in a fresh
3831 * Returns non-zero to indicate a failure - caller is responsible for
3832 * transmitting m, if there was anything in txpkts it has been flushed.
3835 add_to_txpkts(struct port_info *pi, struct sge_txq *txq, struct txpkts *txpkts,
3836 struct mbuf *m, struct sgl *sgl)
3838 struct sge_eq *eq = &txq->eq;
3840 struct tx_sdesc *txsd;
3843 TXQ_LOCK_ASSERT_OWNED(txq);
3845 KASSERT(sgl->nsegs, ("%s: can't coalesce imm data", __func__));
3847 if (txpkts->npkt > 0) {
3848 flits = TXPKTS_PKT_HDR + sgl->nflits;
3849 can_coalesce = m->m_pkthdr.tso_segsz == 0 &&
3850 txpkts->nflits + flits <= TX_WR_FLITS &&
3851 txpkts->nflits + flits <= eq->avail * 8 &&
3852 txpkts->plen + m->m_pkthdr.len < 65536;
3856 txpkts->nflits += flits;
3857 txpkts->plen += m->m_pkthdr.len;
3859 txsd = &txq->sdesc[eq->pidx];
3866 * Couldn't coalesce m into txpkts. The first order of business
3867 * is to send txpkts on its way. Then we'll revisit m.
3869 write_txpkts_wr(txq, txpkts);
3873 * Check if we can start a new coalesced tx work request with m as
3874 * the first packet in it.
3877 KASSERT(txpkts->npkt == 0, ("%s: txpkts not empty", __func__));
3879 flits = TXPKTS_WR_HDR + sgl->nflits;
3880 can_coalesce = m->m_pkthdr.tso_segsz == 0 &&
3881 flits <= eq->avail * 8 && flits <= TX_WR_FLITS;
3883 if (can_coalesce == 0)
3887 * Start a fresh coalesced tx WR with m as the first frame in it.
3890 txpkts->nflits = flits;
3891 txpkts->flitp = &eq->desc[eq->pidx].flit[2];
3892 txpkts->plen = m->m_pkthdr.len;
3894 txsd = &txq->sdesc[eq->pidx];
3901 * Note that write_txpkts_wr can never run out of hardware descriptors (but
3902 * write_txpkt_wr can). add_to_txpkts ensures that a frame is accepted for
3903 * coalescing only if sufficient hardware descriptors are available.
3906 write_txpkts_wr(struct sge_txq *txq, struct txpkts *txpkts)
3908 struct sge_eq *eq = &txq->eq;
3909 struct fw_eth_tx_pkts_wr *wr;
3910 struct tx_sdesc *txsd;
3914 TXQ_LOCK_ASSERT_OWNED(txq);
3916 ndesc = howmany(txpkts->nflits, 8);
3918 wr = (void *)&eq->desc[eq->pidx];
3919 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
3920 ctrl = V_FW_WR_LEN16(howmany(txpkts->nflits, 2));
3921 if (eq->avail == ndesc) {
3922 if (!(eq->flags & EQ_CRFLUSHED)) {
3923 ctrl |= F_FW_WR_EQUEQ | F_FW_WR_EQUIQ;
3924 eq->flags |= EQ_CRFLUSHED;
3926 eq->flags |= EQ_STALLED;
3928 wr->equiq_to_len16 = htobe32(ctrl);
3929 wr->plen = htobe16(txpkts->plen);
3930 wr->npkt = txpkts->npkt;
3931 wr->r3 = wr->type = 0;
3933 /* Everything else already written */
3935 txsd = &txq->sdesc[eq->pidx];
3936 txsd->desc_used = ndesc;
3938 KASSERT(eq->avail >= ndesc, ("%s: out of descriptors", __func__));
3940 eq->pending += ndesc;
3943 if (eq->pidx >= eq->cap)
3944 eq->pidx -= eq->cap;
3946 txq->txpkts_pkts += txpkts->npkt;
3948 txpkts->npkt = 0; /* emptied */
3952 write_ulp_cpl_sgl(struct port_info *pi, struct sge_txq *txq,
3953 struct txpkts *txpkts, struct mbuf *m, struct sgl *sgl)
3955 struct ulp_txpkt *ulpmc;
3956 struct ulptx_idata *ulpsc;
3957 struct cpl_tx_pkt_core *cpl;
3958 struct sge_eq *eq = &txq->eq;
3959 uintptr_t flitp, start, end;
3963 KASSERT(txpkts->npkt > 0, ("%s: txpkts is empty", __func__));
3965 start = (uintptr_t)eq->desc;
3966 end = (uintptr_t)eq->spg;
3968 /* Checksum offload */
3970 if (!(m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO)))
3971 ctrl |= F_TXPKT_IPCSUM_DIS;
3972 if (!(m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
3973 CSUM_TCP_IPV6 | CSUM_TSO)))
3974 ctrl |= F_TXPKT_L4CSUM_DIS;
3975 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
3976 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
3977 txq->txcsum++; /* some hardware assistance provided */
3979 /* VLAN tag insertion */
3980 if (m->m_flags & M_VLANTAG) {
3981 ctrl |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
3982 txq->vlan_insertion++;
3986 * The previous packet's SGL must have ended at a 16 byte boundary (this
3987 * is required by the firmware/hardware). It follows that flitp cannot
3988 * wrap around between the ULPTX master command and ULPTX subcommand (8
3989 * bytes each), and that it can not wrap around in the middle of the
3990 * cpl_tx_pkt_core either.
3992 flitp = (uintptr_t)txpkts->flitp;
3993 KASSERT((flitp & 0xf) == 0,
3994 ("%s: last SGL did not end at 16 byte boundary: %p",
3995 __func__, txpkts->flitp));
3997 /* ULP master command */
3998 ulpmc = (void *)flitp;
3999 ulpmc->cmd_dest = htonl(V_ULPTX_CMD(ULP_TX_PKT) | V_ULP_TXPKT_DEST(0) |
4000 V_ULP_TXPKT_FID(eq->iqid));
4001 ulpmc->len = htonl(howmany(sizeof(*ulpmc) + sizeof(*ulpsc) +
4002 sizeof(*cpl) + 8 * sgl->nflits, 16));
4004 /* ULP subcommand */
4005 ulpsc = (void *)(ulpmc + 1);
4006 ulpsc->cmd_more = htobe32(V_ULPTX_CMD((u32)ULP_TX_SC_IMM) |
4008 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
4010 flitp += sizeof(*ulpmc) + sizeof(*ulpsc);
4015 cpl = (void *)flitp;
4016 cpl->ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
4017 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(pi->adapter->pf));
4019 cpl->len = htobe16(m->m_pkthdr.len);
4020 cpl->ctrl1 = htobe64(ctrl);
4022 flitp += sizeof(*cpl);
4026 /* SGL for this frame */
4027 dst = (caddr_t)flitp;
4028 txpkts->nflits += write_sgl_to_txd(eq, sgl, &dst);
4029 txpkts->flitp = (void *)dst;
4031 KASSERT(((uintptr_t)dst & 0xf) == 0,
4032 ("%s: SGL ends at %p (not a 16 byte boundary)", __func__, dst));
4036 * If the SGL ends on an address that is not 16 byte aligned, this function will
4037 * add a 0 filled flit at the end. It returns 1 in that case.
4040 write_sgl_to_txd(struct sge_eq *eq, struct sgl *sgl, caddr_t *to)
4042 __be64 *flitp, *end;
4043 struct ulptx_sgl *usgl;
4044 bus_dma_segment_t *seg;
4047 KASSERT(sgl->nsegs > 0 && sgl->nflits > 0,
4048 ("%s: bad SGL - nsegs=%d, nflits=%d",
4049 __func__, sgl->nsegs, sgl->nflits));
4051 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
4052 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
4054 flitp = (__be64 *)(*to);
4055 end = flitp + sgl->nflits;
4057 usgl = (void *)flitp;
4060 * We start at a 16 byte boundary somewhere inside the tx descriptor
4061 * ring, so we're at least 16 bytes away from the status page. There is
4062 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
4065 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
4066 V_ULPTX_NSGE(sgl->nsegs));
4067 usgl->len0 = htobe32(seg->ds_len);
4068 usgl->addr0 = htobe64(seg->ds_addr);
4071 if ((uintptr_t)end <= (uintptr_t)eq->spg) {
4073 /* Won't wrap around at all */
4075 for (i = 0; i < sgl->nsegs - 1; i++, seg++) {
4076 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ds_len);
4077 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ds_addr);
4080 usgl->sge[i / 2].len[1] = htobe32(0);
4083 /* Will wrap somewhere in the rest of the SGL */
4085 /* 2 flits already written, write the rest flit by flit */
4086 flitp = (void *)(usgl + 1);
4087 for (i = 0; i < sgl->nflits - 2; i++) {
4088 if ((uintptr_t)flitp == (uintptr_t)eq->spg)
4089 flitp = (void *)eq->desc;
4090 *flitp++ = get_flit(seg, sgl->nsegs - 1, i);
4095 if ((uintptr_t)end & 0xf) {
4096 *(uint64_t *)end = 0;
4102 if ((uintptr_t)end == (uintptr_t)eq->spg)
4103 *to = (void *)eq->desc;
4111 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
4113 if (__predict_true((uintptr_t)(*to) + len <= (uintptr_t)eq->spg)) {
4114 bcopy(from, *to, len);
4117 int portion = (uintptr_t)eq->spg - (uintptr_t)(*to);
4119 bcopy(from, *to, portion);
4121 portion = len - portion; /* remaining */
4122 bcopy(from, (void *)eq->desc, portion);
4123 (*to) = (caddr_t)eq->desc + portion;
4128 ring_eq_db(struct adapter *sc, struct sge_eq *eq)
4133 pending = eq->pending;
4135 clrbit(&db, DOORBELL_WCWR);
4139 switch (ffs(db) - 1) {
4141 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending));
4144 case DOORBELL_WCWR: {
4145 volatile uint64_t *dst, *src;
4149 * Queues whose 128B doorbell segment fits in the page do not
4150 * use relative qid (udb_qid is always 0). Only queues with
4151 * doorbell segments can do WCWR.
4153 KASSERT(eq->udb_qid == 0 && pending == 1,
4154 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
4155 __func__, eq->doorbells, pending, eq->pidx, eq));
4157 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
4159 i = eq->pidx ? eq->pidx - 1 : eq->cap - 1;
4160 src = (void *)&eq->desc[i];
4161 while (src != (void *)&eq->desc[i + 1])
4167 case DOORBELL_UDBWC:
4168 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(pending));
4173 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
4174 V_QID(eq->cntxt_id) | V_PIDX(pending));
4180 reclaimable(struct sge_eq *eq)
4184 cidx = eq->spg->cidx; /* stable snapshot */
4185 cidx = be16toh(cidx);
4187 if (cidx >= eq->cidx)
4188 return (cidx - eq->cidx);
4190 return (cidx + eq->cap - eq->cidx);
4194 * There are "can_reclaim" tx descriptors ready to be reclaimed. Reclaim as
4195 * many as possible but stop when there are around "n" mbufs to free.
4197 * The actual number reclaimed is provided as the return value.
4200 reclaim_tx_descs(struct sge_txq *txq, int can_reclaim, int n)
4202 struct tx_sdesc *txsd;
4203 struct tx_maps *txmaps;
4205 unsigned int reclaimed, maps;
4206 struct sge_eq *eq = &txq->eq;
4208 TXQ_LOCK_ASSERT_OWNED(txq);
4210 if (can_reclaim == 0)
4211 can_reclaim = reclaimable(eq);
4213 maps = reclaimed = 0;
4214 while (can_reclaim && maps < n) {
4217 txsd = &txq->sdesc[eq->cidx];
4218 ndesc = txsd->desc_used;
4220 /* Firmware doesn't return "partial" credits. */
4221 KASSERT(can_reclaim >= ndesc,
4222 ("%s: unexpected number of credits: %d, %d",
4223 __func__, can_reclaim, ndesc));
4225 maps += txsd->credits;
4228 can_reclaim -= ndesc;
4231 if (__predict_false(eq->cidx >= eq->cap))
4232 eq->cidx -= eq->cap;
4235 txmaps = &txq->txmaps;
4236 txm = &txmaps->maps[txmaps->map_cidx];
4240 eq->avail += reclaimed;
4241 KASSERT(eq->avail < eq->cap, /* avail tops out at (cap - 1) */
4242 ("%s: too many descriptors available", __func__));
4244 txmaps->map_avail += maps;
4245 KASSERT(txmaps->map_avail <= txmaps->map_total,
4246 ("%s: too many maps available", __func__));
4249 struct tx_map *next;
4252 if (__predict_false(txmaps->map_cidx + 1 == txmaps->map_total))
4253 next = txmaps->maps;
4256 bus_dmamap_unload(txq->tx_tag, txm->map);
4261 if (__predict_false(++txmaps->map_cidx == txmaps->map_total))
4262 txmaps->map_cidx = 0;
4269 write_eqflush_wr(struct sge_eq *eq)
4271 struct fw_eq_flush_wr *wr;
4273 EQ_LOCK_ASSERT_OWNED(eq);
4274 KASSERT(eq->avail > 0, ("%s: no descriptors left.", __func__));
4275 KASSERT(!(eq->flags & EQ_CRFLUSHED), ("%s: flushed already", __func__));
4277 wr = (void *)&eq->desc[eq->pidx];
4278 bzero(wr, sizeof(*wr));
4279 wr->opcode = FW_EQ_FLUSH_WR;
4280 wr->equiq_to_len16 = htobe32(V_FW_WR_LEN16(sizeof(*wr) / 16) |
4281 F_FW_WR_EQUEQ | F_FW_WR_EQUIQ);
4283 eq->flags |= (EQ_CRFLUSHED | EQ_STALLED);
4286 if (++eq->pidx == eq->cap)
4291 get_flit(bus_dma_segment_t *sgl, int nsegs, int idx)
4293 int i = (idx / 3) * 2;
4299 rc = htobe32(sgl[i].ds_len);
4301 rc |= (uint64_t)htobe32(sgl[i + 1].ds_len) << 32;
4306 return htobe64(sgl[i].ds_addr);
4308 return htobe64(sgl[i + 1].ds_addr);
4315 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
4317 int8_t zidx, hwidx, idx;
4318 uint16_t region1, region3;
4319 int spare, spare_needed, n;
4320 struct sw_zone_info *swz;
4321 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
4324 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
4325 * large enough for the max payload and cluster metadata. Otherwise
4326 * settle for the largest bufsize that leaves enough room in the cluster
4329 * Without buffer packing: Look for the smallest zone which has a
4330 * bufsize large enough for the max payload. Settle for the largest
4331 * bufsize available if there's nothing big enough for max payload.
4333 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
4334 swz = &sc->sge.sw_zone_info[0];
4336 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
4337 if (swz->size > largest_rx_cluster) {
4338 if (__predict_true(hwidx != -1))
4342 * This is a misconfiguration. largest_rx_cluster is
4343 * preventing us from finding a refill source. See
4344 * dev.t5nex.<n>.buffer_sizes to figure out why.
4346 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
4347 " refill source for fl %p (dma %u). Ignored.\n",
4348 largest_rx_cluster, fl, maxp);
4350 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
4351 hwb = &hwb_list[idx];
4352 spare = swz->size - hwb->size;
4353 if (spare < spare_needed)
4356 hwidx = idx; /* best option so far */
4357 if (hwb->size >= maxp) {
4359 if ((fl->flags & FL_BUF_PACKING) == 0)
4360 goto done; /* stop looking (not packing) */
4362 if (swz->size >= safest_rx_cluster)
4363 goto done; /* stop looking (packing) */
4365 break; /* keep looking, next zone */
4369 /* A usable hwidx has been located. */
4371 hwb = &hwb_list[hwidx];
4373 swz = &sc->sge.sw_zone_info[zidx];
4375 region3 = swz->size - hwb->size;
4378 * Stay within this zone and see if there is a better match when mbuf
4379 * inlining is allowed. Remember that the hwidx's are sorted in
4380 * decreasing order of size (so in increasing order of spare area).
4382 for (idx = hwidx; idx != -1; idx = hwb->next) {
4383 hwb = &hwb_list[idx];
4384 spare = swz->size - hwb->size;
4386 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
4390 * Do not inline mbufs if doing so would violate the pad/pack
4391 * boundary alignment requirement.
4393 if (fl_pad && (MSIZE % sc->sge.pad_boundary) != 0)
4395 if (fl->flags & FL_BUF_PACKING &&
4396 (MSIZE % sc->sge.pack_boundary) != 0)
4399 if (spare < CL_METADATA_SIZE + MSIZE)
4401 n = (spare - CL_METADATA_SIZE) / MSIZE;
4402 if (n > howmany(hwb->size, maxp))
4406 if (fl->flags & FL_BUF_PACKING) {
4407 region1 = n * MSIZE;
4408 region3 = spare - region1;
4411 region3 = spare - region1;
4416 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
4417 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
4418 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
4419 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
4420 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
4421 sc->sge.sw_zone_info[zidx].size,
4422 ("%s: bad buffer layout for fl %p, maxp %d. "
4423 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4424 sc->sge.sw_zone_info[zidx].size, region1,
4425 sc->sge.hw_buf_info[hwidx].size, region3));
4426 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
4427 KASSERT(region3 >= CL_METADATA_SIZE,
4428 ("%s: no room for metadata. fl %p, maxp %d; "
4429 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4430 sc->sge.sw_zone_info[zidx].size, region1,
4431 sc->sge.hw_buf_info[hwidx].size, region3));
4432 KASSERT(region1 % MSIZE == 0,
4433 ("%s: bad mbuf region for fl %p, maxp %d. "
4434 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4435 sc->sge.sw_zone_info[zidx].size, region1,
4436 sc->sge.hw_buf_info[hwidx].size, region3));
4439 fl->cll_def.zidx = zidx;
4440 fl->cll_def.hwidx = hwidx;
4441 fl->cll_def.region1 = region1;
4442 fl->cll_def.region3 = region3;
4446 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
4448 struct sge *s = &sc->sge;
4449 struct hw_buf_info *hwb;
4450 struct sw_zone_info *swz;
4454 if (fl->flags & FL_BUF_PACKING)
4455 hwidx = s->safe_hwidx2; /* with room for metadata */
4456 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
4457 hwidx = s->safe_hwidx2;
4458 hwb = &s->hw_buf_info[hwidx];
4459 swz = &s->sw_zone_info[hwb->zidx];
4460 spare = swz->size - hwb->size;
4462 /* no good if there isn't room for an mbuf as well */
4463 if (spare < CL_METADATA_SIZE + MSIZE)
4464 hwidx = s->safe_hwidx1;
4466 hwidx = s->safe_hwidx1;
4469 /* No fallback source */
4470 fl->cll_alt.hwidx = -1;
4471 fl->cll_alt.zidx = -1;
4476 hwb = &s->hw_buf_info[hwidx];
4477 swz = &s->sw_zone_info[hwb->zidx];
4478 spare = swz->size - hwb->size;
4479 fl->cll_alt.hwidx = hwidx;
4480 fl->cll_alt.zidx = hwb->zidx;
4481 if (allow_mbufs_in_cluster &&
4482 (fl_pad == 0 || (MSIZE % sc->sge.pad_boundary) == 0))
4483 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
4485 fl->cll_alt.region1 = 0;
4486 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
4490 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
4492 mtx_lock(&sc->sfl_lock);
4494 if ((fl->flags & FL_DOOMED) == 0) {
4495 fl->flags |= FL_STARVING;
4496 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
4497 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
4500 mtx_unlock(&sc->sfl_lock);
4504 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
4507 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
4508 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
4509 struct adapter *sc = iq->adapter;
4510 struct sge *s = &sc->sge;
4513 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4516 eq = s->eqmap[qid - s->eq_start];
4518 KASSERT(eq->flags & EQ_CRFLUSHED,
4519 ("%s: unsolicited egress update", __func__));
4520 eq->flags &= ~EQ_CRFLUSHED;
4523 if (__predict_false(eq->flags & EQ_DOOMED))
4525 else if (eq->flags & EQ_STALLED && can_resume_tx(eq))
4526 taskqueue_enqueue(sc->tq[eq->tx_chan], &eq->tx_task);
4532 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
4533 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
4534 offsetof(struct cpl_fw6_msg, data));
4537 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
4539 struct adapter *sc = iq->adapter;
4540 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
4542 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4545 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
4546 const struct rss_header *rss2;
4548 rss2 = (const struct rss_header *)&cpl->data[0];
4549 return (sc->cpl_handler[rss2->opcode](iq, rss2, m));
4552 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0]));
4556 sysctl_uint16(SYSCTL_HANDLER_ARGS)
4558 uint16_t *id = arg1;
4561 return sysctl_handle_int(oidp, &i, 0, req);
4565 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
4567 struct sge *s = arg1;
4568 struct hw_buf_info *hwb = &s->hw_buf_info[0];
4569 struct sw_zone_info *swz = &s->sw_zone_info[0];
4574 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
4575 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
4576 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
4581 sbuf_printf(&sb, "%u%c ", hwb->size, c);
4585 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);