2 * Copyright (c) 2011 Chelsio Communications, Inc.
4 * Written by: Navdeep Parhar <np@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/types.h>
36 #include <sys/socket.h>
37 #include <sys/kernel.h>
38 #include <sys/malloc.h>
39 #include <sys/queue.h>
41 #include <sys/taskqueue.h>
43 #include <sys/sglist.h>
44 #include <sys/sysctl.h>
46 #include <sys/counter.h>
48 #include <net/ethernet.h>
50 #include <net/if_vlan_var.h>
51 #include <netinet/in.h>
52 #include <netinet/ip.h>
53 #include <netinet/ip6.h>
54 #include <netinet/tcp.h>
55 #include <machine/md_var.h>
59 #include <machine/bus.h>
60 #include <sys/selinfo.h>
61 #include <net/if_var.h>
62 #include <net/netmap.h>
63 #include <dev/netmap/netmap_kern.h>
66 #include "common/common.h"
67 #include "common/t4_regs.h"
68 #include "common/t4_regs_values.h"
69 #include "common/t4_msg.h"
70 #include "t4_mp_ring.h"
72 #ifdef T4_PKT_TIMESTAMP
73 #define RX_COPY_THRESHOLD (MINCLSIZE - 8)
75 #define RX_COPY_THRESHOLD MINCLSIZE
79 * Ethernet frames are DMA'd at this byte offset into the freelist buffer.
80 * 0-7 are valid values.
83 TUNABLE_INT("hw.cxgbe.fl_pktshift", &fl_pktshift);
86 * Pad ethernet payload up to this boundary.
87 * -1: driver should figure out a good value.
89 * Any power of 2 from 32 to 4096 (both inclusive) is also a valid value.
92 TUNABLE_INT("hw.cxgbe.fl_pad", &fl_pad);
96 * -1: driver should figure out a good value.
97 * 64 or 128 are the only other valid values.
100 TUNABLE_INT("hw.cxgbe.spg_len", &spg_len);
104 * -1: no congestion feedback (not recommended).
105 * 0: backpressure the channel instead of dropping packets right away.
106 * 1: no backpressure, drop packets for the congested queue immediately.
108 static int cong_drop = 0;
109 TUNABLE_INT("hw.cxgbe.cong_drop", &cong_drop);
112 * Deliver multiple frames in the same free list buffer if they fit.
113 * -1: let the driver decide whether to enable buffer packing or not.
114 * 0: disable buffer packing.
115 * 1: enable buffer packing.
117 static int buffer_packing = -1;
118 TUNABLE_INT("hw.cxgbe.buffer_packing", &buffer_packing);
121 * Start next frame in a packed buffer at this boundary.
122 * -1: driver should figure out a good value.
123 * T4: driver will ignore this and use the same value as fl_pad above.
124 * T5: 16, or a power of 2 from 64 to 4096 (both inclusive) is a valid value.
126 static int fl_pack = -1;
127 TUNABLE_INT("hw.cxgbe.fl_pack", &fl_pack);
130 * Allow the driver to create mbuf(s) in a cluster allocated for rx.
131 * 0: never; always allocate mbufs from the zone_mbuf UMA zone.
132 * 1: ok to create mbuf(s) within a cluster if there is room.
134 static int allow_mbufs_in_cluster = 1;
135 TUNABLE_INT("hw.cxgbe.allow_mbufs_in_cluster", &allow_mbufs_in_cluster);
138 * Largest rx cluster size that the driver is allowed to allocate.
140 static int largest_rx_cluster = MJUM16BYTES;
141 TUNABLE_INT("hw.cxgbe.largest_rx_cluster", &largest_rx_cluster);
144 * Size of cluster allocation that's most likely to succeed. The driver will
145 * fall back to this size if it fails to allocate clusters larger than this.
147 static int safest_rx_cluster = PAGE_SIZE;
148 TUNABLE_INT("hw.cxgbe.safest_rx_cluster", &safest_rx_cluster);
151 u_int wr_type; /* type 0 or type 1 */
152 u_int npkt; /* # of packets in this work request */
153 u_int plen; /* total payload (sum of all packets) */
154 u_int len16; /* # of 16B pieces used by this work request */
157 /* A packet's SGL. This + m_pkthdr has all info needed for tx */
160 struct sglist_seg seg[TX_SGL_SEGS];
163 static int service_iq(struct sge_iq *, int);
164 static struct mbuf *get_fl_payload(struct adapter *, struct sge_fl *, uint32_t);
165 static int t4_eth_rx(struct sge_iq *, const struct rss_header *, struct mbuf *);
166 static inline void init_iq(struct sge_iq *, struct adapter *, int, int, int);
167 static inline void init_fl(struct adapter *, struct sge_fl *, int, int, char *);
168 static inline void init_eq(struct sge_eq *, int, int, uint8_t, uint16_t,
170 static int alloc_ring(struct adapter *, size_t, bus_dma_tag_t *, bus_dmamap_t *,
171 bus_addr_t *, void **);
172 static int free_ring(struct adapter *, bus_dma_tag_t, bus_dmamap_t, bus_addr_t,
174 static int alloc_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *,
176 static int free_iq_fl(struct port_info *, struct sge_iq *, struct sge_fl *);
177 static void add_fl_sysctls(struct sysctl_ctx_list *, struct sysctl_oid *,
179 static int alloc_fwq(struct adapter *);
180 static int free_fwq(struct adapter *);
181 static int alloc_mgmtq(struct adapter *);
182 static int free_mgmtq(struct adapter *);
183 static int alloc_rxq(struct port_info *, struct sge_rxq *, int, int,
184 struct sysctl_oid *);
185 static int free_rxq(struct port_info *, struct sge_rxq *);
187 static int alloc_ofld_rxq(struct port_info *, struct sge_ofld_rxq *, int, int,
188 struct sysctl_oid *);
189 static int free_ofld_rxq(struct port_info *, struct sge_ofld_rxq *);
192 static int alloc_nm_rxq(struct port_info *, struct sge_nm_rxq *, int, int,
193 struct sysctl_oid *);
194 static int free_nm_rxq(struct port_info *, struct sge_nm_rxq *);
195 static int alloc_nm_txq(struct port_info *, struct sge_nm_txq *, int, int,
196 struct sysctl_oid *);
197 static int free_nm_txq(struct port_info *, struct sge_nm_txq *);
199 static int ctrl_eq_alloc(struct adapter *, struct sge_eq *);
200 static int eth_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *);
202 static int ofld_eq_alloc(struct adapter *, struct port_info *, struct sge_eq *);
204 static int alloc_eq(struct adapter *, struct port_info *, struct sge_eq *);
205 static int free_eq(struct adapter *, struct sge_eq *);
206 static int alloc_wrq(struct adapter *, struct port_info *, struct sge_wrq *,
207 struct sysctl_oid *);
208 static int free_wrq(struct adapter *, struct sge_wrq *);
209 static int alloc_txq(struct port_info *, struct sge_txq *, int,
210 struct sysctl_oid *);
211 static int free_txq(struct port_info *, struct sge_txq *);
212 static void oneseg_dma_callback(void *, bus_dma_segment_t *, int, int);
213 static inline void ring_fl_db(struct adapter *, struct sge_fl *);
214 static int refill_fl(struct adapter *, struct sge_fl *, int);
215 static void refill_sfl(void *);
216 static int alloc_fl_sdesc(struct sge_fl *);
217 static void free_fl_sdesc(struct adapter *, struct sge_fl *);
218 static void find_best_refill_source(struct adapter *, struct sge_fl *, int);
219 static void find_safe_refill_source(struct adapter *, struct sge_fl *);
220 static void add_fl_to_sfl(struct adapter *, struct sge_fl *);
222 static inline void get_pkt_gl(struct mbuf *, struct sglist *);
223 static inline u_int txpkt_len16(u_int, u_int);
224 static inline u_int txpkts0_len16(u_int);
225 static inline u_int txpkts1_len16(void);
226 static u_int write_txpkt_wr(struct sge_txq *, struct fw_eth_tx_pkt_wr *,
227 struct mbuf *, u_int);
228 static int try_txpkts(struct mbuf *, struct mbuf *, struct txpkts *, u_int);
229 static int add_to_txpkts(struct mbuf *, struct txpkts *, u_int);
230 static u_int write_txpkts_wr(struct sge_txq *, struct fw_eth_tx_pkts_wr *,
231 struct mbuf *, const struct txpkts *, u_int);
232 static void write_gl_to_txd(struct sge_txq *, struct mbuf *, caddr_t *, int);
233 static inline void copy_to_txd(struct sge_eq *, caddr_t, caddr_t *, int);
234 static inline void ring_eq_db(struct adapter *, struct sge_eq *, u_int);
235 static inline uint16_t read_hw_cidx(struct sge_eq *);
236 static inline u_int reclaimable_tx_desc(struct sge_eq *);
237 static inline u_int total_available_tx_desc(struct sge_eq *);
238 static u_int reclaim_tx_descs(struct sge_txq *, u_int);
239 static void tx_reclaim(void *, int);
240 static __be64 get_flit(struct sglist_seg *, int, int);
241 static int handle_sge_egr_update(struct sge_iq *, const struct rss_header *,
243 static int handle_fw_msg(struct sge_iq *, const struct rss_header *,
245 static void wrq_tx_drain(void *, int);
246 static void drain_wrq_wr_list(struct adapter *, struct sge_wrq *);
248 static int sysctl_uint16(SYSCTL_HANDLER_ARGS);
249 static int sysctl_bufsizes(SYSCTL_HANDLER_ARGS);
251 static counter_u64_t extfree_refs;
252 static counter_u64_t extfree_rels;
255 * Called on MOD_LOAD. Validates and calculates the SGE tunables.
261 if (fl_pktshift < 0 || fl_pktshift > 7) {
262 printf("Invalid hw.cxgbe.fl_pktshift value (%d),"
263 " using 2 instead.\n", fl_pktshift);
267 if (spg_len != 64 && spg_len != 128) {
270 #if defined(__i386__) || defined(__amd64__)
271 len = cpu_clflush_line_size > 64 ? 128 : 64;
276 printf("Invalid hw.cxgbe.spg_len value (%d),"
277 " using %d instead.\n", spg_len, len);
282 if (cong_drop < -1 || cong_drop > 1) {
283 printf("Invalid hw.cxgbe.cong_drop value (%d),"
284 " using 0 instead.\n", cong_drop);
288 extfree_refs = counter_u64_alloc(M_WAITOK);
289 extfree_rels = counter_u64_alloc(M_WAITOK);
290 counter_u64_zero(extfree_refs);
291 counter_u64_zero(extfree_rels);
295 t4_sge_modunload(void)
298 counter_u64_free(extfree_refs);
299 counter_u64_free(extfree_rels);
303 t4_sge_extfree_refs(void)
307 rels = counter_u64_fetch(extfree_rels);
308 refs = counter_u64_fetch(extfree_refs);
310 return (refs - rels);
314 t4_init_sge_cpl_handlers(struct adapter *sc)
317 t4_register_cpl_handler(sc, CPL_FW4_MSG, handle_fw_msg);
318 t4_register_cpl_handler(sc, CPL_FW6_MSG, handle_fw_msg);
319 t4_register_cpl_handler(sc, CPL_SGE_EGR_UPDATE, handle_sge_egr_update);
320 t4_register_cpl_handler(sc, CPL_RX_PKT, t4_eth_rx);
321 t4_register_fw_msg_handler(sc, FW6_TYPE_CMD_RPL, t4_handle_fw_rpl);
325 setup_pad_and_pack_boundaries(struct adapter *sc)
331 if (fl_pad < 32 || fl_pad > 4096 || !powerof2(fl_pad)) {
333 * If there is any chance that we might use buffer packing and
334 * the chip is a T4, then pick 64 as the pad/pack boundary. Set
335 * it to 32 in all other cases.
337 pad = is_t4(sc) && buffer_packing ? 64 : 32;
340 * For fl_pad = 0 we'll still write a reasonable value to the
341 * register but all the freelists will opt out of padding.
342 * We'll complain here only if the user tried to set it to a
343 * value greater than 0 that was invalid.
346 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pad value"
347 " (%d), using %d instead.\n", fl_pad, pad);
350 m = V_INGPADBOUNDARY(M_INGPADBOUNDARY);
351 v = V_INGPADBOUNDARY(ilog2(pad) - 5);
352 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
355 if (fl_pack != -1 && fl_pack != pad) {
356 /* Complain but carry on. */
357 device_printf(sc->dev, "hw.cxgbe.fl_pack (%d) ignored,"
358 " using %d instead.\n", fl_pack, pad);
364 if (fl_pack < 16 || fl_pack == 32 || fl_pack > 4096 ||
365 !powerof2(fl_pack)) {
366 pack = max(sc->params.pci.mps, CACHE_LINE_SIZE);
367 MPASS(powerof2(pack));
375 device_printf(sc->dev, "Invalid hw.cxgbe.fl_pack value"
376 " (%d), using %d instead.\n", fl_pack, pack);
379 m = V_INGPACKBOUNDARY(M_INGPACKBOUNDARY);
381 v = V_INGPACKBOUNDARY(0);
383 v = V_INGPACKBOUNDARY(ilog2(pack) - 5);
385 MPASS(!is_t4(sc)); /* T4 doesn't have SGE_CONTROL2 */
386 t4_set_reg_field(sc, A_SGE_CONTROL2, m, v);
390 * adap->params.vpd.cclk must be set up before this is called.
393 t4_tweak_chip_settings(struct adapter *sc)
397 int intr_timer[SGE_NTIMERS] = {1, 5, 10, 50, 100, 200};
398 int timer_max = M_TIMERVALUE0 * 1000 / sc->params.vpd.cclk;
399 int intr_pktcount[SGE_NCOUNTERS] = {1, 8, 16, 32}; /* 63 max */
400 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
401 static int sge_flbuf_sizes[] = {
403 #if MJUMPAGESIZE != MCLBYTES
405 MJUMPAGESIZE - CL_METADATA_SIZE,
406 MJUMPAGESIZE - 2 * MSIZE - CL_METADATA_SIZE,
410 MCLBYTES - MSIZE - CL_METADATA_SIZE,
411 MJUM9BYTES - CL_METADATA_SIZE,
412 MJUM16BYTES - CL_METADATA_SIZE,
415 KASSERT(sc->flags & MASTER_PF,
416 ("%s: trying to change chip settings when not master.", __func__));
418 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
419 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
420 V_EGRSTATUSPAGESIZE(spg_len == 128);
421 t4_set_reg_field(sc, A_SGE_CONTROL, m, v);
423 setup_pad_and_pack_boundaries(sc);
425 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
426 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
427 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
428 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
429 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
430 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
431 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
432 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
433 t4_write_reg(sc, A_SGE_HOST_PAGE_SIZE, v);
435 KASSERT(nitems(sge_flbuf_sizes) <= SGE_FLBUF_SIZES,
436 ("%s: hw buffer size table too big", __func__));
437 for (i = 0; i < min(nitems(sge_flbuf_sizes), SGE_FLBUF_SIZES); i++) {
438 t4_write_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i),
442 v = V_THRESHOLD_0(intr_pktcount[0]) | V_THRESHOLD_1(intr_pktcount[1]) |
443 V_THRESHOLD_2(intr_pktcount[2]) | V_THRESHOLD_3(intr_pktcount[3]);
444 t4_write_reg(sc, A_SGE_INGRESS_RX_THRESHOLD, v);
446 KASSERT(intr_timer[0] <= timer_max,
447 ("%s: not a single usable timer (%d, %d)", __func__, intr_timer[0],
449 for (i = 1; i < nitems(intr_timer); i++) {
450 KASSERT(intr_timer[i] >= intr_timer[i - 1],
451 ("%s: timers not listed in increasing order (%d)",
454 while (intr_timer[i] > timer_max) {
455 if (i == nitems(intr_timer) - 1) {
456 intr_timer[i] = timer_max;
459 intr_timer[i] += intr_timer[i - 1];
464 v = V_TIMERVALUE0(us_to_core_ticks(sc, intr_timer[0])) |
465 V_TIMERVALUE1(us_to_core_ticks(sc, intr_timer[1]));
466 t4_write_reg(sc, A_SGE_TIMER_VALUE_0_AND_1, v);
467 v = V_TIMERVALUE2(us_to_core_ticks(sc, intr_timer[2])) |
468 V_TIMERVALUE3(us_to_core_ticks(sc, intr_timer[3]));
469 t4_write_reg(sc, A_SGE_TIMER_VALUE_2_AND_3, v);
470 v = V_TIMERVALUE4(us_to_core_ticks(sc, intr_timer[4])) |
471 V_TIMERVALUE5(us_to_core_ticks(sc, intr_timer[5]));
472 t4_write_reg(sc, A_SGE_TIMER_VALUE_4_AND_5, v);
474 if (cong_drop == 0) {
475 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 |
477 t4_set_reg_field(sc, A_TP_PARA_REG3, m, 0);
480 /* 4K, 16K, 64K, 256K DDP "page sizes" */
481 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
482 t4_write_reg(sc, A_ULP_RX_TDDP_PSZ, v);
484 m = v = F_TDDPTAGTCB;
485 t4_set_reg_field(sc, A_ULP_RX_CTL, m, v);
487 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
489 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
490 t4_set_reg_field(sc, A_TP_PARA_REG5, m, v);
494 * SGE wants the buffer to be at least 64B and then a multiple of 16. If
495 * padding is is use the buffer's start and end need to be aligned to the pad
496 * boundary as well. We'll just make sure that the size is a multiple of the
497 * boundary here, it is up to the buffer allocation code to make sure the start
498 * of the buffer is aligned as well.
501 hwsz_ok(struct adapter *sc, int hwsz)
503 int mask = fl_pad ? sc->sge.pad_boundary - 1 : 16 - 1;
505 return (hwsz >= 64 && (hwsz & mask) == 0);
509 * XXX: driver really should be able to deal with unexpected settings.
512 t4_read_chip_settings(struct adapter *sc)
514 struct sge *s = &sc->sge;
517 uint16_t indsz = min(RX_COPY_THRESHOLD - 1, M_INDICATESIZE);
518 static int sw_buf_sizes[] = { /* Sorted by size */
520 #if MJUMPAGESIZE != MCLBYTES
526 struct sw_zone_info *swz, *safe_swz;
527 struct hw_buf_info *hwb;
529 m = V_PKTSHIFT(M_PKTSHIFT) | F_RXPKTCPLMODE | F_EGRSTATUSPAGESIZE;
530 v = V_PKTSHIFT(fl_pktshift) | F_RXPKTCPLMODE |
531 V_EGRSTATUSPAGESIZE(spg_len == 128);
532 r = t4_read_reg(sc, A_SGE_CONTROL);
534 device_printf(sc->dev, "invalid SGE_CONTROL(0x%x)\n", r);
537 s->pad_boundary = 1 << (G_INGPADBOUNDARY(r) + 5);
540 s->pack_boundary = s->pad_boundary;
542 r = t4_read_reg(sc, A_SGE_CONTROL2);
543 if (G_INGPACKBOUNDARY(r) == 0)
544 s->pack_boundary = 16;
546 s->pack_boundary = 1 << (G_INGPACKBOUNDARY(r) + 5);
549 v = V_HOSTPAGESIZEPF0(PAGE_SHIFT - 10) |
550 V_HOSTPAGESIZEPF1(PAGE_SHIFT - 10) |
551 V_HOSTPAGESIZEPF2(PAGE_SHIFT - 10) |
552 V_HOSTPAGESIZEPF3(PAGE_SHIFT - 10) |
553 V_HOSTPAGESIZEPF4(PAGE_SHIFT - 10) |
554 V_HOSTPAGESIZEPF5(PAGE_SHIFT - 10) |
555 V_HOSTPAGESIZEPF6(PAGE_SHIFT - 10) |
556 V_HOSTPAGESIZEPF7(PAGE_SHIFT - 10);
557 r = t4_read_reg(sc, A_SGE_HOST_PAGE_SIZE);
559 device_printf(sc->dev, "invalid SGE_HOST_PAGE_SIZE(0x%x)\n", r);
563 /* Filter out unusable hw buffer sizes entirely (mark with -2). */
564 hwb = &s->hw_buf_info[0];
565 for (i = 0; i < nitems(s->hw_buf_info); i++, hwb++) {
566 r = t4_read_reg(sc, A_SGE_FL_BUFFER_SIZE0 + (4 * i));
568 hwb->zidx = hwsz_ok(sc, r) ? -1 : -2;
573 * Create a sorted list in decreasing order of hw buffer sizes (and so
574 * increasing order of spare area) for each software zone.
576 * If padding is enabled then the start and end of the buffer must align
577 * to the pad boundary; if packing is enabled then they must align with
578 * the pack boundary as well. Allocations from the cluster zones are
579 * aligned to min(size, 4K), so the buffer starts at that alignment and
580 * ends at hwb->size alignment. If mbuf inlining is allowed the
581 * starting alignment will be reduced to MSIZE and the driver will
582 * exercise appropriate caution when deciding on the best buffer layout
585 n = 0; /* no usable buffer size to begin with */
586 swz = &s->sw_zone_info[0];
588 for (i = 0; i < SW_ZONE_SIZES; i++, swz++) {
589 int8_t head = -1, tail = -1;
591 swz->size = sw_buf_sizes[i];
592 swz->zone = m_getzone(swz->size);
593 swz->type = m_gettype(swz->size);
595 if (swz->size < PAGE_SIZE) {
596 MPASS(powerof2(swz->size));
597 if (fl_pad && (swz->size % sc->sge.pad_boundary != 0))
601 if (swz->size == safest_rx_cluster)
604 hwb = &s->hw_buf_info[0];
605 for (j = 0; j < SGE_FLBUF_SIZES; j++, hwb++) {
606 if (hwb->zidx != -1 || hwb->size > swz->size)
610 MPASS(hwb->size % sc->sge.pad_boundary == 0);
615 else if (hwb->size < s->hw_buf_info[tail].size) {
616 s->hw_buf_info[tail].next = j;
620 struct hw_buf_info *t;
622 for (cur = &head; *cur != -1; cur = &t->next) {
623 t = &s->hw_buf_info[*cur];
624 if (hwb->size == t->size) {
628 if (hwb->size > t->size) {
636 swz->head_hwidx = head;
637 swz->tail_hwidx = tail;
641 if (swz->size - s->hw_buf_info[tail].size >=
643 sc->flags |= BUF_PACKING_OK;
647 device_printf(sc->dev, "no usable SGE FL buffer size.\n");
653 if (safe_swz != NULL) {
654 s->safe_hwidx1 = safe_swz->head_hwidx;
655 for (i = safe_swz->head_hwidx; i != -1; i = hwb->next) {
658 hwb = &s->hw_buf_info[i];
661 MPASS(hwb->size % sc->sge.pad_boundary == 0);
663 spare = safe_swz->size - hwb->size;
664 if (spare >= CL_METADATA_SIZE) {
671 r = t4_read_reg(sc, A_SGE_INGRESS_RX_THRESHOLD);
672 s->counter_val[0] = G_THRESHOLD_0(r);
673 s->counter_val[1] = G_THRESHOLD_1(r);
674 s->counter_val[2] = G_THRESHOLD_2(r);
675 s->counter_val[3] = G_THRESHOLD_3(r);
677 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_0_AND_1);
678 s->timer_val[0] = G_TIMERVALUE0(r) / core_ticks_per_usec(sc);
679 s->timer_val[1] = G_TIMERVALUE1(r) / core_ticks_per_usec(sc);
680 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_2_AND_3);
681 s->timer_val[2] = G_TIMERVALUE2(r) / core_ticks_per_usec(sc);
682 s->timer_val[3] = G_TIMERVALUE3(r) / core_ticks_per_usec(sc);
683 r = t4_read_reg(sc, A_SGE_TIMER_VALUE_4_AND_5);
684 s->timer_val[4] = G_TIMERVALUE4(r) / core_ticks_per_usec(sc);
685 s->timer_val[5] = G_TIMERVALUE5(r) / core_ticks_per_usec(sc);
687 if (cong_drop == 0) {
688 m = F_TUNNELCNGDROP0 | F_TUNNELCNGDROP1 | F_TUNNELCNGDROP2 |
690 r = t4_read_reg(sc, A_TP_PARA_REG3);
692 device_printf(sc->dev,
693 "invalid TP_PARA_REG3(0x%x)\n", r);
698 v = V_HPZ0(0) | V_HPZ1(2) | V_HPZ2(4) | V_HPZ3(6);
699 r = t4_read_reg(sc, A_ULP_RX_TDDP_PSZ);
701 device_printf(sc->dev, "invalid ULP_RX_TDDP_PSZ(0x%x)\n", r);
705 m = v = F_TDDPTAGTCB;
706 r = t4_read_reg(sc, A_ULP_RX_CTL);
708 device_printf(sc->dev, "invalid ULP_RX_CTL(0x%x)\n", r);
712 m = V_INDICATESIZE(M_INDICATESIZE) | F_REARMDDPOFFSET |
714 v = V_INDICATESIZE(indsz) | F_REARMDDPOFFSET | F_RESETDDPOFFSET;
715 r = t4_read_reg(sc, A_TP_PARA_REG5);
717 device_printf(sc->dev, "invalid TP_PARA_REG5(0x%x)\n", r);
721 r = t4_read_reg(sc, A_SGE_CONM_CTRL);
722 s->fl_starve_threshold = G_EGRTHRESHOLD(r) * 2 + 1;
724 s->fl_starve_threshold2 = s->fl_starve_threshold;
726 s->fl_starve_threshold2 = G_EGRTHRESHOLDPACKING(r) * 2 + 1;
728 /* egress queues: log2 of # of doorbells per BAR2 page */
729 r = t4_read_reg(sc, A_SGE_EGRESS_QUEUES_PER_PAGE_PF);
730 r >>= S_QUEUESPERPAGEPF0 +
731 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf;
732 s->eq_s_qpp = r & M_QUEUESPERPAGEPF0;
734 /* ingress queues: log2 of # of doorbells per BAR2 page */
735 r = t4_read_reg(sc, A_SGE_INGRESS_QUEUES_PER_PAGE_PF);
736 r >>= S_QUEUESPERPAGEPF0 +
737 (S_QUEUESPERPAGEPF1 - S_QUEUESPERPAGEPF0) * sc->pf;
738 s->iq_s_qpp = r & M_QUEUESPERPAGEPF0;
740 t4_init_tp_params(sc);
742 t4_read_mtu_tbl(sc, sc->params.mtus, NULL);
743 t4_load_mtus(sc, sc->params.mtus, sc->params.a_wnd, sc->params.b_wnd);
749 t4_create_dma_tag(struct adapter *sc)
753 rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev), 1, 0,
754 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, BUS_SPACE_MAXSIZE,
755 BUS_SPACE_UNRESTRICTED, BUS_SPACE_MAXSIZE, BUS_DMA_ALLOCNOW, NULL,
758 device_printf(sc->dev,
759 "failed to create main DMA tag: %d\n", rc);
766 t4_sge_sysctls(struct adapter *sc, struct sysctl_ctx_list *ctx,
767 struct sysctl_oid_list *children)
770 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "buffer_sizes",
771 CTLTYPE_STRING | CTLFLAG_RD, &sc->sge, 0, sysctl_bufsizes, "A",
772 "freelist buffer sizes");
774 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pktshift", CTLFLAG_RD,
775 NULL, fl_pktshift, "payload DMA offset in rx buffer (bytes)");
777 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pad", CTLFLAG_RD,
778 NULL, sc->sge.pad_boundary, "payload pad boundary (bytes)");
780 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "spg_len", CTLFLAG_RD,
781 NULL, spg_len, "status page size (bytes)");
783 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "cong_drop", CTLFLAG_RD,
784 NULL, cong_drop, "congestion drop setting");
786 SYSCTL_ADD_INT(ctx, children, OID_AUTO, "fl_pack", CTLFLAG_RD,
787 NULL, sc->sge.pack_boundary, "payload pack boundary (bytes)");
791 t4_destroy_dma_tag(struct adapter *sc)
794 bus_dma_tag_destroy(sc->dmat);
800 * Allocate and initialize the firmware event queue and the management queue.
802 * Returns errno on failure. Resources allocated up to that point may still be
803 * allocated. Caller is responsible for cleanup in case this function fails.
806 t4_setup_adapter_queues(struct adapter *sc)
810 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
812 sysctl_ctx_init(&sc->ctx);
813 sc->flags |= ADAP_SYSCTL_CTX;
816 * Firmware event queue
823 * Management queue. This is just a control queue that uses the fwq as
826 rc = alloc_mgmtq(sc);
835 t4_teardown_adapter_queues(struct adapter *sc)
838 ADAPTER_LOCK_ASSERT_NOTOWNED(sc);
840 /* Do this before freeing the queue */
841 if (sc->flags & ADAP_SYSCTL_CTX) {
842 sysctl_ctx_free(&sc->ctx);
843 sc->flags &= ~ADAP_SYSCTL_CTX;
853 port_intr_count(struct port_info *pi)
857 if (pi->flags & INTR_RXQ)
860 if (pi->flags & INTR_OFLD_RXQ)
864 if (pi->flags & INTR_NM_RXQ)
871 first_vector(struct port_info *pi)
873 struct adapter *sc = pi->adapter;
874 int rc = T4_EXTRA_INTR, i;
876 if (sc->intr_count == 1)
879 for_each_port(sc, i) {
880 if (i == pi->port_id)
883 rc += port_intr_count(sc->port[i]);
890 * Given an arbitrary "index," come up with an iq that can be used by other
891 * queues (of this port) for interrupt forwarding, SGE egress updates, etc.
892 * The iq returned is guaranteed to be something that takes direct interrupts.
894 static struct sge_iq *
895 port_intr_iq(struct port_info *pi, int idx)
897 struct adapter *sc = pi->adapter;
898 struct sge *s = &sc->sge;
899 struct sge_iq *iq = NULL;
902 if (sc->intr_count == 1)
903 return (&sc->sge.fwq);
905 nintr = port_intr_count(pi);
907 ("%s: pi %p has no exclusive interrupts, total interrupts = %d",
908 __func__, pi, sc->intr_count));
910 /* Exclude netmap queues as they can't take anyone else's interrupts */
911 if (pi->flags & INTR_NM_RXQ)
914 ("%s: pi %p has nintr %d after netmap adjustment of %d", __func__,
915 pi, nintr, pi->nnmrxq));
919 if (pi->flags & INTR_RXQ) {
921 iq = &s->rxq[pi->first_rxq + i].iq;
927 if (pi->flags & INTR_OFLD_RXQ) {
928 if (i < pi->nofldrxq) {
929 iq = &s->ofld_rxq[pi->first_ofld_rxq + i].iq;
935 panic("%s: pi %p, intr_flags 0x%lx, idx %d, total intr %d\n", __func__,
936 pi, pi->flags & INTR_ALL, idx, nintr);
939 KASSERT(iq->flags & IQ_INTR,
940 ("%s: iq %p (port %p, intr_flags 0x%lx, idx %d)", __func__, iq, pi,
941 pi->flags & INTR_ALL, idx));
945 /* Maximum payload that can be delivered with a single iq descriptor */
947 mtu_to_max_payload(struct adapter *sc, int mtu, const int toe)
953 payload = sc->tt.rx_coalesce ?
954 G_RXCOALESCESIZE(t4_read_reg(sc, A_TP_PARA_REG2)) : mtu;
957 /* large enough even when hw VLAN extraction is disabled */
958 payload = fl_pktshift + ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
968 t4_setup_port_queues(struct port_info *pi)
970 int rc = 0, i, j, intr_idx, iqid;
973 struct sge_wrq *ctrlq;
975 struct sge_ofld_rxq *ofld_rxq;
976 struct sge_wrq *ofld_txq;
979 struct sge_nm_rxq *nm_rxq;
980 struct sge_nm_txq *nm_txq;
983 struct adapter *sc = pi->adapter;
984 struct ifnet *ifp = pi->ifp;
985 struct sysctl_oid *oid = device_get_sysctl_tree(pi->dev);
986 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
987 int maxp, mtu = ifp->if_mtu;
989 /* Interrupt vector to start from (when using multiple vectors) */
990 intr_idx = first_vector(pi);
993 * First pass over all NIC and TOE rx queues:
994 * a) initialize iq and fl
995 * b) allocate queue iff it will take direct interrupts.
997 maxp = mtu_to_max_payload(sc, mtu, 0);
998 if (pi->flags & INTR_RXQ) {
999 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq",
1000 CTLFLAG_RD, NULL, "rx queues");
1002 for_each_rxq(pi, i, rxq) {
1004 init_iq(&rxq->iq, sc, pi->tmr_idx, pi->pktc_idx, pi->qsize_rxq);
1006 snprintf(name, sizeof(name), "%s rxq%d-fl",
1007 device_get_nameunit(pi->dev), i);
1008 init_fl(sc, &rxq->fl, pi->qsize_rxq / 8, maxp, name);
1010 if (pi->flags & INTR_RXQ) {
1011 rxq->iq.flags |= IQ_INTR;
1012 rc = alloc_rxq(pi, rxq, intr_idx, i, oid);
1019 maxp = mtu_to_max_payload(sc, mtu, 1);
1020 if (is_offload(sc) && pi->flags & INTR_OFLD_RXQ) {
1021 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq",
1023 "rx queues for offloaded TCP connections");
1025 for_each_ofld_rxq(pi, i, ofld_rxq) {
1027 init_iq(&ofld_rxq->iq, sc, pi->tmr_idx, pi->pktc_idx,
1030 snprintf(name, sizeof(name), "%s ofld_rxq%d-fl",
1031 device_get_nameunit(pi->dev), i);
1032 init_fl(sc, &ofld_rxq->fl, pi->qsize_rxq / 8, maxp, name);
1034 if (pi->flags & INTR_OFLD_RXQ) {
1035 ofld_rxq->iq.flags |= IQ_INTR;
1036 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid);
1045 * We don't have buffers to back the netmap rx queues right now so we
1046 * create the queues in a way that doesn't set off any congestion signal
1049 if (pi->flags & INTR_NM_RXQ) {
1050 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_rxq",
1051 CTLFLAG_RD, NULL, "rx queues for netmap");
1052 for_each_nm_rxq(pi, i, nm_rxq) {
1053 rc = alloc_nm_rxq(pi, nm_rxq, intr_idx, i, oid);
1062 * Second pass over all NIC and TOE rx queues. The queues forwarding
1063 * their interrupts are allocated now.
1066 if (!(pi->flags & INTR_RXQ)) {
1067 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "rxq",
1068 CTLFLAG_RD, NULL, "rx queues");
1069 for_each_rxq(pi, i, rxq) {
1070 MPASS(!(rxq->iq.flags & IQ_INTR));
1072 intr_idx = port_intr_iq(pi, j)->abs_id;
1074 rc = alloc_rxq(pi, rxq, intr_idx, i, oid);
1081 if (is_offload(sc) && !(pi->flags & INTR_OFLD_RXQ)) {
1082 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_rxq",
1084 "rx queues for offloaded TCP connections");
1085 for_each_ofld_rxq(pi, i, ofld_rxq) {
1086 MPASS(!(ofld_rxq->iq.flags & IQ_INTR));
1088 intr_idx = port_intr_iq(pi, j)->abs_id;
1090 rc = alloc_ofld_rxq(pi, ofld_rxq, intr_idx, i, oid);
1098 if (!(pi->flags & INTR_NM_RXQ))
1099 CXGBE_UNIMPLEMENTED(__func__);
1103 * Now the tx queues. Only one pass needed.
1105 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "txq", CTLFLAG_RD,
1108 for_each_txq(pi, i, txq) {
1109 iqid = port_intr_iq(pi, j)->cntxt_id;
1110 snprintf(name, sizeof(name), "%s txq%d",
1111 device_get_nameunit(pi->dev), i);
1112 init_eq(&txq->eq, EQ_ETH, pi->qsize_txq, pi->tx_chan, iqid,
1115 rc = alloc_txq(pi, txq, i, oid);
1121 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ofld_txq",
1122 CTLFLAG_RD, NULL, "tx queues for offloaded TCP connections");
1123 for_each_ofld_txq(pi, i, ofld_txq) {
1124 struct sysctl_oid *oid2;
1126 iqid = port_intr_iq(pi, j)->cntxt_id;
1127 snprintf(name, sizeof(name), "%s ofld_txq%d",
1128 device_get_nameunit(pi->dev), i);
1129 init_eq(&ofld_txq->eq, EQ_OFLD, pi->qsize_txq, pi->tx_chan,
1132 snprintf(name, sizeof(name), "%d", i);
1133 oid2 = SYSCTL_ADD_NODE(&pi->ctx, SYSCTL_CHILDREN(oid), OID_AUTO,
1134 name, CTLFLAG_RD, NULL, "offload tx queue");
1136 rc = alloc_wrq(sc, pi, ofld_txq, oid2);
1143 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "nm_txq",
1144 CTLFLAG_RD, NULL, "tx queues for netmap use");
1145 for_each_nm_txq(pi, i, nm_txq) {
1146 iqid = pi->first_nm_rxq + (j % pi->nnmrxq);
1147 rc = alloc_nm_txq(pi, nm_txq, iqid, i, oid);
1155 * Finally, the control queue.
1157 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, "ctrlq", CTLFLAG_RD,
1158 NULL, "ctrl queue");
1159 ctrlq = &sc->sge.ctrlq[pi->port_id];
1160 iqid = port_intr_iq(pi, 0)->cntxt_id;
1161 snprintf(name, sizeof(name), "%s ctrlq", device_get_nameunit(pi->dev));
1162 init_eq(&ctrlq->eq, EQ_CTRL, CTRL_EQ_QSIZE, pi->tx_chan, iqid, name);
1163 rc = alloc_wrq(sc, pi, ctrlq, oid);
1167 t4_teardown_port_queues(pi);
1176 t4_teardown_port_queues(struct port_info *pi)
1179 struct adapter *sc = pi->adapter;
1180 struct sge_rxq *rxq;
1181 struct sge_txq *txq;
1183 struct sge_ofld_rxq *ofld_rxq;
1184 struct sge_wrq *ofld_txq;
1187 struct sge_nm_rxq *nm_rxq;
1188 struct sge_nm_txq *nm_txq;
1191 /* Do this before freeing the queues */
1192 if (pi->flags & PORT_SYSCTL_CTX) {
1193 sysctl_ctx_free(&pi->ctx);
1194 pi->flags &= ~PORT_SYSCTL_CTX;
1198 * Take down all the tx queues first, as they reference the rx queues
1199 * (for egress updates, etc.).
1202 free_wrq(sc, &sc->sge.ctrlq[pi->port_id]);
1204 for_each_txq(pi, i, txq) {
1208 for_each_ofld_txq(pi, i, ofld_txq) {
1209 free_wrq(sc, ofld_txq);
1213 for_each_nm_txq(pi, i, nm_txq)
1214 free_nm_txq(pi, nm_txq);
1218 * Then take down the rx queues that forward their interrupts, as they
1219 * reference other rx queues.
1222 for_each_rxq(pi, i, rxq) {
1223 if ((rxq->iq.flags & IQ_INTR) == 0)
1227 for_each_ofld_rxq(pi, i, ofld_rxq) {
1228 if ((ofld_rxq->iq.flags & IQ_INTR) == 0)
1229 free_ofld_rxq(pi, ofld_rxq);
1233 for_each_nm_rxq(pi, i, nm_rxq)
1234 free_nm_rxq(pi, nm_rxq);
1238 * Then take down the rx queues that take direct interrupts.
1241 for_each_rxq(pi, i, rxq) {
1242 if (rxq->iq.flags & IQ_INTR)
1246 for_each_ofld_rxq(pi, i, ofld_rxq) {
1247 if (ofld_rxq->iq.flags & IQ_INTR)
1248 free_ofld_rxq(pi, ofld_rxq);
1256 * Deals with errors and the firmware event queue. All data rx queues forward
1257 * their interrupt to the firmware event queue.
1260 t4_intr_all(void *arg)
1262 struct adapter *sc = arg;
1263 struct sge_iq *fwq = &sc->sge.fwq;
1266 if (atomic_cmpset_int(&fwq->state, IQS_IDLE, IQS_BUSY)) {
1268 atomic_cmpset_int(&fwq->state, IQS_BUSY, IQS_IDLE);
1272 /* Deals with error interrupts */
1274 t4_intr_err(void *arg)
1276 struct adapter *sc = arg;
1278 t4_write_reg(sc, MYPF_REG(A_PCIE_PF_CLI), 0);
1279 t4_slow_intr_handler(sc);
1283 t4_intr_evt(void *arg)
1285 struct sge_iq *iq = arg;
1287 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1289 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1296 struct sge_iq *iq = arg;
1298 if (atomic_cmpset_int(&iq->state, IQS_IDLE, IQS_BUSY)) {
1300 atomic_cmpset_int(&iq->state, IQS_BUSY, IQS_IDLE);
1305 * Deals with anything and everything on the given ingress queue.
1308 service_iq(struct sge_iq *iq, int budget)
1311 struct sge_rxq *rxq = iq_to_rxq(iq); /* Use iff iq is part of rxq */
1312 struct sge_fl *fl; /* Use iff IQ_HAS_FL */
1313 struct adapter *sc = iq->adapter;
1314 struct iq_desc *d = &iq->desc[iq->cidx];
1315 int ndescs = 0, limit;
1316 int rsp_type, refill;
1318 uint16_t fl_hw_cidx;
1320 STAILQ_HEAD(, sge_iq) iql = STAILQ_HEAD_INITIALIZER(iql);
1321 #if defined(INET) || defined(INET6)
1322 const struct timeval lro_timeout = {0, sc->lro_timeout};
1325 KASSERT(iq->state == IQS_BUSY, ("%s: iq %p not BUSY", __func__, iq));
1327 limit = budget ? budget : iq->qsize / 16;
1329 if (iq->flags & IQ_HAS_FL) {
1331 fl_hw_cidx = fl->hw_cidx; /* stable snapshot */
1334 fl_hw_cidx = 0; /* to silence gcc warning */
1338 * We always come back and check the descriptor ring for new indirect
1339 * interrupts and other responses after running a single handler.
1342 while ((d->rsp.u.type_gen & F_RSPD_GEN) == iq->gen) {
1348 rsp_type = G_RSPD_TYPE(d->rsp.u.type_gen);
1349 lq = be32toh(d->rsp.pldbuflen_qid);
1352 case X_RSPD_TYPE_FLBUF:
1354 KASSERT(iq->flags & IQ_HAS_FL,
1355 ("%s: data for an iq (%p) with no freelist",
1358 m0 = get_fl_payload(sc, fl, lq);
1359 if (__predict_false(m0 == NULL))
1361 refill = IDXDIFF(fl->hw_cidx, fl_hw_cidx, fl->sidx) > 2;
1362 #ifdef T4_PKT_TIMESTAMP
1364 * 60 bit timestamp for the payload is
1365 * *(uint64_t *)m0->m_pktdat. Note that it is
1366 * in the leading free-space in the mbuf. The
1367 * kernel can clobber it during a pullup,
1368 * m_copymdata, etc. You need to make sure that
1369 * the mbuf reaches you unmolested if you care
1370 * about the timestamp.
1372 *(uint64_t *)m0->m_pktdat =
1373 be64toh(ctrl->u.last_flit) &
1379 case X_RSPD_TYPE_CPL:
1380 KASSERT(d->rss.opcode < NUM_CPL_CMDS,
1381 ("%s: bad opcode %02x.", __func__,
1383 sc->cpl_handler[d->rss.opcode](iq, &d->rss, m0);
1386 case X_RSPD_TYPE_INTR:
1389 * Interrupts should be forwarded only to queues
1390 * that are not forwarding their interrupts.
1391 * This means service_iq can recurse but only 1
1394 KASSERT(budget == 0,
1395 ("%s: budget %u, rsp_type %u", __func__,
1399 * There are 1K interrupt-capable queues (qids 0
1400 * through 1023). A response type indicating a
1401 * forwarded interrupt with a qid >= 1K is an
1402 * iWARP async notification.
1405 sc->an_handler(iq, &d->rsp);
1409 q = sc->sge.iqmap[lq - sc->sge.iq_start];
1410 if (atomic_cmpset_int(&q->state, IQS_IDLE,
1412 if (service_iq(q, q->qsize / 16) == 0) {
1413 atomic_cmpset_int(&q->state,
1414 IQS_BUSY, IQS_IDLE);
1416 STAILQ_INSERT_TAIL(&iql, q,
1424 ("%s: illegal response type %d on iq %p",
1425 __func__, rsp_type, iq));
1427 "%s: illegal response type %d on iq %p",
1428 device_get_nameunit(sc->dev), rsp_type, iq);
1433 if (__predict_false(++iq->cidx == iq->sidx)) {
1435 iq->gen ^= F_RSPD_GEN;
1438 if (__predict_false(++ndescs == limit)) {
1439 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS),
1441 V_INGRESSQID(iq->cntxt_id) |
1442 V_SEINTARM(V_QINTR_TIMER_IDX(X_TIMERREG_UPDATE_CIDX)));
1445 #if defined(INET) || defined(INET6)
1446 if (iq->flags & IQ_LRO_ENABLED &&
1447 sc->lro_timeout != 0) {
1448 tcp_lro_flush_inactive(&rxq->lro,
1454 if (iq->flags & IQ_HAS_FL) {
1456 refill_fl(sc, fl, 32);
1459 return (EINPROGRESS);
1464 refill_fl(sc, fl, 32);
1466 fl_hw_cidx = fl->hw_cidx;
1471 if (STAILQ_EMPTY(&iql))
1475 * Process the head only, and send it to the back of the list if
1476 * it's still not done.
1478 q = STAILQ_FIRST(&iql);
1479 STAILQ_REMOVE_HEAD(&iql, link);
1480 if (service_iq(q, q->qsize / 8) == 0)
1481 atomic_cmpset_int(&q->state, IQS_BUSY, IQS_IDLE);
1483 STAILQ_INSERT_TAIL(&iql, q, link);
1486 #if defined(INET) || defined(INET6)
1487 if (iq->flags & IQ_LRO_ENABLED) {
1488 struct lro_ctrl *lro = &rxq->lro;
1489 struct lro_entry *l;
1491 while (!SLIST_EMPTY(&lro->lro_active)) {
1492 l = SLIST_FIRST(&lro->lro_active);
1493 SLIST_REMOVE_HEAD(&lro->lro_active, next);
1494 tcp_lro_flush(lro, l);
1499 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_CIDXINC(ndescs) |
1500 V_INGRESSQID((u32)iq->cntxt_id) | V_SEINTARM(iq->intr_params));
1502 if (iq->flags & IQ_HAS_FL) {
1506 starved = refill_fl(sc, fl, 64);
1508 if (__predict_false(starved != 0))
1509 add_fl_to_sfl(sc, fl);
1516 cl_has_metadata(struct sge_fl *fl, struct cluster_layout *cll)
1518 int rc = fl->flags & FL_BUF_PACKING || cll->region1 > 0;
1521 MPASS(cll->region3 >= CL_METADATA_SIZE);
1526 static inline struct cluster_metadata *
1527 cl_metadata(struct adapter *sc, struct sge_fl *fl, struct cluster_layout *cll,
1531 if (cl_has_metadata(fl, cll)) {
1532 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1534 return ((struct cluster_metadata *)(cl + swz->size) - 1);
1540 rxb_free(struct mbuf *m, void *arg1, void *arg2)
1542 uma_zone_t zone = arg1;
1545 uma_zfree(zone, cl);
1546 counter_u64_add(extfree_rels, 1);
1548 return (EXT_FREE_OK);
1552 * The mbuf returned by this function could be allocated from zone_mbuf or
1553 * constructed in spare room in the cluster.
1555 * The mbuf carries the payload in one of these ways
1556 * a) frame inside the mbuf (mbuf from zone_mbuf)
1557 * b) m_cljset (for clusters without metadata) zone_mbuf
1558 * c) m_extaddref (cluster with metadata) inline mbuf
1559 * d) m_extaddref (cluster with metadata) zone_mbuf
1561 static struct mbuf *
1562 get_scatter_segment(struct adapter *sc, struct sge_fl *fl, int fr_offset,
1566 struct fl_sdesc *sd = &fl->sdesc[fl->cidx];
1567 struct cluster_layout *cll = &sd->cll;
1568 struct sw_zone_info *swz = &sc->sge.sw_zone_info[cll->zidx];
1569 struct hw_buf_info *hwb = &sc->sge.hw_buf_info[cll->hwidx];
1570 struct cluster_metadata *clm = cl_metadata(sc, fl, cll, sd->cl);
1574 blen = hwb->size - fl->rx_offset; /* max possible in this buf */
1575 len = min(remaining, blen);
1576 payload = sd->cl + cll->region1 + fl->rx_offset;
1577 if (fl->flags & FL_BUF_PACKING) {
1578 const u_int l = fr_offset + len;
1579 const u_int pad = roundup2(l, fl->buf_boundary) - l;
1581 if (fl->rx_offset + len + pad < hwb->size)
1583 MPASS(fl->rx_offset + blen <= hwb->size);
1585 MPASS(fl->rx_offset == 0); /* not packing */
1589 if (sc->sc_do_rxcopy && len < RX_COPY_THRESHOLD) {
1592 * Copy payload into a freshly allocated mbuf.
1595 m = fr_offset == 0 ?
1596 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1599 fl->mbuf_allocated++;
1600 #ifdef T4_PKT_TIMESTAMP
1601 /* Leave room for a timestamp */
1604 /* copy data to mbuf */
1605 bcopy(payload, mtod(m, caddr_t), len);
1607 } else if (sd->nmbuf * MSIZE < cll->region1) {
1610 * There's spare room in the cluster for an mbuf. Create one
1611 * and associate it with the payload that's in the cluster.
1615 m = (struct mbuf *)(sd->cl + sd->nmbuf * MSIZE);
1616 /* No bzero required */
1617 if (m_init(m, NULL, 0, M_NOWAIT, MT_DATA,
1618 fr_offset == 0 ? M_PKTHDR | M_NOFREE : M_NOFREE))
1621 m_extaddref(m, payload, blen, &clm->refcount, rxb_free,
1623 if (sd->nmbuf++ == 0)
1624 counter_u64_add(extfree_refs, 1);
1629 * Grab an mbuf from zone_mbuf and associate it with the
1630 * payload in the cluster.
1633 m = fr_offset == 0 ?
1634 m_gethdr(M_NOWAIT, MT_DATA) : m_get(M_NOWAIT, MT_DATA);
1637 fl->mbuf_allocated++;
1639 m_extaddref(m, payload, blen, &clm->refcount,
1640 rxb_free, swz->zone, sd->cl);
1641 if (sd->nmbuf++ == 0)
1642 counter_u64_add(extfree_refs, 1);
1644 m_cljset(m, sd->cl, swz->type);
1645 sd->cl = NULL; /* consumed, not a recycle candidate */
1649 m->m_pkthdr.len = remaining;
1652 if (fl->flags & FL_BUF_PACKING) {
1653 fl->rx_offset += blen;
1654 MPASS(fl->rx_offset <= hwb->size);
1655 if (fl->rx_offset < hwb->size)
1656 return (m); /* without advancing the cidx */
1659 if (__predict_false(++fl->cidx % 8 == 0)) {
1660 uint16_t cidx = fl->cidx / 8;
1662 if (__predict_false(cidx == fl->sidx))
1663 fl->cidx = cidx = 0;
1671 static struct mbuf *
1672 get_fl_payload(struct adapter *sc, struct sge_fl *fl, uint32_t len_newbuf)
1674 struct mbuf *m0, *m, **pnext;
1676 const u_int total = G_RSPD_LEN(len_newbuf);
1678 if (__predict_false(fl->flags & FL_BUF_RESUME)) {
1679 M_ASSERTPKTHDR(fl->m0);
1680 MPASS(fl->m0->m_pkthdr.len == total);
1681 MPASS(fl->remaining < total);
1685 remaining = fl->remaining;
1686 fl->flags &= ~FL_BUF_RESUME;
1690 if (fl->rx_offset > 0 && len_newbuf & F_RSPD_NEWBUF) {
1692 if (__predict_false(++fl->cidx % 8 == 0)) {
1693 uint16_t cidx = fl->cidx / 8;
1695 if (__predict_false(cidx == fl->sidx))
1696 fl->cidx = cidx = 0;
1702 * Payload starts at rx_offset in the current hw buffer. Its length is
1703 * 'len' and it may span multiple hw buffers.
1706 m0 = get_scatter_segment(sc, fl, 0, total);
1709 remaining = total - m0->m_len;
1710 pnext = &m0->m_next;
1711 while (remaining > 0) {
1713 MPASS(fl->rx_offset == 0);
1714 m = get_scatter_segment(sc, fl, total - remaining, remaining);
1715 if (__predict_false(m == NULL)) {
1718 fl->remaining = remaining;
1719 fl->flags |= FL_BUF_RESUME;
1724 remaining -= m->m_len;
1733 t4_eth_rx(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m0)
1735 struct sge_rxq *rxq = iq_to_rxq(iq);
1736 struct ifnet *ifp = rxq->ifp;
1737 const struct cpl_rx_pkt *cpl = (const void *)(rss + 1);
1738 #if defined(INET) || defined(INET6)
1739 struct lro_ctrl *lro = &rxq->lro;
1742 KASSERT(m0 != NULL, ("%s: no payload with opcode %02x", __func__,
1745 m0->m_pkthdr.len -= fl_pktshift;
1746 m0->m_len -= fl_pktshift;
1747 m0->m_data += fl_pktshift;
1749 m0->m_pkthdr.rcvif = ifp;
1750 M_HASHTYPE_SET(m0, M_HASHTYPE_OPAQUE);
1751 m0->m_pkthdr.flowid = be32toh(rss->hash_val);
1753 if (cpl->csum_calc && !cpl->err_vec) {
1754 if (ifp->if_capenable & IFCAP_RXCSUM &&
1755 cpl->l2info & htobe32(F_RXF_IP)) {
1756 m0->m_pkthdr.csum_flags = (CSUM_IP_CHECKED |
1757 CSUM_IP_VALID | CSUM_DATA_VALID | CSUM_PSEUDO_HDR);
1759 } else if (ifp->if_capenable & IFCAP_RXCSUM_IPV6 &&
1760 cpl->l2info & htobe32(F_RXF_IP6)) {
1761 m0->m_pkthdr.csum_flags = (CSUM_DATA_VALID_IPV6 |
1766 if (__predict_false(cpl->ip_frag))
1767 m0->m_pkthdr.csum_data = be16toh(cpl->csum);
1769 m0->m_pkthdr.csum_data = 0xffff;
1773 m0->m_pkthdr.ether_vtag = be16toh(cpl->vlan);
1774 m0->m_flags |= M_VLANTAG;
1775 rxq->vlan_extraction++;
1778 #if defined(INET) || defined(INET6)
1779 if (cpl->l2info & htobe32(F_RXF_LRO) &&
1780 iq->flags & IQ_LRO_ENABLED &&
1781 tcp_lro_rx(lro, m0, 0) == 0) {
1782 /* queued for LRO */
1785 ifp->if_input(ifp, m0);
1791 * Must drain the wrq or make sure that someone else will.
1794 wrq_tx_drain(void *arg, int n)
1796 struct sge_wrq *wrq = arg;
1797 struct sge_eq *eq = &wrq->eq;
1800 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
1801 drain_wrq_wr_list(wrq->adapter, wrq);
1806 drain_wrq_wr_list(struct adapter *sc, struct sge_wrq *wrq)
1808 struct sge_eq *eq = &wrq->eq;
1809 u_int available, dbdiff; /* # of hardware descriptors */
1812 struct fw_eth_tx_pkt_wr *dst; /* any fw WR struct will do */
1814 EQ_LOCK_ASSERT_OWNED(eq);
1815 MPASS(TAILQ_EMPTY(&wrq->incomplete_wrs));
1816 wr = STAILQ_FIRST(&wrq->wr_list);
1817 MPASS(wr != NULL); /* Must be called with something useful to do */
1818 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
1821 eq->cidx = read_hw_cidx(eq);
1822 if (eq->pidx == eq->cidx)
1823 available = eq->sidx - 1;
1825 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
1827 MPASS(wr->wrq == wrq);
1828 n = howmany(wr->wr_len, EQ_ESIZE);
1832 dst = (void *)&eq->desc[eq->pidx];
1833 if (__predict_true(eq->sidx - eq->pidx > n)) {
1834 /* Won't wrap, won't end exactly at the status page. */
1835 bcopy(&wr->wr[0], dst, wr->wr_len);
1838 int first_portion = (eq->sidx - eq->pidx) * EQ_ESIZE;
1840 bcopy(&wr->wr[0], dst, first_portion);
1841 if (wr->wr_len > first_portion) {
1842 bcopy(&wr->wr[first_portion], &eq->desc[0],
1843 wr->wr_len - first_portion);
1845 eq->pidx = n - (eq->sidx - eq->pidx);
1848 if (available < eq->sidx / 4 &&
1849 atomic_cmpset_int(&eq->equiq, 0, 1)) {
1850 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
1852 eq->equeqidx = eq->pidx;
1853 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
1854 dst->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
1855 eq->equeqidx = eq->pidx;
1860 ring_eq_db(sc, eq, dbdiff);
1864 STAILQ_REMOVE_HEAD(&wrq->wr_list, link);
1866 MPASS(wrq->nwr_pending > 0);
1868 MPASS(wrq->ndesc_needed >= n);
1869 wrq->ndesc_needed -= n;
1870 } while ((wr = STAILQ_FIRST(&wrq->wr_list)) != NULL);
1873 ring_eq_db(sc, eq, dbdiff);
1877 * Doesn't fail. Holds on to work requests it can't send right away.
1880 t4_wrq_tx_locked(struct adapter *sc, struct sge_wrq *wrq, struct wrqe *wr)
1883 struct sge_eq *eq = &wrq->eq;
1886 EQ_LOCK_ASSERT_OWNED(eq);
1888 MPASS(wr->wr_len > 0 && wr->wr_len <= SGE_MAX_WR_LEN);
1889 MPASS((wr->wr_len & 0x7) == 0);
1891 STAILQ_INSERT_TAIL(&wrq->wr_list, wr, link);
1893 wrq->ndesc_needed += howmany(wr->wr_len, EQ_ESIZE);
1895 if (!TAILQ_EMPTY(&wrq->incomplete_wrs))
1896 return; /* commit_wrq_wr will drain wr_list as well. */
1898 drain_wrq_wr_list(sc, wrq);
1900 /* Doorbell must have caught up to the pidx. */
1901 MPASS(eq->pidx == eq->dbidx);
1905 t4_update_fl_bufsize(struct ifnet *ifp)
1907 struct port_info *pi = ifp->if_softc;
1908 struct adapter *sc = pi->adapter;
1909 struct sge_rxq *rxq;
1911 struct sge_ofld_rxq *ofld_rxq;
1914 int i, maxp, mtu = ifp->if_mtu;
1916 maxp = mtu_to_max_payload(sc, mtu, 0);
1917 for_each_rxq(pi, i, rxq) {
1921 find_best_refill_source(sc, fl, maxp);
1925 maxp = mtu_to_max_payload(sc, mtu, 1);
1926 for_each_ofld_rxq(pi, i, ofld_rxq) {
1930 find_best_refill_source(sc, fl, maxp);
1937 mbuf_nsegs(struct mbuf *m)
1941 KASSERT(m->m_pkthdr.l5hlen > 0,
1942 ("%s: mbuf %p missing information on # of segments.", __func__, m));
1944 return (m->m_pkthdr.l5hlen);
1948 set_mbuf_nsegs(struct mbuf *m, uint8_t nsegs)
1952 m->m_pkthdr.l5hlen = nsegs;
1956 mbuf_len16(struct mbuf *m)
1961 n = m->m_pkthdr.PH_loc.eigth[0];
1962 MPASS(n > 0 && n <= SGE_MAX_WR_LEN / 16);
1968 set_mbuf_len16(struct mbuf *m, uint8_t len16)
1972 m->m_pkthdr.PH_loc.eigth[0] = len16;
1976 needs_tso(struct mbuf *m)
1981 if (m->m_pkthdr.csum_flags & CSUM_TSO) {
1982 KASSERT(m->m_pkthdr.tso_segsz > 0,
1983 ("%s: TSO requested in mbuf %p but MSS not provided",
1992 needs_l3_csum(struct mbuf *m)
1997 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TSO))
2003 needs_l4_csum(struct mbuf *m)
2008 if (m->m_pkthdr.csum_flags & (CSUM_TCP | CSUM_UDP | CSUM_UDP_IPV6 |
2009 CSUM_TCP_IPV6 | CSUM_TSO))
2015 needs_vlan_insertion(struct mbuf *m)
2020 if (m->m_flags & M_VLANTAG) {
2021 KASSERT(m->m_pkthdr.ether_vtag != 0,
2022 ("%s: HWVLAN requested in mbuf %p but tag not provided",
2030 m_advance(struct mbuf **pm, int *poffset, int len)
2032 struct mbuf *m = *pm;
2033 int offset = *poffset;
2039 if (offset + len < m->m_len) {
2041 p = mtod(m, uintptr_t) + offset;
2044 len -= m->m_len - offset;
2055 same_paddr(char *a, char *b)
2060 else if (a != NULL && b != NULL) {
2061 vm_offset_t x = (vm_offset_t)a;
2062 vm_offset_t y = (vm_offset_t)b;
2064 if ((x & PAGE_MASK) == (y & PAGE_MASK) &&
2065 pmap_kextract(x) == pmap_kextract(y))
2073 * Can deal with empty mbufs in the chain that have m_len = 0, but the chain
2074 * must have at least one mbuf that's not empty.
2077 count_mbuf_nsegs(struct mbuf *m)
2079 char *prev_end, *start;
2086 for (; m; m = m->m_next) {
2089 if (__predict_false(len == 0))
2091 start = mtod(m, char *);
2093 nsegs += sglist_count(start, len);
2094 if (same_paddr(prev_end, start))
2096 prev_end = start + len;
2104 * Analyze the mbuf to determine its tx needs. The mbuf passed in may change:
2105 * a) caller can assume it's been freed if this function returns with an error.
2106 * b) it may get defragged up if the gather list is too long for the hardware.
2109 parse_pkt(struct mbuf **mp)
2111 struct mbuf *m0 = *mp, *m;
2112 int rc, nsegs, defragged = 0, offset;
2113 struct ether_header *eh;
2115 #if defined(INET) || defined(INET6)
2121 if (__predict_false(m0->m_pkthdr.len < ETHER_HDR_LEN)) {
2130 * First count the number of gather list segments in the payload.
2131 * Defrag the mbuf if nsegs exceeds the hardware limit.
2134 MPASS(m0->m_pkthdr.len > 0);
2135 nsegs = count_mbuf_nsegs(m0);
2136 if (nsegs > (needs_tso(m0) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS)) {
2137 if (defragged++ > 0 || (m = m_defrag(m0, M_NOWAIT)) == NULL) {
2141 *mp = m0 = m; /* update caller's copy after defrag */
2145 if (__predict_false(nsegs > 2 && m0->m_pkthdr.len <= MHLEN)) {
2146 m0 = m_pullup(m0, m0->m_pkthdr.len);
2148 /* Should have left well enough alone. */
2152 *mp = m0; /* update caller's copy after pullup */
2155 set_mbuf_nsegs(m0, nsegs);
2156 set_mbuf_len16(m0, txpkt_len16(nsegs, needs_tso(m0)));
2162 eh = mtod(m, struct ether_header *);
2163 eh_type = ntohs(eh->ether_type);
2164 if (eh_type == ETHERTYPE_VLAN) {
2165 struct ether_vlan_header *evh = (void *)eh;
2167 eh_type = ntohs(evh->evl_proto);
2168 m0->m_pkthdr.l2hlen = sizeof(*evh);
2170 m0->m_pkthdr.l2hlen = sizeof(*eh);
2173 l3hdr = m_advance(&m, &offset, m0->m_pkthdr.l2hlen);
2177 case ETHERTYPE_IPV6:
2179 struct ip6_hdr *ip6 = l3hdr;
2181 MPASS(ip6->ip6_nxt == IPPROTO_TCP);
2183 m0->m_pkthdr.l3hlen = sizeof(*ip6);
2190 struct ip *ip = l3hdr;
2192 m0->m_pkthdr.l3hlen = ip->ip_hl * 4;
2197 panic("%s: ethertype 0x%04x unknown. if_cxgbe must be compiled"
2198 " with the same INET/INET6 options as the kernel.",
2202 #if defined(INET) || defined(INET6)
2203 tcp = m_advance(&m, &offset, m0->m_pkthdr.l3hlen);
2204 m0->m_pkthdr.l4hlen = tcp->th_off * 4;
2211 start_wrq_wr(struct sge_wrq *wrq, int len16, struct wrq_cookie *cookie)
2213 struct sge_eq *eq = &wrq->eq;
2214 struct adapter *sc = wrq->adapter;
2215 int ndesc, available;
2220 ndesc = howmany(len16, EQ_ESIZE / 16);
2221 MPASS(ndesc > 0 && ndesc <= SGE_MAX_WR_NDESC);
2225 if (!STAILQ_EMPTY(&wrq->wr_list))
2226 drain_wrq_wr_list(sc, wrq);
2228 if (!STAILQ_EMPTY(&wrq->wr_list)) {
2231 wr = alloc_wrqe(len16 * 16, wrq);
2232 if (__predict_false(wr == NULL))
2235 cookie->ndesc = ndesc;
2239 eq->cidx = read_hw_cidx(eq);
2240 if (eq->pidx == eq->cidx)
2241 available = eq->sidx - 1;
2243 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2244 if (available < ndesc)
2247 cookie->pidx = eq->pidx;
2248 cookie->ndesc = ndesc;
2249 TAILQ_INSERT_TAIL(&wrq->incomplete_wrs, cookie, link);
2251 w = &eq->desc[eq->pidx];
2252 IDXINCR(eq->pidx, ndesc, eq->sidx);
2253 if (__predict_false(eq->pidx < ndesc - 1)) {
2255 wrq->ss_pidx = cookie->pidx;
2256 wrq->ss_len = len16 * 16;
2265 commit_wrq_wr(struct sge_wrq *wrq, void *w, struct wrq_cookie *cookie)
2267 struct sge_eq *eq = &wrq->eq;
2268 struct adapter *sc = wrq->adapter;
2270 struct wrq_cookie *prev, *next;
2272 if (cookie->pidx == -1) {
2273 struct wrqe *wr = __containerof(w, struct wrqe, wr);
2279 ndesc = cookie->ndesc; /* Can be more than SGE_MAX_WR_NDESC here. */
2280 pidx = cookie->pidx;
2281 MPASS(pidx >= 0 && pidx < eq->sidx);
2282 if (__predict_false(w == &wrq->ss[0])) {
2283 int n = (eq->sidx - wrq->ss_pidx) * EQ_ESIZE;
2285 MPASS(wrq->ss_len > n); /* WR had better wrap around. */
2286 bcopy(&wrq->ss[0], &eq->desc[wrq->ss_pidx], n);
2287 bcopy(&wrq->ss[n], &eq->desc[0], wrq->ss_len - n);
2290 wrq->tx_wrs_direct++;
2293 prev = TAILQ_PREV(cookie, wrq_incomplete_wrs, link);
2294 next = TAILQ_NEXT(cookie, link);
2296 MPASS(pidx == eq->dbidx);
2297 if (next == NULL || ndesc >= 16)
2298 ring_eq_db(wrq->adapter, eq, ndesc);
2300 MPASS(IDXDIFF(next->pidx, pidx, eq->sidx) == ndesc);
2302 next->ndesc += ndesc;
2305 MPASS(IDXDIFF(pidx, prev->pidx, eq->sidx) == prev->ndesc);
2306 prev->ndesc += ndesc;
2308 TAILQ_REMOVE(&wrq->incomplete_wrs, cookie, link);
2310 if (TAILQ_EMPTY(&wrq->incomplete_wrs) && !STAILQ_EMPTY(&wrq->wr_list))
2311 drain_wrq_wr_list(sc, wrq);
2314 if (TAILQ_EMPTY(&wrq->incomplete_wrs)) {
2315 /* Doorbell must have caught up to the pidx. */
2316 MPASS(wrq->eq.pidx == wrq->eq.dbidx);
2323 can_resume_eth_tx(struct mp_ring *r)
2325 struct sge_eq *eq = r->cookie;
2327 return (total_available_tx_desc(eq) > eq->sidx / 8);
2331 cannot_use_txpkts(struct mbuf *m)
2333 /* maybe put a GL limit too, to avoid silliness? */
2335 return (needs_tso(m));
2339 * r->items[cidx] to r->items[pidx], with a wraparound at r->size, are ready to
2340 * be consumed. Return the actual number consumed. 0 indicates a stall.
2343 eth_tx(struct mp_ring *r, u_int cidx, u_int pidx)
2345 struct sge_txq *txq = r->cookie;
2346 struct sge_eq *eq = &txq->eq;
2347 struct ifnet *ifp = txq->ifp;
2348 struct port_info *pi = (void *)ifp->if_softc;
2349 struct adapter *sc = pi->adapter;
2350 u_int total, remaining; /* # of packets */
2351 u_int available, dbdiff; /* # of hardware descriptors */
2353 struct mbuf *m0, *tail;
2355 struct fw_eth_tx_pkts_wr *wr; /* any fw WR struct will do */
2357 remaining = IDXDIFF(pidx, cidx, r->size);
2358 MPASS(remaining > 0); /* Must not be called without work to do. */
2362 if (__predict_false((eq->flags & EQ_ENABLED) == 0)) {
2363 while (cidx != pidx) {
2364 m0 = r->items[cidx];
2366 if (++cidx == r->size)
2369 reclaim_tx_descs(txq, 2048);
2374 /* How many hardware descriptors do we have readily available. */
2375 if (eq->pidx == eq->cidx)
2376 available = eq->sidx - 1;
2378 available = IDXDIFF(eq->cidx, eq->pidx, eq->sidx) - 1;
2379 dbdiff = IDXDIFF(eq->pidx, eq->dbidx, eq->sidx);
2381 while (remaining > 0) {
2383 m0 = r->items[cidx];
2385 MPASS(m0->m_nextpkt == NULL);
2387 if (available < SGE_MAX_WR_NDESC) {
2388 available += reclaim_tx_descs(txq, 64);
2389 if (available < howmany(mbuf_len16(m0), EQ_ESIZE / 16))
2390 break; /* out of descriptors */
2393 next_cidx = cidx + 1;
2394 if (__predict_false(next_cidx == r->size))
2397 wr = (void *)&eq->desc[eq->pidx];
2398 if (remaining > 1 &&
2399 try_txpkts(m0, r->items[next_cidx], &txp, available) == 0) {
2401 /* pkts at cidx, next_cidx should both be in txp. */
2402 MPASS(txp.npkt == 2);
2403 tail = r->items[next_cidx];
2404 MPASS(tail->m_nextpkt == NULL);
2405 ETHER_BPF_MTAP(ifp, m0);
2406 ETHER_BPF_MTAP(ifp, tail);
2407 m0->m_nextpkt = tail;
2409 if (__predict_false(++next_cidx == r->size))
2412 while (next_cidx != pidx) {
2413 if (add_to_txpkts(r->items[next_cidx], &txp,
2416 tail->m_nextpkt = r->items[next_cidx];
2417 tail = tail->m_nextpkt;
2418 ETHER_BPF_MTAP(ifp, tail);
2419 if (__predict_false(++next_cidx == r->size))
2423 n = write_txpkts_wr(txq, wr, m0, &txp, available);
2425 remaining -= txp.npkt;
2429 n = write_txpkt_wr(txq, (void *)wr, m0, available);
2430 ETHER_BPF_MTAP(ifp, m0);
2432 MPASS(n >= 1 && n <= available && n <= SGE_MAX_WR_NDESC);
2436 IDXINCR(eq->pidx, n, eq->sidx);
2438 if (total_available_tx_desc(eq) < eq->sidx / 4 &&
2439 atomic_cmpset_int(&eq->equiq, 0, 1)) {
2440 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUIQ |
2442 eq->equeqidx = eq->pidx;
2443 } else if (IDXDIFF(eq->pidx, eq->equeqidx, eq->sidx) >= 32) {
2444 wr->equiq_to_len16 |= htobe32(F_FW_WR_EQUEQ);
2445 eq->equeqidx = eq->pidx;
2448 if (dbdiff >= 16 && remaining >= 4) {
2449 ring_eq_db(sc, eq, dbdiff);
2450 available += reclaim_tx_descs(txq, 4 * dbdiff);
2457 ring_eq_db(sc, eq, dbdiff);
2458 reclaim_tx_descs(txq, 32);
2467 init_iq(struct sge_iq *iq, struct adapter *sc, int tmr_idx, int pktc_idx,
2471 KASSERT(tmr_idx >= 0 && tmr_idx < SGE_NTIMERS,
2472 ("%s: bad tmr_idx %d", __func__, tmr_idx));
2473 KASSERT(pktc_idx < SGE_NCOUNTERS, /* -ve is ok, means don't use */
2474 ("%s: bad pktc_idx %d", __func__, pktc_idx));
2478 iq->intr_params = V_QINTR_TIMER_IDX(tmr_idx);
2479 iq->intr_pktc_idx = SGE_NCOUNTERS - 1;
2480 if (pktc_idx >= 0) {
2481 iq->intr_params |= F_QINTR_CNT_EN;
2482 iq->intr_pktc_idx = pktc_idx;
2484 iq->qsize = roundup2(qsize, 16); /* See FW_IQ_CMD/iqsize */
2485 iq->sidx = iq->qsize - spg_len / IQ_ESIZE;
2489 init_fl(struct adapter *sc, struct sge_fl *fl, int qsize, int maxp, char *name)
2493 fl->sidx = qsize - spg_len / EQ_ESIZE;
2494 strlcpy(fl->lockname, name, sizeof(fl->lockname));
2495 if (sc->flags & BUF_PACKING_OK &&
2496 ((!is_t4(sc) && buffer_packing) || /* T5+: enabled unless 0 */
2497 (is_t4(sc) && buffer_packing == 1)))/* T4: disabled unless 1 */
2498 fl->flags |= FL_BUF_PACKING;
2499 find_best_refill_source(sc, fl, maxp);
2500 find_safe_refill_source(sc, fl);
2504 init_eq(struct sge_eq *eq, int eqtype, int qsize, uint8_t tx_chan,
2505 uint16_t iqid, char *name)
2507 KASSERT(tx_chan < NCHAN, ("%s: bad tx channel %d", __func__, tx_chan));
2508 KASSERT(eqtype <= EQ_TYPEMASK, ("%s: bad qtype %d", __func__, eqtype));
2510 eq->flags = eqtype & EQ_TYPEMASK;
2511 eq->tx_chan = tx_chan;
2513 eq->sidx = qsize - spg_len / EQ_ESIZE;
2514 strlcpy(eq->lockname, name, sizeof(eq->lockname));
2518 alloc_ring(struct adapter *sc, size_t len, bus_dma_tag_t *tag,
2519 bus_dmamap_t *map, bus_addr_t *pa, void **va)
2523 rc = bus_dma_tag_create(sc->dmat, 512, 0, BUS_SPACE_MAXADDR,
2524 BUS_SPACE_MAXADDR, NULL, NULL, len, 1, len, 0, NULL, NULL, tag);
2526 device_printf(sc->dev, "cannot allocate DMA tag: %d\n", rc);
2530 rc = bus_dmamem_alloc(*tag, va,
2531 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, map);
2533 device_printf(sc->dev, "cannot allocate DMA memory: %d\n", rc);
2537 rc = bus_dmamap_load(*tag, *map, *va, len, oneseg_dma_callback, pa, 0);
2539 device_printf(sc->dev, "cannot load DMA map: %d\n", rc);
2544 free_ring(sc, *tag, *map, *pa, *va);
2550 free_ring(struct adapter *sc, bus_dma_tag_t tag, bus_dmamap_t map,
2551 bus_addr_t pa, void *va)
2554 bus_dmamap_unload(tag, map);
2556 bus_dmamem_free(tag, va, map);
2558 bus_dma_tag_destroy(tag);
2564 * Allocates the ring for an ingress queue and an optional freelist. If the
2565 * freelist is specified it will be allocated and then associated with the
2568 * Returns errno on failure. Resources allocated up to that point may still be
2569 * allocated. Caller is responsible for cleanup in case this function fails.
2571 * If the ingress queue will take interrupts directly (iq->flags & IQ_INTR) then
2572 * the intr_idx specifies the vector, starting from 0. Otherwise it specifies
2573 * the abs_id of the ingress queue to which its interrupts should be forwarded.
2576 alloc_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl,
2577 int intr_idx, int cong)
2579 int rc, i, cntxt_id;
2582 struct adapter *sc = iq->adapter;
2585 len = iq->qsize * IQ_ESIZE;
2586 rc = alloc_ring(sc, len, &iq->desc_tag, &iq->desc_map, &iq->ba,
2587 (void **)&iq->desc);
2591 bzero(&c, sizeof(c));
2592 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_IQ_CMD) | F_FW_CMD_REQUEST |
2593 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_IQ_CMD_PFN(sc->pf) |
2594 V_FW_IQ_CMD_VFN(0));
2596 c.alloc_to_len16 = htobe32(F_FW_IQ_CMD_ALLOC | F_FW_IQ_CMD_IQSTART |
2599 /* Special handling for firmware event queue */
2600 if (iq == &sc->sge.fwq)
2601 v |= F_FW_IQ_CMD_IQASYNCH;
2603 if (iq->flags & IQ_INTR) {
2604 KASSERT(intr_idx < sc->intr_count,
2605 ("%s: invalid direct intr_idx %d", __func__, intr_idx));
2607 v |= F_FW_IQ_CMD_IQANDST;
2608 v |= V_FW_IQ_CMD_IQANDSTINDEX(intr_idx);
2610 c.type_to_iqandstindex = htobe32(v |
2611 V_FW_IQ_CMD_TYPE(FW_IQ_TYPE_FL_INT_CAP) |
2612 V_FW_IQ_CMD_VIID(pi->viid) |
2613 V_FW_IQ_CMD_IQANUD(X_UPDATEDELIVERY_INTERRUPT));
2614 c.iqdroprss_to_iqesize = htobe16(V_FW_IQ_CMD_IQPCIECH(pi->tx_chan) |
2615 F_FW_IQ_CMD_IQGTSMODE |
2616 V_FW_IQ_CMD_IQINTCNTTHRESH(iq->intr_pktc_idx) |
2617 V_FW_IQ_CMD_IQESIZE(ilog2(IQ_ESIZE) - 4));
2618 c.iqsize = htobe16(iq->qsize);
2619 c.iqaddr = htobe64(iq->ba);
2621 c.iqns_to_fl0congen = htobe32(F_FW_IQ_CMD_IQFLINTCONGEN);
2624 mtx_init(&fl->fl_lock, fl->lockname, NULL, MTX_DEF);
2626 len = fl->qsize * EQ_ESIZE;
2627 rc = alloc_ring(sc, len, &fl->desc_tag, &fl->desc_map,
2628 &fl->ba, (void **)&fl->desc);
2632 /* Allocate space for one software descriptor per buffer. */
2633 rc = alloc_fl_sdesc(fl);
2635 device_printf(sc->dev,
2636 "failed to setup fl software descriptors: %d\n",
2641 if (fl->flags & FL_BUF_PACKING) {
2642 fl->lowat = roundup2(sc->sge.fl_starve_threshold2, 8);
2643 fl->buf_boundary = sc->sge.pack_boundary;
2645 fl->lowat = roundup2(sc->sge.fl_starve_threshold, 8);
2646 fl->buf_boundary = 16;
2648 if (fl_pad && fl->buf_boundary < sc->sge.pad_boundary)
2649 fl->buf_boundary = sc->sge.pad_boundary;
2651 c.iqns_to_fl0congen |=
2652 htobe32(V_FW_IQ_CMD_FL0HOSTFCMODE(X_HOSTFCMODE_NONE) |
2653 F_FW_IQ_CMD_FL0FETCHRO | F_FW_IQ_CMD_FL0DATARO |
2654 (fl_pad ? F_FW_IQ_CMD_FL0PADEN : 0) |
2655 (fl->flags & FL_BUF_PACKING ? F_FW_IQ_CMD_FL0PACKEN :
2658 c.iqns_to_fl0congen |=
2659 htobe32(V_FW_IQ_CMD_FL0CNGCHMAP(cong) |
2660 F_FW_IQ_CMD_FL0CONGCIF |
2661 F_FW_IQ_CMD_FL0CONGEN);
2663 c.fl0dcaen_to_fl0cidxfthresh =
2664 htobe16(V_FW_IQ_CMD_FL0FBMIN(X_FETCHBURSTMIN_128B) |
2665 V_FW_IQ_CMD_FL0FBMAX(X_FETCHBURSTMAX_512B));
2666 c.fl0size = htobe16(fl->qsize);
2667 c.fl0addr = htobe64(fl->ba);
2670 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
2672 device_printf(sc->dev,
2673 "failed to create ingress queue: %d\n", rc);
2678 iq->gen = F_RSPD_GEN;
2679 iq->intr_next = iq->intr_params;
2680 iq->cntxt_id = be16toh(c.iqid);
2681 iq->abs_id = be16toh(c.physiqid);
2682 iq->flags |= IQ_ALLOCATED;
2684 cntxt_id = iq->cntxt_id - sc->sge.iq_start;
2685 if (cntxt_id >= sc->sge.niq) {
2686 panic ("%s: iq->cntxt_id (%d) more than the max (%d)", __func__,
2687 cntxt_id, sc->sge.niq - 1);
2689 sc->sge.iqmap[cntxt_id] = iq;
2694 iq->flags |= IQ_HAS_FL;
2695 fl->cntxt_id = be16toh(c.fl0id);
2696 fl->pidx = fl->cidx = 0;
2698 cntxt_id = fl->cntxt_id - sc->sge.eq_start;
2699 if (cntxt_id >= sc->sge.neq) {
2700 panic("%s: fl->cntxt_id (%d) more than the max (%d)",
2701 __func__, cntxt_id, sc->sge.neq - 1);
2703 sc->sge.eqmap[cntxt_id] = (void *)fl;
2706 if (isset(&sc->doorbells, DOORBELL_UDB)) {
2707 uint32_t s_qpp = sc->sge.eq_s_qpp;
2708 uint32_t mask = (1 << s_qpp) - 1;
2709 volatile uint8_t *udb;
2711 udb = sc->udbs_base + UDBS_DB_OFFSET;
2712 udb += (qid >> s_qpp) << PAGE_SHIFT;
2714 if (qid < PAGE_SIZE / UDBS_SEG_SIZE) {
2715 udb += qid << UDBS_SEG_SHIFT;
2718 fl->udb = (volatile void *)udb;
2720 fl->dbval = F_DBPRIO | V_QID(qid);
2722 fl->dbval |= F_DBTYPE;
2725 /* Enough to make sure the SGE doesn't think it's starved */
2726 refill_fl(sc, fl, fl->lowat);
2730 if (is_t5(sc) && cong >= 0) {
2731 uint32_t param, val;
2733 param = V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DMAQ) |
2734 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DMAQ_CONM_CTXT) |
2735 V_FW_PARAMS_PARAM_YZ(iq->cntxt_id);
2740 for (i = 0; i < 4; i++) {
2741 if (cong & (1 << i))
2742 val |= 1 << (i << 2);
2746 rc = -t4_set_params(sc, sc->mbox, sc->pf, 0, 1, ¶m, &val);
2748 /* report error but carry on */
2749 device_printf(sc->dev,
2750 "failed to set congestion manager context for "
2751 "ingress queue %d: %d\n", iq->cntxt_id, rc);
2755 /* Enable IQ interrupts */
2756 atomic_store_rel_int(&iq->state, IQS_IDLE);
2757 t4_write_reg(sc, MYPF_REG(A_SGE_PF_GTS), V_SEINTARM(iq->intr_params) |
2758 V_INGRESSQID(iq->cntxt_id));
2764 free_iq_fl(struct port_info *pi, struct sge_iq *iq, struct sge_fl *fl)
2767 struct adapter *sc = iq->adapter;
2771 return (0); /* nothing to do */
2773 dev = pi ? pi->dev : sc->dev;
2775 if (iq->flags & IQ_ALLOCATED) {
2776 rc = -t4_iq_free(sc, sc->mbox, sc->pf, 0,
2777 FW_IQ_TYPE_FL_INT_CAP, iq->cntxt_id,
2778 fl ? fl->cntxt_id : 0xffff, 0xffff);
2781 "failed to free queue %p: %d\n", iq, rc);
2784 iq->flags &= ~IQ_ALLOCATED;
2787 free_ring(sc, iq->desc_tag, iq->desc_map, iq->ba, iq->desc);
2789 bzero(iq, sizeof(*iq));
2792 free_ring(sc, fl->desc_tag, fl->desc_map, fl->ba,
2796 free_fl_sdesc(sc, fl);
2798 if (mtx_initialized(&fl->fl_lock))
2799 mtx_destroy(&fl->fl_lock);
2801 bzero(fl, sizeof(*fl));
2808 add_fl_sysctls(struct sysctl_ctx_list *ctx, struct sysctl_oid *oid,
2811 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2813 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
2815 children = SYSCTL_CHILDREN(oid);
2817 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
2818 CTLTYPE_INT | CTLFLAG_RD, &fl->cntxt_id, 0, sysctl_uint16, "I",
2819 "SGE context id of the freelist");
2820 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "padding", CTLFLAG_RD, NULL,
2821 fl_pad ? 1 : 0, "padding enabled");
2822 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "packing", CTLFLAG_RD, NULL,
2823 fl->flags & FL_BUF_PACKING ? 1 : 0, "packing enabled");
2824 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD, &fl->cidx,
2825 0, "consumer index");
2826 if (fl->flags & FL_BUF_PACKING) {
2827 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "rx_offset",
2828 CTLFLAG_RD, &fl->rx_offset, 0, "packing rx offset");
2830 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD, &fl->pidx,
2831 0, "producer index");
2832 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_allocated",
2833 CTLFLAG_RD, &fl->mbuf_allocated, "# of mbuf allocated");
2834 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "mbuf_inlined",
2835 CTLFLAG_RD, &fl->mbuf_inlined, "# of mbuf inlined in clusters");
2836 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_allocated",
2837 CTLFLAG_RD, &fl->cl_allocated, "# of clusters allocated");
2838 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_recycled",
2839 CTLFLAG_RD, &fl->cl_recycled, "# of clusters recycled");
2840 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "cluster_fast_recycled",
2841 CTLFLAG_RD, &fl->cl_fast_recycled, "# of clusters recycled (fast)");
2845 alloc_fwq(struct adapter *sc)
2848 struct sge_iq *fwq = &sc->sge.fwq;
2849 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2850 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2852 init_iq(fwq, sc, 0, 0, FW_IQ_QSIZE);
2853 fwq->flags |= IQ_INTR; /* always */
2854 intr_idx = sc->intr_count > 1 ? 1 : 0;
2855 rc = alloc_iq_fl(sc->port[0], fwq, NULL, intr_idx, -1);
2857 device_printf(sc->dev,
2858 "failed to create firmware event queue: %d\n", rc);
2862 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "fwq", CTLFLAG_RD,
2863 NULL, "firmware event queue");
2864 children = SYSCTL_CHILDREN(oid);
2866 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "abs_id",
2867 CTLTYPE_INT | CTLFLAG_RD, &fwq->abs_id, 0, sysctl_uint16, "I",
2868 "absolute id of the queue");
2869 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cntxt_id",
2870 CTLTYPE_INT | CTLFLAG_RD, &fwq->cntxt_id, 0, sysctl_uint16, "I",
2871 "SGE context id of the queue");
2872 SYSCTL_ADD_PROC(&sc->ctx, children, OID_AUTO, "cidx",
2873 CTLTYPE_INT | CTLFLAG_RD, &fwq->cidx, 0, sysctl_uint16, "I",
2880 free_fwq(struct adapter *sc)
2882 return free_iq_fl(NULL, &sc->sge.fwq, NULL);
2886 alloc_mgmtq(struct adapter *sc)
2889 struct sge_wrq *mgmtq = &sc->sge.mgmtq;
2891 struct sysctl_oid *oid = device_get_sysctl_tree(sc->dev);
2892 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
2894 oid = SYSCTL_ADD_NODE(&sc->ctx, children, OID_AUTO, "mgmtq", CTLFLAG_RD,
2895 NULL, "management queue");
2897 snprintf(name, sizeof(name), "%s mgmtq", device_get_nameunit(sc->dev));
2898 init_eq(&mgmtq->eq, EQ_CTRL, CTRL_EQ_QSIZE, sc->port[0]->tx_chan,
2899 sc->sge.fwq.cntxt_id, name);
2900 rc = alloc_wrq(sc, NULL, mgmtq, oid);
2902 device_printf(sc->dev,
2903 "failed to create management queue: %d\n", rc);
2911 free_mgmtq(struct adapter *sc)
2914 return free_wrq(sc, &sc->sge.mgmtq);
2918 tnl_cong(struct port_info *pi)
2921 if (cong_drop == -1)
2923 else if (cong_drop == 1)
2926 return (pi->rx_chan_map);
2930 alloc_rxq(struct port_info *pi, struct sge_rxq *rxq, int intr_idx, int idx,
2931 struct sysctl_oid *oid)
2934 struct sysctl_oid_list *children;
2937 rc = alloc_iq_fl(pi, &rxq->iq, &rxq->fl, intr_idx, tnl_cong(pi));
2942 * The freelist is just barely above the starvation threshold right now,
2943 * fill it up a bit more.
2946 refill_fl(pi->adapter, &rxq->fl, 128);
2947 FL_UNLOCK(&rxq->fl);
2949 #if defined(INET) || defined(INET6)
2950 rc = tcp_lro_init(&rxq->lro);
2953 rxq->lro.ifp = pi->ifp; /* also indicates LRO init'ed */
2955 if (pi->ifp->if_capenable & IFCAP_LRO)
2956 rxq->iq.flags |= IQ_LRO_ENABLED;
2960 children = SYSCTL_CHILDREN(oid);
2962 snprintf(name, sizeof(name), "%d", idx);
2963 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
2965 children = SYSCTL_CHILDREN(oid);
2967 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id",
2968 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.abs_id, 0, sysctl_uint16, "I",
2969 "absolute id of the queue");
2970 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id",
2971 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cntxt_id, 0, sysctl_uint16, "I",
2972 "SGE context id of the queue");
2973 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
2974 CTLTYPE_INT | CTLFLAG_RD, &rxq->iq.cidx, 0, sysctl_uint16, "I",
2976 #if defined(INET) || defined(INET6)
2977 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_queued", CTLFLAG_RD,
2978 &rxq->lro.lro_queued, 0, NULL);
2979 SYSCTL_ADD_INT(&pi->ctx, children, OID_AUTO, "lro_flushed", CTLFLAG_RD,
2980 &rxq->lro.lro_flushed, 0, NULL);
2982 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "rxcsum", CTLFLAG_RD,
2983 &rxq->rxcsum, "# of times hardware assisted with checksum");
2984 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_extraction",
2985 CTLFLAG_RD, &rxq->vlan_extraction,
2986 "# of times hardware extracted 802.1Q tag");
2988 add_fl_sysctls(&pi->ctx, oid, &rxq->fl);
2994 free_rxq(struct port_info *pi, struct sge_rxq *rxq)
2998 #if defined(INET) || defined(INET6)
3000 tcp_lro_free(&rxq->lro);
3001 rxq->lro.ifp = NULL;
3005 rc = free_iq_fl(pi, &rxq->iq, &rxq->fl);
3007 bzero(rxq, sizeof(*rxq));
3014 alloc_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq,
3015 int intr_idx, int idx, struct sysctl_oid *oid)
3018 struct sysctl_oid_list *children;
3021 rc = alloc_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl, intr_idx,
3026 children = SYSCTL_CHILDREN(oid);
3028 snprintf(name, sizeof(name), "%d", idx);
3029 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3031 children = SYSCTL_CHILDREN(oid);
3033 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "abs_id",
3034 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.abs_id, 0, sysctl_uint16,
3035 "I", "absolute id of the queue");
3036 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cntxt_id",
3037 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cntxt_id, 0, sysctl_uint16,
3038 "I", "SGE context id of the queue");
3039 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
3040 CTLTYPE_INT | CTLFLAG_RD, &ofld_rxq->iq.cidx, 0, sysctl_uint16, "I",
3043 add_fl_sysctls(&pi->ctx, oid, &ofld_rxq->fl);
3049 free_ofld_rxq(struct port_info *pi, struct sge_ofld_rxq *ofld_rxq)
3053 rc = free_iq_fl(pi, &ofld_rxq->iq, &ofld_rxq->fl);
3055 bzero(ofld_rxq, sizeof(*ofld_rxq));
3063 alloc_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq, int intr_idx,
3064 int idx, struct sysctl_oid *oid)
3067 struct sysctl_oid_list *children;
3068 struct sysctl_ctx_list *ctx;
3071 struct adapter *sc = pi->adapter;
3072 struct netmap_adapter *na = NA(pi->nm_ifp);
3076 len = pi->qsize_rxq * IQ_ESIZE;
3077 rc = alloc_ring(sc, len, &nm_rxq->iq_desc_tag, &nm_rxq->iq_desc_map,
3078 &nm_rxq->iq_ba, (void **)&nm_rxq->iq_desc);
3082 len = na->num_rx_desc * EQ_ESIZE + spg_len;
3083 rc = alloc_ring(sc, len, &nm_rxq->fl_desc_tag, &nm_rxq->fl_desc_map,
3084 &nm_rxq->fl_ba, (void **)&nm_rxq->fl_desc);
3090 nm_rxq->iq_cidx = 0;
3091 nm_rxq->iq_sidx = pi->qsize_rxq - spg_len / IQ_ESIZE;
3092 nm_rxq->iq_gen = F_RSPD_GEN;
3093 nm_rxq->fl_pidx = nm_rxq->fl_cidx = 0;
3094 nm_rxq->fl_sidx = na->num_rx_desc;
3095 nm_rxq->intr_idx = intr_idx;
3098 children = SYSCTL_CHILDREN(oid);
3100 snprintf(name, sizeof(name), "%d", idx);
3101 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, name, CTLFLAG_RD, NULL,
3103 children = SYSCTL_CHILDREN(oid);
3105 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "abs_id",
3106 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_abs_id, 0, sysctl_uint16,
3107 "I", "absolute id of the queue");
3108 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3109 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cntxt_id, 0, sysctl_uint16,
3110 "I", "SGE context id of the queue");
3111 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3112 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->iq_cidx, 0, sysctl_uint16, "I",
3115 children = SYSCTL_CHILDREN(oid);
3116 oid = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "fl", CTLFLAG_RD, NULL,
3118 children = SYSCTL_CHILDREN(oid);
3120 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cntxt_id",
3121 CTLTYPE_INT | CTLFLAG_RD, &nm_rxq->fl_cntxt_id, 0, sysctl_uint16,
3122 "I", "SGE context id of the freelist");
3123 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cidx", CTLFLAG_RD,
3124 &nm_rxq->fl_cidx, 0, "consumer index");
3125 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "pidx", CTLFLAG_RD,
3126 &nm_rxq->fl_pidx, 0, "producer index");
3133 free_nm_rxq(struct port_info *pi, struct sge_nm_rxq *nm_rxq)
3135 struct adapter *sc = pi->adapter;
3137 free_ring(sc, nm_rxq->iq_desc_tag, nm_rxq->iq_desc_map, nm_rxq->iq_ba,
3139 free_ring(sc, nm_rxq->fl_desc_tag, nm_rxq->fl_desc_map, nm_rxq->fl_ba,
3146 alloc_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq, int iqidx, int idx,
3147 struct sysctl_oid *oid)
3151 struct adapter *sc = pi->adapter;
3152 struct netmap_adapter *na = NA(pi->nm_ifp);
3154 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3156 len = na->num_tx_desc * EQ_ESIZE + spg_len;
3157 rc = alloc_ring(sc, len, &nm_txq->desc_tag, &nm_txq->desc_map,
3158 &nm_txq->ba, (void **)&nm_txq->desc);
3162 nm_txq->pidx = nm_txq->cidx = 0;
3163 nm_txq->sidx = na->num_tx_desc;
3165 nm_txq->iqidx = iqidx;
3166 nm_txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3167 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf));
3169 snprintf(name, sizeof(name), "%d", idx);
3170 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3171 NULL, "netmap tx queue");
3172 children = SYSCTL_CHILDREN(oid);
3174 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3175 &nm_txq->cntxt_id, 0, "SGE context id of the queue");
3176 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
3177 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->cidx, 0, sysctl_uint16, "I",
3179 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx",
3180 CTLTYPE_INT | CTLFLAG_RD, &nm_txq->pidx, 0, sysctl_uint16, "I",
3187 free_nm_txq(struct port_info *pi, struct sge_nm_txq *nm_txq)
3189 struct adapter *sc = pi->adapter;
3191 free_ring(sc, nm_txq->desc_tag, nm_txq->desc_map, nm_txq->ba,
3199 ctrl_eq_alloc(struct adapter *sc, struct sge_eq *eq)
3202 struct fw_eq_ctrl_cmd c;
3203 int qsize = eq->sidx + spg_len / EQ_ESIZE;
3205 bzero(&c, sizeof(c));
3207 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_CTRL_CMD) | F_FW_CMD_REQUEST |
3208 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_CTRL_CMD_PFN(sc->pf) |
3209 V_FW_EQ_CTRL_CMD_VFN(0));
3210 c.alloc_to_len16 = htobe32(F_FW_EQ_CTRL_CMD_ALLOC |
3211 F_FW_EQ_CTRL_CMD_EQSTART | FW_LEN16(c));
3212 c.cmpliqid_eqid = htonl(V_FW_EQ_CTRL_CMD_CMPLIQID(eq->iqid));
3213 c.physeqid_pkd = htobe32(0);
3214 c.fetchszm_to_iqid =
3215 htobe32(V_FW_EQ_CTRL_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3216 V_FW_EQ_CTRL_CMD_PCIECHN(eq->tx_chan) |
3217 F_FW_EQ_CTRL_CMD_FETCHRO | V_FW_EQ_CTRL_CMD_IQID(eq->iqid));
3219 htobe32(V_FW_EQ_CTRL_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3220 V_FW_EQ_CTRL_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3221 V_FW_EQ_CTRL_CMD_EQSIZE(qsize));
3222 c.eqaddr = htobe64(eq->ba);
3224 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3226 device_printf(sc->dev,
3227 "failed to create control queue %d: %d\n", eq->tx_chan, rc);
3230 eq->flags |= EQ_ALLOCATED;
3232 eq->cntxt_id = G_FW_EQ_CTRL_CMD_EQID(be32toh(c.cmpliqid_eqid));
3233 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3234 if (cntxt_id >= sc->sge.neq)
3235 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3236 cntxt_id, sc->sge.neq - 1);
3237 sc->sge.eqmap[cntxt_id] = eq;
3243 eth_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
3246 struct fw_eq_eth_cmd c;
3247 int qsize = eq->sidx + spg_len / EQ_ESIZE;
3249 bzero(&c, sizeof(c));
3251 c.op_to_vfn = htobe32(V_FW_CMD_OP(FW_EQ_ETH_CMD) | F_FW_CMD_REQUEST |
3252 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_ETH_CMD_PFN(sc->pf) |
3253 V_FW_EQ_ETH_CMD_VFN(0));
3254 c.alloc_to_len16 = htobe32(F_FW_EQ_ETH_CMD_ALLOC |
3255 F_FW_EQ_ETH_CMD_EQSTART | FW_LEN16(c));
3256 c.autoequiqe_to_viid = htobe32(F_FW_EQ_ETH_CMD_AUTOEQUIQE |
3257 F_FW_EQ_ETH_CMD_AUTOEQUEQE | V_FW_EQ_ETH_CMD_VIID(pi->viid));
3258 c.fetchszm_to_iqid =
3259 htobe32(V_FW_EQ_ETH_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3260 V_FW_EQ_ETH_CMD_PCIECHN(eq->tx_chan) | F_FW_EQ_ETH_CMD_FETCHRO |
3261 V_FW_EQ_ETH_CMD_IQID(eq->iqid));
3262 c.dcaen_to_eqsize = htobe32(V_FW_EQ_ETH_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3263 V_FW_EQ_ETH_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3264 V_FW_EQ_ETH_CMD_EQSIZE(qsize));
3265 c.eqaddr = htobe64(eq->ba);
3267 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3269 device_printf(pi->dev,
3270 "failed to create Ethernet egress queue: %d\n", rc);
3273 eq->flags |= EQ_ALLOCATED;
3275 eq->cntxt_id = G_FW_EQ_ETH_CMD_EQID(be32toh(c.eqid_pkd));
3276 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3277 if (cntxt_id >= sc->sge.neq)
3278 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3279 cntxt_id, sc->sge.neq - 1);
3280 sc->sge.eqmap[cntxt_id] = eq;
3287 ofld_eq_alloc(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
3290 struct fw_eq_ofld_cmd c;
3291 int qsize = eq->sidx + spg_len / EQ_ESIZE;
3293 bzero(&c, sizeof(c));
3295 c.op_to_vfn = htonl(V_FW_CMD_OP(FW_EQ_OFLD_CMD) | F_FW_CMD_REQUEST |
3296 F_FW_CMD_WRITE | F_FW_CMD_EXEC | V_FW_EQ_OFLD_CMD_PFN(sc->pf) |
3297 V_FW_EQ_OFLD_CMD_VFN(0));
3298 c.alloc_to_len16 = htonl(F_FW_EQ_OFLD_CMD_ALLOC |
3299 F_FW_EQ_OFLD_CMD_EQSTART | FW_LEN16(c));
3300 c.fetchszm_to_iqid =
3301 htonl(V_FW_EQ_OFLD_CMD_HOSTFCMODE(X_HOSTFCMODE_NONE) |
3302 V_FW_EQ_OFLD_CMD_PCIECHN(eq->tx_chan) |
3303 F_FW_EQ_OFLD_CMD_FETCHRO | V_FW_EQ_OFLD_CMD_IQID(eq->iqid));
3305 htobe32(V_FW_EQ_OFLD_CMD_FBMIN(X_FETCHBURSTMIN_64B) |
3306 V_FW_EQ_OFLD_CMD_FBMAX(X_FETCHBURSTMAX_512B) |
3307 V_FW_EQ_OFLD_CMD_EQSIZE(qsize));
3308 c.eqaddr = htobe64(eq->ba);
3310 rc = -t4_wr_mbox(sc, sc->mbox, &c, sizeof(c), &c);
3312 device_printf(pi->dev,
3313 "failed to create egress queue for TCP offload: %d\n", rc);
3316 eq->flags |= EQ_ALLOCATED;
3318 eq->cntxt_id = G_FW_EQ_OFLD_CMD_EQID(be32toh(c.eqid_pkd));
3319 cntxt_id = eq->cntxt_id - sc->sge.eq_start;
3320 if (cntxt_id >= sc->sge.neq)
3321 panic("%s: eq->cntxt_id (%d) more than the max (%d)", __func__,
3322 cntxt_id, sc->sge.neq - 1);
3323 sc->sge.eqmap[cntxt_id] = eq;
3330 alloc_eq(struct adapter *sc, struct port_info *pi, struct sge_eq *eq)
3335 mtx_init(&eq->eq_lock, eq->lockname, NULL, MTX_DEF);
3337 qsize = eq->sidx + spg_len / EQ_ESIZE;
3338 len = qsize * EQ_ESIZE;
3339 rc = alloc_ring(sc, len, &eq->desc_tag, &eq->desc_map,
3340 &eq->ba, (void **)&eq->desc);
3344 eq->pidx = eq->cidx = 0;
3345 eq->equeqidx = eq->dbidx = 0;
3346 eq->doorbells = sc->doorbells;
3348 switch (eq->flags & EQ_TYPEMASK) {
3350 rc = ctrl_eq_alloc(sc, eq);
3354 rc = eth_eq_alloc(sc, pi, eq);
3359 rc = ofld_eq_alloc(sc, pi, eq);
3364 panic("%s: invalid eq type %d.", __func__,
3365 eq->flags & EQ_TYPEMASK);
3368 device_printf(sc->dev,
3369 "failed to allocate egress queue(%d): %d\n",
3370 eq->flags & EQ_TYPEMASK, rc);
3373 if (isset(&eq->doorbells, DOORBELL_UDB) ||
3374 isset(&eq->doorbells, DOORBELL_UDBWC) ||
3375 isset(&eq->doorbells, DOORBELL_WCWR)) {
3376 uint32_t s_qpp = sc->sge.eq_s_qpp;
3377 uint32_t mask = (1 << s_qpp) - 1;
3378 volatile uint8_t *udb;
3380 udb = sc->udbs_base + UDBS_DB_OFFSET;
3381 udb += (eq->cntxt_id >> s_qpp) << PAGE_SHIFT; /* pg offset */
3382 eq->udb_qid = eq->cntxt_id & mask; /* id in page */
3383 if (eq->udb_qid >= PAGE_SIZE / UDBS_SEG_SIZE)
3384 clrbit(&eq->doorbells, DOORBELL_WCWR);
3386 udb += eq->udb_qid << UDBS_SEG_SHIFT; /* seg offset */
3389 eq->udb = (volatile void *)udb;
3396 free_eq(struct adapter *sc, struct sge_eq *eq)
3400 if (eq->flags & EQ_ALLOCATED) {
3401 switch (eq->flags & EQ_TYPEMASK) {
3403 rc = -t4_ctrl_eq_free(sc, sc->mbox, sc->pf, 0,
3408 rc = -t4_eth_eq_free(sc, sc->mbox, sc->pf, 0,
3414 rc = -t4_ofld_eq_free(sc, sc->mbox, sc->pf, 0,
3420 panic("%s: invalid eq type %d.", __func__,
3421 eq->flags & EQ_TYPEMASK);
3424 device_printf(sc->dev,
3425 "failed to free egress queue (%d): %d\n",
3426 eq->flags & EQ_TYPEMASK, rc);
3429 eq->flags &= ~EQ_ALLOCATED;
3432 free_ring(sc, eq->desc_tag, eq->desc_map, eq->ba, eq->desc);
3434 if (mtx_initialized(&eq->eq_lock))
3435 mtx_destroy(&eq->eq_lock);
3437 bzero(eq, sizeof(*eq));
3442 alloc_wrq(struct adapter *sc, struct port_info *pi, struct sge_wrq *wrq,
3443 struct sysctl_oid *oid)
3446 struct sysctl_ctx_list *ctx = pi ? &pi->ctx : &sc->ctx;
3447 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3449 rc = alloc_eq(sc, pi, &wrq->eq);
3454 TASK_INIT(&wrq->wrq_tx_task, 0, wrq_tx_drain, wrq);
3455 TAILQ_INIT(&wrq->incomplete_wrs);
3456 STAILQ_INIT(&wrq->wr_list);
3457 wrq->nwr_pending = 0;
3458 wrq->ndesc_needed = 0;
3460 SYSCTL_ADD_UINT(ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3461 &wrq->eq.cntxt_id, 0, "SGE context id of the queue");
3462 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "cidx",
3463 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.cidx, 0, sysctl_uint16, "I",
3465 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "pidx",
3466 CTLTYPE_INT | CTLFLAG_RD, &wrq->eq.pidx, 0, sysctl_uint16, "I",
3468 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_direct", CTLFLAG_RD,
3469 &wrq->tx_wrs_direct, "# of work requests (direct)");
3470 SYSCTL_ADD_UQUAD(ctx, children, OID_AUTO, "tx_wrs_copied", CTLFLAG_RD,
3471 &wrq->tx_wrs_copied, "# of work requests (copied)");
3477 free_wrq(struct adapter *sc, struct sge_wrq *wrq)
3481 rc = free_eq(sc, &wrq->eq);
3485 bzero(wrq, sizeof(*wrq));
3490 alloc_txq(struct port_info *pi, struct sge_txq *txq, int idx,
3491 struct sysctl_oid *oid)
3494 struct adapter *sc = pi->adapter;
3495 struct sge_eq *eq = &txq->eq;
3497 struct sysctl_oid_list *children = SYSCTL_CHILDREN(oid);
3499 rc = mp_ring_alloc(&txq->r, eq->sidx, txq, eth_tx, can_resume_eth_tx,
3502 device_printf(sc->dev, "failed to allocate mp_ring: %d\n", rc);
3506 rc = alloc_eq(sc, pi, eq);
3508 mp_ring_free(txq->r);
3513 /* Can't fail after this point. */
3515 TASK_INIT(&txq->tx_reclaim_task, 0, tx_reclaim, eq);
3517 txq->gl = sglist_alloc(TX_SGL_SEGS, M_WAITOK);
3518 txq->cpl_ctrl0 = htobe32(V_TXPKT_OPCODE(CPL_TX_PKT) |
3519 V_TXPKT_INTF(pi->tx_chan) | V_TXPKT_PF(sc->pf));
3520 txq->sdesc = malloc(eq->sidx * sizeof(struct tx_sdesc), M_CXGBE,
3523 snprintf(name, sizeof(name), "%d", idx);
3524 oid = SYSCTL_ADD_NODE(&pi->ctx, children, OID_AUTO, name, CTLFLAG_RD,
3526 children = SYSCTL_CHILDREN(oid);
3528 SYSCTL_ADD_UINT(&pi->ctx, children, OID_AUTO, "cntxt_id", CTLFLAG_RD,
3529 &eq->cntxt_id, 0, "SGE context id of the queue");
3530 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "cidx",
3531 CTLTYPE_INT | CTLFLAG_RD, &eq->cidx, 0, sysctl_uint16, "I",
3533 SYSCTL_ADD_PROC(&pi->ctx, children, OID_AUTO, "pidx",
3534 CTLTYPE_INT | CTLFLAG_RD, &eq->pidx, 0, sysctl_uint16, "I",
3537 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txcsum", CTLFLAG_RD,
3538 &txq->txcsum, "# of times hardware assisted with checksum");
3539 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "vlan_insertion",
3540 CTLFLAG_RD, &txq->vlan_insertion,
3541 "# of times hardware inserted 802.1Q tag");
3542 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "tso_wrs", CTLFLAG_RD,
3543 &txq->tso_wrs, "# of TSO work requests");
3544 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "imm_wrs", CTLFLAG_RD,
3545 &txq->imm_wrs, "# of work requests with immediate data");
3546 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "sgl_wrs", CTLFLAG_RD,
3547 &txq->sgl_wrs, "# of work requests with direct SGL");
3548 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkt_wrs", CTLFLAG_RD,
3549 &txq->txpkt_wrs, "# of txpkt work requests (one pkt/WR)");
3550 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts0_wrs",
3551 CTLFLAG_RD, &txq->txpkts0_wrs,
3552 "# of txpkts (type 0) work requests");
3553 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts1_wrs",
3554 CTLFLAG_RD, &txq->txpkts1_wrs,
3555 "# of txpkts (type 1) work requests");
3556 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts0_pkts",
3557 CTLFLAG_RD, &txq->txpkts0_pkts,
3558 "# of frames tx'd using type0 txpkts work requests");
3559 SYSCTL_ADD_UQUAD(&pi->ctx, children, OID_AUTO, "txpkts1_pkts",
3560 CTLFLAG_RD, &txq->txpkts1_pkts,
3561 "# of frames tx'd using type1 txpkts work requests");
3563 SYSCTL_ADD_COUNTER_U64(&pi->ctx, children, OID_AUTO, "r_enqueues",
3564 CTLFLAG_RD, &txq->r->enqueues,
3565 "# of enqueues to the mp_ring for this queue");
3566 SYSCTL_ADD_COUNTER_U64(&pi->ctx, children, OID_AUTO, "r_drops",
3567 CTLFLAG_RD, &txq->r->drops,
3568 "# of drops in the mp_ring for this queue");
3569 SYSCTL_ADD_COUNTER_U64(&pi->ctx, children, OID_AUTO, "r_starts",
3570 CTLFLAG_RD, &txq->r->starts,
3571 "# of normal consumer starts in the mp_ring for this queue");
3572 SYSCTL_ADD_COUNTER_U64(&pi->ctx, children, OID_AUTO, "r_stalls",
3573 CTLFLAG_RD, &txq->r->stalls,
3574 "# of consumer stalls in the mp_ring for this queue");
3575 SYSCTL_ADD_COUNTER_U64(&pi->ctx, children, OID_AUTO, "r_restarts",
3576 CTLFLAG_RD, &txq->r->restarts,
3577 "# of consumer restarts in the mp_ring for this queue");
3578 SYSCTL_ADD_COUNTER_U64(&pi->ctx, children, OID_AUTO, "r_abdications",
3579 CTLFLAG_RD, &txq->r->abdications,
3580 "# of consumer abdications in the mp_ring for this queue");
3586 free_txq(struct port_info *pi, struct sge_txq *txq)
3589 struct adapter *sc = pi->adapter;
3590 struct sge_eq *eq = &txq->eq;
3592 rc = free_eq(sc, eq);
3596 sglist_free(txq->gl);
3597 free(txq->sdesc, M_CXGBE);
3598 mp_ring_free(txq->r);
3600 bzero(txq, sizeof(*txq));
3605 oneseg_dma_callback(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3607 bus_addr_t *ba = arg;
3610 ("%s meant for single segment mappings only.", __func__));
3612 *ba = error ? 0 : segs->ds_addr;
3616 ring_fl_db(struct adapter *sc, struct sge_fl *fl)
3620 n = IDXDIFF(fl->pidx / 8, fl->dbidx, fl->sidx);
3624 v = fl->dbval | V_PIDX(n);
3626 *fl->udb = htole32(v);
3628 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL), v);
3629 IDXINCR(fl->dbidx, n, fl->sidx);
3633 * Fills up the freelist by allocating upto 'n' buffers. Buffers that are
3634 * recycled do not count towards this allocation budget.
3636 * Returns non-zero to indicate that this freelist should be added to the list
3637 * of starving freelists.
3640 refill_fl(struct adapter *sc, struct sge_fl *fl, int n)
3643 struct fl_sdesc *sd;
3646 struct cluster_layout *cll;
3647 struct sw_zone_info *swz;
3648 struct cluster_metadata *clm;
3650 uint16_t hw_cidx = fl->hw_cidx; /* stable snapshot */
3652 FL_LOCK_ASSERT_OWNED(fl);
3655 * We always stop at the begining of the hardware descriptor that's just
3656 * before the one with the hw cidx. This is to avoid hw pidx = hw cidx,
3657 * which would mean an empty freelist to the chip.
3659 max_pidx = __predict_false(hw_cidx == 0) ? fl->sidx - 1 : hw_cidx - 1;
3660 if (fl->pidx == max_pidx * 8)
3663 d = &fl->desc[fl->pidx];
3664 sd = &fl->sdesc[fl->pidx];
3665 cll = &fl->cll_def; /* default layout */
3666 swz = &sc->sge.sw_zone_info[cll->zidx];
3670 if (sd->cl != NULL) {
3672 if (sd->nmbuf == 0) {
3674 * Fast recycle without involving any atomics on
3675 * the cluster's metadata (if the cluster has
3676 * metadata). This happens when all frames
3677 * received in the cluster were small enough to
3678 * fit within a single mbuf each.
3680 fl->cl_fast_recycled++;
3682 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3684 MPASS(clm->refcount == 1);
3690 * Cluster is guaranteed to have metadata. Clusters
3691 * without metadata always take the fast recycle path
3692 * when they're recycled.
3694 clm = cl_metadata(sc, fl, &sd->cll, sd->cl);
3697 if (atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3699 counter_u64_add(extfree_rels, 1);
3702 sd->cl = NULL; /* gave up my reference */
3704 MPASS(sd->cl == NULL);
3706 cl = uma_zalloc(swz->zone, M_NOWAIT);
3707 if (__predict_false(cl == NULL)) {
3708 if (cll == &fl->cll_alt || fl->cll_alt.zidx == -1 ||
3709 fl->cll_def.zidx == fl->cll_alt.zidx)
3712 /* fall back to the safe zone */
3714 swz = &sc->sge.sw_zone_info[cll->zidx];
3720 pa = pmap_kextract((vm_offset_t)cl);
3724 *d = htobe64(pa | cll->hwidx);
3725 clm = cl_metadata(sc, fl, cll, cl);
3737 if (__predict_false(++fl->pidx % 8 == 0)) {
3738 uint16_t pidx = fl->pidx / 8;
3740 if (__predict_false(pidx == fl->sidx)) {
3746 if (pidx == max_pidx)
3749 if (IDXDIFF(pidx, fl->dbidx, fl->sidx) >= 4)
3754 if (fl->pidx / 8 != fl->dbidx)
3757 return (FL_RUNNING_LOW(fl) && !(fl->flags & FL_STARVING));
3761 * Attempt to refill all starving freelists.
3764 refill_sfl(void *arg)
3766 struct adapter *sc = arg;
3767 struct sge_fl *fl, *fl_temp;
3769 mtx_lock(&sc->sfl_lock);
3770 TAILQ_FOREACH_SAFE(fl, &sc->sfl, link, fl_temp) {
3772 refill_fl(sc, fl, 64);
3773 if (FL_NOT_RUNNING_LOW(fl) || fl->flags & FL_DOOMED) {
3774 TAILQ_REMOVE(&sc->sfl, fl, link);
3775 fl->flags &= ~FL_STARVING;
3780 if (!TAILQ_EMPTY(&sc->sfl))
3781 callout_schedule(&sc->sfl_callout, hz / 5);
3782 mtx_unlock(&sc->sfl_lock);
3786 alloc_fl_sdesc(struct sge_fl *fl)
3789 fl->sdesc = malloc(fl->sidx * 8 * sizeof(struct fl_sdesc), M_CXGBE,
3796 free_fl_sdesc(struct adapter *sc, struct sge_fl *fl)
3798 struct fl_sdesc *sd;
3799 struct cluster_metadata *clm;
3800 struct cluster_layout *cll;
3804 for (i = 0; i < fl->sidx * 8; i++, sd++) {
3809 clm = cl_metadata(sc, fl, cll, sd->cl);
3811 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3812 else if (clm && atomic_fetchadd_int(&clm->refcount, -1) == 1) {
3813 uma_zfree(sc->sge.sw_zone_info[cll->zidx].zone, sd->cl);
3814 counter_u64_add(extfree_rels, 1);
3819 free(fl->sdesc, M_CXGBE);
3824 get_pkt_gl(struct mbuf *m, struct sglist *gl)
3831 rc = sglist_append_mbuf(gl, m);
3832 if (__predict_false(rc != 0)) {
3833 panic("%s: mbuf %p (%d segs) was vetted earlier but now fails "
3834 "with %d.", __func__, m, mbuf_nsegs(m), rc);
3837 KASSERT(gl->sg_nseg == mbuf_nsegs(m),
3838 ("%s: nsegs changed for mbuf %p from %d to %d", __func__, m,
3839 mbuf_nsegs(m), gl->sg_nseg));
3840 KASSERT(gl->sg_nseg > 0 &&
3841 gl->sg_nseg <= (needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS),
3842 ("%s: %d segments, should have been 1 <= nsegs <= %d", __func__,
3843 gl->sg_nseg, needs_tso(m) ? TX_SGL_SEGS_TSO : TX_SGL_SEGS));
3847 * len16 for a txpkt WR with a GL. Includes the firmware work request header.
3850 txpkt_len16(u_int nsegs, u_int tso)
3856 nsegs--; /* first segment is part of ulptx_sgl */
3857 n = sizeof(struct fw_eth_tx_pkt_wr) + sizeof(struct cpl_tx_pkt_core) +
3858 sizeof(struct ulptx_sgl) + 8 * ((3 * nsegs) / 2 + (nsegs & 1));
3860 n += sizeof(struct cpl_tx_pkt_lso_core);
3862 return (howmany(n, 16));
3866 * len16 for a txpkts type 0 WR with a GL. Does not include the firmware work
3870 txpkts0_len16(u_int nsegs)
3876 nsegs--; /* first segment is part of ulptx_sgl */
3877 n = sizeof(struct ulp_txpkt) + sizeof(struct ulptx_idata) +
3878 sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl) +
3879 8 * ((3 * nsegs) / 2 + (nsegs & 1));
3881 return (howmany(n, 16));
3885 * len16 for a txpkts type 1 WR with a GL. Does not include the firmware work
3893 n = sizeof(struct cpl_tx_pkt_core) + sizeof(struct ulptx_sgl);
3895 return (howmany(n, 16));
3899 imm_payload(u_int ndesc)
3903 n = ndesc * EQ_ESIZE - sizeof(struct fw_eth_tx_pkt_wr) -
3904 sizeof(struct cpl_tx_pkt_core);
3910 * Write a txpkt WR for this packet to the hardware descriptors, update the
3911 * software descriptor, and advance the pidx. It is guaranteed that enough
3912 * descriptors are available.
3914 * The return value is the # of hardware descriptors used.
3917 write_txpkt_wr(struct sge_txq *txq, struct fw_eth_tx_pkt_wr *wr,
3918 struct mbuf *m0, u_int available)
3920 struct sge_eq *eq = &txq->eq;
3921 struct tx_sdesc *txsd;
3922 struct cpl_tx_pkt_core *cpl;
3923 uint32_t ctrl; /* used in many unrelated places */
3925 int len16, ndesc, pktlen, nsegs;
3928 TXQ_LOCK_ASSERT_OWNED(txq);
3930 MPASS(available > 0 && available < eq->sidx);
3932 len16 = mbuf_len16(m0);
3933 nsegs = mbuf_nsegs(m0);
3934 pktlen = m0->m_pkthdr.len;
3935 ctrl = sizeof(struct cpl_tx_pkt_core);
3937 ctrl += sizeof(struct cpl_tx_pkt_lso_core);
3938 else if (pktlen <= imm_payload(2) && available >= 2) {
3939 /* Immediate data. Recalculate len16 and set nsegs to 0. */
3941 len16 = howmany(sizeof(struct fw_eth_tx_pkt_wr) +
3942 sizeof(struct cpl_tx_pkt_core) + pktlen, 16);
3945 ndesc = howmany(len16, EQ_ESIZE / 16);
3946 MPASS(ndesc <= available);
3948 /* Firmware work request header */
3949 MPASS(wr == (void *)&eq->desc[eq->pidx]);
3950 wr->op_immdlen = htobe32(V_FW_WR_OP(FW_ETH_TX_PKT_WR) |
3951 V_FW_ETH_TX_PKT_WR_IMMDLEN(ctrl));
3953 ctrl = V_FW_WR_LEN16(len16);
3954 wr->equiq_to_len16 = htobe32(ctrl);
3957 if (needs_tso(m0)) {
3958 struct cpl_tx_pkt_lso_core *lso = (void *)(wr + 1);
3960 KASSERT(m0->m_pkthdr.l2hlen > 0 && m0->m_pkthdr.l3hlen > 0 &&
3961 m0->m_pkthdr.l4hlen > 0,
3962 ("%s: mbuf %p needs TSO but missing header lengths",
3965 ctrl = V_LSO_OPCODE(CPL_TX_PKT_LSO) | F_LSO_FIRST_SLICE |
3966 F_LSO_LAST_SLICE | V_LSO_IPHDR_LEN(m0->m_pkthdr.l3hlen >> 2)
3967 | V_LSO_TCPHDR_LEN(m0->m_pkthdr.l4hlen >> 2);
3968 if (m0->m_pkthdr.l2hlen == sizeof(struct ether_vlan_header))
3969 ctrl |= V_LSO_ETHHDR_LEN(1);
3970 if (m0->m_pkthdr.l3hlen == sizeof(struct ip6_hdr))
3973 lso->lso_ctrl = htobe32(ctrl);
3974 lso->ipid_ofst = htobe16(0);
3975 lso->mss = htobe16(m0->m_pkthdr.tso_segsz);
3976 lso->seqno_offset = htobe32(0);
3977 lso->len = htobe32(pktlen);
3979 cpl = (void *)(lso + 1);
3983 cpl = (void *)(wr + 1);
3985 /* Checksum offload */
3987 if (needs_l3_csum(m0) == 0)
3988 ctrl1 |= F_TXPKT_IPCSUM_DIS;
3989 if (needs_l4_csum(m0) == 0)
3990 ctrl1 |= F_TXPKT_L4CSUM_DIS;
3991 if (m0->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
3992 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
3993 txq->txcsum++; /* some hardware assistance provided */
3995 /* VLAN tag insertion */
3996 if (needs_vlan_insertion(m0)) {
3997 ctrl1 |= F_TXPKT_VLAN_VLD | V_TXPKT_VLAN(m0->m_pkthdr.ether_vtag);
3998 txq->vlan_insertion++;
4002 cpl->ctrl0 = txq->cpl_ctrl0;
4004 cpl->len = htobe16(pktlen);
4005 cpl->ctrl1 = htobe64(ctrl1);
4008 dst = (void *)(cpl + 1);
4011 write_gl_to_txd(txq, m0, &dst, eq->sidx - ndesc < eq->pidx);
4016 for (m = m0; m != NULL; m = m->m_next) {
4017 copy_to_txd(eq, mtod(m, caddr_t), &dst, m->m_len);
4023 KASSERT(pktlen == 0, ("%s: %d bytes left.", __func__, pktlen));
4030 txsd = &txq->sdesc[eq->pidx];
4032 txsd->desc_used = ndesc;
4038 try_txpkts(struct mbuf *m, struct mbuf *n, struct txpkts *txp, u_int available)
4040 u_int needed, nsegs1, nsegs2, l1, l2;
4042 if (cannot_use_txpkts(m) || cannot_use_txpkts(n))
4045 nsegs1 = mbuf_nsegs(m);
4046 nsegs2 = mbuf_nsegs(n);
4047 if (nsegs1 + nsegs2 == 2) {
4049 l1 = l2 = txpkts1_len16();
4052 l1 = txpkts0_len16(nsegs1);
4053 l2 = txpkts0_len16(nsegs2);
4055 txp->len16 = howmany(sizeof(struct fw_eth_tx_pkts_wr), 16) + l1 + l2;
4056 needed = howmany(txp->len16, EQ_ESIZE / 16);
4057 if (needed > SGE_MAX_WR_NDESC || needed > available)
4060 txp->plen = m->m_pkthdr.len + n->m_pkthdr.len;
4061 if (txp->plen > 65535)
4065 set_mbuf_len16(m, l1);
4066 set_mbuf_len16(n, l2);
4072 add_to_txpkts(struct mbuf *m, struct txpkts *txp, u_int available)
4074 u_int plen, len16, needed, nsegs;
4076 MPASS(txp->wr_type == 0 || txp->wr_type == 1);
4078 nsegs = mbuf_nsegs(m);
4079 if (needs_tso(m) || (txp->wr_type == 1 && nsegs != 1))
4082 plen = txp->plen + m->m_pkthdr.len;
4086 if (txp->wr_type == 0)
4087 len16 = txpkts0_len16(nsegs);
4089 len16 = txpkts1_len16();
4090 needed = howmany(txp->len16 + len16, EQ_ESIZE / 16);
4091 if (needed > SGE_MAX_WR_NDESC || needed > available)
4096 txp->len16 += len16;
4097 set_mbuf_len16(m, len16);
4103 * Write a txpkts WR for the packets in txp to the hardware descriptors, update
4104 * the software descriptor, and advance the pidx. It is guaranteed that enough
4105 * descriptors are available.
4107 * The return value is the # of hardware descriptors used.
4110 write_txpkts_wr(struct sge_txq *txq, struct fw_eth_tx_pkts_wr *wr,
4111 struct mbuf *m0, const struct txpkts *txp, u_int available)
4113 struct sge_eq *eq = &txq->eq;
4114 struct tx_sdesc *txsd;
4115 struct cpl_tx_pkt_core *cpl;
4118 int ndesc, checkwrap;
4122 TXQ_LOCK_ASSERT_OWNED(txq);
4123 MPASS(txp->npkt > 0);
4124 MPASS(txp->plen < 65536);
4126 MPASS(m0->m_nextpkt != NULL);
4127 MPASS(txp->len16 <= howmany(SGE_MAX_WR_LEN, 16));
4128 MPASS(available > 0 && available < eq->sidx);
4130 ndesc = howmany(txp->len16, EQ_ESIZE / 16);
4131 MPASS(ndesc <= available);
4133 MPASS(wr == (void *)&eq->desc[eq->pidx]);
4134 wr->op_pkd = htobe32(V_FW_WR_OP(FW_ETH_TX_PKTS_WR));
4135 ctrl = V_FW_WR_LEN16(txp->len16);
4136 wr->equiq_to_len16 = htobe32(ctrl);
4137 wr->plen = htobe16(txp->plen);
4138 wr->npkt = txp->npkt;
4140 wr->type = txp->wr_type;
4144 * At this point we are 16B into a hardware descriptor. If checkwrap is
4145 * set then we know the WR is going to wrap around somewhere. We'll
4146 * check for that at appropriate points.
4148 checkwrap = eq->sidx - ndesc < eq->pidx;
4149 for (m = m0; m != NULL; m = m->m_nextpkt) {
4150 if (txp->wr_type == 0) {
4151 struct ulp_txpkt *ulpmc;
4152 struct ulptx_idata *ulpsc;
4154 /* ULP master command */
4156 ulpmc->cmd_dest = htobe32(V_ULPTX_CMD(ULP_TX_PKT) |
4157 V_ULP_TXPKT_DEST(0) | V_ULP_TXPKT_FID(eq->iqid));
4158 ulpmc->len = htobe32(mbuf_len16(m));
4160 /* ULP subcommand */
4161 ulpsc = (void *)(ulpmc + 1);
4162 ulpsc->cmd_more = htobe32(V_ULPTX_CMD(ULP_TX_SC_IMM) |
4164 ulpsc->len = htobe32(sizeof(struct cpl_tx_pkt_core));
4166 cpl = (void *)(ulpsc + 1);
4168 (uintptr_t)cpl == (uintptr_t)&eq->desc[eq->sidx])
4169 cpl = (void *)&eq->desc[0];
4170 txq->txpkts0_pkts += txp->npkt;
4174 txq->txpkts1_pkts += txp->npkt;
4178 /* Checksum offload */
4180 if (needs_l3_csum(m) == 0)
4181 ctrl1 |= F_TXPKT_IPCSUM_DIS;
4182 if (needs_l4_csum(m) == 0)
4183 ctrl1 |= F_TXPKT_L4CSUM_DIS;
4184 if (m->m_pkthdr.csum_flags & (CSUM_IP | CSUM_TCP | CSUM_UDP |
4185 CSUM_UDP_IPV6 | CSUM_TCP_IPV6 | CSUM_TSO))
4186 txq->txcsum++; /* some hardware assistance provided */
4188 /* VLAN tag insertion */
4189 if (needs_vlan_insertion(m)) {
4190 ctrl1 |= F_TXPKT_VLAN_VLD |
4191 V_TXPKT_VLAN(m->m_pkthdr.ether_vtag);
4192 txq->vlan_insertion++;
4196 cpl->ctrl0 = txq->cpl_ctrl0;
4198 cpl->len = htobe16(m->m_pkthdr.len);
4199 cpl->ctrl1 = htobe64(ctrl1);
4203 (uintptr_t)flitp == (uintptr_t)&eq->desc[eq->sidx])
4204 flitp = (void *)&eq->desc[0];
4206 write_gl_to_txd(txq, m, (caddr_t *)(&flitp), checkwrap);
4210 txsd = &txq->sdesc[eq->pidx];
4212 txsd->desc_used = ndesc;
4218 * If the SGL ends on an address that is not 16 byte aligned, this function will
4219 * add a 0 filled flit at the end.
4222 write_gl_to_txd(struct sge_txq *txq, struct mbuf *m, caddr_t *to, int checkwrap)
4224 struct sge_eq *eq = &txq->eq;
4225 struct sglist *gl = txq->gl;
4226 struct sglist_seg *seg;
4227 __be64 *flitp, *wrap;
4228 struct ulptx_sgl *usgl;
4229 int i, nflits, nsegs;
4231 KASSERT(((uintptr_t)(*to) & 0xf) == 0,
4232 ("%s: SGL must start at a 16 byte boundary: %p", __func__, *to));
4233 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4234 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4237 nsegs = gl->sg_nseg;
4240 nflits = (3 * (nsegs - 1)) / 2 + ((nsegs - 1) & 1) + 2;
4241 flitp = (__be64 *)(*to);
4242 wrap = (__be64 *)(&eq->desc[eq->sidx]);
4243 seg = &gl->sg_segs[0];
4244 usgl = (void *)flitp;
4247 * We start at a 16 byte boundary somewhere inside the tx descriptor
4248 * ring, so we're at least 16 bytes away from the status page. There is
4249 * no chance of a wrap around in the middle of usgl (which is 16 bytes).
4252 usgl->cmd_nsge = htobe32(V_ULPTX_CMD(ULP_TX_SC_DSGL) |
4253 V_ULPTX_NSGE(nsegs));
4254 usgl->len0 = htobe32(seg->ss_len);
4255 usgl->addr0 = htobe64(seg->ss_paddr);
4258 if (checkwrap == 0 || (uintptr_t)(flitp + nflits) <= (uintptr_t)wrap) {
4260 /* Won't wrap around at all */
4262 for (i = 0; i < nsegs - 1; i++, seg++) {
4263 usgl->sge[i / 2].len[i & 1] = htobe32(seg->ss_len);
4264 usgl->sge[i / 2].addr[i & 1] = htobe64(seg->ss_paddr);
4267 usgl->sge[i / 2].len[1] = htobe32(0);
4271 /* Will wrap somewhere in the rest of the SGL */
4273 /* 2 flits already written, write the rest flit by flit */
4274 flitp = (void *)(usgl + 1);
4275 for (i = 0; i < nflits - 2; i++) {
4277 flitp = (void *)eq->desc;
4278 *flitp++ = get_flit(seg, nsegs - 1, i);
4283 MPASS(((uintptr_t)flitp) & 0xf);
4287 MPASS((((uintptr_t)flitp) & 0xf) == 0);
4288 if (__predict_false(flitp == wrap))
4289 *to = (void *)eq->desc;
4291 *to = (void *)flitp;
4295 copy_to_txd(struct sge_eq *eq, caddr_t from, caddr_t *to, int len)
4298 MPASS((uintptr_t)(*to) >= (uintptr_t)&eq->desc[0]);
4299 MPASS((uintptr_t)(*to) < (uintptr_t)&eq->desc[eq->sidx]);
4301 if (__predict_true((uintptr_t)(*to) + len <=
4302 (uintptr_t)&eq->desc[eq->sidx])) {
4303 bcopy(from, *to, len);
4306 int portion = (uintptr_t)&eq->desc[eq->sidx] - (uintptr_t)(*to);
4308 bcopy(from, *to, portion);
4310 portion = len - portion; /* remaining */
4311 bcopy(from, (void *)eq->desc, portion);
4312 (*to) = (caddr_t)eq->desc + portion;
4317 ring_eq_db(struct adapter *sc, struct sge_eq *eq, u_int n)
4325 clrbit(&db, DOORBELL_WCWR);
4328 switch (ffs(db) - 1) {
4330 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4333 case DOORBELL_WCWR: {
4334 volatile uint64_t *dst, *src;
4338 * Queues whose 128B doorbell segment fits in the page do not
4339 * use relative qid (udb_qid is always 0). Only queues with
4340 * doorbell segments can do WCWR.
4342 KASSERT(eq->udb_qid == 0 && n == 1,
4343 ("%s: inappropriate doorbell (0x%x, %d, %d) for eq %p",
4344 __func__, eq->doorbells, n, eq->dbidx, eq));
4346 dst = (volatile void *)((uintptr_t)eq->udb + UDBS_WR_OFFSET -
4349 src = (void *)&eq->desc[i];
4350 while (src != (void *)&eq->desc[i + 1])
4356 case DOORBELL_UDBWC:
4357 *eq->udb = htole32(V_QID(eq->udb_qid) | V_PIDX(n));
4362 t4_write_reg(sc, MYPF_REG(A_SGE_PF_KDOORBELL),
4363 V_QID(eq->cntxt_id) | V_PIDX(n));
4367 IDXINCR(eq->dbidx, n, eq->sidx);
4371 reclaimable_tx_desc(struct sge_eq *eq)
4375 hw_cidx = read_hw_cidx(eq);
4376 return (IDXDIFF(hw_cidx, eq->cidx, eq->sidx));
4380 total_available_tx_desc(struct sge_eq *eq)
4382 uint16_t hw_cidx, pidx;
4384 hw_cidx = read_hw_cidx(eq);
4387 if (pidx == hw_cidx)
4388 return (eq->sidx - 1);
4390 return (IDXDIFF(hw_cidx, pidx, eq->sidx) - 1);
4393 static inline uint16_t
4394 read_hw_cidx(struct sge_eq *eq)
4396 struct sge_qstat *spg = (void *)&eq->desc[eq->sidx];
4397 uint16_t cidx = spg->cidx; /* stable snapshot */
4399 return (be16toh(cidx));
4403 * Reclaim 'n' descriptors approximately.
4406 reclaim_tx_descs(struct sge_txq *txq, u_int n)
4408 struct tx_sdesc *txsd;
4409 struct sge_eq *eq = &txq->eq;
4410 u_int can_reclaim, reclaimed;
4412 TXQ_LOCK_ASSERT_OWNED(txq);
4416 can_reclaim = reclaimable_tx_desc(eq);
4417 while (can_reclaim && reclaimed < n) {
4419 struct mbuf *m, *nextpkt;
4421 txsd = &txq->sdesc[eq->cidx];
4422 ndesc = txsd->desc_used;
4424 /* Firmware doesn't return "partial" credits. */
4425 KASSERT(can_reclaim >= ndesc,
4426 ("%s: unexpected number of credits: %d, %d",
4427 __func__, can_reclaim, ndesc));
4429 for (m = txsd->m; m != NULL; m = nextpkt) {
4430 nextpkt = m->m_nextpkt;
4431 m->m_nextpkt = NULL;
4435 can_reclaim -= ndesc;
4436 IDXINCR(eq->cidx, ndesc, eq->sidx);
4443 tx_reclaim(void *arg, int n)
4445 struct sge_txq *txq = arg;
4446 struct sge_eq *eq = &txq->eq;
4449 if (TXQ_TRYLOCK(txq) == 0)
4451 n = reclaim_tx_descs(txq, 32);
4452 if (eq->cidx == eq->pidx)
4453 eq->equeqidx = eq->pidx;
4459 get_flit(struct sglist_seg *segs, int nsegs, int idx)
4461 int i = (idx / 3) * 2;
4467 rc = htobe32(segs[i].ss_len);
4469 rc |= (uint64_t)htobe32(segs[i + 1].ss_len) << 32;
4474 return (htobe64(segs[i].ss_paddr));
4476 return (htobe64(segs[i + 1].ss_paddr));
4483 find_best_refill_source(struct adapter *sc, struct sge_fl *fl, int maxp)
4485 int8_t zidx, hwidx, idx;
4486 uint16_t region1, region3;
4487 int spare, spare_needed, n;
4488 struct sw_zone_info *swz;
4489 struct hw_buf_info *hwb, *hwb_list = &sc->sge.hw_buf_info[0];
4492 * Buffer Packing: Look for PAGE_SIZE or larger zone which has a bufsize
4493 * large enough for the max payload and cluster metadata. Otherwise
4494 * settle for the largest bufsize that leaves enough room in the cluster
4497 * Without buffer packing: Look for the smallest zone which has a
4498 * bufsize large enough for the max payload. Settle for the largest
4499 * bufsize available if there's nothing big enough for max payload.
4501 spare_needed = fl->flags & FL_BUF_PACKING ? CL_METADATA_SIZE : 0;
4502 swz = &sc->sge.sw_zone_info[0];
4504 for (zidx = 0; zidx < SW_ZONE_SIZES; zidx++, swz++) {
4505 if (swz->size > largest_rx_cluster) {
4506 if (__predict_true(hwidx != -1))
4510 * This is a misconfiguration. largest_rx_cluster is
4511 * preventing us from finding a refill source. See
4512 * dev.t5nex.<n>.buffer_sizes to figure out why.
4514 device_printf(sc->dev, "largest_rx_cluster=%u leaves no"
4515 " refill source for fl %p (dma %u). Ignored.\n",
4516 largest_rx_cluster, fl, maxp);
4518 for (idx = swz->head_hwidx; idx != -1; idx = hwb->next) {
4519 hwb = &hwb_list[idx];
4520 spare = swz->size - hwb->size;
4521 if (spare < spare_needed)
4524 hwidx = idx; /* best option so far */
4525 if (hwb->size >= maxp) {
4527 if ((fl->flags & FL_BUF_PACKING) == 0)
4528 goto done; /* stop looking (not packing) */
4530 if (swz->size >= safest_rx_cluster)
4531 goto done; /* stop looking (packing) */
4533 break; /* keep looking, next zone */
4537 /* A usable hwidx has been located. */
4539 hwb = &hwb_list[hwidx];
4541 swz = &sc->sge.sw_zone_info[zidx];
4543 region3 = swz->size - hwb->size;
4546 * Stay within this zone and see if there is a better match when mbuf
4547 * inlining is allowed. Remember that the hwidx's are sorted in
4548 * decreasing order of size (so in increasing order of spare area).
4550 for (idx = hwidx; idx != -1; idx = hwb->next) {
4551 hwb = &hwb_list[idx];
4552 spare = swz->size - hwb->size;
4554 if (allow_mbufs_in_cluster == 0 || hwb->size < maxp)
4558 * Do not inline mbufs if doing so would violate the pad/pack
4559 * boundary alignment requirement.
4561 if (fl_pad && (MSIZE % sc->sge.pad_boundary) != 0)
4563 if (fl->flags & FL_BUF_PACKING &&
4564 (MSIZE % sc->sge.pack_boundary) != 0)
4567 if (spare < CL_METADATA_SIZE + MSIZE)
4569 n = (spare - CL_METADATA_SIZE) / MSIZE;
4570 if (n > howmany(hwb->size, maxp))
4574 if (fl->flags & FL_BUF_PACKING) {
4575 region1 = n * MSIZE;
4576 region3 = spare - region1;
4579 region3 = spare - region1;
4584 KASSERT(zidx >= 0 && zidx < SW_ZONE_SIZES,
4585 ("%s: bad zone %d for fl %p, maxp %d", __func__, zidx, fl, maxp));
4586 KASSERT(hwidx >= 0 && hwidx <= SGE_FLBUF_SIZES,
4587 ("%s: bad hwidx %d for fl %p, maxp %d", __func__, hwidx, fl, maxp));
4588 KASSERT(region1 + sc->sge.hw_buf_info[hwidx].size + region3 ==
4589 sc->sge.sw_zone_info[zidx].size,
4590 ("%s: bad buffer layout for fl %p, maxp %d. "
4591 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4592 sc->sge.sw_zone_info[zidx].size, region1,
4593 sc->sge.hw_buf_info[hwidx].size, region3));
4594 if (fl->flags & FL_BUF_PACKING || region1 > 0) {
4595 KASSERT(region3 >= CL_METADATA_SIZE,
4596 ("%s: no room for metadata. fl %p, maxp %d; "
4597 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4598 sc->sge.sw_zone_info[zidx].size, region1,
4599 sc->sge.hw_buf_info[hwidx].size, region3));
4600 KASSERT(region1 % MSIZE == 0,
4601 ("%s: bad mbuf region for fl %p, maxp %d. "
4602 "cl %d; r1 %d, payload %d, r3 %d", __func__, fl, maxp,
4603 sc->sge.sw_zone_info[zidx].size, region1,
4604 sc->sge.hw_buf_info[hwidx].size, region3));
4607 fl->cll_def.zidx = zidx;
4608 fl->cll_def.hwidx = hwidx;
4609 fl->cll_def.region1 = region1;
4610 fl->cll_def.region3 = region3;
4614 find_safe_refill_source(struct adapter *sc, struct sge_fl *fl)
4616 struct sge *s = &sc->sge;
4617 struct hw_buf_info *hwb;
4618 struct sw_zone_info *swz;
4622 if (fl->flags & FL_BUF_PACKING)
4623 hwidx = s->safe_hwidx2; /* with room for metadata */
4624 else if (allow_mbufs_in_cluster && s->safe_hwidx2 != -1) {
4625 hwidx = s->safe_hwidx2;
4626 hwb = &s->hw_buf_info[hwidx];
4627 swz = &s->sw_zone_info[hwb->zidx];
4628 spare = swz->size - hwb->size;
4630 /* no good if there isn't room for an mbuf as well */
4631 if (spare < CL_METADATA_SIZE + MSIZE)
4632 hwidx = s->safe_hwidx1;
4634 hwidx = s->safe_hwidx1;
4637 /* No fallback source */
4638 fl->cll_alt.hwidx = -1;
4639 fl->cll_alt.zidx = -1;
4644 hwb = &s->hw_buf_info[hwidx];
4645 swz = &s->sw_zone_info[hwb->zidx];
4646 spare = swz->size - hwb->size;
4647 fl->cll_alt.hwidx = hwidx;
4648 fl->cll_alt.zidx = hwb->zidx;
4649 if (allow_mbufs_in_cluster &&
4650 (fl_pad == 0 || (MSIZE % sc->sge.pad_boundary) == 0))
4651 fl->cll_alt.region1 = ((spare - CL_METADATA_SIZE) / MSIZE) * MSIZE;
4653 fl->cll_alt.region1 = 0;
4654 fl->cll_alt.region3 = spare - fl->cll_alt.region1;
4658 add_fl_to_sfl(struct adapter *sc, struct sge_fl *fl)
4660 mtx_lock(&sc->sfl_lock);
4662 if ((fl->flags & FL_DOOMED) == 0) {
4663 fl->flags |= FL_STARVING;
4664 TAILQ_INSERT_TAIL(&sc->sfl, fl, link);
4665 callout_reset(&sc->sfl_callout, hz / 5, refill_sfl, sc);
4668 mtx_unlock(&sc->sfl_lock);
4672 handle_wrq_egr_update(struct adapter *sc, struct sge_eq *eq)
4674 struct sge_wrq *wrq = (void *)eq;
4676 atomic_readandclear_int(&eq->equiq);
4677 taskqueue_enqueue(sc->tq[eq->tx_chan], &wrq->wrq_tx_task);
4681 handle_eth_egr_update(struct adapter *sc, struct sge_eq *eq)
4683 struct sge_txq *txq = (void *)eq;
4685 MPASS((eq->flags & EQ_TYPEMASK) == EQ_ETH);
4687 atomic_readandclear_int(&eq->equiq);
4688 mp_ring_check_drainage(txq->r, 0);
4689 taskqueue_enqueue(sc->tq[eq->tx_chan], &txq->tx_reclaim_task);
4693 handle_sge_egr_update(struct sge_iq *iq, const struct rss_header *rss,
4696 const struct cpl_sge_egr_update *cpl = (const void *)(rss + 1);
4697 unsigned int qid = G_EGR_QID(ntohl(cpl->opcode_qid));
4698 struct adapter *sc = iq->adapter;
4699 struct sge *s = &sc->sge;
4701 static void (*h[])(struct adapter *, struct sge_eq *) = {NULL,
4702 &handle_wrq_egr_update, &handle_eth_egr_update,
4703 &handle_wrq_egr_update};
4705 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4708 eq = s->eqmap[qid - s->eq_start];
4709 (*h[eq->flags & EQ_TYPEMASK])(sc, eq);
4714 /* handle_fw_msg works for both fw4_msg and fw6_msg because this is valid */
4715 CTASSERT(offsetof(struct cpl_fw4_msg, data) == \
4716 offsetof(struct cpl_fw6_msg, data));
4719 handle_fw_msg(struct sge_iq *iq, const struct rss_header *rss, struct mbuf *m)
4721 struct adapter *sc = iq->adapter;
4722 const struct cpl_fw6_msg *cpl = (const void *)(rss + 1);
4724 KASSERT(m == NULL, ("%s: payload with opcode %02x", __func__,
4727 if (cpl->type == FW_TYPE_RSSCPL || cpl->type == FW6_TYPE_RSSCPL) {
4728 const struct rss_header *rss2;
4730 rss2 = (const struct rss_header *)&cpl->data[0];
4731 return (sc->cpl_handler[rss2->opcode](iq, rss2, m));
4734 return (sc->fw_msg_handler[cpl->type](sc, &cpl->data[0]));
4738 sysctl_uint16(SYSCTL_HANDLER_ARGS)
4740 uint16_t *id = arg1;
4743 return sysctl_handle_int(oidp, &i, 0, req);
4747 sysctl_bufsizes(SYSCTL_HANDLER_ARGS)
4749 struct sge *s = arg1;
4750 struct hw_buf_info *hwb = &s->hw_buf_info[0];
4751 struct sw_zone_info *swz = &s->sw_zone_info[0];
4756 sbuf_new(&sb, NULL, 32, SBUF_AUTOEXTEND);
4757 for (i = 0; i < SGE_FLBUF_SIZES; i++, hwb++) {
4758 if (hwb->zidx >= 0 && swz[hwb->zidx].size <= largest_rx_cluster)
4763 sbuf_printf(&sb, "%u%c ", hwb->size, c);
4767 rc = sysctl_handle_string(oidp, sbuf_data(&sb), sbuf_len(&sb), req);