2 * Copyright (c) 2016 Chelsio Communications, Inc.
4 * Written by: John Baldwin <jhb@FreeBSD.org>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 #include <sys/cdefs.h>
29 __FBSDID("$FreeBSD$");
32 #include "opt_inet6.h"
34 #include <sys/param.h>
37 #include <sys/counter.h>
38 #include <sys/kernel.h>
39 #include <sys/module.h>
41 #include <dev/pci/pcivar.h>
42 #if defined(__i386__) || defined(__amd64__)
47 #include "common/common.h"
48 #include "common/t4_regs.h"
50 #include "t4_mp_ring.h"
55 * The Virtual Interfaces are connected to an internal switch on the chip
56 * which allows VIs attached to the same port to talk to each other even when
57 * the port link is down. As a result, we might want to always report a
58 * VF's link as being "up".
60 * XXX: Add a TUNABLE and possible per-device sysctl for this?
63 struct intrs_and_queues {
64 uint16_t intr_type; /* MSI, or MSI-X */
65 uint16_t nirq; /* Total # of vectors */
66 uint16_t intr_flags_10g;/* Interrupt flags for each 10G port */
67 uint16_t intr_flags_1g; /* Interrupt flags for each 1G port */
68 uint16_t ntxq10g; /* # of NIC txq's for each 10G port */
69 uint16_t nrxq10g; /* # of NIC rxq's for each 10G port */
70 uint16_t ntxq1g; /* # of NIC txq's for each 1G port */
71 uint16_t nrxq1g; /* # of NIC rxq's for each 1G port */
78 {0x4800, "Chelsio T440-dbg VF"},
79 {0x4801, "Chelsio T420-CR VF"},
80 {0x4802, "Chelsio T422-CR VF"},
81 {0x4803, "Chelsio T440-CR VF"},
82 {0x4804, "Chelsio T420-BCH VF"},
83 {0x4805, "Chelsio T440-BCH VF"},
84 {0x4806, "Chelsio T440-CH VF"},
85 {0x4807, "Chelsio T420-SO VF"},
86 {0x4808, "Chelsio T420-CX VF"},
87 {0x4809, "Chelsio T420-BT VF"},
88 {0x480a, "Chelsio T404-BT VF"},
89 {0x480e, "Chelsio T440-LP-CR VF"},
91 {0x5800, "Chelsio T580-dbg VF"},
92 {0x5801, "Chelsio T520-CR VF"}, /* 2 x 10G */
93 {0x5802, "Chelsio T522-CR VF"}, /* 2 x 10G, 2 X 1G */
94 {0x5803, "Chelsio T540-CR VF"}, /* 4 x 10G */
95 {0x5807, "Chelsio T520-SO VF"}, /* 2 x 10G, nomem */
96 {0x5809, "Chelsio T520-BT VF"}, /* 2 x 10GBaseT */
97 {0x580a, "Chelsio T504-BT VF"}, /* 4 x 1G */
98 {0x580d, "Chelsio T580-CR VF"}, /* 2 x 40G */
99 {0x580e, "Chelsio T540-LP-CR VF"}, /* 4 x 10G */
100 {0x5810, "Chelsio T580-LP-CR VF"}, /* 2 x 40G */
101 {0x5811, "Chelsio T520-LL-CR VF"}, /* 2 x 10G */
102 {0x5812, "Chelsio T560-CR VF"}, /* 1 x 40G, 2 x 10G */
103 {0x5814, "Chelsio T580-LP-SO-CR VF"}, /* 2 x 40G, nomem */
104 {0x5815, "Chelsio T502-BT VF"}, /* 2 x 1G */
106 {0x5804, "Chelsio T520-BCH VF"},
107 {0x5805, "Chelsio T540-BCH VF"},
108 {0x5806, "Chelsio T540-CH VF"},
109 {0x5808, "Chelsio T520-CX VF"},
110 {0x580b, "Chelsio B520-SR VF"},
111 {0x580c, "Chelsio B504-BT VF"},
112 {0x580f, "Chelsio Amsterdam VF"},
113 {0x5813, "Chelsio T580-CHR VF"},
117 static d_ioctl_t t4vf_ioctl;
119 static struct cdevsw t4vf_cdevsw = {
120 .d_version = D_VERSION,
121 .d_ioctl = t4vf_ioctl,
126 t4vf_probe(device_t dev)
131 d = pci_get_device(dev);
132 for (i = 0; i < nitems(t4vf_pciids); i++) {
133 if (d == t4vf_pciids[i].device) {
134 device_set_desc(dev, t4vf_pciids[i].desc);
135 return (BUS_PROBE_DEFAULT);
142 t5vf_probe(device_t dev)
147 d = pci_get_device(dev);
148 for (i = 0; i < nitems(t5vf_pciids); i++) {
149 if (d == t5vf_pciids[i].device) {
150 device_set_desc(dev, t5vf_pciids[i].desc);
151 return (BUS_PROBE_DEFAULT);
157 #define FW_PARAM_DEV(param) \
158 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_DEV) | \
159 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_DEV_##param))
160 #define FW_PARAM_PFVF(param) \
161 (V_FW_PARAMS_MNEM(FW_PARAMS_MNEM_PFVF) | \
162 V_FW_PARAMS_PARAM_X(FW_PARAMS_PARAM_PFVF_##param))
165 get_params__pre_init(struct adapter *sc)
168 uint32_t param[3], val[3];
170 param[0] = FW_PARAM_DEV(FWREV);
171 param[1] = FW_PARAM_DEV(TPREV);
172 param[2] = FW_PARAM_DEV(CCLK);
173 rc = -t4vf_query_params(sc, nitems(param), param, val);
175 device_printf(sc->dev,
176 "failed to query parameters (pre_init): %d.\n", rc);
180 sc->params.fw_vers = val[0];
181 sc->params.tp_vers = val[1];
182 sc->params.vpd.cclk = val[2];
184 snprintf(sc->fw_version, sizeof(sc->fw_version), "%u.%u.%u.%u",
185 G_FW_HDR_FW_VER_MAJOR(sc->params.fw_vers),
186 G_FW_HDR_FW_VER_MINOR(sc->params.fw_vers),
187 G_FW_HDR_FW_VER_MICRO(sc->params.fw_vers),
188 G_FW_HDR_FW_VER_BUILD(sc->params.fw_vers));
190 snprintf(sc->tp_version, sizeof(sc->tp_version), "%u.%u.%u.%u",
191 G_FW_HDR_FW_VER_MAJOR(sc->params.tp_vers),
192 G_FW_HDR_FW_VER_MINOR(sc->params.tp_vers),
193 G_FW_HDR_FW_VER_MICRO(sc->params.tp_vers),
194 G_FW_HDR_FW_VER_BUILD(sc->params.tp_vers));
200 get_params__post_init(struct adapter *sc)
204 rc = -t4vf_get_sge_params(sc);
206 device_printf(sc->dev,
207 "unable to retrieve adapter SGE parameters: %d\n", rc);
211 rc = -t4vf_get_rss_glb_config(sc);
213 device_printf(sc->dev,
214 "unable to retrieve adapter RSS parameters: %d\n", rc);
217 if (sc->params.rss.mode != FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL) {
218 device_printf(sc->dev,
219 "unable to operate with global RSS mode %d\n",
220 sc->params.rss.mode);
224 rc = t4_read_chip_settings(sc);
229 * Grab our Virtual Interface resource allocation, extract the
230 * features that we're interested in and do a bit of sanity testing on
233 rc = -t4vf_get_vfres(sc);
235 device_printf(sc->dev,
236 "unable to get virtual interface resources: %d\n", rc);
241 * Check for various parameter sanity issues.
243 if (sc->params.vfres.pmask == 0) {
244 device_printf(sc->dev, "no port access configured/usable!\n");
247 if (sc->params.vfres.nvi == 0) {
248 device_printf(sc->dev,
249 "no virtual interfaces configured/usable!\n");
252 sc->params.portvec = sc->params.vfres.pmask;
258 set_params__post_init(struct adapter *sc)
262 /* ask for encapsulated CPLs */
263 param = FW_PARAM_PFVF(CPLFW4MSG_ENCAP);
265 (void)t4vf_set_params(sc, 1, ¶m, &val);
274 cfg_itype_and_nqueues(struct adapter *sc, int n10g, int n1g,
275 struct intrs_and_queues *iaq)
277 struct vf_resources *vfres;
278 int nrxq10g, nrxq1g, nrxq;
279 int ntxq10g, ntxq1g, ntxq;
280 int itype, iq_avail, navail, rc;
283 * Figure out the layout of queues across our VIs and ensure
284 * we can allocate enough interrupts for our layout.
286 vfres = &sc->params.vfres;
287 bzero(iaq, sizeof(*iaq));
289 for (itype = INTR_MSIX; itype != 0; itype >>= 1) {
290 if (itype == INTR_INTX)
293 if (itype == INTR_MSIX)
294 navail = pci_msix_count(sc->dev);
296 navail = pci_msi_count(sc->dev);
301 iaq->intr_type = itype;
302 iaq->intr_flags_10g = 0;
303 iaq->intr_flags_1g = 0;
306 * XXX: The Linux driver reserves an Ingress Queue for
307 * forwarded interrupts when using MSI (but not MSI-X).
308 * It seems it just always asks for 2 interrupts and
309 * forwards all rxqs to the forwarded interrupt.
311 * We must reserve one IRQ for the for the firmware
314 * Every rxq requires an ingress queue with a free
315 * list and interrupts and an egress queue. Every txq
316 * requires an ETH egress queue.
318 iaq->nirq = T4VF_EXTRA_INTR;
321 * First, determine how many queues we can allocate.
322 * Start by finding the upper bound on rxqs from the
323 * limit on ingress queues.
325 iq_avail = vfres->niqflint - iaq->nirq;
326 if (iq_avail < n10g + n1g) {
327 device_printf(sc->dev,
328 "Not enough ingress queues (%d) for %d ports\n",
329 vfres->niqflint, n10g + n1g);
334 * Try to honor the cap on interrupts. If there aren't
335 * enough interrupts for at least one interrupt per
336 * port, then don't bother, we will just forward all
337 * interrupts to one interrupt in that case.
339 if (iaq->nirq + n10g + n1g <= navail) {
340 if (iq_avail > navail - iaq->nirq)
341 iq_avail = navail - iaq->nirq;
344 nrxq10g = t4_nrxq10g;
346 nrxq = n10g * nrxq10g + n1g * nrxq1g;
347 if (nrxq > iq_avail && nrxq1g > 1) {
348 /* Too many ingress queues. Try just 1 for 1G. */
350 nrxq = n10g * nrxq10g + n1g * nrxq1g;
352 if (nrxq > iq_avail) {
354 * Still too many ingress queues. Use what we
355 * can for each 10G port.
357 nrxq10g = (iq_avail - n1g) / n10g;
358 nrxq = n10g * nrxq10g + n1g * nrxq1g;
360 KASSERT(nrxq <= iq_avail, ("too many ingress queues"));
363 * Next, determine the upper bound on txqs from the limit
366 if (vfres->nethctrl < n10g + n1g) {
367 device_printf(sc->dev,
368 "Not enough ETH queues (%d) for %d ports\n",
369 vfres->nethctrl, n10g + n1g);
373 ntxq10g = t4_ntxq10g;
375 ntxq = n10g * ntxq10g + n1g * ntxq1g;
376 if (ntxq > vfres->nethctrl) {
377 /* Too many ETH queues. Try just 1 for 1G. */
379 ntxq = n10g * ntxq10g + n1g * ntxq1g;
381 if (ntxq > vfres->nethctrl) {
383 * Still too many ETH queues. Use what we
384 * can for each 10G port.
386 ntxq10g = (vfres->nethctrl - n1g) / n10g;
387 ntxq = n10g * ntxq10g + n1g * ntxq1g;
389 KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues"));
392 * Finally, ensure we have enough egress queues.
394 if (vfres->neq < (n10g + n1g) * 2) {
395 device_printf(sc->dev,
396 "Not enough egress queues (%d) for %d ports\n",
397 vfres->neq, n10g + n1g);
400 if (nrxq + ntxq > vfres->neq) {
401 /* Just punt and use 1 for everything. */
402 nrxq1g = ntxq1g = nrxq10g = ntxq10g = 1;
403 nrxq = n10g * nrxq10g + n1g * nrxq1g;
404 ntxq = n10g * ntxq10g + n1g * ntxq1g;
406 KASSERT(nrxq <= iq_avail, ("too many ingress queues"));
407 KASSERT(ntxq <= vfres->nethctrl, ("too many ETH queues"));
408 KASSERT(nrxq + ntxq <= vfres->neq, ("too many egress queues"));
411 * Do we have enough interrupts? For MSI the interrupts
412 * have to be a power of 2 as well.
415 iaq->ntxq10g = ntxq10g;
416 iaq->ntxq1g = ntxq1g;
417 iaq->nrxq10g = nrxq10g;
418 iaq->nrxq1g = nrxq1g;
419 if (iaq->nirq <= navail &&
420 (itype != INTR_MSI || powerof2(iaq->nirq))) {
422 if (itype == INTR_MSIX)
423 rc = pci_alloc_msix(sc->dev, &navail);
425 rc = pci_alloc_msi(sc->dev, &navail);
427 device_printf(sc->dev,
428 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
429 itype, rc, iaq->nirq, navail);
432 if (navail == iaq->nirq) {
433 iaq->intr_flags_10g = INTR_RXQ;
434 iaq->intr_flags_1g = INTR_RXQ;
437 pci_release_msi(sc->dev);
440 /* Fall back to a single interrupt. */
443 if (itype == INTR_MSIX)
444 rc = pci_alloc_msix(sc->dev, &navail);
446 rc = pci_alloc_msi(sc->dev, &navail);
448 device_printf(sc->dev,
449 "failed to allocate vectors:%d, type=%d, req=%d, rcvd=%d\n",
450 itype, rc, iaq->nirq, navail);
451 iaq->intr_flags_10g = 0;
452 iaq->intr_flags_1g = 0;
456 device_printf(sc->dev,
457 "failed to find a usable interrupt type. "
458 "allowed=%d, msi-x=%d, msi=%d, intx=1", t4_intr_types,
459 pci_msix_count(sc->dev), pci_msi_count(sc->dev));
465 t4vf_attach(device_t dev)
468 int rc = 0, i, j, n10g, n1g, rqidx, tqidx;
469 struct make_dev_args mda;
470 struct intrs_and_queues iaq;
473 sc = device_get_softc(dev);
475 pci_enable_busmaster(dev);
476 pci_set_max_read_req(dev, 4096);
477 sc->params.pci.mps = pci_get_max_payload(dev);
481 sc->sge_gts_reg = VF_SGE_REG(A_SGE_VF_GTS);
482 sc->sge_kdoorbell_reg = VF_SGE_REG(A_SGE_VF_KDOORBELL);
483 snprintf(sc->lockname, sizeof(sc->lockname), "%s",
484 device_get_nameunit(dev));
485 mtx_init(&sc->sc_lock, sc->lockname, 0, MTX_DEF);
488 mtx_init(&sc->sfl_lock, "starving freelists", 0, MTX_DEF);
489 TAILQ_INIT(&sc->sfl);
490 callout_init_mtx(&sc->sfl_callout, &sc->sfl_lock, 0);
492 mtx_init(&sc->reg_lock, "indirect register access", 0, MTX_DEF);
494 rc = t4_map_bars_0_and_4(sc);
496 goto done; /* error message displayed already */
498 rc = -t4vf_prep_adapter(sc);
503 * Leave the 'pf' and 'mbox' values as zero. This ensures
504 * that various firmware messages do not set the fields which
505 * is the correct thing to do for a VF.
508 memset(sc->chan_map, 0xff, sizeof(sc->chan_map));
510 make_dev_args_init(&mda);
511 mda.mda_devsw = &t4vf_cdevsw;
512 mda.mda_uid = UID_ROOT;
513 mda.mda_gid = GID_WHEEL;
515 mda.mda_si_drv1 = sc;
516 rc = make_dev_s(&mda, &sc->cdev, "%s", device_get_nameunit(dev));
518 device_printf(dev, "failed to create nexus char device: %d.\n",
521 #if defined(__i386__)
522 if ((cpu_feature & CPUID_CX8) == 0) {
523 device_printf(dev, "64 bit atomics not available.\n");
530 * Some environments do not properly handle PCIE FLRs -- e.g. in Linux
531 * 2.6.31 and later we can't call pci_reset_function() in order to
532 * issue an FLR because of a self- deadlock on the device semaphore.
533 * Meanwhile, the OS infrastructure doesn't issue FLRs in all the
534 * cases where they're needed -- for instance, some versions of KVM
535 * fail to reset "Assigned Devices" when the VM reboots. Therefore we
536 * use the firmware based reset in order to reset any per function
539 rc = -t4vf_fw_reset(sc);
541 device_printf(dev, "FW reset failed: %d\n", rc);
547 * Grab basic operational parameters. These will predominantly have
548 * been set up by the Physical Function Driver or will be hard coded
549 * into the adapter. We just have to live with them ... Note that
550 * we _must_ get our VPD parameters before our SGE parameters because
551 * we need to know the adapter's core clock from the VPD in order to
552 * properly decode the SGE Timer Values.
554 rc = get_params__pre_init(sc);
556 goto done; /* error message displayed already */
557 rc = get_params__post_init(sc);
559 goto done; /* error message displayed already */
561 rc = set_params__post_init(sc);
563 goto done; /* error message displayed already */
565 rc = t4_map_bar_2(sc);
567 goto done; /* error message displayed already */
569 rc = t4_create_dma_tag(sc);
571 goto done; /* error message displayed already */
574 * The number of "ports" which we support is equal to the number of
575 * Virtual Interfaces with which we've been provisioned.
577 sc->params.nports = imin(sc->params.vfres.nvi, MAX_NPORTS);
580 * We may have been provisioned with more VIs than the number of
581 * ports we're allowed to access (our Port Access Rights Mask).
582 * Just use a single VI for each port.
584 sc->params.nports = imin(sc->params.nports,
585 bitcount32(sc->params.vfres.pmask));
589 * XXX: The Linux VF driver will lower nports if it thinks there
590 * are too few resources in vfres (niqflint, nethctrl, neq).
595 * First pass over all the ports - allocate VIs and initialize some
596 * basic parameters like mac address, port type, etc. We also figure
597 * out whether a port is 10G or 1G and use that information when
598 * calculating how many interrupts to attempt to allocate.
601 for_each_port(sc, i) {
602 struct port_info *pi;
604 pi = malloc(sizeof(*pi), M_CXGBE, M_ZERO | M_WAITOK);
607 /* These must be set before t4_port_init */
611 pi->vi = malloc(sizeof(struct vi_info) * pi->nvi, M_CXGBE,
615 * Allocate the "main" VI and initialize parameters
618 rc = -t4_port_init(sc, sc->mbox, sc->pf, 0, i);
620 device_printf(dev, "unable to initialize port %d: %d\n",
622 free(pi->vi, M_CXGBE);
628 /* No t4_link_start. */
630 snprintf(pi->lockname, sizeof(pi->lockname), "%sp%d",
631 device_get_nameunit(dev), i);
632 mtx_init(&pi->pi_lock, pi->lockname, 0, MTX_DEF);
633 sc->chan_map[pi->tx_chan] = i;
635 pi->tc = malloc(sizeof(struct tx_sched_class) *
636 sc->chip_params->nsched_cls, M_CXGBE, M_ZERO | M_WAITOK);
638 if (is_10G_port(pi) || is_40G_port(pi)) {
646 pi->dev = device_add_child(dev, is_t4(sc) ? "cxgbev" : "cxlv",
648 if (pi->dev == NULL) {
650 "failed to add device for port %d.\n", i);
654 pi->vi[0].dev = pi->dev;
655 device_set_softc(pi->dev, pi);
659 * Interrupt type, # of interrupts, # of rx/tx queues, etc.
661 rc = cfg_itype_and_nqueues(sc, n10g, n1g, &iaq);
663 goto done; /* error message displayed already */
665 sc->intr_type = iaq.intr_type;
666 sc->intr_count = iaq.nirq;
669 s->nrxq = n10g * iaq.nrxq10g + n1g * iaq.nrxq1g;
670 s->ntxq = n10g * iaq.ntxq10g + n1g * iaq.ntxq1g;
671 s->neq = s->ntxq + s->nrxq; /* the free list in an rxq is an eq */
672 s->neq += sc->params.nports + 1;/* ctrl queues: 1 per port + 1 mgmt */
673 s->niq = s->nrxq + 1; /* 1 extra for firmware event queue */
675 s->rxq = malloc(s->nrxq * sizeof(struct sge_rxq), M_CXGBE,
677 s->txq = malloc(s->ntxq * sizeof(struct sge_txq), M_CXGBE,
679 s->iqmap = malloc(s->niq * sizeof(struct sge_iq *), M_CXGBE,
681 s->eqmap = malloc(s->neq * sizeof(struct sge_eq *), M_CXGBE,
684 sc->irq = malloc(sc->intr_count * sizeof(struct irq), M_CXGBE,
688 * Second pass over the ports. This time we know the number of rx and
689 * tx queues that each port should get.
692 for_each_port(sc, i) {
693 struct port_info *pi = sc->port[i];
699 for_each_vi(pi, j, vi) {
701 vi->qsize_rxq = t4_qsize_rxq;
702 vi->qsize_txq = t4_qsize_txq;
704 vi->first_rxq = rqidx;
705 vi->first_txq = tqidx;
706 if (is_10G_port(pi) || is_40G_port(pi)) {
707 vi->tmr_idx = t4_tmr_idx_10g;
708 vi->pktc_idx = t4_pktc_idx_10g;
709 vi->flags |= iaq.intr_flags_10g & INTR_RXQ;
710 vi->nrxq = j == 0 ? iaq.nrxq10g : 1;
711 vi->ntxq = j == 0 ? iaq.ntxq10g : 1;
713 vi->tmr_idx = t4_tmr_idx_1g;
714 vi->pktc_idx = t4_pktc_idx_1g;
715 vi->flags |= iaq.intr_flags_1g & INTR_RXQ;
716 vi->nrxq = j == 0 ? iaq.nrxq1g : 1;
717 vi->ntxq = j == 0 ? iaq.ntxq1g : 1;
722 vi->rsrv_noflowq = 0;
726 rc = t4_setup_intr_handlers(sc);
729 "failed to setup interrupt handlers: %d\n", rc);
733 rc = bus_generic_attach(dev);
736 "failed to attach all child ports: %d\n", rc);
741 "%d ports, %d %s interrupt%s, %d eq, %d iq\n",
742 sc->params.nports, sc->intr_count, sc->intr_type == INTR_MSIX ?
743 "MSI-X" : "MSI", sc->intr_count > 1 ? "s" : "", sc->sge.neq,
748 t4_detach_common(dev);
756 get_regs(struct adapter *sc, struct t4_regdump *regs, uint8_t *buf)
759 /* 0x3f is used as the revision for VFs. */
760 regs->version = chip_id(sc) | (0x3f << 10);
761 t4_get_regs(sc, buf, regs->len);
765 t4_clr_vi_stats(struct adapter *sc)
769 for (reg = A_MPS_VF_STAT_TX_VF_BCAST_BYTES_L;
770 reg <= A_MPS_VF_STAT_RX_VF_ERR_FRAMES_H; reg += 4)
771 t4_write_reg(sc, VF_MPS_REG(reg), 0);
775 t4vf_ioctl(struct cdev *dev, unsigned long cmd, caddr_t data, int fflag,
779 struct adapter *sc = dev->si_drv1;
781 rc = priv_check(td, PRIV_DRIVER);
786 case CHELSIO_T4_GETREG: {
787 struct t4_reg *edata = (struct t4_reg *)data;
789 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
792 if (edata->size == 4)
793 edata->val = t4_read_reg(sc, edata->addr);
794 else if (edata->size == 8)
795 edata->val = t4_read_reg64(sc, edata->addr);
801 case CHELSIO_T4_SETREG: {
802 struct t4_reg *edata = (struct t4_reg *)data;
804 if ((edata->addr & 0x3) != 0 || edata->addr >= sc->mmio_len)
807 if (edata->size == 4) {
808 if (edata->val & 0xffffffff00000000)
810 t4_write_reg(sc, edata->addr, (uint32_t) edata->val);
811 } else if (edata->size == 8)
812 t4_write_reg64(sc, edata->addr, edata->val);
817 case CHELSIO_T4_REGDUMP: {
818 struct t4_regdump *regs = (struct t4_regdump *)data;
819 int reglen = t4_get_regs_len(sc);
822 if (regs->len < reglen) {
823 regs->len = reglen; /* hint to the caller */
828 buf = malloc(reglen, M_CXGBE, M_WAITOK | M_ZERO);
829 get_regs(sc, regs, buf);
830 rc = copyout(buf, regs->data, reglen);
834 case CHELSIO_T4_CLEAR_STATS: {
836 u_int port_id = *(uint32_t *)data;
837 struct port_info *pi;
840 if (port_id >= sc->params.nports)
842 pi = sc->port[port_id];
845 pi->tx_parse_error = 0;
849 * Since this command accepts a port, clear stats for
850 * all VIs on this port.
852 for_each_vi(pi, v, vi) {
853 if (vi->flags & VI_INIT_DONE) {
857 for_each_rxq(vi, i, rxq) {
858 #if defined(INET) || defined(INET6)
859 rxq->lro.lro_queued = 0;
860 rxq->lro.lro_flushed = 0;
863 rxq->vlan_extraction = 0;
866 for_each_txq(vi, i, txq) {
869 txq->vlan_insertion = 0;
873 txq->txpkts0_wrs = 0;
874 txq->txpkts1_wrs = 0;
875 txq->txpkts0_pkts = 0;
876 txq->txpkts1_pkts = 0;
877 mp_ring_reset_stats(txq->r);
883 case CHELSIO_T4_SCHED_CLASS:
884 rc = t4_set_sched_class(sc, (struct t4_sched_params *)data);
886 case CHELSIO_T4_SCHED_QUEUE:
887 rc = t4_set_sched_queue(sc, (struct t4_sched_queue *)data);
896 static device_method_t t4vf_methods[] = {
897 DEVMETHOD(device_probe, t4vf_probe),
898 DEVMETHOD(device_attach, t4vf_attach),
899 DEVMETHOD(device_detach, t4_detach_common),
904 static driver_t t4vf_driver = {
907 sizeof(struct adapter)
910 static device_method_t t5vf_methods[] = {
911 DEVMETHOD(device_probe, t5vf_probe),
912 DEVMETHOD(device_attach, t4vf_attach),
913 DEVMETHOD(device_detach, t4_detach_common),
918 static driver_t t5vf_driver = {
921 sizeof(struct adapter)
924 static driver_t cxgbev_driver = {
927 sizeof(struct port_info)
930 static driver_t cxlv_driver = {
933 sizeof(struct port_info)
936 static devclass_t t4vf_devclass, t5vf_devclass;
937 static devclass_t cxgbev_devclass, cxlv_devclass;
939 DRIVER_MODULE(t4vf, pci, t4vf_driver, t4vf_devclass, 0, 0);
940 MODULE_VERSION(t4vf, 1);
941 MODULE_DEPEND(t4vf, t4nex, 1, 1, 1);
943 DRIVER_MODULE(t5vf, pci, t5vf_driver, t5vf_devclass, 0, 0);
944 MODULE_VERSION(t5vf, 1);
945 MODULE_DEPEND(t5vf, t5nex, 1, 1, 1);
947 DRIVER_MODULE(cxgbev, t4vf, cxgbev_driver, cxgbev_devclass, 0, 0);
948 MODULE_VERSION(cxgbev, 1);
950 DRIVER_MODULE(cxlv, t5vf, cxlv_driver, cxlv_devclass, 0, 0);
951 MODULE_VERSION(cxlv, 1);