1 /* i915_dma.c -- DMA support for the I915 -*- linux-c -*-
4 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include "dev/drm/drmP.h"
33 #include "dev/drm/drm.h"
34 #include "dev/drm/i915_drm.h"
35 #include "dev/drm/i915_drv.h"
37 /* Really want an OS-independent resettable timer. Would like to have
38 * this loop run for (eg) 3 sec, but have the timer reset every time
39 * the head pointer changes, so that EBUSY only happens if the ring
40 * actually stalls for (eg) 3 seconds.
42 int i915_wait_ring(struct drm_device * dev, int n, const char *caller)
44 drm_i915_private_t *dev_priv = dev->dev_private;
45 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
46 u32 last_head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
47 u32 acthd_reg = IS_I965G(dev) ? ACTHD_I965 : ACTHD;
48 u32 last_acthd = I915_READ(acthd_reg);
52 for (i = 0; i < 100000; i++) {
53 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
54 acthd = I915_READ(acthd_reg);
55 ring->space = ring->head - (ring->tail + 8);
57 ring->space += ring->Size;
61 if (dev_priv->sarea_priv)
62 dev_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
64 if (ring->head != last_head)
67 if (acthd != last_acthd)
70 last_head = ring->head;
72 DRM_UDELAY(10 * 1000);
79 * Sets up the hardware status page for devices that need a physical address
82 static int i915_init_phys_hws(struct drm_device *dev)
84 drm_i915_private_t *dev_priv = dev->dev_private;
86 /* Program Hardware Status Page */
88 dev_priv->status_page_dmah =
89 drm_pci_alloc(dev, PAGE_SIZE, PAGE_SIZE, 0xffffffff);
91 if (!dev_priv->status_page_dmah) {
92 DRM_ERROR("Can not allocate hardware status page\n");
95 dev_priv->hw_status_page = dev_priv->status_page_dmah->vaddr;
96 dev_priv->dma_status_page = dev_priv->status_page_dmah->busaddr;
98 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
100 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
101 DRM_DEBUG("Enabled hardware status page\n");
106 * Frees the hardware status page, whether it's a physical address or a virtual
107 * address set up by the X Server.
109 static void i915_free_hws(struct drm_device *dev)
111 drm_i915_private_t *dev_priv = dev->dev_private;
112 if (dev_priv->status_page_dmah) {
113 drm_pci_free(dev, dev_priv->status_page_dmah);
114 dev_priv->status_page_dmah = NULL;
117 if (dev_priv->status_gfx_addr) {
118 dev_priv->status_gfx_addr = 0;
119 drm_core_ioremapfree(&dev_priv->hws_map, dev);
122 /* Need to rewrite hardware status page */
123 I915_WRITE(HWS_PGA, 0x1ffff000);
126 void i915_kernel_lost_context(struct drm_device * dev)
128 drm_i915_private_t *dev_priv = dev->dev_private;
129 drm_i915_ring_buffer_t *ring = &(dev_priv->ring);
131 ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR;
132 ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR;
133 ring->space = ring->head - (ring->tail + 8);
135 ring->space += ring->Size;
137 if (ring->head == ring->tail && dev_priv->sarea_priv)
138 dev_priv->sarea_priv->perf_boxes |= I915_BOX_RING_EMPTY;
141 static int i915_dma_cleanup(struct drm_device * dev)
143 drm_i915_private_t *dev_priv = dev->dev_private;
144 /* Make sure interrupts are disabled here because the uninstall ioctl
145 * may not have been called from userspace and after dev_private
146 * is freed, it's too late.
148 if (dev->irq_enabled)
149 drm_irq_uninstall(dev);
151 if (dev_priv->ring.virtual_start) {
152 drm_core_ioremapfree(&dev_priv->ring.map, dev);
153 dev_priv->ring.virtual_start = NULL;
154 dev_priv->ring.map.virtual = NULL;
155 dev_priv->ring.map.size = 0;
158 /* Clear the HWS virtual address at teardown */
159 if (I915_NEED_GFX_HWS(dev))
165 static int i915_initialize(struct drm_device * dev, drm_i915_init_t * init)
167 drm_i915_private_t *dev_priv = dev->dev_private;
169 dev_priv->sarea = drm_getsarea(dev);
170 if (!dev_priv->sarea) {
171 DRM_ERROR("can not find sarea!\n");
172 i915_dma_cleanup(dev);
176 dev_priv->sarea_priv = (drm_i915_sarea_t *)
177 ((u8 *) dev_priv->sarea->virtual + init->sarea_priv_offset);
179 if (init->ring_size != 0) {
180 if (dev_priv->ring.ring_obj != NULL) {
181 i915_dma_cleanup(dev);
182 DRM_ERROR("Client tried to initialize ringbuffer in "
187 dev_priv->ring.Size = init->ring_size;
188 dev_priv->ring.tail_mask = dev_priv->ring.Size - 1;
190 dev_priv->ring.map.offset = init->ring_start;
191 dev_priv->ring.map.size = init->ring_size;
192 dev_priv->ring.map.type = 0;
193 dev_priv->ring.map.flags = 0;
194 dev_priv->ring.map.mtrr = 0;
196 drm_core_ioremap_wc(&dev_priv->ring.map, dev);
198 if (dev_priv->ring.map.virtual == NULL) {
199 i915_dma_cleanup(dev);
200 DRM_ERROR("can not ioremap virtual address for"
206 dev_priv->ring.virtual_start = dev_priv->ring.map.virtual;
208 dev_priv->cpp = init->cpp;
209 dev_priv->back_offset = init->back_offset;
210 dev_priv->front_offset = init->front_offset;
211 dev_priv->current_page = 0;
212 dev_priv->sarea_priv->pf_current_page = 0;
214 /* Allow hardware batchbuffers unless told otherwise.
216 dev_priv->allow_batchbuffer = 1;
221 static int i915_dma_resume(struct drm_device * dev)
223 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
227 if (!dev_priv->sarea) {
228 DRM_ERROR("can not find sarea!\n");
232 if (dev_priv->ring.map.virtual == NULL) {
233 DRM_ERROR("can not ioremap virtual address for"
238 /* Program Hardware Status Page */
239 if (!dev_priv->hw_status_page) {
240 DRM_ERROR("Can not find hardware status page\n");
243 DRM_DEBUG("hw status page @ %p\n", dev_priv->hw_status_page);
245 if (dev_priv->status_gfx_addr != 0)
246 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
248 I915_WRITE(HWS_PGA, dev_priv->dma_status_page);
249 DRM_DEBUG("Enabled hardware status page\n");
254 static int i915_dma_init(struct drm_device *dev, void *data,
255 struct drm_file *file_priv)
257 drm_i915_init_t *init = data;
260 switch (init->func) {
262 retcode = i915_initialize(dev, init);
264 case I915_CLEANUP_DMA:
265 retcode = i915_dma_cleanup(dev);
267 case I915_RESUME_DMA:
268 retcode = i915_dma_resume(dev);
278 /* Implement basically the same security restrictions as hardware does
279 * for MI_BATCH_NON_SECURE. These can be made stricter at any time.
281 * Most of the calculations below involve calculating the size of a
282 * particular instruction. It's important to get the size right as
283 * that tells us where the next instruction to check is. Any illegal
284 * instruction detected will be given a size of zero, which is a
285 * signal to abort the rest of the buffer.
287 static int do_validate_cmd(int cmd)
289 switch (((cmd >> 29) & 0x7)) {
291 switch ((cmd >> 23) & 0x3f) {
293 return 1; /* MI_NOOP */
295 return 1; /* MI_FLUSH */
297 return 0; /* disallow everything else */
301 return 0; /* reserved */
303 return (cmd & 0xff) + 2; /* 2d commands */
305 if (((cmd >> 24) & 0x1f) <= 0x18)
308 switch ((cmd >> 24) & 0x1f) {
312 switch ((cmd >> 16) & 0xff) {
314 return (cmd & 0x1f) + 2;
316 return (cmd & 0xf) + 2;
318 return (cmd & 0xffff) + 2;
322 return (cmd & 0xffff) + 1;
326 if ((cmd & (1 << 23)) == 0) /* inline vertices */
327 return (cmd & 0x1ffff) + 2;
328 else if (cmd & (1 << 17)) /* indirect random */
329 if ((cmd & 0xffff) == 0)
330 return 0; /* unknown length, too hard */
332 return (((cmd & 0xffff) + 1) / 2) + 1;
334 return 2; /* indirect sequential */
345 static int validate_cmd(int cmd)
347 int ret = do_validate_cmd(cmd);
349 /* printk("validate_cmd( %x ): %d\n", cmd, ret); */
354 static int i915_emit_cmds(struct drm_device *dev, int __user *buffer,
357 drm_i915_private_t *dev_priv = dev->dev_private;
361 if ((dwords+1) * sizeof(int) >= dev_priv->ring.Size - 8)
364 BEGIN_LP_RING((dwords+1)&~1);
366 for (i = 0; i < dwords;) {
369 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i], sizeof(cmd)))
372 if ((sz = validate_cmd(cmd)) == 0 || i + sz > dwords)
378 if (DRM_COPY_FROM_USER_UNCHECKED(&cmd, &buffer[i],
394 int i915_emit_box(struct drm_device * dev,
395 struct drm_clip_rect __user * boxes,
396 int i, int DR1, int DR4)
398 drm_i915_private_t *dev_priv = dev->dev_private;
399 struct drm_clip_rect box;
402 if (DRM_COPY_FROM_USER_UNCHECKED(&box, &boxes[i], sizeof(box))) {
406 if (box.y2 <= box.y1 || box.x2 <= box.x1 || box.y2 <= 0 || box.x2 <= 0) {
407 DRM_ERROR("Bad box %d,%d..%d,%d\n",
408 box.x1, box.y1, box.x2, box.y2);
414 OUT_RING(GFX_OP_DRAWRECT_INFO_I965);
415 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
416 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
421 OUT_RING(GFX_OP_DRAWRECT_INFO);
423 OUT_RING((box.x1 & 0xffff) | (box.y1 << 16));
424 OUT_RING(((box.x2 - 1) & 0xffff) | ((box.y2 - 1) << 16));
433 /* XXX: Emitting the counter should really be moved to part of the IRQ
434 * emit. For now, do it in both places:
437 static void i915_emit_breadcrumb(struct drm_device *dev)
439 drm_i915_private_t *dev_priv = dev->dev_private;
442 if (++dev_priv->counter > 0x7FFFFFFFUL)
443 dev_priv->counter = 0;
444 if (dev_priv->sarea_priv)
445 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
448 OUT_RING(MI_STORE_DWORD_INDEX);
449 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
450 OUT_RING(dev_priv->counter);
455 static int i915_dispatch_cmdbuffer(struct drm_device * dev,
456 drm_i915_cmdbuffer_t * cmd)
458 int nbox = cmd->num_cliprects;
459 int i = 0, count, ret;
462 DRM_ERROR("alignment\n");
466 i915_kernel_lost_context(dev);
468 count = nbox ? nbox : 1;
470 for (i = 0; i < count; i++) {
472 ret = i915_emit_box(dev, cmd->cliprects, i,
478 ret = i915_emit_cmds(dev, (int __user *)cmd->buf, cmd->sz / 4);
483 i915_emit_breadcrumb(dev);
487 static int i915_dispatch_batchbuffer(struct drm_device * dev,
488 drm_i915_batchbuffer_t * batch)
490 drm_i915_private_t *dev_priv = dev->dev_private;
491 struct drm_clip_rect __user *boxes = batch->cliprects;
492 int nbox = batch->num_cliprects;
496 if ((batch->start | batch->used) & 0x7) {
497 DRM_ERROR("alignment\n");
501 i915_kernel_lost_context(dev);
503 count = nbox ? nbox : 1;
505 for (i = 0; i < count; i++) {
507 int ret = i915_emit_box(dev, boxes, i,
508 batch->DR1, batch->DR4);
513 if (!IS_I830(dev) && !IS_845G(dev)) {
516 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6) | MI_BATCH_NON_SECURE_I965);
517 OUT_RING(batch->start);
519 OUT_RING(MI_BATCH_BUFFER_START | (2 << 6));
520 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
525 OUT_RING(MI_BATCH_BUFFER);
526 OUT_RING(batch->start | MI_BATCH_NON_SECURE);
527 OUT_RING(batch->start + batch->used - 4);
533 i915_emit_breadcrumb(dev);
538 static int i915_dispatch_flip(struct drm_device * dev)
540 drm_i915_private_t *dev_priv = dev->dev_private;
543 if (!dev_priv->sarea_priv)
546 DRM_DEBUG("%s: page=%d pfCurrentPage=%d\n",
548 dev_priv->current_page,
549 dev_priv->sarea_priv->pf_current_page);
551 i915_kernel_lost_context(dev);
554 OUT_RING(MI_FLUSH | MI_READ_FLUSH);
559 OUT_RING(CMD_OP_DISPLAYBUFFER_INFO | ASYNC_FLIP);
561 if (dev_priv->current_page == 0) {
562 OUT_RING(dev_priv->back_offset);
563 dev_priv->current_page = 1;
565 OUT_RING(dev_priv->front_offset);
566 dev_priv->current_page = 0;
572 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_PLANE_A_FLIP);
576 if (++dev_priv->counter > 0x7FFFFFFFUL)
577 dev_priv->counter = 0;
578 if (dev_priv->sarea_priv)
579 dev_priv->sarea_priv->last_enqueue = dev_priv->counter;
582 OUT_RING(MI_STORE_DWORD_INDEX);
583 OUT_RING(I915_BREADCRUMB_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
584 OUT_RING(dev_priv->counter);
588 dev_priv->sarea_priv->pf_current_page = dev_priv->current_page;
592 static int i915_quiescent(struct drm_device * dev)
594 drm_i915_private_t *dev_priv = dev->dev_private;
596 i915_kernel_lost_context(dev);
597 return i915_wait_ring(dev, dev_priv->ring.Size - 8, __func__);
600 static int i915_flush_ioctl(struct drm_device *dev, void *data,
601 struct drm_file *file_priv)
605 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
607 ret = i915_quiescent(dev);
612 static int i915_batchbuffer(struct drm_device *dev, void *data,
613 struct drm_file *file_priv)
615 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
616 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
617 dev_priv->sarea_priv;
618 drm_i915_batchbuffer_t *batch = data;
622 if (!dev_priv->allow_batchbuffer) {
623 DRM_ERROR("Batchbuffer ioctl disabled\n");
627 DRM_DEBUG("i915 batchbuffer, start %x used %d cliprects %d\n",
628 batch->start, batch->used, batch->num_cliprects);
630 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
633 cliplen = batch->num_cliprects * sizeof(struct drm_clip_rect);
634 if (batch->num_cliprects && DRM_VERIFYAREA_READ(batch->cliprects,
639 if (batch->num_cliprects) {
640 ret = vslock(batch->cliprects, cliplen);
642 DRM_ERROR("Fault wiring cliprects\n");
648 ret = i915_dispatch_batchbuffer(dev, batch);
650 if (batch->num_cliprects)
651 vsunlock(batch->cliprects, cliplen);
656 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
661 static int i915_cmdbuffer(struct drm_device *dev, void *data,
662 struct drm_file *file_priv)
664 drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
665 drm_i915_sarea_t *sarea_priv = (drm_i915_sarea_t *)
666 dev_priv->sarea_priv;
667 drm_i915_cmdbuffer_t *cmdbuf = data;
671 DRM_DEBUG("i915 cmdbuffer, buf %p sz %d cliprects %d\n",
672 cmdbuf->buf, cmdbuf->sz, cmdbuf->num_cliprects);
674 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
677 cliplen = cmdbuf->num_cliprects * sizeof(struct drm_clip_rect);
678 if (cmdbuf->num_cliprects && DRM_VERIFYAREA_READ(cmdbuf->cliprects,
680 DRM_ERROR("Fault accessing cliprects\n");
684 if (cmdbuf->num_cliprects) {
685 ret = vslock(cmdbuf->cliprects, cliplen);
687 DRM_ERROR("Fault wiring cliprects\n");
691 ret = vslock(cmdbuf->buf, cmdbuf->sz);
693 vsunlock(cmdbuf->cliprects, cliplen);
694 DRM_ERROR("Fault wiring cmds\n");
700 ret = i915_dispatch_cmdbuffer(dev, cmdbuf);
702 if (cmdbuf->num_cliprects) {
703 vsunlock(cmdbuf->buf, cmdbuf->sz);
704 vsunlock(cmdbuf->cliprects, cliplen);
708 DRM_ERROR("i915_dispatch_cmdbuffer failed\n");
713 sarea_priv->last_dispatch = READ_BREADCRUMB(dev_priv);
717 static int i915_flip_bufs(struct drm_device *dev, void *data,
718 struct drm_file *file_priv)
722 DRM_DEBUG("%s\n", __func__);
724 RING_LOCK_TEST_WITH_RETURN(dev, file_priv);
726 ret = i915_dispatch_flip(dev);
731 static int i915_getparam(struct drm_device *dev, void *data,
732 struct drm_file *file_priv)
734 drm_i915_private_t *dev_priv = dev->dev_private;
735 drm_i915_getparam_t *param = data;
739 DRM_ERROR("called with no initialization\n");
743 switch (param->param) {
744 case I915_PARAM_IRQ_ACTIVE:
745 value = dev->irq_enabled ? 1 : 0;
747 case I915_PARAM_ALLOW_BATCHBUFFER:
748 value = dev_priv->allow_batchbuffer ? 1 : 0;
750 case I915_PARAM_LAST_DISPATCH:
751 value = READ_BREADCRUMB(dev_priv);
753 case I915_PARAM_CHIPSET_ID:
754 value = dev->pci_device;
756 case I915_PARAM_HAS_GEM:
757 /* We need to reset this to 1 once we have GEM */
761 DRM_DEBUG("Unknown parameter %d\n", param->param);
765 if (DRM_COPY_TO_USER(param->value, &value, sizeof(int))) {
766 DRM_ERROR("DRM_COPY_TO_USER failed\n");
773 static int i915_setparam(struct drm_device *dev, void *data,
774 struct drm_file *file_priv)
776 drm_i915_private_t *dev_priv = dev->dev_private;
777 drm_i915_setparam_t *param = data;
780 DRM_ERROR("called with no initialization\n");
784 switch (param->param) {
785 case I915_SETPARAM_USE_MI_BATCHBUFFER_START:
787 case I915_SETPARAM_TEX_LRU_LOG_GRANULARITY:
788 dev_priv->tex_lru_log_granularity = param->value;
790 case I915_SETPARAM_ALLOW_BATCHBUFFER:
791 dev_priv->allow_batchbuffer = param->value;
794 DRM_DEBUG("unknown parameter %d\n", param->param);
801 static int i915_set_status_page(struct drm_device *dev, void *data,
802 struct drm_file *file_priv)
804 drm_i915_private_t *dev_priv = dev->dev_private;
805 drm_i915_hws_addr_t *hws = data;
807 if (!I915_NEED_GFX_HWS(dev))
811 DRM_ERROR("called with no initialization\n");
815 DRM_DEBUG("set status page addr 0x%08x\n", (u32)hws->addr);
817 dev_priv->status_gfx_addr = hws->addr & (0x1ffff<<12);
819 dev_priv->hws_map.offset = dev->agp->base + hws->addr;
820 dev_priv->hws_map.size = 4*1024;
821 dev_priv->hws_map.type = 0;
822 dev_priv->hws_map.flags = 0;
823 dev_priv->hws_map.mtrr = 0;
825 drm_core_ioremap_wc(&dev_priv->hws_map, dev);
826 if (dev_priv->hws_map.virtual == NULL) {
827 i915_dma_cleanup(dev);
828 dev_priv->status_gfx_addr = 0;
829 DRM_ERROR("can not ioremap virtual address for"
830 " G33 hw status page\n");
833 dev_priv->hw_status_page = dev_priv->hws_map.virtual;
835 memset(dev_priv->hw_status_page, 0, PAGE_SIZE);
836 I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr);
837 DRM_DEBUG("load hws HWS_PGA with gfx mem 0x%x\n",
838 dev_priv->status_gfx_addr);
839 DRM_DEBUG("load hws at %p\n", dev_priv->hw_status_page);
843 int i915_driver_load(struct drm_device *dev, unsigned long flags)
845 struct drm_i915_private *dev_priv = dev->dev_private;
846 unsigned long base, size;
847 int ret = 0, mmio_bar = IS_I9XX(dev) ? 0 : 1;
849 /* i915 has 4 more counters */
851 dev->types[6] = _DRM_STAT_IRQ;
852 dev->types[7] = _DRM_STAT_PRIMARY;
853 dev->types[8] = _DRM_STAT_SECONDARY;
854 dev->types[9] = _DRM_STAT_DMA;
856 dev_priv = drm_alloc(sizeof(drm_i915_private_t), DRM_MEM_DRIVER);
857 if (dev_priv == NULL)
860 memset(dev_priv, 0, sizeof(drm_i915_private_t));
862 dev->dev_private = (void *)dev_priv;
865 /* Add register map (needed for suspend/resume) */
866 base = drm_get_resource_start(dev, mmio_bar);
867 size = drm_get_resource_len(dev, mmio_bar);
869 ret = drm_addmap(dev, base, size, _DRM_REGISTERS,
870 _DRM_KERNEL | _DRM_DRIVER, &dev_priv->mmio_map);
873 dev->driver->get_vblank_counter = g45_get_vblank_counter;
874 dev->max_vblank_count = 0xffffffff; /* 32 bits of frame count */
876 dev->driver->get_vblank_counter = i915_get_vblank_counter;
877 dev->max_vblank_count = 0x00ffffff; /* 24 bits of frame count */
884 if (!I915_NEED_GFX_HWS(dev)) {
885 ret = i915_init_phys_hws(dev);
887 drm_rmmap(dev, dev_priv->mmio_map);
888 drm_free(dev_priv, sizeof(struct drm_i915_private),
894 /* On the 945G/GM, the chipset reports the MSI capability on the
895 * integrated graphics even though the support isn't actually there
896 * according to the published specs. It doesn't appear to function
897 * correctly in testing on 945G.
898 * This may be a side effect of MSI having been made available for PEG
899 * and the registers being closely associated.
901 * According to chipset errata, on the 965GM, MSI interrupts may
904 if (!IS_I945G(dev) && !IS_I945GM(dev) && !IS_I965GM(dev))
905 if (pci_enable_msi(dev->pdev))
906 DRM_ERROR("failed to enable MSI\n");
908 intel_opregion_init(dev);
910 DRM_SPININIT(&dev_priv->user_irq_lock, "userirq");
911 dev_priv->user_irq_refcount = 0;
913 ret = drm_vblank_init(dev, I915_NUM_PIPE);
916 (void) i915_driver_unload(dev);
923 int i915_driver_unload(struct drm_device *dev)
925 struct drm_i915_private *dev_priv = dev->dev_private;
929 drm_rmmap(dev, dev_priv->mmio_map);
931 intel_opregion_free(dev);
933 DRM_SPINUNINIT(&dev_priv->user_irq_lock);
935 drm_free(dev->dev_private, sizeof(drm_i915_private_t),
941 int i915_driver_open(struct drm_device *dev, struct drm_file *file_priv)
943 struct drm_i915_file_private *i915_file_priv;
946 i915_file_priv = (struct drm_i915_file_private *)
947 drm_alloc(sizeof(*i915_file_priv), DRM_MEM_FILES);
952 file_priv->driver_priv = i915_file_priv;
954 i915_file_priv->mm.last_gem_seqno = 0;
955 i915_file_priv->mm.last_gem_throttle_seqno = 0;
960 void i915_driver_lastclose(struct drm_device * dev)
962 drm_i915_private_t *dev_priv = dev->dev_private;
967 i915_gem_lastclose(dev);
969 if (dev_priv->agp_heap)
970 i915_mem_takedown(&(dev_priv->agp_heap));
972 i915_dma_cleanup(dev);
975 void i915_driver_preclose(struct drm_device * dev, struct drm_file *file_priv)
977 drm_i915_private_t *dev_priv = dev->dev_private;
978 i915_mem_release(dev, file_priv, dev_priv->agp_heap);
981 void i915_driver_postclose(struct drm_device *dev, struct drm_file *file_priv)
983 struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv;
985 drm_free(i915_file_priv, sizeof(*i915_file_priv), DRM_MEM_FILES);
988 struct drm_ioctl_desc i915_ioctls[] = {
989 DRM_IOCTL_DEF(DRM_I915_INIT, i915_dma_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
990 DRM_IOCTL_DEF(DRM_I915_FLUSH, i915_flush_ioctl, DRM_AUTH),
991 DRM_IOCTL_DEF(DRM_I915_FLIP, i915_flip_bufs, DRM_AUTH),
992 DRM_IOCTL_DEF(DRM_I915_BATCHBUFFER, i915_batchbuffer, DRM_AUTH),
993 DRM_IOCTL_DEF(DRM_I915_IRQ_EMIT, i915_irq_emit, DRM_AUTH),
994 DRM_IOCTL_DEF(DRM_I915_IRQ_WAIT, i915_irq_wait, DRM_AUTH),
995 DRM_IOCTL_DEF(DRM_I915_GETPARAM, i915_getparam, DRM_AUTH),
996 DRM_IOCTL_DEF(DRM_I915_SETPARAM, i915_setparam, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
997 DRM_IOCTL_DEF(DRM_I915_ALLOC, i915_mem_alloc, DRM_AUTH),
998 DRM_IOCTL_DEF(DRM_I915_FREE, i915_mem_free, DRM_AUTH),
999 DRM_IOCTL_DEF(DRM_I915_INIT_HEAP, i915_mem_init_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1000 DRM_IOCTL_DEF(DRM_I915_CMDBUFFER, i915_cmdbuffer, DRM_AUTH),
1001 DRM_IOCTL_DEF(DRM_I915_DESTROY_HEAP, i915_mem_destroy_heap, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1002 DRM_IOCTL_DEF(DRM_I915_SET_VBLANK_PIPE, i915_vblank_pipe_set, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY ),
1003 DRM_IOCTL_DEF(DRM_I915_GET_VBLANK_PIPE, i915_vblank_pipe_get, DRM_AUTH ),
1004 DRM_IOCTL_DEF(DRM_I915_VBLANK_SWAP, i915_vblank_swap, DRM_AUTH),
1005 DRM_IOCTL_DEF(DRM_I915_HWS_ADDR, i915_set_status_page, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1006 #ifdef I915_HAVE_GEM
1007 DRM_IOCTL_DEF(DRM_I915_GEM_INIT, i915_gem_init_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1008 DRM_IOCTL_DEF(DRM_I915_GEM_EXECBUFFER, i915_gem_execbuffer, DRM_AUTH),
1009 DRM_IOCTL_DEF(DRM_I915_GEM_PIN, i915_gem_pin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1010 DRM_IOCTL_DEF(DRM_I915_GEM_UNPIN, i915_gem_unpin_ioctl, DRM_AUTH|DRM_ROOT_ONLY),
1011 DRM_IOCTL_DEF(DRM_I915_GEM_BUSY, i915_gem_busy_ioctl, DRM_AUTH),
1012 DRM_IOCTL_DEF(DRM_I915_GEM_THROTTLE, i915_gem_throttle_ioctl, DRM_AUTH),
1013 DRM_IOCTL_DEF(DRM_I915_GEM_ENTERVT, i915_gem_entervt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1014 DRM_IOCTL_DEF(DRM_I915_GEM_LEAVEVT, i915_gem_leavevt_ioctl, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1015 DRM_IOCTL_DEF(DRM_I915_GEM_CREATE, i915_gem_create_ioctl, 0),
1016 DRM_IOCTL_DEF(DRM_I915_GEM_PREAD, i915_gem_pread_ioctl, 0),
1017 DRM_IOCTL_DEF(DRM_I915_GEM_PWRITE, i915_gem_pwrite_ioctl, 0),
1018 DRM_IOCTL_DEF(DRM_I915_GEM_MMAP, i915_gem_mmap_ioctl, 0),
1019 DRM_IOCTL_DEF(DRM_I915_GEM_SET_DOMAIN, i915_gem_set_domain_ioctl, 0),
1020 DRM_IOCTL_DEF(DRM_I915_GEM_SW_FINISH, i915_gem_sw_finish_ioctl, 0),
1021 DRM_IOCTL_DEF(DRM_I915_GEM_SET_TILING, i915_gem_set_tiling, 0),
1022 DRM_IOCTL_DEF(DRM_I915_GEM_GET_TILING, i915_gem_get_tiling, 0),
1026 int i915_max_ioctl = DRM_ARRAY_SIZE(i915_ioctls);
1029 * Determine if the device really is AGP or not.
1031 * All Intel graphics chipsets are treated as AGP, even if they are really
1034 * \param dev The device to be tested.
1037 * A value of 1 is always retured to indictate every i9x5 is AGP.
1039 int i915_driver_device_is_agp(struct drm_device * dev)