1 /* mga_drm.h -- Public header for the Matrox g200/g400 driver -*- linux-c -*-
2 * Created: Tue Jan 25 01:50:01 1999 by jhartmann@precisioninsight.com
4 * Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
28 * Jeff Hartmann <jhartmann@valinux.com>
29 * Keith Whitwell <keith@tungstengraphics.com>
32 * Gareth Hughes <gareth@valinux.com>
35 #include <sys/cdefs.h>
36 __FBSDID("$FreeBSD$");
41 /* WARNING: If you change any of these defines, make sure to change the
42 * defines in the Xserver file (mga_sarea.h)
45 #ifndef __MGA_SAREA_DEFINES__
46 #define __MGA_SAREA_DEFINES__
50 #define MGA_F 0x1 /* fog */
51 #define MGA_A 0x2 /* alpha */
52 #define MGA_S 0x4 /* specular */
53 #define MGA_T2 0x8 /* multitexture */
55 #define MGA_WARP_TGZ 0
56 #define MGA_WARP_TGZF (MGA_F)
57 #define MGA_WARP_TGZA (MGA_A)
58 #define MGA_WARP_TGZAF (MGA_F|MGA_A)
59 #define MGA_WARP_TGZS (MGA_S)
60 #define MGA_WARP_TGZSF (MGA_S|MGA_F)
61 #define MGA_WARP_TGZSA (MGA_S|MGA_A)
62 #define MGA_WARP_TGZSAF (MGA_S|MGA_F|MGA_A)
63 #define MGA_WARP_T2GZ (MGA_T2)
64 #define MGA_WARP_T2GZF (MGA_T2|MGA_F)
65 #define MGA_WARP_T2GZA (MGA_T2|MGA_A)
66 #define MGA_WARP_T2GZAF (MGA_T2|MGA_A|MGA_F)
67 #define MGA_WARP_T2GZS (MGA_T2|MGA_S)
68 #define MGA_WARP_T2GZSF (MGA_T2|MGA_S|MGA_F)
69 #define MGA_WARP_T2GZSA (MGA_T2|MGA_S|MGA_A)
70 #define MGA_WARP_T2GZSAF (MGA_T2|MGA_S|MGA_F|MGA_A)
72 #define MGA_MAX_G200_PIPES 8 /* no multitex */
73 #define MGA_MAX_G400_PIPES 16
74 #define MGA_MAX_WARP_PIPES MGA_MAX_G400_PIPES
75 #define MGA_WARP_UCODE_SIZE 32768 /* in bytes */
77 #define MGA_CARD_TYPE_G200 1
78 #define MGA_CARD_TYPE_G400 2
79 #define MGA_CARD_TYPE_G450 3 /* not currently used */
80 #define MGA_CARD_TYPE_G550 4
86 /* What needs to be changed for the current vertex dma buffer?
88 #define MGA_UPLOAD_CONTEXT 0x1
89 #define MGA_UPLOAD_TEX0 0x2
90 #define MGA_UPLOAD_TEX1 0x4
91 #define MGA_UPLOAD_PIPE 0x8
92 #define MGA_UPLOAD_TEX0IMAGE 0x10 /* handled client-side */
93 #define MGA_UPLOAD_TEX1IMAGE 0x20 /* handled client-side */
94 #define MGA_UPLOAD_2D 0x40
95 #define MGA_WAIT_AGE 0x80 /* handled client-side */
96 #define MGA_UPLOAD_CLIPRECTS 0x100 /* handled client-side */
98 #define MGA_DMA_FLUSH 0x200 /* set when someone gets the lock
102 /* 32 buffers of 64k each, total 2 meg.
104 #define MGA_BUFFER_SIZE (1 << 16)
105 #define MGA_NUM_BUFFERS 128
107 /* Keep these small for testing.
109 #define MGA_NR_SAREA_CLIPRECTS 8
111 /* 2 heaps (1 for card, 1 for agp), each divided into upto 128
112 * regions, subject to a minimum region size of (1<<16) == 64k.
114 * Clients may subdivide regions internally, but when sharing between
115 * clients, the region size is the minimum granularity.
118 #define MGA_CARD_HEAP 0
119 #define MGA_AGP_HEAP 1
120 #define MGA_NR_TEX_HEAPS 2
121 #define MGA_NR_TEX_REGIONS 16
122 #define MGA_LOG_MIN_TEX_REGION_SIZE 16
124 #define DRM_MGA_IDLE_RETRY 2048
126 #endif /* __MGA_SAREA_DEFINES__ */
128 /* Setup registers for 3D context
132 unsigned int maccess;
135 unsigned int alphactrl;
136 unsigned int fogcolor;
138 unsigned int tdualstage0;
139 unsigned int tdualstage1;
141 unsigned int stencil;
142 unsigned int stencilctl;
143 } drm_mga_context_regs_t;
145 /* Setup registers for 2D, X server
149 } drm_mga_server_regs_t;
151 /* Setup registers for each texture unit
155 unsigned int texctl2;
156 unsigned int texfilter;
157 unsigned int texbordercol;
159 unsigned int texwidth;
160 unsigned int texheight;
161 unsigned int texorg1;
162 unsigned int texorg2;
163 unsigned int texorg3;
164 unsigned int texorg4;
165 } drm_mga_texture_regs_t;
167 /* General aging mechanism
170 unsigned int head; /* Position of head pointer */
171 unsigned int wrap; /* Primary DMA wrap count */
174 typedef struct _drm_mga_sarea {
175 /* The channel for communication of state information to the kernel
176 * on firing a vertex dma buffer.
178 drm_mga_context_regs_t context_state;
179 drm_mga_server_regs_t server_state;
180 drm_mga_texture_regs_t tex_state[2];
181 unsigned int warp_pipe;
183 unsigned int vertsize;
185 /* The current cliprects, or a subset thereof.
187 struct drm_clip_rect boxes[MGA_NR_SAREA_CLIPRECTS];
190 /* Information about the most recently used 3d drawable. The
191 * client fills in the req_* fields, the server fills in the
192 * exported_ fields and puts the cliprects into boxes, above.
194 * The client clears the exported_drawable field before
195 * clobbering the boxes data.
197 unsigned int req_drawable; /* the X drawable id */
198 unsigned int req_draw_buffer; /* MGA_FRONT or MGA_BACK */
200 unsigned int exported_drawable;
201 unsigned int exported_index;
202 unsigned int exported_stamp;
203 unsigned int exported_buffers;
204 unsigned int exported_nfront;
205 unsigned int exported_nback;
206 int exported_back_x, exported_front_x, exported_w;
207 int exported_back_y, exported_front_y, exported_h;
208 struct drm_clip_rect exported_boxes[MGA_NR_SAREA_CLIPRECTS];
210 /* Counters for aging textures and for client-side throttling.
212 unsigned int status[4];
213 unsigned int last_wrap;
215 drm_mga_age_t last_frame;
216 unsigned int last_enqueue; /* last time a buffer was enqueued */
217 unsigned int last_dispatch; /* age of the most recently dispatched buffer */
218 unsigned int last_quiescent; /* */
220 /* LRU lists for texture memory in agp space and on the card.
222 struct drm_tex_region texList[MGA_NR_TEX_HEAPS][MGA_NR_TEX_REGIONS + 1];
223 unsigned int texAge[MGA_NR_TEX_HEAPS];
225 /* Mechanism to validate card state.
231 /* MGA specific ioctls
232 * The device specific ioctl range is 0x40 to 0x79.
234 #define DRM_MGA_INIT 0x00
235 #define DRM_MGA_FLUSH 0x01
236 #define DRM_MGA_RESET 0x02
237 #define DRM_MGA_SWAP 0x03
238 #define DRM_MGA_CLEAR 0x04
239 #define DRM_MGA_VERTEX 0x05
240 #define DRM_MGA_INDICES 0x06
241 #define DRM_MGA_ILOAD 0x07
242 #define DRM_MGA_BLIT 0x08
243 #define DRM_MGA_GETPARAM 0x09
246 * ioctls for operating on fences.
248 #define DRM_MGA_SET_FENCE 0x0a
249 #define DRM_MGA_WAIT_FENCE 0x0b
250 #define DRM_MGA_DMA_BOOTSTRAP 0x0c
253 #define DRM_IOCTL_MGA_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INIT, drm_mga_init_t)
254 #define DRM_IOCTL_MGA_FLUSH DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_FLUSH, drm_lock_t)
255 #define DRM_IOCTL_MGA_RESET DRM_IO( DRM_COMMAND_BASE + DRM_MGA_RESET)
256 #define DRM_IOCTL_MGA_SWAP DRM_IO( DRM_COMMAND_BASE + DRM_MGA_SWAP)
257 #define DRM_IOCTL_MGA_CLEAR DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_CLEAR, drm_mga_clear_t)
258 #define DRM_IOCTL_MGA_VERTEX DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_VERTEX, drm_mga_vertex_t)
259 #define DRM_IOCTL_MGA_INDICES DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_INDICES, drm_mga_indices_t)
260 #define DRM_IOCTL_MGA_ILOAD DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_ILOAD, drm_mga_iload_t)
261 #define DRM_IOCTL_MGA_BLIT DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_BLIT, drm_mga_blit_t)
262 #define DRM_IOCTL_MGA_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_GETPARAM, drm_mga_getparam_t)
263 #define DRM_IOCTL_MGA_SET_FENCE DRM_IOW( DRM_COMMAND_BASE + DRM_MGA_SET_FENCE, uint32_t)
264 #define DRM_IOCTL_MGA_WAIT_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_WAIT_FENCE, uint32_t)
265 #define DRM_IOCTL_MGA_DMA_BOOTSTRAP DRM_IOWR(DRM_COMMAND_BASE + DRM_MGA_DMA_BOOTSTRAP, drm_mga_dma_bootstrap_t)
267 typedef struct _drm_mga_warp_index {
269 unsigned long phys_addr;
271 } drm_mga_warp_index_t;
273 typedef struct drm_mga_init {
276 MGA_CLEANUP_DMA = 0x02
279 unsigned long sarea_priv_offset;
284 unsigned int maccess;
287 unsigned int front_offset, front_pitch;
288 unsigned int back_offset, back_pitch;
290 unsigned int depth_cpp;
291 unsigned int depth_offset, depth_pitch;
293 unsigned int texture_offset[MGA_NR_TEX_HEAPS];
294 unsigned int texture_size[MGA_NR_TEX_HEAPS];
296 unsigned long fb_offset;
297 unsigned long mmio_offset;
298 unsigned long status_offset;
299 unsigned long warp_offset;
300 unsigned long primary_offset;
301 unsigned long buffers_offset;
305 typedef struct drm_mga_dma_bootstrap {
307 * \name AGP texture region
309 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, these fields will
310 * be filled in with the actual AGP texture settings.
313 * If these fields are non-zero, but dma_mga_dma_bootstrap::agp_mode
314 * is zero, it means that PCI memory (most likely through the use of
315 * an IOMMU) is being used for "AGP" textures.
318 unsigned long texture_handle; /**< Handle used to map AGP textures. */
319 uint32_t texture_size; /**< Size of the AGP texture region. */
324 * Requested size of the primary DMA region.
326 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
327 * filled in with the actual AGP mode. If AGP was not available
329 uint32_t primary_size;
333 * Requested number of secondary DMA buffers.
335 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
336 * filled in with the actual number of secondary DMA buffers
337 * allocated. Particularly when PCI DMA is used, this may be
338 * (subtantially) less than the number requested.
340 uint32_t secondary_bin_count;
344 * Requested size of each secondary DMA buffer.
346 * While the kernel \b is free to reduce
347 * dma_mga_dma_bootstrap::secondary_bin_count, it is \b not allowed
348 * to reduce dma_mga_dma_bootstrap::secondary_bin_size.
350 uint32_t secondary_bin_size;
354 * Bit-wise mask of AGPSTAT2_* values. Currently only \c AGPSTAT2_1X,
355 * \c AGPSTAT2_2X, and \c AGPSTAT2_4X are supported. If this value is
356 * zero, it means that PCI DMA should be used, even if AGP is
359 * On return from the DRM_MGA_DMA_BOOTSTRAP ioctl, this field will be
360 * filled in with the actual AGP mode. If AGP was not available
361 * (i.e., PCI DMA was used), this value will be zero.
367 * Desired AGP GART size, measured in megabytes.
370 } drm_mga_dma_bootstrap_t;
372 typedef struct drm_mga_clear {
374 unsigned int clear_color;
375 unsigned int clear_depth;
376 unsigned int color_mask;
377 unsigned int depth_mask;
380 typedef struct drm_mga_vertex {
381 int idx; /* buffer to queue */
382 int used; /* bytes in use */
383 int discard; /* client finished with buffer? */
386 typedef struct drm_mga_indices {
387 int idx; /* buffer to queue */
390 int discard; /* client finished with buffer? */
393 typedef struct drm_mga_iload {
399 typedef struct _drm_mga_blit {
400 unsigned int planemask;
403 int src_pitch, dst_pitch;
404 int delta_sx, delta_sy;
405 int delta_dx, delta_dy;
406 int height, ydir; /* flip image vertically */
407 int source_pitch, dest_pitch;
410 /* 3.1: An ioctl to get parameters that aren't available to the 3d
411 * client any other way.
413 #define MGA_PARAM_IRQ_NR 1
415 /* 3.2: Query the actual card type. The DDX only distinguishes between
416 * G200 chips and non-G200 chips, which it calls G400. It turns out that
417 * there are some very sublte differences between the G4x0 chips and the G550
418 * chips. Using this parameter query, a client-side driver can detect the
419 * difference between a G4x0 and a G550.
421 #define MGA_PARAM_CARD_TYPE 2
423 typedef struct drm_mga_getparam {
426 } drm_mga_getparam_t;