1 /* r300_cmdbuf.c -- Command buffer emission for R300 -*- linux-c -*-
3 * Copyright (C) The Weather Channel, Inc. 2002.
4 * Copyright (C) 2004 Nicolai Haehnle.
7 * The Weather Channel (TM) funded Tungsten Graphics to develop the
8 * initial release of the Radeon 8500 driver under the XFree86 license.
9 * This notice must be preserved.
11 * Permission is hereby granted, free of charge, to any person obtaining a
12 * copy of this software and associated documentation files (the "Software"),
13 * to deal in the Software without restriction, including without limitation
14 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
15 * and/or sell copies of the Software, and to permit persons to whom the
16 * Software is furnished to do so, subject to the following conditions:
18 * The above copyright notice and this permission notice (including the next
19 * paragraph) shall be included in all copies or substantial portions of the
22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
25 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
26 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
27 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
28 * DEALINGS IN THE SOFTWARE.
31 * Nicolai Haehnle <prefect_@gmx.net>
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "dev/drm/drmP.h"
38 #include "dev/drm/drm.h"
39 #include "dev/drm/radeon_drm.h"
40 #include "dev/drm/radeon_drv.h"
41 #include "dev/drm/r300_reg.h"
43 #define R300_SIMULTANEOUS_CLIPRECTS 4
45 /* Values for R300_RE_CLIPRECT_CNTL depending on the number of cliprects
47 static const int r300_cliprect_cntl[4] = {
55 * Emit up to R300_SIMULTANEOUS_CLIPRECTS cliprects from the given command
56 * buffer, starting with index n.
58 static int r300_emit_cliprects(drm_radeon_private_t *dev_priv,
59 drm_radeon_kcmd_buffer_t *cmdbuf, int n)
61 struct drm_clip_rect box;
66 nr = cmdbuf->nbox - n;
67 if (nr > R300_SIMULTANEOUS_CLIPRECTS)
68 nr = R300_SIMULTANEOUS_CLIPRECTS;
70 DRM_DEBUG("%i cliprects\n", nr);
73 BEGIN_RING(6 + nr * 2);
74 OUT_RING(CP_PACKET0(R300_RE_CLIPRECT_TL_0, nr * 2 - 1));
76 for (i = 0; i < nr; ++i) {
77 if (DRM_COPY_FROM_USER_UNCHECKED
78 (&box, &cmdbuf->boxes[n + i], sizeof(box))) {
79 DRM_ERROR("copy cliprect faulted\n");
83 box.x2--; /* Hardware expects inclusive bottom-right corner */
86 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
96 box.x1 = (box.x1 + R300_CLIPRECT_OFFSET) &
98 box.y1 = (box.y1 + R300_CLIPRECT_OFFSET) &
100 box.x2 = (box.x2 + R300_CLIPRECT_OFFSET) &
102 box.y2 = (box.y2 + R300_CLIPRECT_OFFSET) &
106 OUT_RING((box.x1 << R300_CLIPRECT_X_SHIFT) |
107 (box.y1 << R300_CLIPRECT_Y_SHIFT));
108 OUT_RING((box.x2 << R300_CLIPRECT_X_SHIFT) |
109 (box.y2 << R300_CLIPRECT_Y_SHIFT));
113 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, r300_cliprect_cntl[nr - 1]);
115 /* TODO/SECURITY: Force scissors to a safe value, otherwise the
116 * client might be able to trample over memory.
117 * The impact should be very limited, but I'd rather be safe than
120 OUT_RING(CP_PACKET0(R300_RE_SCISSORS_TL, 1));
122 OUT_RING(R300_SCISSORS_X_MASK | R300_SCISSORS_Y_MASK);
125 /* Why we allow zero cliprect rendering:
126 * There are some commands in a command buffer that must be submitted
127 * even when there are no cliprects, e.g. DMA buffer discard
128 * or state setting (though state setting could be avoided by
129 * simulating a loss of context).
131 * Now since the cmdbuf interface is so chaotic right now (and is
132 * bound to remain that way for a bit until things settle down),
133 * it is basically impossible to filter out the commands that are
134 * necessary and those that aren't.
136 * So I choose the safe way and don't do any filtering at all;
137 * instead, I simply set up the engine so that all rendering
138 * can't produce any fragments.
141 OUT_RING_REG(R300_RE_CLIPRECT_CNTL, 0);
145 /* flus cache and wait idle clean after cliprect change */
147 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
148 OUT_RING(R300_RB3D_DC_FLUSH);
151 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
152 OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
155 dev_priv->track_flush |= RADEON_FLUSH_EMITED;
160 static u8 r300_reg_flags[0x10000 >> 2];
162 void r300_init_reg_flags(struct drm_device *dev)
165 drm_radeon_private_t *dev_priv = dev->dev_private;
167 memset(r300_reg_flags, 0, 0x10000 >> 2);
168 #define ADD_RANGE_MARK(reg, count,mark) \
169 for(i=((reg)>>2);i<((reg)>>2)+(count);i++)\
170 r300_reg_flags[i]|=(mark);
173 #define MARK_CHECK_OFFSET 2
175 #define ADD_RANGE(reg, count) ADD_RANGE_MARK(reg, count, MARK_SAFE)
177 /* these match cmducs() command in r300_driver/r300/r300_cmdbuf.c */
178 ADD_RANGE(R300_SE_VPORT_XSCALE, 6);
179 ADD_RANGE(R300_VAP_CNTL, 1);
180 ADD_RANGE(R300_SE_VTE_CNTL, 2);
181 ADD_RANGE(0x2134, 2);
182 ADD_RANGE(R300_VAP_CNTL_STATUS, 1);
183 ADD_RANGE(R300_VAP_INPUT_CNTL_0, 2);
184 ADD_RANGE(0x21DC, 1);
185 ADD_RANGE(R300_VAP_UNKNOWN_221C, 1);
186 ADD_RANGE(R300_VAP_CLIP_X_0, 4);
187 ADD_RANGE(R300_VAP_PVS_STATE_FLUSH_REG, 1);
188 ADD_RANGE(R300_VAP_UNKNOWN_2288, 1);
189 ADD_RANGE(R300_VAP_OUTPUT_VTX_FMT_0, 2);
190 ADD_RANGE(R300_VAP_PVS_CNTL_1, 3);
191 ADD_RANGE(R300_GB_ENABLE, 1);
192 ADD_RANGE(R300_GB_MSPOS0, 5);
193 ADD_RANGE(R300_TX_INVALTAGS, 1);
194 ADD_RANGE(R300_TX_ENABLE, 1);
195 ADD_RANGE(0x4200, 4);
196 ADD_RANGE(0x4214, 1);
197 ADD_RANGE(R300_RE_POINTSIZE, 1);
198 ADD_RANGE(0x4230, 3);
199 ADD_RANGE(R300_RE_LINE_CNT, 1);
200 ADD_RANGE(R300_RE_UNK4238, 1);
201 ADD_RANGE(0x4260, 3);
202 ADD_RANGE(R300_RE_SHADE, 4);
203 ADD_RANGE(R300_RE_POLYGON_MODE, 5);
204 ADD_RANGE(R300_RE_ZBIAS_CNTL, 1);
205 ADD_RANGE(R300_RE_ZBIAS_T_FACTOR, 4);
206 ADD_RANGE(R300_RE_OCCLUSION_CNTL, 1);
207 ADD_RANGE(R300_RE_CULL_CNTL, 1);
208 ADD_RANGE(0x42C0, 2);
209 ADD_RANGE(R300_RS_CNTL_0, 2);
211 ADD_RANGE(R300_SU_REG_DEST, 1);
212 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV530)
213 ADD_RANGE(RV530_FG_ZBREG_DEST, 1);
215 ADD_RANGE(R300_SC_HYPERZ, 2);
216 ADD_RANGE(0x43E8, 1);
218 ADD_RANGE(0x46A4, 5);
220 ADD_RANGE(R300_RE_FOG_STATE, 1);
221 ADD_RANGE(R300_FOG_COLOR_R, 3);
222 ADD_RANGE(R300_PP_ALPHA_TEST, 2);
223 ADD_RANGE(0x4BD8, 1);
224 ADD_RANGE(R300_PFS_PARAM_0_X, 64);
225 ADD_RANGE(0x4E00, 1);
226 ADD_RANGE(R300_RB3D_CBLEND, 2);
227 ADD_RANGE(R300_RB3D_COLORMASK, 1);
228 ADD_RANGE(R300_RB3D_BLEND_COLOR, 3);
229 ADD_RANGE_MARK(R300_RB3D_COLOROFFSET0, 1, MARK_CHECK_OFFSET); /* check offset */
230 ADD_RANGE(R300_RB3D_COLORPITCH0, 1);
231 ADD_RANGE(0x4E50, 9);
232 ADD_RANGE(0x4E88, 1);
233 ADD_RANGE(0x4EA0, 2);
234 ADD_RANGE(R300_ZB_CNTL, 3);
235 ADD_RANGE(R300_ZB_FORMAT, 4);
236 ADD_RANGE_MARK(R300_ZB_DEPTHOFFSET, 1, MARK_CHECK_OFFSET); /* check offset */
237 ADD_RANGE(R300_ZB_DEPTHPITCH, 1);
238 ADD_RANGE(R300_ZB_DEPTHCLEARVALUE, 1);
239 ADD_RANGE(R300_ZB_ZMASK_OFFSET, 5);
240 ADD_RANGE(R300_ZB_HIZ_OFFSET, 5);
241 ADD_RANGE(R300_ZB_ZPASS_DATA, 1);
242 ADD_RANGE_MARK(R300_ZB_ZPASS_ADDR, 1, MARK_CHECK_OFFSET); /* check offset */
243 ADD_RANGE(R300_ZB_DEPTHXY_OFFSET, 1)
245 ADD_RANGE(R300_TX_FILTER_0, 16);
246 ADD_RANGE(R300_TX_FILTER1_0, 16);
247 ADD_RANGE(R300_TX_SIZE_0, 16);
248 ADD_RANGE(R300_TX_FORMAT_0, 16);
249 ADD_RANGE(R300_TX_PITCH_0, 16);
250 /* Texture offset is dangerous and needs more checking */
251 ADD_RANGE_MARK(R300_TX_OFFSET_0, 16, MARK_CHECK_OFFSET);
252 ADD_RANGE(R300_TX_CHROMA_KEY_0, 16);
253 ADD_RANGE(R300_TX_BORDER_COLOR_0, 16);
255 /* Sporadic registers used as primitives are emitted */
256 ADD_RANGE(R300_ZB_ZCACHE_CTLSTAT, 1);
257 ADD_RANGE(R300_RB3D_DSTCACHE_CTLSTAT, 1);
258 ADD_RANGE(R300_VAP_INPUT_ROUTE_0_0, 8);
259 ADD_RANGE(R300_VAP_INPUT_ROUTE_1_0, 8);
261 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV515) {
262 ADD_RANGE(R500_VAP_INDEX_OFFSET, 1);
263 ADD_RANGE(R500_US_CONFIG, 2);
264 ADD_RANGE(R500_US_CODE_ADDR, 3);
265 ADD_RANGE(R500_US_FC_CTRL, 1);
266 ADD_RANGE(R500_RS_IP_0, 16);
267 ADD_RANGE(R500_RS_INST_0, 16);
268 ADD_RANGE(R500_RB3D_COLOR_CLEAR_VALUE_AR, 2);
269 ADD_RANGE(R500_RB3D_CONSTANT_COLOR_AR, 2);
270 ADD_RANGE(R500_ZB_FIFO_SIZE, 2);
272 ADD_RANGE(R300_PFS_CNTL_0, 3);
273 ADD_RANGE(R300_PFS_NODE_0, 4);
274 ADD_RANGE(R300_PFS_TEXI_0, 64);
275 ADD_RANGE(R300_PFS_INSTR0_0, 64);
276 ADD_RANGE(R300_PFS_INSTR1_0, 64);
277 ADD_RANGE(R300_PFS_INSTR2_0, 64);
278 ADD_RANGE(R300_PFS_INSTR3_0, 64);
279 ADD_RANGE(R300_RS_INTERP_0, 8);
280 ADD_RANGE(R300_RS_ROUTE_0, 8);
285 static __inline__ int r300_check_range(unsigned reg, int count)
290 for (i = (reg >> 2); i < (reg >> 2) + count; i++)
291 if (r300_reg_flags[i] != MARK_SAFE)
296 static __inline__ int r300_emit_carefully_checked_packet0(drm_radeon_private_t *
298 drm_radeon_kcmd_buffer_t
300 drm_r300_cmd_header_t
309 sz = header.packet0.count;
310 reg = (header.packet0.reghi << 8) | header.packet0.reglo;
312 if ((sz > 64) || (sz < 0)) {
314 ("Cannot emit more than 64 values at a time (reg=%04x sz=%d)\n",
318 for (i = 0; i < sz; i++) {
319 values[i] = ((int *)cmdbuf->buf)[i];
320 switch (r300_reg_flags[(reg >> 2) + i]) {
323 case MARK_CHECK_OFFSET:
324 if (!radeon_check_offset(dev_priv, (u32) values[i])) {
326 ("Offset failed range check (reg=%04x sz=%d)\n",
332 DRM_ERROR("Register %04x failed check as flag=%02x\n",
333 reg + i * 4, r300_reg_flags[(reg >> 2) + i]);
339 OUT_RING(CP_PACKET0(reg, sz - 1));
340 OUT_RING_TABLE(values, sz);
343 cmdbuf->buf += sz * 4;
344 cmdbuf->bufsz -= sz * 4;
350 * Emits a packet0 setting arbitrary registers.
351 * Called by r300_do_cp_cmdbuf.
353 * Note that checks are performed on contents and addresses of the registers
355 static __inline__ int r300_emit_packet0(drm_radeon_private_t *dev_priv,
356 drm_radeon_kcmd_buffer_t *cmdbuf,
357 drm_r300_cmd_header_t header)
363 sz = header.packet0.count;
364 reg = (header.packet0.reghi << 8) | header.packet0.reglo;
366 DRM_DEBUG("R300_CMD_PACKET0: reg %04x, sz %d\n", reg, sz);
370 if (sz * 4 > cmdbuf->bufsz)
373 if (reg + sz * 4 >= 0x10000) {
374 DRM_ERROR("No such registers in hardware reg=%04x sz=%d\n", reg,
379 if (r300_check_range(reg, sz)) {
380 /* go and check everything */
381 return r300_emit_carefully_checked_packet0(dev_priv, cmdbuf,
384 /* the rest of the data is safe to emit, whatever the values the user passed */
387 OUT_RING(CP_PACKET0(reg, sz - 1));
388 OUT_RING_TABLE((int *)cmdbuf->buf, sz);
391 cmdbuf->buf += sz * 4;
392 cmdbuf->bufsz -= sz * 4;
398 * Uploads user-supplied vertex program instructions or parameters onto
400 * Called by r300_do_cp_cmdbuf.
402 static __inline__ int r300_emit_vpu(drm_radeon_private_t *dev_priv,
403 drm_radeon_kcmd_buffer_t *cmdbuf,
404 drm_r300_cmd_header_t header)
410 sz = header.vpu.count;
411 addr = (header.vpu.adrhi << 8) | header.vpu.adrlo;
415 if (sz * 16 > cmdbuf->bufsz)
418 /* VAP is very sensitive so we purge cache before we program it
419 * and we also flush its state before & after */
421 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
422 OUT_RING(R300_RB3D_DC_FLUSH);
423 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
424 OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
425 OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
429 dev_priv->track_flush |= RADEON_FLUSH_EMITED;
431 BEGIN_RING(3 + sz * 4);
432 OUT_RING_REG(R300_VAP_PVS_UPLOAD_ADDRESS, addr);
433 OUT_RING(CP_PACKET0_TABLE(R300_VAP_PVS_UPLOAD_DATA, sz * 4 - 1));
434 OUT_RING_TABLE((int *)cmdbuf->buf, sz * 4);
438 OUT_RING(CP_PACKET0(R300_VAP_PVS_STATE_FLUSH_REG, 0));
442 cmdbuf->buf += sz * 16;
443 cmdbuf->bufsz -= sz * 16;
449 * Emit a clear packet from userspace.
450 * Called by r300_emit_packet3.
452 static __inline__ int r300_emit_clear(drm_radeon_private_t *dev_priv,
453 drm_radeon_kcmd_buffer_t *cmdbuf)
457 if (8 * 4 > cmdbuf->bufsz)
461 OUT_RING(CP_PACKET3(R200_3D_DRAW_IMMD_2, 8));
462 OUT_RING(R300_PRIM_TYPE_POINT | R300_PRIM_WALK_RING |
463 (1 << R300_PRIM_NUM_VERTICES_SHIFT));
464 OUT_RING_TABLE((int *)cmdbuf->buf, 8);
468 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
469 OUT_RING(R300_RB3D_DC_FLUSH);
470 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
471 OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
474 dev_priv->track_flush |= RADEON_FLUSH_EMITED;
476 cmdbuf->buf += 8 * 4;
477 cmdbuf->bufsz -= 8 * 4;
482 static __inline__ int r300_emit_3d_load_vbpntr(drm_radeon_private_t *dev_priv,
483 drm_radeon_kcmd_buffer_t *cmdbuf,
487 #define MAX_ARRAY_PACKET 64
488 u32 payload[MAX_ARRAY_PACKET];
492 count = (header >> 16) & 0x3fff;
494 if ((count + 1) > MAX_ARRAY_PACKET) {
495 DRM_ERROR("Too large payload in 3D_LOAD_VBPNTR (count=%d)\n",
499 memset(payload, 0, MAX_ARRAY_PACKET * 4);
500 memcpy(payload, cmdbuf->buf + 4, (count + 1) * 4);
502 /* carefully check packet contents */
504 narrays = payload[0];
507 while ((k < narrays) && (i < (count + 1))) {
508 i++; /* skip attribute field */
509 if (!radeon_check_offset(dev_priv, payload[i])) {
511 ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
519 /* have one more to process, they come in pairs */
520 if (!radeon_check_offset(dev_priv, payload[i])) {
522 ("Offset failed range check (k=%d i=%d) while processing 3D_LOAD_VBPNTR packet.\n",
529 /* do the counts match what we expect ? */
530 if ((k != narrays) || (i != (count + 1))) {
532 ("Malformed 3D_LOAD_VBPNTR packet (k=%d i=%d narrays=%d count+1=%d).\n",
533 k, i, narrays, count + 1);
537 /* all clear, output packet */
539 BEGIN_RING(count + 2);
541 OUT_RING_TABLE(payload, count + 1);
544 cmdbuf->buf += (count + 2) * 4;
545 cmdbuf->bufsz -= (count + 2) * 4;
550 static __inline__ int r300_emit_bitblt_multi(drm_radeon_private_t *dev_priv,
551 drm_radeon_kcmd_buffer_t *cmdbuf)
553 u32 *cmd = (u32 *) cmdbuf->buf;
557 count=(cmd[0]>>16) & 0x3fff;
559 if (cmd[0] & 0x8000) {
562 if (cmd[1] & (RADEON_GMC_SRC_PITCH_OFFSET_CNTL
563 | RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
564 offset = cmd[2] << 10;
565 ret = !radeon_check_offset(dev_priv, offset);
567 DRM_ERROR("Invalid bitblt first offset is %08X\n", offset);
572 if ((cmd[1] & RADEON_GMC_SRC_PITCH_OFFSET_CNTL) &&
573 (cmd[1] & RADEON_GMC_DST_PITCH_OFFSET_CNTL)) {
574 offset = cmd[3] << 10;
575 ret = !radeon_check_offset(dev_priv, offset);
577 DRM_ERROR("Invalid bitblt second offset is %08X\n", offset);
586 OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
589 cmdbuf->buf += (count+2)*4;
590 cmdbuf->bufsz -= (count+2)*4;
595 static __inline__ int r300_emit_draw_indx_2(drm_radeon_private_t *dev_priv,
596 drm_radeon_kcmd_buffer_t *cmdbuf)
603 cmd = (u32 *) cmdbuf->buf;
604 count = (cmd[0]>>16) & 0x3fff;
605 expected_count = cmd[1] >> 16;
606 if (!(cmd[1] & R300_VAP_VF_CNTL__INDEX_SIZE_32bit))
607 expected_count = (expected_count+1)/2;
609 if (count && count != expected_count) {
610 DRM_ERROR("3D_DRAW_INDX_2: packet size %i, expected %i\n",
611 count, expected_count);
617 OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
620 cmdbuf->buf += (count+2)*4;
621 cmdbuf->bufsz -= (count+2)*4;
624 drm_r300_cmd_header_t header;
626 if (cmdbuf->bufsz < 4*4 + sizeof(header)) {
627 DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER, but stream is too short.\n");
631 header.u = *(unsigned int *)cmdbuf->buf;
633 cmdbuf->buf += sizeof(header);
634 cmdbuf->bufsz -= sizeof(header);
635 cmd = (u32 *) cmdbuf->buf;
637 if (header.header.cmd_type != R300_CMD_PACKET3 ||
638 header.packet3.packet != R300_CMD_PACKET3_RAW ||
639 cmd[0] != CP_PACKET3(RADEON_CP_INDX_BUFFER, 2)) {
640 DRM_ERROR("3D_DRAW_INDX_2: expect subsequent INDX_BUFFER.\n");
644 if ((cmd[1] & 0x8000ffff) != 0x80000810) {
645 DRM_ERROR("Invalid indx_buffer reg address %08X\n", cmd[1]);
648 if (!radeon_check_offset(dev_priv, cmd[2])) {
649 DRM_ERROR("Invalid indx_buffer offset is %08X\n", cmd[2]);
652 if (cmd[3] != expected_count) {
653 DRM_ERROR("INDX_BUFFER: buffer size %i, expected %i\n",
654 cmd[3], expected_count);
660 OUT_RING_TABLE((int *)(cmdbuf->buf + 4), 3);
664 cmdbuf->bufsz -= 4*4;
670 static __inline__ int r300_emit_raw_packet3(drm_radeon_private_t *dev_priv,
671 drm_radeon_kcmd_buffer_t *cmdbuf)
677 if (4 > cmdbuf->bufsz)
680 /* Fixme !! This simply emits a packet without much checking.
681 We need to be smarter. */
683 /* obtain first word - actual packet3 header */
684 header = *(u32 *) cmdbuf->buf;
686 /* Is it packet 3 ? */
687 if ((header >> 30) != 0x3) {
688 DRM_ERROR("Not a packet3 header (0x%08x)\n", header);
692 count = (header >> 16) & 0x3fff;
694 /* Check again now that we know how much data to expect */
695 if ((count + 2) * 4 > cmdbuf->bufsz) {
697 ("Expected packet3 of length %d but have only %d bytes left\n",
698 (count + 2) * 4, cmdbuf->bufsz);
702 /* Is it a packet type we know about ? */
703 switch (header & 0xff00) {
704 case RADEON_3D_LOAD_VBPNTR: /* load vertex array pointers */
705 return r300_emit_3d_load_vbpntr(dev_priv, cmdbuf, header);
707 case RADEON_CNTL_BITBLT_MULTI:
708 return r300_emit_bitblt_multi(dev_priv, cmdbuf);
710 case RADEON_CP_INDX_BUFFER:
711 DRM_ERROR("packet3 INDX_BUFFER without preceding 3D_DRAW_INDX_2 is illegal.\n");
713 case RADEON_CP_3D_DRAW_IMMD_2:
714 /* triggers drawing using in-packet vertex data */
715 case RADEON_CP_3D_DRAW_VBUF_2:
716 /* triggers drawing of vertex buffers setup elsewhere */
717 dev_priv->track_flush &= ~(RADEON_FLUSH_EMITED |
718 RADEON_PURGE_EMITED);
720 case RADEON_CP_3D_DRAW_INDX_2:
721 /* triggers drawing using indices to vertex buffer */
722 /* whenever we send vertex we clear flush & purge */
723 dev_priv->track_flush &= ~(RADEON_FLUSH_EMITED |
724 RADEON_PURGE_EMITED);
725 return r300_emit_draw_indx_2(dev_priv, cmdbuf);
726 case RADEON_WAIT_FOR_IDLE:
728 /* these packets are safe */
731 DRM_ERROR("Unknown packet3 header (0x%08x)\n", header);
735 BEGIN_RING(count + 2);
737 OUT_RING_TABLE((int *)(cmdbuf->buf + 4), count + 1);
740 cmdbuf->buf += (count + 2) * 4;
741 cmdbuf->bufsz -= (count + 2) * 4;
747 * Emit a rendering packet3 from userspace.
748 * Called by r300_do_cp_cmdbuf.
750 static __inline__ int r300_emit_packet3(drm_radeon_private_t *dev_priv,
751 drm_radeon_kcmd_buffer_t *cmdbuf,
752 drm_r300_cmd_header_t header)
756 char *orig_buf = cmdbuf->buf;
757 int orig_bufsz = cmdbuf->bufsz;
759 /* This is a do-while-loop so that we run the interior at least once,
760 * even if cmdbuf->nbox is 0. Compare r300_emit_cliprects for rationale.
764 if (cmdbuf->nbox > R300_SIMULTANEOUS_CLIPRECTS) {
765 ret = r300_emit_cliprects(dev_priv, cmdbuf, n);
769 cmdbuf->buf = orig_buf;
770 cmdbuf->bufsz = orig_bufsz;
773 switch (header.packet3.packet) {
774 case R300_CMD_PACKET3_CLEAR:
775 DRM_DEBUG("R300_CMD_PACKET3_CLEAR\n");
776 ret = r300_emit_clear(dev_priv, cmdbuf);
778 DRM_ERROR("r300_emit_clear failed\n");
783 case R300_CMD_PACKET3_RAW:
784 DRM_DEBUG("R300_CMD_PACKET3_RAW\n");
785 ret = r300_emit_raw_packet3(dev_priv, cmdbuf);
787 DRM_ERROR("r300_emit_raw_packet3 failed\n");
793 DRM_ERROR("bad packet3 type %i at %p\n",
794 header.packet3.packet,
795 cmdbuf->buf - sizeof(header));
799 n += R300_SIMULTANEOUS_CLIPRECTS;
800 } while (n < cmdbuf->nbox);
805 /* Some of the R300 chips seem to be extremely touchy about the two registers
806 * that are configured in r300_pacify.
807 * Among the worst offenders seems to be the R300 ND (0x4E44): When userspace
808 * sends a command buffer that contains only state setting commands and a
809 * vertex program/parameter upload sequence, this will eventually lead to a
810 * lockup, unless the sequence is bracketed by calls to r300_pacify.
811 * So we should take great care to *always* call r300_pacify before
812 * *anything* 3D related, and again afterwards. This is what the
813 * call bracket in r300_do_cp_cmdbuf is for.
817 * Emit the sequence to pacify R300.
819 static __inline__ void r300_pacify(drm_radeon_private_t *dev_priv)
821 uint32_t cache_z, cache_3d, cache_2d;
824 cache_z = R300_ZC_FLUSH;
825 cache_2d = R300_RB2D_DC_FLUSH;
826 cache_3d = R300_RB3D_DC_FLUSH;
827 if (!(dev_priv->track_flush & RADEON_PURGE_EMITED)) {
828 /* we can purge, primitive where draw since last purge */
829 cache_z |= R300_ZC_FREE;
830 cache_2d |= R300_RB2D_DC_FREE;
831 cache_3d |= R300_RB3D_DC_FREE;
834 /* flush & purge zbuffer */
836 OUT_RING(CP_PACKET0(R300_ZB_ZCACHE_CTLSTAT, 0));
839 /* flush & purge 3d */
841 OUT_RING(CP_PACKET0(R300_RB3D_DSTCACHE_CTLSTAT, 0));
844 /* flush & purge texture */
846 OUT_RING(CP_PACKET0(R300_TX_INVALTAGS, 0));
849 /* FIXME: is this one really needed ? */
851 OUT_RING(CP_PACKET0(R300_RB3D_AARESOLVE_CTL, 0));
855 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
856 OUT_RING(RADEON_WAIT_3D_IDLECLEAN);
858 /* flush & purge 2d through E2 as RB2D will trigger lockup */
860 OUT_RING(CP_PACKET0(R300_DSTCACHE_CTLSTAT, 0));
862 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
863 OUT_RING(RADEON_WAIT_2D_IDLECLEAN |
864 RADEON_WAIT_HOST_IDLECLEAN);
866 /* set flush & purge flags */
867 dev_priv->track_flush |= RADEON_FLUSH_EMITED | RADEON_PURGE_EMITED;
871 * Called by r300_do_cp_cmdbuf to update the internal buffer age and state.
872 * The actual age emit is done by r300_do_cp_cmdbuf, which is why you must
873 * be careful about how this function is called.
875 static void r300_discard_buffer(struct drm_device * dev, struct drm_buf * buf)
877 drm_radeon_private_t *dev_priv = dev->dev_private;
878 drm_radeon_buf_priv_t *buf_priv = buf->dev_private;
880 buf_priv->age = ++dev_priv->sarea_priv->last_dispatch;
885 static void r300_cmd_wait(drm_radeon_private_t * dev_priv,
886 drm_r300_cmd_header_t header)
891 if (!header.wait.flags)
896 switch(header.wait.flags) {
898 wait_until = RADEON_WAIT_2D_IDLE;
901 wait_until = RADEON_WAIT_3D_IDLE;
903 case R300_NEW_WAIT_2D_3D:
904 wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_3D_IDLE;
906 case R300_NEW_WAIT_2D_2D_CLEAN:
907 wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_2D_IDLECLEAN;
909 case R300_NEW_WAIT_3D_3D_CLEAN:
910 wait_until = RADEON_WAIT_3D_IDLE|RADEON_WAIT_3D_IDLECLEAN;
912 case R300_NEW_WAIT_2D_2D_CLEAN_3D_3D_CLEAN:
913 wait_until = RADEON_WAIT_2D_IDLE|RADEON_WAIT_2D_IDLECLEAN;
914 wait_until |= RADEON_WAIT_3D_IDLE|RADEON_WAIT_3D_IDLECLEAN;
921 OUT_RING(CP_PACKET0(RADEON_WAIT_UNTIL, 0));
922 OUT_RING(wait_until);
926 static int r300_scratch(drm_radeon_private_t *dev_priv,
927 drm_radeon_kcmd_buffer_t *cmdbuf,
928 drm_r300_cmd_header_t header)
931 u32 i, buf_idx, h_pending;
934 if (cmdbuf->bufsz < sizeof(uint64_t) + header.scratch.n_bufs * sizeof(buf_idx) ) {
938 if (header.scratch.reg >= 5) {
942 dev_priv->scratch_ages[header.scratch.reg] ++;
944 ref_age_base = (u32 *)(unsigned long)*((uint64_t *)cmdbuf->buf);
946 cmdbuf->buf += sizeof(uint64_t);
947 cmdbuf->bufsz -= sizeof(uint64_t);
949 for (i=0; i < header.scratch.n_bufs; i++) {
950 buf_idx = *(u32 *)cmdbuf->buf;
951 buf_idx *= 2; /* 8 bytes per buf */
953 if (DRM_COPY_TO_USER(ref_age_base + buf_idx, &dev_priv->scratch_ages[header.scratch.reg], sizeof(u32))) {
957 if (DRM_COPY_FROM_USER(&h_pending, ref_age_base + buf_idx + 1, sizeof(u32))) {
961 if (h_pending == 0) {
967 if (DRM_COPY_TO_USER(ref_age_base + buf_idx + 1, &h_pending, sizeof(u32))) {
971 cmdbuf->buf += sizeof(buf_idx);
972 cmdbuf->bufsz -= sizeof(buf_idx);
976 OUT_RING( CP_PACKET0( RADEON_SCRATCH_REG0 + header.scratch.reg * 4, 0 ) );
977 OUT_RING( dev_priv->scratch_ages[header.scratch.reg] );
984 * Uploads user-supplied vertex program instructions or parameters onto
986 * Called by r300_do_cp_cmdbuf.
988 static __inline__ int r300_emit_r500fp(drm_radeon_private_t *dev_priv,
989 drm_radeon_kcmd_buffer_t *cmdbuf,
990 drm_r300_cmd_header_t header)
999 sz = header.r500fp.count;
1000 /* address is 9 bits 0 - 8, bit 1 of flags is part of address */
1001 addr = ((header.r500fp.adrhi_flags & 1) << 8) | header.r500fp.adrlo;
1003 type = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_TYPE);
1004 clamp = !!(header.r500fp.adrhi_flags & R500FP_CONSTANT_CLAMP);
1006 addr |= (type << 16);
1007 addr |= (clamp << 17);
1009 stride = type ? 4 : 6;
1011 DRM_DEBUG("r500fp %d %d type: %d\n", sz, addr, type);
1014 if (sz * stride * 4 > cmdbuf->bufsz)
1017 BEGIN_RING(3 + sz * stride);
1018 OUT_RING_REG(R500_GA_US_VECTOR_INDEX, addr);
1019 OUT_RING(CP_PACKET0_TABLE(R500_GA_US_VECTOR_DATA, sz * stride - 1));
1020 OUT_RING_TABLE((int *)cmdbuf->buf, sz * stride);
1024 cmdbuf->buf += sz * stride * 4;
1025 cmdbuf->bufsz -= sz * stride * 4;
1032 * Parses and validates a user-supplied command buffer and emits appropriate
1033 * commands on the DMA ring buffer.
1034 * Called by the ioctl handler function radeon_cp_cmdbuf.
1036 int r300_do_cp_cmdbuf(struct drm_device *dev,
1037 struct drm_file *file_priv,
1038 drm_radeon_kcmd_buffer_t *cmdbuf)
1040 drm_radeon_private_t *dev_priv = dev->dev_private;
1041 struct drm_device_dma *dma = dev->dma;
1042 struct drm_buf *buf = NULL;
1043 int emit_dispatch_age = 0;
1049 r300_pacify(dev_priv);
1051 if (cmdbuf->nbox <= R300_SIMULTANEOUS_CLIPRECTS) {
1052 ret = r300_emit_cliprects(dev_priv, cmdbuf, 0);
1057 while (cmdbuf->bufsz >= sizeof(drm_r300_cmd_header_t)) {
1059 drm_r300_cmd_header_t header;
1061 header.u = *(unsigned int *)cmdbuf->buf;
1063 cmdbuf->buf += sizeof(header);
1064 cmdbuf->bufsz -= sizeof(header);
1066 switch (header.header.cmd_type) {
1067 case R300_CMD_PACKET0:
1068 ret = r300_emit_packet0(dev_priv, cmdbuf, header);
1070 DRM_ERROR("r300_emit_packet0 failed\n");
1076 DRM_DEBUG("R300_CMD_VPU\n");
1077 ret = r300_emit_vpu(dev_priv, cmdbuf, header);
1079 DRM_ERROR("r300_emit_vpu failed\n");
1084 case R300_CMD_PACKET3:
1085 DRM_DEBUG("R300_CMD_PACKET3\n");
1086 ret = r300_emit_packet3(dev_priv, cmdbuf, header);
1088 DRM_ERROR("r300_emit_packet3 failed\n");
1093 case R300_CMD_END3D:
1094 DRM_DEBUG("R300_CMD_END3D\n");
1096 Ideally userspace driver should not need to issue this call,
1097 i.e. the drm driver should issue it automatically and prevent
1100 In practice, we do not understand why this call is needed and what
1101 it does (except for some vague guesses that it has to do with cache
1102 coherence) and so the user space driver does it.
1104 Once we are sure which uses prevent lockups the code could be moved
1105 into the kernel and the userspace driver will not
1106 need to use this command.
1108 Note that issuing this command does not hurt anything
1109 except, possibly, performance */
1110 r300_pacify(dev_priv);
1113 case R300_CMD_CP_DELAY:
1114 /* simple enough, we can do it here */
1115 DRM_DEBUG("R300_CMD_CP_DELAY\n");
1120 BEGIN_RING(header.delay.count);
1121 for (i = 0; i < header.delay.count; i++)
1122 OUT_RING(RADEON_CP_PACKET2);
1127 case R300_CMD_DMA_DISCARD:
1128 DRM_DEBUG("RADEON_CMD_DMA_DISCARD\n");
1129 idx = header.dma.buf_idx;
1130 if (idx < 0 || idx >= dma->buf_count) {
1131 DRM_ERROR("buffer index %d (of %d max)\n",
1132 idx, dma->buf_count - 1);
1137 buf = dma->buflist[idx];
1138 if (buf->file_priv != file_priv || buf->pending) {
1139 DRM_ERROR("bad buffer %p %p %d\n",
1140 buf->file_priv, file_priv,
1146 emit_dispatch_age = 1;
1147 r300_discard_buffer(dev, buf);
1151 DRM_DEBUG("R300_CMD_WAIT\n");
1152 r300_cmd_wait(dev_priv, header);
1155 case R300_CMD_SCRATCH:
1156 DRM_DEBUG("R300_CMD_SCRATCH\n");
1157 ret = r300_scratch(dev_priv, cmdbuf, header);
1159 DRM_ERROR("r300_scratch failed\n");
1164 case R300_CMD_R500FP:
1165 if ((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV515) {
1166 DRM_ERROR("Calling r500 command on r300 card\n");
1170 DRM_DEBUG("R300_CMD_R500FP\n");
1171 ret = r300_emit_r500fp(dev_priv, cmdbuf, header);
1173 DRM_ERROR("r300_emit_r500fp failed\n");
1178 DRM_ERROR("bad cmd_type %i at %p\n",
1179 header.header.cmd_type,
1180 cmdbuf->buf - sizeof(header));
1189 r300_pacify(dev_priv);
1191 /* We emit the vertex buffer age here, outside the pacifier "brackets"
1193 * (1) This may coalesce multiple age emissions into a single one and
1194 * (2) more importantly, some chips lock up hard when scratch registers
1195 * are written inside the pacifier bracket.
1197 if (emit_dispatch_age) {
1200 /* Emit the vertex buffer age */
1202 RADEON_DISPATCH_AGE(dev_priv->sarea_priv->last_dispatch);