2 * Copyright 2008-2009 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
25 * Dave Airlie <airlied@redhat.com>
26 * Alex Deucher <alexander.deucher@amd.com>
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include "dev/drm/drmP.h"
33 #include "dev/drm/drm.h"
34 #include "dev/drm/radeon_drm.h"
35 #include "dev/drm/radeon_drv.h"
37 #include "dev/drm/r600_microcode.h"
39 # define ATI_PCIGART_PAGE_SIZE 4096 /**< PCI GART page size */
40 # define ATI_PCIGART_PAGE_MASK (~(ATI_PCIGART_PAGE_SIZE-1))
42 #define R600_PTE_VALID (1 << 0)
43 #define R600_PTE_SYSTEM (1 << 1)
44 #define R600_PTE_SNOOPED (1 << 2)
45 #define R600_PTE_READABLE (1 << 5)
46 #define R600_PTE_WRITEABLE (1 << 6)
48 /* MAX values used for gfx init */
49 #define R6XX_MAX_SH_GPRS 256
50 #define R6XX_MAX_TEMP_GPRS 16
51 #define R6XX_MAX_SH_THREADS 256
52 #define R6XX_MAX_SH_STACK_ENTRIES 4096
53 #define R6XX_MAX_BACKENDS 8
54 #define R6XX_MAX_BACKENDS_MASK 0xff
55 #define R6XX_MAX_SIMDS 8
56 #define R6XX_MAX_SIMDS_MASK 0xff
57 #define R6XX_MAX_PIPES 8
58 #define R6XX_MAX_PIPES_MASK 0xff
60 #define R7XX_MAX_SH_GPRS 256
61 #define R7XX_MAX_TEMP_GPRS 16
62 #define R7XX_MAX_SH_THREADS 256
63 #define R7XX_MAX_SH_STACK_ENTRIES 4096
64 #define R7XX_MAX_BACKENDS 8
65 #define R7XX_MAX_BACKENDS_MASK 0xff
66 #define R7XX_MAX_SIMDS 16
67 #define R7XX_MAX_SIMDS_MASK 0xffff
68 #define R7XX_MAX_PIPES 8
69 #define R7XX_MAX_PIPES_MASK 0xff
71 static int r600_do_wait_for_fifo(drm_radeon_private_t *dev_priv, int entries)
75 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
77 for (i = 0; i < dev_priv->usec_timeout; i++) {
79 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
80 slots = (RADEON_READ(R600_GRBM_STATUS)
81 & R700_CMDFIFO_AVAIL_MASK);
83 slots = (RADEON_READ(R600_GRBM_STATUS)
84 & R600_CMDFIFO_AVAIL_MASK);
89 DRM_INFO("wait for fifo failed status : 0x%08X 0x%08X\n",
90 RADEON_READ(R600_GRBM_STATUS),
91 RADEON_READ(R600_GRBM_STATUS2));
96 static int r600_do_wait_for_idle(drm_radeon_private_t *dev_priv)
100 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
102 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)
103 ret = r600_do_wait_for_fifo(dev_priv, 8);
105 ret = r600_do_wait_for_fifo(dev_priv, 16);
108 for (i = 0; i < dev_priv->usec_timeout; i++) {
109 if (!(RADEON_READ(R600_GRBM_STATUS) & R600_GUI_ACTIVE))
113 DRM_INFO("wait idle failed status : 0x%08X 0x%08X\n",
114 RADEON_READ(R600_GRBM_STATUS),
115 RADEON_READ(R600_GRBM_STATUS2));
120 void r600_page_table_cleanup(struct drm_device *dev, struct drm_ati_pcigart_info *gart_info)
123 struct drm_sg_mem *entry = dev->sg;
128 if (gart_info->bus_addr) {
130 max_pages = (gart_info->table_size / sizeof(u32));
131 pages = (entry->pages <= max_pages)
132 ? entry->pages : max_pages;
134 for (i = 0; i < pages; i++) {
135 if (!entry->busaddr[i])
137 pci_unmap_single(dev->pdev, entry->busaddr[i],
138 PAGE_SIZE, PCI_DMA_TODEVICE);
141 if (gart_info->gart_table_location == DRM_ATI_GART_MAIN)
142 gart_info->bus_addr = 0;
146 /* R600 has page table setup */
147 int r600_page_table_init(struct drm_device *dev)
149 drm_radeon_private_t *dev_priv = dev->dev_private;
150 struct drm_ati_pcigart_info *gart_info = &dev_priv->gart_info;
151 struct drm_sg_mem *entry = dev->sg;
154 int max_pages, pages;
155 u64 *pci_gart, page_base;
156 dma_addr_t entry_addr;
158 /* okay page table is available - lets rock */
160 /* PTEs are 64-bits */
161 pci_gart = (u64 *)gart_info->addr;
163 max_pages = (gart_info->table_size / sizeof(u64));
164 pages = (entry->pages <= max_pages) ? entry->pages : max_pages;
166 memset(pci_gart, 0, max_pages * sizeof(u64));
168 for (i = 0; i < pages; i++) {
170 entry->busaddr[i] = pci_map_single(dev->pdev,
173 PAGE_SIZE, PCI_DMA_TODEVICE);
174 if (entry->busaddr[i] == 0) {
175 DRM_ERROR("unable to map PCIGART pages!\n");
176 r600_page_table_cleanup(dev, gart_info);
180 entry_addr = entry->busaddr[i];
181 for (j = 0; j < (PAGE_SIZE / ATI_PCIGART_PAGE_SIZE); j++) {
182 page_base = (u64) entry_addr & ATI_PCIGART_PAGE_MASK;
183 page_base |= R600_PTE_VALID | R600_PTE_SYSTEM;
184 page_base |= R600_PTE_READABLE | R600_PTE_WRITEABLE;
186 *pci_gart = page_base;
189 DRM_DEBUG("page entry %d: 0x%016llx\n",
190 i, (unsigned long long)page_base);
192 entry_addr += ATI_PCIGART_PAGE_SIZE;
202 static void r600_vm_flush_gart_range(struct drm_device *dev)
204 drm_radeon_private_t *dev_priv = dev->dev_private;
205 u32 resp, countdown = 1000;
206 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_LOW_ADDR, dev_priv->gart_vm_start >> 12);
207 RADEON_WRITE(R600_VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
208 RADEON_WRITE(R600_VM_CONTEXT0_REQUEST_RESPONSE, 2);
211 resp = RADEON_READ(R600_VM_CONTEXT0_REQUEST_RESPONSE);
214 } while (((resp & 0xf0) == 0) && countdown);
217 static void r600_vm_init(struct drm_device *dev)
219 drm_radeon_private_t *dev_priv = dev->dev_private;
220 /* initialise the VM to use the page table we constructed up there */
223 u32 vm_l2_cntl, vm_l2_cntl3;
224 /* okay set up the PCIE aperture type thingo */
225 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
226 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
227 RADEON_WRITE(R600_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
230 mc_rd_a = R600_MCD_L1_TLB | R600_MCD_L1_FRAG_PROC | R600_MCD_SYSTEM_ACCESS_MODE_IN_SYS |
231 R600_MCD_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | R600_MCD_EFFECTIVE_L1_TLB_SIZE(5) |
232 R600_MCD_EFFECTIVE_L1_QUEUE_SIZE(5) | R600_MCD_WAIT_L2_QUERY;
234 RADEON_WRITE(R600_MCD_RD_A_CNTL, mc_rd_a);
235 RADEON_WRITE(R600_MCD_RD_B_CNTL, mc_rd_a);
237 RADEON_WRITE(R600_MCD_WR_A_CNTL, mc_rd_a);
238 RADEON_WRITE(R600_MCD_WR_B_CNTL, mc_rd_a);
240 RADEON_WRITE(R600_MCD_RD_GFX_CNTL, mc_rd_a);
241 RADEON_WRITE(R600_MCD_WR_GFX_CNTL, mc_rd_a);
243 RADEON_WRITE(R600_MCD_RD_SYS_CNTL, mc_rd_a);
244 RADEON_WRITE(R600_MCD_WR_SYS_CNTL, mc_rd_a);
246 RADEON_WRITE(R600_MCD_RD_HDP_CNTL, mc_rd_a | R600_MCD_L1_STRICT_ORDERING);
247 RADEON_WRITE(R600_MCD_WR_HDP_CNTL, mc_rd_a /*| R600_MCD_L1_STRICT_ORDERING*/);
249 RADEON_WRITE(R600_MCD_RD_PDMA_CNTL, mc_rd_a);
250 RADEON_WRITE(R600_MCD_WR_PDMA_CNTL, mc_rd_a);
252 RADEON_WRITE(R600_MCD_RD_SEM_CNTL, mc_rd_a | R600_MCD_SEMAPHORE_MODE);
253 RADEON_WRITE(R600_MCD_WR_SEM_CNTL, mc_rd_a);
255 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
256 vm_l2_cntl |= R600_VM_L2_CNTL_QUEUE_SIZE(7);
257 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
259 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
260 vm_l2_cntl3 = (R600_VM_L2_CNTL3_BANK_SELECT_0(0) |
261 R600_VM_L2_CNTL3_BANK_SELECT_1(1) |
262 R600_VM_L2_CNTL3_CACHE_UPDATE_MODE(2));
263 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
265 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
267 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
269 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
271 /* disable all other contexts */
272 for (i = 1; i < 8; i++)
273 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
275 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
276 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
277 RADEON_WRITE(R600_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
279 r600_vm_flush_gart_range(dev);
282 /* load r600 microcode */
283 static void r600_cp_load_microcode(drm_radeon_private_t *dev_priv)
289 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
291 DRM_INFO("Loading R600 Microcode\n");
292 cp = R600_cp_microcode;
293 pfp = R600_pfp_microcode;
296 DRM_INFO("Loading RV610 Microcode\n");
297 cp = RV610_cp_microcode;
298 pfp = RV610_pfp_microcode;
301 DRM_INFO("Loading RV630 Microcode\n");
302 cp = RV630_cp_microcode;
303 pfp = RV630_pfp_microcode;
306 DRM_INFO("Loading RV620 Microcode\n");
307 cp = RV620_cp_microcode;
308 pfp = RV620_pfp_microcode;
311 DRM_INFO("Loading RV635 Microcode\n");
312 cp = RV635_cp_microcode;
313 pfp = RV635_pfp_microcode;
316 DRM_INFO("Loading RV670 Microcode\n");
317 cp = RV670_cp_microcode;
318 pfp = RV670_pfp_microcode;
322 DRM_INFO("Loading RS780/RS880 Microcode\n");
323 cp = RS780_cp_microcode;
324 pfp = RS780_pfp_microcode;
330 r600_do_cp_stop(dev_priv);
332 RADEON_WRITE(R600_CP_RB_CNTL,
337 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
338 RADEON_READ(R600_GRBM_SOFT_RESET);
340 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
342 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
344 for (i = 0; i < PM4_UCODE_SIZE; i++) {
345 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][0]);
346 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][1]);
347 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i][2]);
350 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
351 for (i = 0; i < PFP_UCODE_SIZE; i++)
352 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
354 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
355 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
356 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
359 static void r700_vm_init(struct drm_device *dev)
361 drm_radeon_private_t *dev_priv = dev->dev_private;
362 /* initialise the VM to use the page table we constructed up there */
365 u32 vm_l2_cntl, vm_l2_cntl3;
366 /* okay set up the PCIE aperture type thingo */
367 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_LOW_ADDR, dev_priv->gart_vm_start >> 12);
368 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_HIGH_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
369 RADEON_WRITE(R700_MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
371 mc_vm_md_l1 = R700_ENABLE_L1_TLB |
372 R700_ENABLE_L1_FRAGMENT_PROCESSING |
373 R700_SYSTEM_ACCESS_MODE_IN_SYS |
374 R700_SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
375 R700_EFFECTIVE_L1_TLB_SIZE(5) |
376 R700_EFFECTIVE_L1_QUEUE_SIZE(5);
378 RADEON_WRITE(R700_MC_VM_MD_L1_TLB0_CNTL, mc_vm_md_l1);
379 RADEON_WRITE(R700_MC_VM_MD_L1_TLB1_CNTL, mc_vm_md_l1);
380 RADEON_WRITE(R700_MC_VM_MD_L1_TLB2_CNTL, mc_vm_md_l1);
381 RADEON_WRITE(R700_MC_VM_MB_L1_TLB0_CNTL, mc_vm_md_l1);
382 RADEON_WRITE(R700_MC_VM_MB_L1_TLB1_CNTL, mc_vm_md_l1);
383 RADEON_WRITE(R700_MC_VM_MB_L1_TLB2_CNTL, mc_vm_md_l1);
384 RADEON_WRITE(R700_MC_VM_MB_L1_TLB3_CNTL, mc_vm_md_l1);
386 vm_l2_cntl = R600_VM_L2_CACHE_EN | R600_VM_L2_FRAG_PROC | R600_VM_ENABLE_PTE_CACHE_LRU_W;
387 vm_l2_cntl |= R700_VM_L2_CNTL_QUEUE_SIZE(7);
388 RADEON_WRITE(R600_VM_L2_CNTL, vm_l2_cntl);
390 RADEON_WRITE(R600_VM_L2_CNTL2, 0);
391 vm_l2_cntl3 = R700_VM_L2_CNTL3_BANK_SELECT(0) | R700_VM_L2_CNTL3_CACHE_UPDATE_MODE(2);
392 RADEON_WRITE(R600_VM_L2_CNTL3, vm_l2_cntl3);
394 vm_c0 = R600_VM_ENABLE_CONTEXT | R600_VM_PAGE_TABLE_DEPTH_FLAT;
396 RADEON_WRITE(R600_VM_CONTEXT0_CNTL, vm_c0);
398 vm_c0 &= ~R600_VM_ENABLE_CONTEXT;
400 /* disable all other contexts */
401 for (i = 1; i < 8; i++)
402 RADEON_WRITE(R600_VM_CONTEXT0_CNTL + (i * 4), vm_c0);
404 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, dev_priv->gart_info.bus_addr >> 12);
405 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_START_ADDR, dev_priv->gart_vm_start >> 12);
406 RADEON_WRITE(R700_VM_CONTEXT0_PAGE_TABLE_END_ADDR, (dev_priv->gart_vm_start + dev_priv->gart_size - 1) >> 12);
408 r600_vm_flush_gart_range(dev);
411 /* load r600 microcode */
412 static void r700_cp_load_microcode(drm_radeon_private_t *dev_priv)
418 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
420 DRM_INFO("Loading RV770/RV790 Microcode\n");
421 pfp = RV770_pfp_microcode;
422 cp = RV770_cp_microcode;
426 DRM_INFO("Loading RV730/RV740 Microcode\n");
427 pfp = RV730_pfp_microcode;
428 cp = RV730_cp_microcode;
431 DRM_INFO("Loading RV710 Microcode\n");
432 pfp = RV710_pfp_microcode;
433 cp = RV710_cp_microcode;
439 r600_do_cp_stop(dev_priv);
441 RADEON_WRITE(R600_CP_RB_CNTL,
446 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
447 RADEON_READ(R600_GRBM_SOFT_RESET);
449 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
451 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
452 for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
453 RADEON_WRITE(R600_CP_PFP_UCODE_DATA, pfp[i]);
454 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
456 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
457 for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
458 RADEON_WRITE(R600_CP_ME_RAM_DATA, cp[i]);
459 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
461 RADEON_WRITE(R600_CP_PFP_UCODE_ADDR, 0);
462 RADEON_WRITE(R600_CP_ME_RAM_WADDR, 0);
463 RADEON_WRITE(R600_CP_ME_RAM_RADDR, 0);
466 static void r600_test_writeback(drm_radeon_private_t *dev_priv)
470 /* Start with assuming that writeback doesn't work */
471 dev_priv->writeback_works = 0;
473 /* Writeback doesn't seem to work everywhere, test it here and possibly
474 * enable it if it appears to work
476 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
478 RADEON_WRITE(R600_SCRATCH_REG1, 0xdeadbeef);
480 for (tmp = 0; tmp < dev_priv->usec_timeout; tmp++) {
483 val = radeon_read_ring_rptr(dev_priv, R600_SCRATCHOFF(1));
484 if (val == 0xdeadbeef)
489 if (tmp < dev_priv->usec_timeout) {
490 dev_priv->writeback_works = 1;
491 DRM_INFO("writeback test succeeded in %d usecs\n", tmp);
493 dev_priv->writeback_works = 0;
494 DRM_INFO("writeback test failed\n");
496 if (radeon_no_wb == 1) {
497 dev_priv->writeback_works = 0;
498 DRM_INFO("writeback forced off\n");
501 if (!dev_priv->writeback_works) {
502 /* Disable writeback to avoid unnecessary bus master transfer */
503 RADEON_WRITE(R600_CP_RB_CNTL, RADEON_READ(R600_CP_RB_CNTL) |
504 RADEON_RB_NO_UPDATE);
505 RADEON_WRITE(R600_SCRATCH_UMSK, 0);
509 int r600_do_engine_reset(struct drm_device *dev)
511 drm_radeon_private_t *dev_priv = dev->dev_private;
512 u32 cp_ptr, cp_me_cntl, cp_rb_cntl;
514 DRM_INFO("Resetting GPU\n");
516 cp_ptr = RADEON_READ(R600_CP_RB_WPTR);
517 cp_me_cntl = RADEON_READ(R600_CP_ME_CNTL);
518 RADEON_WRITE(R600_CP_ME_CNTL, R600_CP_ME_HALT);
520 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0x7fff);
521 RADEON_READ(R600_GRBM_SOFT_RESET);
523 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
524 RADEON_READ(R600_GRBM_SOFT_RESET);
526 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
527 cp_rb_cntl = RADEON_READ(R600_CP_RB_CNTL);
528 RADEON_WRITE(R600_CP_RB_CNTL, R600_RB_RPTR_WR_ENA);
530 RADEON_WRITE(R600_CP_RB_RPTR_WR, cp_ptr);
531 RADEON_WRITE(R600_CP_RB_WPTR, cp_ptr);
532 RADEON_WRITE(R600_CP_RB_CNTL, cp_rb_cntl);
533 RADEON_WRITE(R600_CP_ME_CNTL, cp_me_cntl);
535 /* Reset the CP ring */
536 r600_do_cp_reset(dev_priv);
538 /* The CP is no longer running after an engine reset */
539 dev_priv->cp_running = 0;
541 /* Reset any pending vertex, indirect buffers */
542 radeon_freelist_reset(dev);
548 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
550 u32 backend_disable_mask)
553 u32 enabled_backends_mask;
554 u32 enabled_backends_count;
556 u32 swizzle_pipe[R6XX_MAX_PIPES];
560 if (num_tile_pipes > R6XX_MAX_PIPES)
561 num_tile_pipes = R6XX_MAX_PIPES;
562 if (num_tile_pipes < 1)
564 if (num_backends > R6XX_MAX_BACKENDS)
565 num_backends = R6XX_MAX_BACKENDS;
566 if (num_backends < 1)
569 enabled_backends_mask = 0;
570 enabled_backends_count = 0;
571 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
572 if (((backend_disable_mask >> i) & 1) == 0) {
573 enabled_backends_mask |= (1 << i);
574 ++enabled_backends_count;
576 if (enabled_backends_count == num_backends)
580 if (enabled_backends_count == 0) {
581 enabled_backends_mask = 1;
582 enabled_backends_count = 1;
585 if (enabled_backends_count != num_backends)
586 num_backends = enabled_backends_count;
588 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
589 switch (num_tile_pipes) {
645 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
646 while (((1 << cur_backend) & enabled_backends_mask) == 0)
647 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
649 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
651 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
657 static int r600_count_pipe_bits(uint32_t val)
660 for (i = 0; i < 32; i++) {
667 static void r600_gfx_init(struct drm_device *dev,
668 drm_radeon_private_t *dev_priv)
670 int i, j, num_qd_pipes;
674 u32 num_gs_verts_per_thread;
676 u32 gs_prim_buffer_depth = 0;
677 u32 sq_ms_fifo_sizes;
679 u32 sq_gpr_resource_mgmt_1 = 0;
680 u32 sq_gpr_resource_mgmt_2 = 0;
681 u32 sq_thread_resource_mgmt = 0;
682 u32 sq_stack_resource_mgmt_1 = 0;
683 u32 sq_stack_resource_mgmt_2 = 0;
684 u32 hdp_host_path_cntl;
686 u32 gb_tiling_config = 0;
687 u32 cc_rb_backend_disable = 0;
688 u32 cc_gc_shader_pipe_config = 0;
691 /* setup chip specs */
692 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
694 dev_priv->r600_max_pipes = 4;
695 dev_priv->r600_max_tile_pipes = 8;
696 dev_priv->r600_max_simds = 4;
697 dev_priv->r600_max_backends = 4;
698 dev_priv->r600_max_gprs = 256;
699 dev_priv->r600_max_threads = 192;
700 dev_priv->r600_max_stack_entries = 256;
701 dev_priv->r600_max_hw_contexts = 8;
702 dev_priv->r600_max_gs_threads = 16;
703 dev_priv->r600_sx_max_export_size = 128;
704 dev_priv->r600_sx_max_export_pos_size = 16;
705 dev_priv->r600_sx_max_export_smx_size = 128;
706 dev_priv->r600_sq_num_cf_insts = 2;
710 dev_priv->r600_max_pipes = 2;
711 dev_priv->r600_max_tile_pipes = 2;
712 dev_priv->r600_max_simds = 3;
713 dev_priv->r600_max_backends = 1;
714 dev_priv->r600_max_gprs = 128;
715 dev_priv->r600_max_threads = 192;
716 dev_priv->r600_max_stack_entries = 128;
717 dev_priv->r600_max_hw_contexts = 8;
718 dev_priv->r600_max_gs_threads = 4;
719 dev_priv->r600_sx_max_export_size = 128;
720 dev_priv->r600_sx_max_export_pos_size = 16;
721 dev_priv->r600_sx_max_export_smx_size = 128;
722 dev_priv->r600_sq_num_cf_insts = 2;
728 dev_priv->r600_max_pipes = 1;
729 dev_priv->r600_max_tile_pipes = 1;
730 dev_priv->r600_max_simds = 2;
731 dev_priv->r600_max_backends = 1;
732 dev_priv->r600_max_gprs = 128;
733 dev_priv->r600_max_threads = 192;
734 dev_priv->r600_max_stack_entries = 128;
735 dev_priv->r600_max_hw_contexts = 4;
736 dev_priv->r600_max_gs_threads = 4;
737 dev_priv->r600_sx_max_export_size = 128;
738 dev_priv->r600_sx_max_export_pos_size = 16;
739 dev_priv->r600_sx_max_export_smx_size = 128;
740 dev_priv->r600_sq_num_cf_insts = 1;
743 dev_priv->r600_max_pipes = 4;
744 dev_priv->r600_max_tile_pipes = 4;
745 dev_priv->r600_max_simds = 4;
746 dev_priv->r600_max_backends = 4;
747 dev_priv->r600_max_gprs = 192;
748 dev_priv->r600_max_threads = 192;
749 dev_priv->r600_max_stack_entries = 256;
750 dev_priv->r600_max_hw_contexts = 8;
751 dev_priv->r600_max_gs_threads = 16;
752 dev_priv->r600_sx_max_export_size = 128;
753 dev_priv->r600_sx_max_export_pos_size = 16;
754 dev_priv->r600_sx_max_export_smx_size = 128;
755 dev_priv->r600_sq_num_cf_insts = 2;
763 for (i = 0; i < 32; i++) {
764 RADEON_WRITE((0x2c14 + j), 0x00000000);
765 RADEON_WRITE((0x2c18 + j), 0x00000000);
766 RADEON_WRITE((0x2c1c + j), 0x00000000);
767 RADEON_WRITE((0x2c20 + j), 0x00000000);
768 RADEON_WRITE((0x2c24 + j), 0x00000000);
772 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
774 /* setup tiling, simd, pipe config */
775 ramcfg = RADEON_READ(R600_RAMCFG);
777 switch (dev_priv->r600_max_tile_pipes) {
779 gb_tiling_config |= R600_PIPE_TILING(0);
782 gb_tiling_config |= R600_PIPE_TILING(1);
785 gb_tiling_config |= R600_PIPE_TILING(2);
788 gb_tiling_config |= R600_PIPE_TILING(3);
794 gb_tiling_config |= R600_BANK_TILING((ramcfg >> R600_NOOFBANK_SHIFT) & R600_NOOFBANK_MASK);
796 gb_tiling_config |= R600_GROUP_SIZE(0);
798 if (((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK) > 3) {
799 gb_tiling_config |= R600_ROW_TILING(3);
800 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
803 R600_ROW_TILING(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
805 R600_SAMPLE_SPLIT(((ramcfg >> R600_NOOFROWS_SHIFT) & R600_NOOFROWS_MASK));
808 gb_tiling_config |= R600_BANK_SWAPS(1);
810 backend_map = r600_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
811 dev_priv->r600_max_backends,
812 (0xff << dev_priv->r600_max_backends) & 0xff);
813 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
815 cc_gc_shader_pipe_config =
816 R600_INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R6XX_MAX_PIPES_MASK);
817 cc_gc_shader_pipe_config |=
818 R600_INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R6XX_MAX_SIMDS_MASK);
820 cc_rb_backend_disable =
821 R600_BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R6XX_MAX_BACKENDS_MASK);
823 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
824 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
825 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
827 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
828 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
829 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
832 R6XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
833 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
834 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
836 /* set HW defaults for 3D engine */
837 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
838 R600_ROQ_IB2_START(0x2b)));
840 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, (R600_MEQ_END(0x40) |
841 R600_ROQ_END(0x40)));
843 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
848 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670)
849 RADEON_WRITE(R600_ARB_GDEC_RD_CNTL, 0x00000021);
851 sx_debug_1 = RADEON_READ(R600_SX_DEBUG_1);
852 sx_debug_1 |= R600_SMX_EVENT_RELEASE;
853 if (((dev_priv->flags & RADEON_FAMILY_MASK) > CHIP_R600))
854 sx_debug_1 |= R600_ENABLE_NEW_SMX_ADDRESS;
855 RADEON_WRITE(R600_SX_DEBUG_1, sx_debug_1);
857 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
858 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
859 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
860 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
861 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
862 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
863 RADEON_WRITE(R600_DB_DEBUG, R600_PREZ_MUST_WAIT_FOR_POSTZ_DONE);
865 RADEON_WRITE(R600_DB_DEBUG, 0);
867 RADEON_WRITE(R600_DB_WATERMARKS, (R600_DEPTH_FREE(4) |
868 R600_DEPTH_FLUSH(16) |
869 R600_DEPTH_PENDING_FREE(4) |
870 R600_DEPTH_CACHELINE_FREE(16)));
871 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
872 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 0);
874 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
875 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(0));
877 sq_ms_fifo_sizes = RADEON_READ(R600_SQ_MS_FIFO_SIZES);
878 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
879 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
880 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
881 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
882 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(0xa) |
883 R600_FETCH_FIFO_HIWATER(0xa) |
884 R600_DONE_FIFO_HIWATER(0xe0) |
885 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
886 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) ||
887 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630)) {
888 sq_ms_fifo_sizes &= ~R600_DONE_FIFO_HIWATER(0xff);
889 sq_ms_fifo_sizes |= R600_DONE_FIFO_HIWATER(0x4);
891 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
893 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
894 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
896 sq_config = RADEON_READ(R600_SQ_CONFIG);
897 sq_config &= ~(R600_PS_PRIO(3) |
901 sq_config |= (R600_DX9_CONSTS |
908 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_R600) {
909 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(124) |
910 R600_NUM_VS_GPRS(124) |
911 R600_NUM_CLAUSE_TEMP_GPRS(4));
912 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(0) |
913 R600_NUM_ES_GPRS(0));
914 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(136) |
915 R600_NUM_VS_THREADS(48) |
916 R600_NUM_GS_THREADS(4) |
917 R600_NUM_ES_THREADS(4));
918 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(128) |
919 R600_NUM_VS_STACK_ENTRIES(128));
920 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(0) |
921 R600_NUM_ES_STACK_ENTRIES(0));
922 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
923 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
924 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
925 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880)) {
926 /* no vertex cache */
927 sq_config &= ~R600_VC_ENABLE;
929 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
930 R600_NUM_VS_GPRS(44) |
931 R600_NUM_CLAUSE_TEMP_GPRS(2));
932 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
933 R600_NUM_ES_GPRS(17));
934 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
935 R600_NUM_VS_THREADS(78) |
936 R600_NUM_GS_THREADS(4) |
937 R600_NUM_ES_THREADS(31));
938 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
939 R600_NUM_VS_STACK_ENTRIES(40));
940 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
941 R600_NUM_ES_STACK_ENTRIES(16));
942 } else if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV630) ||
943 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV635)) {
944 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
945 R600_NUM_VS_GPRS(44) |
946 R600_NUM_CLAUSE_TEMP_GPRS(2));
947 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(18) |
948 R600_NUM_ES_GPRS(18));
949 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
950 R600_NUM_VS_THREADS(78) |
951 R600_NUM_GS_THREADS(4) |
952 R600_NUM_ES_THREADS(31));
953 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(40) |
954 R600_NUM_VS_STACK_ENTRIES(40));
955 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(32) |
956 R600_NUM_ES_STACK_ENTRIES(16));
957 } else if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV670) {
958 sq_gpr_resource_mgmt_1 = (R600_NUM_PS_GPRS(44) |
959 R600_NUM_VS_GPRS(44) |
960 R600_NUM_CLAUSE_TEMP_GPRS(2));
961 sq_gpr_resource_mgmt_2 = (R600_NUM_GS_GPRS(17) |
962 R600_NUM_ES_GPRS(17));
963 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS(79) |
964 R600_NUM_VS_THREADS(78) |
965 R600_NUM_GS_THREADS(4) |
966 R600_NUM_ES_THREADS(31));
967 sq_stack_resource_mgmt_1 = (R600_NUM_PS_STACK_ENTRIES(64) |
968 R600_NUM_VS_STACK_ENTRIES(64));
969 sq_stack_resource_mgmt_2 = (R600_NUM_GS_STACK_ENTRIES(64) |
970 R600_NUM_ES_STACK_ENTRIES(64));
973 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
974 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
975 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
976 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
977 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
978 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
980 if (((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV610) ||
981 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV620) ||
982 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS780) ||
983 ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RS880))
984 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_TC_ONLY));
986 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, R600_CACHE_INVALIDATION(R600_VC_AND_TC));
988 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_2S, (R600_S0_X(0xc) |
992 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_4S, (R600_S0_X(0xe) |
1000 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD0, (R600_S0_X(0xe) |
1008 RADEON_WRITE(R600_PA_SC_AA_SAMPLE_LOCS_8S_WD1, (R600_S4_X(0x6) |
1018 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1022 gs_prim_buffer_depth = 0;
1028 gs_prim_buffer_depth = 32;
1031 gs_prim_buffer_depth = 128;
1037 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1038 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1039 /* Max value for this is 256 */
1040 if (vgt_gs_per_es > 256)
1041 vgt_gs_per_es = 256;
1043 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1044 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1045 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1046 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1048 /* more default values. 2D/3D driver should adjust as needed */
1049 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1050 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1051 RADEON_WRITE(R600_SX_MISC, 0);
1052 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1053 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1054 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1055 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1056 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1057 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1059 /* clear render buffer base addresses */
1060 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1061 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1062 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1063 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1064 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1065 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1066 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1067 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1069 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1074 tc_cntl = R600_TC_L2_SIZE(8);
1078 tc_cntl = R600_TC_L2_SIZE(4);
1081 tc_cntl = R600_TC_L2_SIZE(0) | R600_L2_DISABLE_LATE_HIT;
1084 tc_cntl = R600_TC_L2_SIZE(0);
1088 RADEON_WRITE(R600_TC_CNTL, tc_cntl);
1090 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1091 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1093 arb_pop = RADEON_READ(R600_ARB_POP);
1094 arb_pop |= R600_ENABLE_TC128;
1095 RADEON_WRITE(R600_ARB_POP, arb_pop);
1097 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1098 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1099 R600_NUM_CLIP_SEQ(3)));
1100 RADEON_WRITE(R600_PA_SC_ENHANCE, R600_FORCE_EOV_MAX_CLK_CNT(4095));
1104 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1106 u32 backend_disable_mask)
1108 u32 backend_map = 0;
1109 u32 enabled_backends_mask;
1110 u32 enabled_backends_count;
1112 u32 swizzle_pipe[R7XX_MAX_PIPES];
1116 if (num_tile_pipes > R7XX_MAX_PIPES)
1117 num_tile_pipes = R7XX_MAX_PIPES;
1118 if (num_tile_pipes < 1)
1120 if (num_backends > R7XX_MAX_BACKENDS)
1121 num_backends = R7XX_MAX_BACKENDS;
1122 if (num_backends < 1)
1125 enabled_backends_mask = 0;
1126 enabled_backends_count = 0;
1127 for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
1128 if (((backend_disable_mask >> i) & 1) == 0) {
1129 enabled_backends_mask |= (1 << i);
1130 ++enabled_backends_count;
1132 if (enabled_backends_count == num_backends)
1136 if (enabled_backends_count == 0) {
1137 enabled_backends_mask = 1;
1138 enabled_backends_count = 1;
1141 if (enabled_backends_count != num_backends)
1142 num_backends = enabled_backends_count;
1144 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
1145 switch (num_tile_pipes) {
1147 swizzle_pipe[0] = 0;
1150 swizzle_pipe[0] = 0;
1151 swizzle_pipe[1] = 1;
1154 swizzle_pipe[0] = 0;
1155 swizzle_pipe[1] = 2;
1156 swizzle_pipe[2] = 1;
1159 swizzle_pipe[0] = 0;
1160 swizzle_pipe[1] = 2;
1161 swizzle_pipe[2] = 3;
1162 swizzle_pipe[3] = 1;
1165 swizzle_pipe[0] = 0;
1166 swizzle_pipe[1] = 2;
1167 swizzle_pipe[2] = 4;
1168 swizzle_pipe[3] = 1;
1169 swizzle_pipe[4] = 3;
1172 swizzle_pipe[0] = 0;
1173 swizzle_pipe[1] = 2;
1174 swizzle_pipe[2] = 4;
1175 swizzle_pipe[3] = 5;
1176 swizzle_pipe[4] = 3;
1177 swizzle_pipe[5] = 1;
1180 swizzle_pipe[0] = 0;
1181 swizzle_pipe[1] = 2;
1182 swizzle_pipe[2] = 4;
1183 swizzle_pipe[3] = 6;
1184 swizzle_pipe[4] = 3;
1185 swizzle_pipe[5] = 1;
1186 swizzle_pipe[6] = 5;
1189 swizzle_pipe[0] = 0;
1190 swizzle_pipe[1] = 2;
1191 swizzle_pipe[2] = 4;
1192 swizzle_pipe[3] = 6;
1193 swizzle_pipe[4] = 3;
1194 swizzle_pipe[5] = 1;
1195 swizzle_pipe[6] = 7;
1196 swizzle_pipe[7] = 5;
1201 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1202 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1203 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1205 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1207 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
1213 static void r700_gfx_init(struct drm_device *dev,
1214 drm_radeon_private_t *dev_priv)
1216 int i, j, num_qd_pipes;
1219 u32 num_gs_verts_per_thread;
1221 u32 gs_prim_buffer_depth = 0;
1222 u32 sq_ms_fifo_sizes;
1224 u32 sq_thread_resource_mgmt;
1225 u32 hdp_host_path_cntl;
1226 u32 sq_dyn_gpr_size_simd_ab_0;
1228 u32 gb_tiling_config = 0;
1229 u32 cc_rb_backend_disable = 0;
1230 u32 cc_gc_shader_pipe_config = 0;
1234 /* setup chip specs */
1235 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1237 dev_priv->r600_max_pipes = 4;
1238 dev_priv->r600_max_tile_pipes = 8;
1239 dev_priv->r600_max_simds = 10;
1240 dev_priv->r600_max_backends = 4;
1241 dev_priv->r600_max_gprs = 256;
1242 dev_priv->r600_max_threads = 248;
1243 dev_priv->r600_max_stack_entries = 512;
1244 dev_priv->r600_max_hw_contexts = 8;
1245 dev_priv->r600_max_gs_threads = 16 * 2;
1246 dev_priv->r600_sx_max_export_size = 128;
1247 dev_priv->r600_sx_max_export_pos_size = 16;
1248 dev_priv->r600_sx_max_export_smx_size = 112;
1249 dev_priv->r600_sq_num_cf_insts = 2;
1251 dev_priv->r700_sx_num_of_sets = 7;
1252 dev_priv->r700_sc_prim_fifo_size = 0xF9;
1253 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1254 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1257 dev_priv->r600_max_pipes = 4;
1258 dev_priv->r600_max_tile_pipes = 4;
1259 dev_priv->r600_max_simds = 8;
1260 dev_priv->r600_max_backends = 4;
1261 dev_priv->r600_max_gprs = 256;
1262 dev_priv->r600_max_threads = 248;
1263 dev_priv->r600_max_stack_entries = 512;
1264 dev_priv->r600_max_hw_contexts = 8;
1265 dev_priv->r600_max_gs_threads = 16 * 2;
1266 dev_priv->r600_sx_max_export_size = 256;
1267 dev_priv->r600_sx_max_export_pos_size = 32;
1268 dev_priv->r600_sx_max_export_smx_size = 224;
1269 dev_priv->r600_sq_num_cf_insts = 2;
1271 dev_priv->r700_sx_num_of_sets = 7;
1272 dev_priv->r700_sc_prim_fifo_size = 0x100;
1273 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1274 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1276 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1277 dev_priv->r600_sx_max_export_pos_size -= 16;
1278 dev_priv->r600_sx_max_export_smx_size += 16;
1282 dev_priv->r600_max_pipes = 2;
1283 dev_priv->r600_max_tile_pipes = 4;
1284 dev_priv->r600_max_simds = 8;
1285 dev_priv->r600_max_backends = 2;
1286 dev_priv->r600_max_gprs = 128;
1287 dev_priv->r600_max_threads = 248;
1288 dev_priv->r600_max_stack_entries = 256;
1289 dev_priv->r600_max_hw_contexts = 8;
1290 dev_priv->r600_max_gs_threads = 16 * 2;
1291 dev_priv->r600_sx_max_export_size = 256;
1292 dev_priv->r600_sx_max_export_pos_size = 32;
1293 dev_priv->r600_sx_max_export_smx_size = 224;
1294 dev_priv->r600_sq_num_cf_insts = 2;
1296 dev_priv->r700_sx_num_of_sets = 7;
1297 dev_priv->r700_sc_prim_fifo_size = 0xf9;
1298 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1299 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1301 if (dev_priv->r600_sx_max_export_pos_size > 16) {
1302 dev_priv->r600_sx_max_export_pos_size -= 16;
1303 dev_priv->r600_sx_max_export_smx_size += 16;
1307 dev_priv->r600_max_pipes = 2;
1308 dev_priv->r600_max_tile_pipes = 2;
1309 dev_priv->r600_max_simds = 2;
1310 dev_priv->r600_max_backends = 1;
1311 dev_priv->r600_max_gprs = 256;
1312 dev_priv->r600_max_threads = 192;
1313 dev_priv->r600_max_stack_entries = 256;
1314 dev_priv->r600_max_hw_contexts = 4;
1315 dev_priv->r600_max_gs_threads = 8 * 2;
1316 dev_priv->r600_sx_max_export_size = 128;
1317 dev_priv->r600_sx_max_export_pos_size = 16;
1318 dev_priv->r600_sx_max_export_smx_size = 112;
1319 dev_priv->r600_sq_num_cf_insts = 1;
1321 dev_priv->r700_sx_num_of_sets = 7;
1322 dev_priv->r700_sc_prim_fifo_size = 0x40;
1323 dev_priv->r700_sc_hiz_tile_fifo_size = 0x30;
1324 dev_priv->r700_sc_earlyz_tile_fifo_fize = 0x130;
1330 /* Initialize HDP */
1332 for (i = 0; i < 32; i++) {
1333 RADEON_WRITE((0x2c14 + j), 0x00000000);
1334 RADEON_WRITE((0x2c18 + j), 0x00000000);
1335 RADEON_WRITE((0x2c1c + j), 0x00000000);
1336 RADEON_WRITE((0x2c20 + j), 0x00000000);
1337 RADEON_WRITE((0x2c24 + j), 0x00000000);
1341 RADEON_WRITE(R600_GRBM_CNTL, R600_GRBM_READ_TIMEOUT(0xff));
1343 /* setup tiling, simd, pipe config */
1344 mc_arb_ramcfg = RADEON_READ(R700_MC_ARB_RAMCFG);
1346 switch (dev_priv->r600_max_tile_pipes) {
1348 gb_tiling_config |= R600_PIPE_TILING(0);
1351 gb_tiling_config |= R600_PIPE_TILING(1);
1354 gb_tiling_config |= R600_PIPE_TILING(2);
1357 gb_tiling_config |= R600_PIPE_TILING(3);
1363 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1364 gb_tiling_config |= R600_BANK_TILING(1);
1366 gb_tiling_config |= R600_BANK_TILING((mc_arb_ramcfg >> R700_NOOFBANK_SHIFT) & R700_NOOFBANK_MASK);
1368 gb_tiling_config |= R600_GROUP_SIZE(0);
1370 if (((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK) > 3) {
1371 gb_tiling_config |= R600_ROW_TILING(3);
1372 gb_tiling_config |= R600_SAMPLE_SPLIT(3);
1375 R600_ROW_TILING(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1377 R600_SAMPLE_SPLIT(((mc_arb_ramcfg >> R700_NOOFROWS_SHIFT) & R700_NOOFROWS_MASK));
1380 gb_tiling_config |= R600_BANK_SWAPS(1);
1382 backend_map = r700_get_tile_pipe_to_backend_map(dev_priv->r600_max_tile_pipes,
1383 dev_priv->r600_max_backends,
1384 (0xff << dev_priv->r600_max_backends) & 0xff);
1385 gb_tiling_config |= R600_BACKEND_MAP(backend_map);
1387 cc_gc_shader_pipe_config =
1388 R600_INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << dev_priv->r600_max_pipes) & R7XX_MAX_PIPES_MASK);
1389 cc_gc_shader_pipe_config |=
1390 R600_INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << dev_priv->r600_max_simds) & R7XX_MAX_SIMDS_MASK);
1392 cc_rb_backend_disable =
1393 R600_BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << dev_priv->r600_max_backends) & R7XX_MAX_BACKENDS_MASK);
1395 RADEON_WRITE(R600_GB_TILING_CONFIG, gb_tiling_config);
1396 RADEON_WRITE(R600_DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1397 RADEON_WRITE(R600_HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
1399 RADEON_WRITE(R600_CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1400 RADEON_WRITE(R600_CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1401 RADEON_WRITE(R600_GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1403 RADEON_WRITE(R700_CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1404 RADEON_WRITE(R700_CGTS_SYS_TCC_DISABLE, 0);
1405 RADEON_WRITE(R700_CGTS_TCC_DISABLE, 0);
1406 RADEON_WRITE(R700_CGTS_USER_SYS_TCC_DISABLE, 0);
1407 RADEON_WRITE(R700_CGTS_USER_TCC_DISABLE, 0);
1410 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & R600_INACTIVE_QD_PIPES_MASK);
1411 RADEON_WRITE(R600_VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & R600_DEALLOC_DIST_MASK);
1412 RADEON_WRITE(R600_VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & R600_VTX_REUSE_DEPTH_MASK);
1414 /* set HW defaults for 3D engine */
1415 RADEON_WRITE(R600_CP_QUEUE_THRESHOLDS, (R600_ROQ_IB1_START(0x16) |
1416 R600_ROQ_IB2_START(0x2b)));
1418 RADEON_WRITE(R600_CP_MEQ_THRESHOLDS, R700_STQ_SPLIT(0x30));
1420 RADEON_WRITE(R600_TA_CNTL_AUX, (R600_DISABLE_CUBE_ANISO |
1421 R600_SYNC_GRADIENT |
1423 R600_SYNC_ALIGNER));
1425 sx_debug_1 = RADEON_READ(R700_SX_DEBUG_1);
1426 sx_debug_1 |= R700_ENABLE_NEW_SMX_ADDRESS;
1427 RADEON_WRITE(R700_SX_DEBUG_1, sx_debug_1);
1429 smx_dc_ctl0 = RADEON_READ(R600_SMX_DC_CTL0);
1430 smx_dc_ctl0 &= ~R700_CACHE_DEPTH(0x1ff);
1431 smx_dc_ctl0 |= R700_CACHE_DEPTH((dev_priv->r700_sx_num_of_sets * 64) - 1);
1432 RADEON_WRITE(R600_SMX_DC_CTL0, smx_dc_ctl0);
1434 RADEON_WRITE(R700_SMX_EVENT_CTL, (R700_ES_FLUSH_CTL(4) |
1435 R700_GS_FLUSH_CTL(4) |
1436 R700_ACK_FLUSH_CTL(3) |
1437 R700_SYNC_FLUSH_CTL));
1439 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV770)
1440 RADEON_WRITE(R700_DB_DEBUG3, R700_DB_CLK_OFF_DELAY(0x1f));
1442 db_debug4 = RADEON_READ(RV700_DB_DEBUG4);
1443 db_debug4 |= RV700_DISABLE_TILE_COVERED_FOR_PS_ITER;
1444 RADEON_WRITE(RV700_DB_DEBUG4, db_debug4);
1447 RADEON_WRITE(R600_SX_EXPORT_BUFFER_SIZES, (R600_COLOR_BUFFER_SIZE((dev_priv->r600_sx_max_export_size / 4) - 1) |
1448 R600_POSITION_BUFFER_SIZE((dev_priv->r600_sx_max_export_pos_size / 4) - 1) |
1449 R600_SMX_BUFFER_SIZE((dev_priv->r600_sx_max_export_smx_size / 4) - 1)));
1451 RADEON_WRITE(R700_PA_SC_FIFO_SIZE_R7XX, (R700_SC_PRIM_FIFO_SIZE(dev_priv->r700_sc_prim_fifo_size) |
1452 R700_SC_HIZ_TILE_FIFO_SIZE(dev_priv->r700_sc_hiz_tile_fifo_size) |
1453 R700_SC_EARLYZ_TILE_FIFO_SIZE(dev_priv->r700_sc_earlyz_tile_fifo_fize)));
1455 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1457 RADEON_WRITE(R600_VGT_NUM_INSTANCES, 1);
1459 RADEON_WRITE(R600_SPI_CONFIG_CNTL, R600_GPR_WRITE_PRIORITY(0));
1461 RADEON_WRITE(R600_SPI_CONFIG_CNTL_1, R600_VTX_DONE_DELAY(4));
1463 RADEON_WRITE(R600_CP_PERFMON_CNTL, 0);
1465 sq_ms_fifo_sizes = (R600_CACHE_FIFO_SIZE(16 * dev_priv->r600_sq_num_cf_insts) |
1466 R600_DONE_FIFO_HIWATER(0xe0) |
1467 R600_ALU_UPDATE_FIFO_HIWATER(0x8));
1468 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1470 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x1);
1476 sq_ms_fifo_sizes |= R600_FETCH_FIFO_HIWATER(0x4);
1479 RADEON_WRITE(R600_SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
1481 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1482 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1484 sq_config = RADEON_READ(R600_SQ_CONFIG);
1485 sq_config &= ~(R600_PS_PRIO(3) |
1489 sq_config |= (R600_DX9_CONSTS |
1496 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1497 /* no vertex cache */
1498 sq_config &= ~R600_VC_ENABLE;
1500 RADEON_WRITE(R600_SQ_CONFIG, sq_config);
1502 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_1, (R600_NUM_PS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1503 R600_NUM_VS_GPRS((dev_priv->r600_max_gprs * 24)/64) |
1504 R600_NUM_CLAUSE_TEMP_GPRS(((dev_priv->r600_max_gprs * 24)/64)/2)));
1506 RADEON_WRITE(R600_SQ_GPR_RESOURCE_MGMT_2, (R600_NUM_GS_GPRS((dev_priv->r600_max_gprs * 7)/64) |
1507 R600_NUM_ES_GPRS((dev_priv->r600_max_gprs * 7)/64)));
1509 sq_thread_resource_mgmt = (R600_NUM_PS_THREADS((dev_priv->r600_max_threads * 4)/8) |
1510 R600_NUM_VS_THREADS((dev_priv->r600_max_threads * 2)/8) |
1511 R600_NUM_ES_THREADS((dev_priv->r600_max_threads * 1)/8));
1512 if (((dev_priv->r600_max_threads * 1) / 8) > dev_priv->r600_max_gs_threads)
1513 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS(dev_priv->r600_max_gs_threads);
1515 sq_thread_resource_mgmt |= R600_NUM_GS_THREADS((dev_priv->r600_max_gs_threads * 1)/8);
1516 RADEON_WRITE(R600_SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1518 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_1, (R600_NUM_PS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1519 R600_NUM_VS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1521 RADEON_WRITE(R600_SQ_STACK_RESOURCE_MGMT_2, (R600_NUM_GS_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4) |
1522 R600_NUM_ES_STACK_ENTRIES((dev_priv->r600_max_stack_entries * 1)/4)));
1524 sq_dyn_gpr_size_simd_ab_0 = (R700_SIMDA_RING0((dev_priv->r600_max_gprs * 38)/64) |
1525 R700_SIMDA_RING1((dev_priv->r600_max_gprs * 38)/64) |
1526 R700_SIMDB_RING0((dev_priv->r600_max_gprs * 38)/64) |
1527 R700_SIMDB_RING1((dev_priv->r600_max_gprs * 38)/64));
1529 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
1530 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
1531 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
1532 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
1533 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
1534 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
1535 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
1536 RADEON_WRITE(R700_SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
1538 RADEON_WRITE(R700_PA_SC_FORCE_EOV_MAX_CNTS, (R700_FORCE_EOV_MAX_CLK_CNT(4095) |
1539 R700_FORCE_EOV_MAX_REZ_CNT(255)));
1541 if ((dev_priv->flags & RADEON_FAMILY_MASK) == CHIP_RV710)
1542 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_TC_ONLY) |
1543 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1545 RADEON_WRITE(R600_VGT_CACHE_INVALIDATION, (R600_CACHE_INVALIDATION(R600_VC_AND_TC) |
1546 R700_AUTO_INVLD_EN(R700_ES_AND_GS_AUTO)));
1548 switch (dev_priv->flags & RADEON_FAMILY_MASK) {
1552 gs_prim_buffer_depth = 384;
1555 gs_prim_buffer_depth = 128;
1561 num_gs_verts_per_thread = dev_priv->r600_max_pipes * 16;
1562 vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
1563 /* Max value for this is 256 */
1564 if (vgt_gs_per_es > 256)
1565 vgt_gs_per_es = 256;
1567 RADEON_WRITE(R600_VGT_ES_PER_GS, 128);
1568 RADEON_WRITE(R600_VGT_GS_PER_ES, vgt_gs_per_es);
1569 RADEON_WRITE(R600_VGT_GS_PER_VS, 2);
1571 /* more default values. 2D/3D driver should adjust as needed */
1572 RADEON_WRITE(R600_VGT_GS_VERTEX_REUSE, 16);
1573 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE_STATE, 0);
1574 RADEON_WRITE(R600_VGT_STRMOUT_EN, 0);
1575 RADEON_WRITE(R600_SX_MISC, 0);
1576 RADEON_WRITE(R600_PA_SC_MODE_CNTL, 0);
1577 RADEON_WRITE(R700_PA_SC_EDGERULE, 0xaaaaaaaa);
1578 RADEON_WRITE(R600_PA_SC_AA_CONFIG, 0);
1579 RADEON_WRITE(R600_PA_SC_CLIPRECT_RULE, 0xffff);
1580 RADEON_WRITE(R600_PA_SC_LINE_STIPPLE, 0);
1581 RADEON_WRITE(R600_SPI_INPUT_Z, 0);
1582 RADEON_WRITE(R600_SPI_PS_IN_CONTROL_0, R600_NUM_INTERP(2));
1583 RADEON_WRITE(R600_CB_COLOR7_FRAG, 0);
1585 /* clear render buffer base addresses */
1586 RADEON_WRITE(R600_CB_COLOR0_BASE, 0);
1587 RADEON_WRITE(R600_CB_COLOR1_BASE, 0);
1588 RADEON_WRITE(R600_CB_COLOR2_BASE, 0);
1589 RADEON_WRITE(R600_CB_COLOR3_BASE, 0);
1590 RADEON_WRITE(R600_CB_COLOR4_BASE, 0);
1591 RADEON_WRITE(R600_CB_COLOR5_BASE, 0);
1592 RADEON_WRITE(R600_CB_COLOR6_BASE, 0);
1593 RADEON_WRITE(R600_CB_COLOR7_BASE, 0);
1595 RADEON_WRITE(R700_TCP_CNTL, 0);
1597 hdp_host_path_cntl = RADEON_READ(R600_HDP_HOST_PATH_CNTL);
1598 RADEON_WRITE(R600_HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1600 RADEON_WRITE(R600_PA_SC_MULTI_CHIP_CNTL, 0);
1602 RADEON_WRITE(R600_PA_CL_ENHANCE, (R600_CLIP_VTX_REORDER_ENA |
1603 R600_NUM_CLIP_SEQ(3)));
1607 static void r600_cp_init_ring_buffer(struct drm_device *dev,
1608 drm_radeon_private_t *dev_priv,
1609 struct drm_file *file_priv)
1614 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
1615 r700_gfx_init(dev, dev_priv);
1617 r600_gfx_init(dev, dev_priv);
1619 RADEON_WRITE(R600_GRBM_SOFT_RESET, R600_SOFT_RESET_CP);
1620 RADEON_READ(R600_GRBM_SOFT_RESET);
1622 RADEON_WRITE(R600_GRBM_SOFT_RESET, 0);
1625 /* Set ring buffer size */
1627 RADEON_WRITE(R600_CP_RB_CNTL,
1628 RADEON_BUF_SWAP_32BIT |
1629 RADEON_RB_NO_UPDATE |
1630 (dev_priv->ring.rptr_update_l2qw << 8) |
1631 dev_priv->ring.size_l2qw);
1633 RADEON_WRITE(R600_CP_RB_CNTL,
1634 RADEON_RB_NO_UPDATE |
1635 (dev_priv->ring.rptr_update_l2qw << 8) |
1636 dev_priv->ring.size_l2qw);
1639 RADEON_WRITE(R600_CP_SEM_WAIT_TIMER, 0x4);
1641 /* Set the write pointer delay */
1642 RADEON_WRITE(R600_CP_RB_WPTR_DELAY, 0);
1645 RADEON_WRITE(R600_CP_RB_CNTL,
1646 RADEON_BUF_SWAP_32BIT |
1647 RADEON_RB_NO_UPDATE |
1648 RADEON_RB_RPTR_WR_ENA |
1649 (dev_priv->ring.rptr_update_l2qw << 8) |
1650 dev_priv->ring.size_l2qw);
1652 RADEON_WRITE(R600_CP_RB_CNTL,
1653 RADEON_RB_NO_UPDATE |
1654 RADEON_RB_RPTR_WR_ENA |
1655 (dev_priv->ring.rptr_update_l2qw << 8) |
1656 dev_priv->ring.size_l2qw);
1659 /* Initialize the ring buffer's read and write pointers */
1660 RADEON_WRITE(R600_CP_RB_RPTR_WR, 0);
1661 RADEON_WRITE(R600_CP_RB_WPTR, 0);
1662 SET_RING_HEAD(dev_priv, 0);
1663 dev_priv->ring.tail = 0;
1666 if (dev_priv->flags & RADEON_IS_AGP) {
1667 rptr_addr = dev_priv->ring_rptr->offset
1669 dev_priv->gart_vm_start;
1673 rptr_addr = dev_priv->ring_rptr->offset - dev->sg->vaddr +
1674 dev_priv->gart_vm_start;
1676 RADEON_WRITE(R600_CP_RB_RPTR_ADDR,
1677 rptr_addr & 0xffffffff);
1678 RADEON_WRITE(R600_CP_RB_RPTR_ADDR_HI,
1679 upper_32_bits(rptr_addr));
1682 RADEON_WRITE(R600_CP_RB_CNTL,
1683 RADEON_BUF_SWAP_32BIT |
1684 (dev_priv->ring.rptr_update_l2qw << 8) |
1685 dev_priv->ring.size_l2qw);
1687 RADEON_WRITE(R600_CP_RB_CNTL,
1688 (dev_priv->ring.rptr_update_l2qw << 8) |
1689 dev_priv->ring.size_l2qw);
1693 if (dev_priv->flags & RADEON_IS_AGP) {
1695 radeon_write_agp_base(dev_priv, dev->agp->base);
1698 radeon_write_agp_location(dev_priv,
1699 (((dev_priv->gart_vm_start - 1 +
1700 dev_priv->gart_size) & 0xffff0000) |
1701 (dev_priv->gart_vm_start >> 16)));
1703 ring_start = (dev_priv->cp_ring->offset
1705 + dev_priv->gart_vm_start);
1708 ring_start = dev_priv->cp_ring->offset - dev->sg->vaddr +
1709 dev_priv->gart_vm_start;
1711 RADEON_WRITE(R600_CP_RB_BASE, ring_start >> 8);
1713 RADEON_WRITE(R600_CP_ME_CNTL, 0xff);
1715 RADEON_WRITE(R600_CP_DEBUG, (1 << 27) | (1 << 28));
1717 /* Initialize the scratch register pointer. This will cause
1718 * the scratch register values to be written out to memory
1719 * whenever they are updated.
1721 * We simply put this behind the ring read pointer, this works
1722 * with PCI GART as well as (whatever kind of) AGP GART
1727 scratch_addr = RADEON_READ(R600_CP_RB_RPTR_ADDR);
1728 scratch_addr |= ((u64)RADEON_READ(R600_CP_RB_RPTR_ADDR_HI)) << 32;
1729 scratch_addr += R600_SCRATCH_REG_OFFSET;
1731 scratch_addr &= 0xffffffff;
1733 RADEON_WRITE(R600_SCRATCH_ADDR, (uint32_t)scratch_addr);
1736 RADEON_WRITE(R600_SCRATCH_UMSK, 0x7);
1738 /* Turn on bus mastering */
1739 radeon_enable_bm(dev_priv);
1741 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(0), 0);
1742 RADEON_WRITE(R600_LAST_FRAME_REG, 0);
1744 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(1), 0);
1745 RADEON_WRITE(R600_LAST_DISPATCH_REG, 0);
1747 radeon_write_ring_rptr(dev_priv, R600_SCRATCHOFF(2), 0);
1748 RADEON_WRITE(R600_LAST_CLEAR_REG, 0);
1750 /* reset sarea copies of these */
1751 if (dev_priv->sarea_priv) {
1752 dev_priv->sarea_priv->last_frame = 0;
1753 dev_priv->sarea_priv->last_dispatch = 0;
1754 dev_priv->sarea_priv->last_clear = 0;
1757 r600_do_wait_for_idle(dev_priv);
1761 int r600_do_cleanup_cp(struct drm_device *dev)
1763 drm_radeon_private_t *dev_priv = dev->dev_private;
1766 /* Make sure interrupts are disabled here because the uninstall ioctl
1767 * may not have been called from userspace and after dev_private
1768 * is freed, it's too late.
1770 if (dev->irq_enabled)
1771 drm_irq_uninstall(dev);
1774 if (dev_priv->flags & RADEON_IS_AGP) {
1775 if (dev_priv->cp_ring != NULL) {
1776 drm_core_ioremapfree(dev_priv->cp_ring, dev);
1777 dev_priv->cp_ring = NULL;
1779 if (dev_priv->ring_rptr != NULL) {
1780 drm_core_ioremapfree(dev_priv->ring_rptr, dev);
1781 dev_priv->ring_rptr = NULL;
1783 if (dev->agp_buffer_map != NULL) {
1784 drm_core_ioremapfree(dev->agp_buffer_map, dev);
1785 dev->agp_buffer_map = NULL;
1791 if (dev_priv->gart_info.bus_addr)
1792 r600_page_table_cleanup(dev, &dev_priv->gart_info);
1794 if (dev_priv->gart_info.gart_table_location == DRM_ATI_GART_FB) {
1795 drm_core_ioremapfree(&dev_priv->gart_info.mapping, dev);
1796 dev_priv->gart_info.addr = 0;
1799 /* only clear to the start of flags */
1800 memset(dev_priv, 0, offsetof(drm_radeon_private_t, flags));
1805 int r600_do_init_cp(struct drm_device *dev, drm_radeon_init_t *init,
1806 struct drm_file *file_priv)
1808 drm_radeon_private_t *dev_priv = dev->dev_private;
1812 /* if we require new memory map but we don't have it fail */
1813 if ((dev_priv->flags & RADEON_NEW_MEMMAP) && !dev_priv->new_memmap) {
1814 DRM_ERROR("Cannot initialise DRM on this card\nThis card requires a new X.org DDX for 3D\n");
1815 r600_do_cleanup_cp(dev);
1819 if (init->is_pci && (dev_priv->flags & RADEON_IS_AGP)) {
1820 DRM_DEBUG("Forcing AGP card to PCI mode\n");
1821 dev_priv->flags &= ~RADEON_IS_AGP;
1822 /* The writeback test succeeds, but when writeback is enabled,
1823 * the ring buffer read ptr update fails after first 128 bytes.
1826 } else if (!(dev_priv->flags & (RADEON_IS_AGP | RADEON_IS_PCI | RADEON_IS_PCIE))
1828 DRM_DEBUG("Restoring AGP flag\n");
1829 dev_priv->flags |= RADEON_IS_AGP;
1832 dev_priv->usec_timeout = init->usec_timeout;
1833 if (dev_priv->usec_timeout < 1 ||
1834 dev_priv->usec_timeout > RADEON_MAX_USEC_TIMEOUT) {
1835 DRM_DEBUG("TIMEOUT problem!\n");
1836 r600_do_cleanup_cp(dev);
1840 /* Enable vblank on CRTC1 for older X servers
1842 dev_priv->vblank_crtc = DRM_RADEON_VBLANK_CRTC1;
1844 dev_priv->do_boxes = 0;
1845 dev_priv->cp_mode = init->cp_mode;
1847 /* We don't support anything other than bus-mastering ring mode,
1848 * but the ring can be in either AGP or PCI space for the ring
1851 if ((init->cp_mode != RADEON_CSQ_PRIBM_INDDIS) &&
1852 (init->cp_mode != RADEON_CSQ_PRIBM_INDBM)) {
1853 DRM_DEBUG("BAD cp_mode (%x)!\n", init->cp_mode);
1854 r600_do_cleanup_cp(dev);
1858 switch (init->fb_bpp) {
1860 dev_priv->color_fmt = RADEON_COLOR_FORMAT_RGB565;
1864 dev_priv->color_fmt = RADEON_COLOR_FORMAT_ARGB8888;
1867 dev_priv->front_offset = init->front_offset;
1868 dev_priv->front_pitch = init->front_pitch;
1869 dev_priv->back_offset = init->back_offset;
1870 dev_priv->back_pitch = init->back_pitch;
1872 dev_priv->ring_offset = init->ring_offset;
1873 dev_priv->ring_rptr_offset = init->ring_rptr_offset;
1874 dev_priv->buffers_offset = init->buffers_offset;
1875 dev_priv->gart_textures_offset = init->gart_textures_offset;
1877 dev_priv->sarea = drm_getsarea(dev);
1878 if (!dev_priv->sarea) {
1879 DRM_ERROR("could not find sarea!\n");
1880 r600_do_cleanup_cp(dev);
1884 dev_priv->cp_ring = drm_core_findmap(dev, init->ring_offset);
1885 if (!dev_priv->cp_ring) {
1886 DRM_ERROR("could not find cp ring region!\n");
1887 r600_do_cleanup_cp(dev);
1890 dev_priv->ring_rptr = drm_core_findmap(dev, init->ring_rptr_offset);
1891 if (!dev_priv->ring_rptr) {
1892 DRM_ERROR("could not find ring read pointer!\n");
1893 r600_do_cleanup_cp(dev);
1896 dev->agp_buffer_token = init->buffers_offset;
1897 dev->agp_buffer_map = drm_core_findmap(dev, init->buffers_offset);
1898 if (!dev->agp_buffer_map) {
1899 DRM_ERROR("could not find dma buffer region!\n");
1900 r600_do_cleanup_cp(dev);
1904 if (init->gart_textures_offset) {
1905 dev_priv->gart_textures =
1906 drm_core_findmap(dev, init->gart_textures_offset);
1907 if (!dev_priv->gart_textures) {
1908 DRM_ERROR("could not find GART texture region!\n");
1909 r600_do_cleanup_cp(dev);
1914 dev_priv->sarea_priv =
1915 (drm_radeon_sarea_t *) ((u8 *) dev_priv->sarea->virtual +
1916 init->sarea_priv_offset);
1920 if (dev_priv->flags & RADEON_IS_AGP) {
1921 drm_core_ioremap_wc(dev_priv->cp_ring, dev);
1922 drm_core_ioremap_wc(dev_priv->ring_rptr, dev);
1923 drm_core_ioremap_wc(dev->agp_buffer_map, dev);
1924 if (!dev_priv->cp_ring->virtual ||
1925 !dev_priv->ring_rptr->virtual ||
1926 !dev->agp_buffer_map->virtual) {
1927 DRM_ERROR("could not find ioremap agp regions!\n");
1928 r600_do_cleanup_cp(dev);
1934 dev_priv->cp_ring->virtual =
1935 (void *)dev_priv->cp_ring->offset;
1936 dev_priv->ring_rptr->virtual =
1937 (void *)dev_priv->ring_rptr->offset;
1938 dev->agp_buffer_map->virtual =
1939 (void *)dev->agp_buffer_map->offset;
1941 DRM_DEBUG("dev_priv->cp_ring->virtual %p\n",
1942 dev_priv->cp_ring->virtual);
1943 DRM_DEBUG("dev_priv->ring_rptr->virtual %p\n",
1944 dev_priv->ring_rptr->virtual);
1945 DRM_DEBUG("dev->agp_buffer_map->virtual %p\n",
1946 dev->agp_buffer_map->virtual);
1949 dev_priv->fb_location = (radeon_read_fb_location(dev_priv) & 0xffff) << 24;
1951 (((radeon_read_fb_location(dev_priv) & 0xffff0000u) << 8) + 0x1000000)
1952 - dev_priv->fb_location;
1954 dev_priv->front_pitch_offset = (((dev_priv->front_pitch / 64) << 22) |
1955 ((dev_priv->front_offset
1956 + dev_priv->fb_location) >> 10));
1958 dev_priv->back_pitch_offset = (((dev_priv->back_pitch / 64) << 22) |
1959 ((dev_priv->back_offset
1960 + dev_priv->fb_location) >> 10));
1962 dev_priv->depth_pitch_offset = (((dev_priv->depth_pitch / 64) << 22) |
1963 ((dev_priv->depth_offset
1964 + dev_priv->fb_location) >> 10));
1966 dev_priv->gart_size = init->gart_size;
1968 /* New let's set the memory map ... */
1969 if (dev_priv->new_memmap) {
1972 DRM_INFO("Setting GART location based on new memory map\n");
1974 /* If using AGP, try to locate the AGP aperture at the same
1975 * location in the card and on the bus, though we have to
1980 if (dev_priv->flags & RADEON_IS_AGP) {
1981 base = dev->agp->base;
1982 /* Check if valid */
1983 if ((base + dev_priv->gart_size - 1) >= dev_priv->fb_location &&
1984 base < (dev_priv->fb_location + dev_priv->fb_size - 1)) {
1985 DRM_INFO("Can't use AGP base @0x%08lx, won't fit\n",
1991 /* If not or if AGP is at 0 (Macs), try to put it elsewhere */
1993 base = dev_priv->fb_location + dev_priv->fb_size;
1994 if (base < dev_priv->fb_location ||
1995 ((base + dev_priv->gart_size) & 0xfffffffful) < base)
1996 base = dev_priv->fb_location
1997 - dev_priv->gart_size;
1999 dev_priv->gart_vm_start = base & 0xffc00000u;
2000 if (dev_priv->gart_vm_start != base)
2001 DRM_INFO("GART aligned down from 0x%08x to 0x%08x\n",
2002 base, dev_priv->gart_vm_start);
2007 if (dev_priv->flags & RADEON_IS_AGP)
2008 dev_priv->gart_buffers_offset = (dev->agp_buffer_map->offset
2010 + dev_priv->gart_vm_start);
2013 dev_priv->gart_buffers_offset = dev->agp_buffer_map->offset -
2014 dev->sg->vaddr + dev_priv->gart_vm_start;
2016 DRM_DEBUG("fb 0x%08x size %d\n",
2017 (unsigned int) dev_priv->fb_location,
2018 (unsigned int) dev_priv->fb_size);
2019 DRM_DEBUG("dev_priv->gart_size %d\n", dev_priv->gart_size);
2020 DRM_DEBUG("dev_priv->gart_vm_start 0x%08x\n",
2021 (unsigned int) dev_priv->gart_vm_start);
2022 DRM_DEBUG("dev_priv->gart_buffers_offset 0x%08lx\n",
2023 dev_priv->gart_buffers_offset);
2025 dev_priv->ring.start = (u32 *) dev_priv->cp_ring->virtual;
2026 dev_priv->ring.end = ((u32 *) dev_priv->cp_ring->virtual
2027 + init->ring_size / sizeof(u32));
2028 dev_priv->ring.size = init->ring_size;
2029 dev_priv->ring.size_l2qw = drm_order(init->ring_size / 8);
2031 dev_priv->ring.rptr_update = /* init->rptr_update */ 4096;
2032 dev_priv->ring.rptr_update_l2qw = drm_order(/* init->rptr_update */ 4096 / 8);
2034 dev_priv->ring.fetch_size = /* init->fetch_size */ 32;
2035 dev_priv->ring.fetch_size_l2ow = drm_order(/* init->fetch_size */ 32 / 16);
2037 dev_priv->ring.tail_mask = (dev_priv->ring.size / sizeof(u32)) - 1;
2039 dev_priv->ring.high_mark = RADEON_RING_HIGH_MARK;
2042 if (dev_priv->flags & RADEON_IS_AGP) {
2043 /* XXX turn off pcie gart */
2047 dev_priv->gart_info.table_mask = DMA_BIT_MASK(32);
2048 /* if we have an offset set from userspace */
2049 if (!dev_priv->pcigart_offset_set) {
2050 DRM_ERROR("Need gart offset from userspace\n");
2051 r600_do_cleanup_cp(dev);
2055 DRM_DEBUG("Using gart offset 0x%08lx\n", dev_priv->pcigart_offset);
2057 dev_priv->gart_info.bus_addr =
2058 dev_priv->pcigart_offset + dev_priv->fb_location;
2059 dev_priv->gart_info.mapping.offset =
2060 dev_priv->pcigart_offset + dev_priv->fb_aper_offset;
2061 dev_priv->gart_info.mapping.size =
2062 dev_priv->gart_info.table_size;
2064 drm_core_ioremap_wc(&dev_priv->gart_info.mapping, dev);
2065 if (!dev_priv->gart_info.mapping.virtual) {
2066 DRM_ERROR("ioremap failed.\n");
2067 r600_do_cleanup_cp(dev);
2071 dev_priv->gart_info.addr =
2072 dev_priv->gart_info.mapping.virtual;
2074 DRM_DEBUG("Setting phys_pci_gart to %p %08lX\n",
2075 dev_priv->gart_info.addr,
2076 dev_priv->pcigart_offset);
2078 if (!r600_page_table_init(dev)) {
2079 DRM_ERROR("Failed to init GART table\n");
2080 r600_do_cleanup_cp(dev);
2084 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2090 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770))
2091 r700_cp_load_microcode(dev_priv);
2093 r600_cp_load_microcode(dev_priv);
2095 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2097 dev_priv->last_buf = 0;
2099 r600_do_engine_reset(dev);
2100 r600_test_writeback(dev_priv);
2107 int r600_do_resume_cp(struct drm_device *dev, struct drm_file *file_priv)
2109 drm_radeon_private_t *dev_priv = dev->dev_private;
2112 if (((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RV770)) {
2114 r700_cp_load_microcode(dev_priv);
2117 r600_cp_load_microcode(dev_priv);
2119 r600_cp_init_ring_buffer(dev, dev_priv, file_priv);
2120 r600_do_engine_reset(dev);
2125 /* Wait for the CP to go idle.
2127 int r600_do_cp_idle(drm_radeon_private_t *dev_priv)
2133 OUT_RING(CP_PACKET3(R600_IT_EVENT_WRITE, 0));
2134 OUT_RING(R600_CACHE_FLUSH_AND_INV_EVENT);
2135 /* wait for 3D idle clean */
2136 OUT_RING(CP_PACKET3(R600_IT_SET_CONFIG_REG, 1));
2137 OUT_RING((R600_WAIT_UNTIL - R600_SET_CONFIG_REG_OFFSET) >> 2);
2138 OUT_RING(RADEON_WAIT_3D_IDLE | RADEON_WAIT_3D_IDLECLEAN);
2143 return r600_do_wait_for_idle(dev_priv);
2146 /* Start the Command Processor.
2148 void r600_do_cp_start(drm_radeon_private_t *dev_priv)
2155 OUT_RING(CP_PACKET3(R600_IT_ME_INITIALIZE, 5));
2156 OUT_RING(0x00000001);
2157 if (((dev_priv->flags & RADEON_FAMILY_MASK) < CHIP_RV770))
2158 OUT_RING(0x00000003);
2160 OUT_RING(0x00000000);
2161 OUT_RING((dev_priv->r600_max_hw_contexts - 1));
2162 OUT_RING(R600_ME_INITIALIZE_DEVICE_ID(1));
2163 OUT_RING(0x00000000);
2164 OUT_RING(0x00000000);
2168 /* set the mux and reset the halt bit */
2170 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2172 dev_priv->cp_running = 1;
2176 void r600_do_cp_reset(drm_radeon_private_t *dev_priv)
2181 cur_read_ptr = RADEON_READ(R600_CP_RB_RPTR);
2182 RADEON_WRITE(R600_CP_RB_WPTR, cur_read_ptr);
2183 SET_RING_HEAD(dev_priv, cur_read_ptr);
2184 dev_priv->ring.tail = cur_read_ptr;
2187 void r600_do_cp_stop(drm_radeon_private_t *dev_priv)
2193 cp_me = 0xff | R600_CP_ME_HALT;
2195 RADEON_WRITE(R600_CP_ME_CNTL, cp_me);
2197 dev_priv->cp_running = 0;
2200 int r600_cp_dispatch_indirect(struct drm_device *dev,
2201 struct drm_buf *buf, int start, int end)
2203 drm_radeon_private_t *dev_priv = dev->dev_private;
2207 unsigned long offset = (dev_priv->gart_buffers_offset
2208 + buf->offset + start);
2209 int dwords = (end - start + 3) / sizeof(u32);
2211 DRM_DEBUG("dwords:%d\n", dwords);
2212 DRM_DEBUG("offset 0x%lx\n", offset);
2215 /* Indirect buffer data must be a multiple of 16 dwords.
2216 * pad the data with a Type-2 CP packet.
2218 while (dwords & 0xf) {
2220 ((char *)dev->agp_buffer_map->virtual
2221 + buf->offset + start);
2222 data[dwords++] = RADEON_CP_PACKET2;
2225 /* Fire off the indirect buffer */
2227 OUT_RING(CP_PACKET3(R600_IT_INDIRECT_BUFFER, 2));
2228 OUT_RING((offset & 0xfffffffc));
2229 OUT_RING((upper_32_bits(offset) & 0xff));
2237 void r600_cp_dispatch_swap(struct drm_device * dev)
2239 drm_radeon_private_t *dev_priv = dev->dev_private;
2240 drm_radeon_sarea_t *sarea_priv = dev_priv->sarea_priv;
2241 int nbox = sarea_priv->nbox;
2242 struct drm_clip_rect *pbox = sarea_priv->boxes;
2243 int i, cpp, src_pitch, dst_pitch;
2248 if (dev_priv->color_fmt == RADEON_COLOR_FORMAT_ARGB8888)
2253 if (dev_priv->sarea_priv->pfCurrentPage == 0) {
2254 src_pitch = dev_priv->back_pitch;
2255 dst_pitch = dev_priv->front_pitch;
2256 src = dev_priv->back_offset + dev_priv->fb_location;
2257 dst = dev_priv->front_offset + dev_priv->fb_location;
2259 src_pitch = dev_priv->front_pitch;
2260 dst_pitch = dev_priv->back_pitch;
2261 src = dev_priv->front_offset + dev_priv->fb_location;
2262 dst = dev_priv->back_offset + dev_priv->fb_location;
2265 if (r600_prepare_blit_copy(dev)) {
2266 DRM_ERROR("unable to allocate vertex buffer for swap buffer\n");
2269 for (i = 0; i < nbox; i++) {
2272 int w = pbox[i].x2 - x;
2273 int h = pbox[i].y2 - y;
2275 DRM_DEBUG("%d,%d-%d,%d\n", x, y, w, h);
2280 src_pitch, dst_pitch, cpp);
2282 r600_done_blit_copy(dev);
2284 /* Increment the frame counter. The client-side 3D driver must
2285 * throttle the framerate by waiting for this value before
2286 * performing the swapbuffer ioctl.
2288 dev_priv->sarea_priv->last_frame++;
2291 R600_FRAME_AGE(dev_priv->sarea_priv->last_frame);
2295 int r600_cp_dispatch_texture(struct drm_device * dev,
2296 struct drm_file *file_priv,
2297 drm_radeon_texture_t * tex,
2298 drm_radeon_tex_image_t * image)
2300 drm_radeon_private_t *dev_priv = dev->dev_private;
2301 struct drm_buf *buf;
2303 const u8 __user *data;
2304 int size, pass_size;
2305 u64 src_offset, dst_offset;
2307 if (!radeon_check_offset(dev_priv, tex->offset)) {
2308 DRM_ERROR("Invalid destination offset\n");
2312 /* this might fail for zero-sized uploads - are those illegal? */
2313 if (!radeon_check_offset(dev_priv, tex->offset + tex->height * tex->pitch - 1)) {
2314 DRM_ERROR("Invalid final destination offset\n");
2318 size = tex->height * tex->pitch;
2323 dst_offset = tex->offset;
2325 r600_prepare_blit_copy(dev);
2327 data = (const u8 __user *)image->data;
2330 buf = radeon_freelist_get(dev);
2332 DRM_DEBUG("EAGAIN\n");
2333 if (DRM_COPY_TO_USER(tex->image, image, sizeof(*image)))
2338 if (pass_size > buf->total)
2339 pass_size = buf->total;
2341 /* Dispatch the indirect buffer.
2344 (u32 *) ((char *)dev->agp_buffer_map->virtual +
2347 if (DRM_COPY_FROM_USER(buffer, data, pass_size)) {
2348 DRM_ERROR("EFAULT on pad, %d bytes\n", pass_size);
2352 buf->file_priv = file_priv;
2353 buf->used = pass_size;
2354 src_offset = dev_priv->gart_buffers_offset + buf->offset;
2356 r600_blit_copy(dev, src_offset, dst_offset, pass_size);
2358 radeon_cp_discard_buffer(dev, buf);
2360 /* Update the input parameters for next time */
2361 image->data = (const u8 __user *)image->data + pass_size;
2362 dst_offset += pass_size;
2365 r600_done_blit_copy(dev);