1 /* radeon_irq.c -- IRQ handling for radeon -*- linux-c -*- */
3 * Copyright (C) The Weather Channel, Inc. 2002. All Rights Reserved.
5 * The Weather Channel (TM) funded Tungsten Graphics to develop the
6 * initial release of the Radeon 8500 driver under the XFree86 license.
7 * This notice must be preserved.
9 * Permission is hereby granted, free of charge, to any person obtaining a
10 * copy of this software and associated documentation files (the "Software"),
11 * to deal in the Software without restriction, including without limitation
12 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
13 * and/or sell copies of the Software, and to permit persons to whom the
14 * Software is furnished to do so, subject to the following conditions:
16 * The above copyright notice and this permission notice (including the next
17 * paragraph) shall be included in all copies or substantial portions of the
20 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
21 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
23 * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
24 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
25 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
26 * DEALINGS IN THE SOFTWARE.
29 * Keith Whitwell <keith@tungstengraphics.com>
30 * Michel D�zer <michel@daenzer.net>
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
36 #include "dev/drm/drmP.h"
37 #include "dev/drm/drm.h"
38 #include "dev/drm/radeon_drm.h"
39 #include "dev/drm/radeon_drv.h"
41 void radeon_irq_set_state(struct drm_device *dev, u32 mask, int state)
43 drm_radeon_private_t *dev_priv = dev->dev_private;
46 dev_priv->irq_enable_reg |= mask;
48 dev_priv->irq_enable_reg &= ~mask;
51 RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
54 static void r500_vbl_irq_set_state(struct drm_device *dev, u32 mask, int state)
56 drm_radeon_private_t *dev_priv = dev->dev_private;
59 dev_priv->r500_disp_irq_reg |= mask;
61 dev_priv->r500_disp_irq_reg &= ~mask;
64 RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
67 int radeon_enable_vblank(struct drm_device *dev, int crtc)
69 drm_radeon_private_t *dev_priv = dev->dev_private;
71 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
74 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 1);
77 r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 1);
80 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
87 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 1);
90 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 1);
93 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
102 void radeon_disable_vblank(struct drm_device *dev, int crtc)
104 drm_radeon_private_t *dev_priv = dev->dev_private;
106 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
109 r500_vbl_irq_set_state(dev, R500_D1MODE_INT_MASK, 0);
112 r500_vbl_irq_set_state(dev, R500_D2MODE_INT_MASK, 0);
115 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
122 radeon_irq_set_state(dev, RADEON_CRTC_VBLANK_MASK, 0);
125 radeon_irq_set_state(dev, RADEON_CRTC2_VBLANK_MASK, 0);
128 DRM_ERROR("tried to enable vblank on non-existent crtc %d\n",
135 static __inline__ u32 radeon_acknowledge_irqs(drm_radeon_private_t * dev_priv, u32 *r500_disp_int)
137 u32 irqs = RADEON_READ(RADEON_GEN_INT_STATUS);
138 u32 irq_mask = RADEON_SW_INT_TEST;
141 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
142 /* vbl interrupts in a different place */
144 if (irqs & R500_DISPLAY_INT_STATUS) {
145 /* if a display interrupt */
148 disp_irq = RADEON_READ(R500_DISP_INTERRUPT_STATUS);
150 *r500_disp_int = disp_irq;
151 if (disp_irq & R500_D1_VBLANK_INTERRUPT) {
152 RADEON_WRITE(R500_D1MODE_VBLANK_STATUS, R500_VBLANK_ACK);
154 if (disp_irq & R500_D2_VBLANK_INTERRUPT) {
155 RADEON_WRITE(R500_D2MODE_VBLANK_STATUS, R500_VBLANK_ACK);
158 irq_mask |= R500_DISPLAY_INT_STATUS;
160 irq_mask |= RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT;
165 RADEON_WRITE(RADEON_GEN_INT_STATUS, irqs);
170 /* Interrupts - Used for device synchronization and flushing in the
171 * following circumstances:
173 * - Exclusive FB access with hw idle:
174 * - Wait for GUI Idle (?) interrupt, then do normal flush.
176 * - Frame throttling, NV_fence:
177 * - Drop marker irq's into command stream ahead of time.
178 * - Wait on irq's with lock *not held*
179 * - Check each for termination condition
181 * - Internally in cp_getbuffer, etc:
182 * - as above, but wait with lock held???
184 * NOTE: These functions are misleadingly named -- the irq's aren't
185 * tied to dma at all, this is just a hangover from dri prehistory.
188 irqreturn_t radeon_driver_irq_handler(DRM_IRQ_ARGS)
190 struct drm_device *dev = (struct drm_device *) arg;
191 drm_radeon_private_t *dev_priv =
192 (drm_radeon_private_t *) dev->dev_private;
197 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
200 /* Only consider the bits we're interested in - others could be used
203 stat = radeon_acknowledge_irqs(dev_priv, &r500_disp_int);
207 stat &= dev_priv->irq_enable_reg;
210 if (stat & RADEON_SW_INT_TEST)
211 DRM_WAKEUP(&dev_priv->swi_queue);
213 /* VBLANK interrupt */
214 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
215 if (r500_disp_int & R500_D1_VBLANK_INTERRUPT)
216 drm_handle_vblank(dev, 0);
217 if (r500_disp_int & R500_D2_VBLANK_INTERRUPT)
218 drm_handle_vblank(dev, 1);
220 if (stat & RADEON_CRTC_VBLANK_STAT)
221 drm_handle_vblank(dev, 0);
222 if (stat & RADEON_CRTC2_VBLANK_STAT)
223 drm_handle_vblank(dev, 1);
225 if (dev->msi_enabled) {
226 switch(dev_priv->flags & RADEON_FAMILY_MASK) {
229 tmp = RADEON_READ(RADEON_AIC_CNTL) &
231 RADEON_WRITE(RADEON_AIC_CNTL, tmp);
232 RADEON_WRITE(RADEON_AIC_CNTL,
233 tmp | RS400_MSI_REARM);
238 tmp = RADEON_READ(RADEON_BUS_CNTL) &
240 RADEON_WRITE(RADEON_BUS_CNTL, tmp);
241 RADEON_WRITE(RADEON_BUS_CNTL, tmp |
245 tmp = RADEON_READ(RADEON_MSI_REARM_EN) &
247 RADEON_WRITE(RADEON_MSI_REARM_EN, tmp);
248 RADEON_WRITE(RADEON_MSI_REARM_EN,
249 tmp | RV370_MSI_REARM_EN);
256 static int radeon_emit_irq(struct drm_device * dev)
258 drm_radeon_private_t *dev_priv = dev->dev_private;
262 atomic_inc(&dev_priv->swi_emitted);
263 ret = atomic_read(&dev_priv->swi_emitted);
266 OUT_RING_REG(RADEON_LAST_SWI_REG, ret);
267 OUT_RING_REG(RADEON_GEN_INT_STATUS, RADEON_SW_INT_FIRE);
274 static int radeon_wait_irq(struct drm_device * dev, int swi_nr)
276 drm_radeon_private_t *dev_priv =
277 (drm_radeon_private_t *) dev->dev_private;
280 if (RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr)
283 dev_priv->stats.boxes |= RADEON_BOX_WAIT_IDLE;
285 DRM_WAIT_ON(ret, dev_priv->swi_queue, 3 * DRM_HZ,
286 RADEON_READ(RADEON_LAST_SWI_REG) >= swi_nr);
288 if (ret == -ERESTART)
289 DRM_DEBUG("restarting syscall");
294 u32 radeon_get_vblank_counter(struct drm_device *dev, int crtc)
296 drm_radeon_private_t *dev_priv = dev->dev_private;
299 DRM_ERROR("called with no initialization\n");
303 if (crtc < 0 || crtc > 1) {
304 DRM_ERROR("Invalid crtc %d\n", crtc);
308 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600) {
310 return RADEON_READ(R500_D1CRTC_FRAME_COUNT);
312 return RADEON_READ(R500_D2CRTC_FRAME_COUNT);
315 return RADEON_READ(RADEON_CRTC_CRNT_FRAME);
317 return RADEON_READ(RADEON_CRTC2_CRNT_FRAME);
321 /* Needs the lock as it touches the ring.
323 int radeon_irq_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
325 drm_radeon_private_t *dev_priv = dev->dev_private;
326 drm_radeon_irq_emit_t *emit = data;
329 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
332 LOCK_TEST_WITH_RETURN(dev, file_priv);
335 DRM_ERROR("called with no initialization\n");
339 result = radeon_emit_irq(dev);
341 if (DRM_COPY_TO_USER(emit->irq_seq, &result, sizeof(int))) {
342 DRM_ERROR("copy_to_user\n");
349 /* Doesn't need the hardware lock.
351 int radeon_irq_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
353 drm_radeon_private_t *dev_priv = dev->dev_private;
354 drm_radeon_irq_wait_t *irqwait = data;
357 DRM_ERROR("called with no initialization\n");
361 return radeon_wait_irq(dev, irqwait->irq_seq);
366 void radeon_driver_irq_preinstall(struct drm_device * dev)
368 drm_radeon_private_t *dev_priv =
369 (drm_radeon_private_t *) dev->dev_private;
372 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
375 /* Disable *all* interrupts */
376 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
377 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
378 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
380 /* Clear bits if they're already high */
381 radeon_acknowledge_irqs(dev_priv, &dummy);
384 int radeon_driver_irq_postinstall(struct drm_device * dev)
386 drm_radeon_private_t *dev_priv =
387 (drm_radeon_private_t *) dev->dev_private;
389 atomic_set(&dev_priv->swi_emitted, 0);
390 DRM_INIT_WAITQUEUE(&dev_priv->swi_queue);
392 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
395 radeon_irq_set_state(dev, RADEON_SW_INT_ENABLE, 1);
400 void radeon_driver_irq_uninstall(struct drm_device * dev)
402 drm_radeon_private_t *dev_priv =
403 (drm_radeon_private_t *) dev->dev_private;
407 dev_priv->irq_enabled = 0;
409 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
412 if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
413 RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
414 /* Disable *all* interrupts */
415 RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
419 int radeon_vblank_crtc_get(struct drm_device *dev)
421 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
423 return dev_priv->vblank_crtc;
426 int radeon_vblank_crtc_set(struct drm_device *dev, int64_t value)
428 drm_radeon_private_t *dev_priv = (drm_radeon_private_t *) dev->dev_private;
429 if (value & ~(DRM_RADEON_VBLANK_CRTC1 | DRM_RADEON_VBLANK_CRTC2)) {
430 DRM_ERROR("called with invalid crtc 0x%x\n", (unsigned int)value);
433 dev_priv->vblank_crtc = (unsigned int)value;