2 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
18 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
20 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
22 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
23 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
33 /* Please note that modifications to all structs defined here are
34 * subject to backwards-compatibility constraints.
37 #include <dev/drm2/drm.h>
39 /* Each region is a minimum of 16k, and there are at most 255 of them.
41 #define I915_NR_TEX_REGIONS 255 /* table size 2k - maximum due to use
42 * of chars for next/prev indices */
43 #define I915_LOG_MIN_TEX_REGION_SIZE 14
45 typedef struct _drm_i915_init {
48 I915_CLEANUP_DMA = 0x02,
49 I915_RESUME_DMA = 0x03,
51 /* Since this struct isn't versioned, just used a new
52 * 'func' code to indicate the presence of dri2 sarea
56 unsigned int mmio_offset;
57 int sarea_priv_offset;
58 unsigned int ring_start;
59 unsigned int ring_end;
60 unsigned int ring_size;
61 unsigned int front_offset;
62 unsigned int back_offset;
63 unsigned int depth_offset;
67 unsigned int pitch_bits;
68 unsigned int back_pitch;
69 unsigned int depth_pitch;
72 unsigned int sarea_handle;
75 typedef struct drm_i915_sarea {
76 struct drm_tex_region texList[I915_NR_TEX_REGIONS + 1];
77 int last_upload; /* last time texture was uploaded */
78 int last_enqueue; /* last time a buffer was enqueued */
79 int last_dispatch; /* age of the most recently dispatched buffer */
80 int ctxOwner; /* last context to upload state */
82 int pf_enabled; /* is pageflipping allowed? */
84 int pf_current_page; /* which buffer is being displayed? */
85 int perf_boxes; /* performance boxes to be displayed */
86 int width, height; /* screen size in pixels */
88 drm_handle_t front_handle;
92 drm_handle_t back_handle;
96 drm_handle_t depth_handle;
100 drm_handle_t tex_handle;
103 int log_tex_granularity;
105 int rotation; /* 0, 90, 180 or 270 */
109 int virtualX, virtualY;
111 unsigned int front_tiled;
112 unsigned int back_tiled;
113 unsigned int depth_tiled;
114 unsigned int rotated_tiled;
115 unsigned int rotated2_tiled;
126 /* Triple buffering */
127 drm_handle_t third_handle;
130 unsigned int third_tiled;
132 /* buffer object handles for the static buffers. May change
133 * over the lifetime of the client, though it doesn't in our current
136 unsigned int front_bo_handle;
137 unsigned int back_bo_handle;
138 unsigned int third_bo_handle;
139 unsigned int depth_bo_handle;
142 /* Driver specific fence types and classes.
145 /* The only fence class we support */
146 #define DRM_I915_FENCE_CLASS_ACCEL 0
147 /* Fence type that guarantees read-write flush */
148 #define DRM_I915_FENCE_TYPE_RW 2
149 /* MI_FLUSH programmed just before the fence */
150 #define DRM_I915_FENCE_FLAG_FLUSHED 0x01000000
152 /* Flags for perf_boxes
154 #define I915_BOX_RING_EMPTY 0x1
155 #define I915_BOX_FLIP 0x2
156 #define I915_BOX_WAIT 0x4
157 #define I915_BOX_TEXTURE_LOAD 0x8
158 #define I915_BOX_LOST_CONTEXT 0x10
160 /* I915 specific ioctls
161 * The device specific ioctl range is 0x40 to 0x79.
163 #define DRM_I915_INIT 0x00
164 #define DRM_I915_FLUSH 0x01
165 #define DRM_I915_FLIP 0x02
166 #define DRM_I915_BATCHBUFFER 0x03
167 #define DRM_I915_IRQ_EMIT 0x04
168 #define DRM_I915_IRQ_WAIT 0x05
169 #define DRM_I915_GETPARAM 0x06
170 #define DRM_I915_SETPARAM 0x07
171 #define DRM_I915_ALLOC 0x08
172 #define DRM_I915_FREE 0x09
173 #define DRM_I915_INIT_HEAP 0x0a
174 #define DRM_I915_CMDBUFFER 0x0b
175 #define DRM_I915_DESTROY_HEAP 0x0c
176 #define DRM_I915_SET_VBLANK_PIPE 0x0d
177 #define DRM_I915_GET_VBLANK_PIPE 0x0e
178 #define DRM_I915_VBLANK_SWAP 0x0f
179 #define DRM_I915_MMIO 0x10
180 #define DRM_I915_HWS_ADDR 0x11
181 #define DRM_I915_EXECBUFFER 0x12
182 #define DRM_I915_GEM_INIT 0x13
183 #define DRM_I915_GEM_EXECBUFFER 0x14
184 #define DRM_I915_GEM_PIN 0x15
185 #define DRM_I915_GEM_UNPIN 0x16
186 #define DRM_I915_GEM_BUSY 0x17
187 #define DRM_I915_GEM_THROTTLE 0x18
188 #define DRM_I915_GEM_ENTERVT 0x19
189 #define DRM_I915_GEM_LEAVEVT 0x1a
190 #define DRM_I915_GEM_CREATE 0x1b
191 #define DRM_I915_GEM_PREAD 0x1c
192 #define DRM_I915_GEM_PWRITE 0x1d
193 #define DRM_I915_GEM_MMAP 0x1e
194 #define DRM_I915_GEM_SET_DOMAIN 0x1f
195 #define DRM_I915_GEM_SW_FINISH 0x20
196 #define DRM_I915_GEM_SET_TILING 0x21
197 #define DRM_I915_GEM_GET_TILING 0x22
198 #define DRM_I915_GEM_GET_APERTURE 0x23
199 #define DRM_I915_GEM_MMAP_GTT 0x24
200 #define DRM_I915_GET_PIPE_FROM_CRTC_ID 0x25
201 #define DRM_I915_GEM_MADVISE 0x26
202 #define DRM_I915_OVERLAY_PUT_IMAGE 0x27
203 #define DRM_I915_OVERLAY_ATTRS 0x28
204 #define DRM_I915_GEM_EXECBUFFER2 0x29
205 #define DRM_I915_GET_SPRITE_COLORKEY 0x2a
206 #define DRM_I915_SET_SPRITE_COLORKEY 0x2b
208 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
209 #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
210 #define DRM_IOCTL_I915_FLIP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FLIP, drm_i915_flip_t)
211 #define DRM_IOCTL_I915_BATCHBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_BATCHBUFFER, drm_i915_batchbuffer_t)
212 #define DRM_IOCTL_I915_IRQ_EMIT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_IRQ_EMIT, drm_i915_irq_emit_t)
213 #define DRM_IOCTL_I915_IRQ_WAIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_IRQ_WAIT, drm_i915_irq_wait_t)
214 #define DRM_IOCTL_I915_GETPARAM DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GETPARAM, drm_i915_getparam_t)
215 #define DRM_IOCTL_I915_SETPARAM DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SETPARAM, drm_i915_setparam_t)
216 #define DRM_IOCTL_I915_ALLOC DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_ALLOC, drm_i915_mem_alloc_t)
217 #define DRM_IOCTL_I915_FREE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_FREE, drm_i915_mem_free_t)
218 #define DRM_IOCTL_I915_INIT_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT_HEAP, drm_i915_mem_init_heap_t)
219 #define DRM_IOCTL_I915_CMDBUFFER DRM_IOW( DRM_COMMAND_BASE + DRM_I915_CMDBUFFER, drm_i915_cmdbuffer_t)
220 #define DRM_IOCTL_I915_DESTROY_HEAP DRM_IOW( DRM_COMMAND_BASE + DRM_I915_DESTROY_HEAP, drm_i915_mem_destroy_heap_t)
221 #define DRM_IOCTL_I915_SET_VBLANK_PIPE DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
222 #define DRM_IOCTL_I915_GET_VBLANK_PIPE DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
223 #define DRM_IOCTL_I915_VBLANK_SWAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
224 #define DRM_IOCTL_I915_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_MMIO, drm_i915_mmio)
225 #define DRM_IOCTL_I915_EXECBUFFER DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_EXECBUFFER, struct drm_i915_execbuffer)
226 #define DRM_IOCTL_I915_GEM_INIT DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_INIT, struct drm_i915_gem_init)
227 #define DRM_IOCTL_I915_GEM_EXECBUFFER DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER, struct drm_i915_gem_execbuffer)
228 #define DRM_IOCTL_I915_GEM_EXECBUFFER2 DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_EXECBUFFER2, struct drm_i915_gem_execbuffer2)
229 #define DRM_IOCTL_I915_GEM_PIN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
230 #define DRM_IOCTL_I915_GEM_UNPIN DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
231 #define DRM_IOCTL_I915_GEM_BUSY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
232 #define DRM_IOCTL_I915_GEM_THROTTLE DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
233 #define DRM_IOCTL_I915_GEM_ENTERVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
234 #define DRM_IOCTL_I915_GEM_LEAVEVT DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
235 #define DRM_IOCTL_I915_GEM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
236 #define DRM_IOCTL_I915_GEM_PREAD DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
237 #define DRM_IOCTL_I915_GEM_PWRITE DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
238 #define DRM_IOCTL_I915_GEM_MMAP DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
239 #define DRM_IOCTL_I915_GEM_MMAP_GTT DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP_GTT, struct drm_i915_gem_mmap_gtt)
240 #define DRM_IOCTL_I915_GEM_SET_DOMAIN DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
241 #define DRM_IOCTL_I915_GEM_SW_FINISH DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
242 #define DRM_IOCTL_I915_GEM_SET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
243 #define DRM_IOCTL_I915_GEM_GET_TILING DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
244 #define DRM_IOCTL_I915_GEM_GET_APERTURE DRM_IOR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_APERTURE, struct drm_i915_gem_get_aperture)
245 #define DRM_IOCTL_I915_GET_PIPE_FROM_CRTC_ID DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GET_PIPE_FROM_CRTC_ID, struct drm_i915_get_pipe_from_crtc_id)
246 #define DRM_IOCTL_I915_GEM_MADVISE DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MADVISE, struct drm_i915_gem_madvise)
247 #define DRM_IOCTL_I915_OVERLAY_PUT_IMAGE DRM_IOW(DRM_COMMAND_BASE + DRM_IOCTL_I915_OVERLAY_PUT_IMAGE, struct drm_intel_overlay_put_image)
248 #define DRM_IOCTL_I915_OVERLAY_ATTRS DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_OVERLAY_ATTRS, struct drm_intel_overlay_attrs)
249 #define DRM_IOCTL_I915_SET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
250 #define DRM_IOCTL_I915_GET_SPRITE_COLORKEY DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_SET_SPRITE_COLORKEY, struct drm_intel_sprite_colorkey)
252 /* Asynchronous page flipping:
254 typedef struct drm_i915_flip {
256 * This is really talking about planes, and we could rename it
257 * except for the fact that some of the duplicated i915_drm.h files
258 * out there check for HAVE_I915_FLIP and so might pick up this
264 /* Allow drivers to submit batchbuffers directly to hardware, relying
265 * on the security mechanisms provided by hardware.
267 typedef struct drm_i915_batchbuffer {
268 int start; /* agp offset */
269 int used; /* nr bytes in use */
270 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
271 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
272 int num_cliprects; /* mulitpass with multiple cliprects? */
273 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
274 } drm_i915_batchbuffer_t;
276 /* As above, but pass a pointer to userspace buffer which can be
277 * validated by the kernel prior to sending to hardware.
279 typedef struct _drm_i915_cmdbuffer {
280 char __user *buf; /* pointer to userspace command buffer */
281 int sz; /* nr bytes in buf */
282 int DR1; /* hw flags for GFX_OP_DRAWRECT_INFO */
283 int DR4; /* window origin for GFX_OP_DRAWRECT_INFO */
284 int num_cliprects; /* mulitpass with multiple cliprects? */
285 struct drm_clip_rect __user *cliprects; /* pointer to userspace cliprects */
286 } drm_i915_cmdbuffer_t;
288 /* Userspace can request & wait on irq's:
290 typedef struct drm_i915_irq_emit {
292 } drm_i915_irq_emit_t;
294 typedef struct drm_i915_irq_wait {
296 } drm_i915_irq_wait_t;
298 /* Ioctl to query kernel params:
300 #define I915_PARAM_IRQ_ACTIVE 1
301 #define I915_PARAM_ALLOW_BATCHBUFFER 2
302 #define I915_PARAM_LAST_DISPATCH 3
303 #define I915_PARAM_CHIPSET_ID 4
304 #define I915_PARAM_HAS_GEM 5
305 #define I915_PARAM_NUM_FENCES_AVAIL 6
306 #define I915_PARAM_HAS_OVERLAY 7
307 #define I915_PARAM_HAS_PAGEFLIPPING 8
308 #define I915_PARAM_HAS_EXECBUF2 9
309 #define I915_PARAM_HAS_BSD 10
310 #define I915_PARAM_HAS_BLT 11
311 #define I915_PARAM_HAS_RELAXED_FENCING 12
312 #define I915_PARAM_HAS_COHERENT_RINGS 13
313 #define I915_PARAM_HAS_EXEC_CONSTANTS 14
314 #define I915_PARAM_HAS_RELAXED_DELTA 15
315 #define I915_PARAM_HAS_GEN7_SOL_RESET 16
316 #define I915_PARAM_HAS_LLC 17
318 typedef struct drm_i915_getparam {
321 } drm_i915_getparam_t;
323 /* Ioctl to set kernel params:
325 #define I915_SETPARAM_USE_MI_BATCHBUFFER_START 1
326 #define I915_SETPARAM_TEX_LRU_LOG_GRANULARITY 2
327 #define I915_SETPARAM_ALLOW_BATCHBUFFER 3
328 #define I915_SETPARAM_NUM_USED_FENCES 4
330 typedef struct drm_i915_setparam {
333 } drm_i915_setparam_t;
335 /* A memory manager for regions of shared memory:
337 #define I915_MEM_REGION_AGP 1
339 typedef struct drm_i915_mem_alloc {
343 int __user *region_offset; /* offset from start of fb or agp */
344 } drm_i915_mem_alloc_t;
346 typedef struct drm_i915_mem_free {
349 } drm_i915_mem_free_t;
351 typedef struct drm_i915_mem_init_heap {
355 } drm_i915_mem_init_heap_t;
357 /* Allow memory manager to be torn down and re-initialized (eg on
360 typedef struct drm_i915_mem_destroy_heap {
362 } drm_i915_mem_destroy_heap_t;
364 /* Allow X server to configure which pipes to monitor for vblank signals
366 #define DRM_I915_VBLANK_PIPE_A 1
367 #define DRM_I915_VBLANK_PIPE_B 2
369 typedef struct drm_i915_vblank_pipe {
371 } drm_i915_vblank_pipe_t;
373 /* Schedule buffer swap at given vertical blank:
375 typedef struct drm_i915_vblank_swap {
376 drm_drawable_t drawable;
377 enum drm_vblank_seq_type seqtype;
378 unsigned int sequence;
379 } drm_i915_vblank_swap_t;
381 #define I915_MMIO_READ 0
382 #define I915_MMIO_WRITE 1
384 #define I915_MMIO_MAY_READ 0x1
385 #define I915_MMIO_MAY_WRITE 0x2
387 #define MMIO_REGS_IA_PRIMATIVES_COUNT 0
388 #define MMIO_REGS_IA_VERTICES_COUNT 1
389 #define MMIO_REGS_VS_INVOCATION_COUNT 2
390 #define MMIO_REGS_GS_PRIMITIVES_COUNT 3
391 #define MMIO_REGS_GS_INVOCATION_COUNT 4
392 #define MMIO_REGS_CL_PRIMITIVES_COUNT 5
393 #define MMIO_REGS_CL_INVOCATION_COUNT 6
394 #define MMIO_REGS_PS_INVOCATION_COUNT 7
395 #define MMIO_REGS_PS_DEPTH_COUNT 8
397 typedef struct drm_i915_mmio_entry {
401 } drm_i915_mmio_entry_t;
403 typedef struct drm_i915_mmio {
404 unsigned int read_write:1;
409 typedef struct drm_i915_hws_addr {
411 } drm_i915_hws_addr_t;
414 * Relocation header is 4 uint32_ts
415 * 0 - 32 bit reloc count
416 * 1 - 32-bit relocation type
417 * 2-3 - 64-bit user buffer handle ptr for another list of relocs.
419 #define I915_RELOC_HEADER 4
422 * type 0 relocation has 4-uint32_t stride
423 * 0 - offset into buffer
424 * 1 - delta to add in
426 * 3 - reserved (for optimisations later).
429 * type 1 relocation has 4-uint32_t stride.
430 * Hangs off the first item in the op list.
431 * Performed after all valiations are done.
432 * Try to group relocs into the same relocatee together for
433 * performance reasons.
434 * 0 - offset into buffer
435 * 1 - delta to add in
436 * 2 - buffer index in op list.
437 * 3 - relocatee index in op list.
439 #define I915_RELOC_TYPE_0 0
440 #define I915_RELOC0_STRIDE 4
441 #define I915_RELOC_TYPE_1 1
442 #define I915_RELOC1_STRIDE 4
445 struct drm_i915_op_arg {
451 struct drm_bo_op_req req;
452 struct drm_bo_arg_rep rep;
457 struct drm_i915_execbuffer {
459 uint32_t num_buffers;
460 struct drm_i915_batchbuffer batch;
461 drm_context_t context; /* for lockless use in the future */
462 struct drm_fence_arg fence_arg;
465 struct drm_i915_gem_init {
467 * Beginning offset in the GTT to be managed by the DRM memory
472 * Ending offset in the GTT to be managed by the DRM memory
478 struct drm_i915_gem_create {
480 * Requested size for the object.
482 * The (page-aligned) allocated size for the object will be returned.
486 * Returned handle for the object.
488 * Object handles are nonzero.
494 struct drm_i915_gem_pread {
495 /** Handle for the object being read. */
498 /** Offset into the object to read from */
500 /** Length of data to read */
502 /** Pointer to write the data into. */
503 uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
506 struct drm_i915_gem_pwrite {
507 /** Handle for the object being written to. */
510 /** Offset into the object to write to */
512 /** Length of data to write */
514 /** Pointer to read the data from. */
515 uint64_t data_ptr; /* void *, but pointers are not 32/64 compatible */
518 struct drm_i915_gem_mmap {
519 /** Handle for the object being mapped. */
522 /** Offset in the object to map. */
525 * Length of data to map.
527 * The value will be page-aligned.
530 /** Returned pointer the data was mapped at */
531 uint64_t addr_ptr; /* void *, but pointers are not 32/64 compatible */
534 struct drm_i915_gem_mmap_gtt {
535 /** Handle for the object being mapped. */
539 * Fake offset to use for subsequent mmap call
541 * This is a fixed-size type for 32/64 compatibility.
546 struct drm_i915_gem_set_domain {
547 /** Handle for the object */
550 /** New read domains */
551 uint32_t read_domains;
553 /** New write domain */
554 uint32_t write_domain;
557 struct drm_i915_gem_sw_finish {
558 /** Handle for the object */
562 struct drm_i915_gem_relocation_entry {
564 * Handle of the buffer being pointed to by this relocation entry.
566 * It's appealing to make this be an index into the mm_validate_entry
567 * list to refer to the buffer, but this allows the driver to create
568 * a relocation list for state buffers and not re-write it per
569 * exec using the buffer.
571 uint32_t target_handle;
574 * Value to be added to the offset of the target buffer to make up
575 * the relocation entry.
579 /** Offset in the buffer the relocation entry will be written into */
583 * Offset value of the target buffer that the relocation entry was last
586 * If the buffer has the same offset as last time, we can skip syncing
587 * and writing the relocation. This value is written back out by
588 * the execbuffer ioctl when the relocation is written.
590 uint64_t presumed_offset;
593 * Target memory domains read by this operation.
595 uint32_t read_domains;
598 * Target memory domains written by this operation.
600 * Note that only one domain may be written by the whole
601 * execbuffer operation, so that where there are conflicts,
602 * the application will get -EINVAL back.
604 uint32_t write_domain;
608 * Intel memory domains
610 * Most of these just align with the various caches in
611 * the system and are used to flush and invalidate as
612 * objects end up cached in different domains.
615 #define I915_GEM_DOMAIN_CPU 0x00000001
616 /** Render cache, used by 2D and 3D drawing */
617 #define I915_GEM_DOMAIN_RENDER 0x00000002
618 /** Sampler cache, used by texture engine */
619 #define I915_GEM_DOMAIN_SAMPLER 0x00000004
620 /** Command queue, used to load batch buffers */
621 #define I915_GEM_DOMAIN_COMMAND 0x00000008
622 /** Instruction cache, used by shader programs */
623 #define I915_GEM_DOMAIN_INSTRUCTION 0x00000010
624 /** Vertex address cache */
625 #define I915_GEM_DOMAIN_VERTEX 0x00000020
626 /** GTT domain - aperture and scanout */
627 #define I915_GEM_DOMAIN_GTT 0x00000040
630 struct drm_i915_gem_exec_object {
632 * User's handle for a buffer to be bound into the GTT for this
637 /** Number of relocations to be performed on this buffer */
638 uint32_t relocation_count;
640 * Pointer to array of struct drm_i915_gem_relocation_entry containing
641 * the relocations to be performed in this buffer.
645 /** Required alignment in graphics aperture */
649 * Returned value of the updated offset of the object, for future
650 * presumed_offset writes.
655 struct drm_i915_gem_execbuffer {
657 * List of buffers to be validated with their relocations to be
658 * performend on them.
660 * This is a pointer to an array of struct drm_i915_gem_validate_entry.
662 * These buffers must be listed in an order such that all relocations
663 * a buffer is performing refer to buffers that have already appeared
664 * in the validate list.
666 uint64_t buffers_ptr;
667 uint32_t buffer_count;
669 /** Offset in the batchbuffer to start execution from. */
670 uint32_t batch_start_offset;
671 /** Bytes used in batchbuffer from batch_start_offset */
675 uint32_t num_cliprects;
676 uint64_t cliprects_ptr; /* struct drm_clip_rect *cliprects */
679 struct drm_i915_gem_exec_object2 {
681 * User's handle for a buffer to be bound into the GTT for this
686 /** Number of relocations to be performed on this buffer */
687 uint32_t relocation_count;
689 * Pointer to array of struct drm_i915_gem_relocation_entry containing
690 * the relocations to be performed in this buffer.
694 /** Required alignment in graphics aperture */
698 * Returned value of the updated offset of the object, for future
699 * presumed_offset writes.
703 #define EXEC_OBJECT_NEEDS_FENCE (1<<0)
709 struct drm_i915_gem_execbuffer2 {
711 * List of gem_exec_object2 structs
713 uint64_t buffers_ptr;
714 uint32_t buffer_count;
716 /** Offset in the batchbuffer to start execution from. */
717 uint32_t batch_start_offset;
718 /** Bytes used in batchbuffer from batch_start_offset */
722 uint32_t num_cliprects;
723 /** This is a struct drm_clip_rect *cliprects */
724 uint64_t cliprects_ptr;
725 #define I915_EXEC_RING_MASK (7<<0)
726 #define I915_EXEC_DEFAULT (0<<0)
727 #define I915_EXEC_RENDER (1<<0)
728 #define I915_EXEC_BSD (2<<0)
729 #define I915_EXEC_BLT (3<<0)
731 /* Used for switching the constants addressing mode on gen4+ RENDER ring.
732 * Gen6+ only supports relative addressing to dynamic state (default) and
733 * absolute addressing.
735 * These flags are ignored for the BSD and BLT rings.
737 #define I915_EXEC_CONSTANTS_MASK (3<<6)
738 #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */
739 #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6)
740 #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */
746 /** Resets the SO write offset registers for transform feedback on gen7. */
747 #define I915_EXEC_GEN7_SOL_RESET (1<<8)
749 struct drm_i915_gem_pin {
750 /** Handle of the buffer to be pinned. */
754 /** alignment required within the aperture */
757 /** Returned GTT offset of the buffer. */
761 struct drm_i915_gem_unpin {
762 /** Handle of the buffer to be unpinned. */
767 struct drm_i915_gem_busy {
768 /** Handle of the buffer to check for busy */
771 /** Return busy status (1 if busy, 0 if idle) */
775 #define I915_TILING_NONE 0
776 #define I915_TILING_X 1
777 #define I915_TILING_Y 2
779 #define I915_BIT_6_SWIZZLE_NONE 0
780 #define I915_BIT_6_SWIZZLE_9 1
781 #define I915_BIT_6_SWIZZLE_9_10 2
782 #define I915_BIT_6_SWIZZLE_9_11 3
783 #define I915_BIT_6_SWIZZLE_9_10_11 4
784 /* Not seen by userland */
785 #define I915_BIT_6_SWIZZLE_UNKNOWN 5
786 /* Seen by userland. */
787 #define I915_BIT_6_SWIZZLE_9_17 6
788 #define I915_BIT_6_SWIZZLE_9_10_17 7
790 struct drm_i915_gem_set_tiling {
791 /** Handle of the buffer to have its tiling state updated */
795 * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
798 * This value is to be set on request, and will be updated by the
799 * kernel on successful return with the actual chosen tiling layout.
801 * The tiling mode may be demoted to I915_TILING_NONE when the system
802 * has bit 6 swizzling that can't be managed correctly by GEM.
804 * Buffer contents become undefined when changing tiling_mode.
806 uint32_t tiling_mode;
809 * Stride in bytes for the object when in I915_TILING_X or
815 * Returned address bit 6 swizzling required for CPU access through
818 uint32_t swizzle_mode;
821 struct drm_i915_gem_get_tiling {
822 /** Handle of the buffer to get tiling state for. */
826 * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
829 uint32_t tiling_mode;
832 * Returned address bit 6 swizzling required for CPU access through
835 uint32_t swizzle_mode;
838 struct drm_i915_gem_get_aperture {
839 /** Total size of the aperture used by i915_gem_execbuffer, in bytes */
843 * Available space in the aperture used by i915_gem_execbuffer, in
846 uint64_t aper_available_size;
849 struct drm_i915_get_pipe_from_crtc_id {
850 /** ID of CRTC being requested **/
853 /** pipe of requested CRTC **/
857 #define I915_MADV_WILLNEED 0
858 #define I915_MADV_DONTNEED 1
859 #define I915_MADV_PURGED_INTERNAL 2 /* internal state */
861 struct drm_i915_gem_madvise {
862 /** Handle of the buffer to change the backing store advice */
865 /* Advice: either the buffer will be needed again in the near future,
866 * or wont be and could be discarded under memory pressure.
870 /** Whether the backing store still exists. */
874 #define I915_OVERLAY_TYPE_MASK 0xff
875 #define I915_OVERLAY_YUV_PLANAR 0x01
876 #define I915_OVERLAY_YUV_PACKED 0x02
877 #define I915_OVERLAY_RGB 0x03
879 #define I915_OVERLAY_DEPTH_MASK 0xff00
880 #define I915_OVERLAY_RGB24 0x1000
881 #define I915_OVERLAY_RGB16 0x2000
882 #define I915_OVERLAY_RGB15 0x3000
883 #define I915_OVERLAY_YUV422 0x0100
884 #define I915_OVERLAY_YUV411 0x0200
885 #define I915_OVERLAY_YUV420 0x0300
886 #define I915_OVERLAY_YUV410 0x0400
888 #define I915_OVERLAY_SWAP_MASK 0xff0000
889 #define I915_OVERLAY_NO_SWAP 0x000000
890 #define I915_OVERLAY_UV_SWAP 0x010000
891 #define I915_OVERLAY_Y_SWAP 0x020000
892 #define I915_OVERLAY_Y_AND_UV_SWAP 0x030000
894 #define I915_OVERLAY_FLAGS_MASK 0xff000000
895 #define I915_OVERLAY_ENABLE 0x01000000
897 struct drm_intel_overlay_put_image {
898 /* various flags and src format description */
900 /* source picture description */
902 /* stride values and offsets are in bytes, buffer relative */
903 uint16_t stride_Y; /* stride for packed formats */
905 uint32_t offset_Y; /* offset for packet formats */
911 /* to compensate the scaling factors for partially covered surfaces */
912 uint16_t src_scan_width;
913 uint16_t src_scan_height;
914 /* output crtc description */
923 #define I915_OVERLAY_UPDATE_ATTRS (1<<0)
924 #define I915_OVERLAY_UPDATE_GAMMA (1<<1)
925 struct drm_intel_overlay_attrs {
940 * Intel sprite handling
942 * Color keying works with a min/mask/max tuple. Both source and destination
943 * color keying is allowed.
946 * Sprite pixels within the min & max values, masked against the color channels
947 * specified in the mask field, will be transparent. All other pixels will
948 * be displayed on top of the primary plane. For RGB surfaces, only the min
949 * and mask fields will be used; ranged compares are not allowed.
951 * Destination keying:
952 * Primary plane pixels that match the min value, masked against the color
953 * channels specified in the mask field, will be replaced by corresponding
954 * pixels from the sprite plane.
956 * Note that source & destination keying are exclusive; only one can be
957 * active on a given plane.
960 #define I915_SET_COLORKEY_NONE (1<<0) /* disable color key matching */
961 #define I915_SET_COLORKEY_DESTINATION (1<<1)
962 #define I915_SET_COLORKEY_SOURCE (1<<2)
963 struct drm_intel_sprite_colorkey {
966 uint32_t channel_mask;
971 #endif /* _I915_DRM_H_ */