1 /* i915_drv.c -- Intel i915 driver -*- linux-c -*-
2 * Created: Wed Feb 14 17:10:04 2001 by gareth@valinux.com
5 * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
23 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
24 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
25 * OTHER DEALINGS IN THE SOFTWARE.
28 * Gareth Hughes <gareth@valinux.com>
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
35 #include <dev/drm2/drmP.h>
36 #include <dev/drm2/drm.h>
37 #include <dev/drm2/drm_mm.h>
38 #include <dev/drm2/i915/i915_drm.h>
39 #include <dev/drm2/i915/i915_drv.h>
40 #include <dev/drm2/drm_pciids.h>
41 #include <dev/drm2/i915/intel_drv.h>
43 /* drv_PCI_IDs comes from drm_pciids.h, generated from drm_pciids.txt. */
44 static drm_pci_id_list_t i915_pciidlist[] = {
48 static const struct intel_device_info intel_i830_info = {
49 .gen = 2, .is_mobile = 1, .cursor_needs_physical = 1,
50 .has_overlay = 1, .overlay_needs_physical = 1,
53 static const struct intel_device_info intel_845g_info = {
55 .has_overlay = 1, .overlay_needs_physical = 1,
58 static const struct intel_device_info intel_i85x_info = {
59 .gen = 2, .is_i85x = 1, .is_mobile = 1,
60 .cursor_needs_physical = 1,
61 .has_overlay = 1, .overlay_needs_physical = 1,
64 static const struct intel_device_info intel_i865g_info = {
66 .has_overlay = 1, .overlay_needs_physical = 1,
69 static const struct intel_device_info intel_i915g_info = {
70 .gen = 3, .is_i915g = 1, .cursor_needs_physical = 1,
71 .has_overlay = 1, .overlay_needs_physical = 1,
73 static const struct intel_device_info intel_i915gm_info = {
74 .gen = 3, .is_mobile = 1,
75 .cursor_needs_physical = 1,
76 .has_overlay = 1, .overlay_needs_physical = 1,
79 static const struct intel_device_info intel_i945g_info = {
80 .gen = 3, .has_hotplug = 1, .cursor_needs_physical = 1,
81 .has_overlay = 1, .overlay_needs_physical = 1,
83 static const struct intel_device_info intel_i945gm_info = {
84 .gen = 3, .is_i945gm = 1, .is_mobile = 1,
85 .has_hotplug = 1, .cursor_needs_physical = 1,
86 .has_overlay = 1, .overlay_needs_physical = 1,
90 static const struct intel_device_info intel_i965g_info = {
91 .gen = 4, .is_broadwater = 1,
96 static const struct intel_device_info intel_i965gm_info = {
97 .gen = 4, .is_crestline = 1,
98 .is_mobile = 1, .has_fbc = 1, .has_hotplug = 1,
103 static const struct intel_device_info intel_g33_info = {
104 .gen = 3, .is_g33 = 1,
105 .need_gfx_hws = 1, .has_hotplug = 1,
109 static const struct intel_device_info intel_g45_info = {
110 .gen = 4, .is_g4x = 1, .need_gfx_hws = 1,
111 .has_pipe_cxsr = 1, .has_hotplug = 1,
115 static const struct intel_device_info intel_gm45_info = {
116 .gen = 4, .is_g4x = 1,
117 .is_mobile = 1, .need_gfx_hws = 1, .has_fbc = 1,
118 .has_pipe_cxsr = 1, .has_hotplug = 1,
123 static const struct intel_device_info intel_pineview_info = {
124 .gen = 3, .is_g33 = 1, .is_pineview = 1, .is_mobile = 1,
125 .need_gfx_hws = 1, .has_hotplug = 1,
129 static const struct intel_device_info intel_ironlake_d_info = {
131 .need_gfx_hws = 1, .has_hotplug = 1,
135 static const struct intel_device_info intel_ironlake_m_info = {
136 .gen = 5, .is_mobile = 1,
137 .need_gfx_hws = 1, .has_hotplug = 1,
138 .has_fbc = 0, /* disabled due to buggy hardware */
142 static const struct intel_device_info intel_sandybridge_d_info = {
144 .need_gfx_hws = 1, .has_hotplug = 1,
150 static const struct intel_device_info intel_sandybridge_m_info = {
151 .gen = 6, .is_mobile = 1,
152 .need_gfx_hws = 1, .has_hotplug = 1,
159 static const struct intel_device_info intel_ivybridge_d_info = {
160 .is_ivybridge = 1, .gen = 7,
161 .need_gfx_hws = 1, .has_hotplug = 1,
167 static const struct intel_device_info intel_ivybridge_m_info = {
168 .is_ivybridge = 1, .gen = 7, .is_mobile = 1,
169 .need_gfx_hws = 1, .has_hotplug = 1,
170 .has_fbc = 0, /* FBC is not enabled on Ivybridge mobile yet */
176 #define INTEL_VGA_DEVICE(id, info_) { \
181 static const struct intel_gfx_device_id {
183 const struct intel_device_info *info;
184 } pciidlist[] = { /* aka */
185 INTEL_VGA_DEVICE(0x3577, &intel_i830_info),
186 INTEL_VGA_DEVICE(0x2562, &intel_845g_info),
187 INTEL_VGA_DEVICE(0x3582, &intel_i85x_info),
188 INTEL_VGA_DEVICE(0x358e, &intel_i85x_info),
189 INTEL_VGA_DEVICE(0x2572, &intel_i865g_info),
190 INTEL_VGA_DEVICE(0x2582, &intel_i915g_info),
191 INTEL_VGA_DEVICE(0x258a, &intel_i915g_info),
192 INTEL_VGA_DEVICE(0x2592, &intel_i915gm_info),
193 INTEL_VGA_DEVICE(0x2772, &intel_i945g_info),
194 INTEL_VGA_DEVICE(0x27a2, &intel_i945gm_info),
195 INTEL_VGA_DEVICE(0x27ae, &intel_i945gm_info),
196 INTEL_VGA_DEVICE(0x2972, &intel_i965g_info),
197 INTEL_VGA_DEVICE(0x2982, &intel_i965g_info),
198 INTEL_VGA_DEVICE(0x2992, &intel_i965g_info),
199 INTEL_VGA_DEVICE(0x29a2, &intel_i965g_info),
200 INTEL_VGA_DEVICE(0x29b2, &intel_g33_info),
201 INTEL_VGA_DEVICE(0x29c2, &intel_g33_info),
202 INTEL_VGA_DEVICE(0x29d2, &intel_g33_info),
203 INTEL_VGA_DEVICE(0x2a02, &intel_i965gm_info),
204 INTEL_VGA_DEVICE(0x2a12, &intel_i965gm_info),
205 INTEL_VGA_DEVICE(0x2a42, &intel_gm45_info),
206 INTEL_VGA_DEVICE(0x2e02, &intel_g45_info),
207 INTEL_VGA_DEVICE(0x2e12, &intel_g45_info),
208 INTEL_VGA_DEVICE(0x2e22, &intel_g45_info),
209 INTEL_VGA_DEVICE(0x2e32, &intel_g45_info),
210 INTEL_VGA_DEVICE(0x2e42, &intel_g45_info),
211 INTEL_VGA_DEVICE(0x2e92, &intel_g45_info),
212 INTEL_VGA_DEVICE(0xa001, &intel_pineview_info),
213 INTEL_VGA_DEVICE(0xa011, &intel_pineview_info),
214 INTEL_VGA_DEVICE(0x0042, &intel_ironlake_d_info),
215 INTEL_VGA_DEVICE(0x0046, &intel_ironlake_m_info),
216 INTEL_VGA_DEVICE(0x0102, &intel_sandybridge_d_info),
217 INTEL_VGA_DEVICE(0x0112, &intel_sandybridge_d_info),
218 INTEL_VGA_DEVICE(0x0122, &intel_sandybridge_d_info),
219 INTEL_VGA_DEVICE(0x0106, &intel_sandybridge_m_info),
220 INTEL_VGA_DEVICE(0x0116, &intel_sandybridge_m_info),
221 INTEL_VGA_DEVICE(0x0126, &intel_sandybridge_m_info),
222 INTEL_VGA_DEVICE(0x010A, &intel_sandybridge_d_info),
223 INTEL_VGA_DEVICE(0x0156, &intel_ivybridge_m_info), /* GT1 mobile */
224 INTEL_VGA_DEVICE(0x0166, &intel_ivybridge_m_info), /* GT2 mobile */
225 INTEL_VGA_DEVICE(0x0152, &intel_ivybridge_d_info), /* GT1 desktop */
226 INTEL_VGA_DEVICE(0x0162, &intel_ivybridge_d_info), /* GT2 desktop */
227 INTEL_VGA_DEVICE(0x015a, &intel_ivybridge_d_info), /* GT1 server */
228 INTEL_VGA_DEVICE(0x016a, &intel_ivybridge_d_info), /* GT2 server */
232 static int i915_drm_freeze(struct drm_device *dev)
234 struct drm_i915_private *dev_priv;
237 dev_priv = dev->dev_private;
238 drm_kms_helper_poll_disable(dev);
241 pci_save_state(dev->pdev);
245 /* If KMS is active, we do the leavevt stuff here */
246 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
247 error = -i915_gem_idle(dev);
250 device_printf(dev->device,
251 "GEM idle failed, resume might fail\n");
254 drm_irq_uninstall(dev);
257 i915_save_state(dev);
259 intel_opregion_fini(dev);
261 /* Modeset on resume, not lid events */
262 dev_priv->modeset_on_lid = 0;
269 i915_suspend(device_t kdev)
271 struct drm_device *dev;
274 dev = device_get_softc(kdev);
275 if (dev == NULL || dev->dev_private == NULL) {
276 DRM_ERROR("DRM not initialized, aborting suspend.\n");
280 DRM_DEBUG_KMS("starting suspend\n");
281 error = i915_drm_freeze(dev);
285 error = bus_generic_suspend(kdev);
286 DRM_DEBUG_KMS("finished suspend %d\n", error);
290 static int i915_drm_thaw(struct drm_device *dev)
292 struct drm_i915_private *dev_priv = dev->dev_private;
296 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
297 i915_gem_restore_gtt_mappings(dev);
300 i915_restore_state(dev);
301 intel_opregion_setup(dev);
303 /* KMS EnterVT equivalent */
304 if (drm_core_check_feature(dev, DRIVER_MODESET)) {
305 dev_priv->mm.suspended = 0;
307 error = i915_gem_init_hw(dev);
309 if (HAS_PCH_SPLIT(dev))
310 ironlake_init_pch_refclk(dev);
313 sx_xlock(&dev->mode_config.mutex);
314 drm_mode_config_reset(dev);
315 sx_xunlock(&dev->mode_config.mutex);
316 drm_irq_install(dev);
318 sx_xlock(&dev->mode_config.mutex);
319 /* Resume the modeset for every activated CRTC */
320 drm_helper_resume_force_mode(dev);
321 sx_xunlock(&dev->mode_config.mutex);
323 if (IS_IRONLAKE_M(dev))
324 ironlake_enable_rc6(dev);
328 intel_opregion_init(dev);
330 dev_priv->modeset_on_lid = 0;
338 i915_resume(device_t kdev)
340 struct drm_device *dev;
343 dev = device_get_softc(kdev);
344 DRM_DEBUG_KMS("starting resume\n");
346 if (pci_enable_device(dev->pdev))
349 pci_set_master(dev->pdev);
352 ret = -i915_drm_thaw(dev);
356 drm_kms_helper_poll_enable(dev);
357 ret = bus_generic_resume(kdev);
358 DRM_DEBUG_KMS("finished resume %d\n", ret);
363 i915_probe(device_t kdev)
366 return drm_probe(kdev, i915_pciidlist);
372 i915_attach(device_t kdev)
374 struct drm_device *dev;
376 dev = device_get_softc(kdev);
377 if (i915_modeset == 1)
378 i915_driver_info.driver_features |= DRIVER_MODESET;
379 dev->driver = &i915_driver_info;
380 return (drm_attach(kdev, i915_pciidlist));
383 const struct intel_device_info *
384 i915_get_device_id(int device)
386 const struct intel_gfx_device_id *did;
388 for (did = &pciidlist[0]; did->device != 0; did++) {
389 if (did->device != device)
396 static device_method_t i915_methods[] = {
397 /* Device interface */
398 DEVMETHOD(device_probe, i915_probe),
399 DEVMETHOD(device_attach, i915_attach),
400 DEVMETHOD(device_suspend, i915_suspend),
401 DEVMETHOD(device_resume, i915_resume),
402 DEVMETHOD(device_detach, drm_detach),
406 static driver_t i915_driver = {
409 sizeof(struct drm_device)
412 extern devclass_t drm_devclass;
413 DRIVER_MODULE_ORDERED(i915kms, vgapci, i915_driver, drm_devclass, 0, 0,
415 MODULE_DEPEND(i915kms, drmn, 1, 1, 1);
416 MODULE_DEPEND(i915kms, agp, 1, 1, 1);
417 MODULE_DEPEND(i915kms, iicbus, 1, 1, 1);
418 MODULE_DEPEND(i915kms, iic, 1, 1, 1);
419 MODULE_DEPEND(i915kms, iicbb, 1, 1, 1);
421 int intel_iommu_enabled = 0;
422 TUNABLE_INT("drm.i915.intel_iommu_enabled", &intel_iommu_enabled);
424 int i915_semaphores = -1;
425 TUNABLE_INT("drm.i915.semaphores", &i915_semaphores);
426 static int i915_try_reset = 1;
427 TUNABLE_INT("drm.i915.try_reset", &i915_try_reset);
428 unsigned int i915_lvds_downclock = 0;
429 TUNABLE_INT("drm.i915.lvds_downclock", &i915_lvds_downclock);
430 int i915_vbt_sdvo_panel_type = -1;
431 TUNABLE_INT("drm.i915.vbt_sdvo_panel_type", &i915_vbt_sdvo_panel_type);
432 unsigned int i915_powersave = 1;
433 TUNABLE_INT("drm.i915.powersave", &i915_powersave);
434 int i915_enable_fbc = 0;
435 TUNABLE_INT("drm.i915.enable_fbc", &i915_enable_fbc);
436 int i915_enable_rc6 = 0;
437 TUNABLE_INT("drm.i915.enable_rc6", &i915_enable_rc6);
438 int i915_panel_use_ssc = -1;
439 TUNABLE_INT("drm.i915.panel_use_ssc", &i915_panel_use_ssc);
440 int i915_panel_ignore_lid = 0;
441 TUNABLE_INT("drm.i915.panel_ignore_lid", &i915_panel_ignore_lid);
442 int i915_modeset = 1;
443 TUNABLE_INT("drm.i915.modeset", &i915_modeset);
444 int i915_enable_ppgtt = -1;
445 TUNABLE_INT("drm.i915.enable_ppgtt", &i915_enable_ppgtt);
446 int i915_enable_hangcheck = 1;
447 TUNABLE_INT("drm.i915.enable_hangcheck", &i915_enable_hangcheck);
449 #define PCI_VENDOR_INTEL 0x8086
450 #define INTEL_PCH_DEVICE_ID_MASK 0xff00
451 #define INTEL_PCH_IBX_DEVICE_ID_TYPE 0x3b00
452 #define INTEL_PCH_CPT_DEVICE_ID_TYPE 0x1c00
453 #define INTEL_PCH_PPT_DEVICE_ID_TYPE 0x1e00
456 intel_detect_pch(struct drm_device *dev)
458 struct drm_i915_private *dev_priv;
462 dev_priv = dev->dev_private;
463 pch = pci_find_class(PCIC_BRIDGE, PCIS_BRIDGE_ISA);
464 if (pch != NULL && pci_get_vendor(pch) == PCI_VENDOR_INTEL) {
465 id = pci_get_device(pch) & INTEL_PCH_DEVICE_ID_MASK;
466 if (id == INTEL_PCH_IBX_DEVICE_ID_TYPE) {
467 dev_priv->pch_type = PCH_IBX;
468 DRM_DEBUG_KMS("Found Ibex Peak PCH\n");
469 } else if (id == INTEL_PCH_CPT_DEVICE_ID_TYPE) {
470 dev_priv->pch_type = PCH_CPT;
471 DRM_DEBUG_KMS("Found CougarPoint PCH\n");
472 } else if (id == INTEL_PCH_PPT_DEVICE_ID_TYPE) {
473 /* PantherPoint is CPT compatible */
474 dev_priv->pch_type = PCH_CPT;
475 DRM_DEBUG_KMS("Found PatherPoint PCH\n");
477 DRM_DEBUG_KMS("No PCH detected\n");
479 DRM_DEBUG_KMS("No Intel PCI-ISA bridge found\n");
483 __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
488 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1))
491 I915_WRITE_NOTRACE(FORCEWAKE, 1);
492 POSTING_READ(FORCEWAKE);
495 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0)
500 __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
505 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1))
508 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 1);
509 POSTING_READ(FORCEWAKE_MT);
512 while (count++ < 50 && (I915_READ_NOTRACE(FORCEWAKE_MT_ACK) & 1) == 0)
517 gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
520 mtx_lock(&dev_priv->gt_lock);
521 if (dev_priv->forcewake_count++ == 0)
522 dev_priv->display.force_wake_get(dev_priv);
523 mtx_unlock(&dev_priv->gt_lock);
527 gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
531 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
532 if ((gtfifodbg & GT_FIFO_CPU_ERROR_MASK) != 0) {
533 printf("MMIO read or write has been dropped %x\n", gtfifodbg);
534 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
539 __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
542 I915_WRITE_NOTRACE(FORCEWAKE, 0);
543 /* The below doubles as a POSTING_READ */
544 gen6_gt_check_fifodbg(dev_priv);
548 __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
551 I915_WRITE_NOTRACE(FORCEWAKE_MT, (1<<16) | 0);
552 /* The below doubles as a POSTING_READ */
553 gen6_gt_check_fifodbg(dev_priv);
557 gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
560 mtx_lock(&dev_priv->gt_lock);
561 if (--dev_priv->forcewake_count == 0)
562 dev_priv->display.force_wake_put(dev_priv);
563 mtx_unlock(&dev_priv->gt_lock);
567 __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
571 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
573 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
574 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
576 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
578 if (loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES) {
579 printf("%s loop\n", __func__);
582 dev_priv->gt_fifo_count = fifo;
584 dev_priv->gt_fifo_count--;
590 i8xx_do_reset(struct drm_device *dev, u8 flags)
592 struct drm_i915_private *dev_priv = dev->dev_private;
602 I915_WRITE(D_STATE, I915_READ(D_STATE) | DSTATE_GFX_RESET_I830);
603 POSTING_READ(D_STATE);
605 if (IS_I830(dev) || IS_845G(dev)) {
606 I915_WRITE(DEBUG_RESET_I830,
607 DEBUG_RESET_DISPLAY |
610 POSTING_READ(DEBUG_RESET_I830);
611 pause("i8xxrst1", onems);
613 I915_WRITE(DEBUG_RESET_I830, 0);
614 POSTING_READ(DEBUG_RESET_I830);
617 pause("i8xxrst2", onems);
619 I915_WRITE(D_STATE, I915_READ(D_STATE) & ~DSTATE_GFX_RESET_I830);
620 POSTING_READ(D_STATE);
626 i965_reset_complete(struct drm_device *dev)
630 gdrst = pci_read_config(dev->device, I965_GDRST, 1);
631 return (gdrst & 0x1);
635 i965_do_reset(struct drm_device *dev, u8 flags)
640 * Set the domains we want to reset (GRDOM/bits 2 and 3) as
641 * well as the reset bit (GR/bit 0). Setting the GR bit
642 * triggers the reset; when done, the hardware will clear it.
644 gdrst = pci_read_config(dev->device, I965_GDRST, 1);
645 pci_write_config(dev->device, I965_GDRST, gdrst | flags | 0x1, 1);
647 return (_intel_wait_for(dev, i965_reset_complete(dev), 500, 1,
652 ironlake_do_reset(struct drm_device *dev, u8 flags)
654 struct drm_i915_private *dev_priv;
657 dev_priv = dev->dev_private;
658 gdrst = I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR);
659 I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, gdrst | flags | 0x1);
660 return (_intel_wait_for(dev,
661 (I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & 0x1) != 0,
666 gen6_do_reset(struct drm_device *dev, u8 flags)
668 struct drm_i915_private *dev_priv;
671 dev_priv = dev->dev_private;
673 /* Hold gt_lock across reset to prevent any register access
674 * with forcewake not set correctly
676 mtx_lock(&dev_priv->gt_lock);
680 /* GEN6_GDRST is not in the gt power well, no need to check
681 * for fifo space for the write or forcewake the chip for
684 I915_WRITE_NOTRACE(GEN6_GDRST, GEN6_GRDOM_FULL);
686 /* Spin waiting for the device to ack the reset request */
687 ret = _intel_wait_for(dev,
688 (I915_READ(GEN6_GDRST) & GEN6_GRDOM_FULL) == 0,
691 /* If reset with a user forcewake, try to restore, otherwise turn it off */
692 if (dev_priv->forcewake_count)
693 dev_priv->display.force_wake_get(dev_priv);
695 dev_priv->display.force_wake_put(dev_priv);
697 /* Restore fifo count */
698 dev_priv->gt_fifo_count = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
700 mtx_unlock(&dev_priv->gt_lock);
705 i915_reset(struct drm_device *dev, u8 flags)
707 drm_i915_private_t *dev_priv = dev->dev_private;
709 * We really should only reset the display subsystem if we actually
712 bool need_display = true;
718 if (!sx_try_xlock(&dev->dev_struct_lock))
724 if (time_second - dev_priv->last_gpu_reset < 5) {
725 DRM_ERROR("GPU hanging too fast, declaring wedged!\n");
727 switch (INTEL_INFO(dev)->gen) {
730 ret = gen6_do_reset(dev, flags);
733 ret = ironlake_do_reset(dev, flags);
736 ret = i965_do_reset(dev, flags);
739 ret = i8xx_do_reset(dev, flags);
743 dev_priv->last_gpu_reset = time_second;
745 DRM_ERROR("Failed to reset chip.\n");
750 if (drm_core_check_feature(dev, DRIVER_MODESET) ||
751 !dev_priv->mm.suspended) {
752 dev_priv->mm.suspended = 0;
754 i915_gem_init_swizzling(dev);
756 dev_priv->rings[RCS].init(&dev_priv->rings[RCS]);
758 dev_priv->rings[VCS].init(&dev_priv->rings[VCS]);
760 dev_priv->rings[BCS].init(&dev_priv->rings[BCS]);
762 i915_gem_init_ppgtt(dev);
764 drm_irq_uninstall(dev);
765 drm_mode_config_reset(dev);
767 drm_irq_install(dev);
773 sx_xlock(&dev->mode_config.mutex);
774 drm_helper_resume_force_mode(dev);
775 sx_xunlock(&dev->mode_config.mutex);
781 #define __i915_read(x, y) \
782 u##x i915_read##x(struct drm_i915_private *dev_priv, u32 reg) { \
784 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
785 mtx_lock(&dev_priv->gt_lock); \
786 if (dev_priv->forcewake_count == 0) \
787 dev_priv->display.force_wake_get(dev_priv); \
788 val = DRM_READ##y(dev_priv->mmio_map, reg); \
789 if (dev_priv->forcewake_count == 0) \
790 dev_priv->display.force_wake_put(dev_priv); \
791 mtx_unlock(&dev_priv->gt_lock); \
793 val = DRM_READ##y(dev_priv->mmio_map, reg); \
795 trace_i915_reg_rw(false, reg, val, sizeof(val)); \
805 #define __i915_write(x, y) \
806 void i915_write##x(struct drm_i915_private *dev_priv, u32 reg, u##x val) { \
807 u32 __fifo_ret = 0; \
808 trace_i915_reg_rw(true, reg, val, sizeof(val)); \
809 if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \
810 __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \
812 DRM_WRITE##y(dev_priv->mmio_map, reg, val); \
813 if (__predict_false(__fifo_ret)) { \
814 gen6_gt_check_fifodbg(dev_priv); \