2 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
3 * Copyright © 2006-2008,2010 Intel Corporation
4 * Jesse Barnes <jesse.barnes@intel.com>
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
23 * DEALINGS IN THE SOFTWARE.
26 * Eric Anholt <eric@anholt.net>
27 * Chris Wilson <chris@chris-wilson.co.uk>
29 * Copyright (c) 2011 The FreeBSD Foundation
30 * All rights reserved.
32 * This software was developed by Konstantin Belousov under sponsorship from
33 * the FreeBSD Foundation.
35 * Redistribution and use in source and binary forms, with or without
36 * modification, are permitted provided that the following conditions
38 * 1. Redistributions of source code must retain the above copyright
39 * notice, this list of conditions and the following disclaimer.
40 * 2. Redistributions in binary form must reproduce the above copyright
41 * notice, this list of conditions and the following disclaimer in the
42 * documentation and/or other materials provided with the distribution.
44 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
45 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
47 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
50 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
51 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
52 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
53 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
56 #include <sys/cdefs.h>
57 __FBSDID("$FreeBSD$");
59 #include <dev/drm2/drmP.h>
60 #include <dev/drm2/drm.h>
61 #include <dev/drm2/i915/i915_drm.h>
62 #include <dev/drm2/i915/i915_drv.h>
63 #include <dev/drm2/i915/intel_drv.h>
64 #include <dev/iicbus/iic.h>
65 #include <dev/iicbus/iiconf.h>
66 #include <dev/iicbus/iicbus.h>
67 #include "iicbus_if.h"
70 static void intel_teardown_gmbus_m(struct drm_device *dev, int m);
77 static const struct gmbus_port gmbus_ports[] = {
86 /* Intel GPIO access functions */
88 #define I2C_RISEFALL_TIME 10
90 struct intel_iic_softc {
91 struct drm_device *drm_dev;
100 intel_iic_quirk_set(struct drm_i915_private *dev_priv, bool enable)
104 /* When using bit bashing for I2C, this bit needs to be set to 1 */
105 if (!IS_PINEVIEW(dev_priv->dev))
108 val = I915_READ(DSPCLK_GATE_D);
110 val |= DPCUNIT_CLOCK_GATE_DISABLE;
112 val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
113 I915_WRITE(DSPCLK_GATE_D, val);
117 intel_iic_get_reserved(device_t idev)
119 struct intel_iic_softc *sc;
120 struct drm_device *dev;
121 struct drm_i915_private *dev_priv;
124 sc = device_get_softc(idev);
126 dev_priv = dev->dev_private;
128 if (!IS_I830(dev) && !IS_845G(dev)) {
129 reserved = I915_READ_NOTRACE(sc->reg) &
130 (GPIO_DATA_PULLUP_DISABLE | GPIO_CLOCK_PULLUP_DISABLE);
139 intel_iic_reset(struct drm_device *dev)
141 struct drm_i915_private *dev_priv;
143 dev_priv = dev->dev_private;
144 I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
148 intel_iicbus_reset(device_t idev, u_char speed, u_char addr, u_char *oldaddr)
150 struct intel_iic_softc *sc;
151 struct drm_device *dev;
153 sc = device_get_softc(idev);
156 intel_iic_reset(dev);
161 intel_iicbb_setsda(device_t idev, int val)
163 struct intel_iic_softc *sc;
164 struct drm_i915_private *dev_priv;
168 sc = device_get_softc(idev);
169 dev_priv = sc->drm_dev->dev_private;
171 reserved = intel_iic_get_reserved(idev);
173 data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
175 data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
178 I915_WRITE_NOTRACE(sc->reg, reserved | data_bits);
179 POSTING_READ(sc->reg);
183 intel_iicbb_setscl(device_t idev, int val)
185 struct intel_iic_softc *sc;
186 struct drm_i915_private *dev_priv;
187 u32 clock_bits, reserved;
189 sc = device_get_softc(idev);
190 dev_priv = sc->drm_dev->dev_private;
192 reserved = intel_iic_get_reserved(idev);
194 clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
196 clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
199 I915_WRITE_NOTRACE(sc->reg, reserved | clock_bits);
200 POSTING_READ(sc->reg);
204 intel_iicbb_getsda(device_t idev)
206 struct intel_iic_softc *sc;
207 struct drm_i915_private *dev_priv;
210 sc = device_get_softc(idev);
211 dev_priv = sc->drm_dev->dev_private;
213 reserved = intel_iic_get_reserved(idev);
215 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_DATA_DIR_MASK);
216 I915_WRITE_NOTRACE(sc->reg, reserved);
217 return ((I915_READ_NOTRACE(sc->reg) & GPIO_DATA_VAL_IN) != 0);
221 intel_iicbb_getscl(device_t idev)
223 struct intel_iic_softc *sc;
224 struct drm_i915_private *dev_priv;
227 sc = device_get_softc(idev);
228 dev_priv = sc->drm_dev->dev_private;
230 reserved = intel_iic_get_reserved(idev);
232 I915_WRITE_NOTRACE(sc->reg, reserved | GPIO_CLOCK_DIR_MASK);
233 I915_WRITE_NOTRACE(sc->reg, reserved);
234 return ((I915_READ_NOTRACE(sc->reg) & GPIO_CLOCK_VAL_IN) != 0);
238 gmbus_xfer_read(struct drm_i915_private *dev_priv, struct iic_msg *msg,
241 int reg_offset = dev_priv->gpio_mmio_base;
245 I915_WRITE(GMBUS1 + reg_offset,
248 (len << GMBUS_BYTE_COUNT_SHIFT) |
249 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
250 GMBUS_SLAVE_READ | GMBUS_SW_RDY);
256 ret = _intel_wait_for(sc->drm_dev,
257 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
258 (GMBUS_SATOER | GMBUS_HW_RDY)),
262 if (gmbus2 & GMBUS_SATOER)
265 val = I915_READ(GMBUS3 + reg_offset);
269 } while (--len != 0 && ++loop < 4);
276 gmbus_xfer_write(struct drm_i915_private *dev_priv, struct iic_msg *msg)
278 int reg_offset = dev_priv->gpio_mmio_base;
284 while (len && loop < 4) {
285 val |= *buf++ << (8 * loop++);
289 I915_WRITE(GMBUS3 + reg_offset, val);
290 I915_WRITE(GMBUS1 + reg_offset,
292 (msg->len << GMBUS_BYTE_COUNT_SHIFT) |
293 (msg->slave << (GMBUS_SLAVE_ADDR_SHIFT - 1)) |
294 GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
301 val |= *buf++ << (8 * loop);
302 } while (--len != 0 && ++loop < 4);
304 I915_WRITE(GMBUS3 + reg_offset, val);
306 ret = _intel_wait_for(sc->drm_dev,
307 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
308 (GMBUS_SATOER | GMBUS_HW_RDY)),
312 if (gmbus2 & GMBUS_SATOER)
319 * The gmbus controller can combine a 1 or 2 byte write with a read that
320 * immediately follows it by using an "INDEX" cycle.
323 gmbus_is_index_read(struct iic_msg *msgs, int i, int num)
325 return (i + 1 < num &&
326 !(msgs[i].flags & IIC_M_RD) && msgs[i].len <= 2 &&
327 (msgs[i + 1].flags & IIC_M_RD));
331 gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct iic_msg *msgs)
333 int reg_offset = dev_priv->gpio_mmio_base;
334 u32 gmbus1_index = 0;
338 if (msgs[0].len == 2)
339 gmbus5 = GMBUS_2BYTE_INDEX_EN |
340 msgs[0].buf[1] | (msgs[0].buf[0] << 8);
341 if (msgs[0].len == 1)
342 gmbus1_index = GMBUS_CYCLE_INDEX |
343 (msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
345 /* GMBUS5 holds 16-bit index */
347 I915_WRITE(GMBUS5 + reg_offset, gmbus5);
349 ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
351 /* Clear GMBUS5 after each index transfer */
353 I915_WRITE(GMBUS5 + reg_offset, 0);
359 intel_gmbus_transfer(device_t idev, struct iic_msg *msgs, uint32_t nmsgs)
361 struct intel_iic_softc *sc;
362 struct drm_i915_private *dev_priv;
363 int error, i, ret, reg_offset, unit;
366 sc = device_get_softc(idev);
367 dev_priv = sc->drm_dev->dev_private;
368 unit = device_get_unit(idev);
370 sx_xlock(&dev_priv->gmbus_sx);
371 if (sc->force_bit_dev) {
372 error = -IICBUS_TRANSFER(dev_priv->bbbus[unit], msgs, nmsgs);
376 reg_offset = dev_priv->gpio_mmio_base;
378 I915_WRITE(GMBUS0 + reg_offset, sc->reg0);
380 for (i = 0; i < nmsgs; i++) {
383 if (gmbus_is_index_read(msgs, i, nmsgs)) {
384 error = gmbus_xfer_index_read(dev_priv, &msgs[i]);
385 i += 1; /* set i to the index of the read xfer */
386 } else if (msgs[i].flags & IIC_M_RD) {
387 error = gmbus_xfer_read(dev_priv, &msgs[i], 0);
389 error = gmbus_xfer_write(dev_priv, &msgs[i]);
392 if (error == -ETIMEDOUT)
397 ret = _intel_wait_for(sc->drm_dev,
398 ((gmbus2 = I915_READ(GMBUS2 + reg_offset)) &
399 (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE)),
403 if (gmbus2 & GMBUS_SATOER)
407 /* Generate a STOP condition on the bus. Note that gmbus can't generata
408 * a STOP on the very first cycle. To simplify the code we
409 * unconditionally generate the STOP condition with an additional gmbus
411 I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
413 /* Mark the GMBUS interface as disabled after waiting for idle.
414 * We will re-enable it at the start of the next xfer,
415 * till then let it sleep.
417 if (_intel_wait_for(dev,
418 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
420 DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
424 I915_WRITE(GMBUS0 + reg_offset, 0);
429 * Wait for bus to IDLE before clearing NAK.
430 * If we clear the NAK while bus is still active, then it will stay
431 * active and the next transaction may fail.
433 if (_intel_wait_for(dev,
434 (I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0,
436 DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n", sc->name);
438 /* Toggle the Software Clear Interrupt bit. This has the effect
439 * of resetting the GMBUS controller and so clearing the
440 * BUS_ERROR raised by the slave's NAK.
442 I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
443 I915_WRITE(GMBUS1 + reg_offset, 0);
444 I915_WRITE(GMBUS0 + reg_offset, 0);
446 DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
447 sc->name, msgs[i].slave,
448 (msgs[i].flags & IIC_M_RD) ? 'r' : 'w', msgs[i].len);
451 * If no ACK is received during the address phase of a transaction,
452 * the adapter must report -ENXIO.
453 * It is not clear what to return if no ACK is received at other times.
454 * So, we always return -ENXIO in all NAK cases, to ensure we send
455 * it at least during the one case that is specified.
461 DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
462 sc->name, sc->reg0 & 0xff);
463 I915_WRITE(GMBUS0 + reg_offset, 0);
466 * Hardware may not support GMBUS over these pins?
467 * Try GPIO bitbanging instead.
469 sc->force_bit_dev = true;
470 error = -IICBUS_TRANSFER(idev, msgs, nmsgs);
474 sx_xunlock(&dev_priv->gmbus_sx);
479 intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
483 if (!intel_gmbus_is_port_valid(port))
484 DRM_ERROR("GMBUS get adapter %d: invalid port\n", port);
485 return (intel_gmbus_is_port_valid(port) ? dev_priv->gmbus[port - 1] :
490 intel_gmbus_set_speed(device_t idev, int speed)
492 struct intel_iic_softc *sc;
494 sc = device_get_softc(device_get_parent(idev));
496 sc->reg0 = (sc->reg0 & ~(0x3 << 8)) | speed;
500 intel_gmbus_force_bit(device_t idev, bool force_bit)
502 struct intel_iic_softc *sc;
504 sc = device_get_softc(device_get_parent(idev));
505 sc->force_bit_dev = force_bit;
509 intel_iicbb_pre_xfer(device_t idev)
511 struct intel_iic_softc *sc;
512 struct drm_i915_private *dev_priv;
514 sc = device_get_softc(idev);
515 dev_priv = sc->drm_dev->dev_private;
517 intel_iic_reset(sc->drm_dev);
518 intel_iic_quirk_set(dev_priv, true);
519 IICBB_SETSDA(idev, 1);
520 IICBB_SETSCL(idev, 1);
521 DELAY(I2C_RISEFALL_TIME);
526 intel_iicbb_post_xfer(device_t idev)
528 struct intel_iic_softc *sc;
529 struct drm_i915_private *dev_priv;
531 sc = device_get_softc(idev);
532 dev_priv = sc->drm_dev->dev_private;
534 IICBB_SETSDA(idev, 1);
535 IICBB_SETSCL(idev, 1);
536 intel_iic_quirk_set(dev_priv, false);
540 intel_gmbus_probe(device_t dev)
543 return (BUS_PROBE_SPECIFIC);
547 intel_gmbus_attach(device_t idev)
549 struct drm_i915_private *dev_priv;
550 struct intel_iic_softc *sc;
553 sc = device_get_softc(idev);
554 sc->drm_dev = device_get_softc(device_get_parent(idev));
555 dev_priv = sc->drm_dev->dev_private;
556 pin = device_get_unit(idev);
559 snprintf(sc->name, sizeof(sc->name), "gmbus %s",
560 intel_gmbus_is_port_valid(port) ? gmbus_ports[pin].name :
562 device_set_desc(idev, sc->name);
564 /* By default use a conservative clock rate */
565 sc->reg0 = port | GMBUS_RATE_100KHZ;
567 /* gmbus seems to be broken on i830 */
568 if (IS_I830(sc->drm_dev))
569 sc->force_bit_dev = true;
571 if (IS_GEN2(sc->drm_dev)) {
572 sc->force_bit_dev = true;
576 /* add bus interface device */
577 sc->iic_dev = device_add_child(idev, "iicbus", -1);
578 if (sc->iic_dev == NULL)
580 device_quiet(sc->iic_dev);
581 bus_generic_attach(idev);
587 intel_gmbus_detach(device_t idev)
589 struct intel_iic_softc *sc;
590 struct drm_i915_private *dev_priv;
594 sc = device_get_softc(idev);
595 u = device_get_unit(idev);
596 dev_priv = sc->drm_dev->dev_private;
599 bus_generic_detach(idev);
601 device_delete_child(idev, child);
607 intel_iicbb_probe(device_t dev)
610 return (BUS_PROBE_DEFAULT);
614 intel_iicbb_attach(device_t idev)
616 struct intel_iic_softc *sc;
617 struct drm_i915_private *dev_priv;
620 sc = device_get_softc(idev);
621 sc->drm_dev = device_get_softc(device_get_parent(idev));
622 dev_priv = sc->drm_dev->dev_private;
623 pin = device_get_unit(idev);
626 snprintf(sc->name, sizeof(sc->name), "i915 iicbb %s",
627 intel_gmbus_is_port_valid(port) ? gmbus_ports[pin].name :
629 device_set_desc(idev, sc->name);
631 if (!intel_gmbus_is_port_valid(port))
632 pin = 1 ; /* GPIOA, VGA */
633 sc->reg0 = pin | GMBUS_RATE_100KHZ;
634 sc->reg = dev_priv->gpio_mmio_base + gmbus_ports[pin].reg;
636 /* add generic bit-banging code */
637 sc->iic_dev = device_add_child(idev, "iicbb", -1);
638 if (sc->iic_dev == NULL)
640 device_quiet(sc->iic_dev);
641 bus_generic_attach(idev);
642 iicbus_set_nostop(idev, true);
648 intel_iicbb_detach(device_t idev)
650 struct intel_iic_softc *sc;
653 sc = device_get_softc(idev);
655 bus_generic_detach(idev);
657 device_delete_child(idev, child);
661 static device_method_t intel_gmbus_methods[] = {
662 DEVMETHOD(device_probe, intel_gmbus_probe),
663 DEVMETHOD(device_attach, intel_gmbus_attach),
664 DEVMETHOD(device_detach, intel_gmbus_detach),
665 DEVMETHOD(iicbus_reset, intel_iicbus_reset),
666 DEVMETHOD(iicbus_transfer, intel_gmbus_transfer),
669 static driver_t intel_gmbus_driver = {
672 sizeof(struct intel_iic_softc)
674 static devclass_t intel_gmbus_devclass;
675 DRIVER_MODULE_ORDERED(intel_gmbus, drmn, intel_gmbus_driver,
676 intel_gmbus_devclass, 0, 0, SI_ORDER_FIRST);
677 DRIVER_MODULE(iicbus, intel_gmbus, iicbus_driver, iicbus_devclass, 0, 0);
679 static device_method_t intel_iicbb_methods[] = {
680 DEVMETHOD(device_probe, intel_iicbb_probe),
681 DEVMETHOD(device_attach, intel_iicbb_attach),
682 DEVMETHOD(device_detach, intel_iicbb_detach),
684 DEVMETHOD(bus_add_child, bus_generic_add_child),
685 DEVMETHOD(bus_print_child, bus_generic_print_child),
687 DEVMETHOD(iicbb_callback, iicbus_null_callback),
688 DEVMETHOD(iicbb_reset, intel_iicbus_reset),
689 DEVMETHOD(iicbb_setsda, intel_iicbb_setsda),
690 DEVMETHOD(iicbb_setscl, intel_iicbb_setscl),
691 DEVMETHOD(iicbb_getsda, intel_iicbb_getsda),
692 DEVMETHOD(iicbb_getscl, intel_iicbb_getscl),
693 DEVMETHOD(iicbb_pre_xfer, intel_iicbb_pre_xfer),
694 DEVMETHOD(iicbb_post_xfer, intel_iicbb_post_xfer),
697 static driver_t intel_iicbb_driver = {
700 sizeof(struct intel_iic_softc)
702 static devclass_t intel_iicbb_devclass;
703 DRIVER_MODULE_ORDERED(intel_iicbb, drmn, intel_iicbb_driver,
704 intel_iicbb_devclass, 0, 0, SI_ORDER_FIRST);
705 DRIVER_MODULE(iicbb, intel_iicbb, iicbb_driver, iicbb_devclass, 0, 0);
708 intel_setup_gmbus(struct drm_device *dev)
710 struct drm_i915_private *dev_priv;
714 dev_priv = dev->dev_private;
715 sx_init(&dev_priv->gmbus_sx, "gmbus");
716 if (HAS_PCH_SPLIT(dev))
717 dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
719 dev_priv->gpio_mmio_base = 0;
722 * The Giant there is recursed, most likely. Normally, the
723 * intel_setup_gmbus() is called from the attach method of the
727 for (i = 0; i <= GMBUS_NUM_PORTS; i++) {
729 * Initialized bbbus_bridge before gmbus_bridge, since
730 * gmbus may decide to force quirk transfer in the
733 dev_priv->bbbus_bridge[i] = device_add_child(dev->dev,
735 if (dev_priv->bbbus_bridge[i] == NULL) {
736 DRM_ERROR("bbbus bridge %d creation failed\n", i);
740 device_quiet(dev_priv->bbbus_bridge[i]);
741 ret = -device_probe_and_attach(dev_priv->bbbus_bridge[i]);
743 DRM_ERROR("bbbus bridge %d attach failed, %d\n", i,
748 iic_dev = device_find_child(dev_priv->bbbus_bridge[i], "iicbb",
750 if (iic_dev == NULL) {
751 DRM_ERROR("bbbus bridge doesn't have iicbb child\n");
754 iic_dev = device_find_child(iic_dev, "iicbus", -1);
755 if (iic_dev == NULL) {
757 "bbbus bridge doesn't have iicbus grandchild\n");
761 dev_priv->bbbus[i] = iic_dev;
763 dev_priv->gmbus_bridge[i] = device_add_child(dev->dev,
765 if (dev_priv->gmbus_bridge[i] == NULL) {
766 DRM_ERROR("gmbus bridge %d creation failed\n", i);
770 device_quiet(dev_priv->gmbus_bridge[i]);
771 ret = -device_probe_and_attach(dev_priv->gmbus_bridge[i]);
773 DRM_ERROR("gmbus bridge %d attach failed, %d\n", i,
779 iic_dev = device_find_child(dev_priv->gmbus_bridge[i],
781 if (iic_dev == NULL) {
782 DRM_ERROR("gmbus bridge doesn't have iicbus child\n");
785 dev_priv->gmbus[i] = iic_dev;
787 intel_iic_reset(dev);
794 intel_teardown_gmbus_m(dev, i);
800 intel_teardown_gmbus_m(struct drm_device *dev, int m)
802 struct drm_i915_private *dev_priv;
804 dev_priv = dev->dev_private;
806 sx_destroy(&dev_priv->gmbus_sx);
810 intel_teardown_gmbus(struct drm_device *dev)
814 intel_teardown_gmbus_m(dev, GMBUS_NUM_PORTS);