4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Daniel Vetter <daniel@ffwll.ch>
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <dev/drm2/drmP.h>
33 #include <dev/drm2/drm.h>
34 #include <dev/drm2/i915/i915_drm.h>
35 #include <dev/drm2/i915/i915_drv.h>
36 #include <dev/drm2/i915/i915_reg.h>
37 #include <dev/drm2/i915/intel_drv.h>
39 /* Limits for overlay size. According to intel doc, the real limits are:
40 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
41 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
42 * the mininum of both. */
43 #define IMAGE_MAX_WIDTH 2048
44 #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
45 /* on 830 and 845 these large limits result in the card hanging */
46 #define IMAGE_MAX_WIDTH_LEGACY 1024
47 #define IMAGE_MAX_HEIGHT_LEGACY 1088
49 /* overlay register definitions */
51 #define OCMD_TILED_SURFACE (0x1<<19)
52 #define OCMD_MIRROR_MASK (0x3<<17)
53 #define OCMD_MIRROR_MODE (0x3<<17)
54 #define OCMD_MIRROR_HORIZONTAL (0x1<<17)
55 #define OCMD_MIRROR_VERTICAL (0x2<<17)
56 #define OCMD_MIRROR_BOTH (0x3<<17)
57 #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
58 #define OCMD_UV_SWAP (0x1<<14) /* YVYU */
59 #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
60 #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
61 #define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
62 #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
63 #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
64 #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
65 #define OCMD_YUV_422_PACKED (0x8<<10)
66 #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
67 #define OCMD_YUV_420_PLANAR (0xc<<10)
68 #define OCMD_YUV_422_PLANAR (0xd<<10)
69 #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
70 #define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
71 #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
72 #define OCMD_BUF_TYPE_MASK (0x1<<5)
73 #define OCMD_BUF_TYPE_FRAME (0x0<<5)
74 #define OCMD_BUF_TYPE_FIELD (0x1<<5)
75 #define OCMD_TEST_MODE (0x1<<4)
76 #define OCMD_BUFFER_SELECT (0x3<<2)
77 #define OCMD_BUFFER0 (0x0<<2)
78 #define OCMD_BUFFER1 (0x1<<2)
79 #define OCMD_FIELD_SELECT (0x1<<2)
80 #define OCMD_FIELD0 (0x0<<1)
81 #define OCMD_FIELD1 (0x1<<1)
82 #define OCMD_ENABLE (0x1<<0)
84 /* OCONFIG register */
85 #define OCONF_PIPE_MASK (0x1<<18)
86 #define OCONF_PIPE_A (0x0<<18)
87 #define OCONF_PIPE_B (0x1<<18)
88 #define OCONF_GAMMA2_ENABLE (0x1<<16)
89 #define OCONF_CSC_MODE_BT601 (0x0<<5)
90 #define OCONF_CSC_MODE_BT709 (0x1<<5)
91 #define OCONF_CSC_BYPASS (0x1<<4)
92 #define OCONF_CC_OUT_8BIT (0x1<<3)
93 #define OCONF_TEST_MODE (0x1<<2)
94 #define OCONF_THREE_LINE_BUFFER (0x1<<0)
95 #define OCONF_TWO_LINE_BUFFER (0x0<<0)
97 /* DCLRKM (dst-key) register */
98 #define DST_KEY_ENABLE (0x1<<31)
99 #define CLK_RGB24_MASK 0x0
100 #define CLK_RGB16_MASK 0x070307
101 #define CLK_RGB15_MASK 0x070707
102 #define CLK_RGB8I_MASK 0xffffff
104 #define RGB16_TO_COLORKEY(c) \
105 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
106 #define RGB15_TO_COLORKEY(c) \
107 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
109 /* overlay flip addr flag */
110 #define OFC_UPDATE 0x1
112 /* polyphase filter coefficients */
113 #define N_HORIZ_Y_TAPS 5
114 #define N_VERT_Y_TAPS 3
115 #define N_HORIZ_UV_TAPS 3
116 #define N_VERT_UV_TAPS 3
120 /* memory bufferd overlay registers */
121 struct overlay_registers {
149 u32 RESERVED1; /* 0x6C */
162 u32 FASTHSCALE; /* 0xA0 */
163 u32 UVSCALEV; /* 0xA4 */
164 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
165 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
166 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
167 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
168 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
169 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
170 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
171 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
172 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
175 struct intel_overlay {
176 struct drm_device *dev;
177 struct intel_crtc *crtc;
178 struct drm_i915_gem_object *vid_bo;
179 struct drm_i915_gem_object *old_vid_bo;
182 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
184 u32 brightness, contrast, saturation;
185 u32 old_xscale, old_yscale;
186 /* register access */
188 struct drm_i915_gem_object *reg_bo;
190 uint32_t last_flip_req;
191 void (*flip_tail)(struct intel_overlay *);
194 static struct overlay_registers *
195 intel_overlay_map_regs(struct intel_overlay *overlay)
197 struct overlay_registers *regs;
199 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev)) {
200 regs = overlay->reg_bo->phys_obj->handle->vaddr;
202 regs = pmap_mapdev_attr(overlay->dev->agp->base +
203 overlay->reg_bo->gtt_offset, PAGE_SIZE,
204 PAT_WRITE_COMBINING);
209 static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
210 struct overlay_registers *regs)
212 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
213 pmap_unmapdev((vm_offset_t)regs, PAGE_SIZE);
216 static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
217 struct drm_i915_gem_request *request,
218 void (*tail)(struct intel_overlay *))
220 struct drm_device *dev = overlay->dev;
221 drm_i915_private_t *dev_priv = dev->dev_private;
224 KASSERT(!overlay->last_flip_req, ("Overlay already has flip req"));
225 ret = i915_add_request(LP_RING(dev_priv), NULL, request);
227 free(request, DRM_I915_GEM);
230 overlay->last_flip_req = request->seqno;
231 overlay->flip_tail = tail;
232 ret = i915_wait_request(LP_RING(dev_priv), overlay->last_flip_req,
237 overlay->last_flip_req = 0;
241 /* Workaround for i830 bug where pipe a must be enable to change control regs */
243 i830_activate_pipe_a(struct drm_device *dev)
245 drm_i915_private_t *dev_priv = dev->dev_private;
246 struct intel_crtc *crtc;
247 struct drm_crtc_helper_funcs *crtc_funcs;
248 struct drm_display_mode vesa_640x480 = {
249 DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
250 752, 800, 0, 480, 489, 492, 525, 0,
251 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)
254 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[0]);
255 if (crtc->dpms_mode == DRM_MODE_DPMS_ON)
258 /* most i8xx have pipe a forced on, so don't trust dpms mode */
259 if (I915_READ(_PIPEACONF) & PIPECONF_ENABLE)
262 crtc_funcs = crtc->base.helper_private;
263 if (crtc_funcs->dpms == NULL)
266 DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
268 mode = drm_mode_duplicate(dev, &vesa_640x480);
269 drm_mode_set_crtcinfo(mode, 0);
270 if (!drm_crtc_helper_set_mode(&crtc->base, mode,
271 crtc->base.x, crtc->base.y,
275 crtc_funcs->dpms(&crtc->base, DRM_MODE_DPMS_ON);
280 i830_deactivate_pipe_a(struct drm_device *dev)
282 drm_i915_private_t *dev_priv = dev->dev_private;
283 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[0];
284 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
286 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
289 /* overlay needs to be disable in OCMD reg */
290 static int intel_overlay_on(struct intel_overlay *overlay)
292 struct drm_device *dev = overlay->dev;
293 struct drm_i915_private *dev_priv = dev->dev_private;
294 struct drm_i915_gem_request *request;
295 int pipe_a_quirk = 0;
298 KASSERT(!overlay->active, ("Overlay is active"));
302 pipe_a_quirk = i830_activate_pipe_a(dev);
303 if (pipe_a_quirk < 0)
307 request = malloc(sizeof(*request), DRM_I915_GEM, M_WAITOK | M_ZERO);
309 ret = BEGIN_LP_RING(4);
311 free(request, DRM_I915_GEM);
315 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
316 OUT_RING(overlay->flip_addr | OFC_UPDATE);
317 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
321 ret = intel_overlay_do_wait_request(overlay, request, NULL);
324 i830_deactivate_pipe_a(dev);
329 /* overlay needs to be enabled in OCMD reg */
330 static int intel_overlay_continue(struct intel_overlay *overlay,
331 bool load_polyphase_filter)
333 struct drm_device *dev = overlay->dev;
334 drm_i915_private_t *dev_priv = dev->dev_private;
335 struct drm_i915_gem_request *request;
336 u32 flip_addr = overlay->flip_addr;
340 KASSERT(overlay->active, ("Overlay not active"));
342 request = malloc(sizeof(*request), DRM_I915_GEM, M_WAITOK | M_ZERO);
344 if (load_polyphase_filter)
345 flip_addr |= OFC_UPDATE;
347 /* check for underruns */
348 tmp = I915_READ(DOVSTA);
350 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
352 ret = BEGIN_LP_RING(2);
354 free(request, DRM_I915_GEM);
357 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
361 ret = i915_add_request(LP_RING(dev_priv), NULL, request);
363 free(request, DRM_I915_GEM);
367 overlay->last_flip_req = request->seqno;
371 static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
373 struct drm_i915_gem_object *obj = overlay->old_vid_bo;
375 i915_gem_object_unpin(obj);
376 drm_gem_object_unreference(&obj->base);
378 overlay->old_vid_bo = NULL;
381 static void intel_overlay_off_tail(struct intel_overlay *overlay)
383 struct drm_i915_gem_object *obj = overlay->vid_bo;
385 /* never have the overlay hw on without showing a frame */
386 KASSERT(overlay->vid_bo != NULL, ("No vid_bo"));
388 i915_gem_object_unpin(obj);
389 drm_gem_object_unreference(&obj->base);
390 overlay->vid_bo = NULL;
392 overlay->crtc->overlay = NULL;
393 overlay->crtc = NULL;
397 /* overlay needs to be disabled in OCMD reg */
398 static int intel_overlay_off(struct intel_overlay *overlay)
400 struct drm_device *dev = overlay->dev;
401 struct drm_i915_private *dev_priv = dev->dev_private;
402 u32 flip_addr = overlay->flip_addr;
403 struct drm_i915_gem_request *request;
406 KASSERT(overlay->active, ("Overlay is not active"));
408 request = malloc(sizeof(*request), DRM_I915_GEM, M_WAITOK | M_ZERO);
410 /* According to intel docs the overlay hw may hang (when switching
411 * off) without loading the filter coeffs. It is however unclear whether
412 * this applies to the disabling of the overlay or to the switching off
413 * of the hw. Do it in both cases */
414 flip_addr |= OFC_UPDATE;
416 ret = BEGIN_LP_RING(6);
418 free(request, DRM_I915_GEM);
421 /* wait for overlay to go idle */
422 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
424 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
425 /* turn overlay off */
426 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
428 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
431 return intel_overlay_do_wait_request(overlay, request,
432 intel_overlay_off_tail);
435 /* recover from an interruption due to a signal
436 * We have to be careful not to repeat work forever an make forward progess. */
437 static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay)
439 struct drm_device *dev = overlay->dev;
440 drm_i915_private_t *dev_priv = dev->dev_private;
443 if (overlay->last_flip_req == 0)
446 ret = i915_wait_request(LP_RING(dev_priv), overlay->last_flip_req,
451 if (overlay->flip_tail)
452 overlay->flip_tail(overlay);
454 overlay->last_flip_req = 0;
458 /* Wait for pending overlay flip and release old frame.
459 * Needs to be called before the overlay register are changed
460 * via intel_overlay_(un)map_regs
462 static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
464 struct drm_device *dev = overlay->dev;
465 drm_i915_private_t *dev_priv = dev->dev_private;
468 /* Only wait if there is actually an old frame to release to
469 * guarantee forward progress.
471 if (!overlay->old_vid_bo)
474 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
475 struct drm_i915_gem_request *request;
477 /* synchronous slowpath */
478 request = malloc(sizeof(*request), DRM_I915_GEM, M_WAITOK | M_ZERO);
480 ret = BEGIN_LP_RING(2);
482 free(request, DRM_I915_GEM);
486 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
490 ret = intel_overlay_do_wait_request(overlay, request,
491 intel_overlay_release_old_vid_tail);
496 intel_overlay_release_old_vid_tail(overlay);
500 struct put_image_params {
517 static int packed_depth_bytes(u32 format)
519 switch (format & I915_OVERLAY_DEPTH_MASK) {
520 case I915_OVERLAY_YUV422:
522 case I915_OVERLAY_YUV411:
523 /* return 6; not implemented */
529 static int packed_width_bytes(u32 format, short width)
531 switch (format & I915_OVERLAY_DEPTH_MASK) {
532 case I915_OVERLAY_YUV422:
539 static int uv_hsubsampling(u32 format)
541 switch (format & I915_OVERLAY_DEPTH_MASK) {
542 case I915_OVERLAY_YUV422:
543 case I915_OVERLAY_YUV420:
545 case I915_OVERLAY_YUV411:
546 case I915_OVERLAY_YUV410:
553 static int uv_vsubsampling(u32 format)
555 switch (format & I915_OVERLAY_DEPTH_MASK) {
556 case I915_OVERLAY_YUV420:
557 case I915_OVERLAY_YUV410:
559 case I915_OVERLAY_YUV422:
560 case I915_OVERLAY_YUV411:
567 static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
569 u32 mask, shift, ret;
577 ret = ((offset + width + mask) >> shift) - (offset >> shift);
584 static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
585 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
586 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
587 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
588 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
589 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
590 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
591 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
592 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
593 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
594 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
595 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
596 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
597 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
598 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
599 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
600 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
601 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
604 static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
605 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
606 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
607 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
608 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
609 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
610 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
611 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
612 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
613 0x3000, 0x0800, 0x3000
616 static void update_polyphase_filter(struct overlay_registers *regs)
618 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
619 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
622 static bool update_scaling_factors(struct intel_overlay *overlay,
623 struct overlay_registers *regs,
624 struct put_image_params *params)
626 /* fixed point with a 12 bit shift */
627 u32 xscale, yscale, xscale_UV, yscale_UV;
629 #define FRACT_MASK 0xfff
630 bool scale_changed = false;
631 int uv_hscale = uv_hsubsampling(params->format);
632 int uv_vscale = uv_vsubsampling(params->format);
634 if (params->dst_w > 1)
635 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
638 xscale = 1 << FP_SHIFT;
640 if (params->dst_h > 1)
641 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
644 yscale = 1 << FP_SHIFT;
646 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
647 xscale_UV = xscale/uv_hscale;
648 yscale_UV = yscale/uv_vscale;
649 /* make the Y scale to UV scale ratio an exact multiply */
650 xscale = xscale_UV * uv_hscale;
651 yscale = yscale_UV * uv_vscale;
657 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
658 scale_changed = true;
659 overlay->old_xscale = xscale;
660 overlay->old_yscale = yscale;
662 regs->YRGBSCALE = (((yscale & FRACT_MASK) << 20) |
663 ((xscale >> FP_SHIFT) << 16) |
664 ((xscale & FRACT_MASK) << 3));
666 regs->UVSCALE = (((yscale_UV & FRACT_MASK) << 20) |
667 ((xscale_UV >> FP_SHIFT) << 16) |
668 ((xscale_UV & FRACT_MASK) << 3));
670 regs->UVSCALEV = ((((yscale >> FP_SHIFT) << 16) |
671 ((yscale_UV >> FP_SHIFT) << 0)));
674 update_polyphase_filter(regs);
676 return scale_changed;
679 static void update_colorkey(struct intel_overlay *overlay,
680 struct overlay_registers *regs)
682 u32 key = overlay->color_key;
684 switch (overlay->crtc->base.fb->bits_per_pixel) {
687 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
691 if (overlay->crtc->base.fb->depth == 15) {
692 regs->DCLRKV = RGB15_TO_COLORKEY(key);
693 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
695 regs->DCLRKV = RGB16_TO_COLORKEY(key);
696 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
703 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
708 static u32 overlay_cmd_reg(struct put_image_params *params)
710 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
712 if (params->format & I915_OVERLAY_YUV_PLANAR) {
713 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
714 case I915_OVERLAY_YUV422:
715 cmd |= OCMD_YUV_422_PLANAR;
717 case I915_OVERLAY_YUV420:
718 cmd |= OCMD_YUV_420_PLANAR;
720 case I915_OVERLAY_YUV411:
721 case I915_OVERLAY_YUV410:
722 cmd |= OCMD_YUV_410_PLANAR;
725 } else { /* YUV packed */
726 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
727 case I915_OVERLAY_YUV422:
728 cmd |= OCMD_YUV_422_PACKED;
730 case I915_OVERLAY_YUV411:
731 cmd |= OCMD_YUV_411_PACKED;
735 switch (params->format & I915_OVERLAY_SWAP_MASK) {
736 case I915_OVERLAY_NO_SWAP:
738 case I915_OVERLAY_UV_SWAP:
741 case I915_OVERLAY_Y_SWAP:
744 case I915_OVERLAY_Y_AND_UV_SWAP:
745 cmd |= OCMD_Y_AND_UV_SWAP;
754 max_u32(u32 a, u32 b)
757 return (a > b ? a : b);
760 static int intel_overlay_do_put_image(struct intel_overlay *overlay,
761 struct drm_i915_gem_object *new_bo,
762 struct put_image_params *params)
765 struct overlay_registers *regs;
766 bool scale_changed = false;
768 KASSERT(overlay != NULL, ("No overlay ?"));
769 DRM_LOCK_ASSERT(overlay->dev);
770 DRM_MODE_CONFIG_ASSERT_LOCKED(overlay->dev);
772 ret = intel_overlay_release_old_vid(overlay);
776 ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL);
780 ret = i915_gem_object_put_fence(new_bo);
784 if (!overlay->active) {
785 regs = intel_overlay_map_regs(overlay);
790 regs->OCONFIG = OCONF_CC_OUT_8BIT;
791 if (IS_GEN4(overlay->dev))
792 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
793 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
794 OCONF_PIPE_A : OCONF_PIPE_B;
795 intel_overlay_unmap_regs(overlay, regs);
797 ret = intel_overlay_on(overlay);
802 regs = intel_overlay_map_regs(overlay);
808 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
809 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
811 if (params->format & I915_OVERLAY_YUV_PACKED)
812 tmp_width = packed_width_bytes(params->format, params->src_w);
814 tmp_width = params->src_w;
816 regs->SWIDTH = params->src_w;
817 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
818 params->offset_Y, tmp_width);
819 regs->SHEIGHT = params->src_h;
820 regs->OBUF_0Y = new_bo->gtt_offset + params->offset_Y;
821 regs->OSTRIDE = params->stride_Y;
823 if (params->format & I915_OVERLAY_YUV_PLANAR) {
824 int uv_hscale = uv_hsubsampling(params->format);
825 int uv_vscale = uv_vsubsampling(params->format);
827 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
828 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
829 params->src_w/uv_hscale);
830 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
831 params->src_w/uv_hscale);
832 regs->SWIDTHSW |= max_u32(tmp_U, tmp_V) << 16;
833 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
834 regs->OBUF_0U = new_bo->gtt_offset + params->offset_U;
835 regs->OBUF_0V = new_bo->gtt_offset + params->offset_V;
836 regs->OSTRIDE |= params->stride_UV << 16;
839 scale_changed = update_scaling_factors(overlay, regs, params);
841 update_colorkey(overlay, regs);
843 regs->OCMD = overlay_cmd_reg(params);
845 intel_overlay_unmap_regs(overlay, regs);
847 ret = intel_overlay_continue(overlay, scale_changed);
851 overlay->old_vid_bo = overlay->vid_bo;
852 overlay->vid_bo = new_bo;
857 i915_gem_object_unpin(new_bo);
861 int intel_overlay_switch_off(struct intel_overlay *overlay)
863 struct overlay_registers *regs;
866 DRM_LOCK_ASSERT(overlay->dev);
867 DRM_MODE_CONFIG_ASSERT_LOCKED(overlay->dev);
869 ret = intel_overlay_recover_from_interrupt(overlay);
873 if (!overlay->active)
876 ret = intel_overlay_release_old_vid(overlay);
880 regs = intel_overlay_map_regs(overlay);
882 intel_overlay_unmap_regs(overlay, regs);
884 ret = intel_overlay_off(overlay);
888 intel_overlay_off_tail(overlay);
892 static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
893 struct intel_crtc *crtc)
895 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
900 /* can't use the overlay with double wide pipe */
901 if (INTEL_INFO(overlay->dev)->gen < 4 &&
902 (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
908 static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
910 struct drm_device *dev = overlay->dev;
911 drm_i915_private_t *dev_priv = dev->dev_private;
912 u32 pfit_control = I915_READ(PFIT_CONTROL);
915 /* XXX: This is not the same logic as in the xorg driver, but more in
916 * line with the intel documentation for the i965
918 if (INTEL_INFO(dev)->gen >= 4) {
919 /* on i965 use the PGM reg to read out the autoscaler values */
920 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
922 if (pfit_control & VERT_AUTO_SCALE)
923 ratio = I915_READ(PFIT_AUTO_RATIOS);
925 ratio = I915_READ(PFIT_PGM_RATIOS);
926 ratio >>= PFIT_VERT_SCALE_SHIFT;
929 overlay->pfit_vscale_ratio = ratio;
932 static int check_overlay_dst(struct intel_overlay *overlay,
933 struct drm_intel_overlay_put_image *rec)
935 struct drm_display_mode *mode = &overlay->crtc->base.mode;
937 if (rec->dst_x < mode->hdisplay &&
938 rec->dst_x + rec->dst_width <= mode->hdisplay &&
939 rec->dst_y < mode->vdisplay &&
940 rec->dst_y + rec->dst_height <= mode->vdisplay)
946 static int check_overlay_scaling(struct put_image_params *rec)
950 /* downscaling limit is 8.0 */
951 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
954 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
961 static int check_overlay_src(struct drm_device *dev,
962 struct drm_intel_overlay_put_image *rec,
963 struct drm_i915_gem_object *new_bo)
965 int uv_hscale = uv_hsubsampling(rec->flags);
966 int uv_vscale = uv_vsubsampling(rec->flags);
971 /* check src dimensions */
972 if (IS_845G(dev) || IS_I830(dev)) {
973 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
974 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
977 if (rec->src_height > IMAGE_MAX_HEIGHT ||
978 rec->src_width > IMAGE_MAX_WIDTH)
982 /* better safe than sorry, use 4 as the maximal subsampling ratio */
983 if (rec->src_height < N_VERT_Y_TAPS*4 ||
984 rec->src_width < N_HORIZ_Y_TAPS*4)
987 /* check alignment constraints */
988 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
989 case I915_OVERLAY_RGB:
990 /* not implemented */
993 case I915_OVERLAY_YUV_PACKED:
997 depth = packed_depth_bytes(rec->flags);
1001 /* ignore UV planes */
1005 /* check pixel alignment */
1006 if (rec->offset_Y % depth)
1010 case I915_OVERLAY_YUV_PLANAR:
1011 if (uv_vscale < 0 || uv_hscale < 0)
1013 /* no offset restrictions for planar formats */
1020 if (rec->src_width % uv_hscale)
1023 /* stride checking */
1024 if (IS_I830(dev) || IS_845G(dev))
1029 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1031 if (IS_GEN4(dev) && rec->stride_Y < 512)
1034 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1036 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
1039 /* check buffer dimensions */
1040 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
1041 case I915_OVERLAY_RGB:
1042 case I915_OVERLAY_YUV_PACKED:
1043 /* always 4 Y values per depth pixels */
1044 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1047 tmp = rec->stride_Y*rec->src_height;
1048 if (rec->offset_Y + tmp > new_bo->base.size)
1052 case I915_OVERLAY_YUV_PLANAR:
1053 if (rec->src_width > rec->stride_Y)
1055 if (rec->src_width/uv_hscale > rec->stride_UV)
1058 tmp = rec->stride_Y * rec->src_height;
1059 if (rec->offset_Y + tmp > new_bo->base.size)
1062 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
1063 if (rec->offset_U + tmp > new_bo->base.size ||
1064 rec->offset_V + tmp > new_bo->base.size)
1073 * Return the pipe currently connected to the panel fitter,
1074 * or -1 if the panel fitter is not present or not in use
1076 static int intel_panel_fitter_pipe(struct drm_device *dev)
1078 struct drm_i915_private *dev_priv = dev->dev_private;
1081 /* i830 doesn't have a panel fitter */
1085 pfit_control = I915_READ(PFIT_CONTROL);
1087 /* See if the panel fitter is in use */
1088 if ((pfit_control & PFIT_ENABLE) == 0)
1091 /* 965 can place panel fitter on either pipe */
1093 return (pfit_control >> 29) & 0x3;
1095 /* older chips can only use pipe 1 */
1099 int intel_overlay_put_image(struct drm_device *dev, void *data,
1100 struct drm_file *file_priv)
1102 struct drm_intel_overlay_put_image *put_image_rec = data;
1103 drm_i915_private_t *dev_priv = dev->dev_private;
1104 struct intel_overlay *overlay;
1105 struct drm_mode_object *drmmode_obj;
1106 struct intel_crtc *crtc;
1107 struct drm_i915_gem_object *new_bo;
1108 struct put_image_params *params;
1112 DRM_ERROR("called with no initialization\n");
1116 overlay = dev_priv->overlay;
1118 DRM_DEBUG("userspace bug: no overlay\n");
1122 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1123 sx_xlock(&dev->mode_config.mutex);
1126 ret = intel_overlay_switch_off(overlay);
1129 sx_xunlock(&dev->mode_config.mutex);
1134 params = malloc(sizeof(struct put_image_params), DRM_I915_GEM,
1137 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
1138 DRM_MODE_OBJECT_CRTC);
1143 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1145 new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv,
1146 put_image_rec->bo_handle));
1147 if (&new_bo->base == NULL) {
1152 sx_xlock(&dev->mode_config.mutex);
1155 if (new_bo->tiling_mode) {
1156 DRM_ERROR("buffer used for overlay image can not be tiled\n");
1161 ret = intel_overlay_recover_from_interrupt(overlay);
1165 if (overlay->crtc != crtc) {
1166 struct drm_display_mode *mode = &crtc->base.mode;
1167 ret = intel_overlay_switch_off(overlay);
1171 ret = check_overlay_possible_on_crtc(overlay, crtc);
1175 overlay->crtc = crtc;
1176 crtc->overlay = overlay;
1178 /* line too wide, i.e. one-line-mode */
1179 if (mode->hdisplay > 1024 &&
1180 intel_panel_fitter_pipe(dev) == crtc->pipe) {
1181 overlay->pfit_active = 1;
1182 update_pfit_vscale_ratio(overlay);
1184 overlay->pfit_active = 0;
1187 ret = check_overlay_dst(overlay, put_image_rec);
1191 if (overlay->pfit_active) {
1192 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
1193 overlay->pfit_vscale_ratio);
1194 /* shifting right rounds downwards, so add 1 */
1195 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
1196 overlay->pfit_vscale_ratio) + 1;
1198 params->dst_y = put_image_rec->dst_y;
1199 params->dst_h = put_image_rec->dst_height;
1201 params->dst_x = put_image_rec->dst_x;
1202 params->dst_w = put_image_rec->dst_width;
1204 params->src_w = put_image_rec->src_width;
1205 params->src_h = put_image_rec->src_height;
1206 params->src_scan_w = put_image_rec->src_scan_width;
1207 params->src_scan_h = put_image_rec->src_scan_height;
1208 if (params->src_scan_h > params->src_h ||
1209 params->src_scan_w > params->src_w) {
1214 ret = check_overlay_src(dev, put_image_rec, new_bo);
1217 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1218 params->stride_Y = put_image_rec->stride_Y;
1219 params->stride_UV = put_image_rec->stride_UV;
1220 params->offset_Y = put_image_rec->offset_Y;
1221 params->offset_U = put_image_rec->offset_U;
1222 params->offset_V = put_image_rec->offset_V;
1224 /* Check scaling after src size to prevent a divide-by-zero. */
1225 ret = check_overlay_scaling(params);
1229 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1234 sx_xunlock(&dev->mode_config.mutex);
1236 free(params, DRM_I915_GEM);
1242 sx_xunlock(&dev->mode_config.mutex);
1243 drm_gem_object_unreference_unlocked(&new_bo->base);
1245 free(params, DRM_I915_GEM);
1250 static void update_reg_attrs(struct intel_overlay *overlay,
1251 struct overlay_registers *regs)
1253 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1254 regs->OCLRC1 = overlay->saturation;
1257 static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1261 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1264 for (i = 0; i < 3; i++) {
1265 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
1272 static bool check_gamma5_errata(u32 gamma5)
1276 for (i = 0; i < 3; i++) {
1277 if (((gamma5 >> i*8) & 0xff) == 0x80)
1284 static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1286 if (!check_gamma_bounds(0, attrs->gamma0) ||
1287 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1288 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1289 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1290 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1291 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1292 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
1295 if (!check_gamma5_errata(attrs->gamma5))
1301 int intel_overlay_attrs(struct drm_device *dev, void *data,
1302 struct drm_file *file_priv)
1304 struct drm_intel_overlay_attrs *attrs = data;
1305 drm_i915_private_t *dev_priv = dev->dev_private;
1306 struct intel_overlay *overlay;
1307 struct overlay_registers *regs;
1311 DRM_ERROR("called with no initialization\n");
1315 overlay = dev_priv->overlay;
1317 DRM_DEBUG("userspace bug: no overlay\n");
1321 sx_xlock(&dev->mode_config.mutex);
1325 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1326 attrs->color_key = overlay->color_key;
1327 attrs->brightness = overlay->brightness;
1328 attrs->contrast = overlay->contrast;
1329 attrs->saturation = overlay->saturation;
1331 if (!IS_GEN2(dev)) {
1332 attrs->gamma0 = I915_READ(OGAMC0);
1333 attrs->gamma1 = I915_READ(OGAMC1);
1334 attrs->gamma2 = I915_READ(OGAMC2);
1335 attrs->gamma3 = I915_READ(OGAMC3);
1336 attrs->gamma4 = I915_READ(OGAMC4);
1337 attrs->gamma5 = I915_READ(OGAMC5);
1340 if (attrs->brightness < -128 || attrs->brightness > 127)
1342 if (attrs->contrast > 255)
1344 if (attrs->saturation > 1023)
1347 overlay->color_key = attrs->color_key;
1348 overlay->brightness = attrs->brightness;
1349 overlay->contrast = attrs->contrast;
1350 overlay->saturation = attrs->saturation;
1352 regs = intel_overlay_map_regs(overlay);
1358 update_reg_attrs(overlay, regs);
1360 intel_overlay_unmap_regs(overlay, regs);
1362 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1366 if (overlay->active) {
1371 ret = check_gamma(attrs);
1375 I915_WRITE(OGAMC0, attrs->gamma0);
1376 I915_WRITE(OGAMC1, attrs->gamma1);
1377 I915_WRITE(OGAMC2, attrs->gamma2);
1378 I915_WRITE(OGAMC3, attrs->gamma3);
1379 I915_WRITE(OGAMC4, attrs->gamma4);
1380 I915_WRITE(OGAMC5, attrs->gamma5);
1387 sx_xunlock(&dev->mode_config.mutex);
1392 void intel_setup_overlay(struct drm_device *dev)
1394 drm_i915_private_t *dev_priv = dev->dev_private;
1395 struct intel_overlay *overlay;
1396 struct drm_i915_gem_object *reg_bo;
1397 struct overlay_registers *regs;
1400 if (!HAS_OVERLAY(dev))
1403 overlay = malloc(sizeof(struct intel_overlay), DRM_I915_GEM,
1406 if (dev_priv->overlay != NULL)
1410 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
1413 overlay->reg_bo = reg_bo;
1415 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1416 ret = i915_gem_attach_phys_object(dev, reg_bo,
1417 I915_GEM_PHYS_OVERLAY_REGS,
1420 DRM_ERROR("failed to attach phys overlay regs\n");
1423 overlay->flip_addr = reg_bo->phys_obj->handle->busaddr;
1425 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE, true);
1427 DRM_ERROR("failed to pin overlay register bo\n");
1430 overlay->flip_addr = reg_bo->gtt_offset;
1432 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1434 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1439 /* init all values */
1440 overlay->color_key = 0x0101fe;
1441 overlay->brightness = -19;
1442 overlay->contrast = 75;
1443 overlay->saturation = 146;
1445 regs = intel_overlay_map_regs(overlay);
1449 memset(regs, 0, sizeof(struct overlay_registers));
1450 update_polyphase_filter(regs);
1451 update_reg_attrs(overlay, regs);
1453 intel_overlay_unmap_regs(overlay, regs);
1455 dev_priv->overlay = overlay;
1456 DRM_INFO("initialized overlay support\n");
1461 if (!OVERLAY_NEEDS_PHYSICAL(dev))
1462 i915_gem_object_unpin(reg_bo);
1464 drm_gem_object_unreference(®_bo->base);
1467 free(overlay, DRM_I915_GEM);
1471 void intel_cleanup_overlay(struct drm_device *dev)
1473 drm_i915_private_t *dev_priv = dev->dev_private;
1475 if (!dev_priv->overlay)
1478 /* The bo's should be free'd by the generic code already.
1479 * Furthermore modesetting teardown happens beforehand so the
1480 * hardware should be off already */
1481 KASSERT(!dev_priv->overlay->active, ("Overlay still active"));
1483 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1484 free(dev_priv->overlay, DRM_I915_GEM);
1487 struct intel_overlay_error_state {
1488 struct overlay_registers regs;
1494 struct intel_overlay_error_state *
1495 intel_overlay_capture_error_state(struct drm_device *dev)
1497 drm_i915_private_t *dev_priv = dev->dev_private;
1498 struct intel_overlay *overlay = dev_priv->overlay;
1499 struct intel_overlay_error_state *error;
1500 struct overlay_registers __iomem *regs;
1502 if (!overlay || !overlay->active)
1505 error = malloc(sizeof(*error), DRM_I915_GEM, M_NOWAIT);
1509 error->dovsta = I915_READ(DOVSTA);
1510 error->isr = I915_READ(ISR);
1511 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1512 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
1514 error->base = (long) overlay->reg_bo->gtt_offset;
1516 regs = intel_overlay_map_regs(overlay);
1520 memcpy(&error->regs, regs, sizeof(struct overlay_registers));
1521 intel_overlay_unmap_regs(overlay, regs);
1526 free(error, DRM_I915_GEM);
1531 intel_overlay_print_error_state(struct sbuf *m,
1532 struct intel_overlay_error_state *error)
1534 sbuf_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1535 error->dovsta, error->isr);
1536 sbuf_printf(m, " Register file at 0x%08lx:\n",
1539 #define P(x) sbuf_printf(m, " " #x ": 0x%08x\n", error->regs.x)