2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <dev/drm2/drmP.h>
33 #include <dev/drm2/radeon/radeon_drm.h>
34 #include "radeon_reg.h"
36 #include "radeon_asic.h"
39 #include "r200_reg_safe.h"
41 #include "r100_track.h"
43 static int r200_get_vtx_size_0(uint32_t vtx_fmt_0)
48 if (vtx_fmt_0 & R200_VTX_Z0)
50 if (vtx_fmt_0 & R200_VTX_W0)
53 if (vtx_fmt_0 & (0x7 << R200_VTX_WEIGHT_COUNT_SHIFT))
54 vtx_size += (vtx_fmt_0 >> R200_VTX_WEIGHT_COUNT_SHIFT) & 0x7;
55 if (vtx_fmt_0 & R200_VTX_PV_MATRIX_SEL)
57 if (vtx_fmt_0 & R200_VTX_N0)
59 if (vtx_fmt_0 & R200_VTX_POINT_SIZE)
61 if (vtx_fmt_0 & R200_VTX_DISCRETE_FOG)
63 if (vtx_fmt_0 & R200_VTX_SHININESS_0)
65 if (vtx_fmt_0 & R200_VTX_SHININESS_1)
67 for (i = 0; i < 8; i++) {
68 int color_size = (vtx_fmt_0 >> (11 + 2*i)) & 0x3;
71 case 1: vtx_size++; break;
72 case 2: vtx_size += 3; break;
73 case 3: vtx_size += 4; break;
76 if (vtx_fmt_0 & R200_VTX_XY1)
78 if (vtx_fmt_0 & R200_VTX_Z1)
80 if (vtx_fmt_0 & R200_VTX_W1)
82 if (vtx_fmt_0 & R200_VTX_N1)
87 int r200_copy_dma(struct radeon_device *rdev,
90 unsigned num_gpu_pages,
91 struct radeon_fence **fence)
93 struct radeon_ring *ring = &rdev->ring[RADEON_RING_TYPE_GFX_INDEX];
99 /* radeon pitch is /64 */
100 size = num_gpu_pages << RADEON_GPU_PAGE_SHIFT;
101 num_loops = DIV_ROUND_UP(size, 0x1FFFFF);
102 r = radeon_ring_lock(rdev, ring, num_loops * 4 + 64);
104 DRM_ERROR("radeon: moving bo (%d).\n", r);
107 /* Must wait for 2D idle & clean before DMA or hangs might happen */
108 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
109 radeon_ring_write(ring, (1 << 16));
110 for (i = 0; i < num_loops; i++) {
112 if (cur_size > 0x1FFFFF) {
116 radeon_ring_write(ring, PACKET0(0x720, 2));
117 radeon_ring_write(ring, src_offset);
118 radeon_ring_write(ring, dst_offset);
119 radeon_ring_write(ring, cur_size | (1U << 31) | (1 << 30));
120 src_offset += cur_size;
121 dst_offset += cur_size;
123 radeon_ring_write(ring, PACKET0(RADEON_WAIT_UNTIL, 0));
124 radeon_ring_write(ring, RADEON_WAIT_DMA_GUI_IDLE);
126 r = radeon_fence_emit(rdev, fence, RADEON_RING_TYPE_GFX_INDEX);
128 radeon_ring_unlock_commit(rdev, ring);
133 static int r200_get_vtx_size_1(uint32_t vtx_fmt_1)
135 int vtx_size, i, tex_size;
137 for (i = 0; i < 6; i++) {
138 tex_size = (vtx_fmt_1 >> (i * 3)) & 0x7;
141 vtx_size += tex_size;
146 int r200_packet0_check(struct radeon_cs_parser *p,
147 struct radeon_cs_packet *pkt,
148 unsigned idx, unsigned reg)
150 struct radeon_cs_reloc *reloc;
151 struct r100_cs_track *track;
152 volatile uint32_t *ib;
161 track = (struct r100_cs_track *)p->track;
162 idx_value = radeon_get_ib_value(p, idx);
164 case RADEON_CRTC_GUI_TRIG_VLINE:
165 r = r100_cs_packet_parse_vline(p);
167 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
169 r100_cs_dump_packet(p, pkt);
173 /* FIXME: only allow PACKET3 blit? easier to check for out of
175 case RADEON_DST_PITCH_OFFSET:
176 case RADEON_SRC_PITCH_OFFSET:
177 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
181 case RADEON_RB3D_DEPTHOFFSET:
182 r = r100_cs_packet_next_reloc(p, &reloc);
184 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
186 r100_cs_dump_packet(p, pkt);
189 track->zb.robj = reloc->robj;
190 track->zb.offset = idx_value;
191 track->zb_dirty = true;
192 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
194 case RADEON_RB3D_COLOROFFSET:
195 r = r100_cs_packet_next_reloc(p, &reloc);
197 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
199 r100_cs_dump_packet(p, pkt);
202 track->cb[0].robj = reloc->robj;
203 track->cb[0].offset = idx_value;
204 track->cb_dirty = true;
205 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
207 case R200_PP_TXOFFSET_0:
208 case R200_PP_TXOFFSET_1:
209 case R200_PP_TXOFFSET_2:
210 case R200_PP_TXOFFSET_3:
211 case R200_PP_TXOFFSET_4:
212 case R200_PP_TXOFFSET_5:
213 i = (reg - R200_PP_TXOFFSET_0) / 24;
214 r = r100_cs_packet_next_reloc(p, &reloc);
216 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
218 r100_cs_dump_packet(p, pkt);
221 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
222 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
223 tile_flags |= R200_TXO_MACRO_TILE;
224 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
225 tile_flags |= R200_TXO_MICRO_TILE;
227 tmp = idx_value & ~(0x7 << 2);
229 ib[idx] = tmp + ((u32)reloc->lobj.gpu_offset);
231 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
232 track->textures[i].robj = reloc->robj;
233 track->tex_dirty = true;
235 case R200_PP_CUBIC_OFFSET_F1_0:
236 case R200_PP_CUBIC_OFFSET_F2_0:
237 case R200_PP_CUBIC_OFFSET_F3_0:
238 case R200_PP_CUBIC_OFFSET_F4_0:
239 case R200_PP_CUBIC_OFFSET_F5_0:
240 case R200_PP_CUBIC_OFFSET_F1_1:
241 case R200_PP_CUBIC_OFFSET_F2_1:
242 case R200_PP_CUBIC_OFFSET_F3_1:
243 case R200_PP_CUBIC_OFFSET_F4_1:
244 case R200_PP_CUBIC_OFFSET_F5_1:
245 case R200_PP_CUBIC_OFFSET_F1_2:
246 case R200_PP_CUBIC_OFFSET_F2_2:
247 case R200_PP_CUBIC_OFFSET_F3_2:
248 case R200_PP_CUBIC_OFFSET_F4_2:
249 case R200_PP_CUBIC_OFFSET_F5_2:
250 case R200_PP_CUBIC_OFFSET_F1_3:
251 case R200_PP_CUBIC_OFFSET_F2_3:
252 case R200_PP_CUBIC_OFFSET_F3_3:
253 case R200_PP_CUBIC_OFFSET_F4_3:
254 case R200_PP_CUBIC_OFFSET_F5_3:
255 case R200_PP_CUBIC_OFFSET_F1_4:
256 case R200_PP_CUBIC_OFFSET_F2_4:
257 case R200_PP_CUBIC_OFFSET_F3_4:
258 case R200_PP_CUBIC_OFFSET_F4_4:
259 case R200_PP_CUBIC_OFFSET_F5_4:
260 case R200_PP_CUBIC_OFFSET_F1_5:
261 case R200_PP_CUBIC_OFFSET_F2_5:
262 case R200_PP_CUBIC_OFFSET_F3_5:
263 case R200_PP_CUBIC_OFFSET_F4_5:
264 case R200_PP_CUBIC_OFFSET_F5_5:
265 i = (reg - R200_PP_TXOFFSET_0) / 24;
266 face = (reg - ((i * 24) + R200_PP_TXOFFSET_0)) / 4;
267 r = r100_cs_packet_next_reloc(p, &reloc);
269 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
271 r100_cs_dump_packet(p, pkt);
274 track->textures[i].cube_info[face - 1].offset = idx_value;
275 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
276 track->textures[i].cube_info[face - 1].robj = reloc->robj;
277 track->tex_dirty = true;
279 case RADEON_RE_WIDTH_HEIGHT:
280 track->maxy = ((idx_value >> 16) & 0x7FF);
281 track->cb_dirty = true;
282 track->zb_dirty = true;
284 case RADEON_RB3D_COLORPITCH:
285 r = r100_cs_packet_next_reloc(p, &reloc);
287 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
289 r100_cs_dump_packet(p, pkt);
293 if (!(p->cs_flags & RADEON_CS_KEEP_TILING_FLAGS)) {
294 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
295 tile_flags |= RADEON_COLOR_TILE_ENABLE;
296 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
297 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
299 tmp = idx_value & ~(0x7 << 16);
305 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
306 track->cb_dirty = true;
308 case RADEON_RB3D_DEPTHPITCH:
309 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
310 track->zb_dirty = true;
312 case RADEON_RB3D_CNTL:
313 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
319 track->cb[0].cpp = 1;
324 track->cb[0].cpp = 2;
327 track->cb[0].cpp = 4;
330 DRM_ERROR("Invalid color buffer format (%d) !\n",
331 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
334 if (idx_value & RADEON_DEPTHXY_OFFSET_ENABLE) {
335 DRM_ERROR("No support for depth xy offset in kms\n");
339 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
340 track->cb_dirty = true;
341 track->zb_dirty = true;
343 case RADEON_RB3D_ZSTENCILCNTL:
344 switch (idx_value & 0xf) {
359 track->zb_dirty = true;
361 case RADEON_RB3D_ZPASS_ADDR:
362 r = r100_cs_packet_next_reloc(p, &reloc);
364 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
366 r100_cs_dump_packet(p, pkt);
369 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
373 uint32_t temp = idx_value >> 4;
374 for (i = 0; i < track->num_texture; i++)
375 track->textures[i].enabled = !!(temp & (1 << i));
376 track->tex_dirty = true;
379 case RADEON_SE_VF_CNTL:
380 track->vap_vf_cntl = idx_value;
383 /* VAP_VF_MAX_VTX_INDX */
384 track->max_indx = idx_value & 0x00FFFFFFUL;
386 case R200_SE_VTX_FMT_0:
387 track->vtx_size = r200_get_vtx_size_0(idx_value);
389 case R200_SE_VTX_FMT_1:
390 track->vtx_size += r200_get_vtx_size_1(idx_value);
392 case R200_PP_TXSIZE_0:
393 case R200_PP_TXSIZE_1:
394 case R200_PP_TXSIZE_2:
395 case R200_PP_TXSIZE_3:
396 case R200_PP_TXSIZE_4:
397 case R200_PP_TXSIZE_5:
398 i = (reg - R200_PP_TXSIZE_0) / 32;
399 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
400 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
401 track->tex_dirty = true;
403 case R200_PP_TXPITCH_0:
404 case R200_PP_TXPITCH_1:
405 case R200_PP_TXPITCH_2:
406 case R200_PP_TXPITCH_3:
407 case R200_PP_TXPITCH_4:
408 case R200_PP_TXPITCH_5:
409 i = (reg - R200_PP_TXPITCH_0) / 32;
410 track->textures[i].pitch = idx_value + 32;
411 track->tex_dirty = true;
413 case R200_PP_TXFILTER_0:
414 case R200_PP_TXFILTER_1:
415 case R200_PP_TXFILTER_2:
416 case R200_PP_TXFILTER_3:
417 case R200_PP_TXFILTER_4:
418 case R200_PP_TXFILTER_5:
419 i = (reg - R200_PP_TXFILTER_0) / 32;
420 track->textures[i].num_levels = ((idx_value & R200_MAX_MIP_LEVEL_MASK)
421 >> R200_MAX_MIP_LEVEL_SHIFT);
422 tmp = (idx_value >> 23) & 0x7;
423 if (tmp == 2 || tmp == 6)
424 track->textures[i].roundup_w = false;
425 tmp = (idx_value >> 27) & 0x7;
426 if (tmp == 2 || tmp == 6)
427 track->textures[i].roundup_h = false;
428 track->tex_dirty = true;
430 case R200_PP_TXMULTI_CTL_0:
431 case R200_PP_TXMULTI_CTL_1:
432 case R200_PP_TXMULTI_CTL_2:
433 case R200_PP_TXMULTI_CTL_3:
434 case R200_PP_TXMULTI_CTL_4:
435 case R200_PP_TXMULTI_CTL_5:
436 i = (reg - R200_PP_TXMULTI_CTL_0) / 32;
438 case R200_PP_TXFORMAT_X_0:
439 case R200_PP_TXFORMAT_X_1:
440 case R200_PP_TXFORMAT_X_2:
441 case R200_PP_TXFORMAT_X_3:
442 case R200_PP_TXFORMAT_X_4:
443 case R200_PP_TXFORMAT_X_5:
444 i = (reg - R200_PP_TXFORMAT_X_0) / 32;
445 track->textures[i].txdepth = idx_value & 0x7;
446 tmp = (idx_value >> 16) & 0x3;
456 track->textures[i].tex_coord_type = 0;
460 track->textures[i].tex_coord_type = 2;
464 track->textures[i].tex_coord_type = 1;
467 track->tex_dirty = true;
469 case R200_PP_TXFORMAT_0:
470 case R200_PP_TXFORMAT_1:
471 case R200_PP_TXFORMAT_2:
472 case R200_PP_TXFORMAT_3:
473 case R200_PP_TXFORMAT_4:
474 case R200_PP_TXFORMAT_5:
475 i = (reg - R200_PP_TXFORMAT_0) / 32;
476 if (idx_value & R200_TXFORMAT_NON_POWER2) {
477 track->textures[i].use_pitch = 1;
479 track->textures[i].use_pitch = 0;
480 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
481 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
483 if (idx_value & R200_TXFORMAT_LOOKUP_DISABLE)
484 track->textures[i].lookup_disable = true;
485 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
486 case R200_TXFORMAT_I8:
487 case R200_TXFORMAT_RGB332:
488 case R200_TXFORMAT_Y8:
489 track->textures[i].cpp = 1;
490 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
492 case R200_TXFORMAT_AI88:
493 case R200_TXFORMAT_ARGB1555:
494 case R200_TXFORMAT_RGB565:
495 case R200_TXFORMAT_ARGB4444:
496 case R200_TXFORMAT_VYUY422:
497 case R200_TXFORMAT_YVYU422:
498 case R200_TXFORMAT_LDVDU655:
499 case R200_TXFORMAT_DVDU88:
500 case R200_TXFORMAT_AVYU4444:
501 track->textures[i].cpp = 2;
502 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
504 case R200_TXFORMAT_ARGB8888:
505 case R200_TXFORMAT_RGBA8888:
506 case R200_TXFORMAT_ABGR8888:
507 case R200_TXFORMAT_BGR111110:
508 case R200_TXFORMAT_LDVDU8888:
509 track->textures[i].cpp = 4;
510 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
512 case R200_TXFORMAT_DXT1:
513 track->textures[i].cpp = 1;
514 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
516 case R200_TXFORMAT_DXT23:
517 case R200_TXFORMAT_DXT45:
518 track->textures[i].cpp = 1;
519 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
522 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
523 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
524 track->tex_dirty = true;
526 case R200_PP_CUBIC_FACES_0:
527 case R200_PP_CUBIC_FACES_1:
528 case R200_PP_CUBIC_FACES_2:
529 case R200_PP_CUBIC_FACES_3:
530 case R200_PP_CUBIC_FACES_4:
531 case R200_PP_CUBIC_FACES_5:
533 i = (reg - R200_PP_CUBIC_FACES_0) / 32;
534 for (face = 0; face < 4; face++) {
535 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
536 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
538 track->tex_dirty = true;
541 DRM_ERROR("Forbidden register 0x%04X in cs at %d\n",
548 void r200_set_safe_registers(struct radeon_device *rdev)
550 rdev->config.r100.reg_safe_bm = r200_reg_safe_bm;
551 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r200_reg_safe_bm);