2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #ifndef __RADEON_ASIC_H__
33 #define __RADEON_ASIC_H__
38 uint32_t radeon_legacy_get_engine_clock(struct radeon_device *rdev);
39 void radeon_legacy_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
40 uint32_t radeon_legacy_get_memory_clock(struct radeon_device *rdev);
41 void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
43 uint32_t radeon_atom_get_engine_clock(struct radeon_device *rdev);
44 void radeon_atom_set_engine_clock(struct radeon_device *rdev, uint32_t eng_clock);
45 uint32_t radeon_atom_get_memory_clock(struct radeon_device *rdev);
46 void radeon_atom_set_memory_clock(struct radeon_device *rdev, uint32_t mem_clock);
47 void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
49 void atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
50 u8 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder);
51 void radeon_legacy_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level);
52 u8 radeon_legacy_get_backlight_level(struct radeon_encoder *radeon_encoder);
56 * r100,rv100,rs100,rv200,rs200
66 int r100_init(struct radeon_device *rdev);
67 void r100_fini(struct radeon_device *rdev);
68 int r100_suspend(struct radeon_device *rdev);
69 int r100_resume(struct radeon_device *rdev);
70 void r100_vga_set_state(struct radeon_device *rdev, bool state);
71 bool r100_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
72 int r100_asic_reset(struct radeon_device *rdev);
73 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc);
74 void r100_pci_gart_tlb_flush(struct radeon_device *rdev);
75 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
76 void r100_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
77 int r100_irq_set(struct radeon_device *rdev);
78 irqreturn_t r100_irq_process(struct radeon_device *rdev);
79 void r100_fence_ring_emit(struct radeon_device *rdev,
80 struct radeon_fence *fence);
81 void r100_semaphore_ring_emit(struct radeon_device *rdev,
82 struct radeon_ring *cp,
83 struct radeon_semaphore *semaphore,
85 int r100_cs_parse(struct radeon_cs_parser *p);
86 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
87 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg);
88 int r100_copy_blit(struct radeon_device *rdev,
91 unsigned num_gpu_pages,
92 struct radeon_fence **fence);
93 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
94 uint32_t tiling_flags, uint32_t pitch,
95 uint32_t offset, uint32_t obj_size);
96 void r100_clear_surface_reg(struct radeon_device *rdev, int reg);
97 void r100_bandwidth_update(struct radeon_device *rdev);
98 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
99 int r100_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
100 void r100_hpd_init(struct radeon_device *rdev);
101 void r100_hpd_fini(struct radeon_device *rdev);
102 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
103 void r100_hpd_set_polarity(struct radeon_device *rdev,
104 enum radeon_hpd_id hpd);
105 int r100_debugfs_rbbm_init(struct radeon_device *rdev);
106 int r100_debugfs_cp_init(struct radeon_device *rdev);
107 void r100_cp_disable(struct radeon_device *rdev);
108 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size);
109 void r100_cp_fini(struct radeon_device *rdev);
110 int r100_pci_gart_init(struct radeon_device *rdev);
111 void r100_pci_gart_fini(struct radeon_device *rdev);
112 int r100_pci_gart_enable(struct radeon_device *rdev);
113 void r100_pci_gart_disable(struct radeon_device *rdev);
114 int r100_debugfs_mc_info_init(struct radeon_device *rdev);
115 int r100_gui_wait_for_idle(struct radeon_device *rdev);
116 int r100_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
117 void r100_irq_disable(struct radeon_device *rdev);
118 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save);
119 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save);
120 void r100_vram_init_sizes(struct radeon_device *rdev);
121 int r100_cp_reset(struct radeon_device *rdev);
122 void r100_vga_render_disable(struct radeon_device *rdev);
123 void r100_restore_sanity(struct radeon_device *rdev);
124 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
125 struct radeon_cs_packet *pkt,
126 struct radeon_bo *robj);
127 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
128 struct radeon_cs_packet *pkt,
129 const unsigned *auth, unsigned n,
130 radeon_packet0_check_t check);
131 int r100_cs_packet_parse(struct radeon_cs_parser *p,
132 struct radeon_cs_packet *pkt,
134 void r100_enable_bm(struct radeon_device *rdev);
135 void r100_set_common_regs(struct radeon_device *rdev);
136 void r100_bm_disable(struct radeon_device *rdev);
137 extern bool r100_gui_idle(struct radeon_device *rdev);
138 extern void r100_pm_misc(struct radeon_device *rdev);
139 extern void r100_pm_prepare(struct radeon_device *rdev);
140 extern void r100_pm_finish(struct radeon_device *rdev);
141 extern void r100_pm_init_profile(struct radeon_device *rdev);
142 extern void r100_pm_get_dynpm_state(struct radeon_device *rdev);
143 extern void r100_pre_page_flip(struct radeon_device *rdev, int crtc);
144 extern u32 r100_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
145 extern void r100_post_page_flip(struct radeon_device *rdev, int crtc);
146 extern void r100_wait_for_vblank(struct radeon_device *rdev, int crtc);
147 extern int r100_mc_wait_for_idle(struct radeon_device *rdev);
150 * r200,rv250,rs300,rv280
152 extern int r200_copy_dma(struct radeon_device *rdev,
155 unsigned num_gpu_pages,
156 struct radeon_fence **fence);
157 void r200_set_safe_registers(struct radeon_device *rdev);
160 * r300,r350,rv350,rv380
162 extern int r300_init(struct radeon_device *rdev);
163 extern void r300_fini(struct radeon_device *rdev);
164 extern int r300_suspend(struct radeon_device *rdev);
165 extern int r300_resume(struct radeon_device *rdev);
166 extern int r300_asic_reset(struct radeon_device *rdev);
167 extern void r300_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
168 extern void r300_fence_ring_emit(struct radeon_device *rdev,
169 struct radeon_fence *fence);
170 extern int r300_cs_parse(struct radeon_cs_parser *p);
171 extern void rv370_pcie_gart_tlb_flush(struct radeon_device *rdev);
172 extern int rv370_pcie_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
173 extern void rv370_set_pcie_lanes(struct radeon_device *rdev, int lanes);
174 extern int rv370_get_pcie_lanes(struct radeon_device *rdev);
175 extern void r300_set_reg_safe(struct radeon_device *rdev);
176 extern void r300_mc_program(struct radeon_device *rdev);
177 extern void r300_mc_init(struct radeon_device *rdev);
178 extern void r300_clock_startup(struct radeon_device *rdev);
179 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
180 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
181 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
182 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
183 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
188 extern int r420_init(struct radeon_device *rdev);
189 extern void r420_fini(struct radeon_device *rdev);
190 extern int r420_suspend(struct radeon_device *rdev);
191 extern int r420_resume(struct radeon_device *rdev);
192 extern void r420_pm_init_profile(struct radeon_device *rdev);
193 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
194 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
195 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
196 extern void r420_pipes_init(struct radeon_device *rdev);
201 extern int rs400_init(struct radeon_device *rdev);
202 extern void rs400_fini(struct radeon_device *rdev);
203 extern int rs400_suspend(struct radeon_device *rdev);
204 extern int rs400_resume(struct radeon_device *rdev);
205 void rs400_gart_tlb_flush(struct radeon_device *rdev);
206 int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
207 uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg);
208 void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
209 int rs400_gart_init(struct radeon_device *rdev);
210 int rs400_gart_enable(struct radeon_device *rdev);
211 void rs400_gart_adjust_size(struct radeon_device *rdev);
212 void rs400_gart_disable(struct radeon_device *rdev);
213 void rs400_gart_fini(struct radeon_device *rdev);
214 extern int rs400_mc_wait_for_idle(struct radeon_device *rdev);
219 extern int rs600_asic_reset(struct radeon_device *rdev);
220 extern int rs600_init(struct radeon_device *rdev);
221 extern void rs600_fini(struct radeon_device *rdev);
222 extern int rs600_suspend(struct radeon_device *rdev);
223 extern int rs600_resume(struct radeon_device *rdev);
224 int rs600_irq_set(struct radeon_device *rdev);
225 irqreturn_t rs600_irq_process(struct radeon_device *rdev);
226 void rs600_irq_disable(struct radeon_device *rdev);
227 u32 rs600_get_vblank_counter(struct radeon_device *rdev, int crtc);
228 void rs600_gart_tlb_flush(struct radeon_device *rdev);
229 int rs600_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr);
230 uint32_t rs600_mc_rreg(struct radeon_device *rdev, uint32_t reg);
231 void rs600_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
232 void rs600_bandwidth_update(struct radeon_device *rdev);
233 void rs600_hpd_init(struct radeon_device *rdev);
234 void rs600_hpd_fini(struct radeon_device *rdev);
235 bool rs600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
236 void rs600_hpd_set_polarity(struct radeon_device *rdev,
237 enum radeon_hpd_id hpd);
238 extern void rs600_pm_misc(struct radeon_device *rdev);
239 extern void rs600_pm_prepare(struct radeon_device *rdev);
240 extern void rs600_pm_finish(struct radeon_device *rdev);
241 extern void rs600_pre_page_flip(struct radeon_device *rdev, int crtc);
242 extern u32 rs600_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
243 extern void rs600_post_page_flip(struct radeon_device *rdev, int crtc);
244 void rs600_set_safe_registers(struct radeon_device *rdev);
245 extern void avivo_wait_for_vblank(struct radeon_device *rdev, int crtc);
246 extern int rs600_mc_wait_for_idle(struct radeon_device *rdev);
251 int rs690_init(struct radeon_device *rdev);
252 void rs690_fini(struct radeon_device *rdev);
253 int rs690_resume(struct radeon_device *rdev);
254 int rs690_suspend(struct radeon_device *rdev);
255 uint32_t rs690_mc_rreg(struct radeon_device *rdev, uint32_t reg);
256 void rs690_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
257 void rs690_bandwidth_update(struct radeon_device *rdev);
258 void rs690_line_buffer_adjust(struct radeon_device *rdev,
259 struct drm_display_mode *mode1,
260 struct drm_display_mode *mode2);
261 extern int rs690_mc_wait_for_idle(struct radeon_device *rdev);
266 struct rv515_mc_save {
267 u32 vga_render_control;
269 bool crtc_enabled[2];
272 int rv515_init(struct radeon_device *rdev);
273 void rv515_fini(struct radeon_device *rdev);
274 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg);
275 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
276 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring);
277 void rv515_bandwidth_update(struct radeon_device *rdev);
278 int rv515_resume(struct radeon_device *rdev);
279 int rv515_suspend(struct radeon_device *rdev);
280 void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
281 void rv515_vga_render_disable(struct radeon_device *rdev);
282 void rv515_set_safe_registers(struct radeon_device *rdev);
283 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
284 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
285 void rv515_clock_startup(struct radeon_device *rdev);
286 void rv515_debugfs(struct radeon_device *rdev);
287 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
290 * r520,rv530,rv560,rv570,r580
292 int r520_init(struct radeon_device *rdev);
293 int r520_resume(struct radeon_device *rdev);
294 int r520_mc_wait_for_idle(struct radeon_device *rdev);
297 * r600,rv610,rv630,rv620,rv635,rv670,rs780,rs880
299 int r600_init(struct radeon_device *rdev);
300 void r600_fini(struct radeon_device *rdev);
301 int r600_suspend(struct radeon_device *rdev);
302 int r600_resume(struct radeon_device *rdev);
303 void r600_vga_set_state(struct radeon_device *rdev, bool state);
304 int r600_wb_init(struct radeon_device *rdev);
305 void r600_wb_fini(struct radeon_device *rdev);
306 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
307 uint32_t r600_pciep_rreg(struct radeon_device *rdev, uint32_t reg);
308 void r600_pciep_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v);
309 int r600_cs_parse(struct radeon_cs_parser *p);
310 int r600_dma_cs_parse(struct radeon_cs_parser *p);
311 void r600_fence_ring_emit(struct radeon_device *rdev,
312 struct radeon_fence *fence);
313 void r600_semaphore_ring_emit(struct radeon_device *rdev,
314 struct radeon_ring *cp,
315 struct radeon_semaphore *semaphore,
317 void r600_dma_fence_ring_emit(struct radeon_device *rdev,
318 struct radeon_fence *fence);
319 void r600_dma_semaphore_ring_emit(struct radeon_device *rdev,
320 struct radeon_ring *ring,
321 struct radeon_semaphore *semaphore,
323 void r600_dma_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
324 bool r600_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
325 bool r600_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
326 int r600_asic_reset(struct radeon_device *rdev);
327 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
328 uint32_t tiling_flags, uint32_t pitch,
329 uint32_t offset, uint32_t obj_size);
330 void r600_clear_surface_reg(struct radeon_device *rdev, int reg);
331 int r600_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
332 int r600_dma_ib_test(struct radeon_device *rdev, struct radeon_ring *ring);
333 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
334 int r600_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
335 int r600_dma_ring_test(struct radeon_device *rdev, struct radeon_ring *cp);
336 int r600_copy_blit(struct radeon_device *rdev,
337 uint64_t src_offset, uint64_t dst_offset,
338 unsigned num_gpu_pages, struct radeon_fence **fence);
339 int r600_copy_dma(struct radeon_device *rdev,
340 uint64_t src_offset, uint64_t dst_offset,
341 unsigned num_gpu_pages, struct radeon_fence **fence);
342 void r600_hpd_init(struct radeon_device *rdev);
343 void r600_hpd_fini(struct radeon_device *rdev);
344 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
345 void r600_hpd_set_polarity(struct radeon_device *rdev,
346 enum radeon_hpd_id hpd);
347 extern void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo);
348 extern bool r600_gui_idle(struct radeon_device *rdev);
349 extern void r600_pm_misc(struct radeon_device *rdev);
350 extern void r600_pm_init_profile(struct radeon_device *rdev);
351 extern void rs780_pm_init_profile(struct radeon_device *rdev);
352 extern void r600_pm_get_dynpm_state(struct radeon_device *rdev);
353 extern void r600_set_pcie_lanes(struct radeon_device *rdev, int lanes);
354 extern int r600_get_pcie_lanes(struct radeon_device *rdev);
355 bool r600_card_posted(struct radeon_device *rdev);
356 void r600_cp_stop(struct radeon_device *rdev);
357 int r600_cp_start(struct radeon_device *rdev);
358 void r600_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size);
359 int r600_cp_resume(struct radeon_device *rdev);
360 void r600_cp_fini(struct radeon_device *rdev);
361 int r600_count_pipe_bits(uint32_t val);
362 int r600_mc_wait_for_idle(struct radeon_device *rdev);
363 int r600_pcie_gart_init(struct radeon_device *rdev);
364 void r600_scratch_init(struct radeon_device *rdev);
365 int r600_blit_init(struct radeon_device *rdev);
366 void r600_blit_fini(struct radeon_device *rdev);
367 int r600_init_microcode(struct radeon_device *rdev);
368 void r600_fini_microcode(struct radeon_device *rdev);
370 irqreturn_t r600_irq_process(struct radeon_device *rdev);
371 int r600_irq_init(struct radeon_device *rdev);
372 void r600_irq_fini(struct radeon_device *rdev);
373 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
374 int r600_irq_set(struct radeon_device *rdev);
375 void r600_irq_suspend(struct radeon_device *rdev);
376 void r600_disable_interrupts(struct radeon_device *rdev);
377 void r600_rlc_stop(struct radeon_device *rdev);
379 int r600_audio_init(struct radeon_device *rdev);
380 void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
381 struct r600_audio r600_audio_status(struct radeon_device *rdev);
382 void r600_audio_fini(struct radeon_device *rdev);
383 int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
384 void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
386 int r600_blit_prepare_copy(struct radeon_device *rdev, unsigned num_gpu_pages,
387 struct radeon_fence **fence, struct radeon_sa_bo **vb,
388 struct radeon_semaphore **sem);
389 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence **fence,
390 struct radeon_sa_bo *vb, struct radeon_semaphore *sem);
391 void r600_kms_blit_copy(struct radeon_device *rdev,
392 u64 src_gpu_addr, u64 dst_gpu_addr,
393 unsigned num_gpu_pages,
394 struct radeon_sa_bo *vb);
395 uint64_t r600_get_gpu_clock(struct radeon_device *rdev);
398 * rv770,rv730,rv710,rv740
400 int rv770_init(struct radeon_device *rdev);
401 void rv770_fini(struct radeon_device *rdev);
402 int rv770_suspend(struct radeon_device *rdev);
403 int rv770_resume(struct radeon_device *rdev);
404 void rv770_pm_misc(struct radeon_device *rdev);
405 u32 rv770_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
406 void r700_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
407 void r700_cp_stop(struct radeon_device *rdev);
408 void r700_cp_fini(struct radeon_device *rdev);
409 int rv770_copy_dma(struct radeon_device *rdev,
410 uint64_t src_offset, uint64_t dst_offset,
411 unsigned num_gpu_pages,
412 struct radeon_fence **fence);
417 struct evergreen_mc_save {
418 u32 vga_render_control;
420 bool crtc_enabled[RADEON_MAX_CRTCS];
423 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev);
424 int evergreen_init(struct radeon_device *rdev);
425 void evergreen_fini(struct radeon_device *rdev);
426 int evergreen_suspend(struct radeon_device *rdev);
427 int evergreen_resume(struct radeon_device *rdev);
428 bool evergreen_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
429 int evergreen_asic_reset(struct radeon_device *rdev);
430 void evergreen_bandwidth_update(struct radeon_device *rdev);
431 void evergreen_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
432 void evergreen_hpd_init(struct radeon_device *rdev);
433 void evergreen_hpd_fini(struct radeon_device *rdev);
434 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd);
435 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
436 enum radeon_hpd_id hpd);
437 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc);
438 int evergreen_irq_set(struct radeon_device *rdev);
439 irqreturn_t evergreen_irq_process(struct radeon_device *rdev);
440 extern int evergreen_cs_parse(struct radeon_cs_parser *p);
441 extern int evergreen_dma_cs_parse(struct radeon_cs_parser *p);
442 extern void evergreen_pm_misc(struct radeon_device *rdev);
443 extern void evergreen_pm_prepare(struct radeon_device *rdev);
444 extern void evergreen_pm_finish(struct radeon_device *rdev);
445 extern void sumo_pm_init_profile(struct radeon_device *rdev);
446 extern void btc_pm_init_profile(struct radeon_device *rdev);
447 extern void evergreen_pre_page_flip(struct radeon_device *rdev, int crtc);
448 extern u32 evergreen_page_flip(struct radeon_device *rdev, int crtc, u64 crtc_base);
449 extern void evergreen_post_page_flip(struct radeon_device *rdev, int crtc);
450 extern void dce4_wait_for_vblank(struct radeon_device *rdev, int crtc);
451 void evergreen_disable_interrupt_state(struct radeon_device *rdev);
452 int evergreen_blit_init(struct radeon_device *rdev);
453 int evergreen_mc_wait_for_idle(struct radeon_device *rdev);
454 void evergreen_dma_fence_ring_emit(struct radeon_device *rdev,
455 struct radeon_fence *fence);
456 void evergreen_dma_ring_ib_execute(struct radeon_device *rdev,
457 struct radeon_ib *ib);
458 int evergreen_copy_dma(struct radeon_device *rdev,
459 uint64_t src_offset, uint64_t dst_offset,
460 unsigned num_gpu_pages,
461 struct radeon_fence **fence);
462 void evergreen_fix_pci_max_read_req_size(struct radeon_device *rdev);
463 u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev);
464 void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save);
465 void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save);
466 void evergreen_mc_program(struct radeon_device *rdev);
467 int evergreen_mc_init(struct radeon_device *rdev);
468 void evergreen_irq_suspend(struct radeon_device *rdev);
473 void cayman_fence_ring_emit(struct radeon_device *rdev,
474 struct radeon_fence *fence);
475 void cayman_pcie_gart_tlb_flush(struct radeon_device *rdev);
476 int cayman_init(struct radeon_device *rdev);
477 void cayman_fini(struct radeon_device *rdev);
478 int cayman_suspend(struct radeon_device *rdev);
479 int cayman_resume(struct radeon_device *rdev);
480 int cayman_asic_reset(struct radeon_device *rdev);
481 void cayman_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
482 int cayman_vm_init(struct radeon_device *rdev);
483 void cayman_vm_fini(struct radeon_device *rdev);
484 void cayman_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
485 uint32_t cayman_vm_page_flags(struct radeon_device *rdev, uint32_t flags);
486 void cayman_vm_set_page(struct radeon_device *rdev, uint64_t pe,
487 uint64_t addr, unsigned count,
488 uint32_t incr, uint32_t flags);
489 int evergreen_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
490 int evergreen_dma_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
491 void cayman_dma_ring_ib_execute(struct radeon_device *rdev,
492 struct radeon_ib *ib);
493 bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring);
494 void cayman_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
495 extern void cayman_cp_int_cntl_setup(struct radeon_device *rdev,
496 int ring, u32 cp_int_cntl);
499 void dce6_bandwidth_update(struct radeon_device *rdev);
504 void si_fence_ring_emit(struct radeon_device *rdev,
505 struct radeon_fence *fence);
506 void si_pcie_gart_tlb_flush(struct radeon_device *rdev);
507 int si_init(struct radeon_device *rdev);
508 void si_fini(struct radeon_device *rdev);
509 int si_suspend(struct radeon_device *rdev);
510 int si_resume(struct radeon_device *rdev);
511 bool si_gpu_is_lockup(struct radeon_device *rdev, struct radeon_ring *cp);
512 int si_asic_reset(struct radeon_device *rdev);
513 void si_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib);
514 int si_irq_set(struct radeon_device *rdev);
515 irqreturn_t si_irq_process(struct radeon_device *rdev);
516 int si_vm_init(struct radeon_device *rdev);
517 void si_vm_fini(struct radeon_device *rdev);
518 void si_vm_set_page(struct radeon_device *rdev, uint64_t pe,
519 uint64_t addr, unsigned count,
520 uint32_t incr, uint32_t flags);
521 void si_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
522 int si_ib_parse(struct radeon_device *rdev, struct radeon_ib *ib);
523 uint64_t si_get_gpu_clock(struct radeon_device *rdev);
524 int si_copy_dma(struct radeon_device *rdev,
525 uint64_t src_offset, uint64_t dst_offset,
526 unsigned num_gpu_pages,
527 struct radeon_fence **fence);
528 void si_dma_vm_flush(struct radeon_device *rdev, int ridx, struct radeon_vm *vm);
529 void si_rlc_fini(struct radeon_device *rdev);
530 int si_rlc_init(struct radeon_device *rdev);